mirror of
https://github.com/drasko/open-ameba.git
synced 2024-11-21 21:44:19 +00:00
boot v0.1
This commit is contained in:
pvvx
parent
d8c84cd5fe
commit
d9bd706408
24 changed files with 2734 additions and 2568 deletions
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@ -146,12 +146,12 @@ void fATSR(void *arg)
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#if CONFIG_UART_XMODEM
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void fATSY(void *arg)
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{
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#ifdef RTL8710AF
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if (HalGetChipId() < CHIP_ID_8195AM) {
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OTU_FW_Update(0, 0, 115200);
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#else
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} else {
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// use xmodem to update, RX: PA_6, TX: PA_7, baudrate: 1M
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OTU_FW_Update(0, 2, 115200);
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#endif
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}
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}
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#endif
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@ -1166,17 +1166,18 @@ void fATSL(void *arg) {
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#if CONFIG_UART_XMODEM
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void fATSX(void *arg)
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{
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#ifdef RTL8710AF
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if (HalGetChipId() < CHIP_ID_8195AM) {
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// use xmodem to update, RX: PC_0, TX: PC_3, baudrate: 1M
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OTU_FW_Update(0, 0, 115200);
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// use xmodem to update, RX: PE_3, TX: PE_0, baudrate: 1M
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// JTAG Off!
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// OTU_FW_Update(0, 1, 115200);
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#else
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//#error "Set OTU_FW_Update UARTx pins!"
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}
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else {
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// use xmodem to update, RX: PA_6, TX: PA_7, baudrate: 1M
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OTU_FW_Update(0, 2, 115200);
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#endif
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};
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at_printf("\r\n[ATSX] OK");
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}
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#endif
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@ -226,11 +226,7 @@ u32 xModem_Frame_Img2(char *ptr, unsigned int frame_num, unsigned int frame_siz
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return rx_len;
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}
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*/
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#ifdef RTL8710AF
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if (fw_img2_size > (0x80000-0x0B000)) {
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#else
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if (fw_img2_size > (2*1024*1024)) {
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#endif
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if (fw_img2_size > ((HalGetChipId() < CHIP_ID_8195AM) ? (0x80000-0x0B000) : (2*1024*1024))) {
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DBG_MISC_ERR("OTU: fw_img2_addr=0x%x fw_img2_size(%d) to Big!\n", fw_img2_addr, fw_img2_size);
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fw_img1_size = 0;
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fw_img2_size = 0;
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@ -307,11 +303,7 @@ u32 xModem_Frame_Img2(char *ptr, unsigned int frame_num, unsigned int frame_siz
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return rx_len;
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}
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*/
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#ifdef RTL8710AF
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if (fw_img2_size > (0x80000 - fw_img3_addr)) {
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#else
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if (fw_img2_size > (2*1024*1024)) {
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#endif
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if (fw_img2_size > ((HalGetChipId() < CHIP_ID_8195AM) ? (0x80000 - fw_img3_addr) : (2*1024*1024))) {
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DBG_MISC_ERR("OTU: fw_img3_addr=0x%x fw_img2_size(%d) to Big!\n", fw_img3_addr, fw_img3_size);
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fw_img3_size = 0;
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return rx_len;
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@ -21,7 +21,7 @@
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#include "flash_api.h"
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extern u32 ConfigDebugInfo;
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extern SPIC_INIT_PARA SpicInitParaAllClk[3][CPU_CLK_TYPE_NO];
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extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // SpicMaxMode = 3, CPU_CLK_TYPE_NO = 6 !
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_LONG_CALL_
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extern VOID SpicWaitBusyDoneRtl8195A(VOID);
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@ -538,7 +538,7 @@ const HeapRegion_t *pxHeapRegion;
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pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
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int chip_id = HalGetChipId();
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uint8 chip_id = HalGetChipId();
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while( pxHeapRegion->xSizeInBytes > 0 )
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{
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if(pxHeapRegion->pucStartAddress > 0x20000000
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@ -138,11 +138,11 @@ _WEAK int main(void)
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while(pUartLogCtl->ExecuteEsc != 1);
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pUartLogCtl->RevdNo = 0;
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pUartLogCtl->BootRdy = 1;
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DiagPrintf("\r<RTL8710AF>");
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DiagPrintf("\r<RTL871xAx>");
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while(1) {
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while(pUartLogCtl->ExecuteCmd != 1 );
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UartLogCmdExecute(pUartLogCtl);
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DiagPrintf("\r<RTL8710AF>");
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DiagPrintf("\r<RTL871xAx>");
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pUartLogCtl->ExecuteCmd = 0;
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}
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@ -7,7 +7,6 @@
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _HAL_PLATFORM_
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#define _HAL_PLATFORM_
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@ -16,7 +15,6 @@
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#define SYSTEM_CLK PLATFORM_CLOCK
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#define PERIPHERAL_IRQ_STATUS 0x04
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#define PERIPHERAL_IRQ_MODE 0x08
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#define PERIPHERAL_IRQ_EN 0x0C
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@ -103,7 +103,7 @@ typedef struct _DRAM_DEVICE_INFO_ {
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DRAM_TIMING_INFO *Timing;
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u32 DdrPeriodPs;
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DFI_RATIO_TYPE *DfiRate;
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}DRAM_DEVICE_INFO;
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} DRAM_DEVICE_INFO, *PDRAM_DEVICE_INFO;
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//======================================================
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@ -169,7 +169,7 @@ __attribute__((__section__(".sdr.rand2.data"))) u32 _sdr_rnd2_c = 7654321, _sdr_
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// 100020BC, 100020B8, 100020B4
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HAL_GPIO_ADAPTER PINMUX_RAM_DATA_SECTION gBoot_Gpio_Adapter; // 100020C0 [300=0x12c]
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// SPIC_INIT_PARA HAL_FLASH_DATA_SECTION SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90]
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//SPIC_INIT_PARA HAL_FLASH_DATA_SECTION SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90]
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#ifndef PRESENT_IMAGE2
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IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0; //= { InfraStart + 1 };
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@ -1,5 +1,5 @@
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/*
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* (SRAM) Debug BootLoader
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* BootLoader
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* Created on: 12/02/2017
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* Author: pvvx
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*/
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@ -11,16 +11,31 @@
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//-------------------------------------------------------------------------
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// Data declarations
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//extern u32 STACK_TOP;
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//extern volatile UART_LOG_CTL * pUartLogCtl;
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#define DEFAULT_BAUDRATE UART_BAUD_RATE_38400
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/* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz,
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6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */
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#define DEFAULT_BOOT_CLK_CPU 1 // Warning! If Start CLK > 100 MHz -> Errors SPIC function in Ameba SDK!
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#ifdef DEFAULT_BOOT_CLK_CPU
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#if DEFAULT_BOOT_CLK_CPU < 6
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#define DEFAULT_BOOT_CPU_CLOCK_SEL_DIV5_3 0
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#define DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE DEFAULT_BOOT_CLK_CPU
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#else
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#define DEFAULT_BOOT_CPU_CLOCK_SEL_DIV5_3 1
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#define DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE (DEFAULT_BOOT_CLK_CPU-6)
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#endif
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#endif // DEFAULT_BOOT_CLK_CPU
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#define BOOT_RAM_TEXT_SECTION // __attribute__((section(".boot.text")))
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//#define BOOT_RAM_RODATA_SECTION __attribute__((section(".boot.rodata")))
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//#define BOOT_RAM_DATA_SECTION __attribute__((section(".boot.data")))
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//#define BOOT_RAM_BSS_SECTION __attribute__((section(".boot.bss")))
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//extern u32 STACK_TOP;
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//extern volatile UART_LOG_CTL * pUartLogCtl;
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//-------------------------------------------------------------------------
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typedef struct _seg_header {
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uint32 size;
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@ -42,29 +57,37 @@ typedef struct _img2_header {
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//-------------------------------------------------------------------------
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// Function declarations
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LOCAL void RtlBootToFlash(void); // image1
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LOCAL void RtlBootToSram(void); // image1
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LOCAL void EnterImage15(void); // image1
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LOCAL void JtagOn(void); // image1
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LOCAL void RtlBoot1ToSram(void); // image1
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LOCAL void RtlBoot2ToSram(void); // image1
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LOCAL void RtlBoot3ToSram(void); // image1
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LOCAL void RtlBoot4ToSram(void); // image1
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//LOCAL void EnterImage15(void); // image1
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//LOCAL void JtagOn(void); // image1
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extern _LONG_CALL_ VOID HalCpuClkConfig(unsigned char CpuType);
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//extern _LONG_CALL_ VOID HalCpuClkConfig(unsigned char CpuType);
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extern _LONG_CALL_ VOID VectorTableInitRtl8195A(u32 StackP);
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extern _LONG_CALL_ VOID HalInitPlatformLogUartV02(VOID);
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extern _LONG_CALL_ VOID HalInitPlatformTimerV02(VOID);
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//extern _LONG_CALL_ VOID DramInit_rom(IN DRAM_DEVICE_INFO *DramInfo);
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//extern _LONG_CALL_ u32 SdrCalibration_rom(VOID);
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extern _LONG_CALL_ int SdrControllerInit_rom(PDRAM_DEVICE_INFO pDramInfo);
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//#pragma arm section code = ".boot.text";
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//#pragma arm section rodata = ".boot.rodata", rwdata = ".boot.data", zidata = ".boot.bss";
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typedef void (*START_FUNC)(void);
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//-------------------------------------------------------------------------
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/* Start table: */
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START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__ = {
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RtlBootToFlash + 1, // StartFun(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 )
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RtlBootToSram + 1, // PatchWAKE(), Run if ( v40000210 & 0x20000000 )
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RtlBootToSram + 1, // PatchFun0(), Run if ( v40000210 & 0x10000000 )
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RtlBootToSram + 1,// PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
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RtlBootToFlash + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 )
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// EnterImage15 + 1}; // PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 )
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RtlBoot1ToSram + 1, // PatchWAKE(), Run if ( v40000210 & 0x20000000 )
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RtlBoot2ToSram + 1, // PatchFun0(), Run if ( v40000210 & 0x10000000 )
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RtlBoot3ToSram + 1, // PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
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RtlBoot4ToSram + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 )
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//test RtlBootToFlash + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 )
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//-------------------------------------------------------------------------
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/* Set Debug Flags */
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LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() {
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#if CONFIG_DEBUG_LOG > 3
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@ -98,15 +121,6 @@ LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() {
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#endif
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}
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/* RTL Console ROM */
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LOCAL void BOOT_RAM_TEXT_SECTION RtlConsolRam(void) {
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// DiagPrintf("\r\nRTL Console ROM\r\n");
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pUartLogCtl->pTmpLogBuf->UARTLogBuf[0] = '?';
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pUartLogCtl->pTmpLogBuf->BufCount = 1;
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pUartLogCtl->ExecuteCmd = 1;
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RtlConsolTaskRom(pUartLogCtl);
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}
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/* JTAG On */
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LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) {
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ACTCK_VENDOR_CCTRL(ON);
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@ -114,44 +128,92 @@ LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) {
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HalPinCtrlRtl8195A(JTAG, 0, 1);
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}
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/* Enter Image 1.5 */
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LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(void) {
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SetDebugFlgs();
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DBG_8195A(
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"\n===== Enter SRAM-Boot ====\nImg Sign: %s, Go @ 0x%08x\r\n",
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&__image2_validate_code__, __image2_entry_func__);
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#if CONFIG_DEBUG_LOG > 2
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DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(),
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HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
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#endif
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if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) {
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DBG_MISC_ERR("Invalid Image Signature!\n");
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RtlConsolRam();
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}
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__image2_entry_func__();
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/* GetChipId() */
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LOCAL uint8 INFRA_START_SECTION _Get_ChipId() {
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uint8 ChipId = CHIP_ID_8710AF;
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if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
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&ChipId, L25EOUTVOLTAGE) != 1)
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DBG_8195A("Get Chip ID Failed\r");
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return ChipId;
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}
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/* RtlBootToSram */
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LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToSram(void) {
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JtagOn(); /* JTAG On */
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_memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__);
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/*
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* 16 bytes FIFO ... 16*11/38400 = 0.004583 sec
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* (0.005/5)*166666666 = 166666.666 Tcpu
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*/
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LOCAL void INFRA_START_SECTION loguart_wait_tx_fifo_empty(void) {
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if (HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_LOG_UART_EN) {
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int x = 16384;
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while ((!(HAL_READ8(LOG_UART_REG_BASE, 0x14) & BIT6)) && x--)
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; // иначе глючит LogUART, если переключение CLK приходится на вывод символов !
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}
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}
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extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90]
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/*
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LOCAL uint32 _SpicInitParaAllClk[SpicMaxMode * CPU_CLK_TYPE_NO] = {
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0x01310202, 0x011420C2,
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0x03310002, 0x011420C2,
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0x05310002, 0x011420C2,
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0x07310002, 0x011420C2,
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0x09310002, 0x011420C2,
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0x0B310002, 0x011420C2,
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0x11311301, 0x011420C2,
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0x13311201, 0x011420C2,
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0x15311101, 0x011420C2,
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0x17311101, 0x011420C2,
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0x19311101, 0x011420C2,
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0x1B311101, 0x011420C2,
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0x21311301, 0x011420C2,
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0x23311201, 0x011420C2,
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0x25311101, 0x011420C2,
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0x27311101, 0x011420C2,
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0x29311101, 0x011420C2,
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0x2B311101, 0x011420C2
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};
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*/
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/* SYSPlatformInit */
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LOCAL void INFRA_START_SECTION SYSPlatformInit(void) {
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__asm__ __volatile__ ("cpsid f\n");
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HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1,
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HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) & ( ~BIT_SYS_SYSPLL_DIV5_3));
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HalCpuClkConfig(2); // 41.666666 MHz
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// HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) | BIT_SYS_SYSPLL_DIV5_3); // 50.000 MHz
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JtagOn();
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SetDebugFlgs();
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//----- SYS Init
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HAL_SYS_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0,
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(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0) & (~(BIT_MASK_SYS_EEROM_LDO_PAR_07_04 << BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04))) | BIT_SYS_EEROM_LDO_PAR_07_04(6)); // & 0xF0FFFFFF | 0x6000000
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HAL_SYS_CTRL_WRITE32(REG_SYS_XTAL_CTRL1,
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(HAL_SYS_CTRL_READ32(REG_SYS_XTAL_CTRL1) & (~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1))) | BIT_SYS_XTAL_DRV_RF1(1)); // & 0xFFFFFFE7 | 8;
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//----- SDIO_Device_Off
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HAL_PERI_ON_WRITE32(REG_PESOC_HCI_CLK_CTRL0,
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HAL_PERI_ON_READ32(REG_PESOC_HCI_CLK_CTRL0) & (~BIT_SOC_ACTCK_SDIO_DEV_EN));
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HAL_PERI_ON_WRITE32(REG_SOC_HCI_COM_FUNC_EN,
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HAL_PERI_ON_READ32(REG_SOC_HCI_COM_FUNC_EN) & (~(BIT_SOC_HCI_SDIOD_ON_EN | BIT_SOC_HCI_SDIOD_OFF_EN)));
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HAL_PERI_ON_WRITE32(REG_HCI_PINMUX_CTRL,
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HAL_PERI_ON_READ32(REG_HCI_PINMUX_CTRL) & (~(BIT_HCI_SDIOD_PIN_EN)));
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//----- GPIO Adapter
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extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
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_memset(&gBoot_Gpio_Adapter, 0, sizeof(gBoot_Gpio_Adapter));
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_pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
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#ifdef DEFAULT_BOOT_CLK_CPU
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//----- CLK CPU
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loguart_wait_tx_fifo_empty(); // иначе глючит LogUART, если переключение CLK приходится на вывод символов !
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#if DEFAULT_BOOT_CPU_CLOCK_SEL_DIV5_3
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// 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000 Hz
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HalCpuClkConfig(DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE);
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*((int *)(SYSTEM_CTRL_BASE+REG_SYS_SYSPLL_CTRL1)) |= (1<<17);// REG_SYS_SYSPLL_CTRL1 |= BIT_SYS_SYSPLL_DIV5_3
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#else
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// 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
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*((int *) (SYSTEM_CTRL_BASE + REG_SYS_SYSPLL_CTRL1)) &= ~(1 << 17); // REG_SYS_SYSPLL_CTRL1 &= ~BIT_SYS_SYSPLL_DIV5_3
|
||||
HalCpuClkConfig(DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE);
|
||||
#endif // CPU_CLOCK_SEL_DIV5_3
|
||||
#endif // DEFAULT_CLK_CPU
|
||||
//----- System
|
||||
VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
|
||||
HalInitPlatformLogUartV02();
|
||||
HalInitPlatformLogUartV02(); // Show "<RTL8195A>"... :(
|
||||
HalInitPlatformTimerV02();
|
||||
__asm__ __volatile__ ("cpsie f\n");
|
||||
// SdrPowerOff();
|
||||
SDR_PIN_FCTRL(OFF);
|
||||
LDO25M_CTRL(OFF);
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
|
||||
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21));
|
||||
|
||||
SpicInitRtl8195AV02(1, 0); // StartupSpicBaudRate InitBaudRate 1, SpicBitMode 1 StartupSpicBitMode
|
||||
EnterImage15();
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------------------------
|
||||
|
|
@ -265,7 +327,9 @@ LOCAL uint32 BOOT_RAM_TEXT_SECTION load_segs(uint32 faddr, PIMG2HEAD hdr,
|
|||
uint8 segnum = 0;
|
||||
while (1) {
|
||||
uint32 seg_id = get_seg_id(hdr->seg.ldaddr, hdr->seg.size);
|
||||
if (flgload && (seg_id == SEG_ID_SRAM || seg_id == SEG_ID_TCM)) {
|
||||
if (flgload
|
||||
&& (seg_id == SEG_ID_SRAM || seg_id == SEG_ID_TCM
|
||||
|| seg_id == SEG_ID_SDRAM)) {
|
||||
#if CONFIG_DEBUG_LOG > 1
|
||||
DBG_8195A("Load Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n",
|
||||
segnum, faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr,
|
||||
|
|
@ -327,10 +391,7 @@ LOCAL int BOOT_RAM_TEXT_SECTION loadUserImges(int imgnum) {
|
|||
};
|
||||
return imagenum;
|
||||
}
|
||||
;
|
||||
|
||||
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
|
||||
extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
|
||||
//----- IsForceLoadDefaultImg2
|
||||
LOCAL uint8 BOOT_RAM_TEXT_SECTION IsForceLoadDefaultImg2(void) {
|
||||
uint8 gpio_pin[4];
|
||||
|
|
@ -338,7 +399,7 @@ LOCAL uint8 BOOT_RAM_TEXT_SECTION IsForceLoadDefaultImg2(void) {
|
|||
HAL_GPIO_PIN_STATE flg;
|
||||
int result = 0;
|
||||
flashcpy(FLASH_SYSTEM_DATA_ADDR + 0x08, &gpio_pin, sizeof(gpio_pin)); // config data + 8
|
||||
_pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
|
||||
// _pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
|
||||
for (int i = 1; i; i--) {
|
||||
uint8 x = gpio_pin[i];
|
||||
result <<= 1;
|
||||
|
|
@ -358,29 +419,112 @@ LOCAL uint8 BOOT_RAM_TEXT_SECTION IsForceLoadDefaultImg2(void) {
|
|||
HAL_GPIO_DeInit_8195a(&GPIO_Pin);
|
||||
}
|
||||
}
|
||||
_pHAL_Gpio_Adapter->IrqHandle.IrqFun = NULL;
|
||||
// _pHAL_Gpio_Adapter->IrqHandle.IrqFun = NULL;
|
||||
return result;
|
||||
}
|
||||
|
||||
LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToFlash(void) {
|
||||
/* RTL Console ROM */
|
||||
LOCAL void BOOT_RAM_TEXT_SECTION RtlConsolRam(void) {
|
||||
// DiagPrintf("\r\nRTL Console ROM\r\n");
|
||||
pUartLogCtl->pTmpLogBuf->UARTLogBuf[0] = '?';
|
||||
pUartLogCtl->pTmpLogBuf->BufCount = 1;
|
||||
pUartLogCtl->ExecuteCmd = 1;
|
||||
RtlConsolTaskRom(pUartLogCtl);
|
||||
}
|
||||
|
||||
JtagOn(); /* JTAG On */
|
||||
SetDebugFlgs();
|
||||
DBG_8195A("===== Enter FLASH-Boot ====\n");
|
||||
if (HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (1 << BIT_SOC_FLASH_EN)) {
|
||||
SPI_FLASH_PIN_FCTRL(ON);
|
||||
/*
|
||||
if(!SpicCmpDataForCalibrationRtl8195A()) {
|
||||
DBG_8195A("ReInit Spic DIO...\n");
|
||||
SpicInitRtl8195AV02(1, SpicDualBitMode);
|
||||
}
|
||||
*/
|
||||
loadUserImges(IsForceLoadDefaultImg2() + 1);
|
||||
/* Enter Image 1.5 */
|
||||
LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
|
||||
|
||||
if (flg)
|
||||
_memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__);
|
||||
|
||||
SYSPlatformInit();
|
||||
|
||||
if (!flg)
|
||||
DBG_8195A("\r===== Enter FLASH-Boot ====\n");
|
||||
else
|
||||
DBG_8195A("\r===== Enter SRAM-Boot %d ====\n", flg);
|
||||
|
||||
#if CONFIG_DEBUG_LOG > 2
|
||||
DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(),
|
||||
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
|
||||
#endif
|
||||
uint8 ChipId = _Get_ChipId();
|
||||
if (ChipId < CHIP_ID_8195AM) {
|
||||
//----- SDRAM Off
|
||||
SDR_PIN_FCTRL(OFF);
|
||||
LDO25M_CTRL(OFF);
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off
|
||||
} else {
|
||||
//----- SDRAM On
|
||||
LDO25M_CTRL(ON);
|
||||
HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
|
||||
(HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x0e));
|
||||
SDR_PIN_FCTRL(ON);
|
||||
};
|
||||
if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) {
|
||||
DBG_8195A("Invalid Image Signature!\n");
|
||||
SPI_FLASH_PIN_FCTRL(ON);
|
||||
*(uint32 *)(&SpicInitParaAllClk[0][0].BaudRate) = 0x1311301; // patch
|
||||
*(uint32 *)(&SpicInitParaAllClk[1][0].BaudRate) = 0x1311301; // patch
|
||||
SpicInitRtl8195AV02(CPU_CLK_TYPE_NO - 1 - ((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7),
|
||||
SpicDualBitMode);
|
||||
if (!SpicCmpDataForCalibrationRtl8195A()) {
|
||||
DBG_8195A("Error Init Spic DIO!\n");
|
||||
RtlConsolRam();
|
||||
} else
|
||||
DBG_8195A("Go @ 0x%08x\r\n", __image2_entry_func__);
|
||||
}
|
||||
if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена?
|
||||
// extern DRAM_DEVICE_INFO SdrDramInfo_rom; // 50 MHz
|
||||
if (!SdrControllerInit_rom(&SdrDramInfo)) { // 100 MHz
|
||||
DBG_8195A("SDR Controller Init fail!\n");
|
||||
RtlConsolRam();
|
||||
}
|
||||
#if 0 // Test SDRAM
|
||||
else {
|
||||
uint32 *ptr = SDR_SDRAM_BASE;
|
||||
uint32 tt = 0x55AA55AA;
|
||||
for (int i = 0; i < 512 * 1024; i++) {
|
||||
ptr[i] = tt++;
|
||||
};
|
||||
tt = 0x55AA55AA;
|
||||
for (int i = 0; i < 512 * 1024; i++) {
|
||||
if (ptr[i] != tt) {
|
||||
DBG_8195A("SDR err %p %p != %p!\n", &ptr[i], ptr[i], tt);
|
||||
RtlConsolRam();
|
||||
}
|
||||
tt++;
|
||||
};
|
||||
DBG_8195A("SDR tst end\n");
|
||||
};
|
||||
#endif // test
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21));
|
||||
};
|
||||
if (!flg)
|
||||
loadUserImges(IsForceLoadDefaultImg2() + 1);
|
||||
if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) {
|
||||
DBG_MISC_ERR("Invalid Image Signature!\n");
|
||||
RtlConsolRam();
|
||||
}
|
||||
DBG_8195A("Img Sign: %s, Go @ 0x%08x\r\n", &__image2_validate_code__,
|
||||
__image2_entry_func__);
|
||||
__image2_entry_func__();
|
||||
}
|
||||
|
||||
/* RtlBootToSram */
|
||||
LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot1ToSram(void) {
|
||||
EnterImage15(1);
|
||||
}
|
||||
/* RtlBootToSram */
|
||||
LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot2ToSram(void) {
|
||||
EnterImage15(2);
|
||||
}
|
||||
/* RtlBootToSram */
|
||||
LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot3ToSram(void) {
|
||||
EnterImage15(3);
|
||||
}
|
||||
/* RtlBootToSram */
|
||||
LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot4ToSram(void) {
|
||||
EnterImage15(4);
|
||||
}
|
||||
|
||||
LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToFlash(void) {
|
||||
EnterImage15(0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -56,6 +56,15 @@ void INFRA_START_SECTION VectorTableOverrideRtl8195A(u32 StackP) {
|
|||
}
|
||||
*/
|
||||
|
||||
/*
|
||||
* 16 bytes FIFO ... 16*11/38400 = 0.004583 sec
|
||||
* (0.005/5)*166666666 = 166666.666
|
||||
*/
|
||||
LOCAL void INFRA_START_SECTION loguart_wait_tx_fifo_empty(void) {
|
||||
int x = 16384;
|
||||
while((!(HAL_READ8(LOG_UART_REG_BASE, 0x14) & BIT6)) && x--);
|
||||
}
|
||||
|
||||
//----- SYSPlatformInit
|
||||
void INFRA_START_SECTION SYSPlatformInit(void) {
|
||||
HAL_SYS_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0,
|
||||
|
|
@ -66,6 +75,23 @@ void INFRA_START_SECTION SYSPlatformInit(void) {
|
|||
(HAL_SYS_CTRL_READ32(REG_SYS_XTAL_CTRL1)
|
||||
& (~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1)))
|
||||
| BIT_SYS_XTAL_DRV_RF1(1)); // & 0xFFFFFFE7 | 8;
|
||||
if(HalGetCpuClk() != PLATFORM_CLOCK) {
|
||||
//----- CLK CPU
|
||||
loguart_wait_tx_fifo_empty(); // иначе глючит LogUART, если переключение CLK приходится на вывод символов !
|
||||
#if CPU_CLOCK_SEL_DIV5_3
|
||||
// 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000 Hz
|
||||
HalCpuClkConfig(CPU_CLOCK_SEL_VALUE);
|
||||
*((int *)(SYSTEM_CTRL_BASE+REG_SYS_SYSPLL_CTRL1)) |= (1<<17);// REG_SYS_SYSPLL_CTRL1 |= BIT_SYS_SYSPLL_DIV5_3
|
||||
#else
|
||||
// 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
|
||||
*((int *) (SYSTEM_CTRL_BASE + REG_SYS_SYSPLL_CTRL1)) &= ~(1 << 17); // REG_SYS_SYSPLL_CTRL1 &= ~BIT_SYS_SYSPLL_DIV5_3
|
||||
HalCpuClkConfig(CPU_CLOCK_SEL_VALUE);
|
||||
#endif // CPU_CLOCK_SEL_DIV5_3
|
||||
//----- System
|
||||
VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
|
||||
HalInitPlatformLogUartV02(); // Show "<RTL8195A>"... :(
|
||||
HalInitPlatformTimerV02();
|
||||
};
|
||||
}
|
||||
|
||||
//----- SDIO_Device_Off
|
||||
|
|
@ -93,11 +119,11 @@ __weak int main(void) {
|
|||
while (pUartLogCtl->ExecuteEsc != 1);
|
||||
pUartLogCtl->RevdNo = 0;
|
||||
pUartLogCtl->BootRdy = 1;
|
||||
DiagPrintf("\r<RTL8710AF>");
|
||||
DiagPrintf("\r<RTL>");
|
||||
while (1) {
|
||||
while (pUartLogCtl->ExecuteCmd != 1);
|
||||
UartLogCmdExecute(pUartLogCtl);
|
||||
DiagPrintf("\r<RTL8710AF>");
|
||||
DiagPrintf("\r<RTL>");
|
||||
pUartLogCtl->ExecuteCmd = 0;
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -107,72 +133,65 @@ extern const unsigned char cus_sig[32];
|
|||
//----- InfraStart
|
||||
void INFRA_START_SECTION InfraStart(void) {
|
||||
// NewVectorTable[2] = HalNMIHandler_Patch;
|
||||
// HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL0, HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL0) | BIT4);
|
||||
DBG_8195A("===== Enter Image: %s ====\n", cus_sig);
|
||||
#if CONFIG_DEBUG_LOG > 3
|
||||
DBG_8195A("\rCPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
|
||||
#endif
|
||||
#ifdef CONFIG_TIMER_MODULE
|
||||
HalTimerOpInit_Patch((VOID*) (&HalTimerOp));
|
||||
#endif
|
||||
// ShowRamBuildInfo(); // app_start.c: VOID ShowRamBuildInfo(VOID)
|
||||
// ShowRamBuildInfo(); // app_start.c: VOID ShowRamBuildInfo(VOID)
|
||||
memset(&__bss_start__, 0, &__bss_end__ - &__bss_start__);
|
||||
|
||||
//- Должно быть в boot !?
|
||||
rtl_libc_init(); // ROM Lib C init (rtl_printf!)
|
||||
//- Должно быть в boot
|
||||
extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
|
||||
memset(&gBoot_Gpio_Adapter, 0, sizeof(gBoot_Gpio_Adapter));
|
||||
_pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
|
||||
//-
|
||||
|
||||
rtl_libc_init(); // ROM Lib C init
|
||||
|
||||
int flash_en = HAL_PERI_ON_READ32(REG_SOC_FUNC_EN)
|
||||
& (1 << BIT_SOC_FLASH_EN);
|
||||
if (flash_en) {
|
||||
SPI_FLASH_PIN_FCTRL(ON);
|
||||
if(!SpicCmpDataForCalibrationRtl8195A()) {
|
||||
DBG_8195A("ReInit Spic DIO...\n");
|
||||
SpicInitRtl8195AV02(1, SpicDualBitMode);
|
||||
#if 0
|
||||
SpicFlashInitRtl8195A(SpicDualBitMode);
|
||||
if(!SpicCmpDataForCalibrationRtl8195A()) {
|
||||
// TODO: Spic Not Init!
|
||||
DBG_8195A("Spic error Init!\n"); while(1);
|
||||
};
|
||||
#endif
|
||||
};
|
||||
// Load SpicInitParaAllClk table
|
||||
SpicNVMCalLoadAll();
|
||||
SpicReadIDRtl8195A();
|
||||
};
|
||||
while(!(HAL_READ8(LOG_UART_REG_BASE, 0x14) & BIT6)); // иначе глючит LogUART, если переключение CLK приходится на вывод символов !
|
||||
#if CPU_CLOCK_SEL_DIV5_3
|
||||
// 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000 Hz
|
||||
HalCpuClkConfig(CPU_CLOCK_SEL_VALUE);
|
||||
*((int *)(SYSTEM_CTRL_BASE+REG_SYS_SYSPLL_CTRL1)) |= (1<<17);// REG_SYS_SYSPLL_CTRL1 |= BIT_SYS_SYSPLL_DIV5_3
|
||||
#else
|
||||
// 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
|
||||
*((int *) (SYSTEM_CTRL_BASE + REG_SYS_SYSPLL_CTRL1)) &= ~(1 << 17); // REG_SYS_SYSPLL_CTRL1 &= ~BIT_SYS_SYSPLL_DIV5_3
|
||||
HalCpuClkConfig(CPU_CLOCK_SEL_VALUE);
|
||||
#endif
|
||||
SDIO_Device_Off();
|
||||
HalReInitPlatformLogUartV02();
|
||||
SystemCoreClockUpdate();
|
||||
SYSPlatformInit();
|
||||
HalTimerOpInit_Patch((VOID*) (&HalTimerOp));
|
||||
//-
|
||||
SystemCoreClockUpdate();
|
||||
En32KCalibration();
|
||||
|
||||
#if CONFIG_DEBUG_LOG > 2
|
||||
DBG_8195A("\rCPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
|
||||
#endif
|
||||
_memset(SpicInitParaAllClk, 0, sizeof(SpicInitParaAllClk));
|
||||
*(uint32 *)(&SpicInitParaAllClk[0][0].BaudRate) = 0x1311301; // patch
|
||||
*(uint32 *)(&SpicInitParaAllClk[1][0].BaudRate) = 0x1311301; // patch
|
||||
SPI_FLASH_PIN_FCTRL(ON);
|
||||
uint8 SpicBaudRate = CPU_CLK_TYPE_NO - 1 - ((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7);
|
||||
SpicInitRtl8195AV02(SpicBaudRate, SpicDualBitMode);
|
||||
if(!SpicCmpDataForCalibrationRtl8195A()) {
|
||||
DBG_8195A("ReInit Spic to SIO...\n");
|
||||
SpicInitRtl8195AV02(SpicBaudRate, SpicOneBitMode);
|
||||
if(!SpicCmpDataForCalibrationRtl8195A()) {
|
||||
DBG_8195A("Error Init Spic!\n");
|
||||
};
|
||||
};
|
||||
SpicFlashInitRtl8195A(SpicDualBitMode); // SpicReadIDRtl8195A(); SpicDualBitMode
|
||||
uint8 ChipId = HalGetChipId();
|
||||
if (ChipId >= CHIP_ID_8195AM) {
|
||||
#ifdef CONFIG_SDR_EN
|
||||
if((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена?
|
||||
SdrCtrlInit();
|
||||
if(SdrControllerInit()) {
|
||||
DBG_8195A("SDR Controller Init fail!\n");
|
||||
};
|
||||
};
|
||||
#endif
|
||||
// clear SDRAM bss
|
||||
extern uint8 __sdram_bss_start__[];
|
||||
extern uint8 __sdram_bss_end__[];
|
||||
if((uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__ > 0)
|
||||
memset(__sdram_bss_start__, 0, (uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__);
|
||||
}
|
||||
else
|
||||
{
|
||||
//----- SDRAM Off
|
||||
SDR_PIN_FCTRL(OFF);
|
||||
LDO25M_CTRL(OFF);
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off
|
||||
};
|
||||
SPI_FLASH_PIN_FCTRL(OFF);
|
||||
InitSoCPM();
|
||||
VectorTableInitForOSRtl8195A(&vPortSVCHandler, &xPortPendSVHandler,
|
||||
&xPortSysTickHandler);
|
||||
if (flash_en)
|
||||
SpicFlashInitRtl8195A(SpicDualBitMode); // DIO
|
||||
SPI_FLASH_PIN_FCTRL(OFF);
|
||||
#ifdef CONFIG_SDR_EN
|
||||
// clear SDRAM bss
|
||||
extern u8 __sdram_bss_start__[];
|
||||
extern u8 __sdram_bss_end__[];
|
||||
if((int)__sdram_bss_end__-(int)__sdram_bss_start__ > 0)
|
||||
memset(__sdram_bss_start__, 0, (int)__sdram_bss_end__-(int)__sdram_bss_start__);
|
||||
#endif
|
||||
// force SP align to 8 byte not 4 byte (initial SP is 4 byte align)
|
||||
__asm(
|
||||
"mov r0, sp\n"
|
||||
|
|
|
|||
|
|
@ -47,12 +47,12 @@ HAL_Pwm_Init(
|
|||
pPwmAdapt->sel = sel;
|
||||
timer_id = PWMTimerIdx[pwm_id];
|
||||
pPwmAdapt->gtimer_id = timer_id;
|
||||
|
||||
/*
|
||||
if (_FALSE == FunctionChk((pPwmAdapt->pwm_id + PWM0), pPwmAdapt->sel)) {
|
||||
DBG_PWM_WARN("HAL_Pwm_Init: Warning for RTL8710AF\n");
|
||||
// return HAL_ERR_HW;
|
||||
}
|
||||
|
||||
*/
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
return HAL_Pwm_Init_8195a(pPwmAdapt);
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -19,8 +19,8 @@
|
|||
#endif
|
||||
|
||||
#if !USE_SRC_ONLY_BOOT
|
||||
#define SDRAM_INIT_USE_TCM_HEAP
|
||||
#define SDRAM_INIT_USE_FLASH_API
|
||||
//#define SDRAM_INIT_USE_TCM_HEAP
|
||||
//#define SDRAM_INIT_USE_FLASH_API
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -44,7 +44,9 @@
|
|||
//#define CONFIG_SDR_VERIFY
|
||||
|
||||
extern SPIC_INIT_PARA SpicInitParaAllClk[3][CPU_CLK_TYPE_NO];
|
||||
extern DRAM_DEVICE_INFO SdrDramInfo;
|
||||
|
||||
/*
|
||||
HAL_CUT_B_RAM_DATA_SECTION
|
||||
DRAM_INFO SdrDramDev = {
|
||||
DRAM_INFO_TYPE,
|
||||
|
|
@ -91,7 +93,7 @@ DRAM_DEVICE_INFO SdrDramInfo = {
|
|||
DRAM_TIMING_TCK,
|
||||
DFI_RATIO_1
|
||||
};
|
||||
|
||||
*/
|
||||
|
||||
#define FPGA
|
||||
#define FPGA_TEMP
|
||||
|
|
@ -132,8 +134,8 @@ u32 SdrCalibration(VOID);
|
|||
#ifndef SDRAM_INIT_USE_TCM_HEAP
|
||||
#if !USE_SRC_ONLY_BOOT
|
||||
//3 Note: stack overfloat if the arrary is declared in the task
|
||||
HAL_CUT_B_RAM_DATA_SECTION
|
||||
u32 AvaWds[2][REC_NUM];
|
||||
//HAL_CUT_B_RAM_DATA_SECTION
|
||||
extern u32 AvaWds[2][REC_NUM];
|
||||
#endif
|
||||
#else
|
||||
typedef struct {
|
||||
|
|
@ -382,7 +384,9 @@ VOID
|
|||
){
|
||||
// ConfigDebugErr |= _DBG_MISC_;
|
||||
// DBG_8195A("SDR Ctrl Init\n");
|
||||
HAL_WRITE32(0x40000000, 0x40, ((HAL_READ32(0x40000000, 0x40)&0xfffff)|0xe00000));
|
||||
HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
|
||||
((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x0e)));
|
||||
|
||||
LDO25M_CTRL(ON);
|
||||
}
|
||||
|
||||
|
|
@ -395,8 +399,8 @@ VOID
|
|||
// ConfigDebugErr |= _DBG_MISC_;
|
||||
DBG_8195A("SDR Controller Init\n");
|
||||
|
||||
HAL_WRITE32(0x40000000, 0x40,
|
||||
((HAL_READ32(0x40000000, 0x40)&0xfffff)|0x300000));
|
||||
HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
|
||||
((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03)));
|
||||
|
||||
SRAM_MUX_CFG(0x2);
|
||||
|
||||
|
|
@ -435,6 +439,7 @@ DramInit (
|
|||
IN DRAM_DEVICE_INFO *DramInfo
|
||||
)
|
||||
{
|
||||
DBG_8195A("%s(%p)\n", __func__, DramInfo);
|
||||
u32 CsBstLen = 0; // 0:bst_4, 1:bst_8
|
||||
u32 CasWr = 0;//, CasWrT; // cas write latency
|
||||
u32 CasRd = 0, CasRdT = 0, CrlSrt = 0; // cas read latency
|
||||
|
|
@ -449,7 +454,7 @@ DramInit (
|
|||
u32 DfiRate;
|
||||
volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
|
||||
ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
|
||||
ms_ctrl_0_map = ms_ctrl_0_map;
|
||||
// ms_ctrl_0_map = ms_ctrl_0_map;
|
||||
|
||||
DfiRate = 1 << (u32) (DramInfo->DfiRate);
|
||||
DrmaPeriod = (DramInfo->DdrPeriodPs)*(DfiRate); // according DFI_RATE to setting
|
||||
|
|
@ -460,7 +465,7 @@ DramInit (
|
|||
CrTwr = ((DramInfo->Timing->TwrPs) / DrmaPeriod) + 3;
|
||||
|
||||
if (CrTwr < DramMaxWr) {
|
||||
CrTwr = CrTwr;
|
||||
// CrTwr = CrTwr;
|
||||
}
|
||||
else {
|
||||
CrTwr = DramMaxWr;
|
||||
|
|
@ -745,6 +750,7 @@ SdrCalibration(
|
|||
#else
|
||||
// u32 Value32;
|
||||
#endif
|
||||
DBG_8195A("%s()\n", __func__);
|
||||
u32 RdPipe = 0, TapCnt = 0, Pass = 0, AvaWdsCnt = 0;
|
||||
u32 RdPipeCounter, RecNum[2], RecRdPipe[2];//, AvaWds[2][REC_NUM];
|
||||
BOOL RdPipeFlag, PassFlag = 0, Result;
|
||||
|
|
@ -798,7 +804,7 @@ SdrCalibration(
|
|||
#ifdef SDRAM_INIT_USE_TCM_HEAP
|
||||
pAvaWds AvaWds = (pAvaWds) tcm_heap_calloc(sizeof(u32)*REC_NUM*2);
|
||||
#else
|
||||
_memset((u8*)AvaWds, 0, sizeof(u32)*REC_NUM*2);
|
||||
_memset((u8*)AvaWds, 0, sizeof(AvaWds));
|
||||
#endif
|
||||
#else
|
||||
u32 AvaWds[2][REC_NUM];
|
||||
|
|
@ -807,8 +813,8 @@ SdrCalibration(
|
|||
|
||||
volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
|
||||
ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
|
||||
ms_ctrl_0_map = ms_ctrl_0_map;
|
||||
PassFlag = PassFlag;
|
||||
// ms_ctrl_0_map = ms_ctrl_0_map;
|
||||
// PassFlag = PassFlag;
|
||||
RdPipeCounter =0;
|
||||
|
||||
// DBG_8195A("%d\n",__LINE__);
|
||||
|
|
@ -1004,7 +1010,7 @@ SdrCalibration(
|
|||
return Result;
|
||||
} // SdrCalibration
|
||||
|
||||
HAL_RAM_DATA_SECTION
|
||||
// HAL_RAM_DATA_SECTION
|
||||
/*
|
||||
|
||||
HAL_SDRC_TEXT_SECTION
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@ SECTION SPIC_INIT_PARA SpicInitParaAllClk[CPU_CLK_TYPE_NO] = {{0,0,0,0},
|
|||
{0,0,0,0},
|
||||
{0,0,0,0},};
|
||||
#else
|
||||
extern HAL_FLASH_DATA_SECTION
|
||||
extern // HAL_FLASH_DATA_SECTION
|
||||
SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // in rtl_bios_data.c
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -305,8 +305,8 @@ SECTIONS
|
|||
HalTimerIrq2To7Handle = 0xee59;
|
||||
HalGetTimerIdRtl8195a = 0xef09;
|
||||
HalTimerInitRtl8195a = 0xef3d;
|
||||
HalTimerDisRtl8195a = 0xf069;
|
||||
HalTimerEnRtl8195a = 0xf089;
|
||||
HalTimerDisRtl8195a = 0xf069; /* error! */
|
||||
HalTimerEnRtl8195a = 0xf089; /* error! */
|
||||
HalTimerReadCountRtl8195a = 0xf0a9;
|
||||
HalTimerIrqClearRtl8195a = 0xf0bd;
|
||||
HalTimerDumpRegRtl8195a = 0xf0d1;
|
||||
|
|
@ -624,7 +624,7 @@ SECTIONS
|
|||
rom_wps_rcons = 0x35d88;
|
||||
rom_wps_Td4s = 0x35d94;
|
||||
rom_wps_Td0 = 0x35e94;
|
||||
str_rom_57ch3Dch0A = 0x3ed05;
|
||||
str_rom_57ch3Dch0A = 0x3ed05; /* "========================================================\n" */
|
||||
str_rom_0123456789ABCDEF = 0x3ec24; /* "0123456789ABCDEF" */
|
||||
str_rom_hex_addr = 0x442D6; /* "[Addr] .0 .1 .2 .3 .4 .5 .6 .7 .8 .9 .A .B .C .D .E .F\r\n" */
|
||||
str_rom_0123456789abcdef = 0x44660; /* "0123456789abcdef" */
|
||||
|
|
|
|||
|
|
@ -208,7 +208,7 @@ extern DRAM_MODE_REG_INFO SdrDramModeReg; // 10001c30
|
|||
0 } /* Mode2Cwl */
|
||||
extern DRAM_INFO SdrDramDev; // 10001c4c
|
||||
#define DRAM_INFO_INIT() { DRAM_INFO_TYPE, DRAM_INFO_COL_ADDR_WTH,DRAM_INFO_BANK_SZ, DRAM_INFO_DQ_WTH }
|
||||
//extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // SpicInitParaAllClk[3][6] !
|
||||
extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90]
|
||||
|
||||
/* ROM + "C" standard library */
|
||||
extern struct _reent * _rtl_impure_ptr; // 10001c60 = { &impure_reent };
|
||||
|
|
|
|||
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4760
build/obj/build.nmap
4760
build/obj/build.nmap
File diff suppressed because it is too large
Load diff
|
|
@ -25,7 +25,7 @@
|
|||
#undef CONFIG_MP
|
||||
#undef CONFIG_CP
|
||||
#undef CONFIG_FT
|
||||
#define RTL8195A 7
|
||||
#define RTL8195A 1
|
||||
/* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz,
|
||||
6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */
|
||||
#define CONFIG_CPU_CLK 1
|
||||
|
|
@ -243,7 +243,7 @@
|
|||
#define CPU_CLOCK_SEL_VALUE (CONFIG_CPU_CLK-6)
|
||||
#endif
|
||||
|
||||
#if CPU__CLK_DIV5_3
|
||||
#if CPU_CLOCK_SEL_DIV5_3
|
||||
#define PLATFORM_CLOCK (200000000ul>>CPU_CLOCK_SEL_VALUE)
|
||||
#else
|
||||
#define PLATFORM_CLOCK (((200000000ul*5ul)/6ul)>>CPU_CLOCK_SEL_VALUE)
|
||||
|
|
|
|||
|
|
@ -224,7 +224,7 @@ SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_i2s.c
|
|||
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_nfc.c
|
||||
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_pcm.c
|
||||
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_pwm.c
|
||||
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c
|
||||
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c
|
||||
#SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_ssi.c
|
||||
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_timer.c
|
||||
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_uart.c
|
||||
|
|
|
|||
Loading…
Reference in a new issue