From d9bd70640894a562eb8faca5d013331cf63f545b Mon Sep 17 00:00:00 2001 From: pvvx Date: Thu, 16 Mar 2017 05:01:44 +0300 Subject: [PATCH] boot v0.1 --- .../component/common/api/at_cmd/atcmd_sys.c | 33 +- .../application/xmodem/uart_fw_update.c | 12 +- .../mbed/targets/hal/rtl8195a/flash_api.c | 2 +- .../Source/portable/MemMang/heap_5.c | 2 +- .../realtek/8195a/cmsis/device/app_start.c | 4 +- .../soc/realtek/8195a/fwlib/hal_platform.h | 2 - .../realtek/8195a/fwlib/hal_sdr_controller.h | 2 +- .../8195a/fwlib/ram_lib/rtl_bios_data.c | 2 +- .../realtek/8195a/fwlib/ram_lib/rtl_boot.c | 296 +- .../soc/realtek/8195a/fwlib/ram_lib/startup.c | 133 +- .../soc/realtek/8195a/fwlib/src/hal_pwm.c | 4 +- .../8195a/fwlib/src/hal_sdr_controller.c | 34 +- .../8195a/fwlib/src/hal_spi_flash_ram.c | 2 +- .../bsp/lib/common/GCC/export-rom_v04.txt | 6 +- .../misc/rtl_std_lib/include/rtl_bios_data.h | 2 +- build/bin/ota.bin | Bin 297980 -> 298160 bytes build/bin/ram_1.p.bin | Bin 7360 -> 7732 bytes build/bin/ram_2.bin | Bin 297944 -> 298124 bytes build/bin/ram_2.ns.bin | Bin 297960 -> 298140 bytes build/bin/ram_2.p.bin | Bin 297960 -> 298140 bytes build/bin/ram_all.bin | Bin 343032 -> 343212 bytes build/obj/build.nmap | 4760 +++++++++-------- project/inc/platform_autoconf.h | 4 +- sdkset.mk | 2 +- 24 files changed, 2734 insertions(+), 2568 deletions(-) diff --git a/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_sys.c b/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_sys.c index c11e941..20b7532 100644 --- a/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_sys.c +++ b/RTL00_SDKV35a/component/common/api/at_cmd/atcmd_sys.c @@ -146,12 +146,12 @@ void fATSR(void *arg) #if CONFIG_UART_XMODEM void fATSY(void *arg) { -#ifdef RTL8710AF - OTU_FW_Update(0, 0, 115200); -#else - // use xmodem to update, RX: PA_6, TX: PA_7, baudrate: 1M - OTU_FW_Update(0, 2, 115200); -#endif + if (HalGetChipId() < CHIP_ID_8195AM) { + OTU_FW_Update(0, 0, 115200); + } else { + // use xmodem to update, RX: PA_6, TX: PA_7, baudrate: 1M + OTU_FW_Update(0, 2, 115200); + } } #endif @@ -1166,17 +1166,18 @@ void fATSL(void *arg) { #if CONFIG_UART_XMODEM void fATSX(void *arg) { -#ifdef RTL8710AF - // use xmodem to update, RX: PC_0, TX: PC_3, baudrate: 1M + if (HalGetChipId() < CHIP_ID_8195AM) { + + // use xmodem to update, RX: PC_0, TX: PC_3, baudrate: 1M OTU_FW_Update(0, 0, 115200); - // use xmodem to update, RX: PE_3, TX: PE_0, baudrate: 1M - // JTAG Off! - // OTU_FW_Update(0, 1, 115200); -#else -//#error "Set OTU_FW_Update UARTx pins!" - // use xmodem to update, RX: PA_6, TX: PA_7, baudrate: 1M - OTU_FW_Update(0, 2, 115200); -#endif + // use xmodem to update, RX: PE_3, TX: PE_0, baudrate: 1M + // JTAG Off! + // OTU_FW_Update(0, 1, 115200); + } + else { + // use xmodem to update, RX: PA_6, TX: PA_7, baudrate: 1M + OTU_FW_Update(0, 2, 115200); + }; at_printf("\r\n[ATSX] OK"); } #endif diff --git a/RTL00_SDKV35a/component/common/application/xmodem/uart_fw_update.c b/RTL00_SDKV35a/component/common/application/xmodem/uart_fw_update.c index a318a88..6373916 100644 --- a/RTL00_SDKV35a/component/common/application/xmodem/uart_fw_update.c +++ b/RTL00_SDKV35a/component/common/application/xmodem/uart_fw_update.c @@ -226,11 +226,7 @@ u32 xModem_Frame_Img2(char *ptr, unsigned int frame_num, unsigned int frame_siz return rx_len; } */ -#ifdef RTL8710AF - if (fw_img2_size > (0x80000-0x0B000)) { -#else - if (fw_img2_size > (2*1024*1024)) { -#endif + if (fw_img2_size > ((HalGetChipId() < CHIP_ID_8195AM) ? (0x80000-0x0B000) : (2*1024*1024))) { DBG_MISC_ERR("OTU: fw_img2_addr=0x%x fw_img2_size(%d) to Big!\n", fw_img2_addr, fw_img2_size); fw_img1_size = 0; fw_img2_size = 0; @@ -307,11 +303,7 @@ u32 xModem_Frame_Img2(char *ptr, unsigned int frame_num, unsigned int frame_siz return rx_len; } */ -#ifdef RTL8710AF - if (fw_img2_size > (0x80000 - fw_img3_addr)) { -#else - if (fw_img2_size > (2*1024*1024)) { -#endif + if (fw_img2_size > ((HalGetChipId() < CHIP_ID_8195AM) ? (0x80000 - fw_img3_addr) : (2*1024*1024))) { DBG_MISC_ERR("OTU: fw_img3_addr=0x%x fw_img2_size(%d) to Big!\n", fw_img3_addr, fw_img3_size); fw_img3_size = 0; return rx_len; diff --git a/RTL00_SDKV35a/component/common/mbed/targets/hal/rtl8195a/flash_api.c b/RTL00_SDKV35a/component/common/mbed/targets/hal/rtl8195a/flash_api.c index d633a8c..6a8d455 100644 --- a/RTL00_SDKV35a/component/common/mbed/targets/hal/rtl8195a/flash_api.c +++ b/RTL00_SDKV35a/component/common/mbed/targets/hal/rtl8195a/flash_api.c @@ -21,7 +21,7 @@ #include "flash_api.h" extern u32 ConfigDebugInfo; -extern SPIC_INIT_PARA SpicInitParaAllClk[3][CPU_CLK_TYPE_NO]; +extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // SpicMaxMode = 3, CPU_CLK_TYPE_NO = 6 ! _LONG_CALL_ extern VOID SpicWaitBusyDoneRtl8195A(VOID); diff --git a/RTL00_SDKV35a/component/os/freertos/freertos_v8.1.2/Source/portable/MemMang/heap_5.c b/RTL00_SDKV35a/component/os/freertos/freertos_v8.1.2/Source/portable/MemMang/heap_5.c index 4964a44..f2ce52c 100644 --- a/RTL00_SDKV35a/component/os/freertos/freertos_v8.1.2/Source/portable/MemMang/heap_5.c +++ b/RTL00_SDKV35a/component/os/freertos/freertos_v8.1.2/Source/portable/MemMang/heap_5.c @@ -538,7 +538,7 @@ const HeapRegion_t *pxHeapRegion; pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] ); - int chip_id = HalGetChipId(); + uint8 chip_id = HalGetChipId(); while( pxHeapRegion->xSizeInBytes > 0 ) { if(pxHeapRegion->pucStartAddress > 0x20000000 diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/app_start.c b/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/app_start.c index 70276bd..07ff402 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/app_start.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/app_start.c @@ -138,11 +138,11 @@ _WEAK int main(void) while(pUartLogCtl->ExecuteEsc != 1); pUartLogCtl->RevdNo = 0; pUartLogCtl->BootRdy = 1; - DiagPrintf("\r"); + DiagPrintf("\r"); while(1) { while(pUartLogCtl->ExecuteCmd != 1 ); UartLogCmdExecute(pUartLogCtl); - DiagPrintf("\r"); + DiagPrintf("\r"); pUartLogCtl->ExecuteCmd = 0; } diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_platform.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_platform.h index 41f1126..61b37a8 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_platform.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_platform.h @@ -7,7 +7,6 @@ * possession or use of this module requires written permission of RealTek. */ - #ifndef _HAL_PLATFORM_ #define _HAL_PLATFORM_ @@ -16,7 +15,6 @@ #define SYSTEM_CLK PLATFORM_CLOCK - #define PERIPHERAL_IRQ_STATUS 0x04 #define PERIPHERAL_IRQ_MODE 0x08 #define PERIPHERAL_IRQ_EN 0x0C diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_sdr_controller.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_sdr_controller.h index cb09174..89c99bc 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_sdr_controller.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_sdr_controller.h @@ -103,7 +103,7 @@ typedef struct _DRAM_DEVICE_INFO_ { DRAM_TIMING_INFO *Timing; u32 DdrPeriodPs; DFI_RATIO_TYPE *DfiRate; -}DRAM_DEVICE_INFO; +} DRAM_DEVICE_INFO, *PDRAM_DEVICE_INFO; //====================================================== diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c index 3328a70..9826f15 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c @@ -169,7 +169,7 @@ __attribute__((__section__(".sdr.rand2.data"))) u32 _sdr_rnd2_c = 7654321, _sdr_ // 100020BC, 100020B8, 100020B4 HAL_GPIO_ADAPTER PINMUX_RAM_DATA_SECTION gBoot_Gpio_Adapter; // 100020C0 [300=0x12c] -// SPIC_INIT_PARA HAL_FLASH_DATA_SECTION SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90] +//SPIC_INIT_PARA HAL_FLASH_DATA_SECTION SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90] #ifndef PRESENT_IMAGE2 IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0; //= { InfraStart + 1 }; diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c index 50a4488..93b9f7f 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c @@ -1,5 +1,5 @@ /* - * (SRAM) Debug BootLoader + * BootLoader * Created on: 12/02/2017 * Author: pvvx */ @@ -11,16 +11,31 @@ //------------------------------------------------------------------------- // Data declarations -//extern u32 STACK_TOP; -//extern volatile UART_LOG_CTL * pUartLogCtl; #define DEFAULT_BAUDRATE UART_BAUD_RATE_38400 +/* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz, + 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */ +#define DEFAULT_BOOT_CLK_CPU 1 // Warning! If Start CLK > 100 MHz -> Errors SPIC function in Ameba SDK! + +#ifdef DEFAULT_BOOT_CLK_CPU +#if DEFAULT_BOOT_CLK_CPU < 6 +#define DEFAULT_BOOT_CPU_CLOCK_SEL_DIV5_3 0 +#define DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE DEFAULT_BOOT_CLK_CPU +#else +#define DEFAULT_BOOT_CPU_CLOCK_SEL_DIV5_3 1 +#define DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE (DEFAULT_BOOT_CLK_CPU-6) +#endif +#endif // DEFAULT_BOOT_CLK_CPU + #define BOOT_RAM_TEXT_SECTION // __attribute__((section(".boot.text"))) //#define BOOT_RAM_RODATA_SECTION __attribute__((section(".boot.rodata"))) //#define BOOT_RAM_DATA_SECTION __attribute__((section(".boot.data"))) //#define BOOT_RAM_BSS_SECTION __attribute__((section(".boot.bss"))) +//extern u32 STACK_TOP; +//extern volatile UART_LOG_CTL * pUartLogCtl; + //------------------------------------------------------------------------- typedef struct _seg_header { uint32 size; @@ -42,29 +57,37 @@ typedef struct _img2_header { //------------------------------------------------------------------------- // Function declarations LOCAL void RtlBootToFlash(void); // image1 -LOCAL void RtlBootToSram(void); // image1 -LOCAL void EnterImage15(void); // image1 -LOCAL void JtagOn(void); // image1 +LOCAL void RtlBoot1ToSram(void); // image1 +LOCAL void RtlBoot2ToSram(void); // image1 +LOCAL void RtlBoot3ToSram(void); // image1 +LOCAL void RtlBoot4ToSram(void); // image1 +//LOCAL void EnterImage15(void); // image1 +//LOCAL void JtagOn(void); // image1 -extern _LONG_CALL_ VOID HalCpuClkConfig(unsigned char CpuType); +//extern _LONG_CALL_ VOID HalCpuClkConfig(unsigned char CpuType); extern _LONG_CALL_ VOID VectorTableInitRtl8195A(u32 StackP); extern _LONG_CALL_ VOID HalInitPlatformLogUartV02(VOID); extern _LONG_CALL_ VOID HalInitPlatformTimerV02(VOID); +//extern _LONG_CALL_ VOID DramInit_rom(IN DRAM_DEVICE_INFO *DramInfo); +//extern _LONG_CALL_ u32 SdrCalibration_rom(VOID); +extern _LONG_CALL_ int SdrControllerInit_rom(PDRAM_DEVICE_INFO pDramInfo); //#pragma arm section code = ".boot.text"; //#pragma arm section rodata = ".boot.rodata", rwdata = ".boot.data", zidata = ".boot.bss"; typedef void (*START_FUNC)(void); +//------------------------------------------------------------------------- /* Start table: */ START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__ = { RtlBootToFlash + 1, // StartFun(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 ) - RtlBootToSram + 1, // PatchWAKE(), Run if ( v40000210 & 0x20000000 ) - RtlBootToSram + 1, // PatchFun0(), Run if ( v40000210 & 0x10000000 ) - RtlBootToSram + 1,// PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 ) - RtlBootToFlash + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 ) -// EnterImage15 + 1}; // PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 ) + RtlBoot1ToSram + 1, // PatchWAKE(), Run if ( v40000210 & 0x20000000 ) + RtlBoot2ToSram + 1, // PatchFun0(), Run if ( v40000210 & 0x10000000 ) + RtlBoot3ToSram + 1, // PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 ) + RtlBoot4ToSram + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 ) +//test RtlBootToFlash + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 ) +//------------------------------------------------------------------------- /* Set Debug Flags */ LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() { #if CONFIG_DEBUG_LOG > 3 @@ -98,15 +121,6 @@ LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() { #endif } -/* RTL Console ROM */ -LOCAL void BOOT_RAM_TEXT_SECTION RtlConsolRam(void) { -// DiagPrintf("\r\nRTL Console ROM\r\n"); - pUartLogCtl->pTmpLogBuf->UARTLogBuf[0] = '?'; - pUartLogCtl->pTmpLogBuf->BufCount = 1; - pUartLogCtl->ExecuteCmd = 1; - RtlConsolTaskRom(pUartLogCtl); -} - /* JTAG On */ LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) { ACTCK_VENDOR_CCTRL(ON); @@ -114,44 +128,92 @@ LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) { HalPinCtrlRtl8195A(JTAG, 0, 1); } -/* Enter Image 1.5 */ -LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(void) { - SetDebugFlgs(); - DBG_8195A( - "\n===== Enter SRAM-Boot ====\nImg Sign: %s, Go @ 0x%08x\r\n", - &__image2_validate_code__, __image2_entry_func__); -#if CONFIG_DEBUG_LOG > 2 - DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), - HAL_PERI_ON_READ32(REG_SOC_FUNC_EN)); -#endif - if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) { - DBG_MISC_ERR("Invalid Image Signature!\n"); - RtlConsolRam(); - } - __image2_entry_func__(); +/* GetChipId() */ +LOCAL uint8 INFRA_START_SECTION _Get_ChipId() { + uint8 ChipId = CHIP_ID_8710AF; + if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8, + &ChipId, L25EOUTVOLTAGE) != 1) + DBG_8195A("Get Chip ID Failed\r"); + return ChipId; } -/* RtlBootToSram */ -LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToSram(void) { - JtagOn(); /* JTAG On */ - _memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__); +/* + * 16 bytes FIFO ... 16*11/38400 = 0.004583 sec + * (0.005/5)*166666666 = 166666.666 Tcpu + */ +LOCAL void INFRA_START_SECTION loguart_wait_tx_fifo_empty(void) { + if (HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_LOG_UART_EN) { + int x = 16384; + while ((!(HAL_READ8(LOG_UART_REG_BASE, 0x14) & BIT6)) && x--) + ; // иначе глючит LogUART, если переключение CLK приходится на вывод символов ! + } +} + +extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90] +/* + LOCAL uint32 _SpicInitParaAllClk[SpicMaxMode * CPU_CLK_TYPE_NO] = { + 0x01310202, 0x011420C2, + 0x03310002, 0x011420C2, + 0x05310002, 0x011420C2, + 0x07310002, 0x011420C2, + 0x09310002, 0x011420C2, + 0x0B310002, 0x011420C2, + + 0x11311301, 0x011420C2, + 0x13311201, 0x011420C2, + 0x15311101, 0x011420C2, + 0x17311101, 0x011420C2, + 0x19311101, 0x011420C2, + 0x1B311101, 0x011420C2, + + 0x21311301, 0x011420C2, + 0x23311201, 0x011420C2, + 0x25311101, 0x011420C2, + 0x27311101, 0x011420C2, + 0x29311101, 0x011420C2, + 0x2B311101, 0x011420C2 + }; + */ + +/* SYSPlatformInit */ +LOCAL void INFRA_START_SECTION SYSPlatformInit(void) { __asm__ __volatile__ ("cpsid f\n"); - HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, - HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) & ( ~BIT_SYS_SYSPLL_DIV5_3)); - HalCpuClkConfig(2); // 41.666666 MHz -// HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) | BIT_SYS_SYSPLL_DIV5_3); // 50.000 MHz + JtagOn(); + SetDebugFlgs(); + //----- SYS Init + HAL_SYS_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0, + (HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0) & (~(BIT_MASK_SYS_EEROM_LDO_PAR_07_04 << BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04))) | BIT_SYS_EEROM_LDO_PAR_07_04(6)); // & 0xF0FFFFFF | 0x6000000 + HAL_SYS_CTRL_WRITE32(REG_SYS_XTAL_CTRL1, + (HAL_SYS_CTRL_READ32(REG_SYS_XTAL_CTRL1) & (~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1))) | BIT_SYS_XTAL_DRV_RF1(1)); // & 0xFFFFFFE7 | 8; + //----- SDIO_Device_Off + HAL_PERI_ON_WRITE32(REG_PESOC_HCI_CLK_CTRL0, + HAL_PERI_ON_READ32(REG_PESOC_HCI_CLK_CTRL0) & (~BIT_SOC_ACTCK_SDIO_DEV_EN)); + HAL_PERI_ON_WRITE32(REG_SOC_HCI_COM_FUNC_EN, + HAL_PERI_ON_READ32(REG_SOC_HCI_COM_FUNC_EN) & (~(BIT_SOC_HCI_SDIOD_ON_EN | BIT_SOC_HCI_SDIOD_OFF_EN))); + HAL_PERI_ON_WRITE32(REG_HCI_PINMUX_CTRL, + HAL_PERI_ON_READ32(REG_HCI_PINMUX_CTRL) & (~(BIT_HCI_SDIOD_PIN_EN))); + //----- GPIO Adapter + extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter; + _memset(&gBoot_Gpio_Adapter, 0, sizeof(gBoot_Gpio_Adapter)); + _pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter; +#ifdef DEFAULT_BOOT_CLK_CPU + //----- CLK CPU + loguart_wait_tx_fifo_empty(); // иначе глючит LogUART, если переключение CLK приходится на вывод символов ! +#if DEFAULT_BOOT_CPU_CLOCK_SEL_DIV5_3 + // 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000 Hz + HalCpuClkConfig(DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE); + *((int *)(SYSTEM_CTRL_BASE+REG_SYS_SYSPLL_CTRL1)) |= (1<<17);// REG_SYS_SYSPLL_CTRL1 |= BIT_SYS_SYSPLL_DIV5_3 +#else + // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz + *((int *) (SYSTEM_CTRL_BASE + REG_SYS_SYSPLL_CTRL1)) &= ~(1 << 17); // REG_SYS_SYSPLL_CTRL1 &= ~BIT_SYS_SYSPLL_DIV5_3 + HalCpuClkConfig(DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE); +#endif // CPU_CLOCK_SEL_DIV5_3 +#endif // DEFAULT_CLK_CPU + //----- System VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC - HalInitPlatformLogUartV02(); + HalInitPlatformLogUartV02(); // Show ""... :( HalInitPlatformTimerV02(); __asm__ __volatile__ ("cpsie f\n"); - // SdrPowerOff(); - SDR_PIN_FCTRL(OFF); - LDO25M_CTRL(OFF); - HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, - HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); - - SpicInitRtl8195AV02(1, 0); // StartupSpicBaudRate InitBaudRate 1, SpicBitMode 1 StartupSpicBitMode - EnterImage15(); } /*------------------------------------------------------------------------------------- @@ -265,7 +327,9 @@ LOCAL uint32 BOOT_RAM_TEXT_SECTION load_segs(uint32 faddr, PIMG2HEAD hdr, uint8 segnum = 0; while (1) { uint32 seg_id = get_seg_id(hdr->seg.ldaddr, hdr->seg.size); - if (flgload && (seg_id == SEG_ID_SRAM || seg_id == SEG_ID_TCM)) { + if (flgload + && (seg_id == SEG_ID_SRAM || seg_id == SEG_ID_TCM + || seg_id == SEG_ID_SDRAM)) { #if CONFIG_DEBUG_LOG > 1 DBG_8195A("Load Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n", segnum, faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr, @@ -327,10 +391,7 @@ LOCAL int BOOT_RAM_TEXT_SECTION loadUserImges(int imgnum) { }; return imagenum; } -; -extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter; -extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter; //----- IsForceLoadDefaultImg2 LOCAL uint8 BOOT_RAM_TEXT_SECTION IsForceLoadDefaultImg2(void) { uint8 gpio_pin[4]; @@ -338,7 +399,7 @@ LOCAL uint8 BOOT_RAM_TEXT_SECTION IsForceLoadDefaultImg2(void) { HAL_GPIO_PIN_STATE flg; int result = 0; flashcpy(FLASH_SYSTEM_DATA_ADDR + 0x08, &gpio_pin, sizeof(gpio_pin)); // config data + 8 - _pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter; +// _pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter; for (int i = 1; i; i--) { uint8 x = gpio_pin[i]; result <<= 1; @@ -358,29 +419,112 @@ LOCAL uint8 BOOT_RAM_TEXT_SECTION IsForceLoadDefaultImg2(void) { HAL_GPIO_DeInit_8195a(&GPIO_Pin); } } - _pHAL_Gpio_Adapter->IrqHandle.IrqFun = NULL; +// _pHAL_Gpio_Adapter->IrqHandle.IrqFun = NULL; return result; } -LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToFlash(void) { +/* RTL Console ROM */ +LOCAL void BOOT_RAM_TEXT_SECTION RtlConsolRam(void) { +// DiagPrintf("\r\nRTL Console ROM\r\n"); + pUartLogCtl->pTmpLogBuf->UARTLogBuf[0] = '?'; + pUartLogCtl->pTmpLogBuf->BufCount = 1; + pUartLogCtl->ExecuteCmd = 1; + RtlConsolTaskRom(pUartLogCtl); +} - JtagOn(); /* JTAG On */ - SetDebugFlgs(); - DBG_8195A("===== Enter FLASH-Boot ====\n"); - if (HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (1 << BIT_SOC_FLASH_EN)) { - SPI_FLASH_PIN_FCTRL(ON); - /* - if(!SpicCmpDataForCalibrationRtl8195A()) { - DBG_8195A("ReInit Spic DIO...\n"); - SpicInitRtl8195AV02(1, SpicDualBitMode); - } - */ - loadUserImges(IsForceLoadDefaultImg2() + 1); +/* Enter Image 1.5 */ +LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) { + + if (flg) + _memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__); + + SYSPlatformInit(); + + if (!flg) + DBG_8195A("\r===== Enter FLASH-Boot ====\n"); + else + DBG_8195A("\r===== Enter SRAM-Boot %d ====\n", flg); + +#if CONFIG_DEBUG_LOG > 2 + DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), + HAL_PERI_ON_READ32(REG_SOC_FUNC_EN)); +#endif + uint8 ChipId = _Get_ChipId(); + if (ChipId < CHIP_ID_8195AM) { + //----- SDRAM Off + SDR_PIN_FCTRL(OFF); + LDO25M_CTRL(OFF); + HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off + } else { + //----- SDRAM On + LDO25M_CTRL(ON); + HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0, + (HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x0e)); + SDR_PIN_FCTRL(ON); }; - if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) { - DBG_8195A("Invalid Image Signature!\n"); + SPI_FLASH_PIN_FCTRL(ON); + *(uint32 *)(&SpicInitParaAllClk[0][0].BaudRate) = 0x1311301; // patch + *(uint32 *)(&SpicInitParaAllClk[1][0].BaudRate) = 0x1311301; // patch + SpicInitRtl8195AV02(CPU_CLK_TYPE_NO - 1 - ((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7), + SpicDualBitMode); + if (!SpicCmpDataForCalibrationRtl8195A()) { + DBG_8195A("Error Init Spic DIO!\n"); RtlConsolRam(); - } else - DBG_8195A("Go @ 0x%08x\r\n", __image2_entry_func__); + } + if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена? +// extern DRAM_DEVICE_INFO SdrDramInfo_rom; // 50 MHz + if (!SdrControllerInit_rom(&SdrDramInfo)) { // 100 MHz + DBG_8195A("SDR Controller Init fail!\n"); + RtlConsolRam(); + } +#if 0 // Test SDRAM + else { + uint32 *ptr = SDR_SDRAM_BASE; + uint32 tt = 0x55AA55AA; + for (int i = 0; i < 512 * 1024; i++) { + ptr[i] = tt++; + }; + tt = 0x55AA55AA; + for (int i = 0; i < 512 * 1024; i++) { + if (ptr[i] != tt) { + DBG_8195A("SDR err %p %p != %p!\n", &ptr[i], ptr[i], tt); + RtlConsolRam(); + } + tt++; + }; + DBG_8195A("SDR tst end\n"); + }; +#endif // test + HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); + }; + if (!flg) + loadUserImges(IsForceLoadDefaultImg2() + 1); + if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) { + DBG_MISC_ERR("Invalid Image Signature!\n"); + RtlConsolRam(); + } + DBG_8195A("Img Sign: %s, Go @ 0x%08x\r\n", &__image2_validate_code__, + __image2_entry_func__); __image2_entry_func__(); } + +/* RtlBootToSram */ +LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot1ToSram(void) { + EnterImage15(1); +} +/* RtlBootToSram */ +LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot2ToSram(void) { + EnterImage15(2); +} +/* RtlBootToSram */ +LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot3ToSram(void) { + EnterImage15(3); +} +/* RtlBootToSram */ +LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot4ToSram(void) { + EnterImage15(4); +} + +LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToFlash(void) { + EnterImage15(0); +} diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c index e8a5d4c..903b310 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c @@ -56,6 +56,15 @@ void INFRA_START_SECTION VectorTableOverrideRtl8195A(u32 StackP) { } */ +/* + * 16 bytes FIFO ... 16*11/38400 = 0.004583 sec + * (0.005/5)*166666666 = 166666.666 + */ +LOCAL void INFRA_START_SECTION loguart_wait_tx_fifo_empty(void) { + int x = 16384; + while((!(HAL_READ8(LOG_UART_REG_BASE, 0x14) & BIT6)) && x--); +} + //----- SYSPlatformInit void INFRA_START_SECTION SYSPlatformInit(void) { HAL_SYS_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0, @@ -66,6 +75,23 @@ void INFRA_START_SECTION SYSPlatformInit(void) { (HAL_SYS_CTRL_READ32(REG_SYS_XTAL_CTRL1) & (~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1))) | BIT_SYS_XTAL_DRV_RF1(1)); // & 0xFFFFFFE7 | 8; + if(HalGetCpuClk() != PLATFORM_CLOCK) { + //----- CLK CPU + loguart_wait_tx_fifo_empty(); // иначе глючит LogUART, если переключение CLK приходится на вывод символов ! +#if CPU_CLOCK_SEL_DIV5_3 + // 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000 Hz + HalCpuClkConfig(CPU_CLOCK_SEL_VALUE); + *((int *)(SYSTEM_CTRL_BASE+REG_SYS_SYSPLL_CTRL1)) |= (1<<17);// REG_SYS_SYSPLL_CTRL1 |= BIT_SYS_SYSPLL_DIV5_3 +#else + // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz + *((int *) (SYSTEM_CTRL_BASE + REG_SYS_SYSPLL_CTRL1)) &= ~(1 << 17); // REG_SYS_SYSPLL_CTRL1 &= ~BIT_SYS_SYSPLL_DIV5_3 + HalCpuClkConfig(CPU_CLOCK_SEL_VALUE); +#endif // CPU_CLOCK_SEL_DIV5_3 + //----- System + VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC + HalInitPlatformLogUartV02(); // Show ""... :( + HalInitPlatformTimerV02(); + }; } //----- SDIO_Device_Off @@ -93,11 +119,11 @@ __weak int main(void) { while (pUartLogCtl->ExecuteEsc != 1); pUartLogCtl->RevdNo = 0; pUartLogCtl->BootRdy = 1; - DiagPrintf("\r"); + DiagPrintf("\r"); while (1) { while (pUartLogCtl->ExecuteCmd != 1); UartLogCmdExecute(pUartLogCtl); - DiagPrintf("\r"); + DiagPrintf("\r"); pUartLogCtl->ExecuteCmd = 0; } return 0; @@ -107,72 +133,65 @@ extern const unsigned char cus_sig[32]; //----- InfraStart void INFRA_START_SECTION InfraStart(void) { // NewVectorTable[2] = HalNMIHandler_Patch; -// HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL0, HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL0) | BIT4); DBG_8195A("===== Enter Image: %s ====\n", cus_sig); -#if CONFIG_DEBUG_LOG > 3 - DBG_8195A("\rCPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN)); -#endif -#ifdef CONFIG_TIMER_MODULE - HalTimerOpInit_Patch((VOID*) (&HalTimerOp)); -#endif -// ShowRamBuildInfo(); // app_start.c: VOID ShowRamBuildInfo(VOID) + // ShowRamBuildInfo(); // app_start.c: VOID ShowRamBuildInfo(VOID) memset(&__bss_start__, 0, &__bss_end__ - &__bss_start__); - -//- Должно быть в boot !? + rtl_libc_init(); // ROM Lib C init (rtl_printf!) +//- Должно быть в boot extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter; memset(&gBoot_Gpio_Adapter, 0, sizeof(gBoot_Gpio_Adapter)); _pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter; -//- - - rtl_libc_init(); // ROM Lib C init - - int flash_en = HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) - & (1 << BIT_SOC_FLASH_EN); - if (flash_en) { - SPI_FLASH_PIN_FCTRL(ON); - if(!SpicCmpDataForCalibrationRtl8195A()) { - DBG_8195A("ReInit Spic DIO...\n"); - SpicInitRtl8195AV02(1, SpicDualBitMode); -#if 0 - SpicFlashInitRtl8195A(SpicDualBitMode); - if(!SpicCmpDataForCalibrationRtl8195A()) { - // TODO: Spic Not Init! - DBG_8195A("Spic error Init!\n"); while(1); - }; -#endif - }; - // Load SpicInitParaAllClk table - SpicNVMCalLoadAll(); - SpicReadIDRtl8195A(); - }; - while(!(HAL_READ8(LOG_UART_REG_BASE, 0x14) & BIT6)); // иначе глючит LogUART, если переключение CLK приходится на вывод символов ! -#if CPU_CLOCK_SEL_DIV5_3 - // 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000 Hz - HalCpuClkConfig(CPU_CLOCK_SEL_VALUE); - *((int *)(SYSTEM_CTRL_BASE+REG_SYS_SYSPLL_CTRL1)) |= (1<<17);// REG_SYS_SYSPLL_CTRL1 |= BIT_SYS_SYSPLL_DIV5_3 -#else - // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz - *((int *) (SYSTEM_CTRL_BASE + REG_SYS_SYSPLL_CTRL1)) &= ~(1 << 17); // REG_SYS_SYSPLL_CTRL1 &= ~BIT_SYS_SYSPLL_DIV5_3 - HalCpuClkConfig(CPU_CLOCK_SEL_VALUE); -#endif SDIO_Device_Off(); - HalReInitPlatformLogUartV02(); - SystemCoreClockUpdate(); SYSPlatformInit(); + HalTimerOpInit_Patch((VOID*) (&HalTimerOp)); +//- + SystemCoreClockUpdate(); En32KCalibration(); + +#if CONFIG_DEBUG_LOG > 2 + DBG_8195A("\rCPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN)); +#endif + _memset(SpicInitParaAllClk, 0, sizeof(SpicInitParaAllClk)); + *(uint32 *)(&SpicInitParaAllClk[0][0].BaudRate) = 0x1311301; // patch + *(uint32 *)(&SpicInitParaAllClk[1][0].BaudRate) = 0x1311301; // patch + SPI_FLASH_PIN_FCTRL(ON); + uint8 SpicBaudRate = CPU_CLK_TYPE_NO - 1 - ((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7); + SpicInitRtl8195AV02(SpicBaudRate, SpicDualBitMode); + if(!SpicCmpDataForCalibrationRtl8195A()) { + DBG_8195A("ReInit Spic to SIO...\n"); + SpicInitRtl8195AV02(SpicBaudRate, SpicOneBitMode); + if(!SpicCmpDataForCalibrationRtl8195A()) { + DBG_8195A("Error Init Spic!\n"); + }; + }; + SpicFlashInitRtl8195A(SpicDualBitMode); // SpicReadIDRtl8195A(); SpicDualBitMode + uint8 ChipId = HalGetChipId(); + if (ChipId >= CHIP_ID_8195AM) { +#ifdef CONFIG_SDR_EN + if((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена? + SdrCtrlInit(); + if(SdrControllerInit()) { + DBG_8195A("SDR Controller Init fail!\n"); + }; + }; +#endif + // clear SDRAM bss + extern uint8 __sdram_bss_start__[]; + extern uint8 __sdram_bss_end__[]; + if((uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__ > 0) + memset(__sdram_bss_start__, 0, (uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__); + } + else + { + //----- SDRAM Off + SDR_PIN_FCTRL(OFF); + LDO25M_CTRL(OFF); + HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off + }; + SPI_FLASH_PIN_FCTRL(OFF); InitSoCPM(); VectorTableInitForOSRtl8195A(&vPortSVCHandler, &xPortPendSVHandler, &xPortSysTickHandler); - if (flash_en) - SpicFlashInitRtl8195A(SpicDualBitMode); // DIO - SPI_FLASH_PIN_FCTRL(OFF); -#ifdef CONFIG_SDR_EN - // clear SDRAM bss - extern u8 __sdram_bss_start__[]; - extern u8 __sdram_bss_end__[]; - if((int)__sdram_bss_end__-(int)__sdram_bss_start__ > 0) - memset(__sdram_bss_start__, 0, (int)__sdram_bss_end__-(int)__sdram_bss_start__); -#endif // force SP align to 8 byte not 4 byte (initial SP is 4 byte align) __asm( "mov r0, sp\n" diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pwm.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pwm.c index bdf8c4f..674e091 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pwm.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pwm.c @@ -47,12 +47,12 @@ HAL_Pwm_Init( pPwmAdapt->sel = sel; timer_id = PWMTimerIdx[pwm_id]; pPwmAdapt->gtimer_id = timer_id; - +/* if (_FALSE == FunctionChk((pPwmAdapt->pwm_id + PWM0), pPwmAdapt->sel)) { DBG_PWM_WARN("HAL_Pwm_Init: Warning for RTL8710AF\n"); // return HAL_ERR_HW; } - +*/ #ifndef CONFIG_CHIP_E_CUT return HAL_Pwm_Init_8195a(pPwmAdapt); #else diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c index 840c5ca..29a7c8a 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c @@ -19,8 +19,8 @@ #endif #if !USE_SRC_ONLY_BOOT -#define SDRAM_INIT_USE_TCM_HEAP -#define SDRAM_INIT_USE_FLASH_API +//#define SDRAM_INIT_USE_TCM_HEAP +//#define SDRAM_INIT_USE_FLASH_API #endif @@ -44,7 +44,9 @@ //#define CONFIG_SDR_VERIFY extern SPIC_INIT_PARA SpicInitParaAllClk[3][CPU_CLK_TYPE_NO]; +extern DRAM_DEVICE_INFO SdrDramInfo; +/* HAL_CUT_B_RAM_DATA_SECTION DRAM_INFO SdrDramDev = { DRAM_INFO_TYPE, @@ -91,7 +93,7 @@ DRAM_DEVICE_INFO SdrDramInfo = { DRAM_TIMING_TCK, DFI_RATIO_1 }; - +*/ #define FPGA #define FPGA_TEMP @@ -132,8 +134,8 @@ u32 SdrCalibration(VOID); #ifndef SDRAM_INIT_USE_TCM_HEAP #if !USE_SRC_ONLY_BOOT //3 Note: stack overfloat if the arrary is declared in the task -HAL_CUT_B_RAM_DATA_SECTION -u32 AvaWds[2][REC_NUM]; +//HAL_CUT_B_RAM_DATA_SECTION +extern u32 AvaWds[2][REC_NUM]; #endif #else typedef struct { @@ -382,7 +384,9 @@ VOID ){ // ConfigDebugErr |= _DBG_MISC_; // DBG_8195A("SDR Ctrl Init\n"); - HAL_WRITE32(0x40000000, 0x40, ((HAL_READ32(0x40000000, 0x40)&0xfffff)|0xe00000)); + HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0, + ((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x0e))); + LDO25M_CTRL(ON); } @@ -395,8 +399,8 @@ VOID // ConfigDebugErr |= _DBG_MISC_; DBG_8195A("SDR Controller Init\n"); - HAL_WRITE32(0x40000000, 0x40, - ((HAL_READ32(0x40000000, 0x40)&0xfffff)|0x300000)); + HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0, + ((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); SRAM_MUX_CFG(0x2); @@ -435,6 +439,7 @@ DramInit ( IN DRAM_DEVICE_INFO *DramInfo ) { + DBG_8195A("%s(%p)\n", __func__, DramInfo); u32 CsBstLen = 0; // 0:bst_4, 1:bst_8 u32 CasWr = 0;//, CasWrT; // cas write latency u32 CasRd = 0, CasRdT = 0, CrlSrt = 0; // cas read latency @@ -449,7 +454,7 @@ DramInit ( u32 DfiRate; volatile struct ms_rxi310_portmap *ms_ctrl_0_map; ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE; - ms_ctrl_0_map = ms_ctrl_0_map; +// ms_ctrl_0_map = ms_ctrl_0_map; DfiRate = 1 << (u32) (DramInfo->DfiRate); DrmaPeriod = (DramInfo->DdrPeriodPs)*(DfiRate); // according DFI_RATE to setting @@ -460,7 +465,7 @@ DramInit ( CrTwr = ((DramInfo->Timing->TwrPs) / DrmaPeriod) + 3; if (CrTwr < DramMaxWr) { - CrTwr = CrTwr; +// CrTwr = CrTwr; } else { CrTwr = DramMaxWr; @@ -745,6 +750,7 @@ SdrCalibration( #else // u32 Value32; #endif + DBG_8195A("%s()\n", __func__); u32 RdPipe = 0, TapCnt = 0, Pass = 0, AvaWdsCnt = 0; u32 RdPipeCounter, RecNum[2], RecRdPipe[2];//, AvaWds[2][REC_NUM]; BOOL RdPipeFlag, PassFlag = 0, Result; @@ -798,7 +804,7 @@ SdrCalibration( #ifdef SDRAM_INIT_USE_TCM_HEAP pAvaWds AvaWds = (pAvaWds) tcm_heap_calloc(sizeof(u32)*REC_NUM*2); #else - _memset((u8*)AvaWds, 0, sizeof(u32)*REC_NUM*2); + _memset((u8*)AvaWds, 0, sizeof(AvaWds)); #endif #else u32 AvaWds[2][REC_NUM]; @@ -807,8 +813,8 @@ SdrCalibration( volatile struct ms_rxi310_portmap *ms_ctrl_0_map; ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE; - ms_ctrl_0_map = ms_ctrl_0_map; - PassFlag = PassFlag; +// ms_ctrl_0_map = ms_ctrl_0_map; +// PassFlag = PassFlag; RdPipeCounter =0; // DBG_8195A("%d\n",__LINE__); @@ -1004,7 +1010,7 @@ SdrCalibration( return Result; } // SdrCalibration -HAL_RAM_DATA_SECTION +// HAL_RAM_DATA_SECTION /* HAL_SDRC_TEXT_SECTION diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_spi_flash_ram.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_spi_flash_ram.c index 5ce7052..e30679c 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_spi_flash_ram.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_spi_flash_ram.c @@ -86,7 +86,7 @@ SECTION SPIC_INIT_PARA SpicInitParaAllClk[CPU_CLK_TYPE_NO] = {{0,0,0,0}, {0,0,0,0}, {0,0,0,0},}; #else -extern HAL_FLASH_DATA_SECTION +extern // HAL_FLASH_DATA_SECTION SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // in rtl_bios_data.c #endif diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/export-rom_v04.txt b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/export-rom_v04.txt index 4c20862..d9fd885 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/export-rom_v04.txt +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/export-rom_v04.txt @@ -305,8 +305,8 @@ SECTIONS HalTimerIrq2To7Handle = 0xee59; HalGetTimerIdRtl8195a = 0xef09; HalTimerInitRtl8195a = 0xef3d; - HalTimerDisRtl8195a = 0xf069; - HalTimerEnRtl8195a = 0xf089; + HalTimerDisRtl8195a = 0xf069; /* error! */ + HalTimerEnRtl8195a = 0xf089; /* error! */ HalTimerReadCountRtl8195a = 0xf0a9; HalTimerIrqClearRtl8195a = 0xf0bd; HalTimerDumpRegRtl8195a = 0xf0d1; @@ -624,7 +624,7 @@ SECTIONS rom_wps_rcons = 0x35d88; rom_wps_Td4s = 0x35d94; rom_wps_Td0 = 0x35e94; - str_rom_57ch3Dch0A = 0x3ed05; + str_rom_57ch3Dch0A = 0x3ed05; /* "========================================================\n" */ str_rom_0123456789ABCDEF = 0x3ec24; /* "0123456789ABCDEF" */ str_rom_hex_addr = 0x442D6; /* "[Addr] .0 .1 .2 .3 .4 .5 .6 .7 .8 .9 .A .B .C .D .E .F\r\n" */ str_rom_0123456789abcdef = 0x44660; /* "0123456789abcdef" */ diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/include/rtl_bios_data.h b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/include/rtl_bios_data.h index 3b04f97..cc58bb5 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/include/rtl_bios_data.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/include/rtl_bios_data.h @@ -208,7 +208,7 @@ extern DRAM_MODE_REG_INFO SdrDramModeReg; // 10001c30 0 } /* Mode2Cwl */ extern DRAM_INFO SdrDramDev; // 10001c4c #define DRAM_INFO_INIT() { DRAM_INFO_TYPE, DRAM_INFO_COL_ADDR_WTH,DRAM_INFO_BANK_SZ, DRAM_INFO_DQ_WTH } -//extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // SpicInitParaAllClk[3][6] ! +extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90] /* ROM + "C" standard library */ extern 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+801,23 @@ 100021ec T SpicInitParaAllClk 1000227c t txt_tab_seg 1000229c t tab_seg_def -100023ea t flashcpy 10002400 B __rom_heap_start__ 10002400 B end -10002488 t get_seg_id -100024bc t JtagOn -100024e0 t RtlConsolRam -10002500 t RtlBootToFlash -1000276c t RtlBootToSram -10002864 T SEG_ID -10002864 T __image1_bss_start__ -10002868 T __image1_bss_end__ -10002868 T __ram_image1_text_end__ +10002434 t flashcpy +100024d4 t get_seg_id +10002508 t RtlConsolRam +10002528 t EnterImage15 +10002994 t RtlBoot4ToSram +1000299a t RtlBoot3ToSram +100029a0 t RtlBoot2ToSram +100029a6 t RtlBoot1ToSram +100029ac t RtlBootToFlash +100029b8 t __HalCpuClkConfig_veneer +100029c8 t __SpicCmpDataForCalibrationRtl8195A_veneer +100029d8 T SEG_ID +100029d8 T __image1_bss_start__ +100029dc T __image1_bss_end__ +100029dc T __ram_image1_text_end__ 10003000 B __ram_heap1_start__ 10003000 B __rom_heap_end__ 10006000 D .image2.start.table1$$Base @@ -824,2374 +829,2375 @@ 10006004 D __image2_validate_code__ 10006018 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rtw_xmitframe_coalesce -1002b804 T rtl8195ab_xmitframe_resume -1002b8fa T rtl8195ab_mgnt_xmit -1002b936 T rtl8195ab_hal_xmit -1002ba44 t Hal_GetEfuseDefinition -1002ba74 t ResumeTxBeacon -1002bab8 T UpdateHalRAMask8195A -1002bc50 T HalLittleWifiMCUThreadRtl8195a -1002bca4 T HalCheckInReqStateThreadRtl8195a -1002bcf0 T HalTDMAChangeStateThreadRtl8195a -1002bd3c t rtl8195a_read_chip_version -1002bdb0 t Hal_EfuseWordEnableDataWrite -1002bff4 t Hal_EfusePowerSwitch -1002c008 t rtl8195a_free_hal_data -1002c022 t StopTxBeacon -1002c06c T SetHalODMVar8195A -1002c124 T rtl8195a_start_thread -1002c18c T rtl8195a_stop_thread -1002c1b0 t Hal_ReadEFuse -1002c320 T GetHalODMVar8195A -1002c334 t rtw_flash_map_update.part.12 -1002c3d4 t rtw_flash_map_erase -1002c418 t Hal_EfusePgPacketWrite -1002c694 t Hal_EfuseGetCurrentSize -1002c774 t rtw_flash_map_write -1002c942 T rtl8195a_InitBeaconParameters -1002c9b2 T _InitBurstPktLen_8195AB -1002c9bc T rtl8195a_set_hal_ops -1002ca9c T rtl8195a_init_default_value -1002ca9e T rtl8195a_InitLLTTable -1002cae8 T Hal_GetChnlGroup8195A -1002cb24 T rtw_config_map_read -1002cc10 T rtw_config_map_write -1002ccbc T Hal_InitPGData -1002cd1a T Hal_EfuseParseIDCode -1002cd32 T Hal_ReadPowerValueFromPROM_8195A -1002cdd0 T Hal_EfuseParseTxPowerInfo_8195A -1002ce68 T Hal_EfuseParseEEPROMVer_8195A -1002ce7e T Hal_EfuseParsePackageType_8195A -1002cee8 T Hal_EfuseParseChnlPlan_8195A -1002cf18 T Hal_EfuseParseCustomerID_8195A -1002cf2e T Hal_EfuseParseXtal_8195A -1002cf46 T Hal_EfuseParseThermalMeter_8195A -1002cf6e T Hal_ReadRFGainOffset -1002cfbe T BWMapping_8195A -1002cfde T SCMapping_8195A -1002d006 T rtl8195a_update_txdesc -1002d2d6 T rtl8195a_fill_fake_txdesc -1002d394 T SetHwReg8195A -1002e054 T GetHwReg8195A -1002e0e8 T SetHalDefVar8195A -1002e1c8 T GetHalDefVar8195A -1002e1ec T PHY_QueryBBReg_8195A_Safe -1002e218 T PHY_SetBBReg_8195A_Safe -1002e244 t phy_RFSerialRead_8195A -1002e2f8 T PHY_QueryRFReg_8195A -1002e310 T PHY_SetRFReg_8195A -1002e368 T PHY_MACConfig8195A -1002e382 T PHY_BBConfig8195A -1002e492 T PHY_RFConfig8195A -1002e496 T PHY_SetTxPowerIndex_8195A -1002e5a0 T phy_TxPwrAdjInPercentage -1002e5e0 T PHY_GetTxPowerIndex_8195A -1002e6d0 T PHY_SetTxPowerLevel8195A -1002e6d6 T phy_SpurCalibration_8195A -1002e98e T phy_SetRegBW_8195A -1002e9cc T phy_PostSetBwMode8195A -1002eb28 T phy_SwChnl8195A -1002ebd0 T phy_SwChnlAndSetBwMode8195A -1002ec20 T PHY_HandleSwChnlAndSetBW8195A -1002ecd0 T PHY_SetBWMode8195A -1002ecf2 T PHY_SwChnl8195A -1002ed0c T PHY_SetSwChnlBWMode8195A -1002ed2a t HalTimerEnable -1002ed3c T InitTDMATimer -1002ed64 T ChangeStateByTDMA -1002ed74 T GetMinRateInRRSR -1002eda8 T CheckInReqState -1002edb8 T InitCheckStateTimer -1002ede8 T InitGTimer1ms -1002ee34 T DeInitGTimer1ms -1002ee7c T ChangeTransmiteRate -1002eeb8 T PowerBitSetting -1002ef34 T ChkandChangePS -1002ef98 T IssueRsvdPagePacketSetting -1002f00c T IssuePSPoll -1002f038 T WaitTxStateMachineOk -1002f08c T IssueNullData -1002f11c T PsCloseRF -1002f150 T PsOpenRF -1002f180 T ChkTxQueueIsEmpty -1002f198 T InitPS -1002f208 T ConfigListenBeaconPeriod -1002f22c T PS_S2_Condition_Match -1002f260 T PS_S4_Condition_Match -1002f2dc T PS_32K_Condition_Match -1002f318 T PS_S2ToS3ToS0State -1002f380 T PS_S2ToS0State -1002f39c T PS_S3ToS2orS0State -1002f3cc T PS_S0ToS1ToS2State -1002f428 T PS_S1ToS0orS2State -1002f458 T PS_S2ToS4State -1002f4a4 T PS_S0ToS6State -1002f4c4 T PS_S6ToS0State -1002f4dc T CheckTSFIsStable -1002f52c T WaitHWStateReady -1002f53c T SysClkDown -1002f5ac T SysClkUp -1002f5f8 T ResetPSParm -1002f66c T PS_S4ToS2State -1002f690 T SleepTo32K -1002f6f0 T Change_PS_State -1002f89c T Legacy_PS_Setting -1002f910 T PSModeSetting -1002f9b4 T ChangePSStateByRPWM -1002f9f8 T ChangeTDMAState -1002fb18 T TDMAChangeStateTask -1002fb42 T EnterPS -1002fb64 T SetSmartPSTimer -1002fba0 T GTimer7Handle -1002fbfc T SmartPS2InitTimerAndToGetRxPkt -1002fc38 T PS_OnBeacon -1002fce8 T PSBcnEarlyProcess -1002fda4 T PSMtiBcnEarlyProcess -1002fe50 T PSRxBcnProcess -1002ffa0 T TxPktInPSOn -1002ffde T PsBcnToProcess -10030098 T GTimer6Handle -100300e4 T RPWMProcess -10030120 T PSSetMode -10030198 T SpeRPT -100302b8 T ISR_BcnEarly -10030324 T ISR_MtiBcnEarly -10030358 T ISR_RxBcn -10030374 T ISR_RxBCMD1 -100303a4 T ISR_RxBCMD0 -100303f8 T ISR_RxUCMD1 -10030436 T ISR_RxUCMD0 -10030472 T ISR_TxPktIn -10030484 T ISR_TXCCX -10030488 T H2CHDL_SetPwrMode -100305b0 T CheckInReqStateTask -100305f6 T HalGetNullTxRpt -10030614 T ISR_TBTT -1003068c T H2CHDL_BcnIgnoreEDCCA -1003069c T PMUInitial -100306ec T PMUTask -100307f8 T PHY_RF6052SetBandwidth8195A -1003083c T PHY_RF6052_Config8195A -100308f4 t process_rssi -1003092a T rtl8195a_query_rx_desc_status -100309da T rtl8195a_query_rx_phy_status -10030b32 T hal_com_get_channel_plan -10030b66 T HAL_IsLegalChannel -10030b84 T MRateToHwRate -10030b98 T HwRateToMRate -10030bac T HalSetBrateCfg -10030c58 T Hal_MappingOutPipe -10030c74 T hal_init_macaddr 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rtw_hal_write_rfreg -10031c30 T rtw_hal_interrupt_handler -10031c42 T rtw_hal_set_bwmode -10031c50 T rtw_hal_set_chan -10031c5e T rtw_hal_set_chnl_bw -10031c74 T rtw_hal_dm_watchdog -10031c8a T rtw_hal_macid_sleep -10031caa T rtw_hal_macid_wakeup -10031cca T decide_chip_type_by_device_id -10031cd0 t rtw_net_get_stats -10031d20 t netdev_if2_close -10031d40 t netdev_close -10031d9c t rtw_if1_deinit -10031e36 T rtw_os_indicate_connect -10031e3a T rtw_os_indicate_scan_done -10031e3e T rtw_reset_securitypriv -10031f32 T rtw_os_indicate_disconnect -10031f7c T rtw_init_netdev -100320cc T rtw_drv_if2_init -100322d4 T rtw_drv_if2_stop -1003232a T rtw_drv_if2_free -10032378 T _netdev_open -10032494 T _netdev_if2_open -10032550 T netdev_if2_open -10032578 T netdev_open -100325a0 T rtw_drv_probe -10032720 T rtw_dev_remove -10032764 T rtw_drv_entry -10032790 T rtw_drv_halt -100327c0 t rtw_wx_set_autoreconnect -100327ee t rtw_wx_get_autoreconnect -100327fc t rtw_forwarding_set -1003281e t rtw_set_ch_deauth -10032840 t get_priv_size -10032854 t rtw_wx_del_custome_ie -100328a0 t rtw_wx_set_pscan_freq -10032922 t rtw_wx_update_custome_ie -10032994 t rtw_set_tos_value -100329b4 t rtw_get_tx_power -10032af8 t rtw_wx_set_custome_ie -10032ba4 t rtw_pm_get -10032be8 t rtw_pm_set -10032c9c t rtw_wx_read32 -10032d48 t rtw_wx_write32 -10032dac t rtw_wx_set_freq.isra.10 -10032e54 T rtw_ex_set -10032f14 T wireless_send_event -10032f1e T indicate_wx_custom_event -10032f7a T indicate_wx_scan_result_present -10032fa2 T indicate_wx_scan_complete_event -10032fcc T rtw_indicate_sta_assoc -1003301c T rtw_indicate_sta_disassoc -10033074 T rtw_indicate_wx_assoc_event -100330a6 T rtw_indicate_wx_disassoc_event -100330d6 T rtw_set_wpa_ie -100331ec T strtopsk -10033258 T rtw_wx_get_passphrase -100332a4 T rtw_wx_set_ap_essid -10033394 T mac_reg_dump -10033440 T bb_reg_dump -1003349c T rf_reg_dump -10033514 t rtw_dbg_port -10033b7c T rtw_set_sta_num -10033b98 T rtw_ex_get_drv_ability -10033c58 T rtw_ex_get -10033ef0 T rtw_ioctl -10034e7c T rtw_os_recv_resource_init -10034e80 T rtw_os_recv_resource_alloc -10034e8a T rtw_os_recv_resource_free -10034e8c T rtw_tkip_countermeasure -10034f2c T rtw_handle_tkip_mic_err -10034fd4 T rtw_recv_indicatepkt -10035224 T skb_fail_inc -10035240 T skb_fail_get_and_rst -1003525c T init_skb_pool -100352b4 T init_skb_data_pool -1003530c T alloc_skb -1003540c T kfree_skb -10035474 T kfree_skb_chk_key -10035478 T skb_put -100354ac T skb_reserve -100354ba T dev_alloc_skb -100354d6 T skb_end_pointer -100354da T skb_set_tail_pointer -100354e2 T skb_pull -100354fa T skb_copy -10035522 T rtw_remainder_len -1003552e T _rtw_open_pktfile -10035540 T _rtw_pktfile_read -1003556e T rtw_set_tx_chksum_offload -10035570 T rtw_os_xmit_resource_alloc -1003557a T rtw_os_xmit_resource_free -1003557c T rtw_os_pkt_complete -10035584 T rtw_os_xmit_complete -10035596 T rtw_os_xmit_schedule -100355d2 T rtw_xmit_entry -1003561e T rtw_alloc_etherdev_with_old_priv -10035634 T rtw_alloc_etherdev -10035660 T rtw_free_netdev -10035680 T timer_wrapper -100356d4 T alloc_etherdev -10035730 T free_netdev -1003574a T dev_alloc_name -10035754 T init_timer_wrapper -10035774 T deinit_timer_wrapper -100357c0 T init_timer -10035878 T mod_timer -10035958 T cancel_timer_ex -100359a0 T del_timer_sync -10035a04 T rtw_init_timer -10035a0c T rtw_set_timer -10035a10 T rtw_cancel_timer -10035a1a T rtw_del_timer -10035a20 T rltk_get_idx_bydev -10035a30 T rltk_wlan_init -10035ab8 T rltk_wlan_deinit -10035b7c T rltk_wlan_start -10035bb0 T rltk_wlan_check_isup -10035bc0 T rltk_wlan_tx_inc -10035bd4 T rltk_wlan_tx_dec -10035be8 T rltk_wlan_get_recv_skb -10035bf8 T rltk_wlan_alloc_skb -10035c38 T rltk_wlan_send_skb -10035c6c T rltk_netif_rx -10035d18 T rltk_set_sta_num -10035d1c T rltk_set_tx_power_percentage -10035d50 T rltk_wlan_control -10035de4 T rltk_wlan_running -10035dfc T rltk_wlan_handshake_done -10035e30 T rltk_wlan_is_connected_to_ap -10035e74 T Efuse_PowerSwitch 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-10036b36 T rtw_set_802_11_authentication_mode -10036b58 T rtw_set_802_11_add_wep -10036bb8 T ODM_InitRAInfo -10036c58 T InitialRateUpdate -10036d58 T RateUp_search_RateMask -10036d8a T RateDown_search_RateMask -10036ddc T StartRateByRSSI -10036e06 T RateUpRAM8195A -10036e9a T RateDownTrying -10036ed8 T TryDone -10036f70 T RateDownStepRAM8195A -10037010 T RateDecisionRAM8195A -100370f4 T ArfrRefresh -100372fc T H2CHDL_Set_MACID_Config -100373c0 T PHY_DM_RA_SetRSSI_8195A -100373ee t CheckPositive.isra.0 -100374d0 T ODM_ReadAndConfig_MP_8195A_AGC_TAB -10037548 T ODM_ReadAndConfig_MP_8195A_PHY_REG -100375c0 T ODM_GetVersion_MP_8195A_PHY_REG -100375c4 T ODM_ReadAndConfig_MP_8195A_PHY_REG_PG -100375f8 T odm_ConfigRFReg_8195A -10037630 T odm_ConfigRF_RadioA_8195A -10037640 T odm_ConfigMAC_8195A -10037644 T odm_ConfigBB_AGC_8195A -10037654 T odm_ConfigBB_PHY_REG_PG_8195A -10037682 T odm_ConfigBB_PHY_8195A -100376ca T odm_ConfigBB_TXPWR_LMT_8195A -100376f0 T ODM_CmnInfoInit -100377e4 T ODM_CmnInfoHook -10037888 T ODM_CmnInfoPtrArrayHook -10037898 T ODM_CmnInfoUpdate -10037968 T odm_CommonInfoSelfInit -100379dc T ODM_DMInit -10037a2a T odm_CommonInfoSelfUpdate -10037a7c T ODM_DMWatchdog -10037ae8 T PhyDM_Get_Structure -10037b0c T Phydm_CheckAdaptivity -10037b3a T Phydm_NHMCounterStatisticsInit -10037bb0 T Phydm_SetEDCCAThreshold -10037be8 T Phydm_MACEDCCAState -10037c26 T Phydm_AdaptivityInit -10037d04 T Phydm_Adaptivity -10037e24 T ODM_CfoTrackingInit -10037e4e T ODM_CfoTracking -10037e6e T ODM_ParsingCFO -10037ea0 T ODM_InitDebugSetting -10037eb4 T ODM_Write_DIG -10037f54 T odm_ForbiddenIGICheck -10037fe6 T ODM_Write_CCK_CCA_Thres -10038020 T odm_DIGInit -100380ba T odm_DigAbort -100380dc T odm_DIGbyRSSI_LPS -10038188 T odm_FAThresholdCheck -100381b4 T odm_DIG -10038414 T odm_FalseAlarmCounterStatistics -10038440 T odm_CCKPacketDetectionThresh -10038498 T odm_RxPhyStatus8195A_Parsing -1003859c T odm_Process_RSSIForDM_8195A -100386de T ODM_PhyStatusQuery_8195A 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gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_QFN56_8195A -1004e4fc D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_QFN48_8195A -1004e51a D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN56_8195A -1004e538 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_TFBGA96_8195A -1004e558 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_QFN56_8195A -1004e576 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_QFN48_8195A -1004e594 D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_QFN56_8195A -1004e5b4 D Array_MP_8195A_RadioA -1004eb7c D gDeltaSwingTableXtal_MP_P_TxXtalTrack_8195A -1004eb9a D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_TFBGA96_8195A -1004ebba D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN48_8195A -1004ebd8 D .ram.bss$$Base -1004ebd8 D __bss_start__ -1004ebd8 D __data_end__ -1004ebd8 D __ram_image2_text_end__ -1004ebd8 d skbdata_list -1004ebe0 V skb_data_pool -10051fe0 d ucIdleTaskHeap -100520f8 D HalI2SOpSAL -10052134 D SYSAdapte -10052138 D PwrAdapter -100523c4 D libc_has_init -100523c8 d rheap_end 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rtw_adaptivity_mode +1004d518 D g_user_ap_sta_num +1004d51c d rtw_private_handler +1004d560 V max_local_skb_num +1004d564 V max_skb_buf_num +1004d568 D rom_e_rtw_msgp_str_ +1004d744 D ARFB_table +1004d783 D TRYING_NECESSARY_idx +1004d797 D DROPING_NECESSARY +1004d7ab D PER_RATE_UP +1004d7bf D PER_RATE_DOWN +1004d7d4 V Array_MP_8195A_PHY_REG_PG +1004d864 D Array_MP_8195A_AGC_TAB +1004da74 D Array_MP_8195A_PHY_REG +1004e0ec D rtl8195A_card_disable_flow +1004e18c D rtl8195A_card_enable_flow +1004e22c D Array_MP_8195A_MAC_REG +1004e534 D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_TFBGA96_8195A +1004e554 D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_TFBGA96_8195A +1004e574 D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_QFN48_8195A +1004e592 D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_QFN56_8195A +1004e5b0 D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_QFN48_8195A +1004e5ce D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN56_8195A +1004e5ec D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_TFBGA96_8195A +1004e60c D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_QFN56_8195A +1004e62a D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_QFN48_8195A +1004e648 D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_QFN56_8195A +1004e668 D Array_MP_8195A_RadioA +1004ec30 D gDeltaSwingTableXtal_MP_P_TxXtalTrack_8195A +1004ec4e D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_TFBGA96_8195A +1004ec6e D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN48_8195A +1004ec8c D .ram.bss$$Base +1004ec8c D __bss_start__ +1004ec8c D __data_end__ +1004ec8c D __ram_image2_text_end__ +1004ec8c d skbdata_list +1004ec94 V skb_data_pool +10052094 d ucIdleTaskHeap +100521ac D HalI2SOpSAL +100521e8 D SYSAdapte +100521ec D PwrAdapter +10052478 D libc_has_init +1005247c d rheap_end +10052480 d event_init.21281 +10052484 D wifi_run_mode +10052488 D wlan_st_netifn +10052489 d sampCntAdd +1005248c d sampCnt +10052490 D mp3_serv +10052512 D tskreader_enable +10052514 D readBuf +10052518 D tskmad_enable +1005251c d bufUnderrunCt +10052520 d oldRate +10052524 d sampDelCnt +10052528 D pbuf_fifo +1005252c D pi2s +10052534 D I2sTxSema +10052538 D eap_method +10052539 D eap_phase +1005253c D rtw_join_status +10052540 D wifi_mode +10052544 d param.21254 +1005255c d join_user_data +10052560 d event_callback_list +100526e0 D paff_array +10052758 D lwip_init_done +1005275c D xnetif +100527dc d s_aliases.6960 +100527e0 D h_errno +100527e4 d s_hostent.6959 +100527f8 d s_hostent_addr.6961 +100527fc d s_phostent_addr.6962 +10052804 d select_cb_list +10052808 d sockets +100528c8 d select_cb_ctr +100528cc d mbox +100528d0 d tcpip_init_done_arg +100528d4 d tcpip_init_done +100528d8 d allsystems +100528dc d allrouters +100528e0 d igmp_group_list +100528e4 D current_header +100528e8 d ip_id +100528ec D current_iphdr_src +100528f0 D current_iphdr_dest +100528f4 D current_netif +100528f8 d str.6325 +10052908 d reassdatagrams +1005290c d ip_reass_pbufcount +1005290e D dhcp_rx_options_given +10052918 D dhcp_rx_options_val +10052940 d xid.7275 +10052944 d dns_seqno +10052948 d dns_table +10052da8 d dns_servers +10052db0 d dns_payload_buffer +10052fb4 d dns_pcb +10052fb8 d dns_payload +10052fbc d tcpip_tcp_timer_active +10052fc0 d next_timeout +10052fc4 D netif_list +10052fc8 D netif_default +10052fcc d netif_num +10052fcd D pbuf_free_ooseq_pending +10052fd0 d raw_pcbs +10052fd4 D tcp_active_pcbs_changed +10052fd8 D tcp_ticks +10052fdc d tcp_timer +10052fe0 D tcp_listen_pcbs +10052fe4 D tcp_active_pcbs +10052fe8 d tcp_timer_ctr +10052fec D tcp_tw_pcbs +10052ff0 D tcp_tmp_pcb +10052ff4 D tcp_bound_pcbs +10052ff8 d seqno +10052ffc d tcplen +10053000 d ackno +10053004 d flags +10053005 d recv_flags +10053008 d tcphdr +1005300c d recv_data +10053010 d inseg +10053024 D tcp_input_pcb +10053028 D udp_pcbs +1005302c d etharp_cached_entry +10053030 d arp_table +100530f8 D lwip_tickless_used +100530fc d s_timeoutlist +1005312c d s_nextthread +10053130 d dhcps_ip_table_semaphore +10053134 d dhcps_send_broadcast_address +10053138 D dhcps_ip4addr_pool_end +10053139 d dhcp_client_ethernet_address +1005314c d dhcps_subnet_broadcast +10053150 d bound_client_ethernet_address +10053160 d ip_table +10053180 d dhcps_pcb +10053184 d dhcp_message_total_options_lenth +10053188 d dhcps_local_address +1005318c d dhcps_netif +10053190 d client_request_ip +10053194 d dhcps_allocated_client_address +10053198 d dhcps_local_mask +1005319c d dhcps_local_gateway +100531a0 d dhcps_network_id +100531a4 D dhcps_ip4addr_pool_start +100531a8 d dhcp_message_repository +100531ac D ext_upper +100531b0 d xFreeBytesRemaining +100531b4 d ext_free +100531b8 D ext_lower +100531bc d pxEnd +100531c0 d xStart +100531c8 d xMinimumEverFreeBytesRemaining +100531cc d ulTimerCountsForOneTick +100531d0 d ulStoppedTimerCompensation +100531d4 d xMaximumPossibleSuppressedTicks +100531d8 d xPendingReadyList +100531ec d uxTopReadyPriority +100531f0 d uxTasksDeleted +100531f4 d xTickCount +100531f8 d pxReadyTasksLists +100532d4 d pxOverflowDelayedTaskList +100532d8 d xTasksWaitingTermination +100532ec d pxDelayedTaskList +100532f0 d xSchedulerRunning +100532f4 d ulTaskSwitchedInTime +100532f8 D pxCurrentTCB +100532fc d uxPendedTicks +10053300 d xSuspendedTaskList +10053314 d uxCurrentNumberOfTasks +10053318 d ulDeltaTotalRunTime +1005331c d xDelayedTaskList2 +10053330 d xDelayedTaskList1 +10053344 d uxTaskNumber +10053348 d xYieldPending +1005334c d uxSchedulerSuspended +10053350 d xNumOfOverflows +10053354 d pxCurrentTimerList +10053358 d xActiveTimerList1 +1005336c d xActiveTimerList2 +10053380 d xLastTime.5284 +10053384 d xTimerQueue +10053388 d pxOverflowTimerList +1005338c d xTimerTaskHandle +10053390 d device_mutex +1005339c d mutex_init +100533a0 d uxSavedInterruptStatus +100533a4 D min_free_heap_size +100533a8 d g_heap_inited +100533ac d tcm_lock +100533b0 D g_tcm_heap +100533b4 D flashobj +100533c0 D fspic_isinit +100533c4 D WDGAdapter +10053400 d last_acquire_wakelock_time +10053480 D post_sleep_callback +10053500 D pre_sleep_callback +10053580 D reserve_pll +10053584 d sys_sleep_time +10053588 d hold_wakelock_time +10053608 D missing_tick +1005360c D Timer2To7HandlerData +10053624 D auto_reconnect_running +10053628 D p_wlan_autoreconnect_hdl +1005362c D mac_monitor_callback +10053630 D mf_list_head +10053634 d pscan_retry_cnt.21430 +10053638 D promisc_callback_all +1005363c D promisc_sema +10053640 D promisc_callback +10053644 D psk_essid +1005368c D psk_passphrase +1005370e D psk_passphrase64 +1005374f D wpa_global_PSK +1005379f d RFC1042_OUI +100537a4 d rx_ring_pool +10055884 d stop_report_count.20629 +10055885 D bCheckStateTIMER +10055888 d WifiMcuCmdBitMap.20974 +1005588c D p_wlan_init_done_callback +10055890 D rtw_power_percentage_idx +10055894 D p_wlan_uart_adapter_callback +10055898 D rtw_adaptivity_en +1005589c D p_wlan_mgmt_filter +100558a0 D rtw_initmac +100558a4 D rtw_adaptivity_th_l2h_ini +100558a8 d drvpriv +100558bc D skbbuf_used_num +100558c0 V skb_pool +10055a78 D skbdata_used_num +10055a7c d wrapper_skbbuf_list +10055a84 D max_skbdata_used_num +10055a88 D max_skbbuf_used_num +10055a8c d skb_fail_count +10055a90 D timer_table +10055a98 D rltk_wlan_info +10055ac8 d timer_used_num +10055acc D max_timer_used_num +10055ad0 D Noisy_State +10055ad4 D pExportWlanIrqSemaphore +10055ad8 D gDeltaSwingTableXtal_MP_N_TxXtalTrack_8195A +10055af6 D .ram.bss$$Limit +10055af6 D __bss_end__ +10055af8 B __ram_heap2_start__ 10070000 A __ram_heap2_end__ 1fff0000 D __ram_tcm_start__ 1fff0000 D __tcm_heap_start__ diff --git a/project/inc/platform_autoconf.h b/project/inc/platform_autoconf.h index 566549a..c060959 100644 --- a/project/inc/platform_autoconf.h +++ b/project/inc/platform_autoconf.h @@ -25,7 +25,7 @@ #undef CONFIG_MP #undef CONFIG_CP #undef CONFIG_FT -#define RTL8195A 7 +#define RTL8195A 1 /* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz, 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */ #define CONFIG_CPU_CLK 1 @@ -243,7 +243,7 @@ #define CPU_CLOCK_SEL_VALUE (CONFIG_CPU_CLK-6) #endif -#if CPU__CLK_DIV5_3 +#if CPU_CLOCK_SEL_DIV5_3 #define PLATFORM_CLOCK (200000000ul>>CPU_CLOCK_SEL_VALUE) #else #define PLATFORM_CLOCK (((200000000ul*5ul)/6ul)>>CPU_CLOCK_SEL_VALUE) diff --git a/sdkset.mk b/sdkset.mk index 5e22c50..0b5bf49 100644 --- a/sdkset.mk +++ b/sdkset.mk @@ -224,7 +224,7 @@ SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_i2s.c #SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_nfc.c #SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_pcm.c #SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_pwm.c -#SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c +SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c #SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_ssi.c SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_timer.c SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_uart.c