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<div class="title">SPI_EX<div class="ingroups"><a class="el" href="group__sdk.html">Ameba SDK</a> » <a class="el" href="group__hal.html">HAL</a></div></div> </div>
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<p>spi extended functions
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Ameba Common</h2></td></tr>
<tr class="memitem:gab04a0655cd1e3bcac5e8f48c18df1a57"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab04a0655cd1e3bcac5e8f48c18df1a57"></a>enum  </td><td class="memItemRight" valign="bottom">{ <b>SPI_SCLK_IDLE_LOW</b> =0,
<b>SPI_SCLK_IDLE_HIGH</b> =2
}</td></tr>
<tr class="separator:gab04a0655cd1e3bcac5e8f48c18df1a57"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga385c44f6fb256e5716a2302a5b940388"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga385c44f6fb256e5716a2302a5b940388"></a>enum  </td><td class="memItemRight" valign="bottom">{ <b>SPI_CS_TOGGLE_EVERY_FRAME</b> =0,
<b>SPI_CS_TOGGLE_START_STOP</b> =1
}</td></tr>
<tr class="separator:ga385c44f6fb256e5716a2302a5b940388"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gabc5c98fcc1211af2b80116dd6e0a035d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabc5c98fcc1211af2b80116dd6e0a035d"></a>enum  </td><td class="memItemRight" valign="bottom">{ <b>SPI_SCLK_TOGGLE_MIDDLE</b> =0,
<b>SPI_SCLK_TOGGLE_START</b> =1
}</td></tr>
<tr class="separator:gabc5c98fcc1211af2b80116dd6e0a035d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga72ea50c5dc70388ca9f1e7ebdefcd3d3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga72ea50c5dc70388ca9f1e7ebdefcd3d3"></a>enum  </td><td class="memItemRight" valign="bottom"><b>ChipSelect</b> { <br />
  <b>CS_0</b> = 0,
<b>CS_1</b> = 1,
<b>CS_2</b> = 2,
<b>CS_3</b> = 3,
<br />
  <b>CS_4</b> = 4,
<b>CS_5</b> = 5,
<b>CS_6</b> = 6,
<b>CS_7</b> = 7
<br />
}</td></tr>
<tr class="separator:ga72ea50c5dc70388ca9f1e7ebdefcd3d3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga16cbc562f954b30c69df51a8adee8534"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga16cbc562f954b30c69df51a8adee8534"></a>enum  </td><td class="memItemRight" valign="bottom"><b>SpiIrq</b> { <b>SpiRxIrq</b>,
<b>SpiTxIrq</b>
}</td></tr>
<tr class="separator:ga16cbc562f954b30c69df51a8adee8534"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga26bef3c52a19e67ab560865256694136"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga26bef3c52a19e67ab560865256694136"></a>
typedef void(* </td><td class="memItemRight" valign="bottom"><b>spi_irq_handler</b>) (uint32_t id, SpiIrq event)</td></tr>
<tr class="separator:ga26bef3c52a19e67ab560865256694136"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6e9595b7958847037dac25bbf21763da"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#ga6e9595b7958847037dac25bbf21763da">spi_irq_hook</a> (spi_t *obj, spi_irq_handler handler, uint32_t id)</td></tr>
<tr class="memdesc:ga6e9595b7958847037dac25bbf21763da"><td class="mdescLeft"> </td><td class="mdescRight">Set SPI interrupt handler if needed. <a href="#ga6e9595b7958847037dac25bbf21763da">More...</a><br /></td></tr>
<tr class="separator:ga6e9595b7958847037dac25bbf21763da"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga58c120ca975e75b9922eff12078d911f"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#ga58c120ca975e75b9922eff12078d911f">spi_bus_tx_done_irq_hook</a> (spi_t *obj, spi_irq_handler handler, uint32_t id)</td></tr>
<tr class="memdesc:ga58c120ca975e75b9922eff12078d911f"><td class="mdescLeft"> </td><td class="mdescRight">Set SPI interrupt bus tx done handler if needed. <a href="#ga58c120ca975e75b9922eff12078d911f">More...</a><br /></td></tr>
<tr class="separator:ga58c120ca975e75b9922eff12078d911f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga249e20a01a8af9b5a19e672f66dabf6a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#ga249e20a01a8af9b5a19e672f66dabf6a">spi_slave_flush_fifo</a> (spi_t *obj)</td></tr>
<tr class="memdesc:ga249e20a01a8af9b5a19e672f66dabf6a"><td class="mdescLeft"> </td><td class="mdescRight">Slave device to flush tx fifo. <a href="#ga249e20a01a8af9b5a19e672f66dabf6a">More...</a><br /></td></tr>
<tr class="separator:ga249e20a01a8af9b5a19e672f66dabf6a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaba7c845992387eeb5fb215bd1cb7e690"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#gaba7c845992387eeb5fb215bd1cb7e690">spi_slave_read_stream</a> (spi_t *obj, char *rx_buffer, uint32_t length)</td></tr>
<tr class="memdesc:gaba7c845992387eeb5fb215bd1cb7e690"><td class="mdescLeft"> </td><td class="mdescRight">slave recv target length data use interrupt mode. <a href="#gaba7c845992387eeb5fb215bd1cb7e690">More...</a><br /></td></tr>
<tr class="separator:gaba7c845992387eeb5fb215bd1cb7e690"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga678b03ba73fb3758e5b201417fddca9d"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#ga678b03ba73fb3758e5b201417fddca9d">spi_slave_write_stream</a> (spi_t *obj, char *tx_buffer, uint32_t length)</td></tr>
<tr class="memdesc:ga678b03ba73fb3758e5b201417fddca9d"><td class="mdescLeft"> </td><td class="mdescRight">slave send target length data use interrupt mode. <a href="#ga678b03ba73fb3758e5b201417fddca9d">More...</a><br /></td></tr>
<tr class="separator:ga678b03ba73fb3758e5b201417fddca9d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga366686e2250422fbb876eda6ab5121b8"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#ga366686e2250422fbb876eda6ab5121b8">spi_master_read_stream</a> (spi_t *obj, char *rx_buffer, uint32_t length)</td></tr>
<tr class="memdesc:ga366686e2250422fbb876eda6ab5121b8"><td class="mdescLeft"> </td><td class="mdescRight">master recv target length data use interrupt mode. <a href="#ga366686e2250422fbb876eda6ab5121b8">More...</a><br /></td></tr>
<tr class="separator:ga366686e2250422fbb876eda6ab5121b8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaa8f8fdf9dabf959074f3ae8b5b989c2"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#gaaa8f8fdf9dabf959074f3ae8b5b989c2">spi_master_write_stream</a> (spi_t *obj, char *tx_buffer, uint32_t length)</td></tr>
<tr class="memdesc:gaaa8f8fdf9dabf959074f3ae8b5b989c2"><td class="mdescLeft"> </td><td class="mdescRight">master send target length data use interrupt mode. <a href="#gaaa8f8fdf9dabf959074f3ae8b5b989c2">More...</a><br /></td></tr>
<tr class="separator:gaaa8f8fdf9dabf959074f3ae8b5b989c2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9056b0cb0dfab24ba0cfc1ce3367e625"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#ga9056b0cb0dfab24ba0cfc1ce3367e625">spi_master_write_read_stream</a> (spi_t *obj, char *tx_buffer, char *rx_buffer, uint32_t length)</td></tr>
<tr class="memdesc:ga9056b0cb0dfab24ba0cfc1ce3367e625"><td class="mdescLeft"> </td><td class="mdescRight">master send & recv target length data use interrupt mode. <a href="#ga9056b0cb0dfab24ba0cfc1ce3367e625">More...</a><br /></td></tr>
<tr class="separator:ga9056b0cb0dfab24ba0cfc1ce3367e625"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae906eba39b6ecc4746a2bf06bac1c882"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#gae906eba39b6ecc4746a2bf06bac1c882">spi_slave_read_stream_timeout</a> (spi_t *obj, char *rx_buffer, uint32_t length, uint32_t timeout_ms)</td></tr>
<tr class="memdesc:gae906eba39b6ecc4746a2bf06bac1c882"><td class="mdescLeft"> </td><td class="mdescRight">slave recv target length data use interrupt mode and timeout mechanism. <a href="#gae906eba39b6ecc4746a2bf06bac1c882">More...</a><br /></td></tr>
<tr class="separator:gae906eba39b6ecc4746a2bf06bac1c882"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gad7fea472a2340511b69840d41a6ec89f"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#gad7fea472a2340511b69840d41a6ec89f">spi_slave_read_stream_terminate</a> (spi_t *obj, char *rx_buffer, uint32_t length)</td></tr>
<tr class="memdesc:gad7fea472a2340511b69840d41a6ec89f"><td class="mdescLeft"> </td><td class="mdescRight">slave recv target length data use interrupt mode and stop if the spi bus is idle. <a href="#gad7fea472a2340511b69840d41a6ec89f">More...</a><br /></td></tr>
<tr class="separator:gad7fea472a2340511b69840d41a6ec89f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga914a3e32ac9fdd6c160d1b948a897c31"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#ga914a3e32ac9fdd6c160d1b948a897c31">spi_slave_read_stream_dma</a> (spi_t *obj, char *rx_buffer, uint32_t length)</td></tr>
<tr class="memdesc:ga914a3e32ac9fdd6c160d1b948a897c31"><td class="mdescLeft"> </td><td class="mdescRight">slave recv target length data use DMA mode. <a href="#ga914a3e32ac9fdd6c160d1b948a897c31">More...</a><br /></td></tr>
<tr class="separator:ga914a3e32ac9fdd6c160d1b948a897c31"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaee7e542d8e71a6ed4b2552256f55ac54"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#gaee7e542d8e71a6ed4b2552256f55ac54">spi_slave_write_stream_dma</a> (spi_t *obj, char *tx_buffer, uint32_t length)</td></tr>
<tr class="memdesc:gaee7e542d8e71a6ed4b2552256f55ac54"><td class="mdescLeft"> </td><td class="mdescRight">slave send target length data use DMA mode. <a href="#gaee7e542d8e71a6ed4b2552256f55ac54">More...</a><br /></td></tr>
<tr class="separator:gaee7e542d8e71a6ed4b2552256f55ac54"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae3fba6e84103f5d3cfd5884c4a15366c"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#gae3fba6e84103f5d3cfd5884c4a15366c">spi_master_write_read_stream_dma</a> (spi_t *obj, char *tx_buffer, char *rx_buffer, uint32_t length)</td></tr>
<tr class="memdesc:gae3fba6e84103f5d3cfd5884c4a15366c"><td class="mdescLeft"> </td><td class="mdescRight">master send & recv target length data use DMA mode. <a href="#gae3fba6e84103f5d3cfd5884c4a15366c">More...</a><br /></td></tr>
<tr class="separator:gae3fba6e84103f5d3cfd5884c4a15366c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab600e2403b6b4e8a924dc68f45c0ab31"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#gab600e2403b6b4e8a924dc68f45c0ab31">spi_master_read_stream_dma</a> (spi_t *obj, char *rx_buffer, uint32_t length)</td></tr>
<tr class="memdesc:gab600e2403b6b4e8a924dc68f45c0ab31"><td class="mdescLeft"> </td><td class="mdescRight">master recv target length data use DMA mode. <a href="#gab600e2403b6b4e8a924dc68f45c0ab31">More...</a><br /></td></tr>
<tr class="separator:gab600e2403b6b4e8a924dc68f45c0ab31"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac73da5724fc8abb20728382d5eed7f25"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#gac73da5724fc8abb20728382d5eed7f25">spi_master_write_stream_dma</a> (spi_t *obj, char *tx_buffer, uint32_t length)</td></tr>
<tr class="memdesc:gac73da5724fc8abb20728382d5eed7f25"><td class="mdescLeft"> </td><td class="mdescRight">master send target length data use DMA mode. <a href="#gac73da5724fc8abb20728382d5eed7f25">More...</a><br /></td></tr>
<tr class="separator:gac73da5724fc8abb20728382d5eed7f25"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf64e666ba72cd21b3a7905018212cdd3"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#gaf64e666ba72cd21b3a7905018212cdd3">spi_slave_read_stream_dma_timeout</a> (spi_t *obj, char *rx_buffer, uint32_t length, uint32_t timeout_ms)</td></tr>
<tr class="memdesc:gaf64e666ba72cd21b3a7905018212cdd3"><td class="mdescLeft"> </td><td class="mdescRight">slave recv target length data use DMA mode and timeout mechanism. <a href="#gaf64e666ba72cd21b3a7905018212cdd3">More...</a><br /></td></tr>
<tr class="separator:gaf64e666ba72cd21b3a7905018212cdd3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6842485cab5cc26d4a86d01f4d2288fd"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__ex.html#ga6842485cab5cc26d4a86d01f4d2288fd">spi_slave_read_stream_dma_terminate</a> (spi_t *obj, char *rx_buffer, uint32_t length)</td></tr>
<tr class="memdesc:ga6842485cab5cc26d4a86d01f4d2288fd"><td class="mdescLeft"> </td><td class="mdescRight">slave recv target length data use DMA mode and stop if the spi bus is idle. <a href="#ga6842485cab5cc26d4a86d01f4d2288fd">More...</a><br /></td></tr>
<tr class="separator:ga6842485cab5cc26d4a86d01f4d2288fd"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<p>spi extended functions </p>
<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="ga58c120ca975e75b9922eff12078d911f"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">void spi_bus_tx_done_irq_hook </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">spi_irq_handler </td>
<td class="paramname"><em>handler</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>id</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Set SPI interrupt bus tx done handler if needed. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi object define in application software. </td></tr>
<tr><td class="paramname">handler</td><td>interrupt bus tx done callback function </td></tr>
<tr><td class="paramname">id</td><td>interrupt callback parameter </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname">none</td><td></td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="ga6e9595b7958847037dac25bbf21763da"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">void spi_irq_hook </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">spi_irq_handler </td>
<td class="paramname"><em>handler</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>id</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Set SPI interrupt handler if needed. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi object define in application software. </td></tr>
<tr><td class="paramname">handler</td><td>interrupt callback function </td></tr>
<tr><td class="paramname">id</td><td>interrupt callback parameter </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname">none</td><td></td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="ga366686e2250422fbb876eda6ab5121b8"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t spi_master_read_stream </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>rx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>length</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>master recv target length data use interrupt mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi master object define in application software. </td></tr>
<tr><td class="paramname">rx_buffer</td><td>buffer to save data read from SPI FIFO. </td></tr>
<tr><td class="paramname">length</td><td>number of data bytes to be read. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname"></td><td>stream init status </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="gab600e2403b6b4e8a924dc68f45c0ab31"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t spi_master_read_stream_dma </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>rx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>length</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>master recv target length data use DMA mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi master object define in application software. </td></tr>
<tr><td class="paramname">rx_buffer</td><td>buffer to save data read from SPI FIFO. </td></tr>
<tr><td class="paramname">length</td><td>number of data bytes to be read. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname"></td><td>stream init status </td></tr>
</table>
</dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>: DMA or Interrupt mode can be used to TX dummy data </dd></dl>
</div>
</div>
<a class="anchor" id="ga9056b0cb0dfab24ba0cfc1ce3367e625"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t spi_master_write_read_stream </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>tx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>rx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>length</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>master send & recv target length data use interrupt mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi master object define in application software. </td></tr>
<tr><td class="paramname">tx_buffer</td><td>buffer to be written to Tx FIFO. </td></tr>
<tr><td class="paramname">rx_buffer</td><td>buffer to save data read from SPI FIFO. </td></tr>
<tr><td class="paramname">length</td><td>number of data bytes to be send & recv. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname"></td><td>stream init status </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="gae3fba6e84103f5d3cfd5884c4a15366c"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t spi_master_write_read_stream_dma </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>tx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>rx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>length</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>master send & recv target length data use DMA mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi master object define in application software. </td></tr>
<tr><td class="paramname">tx_buffer</td><td>buffer to be written to Tx FIFO. </td></tr>
<tr><td class="paramname">rx_buffer</td><td>buffer to save data read from SPI FIFO. </td></tr>
<tr><td class="paramname">length</td><td>number of data bytes to be send & recv. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname"></td><td>stream init status </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="gaaa8f8fdf9dabf959074f3ae8b5b989c2"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t spi_master_write_stream </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>tx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>length</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>master send target length data use interrupt mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi master object define in application software. </td></tr>
<tr><td class="paramname">tx_buffer</td><td>buffer to be written to Tx FIFO. </td></tr>
<tr><td class="paramname">length</td><td>number of data bytes to be send. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname"></td><td>stream init status </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="gac73da5724fc8abb20728382d5eed7f25"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t spi_master_write_stream_dma </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>tx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>length</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>master send target length data use DMA mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi master object define in application software. </td></tr>
<tr><td class="paramname">tx_buffer</td><td>buffer to be written to Tx FIFO. </td></tr>
<tr><td class="paramname">length</td><td>number of data bytes to be send. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname"></td><td>stream init status </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="ga249e20a01a8af9b5a19e672f66dabf6a"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">void spi_slave_flush_fifo </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<p>Slave device to flush tx fifo. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi slave object define in application software. </td></tr>
</table>
</dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>: It will discard all data in both tx fifo and rx fifo </dd></dl>
</div>
</div>
<a class="anchor" id="gaba7c845992387eeb5fb215bd1cb7e690"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t spi_slave_read_stream </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>rx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>length</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>slave recv target length data use interrupt mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi slave object define in application software. </td></tr>
<tr><td class="paramname">rx_buffer</td><td>buffer to save data read from SPI FIFO. </td></tr>
<tr><td class="paramname">length</td><td>number of data bytes to be read. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname"></td><td>stream init status </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="ga914a3e32ac9fdd6c160d1b948a897c31"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t spi_slave_read_stream_dma </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>rx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>length</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>slave recv target length data use DMA mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi slave object define in application software. </td></tr>
<tr><td class="paramname">rx_buffer</td><td>buffer to save data read from SPI FIFO. </td></tr>
<tr><td class="paramname">length</td><td>number of data bytes to be read. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname"></td><td>stream init status </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="ga6842485cab5cc26d4a86d01f4d2288fd"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t spi_slave_read_stream_dma_terminate </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>rx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>length</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>slave recv target length data use DMA mode and stop if the spi bus is idle. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi slave object define in application software. </td></tr>
<tr><td class="paramname">rx_buffer</td><td>buffer to save data read from SPI FIFO. </td></tr>
<tr><td class="paramname">length</td><td>number of data bytes to be read. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname"></td><td>number of bytes read already </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="gaf64e666ba72cd21b3a7905018212cdd3"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t spi_slave_read_stream_dma_timeout </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>rx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>length</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>timeout_ms</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>slave recv target length data use DMA mode and timeout mechanism. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi slave object define in application software. </td></tr>
<tr><td class="paramname">rx_buffer</td><td>buffer to save data read from SPI FIFO. </td></tr>
<tr><td class="paramname">length</td><td>number of data bytes to be read. </td></tr>
<tr><td class="paramname">timeout_ms</td><td>timeout waiting time. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname"></td><td>number of bytes read already </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="gad7fea472a2340511b69840d41a6ec89f"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t spi_slave_read_stream_terminate </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>rx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>length</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>slave recv target length data use interrupt mode and stop if the spi bus is idle. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi slave object define in application software. </td></tr>
<tr><td class="paramname">rx_buffer</td><td>buffer to save data read from SPI FIFO. </td></tr>
<tr><td class="paramname">length</td><td>number of data bytes to be read. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname"></td><td>number of bytes read already </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="gae906eba39b6ecc4746a2bf06bac1c882"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t spi_slave_read_stream_timeout </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>rx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>length</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>timeout_ms</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>slave recv target length data use interrupt mode and timeout mechanism. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi slave object define in application software. </td></tr>
<tr><td class="paramname">rx_buffer</td><td>buffer to save data read from SPI FIFO. </td></tr>
<tr><td class="paramname">length</td><td>number of data bytes to be read. </td></tr>
<tr><td class="paramname">timeout_ms</td><td>timeout waiting time. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname"></td><td>number of bytes read already </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="ga678b03ba73fb3758e5b201417fddca9d"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t spi_slave_write_stream </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>tx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>length</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>slave send target length data use interrupt mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi slave object define in application software. </td></tr>
<tr><td class="paramname">tx_buffer</td><td>buffer to be written to Tx FIFO. </td></tr>
<tr><td class="paramname">length</td><td>number of data bytes to be send. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname"></td><td>stream init status </td></tr>
</table>
</dd>
</dl>
</div>
</div>
<a class="anchor" id="gaee7e542d8e71a6ed4b2552256f55ac54"></a>
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">int32_t spi_slave_write_stream_dma </td>
<td>(</td>
<td class="paramtype">spi_t * </td>
<td class="paramname"><em>obj</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">char * </td>
<td class="paramname"><em>tx_buffer</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>length</em> </td>
</tr>
<tr>
<td></td>
<td>)</td>
<td></td><td></td>
</tr>
</table>
</div><div class="memdoc">
<p>slave send target length data use DMA mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramname">obj</td><td>spi slave object define in application software. </td></tr>
<tr><td class="paramname">tx_buffer</td><td>buffer to be written to Tx FIFO. </td></tr>
<tr><td class="paramname">length</td><td>number of data bytes to be send. </td></tr>
</table>
</dd>
</dl>
<dl class="retval"><dt>Return values</dt><dd>
<table class="retval">
<tr><td class="paramname"></td><td>stream init status </td></tr>
</table>
</dd>
</dl>
</div>
</div>
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