j3d1/sdk-ameba-v4.0c_180328
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jialexd 2019-04-02 16:34:25 +08:00
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377
component/common/drivers/ethernet_mii/ethernet_mii.c Executable file
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#include "rtl8195a.h"
#include "build_info.h"
#ifdef PLATFORM_FREERTOS
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
#endif
#include "osdep_service.h"
#include "lwip_netconf.h"
#include "ethernet_api.h"
#include "lwip_intf.h"
#include "ethernet_mii.h"
#include "platform_opts.h"
#include "ethernet_ex_api.h"
static _sema mii_rx_sema;
static _mutex mii_tx_mutex;
extern volatile u32 ethernet_unplug;
extern struct netif xnetif[NET_IF_NUM];
static u8 TX_BUFFER[1536];
static u8 RX_BUFFER[1536];
static u8 *pTmpTxDesc = NULL;
static u8 *pTmpRxDesc = NULL;
static u8 *pTmpTxPktBuf = NULL;
static u8 *pTmpRxPktBuf = NULL;
int ethernet_init_done = 0;
int dhcp_ethernet_mii = 1;
int ethernet_if_default = 0;
int link_is_up = 0;
link_up_down_callback p_link_change_callback = 0;
extern int lwip_init_done;
static _sema mii_linkup_sema;
void mii_rx_thread(void* param){
u32 len = 0;
u8* pbuf = RX_BUFFER;
while(1){
if (rtw_down_sema(&mii_rx_sema) == _FAIL){
DBG_8195A("%s, Take Semaphore Fail\n", __FUNCTION__);
goto exit;
}
// continues read the rx ring until its empty
while(1){
len = ethernet_receive();
if(len){
//DBG_8195A("mii_recv len = %d\n\r", len);
ethernet_read(pbuf, len);
// calculate the time duration
ethernetif_mii_recv(&xnetif[ETHERNET_IDX], len);
//__rtl_memDump_v1_00(pbuf, len, "ethernet_receive Data:");
//rtw_memset(pbuf, 0, len);
}else if(len == 0){
break;
}
}
}
exit:
rtw_free_sema(&mii_rx_sema);
vTaskDelete(NULL);
}
void mii_intr_thread(void* param)
{
u32 dhcp_status = 0;
while(1)
{
if (rtw_down_sema(&mii_linkup_sema) == _FAIL){
DBG_8195A("%s, Take Semaphore Fail\n", __FUNCTION__);
break;
}
//Used to process there is no cable plugged in when power-on
if(1 == ethernet_unplug){
if(p_link_change_callback)
p_link_change_callback(link_is_up);
}
if(1 == ethernet_init_done){
if(link_is_up){
DBG_8195A("...Link up\n");
if(dhcp_ethernet_mii == 1)
dhcp_status = LwIP_DHCP(ETHERNET_IDX, DHCP_START);
if(DHCP_ADDRESS_ASSIGNED == dhcp_status){
if(1 == ethernet_if_default)
netif_set_default(&xnetif[ETHERNET_IDX]); //Set default gw to ether netif
else
netif_set_default(&xnetif[WLAN_IDX]);
}
}else{
DBG_8195A("...Link down\n");
netif_set_default(&xnetif[WLAN_IDX]); //Set default gw to wlan netif
#if CONFIG_LWIP_LAYER
LwIP_ReleaseIP(ETHERNET_IDX);
#endif
}
if(p_link_change_callback)
p_link_change_callback(link_is_up);
}
}
rtw_free_sema(&mii_linkup_sema);
vTaskDelete(NULL);
}
void mii_intr_handler(u32 Event, u32 Data)
{
switch(Event)
{
case ETH_TXDONE:
//DBG_8195A("TX Data = %d\n", Data);
break;
case ETH_RXDONE:
//DBG_8195A("\r\nRX Data = %d\n", Data);
// wake up rx thread to receive data
rtw_up_sema_from_isr(&mii_rx_sema);
break;
case ETH_LINKUP:
DBG_8195A("Link Up\n");
link_is_up = 1;
rtw_up_sema_from_isr(&mii_linkup_sema);
break;
case ETH_LINKDOWN:
DBG_8195A("Link Down\n");
link_is_up = 0;
rtw_up_sema_from_isr(&mii_linkup_sema);
break;
default:
DBG_8195A("Unknown event !!\n");
break;
}
}
void ethernet_demo(void* param){
u8 mac[6];
/* Initilaize the LwIP stack */
// can not init twice
if(!lwip_init_done)
LwIP_Init();
DBG_8195A("LWIP Init done\n");
ethernet_irq_hook(mii_intr_handler);
if(pTmpTxDesc)
{
free(pTmpTxDesc);
pTmpTxDesc = NULL;
}
if(pTmpRxDesc)
{
free(pTmpRxDesc);
pTmpRxDesc = NULL;
}
if(pTmpTxPktBuf)
{
free(pTmpTxPktBuf);
pTmpTxPktBuf = NULL;
}
if(pTmpRxPktBuf)
{
free(pTmpRxPktBuf);
pTmpRxPktBuf = NULL;
}
pTmpTxDesc = (u8 *)malloc(/*MII_TX_DESC_CNT*/MII_TX_DESC_NO * ETH_TX_DESC_SIZE);
pTmpRxDesc = (u8 *)malloc(/*MII_RX_DESC_CNT*/MII_RX_DESC_NO * ETH_RX_DESC_SIZE);
pTmpTxPktBuf = (u8 *)malloc(/*MII_TX_DESC_CNT*/MII_TX_DESC_NO * ETH_PKT_BUF_SIZE);
pTmpRxPktBuf = (u8 *)malloc(/*MII_RX_DESC_CNT*/MII_RX_DESC_NO * ETH_PKT_BUF_SIZE);
if(pTmpTxDesc == NULL || pTmpRxDesc == NULL || pTmpTxPktBuf == NULL || pTmpRxPktBuf == NULL)
{
printf("TX/RX descriptor malloc fail\n");
return;
}
memset(pTmpTxDesc, 0, MII_TX_DESC_NO * ETH_TX_DESC_SIZE);
memset(pTmpRxDesc, 0, MII_RX_DESC_NO * ETH_RX_DESC_SIZE);
memset(pTmpTxPktBuf, 0, MII_TX_DESC_NO * ETH_PKT_BUF_SIZE);
memset(pTmpRxPktBuf, 0, MII_RX_DESC_NO * ETH_PKT_BUF_SIZE);
//size 160 128 12288 12288
ethernet_set_descnum(MII_TX_DESC_NO, MII_RX_DESC_NO);
printf("TRX descriptor number setting done\n");
ethernet_trx_pre_setting(pTmpTxDesc, pTmpRxDesc, pTmpTxPktBuf, pTmpRxPktBuf);
printf("TRX pre setting done\n");
ethernet_init();
DBG_INFO_MSG_OFF(_DBG_MII_);
DBG_WARN_MSG_OFF(_DBG_MII_);
DBG_ERR_MSG_ON(_DBG_MII_);
/*get mac*/
ethernet_address(mac);
memcpy((void*)xnetif[ETHERNET_IDX].hwaddr,(void*)mac, 6);
rtw_init_sema(&mii_rx_sema,0);
rtw_mutex_init(&mii_tx_mutex);
if(xTaskCreate(mii_rx_thread, ((const char*)"mii_rx_thread"), 1024, NULL, tskIDLE_PRIORITY+5, NULL) != pdPASS)
DBG_8195A("\n\r%s xTaskCreate(mii_rx_thread) failed", __FUNCTION__);
DBG_8195A("\nEthernet_mii Init done, interface %d", ETHERNET_IDX);
if(dhcp_ethernet_mii == 1){
LwIP_DHCP(ETHERNET_IDX, DHCP_START);
netif_set_default(&xnetif[ETHERNET_IDX]); //Set default gw to ether netif
}
ethernet_init_done = 1;
vTaskDelete(NULL);
}
int ethernet_is_linked()
{
if((link_is_up == 1)&&(1 == ethernet_init_done))
return TRUE;
else
return FALSE;
}
int ethernet_is_unplug()
{
if(ethernet_unplug == 1)
return TRUE;
else
return FALSE;
}
void ethernet_mii_init()
{
printf("\ninitializing Ethernet_mii......\n");
// set the ethernet interface as default
ethernet_if_default = 1;
vSemaphoreCreateBinary(mii_linkup_sema);
if( xTaskCreate((TaskFunction_t)mii_intr_thread, "DHCP_START_MII", 1024, NULL, 3, NULL) != pdPASS) {
DBG_8195A("Cannot create demo task\n\r");
}
if( xTaskCreate((TaskFunction_t)ethernet_demo, "ETHERNET DEMO", 1024, NULL, 2, NULL) != pdPASS) {
DBG_8195A("Cannot create demo task\n\r");
}
#if 0
extern void ethernet_wlan_iperf_test_task(void *param);
if(xTaskCreate((TaskFunction_t)ethernet_wlan_iperf_test_task, "wifi_entry_task", 1024, NULL, 2, NULL) != pdPASS){
printf("\n\r%s xTaskCreate(wifi_entry_task) failed", __FUNCTION__);
}
#endif
}
void rltk_mii_recv(struct eth_drv_sg *sg_list, int sg_len){
struct eth_drv_sg *last_sg;
u8* pbuf = RX_BUFFER;
for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
if (sg_list->buf != 0) {
rtw_memcpy((void *)(sg_list->buf), pbuf, sg_list->len);
pbuf+=sg_list->len;
}
}
}
s8 rltk_mii_send(struct eth_drv_sg *sg_list, int sg_len, int total_len){
int ret =0;
struct eth_drv_sg *last_sg;
u8* pdata = TX_BUFFER;
u8 retry_cnt = 0;
u32 size = 0;
for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
rtw_memcpy(pdata, (void *)(sg_list->buf), sg_list->len);
pdata += sg_list->len;
size += sg_list->len;
}
pdata = TX_BUFFER;
//DBG_8195A("mii_send len= %d\n\r", size);
rtw_mutex_get(&mii_tx_mutex);
while(1){
ret = ethernet_write(pdata, size);
if(ret > 0){
ethernet_send();
ret = 0;
break;
}
if(++retry_cnt > 3){
DBG_8195A("TX drop\n\r");
ret = -1;
}
else
rtw_udelay_os(1);
}
rtw_mutex_put(&mii_tx_mutex);
return ret;
}
#define ____TEST____
/* used for test */
#if 0
#include "wifi_constants.h"
struct iperf_data_t{
uint64_t total_size;
uint64_t bandwidth;
int server_fd;
int client_fd;
uint32_t buf_size;
uint32_t time;
uint32_t report_interval;
uint16_t port;
uint8_t server_ip[16];
uint8_t start;
uint8_t tos_value;
};
/*ATWT=-c,192.168.31.111,-t,10*/
int ethernet_wlan_iperf_test()
{
char server_ip[] = "192.168.31.111";
u16 time = 10;
struct iperf_data_t tcp_client_data;
printf("\n###################ethernet wlan iperf test !!!...\n");
memset(&tcp_client_data, 0, sizeof(tcp_client_data));
strncpy(tcp_client_data.server_ip, server_ip, (strlen(server_ip)>16)?16:strlen(server_ip));
tcp_client_data.time = time;
tcp_client_data.bandwidth = 268459220;
tcp_client_data.buf_size = 1460;
tcp_client_data.client_fd = 0;
tcp_client_data.port = 5001;
tcp_client_data.report_interval = -1;
tcp_client_data.server_fd = 0;
tcp_client_data.start = 1;
tcp_client_data.tos_value = 0;
tcp_client_data.total_size = 0;
tcp_client_func(tcp_client_data);
return 0;
}
void ethernet_wlan_iperf_test_task(void *param)
{
printf("\n#########################ethernet wlan iperf test task...\n");
/* used for test */
p_link_change_callback = (link_up_down_callback)ethernet_wlan_iperf_test;
/*sys_reset is not necessary, upper layer can define p_link_change_callback on demand*/
//p_link_change_callback = (link_up_down_callback)sys_reset();
while(1)
{
if(((wifi_is_ready_to_transceive(RTW_STA_INTERFACE)==RTW_SUCCESS)&&ethernet_is_unplug())||(ethernet_is_linked()))
break;
else
vTaskDelay(500);
}
ethernet_wlan_iperf_test();
printf("\r\n[%s] task del", __func__);
vTaskDelete(NULL);
}
#endif

14
component/common/drivers/ethernet_mii/ethernet_mii.h Executable file
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#ifndef __MII_ETHERNETIF_H__
#define __MII_ETHERNETIF_H__
#include "lwip_netconf.h"
#define MII_TX_DESC_CNT 4
#define MII_RX_DESC_CNT 10
#define ETHERNET_IDX (NET_IF_NUM - 1)
#define WLAN_IDX 0
typedef void (*link_up_down_callback)(int blinkup);
#endif // __MII_ETHERNETIF_H__

183
component/common/drivers/i2s/alc5616.c Executable file
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#include <stdio.h>
#include "PinNames.h"
#include "basic_types.h"
#include "diag.h"
#include "i2c_api.h"
#include "pinmap.h"
//#define I2C_MTR_SDA PC_4//PB_3
//#define I2C_MTR_SCL PC_5//PB_2
#if defined(CONFIG_PLATFORM_8195A)
#define I2C_MTR_SDA PB_3
#define I2C_MTR_SCL PB_2
#elif defined(CONFIG_PLATFORM_8711B)
#define I2C_MTR_SDA PA_30
#define I2C_MTR_SCL PA_29
#endif
#define I2C_BUS_CLK 100000 //hz
#define I2C_ALC5616_ADDR (0x36/2)
#define RT5616_PRIV_INDEX 0x6a
#define RT5616_PRIV_DATA 0x6c
#if defined (__ICCARM__)
i2c_t alc5616_i2c;
#else
volatile i2c_t alc5616_i2c;
#define printf DBG_8195A
#endif
static void alc5616_delay(void)
{
int i;
i=10000;
while (i) {
i--;
asm volatile ("nop\n\t");
}
}
void alc5616_reg_write(unsigned int reg, unsigned int value)
{
char buf[4];
buf[0] = (char)reg;
buf[1] = (char)(value>>8);
buf[2] = (char)(value&0xff);
i2c_write(&alc5616_i2c, I2C_ALC5616_ADDR, &buf[0], 3, 1);
alc5616_delay();
}
void alc5616_reg_read(unsigned int reg, unsigned int *value)
{
int tmp;
char *buf = (char*)&tmp;
buf[0] = (char)reg;
i2c_write(&alc5616_i2c, I2C_ALC5616_ADDR, &buf[0], 1, 1);
alc5616_delay();
buf[0] = 0xaa;
buf[1] = 0xaa;
i2c_read(&alc5616_i2c, I2C_ALC5616_ADDR, &buf[0], 2, 1);
alc5616_delay();
*value= ((buf[0]&0xFF)<<8)|(buf[1]&0xFF);
}
void alc5616_index_write(unsigned int reg, unsigned int value)
{
alc5616_reg_write(RT5616_PRIV_INDEX, reg);
alc5616_reg_write(RT5616_PRIV_DATA, value);
}
void alc5616_index_read(unsigned int reg, unsigned int *value)
{
alc5616_reg_write(RT5616_PRIV_INDEX, reg);
alc5616_reg_read(RT5616_PRIV_DATA, value);
}
void alc5616_reg_dump(void)
{
int i;
unsigned int value;
printf("alc5616 codec reg dump\n\r");
printf("------------------------\n\r");
for(i=0;i<=0xff;i++){
alc5616_reg_read(i, &value);
printf("%02x : %04x\n\r", i, (unsigned short)value);
}
printf("------------------------\n\r");
}
void alc5616_index_dump(void)
{
int i;
unsigned int value;
printf("alc5616 codec index dump\n\r");
printf("------------------------\n\r");
for(i=0;i<=0xff;i++){
alc5616_index_read(i, &value);
printf("%02x : %04x\n\r", i, (unsigned short)value);
}
printf("------------------------\n\r");
}
void alc5616_init(void)
{
i2c_init(&alc5616_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
i2c_frequency(&alc5616_i2c, I2C_BUS_CLK);
}
void alc5616_set_word_len(int len_idx) // interface2
{
// 0: 16 1: 20 2: 24 3: 8
unsigned int val;
alc5616_reg_read(0x71,&val);
val &= (~(0x3<<2));
val |= (len_idx<<2);
alc5616_reg_write(0x71,val);
alc5616_reg_read(0x70,&val);
val &= (~(0x3<<2));
val |= (len_idx<<2);
alc5616_reg_write(0x70,val);
}
void alc5616_init_interface1(void)
{
alc5616_reg_write(0x00,0x0021);
alc5616_reg_write(0x63,0xE8FE);
alc5616_reg_write(0x61,0x5800);
alc5616_reg_write(0x62,0x0C00);
alc5616_reg_write(0x73,0x0000);
alc5616_reg_write(0x2A,0x4242);
alc5616_reg_write(0x45,0x2000);
alc5616_reg_write(0x02,0x4848);
alc5616_reg_write(0x8E,0x0019);
alc5616_reg_write(0x8F,0x3100);
alc5616_reg_write(0x91,0x0E00);
alc5616_index_write(0x3D,0x3E00);
alc5616_reg_write(0xFA,0x0011);
alc5616_reg_write(0x83,0x0800);
alc5616_reg_write(0x84,0xA000);
alc5616_reg_write(0xFA,0x0C11);
alc5616_reg_write(0x64,0x4010);
alc5616_reg_write(0x65,0x0C00);
alc5616_reg_write(0x61,0x5806);
alc5616_reg_write(0x62,0xCC00);
alc5616_reg_write(0x3C,0x004F);
alc5616_reg_write(0x3E,0x004F);
alc5616_reg_write(0x27,0x3820);
alc5616_reg_write(0x77,0x0000);
}
void alc5616_init_interface2(void)
{
alc5616_reg_write(0x00,0x0000);
alc5616_reg_write(0x02,0x0808);
alc5616_reg_write(0x19,0xAFAF);
alc5616_reg_write(0x29,0x8080);
alc5616_reg_write(0x45,0x2000);
alc5616_reg_write(0x2A,0x1212);
alc5616_reg_write(0x53,0x3000);
alc5616_reg_write(0x03,0x4848);
alc5616_reg_write(0x61,0x9800);
alc5616_reg_write(0x62,0x0800);
alc5616_reg_write(0x63,0xF8FF);
alc5616_reg_write(0x64,0x0000);
alc5616_reg_write(0x65,0x0000);
alc5616_reg_write(0x66,0x0000);
alc5616_reg_write(0x70,0x8000);
alc5616_reg_write(0x73,0x0104);
alc5616_reg_write(0x8E,0x0019);
alc5616_reg_write(0x8F,0x2000);
alc5616_reg_write(0xFA,0x0001);
alc5616_index_write(0x3D,0x0600);
}

9
component/common/drivers/i2s/alc5616.h Executable file
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#ifndef _ALC5616_H_
#define _ALC5616_H_
void alc5616_reg_dump(void);
void alc5616_index_dump(void);
void alc5616_init(void);
void alc5616_set_word_len(int len_idx);
void alc5616_init_interface1(void);
void alc5616_init_interface2(void);
#endif

181
component/common/drivers/i2s/alc5640.c Executable file
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#include <stdio.h>
#include "FreeRTOS.h"
#include "PinNames.h"
#include "basic_types.h"
#include "diag.h"
#include <osdep_api.h>
#include "i2c_api.h"
#include "pinmap.h"
//#define I2C_MTR_SDA PC_4//PB_3
//#define I2C_MTR_SCL PC_5//PB_2
#if defined(CONFIG_PLATFORM_8195A)
#define I2C_MTR_SDA PB_3
#define I2C_MTR_SCL PB_2
#elif defined(CONFIG_PLATFORM_8711B)
#define I2C_MTR_SDA PA_30
#define I2C_MTR_SCL PA_29
#endif
#define I2C_BUS_CLK 100000 //hz
#define I2C_ALC5640_ADDR (0x38/2)
#define RT5640_PRIV_INDEX 0x6a
#define RT5640_PRIV_DATA 0x6c
#if defined (__ICCARM__)
i2c_t alc5640_i2c;
#else
volatile i2c_t alc5640_i2c;
#endif
static void alc5640_delay(void)
{
int i;
i=10000;
while (i) {
i--;
asm volatile ("nop\n\t");
}
}
void alc5640_reg_write(unsigned int reg, unsigned int value)
{
char buf[4];
buf[0] = (char)reg;
buf[1] = (char)(value>>8);
buf[2] = (char)(value&0xff);
i2c_write(&alc5640_i2c, I2C_ALC5640_ADDR, &buf[0], 3, 1);
alc5640_delay();
}
void alc5640_reg_read(unsigned int reg, unsigned int *value)
{
int tmp;
char *buf = (char*)&tmp;
buf[0] = (char)reg;
i2c_write(&alc5640_i2c, I2C_ALC5640_ADDR, &buf[0], 1, 1);
alc5640_delay();
buf[0] = 0xaa;
buf[1] = 0xaa;
i2c_read(&alc5640_i2c, I2C_ALC5640_ADDR, &buf[0], 2, 1);
alc5640_delay();
*value= ((buf[0]&0xFF)<<8)|(buf[1]&0xFF);
}
void alc5640_index_write(unsigned int reg, unsigned int value)
{
alc5640_reg_write(RT5640_PRIV_INDEX, reg);
alc5640_reg_write(RT5640_PRIV_DATA, value);
}
void alc5640_index_read(unsigned int reg, unsigned int *value)
{
alc5640_reg_write(RT5640_PRIV_INDEX, reg);
alc5640_reg_read(RT5640_PRIV_DATA, value);
}
void alc5640_reg_dump(void)
{
int i;
unsigned int value;
printf("alc5640 codec reg dump\n\r");
printf("------------------------\n\r");
for(i=0;i<=0xff;i++){
alc5640_reg_read(i, &value);
printf("%02x : %04x\n\r", i, (unsigned short)value);
}
printf("------------------------\n\r");
}
void alc5640_index_dump(void)
{
int i;
unsigned int value;
printf("alc5640 codec index dump\n\r");
printf("------------------------\n\r");
for(i=0;i<=0xff;i++){
alc5640_index_read(i, &value);
printf("%02x : %04x\n\r", i, (unsigned short)value);
}
printf("------------------------\n\r");
}
void alc5640_init(void)
{
i2c_init(&alc5640_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
i2c_frequency(&alc5640_i2c, I2C_BUS_CLK);
}
void alc5640_set_word_len(int len_idx) // interface2
{
// 0: 16 1: 20 2: 24 3: 8
unsigned int val;
alc5640_reg_read(0x71,&val);
val &= (~(0x3<<2));
val |= (len_idx<<2);
alc5640_reg_write(0x71,val);
alc5640_reg_read(0x70,&val);
val &= (~(0x3<<2));
val |= (len_idx<<2);
alc5640_reg_write(0x70,val);
}
void alc5640_init_interface1(void)
{
// I2S1 -> DAC -> SPK R/L
alc5640_reg_write(0x00,0x0021);
alc5640_reg_write(0xD9,0x0009);
alc5640_reg_write(0x73,0x0014);
alc5640_reg_write(0xFA,0x3401);
alc5640_index_write(0x1C,0x0D21);
alc5640_reg_write(0x63,0xA8F0);
wait_ms(100); // delay 100 ms.
alc5640_reg_write(0x63,0xE8F8);
alc5640_reg_write(0x61,0x9801);
alc5640_index_write(0x3D,0x2600);
alc5640_index_write(0x1C,0xFD21);
alc5640_reg_write(0x2A,0x1414);
alc5640_reg_write(0x48,0xB800);
alc5640_reg_write(0x49,0x1800);
alc5640_reg_write(0x01,0x4848);
alc5640_reg_write(0xD9,0x0809);
}
void alc5640_init_interface2(void)
{
alc5640_reg_write(0x00,0x0021);
alc5640_reg_write(0x63,0xE8FE);
alc5640_reg_write(0x61,0x5800);
alc5640_reg_write(0x62,0x0C00);
alc5640_reg_write(0x73,0x0000);
alc5640_reg_write(0x2A,0x4242);
alc5640_reg_write(0x45,0x2000);
alc5640_reg_write(0x02,0x4848);
alc5640_reg_write(0x8E,0x0019);
alc5640_reg_write(0x8F,0x3100);
alc5640_reg_write(0x91,0x0E00);
alc5640_index_write(0x3D,0x3E00);
alc5640_reg_write(0xFA,0x0011);
alc5640_reg_write(0x83,0x0800);
alc5640_reg_write(0x84,0xA000);
alc5640_reg_write(0xFA,0x0C11);
alc5640_reg_write(0x64,0x4010);
alc5640_reg_write(0x65,0x0C00);
alc5640_reg_write(0x61,0x5806);
alc5640_reg_write(0x62,0xCC00);
alc5640_reg_write(0x3C,0x004F);
alc5640_reg_write(0x3E,0x004F);
alc5640_reg_write(0x28,0x3030);
alc5640_reg_write(0x2F,0x0080);
}

9
component/common/drivers/i2s/alc5640.h Executable file
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#ifndef _ALC5640_H_
#define _ALC5640_H_
void alc5640_reg_dump(void);
void alc5640_index_dump(void);
void alc5640_init(void);
void alc5640_set_word_len(int len_idx);
void alc5640_init_interface1(void);
void alc5640_init_interface2(void);
#endif

201
component/common/drivers/i2s/alc5651.c Executable file
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#include <stdio.h>
#include "PinNames.h"
#include "basic_types.h"
#include "diag.h"
#include <osdep_api.h>
#include "i2c_api.h"
#include "pinmap.h"
//#define I2C_MTR_SDA PC_4//PB_3
//#define I2C_MTR_SCL PC_5//PB_2
#if defined(CONFIG_PLATFORM_8195A)
#define I2C_MTR_SDA PB_3
#define I2C_MTR_SCL PB_2
#elif defined(CONFIG_PLATFORM_8711B)
#define I2C_MTR_SDA PA_30
#define I2C_MTR_SCL PA_29
#endif
#define I2C_BUS_CLK 100000 //hz
#define I2C_ALC5651_ADDR (0x34/2)
#define RT5651_PRIV_INDEX 0x6a
#define RT5651_PRIV_DATA 0x6c
#if defined (__ICCARM__)
i2c_t alc5651_i2c;
#else
volatile i2c_t alc5651_i2c;
#define printf DBG_8195A
#endif
static void alc5651_delay(void)
{
int i;
i=10000;
while (i) {
i--;
asm volatile ("nop\n\t");
}
}
void alc5651_reg_write(unsigned int reg, unsigned int value)
{
char buf[4];
buf[0] = (char)reg;
buf[1] = (char)(value>>8);
buf[2] = (char)(value&0xff);
i2c_write(&alc5651_i2c, I2C_ALC5651_ADDR, &buf[0], 3, 1);
alc5651_delay();
}
void alc5651_reg_read(unsigned int reg, unsigned int *value)
{
int tmp;
char *buf = (char*)&tmp;
buf[0] = (char)reg;
i2c_write(&alc5651_i2c, I2C_ALC5651_ADDR, &buf[0], 1, 1);
alc5651_delay();
buf[0] = 0xaa;
buf[1] = 0xaa;
i2c_read(&alc5651_i2c, I2C_ALC5651_ADDR, &buf[0], 2, 1);
alc5651_delay();
*value= ((buf[0]&0xFF)<<8)|(buf[1]&0xFF);
}
void alc5651_index_write(unsigned int reg, unsigned int value)
{
alc5651_reg_write(RT5651_PRIV_INDEX, reg);
alc5651_reg_write(RT5651_PRIV_DATA, value);
}
void alc5651_index_read(unsigned int reg, unsigned int *value)
{
alc5651_reg_write(RT5651_PRIV_INDEX, reg);
alc5651_reg_read(RT5651_PRIV_DATA, value);
}
void alc5651_reg_dump(void)
{
int i;
unsigned int value;
printf("alc5651 codec reg dump\n\r");
printf("------------------------\n\r");
for(i=0;i<=0xff;i++){
alc5651_reg_read(i, &value);
printf("%02x : %04x\n\r", i, (unsigned short)value);
}
printf("------------------------\n\r");
}
void alc5651_index_dump(void)
{
int i;
unsigned int value;
printf("alc5651 codec index dump\n\r");
printf("------------------------\n\r");
for(i=0;i<=0xff;i++){
alc5651_index_read(i, &value);
printf("%02x : %04x\n\r", i, (unsigned short)value);
}
printf("------------------------\n\r");
}
void alc5651_init(void)
{
i2c_init(&alc5651_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
i2c_frequency(&alc5651_i2c, I2C_BUS_CLK);
}
void alc5651_set_word_len(int len_idx) // interface2
{
// 0: 16 1: 20 2: 24 3: 8
unsigned int val;
alc5651_reg_read(0x71,&val);
val &= (~(0x3<<2));
val |= (len_idx<<2);
alc5651_reg_write(0x71,val);
alc5651_reg_read(0x70,&val);
val &= (~(0x3<<2));
val |= (len_idx<<2);
alc5651_reg_write(0x70,val);
}
void alc5651_init_interface1(void)
{
alc5651_reg_write(0x00,0x0021);
alc5651_reg_write(0x63,0xE8FE);
alc5651_reg_write(0x61,0x5800);
alc5651_reg_write(0x62,0x0C00);
alc5651_reg_write(0x73,0x0000);
alc5651_reg_write(0x2A,0x4242);
alc5651_reg_write(0x45,0x2000);
alc5651_reg_write(0x02,0x4848);
alc5651_reg_write(0x8E,0x0019);
alc5651_reg_write(0x8F,0x3100);
alc5651_reg_write(0x91,0x0E00);
alc5651_index_write(0x3D,0x3E00);
alc5651_reg_write(0xFA,0x0011);
alc5651_reg_write(0x83,0x0800);
alc5651_reg_write(0x84,0xA000);
alc5651_reg_write(0xFA,0x0C11);
alc5651_reg_write(0x64,0x4010);
alc5651_reg_write(0x65,0x0C00);
alc5651_reg_write(0x61,0x5806);
alc5651_reg_write(0x62,0xCC00);
alc5651_reg_write(0x3C,0x004F);
alc5651_reg_write(0x3E,0x004F);
alc5651_reg_write(0x27,0x3820);
alc5651_reg_write(0x77,0x0000);
}
void alc5651_init_interface2(void)
{
int reg_value=0;
alc5651_reg_write(0x00,0x0021);//reset all, device id 1
alc5651_reg_write(0x63,0xE8FE);//Power managerment control 3:
//VREF1&2 on, both slow VREF, MBIAS on, MBIAS bandcap power on, L & R HP Amp on, improve HP Amp driving enabled
alc5651_reg_write(0x61,0x5800);//power managerment control 1:
//I2S2 digital interface on, Analog DACL1 & DACR1 on.
alc5651_reg_write(0x62,0x0C00);//stereo1 & 2 DAC filter power on
alc5651_reg_write(0x73,0x0000);//ADC/DAC Clock control 1:
//I2S Clock Pre-Divider 1 & 2: /1. Stereo DAC Over Sample Rate : 128Fs
alc5651_reg_write(0x2A,0x4242);//Stereo DAC digital mixer control
//Un-mute DACL2 to Stereo DAC Left & Right Mixer
alc5651_reg_write(0x45,0x2000);//HPOMIX: Un-mute DAC1 to HPOMIX
alc5651_reg_write(0x02,0x4848);//HP Output Control:
//Unmute HPOL, HPOR
// alc5651_reg_write(0x0F,0x1F1F);//INL & INR Volume Control
// alc5651_reg_write(0x0D,0x0800);//IN1/2 Input Control
// alc5651_reg_write(0x1C,0x7F7F);//Stereo1 ADC Digital Volume Control
// alc5651_reg_write(0x1E,0xF000);// ADC Digital Boost Gain Control
alc5651_reg_write(0x8E,0x0019);//HP Amp Control 1
// Enable HP Output, Charge Pump Power On, HP Amp All Power On
alc5651_reg_write(0x8F,0x3100);//HP Amp Control 2, HP Depop Mode 2
alc5651_reg_write(0x91,0x0E00);//HP Amp Control 3, select HP capless power mode
alc5651_index_write(0x3D,0x3E00);//unknown
alc5651_reg_write(0xFA,0x0011);//enable input clock
alc5651_reg_write(0x83,0x0800);//default ASRC control 1
alc5651_reg_write(0x84,0xA000);//ASRC control 2: I2S1 enable ASRC mode, Sterol1 DAC filter ASRC mode.
// alc5651_reg_write(0xFA,0x0C11);//? ? ? MX-FAh[15:4]reserved
alc5651_reg_write(0x64,0x4010);//power managerment control 4:
//MIC BST2 Power On; MIC2 SE Mode single-end mode or line-input mode
alc5651_reg_write(0x65,0x0C00);//power managerment control 5: RECMIX L & R power on
alc5651_reg_write(0x61,0x5806);//power managerment control 1:
// I2S2 Digital Interface On, Analog DACL1, DACR1 power on; Analog ADCL, ADCR power on
alc5651_reg_write(0x62,0xCC00);//power managerment control 2: Stereo1&2 ADC/DAC digital filter power on
alc5651_reg_write(0x3C,0x004F);//RECMIXL
alc5651_reg_write(0x3E,0x004F);//RECMIXR
alc5651_reg_write(0x28,0x3030);//stereo2 ADC digital mixer control : Mute Stereo2 ADC L&R channel, ADCR
alc5651_reg_write(0x2F,0x0080); //Interface DAC/ADC Data control: Select IF2 ADCDAT Data Source IF1_ADC2
}

9
component/common/drivers/i2s/alc5651.h Executable file
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#ifndef _ALC5651_H_
#define _ALC5651_H_
void alc5651_reg_dump(void);
void alc5651_index_dump(void);
void alc5651_init(void);
void alc5651_set_word_len(int len_idx);
void alc5651_init_interface1(void);
void alc5651_init_interface2(void);
#endif

184
component/common/drivers/i2s/alc5660.c Executable file
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#include <stdio.h>
#include "PinNames.h"
#include "basic_types.h"
#include "diag.h"
#include <osdep_api.h>
#include "i2c_api.h"
#include "pinmap.h"
#include "alc5660.h"
//#define I2C_MTR_SDA PC_4//PB_3
//#define I2C_MTR_SCL PC_5//PB_2
#define I2C_MTR_SDA PB_3
#define I2C_MTR_SCL PB_2
#define I2C_BUS_CLK 100000 //hz
#define I2C_ALC5660_ADDR (0x38/2)
#define RT5660_PRIV_INDEX 0x6a
#define RT5660_PRIV_DATA 0x6c
i2c_t alc5660_i2c;
#undef printf
#define printf DBG_8195A
static void alc5660_delay(void)
{
int i;
i=10000;
while (i) {
i--;
asm volatile ("nop\n\t");
}
}
void alc5660_reg_write(unsigned int reg, unsigned int value)
{
char buf[4];
buf[0] = (char)reg;
buf[1] = (char)(value>>8);
buf[2] = (char)(value&0xff);
i2c_write(&alc5660_i2c, I2C_ALC5660_ADDR, &buf[0], 3, 1);
alc5660_delay();
}
void alc5660_reg_read(unsigned int reg, unsigned int *value)
{
int tmp;
char *buf = (char*)&tmp;
buf[0] = (char)reg;
i2c_write(&alc5660_i2c, I2C_ALC5660_ADDR, &buf[0], 1, 1);
alc5660_delay();
buf[0] = 0xaa;
buf[1] = 0xaa;
i2c_read(&alc5660_i2c, I2C_ALC5660_ADDR, &buf[0], 2, 1);
alc5660_delay();
*value= ((buf[0]&0xFF)<<8)|(buf[1]&0xFF);
}
void alc5660_index_write(unsigned int reg, unsigned int value)
{
alc5660_reg_write(RT5660_PRIV_INDEX, reg);
alc5660_reg_write(RT5660_PRIV_DATA, value);
}
void alc5660_index_read(unsigned int reg, unsigned int *value)
{
alc5660_reg_write(RT5660_PRIV_INDEX, reg);
alc5660_reg_read(RT5660_PRIV_DATA, value);
}
void alc5660_reg_dump(void)
{
int i;
unsigned int value;
printf("alc5660 codec reg dump\n\r");
printf("------------------------\n\r");
for(i=0;i<=0xff;i++){
alc5660_reg_read(i, &value);
printf("%02x : %04x\n\r", i, (unsigned short)value);
}
printf("------------------------\n\r");
}
void alc5660_index_dump(void)
{
int i;
unsigned int value;
printf("alc5660 codec index dump\n\r");
printf("------------------------\n\r");
for(i=0;i<=0xff;i++){
alc5660_index_read(i, &value);
printf("%02x : %04x\n\r", i, (unsigned short)value);
}
printf("------------------------\n\r");
}
void alc5660_init(void)
{
i2c_init(&alc5660_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
i2c_frequency(&alc5660_i2c, I2C_BUS_CLK);
}
void alc5660_set_word_len(int len_idx) // interface2
{
// 0: 16 1: 20 2: 24 3: 8
unsigned int val;
alc5660_reg_read(0x71,&val);
val &= (~(0x3<<2));
val |= (len_idx<<2);
alc5660_reg_write(0x71,val);
alc5660_reg_read(0x70,&val);
val &= (~(0x3<<2));
val |= (len_idx<<2);
alc5660_reg_write(0x70,val);
}
void alc5660_init_interface1(void)
{
alc5660_reg_write(0x00,0x0021);
alc5660_reg_write(0x63,0xA8F4);
alc5660_reg_write(0x61,0x5800);
alc5660_reg_write(0x62,0x0C00);
alc5660_reg_write(0x73,0x0000);
alc5660_reg_write(0x2A,0x4242);
alc5660_reg_write(0x45,0x2000);
alc5660_reg_write(0x02,0x4848);
alc5660_reg_write(0x8E,0x0019);
alc5660_reg_write(0x8F,0x3100);
alc5660_reg_write(0x91,0x0E00);
alc5660_index_write(0x3D,0x3E00);
alc5660_reg_write(0xFA,0x0821);
alc5660_reg_write(0x83,0x0800);
alc5660_reg_write(0x84,0xA000);
//alc5660_reg_write(0xFA,0x0C11);
alc5660_reg_write(0x64,0x4010);
alc5660_reg_write(0x65,0x0C00);
alc5660_reg_write(0x61,0x5806);
alc5660_reg_write(0x62,0xCC00);
alc5660_reg_write(0x3C,0x004F);
alc5660_reg_write(0x3E,0x004F);
alc5660_reg_write(0x27,0x3820);
alc5660_reg_write(0x77,0x0000);
}
void alc5660_init_interface2(void)
{
alc5660_reg_write(0x00,0x0001);
alc5660_reg_write(0xFA,0x0821);
alc5660_reg_write(0x63,0xA8F4);
//alc5660_reg_write(0x63,0xA814);
//alc5660_delay();
alc5660_reg_write(0x61,0x9807);
//alc5660_delay();
alc5660_reg_write(0x62,0x8800);
alc5660_reg_write(0x64,0x8a00);
alc5660_reg_write(0x65,0x0C00);
alc5660_reg_write(0x6A,0x003D);
alc5660_reg_write(0x6C,0x3600);
alc5660_reg_write(0x73,0x0004);
alc5660_reg_write(0x0D,0x9010);
alc5660_reg_write(0x3C,0x007D);
alc5660_reg_write(0x3E,0x007D);
alc5660_reg_write(0x27,0x2020);
alc5660_reg_write(0x02,0x4848);
alc5660_reg_write(0x45,0xA000);
alc5660_reg_write(0x2A,0x0202);
alc5660_reg_write(0x73,0x0000);
alc5660_reg_write(0x8E,0x0011);
alc5660_reg_write(0x29,0x8080);
alc5660_reg_write(0xEB,0x44C3);
alc5660_reg_write(0x48,0x9800);
alc5660_reg_write(0x01,0x4800);
}

9
component/common/drivers/i2s/alc5660.h Executable file
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#ifndef _ALC5660_H_
#define _ALC5660_H_
void alc5660_reg_dump(void);
void alc5660_index_dump(void);
void alc5660_init(void);
void alc5660_set_word_len(int len_idx);
void alc5660_init_interface1(void);
void alc5660_init_interface2(void);
#endif

227
component/common/drivers/i2s/alc5679.c Executable file
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#include "PinNames.h"
#include "basic_types.h"
#include <osdep_api.h>
#include "i2c_api.h"
#include "i2c_ex_api.h"
#include "pinmap.h"
#include "wait_api.h"
#include "alc5679.h"
#define I2C_ALC5679_ADDR (0X5A/2)//(0x58/2)
#if defined(CONFIG_PLATFORM_8195A)
#define I2C_MTR_SDA PB_3
#define I2C_MTR_SCL PB_2
#elif defined(CONFIG_PLATFORM_8711B)
#define I2C_MTR_SDA PA_30
#define I2C_MTR_SCL PA_29
#endif
#define I2C_BUS_CLK 100000 //100K HZ
//i2c_t rt5679_i2c;
#if defined (__ICCARM__)
i2c_t rt5679_i2c;
#else
volatile i2c_t rt5679_i2c;
#define printf DBG_8195A
#endif
static void rt5679_delay(void)
{
int i;
i=10000;
while (i) {
i--;
asm volatile ("nop\n\t");
}
}
u8 rt5679_reg_write(u16 reg, u16 val)
{
int length = 0;
char buf[4];
buf[0] = (char)(reg >> 8);
buf[1] = (char)(reg&0xff);
buf[2] = (char)(val>>8);
buf[3] = (char)(val&0xff);
length = i2c_write(&rt5679_i2c, I2C_ALC5679_ADDR, &buf[0], 4, 1);
rt5679_delay();
return (length==4)?0:1;
}
u8 rt5679_reg_read(u16 reg, u16* val)
{
int tmp;
char *buf = (char*)&tmp;
u8 ret = 0;
buf[0] = (char)(reg >> 8);
buf[1] = (char)(reg&0xff);
if(i2c_write(&rt5679_i2c, I2C_ALC5679_ADDR, &buf[0], 2, 1) != 2){
DBG_8195A("rt5679_reg_read(): write register addr fail\n");
ret = 1;
}
rt5679_delay();
buf[0] = 0xaa;
buf[1] = 0xaa;
if(i2c_read(&rt5679_i2c, I2C_ALC5679_ADDR, &buf[0], 2, 1) < 2){
DBG_8195A("rt5679_reg_read(): read register value fail\n");
ret = 1;
}else
*val = ((buf[0]&0xFF)<<8)|(buf[1]&0xFF);
rt5679_delay();
return ret;
}
u16 rt5679_reg_modify(u16 reg, u16 val, u16 iMask)
{
u16 val1;
rt5679_reg_read(reg, &val1);
u16 val2 = (val1 &(~iMask))|val;
if(!rt5679_reg_write(reg, val2)) return 0;
return val2;
}
void rt5679_i2c_init(void)
{
i2c_init(&rt5679_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
i2c_frequency(&rt5679_i2c, I2C_BUS_CLK);
}
int rt5679_check_id(void)
{
unsigned short ret = 0;
rt5679_reg_read(RT5679_VENDOR_ID2, &ret);
printf("Device with ID register is %x \n", ret);
if (ret != RT5679_DEVICE_ID) {
printf("Device with ID register %x is not rt5679\n", ret);
return 1;
}else{
return 0;
}
}
void rt5679_reg_dump(void)
{
int i;
unsigned short value;
printf("rt5679 codec reg dump\n\r");
printf("------------------------\n\r");
for(i=0;i<=0xff;i++){
rt5679_reg_read(i, &value);
printf("%02x : %04x\n\r", i, value);
}
printf("------------------------\n\r");
}
void rt5679_mic_to_i2s(void)
{
rt5679_reg_write(0x0000,0x10EC);
rt5679_reg_write(0x00FA,0x0001);
rt5679_reg_write(0x0076,0x0777);
rt5679_reg_write(0x0078,0x0000);
rt5679_reg_write(0x004A,0x8080);
rt5679_reg_write(0x0050,0x8553);
rt5679_reg_write(0x0061,0x8000);
rt5679_reg_write(0x0062,0x8000);
rt5679_reg_write(0x00C2,0x5000);
}
void rt5679_linein_to_i2s(void)
{
rt5679_reg_write(0x0000,0x10EC);
rt5679_reg_write(0x061D,0x04DF);
rt5679_reg_write(0x0007,0x1010);
rt5679_reg_write(0x004A,0x4040);
rt5679_reg_write(0x0060,0x0060);
rt5679_reg_write(0x0061,0x8000);
rt5679_reg_write(0x0062,0x8000);
rt5679_reg_write(0x0063,0xE340);
rt5679_reg_write(0x0064,0xC000);
rt5679_reg_write(0x0066,0x2000);
//rt5679_reg_write(0x0070,0x8020);//32 bit
rt5679_reg_write(0x0070,0x8000);//16bit
//rt5679_reg_write(0x0070,0x8040);//enable mono mode
rt5679_reg_write(0x0076,0x0777);
rt5679_reg_write(0x0078,0x0000);
rt5679_reg_write(0x00FA,0x0001);
rt5679_reg_write(0x0610,0xB490);
}
void rt5679_i2s_to_hp(void)
{
rt5679_reg_write(0x0000,0x10EC);
rt5679_reg_write(0x0609,0x1122);
rt5679_reg_write(0x060A,0x3622);
rt5679_reg_write(0x060B,0x1022);
rt5679_reg_write(0x060C,0x3622);
rt5679_reg_write(0x0671,0xC0D0);
rt5679_reg_write(0x0603,0x0444);
rt5679_reg_write(0x068F,0x0007);
rt5679_reg_write(0x0690,0x0007);
rt5679_reg_write(0x0684,0x0217);
rt5679_reg_write(0x0122,0x0000);
rt5679_reg_write(0x0121,0x0000);
rt5679_reg_write(0x0014,0x5454);
rt5679_reg_write(0x0673,0xAEAA);
rt5679_reg_write(0x0660,0x3840);
///////////////////////////////
rt5679_reg_write(0x0661,0x3840);
rt5679_reg_write(0x0665,0x0101);
rt5679_reg_write(0x0681,0x0118);
rt5679_reg_write(0x0682,0x0118);
rt5679_reg_write(0x07F3,0x0008);
rt5679_reg_write(0x061D,0xE4CF);
rt5679_reg_write(0x00FA,0x0001);
rt5679_reg_write(0x0076,0x0777);
rt5679_reg_write(0x0078,0x0000);
rt5679_reg_write(0x0660,0x3840);
rt5679_reg_write(0x0661,0x3840);
rt5679_reg_write(0x0070,0x8000);//16bit 8000 32bit 8020
rt5679_reg_write(0x0040,0xF0AA);
rt5679_reg_write(0x0046,0x8080);
////////////////////////////////
rt5679_reg_write(0x0061,0x8000);
rt5679_reg_write(0x0062,0x0400);
rt5679_reg_write(0x061D,0xE4CF);
rt5679_reg_write(0x0063,0xA240);
rt5679_reg_write(0x0066,0x1680);
wait_ms(20);
rt5679_reg_write(0x0063,0xE340);
rt5679_reg_write(0x0066,0x1F80);
rt5679_reg_write(0x0066,0xDF80);
rt5679_reg_write(0x0080,0x6000);
rt5679_reg_write(0x0063,0xE342);
rt5679_reg_write(0x0076,0x1777);
rt5679_reg_write(0x0066,0xFF80);
rt5679_reg_write(0x000A,0x5353);
rt5679_reg_write(0x0614,0xB490);
rt5679_reg_write(0x0060,0x0003);
rt5679_reg_write(0x0401,0x0630);
////////////////////////////////
rt5679_reg_write(0x0403,0x0267);
rt5679_reg_write(0x0404,0x9ECD);
rt5679_reg_write(0x0400,0x7D00);
rt5679_reg_write(0x0400,0xFD00);
wait_ms(650);
rt5679_reg_write(0x0080,0x0000);
rt5679_reg_write(0x0063,0xE340);
rt5679_reg_write(0x0076,0x0777);
rt5679_reg_write(0x019B,0x0003);
rt5679_reg_write(0x0003,0x8080);
rt5679_reg_write(0x0066,0xDF80);
rt5679_reg_write(0x000A,0x5455);
rt5679_reg_write(0x0614,0xA490);
rt5679_reg_write(0x0060,0x0000);
rt5679_reg_write(0x0404,0x9E0C);
}

13
component/common/drivers/i2s/alc5679.h Executable file
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#ifndef _ALC5679_H_
#define _ALC5679_H_
#define RT5679_DEVICE_ID 0x6385
#define RT5679_VENDOR_ID2 0x00ff
/////////////////////////////////////////////////////
void rt5679_i2c_init(void);
int check_id();
void rt5679_linein_to_i2s(void);
void rt5679_i2s_to_hp(void);
void rt5679_mic_to_i2s(void);
#endif

446
component/common/drivers/i2s/alc5680.c Executable file
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#include "PinNames.h"
#include "basic_types.h"
#include <osdep_api.h>
#include "i2c_api.h"
#include "i2c_ex_api.h"
#include "pinmap.h"
#include "wait_api.h"
#include "alc5680.h"
#define I2C_ALC5680_ADDR (0X5A/2)
#if defined(CONFIG_PLATFORM_8195A)
#define I2C_MTR_SDA PB_3
#define I2C_MTR_SCL PB_2
#elif defined(CONFIG_PLATFORM_8711B)
#define I2C_MTR_SDA PA_30
#define I2C_MTR_SCL PA_29
#endif
#define I2C_BUS_CLK 100000 //100K HZ
//i2c_t alc5680_i2c;
#if defined (__ICCARM__)
i2c_t alc5680_i2c;
#else
volatile i2c_t alc5680_i2c;
#define printf DBG_8195A
#endif
#define HELLO_BLUE_GENIE 0X03
#define ALEXA 0X04
#define SESAMEE 0X05
#define BAIDU 0X76
#define OLD_VERSION 0
#define NEW_VERSION 1
#define ALC_FW_START_ADDR 0X70000000
#if OLD_VERSION
#define header_offset 32 //[addr1][len1][addr2]][len2][addr3]][len3][size][checksum]
typedef struct _alc5680_fw{
unsigned int alc_addr[3];
unsigned int alc_len[3];
unsigned int size;
unsigned int checksum;
unsigned int alc_addr_offset;
unsigned int alc_len_offset;
unsigned int alc_len_index;
}alc5680_fw;
#endif
#if NEW_VERSION
#define header_offset 12 //[size][checksum][version]
typedef struct _alc5680_fw{
unsigned int version;
unsigned int size;
unsigned int checksum;
unsigned int alc_addr_offset;
unsigned int alc_len_offset;
}alc5680_fw;
#endif
static alc5680_fw alc5680_info;
static void alc5680_delay(void)
{
int i;
i=10000;
while (i) {
i--;
asm volatile ("nop\n\t");
}
}
u8 alc5680_reg_write_16(u16 reg, u16 val)
{
int length = 0;
char buf[4];
buf[0] = (char)(reg >> 8);
buf[1] = (char)(reg&0xff);
buf[2] = (char)(val>>8);
buf[3] = (char)(val&0xff);
length = i2c_write(&alc5680_i2c, I2C_ALC5680_ADDR, &buf[0], 4, 1);
//alc5680_delay();
return (length==4)?0:1;
}
u8 alc5680_reg_write_32(u32 reg, u32 val)
{
int tmp;
char *buf = (char*)&tmp;
u16 val1;
u8 ret = 0;
ret = alc5680_reg_write_16(0x0001,reg&0xffff);
if(ret != 0)
printf("error\r\n");
ret = alc5680_reg_write_16(0x0002,reg>>16);
if(ret != 0)
printf("error\r\n");
ret = alc5680_reg_write_16(0x0003,val&0xffff);
if(ret != 0)
printf("error\r\n");
ret = alc5680_reg_write_16(0x0004,val>>16);
if(ret != 0)
printf("error\r\n");
ret = alc5680_reg_write_16(0x0000,0x0003);
if(ret != 0)
printf("error\r\n");
return 0;
}//0x1800C02C
u8 alc5680_reg_write_16b(u32 reg, u16 val)
{
int tmp;
char *buf = (char*)&tmp;
u16 val1;
u8 ret = 0;
ret = alc5680_reg_write_16(0x0001,reg&0xffff);
if(ret != 0)
printf("error\r\n");
ret = alc5680_reg_write_16(0x0002,reg>>16);
if(ret != 0)
printf("error\r\n");
ret = alc5680_reg_write_16(0x0003,val&0xffff);
if(ret != 0)
printf("error\r\n");
ret = alc5680_reg_write_16(0x0000,0x0001);
if(ret != 0)
printf("error\r\n");
return 0;
}
u8 alc5680_reg_read_32(u32 reg, u32* val)
{
unsigned int tmp;
char *buf = (char*)&tmp;
u16 val1;
u8 ret = 0;
ret = alc5680_reg_write_16(0x0001,reg&0xffff);
if(ret != 0)
printf("error\r\n");
ret = alc5680_reg_write_16(0x0002,reg>>16);
if(ret != 0)
printf("error\r\n");
ret = alc5680_reg_write_16(0x0000,0x0002);
if(ret != 0)
printf("error\r\n");
buf[0] = 0x0003>>8;
buf[1] = 0x0003&0xff;
if(i2c_write(&alc5680_i2c, I2C_ALC5680_ADDR, &buf[0], 2, 1) != 2){
DBG_8195A("alc5680_reg_read(): write register addr fail\n");
ret = 1;
}
//alc5680_delay();
buf[0] = 0xaa;
buf[1] = 0xaa;
if(i2c_read(&alc5680_i2c, I2C_ALC5680_ADDR, &buf[0], 2, 1) < 2){
printf("alc5680_reg_read(): read register value fail\n");
ret = 1;
}else
*val = ((buf[1]&0xFF)<<24)|((buf[0]&0xFF)<<16);
buf[0] = 0x0004>>8;
buf[1] = 0x0004&0xff;
if(i2c_write(&alc5680_i2c, I2C_ALC5680_ADDR, &buf[0], 2, 1) != 2){
DBG_8195A("alc5680_reg_read(): write register addr fail\n");
ret = 1;
}
if(i2c_read(&alc5680_i2c, I2C_ALC5680_ADDR, &buf[0], 2, 1) < 2){
printf("alc5680_reg_read(): read register value fail\n");
ret = 1;
}else
*val |= ((buf[1]&0xFF)<<8)|(buf[0]&0xFF);
//alc5680_delay();
return ret;
}
u8 alc5680_reg_read_16(u32 reg, u16* val)
{
int tmp;
char *buf = (char*)&tmp;
u16 val1;
u8 ret = 0;
ret = alc5680_reg_write_16(0x0001,reg&0xffff);
if(ret != 0)
printf("error\r\n");
ret = alc5680_reg_write_16(0x0002,reg>>16);
if(ret != 0)
printf("error\r\n");
ret = alc5680_reg_write_16(0x0000,0x0002);
if(ret != 0)
printf("error\r\n");
buf[0] = 0x0003>>8;
buf[1] = 0x0003&0xff;
if(i2c_write(&alc5680_i2c, I2C_ALC5680_ADDR, &buf[0], 2, 1) != 2){
DBG_8195A("alc5680_reg_read(): write register addr fail\n");
ret = 1;
}
//alc5680_delay();
buf[0] = 0xaa;
buf[1] = 0xaa;
if(i2c_read(&alc5680_i2c, I2C_ALC5680_ADDR, &buf[0], 2, 1) < 2){
printf("alc5680_reg_read(): read register value fail\n");
ret = 1;
}else
*val = ((buf[0]&0xFF)<<8)|(buf[1]&0xFF);
//alc5680_delay();
return ret;
}
void alc5680_i2c_init(void)
{
i2c_init(&alc5680_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
i2c_frequency(&alc5680_i2c, I2C_BUS_CLK);
memset(&alc5680_info,0,sizeof(alc5680_fw));
}
void alc5680_erase()
{
unsigned short value = 0;
alc5680_reg_write_32(0x18009508,0x00000001);//erase command
while(1){
vTaskDelay(1000);
alc5680_reg_read_16(0x18009508,&value);
if((value&0x01)==0x00){
printf("Erase finish %d\r\n",value);
break;
}else{
printf("Erase ..... %x\r\n",value);
}
vTaskDelay(1000);
}
}
void alc5680_write_data_to_flash(const unsigned char *data_value,unsigned int len,unsigned int addr)
{
int i = 0;
unsigned int value = 0;
const unsigned char *ptr = data_value;
for(int i =0; i < len/4;i++){
value = (ptr[0])|(ptr[1]<<8)|(ptr[2]<<16)|(ptr[3]<<24);
alc5680_reg_write_32(addr+i*4,value);
ptr+=4;
}
}
int alc5680_get_version()
{
unsigned int value = 0;
alc5680_reg_read_32(0x7000A004,&value);
value = value>>24;
if(value == HELLO_BLUE_GENIE )
printf("VERSION:HELLO_BLUE_GENIE\r\n");
else if(value == ALEXA)
printf("VERSION:ALEXA\r\n");
else if(value == SESAMEE)
printf("VERSION:Zhima kaimen\r\n");
else if(value == BAIDU)
printf("VERSION:Xiao du xiao du\r\n");
else
printf("NON-DEFINE VERSION ADDR=0X7000A004 %x\r\n",value);
return value;
}
void set_alc5680_volume(unsigned char left,unsigned char right)
{
alc5680_reg_write_16b(0x1800C02C, left<<8|right);
}
void get_alc5680_volume(unsigned short *value)
{
alc5680_reg_read_16(0x1800C02C, value);
}
void alc5680_status()
{
unsigned int value = 0;
alc5680_reg_read_16(0x1800c1fe,&value);
printf("codec id = %x\r\n",value);
alc5680_reg_read_16(0x1800C0CA,&value);
printf("status state = %x\r\n",value);
alc5680_get_version();
}
/////////////////////////////////////////////////////
#if OLD_VERSION
void alc5680_get_info(unsigned char *buffer)
{
alc5680_info.size = buffer[0]<<24|buffer[1]<<16|buffer[2]<<8|buffer[3];
alc5680_info.checksum = buffer[4]<<24|buffer[5]<<16|buffer[6]<<8|buffer[7];
alc5680_info.version = buffer[8]<<24|buffer[9]<<16|buffer[10]<<8|buffer[11];
printf("codec size = %x checksum = %x version = %x\r\n",alc5680_info.size,alc5680_info.version);
}
void alc5680_handler_function(unsigned char *buffer,int len,unsigned int index)
{
unsigned char *buf_index = buffer;
unsigned int buf_len = len;
if(index == 1){
alc5680_get_info(buf_index);
buf_index += header_offset;
buf_len = buf_len - header_offset;
alc5680_info.alc_len_offset = 0;
alc5680_info.alc_len_index = 0;
alc5680_info.alc_addr_offset = ALC_FW_START_ADDR;
}
alc5680_write_data_to_flash(buf_index,buf_len,alc5680_info.alc_addr_offset);
alc5680_info.alc_addr_offset += buf_len;
alc5680_info.alc_len_offset += buf_len;
if(len != 512){
printf(" alc_addr_offset = %x alc_len_offset = %x \r\n",alc5680_info.alc_addr_offset,alc5680_info.alc_len_offset);
}
}
void alc5680_check_sum()
{
unsigned int alc_checksum = 0;
unsigned int i = 0, j = 0;
unsigned int value = 0;
unsigned int count = 0;
unsigned int percent = alc5680_info.size/100;
unsigned int percent_count = 0;
if(percent%4)
percent=percent+(4-(percent%4));
printf("checksum start\r\n");
for(i=ALC_FW_START_ADDR;i<ALC_FW_START_ADDR+alc5680_info.size;i+=4){
alc5680_reg_read_32(i,&value);
alc_checksum+=((value&0xff)+((value&0xff00)>>8)+((value&0xff0000)>>16)+((value&0xff000000)>>24));
count+=4;
if(count%percent == 0){
printf("%d%%\r", percent_count );
percent_count++;
}
}
if(alc_checksum != alc5680_info.checksum)
printf("Checksum error\r\n");
else
printf("Checksum successful\r\n");
printf("bin_checksum %x alc_checksum = %x count = %d\r\n",alc5680_info.checksum,alc_checksum,count);
}
#endif
#if NEW_VERSION
void alc5680_get_info(unsigned char *buffer)
{
alc5680_info.size = buffer[0]<<24|buffer[1]<<16|buffer[2]<<8|buffer[3];
alc5680_info.checksum = buffer[4]<<24|buffer[5]<<16|buffer[6]<<8|buffer[7];
alc5680_info.version = buffer[8]<<24|buffer[9]<<16|buffer[10]<<8|buffer[11];
printf("codec size = %x checksum = %x version = %x\r\n",alc5680_info.size,alc5680_info.checksum,alc5680_info.version);
}
void alc5680_handler_function(unsigned char *buffer,int len,unsigned int index)
{
unsigned char *buf_index = buffer;
unsigned int buf_len = len;
if(index == 1){
alc5680_get_info(buf_index);
buf_index += header_offset;
buf_len = buf_len - header_offset;
alc5680_info.alc_len_offset = 0;
alc5680_info.alc_addr_offset = ALC_FW_START_ADDR;
}
alc5680_write_data_to_flash(buf_index,buf_len,alc5680_info.alc_addr_offset);
alc5680_info.alc_addr_offset += buf_len;
alc5680_info.alc_len_offset += buf_len;
if(len != 512){
printf(" alc_addr_offset = %x alc_len_offset = %x \r\n",alc5680_info.alc_addr_offset,alc5680_info.alc_len_offset);
}
}
void alc5680_check_sum()
{
unsigned int alc_checksum = 0;
unsigned int i = 0, j = 0;
unsigned int value = 0;
unsigned int count = 0;
unsigned int percent = alc5680_info.size/100;
unsigned int percent_count = 0;
if(percent%4)
percent=percent+(4-(percent%4));
printf("checksum start\r\n");
for(i=ALC_FW_START_ADDR;i<ALC_FW_START_ADDR+alc5680_info.size;i+=4){
alc5680_reg_read_32(i,&value);
alc_checksum+=((value&0xff)+((value&0xff00)>>8)+((value&0xff0000)>>16)+((value&0xff000000)>>24));
count+=4;
if(count%percent == 0){
printf("%d%%\r", percent_count );
percent_count++;
}
}
if(alc_checksum != alc5680_info.checksum)
printf("Checksum error\r\n");
else
printf("Checksum successful\r\n");
printf("bin_checksum %x alc_checksum = %x count = %d\r\n",alc5680_info.checksum,alc_checksum,count);
}
#endif

22
component/common/drivers/i2s/alc5680.h Executable file
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#ifndef _ALC5680_H_
#define _ALC5680_H_
#define RT5680_DEVICE_ID 0x6385
void alc5680_status();
void alc5680_write_data_to_flash(const unsigned char *data_value,unsigned int len,unsigned int addr);
void alc5680_erase();
void alc5680_i2c_init(void);
u8 alc5680_reg_read_16(u32 reg, u16* val);
u8 alc5680_reg_read_32(u32 reg, u32* val);
u8 alc5680_reg_write_32(u32 reg, u32 val);
u8 alc5680_reg_write_16b(u32 reg, u16 val);
void alc5680_get_info(unsigned char *buffer);
void alc5680_handler_function(unsigned char *buffer,int len,unsigned int index);
void alc5680_check_sum();
int alc5680_get_version();
void set_alc5680_volume(unsigned char left,unsigned char right);
void get_alc5680_volume(unsigned short *value);//high byte is left and low byte is high
#endif

200
component/common/drivers/i2s/sgtl5000.c Executable file
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#include "sgtl5000.h"
#include "PinNames.h"
#include "basic_types.h"
#include "i2c_api.h"
#include "i2c_ex_api.h"
#include "pinmap.h"
#include "wait_api.h"
//#define I2C_MTR_SDA PC_4//PB_3
//#define I2C_MTR_SCL PC_5//PB_2
#define I2C_MTR_SDA PB_3
#define I2C_MTR_SCL PB_2
#define I2C_BUS_CLK 100000 //100K HZ
i2c_t sgtl5000_i2c;
uint16_t ana_ctrl;
uint8_t i2c_addr;
bool muted;
u8 sgtl5000_reg_write(u16 reg, u16 val)
{
int length = 0;
char buf[4];
buf[0] = (char)(reg >> 8);
buf[1] = (char)(reg&0xff);
buf[2] = (char)(val>>8);
buf[3] = (char)(val&0xff);
length = i2c_write(&sgtl5000_i2c, i2c_addr, &buf[0], 4, 1);
return (length==4)?0:1;
}
u8 sgtl5000_reg_read(u16 reg, u16* val)
{
int tmp;
char *buf = (char*)&tmp;
u8 ret = 0;
buf[0] = (char)(reg >> 8);
buf[1] = (char)(reg&0xff);
if(i2c_write(&sgtl5000_i2c, i2c_addr, &buf[0], 2, 1) != 2){
DBG_8195A("sgtl5000_reg_read(): write register addr fail\n");
ret = 1;
}
buf[0] = 0xaa;
buf[1] = 0xaa;
if(i2c_read(&sgtl5000_i2c, i2c_addr, &buf[0], 2, 1) < 2){
DBG_8195A("sgtl5000_reg_read(): read register value fail\n");
ret = 1;
}else
*val = ((buf[0]&0xFF)<<8)|(buf[1]&0xFF);
return ret;
}
u16 sgtl5000_reg_modify(u16 reg, u16 val, u16 iMask)
{
u16 val1;
sgtl5000_reg_read(reg, &val1);
u16 val2 = (val1 &(~iMask))|val;
if(!sgtl5000_reg_write(reg, val2)) return 0;
return val2;
}
void sgtl5000_setAddress(uint8_t level)
{
if (level == 0) {
i2c_addr = SGTL5000_I2C_ADDR_CS_LOW;
} else {
i2c_addr = SGTL5000_I2C_ADDR_CS_HIGH;
}
}
void sgtl5000_i2c_master_txc_callback(void *userdata)
{
}
void sgtl5000_i2c_master_rxc_callback(void *userdata)
{
}
void sgtl5000_i2c_master_err_callback(void *userdata)
{
//DBG_8195A("I2C Ack address:%d", (sgtl5000_i2c.I2Cx->IC_TAR)& BIT_CTRL_IC_TAR);//sgtl5000_i2c.SalI2CHndPriv.SalI2CHndPriv.I2CAckAddr);
//DBG_8195A("I2C Error:%x\n", sgtl5000_i2c.I2Cx->IC_TX_ABRT_SOURCE);//sgtl5000_i2c.SalI2CHndPriv.SalI2CHndPriv.ErrType);
}
void sgtl5000_reg_dump(void);
u8 sgtl5000_enable(void){
u16 temp = 0;
u8 ret = 0;
muted = 1;
memset(&sgtl5000_i2c, 0x00, sizeof(sgtl5000_i2c));
i2c_init(&sgtl5000_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
i2c_frequency(&sgtl5000_i2c, I2C_BUS_CLK);
i2c_set_user_callback(&sgtl5000_i2c, I2C_ERR_OCCURRED, sgtl5000_i2c_master_err_callback);
// set I2C address
sgtl5000_setAddress(0); // CTRL_ADR0_CS is tied to GND
wait_ms(5);
ret = sgtl5000_reg_read(CHIP_ID, &temp);
if(ret == 0)
DBG_8195A("SGTL5000 CHIP ID:0x%04X\n", temp);
else
DBG_8195A("Get SGTL5000 CHIP ID fail\n");
sgtl5000_reg_write(CHIP_ANA_POWER, 0x4060); // VDDD is externally driven with 1.8V
sgtl5000_reg_write(CHIP_LINREG_CTRL, 0x006C); // VDDA & VDDIO both over 3.1V
sgtl5000_reg_write(CHIP_REF_CTRL, 0x01F2); // VAG=1.575, normal ramp, +12.5% bias current
sgtl5000_reg_write(CHIP_LINE_OUT_CTRL, 0x0F22); // LO_VAGCNTRL=1.65V, OUT_CURRENT=0.54mA
sgtl5000_reg_write(CHIP_SHORT_CTRL, 0x4446); // allow up to 125mA
sgtl5000_reg_write(CHIP_ANA_CTRL, 0x0137); // enable zero cross detectors
sgtl5000_reg_write(CHIP_ANA_POWER, 0x40FF); // power up: lineout, hp, adc, dac
sgtl5000_reg_write(CHIP_DIG_POWER, 0x0073); // power up all digital stuff
wait_ms(400);
sgtl5000_reg_write(CHIP_LINE_OUT_VOL, 0x1D1D); // default approx 1.3 volts peak-to-peak
sgtl5000_reg_write(CHIP_CLK_CTRL, 0x0004); // 44.1 kHz, 256*Fs
sgtl5000_reg_write(CHIP_I2S_CTRL, 0x0130); // SCLK=32*Fs, 16bit, I2S format
// default signal routing is ok?
sgtl5000_reg_write(CHIP_SSS_CTRL, 0x0010); // ADC->I2S, I2S->DAC
sgtl5000_reg_write(CHIP_ADCDAC_CTRL, 0x0000); // disable dac mute
sgtl5000_reg_write(CHIP_DAC_VOL, 0x3C3C); // digital gain, 0dB
sgtl5000_reg_write(CHIP_ANA_HP_CTRL, 0x7F7F); // set volume (lowest level)
sgtl5000_reg_write(CHIP_ANA_CTRL, 0x0036); // enable zero cross detectors
//semi_automated = true;
//sgtl5000_reg_dump();
return 0;
}
bool sgtl5000_muteHeadphone(void) {
return sgtl5000_reg_write(CHIP_ANA_CTRL, ana_ctrl | (1<<4));
}
bool sgtl5000_unmuteHeadphone(void) {
return sgtl5000_reg_write(CHIP_ANA_CTRL, ana_ctrl & ~(1<<4));
}
bool sgtl5000_muteLineout(void) {
return sgtl5000_reg_write(CHIP_ANA_CTRL, ana_ctrl | (1<<8));
}
bool sgtl5000_unmuteLineout(void) {
return sgtl5000_reg_write(CHIP_ANA_CTRL, ana_ctrl & ~(1<<8));
}
u8 sgtl5000_setVolume(float val){
int volumeInt = 0;
volumeInt = (int)(val * 129 + 0.499);
if (volumeInt == 0) {
muted = 1;
sgtl5000_reg_write(CHIP_ANA_HP_CTRL, 0x7F7F);
return sgtl5000_muteHeadphone();
} else if (volumeInt > 0x80) {
volumeInt = 0;
} else {
volumeInt = 0x80 - volumeInt;
}
if (muted) {
muted = 0;
sgtl5000_unmuteHeadphone();
}
volumeInt = volumeInt | (volumeInt << 8);
return sgtl5000_reg_write(CHIP_ANA_HP_CTRL, volumeInt); // set volume
}
void sgtl5000_reg_dump(void)
{
u16 reg;
u8 ret = 0;
u16 value;
DBG_8195A("SGTL5000 codec reg dump\n\r");
DBG_8195A("------------------------\n\r");
for(reg = 0; reg <= 0x013A; ){
ret = sgtl5000_reg_read(reg, &value);
if(ret == 0)
DBG_8195A("0x%04X : 0x%04X\n\r", reg, value);
reg += 0x02;
}
DBG_8195A("------------------------\n\r");
}

479
component/common/drivers/i2s/sgtl5000.h Executable file
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#ifndef _SGTL5000_H_
#define _SGTL5000_H_
#define CHIP_ID 0x0000
// 15:8 PARTID 0xA0 - 8 bit identifier for SGTL5000
// 7:0 REVID 0x00 - revision number for SGTL5000.
#define CHIP_DIG_POWER 0x0002
// 6 ADC_POWERUP 1=Enable, 0=disable the ADC block, both digital & analog,
// 5 DAC_POWERUP 1=Enable, 0=disable the DAC block, both analog and digital
// 4 DAP_POWERUP 1=Enable, 0=disable the DAP block
// 1 I2S_OUT_POWERUP 1=Enable, 0=disable the I2S data output
// 0 I2S_IN_POWERUP 1=Enable, 0=disable the I2S data input
#define CHIP_CLK_CTRL 0x0004
// 5:4 RATE_MODE Sets the sample rate mode. MCLK_FREQ is still specified
// relative to the rate in SYS_FS
// 0x0 = SYS_FS specifies the rate
// 0x1 = Rate is 1/2 of the SYS_FS rate
// 0x2 = Rate is 1/4 of the SYS_FS rate
// 0x3 = Rate is 1/6 of the SYS_FS rate
// 3:2 SYS_FS Sets the internal system sample rate (default=2)
// 0x0 = 32 kHz
// 0x1 = 44.1 kHz
// 0x2 = 48 kHz
// 0x3 = 96 kHz
// 1:0 MCLK_FREQ Identifies incoming SYS_MCLK frequency and if the PLL should be used
// 0x0 = 256*Fs
// 0x1 = 384*Fs
// 0x2 = 512*Fs
// 0x3 = Use PLL
// The 0x3 (Use PLL) setting must be used if the SYS_MCLK is not
// a standard multiple of Fs (256, 384, or 512). This setting can
// also be used if SYS_MCLK is a standard multiple of Fs.
// Before this field is set to 0x3 (Use PLL), the PLL must be
// powered up by setting CHIP_ANA_POWER->PLL_POWERUP and
// CHIP_ANA_POWER->VCOAMP_POWERUP. Also, the PLL dividers must
// be calculated based on the external MCLK rate and
// CHIP_PLL_CTRL register must be set (see CHIP_PLL_CTRL register
// description details on how to calculate the divisors).
#define CHIP_I2S_CTRL 0x0006
// 8 SCLKFREQ Sets frequency of I2S_SCLK when in master mode (MS=1). When in slave
// mode (MS=0), this field must be set appropriately to match SCLK input
// rate.
// 0x0 = 64Fs
// 0x1 = 32Fs - Not supported for RJ mode (I2S_MODE = 1)
// 7 MS Configures master or slave of I2S_LRCLK and I2S_SCLK.
// 0x0 = Slave: I2S_LRCLK an I2S_SCLK are inputs
// 0x1 = Master: I2S_LRCLK and I2S_SCLK are outputs
// NOTE: If the PLL is used (CHIP_CLK_CTRL->MCLK_FREQ==0x3),
// the SGTL5000 must be a master of the I2S port (MS==1)
// 6 SCLK_INV Sets the edge that data (input and output) is clocked in on for I2S_SCLK
// 0x0 = data is valid on rising edge of I2S_SCLK
// 0x1 = data is valid on falling edge of I2S_SCLK
// 5:4 DLEN I2S data length (default=1)
// 0x0 = 32 bits (only valid when SCLKFREQ=0),
// not valid for Right Justified Mode
// 0x1 = 24 bits (only valid when SCLKFREQ=0)
// 0x2 = 20 bits
// 0x3 = 16 bits
// 3:2 I2S_MODE Sets the mode for the I2S port
// 0x0 = I2S mode or Left Justified (Use LRALIGN to select)
// 0x1 = Right Justified Mode
// 0x2 = PCM Format A/B
// 0x3 = RESERVED
// 1 LRALIGN I2S_LRCLK Alignment to data word. Not used for Right Justified mode
// 0x0 = Data word starts 1 I2S_SCLK delay after I2S_LRCLK
// transition (I2S format, PCM format A)
// 0x1 = Data word starts after I2S_LRCLK transition (left
// justified format, PCM format B)
// 0 LRPOL I2S_LRCLK Polarity when data is presented.
// 0x0 = I2S_LRCLK = 0 - Left, 1 - Right
// 1x0 = I2S_LRCLK = 0 - Right, 1 - Left
// The left subframe should be presented first regardless of
// the setting of LRPOL.
#define CHIP_SSS_CTRL 0x000A
// 14 DAP_MIX_LRSWAP DAP Mixer Input Swap
// 0x0 = Normal Operation
// 0x1 = Left and Right channels for the DAP MIXER Input are swapped.
// 13 DAP_LRSWAP DAP Mixer Input Swap
// 0x0 = Normal Operation
// 0x1 = Left and Right channels for the DAP Input are swapped
// 12 DAC_LRSWAP DAC Input Swap
// 0x0 = Normal Operation
// 0x1 = Left and Right channels for the DAC are swapped
// 10 I2S_LRSWAP I2S_DOUT Swap
// 0x0 = Normal Operation
// 0x1 = Left and Right channels for the I2S_DOUT are swapped
// 9:8 DAP_MIX_SELECT Select data source for DAP mixer
// 0x0 = ADC
// 0x1 = I2S_IN
// 0x2 = Reserved
// 0x3 = Reserved
// 7:6 DAP_SELECT Select data source for DAP
// 0x0 = ADC
// 0x1 = I2S_IN
// 0x2 = Reserved
// 0x3 = Reserved
// 5:4 DAC_SELECT Select data source for DAC (default=1)
// 0x0 = ADC
// 0x1 = I2S_IN
// 0x2 = Reserved
// 0x3 = DAP
// 1:0 I2S_SELECT Select data source for I2S_DOUT
// 0x0 = ADC
// 0x1 = I2S_IN
// 0x2 = Reserved
// 0x3 = DAP
#define CHIP_ADCDAC_CTRL 0x000E
// 13 VOL_BUSY_DAC_RIGHT Volume Busy DAC Right
// 0x0 = Ready
// 0x1 = Busy - This indicates the channel has not reached its
// programmed volume/mute level
// 12 VOL_BUSY_DAC_LEFT Volume Busy DAC Left
// 0x0 = Ready
// 0x1 = Busy - This indicates the channel has not reached its
// programmed volume/mute level
// 9 VOL_RAMP_EN Volume Ramp Enable (default=1)
// 0x0 = Disables volume ramp. New volume settings take immediate
// effect without a ramp
// 0x1 = Enables volume ramp
// This field affects DAC_VOL. The volume ramp effects both
// volume settings and mute When set to 1 a soft mute is enabled.
// 8 VOL_EXPO_RAMP Exponential Volume Ramp Enable
// 0x0 = Linear ramp over top 4 volume octaves
// 0x1 = Exponential ramp over full volume range
// This bit only takes effect if VOL_RAMP_EN is 1.
// 3 DAC_MUTE_RIGHT DAC Right Mute (default=1)
// 0x0 = Unmute
// 0x1 = Muted
// If VOL_RAMP_EN = 1, this is a soft mute.
// 2 DAC_MUTE_LEFT DAC Left Mute (default=1)
// 0x0 = Unmute
// 0x1 = Muted
// If VOL_RAMP_EN = 1, this is a soft mute.
// 1 ADC_HPF_FREEZE ADC High Pass Filter Freeze
// 0x0 = Normal operation
// 0x1 = Freeze the ADC high-pass filter offset register. The
// offset continues to be subtracted from the ADC data stream.
// 0 ADC_HPF_BYPASS ADC High Pass Filter Bypass
// 0x0 = Normal operation
// 0x1 = Bypassed and offset not updated
#define CHIP_DAC_VOL 0x0010
// 15:8 DAC_VOL_RIGHT DAC Right Channel Volume. Set the Right channel DAC volume
// with 0.5017 dB steps from 0 to -90 dB
// 0x3B and less = Reserved
// 0x3C = 0 dB
// 0x3D = -0.5 dB
// 0xF0 = -90 dB
// 0xFC and greater = Muted
// If VOL_RAMP_EN = 1, there is an automatic ramp to the
// new volume setting.
// 7:0 DAC_VOL_LEFT DAC Left Channel Volume. Set the Left channel DAC volume
// with 0.5017 dB steps from 0 to -90 dB
// 0x3B and less = Reserved
// 0x3C = 0 dB
// 0x3D = -0.5 dB
// 0xF0 = -90 dB
// 0xFC and greater = Muted
// If VOL_RAMP_EN = 1, there is an automatic ramp to the
// new volume setting.
#define CHIP_PAD_STRENGTH 0x0014
// 9:8 I2S_LRCLK I2S LRCLK Pad Drive Strength (default=1)
// Sets drive strength for output pads per the table below.
// VDDIO 1.8 V 2.5 V 3.3 V
// 0x0 = Disable
// 0x1 = 1.66 mA 2.87 mA 4.02 mA
// 0x2 = 3.33 mA 5.74 mA 8.03 mA
// 0x3 = 4.99 mA 8.61 mA 12.05 mA
// 7:6 I2S_SCLK I2S SCLK Pad Drive Strength (default=1)
// 5:4 I2S_DOUT I2S DOUT Pad Drive Strength (default=1)
// 3:2 CTRL_DATA I2C DATA Pad Drive Strength (default=3)
// 1:0 CTRL_CLK I2C CLK Pad Drive Strength (default=3)
// (all use same table as I2S_LRCLK)
#define CHIP_ANA_ADC_CTRL 0x0020
// 8 ADC_VOL_M6DB ADC Volume Range Reduction
// This bit shifts both right and left analog ADC volume
// range down by 6.0 dB.
// 0x0 = No change in ADC range
// 0x1 = ADC range reduced by 6.0 dB
// 7:4 ADC_VOL_RIGHT ADC Right Channel Volume
// Right channel analog ADC volume control in 1.5 dB steps.
// 0x0 = 0 dB
// 0x1 = +1.5 dB
// ...
// 0xF = +22.5 dB
// This range is -6.0 dB to +16.5 dB if ADC_VOL_M6DB is set to 1.
// 3:0 ADC_VOL_LEFT ADC Left Channel Volume
// (same scale as ADC_VOL_RIGHT)
#define CHIP_ANA_HP_CTRL 0x0022
// 14:8 HP_VOL_RIGHT Headphone Right Channel Volume (default 0x18)
// Right channel headphone volume control with 0.5 dB steps.
// 0x00 = +12 dB
// 0x01 = +11.5 dB
// 0x18 = 0 dB
// ...
// 0x7F = -51.5 dB
// 6:0 HP_VOL_LEFT Headphone Left Channel Volume (default 0x18)
// (same scale as HP_VOL_RIGHT)
#define CHIP_ANA_CTRL 0x0024
// 8 MUTE_LO LINEOUT Mute, 0 = Unmute, 1 = Mute (default 1)
// 6 SELECT_HP Select the headphone input, 0 = DAC, 1 = LINEIN
// 5 EN_ZCD_HP Enable the headphone zero cross detector (ZCD)
// 0x0 = HP ZCD disabled
// 0x1 = HP ZCD enabled
// 4 MUTE_HP Mute the headphone outputs, 0 = Unmute, 1 = Mute (default)
// 2 SELECT_ADC Select the ADC input, 0 = Microphone, 1 = LINEIN
// 1 EN_ZCD_ADC Enable the ADC analog zero cross detector (ZCD)
// 0x0 = ADC ZCD disabled
// 0x1 = ADC ZCD enabled
// 0 MUTE_ADC Mute the ADC analog volume, 0 = Unmute, 1 = Mute (default)
#define CHIP_LINREG_CTRL 0x0026
// 6 VDDC_MAN_ASSN Determines chargepump source when VDDC_ASSN_OVRD is set.
// 0x0 = VDDA
// 0x1 = VDDIO
// 5 VDDC_ASSN_OVRD Charge pump Source Assignment Override
// 0x0 = Charge pump source is automatically assigned based
// on higher of VDDA and VDDIO
// 0x1 = the source of charge pump is manually assigned by
// VDDC_MAN_ASSN If VDDIO and VDDA are both the same
// and greater than 3.1 V, VDDC_ASSN_OVRD and
// VDDC_MAN_ASSN should be used to manually assign
// VDDIO as the source for charge pump.
// 3:0 D_PROGRAMMING Sets the VDDD linear regulator output voltage in 50 mV steps.
// Must clear the LINREG_SIMPLE_POWERUP and STARTUP_POWERUP bits
// in the 0x0030 (CHIP_ANA_POWER) register after power-up, for
// this setting to produce the proper VDDD voltage.
// 0x0 = 1.60
// 0xF = 0.85
#define CHIP_REF_CTRL 0x0028 // bandgap reference bias voltage and currents
// 8:4 VAG_VAL Analog Ground Voltage Control
// These bits control the analog ground voltage in 25 mV steps.
// This should usually be set to VDDA/2 or lower for best
// performance (maximum output swing at minimum THD). This VAG
// reference is also used for the DAC and ADC voltage reference.
// So changing this voltage scales the output swing of the DAC
// and the output signal of the ADC.
// 0x00 = 0.800 V
// 0x1F = 1.575 V
// 3:1 BIAS_CTRL Bias control
// These bits adjust the bias currents for all of the analog
// blocks. By lowering the bias current a lower quiescent power
// is achieved. It should be noted that this mode can affect
// performance by 3-4 dB.
// 0x0 = Nominal
// 0x1-0x3=+12.5%
// 0x4=-12.5%
// 0x5=-25%
// 0x6=-37.5%
// 0x7=-50%
// 0 SMALL_POP VAG Ramp Control
// Setting this bit slows down the VAG ramp from ~200 to ~400 ms
// to reduce the startup pop, but increases the turn on/off time.
// 0x0 = Normal VAG ramp
// 0x1 = Slow down VAG ramp
#define CHIP_MIC_CTRL 0x002A // microphone gain & internal microphone bias
// 9:8 BIAS_RESISTOR MIC Bias Output Impedance Adjustment
// Controls an adjustable output impedance for the microphone bias.
// If this is set to zero the micbias block is powered off and
// the output is highZ.
// 0x0 = Powered off
// 0x1 = 2.0 kohm
// 0x2 = 4.0 kohm
// 0x3 = 8.0 kohm
// 6:4 BIAS_VOLT MIC Bias Voltage Adjustment
// Controls an adjustable bias voltage for the microphone bias
// amp in 250 mV steps. This bias voltage setting should be no
// more than VDDA-200 mV for adequate power supply rejection.
// 0x0 = 1.25 V
// ...
// 0x7 = 3.00 V
// 1:0 GAIN MIC Amplifier Gain
// Sets the microphone amplifier gain. At 0 dB setting the THD
// can be slightly higher than other paths- typically around
// ~65 dB. At other gain settings the THD are better.
// 0x0 = 0 dB
// 0x1 = +20 dB
// 0x2 = +30 dB
// 0x3 = +40 dB
#define CHIP_LINE_OUT_CTRL 0x002C
// 11:8 OUT_CURRENT Controls the output bias current for the LINEOUT amplifiers. The
// nominal recommended setting for a 10 kohm load with 1.0 nF load cap
// is 0x3. There are only 5 valid settings.
// 0x0=0.18 mA
// 0x1=0.27 mA
// 0x3=0.36 mA
// 0x7=0.45 mA
// 0xF=0.54 mA
// 5:0 LO_VAGCNTRL LINEOUT Amplifier Analog Ground Voltage
// Controls the analog ground voltage for the LINEOUT amplifiers
// in 25 mV steps. This should usually be set to VDDIO/2.
// 0x00 = 0.800 V
// ...
// 0x1F = 1.575 V
// ...
// 0x23 = 1.675 V
// 0x24-0x3F are invalid
#define CHIP_LINE_OUT_VOL 0x002E
// 12:8 LO_VOL_RIGHT LINEOUT Right Channel Volume (default=4)
// Controls the right channel LINEOUT volume in 0.5 dB steps.
// Higher codes have more attenuation.
// 4:0 LO_VOL_LEFT LINEOUT Left Channel Output Level (default=4)
// Used to normalize the output level of the left line output
// to full scale based on the values used to set
// LINE_OUT_CTRL->LO_VAGCNTRL and CHIP_REF_CTRL->VAG_VAL.
// In general this field should be set to:
// 40*log((VAG_VAL)/(LO_VAGCNTRL)) + 15
// Suggested values based on typical VDDIO and VDDA voltages.
// VDDA VAG_VAL VDDIO LO_VAGCNTRL LO_VOL_*
// 1.8 V 0.9 3.3 V 1.55 0x06
// 1.8 V 0.9 1.8 V 0.9 0x0F
// 3.3 V 1.55 1.8 V 0.9 0x19
// 3.3 V 1.55 3.3 V 1.55 0x0F
// After setting to the nominal voltage, this field can be used
// to adjust the output level in +/-0.5 dB increments by using
// values higher or lower than the nominal setting.
#define CHIP_ANA_POWER 0x0030 // power down controls for the analog blocks.
// The only other power-down controls are BIAS_RESISTOR in the MIC_CTRL register
// and the EN_ZCD control bits in ANA_CTRL.
// 14 DAC_MONO While DAC_POWERUP is set, this allows the DAC to be put into left only
// mono operation for power savings. 0=mono, 1=stereo (default)
// 13 LINREG_SIMPLE_POWERUP Power up the simple (low power) digital supply regulator.
// After reset, this bit can be cleared IF VDDD is driven
// externally OR the primary digital linreg is enabled with
// LINREG_D_POWERUP
// 12 STARTUP_POWERUP Power up the circuitry needed during the power up ramp and reset.
// After reset this bit can be cleared if VDDD is coming from
// an external source.
// 11 VDDC_CHRGPMP_POWERUP Power up the VDDC charge pump block. If neither VDDA or VDDIO
// is 3.0 V or larger this bit should be cleared before analog
// blocks are powered up.
// 10 PLL_POWERUP PLL Power Up, 0 = Power down, 1 = Power up
// When cleared, the PLL is turned off. This must be set before
// CHIP_CLK_CTRL->MCLK_FREQ is programmed to 0x3. The
// CHIP_PLL_CTRL register must be configured correctly before
// setting this bit.
// 9 LINREG_D_POWERUP Power up the primary VDDD linear regulator, 0 = Power down, 1 = Power up
// 8 VCOAMP_POWERUP Power up the PLL VCO amplifier, 0 = Power down, 1 = Power up
// 7 VAG_POWERUP Power up the VAG reference buffer.
// Setting this bit starts the power up ramp for the headphone
// and LINEOUT. The headphone (and/or LINEOUT) powerup should
// be set BEFORE clearing this bit. When this bit is cleared
// the power-down ramp is started. The headphone (and/or LINEOUT)
// powerup should stay set until the VAG is fully ramped down
// (200 to 400 ms after clearing this bit).
// 0x0 = Power down, 0x1 = Power up
// 6 ADC_MONO While ADC_POWERUP is set, this allows the ADC to be put into left only
// mono operation for power savings. This mode is useful when
// only using the microphone input.
// 0x0 = Mono (left only), 0x1 = Stereo
// 5 REFTOP_POWERUP Power up the reference bias currents
// 0x0 = Power down, 0x1 = Power up
// This bit can be cleared when the part is a sleep state
// to minimize analog power.
// 4 HEADPHONE_POWERUP Power up the headphone amplifiers
// 0x0 = Power down, 0x1 = Power up
// 3 DAC_POWERUP Power up the DACs
// 0x0 = Power down, 0x1 = Power up
// 2 CAPLESS_HEADPHONE_POWERUP Power up the capless headphone mode
// 0x0 = Power down, 0x1 = Power up
// 1 ADC_POWERUP Power up the ADCs
// 0x0 = Power down, 0x1 = Power up
// 0 LINEOUT_POWERUP Power up the LINEOUT amplifiers
// 0x0 = Power down, 0x1 = Power up
#define CHIP_PLL_CTRL 0x0032
// 15:11 INT_DIVISOR
// 10:0 FRAC_DIVISOR
#define CHIP_CLK_TOP_CTRL 0x0034
// 11 ENABLE_INT_OSC Setting this bit enables an internal oscillator to be used for the
// zero cross detectors, the short detect recovery, and the
// charge pump. This allows the I2S clock to be shut off while
// still operating an analog signal path. This bit can be kept
// on when the I2S clock is enabled, but the I2S clock is more
// accurate so it is preferred to clear this bit when I2S is present.
// 3 INPUT_FREQ_DIV2 SYS_MCLK divider before PLL input
// 0x0 = pass through
// 0x1 = SYS_MCLK is divided by 2 before entering PLL
// This must be set when the input clock is above 17 Mhz. This
// has no effect when the PLL is powered down.
#define CHIP_ANA_STATUS 0x0036
// 9 LRSHORT_STS This bit is high whenever a short is detected on the left or right
// channel headphone drivers.
// 8 CSHORT_STS This bit is high whenever a short is detected on the capless headphone
// common/center channel driver.
// 4 PLL_IS_LOCKED This bit goes high after the PLL is locked.
#define CHIP_ANA_TEST1 0x0038 // intended only for debug.
#define CHIP_ANA_TEST2 0x003A // intended only for debug.
#define CHIP_SHORT_CTRL 0x003C
// 14:12 LVLADJR Right channel headphone short detector in 25 mA steps.
// 0x3=25 mA
// 0x2=50 mA
// 0x1=75 mA
// 0x0=100 mA
// 0x4=125 mA
// 0x5=150 mA
// 0x6=175 mA
// 0x7=200 mA
// This trip point can vary by ~30% over process so leave plenty
// of guard band to avoid false trips. This short detect trip
// point is also effected by the bias current adjustments made
// by CHIP_REF_CTRL->BIAS_CTRL and by CHIP_ANA_TEST1->HP_IALL_ADJ.
// 10:8 LVLADJL Left channel headphone short detector in 25 mA steps.
// (same scale as LVLADJR)
// 6:4 LVLADJC Capless headphone center channel short detector in 50 mA steps.
// 0x3=50 mA
// 0x2=100 mA
// 0x1=150 mA
// 0x0=200 mA
// 0x4=250 mA
// 0x5=300 mA
// 0x6=350 mA
// 0x7=400 mA
// 3:2 MODE_LR Behavior of left/right short detection
// 0x0 = Disable short detector, reset short detect latch,
// software view non-latched short signal
// 0x1 = Enable short detector and reset the latch at timeout
// (every ~50 ms)
// 0x2 = This mode is not used/invalid
// 0x3 = Enable short detector with only manual reset (have
// to return to 0x0 to reset the latch)
// 1:0 MODE_CM Behavior of capless headphone central short detection
// (same settings as MODE_LR)
#define DAP_CONTROL 0x0100
#define DAP_PEQ 0x0102
#define DAP_BASS_ENHANCE 0x0104
#define DAP_BASS_ENHANCE_CTRL 0x0106
#define DAP_AUDIO_EQ 0x0108
#define DAP_SGTL_SURROUND 0x010A
#define DAP_FILTER_COEF_ACCESS 0x010C
#define DAP_COEF_WR_B0_MSB 0x010E
#define DAP_COEF_WR_B0_LSB 0x0110
#define DAP_AUDIO_EQ_BASS_BAND0 0x0116 // 115 Hz
#define DAP_AUDIO_EQ_BAND1 0x0118 // 330 Hz
#define DAP_AUDIO_EQ_BAND2 0x011A // 990 Hz
#define DAP_AUDIO_EQ_BAND3 0x011C // 3000 Hz
#define DAP_AUDIO_EQ_TREBLE_BAND4 0x011E // 9900 Hz
#define DAP_MAIN_CHAN 0x0120
#define DAP_MIX_CHAN 0x0122
#define DAP_AVC_CTRL 0x0124
#define DAP_AVC_THRESHOLD 0x0126
#define DAP_AVC_ATTACK 0x0128
#define DAP_AVC_DECAY 0x012A
#define DAP_COEF_WR_B1_MSB 0x012C
#define DAP_COEF_WR_B1_LSB 0x012E
#define DAP_COEF_WR_B2_MSB 0x0130
#define DAP_COEF_WR_B2_LSB 0x0132
#define DAP_COEF_WR_A1_MSB 0x0134
#define DAP_COEF_WR_A1_LSB 0x0136
#define DAP_COEF_WR_A2_MSB 0x0138
#define DAP_COEF_WR_A2_LSB 0x013A
#define SGTL5000_I2C_ADDR_CS_LOW 0x0A // CTRL_ADR0_CS pin low (normal configuration)
#define SGTL5000_I2C_ADDR_CS_HIGH 0x2A // CTRL_ADR0_CS pin high
unsigned char sgtl5000_enable(void);
unsigned char sgtl5000_setVolume(float val);
#endif

39
component/common/drivers/sdio/realtek/sdio_host/inc/sd.h Executable file
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#ifndef _SD_DRIVER_H
#define _SD_DRIVER_H
#include "basic_types.h"
#define CONFIG_SD_SDIO 1
#define CONFIG_SD_SPI 0
typedef enum
{
SD_OK = 0,
SD_PROTECTED,
SD_NODISK,
SD_INITERR,
SD_ERROR,
}SD_RESULT;
typedef enum{
SD_CLK_LOW, // 10.4MHz
SD_CLK_MID, // 20.8MHz
SD_CLK_HIGH, // 41.6MHz
SD_CLK_RSV, // 5.2MHz
}SD_CLK;
SD_RESULT SD_WaitReady(void);
SD_RESULT SD_Init(void);
SD_RESULT SD_DeInit(void);
SD_RESULT SD_SetCLK(SD_CLK CLK);
SD_RESULT SD_Status(void);
SD_RESULT SD_GetCID(u8 *cid_data); // read sd card CID
SD_RESULT SD_GetCSD(u8 *csd_data); // read sd card CSD
SD_RESULT SD_GetCapacity(u32* sector_count); // read sd card Capacity
SD_RESULT SD_ReadBlocks(u32 sector,u8 *data,u32 count); //read multi sector
SD_RESULT SD_WriteBlocks(u32 sector,const u8 *data,u32 count); //write multi sector
#endif

41
component/common/drivers/sdio/realtek/sdio_host/inc/sdio_host.h Executable file
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#ifndef _SDIO_HOST_H
#define _SDIO_HOST_H
#include "basic_types.h"
#include "rtl8195a_sdio_host.h"
#define SDIO_HOST_BYTES_ALINGMENT 4
typedef enum{
SDIO_INIT_NONE = -1,
SDIO_INIT_FAIL = 0,
SDIO_INIT_OK = 1,
SDIO_SD_NONE = 2,
SDIO_SD_OK = 3,
}_sdio_init_s;
typedef void (*sdio_sd_irq_handler)(void* param);
s8 sdio_init_host(void); // init sdio host interface
void sdio_deinit_host(void);
s8 sdio_sd_init(void); // init sd card through sdio
void sdio_sd_deinit(void); //de-init sd card through sdio
s8 sdio_sd_status(void);
u32 sdio_sd_getCapacity(void);
s8 sdio_sd_getProtection(void);
s8 sdio_sd_setProtection(bool protection);
s8 sdio_sd_getCSD(u8* CSD);
s8 sdio_sd_isReady();
s8 sdio_sd_setClock(SD_CLK_FREQUENCY SDCLK);
s8 sdio_read_blocks(u32 sector, u8 *buffer, u32 count);
s8 sdio_write_blocks(u32 sector, const u8 *buffer, u32 count);
s8 sdio_sd_hook_xfer_cmp_cb(IN sdio_sd_irq_handler CallbackFun,IN VOID *param);
s8 sdio_sd_hook_remove_cb(IN sdio_sd_irq_handler CallbackFun,IN VOID *param);
s8 sdio_sd_hook_insert_cb(IN sdio_sd_irq_handler CallbackFun,IN VOID *param);
s8 sdio_sd_hook_xfer_err_cb(IN sdio_sd_irq_handler CallbackFun,IN VOID *param);
#endif

183
component/common/drivers/usb_class/device/class/msc/inc/usbd_msc.h Executable file
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#ifndef USBD_MSC_H
#define USBD_MSC_H
#include "usb.h"
#include "usb_gadget.h"
#include "core/inc/usb_composite.h"
#include "msc/inc/usbd_msc_config.h"
/* config usb msc device debug inforation */
#define USBD_MSC_DEBUG 0
#if USBD_MSC_DEBUG
#define USBD_PRINTF(fmt, args...) DBG_8195A("\n\r%s: " fmt, __FUNCTION__, ## args)
#define USBD_ERROR(fmt, args...) DBG_8195A("\n\r%s: " fmt, __FUNCTION__, ## args)
#define USBD_WARN(fmt, args...) DBG_8195A("\n\r%s: " fmt, __FUNCTION__, ## args)
#define FUN_ENTER DBG_8195A("\n\r%s ==>\n", __func__)
#define FUN_EXIT DBG_8195A("\n\r%s <==\n", __func__)
#define FUN_TRACE DBG_8195A("\n\r%s:%d \n", __func__, __LINE__)
#else
#define USBD_PRINTF(fmt, args...)
#define USBD_ERROR(fmt, args...) DBG_8195A("\n\r%s: " fmt, __FUNCTION__, ## args)
#define USBD_WARN(fmt, args...)
#define FUN_ENTER
#define FUN_EXIT
#define FUN_TRACE
#endif
/* MSC Request Codes */
#define MSC_REQUEST_RESET 0xFF
#define MSC_REQUEST_GET_MAX_LUN 0xFE
/* MSC LUN */
#define MSC_MAX_LOGIC_UNIT_NUMBER 1
enum data_direction{
DATA_DIR_UNKNOWN = 0,
DATA_DIR_FROM_HOST,
DATA_DIR_TO_HOST,
DATA_DIR_NONE
};
typedef enum _disk_type{
DISK_SDCARD,
DISK_FLASH
}disk_type;
//structure predefine
struct msc_dev;
struct msc_bufhd;
struct msc_opts{
int (*disk_init)(void);
int (*disk_deinit)(void);
int (*disk_getcapacity)(u32* sectors);
int (*disk_read)(u32 sector,u8 *buffer,u32 count);
int (*disk_write)(u32 sector,const u8 *buffer,u32 count);
};
struct msc_lun {
unsigned int initially_ro:1;
unsigned int ro:1;
unsigned int removable:1;
unsigned int cdrom:1;
unsigned int prevent_medium_removal:1;
unsigned int registered:1;
unsigned int info_valid:1;
unsigned int nofua:1;
u32 sense_data;
u32 sense_data_info;
u32 unit_attention_data;
u64 file_length;
unsigned int num_sectors; /* */
unsigned int blkbits; /* Bits of logical block size
of bound block device */
unsigned int blksize; /* logical block size of bound block device */
const char *name; /* "lun.name" */
unsigned int lba; // the current read and write logical block address
u8 is_open;
_mutex lun_mutex;
struct msc_opts *lun_opts;
};
struct msc_common{
struct msc_dev *mscdev;
struct msc_lun **luns;
struct msc_lun *curlun;
struct usb_gadget *gadget;
struct usb_ep *ep0;
struct usb_request *req0; /* for control responses */
/* scsi cbw relevant */
enum data_direction data_dir;
u32 data_size;
u32 data_size_from_cmnd;
u32 tag;
u32 residue;
u32 usb_amount_left;
u8 scsi_cmnd[16]; // max command
u8 cmnd_size;
u8 lun; /* current lun*/
u8 nluns;
u8 nbufhd;
u8 nbufhd_a;
_list bufhd_pool;
_mutex bufhd_mutex;
/* bulk out cmd*/
_list boc_list;
_mutex boc_mutex;
/* bolk out data*/
_mutex bod_mutex;
_list bod_list;
/**/
struct msc_bufhd* curbh; // current buffer header
struct msc_bufhd* cbw_bh; // buffer header for CBW
struct msc_bufhd* csw_bh; // buffer header for CSW
unsigned int can_stall:1;
unsigned int phase_error:1;
unsigned int short_packet_received:1;
unsigned int bad_lun_okay:1;
unsigned int running:1;
};
typedef enum _bufhd_type{
BUFHD_CBW = 0,
BUFHD_CSW,
BUFHD_DATA,
}bufhd_type;
struct msc_bufhd{
u8* buf;
int buf_size;
bufhd_type type;
_list list;
struct usb_request *reqin; /* for bulkin responses */
struct usb_request *reqout;
};
struct msc_dev{
struct msc_common *common;
u16 interface_number;
u8 config;
struct usb_ep *in_ep;
struct usb_ep *out_ep;
unsigned int bulk_in_enabled:1;
unsigned int bulk_out_enabled:1;
const struct usb_endpoint_descriptor
*in, *out, *status;
// lock is held when accessing usb
struct task_struct msc_outCmdTask;
struct task_struct msc_outDataTask;
struct usb_function func;
};
u32 min(u32 value1,u32 value2);
int usbd_msc_halt_bulk_in_endpoint(struct msc_dev *mscdev);
void usbd_msc_put_bufhd(struct msc_common *common, struct msc_bufhd* bufhd);
struct msc_bufhd* usbd_msc_get_bufhd(struct msc_common *common);
int usbd_msc_bulk_in_transfer(struct msc_dev *mscdev, struct usb_request *req);
int usbd_msc_bulk_out_transfer(struct msc_dev *mscdev, struct usb_request *req);
/*
* N_bh : number of buffer header
* Size_bh: buffer size per buffer
* type:msc physical disk type
*/
int usbd_msc_init(int N_bh, int Size_bh, disk_type type);
void usbd_msc_deinit(void);
#endif

8
component/common/drivers/usb_class/device/class/msc/inc/usbd_msc_config.h Executable file
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#ifndef _USBD_MSC_CONFIG_H
#define _USBD_MSC_CONFIG_H
/* config usb MSC device buffer resource */
#define MSC_NBR_BUFHD 2 /* number of buffer header for bulk in/out data*/
#define MSC_BUFLEN (32*512)/* Default size of buffer length. Minmun of 512 byte*/
#endif

196
component/common/drivers/usb_class/device/class/msc/inc/usbd_msc_desc.h Executable file
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#include "usb_ch9.h"
#include "usb_defs.h"
#include "usb_gadget.h"
// <i> Enable high-speed functionality (if device supports it)
#define USBD_HS_ENABLE 1
// define string index
#define STRING_MANUFACTURER 1
#define STRING_PRODUCT 2
#define STRING_SERIALNUMBER 3
#define STRING_INTERFACE 4
#define STRING_MSC 5
#define DEV_CONFIG_VALUE 1
#define DRIVER_DESC "USB Mass Storage"
#define DRIVER_VERSION "Feb 2016"
#define MANUFACTURER "Realtek Singapore Semiconductor"
static char string_manufacturer [50] = MANUFACTURER;
static char string_product [40] = DRIVER_DESC;
static char string_serial [20] = "0123456789";
struct usb_string
usbd_msc_strings [] = {
{ STRING_MANUFACTURER, string_manufacturer, },
{ STRING_PRODUCT, string_product, },
{ STRING_SERIALNUMBER, string_serial, },
{ STRING_INTERFACE, "USB MSC Interface", },
{ STRING_MSC, "USB MSC", },
};
struct usb_gadget_strings msc_stringtab = {
.language = 0x0409, /* en-us */
.strings = usbd_msc_strings,
};
struct usb_gadget_strings *dev_msc_strings[] = {
&msc_stringtab,
NULL,
};
static struct usb_device_descriptor
usbd_msc_device_desc = {
.bLength = sizeof usbd_msc_device_desc,
.bDescriptorType = USB_DT_DEVICE,
.bcdUSB = (0x0200),
.bDeviceClass = 0x00,// define in interface descriptor
.bDeviceSubClass = 0x00,
.bDeviceProtocol = 0x00,
.bMaxPacketSize0 = 64, // this will be set automatically depends on ep0 setting
.idVendor = 0x0BDA,
.idProduct = 0x8195,
// .bcdDevice = ,
.iManufacturer = STRING_MANUFACTURER,
.iProduct = STRING_PRODUCT,
.iSerialNumber = STRING_SERIALNUMBER,
.bNumConfigurations=0x01,
};
#if 0
struct usb_config_descriptor
usbd_msc_config_desc = {
.bLength = sizeof usbd_msc_config_desc,
.bDescriptorType = USB_DT_CONFIG,
/* compute wTotalLength on the fly */
.bNumInterfaces = 1,
.bConfigurationValue = DEV_CONFIG_VALUE,
.iConfiguration = STRING_MSC,
.bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
.bMaxPower = 0x32,
};
#endif
#if USBD_HS_ENABLE
/* USB Device Qualifier Descriptor (for Full Speed) */
static struct usb_qualifier_descriptor
usbd_msc_qualifier_desc_FS = {
.bLength = sizeof usbd_msc_qualifier_desc_FS,
.bDescriptorType = USB_DT_DEVICE_QUALIFIER,
.bcdUSB = 0x0200,
.bDeviceClass = 0x00,
.bDeviceSubClass = 0x00,
.bDeviceProtocol = 0x00,
.bMaxPacketSize0 = 64,
.bNumConfigurations = 0x01,
.bRESERVED = 0x00,
};
/* USB Device Qualifier Descriptor for High Speed */
static struct usb_qualifier_descriptor
usbd_msc_qualifier_desc_HS = {
.bLength = sizeof usbd_msc_qualifier_desc_HS,
.bDescriptorType = USB_DT_DEVICE_QUALIFIER,
.bcdUSB = 0x0200,
.bDeviceClass = 0x00,
.bDeviceSubClass = 0x00,
.bDeviceProtocol = 0x00,
.bMaxPacketSize0 = 64,
.bNumConfigurations = 0x01,
.bRESERVED = 0x00,
};
#else
/* USB Device Qualifier Descriptor (for Full Speed) */
static struct usb_qualifier_descriptor
usbd_msc_qualifier_desc_FS = { 0 };
/* USB Device Qualifier Descriptor for High Speed */
static struct usb_qualifier_descriptor
usbd_msc_qualifier_desc_HS = { 0 };
#endif
/* MSC Interface, Alternate Setting 0*/
struct usb_interface_descriptor
usbd_msc_intf_desc = {
.bLength = sizeof usbd_msc_intf_desc,
.bDescriptorType = USB_DT_INTERFACE,
.bInterfaceNumber = 0x00, // this will be assign automatically
.bAlternateSetting =0x00,
.bNumEndpoints = 0x02,
.bInterfaceClass = USB_CLASS_MASS_STORAGE,
.bInterfaceSubClass = US_SC_SCSI,
.bInterfaceProtocol = US_PR_BULK,
.iInterface = STRING_INTERFACE,
};
/* MSC Endpoints for Low-speed/Full-speed */
/* Endpoint, EP Bulk IN */
struct usb_endpoint_descriptor
usbd_msc_source_desc_FS = {
.bLength = USB_DT_ENDPOINT_SIZE,
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = USB_DIR_IN,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
.wMaxPacketSize = (64),
.bInterval = 0x00,
};
/* Endpoint, EP Bulk OUT */
struct usb_endpoint_descriptor
usbd_msc_sink_desc_FS = {
.bLength = USB_DT_ENDPOINT_SIZE,
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = USB_DIR_OUT,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
.wMaxPacketSize = (64),
.bInterval = 0x00,
};
/* MSC Endpoints for High-speed */
/* Endpoint, EP Bulk IN */
struct usb_endpoint_descriptor
usbd_msc_source_desc_HS = {
.bLength = USB_DT_ENDPOINT_SIZE,
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = USB_DIR_IN,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
.wMaxPacketSize = (512),
.bInterval = 0x00,
};
/* Endpoint, EP Bulk OUT */
struct usb_endpoint_descriptor
usbd_msc_sink_desc_HS = {
.bLength = USB_DT_ENDPOINT_SIZE,
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = USB_DIR_OUT,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
.wMaxPacketSize = (512),
.bInterval = 0x00,
};
struct usb_descriptor_header *usbd_msc_descriptors_FS [] = {
/* data interface has no altsetting */
(struct usb_descriptor_header *) &usbd_msc_intf_desc,
(struct usb_descriptor_header *) &usbd_msc_source_desc_FS,
(struct usb_descriptor_header *) &usbd_msc_sink_desc_FS,
NULL,
};
struct usb_descriptor_header *usbd_msc_descriptors_HS [] = {
/* data interface has no altsetting */
(struct usb_descriptor_header *) &usbd_msc_intf_desc,
(struct usb_descriptor_header *) &usbd_msc_source_desc_HS,
(struct usb_descriptor_header *) &usbd_msc_sink_desc_HS,
NULL,
};

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component/common/drivers/usb_class/device/class/msc/inc/usbd_scsi.h Executable file
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#ifndef USBD_SCSI_H
#define USBD_SCSI_H
#include "basic_types.h"
#include "msc/inc/usbd_msc.h"
#define MAX_COMMAND_SIZE 16
#define MSC_MAX_LUNS 8
/* SCSI Commands */
#define SCSI_FORMAT_UNIT 0x04
#define SCSI_INQUIRY 0x12
#define SCSI_MODE_SELECT6 0x15
#define SCSI_MODE_SELECT10 0x55
#define SCSI_MODE_SENSE6 0x1A
#define SCSI_MODE_SENSE10 0x5A
#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1E
#define SCSI_READ6 0x08
#define SCSI_READ10 0x28
#define SCSI_READ12 0xA8
#define SCSI_READ16 0x88
#define SCSI_READ_CAPACITY10 0x25
#define SCSI_READ_CAPACITY16 0x9E
#define SCSI_SYNCHRONIZE_CACHE 0x35
#define SCSI_REQUEST_SENSE 0x03
#define SCSI_START_STOP_UNIT 0x1B
#define SCSI_TEST_UNIT_READY 0x00
#define SCSI_WRITE6 0x0A
#define SCSI_WRITE10 0x2A
#define SCSI_WRITE12 0xAA
#define SCSI_WRITE16 0x8A
#define SCSI_VERIFY10 0x2F
#define SCSI_VERIFY12 0xAF
#define SCSI_VERIFY16 0x8F
#define SCSI_SEND_DIAGNOSTIC 0x1D
#define SCSI_READ_FORMAT_CAPACITIES 0x23
#define READ_FORMAT_CAPACITY_DATA_LEN 0x0C
#define READ_CAPACITY10_DATA_LEN 0x08
#define MODE_SENSE10_DATA_LEN 0x08
#define MODE_SENSE6_DATA_LEN 0x04
#define REQUEST_SENSE_DATA_LEN 0x12
#define STANDARD_INQUIRY_DATA_LEN 0x24
/* SCSI Sense Key/Additional Sense Code/ASC Qualifier values */
#define SS_NO_SENSE 0
#define SS_COMMUNICATION_FAILURE 0x040800
#define SS_INVALID_COMMAND 0x052000
#define SS_INVALID_FIELD_IN_CDB 0x052400
#define SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x052100
#define SS_LOGICAL_UNIT_NOT_SUPPORTED 0x052500
#define SS_MEDIUM_NOT_PRESENT 0x023a00
#define SS_MEDIUM_REMOVAL_PREVENTED 0x055302
#define SS_NOT_READY_TO_READY_TRANSITION 0x062800
#define SS_RESET_OCCURRED 0x062900
#define SS_SAVING_PARAMETERS_NOT_SUPPORTED 0x053900
#define SS_UNRECOVERED_READ_ERROR 0x031100
#define SS_WRITE_ERROR 0x030c02
#define SS_WRITE_PROTECTED 0x072700
#define SK(x) ((u8) ((x) >> 16)) /* Sense Key byte, etc. */
#define ASC(x) ((u8) ((x) >> 8))
#define ASCQ(x) ((u8) (x))
/*
* Bulk only data structures
*/
/* command block wrapper */
struct bulk_cb_wrap {
unsigned int Signature; /* contains 'USBC', denote bulk_cb_wrap */
unsigned int Tag; /* unique per command id */
unsigned int DataTransferLength; /* size of data for transfer */
unsigned char Flags; /* data transfer direction */
unsigned char Lun; /* LUN normally 0, (which command block is sent) */
unsigned char Length; /* length of the CDB */
unsigned char CDB[16]; /* max command */
};
#define US_BULK_CB_WRAP_LEN 31
#define US_BULK_CB_SIGN 0x43425355 /*spells out USBC */
#define US_BULK_FLAG_IN (1 << 7)
#define US_BULK_FLAG_OUT 0
/* command status wrapper */
struct bulk_cs_wrap {
unsigned int Signature; /* should = 'USBS' */
unsigned int Tag; /* same as original command, echoed by the device as received */
unsigned int Residue; /* amount not transferred */
unsigned char Status; /* execute command status */
};
#define US_BULK_CS_WRAP_LEN 13
#define US_BULK_CS_SIGN 0x53425355 /* spells out 'USBS' */
// execute command status
#define US_BULK_STAT_OK 0
#define US_BULK_STAT_FAIL 1
#define US_BULK_STAT_PHASE 2
/* bulk-only class specific requests */
#define US_BULK_RESET_REQUEST 0xff
#define US_BULK_GET_MAX_LUN 0xfe
extern int usbd_msc_receive_cbw(struct msc_dev *mscdev, struct usb_request *req);
#endif

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component/common/drivers/usb_class/device/core/inc/gadget_debug.h Executable file
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#ifndef _GADEGT_DEBUG_H_
#define _GADGET_DEBUG_H_
#include "diag.h"
#define GADGET_DEBUG 0
#if GADGET_DEBUG
#define GADGET_PRINT(fmt, args...) DBG_8195A("\n\r[%s]: " fmt, __FUNCTION__, ## args)
#define GADGET_ERROR(fmt, args...) DBG_8195A("\n\r[%s]: " fmt, __FUNCTION__, ## args)
#define GADGET_WARN(fmt, args...) DBG_8195A("\n\r[%s]: " fmt, __FUNCTION__, ## args)
#define FUN_ENTER DBG_8195A("\n\r[%s ==>]\n", __func__)
#define FUN_EXIT DBG_8195A("\n\r[%s <==]\n", __func__)
#define FUN_TRACE DBG_8195A("\n\r[%s]:%d \n", __func__, __LINE__)
#else
#define GADGET_PRINT(fmt, args...)
#define GADGET_ERROR(fmt, args...) DBG_8195A("\n\r[%s]: " fmt, __FUNCTION__, ## args)
#define GADGET_WARN(fmt, args...)
#define FUN_ENTER
#define FUN_EXIT
#define FUN_TRACE
#endif
#endif

398
component/common/drivers/usb_class/device/core/inc/usb_composite.h Executable file
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#ifndef _USB_COMPOSITE_H_
#define _USB_COMPOSITE_H_
#include "usb_gadget.h"
#include "usb.h"
/*
* USB function drivers should return USB_GADGET_DELAYED_STATUS if they
* wish to delay the data/status stages of the control transfer till they
* are ready. The control transfer will then be kept from completing till
* all the function drivers that requested for USB_GADGET_DELAYED_STAUS
* invoke usb_composite_setup_continue().
*/
#define USB_GADGET_DELAYED_STATUS 0x7fff /* Impossibly large value */
/* big enough to hold our biggest descriptor */
#define USB_COMP_EP0_BUFSIZ 1024+24
#define MAX_CONFIG_INTERFACES 16 /* arbitrary; max 255 */
// predefine structure
struct usb_composite_dev;
struct usb_composite_driver;
enum control_request_return_codes {
USBD_REQ_NOTSUPP = 0,
USBD_REQ_HANDLED = 1,
USBD_REQ_NEXT_CALLBACK = 2,
};
/**
* struct usb_composite_driver - groups configurations into a gadget
* @name: For diagnostics, identifies the driver.
* @dev: Template descriptor for the device, including default device
* identifiers.
* @strings: tables of strings, keyed by identifiers assigned during @bind
* and language IDs provided in control requests. Note: The first entries
* are predefined. The first entry that may be used is
* USB_GADGET_FIRST_AVAIL_IDX
* @max_speed: Highest speed the driver supports.
* @needs_serial: set to 1 if the gadget needs userspace to provide
* a serial number. If one is not provided, warning will be printed.
* @bind: (REQUIRED) Used to allocate resources that are shared across the
* whole device, such as string IDs, and add its configurations using
* @usb_add_config(). This may fail by returning a negative errno
* value; it should return zero on successful initialization.
* @unbind: Reverses @bind; called as a side effect of unregistering
* this driver.
* @disconnect: optional driver disconnect method
* @suspend: Notifies when the host stops sending USB traffic,
* after function notifications
* @resume: Notifies configuration when the host restarts USB traffic,
* before function notifications
* @gadget_driver: Gadget driver controlling this driver
*
* Devices default to reporting self powered operation. Devices which rely
* on bus powered operation should report this in their @bind method.
*
* Before returning from @bind, various fields in the template descriptor
* may be overridden. These include the idVendor/idProduct/bcdDevice values
* normally to bind the appropriate host side driver, and the three strings
* (iManufacturer, iProduct, iSerialNumber) normally used to provide user
* meaningful device identifiers. (The strings will not be defined unless
* they are defined in @dev and @strings.) The correct ep0 maxpacket size
* is also reported, as defined by the underlying controller driver.
*/
struct usb_composite_driver {
const char *name;
const struct usb_device_descriptor *dev;
struct usb_gadget_strings **strings;
enum usb_device_speed max_speed;
unsigned needs_serial:1;
int (*bind)(struct usb_composite_dev *cdev);
int (*unbind)(struct usb_composite_dev *);
void (*disconnect)(struct usb_composite_dev *);
/* global suspend hooks */
void (*suspend)(struct usb_composite_dev *);
void (*resume)(struct usb_composite_dev *);
struct usb_gadget_driver gadget_driver;
};
/**
* struct usb_composite_device - represents one composite usb gadget
* @gadget: read-only, abstracts the gadget's usb peripheral controller
* @req: used for control responses; buffer is pre-allocated
* @os_desc_req: used for OS descriptors responses; buffer is pre-allocated
* @config: the currently active configuration
* @qw_sign: qwSignature part of the OS string
* @b_vendor_code: bMS_VendorCode part of the OS string
* @use_os_string: false by default, interested gadgets set it
* @os_desc_config: the configuration to be used with OS descriptors
*
* One of these devices is allocated and initialized before the
* associated device driver's bind() is called.
*
* OPEN ISSUE: it appears that some WUSB devices will need to be
* built by combining a normal (wired) gadget with a wireless one.
* This revision of the gadget framework should probably try to make
* sure doing that won't hurt too much.
*
* One notion for how to handle Wireless USB devices involves:
* (a) a second gadget here, discovery mechanism TBD, but likely
* needing separate "register/unregister WUSB gadget" calls;
* (b) updates to usb_gadget to include flags "is it wireless",
* "is it wired", plus (presumably in a wrapper structure)
* bandgroup and PHY info;
* (c) presumably a wireless_ep wrapping a usb_ep, and reporting
* wireless-specific parameters like maxburst and maxsequence;
* (d) configurations that are specific to wireless links;
* (e) function drivers that understand wireless configs and will
* support wireless for (additional) function instances;
* (f) a function to support association setup (like CBAF), not
* necessarily requiring a wireless adapter;
* (g) composite device setup that can create one or more wireless
* configs, including appropriate association setup support;
* (h) more, TBD.
*/
#define MAX_USER_CONTROL_CALLBACK 2
typedef int (*user_control_callback)(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl);
struct usb_composite_dev {
struct usb_gadget *gadget;
struct usb_request *req;
struct usb_request *os_desc_req;
struct usb_configuration *config;
//
// /* OS String is a custom (yet popular) extension to the USB standard. */
// u8 qw_sign[OS_STRING_QW_SIGN_LEN];
// u8 b_vendor_code;
// struct usb_configuration *os_desc_config;
// unsigned int use_os_string:1;
//
// /* private: */
// /* internals */
unsigned int suspended:1;
struct usb_device_descriptor desc;
//_LIST config_list;
dwc_list_link_t config_list; // by jimmy
//_LIST gstring_list;
dwc_list_link_t gstring_list;// by jimmy
struct usb_composite_driver *driver;
// u8 next_string_id;
// char *def_manufacturer;
//
// /* the gadget driver won't enable the data pullup
// * while the deactivation count is nonzero.
// */
// unsigned deactivations;
//
// /* the composite driver won't complete the control transfer's
// * data/status stages till delayed_status is zero.
// */
// int delayed_status;
//
// /* protects deactivations and delayed_status counts*/
_Lock lock;
/* for unstandard control request handler */
user_control_callback control_cb[MAX_USER_CONTROL_CALLBACK];
};
#if 0
#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n))
static inline struct usb_composite_driver *to_cdriver(
struct usb_gadget_driver *gdrv)
{
return container_of(gdrv, struct usb_composite_driver, gadget_driver);
}
#endif
#if 1
/**
* struct usb_configuration - represents one gadget configuration
* @label: For diagnostics, describes the configuration.
* @strings: Tables of strings, keyed by identifiers assigned during @bind()
* and by language IDs provided in control requests.
* @descriptors: Table of descriptors preceding all function descriptors.
* Examples include OTG and vendor-specific descriptors.
* @unbind: Reverses @bind; called as a side effect of unregistering the
* driver which added this configuration.
* @setup: Used to delegate control requests that aren't handled by standard
* device infrastructure or directed at a specific interface.
* @bConfigurationValue: Copied into configuration descriptor.
* @iConfiguration: Copied into configuration descriptor.
* @bmAttributes: Copied into configuration descriptor.
* @MaxPower: Power consumtion in mA. Used to compute bMaxPower in the
* configuration descriptor after considering the bus speed.
* @cdev: assigned by @usb_add_config() before calling @bind(); this is
* the device associated with this configuration.
*
* Configurations are building blocks for gadget drivers structured around
* function drivers. Simple USB gadgets require only one function and one
* configuration, and handle dual-speed hardware by always providing the same
* functionality. Slightly more complex gadgets may have more than one
* single-function configuration at a given speed; or have configurations
* that only work at one speed.
*
* Composite devices are, by definition, ones with configurations which
* include more than one function.
*
* The lifecycle of a usb_configuration includes allocation, initialization
* of the fields described above, and calling @usb_add_config() to set up
* internal data and bind it to a specific device. The configuration's
* @bind() method is then used to initialize all the functions and then
* call @usb_add_function() for them.
*
* Those functions would normally be independent of each other, but that's
* not mandatory. CDC WMC devices are an example where functions often
* depend on other functions, with some functions subsidiary to others.
* Such interdependency may be managed in any way, so long as all of the
* descriptors complete by the time the composite driver returns from
* its bind() routine.
*/
struct usb_configuration {
const char *label;
struct usb_gadget_strings **strings;
const struct usb_descriptor_header **descriptors;
/* REVISIT: bind() functions can be marked __init, which
* makes trouble for section mismatch analysis. See if
* we can't restructure things to avoid mismatching...
*/
/* configuration management: unbind/setup */
void (*unbind)(struct usb_configuration *);
int (*setup)(struct usb_configuration *,
const struct usb_ctrlrequest *);
/* fields in the config descriptor */
u8 bConfigurationValue;
u8 iConfiguration;
u8 bmAttributes;
u16 MaxPower;
struct usb_composite_dev *cdev;
/* private: */
/* internals */
//_LIST list;
//_LIST function_lists;
dwc_list_link_t list;
dwc_list_link_t function_lists; // by jimmy
u8 next_interface_id;
unsigned superspeed:1;
unsigned highspeed:1;
unsigned fullspeed:1;
struct usb_function *interface[MAX_CONFIG_INTERFACES];
};
_LONG_CALL_ int usb_interface_id(struct usb_configuration *config,
struct usb_function *function);
_LONG_CALL_ int usb_add_config(struct usb_composite_dev *,
struct usb_configuration *,
int (*)(struct usb_configuration *));
_LONG_CALL_ void usb_remove_config(struct usb_composite_dev *,
struct usb_configuration *);
/**
* struct usb_function - describes one function of a configuration
* @name: For diagnostics, identifies the function.
* @strings: tables of strings, keyed by identifiers assigned during bind()
* and by language IDs provided in control requests
* @fs_descriptors: Table of full (or low) speed descriptors, using interface and
* string identifiers assigned during @bind(). If this pointer is null,
* the function will not be available at full speed (or at low speed).
* @hs_descriptors: Table of high speed descriptors, using interface and
* string identifiers assigned during @bind(). If this pointer is null,
* the function will not be available at high speed.
* @ss_descriptors: Table of super speed descriptors, using interface and
* string identifiers assigned during @bind(). If this
* pointer is null after initiation, the function will not
* be available at super speed.
* @config: assigned when @usb_add_function() is called; this is the
* configuration with which this function is associated.
* @os_desc_table: Table of (interface id, os descriptors) pairs. The function
* can expose more than one interface. If an interface is a member of
* an IAD, only the first interface of IAD has its entry in the table.
* @os_desc_n: Number of entries in os_desc_table
* @bind: Before the gadget can register, all of its functions bind() to the
* available resources including string and interface identifiers used
* in interface or class descriptors; endpoints; I/O buffers; and so on.
* @unbind: Reverses @bind; called as a side effect of unregistering the
* driver which added this function.
* @free_func: free the struct usb_function.
* @mod: (internal) points to the module that created this structure.
* @set_alt: (REQUIRED) Reconfigures altsettings; function drivers may
* initialize usb_ep.driver data at this time (when it is used).
* Note that setting an interface to its current altsetting resets
* interface state, and that all interfaces have a disabled state.
* @get_alt: Returns the active altsetting. If this is not provided,
* then only altsetting zero is supported.
* @disable: (REQUIRED) Indicates the function should be disabled. Reasons
* include host resetting or reconfiguring the gadget, and disconnection.
* @setup: Used for interface-specific control requests.
* @suspend: Notifies functions when the host stops sending USB traffic.
* @resume: Notifies functions when the host restarts USB traffic.
* @get_status: Returns function status as a reply to
* GetStatus() request when the recipient is Interface.
* @func_suspend: callback to be called when
* SetFeature(FUNCTION_SUSPEND) is reseived
*
* A single USB function uses one or more interfaces, and should in most
* cases support operation at both full and high speeds. Each function is
* associated by @usb_add_function() with a one configuration; that function
* causes @bind() to be called so resources can be allocated as part of
* setting up a gadget driver. Those resources include endpoints, which
* should be allocated using @usb_ep_autoconfig().
*
* To support dual speed operation, a function driver provides descriptors
* for both high and full speed operation. Except in rare cases that don't
* involve bulk endpoints, each speed needs different endpoint descriptors.
*
* Function drivers choose their own strategies for managing instance data.
* The simplest strategy just declares it "static', which means the function
* can only be activated once. If the function needs to be exposed in more
* than one configuration at a given speed, it needs to support multiple
* usb_function structures (one for each configuration).
*
* A more complex strategy might encapsulate a @usb_function structure inside
* a driver-specific instance structure to allows multiple activations. An
* example of multiple activations might be a CDC ACM function that supports
* two or more distinct instances within the same configuration, providing
* several independent logical data links to a USB host.
*/
struct usb_function {
const char *name;
struct usb_gadget_strings **strings;
struct usb_descriptor_header **fs_descriptors;
struct usb_descriptor_header **hs_descriptors;
// struct usb_descriptor_header **ss_descriptors;
struct usb_configuration *config;
// struct usb_os_desc_table *os_desc_table;
// unsigned os_desc_n;
/* REVISIT: bind() functions can be marked __init, which
* makes trouble for section mismatch analysis. See if
* we can't restructure things to avoid mismatching.
* Related: unbind() may kfree() but bind() won't...
*/
/* configuration management: bind/unbind */
int (*bind)(struct usb_configuration *,
struct usb_function *);
void (*unbind)(struct usb_configuration *,
struct usb_function *);
void (*free_func)(struct usb_function *f);
struct module *mod;
/* runtime state management */
int (*set_alt)(struct usb_function *,
unsigned interface, unsigned alt);
int (*get_alt)(struct usb_function *,
unsigned interface);
void (*disable)(struct usb_function *);
int (*setup)(struct usb_function *,
const struct usb_ctrlrequest *);
void (*suspend)(struct usb_function *);
void (*resume)(struct usb_function *);
/* USB 3.0 additions */
int (*get_status)(struct usb_function *);
int (*func_suspend)(struct usb_function *,
u8 suspend_opt);
/* private: */
/* internals */
//_LIST list;
dwc_list_link_t list; // by jimmy
// DECLARE_BITMAP(endpoints, 32);
// const struct usb_function_instance *fi;
};
#endif
extern _LONG_CALL_ int usb_add_function(struct usb_configuration *, struct usb_function *);
extern _LONG_CALL_ void usb_remove_function(struct usb_configuration *, struct usb_function *);
extern _LONG_CALL_ void usb_put_function(struct usb_function *);
extern _LONG_CALL_ int usb_function_deactivate(struct usb_function *);
extern _LONG_CALL_ int usb_function_activate(struct usb_function *);
extern _LONG_CALL_ int usb_interface_id(struct usb_configuration *, struct usb_function *);
extern _LONG_CALL_ int usb_composite_probe(struct usb_composite_driver *driver);
extern _LONG_CALL_ int register_class_vendor_control_request_cb(struct usb_composite_dev *cdev, user_control_callback cb);
extern _LONG_CALL_ void usb_composite_unregister(struct usb_composite_driver *driver);
#endif

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component/common/drivers/usb_class/device/core/inc/usb_config.h Executable file
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#ifndef _USB_CONFIG_H_
#define _USB_CONFIG_H_
#include "core/inc/usb_composite.h"
extern _LONG_CALL_ int usb_assign_descriptors(struct usb_function *f,
struct usb_descriptor_header **fs,
struct usb_descriptor_header **hs,
struct usb_descriptor_header **ss);
extern _LONG_CALL_ void usb_free_all_descriptors(struct usb_function *f);
#endif

71
component/common/drivers/usb_class/host/uvc/inc/uapi_uvcvideo.h Executable file
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#ifndef __LINUX_UVCVIDEO_H_
#define __LINUX_UVCVIDEO_H_
#if 0
#include <linux/ioctl.h>
#include <linux/types.h>
#endif
#include "uvc_os_wrap_via_osdep_api.h"
/*
* Dynamic controls
*/
/* Data types for UVC control data */
#define UVC_CTRL_DATA_TYPE_RAW 0
#define UVC_CTRL_DATA_TYPE_SIGNED 1
#define UVC_CTRL_DATA_TYPE_UNSIGNED 2
#define UVC_CTRL_DATA_TYPE_BOOLEAN 3
#define UVC_CTRL_DATA_TYPE_ENUM 4
#define UVC_CTRL_DATA_TYPE_BITMASK 5
/* Control flags */
#define UVC_CTRL_FLAG_SET_CUR (1 << 0)
#define UVC_CTRL_FLAG_GET_CUR (1 << 1)
#define UVC_CTRL_FLAG_GET_MIN (1 << 2)
#define UVC_CTRL_FLAG_GET_MAX (1 << 3)
#define UVC_CTRL_FLAG_GET_RES (1 << 4)
#define UVC_CTRL_FLAG_GET_DEF (1 << 5)
/* Control should be saved at suspend and restored at resume. */
#define UVC_CTRL_FLAG_RESTORE (1 << 6)
/* Control can be updated by the camera. */
#define UVC_CTRL_FLAG_AUTO_UPDATE (1 << 7)
#define UVC_CTRL_FLAG_GET_RANGE \
(UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MIN | \
UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_RES | \
UVC_CTRL_FLAG_GET_DEF)
struct uvc_menu_info {
__u32 value;
__u8 name[32];
};
struct uvc_xu_control_mapping {
__u32 id;
__u8 name[32];
__u8 entity[16];
__u8 selector;
__u8 size;
__u8 offset;
__u32 v4l2_type;
__u32 data_type;
struct uvc_menu_info __user *menu_info;
__u32 menu_count;
__u32 reserved[4];
};
struct uvc_xu_control_query {
__u8 unit;
__u8 selector;
__u8 query; /* Video Class-Specific Request Code, */
/* defined in linux/usb/video.h A.8. */
__u16 size;
__u8 __user *data;
};
#define UVCIOC_CTRL_MAP _IOWR('u', 0x20, struct uvc_xu_control_mapping)
#define UVCIOC_CTRL_QUERY _IOWR('u', 0x21, struct uvc_xu_control_query)
#endif

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component/common/drivers/usb_class/host/uvc/inc/uvc_intf.h Executable file
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#ifndef _UVC_INTF_H_
#define _UVC_INTF_H_
enum uvc_format_type{
UVC_FORMAT_MJPEG = 1,
UVC_FORMAT_H264 = 2,
UVC_FORMAT_UNKNOWN = -1,
};
typedef enum uvc_format_type uvc_fmt_t;
struct uvc_context
{
uvc_fmt_t fmt_type; //video format type
int width;//video frame width
int height;//video frame height
int frame_rate;//video frame rate
int compression_ratio;//compression format video compression ratio
};
#define USER_CTRL_BRIGHTNESS 0
#define USER_CTRL_CONTRAST 1
#define USER_CTRL_SATURATION 2
#define USER_CTRL_HUE 3
#define USER_CTRL_AUTO_WHITE_BALANCE 12
#define USER_CTRL_DO_WHITE_BALANCE 13
#define USER_CTRL_RED_BALANCE 14
#define USER_CTRL_BLUE_BALANCE 15
#define USER_CTRL_GAMMA 16
#define USER_CTRL_EXPOSURE 17
#define USER_CTRL_AUTOGAIN 18
#define USER_CTRL_GAIN 19
#define USER_CTRL_HFLIP 20
#define USER_CTRL_VFLIP 21
#define USER_CTRL_POWER_LINE_FREQUENCY 24
#define USER_CTRL_HUE_AUTO 25
#define USER_CTRL_WHITE_BALANCE_TEMPERATURE 26
#define USER_CTRL_SHARPNESS 27
#define USER_CTRL_BACKLIGHT_COMPENSATION 28
struct uvc_user_ctrl
{
u32 ctrl_id;
s32 ctrl_value;
};
struct uvc_buf_context
{
int index; //index of internal uvc buffer
unsigned char *data; //address of uvc data
int len; //length of uvc data
u32 timestamp; //timestamp
};
int uvc_stream_init(void); //entry function to start uvc
void uvc_stream_free(void); // free streaming resources
int uvc_is_stream_ready(void); // return true if uvc device is initialized successfully
int uvc_is_stream_on(void); //return true if uvc device is streaming now
int uvc_is_stream_off(void); //return true if uvc device is free already
int uvc_stream_on(void); //enable camera streaming
void uvc_stream_off(void); //disable camera streaming
int uvc_set_param(uvc_fmt_t fmt_type, int *width, int *height, int *frame_rate, int *compression_ratio);//set camera streaming video parameters:video format, resolution and frame rate.
int uvc_get_user_ctrl(struct uvc_user_ctrl *user_ctrl);
int uvc_set_user_ctrl(struct uvc_user_ctrl *user_ctrl);
int uvc_buf_check(struct uvc_buf_context *b); //check if uvc_buf_context is legal (return 0 is legal otherwise -1)
int uvc_dqbuf(struct uvc_buf_context *b); //dequeue internal buffer & get internal buffer info
int uvc_qbuf(struct uvc_buf_context *b); //queue internal buffer
int is_pure_thru_on(void); //return 1 if pure throughput test mode is on otherwise return 0
void uvc_pure_thru_on(void); //turn on pure uvc throughput test mode (i.e. no decoding is involved)
void uvc_dec_thru_on(void); //turn on uvc throughput test mode with uvc payload decoding
void uvc_thru_off(void); //turn off uvc throughput log service
#endif

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component/common/drivers/usb_class/host/uvc/inc/uvc_os_wrap_via_osdep_api.h Executable file
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#ifndef _UVC_OSDEP_WRAP_H_
#define _UVC_OSDEP_WRAP_H_
//#include "rtl_utility.h"
#include "platform/platform_stdlib.h"
#include "basic_types.h"
#include "osdep_api.h"
#include "usb_defs.h"
#include "usb_errno.h"
#include "dlist.h"
#define UVC_LAYER_DEBUG 0
#if UVC_LAYER_DEBUG
#define UVC_PRINTF(fmt, args...) printf("\n\r%s: " fmt, __FUNCTION__, ## args)
#define UVC_ERROR(fmt, args...) printf("\n\r%s: " fmt, __FUNCTION__, ## args)
#define FUN_ENTER //printf("\n\r%s ==>\n", __func__)
#define FUN_EXIT //printf("\n\r%s <==\n", __func__)
#define FUN_TRACE //printf("\n\r%s:%d \n", __func__, __LINE__)
#else
#define UVC_PRINTF(fmt, args...)
#define UVC_ERROR(fmt, args...) printf("\n\r%s: " fmt, __FUNCTION__, ## args)
#define FUN_ENTER
#define FUN_EXIT
#define FUN_TRACE
#endif
/* add by Ian -- define uvc task priority */
#define UVC_TASK_PRIORITY 2
#ifndef __u8
#define __u8 u8
#endif
#ifndef __u16
#define __u16 u16
#endif
#ifndef __u32
#define __u32 u32
#endif
#ifndef __u64
#define __u64 u64
#endif
#ifndef __s8
#define __s8 s8
#endif
#ifndef __s16
#define __s16 s16
#endif
#ifndef __s32
#define __s32 s32
#endif
#ifndef __s64
#define __s64 s64
#endif
#ifndef gfp_t
#define gfp_t u32
#endif
#define ALIGN(x, a, type_of_x) (((x) + ((type_of_x)(a) - 1)) & ~((type_of_x)(a) - 1))
#ifndef IS_ALIGNED
#define IS_ALIGNED(x, a, type_of_x) (((x) & ((type_of_x)(a) - 1)) == 0)
#endif
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#endif
#ifndef BITS_PER_LONG
#define BITS_PER_LONG (32)
#endif
#ifndef BITS_PER_LONG_LONG
#define BITS_PER_LONG_LONG (32)
#endif
/* Atomic integer operations */
#ifndef atomic_set
#define atomic_set(v, i) RTL_ATOMIC_SET((v), (i))
#endif
#ifndef atomic_read
#define atomic_read(v) RTL_ATOMIC_READ((v))
#endif
#ifndef atomic_add
#define atomic_add(v, i) RTL_ATOMIC_ADD((v), (i))
#endif
#ifndef atomic_sub
#define atomic_sub(v, i) RTL_ATOMIC_SUB((v), (i))
#endif
#ifndef atomic_inc
#define atomic_inc(v) RTL_ATOMIC_INC((v))
#endif
#ifndef atomic_dec
#define atomic_dec(v) RTL_ATOMIC_DEC((v))
#endif
#ifndef MEDIA_PAD_FL_SINK
#define MEDIA_PAD_FL_SINK (1 << 0)
#endif
#ifndef MEDIA_PAD_FL_SOURCE
#define MEDIA_PAD_FL_SOURCE (1 << 1)
#endif
#ifndef MEDIA_PAD_FL_MUST_CONNECT
#define MEDIA_PAD_FL_MUST_CONNECT (1 << 2)
#endif
static inline u16 __get_unaligned_le16(const u8 *p)
{
return p[0] | p[1] << 8;
}
static inline u32 __get_unaligned_le32(const u8 *p)
{
return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24;
}
static inline u64 __get_unaligned_le64(const u8 *p)
{
return (u64)__get_unaligned_le32(p + 4) << 32 |
__get_unaligned_le32(p);
}
static inline void __put_unaligned_le16(u16 val, u8 *p)
{
*p++ = val;
*p++ = val >> 8;
}
static inline void __put_unaligned_le32(u32 val, u8 *p)
{
__put_unaligned_le16(val >> 16, p + 2);
__put_unaligned_le16(val, p);
}
static inline void __put_unaligned_le64(u64 val, u8 *p)
{
__put_unaligned_le32(val >> 32, p + 4);
__put_unaligned_le32(val, p);
}
static inline u16 get_unaligned_le16(const void *p)
{
return __get_unaligned_le16((const u8 *)p);
}
static inline u32 get_unaligned_le32(const void *p)
{
return __get_unaligned_le32((const u8 *)p);
}
static inline u64 get_unaligned_le64(const void *p)
{
return __get_unaligned_le64((const u8 *)p);
}
static inline void put_unaligned_le16(u16 val, void *p)
{
__put_unaligned_le16(val, p);
}
static inline void put_unaligned_le32(u32 val, void *p)
{
__put_unaligned_le32(val, p);
}
static inline void put_unaligned_le64(u64 val, void *p)
{
__put_unaligned_le64(val, p);
}
/**
* kmemdup - duplicate region of memory
*
* @src: memory region to duplicate
* @len: memory region length
* @gfp: GFP mask to use
*/
static inline void *kmemdup(const void *src, size_t len, gfp_t gfp)
{
void *p;
//p = kmalloc_track_caller(len, gfp);
//p = kmalloc(len, gfp);
p = malloc(len);
if (p)
memcpy(p, src, len);
return p;
}
#ifndef __force
#define __force __attribute__((force))
#endif
#if 0
typedef __u16 __bitwise __le16;
typedef __u16 __bitwise __be16;
typedef __u32 __bitwise __le32;
typedef __u32 __bitwise __be32;
typedef __u64 __bitwise __le64;
typedef __u64 __bitwise __be64;
typedef __u16 __bitwise __sum16;
typedef __u32 __bitwise __wsum;
#endif
//edit by Ian -- remove duplicated definitions
#if 0
typedef __u16 __le16;
typedef __u16 __be16;
typedef __u32 __le32;
typedef __u32 __be32;
typedef __u64 __le64;
typedef __u64 __be64;
typedef __u16 __sum16;
typedef __u32 __wsum;
#endif
#ifndef __le16
#define __le16 __u16
#endif
#ifndef __be16
#define __be16 __u16
#endif
#ifndef __le32
#define __le32 __u32
#endif
#ifndef __be32
#define __be32 __u32
#endif
static inline __u32 le32_to_cpup(const __le32 *p)
{
//return (__force __u32)*p;
return (__u32)*p;
}
static inline __u16 le16_to_cpup(const __le16 *p)
{
//return (__force __u16)*p;
return (__u16)*p;
}
/* Endian macros */
#ifndef htonl
#define htonl(x) rtk_cpu_to_be32(x)
#endif
#ifndef ntohl
#define ntohl(x) rtk_be32_to_cpu(x)
#endif
#ifndef htons
#define htons(x) rtk_cpu_to_be16(x)
#endif
#ifndef ntohs
#define ntohs(x) rtk_be16_to_cpu(x)
#endif
#ifndef cpu_to_le32
#define cpu_to_le32(x) rtk_cpu_to_le32(x)
#endif
#ifndef le32_to_cpu
#define le32_to_cpu(x) rtk_le32_to_cpu(x)
#endif
#ifndef cpu_to_le16
#define cpu_to_le16(x) rtk_cpu_to_le16(x)
#endif
#ifndef le16_to_cpu
#define le16_to_cpu(x) rtk_le16_to_cpu(x)
#endif
#ifndef cpu_to_be32
#define cpu_to_be32(x) rtk_cpu_to_be32(x)
#endif
#ifndef be32_to_cpu
#define be32_to_cpu(x) rtk_be32_to_cpu(x)
#endif
#ifndef cpu_to_be16
#define cpu_to_be16(x) rtk_cpu_to_be16(x)
#endif
#ifndef be16_to_cpu
#define be16_to_cpu(x) rtk_be16_to_cpu(x)
#endif
/* Parameters used to convert the timespec values: */
#ifndef MSEC_PER_SEC
#define MSEC_PER_SEC 1000L
#endif
#ifndef USEC_PER_MSEC
#define USEC_PER_MSEC 1000L
#endif
#ifndef NSEC_PER_USEC
#define NSEC_PER_USEC 1000L
#endif
#ifndef NSEC_PER_MSEC
#define NSEC_PER_MSEC 1000000L
#endif
#ifndef USEC_PER_SEC
#define USEC_PER_SEC 1000000L
#endif
#ifndef NSEC_PER_SEC
#define NSEC_PER_SEC 1000000000L
#endif
#ifndef FSEC_PER_SEC
#define FSEC_PER_SEC 1000000000000000LL
#endif
#ifndef TIME_T_MAX
#define TIME_T_MAX (time_t)((1UL << ((sizeof(time_t) << 3) - 1)) - 1)
#endif
#ifndef __GFP_WAIT
#define __GFP_WAIT (0x10u)
#endif
#ifndef __GFP_HIGH
#define __GFP_HIGH (0x20u)
#endif
#ifndef __GFP_IO
#define __GFP_IO (0x40u)
#endif
#ifndef __GFP_FS
#define __GFP_FS (0x80u)
#endif
#ifndef GFP_NOIO
#define GFP_NOIO (0x10u)
#endif
#ifndef __GFP_NOWARN
#define __GFP_NOWARN (0x200u)
#endif
#ifndef GFP_KERNEL
#define GFP_KERNEL (__GFP_WAIT | __GFP_IO | __GFP_FS)
#endif
#ifndef copy_from_user
#define copy_from_user(to, from, sz) RtlMemcpy((to), (from), (sz))
#endif
#ifndef copy_to_user
#define copy_to_user(to, from, sz) RtlMemcpy((to), (from), (sz))
#endif
typedef u32 compat_caddr_t; //used for compatibility in uvc_v4l2.c
/**
* strlcpy - Copy a %NUL terminated string into a sized buffer
* @dest: Where to copy the string to
* @src: Where to copy the string from
* @size: size of destination buffer
*
* Compatible with *BSD: the result is always a valid
* NUL-terminated string that fits in the buffer (unless,
* of course, the buffer size is zero). It does not pad
* out the result like strncpy() does.
*/
#ifndef __GNUC__
static inline size_t strlcpy(char *dest, const char *src, size_t size)
{
size_t ret = _strlen(src);
if (size) {
size_t len = (ret >= size) ? size - 1 : ret;
memcpy(dest, src, len);
dest[len] = '\0';
}
return ret;
}
#endif
/**
* clamp - return a value clamped to a given range with strict typechecking
* @val: current value
* @min: minimum allowable value
* @max: maximum allowable value
*
* This macro does strict typechecking of min/max to make sure they are of the
* same type as val. See the unnecessary pointer comparisons.
*/
#ifndef clamp
#define clamp(new_val, val, min, max, type) do{ \
type __val = (val); \
type __min = (min); \
type __max = (max); \
(void) (&__val == &__min); \
(void) (&__val == &__max); \
__val = (__val < __min) ? __min: __val; \
new_val = (__val > __max) ? __max: __val; }while(0)
#endif
/*
* Compile time versions of __arch_hweightN()
*/
#ifndef __const_hweight8
#define __const_hweight8(w) \
( (!!((w) & (1ULL << 0))) + \
(!!((w) & (1ULL << 1))) + \
(!!((w) & (1ULL << 2))) + \
(!!((w) & (1ULL << 3))) + \
(!!((w) & (1ULL << 4))) + \
(!!((w) & (1ULL << 5))) + \
(!!((w) & (1ULL << 6))) + \
(!!((w) & (1ULL << 7))) )
#endif
#ifndef hweight8
#define hweight8(w) __const_hweight8(w)
#endif
#ifndef BITMAP_LAST_WORD_MASK
#define BITMAP_LAST_WORD_MASK(nbits) \
( \
((nbits) % BITS_PER_LONG) ? \
(1UL<<((nbits) % BITS_PER_LONG))-1 : ~0UL \
)
#endif
/**
* hweightN - returns the hamming weight of a N-bit word
* @x: the word to weigh
*
* The Hamming Weight of a number is the total number of bits set in it.
*/
static inline unsigned int hweight32(unsigned int w)
{
unsigned int res = w - ((w >> 1) & 0x55555555);
res = (res & 0x33333333) + ((res >> 2) & 0x33333333);
res = (res + (res >> 4)) & 0x0F0F0F0F;
res = res + (res >> 8);
return (res + (res >> 16)) & 0x000000FF;
}
static inline unsigned long hweight64(__u64 w)
{
#if BITS_PER_LONG == 32
return hweight32((unsigned int)(w >> 32)) + hweight32((unsigned int)w);
#elif BITS_PER_LONG == 64
__u64 res = w - ((w >> 1) & 0x5555555555555555ul);
res = (res & 0x3333333333333333ul) + ((res >> 2) & 0x3333333333333333ul);
res = (res + (res >> 4)) & 0x0F0F0F0F0F0F0F0Ful;
res = res + (res >> 8);
res = res + (res >> 16);
return (res + (res >> 32)) & 0x00000000000000FFul;
#endif
}
static inline unsigned long hweight_long(unsigned long w)
{
return sizeof(w) == 4 ? hweight32(w) : hweight64(w);
}
static inline int __bitmap_weight(const unsigned long *bitmap, int bits)
{
int k, w = 0, lim = bits/BITS_PER_LONG;
for (k = 0; k < lim; k++)
w += hweight_long(bitmap[k]);
if (bits % BITS_PER_LONG)
w += hweight_long(bitmap[k] & BITMAP_LAST_WORD_MASK(bits));
return w;
}
static inline int bitmap_weight(const unsigned long *src, int nbits)
{
// if (small_const_nbits(nbits))
// return hweight_long(*src & BITMAP_LAST_WORD_MASK(nbits));
return __bitmap_weight(src, nbits);
}
/**
* memweight - count the total number of bits set in memory area
* @ptr: pointer to the start of the area
* @bytes: the size of the area
*/
static inline size_t memweight(const void *ptr, size_t bytes)
{
size_t ret = 0;
size_t longs;
const unsigned char *bitmap = ptr;
for (; bytes > 0 && ((unsigned long)bitmap) % sizeof(long);
bytes--, bitmap++)
ret += hweight8(*bitmap);
longs = bytes / sizeof(long);
if (longs) {
//BUG_ON(longs >= INT_MAX / BITS_PER_LONG);
ret += bitmap_weight((unsigned long *)bitmap, longs * BITS_PER_LONG);
bytes -= longs * sizeof(long);
bitmap += longs * sizeof(long);
}
/*
* The reason that this last loop is distinct from the preceding
* bitmap_weight() call is to compute 1-bits in the last region smaller
* than sizeof(long) properly on big-endian systems.
*/
for (; bytes > 0; bytes--, bitmap++)
ret += hweight8(*bitmap);
return ret;
}
/**
* strlcat - Append a length-limited, %NUL-terminated string to another
* @dest: The string to be appended to
* @src: The string to append to it
* @count: The size of the destination buffer.
*/
#ifndef __GNUC__
static inline size_t strlcat(char *dest, const char *src, size_t count)
{
size_t dsize = _strlen(dest);
size_t len = _strlen(src);
size_t res = dsize + len;
/* This would be a bug */
//BUG_ON(dsize >= count);
dest += dsize;
count -= dsize;
if (len >= count)
len = count-1;
memcpy(dest, src, len);
dest[len] = 0;
return res;
}
#endif
/**
* atomic_dec_and_test - decrement and test
* @v: pointer of type atomic_t
*
* Atomically decrements @v by 1 and
* returns true if the result is 0, or false for all other
* cases.
*/
static inline int atomic_dec_and_test(atomic_t *v)
{
atomic_dec(v);
if (v->counter == 0)
return TRUE;
else
return FALSE;
}
/**
* kcalloc - allocate memory for an array. The memory is set to zero.
* @n: number of elements.
* @size: element size.
* @flags: the type of memory to allocate (see kmalloc).
*/
static inline void *kcalloc(size_t n, size_t size, gfp_t flags)
{
return RtlZmalloc(((n) * (size)));
}
#ifndef GFP_ATOMIC
#define GFP_ATOMIC GFP_KERNEL
#endif
#ifndef offsetof
#define offsetof(s,m) (size_t)&(((s *)0)->m)
#endif
//enum linux kernel version
#ifndef KERNEL_VERSION
#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
#endif
#ifndef LINUX_VERSION_CODE
#define LINUX_VERSION_CODE KERNEL_VERSION(3, 12, 0)
#endif
#endif //_UVC_OSDEP_WRAP_H_

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component/common/drivers/usb_class/host/uvc/inc/uvc_osdep.h Executable file
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#ifndef _UVC_OSDEP_WRAP_H_
#define _UVC_OSDEP_WRAP_H_
//#include "rtl_utility.h"
#include "platform/platform_stdlib.h"
#include "basic_types.h"
#include "osdep_api.h"
#include "usb_defs.h"
#include "errno.h"
#include "dlist.h"
#define UVC_LAYER_DEBUG 0
#if UVC_LAYER_DEBUG
#define UVC_PRINTF(fmt, args...) printf("\n\r%s: " fmt, __FUNCTION__, ## args)
#define UVC_ERROR(fmt, args...) printf("\n\r%s: " fmt, __FUNCTION__, ## args)
#define UVC_WARN(fmt, args...) printf("\n\r%s: " fmt, __FUNCTION__, ## args)
#define FUN_ENTER //printf("\n\r%s ==>\n", __func__)
#define FUN_EXIT //printf("\n\r%s <==\n", __func__)
#define FUN_TRACE //printf("\n\r%s:%d \n", __func__, __LINE__)
#else
#define UVC_PRINTF(fmt, args...)
#define UVC_ERROR(fmt, args...) printf("\n\r%s: " fmt, __FUNCTION__, ## args)
#define UVC_WARN(fmt, args...) printf("\n\r%s: " fmt, __FUNCTION__, ## args)
#define FUN_ENTER
#define FUN_EXIT
#define FUN_TRACE
#endif
/* add by Ian -- define uvc task priority */
#define UVC_TASK_PRIORITY 2
#ifndef __u8
#define __u8 u8
#endif
#ifndef __u16
#define __u16 u16
#endif
#ifndef __u32
#define __u32 u32
#endif
#ifndef __u64
#define __u64 u64
#endif
#ifndef __s8
#define __s8 s8
#endif
#ifndef __s16
#define __s16 s16
#endif
#ifndef __s32
#define __s32 s32
#endif
#ifndef __s64
#define __s64 s64
#endif
#ifndef gfp_t
#define gfp_t u32
#endif
#define ALIGN(x, a, type_of_x) (((x) + ((type_of_x)(a) - 1)) & ~((type_of_x)(a) - 1))
#ifndef IS_ALIGNED
#define IS_ALIGNED(x, a, type_of_x) (((x) & ((type_of_x)(a) - 1)) == 0)
#endif
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#endif
#ifndef BITS_PER_LONG
#define BITS_PER_LONG (32)
#endif
#ifndef BITS_PER_LONG_LONG
#define BITS_PER_LONG_LONG (32)
#endif
/* Atomic integer operations */
#ifndef atomic_set
#define atomic_set(v, i) RTL_ATOMIC_SET((v), (i))
#endif
#ifndef atomic_read
#define atomic_read(v) RTL_ATOMIC_READ((v))
#endif
#ifndef atomic_add
#define atomic_add(v, i) RTL_ATOMIC_ADD((v), (i))
#endif
#ifndef atomic_sub
#define atomic_sub(v, i) RTL_ATOMIC_SUB((v), (i))
#endif
#ifndef atomic_inc
#define atomic_inc(v) RTL_ATOMIC_INC((v))
#endif
#ifndef atomic_dec
#define atomic_dec(v) RTL_ATOMIC_DEC((v))
#endif
#ifndef MEDIA_PAD_FL_SINK
#define MEDIA_PAD_FL_SINK (1 << 0)
#endif
#ifndef MEDIA_PAD_FL_SOURCE
#define MEDIA_PAD_FL_SOURCE (1 << 1)
#endif
#ifndef MEDIA_PAD_FL_MUST_CONNECT
#define MEDIA_PAD_FL_MUST_CONNECT (1 << 2)
#endif
static inline u16 __get_unaligned_le16(const u8 *p)
{
return p[0] | p[1] << 8;
}
static inline u32 __get_unaligned_le32(const u8 *p)
{
return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24;
}
static inline u64 __get_unaligned_le64(const u8 *p)
{
return (u64)__get_unaligned_le32(p + 4) << 32 |
__get_unaligned_le32(p);
}
static inline void __put_unaligned_le16(u16 val, u8 *p)
{
*p++ = val;
*p++ = val >> 8;
}
static inline void __put_unaligned_le32(u32 val, u8 *p)
{
__put_unaligned_le16(val >> 16, p + 2);
__put_unaligned_le16(val, p);
}
static inline void __put_unaligned_le64(u64 val, u8 *p)
{
__put_unaligned_le32(val >> 32, p + 4);
__put_unaligned_le32(val, p);
}
static inline u16 get_unaligned_le16(const void *p)
{
return __get_unaligned_le16((const u8 *)p);
}
static inline u32 get_unaligned_le32(const void *p)
{
return __get_unaligned_le32((const u8 *)p);
}
static inline u64 get_unaligned_le64(const void *p)
{
return __get_unaligned_le64((const u8 *)p);
}
static inline void put_unaligned_le16(u16 val, void *p)
{
__put_unaligned_le16(val, p);
}
static inline void put_unaligned_le32(u32 val, void *p)
{
__put_unaligned_le32(val, p);
}
static inline void put_unaligned_le64(u64 val, void *p)
{
__put_unaligned_le64(val, p);
}
/**
* kmemdup - duplicate region of memory
*
* @src: memory region to duplicate
* @len: memory region length
* @gfp: GFP mask to use
*/
static inline void *kmemdup(const void *src, size_t len, gfp_t gfp)
{
void *p;
//p = kmalloc_track_caller(len, gfp);
//p = kmalloc(len, gfp);
p = rtw_malloc(len);
if (p)
memcpy(p, src, len);
return p;
}
#ifndef __force
#define __force __attribute__((force))
#endif
#if 0
typedef __u16 __bitwise __le16;
typedef __u16 __bitwise __be16;
typedef __u32 __bitwise __le32;
typedef __u32 __bitwise __be32;
typedef __u64 __bitwise __le64;
typedef __u64 __bitwise __be64;
typedef __u16 __bitwise __sum16;
typedef __u32 __bitwise __wsum;
#endif
//edit by Ian -- remove duplicated definitions
#if 0
typedef __u16 __le16;
typedef __u16 __be16;
typedef __u32 __le32;
typedef __u32 __be32;
typedef __u64 __le64;
typedef __u64 __be64;
typedef __u16 __sum16;
typedef __u32 __wsum;
#endif
#ifndef __le16
#define __le16 __u16
#endif
#ifndef __be16
#define __be16 __u16
#endif
#ifndef __le32
#define __le32 __u32
#endif
#ifndef __be32
#define __be32 __u32
#endif
static inline __u32 le32_to_cpup(const __le32 *p)
{
//return (__force __u32)*p;
return (__u32)*p;
}
static inline __u16 le16_to_cpup(const __le16 *p)
{
//return (__force __u16)*p;
return (__u16)*p;
}
/* Endian macros */
#ifndef htonl
#define htonl(x) rtk_cpu_to_be32(x)
#endif
#ifndef ntohl
#define ntohl(x) rtk_be32_to_cpu(x)
#endif
#ifndef htons
#define htons(x) rtk_cpu_to_be16(x)
#endif
#ifndef ntohs
#define ntohs(x) rtk_be16_to_cpu(x)
#endif
#ifndef cpu_to_le32
#define cpu_to_le32(x) rtk_cpu_to_le32(x)
#endif
#ifndef le32_to_cpu
#define le32_to_cpu(x) rtk_le32_to_cpu(x)
#endif
#ifndef cpu_to_le16
#define cpu_to_le16(x) rtk_cpu_to_le16(x)
#endif
#ifndef le16_to_cpu
#define le16_to_cpu(x) rtk_le16_to_cpu(x)
#endif
#ifndef cpu_to_be32
#define cpu_to_be32(x) rtk_cpu_to_be32(x)
#endif
#ifndef be32_to_cpu
#define be32_to_cpu(x) rtk_be32_to_cpu(x)
#endif
#ifndef cpu_to_be16
#define cpu_to_be16(x) rtk_cpu_to_be16(x)
#endif
#ifndef be16_to_cpu
#define be16_to_cpu(x) rtk_be16_to_cpu(x)
#endif
/* Parameters used to convert the timespec values: */
#ifndef MSEC_PER_SEC
#define MSEC_PER_SEC 1000L
#endif
#ifndef USEC_PER_MSEC
#define USEC_PER_MSEC 1000L
#endif
#ifndef NSEC_PER_USEC
#define NSEC_PER_USEC 1000L
#endif
#ifndef NSEC_PER_MSEC
#define NSEC_PER_MSEC 1000000L
#endif
#ifndef USEC_PER_SEC
#define USEC_PER_SEC 1000000L
#endif
#ifndef NSEC_PER_SEC
#define NSEC_PER_SEC 1000000000L
#endif
#ifndef FSEC_PER_SEC
#define FSEC_PER_SEC 1000000000000000LL
#endif
#ifndef TIME_T_MAX
#define TIME_T_MAX (time_t)((1UL << ((sizeof(time_t) << 3) - 1)) - 1)
#endif
#ifndef __GFP_WAIT
#define __GFP_WAIT (0x10u)
#endif
#ifndef __GFP_HIGH
#define __GFP_HIGH (0x20u)
#endif
#ifndef __GFP_IO
#define __GFP_IO (0x40u)
#endif
#ifndef __GFP_FS
#define __GFP_FS (0x80u)
#endif
#ifndef GFP_NOIO
#define GFP_NOIO (0x10u)
#endif
#ifndef __GFP_NOWARN
#define __GFP_NOWARN (0x200u)
#endif
#ifndef GFP_KERNEL
#define GFP_KERNEL (__GFP_WAIT | __GFP_IO | __GFP_FS)
#endif
#if 0
#ifndef copy_from_user
#define copy_from_user(to, from, sz) rtw_memcpy((to), (from), (sz))
#endif
#ifndef copy_to_user
#define copy_to_user(to, from, sz) rtw_memcpy((to), (from), (sz))
#endif
#endif
int inline copy_from_user(void* to, void* from, u32 sz)
{
memcpy(to, from, sz);
return TRUE;
}
int inline copy_to_user(void* to, void* from, u32 sz)
{
memcpy(to, from, sz);
return TRUE;
}
typedef u32 compat_caddr_t; //used for compatibility in uvc_v4l2.c
/**
* strlcpy - Copy a %NUL terminated string into a sized buffer
* @dest: Where to copy the string to
* @src: Where to copy the string from
* @size: size of destination buffer
*
* Compatible with *BSD: the result is always a valid
* NUL-terminated string that fits in the buffer (unless,
* of course, the buffer size is zero). It does not pad
* out the result like strncpy() does.
*/
static inline size_t strlcpy(char *dest, const char *src, size_t size)
{
size_t ret = _strlen(src);
if (size) {
size_t len = (ret >= size) ? size - 1 : ret;
memcpy(dest, src, len);
dest[len] = '\0';
}
return ret;
}
/**
* clamp - return a value clamped to a given range with strict typechecking
* @val: current value
* @min: minimum allowable value
* @max: maximum allowable value
*
* This macro does strict typechecking of min/max to make sure they are of the
* same type as val. See the unnecessary pointer comparisons.
*/
#ifndef clamp
#define clamp(new_val, val, min, max, type) do{ \
type __val = (val); \
type __min = (min); \
type __max = (max); \
(void) (&__val == &__min); \
(void) (&__val == &__max); \
__val = (__val < __min) ? __min: __val; \
new_val = (__val > __max) ? __max: __val; }while(0)
#endif
/*
* Compile time versions of __arch_hweightN()
*/
#ifndef __const_hweight8
#define __const_hweight8(w) \
( (!!((w) & (1ULL << 0))) + \
(!!((w) & (1ULL << 1))) + \
(!!((w) & (1ULL << 2))) + \
(!!((w) & (1ULL << 3))) + \
(!!((w) & (1ULL << 4))) + \
(!!((w) & (1ULL << 5))) + \
(!!((w) & (1ULL << 6))) + \
(!!((w) & (1ULL << 7))) )
#endif
#ifndef hweight8
#define hweight8(w) __const_hweight8(w)
#endif
#ifndef BITMAP_LAST_WORD_MASK
#define BITMAP_LAST_WORD_MASK(nbits) \
( \
((nbits) % BITS_PER_LONG) ? \
(1UL<<((nbits) % BITS_PER_LONG))-1 : ~0UL \
)
#endif
/**
* hweightN - returns the hamming weight of a N-bit word
* @x: the word to weigh
*
* The Hamming Weight of a number is the total number of bits set in it.
*/
static inline unsigned int hweight32(unsigned int w)
{
unsigned int res = w - ((w >> 1) & 0x55555555);
res = (res & 0x33333333) + ((res >> 2) & 0x33333333);
res = (res + (res >> 4)) & 0x0F0F0F0F;
res = res + (res >> 8);
return (res + (res >> 16)) & 0x000000FF;
}
static inline unsigned long hweight64(__u64 w)
{
#if BITS_PER_LONG == 32
return hweight32((unsigned int)(w >> 32)) + hweight32((unsigned int)w);
#elif BITS_PER_LONG == 64
__u64 res = w - ((w >> 1) & 0x5555555555555555ul);
res = (res & 0x3333333333333333ul) + ((res >> 2) & 0x3333333333333333ul);
res = (res + (res >> 4)) & 0x0F0F0F0F0F0F0F0Ful;
res = res + (res >> 8);
res = res + (res >> 16);
return (res + (res >> 32)) & 0x00000000000000FFul;
#endif
}
static inline unsigned long hweight_long(unsigned long w)
{
return sizeof(w) == 4 ? hweight32(w) : hweight64(w);
}
static inline int __bitmap_weight(const unsigned long *bitmap, int bits)
{
int k, w = 0, lim = bits/BITS_PER_LONG;
for (k = 0; k < lim; k++)
w += hweight_long(bitmap[k]);
if (bits % BITS_PER_LONG)
w += hweight_long(bitmap[k] & BITMAP_LAST_WORD_MASK(bits));
return w;
}
static inline int bitmap_weight(const unsigned long *src, int nbits)
{
// if (small_const_nbits(nbits))
// return hweight_long(*src & BITMAP_LAST_WORD_MASK(nbits));
return __bitmap_weight(src, nbits);
}
/**
* memweight - count the total number of bits set in memory area
* @ptr: pointer to the start of the area
* @bytes: the size of the area
*/
static inline size_t memweight(const void *ptr, size_t bytes)
{
size_t ret = 0;
size_t longs;
const unsigned char *bitmap = ptr;
for (; bytes > 0 && ((unsigned long)bitmap) % sizeof(long);
bytes--, bitmap++)
ret += hweight8(*bitmap);
longs = bytes / sizeof(long);
if (longs) {
//BUG_ON(longs >= INT_MAX / BITS_PER_LONG);
ret += bitmap_weight((unsigned long *)bitmap, longs * BITS_PER_LONG);
bytes -= longs * sizeof(long);
bitmap += longs * sizeof(long);
}
/*
* The reason that this last loop is distinct from the preceding
* bitmap_weight() call is to compute 1-bits in the last region smaller
* than sizeof(long) properly on big-endian systems.
*/
for (; bytes > 0; bytes--, bitmap++)
ret += hweight8(*bitmap);
return ret;
}
/**
* strlcat - Append a length-limited, %NUL-terminated string to another
* @dest: The string to be appended to
* @src: The string to append to it
* @count: The size of the destination buffer.
*/
static inline size_t strlcat(char *dest, const char *src, size_t count)
{
size_t dsize = _strlen(dest);
size_t len = _strlen(src);
size_t res = dsize + len;
/* This would be a bug */
//BUG_ON(dsize >= count);
dest += dsize;
count -= dsize;
if (len >= count)
len = count-1;
memcpy(dest, src, len);
dest[len] = 0;
return res;
}
/**
* atomic_dec_and_test - decrement and test
* @v: pointer of type atomic_t
*
* Atomically decrements @v by 1 and
* returns true if the result is 0, or false for all other
* cases.
*/
static inline int atomic_dec_and_test(atomic_t *v)
{
atomic_dec(v);
if (v->counter == 0)
return TRUE;
else
return FALSE;
}
/**
* kcalloc - allocate memory for an array. The memory is set to zero.
* @n: number of elements.
* @size: element size.
* @flags: the type of memory to allocate (see kmalloc).
*/
static inline void *kcalloc(size_t n, size_t size, gfp_t flags)
{
//return RtlZmalloc(((n) * (size)));
return rtw_zmalloc(((n) * (size)));
}
#ifndef GFP_ATOMIC
#define GFP_ATOMIC GFP_KERNEL
#endif
#ifndef offsetof
#define offsetof(s,m) (size_t)&(((s *)0)->m)
#endif
//enum linux kernel version
#ifndef KERNEL_VERSION
#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
#endif
#ifndef LINUX_VERSION_CODE
#define LINUX_VERSION_CODE KERNEL_VERSION(3, 12, 0)
#endif
#endif //_UVC_OSDEP_WRAP_H_

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component/common/drivers/usb_class/host/uvc/inc/uvcvideo.h Executable file
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#ifndef _USB_VIDEO_H_
#define _USB_VIDEO_H_
#if 0
#ifndef __KERNEL__
#error "The uvcvideo.h header is deprecated, use linux/uvcvideo.h instead."
#endif /* __KERNEL__ */
#include <linux/kernel.h>
#include <linux/poll.h>
#endif
#include "usb.h"
#include "video.h"
#include "uvcvideo.h"
#include "videodev2.h"
#include "media-device.h"
#include "v4l2-device.h"
#include "v4l2-event.h"
#include "v4l2-fh.h"
#include "videobuf2-core.h"
/* --------------------------------------------------------------------------
* UVC constants
*/
#define UVC_TERM_INPUT 0x0000
#define UVC_TERM_OUTPUT 0x8000
#define UVC_TERM_DIRECTION(term) ((term)->type & 0x8000)
#define UVC_ENTITY_TYPE(entity) ((entity)->type & 0x7fff)
#define UVC_ENTITY_IS_UNIT(entity) (((entity)->type & 0xff00) == 0)
#define UVC_ENTITY_IS_TERM(entity) (((entity)->type & 0xff00) != 0)
#define UVC_ENTITY_IS_ITERM(entity) \
(UVC_ENTITY_IS_TERM(entity) && \
((entity)->type & 0x8000) == UVC_TERM_INPUT)
#define UVC_ENTITY_IS_OTERM(entity) \
(UVC_ENTITY_IS_TERM(entity) && \
((entity)->type & 0x8000) == UVC_TERM_OUTPUT)
/* ------------------------------------------------------------------------
* GUIDs
*/
#define UVC_GUID_UVC_CAMERA \
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}
#define UVC_GUID_UVC_OUTPUT \
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02}
#define UVC_GUID_UVC_MEDIA_TRANSPORT_INPUT \
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
#define UVC_GUID_UVC_PROCESSING \
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01}
#define UVC_GUID_UVC_SELECTOR \
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02}
#define UVC_GUID_FORMAT_MJPEG \
{ 'M', 'J', 'P', 'G', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_YUY2 \
{ 'Y', 'U', 'Y', '2', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_YUY2_ISIGHT \
{ 'Y', 'U', 'Y', '2', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0x00, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_NV12 \
{ 'N', 'V', '1', '2', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_YV12 \
{ 'Y', 'V', '1', '2', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_I420 \
{ 'I', '4', '2', '0', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_UYVY \
{ 'U', 'Y', 'V', 'Y', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_Y800 \
{ 'Y', '8', '0', '0', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_Y8 \
{ 'Y', '8', ' ', ' ', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_Y10 \
{ 'Y', '1', '0', ' ', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_Y12 \
{ 'Y', '1', '2', ' ', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_Y16 \
{ 'Y', '1', '6', ' ', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_BY8 \
{ 'B', 'Y', '8', ' ', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_RGBP \
{ 'R', 'G', 'B', 'P', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_M420 \
{ 'M', '4', '2', '0', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_H264 \
{ 'H', '2', '6', '4', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
/* edit by Ian -- patch for GEO add two new guids*/
#define UVC_GUID_FORMAT_MPEG \
{ 'M', 'P', 'E', 'G', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
#define UVC_GUID_FORMAT_MUX \
{ 'M', 'U', 'X', 0x00, 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
/* ------------------------------------------------------------------------
* Driver specific constants.
*/
#define DRIVER_VERSION "1.1.1"
/* Number of isochronous URBs. */
#define UVC_URBS 2
/* Maximum number of packets per URB. */
#define UVC_MAX_PACKETS 32
/* Maximum number of video buffers. */
#define UVC_MAX_VIDEO_BUFFERS 8
/* Maximum status buffer size in bytes of interrupt URB. */
#define UVC_MAX_STATUS_SIZE 16
//modified by Ian
#define UVC_REQBUF_SIZE (150000)
#define UVC_CTRL_CONTROL_TIMEOUT 300
#define UVC_CTRL_STREAMING_TIMEOUT 5000
/* Maximum allowed number of control mappings per device */
#define UVC_MAX_CONTROL_MAPPINGS 1024
#define UVC_MAX_CONTROL_MENU_ENTRIES 32
/* Devices quirks */
#define UVC_QUIRK_STATUS_INTERVAL 0x00000001
#define UVC_QUIRK_PROBE_MINMAX 0x00000002
#define UVC_QUIRK_PROBE_EXTRAFIELDS 0x00000004
#define UVC_QUIRK_BUILTIN_ISIGHT 0x00000008
#define UVC_QUIRK_STREAM_NO_FID 0x00000010
#define UVC_QUIRK_IGNORE_SELECTOR_UNIT 0x00000020
#define UVC_QUIRK_FIX_BANDWIDTH 0x00000080
#define UVC_QUIRK_PROBE_DEF 0x00000100
#define UVC_QUIRK_RESTRICT_FRAME_RATE 0x00000200
/* Format flags */
#define UVC_FMT_FLAG_COMPRESSED 0x00000001
#define UVC_FMT_FLAG_STREAM 0x00000002
/* ------------------------------------------------------------------------
* Structures.
*/
struct uvc_device;
/* TODO: Put the most frequently accessed fields at the beginning of
* structures to maximize cache efficiency.
*/
struct uvc_control_info {
struct list_head mappings;
__u8 entity[16];
__u8 index; /* Bit index in bmControls */
__u8 selector;
__u16 size;
__u32 flags;
};
struct uvc_control_mapping {
struct list_head list;
struct list_head ev_subs;
__u32 id;
__u8 name[32];
__u8 entity[16];
__u8 selector;
__u8 size;
__u8 offset;
enum v4l2_ctrl_type v4l2_type;
__u32 data_type;
struct uvc_menu_info *menu_info;
__u32 menu_count;
__u32 master_id;
__s32 master_manual;
__u32 slave_ids[2];
__s32 (*get) (struct uvc_control_mapping *mapping, __u8 query,
const __u8 *data);
void (*set) (struct uvc_control_mapping *mapping, __s32 value,
__u8 *data);
};
struct uvc_control {
struct uvc_entity *entity;
struct uvc_control_info info;
__u8 index; /* Used to match the uvc_control entry with a
uvc_control_info. */
__u8 dirty:1,
loaded:1,
modified:1,
cached:1,
initialized:1;
__u8 *uvc_data;
};
struct uvc_format_desc {
char *name;
__u8 guid[16];
__u32 fcc;
};
/* The term 'entity' refers to both UVC units and UVC terminals.
*
* The type field is either the terminal type (wTerminalType in the terminal
* descriptor), or the unit type (bDescriptorSubtype in the unit descriptor).
* As the bDescriptorSubtype field is one byte long, the type value will
* always have a null MSB for units. All terminal types defined by the UVC
* specification have a non-null MSB, so it is safe to use the MSB to
* differentiate between units and terminals as long as the descriptor parsing
* code makes sure terminal types have a non-null MSB.
*
* For terminals, the type's most significant bit stores the terminal
* direction (either UVC_TERM_INPUT or UVC_TERM_OUTPUT). The type field should
* always be accessed with the UVC_ENTITY_* macros and never directly.
*/
#define UVC_ENTITY_FLAG_DEFAULT (1 << 0)
struct uvc_entity {
struct list_head list; /* Entity as part of a UVC device. */
struct list_head chain; /* Entity as part of a video device
* chain. */
unsigned int flags;
__u8 id;
__u16 type;
char name[64];
/* Media controller-related fields. */
struct video_device *vdev;
struct v4l2_subdev subdev;
unsigned int num_pads;
unsigned int num_links;
struct media_pad *pads;
union {
struct {
__u16 wObjectiveFocalLengthMin;
__u16 wObjectiveFocalLengthMax;
__u16 wOcularFocalLength;
__u8 bControlSize;
__u8 *bmControls;
} camera;
struct {
__u8 bControlSize;
__u8 *bmControls;
__u8 bTransportModeSize;
__u8 *bmTransportModes;
} media;
#if 0
struct {
} output;
#endif
struct {
__u16 wMaxMultiplier;
__u8 bControlSize;
__u8 *bmControls;
__u8 bmVideoStandards;
} processing;
#if 0
struct {
} selector;
#endif
struct {
__u8 guidExtensionCode[16];
__u8 bNumControls;
__u8 bControlSize;
__u8 *bmControls;
__u8 *bmControlsType;
} extension;
};
__u8 bNrInPins;
__u8 *baSourceID;
unsigned int ncontrols;
struct uvc_control *controls;
};
// total (27)-> 28 Bytes
struct uvc_frame {
__u8 bFrameIndex;
__u8 bmCapabilities;
__u16 wWidth;
__u16 wHeight;
__u32 dwMinBitRate;
__u32 dwMaxBitRate;
__u32 dwMaxVideoFrameBufferSize;
__u8 bFrameIntervalType;
__u32 dwDefaultFrameInterval;
__u32 *dwFrameInterval;
};
// total 52 Bytes
struct uvc_format {
__u8 type;
__u8 index;
__u8 bpp;
__u8 colorspace;
__u32 fcc;
__u32 flags;
char name[32];
unsigned int nframes;
struct uvc_frame *frame;
};
struct uvc_streaming_header {
__u8 bNumFormats;
__u8 bEndpointAddress;
__u8 bTerminalLink;
__u8 bControlSize;
__u8 *bmaControls;
/* The following fields are used by input headers only. */
__u8 bmInfo;
__u8 bStillCaptureMethod;
__u8 bTriggerSupport;
__u8 bTriggerUsage;
};
enum uvc_buffer_state {
UVC_BUF_STATE_IDLE = 0,
UVC_BUF_STATE_QUEUED = 1,
UVC_BUF_STATE_ACTIVE = 2,
UVC_BUF_STATE_READY = 3,
UVC_BUF_STATE_DONE = 4,
UVC_BUF_STATE_ERROR = 5,
};
struct uvc_buffer {
struct vb2_buffer buf;
struct list_head queue;
_Mutex mutex;
enum uvc_buffer_state state;
unsigned int error;
void *mem;
unsigned int length;
unsigned int bytesused;
u32 pts;
};
#define UVC_QUEUE_DISCONNECTED (1 << 0)
#define UVC_QUEUE_DROP_CORRUPTED (1 << 1)
struct uvc_video_queue {
struct vb2_queue queue;
//struct mutex mutex; /* Protects queue */
_Mutex mutex;
unsigned int flags;
unsigned int buf_used;
//spinlock_t irqlock; /* Protects irqqueue */
//_LOCK_T irqlock;
_Mutex irqlock;
struct list_head irqqueue;
};
struct uvc_video_chain {
struct uvc_device *dev;
struct list_head list;
struct list_head entities; /* All entities */
struct uvc_entity *processing; /* Processing unit */
struct uvc_entity *selector; /* Selector unit */
//struct mutex ctrl_mutex; /* Protects ctrl.info */
_Mutex ctrl_mutex;
struct v4l2_prio_state prio; /* V4L2 priority state */
u32 caps; /* V4L2 chain-wide caps */
};
struct uvc_stats_frame {
unsigned int size; /* Number of bytes captured */
unsigned int first_data; /* Index of the first non-empty packet */
unsigned int nb_packets; /* Number of packets */
unsigned int nb_empty; /* Number of empty packets */
unsigned int nb_invalid; /* Number of packets with an invalid header */
unsigned int nb_errors; /* Number of packets with the error bit set */
unsigned int nb_pts; /* Number of packets with a PTS timestamp */
unsigned int nb_pts_diffs; /* Number of PTS differences inside a frame */
unsigned int last_pts_diff; /* Index of the last PTS difference */
bool has_initial_pts; /* Whether the first non-empty packet has a PTS */
bool has_early_pts; /* Whether a PTS is present before the first non-empty packet */
u32 pts; /* PTS of the last packet */
unsigned int nb_scr; /* Number of packets with a SCR timestamp */
unsigned int nb_scr_diffs; /* Number of SCR.STC differences inside a frame */
u16 scr_sof; /* SCR.SOF of the last packet */
u32 scr_stc; /* SCR.STC of the last packet */
};
struct uvc_stats_stream {
//struct timespec start_ts; /* Stream start timestamp */
//struct timespec stop_ts; /* Stream stop timestamp */
u32 start_ts;
u32 stop_ts;
unsigned int nb_frames; /* Number of frames */
unsigned int nb_packets; /* Number of packets */
unsigned int nb_empty; /* Number of empty packets */
unsigned int nb_invalid; /* Number of packets with an invalid header */
unsigned int nb_errors; /* Number of packets with the error bit set */
unsigned int nb_pts_constant; /* Number of frames with constant PTS */
unsigned int nb_pts_early; /* Number of frames with early PTS */
unsigned int nb_pts_initial; /* Number of frames with initial PTS */
unsigned int nb_scr_count_ok; /* Number of frames with at least one SCR per non empty packet */
unsigned int nb_scr_diffs_ok; /* Number of frames with varying SCR.STC */
unsigned int scr_sof_count; /* STC.SOF counter accumulated since stream start */
unsigned int scr_sof; /* STC.SOF of the last packet */
unsigned int min_sof; /* Minimum STC.SOF value */
unsigned int max_sof; /* Maximum STC.SOF value */
};
struct uvc_streaming {
struct list_head list;
struct uvc_device *dev;
struct video_device *vdev;
struct uvc_video_chain *chain;
atomic_t active;
struct usb_interface *intf;
int intfnum;
__u16 maxpsize;
struct uvc_streaming_header header;
enum v4l2_buf_type type;
unsigned int nformats;
struct uvc_format *format;
struct uvc_streaming_control ctrl;
struct uvc_format *def_format;
struct uvc_format *cur_format;
struct uvc_frame *cur_frame;
/* Protect access to ctrl, cur_format, cur_frame and hardware video
* probe control.
*/
//struct mutex mutex;
_Mutex mutex;
/* Buffers queue. */
unsigned int frozen : 1;
struct uvc_video_queue queue;
void (*decode) (struct urb *urb, struct uvc_streaming *video,
struct uvc_buffer *buf);
/* Context data used by the bulk completion handler. */
struct {
__u8 header[256];
unsigned int header_size;
int skip_payload;
__u32 payload_size;
__u32 max_payload_size;
} bulk;
struct urb *urb[UVC_URBS];
char *urb_buffer[UVC_URBS];
dma_addr_t urb_dma[UVC_URBS];
unsigned int urb_size;
__u32 sequence;
__u8 last_fid;
/* debugfs */
//struct dentry *debugfs_dir;
struct {
struct uvc_stats_frame frame;
struct uvc_stats_stream stream;
} stats;
/* Timestamps support. */
struct uvc_clock {
struct uvc_clock_sample {
u32 dev_stc;
u16 dev_sof;
//struct timespec host_ts;
u32 host_ts; //change to tick
u16 host_sof;
} *samples;
unsigned int head;
unsigned int count;
unsigned int size;
u16 last_sof;
u16 sof_offset;
//spinlock_t lock;
_Lock lock;
} clock;
};
enum uvc_device_state {
UVC_DEV_DISCONNECTED = 1,
};
struct uvc_device {
struct usb_device *udev;
struct usb_interface *intf;
unsigned long warnings;
__u32 quirks;
int intfnum;
char name[32];
enum uvc_device_state state;
//struct mutex lock; /* Protects users */
_Mutex lock;
unsigned int users;
atomic_t nmappings;
/* Video control interface */
#ifdef CONFIG_MEDIA_CONTROLLER
struct media_device mdev;
#endif
struct v4l2_device vdev;
__u16 uvc_version;
__u32 clock_frequency;
struct list_head entities; // VC_EXTENSION_UNIT ->VC_INPUT_TERMINAL ->VC_PROCESSING_UNIT ->VC_OUTPUT_TERMINAL
struct list_head chains;
/* Video Streaming interfaces */
struct list_head streams;
atomic_t nstreams;
/* Status Interrupt Endpoint */
struct usb_host_endpoint *int_ep;
struct urb *int_urb;
__u8 *status;
//struct input_dev *input;
char input_phys[64];
};
enum uvc_handle_state {
UVC_HANDLE_PASSIVE = 0,
UVC_HANDLE_ACTIVE = 1,
};
/* uvc file handle */
struct uvc_fh {
struct v4l2_fh vfh;
struct uvc_video_chain *chain;
struct uvc_streaming *stream;
enum uvc_handle_state state;
};
#if 0
/* uvc_driver = usb_driver for interface
* - identifies USB interface driver to usbcore
*/
struct uvc_driver {
struct usb_driver driver;
};
#endif
/* ------------------------------------------------------------------------
* Debugging, printing and logging
*/
#define UVC_TRACE_PROBE (1 << 0)
#define UVC_TRACE_DESCR (1 << 1)
#define UVC_TRACE_CONTROL (1 << 2)
#define UVC_TRACE_FORMAT (1 << 3)
#define UVC_TRACE_CAPTURE (1 << 4)
#define UVC_TRACE_CALLS (1 << 5)
#define UVC_TRACE_IOCTL (1 << 6)
#define UVC_TRACE_FRAME (1 << 7)
#define UVC_TRACE_SUSPEND (1 << 8)
#define UVC_TRACE_STATUS (1 << 9)
#define UVC_TRACE_VIDEO (1 << 10)
#define UVC_TRACE_STATS (1 << 11)
#define UVC_TRACE_CLOCK (1 << 12)
#define UVC_WARN_MINMAX 0
#define UVC_WARN_PROBE_DEF 1
#define UVC_WARN_XU_GET_RES 2
extern unsigned int uvc_clock_param;
extern unsigned int uvc_no_drop_param;
extern unsigned int uvc_trace_param;
extern unsigned int uvc_timeout_param;
#if 0
#define uvc_trace(flag, msg...) \
do { \
if (uvc_trace_param & flag) \
printk(KERN_DEBUG "uvcvideo: " msg); \
} while (0)
#define uvc_warn_once(dev, warn, msg...) \
do { \
if (!test_and_set_bit(warn, &dev->warnings)) \
printk(KERN_INFO "uvcvideo: " msg); \
} while (0)
#define uvc_printk(level, msg...) \
printk(level "uvcvideo: " msg)
#endif
/* --------------------------------------------------------------------------
* Internal functions.
*/
/* Core driver */
extern struct uvc_driver uvc_driver;
extern struct uvc_entity *uvc_entity_by_id(struct uvc_device *dev, int id);
/* Video buffers queue management. */
extern int uvc_queue_init(struct uvc_video_queue *queue,
enum v4l2_buf_type type, int drop_corrupted);
extern int uvc_alloc_buffers(struct uvc_video_queue *queue,
struct v4l2_requestbuffers *rb);
extern void uvc_free_buffers(struct uvc_video_queue *queue);
extern int uvc_query_buffer(struct uvc_video_queue *queue,
struct v4l2_buffer *v4l2_buf);
extern int uvc_queue_buffer(struct uvc_video_queue *queue,
struct v4l2_buffer *v4l2_buf);
extern int uvc_dequeue_buffer(struct uvc_video_queue *queue,
struct v4l2_buffer *v4l2_buf, int nonblocking);
extern int uvc_queue_enable(struct uvc_video_queue *queue, int enable);
extern void uvc_queue_cancel(struct uvc_video_queue *queue, int disconnect);
extern struct uvc_buffer *uvc_queue_next_buffer(struct uvc_video_queue *queue,
struct uvc_buffer *buf);
extern int uvc_queue_mmap(struct uvc_video_queue *queue);
#if 0
extern unsigned int uvc_queue_poll(struct uvc_video_queue *queue,
struct file *file, poll_table *wait);
#endif
#ifndef CONFIG_MMU
extern unsigned long uvc_queue_get_unmapped_area(struct uvc_video_queue *queue,
unsigned long pgoff);
#endif
extern int uvc_queue_allocated(struct uvc_video_queue *queue);
static inline int uvc_queue_streaming(struct uvc_video_queue *queue)
{
return vb2_is_streaming(&queue->queue);
}
/* V4L2 interface */
extern const struct v4l2_file_operations uvc_fops;
/* Media controller */
extern int uvc_mc_register_entities(struct uvc_video_chain *chain);
extern void uvc_mc_cleanup_entity(struct uvc_entity *entity);
/* Video */
extern int uvc_video_init(struct uvc_streaming *stream);
extern int uvc_video_suspend(struct uvc_streaming *stream);
extern int uvc_video_resume(struct uvc_streaming *stream, int reset);
extern int uvc_video_enable(struct uvc_streaming *stream, int enable);
extern int uvc_probe_video(struct uvc_streaming *stream,
struct uvc_streaming_control *probe);
/* edit by Ian -- patch for GEO */
extern int uvc_commit_video(struct uvc_streaming *stream,
struct uvc_streaming_control *probe);
extern int uvc_query_ctrl(struct uvc_device *dev, __u8 query, __u8 unit,
__u8 intfnum, __u8 cs, void *data, __u16 size);
/* edit by Ian -- disable uvc clock api*/
#if 0
void uvc_video_clock_update(struct uvc_streaming *stream,
struct v4l2_buffer *v4l2_buf,
struct uvc_buffer *buf);
#endif
/* Status */
//#define UVC_STATUS_EN
#ifdef UVC_STATUS_EN
extern int uvc_status_init(struct uvc_device *dev);
extern void uvc_status_cleanup(struct uvc_device *dev);
extern int uvc_status_start(struct uvc_device *dev, gfp_t flags);
extern void uvc_status_stop(struct uvc_device *dev);
#endif
/* Controls */
extern const struct v4l2_subscribed_event_ops uvc_ctrl_sub_ev_ops;
extern int uvc_query_v4l2_ctrl(struct uvc_video_chain *chain,
struct v4l2_queryctrl *v4l2_ctrl);
extern int uvc_query_v4l2_menu(struct uvc_video_chain *chain,
struct v4l2_querymenu *query_menu);
extern int uvc_ctrl_add_mapping(struct uvc_video_chain *chain,
const struct uvc_control_mapping *mapping);
extern int uvc_ctrl_init_device(struct uvc_device *dev);
extern void uvc_ctrl_cleanup_device(struct uvc_device *dev);
extern int uvc_ctrl_resume_device(struct uvc_device *dev);
extern int uvc_ctrl_begin(struct uvc_video_chain *chain);
extern int __uvc_ctrl_commit(struct uvc_fh *handle, int rollback,
const struct v4l2_ext_control *xctrls,
unsigned int xctrls_count);
static inline int uvc_ctrl_commit(struct uvc_fh *handle,
const struct v4l2_ext_control *xctrls,
unsigned int xctrls_count)
{
return __uvc_ctrl_commit(handle, 0, xctrls, xctrls_count);
}
static inline int uvc_ctrl_rollback(struct uvc_fh *handle)
{
return __uvc_ctrl_commit(handle, 1, NULL, 0);
}
extern int uvc_ctrl_get(struct uvc_video_chain *chain,
struct v4l2_ext_control *xctrl);
extern int uvc_ctrl_set(struct uvc_video_chain *chain,
struct v4l2_ext_control *xctrl);
//edit by Ian -- remove uvc_xu_ctrl_query declaration
//extern int uvc_xu_ctrl_query(struct uvc_video_chain *chain, struct uvc_xu_control_query *xqry);
/* Utility functions */
extern void uvc_simplify_fraction(uint32_t *numerator, uint32_t *denominator,
unsigned int n_terms, unsigned int threshold);
extern uint32_t uvc_fraction_to_interval(uint32_t numerator,
uint32_t denominator);
extern struct usb_host_endpoint *uvc_find_endpoint(
struct usb_host_interface *alts, __u8 epaddr);
/* Quirks support */
void uvc_video_decode_isight(struct urb *urb, struct uvc_streaming *stream,
struct uvc_buffer *buf);
/* debugfs and statistics */
#if 0
int uvc_debugfs_init(void);
void uvc_debugfs_cleanup(void);
int uvc_debugfs_init_stream(struct uvc_streaming *stream);
void uvc_debugfs_cleanup_stream(struct uvc_streaming *stream);
size_t uvc_video_stats_dump(struct uvc_streaming *stream, char *buf,
size_t size);
#endif
#endif

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component/common/drivers/usb_class/host/uvc/inc/video.h Executable file
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@ -0,0 +1,725 @@
/*
* USB Video Class definitions.
*
* Copyright (C) 2009 Laurent Pinchart <laurent.pinchart@skynet.be>
*
* This file holds USB constants and structures defined by the USB Device
* Class Definition for Video Devices. Unless otherwise stated, comments
* below reference relevant sections of the USB Video Class 1.1 specification
* available at
*
* http://www.usb.org/developers/devclass_docs/USB_Video_Class_1_1.zip
*/
#ifndef __LINUX_USB_VIDEO_H
#define __LINUX_USB_VIDEO_H
#if 0
#include <linux/types.h>
#endif
/* --------------------------------------------------------------------------
* UVC constants
*/
/* A.2. Video Interface Subclass Codes */
#define UVC_SC_UNDEFINED 0x00
#define UVC_SC_VIDEOCONTROL 0x01
#define UVC_SC_VIDEOSTREAMING 0x02
#define UVC_SC_VIDEO_INTERFACE_COLLECTION 0x03
/* A.3. Video Interface Protocol Codes */
#define UVC_PC_PROTOCOL_UNDEFINED 0x00
/* A.5. Video Class-Specific VC Interface Descriptor Subtypes */
#define UVC_VC_DESCRIPTOR_UNDEFINED 0x00
#define UVC_VC_HEADER 0x01
#define UVC_VC_INPUT_TERMINAL 0x02
#define UVC_VC_OUTPUT_TERMINAL 0x03
#define UVC_VC_SELECTOR_UNIT 0x04
#define UVC_VC_PROCESSING_UNIT 0x05
#define UVC_VC_EXTENSION_UNIT 0x06
/* A.6. Video Class-Specific VS Interface Descriptor Subtypes */
#define UVC_VS_UNDEFINED 0x00
#define UVC_VS_INPUT_HEADER 0x01
#define UVC_VS_OUTPUT_HEADER 0x02
#define UVC_VS_STILL_IMAGE_FRAME 0x03
#define UVC_VS_FORMAT_UNCOMPRESSED 0x04
#define UVC_VS_FRAME_UNCOMPRESSED 0x05
#define UVC_VS_FORMAT_MJPEG 0x06
#define UVC_VS_FRAME_MJPEG 0x07
#define UVC_VS_FORMAT_MPEG2TS 0x0a
#define UVC_VS_FORMAT_DV 0x0c
#define UVC_VS_COLORFORMAT 0x0d
#define UVC_VS_FORMAT_FRAME_BASED 0x10
#define UVC_VS_FRAME_FRAME_BASED 0x11
#define UVC_VS_FORMAT_STREAM_BASED 0x12
/* A.7. Video Class-Specific Endpoint Descriptor Subtypes */
#define UVC_EP_UNDEFINED 0x00
#define UVC_EP_GENERAL 0x01
#define UVC_EP_ENDPOINT 0x02
#define UVC_EP_INTERRUPT 0x03
/* A.8. Video Class-Specific Request Codes */
#define UVC_RC_UNDEFINED 0x00
#define UVC_SET_CUR 0x01
#define UVC_GET_CUR 0x81
#define UVC_GET_MIN 0x82
#define UVC_GET_MAX 0x83
#define UVC_GET_RES 0x84
#define UVC_GET_LEN 0x85
#define UVC_GET_INFO 0x86
#define UVC_GET_DEF 0x87
/* A.9.1. VideoControl Interface Control Selectors */
#define UVC_VC_CONTROL_UNDEFINED 0x00
#define UVC_VC_VIDEO_POWER_MODE_CONTROL 0x01
#define UVC_VC_REQUEST_ERROR_CODE_CONTROL 0x02
/* A.9.2. Terminal Control Selectors */
#define UVC_TE_CONTROL_UNDEFINED 0x00
/* A.9.3. Selector Unit Control Selectors */
#define UVC_SU_CONTROL_UNDEFINED 0x00
#define UVC_SU_INPUT_SELECT_CONTROL 0x01
/* A.9.4. Camera Terminal Control Selectors */
#define UVC_CT_CONTROL_UNDEFINED 0x00
#define UVC_CT_SCANNING_MODE_CONTROL 0x01
#define UVC_CT_AE_MODE_CONTROL 0x02
#define UVC_CT_AE_PRIORITY_CONTROL 0x03
#define UVC_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x04
#define UVC_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x05
#define UVC_CT_FOCUS_ABSOLUTE_CONTROL 0x06
#define UVC_CT_FOCUS_RELATIVE_CONTROL 0x07
#define UVC_CT_FOCUS_AUTO_CONTROL 0x08
#define UVC_CT_IRIS_ABSOLUTE_CONTROL 0x09
#define UVC_CT_IRIS_RELATIVE_CONTROL 0x0a
#define UVC_CT_ZOOM_ABSOLUTE_CONTROL 0x0b
#define UVC_CT_ZOOM_RELATIVE_CONTROL 0x0c
#define UVC_CT_PANTILT_ABSOLUTE_CONTROL 0x0d
#define UVC_CT_PANTILT_RELATIVE_CONTROL 0x0e
#define UVC_CT_ROLL_ABSOLUTE_CONTROL 0x0f
#define UVC_CT_ROLL_RELATIVE_CONTROL 0x10
#define UVC_CT_PRIVACY_CONTROL 0x11
/* A.9.5. Processing Unit Control Selectors */
#define UVC_PU_CONTROL_UNDEFINED 0x00
#define UVC_PU_BACKLIGHT_COMPENSATION_CONTROL 0x01
#define UVC_PU_BRIGHTNESS_CONTROL 0x02
#define UVC_PU_CONTRAST_CONTROL 0x03
#define UVC_PU_GAIN_CONTROL 0x04
#define UVC_PU_POWER_LINE_FREQUENCY_CONTROL 0x05
#define UVC_PU_HUE_CONTROL 0x06
#define UVC_PU_SATURATION_CONTROL 0x07
#define UVC_PU_SHARPNESS_CONTROL 0x08
#define UVC_PU_GAMMA_CONTROL 0x09
#define UVC_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x0a
#define UVC_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x0b
#define UVC_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x0c
#define UVC_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x0d
#define UVC_PU_DIGITAL_MULTIPLIER_CONTROL 0x0e
#define UVC_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x0f
#define UVC_PU_HUE_AUTO_CONTROL 0x10
#define UVC_PU_ANALOG_VIDEO_STANDARD_CONTROL 0x11
#define UVC_PU_ANALOG_LOCK_STATUS_CONTROL 0x12
/* A.9.7. VideoStreaming Interface Control Selectors */
#define UVC_VS_CONTROL_UNDEFINED 0x00
#define UVC_VS_PROBE_CONTROL 0x01
#define UVC_VS_COMMIT_CONTROL 0x02
#define UVC_VS_STILL_PROBE_CONTROL 0x03
#define UVC_VS_STILL_COMMIT_CONTROL 0x04
#define UVC_VS_STILL_IMAGE_TRIGGER_CONTROL 0x05
#define UVC_VS_STREAM_ERROR_CODE_CONTROL 0x06
#define UVC_VS_GENERATE_KEY_FRAME_CONTROL 0x07
#define UVC_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x08
#define UVC_VS_SYNC_DELAY_CONTROL 0x09
/* B.1. USB Terminal Types */
#define UVC_TT_VENDOR_SPECIFIC 0x0100
#define UVC_TT_STREAMING 0x0101
/* B.2. Input Terminal Types */
#define UVC_ITT_VENDOR_SPECIFIC 0x0200
#define UVC_ITT_CAMERA 0x0201
#define UVC_ITT_MEDIA_TRANSPORT_INPUT 0x0202
/* B.3. Output Terminal Types */
#define UVC_OTT_VENDOR_SPECIFIC 0x0300
#define UVC_OTT_DISPLAY 0x0301
#define UVC_OTT_MEDIA_TRANSPORT_OUTPUT 0x0302
/* B.4. External Terminal Types */
#define UVC_EXTERNAL_VENDOR_SPECIFIC 0x0400
#define UVC_COMPOSITE_CONNECTOR 0x0401
#define UVC_SVIDEO_CONNECTOR 0x0402
#define UVC_COMPONENT_CONNECTOR 0x0403
/* 2.4.2.2. Status Packet Type */
#define UVC_STATUS_TYPE_CONTROL 1
#define UVC_STATUS_TYPE_STREAMING 2
/* 2.4.3.3. Payload Header Information */
#define UVC_STREAM_EOH (1 << 7)
#define UVC_STREAM_ERR (1 << 6)
#define UVC_STREAM_STI (1 << 5)
#define UVC_STREAM_RES (1 << 4)
#define UVC_STREAM_SCR (1 << 3)
#define UVC_STREAM_PTS (1 << 2)
#define UVC_STREAM_EOF (1 << 1)
#define UVC_STREAM_FID (1 << 0)
/* 4.1.2. Control Capabilities */
#define UVC_CONTROL_CAP_GET (1 << 0)
#define UVC_CONTROL_CAP_SET (1 << 1)
#define UVC_CONTROL_CAP_DISABLED (1 << 2)
#define UVC_CONTROL_CAP_AUTOUPDATE (1 << 3)
#define UVC_CONTROL_CAP_ASYNCHRONOUS (1 << 4)
/* ------------------------------------------------------------------------
* UVC structures
*/
/* All UVC descriptors have these 3 fields at the beginning */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_descriptor_header {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
} //__attribute__((packed));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
/* 3.7.2. Video Control Interface Header Descriptor */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_header_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u16 bcdUVC;
__u16 wTotalLength;
__u32 dwClockFrequency;
__u8 bInCollection;
__u8 baInterfaceNr[];
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_HEADER_SIZE(n) (12+(n))
#define UVC_HEADER_DESCRIPTOR(n) \
uvc_header_descriptor_##n
#define DECLARE_UVC_HEADER_DESCRIPTOR(n) \
struct UVC_HEADER_DESCRIPTOR(n) { \
__u8 bLength; \
__u8 bDescriptorType; \
__u8 bDescriptorSubType; \
__u16 bcdUVC; \
__u16 wTotalLength; \
__u32 dwClockFrequency; \
__u8 bInCollection; \
__u8 baInterfaceNr[n]; \
} __attribute__ ((packed))
/* 3.7.2.1. Input Terminal Descriptor */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_input_terminal_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u8 bTerminalID;
__u16 wTerminalType;
__u8 bAssocTerminal;
__u8 iTerminal;
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_INPUT_TERMINAL_SIZE 8
/* 3.7.2.2. Output Terminal Descriptor */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_output_terminal_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u8 bTerminalID;
__u16 wTerminalType;
__u8 bAssocTerminal;
__u8 bSourceID;
__u8 iTerminal;
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_OUTPUT_TERMINAL_SIZE 9
/* 3.7.2.3. Camera Terminal Descriptor */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_camera_terminal_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u8 bTerminalID;
__u16 wTerminalType;
__u8 bAssocTerminal;
__u8 iTerminal;
__u16 wObjectiveFocalLengthMin;
__u16 wObjectiveFocalLengthMax;
__u16 wOcularFocalLength;
__u8 bControlSize;
__u8 bmControls[3];
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_CAMERA_TERMINAL_SIZE(n) (15+(n))
/* 3.7.2.4. Selector Unit Descriptor */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_selector_unit_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u8 bUnitID;
__u8 bNrInPins;
// __u8 baSourceID[0];
__u8 * baSourceID;
__u8 iSelector;
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_SELECTOR_UNIT_SIZE(n) (6+(n))
#define UVC_SELECTOR_UNIT_DESCRIPTOR(n) \
uvc_selector_unit_descriptor_##n
#define DECLARE_UVC_SELECTOR_UNIT_DESCRIPTOR(n) \
struct UVC_SELECTOR_UNIT_DESCRIPTOR(n) { \
__u8 bLength; \
__u8 bDescriptorType; \
__u8 bDescriptorSubType; \
__u8 bUnitID; \
__u8 bNrInPins; \
__u8 baSourceID[n]; \
__u8 iSelector; \
} __attribute__ ((packed))
/* 3.7.2.5. Processing Unit Descriptor */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_processing_unit_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u8 bUnitID;
__u8 bSourceID;
__u16 wMaxMultiplier;
__u8 bControlSize;
__u8 bmControls[2];
__u8 iProcessing;
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_PROCESSING_UNIT_SIZE(n) (9+(n))
/* 3.7.2.6. Extension Unit Descriptor */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_extension_unit_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u8 bUnitID;
__u8 guidExtensionCode[16];
__u8 bNumControls;
__u8 bNrInPins;
// __u8 baSourceID[0];
__u8 * baSourceID;
__u8 bControlSize;
// __u8 bmControls[0];
__u8 * bmControls;
__u8 iExtension;
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_EXTENSION_UNIT_SIZE(p, n) (24+(p)+(n))
#define UVC_EXTENSION_UNIT_DESCRIPTOR(p, n) \
uvc_extension_unit_descriptor_##p_##n
#define DECLARE_UVC_EXTENSION_UNIT_DESCRIPTOR(p, n) \
struct UVC_EXTENSION_UNIT_DESCRIPTOR(p, n) { \
__u8 bLength; \
__u8 bDescriptorType; \
__u8 bDescriptorSubType; \
__u8 bUnitID; \
__u8 guidExtensionCode[16]; \
__u8 bNumControls; \
__u8 bNrInPins; \
__u8 baSourceID[p]; \
__u8 bControlSize; \
__u8 bmControls[n]; \
__u8 iExtension; \
} __attribute__ ((packed))
/* 3.8.2.2. Video Control Interrupt Endpoint Descriptor */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_control_endpoint_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u16 wMaxTransferSize;
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_CONTROL_ENDPOINT_SIZE 5
/* 3.9.2.1. Input Header Descriptor */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_input_header_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u8 bNumFormats;
__u16 wTotalLength;
__u8 bEndpointAddress;
__u8 bmInfo;
__u8 bTerminalLink;
__u8 bStillCaptureMethod;
__u8 bTriggerSupport;
__u8 bTriggerUsage;
__u8 bControlSize;
__u8 bmaControls[];
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_INPUT_HEADER_SIZE(n, p) (13+(n*p))
#define UVC_INPUT_HEADER_DESCRIPTOR(n, p) \
uvc_input_header_descriptor_##n_##p
#define DECLARE_UVC_INPUT_HEADER_DESCRIPTOR(n, p) \
struct UVC_INPUT_HEADER_DESCRIPTOR(n, p) { \
__u8 bLength; \
__u8 bDescriptorType; \
__u8 bDescriptorSubType; \
__u8 bNumFormats; \
__u16 wTotalLength; \
__u8 bEndpointAddress; \
__u8 bmInfo; \
__u8 bTerminalLink; \
__u8 bStillCaptureMethod; \
__u8 bTriggerSupport; \
__u8 bTriggerUsage; \
__u8 bControlSize; \
__u8 bmaControls[p][n]; \
} __attribute__ ((packed))
/* 3.9.2.2. Output Header Descriptor */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_output_header_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u8 bNumFormats;
__u16 wTotalLength;
__u8 bEndpointAddress;
__u8 bTerminalLink;
__u8 bControlSize;
__u8 bmaControls[];
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_OUTPUT_HEADER_SIZE(n, p) (9+(n*p))
#define UVC_OUTPUT_HEADER_DESCRIPTOR(n, p) \
uvc_output_header_descriptor_##n_##p
#define DECLARE_UVC_OUTPUT_HEADER_DESCRIPTOR(n, p) \
struct UVC_OUTPUT_HEADER_DESCRIPTOR(n, p) { \
__u8 bLength; \
__u8 bDescriptorType; \
__u8 bDescriptorSubType; \
__u8 bNumFormats; \
__u16 wTotalLength; \
__u8 bEndpointAddress; \
__u8 bTerminalLink; \
__u8 bControlSize; \
__u8 bmaControls[p][n]; \
} __attribute__ ((packed))
/* 3.9.2.6. Color matching descriptor */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_color_matching_descriptor {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u8 bColorPrimaries;
__u8 bTransferCharacteristics;
__u8 bMatrixCoefficients;
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_COLOR_MATCHING_SIZE 6
/* 4.3.1.1. Video Probe and Commit Controls */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_streaming_control {
__u16 bmHint;
__u8 bFormatIndex;
__u8 bFrameIndex;
__u32 dwFrameInterval;
__u16 wKeyFrameRate;
__u16 wPFrameRate;
__u16 wCompQuality;
__u16 wCompWindowSize;
__u16 wDelay;
__u32 dwMaxVideoFrameSize;
__u32 dwMaxPayloadTransferSize;
__u32 dwClockFrequency;
__u8 bmFramingInfo;
__u8 bPreferedVersion;
__u8 bMinVersion;
__u8 bMaxVersion;
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
/* Uncompressed Payload - 3.1.1. Uncompressed Video Format Descriptor */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_format_uncompressed {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u8 bFormatIndex;
__u8 bNumFrameDescriptors;
__u8 guidFormat[16];
__u8 bBitsPerPixel;
__u8 bDefaultFrameIndex;
__u8 bAspectRatioX;
__u8 bAspectRatioY;
__u8 bmInterfaceFlags;
__u8 bCopyProtect;
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_FORMAT_UNCOMPRESSED_SIZE 27
/* Uncompressed Payload - 3.1.2. Uncompressed Video Frame Descriptor */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_frame_uncompressed {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u8 bFrameIndex;
__u8 bmCapabilities;
__u16 wWidth;
__u16 wHeight;
__u32 dwMinBitRate;
__u32 dwMaxBitRate;
__u32 dwMaxVideoFrameBufferSize;
__u32 dwDefaultFrameInterval;
__u8 bFrameIntervalType;
__u32 dwFrameInterval[];
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_FRAME_UNCOMPRESSED_SIZE(n) (26+4*(n))
#define UVC_FRAME_UNCOMPRESSED(n) \
uvc_frame_uncompressed_##n
#define DECLARE_UVC_FRAME_UNCOMPRESSED(n) \
struct UVC_FRAME_UNCOMPRESSED(n) { \
__u8 bLength; \
__u8 bDescriptorType; \
__u8 bDescriptorSubType; \
__u8 bFrameIndex; \
__u8 bmCapabilities; \
__u16 wWidth; \
__u16 wHeight; \
__u32 dwMinBitRate; \
__u32 dwMaxBitRate; \
__u32 dwMaxVideoFrameBufferSize; \
__u32 dwDefaultFrameInterval; \
__u8 bFrameIntervalType; \
__u32 dwFrameInterval[n]; \
} __attribute__ ((packed))
/* MJPEG Payload - 3.1.1. MJPEG Video Format Descriptor */
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
struct uvc_format_mjpeg {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u8 bFormatIndex;
__u8 bNumFrameDescriptors;
__u8 bmFlags;
__u8 bDefaultFrameIndex;
__u8 bAspectRatioX;
__u8 bAspectRatioY;
__u8 bmInterfaceFlags;
__u8 bCopyProtect;
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_FORMAT_MJPEG_SIZE 11
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_begin.h"
#endif
RTW_PACK_STRUCT_BEGIN
/* MJPEG Payload - 3.1.2. MJPEG Video Frame Descriptor */
struct uvc_frame_mjpeg {
__u8 bLength;
__u8 bDescriptorType;
__u8 bDescriptorSubType;
__u8 bFrameIndex;
__u8 bmCapabilities;
__u16 wWidth;
__u16 wHeight;
__u32 dwMinBitRate;
__u32 dwMaxBitRate;
__u32 dwMaxVideoFrameBufferSize;
__u32 dwDefaultFrameInterval;
__u8 bFrameIntervalType;
__u32 dwFrameInterval[];
} //__attribute__((__packed__));
RTW_PACK_STRUCT_STRUCT;
RTW_PACK_STRUCT_END
#ifdef RTW_PACK_STRUCT_USE_INCLUDES
# include "pack_end.h"
#endif
#define UVC_DT_FRAME_MJPEG_SIZE(n) (26+4*(n))
#define UVC_FRAME_MJPEG(n) \
uvc_frame_mjpeg_##n
#define DECLARE_UVC_FRAME_MJPEG(n) \
struct UVC_FRAME_MJPEG(n) { \
__u8 bLength; \
__u8 bDescriptorType; \
__u8 bDescriptorSubType; \
__u8 bFrameIndex; \
__u8 bmCapabilities; \
__u16 wWidth; \
__u16 wHeight; \
__u32 dwMinBitRate; \
__u32 dwMaxBitRate; \
__u32 dwMaxVideoFrameBufferSize; \
__u32 dwDefaultFrameInterval; \
__u8 bFrameIntervalType; \
__u32 dwFrameInterval[n]; \
} __attribute__ ((packed))
#endif /* __LINUX_USB_VIDEO_H */

508
component/common/drivers/wlan/realtek/include/autoconf.h Executable file
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#ifndef WLANCONFIG_H
#define WLANCONFIG_H
/*
* Include user defined options first. Anything not defined in these files
* will be set to standard values. Override anything you dont like!
*/
#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) || defined(CONFIG_HARDWARE_8188F)
#include "platform_opts.h"
#endif
#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
#define CONFIG_PLATFORM_AMEBA_X
#endif
#if !defined(CONFIG_PLATFORM_AMEBA_X)
#define PLATFORM_FREERTOS 1
#define CONFIG_GSPI_HCI
#else
#define CONFIG_LX_HCI
#endif
#ifndef CONFIG_INIC_EN
#define CONFIG_INIC_EN 0 //For iNIC project
#endif
#if CONFIG_INIC_EN
#define CONFIG_LWIP_LAYER 0
#endif
#define CONFIG_LITTLE_ENDIAN
#define CONFIG_80211N_HT
//#define CONFIG_RECV_REORDERING_CTRL
#define RTW_NOTCH_FILTER 0
#define CONFIG_EMBEDDED_FWIMG
#define CONFIG_PHY_SETTING_WITH_ODM
#if !defined(CONFIG_PLATFORM_AMEBA_X)
#define CONFIG_ODM_REFRESH_RAMASK
#define HAL_MAC_ENABLE 1
#define HAL_BB_ENABLE 1
#define HAL_RF_ENABLE 1
#endif
#if defined(CONFIG_PLATFORM_AMEBA_X)
/* Patch when dynamic mechanism is not ready */
//#define CONFIG_DM_PATCH
#endif
//#define CONFIG_DEBUG
//#define CONFIG_DEBUG_RTL871X
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define CONFIG_MEM_MONITOR MEM_MONITOR_SIMPLE
#define WLAN_INTF_DBG 0
//#define CONFIG_DEBUG_DYNAMIC
//#define DBG_TX 1
//#define DBG_XMIT_BUF 1
//#define DBG_XMIT_BUF_EXT 1
#define DBG_TX_DROP_FRAME
#else
#define CONFIG_MEM_MONITOR MEM_MONITOR_LEAK
//#define CONFIG_TRACE_SKB
//#define WLAN_INTF_DBG
#endif // CONFIG_PLATFORM_AMEBA_X
//#define CONFIG_DONT_CARE_TP
//#define CONFIG_HIGH_TP
//#define CONFIG_MEMORY_ACCESS_ALIGNED
#define CONFIG_POWER_SAVING
#ifdef CONFIG_POWER_SAVING
#define CONFIG_IPS
#define CONFIG_LPS
//#define CONFIG_LPS_LCLK
#define CONFIG_LPS_32K
#define TDMA_POWER_SAVING
#define CONFIG_WAIT_PS_ACK
#endif
#define BAD_MIC_COUNTERMEASURE 1
#define DEFRAGMENTATION 1
#define WIFI_LOGO_CERTIFICATION 0
#if WIFI_LOGO_CERTIFICATION
#define RX_AGGREGATION 1
#define RX_AMSDU 1
#else
#define RX_AGGREGATION 0
#define RX_AMSDU 0
#endif
#if defined(CONFIG_PLATFORM_AMEBA_X)
#if !defined(CONFIG_PLATFORM_8711B)
#define CONFIG_USE_TCM_HEAP 1 /* USE TCM HEAP */
#endif
#define CONFIG_RECV_TASKLET_THREAD
#define CONFIG_XMIT_TASKLET_THREAD
#else
#define CONFIG_XMIT_THREAD_MODE
#endif // CONFIG_PLATFORM_AMEBA_X
//#define CONFIG_RECV_THREAD_MODE /* Wlan IRQ Polling Mode*/
//#define CONFIG_ISR_THREAD_MODE_POLLING /* Wlan IRQ Polling Mode*/
//1 Chris
#ifndef CONFIG_SDIO_HCI
#define CONFIG_ISR_THREAD_MODE_INTERRUPT /* Wlan IRQ Interrupt Mode*/
#endif
#if defined(CONFIG_ISR_THREAD_MODE_POLLING) && defined(CONFIG_ISR_THREAD_MODE_INTERRUPT)
#error "CONFIG_ISR_THREAD_MODE_POLLING and CONFIG_ISR_THREAD_MODE_INTERRUPT are mutually exclusive. "
#endif
#if defined(CONFIG_PLATFORM_AMEBA_X)
/* CRC DMEM optimized mode consume 1k less SRM memory consumption */
#define CRC_IMPLEMENTATION_MODE CRC_IMPLEMENTATION_DMEM_OPTIMIZED
#endif
/* AES DMEM optimized mode comsume 10k less memory compare to
IMEM optimized mode AES_IMPLEMENTATION_IMEM_OPTIMIZED */
#define AES_IMPLEMENTATION_MODE AES_IMPLEMENTATION_DMEM_OPTIMIZED
#define USE_SKB_AS_XMITBUF 1
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define USE_XMIT_EXTBUFF 1
#else
#define USE_XMIT_EXTBUFF 0
#endif
#define USE_MUTEX_FOR_SPINLOCK 1
// remove function to reduce code
#define NOT_SUPPORT_5G
#define NOT_SUPPORT_RF_MULTIPATH
#define NOT_SUPPORT_VHT
#define NOT_SUPPORT_40M
#define NOT_SUPPORT_80M
#ifndef CONFIG_PLATFORM_8711B
#define NOT_SUPPORT_BBSWING
#endif
#define NOT_SUPPORT_OLD_CHANNEL_PLAN
#define NOT_SUPPORT_BT
#define CONFIG_WIFI_SPEC 0
#define CONFIG_FAKE_EFUSE 0
#if CONFIG_FAKE_EFUSE
#define FAKE_CHIPID CHIPID_8710BN
#endif
#define CONFIG_AUTO_RECONNECT 1
#define ENABLE_HWPDN_PIN
#define SUPPORT_SCAN_BUF 1
#if !defined(CONFIG_PLATFORM_AMEBA_X)
#define BE_I_CUT 1
#endif
/* For WPA2 */
#define CONFIG_INCLUDE_WPA_PSK
#ifdef CONFIG_INCLUDE_WPA_PSK
#define CONFIG_MULTIPLE_WPA_STA
//#define CONFIG_WPA2_PREAUTH
#define PSK_SUPPORT_TKIP 1
#endif
//#define AP_PSK_SUPPORT_TKIP
/* For promiscuous mode */
#define CONFIG_PROMISC
#define PROMISC_DENY_PAIRWISE 0
/* For Simple Link */
#ifndef CONFIG_INCLUDE_SIMPLE_CONFIG
//#define CONFIG_INCLUDE_SIMPLE_CONFIG 1
#endif
// for probe request with custom vendor specific IE
#define CONFIG_CUSTOM_IE
#if !defined(CONFIG_PLATFORM_AMEBA_X)
/* For multicast */
#define CONFIG_MULTICAST
#endif
/* For STA+AP Concurrent MODE */
#define CONFIG_CONCURRENT_MODE
#ifdef CONFIG_CONCURRENT_MODE
#if defined(CONFIG_PLATFORM_8195A)
#define CONFIG_RUNTIME_PORT_SWITCH
#endif
#if defined(CONFIG_HARDWARE_8188F)
#define NET_IF_NUM 2
#else
#define NET_IF_NUM ((CONFIG_ETHERNET) + (CONFIG_WLAN) + 1)
#endif
#else
#if defined(CONFIG_HARDWARE_8188F)
#define NET_IF_NUM 1
#else
#define NET_IF_NUM ((CONFIG_ETHERNET) + (CONFIG_WLAN))
#endif
#endif
/****************** For EAP auth configurations *******************/
#define CONFIG_TLS 0
#define CONFIG_PEAP 0
#define CONFIG_TTLS 0
// DO NOT change the below config of EAP
#ifdef PRE_CONFIG_EAP
#undef CONFIG_TLS
#define CONFIG_TLS 1
#undef CONFIG_PEAP
#define CONFIG_PEAP 1
#undef CONFIG_TTLS
#define CONFIG_TTLS 1
#endif
// enable 1X code in lib_wlan as default (increase 380 bytes)
#define CONFIG_EAP
#if CONFIG_TLS || CONFIG_PEAP || CONFIG_TTLS
#define EAP_REMOVE_UNUSED_CODE 1
#endif
#define EAP_SSL_VERIFY_SERVER
#if CONFIG_TLS
#define EAP_SSL_VERIFY_CLIENT
#endif
#if CONFIG_TTLS
#define EAP_MSCHAPv2
#define EAP_TTLS_MSCHAPv2
//#define EAP_TTLS_EAP
//#define EAP_TTLS_MSCHAP
//#define EAP_TTLS_PAP
//#define EAP_TTLS_CHAP
#endif
/****************** End of EAP configurations *******************/
/* For WPS and P2P */
#define CONFIG_WPS
#if 0
#define CONFIG_WPS_AP
#define CONFIG_P2P_NEW
#if (!defined(SUPPORT_SCAN_BUF)||!defined(CONFIG_WPS_AP)) && defined(CONFIG_P2P_NEW)
#error "If CONFIG_P2P_NEW, need to SUPPORT_SCAN_BUF"
#endif
#endif
#define CONFIG_NEW_SIGNAL_STAT_PROCESS
#define CONFIG_SKIP_SIGNAL_SCALE_MAPPING
/* For AP_MODE */
#define CONFIG_AP_MODE
extern unsigned char g_user_ap_sta_num;
#define USER_AP_STA_NUM g_user_ap_sta_num
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define AP_STA_NUM 3 //2014/10/27 modify to 3
#define USE_DEDICATED_BCN_TX 0
#if USE_DEDICATED_BCN_TX
#error "WLAN driver for Ameba should not enable USE_DEDICATED_BCN_TX"
#endif
#else
extern unsigned int g_ap_sta_num;
#define AP_STA_NUM 3//g_ap_sta_num
#endif
#ifdef CONFIG_AP_MODE
#if defined(CONFIG_PLATFORM_8195A)
//softap sent qos null0 polling client alive or not
#define CONFIG_AP_POLLING_CLIENT_ALIVE
#endif
#define CONFIG_NATIVEAP_MLME
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define CONFIG_INTERRUPT_BASED_TXBCN
#endif
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
//#define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
#define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
#endif
// #define CONFIG_GK_REKEY
#if !defined(CONFIG_PLATFORM_AMEBA_X)
#define USE_DEDICATED_BCN_TX 1
#endif
#if CONFIG_INIC_EN
// #define REPORT_STA_EVENT //useless
#endif
#else
#if !defined(CONFIG_PLATFORM_AMEBA_X)
#define USE_DEDICATED_BCN_TX 0
#endif
#endif
#if defined(CONFIG_AP_MODE) && defined(CONFIG_GK_REKEY) && !defined(CONFIG_MULTIPLE_WPA_STA)
#error "If CONFIG_GK_REKEY when CONFIG_AP_MODE, need to CONFIG_MULTIPLE_WPA_STA"
#endif
#if !defined(CONFIG_PLATFORM_AMEBA_X)
#if !defined(CONFIG_AP_MODE) && defined(CONFIG_CONCURRENT_MODE)
#error "If CONFIG_CONCURRENT_MODEE, need to CONFIG_AP_MODE"
#endif
#endif
/* For efuse or flash config */
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define CONFIG_RW_PHYSICAL_EFUSE 0 // Mask efuse user blocks
#define CONFIG_HIDE_PROTECT_EFUSE 1
#define CONFIG_ADAPTOR_INFO_CACHING_FLASH 1
#define CHECK_FLASH_VALID_MASK 1
#define CHECK_EFUSE_VALID_MASK 1
/* For K-free */
// #if !defined(CONFIG_PLATFORM_8711B)
#define CONFIG_RF_GAIN_OFFSET
// #endif
#endif // CONFIG_PLATFORM_AMEBA_X
/* For MP_MODE */
//#define CONFIG_MP_INCLUDED
#ifdef CONFIG_MP_INCLUDED
#define MP_DRIVER 1
#define CONFIG_MP_IWPRIV_SUPPORT
// #define HAL_EFUSE_MEMORY
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define MP_REG_TEST
#endif
#else
#define MP_DRIVER 0
#if defined(CONFIG_PLATFORM_8195A)
//Control wifi mcu function
#define CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD
#define CONFIG_ODM_REFRESH_RAMASK
//#define CONFIG_ANTENNA_DIVERSITY
//#define CONFIG_BT_COEXIST
#endif
#endif // #ifdef CONFIG_MP_INCLUDED
#ifdef CONFIG_BT_COEXIST
#undef NOT_SUPPORT_BT
#define CONFIG_BT_MAILBOX
//#define CONFIG_BT_TWO_ANTENNA
#endif
#if defined(CONFIG_PLATFORM_AMEBA_X)
#if defined(CONFIG_PLATFORM_8195A)
#undef CONFIG_RTL8195A
#define CONFIG_RTL8195A
#endif
#if defined(CONFIG_PLATFORM_8711B)
#ifndef CONFIG_RTL8711B
#define CONFIG_RTL8711B
#endif
#undef CONFIG_ADAPTOR_INFO_CACHING_FLASH
#define CONFIG_ADAPTOR_INFO_CACHING_FLASH 0
//#undef CONFIG_EAP
//#undef CONFIG_IPS
#define CONFIG_8710B_MOVE_TO_ROM
#define CONFIG_EFUSE_SEPARATE
#define CONFIG_MOVE_PSK_TO_ROM
#define CONFIG_WOWLAN
#define CONFIG_TRAFFIC_PROTECT
#ifdef CONFIG_LPS
#define REKEY_LEAVE_LPS
#endif
#endif
#elif defined(CONFIG_HARDWARE_8188F)
#define CONFIG_RTL8188F
#else
#define CONFIG_RTL8188E
#endif
#define RTL8192C_SUPPORT 0
#define RTL8192CE_SUPPORT 0
#define RTL8192CU_SUPPORT 0
#define RTL8192D_SUPPORT 0
#define RTL8192DE_SUPPORT 0
#define RTL8192DU_SUPPORT 0
#define RTL8723A_SUPPORT 0
#define RTL8723AU_SUPPORT 0
#define RTL8723AS_SUPPORT 0
#define RTL8192E_SUPPORT 0
#define RTL8812A_SUPPORT 0
#define RTL8821A_SUPPORT 0
#define RTL8723B_SUPPORT 0
#define RTL8195A_SUPPORT 0
#define RTL8188E_SUPPORT 0
#define RTL8188F_SUPPORT 0
#define RTL8711B_SUPPORT 0
#if defined(CONFIG_PLATFORM_8195A)
#undef RTL8195A_SUPPORT
#define RTL8195A_SUPPORT 1
#elif defined(CONFIG_PLATFORM_8711B)
#undef RTL8711B_SUPPORT
#define RTL8711B_SUPPORT 1
#elif defined(CONFIG_HARDWARE_8188F)
#undef RTL8188F_SUPPORT
#define RTL8188F_SUPPORT 1
#else
#undef RTL8188E_SUPPORT
#define RTL8188E_SUPPORT 1
#endif
#define TEST_CHIP_SUPPORT 0
#define RTL8188E_FOR_TEST_CHIP 0
#define RTL8188E_FPGA_TRUE_PHY_VERIFICATION 0
// for Debug message
#define DBG 0
#if defined(CONFIG_PLATFORM_AMEBA_X)
#if(DBG == 0)
#define ROM_E_RTW_MSG 1
#define ROM_F_RTW_MSG 1
/* For DM debug*/
// BB
#define DBG_RX_INFO 1
#define DBG_DM_DIG 1 // DebugComponents: bit0
#define DBG_DM_RA_MASK 1 // DebugComponents: bit1
#define DBG_DM_ANT_DIV 1 // DebugComponents: bit6
#define DBG_TX_RATE 1 // DebugComponents: bit9
#define DBG_DM_RA 1 // DebugComponents: bit9
#define DBG_DM_ADAPTIVITY 1 // DebugComponents: bit17
// RF
#define DBG_PWR_TRACKING 1 // DebugComponents: bit24
#define DBG_RF_IQK 1 // DebugComponents: bit26
// Common
#define DBG_PWR_INDEX 1 // DebugComponents: bit30
#endif
#endif
/* For DM support */
#if defined(CONFIG_RTL8188F)
#define RATE_ADAPTIVE_SUPPORT 0
#elif defined(CONFIG_PLATFORM_8711B)
#define RATE_ADAPTIVE_SUPPORT 0
#define CONFIG_ODM_REFRESH_RAMASK
#else
#define RATE_ADAPTIVE_SUPPORT 1
#endif
// adaptivity
#define RTW_ADAPTIVITY_EN_DISABLE 0
#define RTW_ADAPTIVITY_EN_ENABLE 1
#define CONFIG_RTW_ADAPTIVITY_EN RTW_ADAPTIVITY_EN_DISABLE
#define RTW_ADAPTIVITY_MODE_NORMAL 0
#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
#define CONFIG_RTW_ADAPTIVITY_MODE RTW_ADAPTIVITY_MODE_CARRIER_SENSE
#define CONFIG_RTW_ADAPTIVITY_DML 0
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define CONFIG_POWER_TRAINING_WIL 0 // in RA
#else
#define POWER_BY_RATE_SUPPORT 0
#endif
#if defined(CONFIG_PLATFORM_AMEBA_X)
#define RTL8195A_FOR_TEST_CHIP 0
//#define CONFIG_WIFI_TEST 1
//#define CONFIG_MAC_LOOPBACK_DRIVER 1
//#define CONFIG_WLAN_HAL_TEST 1
//#define SKB_PRE_ALLOCATE_TX 1
#define SKB_PRE_ALLOCATE_RX 0
#define TX_CHECK_DSEC_ALWAYS 1
#define CONFIG_DBG_DISABLE_RDU_INTERRUPT
//#define CONFIG_WLAN_HAL_RX_TASK
#if (SKB_PRE_ALLOCATE_RX == 1)
#define EXCHANGE_LXBUS_RX_SKB 0
#endif
#ifdef CONFIG_FPGA
//Enable mac loopback for test mode (Ameba)
#define CONFIG_TWO_MAC_DRIVER // for test mode
#endif
#ifdef ENABLE_MAC_LB_FOR_TEST_MODE
#define CONFIG_SUDO_PHY_SETTING
#define INT_HANDLE_IN_ISR 1
#define CONFIG_LWIP_LAYER 0
#define CONFIG_WLAN_HAL_TEST
#define CONFIG_WLAN_HAL_RX_TASK
#define CONFIG_MAC_LOOPBACK_DRIVER_RTL8711B 1
#define HAL_MAC_ENABLE 1
#define CONFIG_TWO_MAC_TEST_MODE
#define DISABLE_BB_RF 1
#else
//#define CONFIG_TWO_MAC_DRIVER //for mornal driver; two mac
#ifdef CONFIG_TWO_MAC_DRIVER
#define CONFIG_SUDO_PHY_SETTING
#define HAL_MAC_ENABLE 1
#define DISABLE_BB_RF 1
#else
#define HAL_MAC_ENABLE 1
#define HAL_BB_ENABLE 1
#define HAL_RF_ENABLE 1
#define DISABLE_BB_RF 0
#endif
//#define INT_HANDLE_IN_ISR 1
#endif
#endif // CONFIG_PLATFORM_AMEBA_X
#ifndef CONFIG_LWIP_LAYER
#define CONFIG_LWIP_LAYER 1
#endif
#define CONFIG_MAC_ADDRESS 0
//fast reconnection
//#define CONFIG_FAST_RECONNECTION 1
#if defined(CONFIG_INIC_EN)&&(CONFIG_INIC_EN==1)
#define CONFIG_RECV_REORDERING_CTRL //enable reordering for iNIC high throughput
#undef RX_AGGREGATION
#define RX_AGGREGATION 1
#undef NOT_SUPPORT_40M
#undef CONFIG_CONCURRENT_MODE
#endif
#endif //WLANCONFIG_H

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component/common/drivers/wlan/realtek/include/drv_conf.h Executable file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __DRV_CONF_H__
#define __DRV_CONF_H__
#include "autoconf.h"
#if ((RTL8195A_SUPPORT==1) || (RTL8711B_SUPPORT==1))
#include "platform_autoconf.h"
#endif
#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
#error "Shall be Linux or Windows, but not both!\n"
#endif
//Older Android kernel doesn't has CONFIG_ANDROID defined,
//add this to force CONFIG_ANDROID defined
#ifdef CONFIG_PLATFORM_ANDROID
#define CONFIG_ANDROID
#endif
#ifdef CONFIG_ANDROID
//Some Android build will restart the UI while non-printable ascii is passed
//between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID
//for Android here. If you are sure there is no risk on your system about this,
//mask this macro define to support non-printable ascii ssid.
//#define CONFIG_VALIDATE_SSID
#ifdef CONFIG_PLATFORM_ARM_SUNxI
#ifdef CONFIG_VALIDATE_SSID
#undef CONFIG_VALIDATE_SSID
#endif
#endif
//Android expect dbm as the rx signal strength unit
#define CONFIG_SIGNAL_DISPLAY_DBM
#endif
#if defined(CONFIG_HAS_EARLYSUSPEND) && defined (CONFIG_RESUME_IN_WORKQUEUE)
#warning "You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
#undef CONFIG_RESUME_IN_WORKQUEUE
#endif
#if defined(CONFIG_ANDROID_POWER) && defined (CONFIG_RESUME_IN_WORKQUEUE)
#warning "You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
#undef CONFIG_RESUME_IN_WORKQUEUE
#endif
#ifdef CONFIG_RESUME_IN_WORKQUEUE //this can be removed, because there is no case for this...
#if !defined( CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER)
#error "enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality..."
#error "If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK..."
#endif
#endif
//About USB VENDOR REQ
#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically"
#define CONFIG_USB_VENDOR_REQ_MUTEX
#endif
#if defined(CONFIG_VENDOR_REQ_RETRY) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically"
#define CONFIG_USB_VENDOR_REQ_MUTEX
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_EN
#define CONFIG_RTW_ADAPTIVITY_EN 0
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_MODE
#define CONFIG_RTW_ADAPTIVITY_MODE 0
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_DML
#define CONFIG_RTW_ADAPTIVITY_DML 0
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_DC_BACKOFF
#define CONFIG_RTW_ADAPTIVITY_DC_BACKOFF 4
#endif
#ifndef CONFIG_RTW_NHM_EN
#define CONFIG_RTW_NHM_EN 0
#endif
//#include <rtl871x_byteorder.h>
#endif // __DRV_CONF_H__

38
component/common/drivers/wlan/realtek/include/rom_aes.h Executable file
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/******************************************************************************
*
* Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved.
*
* This is ROM code section.
*
*
******************************************************************************/
#ifndef ROM_AES_H
#define ROM_AES_H
typedef struct
{
u32 erk[64]; /* encryption round keys */
u32 drk[64]; /* decryption round keys */
int nr; /* number of rounds */
}aes_context;
#define AES_BLOCKSIZE8 8
#define AES_BLK_SIZE 16 // # octets in an AES block
typedef union _aes_block // AES cipher block
{
unsigned long x[AES_BLK_SIZE/4]; // access as 8-bit octets or 32-bit words
unsigned char b[AES_BLK_SIZE];
}aes_block;
void AES_WRAP(unsigned char * plain, int plain_len,
unsigned char * iv, int iv_len,
unsigned char * kek, int kek_len,
unsigned char *cipher, unsigned short *cipher_len);
void AES_UnWRAP(unsigned char * cipher, int cipher_len,
unsigned char * kek, int kek_len,
unsigned char * plain);
#endif

468
component/common/drivers/wlan/realtek/include/rtw_debug.h Executable file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTW_DEBUG_H__
#define __RTW_DEBUG_H__
#define _drv_always_ 1
#define _drv_emerg_ 2
#define _drv_alert_ 3
#define _drv_crit_ 4
#define _drv_err_ 5
#define _drv_warning_ 6
#define _drv_notice_ 7
#define _drv_info_ 8
#define _drv_dump_ 9
#define _drv_debug_ 10
#define _module_rtl871x_xmit_c_ BIT(0)
#define _module_xmit_osdep_c_ BIT(1)
#define _module_rtl871x_recv_c_ BIT(2)
#define _module_recv_osdep_c_ BIT(3)
#define _module_rtl871x_mlme_c_ BIT(4)
#define _module_mlme_osdep_c_ BIT(5)
#define _module_rtl871x_sta_mgt_c_ BIT(6)
#define _module_rtl871x_cmd_c_ BIT(7)
#define _module_cmd_osdep_c_ BIT(8)
#define _module_rtl871x_io_c_ BIT(9)
#define _module_io_osdep_c_ BIT(10)
#define _module_os_intfs_c_ BIT(11)
#define _module_rtl871x_security_c_ BIT(12)
#define _module_rtl871x_eeprom_c_ BIT(13)
#define _module_hal_init_c_ BIT(14)
#define _module_hci_hal_init_c_ BIT(15)
#define _module_rtl871x_ioctl_c_ BIT(16)
#define _module_rtl871x_ioctl_set_c_ BIT(17)
#define _module_rtl871x_ioctl_query_c_ BIT(18)
#define _module_rtl871x_pwrctrl_c_ BIT(19)
#define _module_hci_intfs_c_ BIT(20)
#define _module_hci_ops_c_ BIT(21)
#define _module_osdep_service_c_ BIT(22)
#define _module_mp_ BIT(23)
#define _module_hci_ops_os_c_ BIT(24)
#define _module_rtl871x_ioctl_os_c BIT(25)
#define _module_rtl8712_cmd_c_ BIT(26)
#define _module_fwcmd_c_ BIT(27)
#define _module_rtl8192c_xmit_c_ BIT(28)
#define _module_hal_xmit_c_ BIT(28)
#define _module_efuse_ BIT(29)
#define _module_rtl8712_recv_c_ BIT(30)
#define _module_rtl8712_led_c_ BIT(31)
#undef _MODULE_DEFINE_
#if defined _RTW_XMIT_C_
#define _MODULE_DEFINE_ _module_rtl871x_xmit_c_
#elif defined _XMIT_OSDEP_C_
#define _MODULE_DEFINE_ _module_xmit_osdep_c_
#elif defined _RTW_RECV_C_
#define _MODULE_DEFINE_ _module_rtl871x_recv_c_
#elif defined _RECV_OSDEP_C_
#define _MODULE_DEFINE_ _module_recv_osdep_c_
#elif defined _RTW_MLME_C_
#define _MODULE_DEFINE_ _module_rtl871x_mlme_c_
#elif defined _MLME_OSDEP_C_
#define _MODULE_DEFINE_ _module_mlme_osdep_c_
#elif defined _RTW_MLME_EXT_C_
#define _MODULE_DEFINE_ 1
#elif defined _RTW_STA_MGT_C_
#define _MODULE_DEFINE_ _module_rtl871x_sta_mgt_c_
#elif defined _RTW_CMD_C_
#define _MODULE_DEFINE_ _module_rtl871x_cmd_c_
#elif defined _CMD_OSDEP_C_
#define _MODULE_DEFINE_ _module_cmd_osdep_c_
#elif defined _RTW_IO_C_
#define _MODULE_DEFINE_ _module_rtl871x_io_c_
#elif defined _IO_OSDEP_C_
#define _MODULE_DEFINE_ _module_io_osdep_c_
#elif defined _OS_INTFS_C_
#define _MODULE_DEFINE_ _module_os_intfs_c_
#elif defined _RTW_SECURITY_C_
#define _MODULE_DEFINE_ _module_rtl871x_security_c_
#elif defined _RTW_EEPROM_C_
#define _MODULE_DEFINE_ _module_rtl871x_eeprom_c_
#elif defined _HAL_INTF_C_
#define _MODULE_DEFINE_ _module_hal_init_c_
#elif (defined _HCI_HAL_INIT_C_) || (defined _SDIO_HALINIT_C_)
#define _MODULE_DEFINE_ _module_hci_hal_init_c_
#elif defined _RTL871X_IOCTL_C_
#define _MODULE_DEFINE_ _module_rtl871x_ioctl_c_
#elif defined _RTL871X_IOCTL_SET_C_
#define _MODULE_DEFINE_ _module_rtl871x_ioctl_set_c_
#elif defined _RTL871X_IOCTL_QUERY_C_
#define _MODULE_DEFINE_ _module_rtl871x_ioctl_query_c_
#elif defined _RTL871X_PWRCTRL_C_
#define _MODULE_DEFINE_ _module_rtl871x_pwrctrl_c_
#elif defined _RTW_PWRCTRL_C_
#define _MODULE_DEFINE_ 1
#elif defined _HCI_INTF_C_
#define _MODULE_DEFINE_ _module_hci_intfs_c_
#elif defined _HCI_OPS_C_
#define _MODULE_DEFINE_ _module_hci_ops_c_
#elif defined _SDIO_OPS_C_
#define _MODULE_DEFINE_ 1
#elif defined _OSDEP_HCI_INTF_C_
#define _MODULE_DEFINE_ _module_hci_intfs_c_
#elif defined _OSDEP_SERVICE_C_
#define _MODULE_DEFINE_ _module_osdep_service_c_
#elif defined _HCI_OPS_OS_C_
#define _MODULE_DEFINE_ _module_hci_ops_os_c_
#elif defined _RTL871X_IOCTL_LINUX_C_
#define _MODULE_DEFINE_ _module_rtl871x_ioctl_os_c
#elif defined _RTL8712_CMD_C_
#define _MODULE_DEFINE_ _module_rtl8712_cmd_c_
#elif defined _RTL8192C_XMIT_C_
#define _MODULE_DEFINE_ 1
#elif defined _RTL8723AS_XMIT_C_
#define _MODULE_DEFINE_ 1
#elif defined _RTL8712_RECV_C_
#define _MODULE_DEFINE_ _module_rtl8712_recv_c_
#elif defined _RTL8192CU_RECV_C_
#define _MODULE_DEFINE_ _module_rtl8712_recv_c_
#elif defined _RTL871X_MLME_EXT_C_
#define _MODULE_DEFINE_ _module_mlme_osdep_c_
#elif defined _RTW_MP_C_
#define _MODULE_DEFINE_ _module_mp_
#elif defined _RTW_MP_IOCTL_C_
#define _MODULE_DEFINE_ _module_mp_
#elif defined _RTW_EFUSE_C_
#define _MODULE_DEFINE_ _module_efuse_
#endif
#ifdef PLATFORM_OS_CE
extern void rtl871x_cedbg(const char *fmt, ...);
#endif
extern u32 GlobalDebugEnable;
#define RT_TRACE(_Comp, _Level, Fmt) do{}while(0)
#define _func_enter_ do{}while(0)
#define _func_exit_ do{}while(0)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) do{}while(0)
#ifdef PLATFORM_WINDOWS
#define DBG_871X do {} while(0)
#define MSG_8192C do {} while(0)
#define DBG_8192C do {} while(0)
#define DBG_871X_LEVEL do {} while(0)
#else
#define DBG_871X(x, ...) do {} while(0)
#define MSG_8192C(x, ...) do {} while(0)
#define DBG_8192C(x,...) do {} while(0)
#define DBG_871X_LEVEL(x,...) do {} while(0)
#endif
#ifdef CONFIG_BT_COEXIST
#define RTW_INFO(x,...) do {} while (0)
#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0)
#endif
#undef _dbgdump
#ifdef PLATFORM_WINDOWS
#ifdef PLATFORM_OS_XP
#define _dbgdump DbgPrint
#elif defined PLATFORM_OS_CE
#define _dbgdump rtl871x_cedbg
#endif
#elif defined PLATFORM_LINUX
#define _dbgdump printk
#elif defined PLATFORM_ECOS
#define _dbgdump diag_printf
#elif defined PLATFORM_FREERTOS
#define _dbgdump printf("\n\r"); printf
#elif defined PLATFORM_FREEBSD
#define _dbgdump printf
#endif
#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B)
#define DRIVER_PREFIX "RTL871X: "
#endif
#define DEBUG_LEVEL (_drv_err_)
#if defined (_dbgdump)
#undef DBG_871X_LEVEL
#if defined (__ICCARM__) || defined (__CC_ARM) ||defined(__GNUC__)|| defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
#define DBG_871X_LEVEL(level, ...) \
do {\
if(GlobalDebugEnable){\
_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
}\
}while(0)
#else
#define DBG_871X_LEVEL(level, fmt, arg...) \
do {\
if(GlobalDebugEnable){\
if (level <= DEBUG_LEVEL) {\
if (level <= _drv_err_ && level > _drv_always_) {\
_dbgdump(DRIVER_PREFIX"ERROR " fmt, ##arg);\
} \
else {\
_dbgdump(DRIVER_PREFIX fmt, ##arg);\
} \
}\
}\
}while(0)
#endif //#ifdef __CC_ARM
#endif
#ifdef CONFIG_DEBUG
#if defined (_dbgdump)
#undef DBG_871X
#define DBG_871X(...) do {\
_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
}while(0)
#undef MSG_8192C
#define MSG_8192C(...) do {\
_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
}while(0)
#undef DBG_8192C
#define DBG_8192C(...) do {\
_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
}while(0)
#endif
#endif /* CONFIG_DEBUG */
#ifdef CONFIG_DEBUG_RTL871X
#ifndef _RTL871X_DEBUG_C_
extern u32 GlobalDebugLevel;
extern u64 GlobalDebugComponents;
#endif
#if defined (_dbgdump) && defined (_MODULE_DEFINE_)
#undef RT_TRACE
#define RT_TRACE(_Comp, _Level, Fmt)\
do {\
if((_Comp & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) {\
_dbgdump("%s [0x%08x,%d]", DRIVER_PREFIX, (unsigned int)_Comp, _Level);\
_dbgdump Fmt;\
}\
}while(0)
#endif
#if defined (_dbgdump)
#undef _func_enter_
#define _func_enter_ \
do { \
if (GlobalDebugLevel >= _drv_debug_) \
{ \
_dbgdump("\n %s : %s enters at %d\n", DRIVER_PREFIX, __FUNCTION__, __LINE__);\
} \
} while(0)
#undef _func_exit_
#define _func_exit_ \
do { \
if (GlobalDebugLevel >= _drv_debug_) \
{ \
_dbgdump("\n %s : %s exits at %d\n", DRIVER_PREFIX, __FUNCTION__, __LINE__); \
} \
} while(0)
#undef RT_PRINT_DATA
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
u8 *ptr = (u8 *)_HexData; \
printf("\r\n%s", DRIVER_PREFIX); \
printf(_TitleString "--------Len=%d\n\r", _HexDataLen); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
printf("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
if (((__i + 1) % 16) == 0) printf("\n\r"); \
} \
printf("\n\r"); \
}
#endif
#endif /* CONFIG_DEBUG_RTL871X */
#ifdef CONFIG_PROC_DEBUG
int proc_get_drv_version(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_write_reg(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_write_reg(struct file *file, const char *buffer,
unsigned long count, void *data);
int proc_get_read_reg(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_read_reg(struct file *file, const char *buffer,
unsigned long count, void *data);
int proc_get_fwstate(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_sec_info(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_mlmext_state(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_qos_option(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_ht_option(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_rf_info(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_ap_info(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_adapter_state(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_trx_info(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_mac_reg_dump1(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_mac_reg_dump2(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_mac_reg_dump3(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_bb_reg_dump1(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_bb_reg_dump2(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_bb_reg_dump3(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_rf_reg_dump1(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_rf_reg_dump2(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_rf_reg_dump3(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_rf_reg_dump4(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
#ifdef CONFIG_AP_MODE
int proc_get_all_sta_info(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
#endif
#ifdef DBG_MEMORY_LEAK
int proc_get_malloc_cnt(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
#endif
#ifdef CONFIG_FIND_BEST_CHANNEL
int proc_get_best_channel(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
#endif
int proc_get_rx_signal(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_rx_signal(struct file *file, const char *buffer,
unsigned long count, void *data);
#ifdef CONFIG_80211N_HT
int proc_get_cbw40_enable(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_cbw40_enable(struct file *file, const char *buffer,
unsigned long count, void *data);
int proc_get_ampdu_enable(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_ampdu_enable(struct file *file, const char *buffer,
unsigned long count, void *data);
int proc_get_rx_stbc(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_rx_stbc(struct file *file, const char *buffer,
unsigned long count, void *data);
#endif //CONFIG_80211N_HT
int proc_get_two_path_rssi(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_get_rssi_disp(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_rssi_disp(struct file *file, const char *buffer,
unsigned long count, void *data);
#endif //CONFIG_PROC_DEBUG
#endif //__RTW_DEBUG_H__

550
component/common/drivers/wlan/realtek/include/wifi_constants.h Executable file
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/**
******************************************************************************
* @file wifi_constants.h
* @author
* @version
* @brief This file provides the data types used for wlan API.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _WIFI_CONSTANTS_H
#define _WIFI_CONSTANTS_H
/** @addtogroup nic NIC
* @ingroup wlan
* @brief NIC functions
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef WLAN0_NAME
#define WLAN0_NAME "wlan0"
#endif
#ifndef WLAN1_NAME
#define WLAN1_NAME "wlan1"
#endif
#define WEP_ENABLED 0x0001
#define TKIP_ENABLED 0x0002
#define AES_ENABLED 0x0004
#define WSEC_SWFLAG 0x0008
#define SHARED_ENABLED 0x00008000
#define WPA_SECURITY 0x00200000
#define WPA2_SECURITY 0x00400000
#define WPS_ENABLED 0x10000000
#define RTW_MAX_PSK_LEN (64)
#define RTW_MIN_PSK_LEN (8)
#define MCSSET_LEN 16
/**
* @brief The enumeration lists the results of the function.
*/
typedef enum
{
RTW_SUCCESS = 0, /**< Success */
RTW_PENDING = 1, /**< Pending */
RTW_TIMEOUT = 2, /**< Timeout */
RTW_PARTIAL_RESULTS = 3, /**< Partial results */
RTW_INVALID_KEY = 4, /**< Invalid key */
RTW_DOES_NOT_EXIST = 5, /**< Does not exist */
RTW_NOT_AUTHENTICATED = 6, /**< Not authenticated */
RTW_NOT_KEYED = 7, /**< Not keyed */
RTW_IOCTL_FAIL = 8, /**< IOCTL fail */
RTW_BUFFER_UNAVAILABLE_TEMPORARY = 9, /**< Buffer unavailable temporarily */
RTW_BUFFER_UNAVAILABLE_PERMANENT = 10, /**< Buffer unavailable permanently */
RTW_WPS_PBC_OVERLAP = 11, /**< WPS PBC overlap */
RTW_CONNECTION_LOST = 12, /**< Connection lost */
RTW_ERROR = -1, /**< Generic Error */
RTW_BADARG = -2, /**< Bad Argument */
RTW_BADOPTION = -3, /**< Bad option */
RTW_NOTUP = -4, /**< Not up */
RTW_NOTDOWN = -5, /**< Not down */
RTW_NOTAP = -6, /**< Not AP */
RTW_NOTSTA = -7, /**< Not STA */
RTW_BADKEYIDX = -8, /**< BAD Key Index */
RTW_RADIOOFF = -9, /**< Radio Off */
RTW_NOTBANDLOCKED = -10, /**< Not band locked */
RTW_NOCLK = -11, /**< No Clock */
RTW_BADRATESET = -12, /**< BAD Rate valueset */
RTW_BADBAND = -13, /**< BAD Band */
RTW_BUFTOOSHORT = -14, /**< Buffer too short */
RTW_BUFTOOLONG = -15, /**< Buffer too long */
RTW_BUSY = -16, /**< Busy */
RTW_NOTASSOCIATED = -17, /**< Not Associated */
RTW_BADSSIDLEN = -18, /**< Bad SSID len */
RTW_OUTOFRANGECHAN = -19, /**< Out of Range Channel */
RTW_BADCHAN = -20, /**< Bad Channel */
RTW_BADADDR = -21, /**< Bad Address */
RTW_NORESOURCE = -22, /**< Not Enough Resources */
RTW_UNSUPPORTED = -23, /**< Unsupported */
RTW_BADLEN = -24, /**< Bad length */
RTW_NOTREADY = -25, /**< Not Ready */
RTW_EPERM = -26, /**< Not Permitted */
RTW_NOMEM = -27, /**< No Memory */
RTW_ASSOCIATED = -28, /**< Associated */
RTW_RANGE = -29, /**< Not In Range */
RTW_NOTFOUND = -30, /**< Not Found */
RTW_WME_NOT_ENABLED = -31, /**< WME Not Enabled */
RTW_TSPEC_NOTFOUND = -32, /**< TSPEC Not Found */
RTW_ACM_NOTSUPPORTED = -33, /**< ACM Not Supported */
RTW_NOT_WME_ASSOCIATION = -34, /**< Not WME Association */
RTW_SDIO_ERROR = -35, /**< SDIO Bus Error */
RTW_WLAN_DOWN = -36, /**< WLAN Not Accessible */
RTW_BAD_VERSION = -37, /**< Incorrect version */
RTW_TXFAIL = -38, /**< TX failure */
RTW_RXFAIL = -39, /**< RX failure */
RTW_NODEVICE = -40, /**< Device not present */
RTW_UNFINISHED = -41, /**< To be finished */
RTW_NONRESIDENT = -42, /**< access to nonresident overlay */
RTW_DISABLED = -43 /**< Disabled in this build */
} rtw_result_t;
/**
* @brief The enumeration lists the possible security types to set when connection.\n
* Station mode supports OPEN, WEP, and WPA2.\n
* AP mode support OPEN and WPA2.
*/
typedef enum {
RTW_SECURITY_OPEN = 0, /**< Open security */
RTW_SECURITY_WEP_PSK = WEP_ENABLED, /**< WEP Security with open authentication */
RTW_SECURITY_WEP_SHARED = ( WEP_ENABLED | SHARED_ENABLED ), /**< WEP Security with shared authentication */
RTW_SECURITY_WPA_TKIP_PSK = ( WPA_SECURITY | TKIP_ENABLED ), /**< WPA Security with TKIP */
RTW_SECURITY_WPA_AES_PSK = ( WPA_SECURITY | AES_ENABLED ), /**< WPA Security with AES */
RTW_SECURITY_WPA2_AES_PSK = ( WPA2_SECURITY | AES_ENABLED ), /**< WPA2 Security with AES */
RTW_SECURITY_WPA2_TKIP_PSK = ( WPA2_SECURITY | TKIP_ENABLED ), /**< WPA2 Security with TKIP */
RTW_SECURITY_WPA2_MIXED_PSK = ( WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED ), /**< WPA2 Security with AES & TKIP */
RTW_SECURITY_WPA_WPA2_MIXED = ( WPA_SECURITY | WPA2_SECURITY ), /**< WPA/WPA2 Security */
RTW_SECURITY_WPS_OPEN = WPS_ENABLED, /**< WPS with open security */
RTW_SECURITY_WPS_SECURE = (WPS_ENABLED | AES_ENABLED), /**< WPS with AES security */
RTW_SECURITY_UNKNOWN = -1, /**< May be returned by scan function if security is unknown. Do not pass this to the join function! */
RTW_SECURITY_FORCE_32_BIT = 0x7fffffff /**< Exists only to force rtw_security_t type to 32 bits */
} rtw_security_t;
typedef enum {
RTW_ENCRYPTION_UNKNOWN = 0,
RTW_ENCRYPTION_OPEN = 1,
RTW_ENCRYPTION_WEP40 = 2,
RTW_ENCRYPTION_WPA_TKIP = 3,
RTW_ENCRYPTION_WPA_AES = 4,
RTW_ENCRYPTION_WPA2_TKIP = 5,
RTW_ENCRYPTION_WPA2_AES = 6,
RTW_ENCRYPTION_WPA2_MIXED = 7,
RTW_ENCRYPTION_WEP104 = 9,
RTW_ENCRYPTION_UNDEF = 0xFF,
} rtw_encryption_t;
typedef enum {
RTW_FALSE = 0,
RTW_TRUE = 1
} rtw_bool_t;
/**
* @brief The enumeration lists the band types.
*/
typedef enum {
RTW_802_11_BAND_5GHZ = 0, /**< Denotes 5GHz radio band */
RTW_802_11_BAND_2_4GHZ = 1 /**< Denotes 2.4GHz radio band */
} rtw_802_11_band_t;
/**
* @brief The enumeration lists all the country codes able to set to Wi-Fi driver.
*/
typedef enum {
/* CHANNEL PLAN */
RTW_COUNTRY_WORLD1, // 0x20
RTW_COUNTRY_ETSI1, // 0x21
RTW_COUNTRY_FCC1, // 0x22
RTW_COUNTRY_MKK1, // 0x23
RTW_COUNTRY_ETSI2, // 0x24
RTW_COUNTRY_FCC2, // 0x2A
RTW_COUNTRY_WORLD2, // 0x47
RTW_COUNTRY_MKK2, // 0x58
RTW_COUNTRY_GLOBAL, // 0x41
/* SPECIAL */
RTW_COUNTRY_WORLD, // WORLD1
RTW_COUNTRY_EU, // ETSI1
/* JAPANESE */
RTW_COUNTRY_JP, // MKK1
/* FCC , 19 countries*/
RTW_COUNTRY_AS, // FCC2
RTW_COUNTRY_BM,
RTW_COUNTRY_CA,
RTW_COUNTRY_DM,
RTW_COUNTRY_DO,
RTW_COUNTRY_FM,
RTW_COUNTRY_GD,
RTW_COUNTRY_GT,
RTW_COUNTRY_GU,
RTW_COUNTRY_HT,
RTW_COUNTRY_MH,
RTW_COUNTRY_MP,
RTW_COUNTRY_NI,
RTW_COUNTRY_PA,
RTW_COUNTRY_PR,
RTW_COUNTRY_PW,
RTW_COUNTRY_TW,
RTW_COUNTRY_US,
RTW_COUNTRY_VI,
/* others, ETSI */
RTW_COUNTRY_AD, // ETSI1
RTW_COUNTRY_AE,
RTW_COUNTRY_AF,
RTW_COUNTRY_AI,
RTW_COUNTRY_AL,
RTW_COUNTRY_AM,
RTW_COUNTRY_AN,
RTW_COUNTRY_AR,
RTW_COUNTRY_AT,
RTW_COUNTRY_AU,
RTW_COUNTRY_AW,
RTW_COUNTRY_AZ,
RTW_COUNTRY_BA,
RTW_COUNTRY_BB,
RTW_COUNTRY_BD,
RTW_COUNTRY_BE,
RTW_COUNTRY_BF,
RTW_COUNTRY_BG,
RTW_COUNTRY_BH,
RTW_COUNTRY_BL,
RTW_COUNTRY_BN,
RTW_COUNTRY_BO,
RTW_COUNTRY_BR,
RTW_COUNTRY_BS,
RTW_COUNTRY_BT,
RTW_COUNTRY_BY,
RTW_COUNTRY_BZ,
RTW_COUNTRY_CF,
RTW_COUNTRY_CH,
RTW_COUNTRY_CI,
RTW_COUNTRY_CL,
RTW_COUNTRY_CN,
RTW_COUNTRY_CO,
RTW_COUNTRY_CR,
RTW_COUNTRY_CX,
RTW_COUNTRY_CY,
RTW_COUNTRY_CZ,
RTW_COUNTRY_DE,
RTW_COUNTRY_DK,
RTW_COUNTRY_DZ,
RTW_COUNTRY_EC,
RTW_COUNTRY_EE,
RTW_COUNTRY_EG,
RTW_COUNTRY_ES,
RTW_COUNTRY_ET,
RTW_COUNTRY_FI,
RTW_COUNTRY_FR,
RTW_COUNTRY_GB,
RTW_COUNTRY_GE,
RTW_COUNTRY_GF,
RTW_COUNTRY_GH,
RTW_COUNTRY_GL,
RTW_COUNTRY_GP,
RTW_COUNTRY_GR,
RTW_COUNTRY_GY,
RTW_COUNTRY_HK,
RTW_COUNTRY_HN,
RTW_COUNTRY_HR,
RTW_COUNTRY_HU,
RTW_COUNTRY_ID,
RTW_COUNTRY_IE,
RTW_COUNTRY_IL,
RTW_COUNTRY_IN,
RTW_COUNTRY_IQ,
RTW_COUNTRY_IR,
RTW_COUNTRY_IS,
RTW_COUNTRY_IT,
RTW_COUNTRY_JM,
RTW_COUNTRY_JO,
RTW_COUNTRY_KE,
RTW_COUNTRY_KH,
RTW_COUNTRY_KN,
RTW_COUNTRY_KP,
RTW_COUNTRY_KR,
RTW_COUNTRY_KW,
RTW_COUNTRY_KY,
RTW_COUNTRY_KZ,
RTW_COUNTRY_LA,
RTW_COUNTRY_LB,
RTW_COUNTRY_LC,
RTW_COUNTRY_LI,
RTW_COUNTRY_LK,
RTW_COUNTRY_LR,
RTW_COUNTRY_LS,
RTW_COUNTRY_LT,
RTW_COUNTRY_LU,
RTW_COUNTRY_LV,
RTW_COUNTRY_MA,
RTW_COUNTRY_MC,
RTW_COUNTRY_MD,
RTW_COUNTRY_ME,
RTW_COUNTRY_MF,
RTW_COUNTRY_MK,
RTW_COUNTRY_MN,
RTW_COUNTRY_MO,
RTW_COUNTRY_MQ,
RTW_COUNTRY_MR,
RTW_COUNTRY_MT,
RTW_COUNTRY_MU,
RTW_COUNTRY_MV,
RTW_COUNTRY_MW,
RTW_COUNTRY_MX,
RTW_COUNTRY_MY,
RTW_COUNTRY_NG,
RTW_COUNTRY_NL,
RTW_COUNTRY_NO,
RTW_COUNTRY_NP,
RTW_COUNTRY_NZ,
RTW_COUNTRY_OM,
RTW_COUNTRY_PE,
RTW_COUNTRY_PF,
RTW_COUNTRY_PG,
RTW_COUNTRY_PH,
RTW_COUNTRY_PK,
RTW_COUNTRY_PL,
RTW_COUNTRY_PM,
RTW_COUNTRY_PT,
RTW_COUNTRY_PY,
RTW_COUNTRY_QA,
RTW_COUNTRY_RS,
RTW_COUNTRY_RU,
RTW_COUNTRY_RW,
RTW_COUNTRY_SA,
RTW_COUNTRY_SE,
RTW_COUNTRY_SG,
RTW_COUNTRY_SI,
RTW_COUNTRY_SK,
RTW_COUNTRY_SN,
RTW_COUNTRY_SR,
RTW_COUNTRY_SV,
RTW_COUNTRY_SY,
RTW_COUNTRY_TC,
RTW_COUNTRY_TD,
RTW_COUNTRY_TG,
RTW_COUNTRY_TH,
RTW_COUNTRY_TN,
RTW_COUNTRY_TR,
RTW_COUNTRY_TT,
RTW_COUNTRY_TZ,
RTW_COUNTRY_UA,
RTW_COUNTRY_UG,
RTW_COUNTRY_UY,
RTW_COUNTRY_UZ,
RTW_COUNTRY_VC,
RTW_COUNTRY_VE,
RTW_COUNTRY_VN,
RTW_COUNTRY_VU,
RTW_COUNTRY_WF,
RTW_COUNTRY_WS,
RTW_COUNTRY_YE,
RTW_COUNTRY_YT,
RTW_COUNTRY_ZA,
RTW_COUNTRY_ZW,
RTW_COUNTRY_MAX
}rtw_country_code_t;
/**
* @brief The enumeration lists the adaptivity types.
*/
typedef enum {
RTW_ADAPTIVITY_DISABLE = 0,
RTW_ADAPTIVITY_NORMAL, // CE
RTW_ADAPTIVITY_CARRIER_SENSE // MKK
} rtw_adaptivity_mode_t;
/**
* @brief The enumeration lists the supported operation mode by WIFI driver,
* including station and AP mode.
*/
typedef enum {
RTW_MODE_NONE = 0,
RTW_MODE_STA,
RTW_MODE_AP,
RTW_MODE_STA_AP,
RTW_MODE_PROMISC,
RTW_MODE_P2P
}rtw_mode_t;
typedef enum {
RTW_SCAN_FULL = 0,
RTW_SCAN_SOCIAL,
RTW_SCAN_ONE
}rtw_scan_mode_t;
/**
* @brief The enumeration lists the supported autoreconnect mode by WIFI driver.
*/
typedef enum{
RTW_AUTORECONNECT_DISABLE,
RTW_AUTORECONNECT_FINITE,
RTW_AUTORECONNECT_INFINITE
} rtw_autoreconnect_mode_t;
/**
* @brief The enumeration lists the status to describe the connection link.
*/
typedef enum {
RTW_LINK_DISCONNECTED = 0,
RTW_LINK_CONNECTED
} rtw_link_status_t;
/**
* @brief The enumeration lists the scan types.
*/
typedef enum {
RTW_SCAN_TYPE_ACTIVE = 0x00, /**< Actively scan a network by sending 802.11 probe(s) */
RTW_SCAN_TYPE_PASSIVE = 0x01, /**< Passively scan a network by listening for beacons from APs */
RTW_SCAN_TYPE_PROHIBITED_CHANNELS = 0x04 /**< Passively scan on channels not enabled by the country code */
} rtw_scan_type_t;
/**
* @brief The enumeration lists the bss types.
*/
typedef enum {
RTW_BSS_TYPE_INFRASTRUCTURE = 0, /**< Denotes infrastructure network */
RTW_BSS_TYPE_ADHOC = 1, /**< Denotes an 802.11 ad-hoc IBSS network */
RTW_BSS_TYPE_ANY = 2, /**< Denotes either infrastructure or ad-hoc network */
RTW_BSS_TYPE_UNKNOWN = -1 /**< May be returned by scan function if BSS type is unknown. Do not pass this to the Join function */
} rtw_bss_type_t;
typedef enum {
RTW_SCAN_COMMAMD = 0x01
} rtw_scan_command_t;
typedef enum{
COMMAND1 = 0x01
}rtw_command_type;
typedef enum {
RTW_WPS_TYPE_DEFAULT = 0x0000,
RTW_WPS_TYPE_USER_SPECIFIED = 0x0001,
RTW_WPS_TYPE_MACHINE_SPECIFIED = 0x0002,
RTW_WPS_TYPE_REKEY = 0x0003,
RTW_WPS_TYPE_PUSHBUTTON = 0x0004,
RTW_WPS_TYPE_REGISTRAR_SPECIFIED = 0x0005,
RTW_WPS_TYPE_NONE = 0x0006,
RTW_WPS_TYPE_WSC = 0x0007
} rtw_wps_type_t;
/**
* @brief The enumeration lists all the network bgn mode.
*/
typedef enum {
RTW_NETWORK_B = 1,
RTW_NETWORK_BG = 3,
RTW_NETWORK_BGN = 11
} rtw_network_mode_t;
/**
* @brief The enumeration lists the interfaces.
*/
typedef enum {
RTW_STA_INTERFACE = 0, /**< STA or Client Interface */
RTW_AP_INTERFACE = 1, /**< SoftAP Interface */
} rtw_interface_t;
/**
* @brief The enumeration lists the packet filter rules.
*/
typedef enum {
RTW_POSITIVE_MATCHING = 0, /**< Receive the data matching with this pattern and discard the other data */
RTW_NEGATIVE_MATCHING = 1 /**< Discard the data matching with this pattern and receive the other data */
} rtw_packet_filter_rule_t;
/**
* @brief The enumeration lists the promisc levels.
*/
typedef enum {
RTW_PROMISC_DISABLE = 0, /**< Disable the promisc */
RTW_PROMISC_ENABLE = 1, /**< Fetch all ethernet packets */
RTW_PROMISC_ENABLE_1 = 2, /**< Fetch only B/M packets */
RTW_PROMISC_ENABLE_2 = 3, /**< Fetch all 802.11 packets*/
RTW_PROMISC_ENABLE_3 = 4, /**< Fetch only B/M 802.11 packets*/
RTW_PROMISC_ENABLE_4 = 5, /**< Fetch all 802.11 packets & MIMO PLCP headers. Please note that the PLCP header would be struct rtw_rx_info_t defined in wifi_structures.h*/
} rtw_rcr_level_t;
/**
* @brief The enumeration lists the promisc rx type.
*/
#if CONFIG_UNSUPPORT_PLCPHDR_RPT
typedef enum {
RTW_RX_NORMAL = 0, /**< The supported 802.11 packet*/
RTW_RX_UNSUPPORT = 1, /**< Unsupported 802.11 packet info */
}rtw_rx_type_t;
#endif
/**
* @brief The enumeration lists the disconnect reasons.
*/
typedef enum{
RTW_NO_ERROR = 0,
RTW_NONE_NETWORK = 1,
RTW_CONNECT_FAIL = 2,
RTW_WRONG_PASSWORD = 3 ,
RTW_4WAY_HANDSHAKE_TIMEOUT = 4,
RTW_DHCP_FAIL = 5,
RTW_UNKNOWN,
}rtw_connect_error_flag_t;
typedef enum {
RTW_TX_PWR_PERCENTAGE_100 = 0, /* 100%, default target output power. */
RTW_TX_PWR_PERCENTAGE_75 = 1, /* 75% */
RTW_TX_PWR_PERCENTAGE_50 = 2, /* 50% */
RTW_TX_PWR_PERCENTAGE_25 = 3, /* 25% */
RTW_TX_PWR_PERCENTAGE_12_5 = 4, /* 12.5% */
}rtw_tx_pwr_percentage_t;
/**
* @brief The enumeration is event type indicated from wlan driver.
*/
typedef enum _WIFI_EVENT_INDICATE{
WIFI_EVENT_CONNECT = 0,
WIFI_EVENT_DISCONNECT = 1,
WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2,
WIFI_EVENT_SCAN_RESULT_REPORT = 3,
WIFI_EVENT_SCAN_DONE = 4,
WIFI_EVENT_RECONNECTION_FAIL = 5,
WIFI_EVENT_SEND_ACTION_DONE = 6,
WIFI_EVENT_RX_MGNT = 7,
WIFI_EVENT_STA_ASSOC = 8,
WIFI_EVENT_STA_DISASSOC = 9,
WIFI_EVENT_STA_WPS_START = 10,
WIFI_EVENT_WPS_FINISH = 11,
WIFI_EVENT_EAPOL_START = 12,
WIFI_EVENT_EAPOL_RECVD = 13,
WIFI_EVENT_NO_NETWORK = 14,
WIFI_EVENT_BEACON_AFTER_DHCP = 15,
WIFI_EVENT_IP_CHANGED = 16,
WIFI_EVENT_ICV_ERROR = 17,
WIFI_EVENT_CHALLENGE_FAIL = 18,
WIFI_EVENT_MAX,
}rtw_event_indicate_t;
#ifdef __cplusplus
}
#endif
/*\@}*/
#endif /* _WIFI_CONSTANTS_H */

261
component/common/drivers/wlan/realtek/include/wifi_structures.h Executable file
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/**
******************************************************************************
* @file wifi_structures.h
* @author
* @version
* @brief This file provides the data structures used for wlan API.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _WIFI_STRUCTURES_H
#define _WIFI_STRUCTURES_H
/** @addtogroup nic NIC
* @ingroup wlan
* @brief NIC functions
* @{
*/
//#include <freertos/freertos_service.h>
#include "wifi_constants.h"
#include "dlist.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__IAR_SYSTEMS_ICC__)|| defined (__GNUC__)
#pragma pack(1)
#endif
/**
* @brief The structure is used to describe the SSID.
*/
typedef struct rtw_ssid {
unsigned char len; /**< SSID length */
unsigned char val[33]; /**< SSID name (AP name) */
} rtw_ssid_t;
#if defined(__IAR_SYSTEMS_ICC__)|| defined (__GNUC__)
#pragma pack()
#endif
#if defined(__IAR_SYSTEMS_ICC__)|| defined (__GNUC__)
#pragma pack(1)
#endif
/**
* @brief The structure is used to describe the unique 6-byte MAC address.
*/
typedef struct rtw_mac {
unsigned char octet[6]; /**< Unique 6-byte MAC address */
} rtw_mac_t;
#if defined(__IAR_SYSTEMS_ICC__)|| defined (__GNUC__)
#pragma pack()
#endif
/**
* @brief The structure is used to describe the setting about SSID,
* security type, password and default channel, used to start AP mode.
* @note The data length of string pointed by ssid should not exceed 32,
* and the data length of string pointed by password should not exceed 64.
*/
typedef struct rtw_ap_info {
rtw_ssid_t ssid;
rtw_security_t security_type;
unsigned char *password;
int password_len;
int channel;
}rtw_ap_info_t;
/**
* @brief The structure is used to describe the station mode setting about SSID,
* security type and password, used when connecting to an AP.
* @note The data length of string pointed by ssid should not exceed 32,
* and the data length of string pointed by password should not exceed 64.
*/
typedef struct rtw_network_info {
rtw_ssid_t ssid;
rtw_mac_t bssid;
rtw_security_t security_type;
unsigned char *password;
int password_len;
int key_id;
}rtw_network_info_t;
#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
#pragma pack(1)
#endif
/**
* @brief The structure is used to describe the scan result of the AP.
*/
typedef struct rtw_scan_result {
rtw_ssid_t SSID; /**< Service Set Identification (i.e. Name of Access Point) */
rtw_mac_t BSSID; /**< Basic Service Set Identification (i.e. MAC address of Access Point) */
signed short signal_strength; /**< Receive Signal Strength Indication in dBm. <-90=Very poor, >-30=Excellent */
rtw_bss_type_t bss_type; /**< Network type */
rtw_security_t security; /**< Security type */
rtw_wps_type_t wps_type; /**< WPS type */
unsigned int channel; /**< Radio channel that the AP beacon was received on */
rtw_802_11_band_t band; /**< Radio band */
} rtw_scan_result_t;
#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
#pragma pack()
#endif
/**
* @brief The structure is used to describe the data needed by scan result handler function.
*/
typedef struct rtw_scan_handler_result {
rtw_scan_result_t ap_details;
rtw_bool_t scan_complete;
void* user_data;
} rtw_scan_handler_result_t;
#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
#pragma pack(1)
#endif
/**
* @brief The structure is used to store the WIFI setting gotten from WIFI driver.
*/
typedef struct rtw_wifi_setting {
rtw_mode_t mode;
unsigned char ssid[33];
unsigned char channel;
rtw_security_t security_type;
unsigned char password[65];
unsigned char key_idx;
}rtw_wifi_setting_t;
#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
#pragma pack()
#endif
/**
* @brief The structure is used to describe the setting when configure the network.
*/
typedef struct rtw_wifi_config {
unsigned int boot_mode;
unsigned char ssid[32];
unsigned char ssid_len;
unsigned char security_type;
unsigned char password[65];
unsigned char password_len;
unsigned char channel;
} rtw_wifi_config_t;
/**
* @brief The structure is used to describe the maclist.
*/
typedef struct
{
unsigned int count; /**< Number of MAC addresses in the list */
rtw_mac_t mac_list[1]; /**< Variable length array of MAC addresses */
} rtw_maclist_t;
/**
* @brief The structure is used to describe the bss info of the network.\n
* It include the version, BSSID, beacon_period, capability, SSID,
* channel, atm_window, dtim_period, RSSI e.g.
*/
typedef struct {
unsigned int version; /**< version field */
unsigned int length; /**< byte length of data in this record, */
/* starting at version and including IEs */
rtw_mac_t BSSID;
unsigned short beacon_period; /**< units are Kusec */
unsigned short capability; /**< Capability information */
unsigned char SSID_len;
unsigned char SSID[32];
unsigned char channel;
// struct {
// uint32_t count; /* # rates in this set */
// uint8_t rates[16]; /* rates in 500kbps units w/hi bit set if basic */
// } rateset; /* supported rates */
// rtw_chanspec_t chanspec; /* chanspec for bss */
unsigned short atim_window; /**< units are Kusec */
unsigned char dtim_period; /**< DTIM period */
signed short RSSI; /**< receive signal strength (in dBm) */
unsigned char n_cap; /**< BSS is 802.11N Capable */
unsigned int nbss_cap; /**< 802.11N BSS Capabilities (based on HT_CAP_*) */
unsigned char basic_mcs[MCSSET_LEN]; /**< 802.11N BSS required MCS set */
unsigned short ie_offset; /**< offset at which IEs start, from beginning */
unsigned int ie_length; /**< byte length of Information Elements */
} rtw_bss_info_t;
/**
* @brief The structure is used to set WIFI packet filter pattern.
*/
typedef struct {
unsigned short offset; /**< Offset in bytes to start filtering (referenced to the start of the ethernet packet) */
unsigned short mask_size; /**< Size of the mask in bytes */
unsigned char* mask; /**< Pattern mask bytes to be ANDed with the pattern eg. "\xff00" (must be in network byte order) */
unsigned char* pattern; /**< Pattern bytes used to filter eg. "\x0800" (must be in network byte order) */
} rtw_packet_filter_pattern_t;
typedef struct ieee80211_frame_info{
unsigned short i_fc;
unsigned short i_dur;
unsigned char i_addr1[6];
unsigned char i_addr2[6];
unsigned char i_addr3[6];
unsigned short i_seq;
unsigned char bssid[6];
unsigned char encrypt;
signed char rssi;
#if CONFIG_UNSUPPORT_PLCPHDR_RPT
rtw_rx_type_t type;
#endif
}ieee80211_frame_info_t;
#if CONFIG_UNSUPPORT_PLCPHDR_RPT
typedef struct rtw_rx_info {
unsigned short length; // length without FCS
unsigned char filter; // 1: HT-20 2T and not LDPC pkt; 2: HT-40 2T and not LDPC pkt; 3: LDPC pkt
signed char rssi; // -128~-1
unsigned short channel; // channel whick this pkt in
unsigned char agg:1; // aggregation pkt or not. If an AMPDU contains only one MPDU then above 'length' is the antual pkt length without FCS, buuut if it contains multiple MPDUs then above 'length' is useless because it cannot tell how many MPDUs are contained and how long is each MPDU.
unsigned char mcs:7; // mcs index
}rtw_rx_info_t;
struct rtw_plcp_info {
struct rtw_plcp_info *prev;
struct rtw_plcp_info *next;
rtw_rx_info_t rtw_plcp_info;
};
struct rtw_rx_buffer {
struct rtw_plcp_info *head;
struct rtw_plcp_info *tail;
};
#endif
typedef struct {
char filter_id;
rtw_packet_filter_pattern_t patt;
rtw_packet_filter_rule_t rule;
unsigned char enable;
}rtw_packet_filter_info_t;
typedef struct rtw_mac_filter_list{
struct list_head node;
unsigned char mac_addr[6];
}rtw_mac_filter_list_t;
#ifdef __cplusplus
}
#endif
/*\@}*/
#endif /* _WIFI_STRUCTURES_H */

24
component/common/drivers/wlan/realtek/src/core/option/rtw_opt_power_by_rate.c Executable file
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@ -0,0 +1,24 @@
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
// Note: power index value = power*2
// => ex: 16dBm => 0x32 , 13dBm => 0x26, 0x26262830 => 13 13 14 15 dBm
unsigned int Array_MP_8195A_PHY_REG_PG[] = {
0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200,// 1M (16 dBm)
0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200,// 11M 5.5M 2M (16 16 16 dBm)
0, 0, 0, 0x00000e00, 0xffffffff, 0x34363636,// 18M 12M 9M 6M (17 18 18 18 dBm)
0, 0, 0, 0x00000e04, 0xffffffff, 0x28303234,// 54M 48M 36M 24M (14 15 16 17 dBm)
0, 0, 0, 0x00000e10, 0xffffffff, 0x30343434,// MCS3 MCS2 MCS1 MCS0 (15 17 17 17 dBm)
0, 0, 0, 0x00000e14, 0xffffffff, 0x26262830 // MCS7 MCS6 MCS5 MCS4 (13 13 14 15 dBm)
};
const unsigned int Array_MP_8711B_PHY_REG_PG[] = {
0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200,// 1M (16 dBm)
0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200,// 11M 5.5M 2M (16 16 16 dBm)
0, 0, 0, 0x00000e00, 0xffffffff, 0x34363636,// 18M 12M 9M 6M (17 18 18 18 dBm)
0, 0, 0, 0x00000e04, 0xffffffff, 0x28303234,// 54M 48M 36M 24M (14 15 16 17 dBm)
0, 0, 0, 0x00000e10, 0xffffffff, 0x30343434,// MCS3 MCS2 MCS1 MCS0 (15 17 17 17 dBm)
0, 0, 0, 0x00000e14, 0xffffffff, 0x26262830// MCS7 MCS6 MCS5 MCS4 (13 13 14 15 dBm)
};

390
component/common/drivers/wlan/realtek/src/core/option/rtw_opt_power_limit.c Executable file
View file

@ -0,0 +1,390 @@
/******************************************************************************
* TXPWR_LMT.TXT
******************************************************************************/
typedef enum _ODM_PW_LMT_REGULATION_TYPE{
PW_LMT_REGU_NULL = 0,
PW_LMT_REGU_FCC = 1,
PW_LMT_REGU_ETSI = 2,
PW_LMT_REGU_MKK = 3,
PW_LMT_REGU_WW13 = 4
}ODM_PW_LMT_REGULATION_TYPE;
typedef enum _ODM_PW_LMT_BAND_TYPE{
PW_LMT_BAND_NULL = 0,
PW_LMT_BAND_2_4G = 1,
PW_LMT_BAND_5G = 2
}ODM_PW_LMT_BAND_TYPE;
typedef enum _ODM_PW_LMT_BANDWIDTH_TYPE{
PW_LMT_BW_NULL = 0,
PW_LMT_BW_20M = 1,
PW_LMT_BW_40M = 2,
PW_LMT_BW_80M = 3
}ODM_PW_LMT_BANDWIDTH_TYPE;
typedef enum _ODM_PW_LMT_RATESECTION_TYPE{
PW_LMT_RS_NULL = 0,
PW_LMT_RS_CCK = 1,
PW_LMT_RS_OFDM = 2,
PW_LMT_RS_HT = 3,
PW_LMT_RS_VHT = 4
}ODM_PW_LMT_RATESECTION_TYPE;
typedef enum _ODM_PW_LMT_RFPATH_TYPE{
PW_LMT_PH_NULL = 0,
PW_LMT_PH_1T = 1,
PW_LMT_PH_2T = 2,
PW_LMT_PH_3T = 3,
PW_LMT_PH_4T = 4
}ODM_PW_LMT_RFPATH_TYPE;
typedef unsigned char u1Byte;
// Note: power index = power*2
// => ex: if power = 16dBm, set power index = 32
const u1Byte Array_MP_8195A_TXPWR_LMT[] = {
// regulation, band, bandwidth, rate, path, channel, power index
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 1, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 1, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 1, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 2, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 2, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 2, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 3, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 3, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 3, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 4, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 4, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 4, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 5, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 5, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 5, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 6, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 6, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 6, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 7, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 7, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 7, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 8, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 8, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 8, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 9, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 9, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 9, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 10, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 10, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 10, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 11, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 11, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 11, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 12, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 12, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 12, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 13, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 13, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 13, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 14, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 1, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 1, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 1, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 2, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 2, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 2, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 3, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 3, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 3, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 4, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 4, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 4, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 5, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 5, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 5, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 6, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 6, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 6, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 7, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 7, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 7, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 8, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 8, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 8, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 9, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 9, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 9, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 10, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 10, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 10, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 11, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 11, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 11, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 12, 24,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 12, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 12, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 13, 12,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 13, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 13, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 1, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 1, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 1, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 2, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 2, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 2, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 3, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 3, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 3, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 4, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 4, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 4, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 5, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 5, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 5, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 6, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 6, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 6, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 7, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 7, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 7, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 8, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 8, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 8, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 9, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 9, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 9, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 10, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 10, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 10, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 11, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 11, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 11, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 12, 24,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 12, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 12, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 13, 12,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 13, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 13, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 1, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 1, 63,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 1, 63,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 2, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 2, 63,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 2, 63,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 3, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 3, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 3, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 4, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 4, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 4, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 5, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 5, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 5, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 6, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 6, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 6, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 7, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 7, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 7, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 8, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 8, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 8, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 9, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 9, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 9, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 10, 24,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 10, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 10, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 11, 6,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 11, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 11, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 12, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 12, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 12, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 13, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 13, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 13, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 14, 63
};
const u1Byte Array_MP_8711B_TXPWR_LMT[] = {
/* regulation, band, bandwidth, rateSection, rfPath, chnl, value */
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 1, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 1, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 1, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 2, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 2, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 2, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 3, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 3, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 3, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 4, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 4, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 4, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 5, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 5, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 5, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 6, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 6, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 6, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 7, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 7, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 7, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 8, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 8, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 8, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 9, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 9, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 9, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 10, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 10, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 10, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 11, 32,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 11, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 11, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 12, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 12, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 12, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 13, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 13, 28,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 13, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_CCK, PW_LMT_PH_1T, 14, 32,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 1, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 1, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 1, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 2, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 2, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 2, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 3, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 3, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 3, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 4, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 4, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 4, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 5, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 5, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 5, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 6, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 6, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 6, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 7, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 7, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 7, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 8, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 8, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 8, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 9, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 9, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 9, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 10, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 10, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 10, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 11, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 11, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 11, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 12, 24,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 12, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 12, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 13, 12,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 13, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 13, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_OFDM, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 1, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 1, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 1, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 2, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 2, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 2, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 3, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 3, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 3, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 4, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 4, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 4, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 5, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 5, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 5, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 6, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 6, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 6, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 7, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 7, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 7, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 8, 30,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 8, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 8, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 9, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 9, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 9, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 10, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 10, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 10, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 11, 28,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 11, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 11, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 12, 24,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 12, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 12, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 13, 12,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 13, 30,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 13, 30,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_20M, PW_LMT_RS_HT, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 1, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 1, 63,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 1, 63,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 2, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 2, 63,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 2, 63,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 3, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 3, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 3, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 4, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 4, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 4, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 5, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 5, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 5, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 6, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 6, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 6, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 7, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 7, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 7, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 8, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 8, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 8, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 9, 26,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 9, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 9, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 10, 24,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 10, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 10, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 11, 6,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 11, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 11, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 12, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 12, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 12, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 13, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 13, 26,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 13, 26,
PW_LMT_REGU_FCC, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_ETSI, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 14, 63,
PW_LMT_REGU_MKK, PW_LMT_BAND_2_4G, PW_LMT_BW_40M, PW_LMT_RS_HT, PW_LMT_PH_1T, 14, 63
};

70
component/common/drivers/wlan/realtek/src/core/option/rtw_opt_skbuf.c Executable file
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@ -0,0 +1,70 @@
#include <section_config.h>
#include <osdep_service.h>
#include <skbuff.h>
#define MAX_SKB_BUF_SIZE 1650 // should >= the size in wlan driver
#define MAX_SKB_BUF_NUM 8
#define MAX_LOCAL_SKB_NUM (MAX_SKB_BUF_NUM + 2)
/* DO NOT modify skb_buf and skb_data structure */
struct skb_buf {
struct list_head list;
struct sk_buff skb;
};
struct skb_data {
struct list_head list;
unsigned char buf[MAX_SKB_BUF_SIZE];
atomic_t ref;
};
unsigned int nr_xmitframe = MAX_SKB_BUF_NUM;
unsigned int nr_xmitbuff = MAX_SKB_BUF_NUM;
int max_local_skb_num = MAX_LOCAL_SKB_NUM;
int max_skb_buf_num = MAX_SKB_BUF_NUM;
/* DO NOT access skb_pool and skb_data_pool out of wlan driver */
struct skb_buf skb_pool[MAX_LOCAL_SKB_NUM];
#define SKB_DATA_POOL_USING_GLOBAL_BUF 1
#if SKB_DATA_POOL_USING_GLOBAL_BUF
// SRAM_BD_DATA_SECTION default in SRAM. Can modify image2.icf to link to the end of SDRAM
SRAM_BD_DATA_SECTION
struct skb_data skb_data_pool[MAX_SKB_BUF_NUM];
#else
// Change to use heap (malloc) to save SRAM memory
SRAM_BD_DATA_SECTION
struct skb_data * skb_data_pool;
extern struct list_head skbdata_list;
extern int skbdata_used_num;
extern int max_skbdata_used_num;
void init_skb_data_pool(void)
{
int i;
//printf("\ninit_skb_data_pool\n");
skb_data_pool = (struct skb_data *)rtw_zmalloc(max_skb_buf_num * sizeof(struct skb_data));
if(!skb_data_pool){
printf("\nskb_data_pool alloc fail\n");
return;
}
memset(skb_data_pool, '\0', max_skb_buf_num*sizeof(struct skb_data));
INIT_LIST_HEAD(&skbdata_list);
for (i=0; i<max_skb_buf_num; i++) {
INIT_LIST_HEAD(&skb_data_pool[i].list);
list_add_tail(&skb_data_pool[i].list, &skbdata_list);
}
skbdata_used_num = 0;
max_skbdata_used_num = 0;
}
void deinit_skb_data_pool(void)
{
//printf("\ndeinit_skb_data_pool\n");
rtw_mfree(skb_data_pool, MAX_SKB_BUF_NUM * sizeof(struct skb_data));
}
#endif

440
component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h Executable file
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#ifndef __WRAPPER_H__
#define __WRAPPER_H__
/**************************************************************************
* Wrapper provide a linux-like interface
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
************************************************************************/
//----- ------------------------------------------------------------------
// Include Files
//----- ------------------------------------------------------------------
#include <stdio.h>
#include <string.h>
#include "wireless.h"
#include <skbuff.h>
#include "freertos_service.h"
#ifndef __LIST_H
#warning "DLIST_NOT_DEFINE!!!!!!"
//----- ------------------------------------------------------------------
// Linled List
//----- ------------------------------------------------------------------
/*
* Simple doubly linked list implementation.
*
* Some of the internal functions ("__xxx") are useful when
* manipulating whole lists rather than single entries, as
* sometimes we already know the next/prev entries and we can
* generate better code by using them directly rather than
* using the generic single-entry routines.
*/
// struct list_head {
// struct list_head *next, *prev;
// };
#define LIST_HEAD_INIT(name) { &(name), &(name) }
#define INIT_LIST_HEAD(ptr) do { \
(ptr)->next = (ptr); (ptr)->prev = (ptr); \
} while (0)
/*
* Insert a new entry between two known consecutive entries.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static __inline void __list_add(struct list_head * new,
struct list_head * prev,
struct list_head * next)
{
next->prev = new;
new->next = next;
new->prev = prev;
prev->next = new;
}
/*
* Delete a list entry by making the prev/next entries
* point to each other.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static __inline void __list_del(struct list_head * prev,
struct list_head * next)
{
next->prev = prev;
prev->next = next;
}
/**
* list_del - deletes entry from list.
* @entry: the element to delete from the list.
* Note: list_empty on entry does not return true after this, the entry is in an undefined state.
*/
static __inline void list_del(struct list_head *entry)
{
__list_del(entry->prev, entry->next);
}
/**
* list_del_init - deletes entry from list and reinitialize it.
* @entry: the element to delete from the list.
*/
static __inline void list_del_init(struct list_head *entry)
{
__list_del(entry->prev, entry->next);
INIT_LIST_HEAD(entry);
}
/**
* list_empty - tests whether a list is empty
* @head: the list to test.
*/
static __inline int list_empty(struct list_head *head)
{
return head->next == head;
}
/**
* list_splice - join two lists
* @list: the new list to add.
* @head: the place to add it in the first list.
*/
static __inline void list_splice(struct list_head *list, struct list_head *head)
{
struct list_head *first = list->next;
if (first != list) {
struct list_head *last = list->prev;
struct list_head *at = head->next;
first->prev = head;
head->next = first;
last->next = at;
at->prev = last;
}
}
void list_add(struct list_head *new, struct list_head *head);
void list_add_tail(struct list_head *new, struct list_head *head);
#endif
extern void save_and_cli(void);
extern void restore_flags(void);
//----- ------------------------------------------------------------------
// SKB Operation
//----- ------------------------------------------------------------------
#define SMP_CACHE_BYTES 4
#define SKB_DATA_ALIGN(X) (((X) + (SMP_CACHE_BYTES - 1)) & ~(SMP_CACHE_BYTES - 1))
// Consideration for SKB size
// Tx: [INTF_CMD][TX_DESC][WLAN_HDR][QoS][IV][SNAP][Data][MIC][ICV][INTF_STATUS]
// Since SKB is used to accept ethernet packet from upper layer, SKB length of WLAN_MAX_ETHFRM_LEN
// (= 1514) is enough. But since SKB is also used to get spi receive packet, overall buffer space
// should be taken into consideration.
// RX: [INTF_CMD][RX_DESC][Drv_Info][WLAN_HDR][QoS][IV][SNAP][Data][MIC][ICV][CRC][INTF_STATUS]
//
// 32: Driver_Info that carry phy related information for each packets. Required only for receive case.
// WLAN_MAX_ETHFRM_LEN : May not be required because WLAN_HEADER +SNAP can totally
// cover ethernet header. Keep in only for safety.
//
// **Notes** SDIO requires 512 blocks r/w, so 512*4 = 2048 is required.
// 2003/12/26. The value is reduced from 2048 to 1658 for GSPI
// 2014/02/05. The value is 1650 for 8195A LX_BUS
#define SKB_RESERVED_FOR_SAFETY 0
#define SKB_WLAN_TX_EXTRA_LEN (TXDESC_SIZE + WLAN_HDR_A4_QOS_LEN + WLAN_MAX_IV_LEN + WLAN_SNAP_HEADER - WLAN_ETHHDR_LEN)
#define RX_DRIVER_INFO 32
#if (defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI)
#define HAL_INTERFACE_OVERHEAD_SKB_DATA 12 //HAL_INTERFACE_CMD (4) + HAL_INTERFACE_STATUS (8)
#elif defined(CONFIG_LX_HCI)
#define HAL_INTERFACE_OVERHEAD_SKB_DATA 0
#endif
#if defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI || defined(CONFIG_LX_HCI)
#if defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B)
#if defined(CONFIG_MP_INCLUDED)
#ifdef CONFIG_DONT_CARE_TP
#define MAX_RX_PKT_LIMIT ((WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN + 511) / 512) // 4, for lxbus
#else
#define MAX_RX_PKT_LIMIT ((WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN + 511) / 512) // 4, for lxbus
#endif
#define MAX_RX_PKT_SIZE MAX_RX_PKT_LIMIT*512 // MAX_SKB_BUF_SIZE = 0+32+40+512*4+0 = 2120
#else
#ifdef CONFIG_DONT_CARE_TP
#define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN
#else
#define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN // MAX_RX_PKT_SIZE = 64+1514 = 1578
#endif
#define MAX_RX_PKT_LIMIT ((MAX_RX_PKT_SIZE + 511) / 512) // ((1578 + 512) / 512) = 4
#endif
#else
#ifdef CONFIG_DONT_CARE_TP
#define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN
#else
#define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN
#endif
#endif
#ifdef CONFIG_DONT_CARE_TP
#define MAX_TX_SKB_BUF_SIZE (HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\
((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\
WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_TX_ETHFRM_LEN +\
SKB_RESERVED_FOR_SAFETY)
#define MAX_RX_SKB_BUF_SIZE (HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\
((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\
MAX_RX_PKT_SIZE +\
SKB_RESERVED_FOR_SAFETY)
#else
#define MAX_SKB_BUF_SIZE (HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\
((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\
MAX_RX_PKT_SIZE +\
SKB_RESERVED_FOR_SAFETY) // 0+32+40+1578+0 = 1650
#endif
#else
#define MAX_SKB_BUF_SIZE 2048
#endif
#if 0
struct sk_buff_head {
struct list_head *next, *prev;
u32 qlen;
};
struct sk_buff {
/* These two members must be first. */
struct sk_buff *next; /* Next buffer in list */
struct sk_buff *prev; /* Previous buffer in list */
struct sk_buff_head *list; /* List we are on */
unsigned char *head; /* Head of buffer */
unsigned char *data; /* Data head pointer */
unsigned char *tail; /* Tail pointer */
unsigned char *end; /* End pointer */
struct net_device *dev; /* Device we arrived on/are leaving by */
unsigned int len; /* Length of actual data */
};
/**
* skb_put - add data to a buffer
* @skb: buffer to use
* @len: amount of data to add
*
* This function extends the used data area of the buffer. If this would
* exceed the total buffer size the kernel will panic. A pointer to the
* first byte of the extra data is returned.
*/
static __inline__ unsigned char *skb_put(struct sk_buff *skb, unsigned int len)
{
unsigned char *tmp=skb->tail;
skb->tail+=len;
skb->len+=len;
if(skb->tail>skb->end) {
ASSERT(0);
}
return tmp;
}
static __inline__ unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len)
{
skb->len-=len;
skb->data = (unsigned char *)(((unsigned int)skb->data) + len);
return skb->data;
}
/**
* skb_reserve - adjust headroom
* @skb: buffer to alter
* @len: bytes to move
*
* Increase the headroom of an empty &sk_buff by reducing the tail
* room. This is only allowed for an empty buffer.
*/
static __inline__ void skb_reserve(struct sk_buff *skb, unsigned int len)
{
skb->data+=len;
skb->tail+=len;
}
static __inline__ void skb_queue_head_init(struct sk_buff_head *list)
{
list->prev = (struct list_head *)list;
list->next = (struct list_head *)list;
list->qlen = 0;
}
/**
* __skb_queue_tail - queue a buffer at the list tail
* @list: list to use
* @newsk: buffer to queue
*
* Queue a buffer at the end of a list. This function takes no locks
* and you must therefore hold required locks before calling it.
*
* A buffer cannot be placed on two lists at the same time.
*/
static __inline__ void __skb_queue_tail(struct sk_buff_head *list, struct sk_buff *newsk)
{
struct sk_buff *prev, *next;
newsk->list = list;
list->qlen++;
next = (struct sk_buff *)list;
prev = next->prev;
newsk->next = next;
newsk->prev = prev;
next->prev = newsk;
prev->next = newsk;
}
/**
* skb_queue_tail - queue a buffer at the list tail
* @list: list to use
* @newsk: buffer to queue
*
* Queue a buffer at the tail of the list. This function takes the
* list lock and can be used safely with other locking &sk_buff functions
* safely.
*
* A buffer cannot be placed on two lists at the same time.
*/
static __inline__ void skb_queue_tail(struct sk_buff_head *list, struct sk_buff *newsk)
{
save_and_cli();
__skb_queue_tail(list, newsk);
restore_flags();
}
static __inline__ void skb_assign_buf(struct sk_buff *skb, unsigned char *buf, unsigned int len)
{
skb->head = buf;
skb->data = buf;
skb->tail = buf;
skb->end = buf + len;
}
static __inline__ unsigned char *skb_tail_pointer(const struct sk_buff *skb)
{
return skb->tail;
}
static __inline__ void skb_reset_tail_pointer(struct sk_buff *skb)
{
skb->tail = skb->data;
}
static __inline__ void skb_set_tail_pointer(struct sk_buff *skb, const int offset)
{
skb->tail = skb->data + offset;
}
static __inline__ unsigned char *skb_end_pointer(const struct sk_buff *skb)
{
return skb->end;
}
#endif
/*
* External functions
*/
struct net_device;
extern void kfree_skb_chk_key(struct sk_buff *skb, struct net_device *root_dev);
#ifdef CONFIG_TRACE_SKB
extern void show_skb(void);
extern int _set_skb_list_flag(struct sk_buff *skb, unsigned int queueflag);
extern void dump_skb_list(void);
#define set_skb_list_flag(skb, queueflag) \
(\
_set_skb_list_flag((skb), queueflag), \
(skb) ? (skb)->funcname[(skb)->list_idx] = __FUNCTION__:NULL \
)
extern int _clear_skb_list_flag(struct sk_buff *skb, unsigned int queueflag);
#define clear_skb_list_flag(skb, queueflag) \
(\
_clear_skb_list_flag((skb), queueflag), \
(skb) ? (skb)->funcname[(skb)->list_idx] = __FUNCTION__ : NULL \
)
#define dev_kfree_skb_any(trx, holder, skb) \
do{\
clear_skb_list_flag(skb, SKBLIST_##trx##holder##_MASK);\
set_skb_list_flag(skb, SKBLIST_POOL);\
kfree_skb_chk_key(skb, skb->dev);\
}while (0)
#else
#define dev_kfree_skb_any(skb) kfree_skb_chk_key(skb, skb->dev)
#endif
extern struct sk_buff *dev_alloc_skb(unsigned int length, unsigned int reserve_len);
extern struct sk_buff *skb_clone(struct sk_buff *skb, int gfp_mask);
extern struct sk_buff *skb_copy(const struct sk_buff *skb, int gfp_mask, unsigned int reserve_len);
extern unsigned char *skb_pull(struct sk_buff *skb, unsigned int len);
//----- ------------------------------------------------------------------
// Device structure
//----- ------------------------------------------------------------------
struct net_device_stats {
unsigned long rx_packets; /* total packets received */
unsigned long tx_packets; /* total packets transmitted */
unsigned long rx_dropped; /* no space in linux buffers */
unsigned long tx_dropped; /* no space available in linux */
unsigned long rx_bytes; /* total bytes received */
unsigned long tx_bytes; /* total bytes transmitted */
unsigned long rx_overflow; /* rx fifo overflow count */
};
struct net_device {
char name[16];
void *priv; /* pointer to private data */
unsigned char dev_addr[6]; /* set during bootup */
int (*init)(void);
int (*open)(struct net_device *dev);
int (*stop)(struct net_device *dev);
int (*hard_start_xmit)(struct sk_buff *skb, struct net_device *dev);
int (*do_ioctl)(struct net_device *dev, struct iwreq *ifr, int cmd);
struct net_device_stats* (*get_stats)(struct net_device *dev);
};
typedef struct {
struct net_device *dev; /* Binding wlan driver netdev */
void *skb; /* pending Rx packet */
unsigned int tx_busy;
unsigned int rx_busy;
unsigned char enable;
unsigned char mac[6];
} Rltk_wlan_t;
#define netdev_priv(dev) dev->priv
extern struct net_device *alloc_etherdev(int sizeof_priv);
void free_netdev(struct net_device *dev);
int dev_alloc_name(struct net_device *net_dev, const char *ifname);
//----- ------------------------------------------------------------------
// Timer Operation
//----- ------------------------------------------------------------------
void init_timer(struct timer_list *timer);
void mod_timer(struct timer_list *timer, u32 delay_time_ms);
void cancel_timer_ex(struct timer_list * timer);
void del_timer_sync(struct timer_list * timer);
void init_timer_wrapper(void);
void deinit_timer_wrapper(void);
void rtw_init_timer(_timer *ptimer, void *adapter, TIMER_FUN pfunc,void* cntx, const char *name);
void rtw_set_timer(_timer *ptimer,u32 delay_time);
u8 rtw_cancel_timer(_timer *ptimer);
void rtw_del_timer(_timer *ptimer);
#endif //__WRAPPER_H__

236
component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c Executable file
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@ -0,0 +1,236 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//#define _LWIP_INTF_C_
#include <autoconf.h>
#include <lwip_intf.h>
#include <lwip/netif.h>
#include <lwip_netconf.h>
#include <ethernetif.h>
#include <osdep_service.h>
#include <wifi/wifi_util.h>
//----- ------------------------------------------------------------------
// External Reference
//----- ------------------------------------------------------------------
#if (CONFIG_LWIP_LAYER == 1)
extern struct netif xnetif[]; //LWIP netif
#endif
/**
* rltk_wlan_set_netif_info - set netif hw address and register dev pointer to netif device
* @idx_wlan: netif index
* 0 for STA only or SoftAP only or STA in STA+SoftAP concurrent mode,
* 1 for SoftAP in STA+SoftAP concurrent mode
* @dev: register netdev pointer to LWIP. Reserved.
* @dev_addr: set netif hw address
*
* Return Value: None
*/
void rltk_wlan_set_netif_info(int idx_wlan, void * dev, unsigned char * dev_addr)
{
#if (CONFIG_LWIP_LAYER == 1)
rtw_memcpy(xnetif[idx_wlan].hwaddr, dev_addr, 6);
xnetif[idx_wlan].state = dev;
#endif
}
/**
* rltk_wlan_send - send IP packets to WLAN. Called by low_level_output().
* @idx: netif index
* @sg_list: data buffer list
* @sg_len: size of each data buffer
* @total_len: total data len
*
* Return Value: None
*/
int rltk_wlan_send(int idx, struct eth_drv_sg *sg_list, int sg_len, int total_len)
{
#if (CONFIG_LWIP_LAYER == 1)
struct eth_drv_sg *last_sg;
struct sk_buff *skb = NULL;
int ret = 0;
if(idx == -1){
DBG_ERR("netif is DOWN");
return -1;
}
DBG_TRACE("%s is called", __FUNCTION__);
save_and_cli();
if(rltk_wlan_check_isup(idx))
rltk_wlan_tx_inc(idx);
else {
DBG_ERR("netif is DOWN");
restore_flags();
return -1;
}
restore_flags();
skb = rltk_wlan_alloc_skb(total_len);
if (skb == NULL) {
//DBG_ERR("rltk_wlan_alloc_skb() for data len=%d failed!", total_len);
ret = -1;
goto exit;
}
for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
rtw_memcpy(skb->tail, (void *)(sg_list->buf), sg_list->len);
skb_put(skb, sg_list->len);
}
rltk_wlan_send_skb(idx, skb);
exit:
save_and_cli();
rltk_wlan_tx_dec(idx);
restore_flags();
return ret;
#endif
}
/**
* rltk_wlan_recv - indicate packets to LWIP. Called by ethernetif_recv().
* @idx: netif index
* @sg_list: data buffer list
* @sg_len: size of each data buffer
*
* Return Value: None
*/
void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len)
{
#if (CONFIG_LWIP_LAYER == 1)
struct eth_drv_sg *last_sg;
struct sk_buff *skb;
DBG_TRACE("%s is called", __FUNCTION__);
if(idx == -1){
DBG_ERR("skb is NULL");
return;
}
skb = rltk_wlan_get_recv_skb(idx);
DBG_ASSERT(skb, "No pending rx skb");
for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
if (sg_list->buf != 0) {
rtw_memcpy((void *)(sg_list->buf), skb->data, sg_list->len);
skb_pull(skb, sg_list->len);
}
}
#endif
}
int netif_is_valid_IP(int idx, unsigned char *ip_dest)
{
#if CONFIG_LWIP_LAYER == 1
struct netif * pnetif = &xnetif[idx];
struct ip_addr addr = { 0 };
#ifdef CONFIG_MEMORY_ACCESS_ALIGNED
unsigned int temp;
memcpy(&temp, ip_dest, sizeof(unsigned int));
u32_t *ip_dest_addr = &temp;
#else
u32_t *ip_dest_addr = (u32_t*)ip_dest;
#endif
addr.addr = *ip_dest_addr;
if(pnetif->ip_addr.addr == 0)
return 1;
if(ip_addr_ismulticast(&addr) || ip_addr_isbroadcast(&addr,pnetif)){
return 1;
}
//if(ip_addr_netcmp(&(pnetif->ip_addr), &addr, &(pnetif->netmask))) //addr&netmask
// return 1;
if(ip_addr_cmp(&(pnetif->ip_addr),&addr))
return 1;
DBG_TRACE("invalid IP: %d.%d.%d.%d ",ip_dest[0],ip_dest[1],ip_dest[2],ip_dest[3]);
#endif
#ifdef CONFIG_DONT_CARE_TP
if(pnetif->flags & NETIF_FLAG_IPSWITCH)
return 1;
else
#endif
return 0;
}
int netif_get_idx(struct netif* pnetif)
{
#if CONFIG_LWIP_LAYER == 1
int idx = pnetif - xnetif;
switch(idx) {
case 0:
return 0;
case 1:
return 1;
default:
return -1;
}
#else
return -1;
#endif
}
unsigned char *netif_get_hwaddr(int idx_wlan)
{
#if (CONFIG_LWIP_LAYER == 1)
return xnetif[idx_wlan].hwaddr;
#else
return NULL;
#endif
}
void netif_rx(int idx, unsigned int len)
{
#if (CONFIG_LWIP_LAYER == 1)
ethernetif_recv(&xnetif[idx], len);
#endif
#if (CONFIG_INIC_EN == 1)
inic_netif_rx(idx, len);
#endif
}
void netif_post_sleep_processing(void)
{
#if (CONFIG_LWIP_LAYER == 1)
lwip_POST_SLEEP_PROCESSING(); //For FreeRTOS tickless to enable Lwip ARP timer when leaving IPS - Alex Fang
#endif
}
void netif_pre_sleep_processing(void)
{
#if (CONFIG_LWIP_LAYER == 1)
lwip_PRE_SLEEP_PROCESSING();
#endif
}
#ifdef CONFIG_WOWLAN
unsigned char *rltk_wlan_get_ip(int idx){
#if (CONFIG_LWIP_LAYER == 1)
return LwIP_GetIP(&xnetif[idx]);
#else
return NULL;
#endif
}
#endif

61
component/common/drivers/wlan/realtek/src/osdep/lwip_intf.h Executable file
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#ifndef __LWIP_INTF_H__
#define __LWIP_INTF_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <wireless.h>
#include <skbuff.h>
#include "ethernetif.h"
#if 0 // moved to ethernetif.h by jimmy 12/2/2015
//----- ------------------------------------------------------------------
// Ethernet Buffer
//----- ------------------------------------------------------------------
struct eth_drv_sg {
unsigned int buf;
unsigned int len;
};
#define MAX_ETH_DRV_SG 32
#define MAX_ETH_MSG 1540
#endif
//----- ------------------------------------------------------------------
// Wlan Interface Provided
//----- ------------------------------------------------------------------
unsigned char rltk_wlan_check_isup(int idx);
void rltk_wlan_tx_inc(int idx);
void rltk_wlan_tx_dec(int idx);
struct sk_buff * rltk_wlan_get_recv_skb(int idx);
struct sk_buff * rltk_wlan_alloc_skb(unsigned int total_len);
void rltk_wlan_set_netif_info(int idx_wlan, void * dev, unsigned char * dev_addr);
void rltk_wlan_send_skb(int idx, struct sk_buff *skb); //struct sk_buff as defined above comment line
int rltk_wlan_send(int idx, struct eth_drv_sg *sg_list, int sg_len, int total_len);
void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len);
unsigned char rltk_wlan_running(unsigned char idx); // interface is up. 0: interface is down
//----- ------------------------------------------------------------------
// Network Interface provided
//----- ------------------------------------------------------------------
struct netif;
int netif_is_valid_IP(int idx,unsigned char * ip_dest);
int netif_get_idx(struct netif *pnetif);
unsigned char *netif_get_hwaddr(int idx_wlan);
void netif_rx(int idx, unsigned int len);
void netif_post_sleep_processing(void);
void netif_pre_sleep_processing(void);
#if (CONFIG_LWIP_LAYER == 1)
extern void ethernetif_recv(struct netif *netif, int total_len);
extern void lwip_PRE_SLEEP_PROCESSING(void);
extern void lwip_POST_SLEEP_PROCESSING(void);
#endif //CONFIG_LWIP_LAYER == 1
#ifdef CONFIG_WOWLAN
extern unsigned char *rltk_wlan_get_ip(int idx);
#endif
#ifdef __cplusplus
}
#endif
#endif //#ifndef __LWIP_INTF_H__

57
component/common/drivers/wlan/realtek/src/osdep/skbuff.h Executable file
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#ifndef __SKBUFF_H__
#define __SKBUFF_H__
struct sk_buff_head {
struct list_head *next, *prev;
unsigned int qlen;
};
#ifdef CONFIG_TRACE_SKB
#define TRACE_SKB_DEPTH 8
#endif
struct sk_buff {
/* These two members must be first. */
struct sk_buff *next; /* Next buffer in list */
struct sk_buff *prev; /* Previous buffer in list */
struct sk_buff_head *list; /* List we are on */
unsigned char *head; /* Head of buffer */
unsigned char *data; /* Data head pointer */
unsigned char *tail; /* Tail pointer */
unsigned char *end; /* End pointer */
void *dev; /* Device we arrived on/are leaving by */
unsigned int len; /* Length of actual data */
#ifdef CONFIG_TRACE_SKB
unsigned int liston[TRACE_SKB_DEPTH]; /* Trace the Lists we went through */
const char *funcname[TRACE_SKB_DEPTH];
unsigned int list_idx; /* Trace the List we are on */
#endif
//#ifdef CONFIG_DONT_CARE_TP
int dyalloc_flag;
//#endif
};
unsigned char *skb_put(struct sk_buff *skb, unsigned int len);
unsigned char *skb_pull(struct sk_buff *skb, unsigned int len);
void skb_reserve(struct sk_buff *skb, unsigned int len);
void skb_assign_buf(struct sk_buff *skb, unsigned char *buf, unsigned int len);
unsigned char *skb_tail_pointer(const struct sk_buff *skb);
void skb_set_tail_pointer(struct sk_buff *skb, const int offset);
unsigned char *skb_end_pointer(const struct sk_buff *skb);
void init_skb_pool(void);
void init_skb_data_pool(void);
#ifndef CONFIG_DONT_CARE_TP
struct sk_buff *dev_alloc_skb(unsigned int length, unsigned int reserve_len);
#else
struct sk_buff *dev_alloc_tx_skb(unsigned int length, unsigned int reserve_len);
struct sk_buff *dev_alloc_rx_skb(unsigned int length, unsigned int reserve_len);
#define dev_alloc_skb dev_alloc_tx_skb
#endif
void kfree_skb(struct sk_buff *skb);
#endif //__SKBUFF_H__

1209
component/common/drivers/wlan/realtek/src/osdep/wireless.h Executable file
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File diff suppressed because it is too large Load diff

66
component/common/drivers/wlan/realtek/src/osdep/wlan_intf.h Executable file
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#ifndef __WLAN_INTF_H__
#define __WLAN_INTF_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <autoconf.h>
#include <wireless.h>
#include "wifi_constants.h"
#ifndef WLAN0_IDX
#define WLAN0_IDX 0
#endif
#ifndef WLAN1_IDX
#define WLAN1_IDX 1
#endif
#ifndef WLAN_UNDEF
#define WLAN_UNDEF -1
#endif
/***********************************************************/
/*
struct sk_buff {
// These two members must be first.
struct sk_buff *next; // Next buffer in list
struct sk_buff *prev; // Previous buffer in list
struct sk_buff_head *list; // List we are on
unsigned char *head; // Head of buffer
unsigned char *data; // Data head pointer
unsigned char *tail; // Tail pointer
unsigned char *end; //End pointer
struct net_device *dev; //Device we arrived on/are leaving by
unsigned int len; // Length of actual data
};
*/
/************************************************************/
//----- ------------------------------------------------------------------
// Wlan Interface opened for upper layer
//----- ------------------------------------------------------------------
int rltk_wlan_init(int idx_wlan, rtw_mode_t mode); //return 0: success. -1:fail
void rltk_wlan_deinit(void);
void rltk_wlan_deinit_fastly(void);
int rltk_wlan_start(int idx_wlan);
void rltk_wlan_statistic(unsigned char idx);
unsigned char rltk_wlan_running(unsigned char idx); // interface is up. 0: interface is down
int rltk_wlan_control(unsigned long cmd, void *data);
int rltk_wlan_handshake_done(void);
int rltk_wlan_rf_on(void);
int rltk_wlan_rf_off(void);
int rltk_wlan_check_bus(void);
int rltk_wlan_wireless_mode(unsigned char mode);
int rltk_wlan_set_wps_phase(unsigned char is_trigger_wps);
int rtw_ps_enable(int enable);
int rltk_wlan_is_connected_to_ap(void);
#ifdef __cplusplus
}
#endif
#endif //#ifndef __WLAN_INTF_H__

9
component/common/drivers/wlan/realtek/wlan_ram_map/rom/rom_wlan_ram_map.h Executable file
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#ifndef ROM_WLAN_RAM_MAP_H
#define ROM_WLAN_RAM_MAP_H
struct _rom_wlan_ram_map {
unsigned char * (*rtw_malloc)(unsigned int sz);
void (*rtw_mfree)(unsigned char *pbuf, unsigned int sz);
};
#endif /* ROM_WLAN_RAM_MAP_H */