mirror of
https://github.com/drasko/open-ameba.git
synced 2024-11-21 21:44:19 +00:00
Update boot-loader
This commit is contained in:
pvvx
parent
67ea7a663c
commit
d8c84cd5fe
17 changed files with 2685 additions and 2397 deletions
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@ -38,9 +38,11 @@
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* ---------------------------------------------------*/
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// This signature can be used to verify the correctness of the image
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// It will be located in fixed location in application image
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/* Moved in main.c
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#include "section_config.h"
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SECTION(".custom.validate.rodata")
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const unsigned char cus_sig[32] = "Customer Signature-modelxxx";
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*/
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#endif
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#else
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@ -21,8 +21,27 @@
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//#define BOOT_RAM_DATA_SECTION __attribute__((section(".boot.data")))
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//#define BOOT_RAM_BSS_SECTION __attribute__((section(".boot.bss")))
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//-------------------------------------------------------------------------
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typedef struct _seg_header {
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uint32 size;
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uint32 ldaddr;
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} IMGSEGHEAD, *PIMGSEGHEAD;
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typedef struct _img2_header {
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IMGSEGHEAD seg;
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uint32 sign[2];
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void (*startfunc)(void);
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uint8 rtkwin[7];
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uint8 ver[13];
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uint8 name[32];
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} IMG2HEAD, *PIMG2HEAD;
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#ifndef FLASH_SECTOR_SIZE
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#define FLASH_SECTOR_SIZE 4096
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#endif
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//-------------------------------------------------------------------------
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// Function declarations
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LOCAL void RtlBootToFlash(void); // image1
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LOCAL void RtlBootToSram(void); // image1
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LOCAL void EnterImage15(void); // image1
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LOCAL void JtagOn(void); // image1
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@ -39,11 +58,12 @@ typedef void (*START_FUNC)(void);
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/* Start table: */
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START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__ = {
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RtlBootToSram + 1, // StartFun(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 )
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RtlBootToFlash + 1, // StartFun(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 )
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RtlBootToSram + 1, // PatchWAKE(), Run if ( v40000210 & 0x20000000 )
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RtlBootToSram + 1, //- PatchFun0(), Run if ( v40000210 & 0x10000000 )
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RtlBootToSram + 1, //+ PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
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EnterImage15 + 1}; // PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 )
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RtlBootToSram + 1, // PatchFun0(), Run if ( v40000210 & 0x10000000 )
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RtlBootToSram + 1,// PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
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RtlBootToFlash + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 )
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// EnterImage15 + 1}; // PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 )
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/* Set Debug Flags */
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LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() {
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@ -97,11 +117,15 @@ LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) {
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/* Enter Image 1.5 */
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LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(void) {
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SetDebugFlgs();
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DBG_8195A("\rCPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
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DBG_8195A("==!== Enter Image 1.5 ====\nImg2 Sign: %s, InfaStart @ 0x%08x\r\n",
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DBG_8195A(
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"\n===== Enter SRAM-Boot ====\nImg Sign: %s, Go @ 0x%08x\r\n",
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&__image2_validate_code__, __image2_entry_func__);
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#if CONFIG_DEBUG_LOG > 2
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DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(),
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HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
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#endif
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if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) {
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DBG_MISC_ERR("Invalid Image2 Signature!\n");
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DBG_MISC_ERR("Invalid Image Signature!\n");
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RtlConsolRam();
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}
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__image2_entry_func__();
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@ -112,14 +136,251 @@ LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToSram(void) {
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JtagOn(); /* JTAG On */
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_memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__);
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__asm__ __volatile__ ("cpsid f\n");
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HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) & ( ~BIT_SYS_SYSPLL_DIV5_3));
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HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1,
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HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) & ( ~BIT_SYS_SYSPLL_DIV5_3));
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HalCpuClkConfig(2); // 41.666666 MHz
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// HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) | BIT_SYS_SYSPLL_DIV5_3); // 50.000 MHz
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VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
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HalInitPlatformLogUartV02();
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HalInitPlatformTimerV02();
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__asm__ __volatile__ ("cpsie f\n");
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// SdrPowerOff();
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SDR_PIN_FCTRL(OFF);
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LDO25M_CTRL(OFF);
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
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HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21));
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SpicInitRtl8195AV02(1, 0); // StartupSpicBaudRate InitBaudRate 1, SpicBitMode 1 StartupSpicBitMode
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// HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & 0x1FFFFF); // Clear debug flags
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EnterImage15();
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}
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/*-------------------------------------------------------------------------------------
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Копирует данные из области align(4) (flash, registers, ...) в область align(1) (ram)
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--------------------------------------------------------------------------------------*/
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LOCAL unsigned int BOOT_RAM_TEXT_SECTION flashcpy(unsigned int faddr,
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void *dist, unsigned int size) {
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union {
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unsigned char uc[4];
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unsigned int ud;
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} tmp;
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if (faddr < SPI_FLASH_BASE)
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faddr += SPI_FLASH_BASE;
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unsigned char * pd = (unsigned char *) dist;
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unsigned int *p = (unsigned int *) ((unsigned int) faddr & (~3));
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unsigned int xlen = (unsigned int) faddr & 3;
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unsigned int len = size;
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if (xlen) {
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tmp.ud = *p++;
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while (len) {
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len--;
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*pd++ = tmp.uc[xlen++];
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if (xlen & 4)
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break;
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};
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};
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xlen = len >> 2;
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while (xlen) {
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tmp.ud = *p++;
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*pd++ = tmp.uc[0];
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*pd++ = tmp.uc[1];
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*pd++ = tmp.uc[2];
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*pd++ = tmp.uc[3];
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xlen--;
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};
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if (len & 3) {
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tmp.ud = *p;
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pd[0] = tmp.uc[0];
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if (len & 2) {
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pd[1] = tmp.uc[1];
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if (len & 1) {
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pd[2] = tmp.uc[2];
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};
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};
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};
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return size;
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}
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enum {
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SEG_ID_ERR,
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SEG_ID_SRAM,
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SEG_ID_TCM,
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SEG_ID_SDRAM,
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SEG_ID_SOC,
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SEG_ID_FLASH,
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SEG_ID_CPU,
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SEG_ID_ROM,
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SEG_ID_MAX
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} SEG_ID;
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LOCAL const char * const txt_tab_seg[] = {
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"UNK", // 0
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"SRAM", // 1
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"TCM", // 2
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"SDRAM", // 3
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"SOC", // 4
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"FLASH", // 5
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"CPU", // 6
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"ROM" // 7
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};
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LOCAL const uint32 tab_seg_def[] = { 0x10000000, 0x10070000, 0x1fff0000,
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0x20000000, 0x30000000, 0x30200000, 0x40000000, 0x40800000, 0x98000000,
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0xA0000000, 0xE0000000, 0xE0010000, 0x00000000, 0x00050000 };
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LOCAL uint32 BOOT_RAM_TEXT_SECTION get_seg_id(uint32 addr, int32 size) {
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uint32 ret = SEG_ID_ERR;
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uint32 * ptr = &tab_seg_def;
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if (size > 0) {
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do {
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ret++;
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if (addr >= ptr[0] && addr + size <= ptr[1]) {
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return ret;
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};
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ptr += 2;
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} while (ret < SEG_ID_MAX);
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};
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return 0;
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}
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LOCAL uint32 BOOT_RAM_TEXT_SECTION load_img2_head(uint32 faddr, PIMG2HEAD hdr) {
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flashcpy(faddr, hdr, sizeof(IMG2HEAD));
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uint32 ret = get_seg_id(hdr->seg.ldaddr, hdr->seg.size);
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if (hdr->sign[1] == IMG_SIGN2_RUN) {
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if (hdr->sign[0] == IMG_SIGN1_RUN) {
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ret |= 1 << 9;
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} else if (hdr->sign[0] == IMG_SIGN1_SWP) {
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ret |= 1 << 8;
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};
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}
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if (*(u32 *) (&hdr->rtkwin) == IMG2_SIGN_DW1_TXT) {
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ret |= 1 << 10;
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};
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return ret;
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}
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LOCAL uint32 BOOT_RAM_TEXT_SECTION load_segs(uint32 faddr, PIMG2HEAD hdr,
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uint8 flgload) {
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uint32 fnextaddr = faddr;
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uint8 segnum = 0;
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while (1) {
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uint32 seg_id = get_seg_id(hdr->seg.ldaddr, hdr->seg.size);
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if (flgload && (seg_id == SEG_ID_SRAM || seg_id == SEG_ID_TCM)) {
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#if CONFIG_DEBUG_LOG > 1
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DBG_8195A("Load Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n",
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segnum, faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr,
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hdr->seg.size);
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#endif
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fnextaddr += flashcpy(fnextaddr, hdr->seg.ldaddr, hdr->seg.size);
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} else if (seg_id) {
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#if CONFIG_DEBUG_LOG > 2
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DBG_8195A("Skip Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n", segnum,
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faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr, hdr->seg.size);
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#endif
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fnextaddr += hdr->seg.size;
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} else {
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break;
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}
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fnextaddr += flashcpy(fnextaddr, &hdr->seg, sizeof(IMGSEGHEAD));
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segnum++;
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}
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return fnextaddr;
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}
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/*-------------------------------------------------------------------------------------
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* 0 - default image (config data + 0), 1 - image N1, 2 - image N2, ...
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--------------------------------------------------------------------------------------*/
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LOCAL int BOOT_RAM_TEXT_SECTION loadUserImges(int imgnum) {
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IMG2HEAD hdr;
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int imagenum = 1;
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uint32 faddr = 0xb000; // start image2 in flash
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DBG_8195A("Selected Image %d.\n", imgnum);
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while (1) {
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faddr = (faddr + FLASH_SECTOR_SIZE - 1) & (~(FLASH_SECTOR_SIZE - 1));
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uint32 img_id = load_img2_head(faddr, &hdr);
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if ((img_id >> 8) > 4 || (uint8) img_id != 0) {
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faddr = load_segs(faddr + 0x10, &hdr.seg, imagenum == imgnum);
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if (imagenum == imgnum) {
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// DBG_8195A("Image%d: %s\n", imgnum, hdr.name);
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break;
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}
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imagenum++;
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} else if (imagenum) {
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DBG_8195A("No Image%d! Trying Image0...\n", imgnum);
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// пробуем загрузить image по умолчанию, по записи в секторе установок
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flashcpy(FLASH_SYSTEM_DATA_ADDR, &faddr, sizeof(faddr));
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if (faddr < 0x8000000)
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faddr += SPI_FLASH_BASE;
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if (get_seg_id(faddr, 0x100) == SEG_ID_FLASH) {
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imagenum = 0;
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imgnum = 0;
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} else {
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DBG_8195A("No Image0!\n");
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imagenum = -1;
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break;
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};
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} else {
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imagenum = -1;
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break;
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}
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};
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return imagenum;
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}
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;
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extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
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extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
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//----- IsForceLoadDefaultImg2
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LOCAL uint8 BOOT_RAM_TEXT_SECTION IsForceLoadDefaultImg2(void) {
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uint8 gpio_pin[4];
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HAL_GPIO_PIN GPIO_Pin;
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HAL_GPIO_PIN_STATE flg;
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int result = 0;
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flashcpy(FLASH_SYSTEM_DATA_ADDR + 0x08, &gpio_pin, sizeof(gpio_pin)); // config data + 8
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_pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
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for (int i = 1; i; i--) {
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uint8 x = gpio_pin[i];
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result <<= 1;
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if (x != 0xff) {
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GPIO_Pin.pin_name = HAL_GPIO_GetIPPinName_8195a(x & 0x7F);
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if (x & 0x80) {
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GPIO_Pin.pin_mode = DIN_PULL_LOW;
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flg = GPIO_PIN_HIGH;
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} else {
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GPIO_Pin.pin_mode = DIN_PULL_HIGH;
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flg = GPIO_PIN_LOW;
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}
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HAL_GPIO_Init_8195a(&GPIO_Pin);
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if (HAL_GPIO_ReadPin_8195a(&GPIO_Pin) == flg) {
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result |= 1;
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}
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HAL_GPIO_DeInit_8195a(&GPIO_Pin);
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}
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}
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_pHAL_Gpio_Adapter->IrqHandle.IrqFun = NULL;
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return result;
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}
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LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToFlash(void) {
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JtagOn(); /* JTAG On */
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SetDebugFlgs();
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DBG_8195A("===== Enter FLASH-Boot ====\n");
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if (HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (1 << BIT_SOC_FLASH_EN)) {
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SPI_FLASH_PIN_FCTRL(ON);
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/*
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if(!SpicCmpDataForCalibrationRtl8195A()) {
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DBG_8195A("ReInit Spic DIO...\n");
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SpicInitRtl8195AV02(1, SpicDualBitMode);
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}
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*/
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loadUserImges(IsForceLoadDefaultImg2() + 1);
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};
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if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) {
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DBG_8195A("Invalid Image Signature!\n");
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RtlConsolRam();
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} else
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DBG_8195A("Go @ 0x%08x\r\n", __image2_entry_func__);
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__image2_entry_func__();
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}
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@ -42,6 +42,7 @@ extern u8 __bss_start__, __bss_end__;
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IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 =
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{ InfraStart + 1 };
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/*
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//----- HalNMIHandler_Patch
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void HalNMIHandler_Patch(void) {
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DBG_8195A_HAL("%s:NMI Error!\n", __func__);
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@ -49,7 +50,6 @@ void HalNMIHandler_Patch(void) {
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HalWdgIntrHandle(); // ROM: HalWdgIntrHandle = 0x3485;
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}
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/*
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//----- VectorTableOverrideRtl8195A
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void INFRA_START_SECTION VectorTableOverrideRtl8195A(u32 StackP) {
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NewVectorTable[2] = HalNMIHandler_Patch;
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@ -100,20 +100,32 @@ __weak int main(void) {
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DiagPrintf("\r<RTL8710AF>");
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pUartLogCtl->ExecuteCmd = 0;
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}
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return 0;
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}
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extern const unsigned char cus_sig[32];
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//----- InfraStart
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void INFRA_START_SECTION InfraStart(void) {
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NewVectorTable[2] = HalNMIHandler_Patch;
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// NewVectorTable[2] = HalNMIHandler_Patch;
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// HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL0, HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL0) | BIT4);
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DBG_8195A("===== Enter Image: %s ====\n", cus_sig);
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#if CONFIG_DEBUG_LOG > 3
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DBG_8195A("\rCPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
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#endif
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#ifdef CONFIG_TIMER_MODULE
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HalTimerOpInit_Patch((VOID*) (&HalTimerOp));
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#endif
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// HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL0, HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL0) | BIT4);
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DBG_8195A("==!== Enter Image 2 ====\n");
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// ShowRamBuildInfo(); // app_start.c: VOID ShowRamBuildInfo(VOID)
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memset(&__bss_start__, 0, &__bss_end__ - &__bss_start__);
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//- Должно быть в boot !?
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extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
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memset(&gBoot_Gpio_Adapter, 0, sizeof(gBoot_Gpio_Adapter));
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_pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
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//-
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rtl_libc_init(); // ROM Lib C init
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int flash_en = HAL_PERI_ON_READ32(REG_SOC_FUNC_EN)
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& (1 << BIT_SOC_FLASH_EN);
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if (flash_en) {
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@ -129,6 +141,7 @@ void INFRA_START_SECTION InfraStart(void) {
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};
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#endif
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};
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// Load SpicInitParaAllClk table
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SpicNVMCalLoadAll();
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SpicReadIDRtl8195A();
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};
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@ -142,15 +155,12 @@ void INFRA_START_SECTION InfraStart(void) {
|
|||
*((int *) (SYSTEM_CTRL_BASE + REG_SYS_SYSPLL_CTRL1)) &= ~(1 << 17); // REG_SYS_SYSPLL_CTRL1 &= ~BIT_SYS_SYSPLL_DIV5_3
|
||||
HalCpuClkConfig(CPU_CLOCK_SEL_VALUE);
|
||||
#endif
|
||||
SDIO_Device_Off();
|
||||
HalReInitPlatformLogUartV02();
|
||||
/* HAL_LOG_UART_ADAPTER pUartAdapter;
|
||||
pUartAdapter.BaudRate = UART_BAUD_RATE_38400;
|
||||
HalLogUartSetBaudRate(&pUartAdapter); */
|
||||
SystemCoreClockUpdate();
|
||||
SYSPlatformInit();
|
||||
En32KCalibration();
|
||||
InitSoCPM();
|
||||
SDIO_Device_Off();
|
||||
VectorTableInitForOSRtl8195A(&vPortSVCHandler, &xPortPendSVHandler,
|
||||
&xPortSysTickHandler);
|
||||
if (flash_en)
|
||||
|
|
@ -169,7 +179,6 @@ void INFRA_START_SECTION InfraStart(void) {
|
|||
"bic r0, r0, #7\n"
|
||||
"mov sp, r0\n"
|
||||
);
|
||||
rtl_libc_init();
|
||||
__low_level_init();
|
||||
main();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -166,6 +166,8 @@
|
|||
#define IMG_SIGN2_RUN 0x31313738 // "8711"
|
||||
#define IMG_SIGN2_SWP IMG_SIGN2_RUN // "8711"
|
||||
#define IMG2_SIGN_TXT "RTKWin"
|
||||
#define IMG2_SIGN_DW1_TXT 0x574b5452 // "RTKW"
|
||||
#define IMG2_SIGN_SW2_TXT 0x6e69 // "in"
|
||||
|
||||
typedef struct _RAM_FUNCTION_START_TABLE_ {
|
||||
VOID (*RamStartFun) (VOID); // Run for Init console, Run if ( v40000210 & 0x4000000 )
|
||||
|
|
|
|||
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4746
build/obj/build.nmap
4746
build/obj/build.nmap
File diff suppressed because it is too large
Load diff
|
|
@ -192,8 +192,8 @@ ifdef COMPILED_BOOT_BIN
|
|||
$(OBJCOPY) --change-section-address .boot.head=0x10000ba8 -j .boot.head -j .bootloader -Obinary $(ELFFILE) $(RAM1P_IMAGE)
|
||||
else
|
||||
$(OBJCOPY) -j .rom_ram -Obinary $(ELFFILE) $(RAM_IMAGE)
|
||||
$(OBJCOPY) -j .ram.start.table -j .ram_image1.text -Obinary $(ELFFILE) $(RAM1_IMAGE)
|
||||
$(PICK) 0x$(RAM1_START_ADDR) 0x$(RAM1_END_ADDR) $(RAM1_IMAGE) $(RAM1R_IMAGE) head+reset_offset 0x0B000
|
||||
$(OBJCOPY) -j .ram.start.table -j .ram_image1.text -Obinary $(ELFFILE) $(RAM1R_IMAGE)
|
||||
$(PICK) 0x$(RAM1_START_ADDR) 0x$(RAM1_END_ADDR) $(RAM1R_IMAGE) $(RAM1P_IMAGE) head+reset_offset 0x0B000
|
||||
endif
|
||||
else
|
||||
$(error "BOOT-image size = 0")
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ r1
|
|||
trst1
|
||||
h
|
||||
r
|
||||
loadbin build/bin/ram_1.bin 0x10000bc8
|
||||
loadbin build/bin/ram_1.r.bin 0x10000bc8
|
||||
loadbin build/bin/ram_2.bin 0x10006000
|
||||
r
|
||||
w4 0x40000210,0x20111117
|
||||
w4 0x40000210,0x20111113
|
||||
g
|
||||
q
|
||||
|
|
@ -25,7 +25,7 @@
|
|||
#undef CONFIG_MP
|
||||
#undef CONFIG_CP
|
||||
#undef CONFIG_FT
|
||||
#define RTL8195A 1
|
||||
#define RTL8195A 7
|
||||
/* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz,
|
||||
6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */
|
||||
#define CONFIG_CPU_CLK 1
|
||||
|
|
|
|||
|
|
@ -35,6 +35,14 @@
|
|||
#include "main.h"
|
||||
#include "wifi_api.h"
|
||||
|
||||
/* ---------------------------------------------------
|
||||
* Customized Signature (Image Name)
|
||||
* ---------------------------------------------------*/
|
||||
#include "section_config.h"
|
||||
SECTION(".custom.validate.rodata")
|
||||
const unsigned char cus_sig[32] = "MP3 Stereo";
|
||||
|
||||
|
||||
#define DEBUG_MAIN_LEVEL 1
|
||||
|
||||
//Priorities of the reader and the decoder thread. Higher = higher prio.
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ application: build_info $(SRC_O) $(DRAM_O) $(BOOT_O)
|
|||
# @echo "==========================================================="
|
||||
@mkdir -p $(BIN_DIR) $(OBJ_DIR)
|
||||
## @cp $(patsubst sdk/%,$(SDK_PATH)%,$(BOOTS))/ram_1.r.bin $(BIN_DIR)/ram_1.r.bin
|
||||
@cp $(patsubst sdk/%,$(SDK_PATH)%,$(BOOTS))/ram_1.p.bin $(BIN_DIR)/ram_1.p.bin
|
||||
## @cp $(patsubst sdk/%,$(SDK_PATH)%,$(BOOTS))/ram_1.p.bin $(BIN_DIR)/ram_1.p.bin
|
||||
# @chmod 777 $(OBJ_DIR)/ram_1.r.bin
|
||||
## $(OBJCOPY) --rename-section .data=.loader.data,contents,alloc,load,readonly,data -I binary -O elf32-littlearm -B arm $(BIN_DIR)/ram_1.r.bin $(OBJ_DIR)/ram_1.r.o
|
||||
@echo "==========================================================="
|
||||
|
|
|
|||
|
|
@ -116,7 +116,7 @@ SRC_C += sdk/component/common/api/lwip_netconf.c
|
|||
#SRC_C += sdk/component/common/utilities/ssl_client_ext.c
|
||||
SRC_C += sdk/component/common/utilities/tcptest.c
|
||||
SRC_C += sdk/component/common/utilities/uart_ymodem.c
|
||||
SRC_C += sdk/component/common/utilities/update.c
|
||||
#SRC_C += sdk/component/common/utilities/update.c
|
||||
#SRC_C += sdk/component/common/application/uart_adapter/uart_adapter.c
|
||||
SRC_C += sdk/component/common/api/network/src/wlan_network.c
|
||||
SRC_C += sdk/component/common/api/wifi_interactive_mode.c
|
||||
|
|
|
|||
Loading…
Reference in a new issue