diff --git a/RTL00_SDKV35a/component/common/utilities/update.c b/RTL00_SDKV35a/component/common/utilities/update.c index f2fb17a..9dce4f0 100644 --- a/RTL00_SDKV35a/component/common/utilities/update.c +++ b/RTL00_SDKV35a/component/common/utilities/update.c @@ -38,9 +38,11 @@ * ---------------------------------------------------*/ // This signature can be used to verify the correctness of the image // It will be located in fixed location in application image +/* Moved in main.c #include "section_config.h" SECTION(".custom.validate.rodata") const unsigned char cus_sig[32] = "Customer Signature-modelxxx"; +*/ #endif #else diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c index de853f5..50a4488 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c @@ -21,8 +21,27 @@ //#define BOOT_RAM_DATA_SECTION __attribute__((section(".boot.data"))) //#define BOOT_RAM_BSS_SECTION __attribute__((section(".boot.bss"))) +//------------------------------------------------------------------------- +typedef struct _seg_header { + uint32 size; + uint32 ldaddr; +} IMGSEGHEAD, *PIMGSEGHEAD; + +typedef struct _img2_header { + IMGSEGHEAD seg; + uint32 sign[2]; + void (*startfunc)(void); + uint8 rtkwin[7]; + uint8 ver[13]; + uint8 name[32]; +} IMG2HEAD, *PIMG2HEAD; + +#ifndef FLASH_SECTOR_SIZE +#define FLASH_SECTOR_SIZE 4096 +#endif //------------------------------------------------------------------------- // Function declarations +LOCAL void RtlBootToFlash(void); // image1 LOCAL void RtlBootToSram(void); // image1 LOCAL void EnterImage15(void); // image1 LOCAL void JtagOn(void); // image1 @@ -39,11 +58,12 @@ typedef void (*START_FUNC)(void); /* Start table: */ START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__ = { - RtlBootToSram + 1, // StartFun(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 ) + RtlBootToFlash + 1, // StartFun(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 ) RtlBootToSram + 1, // PatchWAKE(), Run if ( v40000210 & 0x20000000 ) - RtlBootToSram + 1, //- PatchFun0(), Run if ( v40000210 & 0x10000000 ) - RtlBootToSram + 1, //+ PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 ) - EnterImage15 + 1}; // PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 ) + RtlBootToSram + 1, // PatchFun0(), Run if ( v40000210 & 0x10000000 ) + RtlBootToSram + 1,// PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 ) + RtlBootToFlash + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 ) +// EnterImage15 + 1}; // PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 ) /* Set Debug Flags */ LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() { @@ -97,11 +117,15 @@ LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) { /* Enter Image 1.5 */ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(void) { SetDebugFlgs(); - DBG_8195A("\rCPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN)); - DBG_8195A("==!== Enter Image 1.5 ====\nImg2 Sign: %s, InfaStart @ 0x%08x\r\n", + DBG_8195A( + "\n===== Enter SRAM-Boot ====\nImg Sign: %s, Go @ 0x%08x\r\n", &__image2_validate_code__, __image2_entry_func__); +#if CONFIG_DEBUG_LOG > 2 + DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), + HAL_PERI_ON_READ32(REG_SOC_FUNC_EN)); +#endif if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) { - DBG_MISC_ERR("Invalid Image2 Signature!\n"); + DBG_MISC_ERR("Invalid Image Signature!\n"); RtlConsolRam(); } __image2_entry_func__(); @@ -112,14 +136,251 @@ LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToSram(void) { JtagOn(); /* JTAG On */ _memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__); __asm__ __volatile__ ("cpsid f\n"); - HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) & ( ~BIT_SYS_SYSPLL_DIV5_3)); + HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, + HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) & ( ~BIT_SYS_SYSPLL_DIV5_3)); HalCpuClkConfig(2); // 41.666666 MHz // HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) | BIT_SYS_SYSPLL_DIV5_3); // 50.000 MHz VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC HalInitPlatformLogUartV02(); HalInitPlatformTimerV02(); __asm__ __volatile__ ("cpsie f\n"); + // SdrPowerOff(); + SDR_PIN_FCTRL(OFF); + LDO25M_CTRL(OFF); + HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, + HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); + SpicInitRtl8195AV02(1, 0); // StartupSpicBaudRate InitBaudRate 1, SpicBitMode 1 StartupSpicBitMode -// HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & 0x1FFFFF); // Clear debug flags EnterImage15(); } + +/*------------------------------------------------------------------------------------- + Копирует данные из области align(4) (flash, registers, ...) в область align(1) (ram) + --------------------------------------------------------------------------------------*/ +LOCAL unsigned int BOOT_RAM_TEXT_SECTION flashcpy(unsigned int faddr, + void *dist, unsigned int size) { + union { + unsigned char uc[4]; + unsigned int ud; + } tmp; + if (faddr < SPI_FLASH_BASE) + faddr += SPI_FLASH_BASE; + unsigned char * pd = (unsigned char *) dist; + unsigned int *p = (unsigned int *) ((unsigned int) faddr & (~3)); + unsigned int xlen = (unsigned int) faddr & 3; + unsigned int len = size; + + if (xlen) { + tmp.ud = *p++; + while (len) { + len--; + *pd++ = tmp.uc[xlen++]; + if (xlen & 4) + break; + }; + }; + xlen = len >> 2; + while (xlen) { + tmp.ud = *p++; + *pd++ = tmp.uc[0]; + *pd++ = tmp.uc[1]; + *pd++ = tmp.uc[2]; + *pd++ = tmp.uc[3]; + xlen--; + }; + if (len & 3) { + tmp.ud = *p; + pd[0] = tmp.uc[0]; + if (len & 2) { + pd[1] = tmp.uc[1]; + if (len & 1) { + pd[2] = tmp.uc[2]; + }; + }; + }; + return size; +} + +enum { + SEG_ID_ERR, + SEG_ID_SRAM, + SEG_ID_TCM, + SEG_ID_SDRAM, + SEG_ID_SOC, + SEG_ID_FLASH, + SEG_ID_CPU, + SEG_ID_ROM, + SEG_ID_MAX +} SEG_ID; + +LOCAL const char * const txt_tab_seg[] = { + "UNK", // 0 + "SRAM", // 1 + "TCM", // 2 + "SDRAM", // 3 + "SOC", // 4 + "FLASH", // 5 + "CPU", // 6 + "ROM" // 7 + }; + +LOCAL const uint32 tab_seg_def[] = { 0x10000000, 0x10070000, 0x1fff0000, + 0x20000000, 0x30000000, 0x30200000, 0x40000000, 0x40800000, 0x98000000, + 0xA0000000, 0xE0000000, 0xE0010000, 0x00000000, 0x00050000 }; + +LOCAL uint32 BOOT_RAM_TEXT_SECTION get_seg_id(uint32 addr, int32 size) { + uint32 ret = SEG_ID_ERR; + uint32 * ptr = &tab_seg_def; + if (size > 0) { + do { + ret++; + if (addr >= ptr[0] && addr + size <= ptr[1]) { + return ret; + }; + ptr += 2; + } while (ret < SEG_ID_MAX); + }; + return 0; +} + +LOCAL uint32 BOOT_RAM_TEXT_SECTION load_img2_head(uint32 faddr, PIMG2HEAD hdr) { + flashcpy(faddr, hdr, sizeof(IMG2HEAD)); + uint32 ret = get_seg_id(hdr->seg.ldaddr, hdr->seg.size); + if (hdr->sign[1] == IMG_SIGN2_RUN) { + if (hdr->sign[0] == IMG_SIGN1_RUN) { + ret |= 1 << 9; + } else if (hdr->sign[0] == IMG_SIGN1_SWP) { + ret |= 1 << 8; + }; + } + if (*(u32 *) (&hdr->rtkwin) == IMG2_SIGN_DW1_TXT) { + ret |= 1 << 10; + }; + return ret; +} + +LOCAL uint32 BOOT_RAM_TEXT_SECTION load_segs(uint32 faddr, PIMG2HEAD hdr, + uint8 flgload) { + uint32 fnextaddr = faddr; + uint8 segnum = 0; + while (1) { + uint32 seg_id = get_seg_id(hdr->seg.ldaddr, hdr->seg.size); + if (flgload && (seg_id == SEG_ID_SRAM || seg_id == SEG_ID_TCM)) { +#if CONFIG_DEBUG_LOG > 1 + DBG_8195A("Load Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n", + segnum, faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr, + hdr->seg.size); +#endif + fnextaddr += flashcpy(fnextaddr, hdr->seg.ldaddr, hdr->seg.size); + } else if (seg_id) { +#if CONFIG_DEBUG_LOG > 2 + DBG_8195A("Skip Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n", segnum, + faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr, hdr->seg.size); +#endif + fnextaddr += hdr->seg.size; + } else { + break; + } + fnextaddr += flashcpy(fnextaddr, &hdr->seg, sizeof(IMGSEGHEAD)); + segnum++; + } + return fnextaddr; +} + +/*------------------------------------------------------------------------------------- + * 0 - default image (config data + 0), 1 - image N1, 2 - image N2, ... + --------------------------------------------------------------------------------------*/ +LOCAL int BOOT_RAM_TEXT_SECTION loadUserImges(int imgnum) { + IMG2HEAD hdr; + int imagenum = 1; + uint32 faddr = 0xb000; // start image2 in flash + DBG_8195A("Selected Image %d.\n", imgnum); + + while (1) { + faddr = (faddr + FLASH_SECTOR_SIZE - 1) & (~(FLASH_SECTOR_SIZE - 1)); + uint32 img_id = load_img2_head(faddr, &hdr); + if ((img_id >> 8) > 4 || (uint8) img_id != 0) { + faddr = load_segs(faddr + 0x10, &hdr.seg, imagenum == imgnum); + if (imagenum == imgnum) { +// DBG_8195A("Image%d: %s\n", imgnum, hdr.name); + break; + } + imagenum++; + } else if (imagenum) { + DBG_8195A("No Image%d! Trying Image0...\n", imgnum); + // пробуем загрузить image по умолчанию, по записи в секторе установок + flashcpy(FLASH_SYSTEM_DATA_ADDR, &faddr, sizeof(faddr)); + if (faddr < 0x8000000) + faddr += SPI_FLASH_BASE; + if (get_seg_id(faddr, 0x100) == SEG_ID_FLASH) { + imagenum = 0; + imgnum = 0; + } else { + DBG_8195A("No Image0!\n"); + imagenum = -1; + break; + }; + } else { + imagenum = -1; + break; + } + }; + return imagenum; +} +; + +extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter; +extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter; +//----- IsForceLoadDefaultImg2 +LOCAL uint8 BOOT_RAM_TEXT_SECTION IsForceLoadDefaultImg2(void) { + uint8 gpio_pin[4]; + HAL_GPIO_PIN GPIO_Pin; + HAL_GPIO_PIN_STATE flg; + int result = 0; + flashcpy(FLASH_SYSTEM_DATA_ADDR + 0x08, &gpio_pin, sizeof(gpio_pin)); // config data + 8 + _pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter; + for (int i = 1; i; i--) { + uint8 x = gpio_pin[i]; + result <<= 1; + if (x != 0xff) { + GPIO_Pin.pin_name = HAL_GPIO_GetIPPinName_8195a(x & 0x7F); + if (x & 0x80) { + GPIO_Pin.pin_mode = DIN_PULL_LOW; + flg = GPIO_PIN_HIGH; + } else { + GPIO_Pin.pin_mode = DIN_PULL_HIGH; + flg = GPIO_PIN_LOW; + } + HAL_GPIO_Init_8195a(&GPIO_Pin); + if (HAL_GPIO_ReadPin_8195a(&GPIO_Pin) == flg) { + result |= 1; + } + HAL_GPIO_DeInit_8195a(&GPIO_Pin); + } + } + _pHAL_Gpio_Adapter->IrqHandle.IrqFun = NULL; + return result; +} + +LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToFlash(void) { + + JtagOn(); /* JTAG On */ + SetDebugFlgs(); + DBG_8195A("===== Enter FLASH-Boot ====\n"); + if (HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (1 << BIT_SOC_FLASH_EN)) { + SPI_FLASH_PIN_FCTRL(ON); + /* + if(!SpicCmpDataForCalibrationRtl8195A()) { + DBG_8195A("ReInit Spic DIO...\n"); + SpicInitRtl8195AV02(1, SpicDualBitMode); + } + */ + loadUserImges(IsForceLoadDefaultImg2() + 1); + }; + if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) { + DBG_8195A("Invalid Image Signature!\n"); + RtlConsolRam(); + } else + DBG_8195A("Go @ 0x%08x\r\n", __image2_entry_func__); + __image2_entry_func__(); +} diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c index 97c349b..e8a5d4c 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c @@ -42,6 +42,7 @@ extern u8 __bss_start__, __bss_end__; IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 = { InfraStart + 1 }; +/* //----- HalNMIHandler_Patch void HalNMIHandler_Patch(void) { DBG_8195A_HAL("%s:NMI Error!\n", __func__); @@ -49,7 +50,6 @@ void HalNMIHandler_Patch(void) { HalWdgIntrHandle(); // ROM: HalWdgIntrHandle = 0x3485; } -/* //----- VectorTableOverrideRtl8195A void INFRA_START_SECTION VectorTableOverrideRtl8195A(u32 StackP) { NewVectorTable[2] = HalNMIHandler_Patch; @@ -100,20 +100,32 @@ __weak int main(void) { DiagPrintf("\r"); pUartLogCtl->ExecuteCmd = 0; } - return 0; } +extern const unsigned char cus_sig[32]; //----- InfraStart void INFRA_START_SECTION InfraStart(void) { - NewVectorTable[2] = HalNMIHandler_Patch; +// NewVectorTable[2] = HalNMIHandler_Patch; +// HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL0, HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL0) | BIT4); + DBG_8195A("===== Enter Image: %s ====\n", cus_sig); +#if CONFIG_DEBUG_LOG > 3 + DBG_8195A("\rCPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN)); +#endif #ifdef CONFIG_TIMER_MODULE HalTimerOpInit_Patch((VOID*) (&HalTimerOp)); #endif -// HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL0, HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL0) | BIT4); - DBG_8195A("==!== Enter Image 2 ====\n"); // ShowRamBuildInfo(); // app_start.c: VOID ShowRamBuildInfo(VOID) memset(&__bss_start__, 0, &__bss_end__ - &__bss_start__); + +//- Должно быть в boot !? +extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter; + memset(&gBoot_Gpio_Adapter, 0, sizeof(gBoot_Gpio_Adapter)); + _pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter; +//- + + rtl_libc_init(); // ROM Lib C init + int flash_en = HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (1 << BIT_SOC_FLASH_EN); if (flash_en) { @@ -129,6 +141,7 @@ void INFRA_START_SECTION InfraStart(void) { }; #endif }; + // Load SpicInitParaAllClk table SpicNVMCalLoadAll(); SpicReadIDRtl8195A(); }; @@ -142,20 +155,17 @@ void INFRA_START_SECTION InfraStart(void) { *((int *) (SYSTEM_CTRL_BASE + REG_SYS_SYSPLL_CTRL1)) &= ~(1 << 17); // REG_SYS_SYSPLL_CTRL1 &= ~BIT_SYS_SYSPLL_DIV5_3 HalCpuClkConfig(CPU_CLOCK_SEL_VALUE); #endif + SDIO_Device_Off(); HalReInitPlatformLogUartV02(); -/* HAL_LOG_UART_ADAPTER pUartAdapter; - pUartAdapter.BaudRate = UART_BAUD_RATE_38400; - HalLogUartSetBaudRate(&pUartAdapter); */ SystemCoreClockUpdate(); SYSPlatformInit(); En32KCalibration(); InitSoCPM(); - SDIO_Device_Off(); VectorTableInitForOSRtl8195A(&vPortSVCHandler, &xPortPendSVHandler, &xPortSysTickHandler); if (flash_en) SpicFlashInitRtl8195A(SpicDualBitMode); // DIO - SPI_FLASH_PIN_FCTRL(OFF); + SPI_FLASH_PIN_FCTRL(OFF); #ifdef CONFIG_SDR_EN // clear SDRAM bss extern u8 __sdram_bss_start__[]; @@ -169,7 +179,6 @@ void INFRA_START_SECTION InfraStart(void) { "bic r0, r0, #7\n" "mov sp, r0\n" ); - rtl_libc_init(); __low_level_init(); main(); } diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h index a7f3d27..91c6dc3 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h @@ -166,6 +166,8 @@ #define IMG_SIGN2_RUN 0x31313738 // "8711" #define IMG_SIGN2_SWP IMG_SIGN2_RUN // "8711" #define IMG2_SIGN_TXT "RTKWin" +#define IMG2_SIGN_DW1_TXT 0x574b5452 // "RTKW" +#define IMG2_SIGN_SW2_TXT 0x6e69 // "in" typedef struct _RAM_FUNCTION_START_TABLE_ { VOID (*RamStartFun) (VOID); // Run for Init console, Run if ( v40000210 & 0x4000000 ) diff --git a/build/bin/ota.bin b/build/bin/ota.bin index 0b16bbb..88d40fa 100644 Binary files a/build/bin/ota.bin and b/build/bin/ota.bin differ diff --git a/build/bin/ram_1.p.bin b/build/bin/ram_1.p.bin index b681894..13fca69 100644 Binary files a/build/bin/ram_1.p.bin and b/build/bin/ram_1.p.bin differ diff --git a/build/bin/ram_2.bin b/build/bin/ram_2.bin index 8ae43ee..a6e2a20 100644 Binary files a/build/bin/ram_2.bin and b/build/bin/ram_2.bin differ diff --git a/build/bin/ram_2.ns.bin b/build/bin/ram_2.ns.bin index 3808eec..6c7fe55 100644 Binary files a/build/bin/ram_2.ns.bin and b/build/bin/ram_2.ns.bin differ diff --git a/build/bin/ram_2.p.bin b/build/bin/ram_2.p.bin index 77a4f8a..c3d052c 100644 Binary files a/build/bin/ram_2.p.bin and b/build/bin/ram_2.p.bin differ diff --git a/build/bin/ram_all.bin b/build/bin/ram_all.bin index f309892..bdba22b 100644 Binary files a/build/bin/ram_all.bin and b/build/bin/ram_all.bin differ diff --git a/build/obj/build.nmap b/build/obj/build.nmap index 0235345..6845bfe 100644 --- a/build/obj/build.nmap +++ b/build/obj/build.nmap @@ -12,6 +12,7 @@ U __aeabi_i2f U __aeabi_ui2f U __ctype_ptr__ + U cmd_update U floor U free U localtime @@ -798,13 +799,20 @@ 100020c0 T gBoot_Gpio_Adapter 100020c0 t __ram_image_end__ 100021ec T SpicInitParaAllClk -1000230c t EnterImage15 -100023b8 t RtlBootToSram +1000227c t txt_tab_seg +1000229c t tab_seg_def +100023ea t flashcpy 10002400 B __rom_heap_start__ 10002400 B end -10002444 T __image1_bss_end__ -10002444 T __image1_bss_start__ -10002444 T __ram_image1_text_end__ +10002488 t get_seg_id +100024bc t JtagOn +100024e0 t RtlConsolRam +10002500 t RtlBootToFlash +1000276c t RtlBootToSram +10002864 T SEG_ID +10002864 T __image1_bss_start__ +10002868 T __image1_bss_end__ +10002868 T __ram_image1_text_end__ 10003000 B __ram_heap1_start__ 10003000 B __rom_heap_end__ 10006000 D .image2.start.table1$$Base @@ -818,2374 +826,2372 @@ 10006038 T SYSPlatformInit 10006058 T SDIO_Device_Off 1000607c T InfraStart -10006188 T UartLogIrqHandleRam -10006250 T RtlConsolTaskRam -10006318 T console_init -100063e4 T SpicRxCmdRefinedRtl8195A -100064ec T SpicInitRefinedRtl8195A -100065a0 T SpicReadIDRtl8195A -100066a4 T SpicConfigAutoModeRtl8195A -10006714 T SpicUserReadRtl8195A -10006888 T SpicUserReadFourByteRtl8195A -100069a4 T SpicGetExtendAddrRtl8195A -100069fc T SpicGetConfigRegRtl8195A -10006a54 T SpicGetFlashStatusRefinedRtl8195A -10006aac T SpicWaitWipDoneRefinedRtl8195A -10006ae8 T SpicTxCmdWithDataRtl8195A -10006bbc T SpicGetFlashFlagRtl8195A -10006c48 T SpicWaitOperationDoneRtl8195A -10006c84 T SpicDeepPowerDownFlashRtl8195A -10006d10 T SpicUserProgramRtl8195A -10006f40 T SpicWaitWipRtl8195A -10006f54 T SpicTxFlashInstRtl8195A -10006fe8 T SpicEraseFlashRefinedRtl8195A -10006ff2 T SpicDieEraseFlashRtl8195A -10007014 T SpicBlockEraseFlashRtl8195A -10007036 T SpicSectorEraseFlashRtl8195A -10007058 T SpicSetExtendAddrRtl8195A -10007072 T SpicSetFlashStatusRefinedRtl8195A -100070a4 T SpicWriteProtectFlashRtl8195A -100070cc T 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rtw_free_hwxmits -1002936c T _rtw_free_xmit_priv -10029438 T rtw_init_hwxmits -10029450 T _rtw_init_xmit_priv -10029608 T rtw_get_ff_hwaddr -1002961c T xmitframe_enqueue_for_sleeping_sta -100297dc t dequeue_xmitframes_to_sleeping_queue -10029832 T stop_sta_xmit -1002991a T wakeup_sta_to_xmit -10029b30 T xmit_delivery_enabled_frames -10029c4c T rtw_xmit_tasklet -10029ca4 T rtw_xmit_mgnt -10029ca8 T rtw_xmit -10029fd2 T rtw_sctx_done_err -10029fde T rtw_alloc_xmitbuf -1002a038 T rtw_free_xmitbuf -1002a0aa T rtw_alloc_xmitbuf_ext -1002a130 T rtw_sctx_done -1002a136 t rtl8195a_free_rx_ring -1002a144 t bus_write32 -1002a1a0 t bus_write16 -1002a1fc t bus_write8 -1002a258 t bus_read32 -1002a2b2 t bus_read16 -1002a30e t bus_read8 -1002a36a t rtl8195a_free_tx_ring -1002a3f8 T rtl8195a_init_desc_ring -1002a538 T rtl8195a_free_desc_ring -1002a554 T rtl8195a_reset_desc_ring -1002a5ea T InitLxDmaRtl8195a -1002a74c T rtl8195a_check_txdesc_closed -1002a7c4 t rtl8195a_tx_isr -1002a8a8 T InterruptRecognized8195a -1002a938 T InitInterrupt8195a -1002a958 T EnableDMA8195a -1002a980 T EnableInterrupt8195a -1002a9c0 T DisableDMA8195a -1002a9cc T DisableInterrupt8195a -1002a9e4 T UpdateInterruptMask8195a -1002aa46 T CheckRxTgRtl8195a -1002aa80 T rtl8192ee_check_rxdesc_remain -1002aab0 T rtl8195a_recv_tasklet -1002adc4 T rtl8195a_tx_int_handler -1002adf0 T InterruptHandle8195a -1002b064 T rtl8195a_xmit_tasklet -1002b08c T lxbus_set_intf_ops -1002b0cc t GetTxBufDesc -1002b116 t UpdateFirstTxbdtoXmitBuf.isra.3 -1002b148 t check_nic_enough_desc.isra.4 -1002b198 T rtl8195ab_init_xmit_priv -1002b1a6 T rtl8195ab_free_xmit_priv -1002b1ae T GetDmaTxbdIdx -1002b1ca T rtl8195a_enqueue_xmitbuf -1002b1ee T rtl8195a_dequeue_xmitbuf -1002b212 T SetTxbdForLxDMARtl8195ab -1002b292 T UpdateTxbdHostIndex -1002b2d0 T rtw_dump_xframe -1002b4a2 T check_tx_desc_resource -1002b4dc T rtw_dequeue_xframe -1002b570 T rtw_xmitframe_coalesce -1002b824 T rtl8195ab_xmitframe_resume -1002b91a T rtl8195ab_mgnt_xmit -1002b956 T rtl8195ab_hal_xmit -1002ba64 t Hal_GetEfuseDefinition -1002ba94 t ResumeTxBeacon -1002bad8 T UpdateHalRAMask8195A -1002bc70 T HalLittleWifiMCUThreadRtl8195a -1002bcc4 T HalCheckInReqStateThreadRtl8195a -1002bd10 T HalTDMAChangeStateThreadRtl8195a -1002bd5c t rtl8195a_read_chip_version -1002bdd0 t Hal_EfuseWordEnableDataWrite -1002c014 t Hal_EfusePowerSwitch -1002c028 t rtl8195a_free_hal_data -1002c042 t StopTxBeacon -1002c08c T SetHalODMVar8195A -1002c144 T rtl8195a_start_thread -1002c1ac T rtl8195a_stop_thread -1002c1d0 t Hal_ReadEFuse -1002c340 T GetHalODMVar8195A -1002c354 t rtw_flash_map_update.part.12 -1002c3f4 t rtw_flash_map_erase -1002c438 t Hal_EfusePgPacketWrite -1002c6b4 t Hal_EfuseGetCurrentSize -1002c794 t rtw_flash_map_write -1002c962 T rtl8195a_InitBeaconParameters -1002c9d2 T _InitBurstPktLen_8195AB -1002c9dc T rtl8195a_set_hal_ops -1002cabc T rtl8195a_init_default_value -1002cabe T rtl8195a_InitLLTTable -1002cb08 T Hal_GetChnlGroup8195A -1002cb44 T rtw_config_map_read -1002cc30 T rtw_config_map_write -1002ccdc T Hal_InitPGData -1002cd3a T Hal_EfuseParseIDCode -1002cd52 T Hal_ReadPowerValueFromPROM_8195A -1002cdf0 T Hal_EfuseParseTxPowerInfo_8195A -1002ce88 T Hal_EfuseParseEEPROMVer_8195A -1002ce9e T Hal_EfuseParsePackageType_8195A -1002cf08 T Hal_EfuseParseChnlPlan_8195A -1002cf38 T Hal_EfuseParseCustomerID_8195A -1002cf4e T Hal_EfuseParseXtal_8195A -1002cf66 T Hal_EfuseParseThermalMeter_8195A -1002cf8e T Hal_ReadRFGainOffset -1002cfde T BWMapping_8195A -1002cffe T SCMapping_8195A -1002d026 T rtl8195a_update_txdesc -1002d2f6 T rtl8195a_fill_fake_txdesc -1002d3b4 T SetHwReg8195A -1002e074 T GetHwReg8195A -1002e108 T SetHalDefVar8195A -1002e1e8 T GetHalDefVar8195A -1002e20c T PHY_QueryBBReg_8195A_Safe -1002e238 T PHY_SetBBReg_8195A_Safe -1002e264 t phy_RFSerialRead_8195A -1002e318 T PHY_QueryRFReg_8195A -1002e330 T PHY_SetRFReg_8195A -1002e388 T PHY_MACConfig8195A -1002e3a2 T PHY_BBConfig8195A -1002e4b2 T PHY_RFConfig8195A -1002e4b6 T PHY_SetTxPowerIndex_8195A -1002e5c0 T phy_TxPwrAdjInPercentage -1002e600 T PHY_GetTxPowerIndex_8195A -1002e6f0 T PHY_SetTxPowerLevel8195A -1002e6f6 T phy_SpurCalibration_8195A -1002e9ae T phy_SetRegBW_8195A -1002e9ec T phy_PostSetBwMode8195A -1002eb48 T phy_SwChnl8195A -1002ebf0 T phy_SwChnlAndSetBwMode8195A -1002ec40 T PHY_HandleSwChnlAndSetBW8195A -1002ecf0 T PHY_SetBWMode8195A -1002ed12 T PHY_SwChnl8195A -1002ed2c T PHY_SetSwChnlBWMode8195A -1002ed4a t HalTimerEnable -1002ed5c T InitTDMATimer -1002ed84 T ChangeStateByTDMA -1002ed94 T GetMinRateInRRSR -1002edc8 T CheckInReqState -1002edd8 T InitCheckStateTimer -1002ee08 T InitGTimer1ms -1002ee54 T DeInitGTimer1ms -1002ee9c T ChangeTransmiteRate -1002eed8 T PowerBitSetting -1002ef54 T ChkandChangePS -1002efb8 T IssueRsvdPagePacketSetting -1002f02c T IssuePSPoll -1002f058 T WaitTxStateMachineOk -1002f0ac T IssueNullData -1002f13c T PsCloseRF -1002f170 T PsOpenRF -1002f1a0 T ChkTxQueueIsEmpty -1002f1b8 T InitPS -1002f228 T ConfigListenBeaconPeriod -1002f24c T PS_S2_Condition_Match -1002f280 T PS_S4_Condition_Match -1002f2fc T PS_32K_Condition_Match -1002f338 T PS_S2ToS3ToS0State -1002f3a0 T PS_S2ToS0State -1002f3bc T PS_S3ToS2orS0State -1002f3ec T PS_S0ToS1ToS2State -1002f448 T PS_S1ToS0orS2State -1002f478 T PS_S2ToS4State -1002f4c4 T PS_S0ToS6State -1002f4e4 T PS_S6ToS0State -1002f4fc T CheckTSFIsStable -1002f54c T WaitHWStateReady -1002f55c T SysClkDown -1002f5cc T SysClkUp -1002f618 T ResetPSParm -1002f68c T PS_S4ToS2State -1002f6b0 T SleepTo32K -1002f710 T Change_PS_State -1002f8bc T Legacy_PS_Setting -1002f930 T PSModeSetting -1002f9d4 T ChangePSStateByRPWM -1002fa18 T ChangeTDMAState -1002fb38 T TDMAChangeStateTask -1002fb62 T EnterPS -1002fb84 T SetSmartPSTimer -1002fbc0 T GTimer7Handle -1002fc1c T SmartPS2InitTimerAndToGetRxPkt -1002fc58 T PS_OnBeacon -1002fd08 T PSBcnEarlyProcess -1002fdc4 T PSMtiBcnEarlyProcess -1002fe70 T PSRxBcnProcess -1002ffc0 T TxPktInPSOn -1002fffe T PsBcnToProcess -100300b8 T GTimer6Handle -10030104 T RPWMProcess -10030140 T PSSetMode -100301b8 T SpeRPT -100302d8 T ISR_BcnEarly -10030344 T ISR_MtiBcnEarly -10030378 T ISR_RxBcn -10030394 T ISR_RxBCMD1 -100303c4 T ISR_RxBCMD0 -10030418 T ISR_RxUCMD1 -10030456 T ISR_RxUCMD0 -10030492 T ISR_TxPktIn -100304a4 T ISR_TXCCX -100304a8 T H2CHDL_SetPwrMode -100305d0 T CheckInReqStateTask -10030616 T HalGetNullTxRpt -10030634 T ISR_TBTT -100306ac T H2CHDL_BcnIgnoreEDCCA -100306bc T PMUInitial -1003070c T PMUTask -10030818 T PHY_RF6052SetBandwidth8195A -1003085c T PHY_RF6052_Config8195A -10030914 t process_rssi -1003094a T rtl8195a_query_rx_desc_status -100309fa T rtl8195a_query_rx_phy_status -10030b52 T hal_com_get_channel_plan -10030b86 T HAL_IsLegalChannel -10030ba4 T MRateToHwRate -10030bb8 T HwRateToMRate -10030bcc T HalSetBrateCfg -10030c78 T Hal_MappingOutPipe -10030c94 T hal_init_macaddr -10030cc0 T hw_var_port_switch -10030f48 T SetHwReg -10030f52 T GetHwReg -10030f54 T switch_power_saving_mode -10030f98 T rtw_bb_rf_gain_offset -10030fe0 T PHY_GetRateValuesOfTxPowerByRate -10031178 T PHY_StoreTxPowerByRateNew -10031214 T PHY_InitTxPowerByRate -1003122c T PHY_StoreTxPowerByRate -10031244 T PHY_GetTxPowerIndexBase -100312e4 T PHY_GetTxPowerTrackingOffset -10031310 T PHY_GetRateIndexOfTxPowerByRate -10031324 T PHY_GetTxPowerByRate -10031384 T phy_StoreTxPowerByRateBase -100313d0 T PHY_SetTxPowerByRate -1003140c T phy_ConvertTxPowerByRateInDbmToRelativeValues -1003150c T PHY_TxPowerByRateConfiguration -1003151e T PHY_SetTxPowerIndexByRateArray -1003155c T PHY_SetTxPowerIndexByRateSection -100315c0 T PHY_SetTxPowerLevelByPath -100315f6 T phy_GetWorldWideLimit -10031622 T PHY_GetTxPowerLimit -1003174c T PHY_ConvertTxPowerLimitToPowerIndex -1003189c T PHY_InitTxPowerLimit -100318e4 T PHY_SetTxPowerLimit -10031960 T PHY_GetTxPowerIndex -10031970 T rtw_hal_chip_configure -10031986 T rtw_hal_read_chip_info -1003199c T rtw_hal_read_chip_version -100319b2 T rtw_hal_def_value_init -100319c8 T rtw_hal_free_data -100319de T rtw_hal_dm_init -100319f4 T rtw_hal_dm_deinit -10031a0a T rtw_hal_init -10031a34 T rtw_hal_deinit -10031a4e T rtw_hal_set_hwreg -10031a5c T rtw_hal_get_hwreg -10031a6a T rtw_hal_set_def_var -10031a7c T rtw_hal_get_def_var -10031a8e T rtw_hal_set_odm_var -10031a9c T rtw_hal_get_odm_var -10031aaa T rtw_hal_enable_interrupt -10031acc T rtw_hal_disable_interrupt -10031aee T rtw_hal_inirp_init -10031b00 T rtw_hal_inirp_deinit -10031b12 T rtw_hal_irp_reset -10031b20 T rtw_hal_xmit -10031b32 T rtw_hal_mgnt_xmit -10031b44 T rtw_hal_init_xmit_priv -10031b56 T rtw_hal_free_xmit_priv -10031b64 T rtw_hal_update_ra_mask -10031b92 T rtw_hal_add_ra_tid -10031ba0 T rtw_hal_clone_data -10031bae T rtw_hal_start_thread -10031bbc T rtw_hal_stop_thread -10031bca T rtw_hal_read_bbreg -10031bfe T rtw_hal_write_bbreg -10031c2a T rtw_hal_read_rfreg -10031c3c T rtw_hal_write_rfreg -10031c50 T rtw_hal_interrupt_handler -10031c62 T rtw_hal_set_bwmode -10031c70 T rtw_hal_set_chan -10031c7e T rtw_hal_set_chnl_bw -10031c94 T rtw_hal_dm_watchdog -10031caa T rtw_hal_macid_sleep -10031cca T rtw_hal_macid_wakeup -10031cea T decide_chip_type_by_device_id -10031cf0 t rtw_net_get_stats -10031d40 t netdev_if2_close -10031d60 t netdev_close -10031dbc t rtw_if1_deinit -10031e56 T rtw_os_indicate_connect -10031e5a T rtw_os_indicate_scan_done -10031e5e T rtw_reset_securitypriv -10031f52 T rtw_os_indicate_disconnect -10031f9c T rtw_init_netdev -100320ec T rtw_drv_if2_init -100322f4 T rtw_drv_if2_stop -1003234a T rtw_drv_if2_free -10032398 T _netdev_open -100324b4 T _netdev_if2_open -10032570 T netdev_if2_open -10032598 T netdev_open -100325c0 T rtw_drv_probe -10032740 T rtw_dev_remove -10032784 T rtw_drv_entry -100327b0 T rtw_drv_halt -100327e0 t rtw_wx_set_autoreconnect -1003280e t rtw_wx_get_autoreconnect -1003281c t rtw_forwarding_set -1003283e t rtw_set_ch_deauth -10032860 t get_priv_size -10032874 t rtw_wx_del_custome_ie -100328c0 t rtw_wx_set_pscan_freq -10032942 t rtw_wx_update_custome_ie -100329b4 t rtw_set_tos_value -100329d4 t rtw_get_tx_power -10032b18 t rtw_wx_set_custome_ie -10032bc4 t rtw_pm_get -10032c08 t rtw_pm_set -10032cbc t rtw_wx_read32 -10032d68 t rtw_wx_write32 -10032dcc t rtw_wx_set_freq.isra.10 -10032e74 T rtw_ex_set -10032f34 T wireless_send_event -10032f3e T indicate_wx_custom_event -10032f9a T indicate_wx_scan_result_present -10032fc2 T indicate_wx_scan_complete_event -10032fec T rtw_indicate_sta_assoc -1003303c T rtw_indicate_sta_disassoc -10033094 T rtw_indicate_wx_assoc_event -100330c6 T rtw_indicate_wx_disassoc_event -100330f6 T rtw_set_wpa_ie -1003320c T strtopsk -10033278 T rtw_wx_get_passphrase -100332c4 T rtw_wx_set_ap_essid -100333b4 T mac_reg_dump -10033460 T bb_reg_dump -100334bc T rf_reg_dump -10033534 t rtw_dbg_port -10033b9c T rtw_set_sta_num -10033bb8 T rtw_ex_get_drv_ability -10033c78 T rtw_ex_get -10033f10 T rtw_ioctl -10034e9c T rtw_os_recv_resource_init -10034ea0 T rtw_os_recv_resource_alloc -10034eaa T rtw_os_recv_resource_free -10034eac T rtw_tkip_countermeasure -10034f4c T rtw_handle_tkip_mic_err -10034ff4 T rtw_recv_indicatepkt -10035244 T skb_fail_inc -10035260 T skb_fail_get_and_rst -1003527c T init_skb_pool -100352d4 T init_skb_data_pool -1003532c T alloc_skb -1003542c T kfree_skb -10035494 T kfree_skb_chk_key -10035498 T skb_put -100354cc T skb_reserve -100354da T dev_alloc_skb -100354f6 T skb_end_pointer -100354fa T skb_set_tail_pointer -10035502 T skb_pull -1003551a T skb_copy -10035542 T rtw_remainder_len -1003554e T _rtw_open_pktfile -10035560 T _rtw_pktfile_read -1003558e T rtw_set_tx_chksum_offload -10035590 T rtw_os_xmit_resource_alloc -1003559a T rtw_os_xmit_resource_free -1003559c T rtw_os_pkt_complete -100355a4 T rtw_os_xmit_complete -100355b6 T rtw_os_xmit_schedule -100355f2 T rtw_xmit_entry -1003563e T rtw_alloc_etherdev_with_old_priv -10035654 T rtw_alloc_etherdev -10035680 T rtw_free_netdev -100356a0 T timer_wrapper -100356f4 T alloc_etherdev -10035750 T free_netdev -1003576a T dev_alloc_name -10035774 T init_timer_wrapper -10035794 T deinit_timer_wrapper -100357e0 T init_timer -10035898 T mod_timer -10035978 T cancel_timer_ex -100359c0 T del_timer_sync -10035a24 T rtw_init_timer -10035a2c T rtw_set_timer -10035a30 T rtw_cancel_timer -10035a3a T rtw_del_timer -10035a40 T rltk_get_idx_bydev -10035a50 T rltk_wlan_init -10035ad8 T rltk_wlan_deinit -10035b9c T rltk_wlan_start -10035bd0 T rltk_wlan_check_isup -10035be0 T rltk_wlan_tx_inc -10035bf4 T rltk_wlan_tx_dec -10035c08 T rltk_wlan_get_recv_skb -10035c18 T rltk_wlan_alloc_skb -10035c58 T rltk_wlan_send_skb -10035c8c T rltk_netif_rx -10035d38 T rltk_set_sta_num -10035d3c T rltk_set_tx_power_percentage -10035d70 T rltk_wlan_control -10035e04 T rltk_wlan_running -10035e1c T rltk_wlan_handshake_done -10035e50 T rltk_wlan_is_connected_to_ap -10035e94 T Efuse_PowerSwitch -10035ea0 T Efuse_GetCurrentSize -10035eac T Efuse_CalculateWordCnts -10035ed0 T EFUSE_GetEfuseDefinition -10035ee4 T efuse_OneByteRead -10035f18 T efuse_OneByteWrite -10035f4c T Efuse_PgPacketWrite -10035f60 T efuse_WordEnableDataRead -10035f92 T Efuse_WordEnableDataWrite -10035fa6 T efuse_GetCurrentSize -10035fce T rtw_efuse_map_read -10036030 T rtw_efuse_map_write -100361b0 T rtw_macaddr_cfg -10036274 T rtw_get_cipher_info -100362ee T rtw_get_bcn_info -100363be T rtw_init_default_value -1003642c T rtw_cancel_all_timer -10036496 T rtw_free_drv_sw -1003650c T rtw_reset_drv_sw -10036568 T rtw_init_drv_sw -100365f0 T rtw_start_drv_threads -100366ac T rtw_stop_drv_threads -100366e0 T rtw_read8 -100366ee T rtw_read16 -100366fc T rtw_read32 -1003670a T rtw_write8 -10036718 T rtw_write16 -10036726 T rtw_write32 -10036734 T rtw_do_join -100367d8 T rtw_set_802_11_bssid -1003695c T rtw_set_802_11_ssid -10036a64 T rtw_set_802_11_infrastructure_mode -10036b06 T rtw_set_802_11_bssid_list_scan -10036b56 T rtw_set_802_11_authentication_mode -10036b78 T rtw_set_802_11_add_wep -10036bd8 T ODM_InitRAInfo -10036c78 T InitialRateUpdate -10036d78 T RateUp_search_RateMask -10036daa T RateDown_search_RateMask -10036dfc T StartRateByRSSI -10036e26 T RateUpRAM8195A -10036eba T RateDownTrying -10036ef8 T TryDone -10036f90 T RateDownStepRAM8195A -10037030 T RateDecisionRAM8195A -10037114 T ArfrRefresh -1003731c T H2CHDL_Set_MACID_Config -100373e0 T PHY_DM_RA_SetRSSI_8195A -1003740e t CheckPositive.isra.0 -100374f0 T ODM_ReadAndConfig_MP_8195A_AGC_TAB -10037568 T ODM_ReadAndConfig_MP_8195A_PHY_REG -100375e0 T ODM_GetVersion_MP_8195A_PHY_REG -100375e4 T ODM_ReadAndConfig_MP_8195A_PHY_REG_PG -10037618 T odm_ConfigRFReg_8195A -10037650 T odm_ConfigRF_RadioA_8195A -10037660 T odm_ConfigMAC_8195A -10037664 T odm_ConfigBB_AGC_8195A -10037674 T odm_ConfigBB_PHY_REG_PG_8195A -100376a2 T odm_ConfigBB_PHY_8195A -100376ea T odm_ConfigBB_TXPWR_LMT_8195A -10037710 T ODM_CmnInfoInit -10037804 T ODM_CmnInfoHook -100378a8 T ODM_CmnInfoPtrArrayHook -100378b8 T ODM_CmnInfoUpdate -10037988 T odm_CommonInfoSelfInit -100379fc T ODM_DMInit -10037a4a T odm_CommonInfoSelfUpdate -10037a9c T ODM_DMWatchdog -10037b08 T PhyDM_Get_Structure -10037b2c T Phydm_CheckAdaptivity -10037b5a T Phydm_NHMCounterStatisticsInit -10037bd0 T Phydm_SetEDCCAThreshold -10037c08 T Phydm_MACEDCCAState -10037c46 T Phydm_AdaptivityInit -10037d24 T Phydm_Adaptivity -10037e44 T ODM_CfoTrackingInit -10037e6e T ODM_CfoTracking -10037e8e T ODM_ParsingCFO -10037ec0 T ODM_InitDebugSetting -10037ed4 T ODM_Write_DIG -10037f74 T odm_ForbiddenIGICheck -10038006 T ODM_Write_CCK_CCA_Thres -10038040 T odm_DIGInit -100380da T odm_DigAbort -100380fc T odm_DIGbyRSSI_LPS -100381a8 T odm_FAThresholdCheck -100381d4 T odm_DIG -10038434 T odm_FalseAlarmCounterStatistics -10038460 T odm_CCKPacketDetectionThresh -100384b8 T odm_RxPhyStatus8195A_Parsing -100385bc T odm_Process_RSSIForDM_8195A -100386fe T ODM_PhyStatusQuery_8195A -1003872a T ODM_PhyStatusQuery -1003872e T ODM_ConfigRFWithHeaderFile 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gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_TFBGA96_8195A -1004e5a8 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_QFN56_8195A -1004e5c6 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_QFN48_8195A -1004e5e4 D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_QFN56_8195A -1004e604 D Array_MP_8195A_RadioA -1004ebcc D gDeltaSwingTableXtal_MP_P_TxXtalTrack_8195A -1004ebea D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_TFBGA96_8195A -1004ec0a D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN48_8195A -1004ec28 D .ram.bss$$Base -1004ec28 D __bss_start__ -1004ec28 D __data_end__ -1004ec28 D __ram_image2_text_end__ -1004ec28 d skbdata_list -1004ec30 V skb_data_pool -10052030 d ucIdleTaskHeap -10052148 D HalI2SOpSAL -10052184 D SYSAdapte -10052188 D PwrAdapter -10052414 D libc_has_init -10052418 d rheap_end -1005241c d event_init.21279 -10052420 D wifi_run_mode -10052424 D wlan_st_netifn -10052425 d sampCntAdd -10052428 d sampCnt -1005242c D mp3_serv -100524ae D tskreader_enable -100524b0 D readBuf -100524b4 D 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-10055858 D skbbuf_used_num -1005585c V skb_pool -10055a14 D skbdata_used_num -10055a18 d wrapper_skbbuf_list -10055a20 D max_skbdata_used_num -10055a24 D max_skbbuf_used_num -10055a28 d skb_fail_count -10055a2c D timer_table -10055a34 D rltk_wlan_info -10055a64 d timer_used_num -10055a68 D max_timer_used_num -10055a6c D Noisy_State -10055a70 D pExportWlanIrqSemaphore -10055a74 D gDeltaSwingTableXtal_MP_N_TxXtalTrack_8195A -10055a92 D .ram.bss$$Limit -10055a92 D __bss_end__ -10055a98 B __ram_heap2_start__ +1003c228 t __rtw_get_wpa_ie_veneer +1003c238 t __rtw_get_wps_attr_content_veneer +1003c248 t __ROM_odm_SetCrystalCap_veneer +1003c258 t __CmdDumpWord_veneer +1003c268 t __PHY_QueryBBReg_8195A_veneer +1003c278 t __prvStrCmp_veneer +1003c288 t __ROM_odm_CfoTrackingFlow_veneer +1003c298 t __HalReInitPlatformLogUartV02_veneer +1003c2a8 t __HalI2SClrAllIntrRtl8195a_veneer +1003c2b8 t __rtw_check_network_type_veneer +1003c2c8 t __HalDelayUs_veneer +1003c2d8 t __rom_psk_CalcGTK_veneer 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UartLogRamCmdTable_end +1004d230 D __data_start__ +1004d230 D wlan_st_name +1004d238 D wifi_st_dhcp +1004d248 D wlan_ap_name +1004d250 D wifi_ap_dhcp +1004d260 D feep_tab +1004d290 D wifi_st_cfg +1004d2fc D wifi_cfg +1004d303 D wlan_ap_netifn +1004d304 D wifi_ap_cfg +1004d370 D oversampling +1004d374 D SystemCoreClock +1004d378 D error_flag +1004d37c d tcp_port +1004d380 d iss.7348 +1004d384 d udp_port +1004d386 D lwip_host_name +1004d3a6 d dhcp_server_state_machine +1004d3a7 d dhcp_recorded_xid +1004d3ac d uxCriticalNesting +1004d3b0 d xNextTaskUnblockTime +1004d3b4 d seed.11739 +1004d3b8 d wakeup_event +1004d3bc d wakelock +1004d3c0 d last_wakelock_state +1004d3e0 D mlme_sta_tbl +1004d450 d PMKID_KDE_TYPE.17744 +1004d458 V nr_xmitbuff +1004d45c V nr_xmitframe +1004d460 d P802_1H_OUI +1004d463 D rtw_adaptivity_mode +1004d464 D g_user_ap_sta_num +1004d468 d rtw_private_handler +1004d4ac V max_local_skb_num +1004d4b0 V max_skb_buf_num +1004d4b4 D rom_e_rtw_msgp_str_ +1004d690 D ARFB_table +1004d6cf D TRYING_NECESSARY_idx +1004d6e3 D DROPING_NECESSARY +1004d6f7 D PER_RATE_UP +1004d70b D PER_RATE_DOWN +1004d720 V Array_MP_8195A_PHY_REG_PG +1004d7b0 D Array_MP_8195A_AGC_TAB +1004d9c0 D Array_MP_8195A_PHY_REG +1004e038 D rtl8195A_card_disable_flow +1004e0d8 D rtl8195A_card_enable_flow +1004e178 D Array_MP_8195A_MAC_REG +1004e480 D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_TFBGA96_8195A +1004e4a0 D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_TFBGA96_8195A +1004e4c0 D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_QFN48_8195A +1004e4de D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_QFN56_8195A +1004e4fc D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_QFN48_8195A +1004e51a D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN56_8195A +1004e538 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_TFBGA96_8195A +1004e558 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_QFN56_8195A +1004e576 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_QFN48_8195A +1004e594 D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_QFN56_8195A +1004e5b4 D Array_MP_8195A_RadioA +1004eb7c D gDeltaSwingTableXtal_MP_P_TxXtalTrack_8195A +1004eb9a D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_TFBGA96_8195A +1004ebba D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN48_8195A +1004ebd8 D .ram.bss$$Base +1004ebd8 D __bss_start__ +1004ebd8 D __data_end__ +1004ebd8 D __ram_image2_text_end__ +1004ebd8 d skbdata_list +1004ebe0 V skb_data_pool +10051fe0 d ucIdleTaskHeap +100520f8 D HalI2SOpSAL +10052134 D SYSAdapte +10052138 D PwrAdapter +100523c4 D libc_has_init +100523c8 d rheap_end +100523cc d event_init.21279 +100523d0 D wifi_run_mode +100523d4 D wlan_st_netifn +100523d5 d sampCntAdd +100523d8 d sampCnt +100523dc D mp3_serv +1005245e D tskreader_enable +10052460 D readBuf +10052464 D tskmad_enable +10052468 d bufUnderrunCt +1005246c d oldRate +10052470 d sampDelCnt +10052474 D pbuf_fifo +10052478 D pi2s +10052480 D I2sTxSema +10052484 D eap_method +10052485 D eap_phase +10052488 D rtw_join_status +1005248c d param.21252 +100524a4 D wifi_mode +100524a8 d join_user_data +100524ac d event_callback_list +1005262c D paff_array +100526a4 D lwip_init_done +100526a8 D xnetif +10052728 d s_aliases.6960 +1005272c D h_errno +10052730 d s_hostent.6959 +10052744 d s_hostent_addr.6961 +10052748 d s_phostent_addr.6962 +10052750 d select_cb_list +10052754 d sockets +10052814 d select_cb_ctr +10052818 d mbox +1005281c d tcpip_init_done_arg +10052820 d tcpip_init_done +10052824 d allsystems +10052828 d allrouters +1005282c d igmp_group_list +10052830 D current_header +10052834 d ip_id +10052838 D current_iphdr_src +1005283c D current_iphdr_dest +10052840 D current_netif +10052844 d str.6325 +10052854 d reassdatagrams +10052858 d ip_reass_pbufcount +1005285a D dhcp_rx_options_given +10052864 D dhcp_rx_options_val +1005288c d xid.7275 +10052890 d dns_seqno +10052894 d dns_table +10052cf4 d dns_servers +10052cfc d dns_payload_buffer +10052f00 d dns_pcb +10052f04 d dns_payload +10052f08 d tcpip_tcp_timer_active +10052f0c d next_timeout +10052f10 D netif_list +10052f14 D netif_default +10052f18 d netif_num +10052f19 D pbuf_free_ooseq_pending +10052f1c d raw_pcbs +10052f20 D tcp_active_pcbs_changed +10052f24 D tcp_ticks +10052f28 d tcp_timer +10052f2c D tcp_listen_pcbs +10052f30 D tcp_active_pcbs +10052f34 d tcp_timer_ctr +10052f38 D tcp_tw_pcbs +10052f3c D tcp_tmp_pcb +10052f40 D tcp_bound_pcbs +10052f44 d seqno +10052f48 d tcplen +10052f4c d ackno +10052f50 d flags +10052f51 d recv_flags +10052f54 d tcphdr +10052f58 d recv_data +10052f5c d inseg +10052f70 D tcp_input_pcb +10052f74 D udp_pcbs +10052f78 d etharp_cached_entry +10052f7c d arp_table +10053044 D lwip_tickless_used +10053048 d s_timeoutlist +10053078 d s_nextthread +1005307c d dhcps_ip_table_semaphore +10053080 d dhcps_send_broadcast_address +10053084 D dhcps_ip4addr_pool_end +10053085 d dhcp_client_ethernet_address +10053098 d dhcps_subnet_broadcast +1005309c d bound_client_ethernet_address +100530ac d ip_table +100530cc d dhcps_pcb +100530d0 d dhcp_message_total_options_lenth +100530d4 d dhcps_local_address +100530d8 d dhcps_netif +100530dc d client_request_ip +100530e0 d dhcps_allocated_client_address +100530e4 d dhcps_local_mask +100530e8 d dhcps_local_gateway +100530ec d dhcps_network_id +100530f0 D dhcps_ip4addr_pool_start +100530f4 d dhcp_message_repository +100530f8 D ext_upper +100530fc d xFreeBytesRemaining +10053100 d ext_free +10053104 D ext_lower +10053108 d pxEnd +1005310c d xStart +10053114 d xMinimumEverFreeBytesRemaining +10053118 d ulTimerCountsForOneTick +1005311c d ulStoppedTimerCompensation +10053120 d xMaximumPossibleSuppressedTicks +10053124 d xPendingReadyList +10053138 d uxTopReadyPriority +1005313c d uxTasksDeleted +10053140 d xTickCount +10053144 d pxReadyTasksLists +10053220 d pxOverflowDelayedTaskList +10053224 d xTasksWaitingTermination +10053238 d pxDelayedTaskList +1005323c d xSchedulerRunning +10053240 d ulTaskSwitchedInTime +10053244 D pxCurrentTCB +10053248 d uxPendedTicks +1005324c d xSuspendedTaskList +10053260 d uxCurrentNumberOfTasks +10053264 d ulDeltaTotalRunTime +10053268 d xDelayedTaskList2 +1005327c d xDelayedTaskList1 +10053290 d uxTaskNumber +10053294 d xYieldPending +10053298 d uxSchedulerSuspended +1005329c d xNumOfOverflows +100532a0 d pxCurrentTimerList +100532a4 d xActiveTimerList1 +100532b8 d xActiveTimerList2 +100532cc d xLastTime.5284 +100532d0 d xTimerQueue +100532d4 d pxOverflowTimerList +100532d8 d xTimerTaskHandle +100532dc d device_mutex +100532e8 d mutex_init +100532ec d uxSavedInterruptStatus +100532f0 D min_free_heap_size +100532f4 d g_heap_inited +100532f8 d tcm_lock +100532fc D g_tcm_heap +10053300 D flashobj +1005330c D fspic_isinit +10053310 D WDGAdapter +1005334c d last_acquire_wakelock_time +100533cc D post_sleep_callback +1005344c D pre_sleep_callback +100534cc D reserve_pll +100534d0 d sys_sleep_time +100534d4 d hold_wakelock_time +10053554 D missing_tick +10053558 D Timer2To7HandlerData +10053570 D auto_reconnect_running +10053574 D p_wlan_autoreconnect_hdl +10053578 D mac_monitor_callback +1005357c D mf_list_head +10053580 d pscan_retry_cnt.21430 +10053584 D promisc_callback_all +10053588 D promisc_sema +1005358c D promisc_callback +10053590 D psk_essid +100535d8 D psk_passphrase +1005365a D psk_passphrase64 +1005369b D wpa_global_PSK +100536eb d RFC1042_OUI +100536f0 d rx_ring_pool +100557d0 d stop_report_count.20629 +100557d1 D bCheckStateTIMER +100557d4 d WifiMcuCmdBitMap.20974 +100557d8 D p_wlan_init_done_callback +100557dc D rtw_power_percentage_idx +100557e0 D p_wlan_uart_adapter_callback +100557e4 D rtw_adaptivity_en +100557e8 D p_wlan_mgmt_filter +100557ec D rtw_initmac +100557f0 D rtw_adaptivity_th_l2h_ini +100557f4 d drvpriv +10055808 D skbbuf_used_num +1005580c V skb_pool +100559c4 D skbdata_used_num +100559c8 d wrapper_skbbuf_list +100559d0 D max_skbdata_used_num +100559d4 D max_skbbuf_used_num +100559d8 d skb_fail_count +100559dc D timer_table +100559e4 D rltk_wlan_info +10055a14 d timer_used_num +10055a18 D max_timer_used_num +10055a1c D Noisy_State +10055a20 D pExportWlanIrqSemaphore +10055a24 D gDeltaSwingTableXtal_MP_N_TxXtalTrack_8195A +10055a42 D .ram.bss$$Limit +10055a42 D __bss_end__ +10055a48 B __ram_heap2_start__ 10070000 A __ram_heap2_end__ 1fff0000 D __ram_tcm_start__ 1fff0000 D __tcm_heap_start__ diff --git a/flasher.mk b/flasher.mk index c8d55e3..d39cbc3 100644 --- a/flasher.mk +++ b/flasher.mk @@ -192,8 +192,8 @@ ifdef COMPILED_BOOT_BIN $(OBJCOPY) --change-section-address .boot.head=0x10000ba8 -j .boot.head -j .bootloader -Obinary $(ELFFILE) $(RAM1P_IMAGE) else $(OBJCOPY) -j .rom_ram -Obinary $(ELFFILE) $(RAM_IMAGE) - $(OBJCOPY) -j .ram.start.table -j .ram_image1.text -Obinary $(ELFFILE) $(RAM1_IMAGE) - $(PICK) 0x$(RAM1_START_ADDR) 0x$(RAM1_END_ADDR) $(RAM1_IMAGE) $(RAM1R_IMAGE) head+reset_offset 0x0B000 + $(OBJCOPY) -j .ram.start.table -j .ram_image1.text -Obinary $(ELFFILE) $(RAM1R_IMAGE) + $(PICK) 0x$(RAM1_START_ADDR) 0x$(RAM1_END_ADDR) $(RAM1R_IMAGE) $(RAM1P_IMAGE) head+reset_offset 0x0B000 endif else $(error "BOOT-image size = 0") diff --git a/flasher/RTL_RunRAM.JLinkScript b/flasher/RTL_RunRAM.JLinkScript index f7410ac..7632f1e 100644 --- a/flasher/RTL_RunRAM.JLinkScript +++ b/flasher/RTL_RunRAM.JLinkScript @@ -4,9 +4,9 @@ r1 trst1 h r -loadbin build/bin/ram_1.bin 0x10000bc8 +loadbin build/bin/ram_1.r.bin 0x10000bc8 loadbin build/bin/ram_2.bin 0x10006000 r -w4 0x40000210,0x20111117 +w4 0x40000210,0x20111113 g q \ No newline at end of file diff --git a/project/inc/platform_autoconf.h b/project/inc/platform_autoconf.h index dd12268..566549a 100644 --- a/project/inc/platform_autoconf.h +++ b/project/inc/platform_autoconf.h @@ -25,7 +25,7 @@ #undef CONFIG_MP #undef CONFIG_CP #undef CONFIG_FT -#define RTL8195A 1 +#define RTL8195A 7 /* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz, 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */ #define CONFIG_CPU_CLK 1 diff --git a/project/src/user/main.c b/project/src/user/main.c index 49b740d..cee3de4 100644 --- a/project/src/user/main.c +++ b/project/src/user/main.c @@ -35,6 +35,14 @@ #include "main.h" #include "wifi_api.h" +/* --------------------------------------------------- + * Customized Signature (Image Name) + * ---------------------------------------------------*/ +#include "section_config.h" +SECTION(".custom.validate.rodata") +const unsigned char cus_sig[32] = "MP3 Stereo"; + + #define DEBUG_MAIN_LEVEL 1 //Priorities of the reader and the decoder thread. Higher = higher prio. diff --git a/sdkbuild.mk b/sdkbuild.mk index e9ccb37..3bb1cfa 100644 --- a/sdkbuild.mk +++ b/sdkbuild.mk @@ -50,7 +50,7 @@ application: build_info $(SRC_O) $(DRAM_O) $(BOOT_O) # @echo "===========================================================" @mkdir -p $(BIN_DIR) $(OBJ_DIR) ## @cp $(patsubst sdk/%,$(SDK_PATH)%,$(BOOTS))/ram_1.r.bin $(BIN_DIR)/ram_1.r.bin - @cp $(patsubst sdk/%,$(SDK_PATH)%,$(BOOTS))/ram_1.p.bin $(BIN_DIR)/ram_1.p.bin +## @cp $(patsubst sdk/%,$(SDK_PATH)%,$(BOOTS))/ram_1.p.bin $(BIN_DIR)/ram_1.p.bin # @chmod 777 $(OBJ_DIR)/ram_1.r.bin ## $(OBJCOPY) --rename-section .data=.loader.data,contents,alloc,load,readonly,data -I binary -O elf32-littlearm -B arm $(BIN_DIR)/ram_1.r.bin $(OBJ_DIR)/ram_1.r.o @echo "===========================================================" diff --git a/sdkset.mk b/sdkset.mk index 7f8c9af..5e22c50 100644 --- a/sdkset.mk +++ b/sdkset.mk @@ -116,7 +116,7 @@ SRC_C += sdk/component/common/api/lwip_netconf.c #SRC_C += sdk/component/common/utilities/ssl_client_ext.c SRC_C += sdk/component/common/utilities/tcptest.c SRC_C += sdk/component/common/utilities/uart_ymodem.c -SRC_C += sdk/component/common/utilities/update.c +#SRC_C += sdk/component/common/utilities/update.c #SRC_C += sdk/component/common/application/uart_adapter/uart_adapter.c SRC_C += sdk/component/common/api/network/src/wlan_network.c SRC_C += sdk/component/common/api/wifi_interactive_mode.c