update

RTL00_SDKV35a/component/common/api/network/include/util.h

@@ -15,6 +15,7 @@ typedef enum _WIFI_EVENT_INDICATE{
 	WIFI_EVENT_DISCONNECT = 1,
 	WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2,
 }WIFI_EVENT_INDICATE;
+rtw_event_indicate_t
 
 int wext_get_ssid(const char *ifname, __u8 *ssid);
 int wext_set_ssid(const char *ifname, const __u8 *ssid, __u16 ssid_len);

RTL00_SDKV35a/component/common/api/platform/platform_stdlib.h

@@ -1,17 +1,38 @@
 /******************************************************************************
+ * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
  *
- * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved.
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
  *
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  ******************************************************************************/
 #ifndef __PLATFORM_STDLIB_H__
 #define __PLATFORM_STDLIB_H__
 
 #define USE_CLIB_PATCH		0
 #if defined (__GNUC__)
+/* build rom should set USE_RTL_ROM_CLIB=0 */
+#ifndef CONFIG_MBED_ENABLED
+#include <rt_lib_rom.h>
+#endif
+#endif
+
+#ifdef CONFIG_BUILD_ROM
+#define USE_RTL_ROM_CLIB	0
+#else
+#define BUFFERED_PRINTF         0
+#ifndef CONFIG_MBED_ENABLED
 #define USE_RTL_ROM_CLIB	1
 #else
-#define USE_RTL_ROM_CLIB	1
+#define USE_RTL_ROM_CLIB	0
+#endif
 #endif
 
 #if defined(CONFIG_PLATFORM_8195A)
@@ -59,7 +80,12 @@
   #endif
 
   #if USE_RTL_ROM_CLIB
+#if BUFFERED_PRINTF
+        extern int buffered_printf(const char* fmt, ...);
+        #define printf				buffered_printf
+#else
 	#define printf                  	rtl_printf
+#endif
 	#define sprintf						rtl_sprintf
 	#define snprintf					rtl_snprintf
 	#define memchr						rtl_memchr
@@ -67,7 +93,6 @@
 	#define memcpy						rtl_memcpy
 	#define memmove						rtl_memmove
 	#define memset						rtl_memset
-	#define bzero(s,l)					rtl_memset(s,0,l)
 	#define strcat						rtl_strcat
 	#define strchr						rtl_strchr
 	#define strcmp(s1, s2)				rtl_strcmp((const char *)s1, (const char *)s2)
@@ -85,8 +110,8 @@
 		extern char* DiagStrtokPatch(char *str, const char* delim);
 		extern char* DiagStrstrPatch(char *string, char *substring);
 		extern int DiagSnPrintfPatch(char *buf, size_t size, const char *fmt, ...);
-		extern int DiagPrintfPatch(const char *fmt, ...);
+		extern u32 DiagPrintfPatch(const char *fmt, ...);
-		extern int DiagSPrintfPatch(u8 *buf, const char *fmt, ...);
+		extern u32  DiagSPrintfPatch(u8 *buf, const char *fmt, ...);
 		#define printf                  DiagPrintfPatch
 		#define sprintf					DiagSPrintfPatch
 		#define snprintf				DiagSnPrintfPatch
@@ -132,18 +157,20 @@
 //
 // memory management
 //
+#ifndef CONFIG_MBED_ENABLED
 extern void *pvPortMalloc( size_t xWantedSize );
 extern void vPortFree( void *pv );
-#undef malloc
 #define malloc                  pvPortMalloc
-#undef free
 #define free                    vPortFree
+#endif
 #elif defined (CONFIG_PLATFORM_8711B)
+
 #if defined (__IARSTDLIB__)
 	#include <stdio.h>
 	#include <stdlib.h>
 	#include <string.h>
 	#include <stdint.h>
+	#include <stdarg.h> /* va_list */
 	#include "diag.h"
 
 	#define strsep(str, delim)      	_strsep(str, delim)
@@ -151,18 +178,24 @@ extern void vPortFree( void *pv );
 	#include <stdio.h>
 	#include <stdlib.h>
 	#include <string.h>
+	#include <stdarg.h> /* va_list */
 	#include "diag.h"
 	#include "strproc.h"
+	#include "memproc.h"
 	#include "basic_types.h"
-	#include "hal_misc.h"
+#if USE_RTL_ROM_CLIB
+	#include "rtl_lib.h"
+	#include "rom_libc_string.h"
+#endif
 
 	#undef printf
 	#undef sprintf
 	#undef snprintf
-	#undef atoi
+	#undef memchr
 	#undef memcmp
 	#undef memcpy
 	#undef memset
+	#undef memmove
 	#undef strcmp
 	#undef strcpy
 	#undef strlen
@@ -170,63 +203,61 @@ extern void vPortFree( void *pv );
 	#undef strncpy
 	#undef strsep
 	#undef strtok
-
-#if USE_RTL_ROM_CLIB
-	#undef memchr
-	#undef memmove
 	#undef strcat
 	#undef strchr
 	#undef strncat
 	#undef strstr
+	#undef atol
+	#undef atoi
+	#undef strpbrk
 	
+#if USE_RTL_ROM_CLIB
+#if BUFFERED_PRINTF
+        extern int buffered_printf(const char* fmt, ...);
+        #define printf				buffered_printf
+#else
 	#define printf				rtl_printf
+#endif
 	#define sprintf				rtl_sprintf
 	#define snprintf				rtl_snprintf
-	#define memchr				rtl_memchr
+	#define vsnprintf				rtl_vsnprintf
-	#define memcmp				rtl_memcmp
-	#define memcpy				rtl_memcpy
-	#define memmove				rtl_memmove
-	#define memset				rtl_memset
-	#define strcat				rtl_strcat
-	#define strchr				rtl_strchr
-	#define strcmp(s1, s2)		rtl_strcmp((const char *)s1, (const char *)s2)
-	#define strcpy				rtl_strcpy
-	#define strlen(str)			rtl_strlen((const char *)str)
-	#define strncat				rtl_strncat
-	#define strncmp(s1, s2, n)	rtl_strncmp((const char *)s1, (const char *)s2, n)
-	#define strncpy				rtl_strncpy
-	#define strstr				rtl_strstr
-	#define strsep				rtl_strsep
-	#define strtok				rtl_strtok
 #else
 	#define printf					DiagPrintf
 	#define sprintf(fmt, arg...)			DiagSPrintf((u8*)fmt, ##arg)
-#if defined (__GNUC__)
 	#define snprintf					DiagSnPrintf			// NULL function
-	#define strstr(str1, str2)			prvStrStr(str1, str2)	// NULL function
+	#define vsnprintf(buf, size, fmt, ap)	VSprintf(buf, fmt, ap)
 #endif
-	#define strtok(str, delim)			_strsep(str, delim)
+	#define memchr					__rtl_memchr_v1_00
-
 	#define memcmp(dst, src, sz)		_memcmp(dst, src, sz)
 	#define memcpy(dst, src, sz)		_memcpy(dst, src, sz)
+	#define memmove						__rtl_memmove_v1_00
 	#define memset(dst, val, sz)		_memset(dst, val, sz)
+	
 	#define strchr(s, c)				_strchr(s, c)			// for B-cut ROM
 	#define strcmp(str1, str2)			prvStrCmp((const unsigned char *) str1, (const unsigned char *) str2)
 	#define strcpy(dest, src)			_strcpy(dest, src)
 	#define strlen(str)				prvStrLen((const unsigned char *) str)
+	#define strsep(str, delim)			_strsep(str, delim)
+	#define strstr(str1, str2)			prvStrStr(str1, str2)	// NULL function
+	#define strtok(str, delim)			prvStrtok(str, delim)//_strsep(str, delim)
+	#define strcat					__rtl_strcat_v1_00
+	
 	#define strncmp(str1, str2, cnt)	_strncmp(str1, str2, cnt)
 	#define strncpy(dest, src, count)	_strncpy(dest, src, count)
-	#define strsep(str, delim)			_strsep(str, delim)
+	#define strncat					__rtl_strncat_v1_00
 	
+	#define atol(str)					strtol(str,NULL,10)
 	#define atoi(str)					prvAtoi(str)	
 	#define strpbrk(cs, ct)			_strpbrk(cs, ct)		// for B-cut ROM
-
 #if defined (__GNUC__)
 	#undef sscanf
-	#define sscanf						_sscanf
+	#define sscanf					_sscanf_patch
+	#define rand					Rand
 #endif
+	//extern int _sscanf_patch(const char *buf, const char *fmt, ...);
+	//#define sscanf					_sscanf_patch
+	
 
-#endif
 #endif	// defined (__IARSTDLIB__)
 
 //
@@ -245,3 +276,4 @@ extern void vPortFree( void *pv );
 
 
 #endif //__PLATFORM_STDLIB_H__
+

RTL00_SDKV35a/component/common/api/wifi/wifi_conf.h

@@ -1,6 +1,6 @@
 //----------------------------------------------------------------------------//
-#ifndef __WIFI_API_H
+#ifndef __WIFI_CONF_API_H
-#define __WIFI_API_H
+#define __WIFI_CONF_API_H
 
 #include "FreeRTOS.h"
 #include "wifi_constants.h"   
@@ -705,6 +705,6 @@ int wifi_remove_packet_filter(unsigned char filter_id);
   }
 #endif
 
-#endif // __WIFI_API_H
+#endif // __WIFI_CONF_API_H
 
 //----------------------------------------------------------------------------//

RTL00_SDKV35a/component/common/api/wifi_api.c

@@ -367,6 +367,7 @@ extern int lwip_init_done;
 
 void _LwIP_Init(void)
 {
+	if(!lwip_init_done) {
 		int idx;
 		debug_printf("LwIP Init (%d)\n", wifi_mode);
 		/* Create tcp_ip stack thread */
@@ -400,12 +401,16 @@ void _LwIP_Init(void)
 		wifi_mode = 0;
 		lwip_init_done = 1;
 	}
+}
 
 int wifi_run(rtw_mode_t mode) {
 	int ret = 0;
 #if CONFIG_DEBUG_LOG > 4
 	debug_printf("\n%s(%d), %d\n", __func__, mode, wifi_run_mode);
 #endif
+	if(mode != RTW_MODE_NONE) {
+		_LwIP_Init();
+	};
 	if(wifi_run_mode & RTW_MODE_AP) {
 		info_printf("Deinit old AP...\n");
 		LwIP_DHCP(WLAN_AP_NETIF_NUM, DHCP_STOP);
@@ -414,12 +419,12 @@ int wifi_run(rtw_mode_t mode) {
 #endif
 		dhcps_deinit();
 		wifi_run_mode &= ~RTW_MODE_AP;
-	}
+	};
 	if(wifi_run_mode & RTW_MODE_STA) {
 		info_printf("Deinit old ST...\n");
 		LwIP_DHCP(WLAN_ST_NETIF_NUM, DHCP_STOP);
 		wifi_run_mode &= ~RTW_MODE_STA;
-	}
+	};
 //	if(mode != wifi_mode)
 //	wifi_mode = mode;
 //	chk_ap_netif_num();
@@ -469,7 +474,7 @@ error_end:
 		connect_close();
 #endif
 		wifi_off();
-	}
+	};
 	chk_ap_netif_num();
 	return ret;
 }
@@ -484,10 +489,6 @@ void wifi_init_thrd(void) {
 	p_wlan_autoreconnect_hdl = NULL;
 	if (wifi_cfg.mode != RTW_MODE_NONE) {
 		wifi_mode = wifi_cfg.mode;
-		if(!lwip_init_done) {
-		/* Initilaize the LwIP stack */
-			_LwIP_Init();
-		};
 		user_start();
 #if CONFIG_WIFI_IND_USE_THREAD
 		wifi_manager_init();

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/HalPwrSeqCmd.h

@@ -0,0 +1,136 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __HALPWRSEQCMD_H__
+#define __HALPWRSEQCMD_H__
+
+/*---------------------------------------------*/
+//3 The value of cmd: 4 bits
+/*---------------------------------------------*/
+#define PWR_CMD_READ			0x00
+     // offset: the read register offset
+     // msk: the mask of the read value
+     // value: N/A, left by 0
+     // note: dirver shall implement this function by read & msk
+
+#define PWR_CMD_WRITE			0x01
+     // offset: the read register offset
+     // msk: the mask of the write bits
+     // value: write value
+     // note: driver shall implement this cmd by read & msk after write
+
+#define PWR_CMD_POLLING			0x02
+     // offset: the read register offset
+     // msk: the mask of the polled value
+     // value: the value to be polled, masked by the msd field.
+     // note: driver shall implement this cmd by
+     // do{
+     // if( (Read(offset) & msk) == (value & msk) )
+     // break;
+     // } while(not timeout);
+
+#define PWR_CMD_DELAY			0x03
+     // offset: the value to delay
+     // msk: N/A
+     // value: the unit of delay, 0: us, 1: ms
+
+#define PWR_CMD_END				0x04
+     // offset: N/A
+     // msk: N/A
+     // value: N/A
+
+/*---------------------------------------------*/
+//3 The value of base: 4 bits
+/*---------------------------------------------*/
+   // define the base address of each block
+#define PWR_BASEADDR_MAC		0x00
+#define PWR_BASEADDR_USB		0x01
+#define PWR_BASEADDR_PCIE		0x02
+#define PWR_BASEADDR_SDIO		0x03
+
+/*---------------------------------------------*/
+//3 The value of interface_msk: 4 bits
+/*---------------------------------------------*/
+#define	PWR_INTF_SDIO_MSK		BIT(0)
+#define	PWR_INTF_USB_MSK		BIT(1)
+#define	PWR_INTF_PCI_MSK		BIT(2)
+#define	PWR_INTF_ALL_MSK		(BIT(0)|BIT(1)|BIT(2)|BIT(3))
+
+/*---------------------------------------------*/
+//3 The value of fab_msk: 4 bits
+/*---------------------------------------------*/
+#define	PWR_FAB_TSMC_MSK		BIT(0)
+#define	PWR_FAB_UMC_MSK			BIT(1)
+#define	PWR_FAB_ALL_MSK			(BIT(0)|BIT(1)|BIT(2)|BIT(3))
+
+/*---------------------------------------------*/
+//3 The value of cut_msk: 8 bits
+/*---------------------------------------------*/
+#define	PWR_CUT_TESTCHIP_MSK	BIT(0)
+#define	PWR_CUT_A_MSK			BIT(1)
+#define	PWR_CUT_B_MSK			BIT(2)
+#define	PWR_CUT_C_MSK			BIT(3)
+#define	PWR_CUT_D_MSK			BIT(4)
+#define	PWR_CUT_E_MSK			BIT(5)
+#define	PWR_CUT_F_MSK			BIT(6)
+#define	PWR_CUT_G_MSK			BIT(7)
+#define	PWR_CUT_ALL_MSK			0xFF
+
+
+typedef enum _PWRSEQ_CMD_DELAY_UNIT_
+{
+	PWRSEQ_DELAY_US,
+	PWRSEQ_DELAY_MS,
+} PWRSEQ_DELAY_UNIT;
+
+typedef struct _WL_PWR_CFG_
+{
+	u16 offset;
+	u8 cut_msk;
+	u8 fab_msk:4;
+	u8 interface_msk:4;
+	u8 base:4;
+	u8 cmd:4;
+	u8 msk;
+	u8 value;
+} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
+
+
+#define GET_PWR_CFG_OFFSET(__PWR_CMD)		__PWR_CMD.offset
+#define GET_PWR_CFG_CUT_MASK(__PWR_CMD)		__PWR_CMD.cut_msk
+#define GET_PWR_CFG_FAB_MASK(__PWR_CMD)		__PWR_CMD.fab_msk
+#define GET_PWR_CFG_INTF_MASK(__PWR_CMD)	__PWR_CMD.interface_msk
+#define GET_PWR_CFG_BASE(__PWR_CMD)			__PWR_CMD.base
+#define GET_PWR_CFG_CMD(__PWR_CMD)			__PWR_CMD.cmd
+#define GET_PWR_CFG_MASK(__PWR_CMD)			__PWR_CMD.msk
+#define GET_PWR_CFG_VALUE(__PWR_CMD)		__PWR_CMD.value
+
+
+//================================================================================
+//	Prototype of protected function.
+//================================================================================
+u8 HalPwrSeqCmdParsing(
+	_adapter *		padapter,
+	u8				CutVersion,
+	u8				FabVersion,
+	u8				InterfaceType,
+	WLAN_PWR_CFG	PwrCfgCmd[]);
+
+#endif
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/HalVerDef.h

@@ -0,0 +1,178 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __HAL_VERSION_DEF_H__
+#define __HAL_VERSION_DEF_H__
+
+#ifndef TRUE
+#define TRUE 	_TRUE	
+#endif
+#ifndef FALSE
+#define FALSE	_FALSE
+#endif
+
+// HAL_IC_TYPE_E
+typedef enum tag_HAL_IC_Type_Definition
+{
+	CHIP_8192S	=	0,
+	CHIP_8188C	=	1,
+	CHIP_8192C	=	2,
+	CHIP_8192D	=	3,
+	CHIP_8723A	=	4,
+	CHIP_8188E	=	5,
+	CHIP_8812	=	6,
+	CHIP_8821	=	7,
+	CHIP_8723B 	=	8,
+	CHIP_8192E 	=	9,
+	CHIP_8195A =	10,
+	CHIP_8710B =    11,
+	CHIP_8188F = 	12,
+}HAL_IC_TYPE_E;
+
+//HAL_CHIP_TYPE_E
+typedef enum tag_HAL_CHIP_Type_Definition
+{
+	TEST_CHIP 		=	0,
+	NORMAL_CHIP 	=	1,
+	FPGA			=	2,
+}HAL_CHIP_TYPE_E;
+
+//HAL_CUT_VERSION_E
+typedef enum tag_HAL_Cut_Version_Definition
+{
+	A_CUT_VERSION 		=	0,
+	B_CUT_VERSION 		=	1,
+	C_CUT_VERSION 		=	2,
+	D_CUT_VERSION 		=	3,
+	E_CUT_VERSION 		=	4,
+	F_CUT_VERSION 		=	5,
+	G_CUT_VERSION 		=	6,
+	H_CUT_VERSION 		=	7,	
+	I_CUT_VERSION 		=	8,
+	J_CUT_VERSION 		=	9,
+	K_CUT_VERSION 		=	10,
+}HAL_CUT_VERSION_E;
+
+// HAL_Manufacturer
+typedef enum tag_HAL_Manufacturer_Version_Definition
+{
+	CHIP_VENDOR_TSMC 	=	0,
+	CHIP_VENDOR_UMC 	=	1,
+	CHIP_VENDOR_SMIC 	=	2,
+}HAL_VENDOR_E;
+
+typedef enum tag_HAL_RF_Type_Definition
+{
+	RF_TYPE_1T1R 	=	0,
+	RF_TYPE_1T2R 	=	1,
+	RF_TYPE_2T2R	=	2,
+	RF_TYPE_2T3R	=	3,
+	RF_TYPE_2T4R	=	4,
+	RF_TYPE_3T3R	=	5,
+	RF_TYPE_3T4R	=	6,
+	RF_TYPE_4T4R	=	7,
+}HAL_RF_TYPE_E;
+
+typedef	struct tag_HAL_VERSION
+{
+	HAL_IC_TYPE_E		ICType;
+	HAL_CHIP_TYPE_E		ChipType;
+	HAL_CUT_VERSION_E	CUTVersion;
+	HAL_VENDOR_E		VendorType;
+	HAL_RF_TYPE_E		RFType;	
+	u8					ROMVer;
+}HAL_VERSION,*PHAL_VERSION;
+
+//VERSION_8192C			VersionID;
+//HAL_VERSION			VersionID;
+
+// Get element
+#define GET_CVID_IC_TYPE(version)			((HAL_IC_TYPE_E)((version).ICType)	)
+#define GET_CVID_CHIP_TYPE(version)			((HAL_CHIP_TYPE_E)((version).ChipType)	)
+#define GET_CVID_RF_TYPE(version)			((HAL_RF_TYPE_E)((version).RFType))
+#define GET_CVID_MANUFACTUER(version)		((HAL_VENDOR_E)((version).VendorType))
+#define GET_CVID_CUT_VERSION(version)		((HAL_CUT_VERSION_E)((version).CUTVersion))
+#define GET_CVID_ROM_VERSION(version)		(((version).ROMVer) & ROM_VERSION_MASK)
+
+//----------------------------------------------------------------------------
+//Common Macro. --
+//----------------------------------------------------------------------------
+//HAL_VERSION VersionID
+
+// HAL_IC_TYPE_E
+#define IS_81XXC(version)				(((GET_CVID_IC_TYPE(version) == CHIP_8192C)||(GET_CVID_IC_TYPE(version) == CHIP_8188C))? TRUE : FALSE)
+#define IS_8723_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8723A)? TRUE : FALSE)
+#define IS_92D(version)					((GET_CVID_IC_TYPE(version) == CHIP_8192D)? TRUE : FALSE)
+#define IS_8188E(version)					((GET_CVID_IC_TYPE(version) == CHIP_8188E)? TRUE : FALSE)
+#define IS_8192E(version)					((GET_CVID_IC_TYPE(version) == CHIP_8192E)? TRUE : FALSE)
+#define IS_8812_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8812)? TRUE : FALSE)
+#define IS_8821_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8821)? TRUE : FALSE)
+#define IS_8723B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8723B)? TRUE : FALSE)
+#define IS_8710B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8710B)? TRUE : FALSE)
+#define IS_8188F(version)					((GET_CVID_IC_TYPE(version) == CHIP_8188F)? TRUE : FALSE)
+
+//HAL_CHIP_TYPE_E
+#define IS_TEST_CHIP(version)			((GET_CVID_CHIP_TYPE(version)==TEST_CHIP)? TRUE: FALSE)
+#define IS_NORMAL_CHIP(version)			((GET_CVID_CHIP_TYPE(version)==NORMAL_CHIP)? TRUE: FALSE)
+
+//HAL_CUT_VERSION_E
+#define IS_A_CUT(version)				((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? TRUE : FALSE)
+#define IS_B_CUT(version)				((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? TRUE : FALSE)
+#define IS_C_CUT(version)				((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE)
+#define IS_D_CUT(version)				((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE)
+#define IS_E_CUT(version)				((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)
+#define IS_I_CUT(version)				((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? TRUE : FALSE)
+#define IS_J_CUT(version)				((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? TRUE : FALSE)
+#define IS_K_CUT(version)				((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? TRUE : FALSE)
+
+//HAL_VENDOR_E
+#define IS_CHIP_VENDOR_TSMC(version)	((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC)? TRUE: FALSE)
+#define IS_CHIP_VENDOR_UMC(version)	((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC)? TRUE: FALSE)
+#define IS_CHIP_VENDOR_SMIC(version)	((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_SMIC)? TRUE: FALSE)
+
+//HAL_RF_TYPE_E
+#define IS_1T1R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R)? TRUE : FALSE )
+#define IS_1T2R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? TRUE : FALSE)
+#define IS_2T2R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? TRUE : FALSE)
+
+
+//----------------------------------------------------------------------------
+//Chip version Macro. --
+//----------------------------------------------------------------------------
+#define IS_81XXC_TEST_CHIP(version)		((IS_81XXC(version) && (!IS_NORMAL_CHIP(version)))? TRUE: FALSE)
+
+#define IS_92C_SERIAL(version)   					((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
+#define IS_81xxC_VENDOR_UMC_A_CUT(version)	(IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE): FALSE)
+#define IS_81xxC_VENDOR_UMC_B_CUT(version)	(IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE): FALSE)
+#define IS_81xxC_VENDOR_UMC_C_CUT(version)	(IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE): FALSE)
+
+#define IS_NORMAL_CHIP92D(version)		(( IS_92D(version))?((GET_CVID_CHIP_TYPE(version)==NORMAL_CHIP)? TRUE: FALSE):FALSE)
+
+#define IS_92D_SINGLEPHY(version)		((IS_92D(version)) ? (IS_2T2R(version) ? TRUE: FALSE) : FALSE)
+#define IS_92D_C_CUT(version)			((IS_92D(version)) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE)
+#define IS_92D_D_CUT(version)			((IS_92D(version)) ? (IS_D_CUT(version) ? TRUE : FALSE) : FALSE)
+#define IS_92D_E_CUT(version)			((IS_92D(version)) ? (IS_E_CUT(version) ? TRUE : FALSE) : FALSE)
+
+#define IS_8723A_A_CUT(version)				((IS_8723_SERIES(version)) ? ( IS_A_CUT(version)?TRUE : FALSE) : FALSE)
+#define IS_8723A_B_CUT(version)				((IS_8723_SERIES(version)) ? ( IS_B_CUT(version)?TRUE : FALSE) : FALSE)
+
+#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)		((IS_8188E(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE)
+
+#endif
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/autoconf.h

@@ -1,3 +1,22 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
 #ifndef WLANCONFIG_H
 #define WLANCONFIG_H
 
@@ -22,10 +41,11 @@
 
 #ifndef CONFIG_INIC_EN
 #define CONFIG_INIC_EN 0 //For iNIC project
+#endif
+
 #if CONFIG_INIC_EN
 #define CONFIG_LWIP_LAYER    0
 #endif
-#endif
 
 #define CONFIG_LITTLE_ENDIAN
 #define CONFIG_80211N_HT 
@@ -61,8 +81,11 @@
 #endif // CONFIG_PLATFORM_AMEBA_X
 
 //#define CONFIG_DONT_CARE_TP
+//#define CONFIG_HIGH_TP
 //#define CONFIG_MEMORY_ACCESS_ALIGNED
+#ifndef PLATFORM_CMSIS_RTOS  // unsupported feature
 #define CONFIG_POWER_SAVING
+#endif
 #ifdef CONFIG_POWER_SAVING
 	#define CONFIG_IPS
 	#define CONFIG_LPS
@@ -128,14 +151,16 @@
 #define NOT_SUPPORT_VHT
 #define NOT_SUPPORT_40M
 #define NOT_SUPPORT_80M
+#ifndef CONFIG_PLATFORM_8711B
 #define NOT_SUPPORT_BBSWING
+#endif
 #define NOT_SUPPORT_OLD_CHANNEL_PLAN
 #define NOT_SUPPORT_BT
 
 #define CONFIG_WIFI_SPEC	0
 #define CONFIG_FAKE_EFUSE	0
 #if CONFIG_FAKE_EFUSE
-	#define FAKE_CHIPID		CHIPID_8711AN
+	#define FAKE_CHIPID		CHIPID_8710BN
 #endif
 
 #define CONFIG_AUTO_RECONNECT 1
@@ -156,9 +181,6 @@
 
 /* For promiscuous mode */
 #define CONFIG_PROMISC
-#ifdef CONFIG_PROMISC
-//#define CONFIG_PROMISC_SCAN_CONCURENT
-#endif
 
 #define PROMISC_DENY_PAIRWISE	0
 
@@ -176,9 +198,7 @@
 #endif
 
 /* For STA+AP Concurrent MODE */
-#if !defined(CONFIG_PLATFORM_8711B)
 #define CONFIG_CONCURRENT_MODE
-#endif
 #ifdef CONFIG_CONCURRENT_MODE
   #if defined(CONFIG_PLATFORM_8195A)
     #define CONFIG_RUNTIME_PORT_SWITCH
@@ -210,8 +230,9 @@
 #endif
 
 // enable 1X code in lib_wlan as default (increase 380 bytes)
+#ifndef PLATFORM_CMSIS_RTOS  // unsupported feature
 #define CONFIG_EAP
-
+#endif
 #if CONFIG_TLS || CONFIG_PEAP || CONFIG_TTLS
 #define EAP_REMOVE_UNUSED_CODE 1
 #endif	     
@@ -233,7 +254,7 @@
 /****************** End of EAP configurations *******************/
 
 /* For WPS and P2P */
-// #define CONFIG_WPS
+#define CONFIG_WPS
 #if 0
 #define CONFIG_WPS_AP
 #define CONFIG_P2P_NEW
@@ -243,6 +264,7 @@
 #endif
 
 #define CONFIG_NEW_SIGNAL_STAT_PROCESS
+#define CONFIG_SKIP_SIGNAL_SCALE_MAPPING
 
 /* For AP_MODE */
 #define CONFIG_AP_MODE
@@ -259,6 +281,10 @@ extern unsigned int g_ap_sta_num;
 #define AP_STA_NUM 3//g_ap_sta_num
 #endif
 #ifdef CONFIG_AP_MODE
+#if defined(CONFIG_PLATFORM_8195A)  
+	 //softap sent qos null0 polling client alive or not
+	#define CONFIG_AP_POLLING_CLIENT_ALIVE 
+#endif
 	#define CONFIG_NATIVEAP_MLME
 #if defined(CONFIG_PLATFORM_AMEBA_X)
 	#define CONFIG_INTERRUPT_BASED_TXBCN
@@ -318,20 +344,27 @@ extern unsigned int g_ap_sta_num;
 		//Control wifi mcu function
 		#define CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD
 		#define CONFIG_ODM_REFRESH_RAMASK
-		#define CONFIG_ANTENNA_DIVERSITY
 	#endif
 #endif // #ifdef CONFIG_MP_INCLUDED
 
 #if defined(CONFIG_PLATFORM_AMEBA_X)
 	#if defined(CONFIG_PLATFORM_8195A)
-		#ifndef CONFIG_RTL8195A
+		#undef CONFIG_RTL8195A
 		#define CONFIG_RTL8195A
 	#endif
-	#endif
 	#if defined(CONFIG_PLATFORM_8711B)
 		#ifndef CONFIG_RTL8711B 
 			#define CONFIG_RTL8711B
 		#endif
+		#undef CONFIG_ADAPTOR_INFO_CACHING_FLASH
+		#define CONFIG_ADAPTOR_INFO_CACHING_FLASH 0
+		//#undef CONFIG_EAP
+		//#undef CONFIG_IPS
+		#define CONFIG_8710B_MOVE_TO_ROM
+		#define CONFIG_EFUSE_SEPARATE
+		#define CONFIG_MOVE_PSK_TO_ROM
+		#define CONFIG_WOWLAN
+		#define CONFIG_TRAFFIC_PROTECT
 	#endif
 #elif defined(CONFIG_HARDWARE_8188F)
 #define CONFIG_RTL8188F
@@ -385,8 +418,7 @@ extern unsigned int g_ap_sta_num;
 	#define DBG_TX_RATE 1			// DebugComponents: bit9
 	#define DBG_DM_RA 1				// DebugComponents: bit9
 	#define DBG_DM_DIG 1			// DebugComponents: bit0
-	#define DBG_DM_ANT_DIV 1		// DebugComponents: bit6
+	#define DBG_DM_ADAPTIVITY 1		// DebugComponents: bit16
-	#define DBG_DM_ADAPTIVITY 1		// DebugComponents: bit17
 	// RF
 	#define DBG_PWR_TRACKING 1		// DebugComponents: bit24
 	#define DBG_RF_IQK 1			// DebugComponents: bit26
@@ -398,6 +430,9 @@ extern unsigned int g_ap_sta_num;
 /* For DM support */
 #if defined(CONFIG_RTL8188F)
 #define RATE_ADAPTIVE_SUPPORT 0
+#elif defined(CONFIG_PLATFORM_8711B)
+#define RATE_ADAPTIVE_SUPPORT 1
+#define CONFIG_ODM_REFRESH_RAMASK
 #else
 #define RATE_ADAPTIVE_SUPPORT 1
 #endif
@@ -431,7 +466,7 @@ extern unsigned int g_ap_sta_num;
 #if (SKB_PRE_ALLOCATE_RX == 1)
 	#define EXCHANGE_LXBUS_RX_SKB 0
 #endif
-#if defined(CONFIG_PLATFORM_8711B)
+#ifdef CONFIG_FPGA
 	//Enable mac loopback for test mode (Ameba)
 	#define CONFIG_TWO_MAC_DRIVER // for test mode
 #endif

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/byteorder/generic.h

@@ -0,0 +1,223 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef _LINUX_BYTEORDER_GENERIC_H
+#define _LINUX_BYTEORDER_GENERIC_H
+
+/*
+ * linux/byteorder_generic.h
+ * Generic Byte-reordering support
+ *
+ * Francois-Rene Rideau <fare@tunes.org> 19970707
+ *    gathered all the good ideas from all asm-foo/byteorder.h into one file,
+ *    cleaned them up.
+ *    I hope it is compliant with non-GCC compilers.
+ *    I decided to put __BYTEORDER_HAS_U64__ in byteorder.h,
+ *    because I wasn't sure it would be ok to put it in types.h
+ *    Upgraded it to 2.1.43
+ * Francois-Rene Rideau <fare@tunes.org> 19971012
+ *    Upgraded it to 2.1.57
+ *    to please Linus T., replaced huge #ifdef's between little/big endian
+ *    by nestedly #include'd files.
+ * Francois-Rene Rideau <fare@tunes.org> 19971205
+ *    Made it to 2.1.71; now a facelift:
+ *    Put files under include/linux/byteorder/
+ *    Split swab from generic support.
+ *
+ * TODO:
+ *   = Regular kernel maintainers could also replace all these manual
+ *    byteswap macros that remain, disseminated among drivers,
+ *    after some grep or the sources...
+ *   = Linus might want to rename all these macros and files to fit his taste,
+ *    to fit his personal naming scheme.
+ *   = it seems that a few drivers would also appreciate
+ *    nybble swapping support...
+ *   = every architecture could add their byteswap macro in asm/byteorder.h
+ *    see how some architectures already do (i386, alpha, ppc, etc)
+ *   = cpu_to_beXX and beXX_to_cpu might some day need to be well
+ *    distinguished throughout the kernel. This is not the case currently,
+ *    since little endian, big endian, and pdp endian machines needn't it.
+ *    But this might be the case for, say, a port of Linux to 20/21 bit
+ *    architectures (and F21 Linux addict around?).
+ */
+
+/*
+ * The following macros are to be defined by <asm/byteorder.h>:
+ *
+ * Conversion of long and short int between network and host format
+ *	ntohl(__u32 x)
+ *	ntohs(__u16 x)
+ *	htonl(__u32 x)
+ *	htons(__u16 x)
+ * It seems that some programs (which? where? or perhaps a standard? POSIX?)
+ * might like the above to be functions, not macros (why?).
+ * if that's true, then detect them, and take measures.
+ * Anyway, the measure is: define only ___ntohl as a macro instead,
+ * and in a separate file, have
+ * unsigned long inline ntohl(x){return ___ntohl(x);}
+ *
+ * The same for constant arguments
+ *	__constant_ntohl(__u32 x)
+ *	__constant_ntohs(__u16 x)
+ *	__constant_htonl(__u32 x)
+ *	__constant_htons(__u16 x)
+ *
+ * Conversion of XX-bit integers (16- 32- or 64-)
+ * between native CPU format and little/big endian format
+ * 64-bit stuff only defined for proper architectures
+ *	cpu_to_[bl]eXX(__uXX x)
+ *	[bl]eXX_to_cpu(__uXX x)
+ *
+ * The same, but takes a pointer to the value to convert
+ *	cpu_to_[bl]eXXp(__uXX x)
+ *	[bl]eXX_to_cpup(__uXX x)
+ *
+ * The same, but change in situ
+ *	cpu_to_[bl]eXXs(__uXX x)
+ *	[bl]eXX_to_cpus(__uXX x)
+ *
+ * See asm-foo/byteorder.h for examples of how to provide
+ * architecture-optimized versions
+ *
+ */
+
+
+#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) || defined(PLATFORM_FREEBSD) || defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
+/*
+ * inside the kernel, we can use nicknames;
+ * outside of it, we must avoid POSIX namespace pollution...
+ */
+
+//TODO
+#if 0
+
+#define cpu_to_le64 __cpu_to_le64
+#define le64_to_cpu __le64_to_cpu
+
+#endif	//#if 0
+
+#define cpu_to_le32 __cpu_to_le32
+#define le32_to_cpu __le32_to_cpu
+#define cpu_to_le16 __cpu_to_le16
+#define le16_to_cpu __le16_to_cpu
+#define cpu_to_be64 __cpu_to_be64
+#define be64_to_cpu __be64_to_cpu
+#define cpu_to_be32 __cpu_to_be32
+#define be32_to_cpu __be32_to_cpu
+#define cpu_to_be16 __cpu_to_be16
+#define be16_to_cpu __be16_to_cpu
+#define cpu_to_le64p __cpu_to_le64p
+#define le64_to_cpup __le64_to_cpup
+#define cpu_to_le32p __cpu_to_le32p
+#define le32_to_cpup __le32_to_cpup
+#define cpu_to_le16p __cpu_to_le16p
+#define le16_to_cpup __le16_to_cpup
+#define cpu_to_be64p __cpu_to_be64p
+#define be64_to_cpup __be64_to_cpup
+#define cpu_to_be32p __cpu_to_be32p
+#define be32_to_cpup __be32_to_cpup
+#define cpu_to_be16p __cpu_to_be16p
+#define be16_to_cpup __be16_to_cpup
+#define cpu_to_le64s __cpu_to_le64s
+#define le64_to_cpus __le64_to_cpus
+#define cpu_to_le32s __cpu_to_le32s
+#define le32_to_cpus __le32_to_cpus
+#define cpu_to_le16s __cpu_to_le16s
+#define le16_to_cpus __le16_to_cpus
+#define cpu_to_be64s __cpu_to_be64s
+#define be64_to_cpus __be64_to_cpus
+#define cpu_to_be32s __cpu_to_be32s
+#define be32_to_cpus __be32_to_cpus
+#define cpu_to_be16s __cpu_to_be16s
+#define be16_to_cpus __be16_to_cpus
+#endif
+
+//TODO
+#if 0
+
+/*
+ * Handle ntohl and suches. These have various compatibility
+ * issues - like we want to give the prototype even though we
+ * also have a macro for them in case some strange program
+ * wants to take the address of the thing or something..
+ *
+ * Note that these used to return a "long" in libc5, even though
+ * long is often 64-bit these days.. Thus the casts.
+ *
+ * They have to be macros in order to do the constant folding
+ * correctly - if the argument passed into a inline function
+ * it is no longer constant according to gcc..
+ */
+
+#undef ntohl
+#undef ntohs
+#undef htonl
+#undef htons
+
+/*
+ * Do the prototypes. Somebody might want to take the
+ * address or some such sick thing..
+ */
+#if defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2)
+extern __u32			ntohl(__u32);
+extern __u32			htonl(__u32);
+#else //defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2)
+#ifndef PLATFORM_FREEBSD
+extern unsigned long int	ntohl(unsigned long int);
+extern unsigned long int	htonl(unsigned long int);
+#endif
+#endif
+#ifndef PLATFORM_FREEBSD
+extern unsigned short int	ntohs(unsigned short int);
+extern unsigned short int	htons(unsigned short int);
+#endif
+
+#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) ||  defined(PLATFORM_MPIXEL)
+
+#define ___htonl(x) __cpu_to_be32(x)
+#define ___htons(x) __cpu_to_be16(x)
+#define ___ntohl(x) __be32_to_cpu(x)
+#define ___ntohs(x) __be16_to_cpu(x)
+
+#if defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2)
+#define htonl(x) ___htonl(x)
+#define ntohl(x) ___ntohl(x)
+#else
+#define htonl(x) ((unsigned long)___htonl(x))
+#define ntohl(x) ((unsigned long)___ntohl(x))
+#endif
+#define htons(x) ___htons(x)
+#define ntohs(x) ___ntohs(x)
+
+#endif /* OPTIMIZE */
+
+
+#if defined (PLATFORM_WINDOWS)
+
+#define htonl(x) __cpu_to_be32(x)
+#define ntohl(x) __be32_to_cpu(x)
+#define htons(x) __cpu_to_be16(x)
+#define ntohs(x) __be16_to_cpu(x)
+
+#endif
+
+#endif	//#if 0
+
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/byteorder/little_endian.h

@@ -0,0 +1,97 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+
+#ifndef __LITTLE_ENDIAN
+#define __LITTLE_ENDIAN 1234
+#endif
+#ifndef __LITTLE_ENDIAN_BITFIELD
+#define __LITTLE_ENDIAN_BITFIELD
+#endif
+
+#include <byteorder/swab.h>
+
+#ifndef __constant_htonl
+
+//TODO
+#if 0
+
+#define __constant_htonl(x) ___constant_swab32((x))
+#define __constant_ntohl(x) ___constant_swab32((x))
+#define __constant_htons(x) ___constant_swab16((x))
+#define __constant_ntohs(x) ___constant_swab16((x))
+#define __constant_cpu_to_le64(x) ((__u64)(x))
+#define __constant_le64_to_cpu(x) ((__u64)(x))
+#define __constant_cpu_to_le32(x) ((__u32)(x))
+#define __constant_le32_to_cpu(x) ((__u32)(x))
+#define __constant_cpu_to_le16(x) ((__u16)(x))
+#define __constant_le16_to_cpu(x) ((__u16)(x))
+#define __constant_cpu_to_be64(x) ___constant_swab64((x))
+#define __constant_be64_to_cpu(x) ___constant_swab64((x))
+#define __constant_cpu_to_be32(x) ___constant_swab32((x))
+#define __constant_be32_to_cpu(x) ___constant_swab32((x))
+#define __constant_cpu_to_be16(x) ___constant_swab16((x))
+#define __constant_be16_to_cpu(x) ___constant_swab16((x))
+#define __cpu_to_le64(x) ((__u64)(x))
+#define __le64_to_cpu(x) ((__u64)(x))
+
+#endif	//#if 0
+
+#define __cpu_to_le32(x) ((__u32)(x))
+#define __le32_to_cpu(x) ((__u32)(x))
+#define __cpu_to_le16(x) ((__u16)(x))
+#define __le16_to_cpu(x) ((__u16)(x))
+#define __cpu_to_be64(x) __swab64((x))
+#define __be64_to_cpu(x) __swab64((x))
+#define __cpu_to_be32(x) __swab32((x))
+#define __be32_to_cpu(x) __swab32((x))
+#define __cpu_to_be16(x) __swab16((x))
+#define __be16_to_cpu(x) __swab16((x))
+#define __cpu_to_le64p(x) (*(__u64*)(x))
+#define __le64_to_cpup(x) (*(__u64*)(x))
+#define __cpu_to_le32p(x) (*(__u32*)(x))
+#define __le32_to_cpup(x) (*(__u32*)(x))
+#define __cpu_to_le16p(x) (*(__u16*)(x))
+#define __le16_to_cpup(x) (*(__u16*)(x))
+#define __cpu_to_be64p(x) __swab64p((x))
+#define __be64_to_cpup(x) __swab64p((x))
+#define __cpu_to_be32p(x) __swab32p((x))
+#define __be32_to_cpup(x) __swab32p((x))
+#define __cpu_to_be16p(x) __swab16p((x))
+#define __be16_to_cpup(x) __swab16p((x))
+#define __cpu_to_le64s(x) do {} while (0)
+#define __le64_to_cpus(x) do {} while (0)
+#define __cpu_to_le32s(x) do {} while (0)
+#define __le32_to_cpus(x) do {} while (0)
+#define __cpu_to_le16s(x) do {} while (0)
+#define __le16_to_cpus(x) do {} while (0)
+#define __cpu_to_be64s(x) __swab64s((x))
+#define __be64_to_cpus(x) __swab64s((x))
+#define __cpu_to_be32s(x) __swab32s((x))
+#define __be32_to_cpus(x) __swab32s((x))
+#define __cpu_to_be16s(x) __swab16s((x))
+#define __be16_to_cpus(x) __swab16s((x))
+#endif	// __constant_htonl
+
+#include <byteorder/generic.h>
+
+#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/byteorder/swab.h

@@ -0,0 +1,145 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef _LINUX_BYTEORDER_SWAB_H
+#define _LINUX_BYTEORDER_SWAB_H
+/*
+#if !defined(CONFIG_PLATFORM_MSTAR_TITANIA12) && 	!defined(PLATFORM_ECOS) && \
+		!defined(CONFIG_PLATFORM_8195A)
+*/
+#if !defined(CONFIG_PLATFORM_MSTAR_TITANIA12) && !defined(PLATFORM_ECOS)
+
+#if !defined(PLATFORM_FREERTOS) && !defined (PLATFORM_CMSIS_RTOS)
+#ifndef __u16
+typedef unsigned short __u16;
+#endif
+
+#ifndef __u32
+typedef unsigned int	__u32;
+#endif
+
+#ifndef __u8
+typedef unsigned char __u8;
+#endif
+
+#ifndef __u64
+typedef unsigned long long	__u64;	
+#endif
+#endif
+__inline static __u16  ___swab16(__u16 x)
+{
+	__u16 __x = x; 
+	return 
+	((__u16)( 
+		(((__u16)(__x) & (__u16)0x00ffU) << 8) |
+		(((__u16)(__x) & (__u16)0xff00U) >> 8) ));
+
+}
+
+__inline static __u32  ___swab32(__u32 x)
+{
+	__u32 __x = (x);
+	return ((__u32)(
+		(((__u32)(__x) & (__u32)0x000000ffUL) << 24) |
+		(((__u32)(__x) & (__u32)0x0000ff00UL) <<  8) |
+		(((__u32)(__x) & (__u32)0x00ff0000UL) >>  8) |
+		(((__u32)(__x) & (__u32)0xff000000UL) >> 24) ));
+}
+
+__inline static __u64  ___swab64(__u64 x)
+{
+	__u64 __x = (x);
+	
+	return 
+	((__u64)( \
+		(__u64)(((__u64)(__x) & (__u64)0x00000000000000ffULL) << 56) | \
+		(__u64)(((__u64)(__x) & (__u64)0x000000000000ff00ULL) << 40) | \
+		(__u64)(((__u64)(__x) & (__u64)0x0000000000ff0000ULL) << 24) | \
+		(__u64)(((__u64)(__x) & (__u64)0x00000000ff000000ULL) <<  8) | \
+	        (__u64)(((__u64)(__x) & (__u64)0x000000ff00000000ULL) >>  8) | \
+		(__u64)(((__u64)(__x) & (__u64)0x0000ff0000000000ULL) >> 24) | \
+		(__u64)(((__u64)(__x) & (__u64)0x00ff000000000000ULL) >> 40) | \
+		(__u64)(((__u64)(__x) & (__u64)0xff00000000000000ULL) >> 56) )); \
+}
+#endif // CONFIG_PLATFORM_MSTAR_TITANIA12
+
+#ifndef __arch__swab16
+__inline static __u16 __arch__swab16(__u16 x)
+{
+	return ___swab16(x);
+}
+
+#endif
+
+#ifndef __arch__swab32
+__inline static __u32 __arch__swab32(__u32 x)
+{
+	__u32 __tmp = (x) ; 
+	return ___swab32(__tmp);
+}
+#endif
+
+#ifndef __arch__swab64
+
+__inline static __u64 __arch__swab64(__u64 x)
+{
+	__u64 __tmp = (x) ; 
+	return ___swab64(__tmp);
+}
+
+
+#endif
+
+#ifndef __swab16
+#define __swab16(x) __fswab16(x)
+#define __swab32(x) __fswab32(x)
+#define __swab64(x) __fswab64(x)
+#endif	// __swab16
+
+#ifdef PLATFORM_FREEBSD
+__inline static __u16 __fswab16(__u16 x)
+#else
+__inline static __u16 __fswab16(__u16 x)
+#endif //PLATFORM_FREEBSD
+{
+	return __arch__swab16(x);
+}
+#ifdef PLATFORM_FREEBSD
+__inline static __u32 __fswab32(__u32 x)
+#else
+__inline static __u32 __fswab32(__u32 x)
+#endif //PLATFORM_FREEBSD
+{
+	return __arch__swab32(x);
+}
+
+#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS)
+#define swab16 __swab16
+#define swab32 __swab32
+#define swab64 __swab64
+#define swab16p __swab16p
+#define swab32p __swab32p
+#define swab64p __swab64p
+#define swab16s __swab16s
+#define swab32s __swab32s
+#define swab64s __swab64s
+#endif
+
+#endif /* _LINUX_BYTEORDER_SWAB_H */
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/drv_types.h

@@ -0,0 +1,863 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+/*-------------------------------------------------------------------------------
+
+	For type defines and data structure defines
+
+--------------------------------------------------------------------------------*/
+
+
+#ifndef __DRV_TYPES_H__
+#define __DRV_TYPES_H__
+
+#include <drv_conf.h>
+
+
+#ifdef PLATFORM_OS_XP
+#include <drv_types_xp.h>
+#endif
+
+#ifdef PLATFORM_OS_CE
+#include <drv_types_ce.h>
+#endif
+
+#ifdef PLATFORM_LINUX
+#include <drv_types_linux.h>
+#endif
+
+
+#if defined (__ICCARM__)
+#define _PACKED         __packed
+#define _WEAK           __weak
+#else
+#define _PACKED         __attribute__ ((packed))
+#define _WEAK           __attribute__ ((weak))
+#endif
+
+// Assign memory sectinon usage
+#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
+#include <section_config.h>
+//#include "rtl_utility_ram.h"
+#include "platform/platform_stdlib.h"
+#else
+#define SRAM_BD_DATA_SECTION
+#define WLAN_ROM_TEXT_SECTION
+#define WLAN_ROM_DATA_SECTION
+#define _LONG_CALL_     
+#endif
+
+#ifdef CONFIG_TRACE_SKB
+#define SKBLIST_ALL								0xFFFFFFFF
+// receive
+#define	SKBLIST_RECVBUF_MASK					0x0000000F
+#define	SKBLIST_RECVBUF							0x00000001
+#define	SKBLIST_RECVBUF_FREEQUEUE				0x00000002
+#define	SKBLIST_RECVBUF_PENDINGQUEUE			0x00000004
+
+#define	SKBLIST_RECVFRAME_MASK					0x000000F0
+#define	SKBLIST_RECVFRAME						0x00000010
+#define	SKBLIST_RECVFRAME_FREEQUEUE				0x00000020
+#define	SKBLIST_RECVFRAME_SWDECQUEUE			0x00000040
+#ifdef CONFIG_RECV_REORDERING_CTRL
+#define	SKBLIST_RECVFRAME_REORDERQUEUE			0x00000080
+#endif
+
+// transmit
+#define	SKBLIST_XMITBUF_MASK					0x0000FF00
+#define	SKBLIST_XMITBUF							0x00000100
+#define	SKBLIST_XMITEXTBUF						0x00000200
+#define	SKBLIST_XMITBUF_FREEQUEUE				0x00000400
+#define	SKBLIST_XMITEXTBUF_FREEQUEUE			0x00000800
+#define	SKBLIST_XMITBUF_PENDINGQUEUE			0x00001000
+#ifdef CONFIG_SDIO_TX_MULTI_QUEUE
+#define	SKBLIST_XMITBUF_PENDING0QUEUE			0x00002000
+#define	SKBLIST_XMITBUF_PENDING1QUEUE			0x00004000
+#define	SKBLIST_XMITBUF_PENDING2QUEUE			0x00008000
+#endif
+
+#define	SKBLIST_XMITFRAME_MASK					0x0FFF0000
+#define	SKBLIST_XMITFRAME						0x00010000
+#define	SKBLIST_XMITFRAME_FREEQUEUE				0x00020000
+#define	SKBLIST_XMITFRAME_SLEEPQUEUE			0x00040000
+#define	SKBLIST_XMITFRAME_VOQUEUE				0x00100000
+#define	SKBLIST_XMITFRAME_VIQUEUE				0x00200000
+#define	SKBLIST_XMITFRAME_BEQUEUE				0x00400000
+#define	SKBLIST_XMITFRAME_BKQUEUE				0x00800000
+#define	SKBLIST_XMITFRAME_BMQUEUE				0x01000000
+
+#define	SKBLIST_POOL							0x10000000
+#endif
+
+enum _NIC_VERSION {
+
+	RTL8711_NIC,
+	RTL8712_NIC,
+	RTL8713_NIC,
+	RTL8716_NIC
+
+};
+
+typedef struct _ADAPTER _adapter, ADAPTER,*PADAPTER;
+
+#include "wireless.h"
+#include <netdev.h>
+#include <osdep_service.h>
+#include <rtw_byteorder.h>
+#include <rtw_io.h>
+#include <hci_spec.h>
+
+#include <wifi.h>
+
+#ifdef CONFIG_80211N_HT
+#include <rtw_ht.h>
+#endif
+
+#include <wlan_basic_types.h>
+#include <rtw_intfs.h>
+//#include <hal_pg.h>
+#include <wlan_bssdef.h>
+#include <rtw_cmd.h>
+#include <rtw_xmit.h>
+#include <rtw_recv.h>
+#include <hal_com.h>
+#include <rtw_qos.h>
+#ifdef CONFIG_INCLUDE_WPA_PSK
+#include <rtw_psk.h>
+#endif
+#include <rtw_security.h>
+#include <rom_rtw_security.h>
+#include <rtw_pwrctrl.h>
+#include <rtw_eeprom.h>
+#include <sta_info.h>
+#include <rtw_mlme.h>
+#include <rtw_debug.h>
+#include <ieee80211.h>
+#include <rom_ieee80211.h>
+#include <rtw_ioctl_set.h>
+#include <rtw_rf.h>
+#include <rtw_event.h>
+#include <rtw_led.h>
+#include <rtw_mlme_ext.h>
+#ifdef CONFIG_P2P_NEW
+#include <rtw_p2p.h>
+#endif
+//#include <rtw_tdls.h>
+#include <rtw_ap.h>
+#include <rtw_efuse.h>
+
+#include <osdep_intf.h>
+
+#include <hci_intfs.h>
+
+#ifdef CONFIG_WAPI_SUPPORT
+#include <rtw_wapi.h>
+#endif
+
+#ifdef CONFIG_DRVEXT_MODULE
+#include <drvext_api.h>
+#endif
+
+#ifdef CONFIG_MP_INCLUDED
+#include <rtw_mp.h>
+#endif
+
+#ifdef CONFIG_BR_EXT
+#include <rtw_br_ext.h>
+#endif	// CONFIG_BR_EXT
+
+#ifdef CONFIG_IOCTL_CFG80211
+	#include "ioctl_cfg80211.h"
+#endif //CONFIG_IOCTL_CFG80211
+
+#define SPEC_DEV_ID_NONE BIT(0)
+#define SPEC_DEV_ID_DISABLE_HT BIT(1)
+#define SPEC_DEV_ID_ENABLE_PS BIT(2)
+#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3)
+#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4)
+#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5)
+
+struct specific_device_id{
+
+	u32		flags;
+
+	u16		idVendor;
+	u16		idProduct;
+
+};
+
+struct registry_priv
+{
+	u8	chip_version;
+//	u8	rfintfs;
+//	u8	lbkmode;
+	u8	hci;
+	NDIS_802_11_SSID	ssid;
+//	u8	network_mode;	//infra, ad-hoc, auto
+	u8	channel;//ad-hoc support requirement
+	u8	wireless_mode;//A, B, G, auto
+	u8 	scan_mode;//active, passive
+//	u8	radio_enable;
+//	u8	preamble;//long, short, auto
+	u8	vrtl_carrier_sense;//Enable, Disable, Auto
+	u8	vcs_type;//RTS/CTS, CTS-to-self
+	u16	rts_thresh;
+//	u8	adhoc_tx_pwr;
+	u8	soft_ap;
+	u8	power_mgnt;
+	u8 	ps_enable;
+	u8	ips_mode;
+	u8	smart_ps;
+//	u8	long_retry_lmt;
+//	u8	short_retry_lmt;
+//	u16	busy_thresh;
+//	u8	ack_policy;
+	u8	mp_mode;
+	u8	software_encrypt;
+	u8	software_decrypt;
+	#ifdef CONFIG_TX_EARLY_MODE
+	u8   	early_mode;
+	#endif
+	u8	acm_method;
+	  //UAPSD
+	u8	wmm_enable;
+	u8	uapsd_enable;
+//	u8	uapsd_max_sp;
+//	u8	uapsd_acbk_en;
+//	u8	uapsd_acbe_en;
+//	u8	uapsd_acvi_en;
+//	u8	uapsd_acvo_en;
+
+//	WLAN_BSSID_EX    dev_network;
+	u32  beacon_period;
+
+#ifdef CONFIG_80211N_HT
+	u8	ht_enable;
+#if !defined(NOT_SUPPORT_40M)
+	u8	cbw40_enable;
+#endif
+	u8	ampdu_enable;//for tx
+	u8 	rx_stbc;
+	u8	ampdu_amsdu;//A-MPDU Supports A-MSDU is permitted
+#endif
+	//u8	lowrate_two_xmit;
+
+	u8	rf_config ;
+//	u8	low_power ;
+	u8	power_percentage_idx;
+
+	u8	wifi_spec;// !turbo_mode
+
+	u8	channel_plan;
+#ifdef CONFIG_BT_COEXIST
+	u8	btcoex;
+	u8	bt_iso;
+	u8	bt_sco;
+	u8	bt_ampdu;
+#endif
+#if RX_AGGREGATION 
+	BOOLEAN	bAcceptAddbaReq;
+#endif
+//	u8	antdiv_cfg;
+//	u8	antdiv_type;
+
+#ifdef CONFIG_AUTOSUSPEND
+	u8	usbss_enable;//0:disable,1:enable
+#endif
+#ifdef SUPPORT_HW_RFOFF_DETECTED
+	u8	hwpdn_mode;//0:disable,1:enable,2:decide by EFUSE config
+	u8	hwpwrp_detect;//0:disable,1:enable
+#endif
+#ifdef CONFIG_SUPPORT_HW_WPS_PBC
+	u8	hw_wps_pbc;//0:disable,1:enable
+#endif
+
+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
+	char	adaptor_info_caching_file_path[PATH_LENGTH_MAX];
+#endif
+
+#ifdef CONFIG_LAYER2_ROAMING
+	u8	max_roaming_times; // the max number driver will try to roaming
+#endif
+
+#ifdef CONFIG_IOL
+	bool 	force_iol; //enable iol without other concern
+#endif
+
+#ifdef CONFIG_80211D
+	u8 	enable80211d;
+#endif
+
+	u8 	ifname[16];
+	u8 	if2name[16];
+	
+#if (RTW_NOTCH_FILTER != 0)
+	u8 	notch_filter;
+#endif
+
+#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
+	u8 	force_ant;//0 normal,1 main,2 aux
+	u8 	force_igi;//0 normal
+#endif
+
+	//define for tx power adjust
+	u8	RegEnableTxPowerLimit;
+	u8	RegEnableTxPowerByRate;
+#ifdef CONFIG_RF_GAIN_OFFSET
+	u8	RegEnableKFree;
+#endif
+	u8	RegPowerBase;
+	u8	RegPwrTblSel;
+
+	u8 adaptivity_en;
+	u8 adaptivity_mode;
+	u8 adaptivity_dml;
+	u8 adaptivity_dc_backoff;
+	s8 adaptivity_th_l2h_ini;
+//	u8 nhm_en;
+};
+
+//For registry parameters
+#define RGTRY_OFT(field) ((u32)FIELD_OFFSET(struct registry_priv,field))
+#define RGTRY_SZ(field)   sizeof(((struct registry_priv*) 0)->field)
+#define BSSID_OFT(field) ((u32)FIELD_OFFSET(WLAN_BSSID_EX,field))
+#define BSSID_SZ(field)   sizeof(((PWLAN_BSSID_EX) 0)->field)
+
+#define MAX_CONTINUAL_URB_ERR 4
+
+#ifdef CONFIG_CONCURRENT_MODE
+#define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER)
+#define get_iface_type(adapter) (adapter->iface_type)
+#else
+#define is_primary_adapter(adapter) (1)
+#define get_iface_type(adapter) (IFACE_PORT0)
+#endif
+
+enum _IFACE_TYPE {
+	IFACE_PORT0, //mapping to port0 for C/D series chips
+	IFACE_PORT1, //mapping to port1 for C/D series chip
+	MAX_IFACE_PORT,
+};
+
+enum _ADAPTER_TYPE {
+	PRIMARY_ADAPTER,
+	SECONDARY_ADAPTER,
+	MAX_ADAPTER,
+};
+
+struct dvobj_priv
+{
+	void *if1;
+#ifdef CONFIG_CONCURRENT_MODE	
+	void *if2;
+#endif
+
+	//For 92D, DMDP have 2 interface.
+	//u8	InterfaceNumber;
+	//u8	NumInterfaces;
+#ifdef CONFIG_CONCURRENT_MODE
+	void *padapters[MAX_IFACE_PORT];
+	u8 iface_nums; // total number of ifaces used runtime
+#endif
+	//In /Out Pipe information
+	//int	RtInPipe[2];
+	u8	RtOutPipe[3];//int	RtOutPipe[3];
+	u8	Queue2Pipe[HW_QUEUE_ENTRY];//for out pipe mapping
+
+	//u8	irq_alloc;
+
+/*-------- below is for SDIO INTERFACE --------*/
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	//
+	// SDIO ISR Related
+	//
+	u32 sdio_himr;
+
+	//
+	// SDIO Tx FIFO related.
+	//
+	// HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg
+	u8  SdioTxFIFOFreePage[TX_FREE_PG_QUEUE];
+	_lock SdioTxFIFOFreePageLock;
+
+	//
+	// SDIO Rx FIFO related.
+	//
+	u16 SdioRxFIFOSize;
+
+#ifdef INTF_DATA
+	INTF_DATA intf_data;
+#endif
+#endif //CONFIG_SDIO_HCI
+
+/*-------- below is for USB INTERFACE --------*/
+
+#ifdef CONFIG_USB_HCI
+
+	u8	irq_alloc; 
+	u8	nr_endpoint;
+	u8	ishighspeed;
+	u8	RtNumInPipes;
+	u8	RtNumOutPipes;
+	int	ep_num[5]; //endpoint number
+
+	int	RegUsbSS;
+
+	_sema	usb_suspend_sema;
+
+#ifdef CONFIG_USB_VENDOR_REQ_MUTEX
+	_mutex  usb_vendor_req_mutex;
+#endif
+
+#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
+	u8 * usb_alloc_vendor_req_buf;
+	u8 * usb_vendor_req_buf;
+#endif
+
+#ifdef PLATFORM_WINDOWS
+	//related device objects
+	PDEVICE_OBJECT	pphysdevobj;//pPhysDevObj;
+	PDEVICE_OBJECT	pfuncdevobj;//pFuncDevObj;
+	PDEVICE_OBJECT	pnextdevobj;//pNextDevObj;
+
+	u8	nextdevstacksz;//unsigned char NextDeviceStackSize;	//= (CHAR)CEdevice->pUsbDevObj->StackSize + 1;
+
+	//urb for control diescriptor request
+
+#ifdef PLATFORM_OS_XP
+	struct _URB_CONTROL_DESCRIPTOR_REQUEST descriptor_urb;
+	PUSB_CONFIGURATION_DESCRIPTOR	pconfig_descriptor;//UsbConfigurationDescriptor;
+#endif
+
+#ifdef PLATFORM_OS_CE
+	WCHAR			active_path[MAX_ACTIVE_REG_PATH];	// adapter regpath
+	USB_EXTENSION	usb_extension;
+
+	_nic_hdl		pipehdls_r8192c[0x10];
+#endif
+
+	u32	config_descriptor_len;//u32 UsbConfigurationDescriptorLength;
+#endif//PLATFORM_WINDOWS
+
+#ifdef PLATFORM_LINUX
+	struct usb_interface *pusbintf;
+	struct usb_device *pusbdev;
+#endif//PLATFORM_LINUX
+
+#ifdef PLATFORM_FREEBSD
+	struct usb_interface *pusbintf;
+	struct usb_device *pusbdev;
+#endif//PLATFORM_FREEBSD
+	ATOMIC_T continual_urb_error;
+#endif//CONFIG_USB_HCI
+
+/*-------- below is for PCIE INTERFACE --------*/
+
+#ifdef CONFIG_PCI_HCI
+	u8	irq_alloc; 
+
+#ifdef PLATFORM_LINUX
+	struct pci_dev *ppcidev;
+
+	//PCI MEM map
+	unsigned long	pci_mem_end;	/* shared mem end	*/
+	unsigned long	pci_mem_start;	/* shared mem start	*/
+
+	//PCI IO map
+	unsigned long	pci_base_addr;	/* device I/O address	*/
+
+	//PciBridge
+	struct pci_priv	pcipriv;
+
+	u16	irqline;
+	u8	irq_enabled;
+	RT_ISR_CONTENT	isr_content;
+	_lock	irq_th_lock;
+
+	//ASPM
+	u8	const_pci_aspm;
+	u8	const_amdpci_aspm;
+	u8	const_hwsw_rfoff_d3;
+	u8	const_support_pciaspm;
+	// pci-e bridge */
+	u8 	const_hostpci_aspm_setting;
+	// pci-e device */
+	u8 	const_devicepci_aspm_setting;
+	u8 	b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
+	u8	b_support_backdoor;
+	u8 bdma64;
+#endif//PLATFORM_LINUX
+
+#if defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
+	u8	irq_enabled;
+	_lock	irq_th_lock;
+#endif //PLATFORM_FREERTOS
+
+#endif//CONFIG_PCI_HCI
+
+#ifdef CONFIG_LX_HCI
+	u8	irq_alloc; 
+#if defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
+	u8	irq_enabled;
+	_lock	irq_th_lock;
+#endif //PLATFORM_FREERTOS
+#endif
+
+};
+
+#ifdef PLATFORM_LINUX
+static struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
+{
+	/* todo: get interface type from dvobj and the return the dev accordingly */
+#ifdef RTW_DVOBJ_CHIP_HW_TYPE
+#endif
+
+#ifdef CONFIG_USB_HCI
+	return &dvobj->pusbintf->dev;
+#endif
+#ifdef CONFIG_SDIO_HCI
+	return &dvobj->intf_data.func->dev;
+#endif
+#ifdef CONFIG_GSPI_HCI
+	return &dvobj->intf_data.func->dev;
+#endif
+#ifdef CONFIG_PCI_HCI
+	return &dvobj->ppcidev->dev;
+#endif
+}
+#endif
+
+#ifdef CONFIG_CONCURRENT_MODE
+struct co_data_priv{
+
+	//george@20120518
+	//current operating channel/bw/ch_offset
+	//save the correct ch/bw/ch_offset whatever the inputted values are
+	//when calling set_channel_bwmode() at concurrent mode
+	//for debug check or reporting to layer app (such as wpa_supplicant for nl80211)
+	u8 co_ch;
+	u8 co_bw;
+	u8 co_ch_offset;
+	u8 rsvd;
+
+};
+#endif //CONFIG_CONCURRENT_MODE
+
+typedef enum _DRIVER_STATE{
+	DRIVER_NORMAL = 0,
+	DRIVER_DISAPPEAR = 1,
+	DRIVER_REPLACE_DONGLE = 2,
+}DRIVER_STATE;
+
+#ifdef CONFIG_INTEL_PROXIM
+struct proxim {
+	bool proxim_support;
+	bool proxim_on;
+
+	void *proximity_priv;
+	int (*proxim_rx)(_adapter *padapter,
+		union recv_frame *precv_frame);
+	u8	(*proxim_get_var)(_adapter* padapter, u8 type);
+};
+#endif	//CONFIG_INTEL_PROXIM
+
+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
+typedef struct loopbackdata
+{
+	_sema	sema;
+	_thread_hdl_ lbkthread;
+	u8 bstop;
+	u32 cnt;
+	u16 size;
+	u16 txsize;
+	u8 txbuf[0x8000];
+	u16 rxsize;
+	u8 rxbuf[0x8000];
+	u8 msg[100];
+
+}LOOPBACKDATA, *PLOOPBACKDATA;
+#endif
+
+struct _ADAPTER{
+#ifdef CONFIG_EASY_REPLACEMENT
+	int	DriverState;// for disable driver using module, use dongle to replace module.
+	int	bDongle;//build-in module or external dongle
+
+#endif
+#ifdef PLATFORM_LINUX
+	int	pid[3];//process id from UI, 0:wps, 1:hostapd, 2:dhcpcd
+#endif	
+
+#ifdef CONFIG_PROC_DEBUG
+	u16 	chip_type;
+#endif
+
+	u16	HardwareType;
+	u16	interface_type;//USB,SDIO,SPI,PCI
+	u32	work_mode; //STA, AP, STA+AP, PROMISC, P2P
+
+	struct	dvobj_priv	*dvobj;
+	struct	mlme_priv	mlmepriv;
+	struct	mlme_ext_priv	mlmeextpriv;
+	struct	cmd_priv	cmdpriv;
+	struct	evt_priv	evtpriv;
+	//struct	io_queue	*pio_queue;
+	struct 	io_priv	iopriv;
+	struct	xmit_priv	xmitpriv;
+	struct	recv_priv	recvpriv;
+	struct	sta_priv	stapriv;
+	struct	security_priv	securitypriv;
+	struct	registry_priv	registrypriv;
+	struct	pwrctrl_priv	pwrctrlpriv;
+	struct 	eeprom_priv eeprompriv;
+//TODO
+//	struct	led_priv	ledpriv;
+
+
+#ifdef CONFIG_MP_INCLUDED
+       struct	mp_priv	mppriv;
+#endif
+
+#ifdef CONFIG_DRVEXT_MODULE
+	struct	drvext_priv	drvextpriv;
+#endif
+
+#if defined(CONFIG_HOSTAPD_MLME) && defined (CONFIG_AP_MODE)
+	struct	hostapd_priv	*phostapdpriv;
+#endif
+
+#ifdef CONFIG_IOCTL_CFG80211
+#ifdef CONFIG_P2P
+	struct cfg80211_wifidirect_info	cfg80211_wdinfo;
+#endif //CONFIG_P2P
+#endif //CONFIG_IOCTL_CFG80211
+
+#ifdef CONFIG_P2P_NEW
+	struct wifidirect_info	wdinfo;
+#endif //CONFIG_P2P
+
+#ifdef CONFIG_TDLS
+	struct tdls_info	tdlsinfo;
+#endif //CONFIG_TDLS
+
+#ifdef CONFIG_WAPI_SUPPORT
+	u8	WapiSupport;
+	RT_WAPI_T	wapiInfo;
+#endif
+
+
+#ifdef CONFIG_WFD
+	struct wifi_display_info wfd_info;
+#endif //CONFIG_WFD
+
+	PVOID		HalData;
+	u32 		hal_data_sz;
+	struct hal_ops	HalFunc;
+
+	s32	bDriverStopped;
+	s32	bSurpriseRemoved;
+	s32	bCardDisableWOHSM;
+	u8	RxStop;	//Used to stop rx thread as early as possible
+
+	u32	IsrContent;
+	u32	ImrContent;
+
+	u8	EepromAddressSize;
+	u8	hw_init_completed;
+	u8	bDriverIsGoingToUnload;
+	u8	init_adpt_in_progress;
+	u8	bMpDriver;
+
+#ifdef CONFIG_AP_MODE
+	u8	bForwardingDisabled;
+#endif
+
+#if defined(CONFIG_EVENT_THREAD_MODE)
+	_thread_hdl_	evtThread;
+#endif
+#if defined(CONFIG_ISR_THREAD_MODE_POLLING) || defined(CONFIG_ISR_THREAD_MODE_INTERRUPT)
+	struct task_struct	isrThread;
+#endif
+	struct task_struct	cmdThread;
+#ifdef CONFIG_XMIT_THREAD_MODE
+	struct task_struct	xmitThread;
+#endif
+#if defined(CONFIG_RECV_THREAD_MODE)
+	struct task_struct	recvThread;
+#endif
+#ifdef CONFIG_RECV_TASKLET_THREAD
+	struct task_struct	recvtasklet_thread;
+#endif
+#ifdef CONFIG_XMIT_TASKLET_THREAD
+#ifdef PLATFORM_LINUX
+	struct tasklet_struct xmit_tasklet;
+#else
+	struct task_struct	xmittasklet_thread;
+#endif
+#endif
+#ifdef CONFIG_SDIO_XMIT_THREAD
+	struct task_struct	SdioXmitThread;
+#endif //CONFIG_XMIT_TASKLET_THREAD
+
+
+#if !defined(PLATFORM_LINUX) && !defined(PLATFORM_ECOS) && !defined(PLATFORM_FREERTOS) && !defined(PLATFORM_CMSIS_RTOS)
+	NDIS_STATUS (*dvobj_init)(struct dvobj_priv *dvobj);
+	void (*dvobj_deinit)(struct dvobj_priv *dvobj);
+#endif
+
+	void (*intf_start)(_adapter * adapter);
+	void (*intf_stop)(_adapter * adapter);
+
+#ifdef PLATFORM_WINDOWS
+	_nic_hdl		hndis_adapter;//hNdisAdapter(NDISMiniportAdapterHandle);
+	_nic_hdl		hndis_config;//hNdisConfiguration;
+	NDIS_STRING fw_img;
+
+	u32	NdisPacketFilter;
+	u8	MCList[MAX_MCAST_LIST_NUM][6];
+	u32	MCAddrCount;
+#endif //end of PLATFORM_WINDOWS
+
+#ifdef PLATFORM_ECOS
+	_nic_hdl pnetdev;
+	int bup;
+	struct net_device_stats stats;
+#endif	//#ifdef PLATFORM_ECOS
+
+#if defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
+	_nic_hdl	pnetdev;
+	int		bup;
+	struct net_device_stats stats;
+#endif	//#ifdef PLATFORM_FREERTOS
+
+#ifdef PLATFORM_LINUX
+	_nic_hdl pnetdev;
+
+	// used by rtw_rereg_nd_name related function
+	struct rereg_nd_name_data {
+		_nic_hdl old_pnetdev;
+		char old_ifname[IFNAMSIZ];
+		u8 old_ips_mode;
+		u8 old_bRegUseLed;
+	} rereg_nd_name_priv;
+
+	int bup;
+	struct net_device_stats stats;
+	struct iw_statistics iwstats;
+	struct proc_dir_entry *dir_dev;// for proc directory
+
+#ifdef CONFIG_IOCTL_CFG80211
+	struct wireless_dev *rtw_wdev;
+#endif //CONFIG_IOCTL_CFG80211
+
+#endif //end of PLATFORM_LINUX
+
+#ifdef PLATFORM_FREEBSD
+	_nic_hdl pifp;
+	int bup;
+	_lock glock;
+#endif //PLATFORM_FREEBSD
+	u8 net_closed;
+
+	u8 bFWReady;
+	//u8 bBTFWReady;
+	//u8 bReadPortCancel;
+	//u8 bWritePortCancel;
+	u8 bLinkInfoDump;
+	u8 bRxRSSIDisplay;
+#ifdef CONFIG_AUTOSUSPEND
+	u8	bDisableAutosuspend;
+#endif
+
+	_adapter *pbuddy_adapter;
+
+	_mutex *hw_init_mutex;
+#if defined(CONFIG_CONCURRENT_MODE) 
+	u8 isprimary; //is primary adapter or not
+	u8 adapter_type;
+	u8 iface_type; //interface port type
+
+	//for global synchronization
+	_mutex *ph2c_fwcmd_mutex;
+	_mutex *psetch_mutex;
+	_mutex *psetbw_mutex;
+
+	struct co_data_priv *pcodatapriv;//data buffer shared among interfaces
+#endif
+
+#ifdef CONFIG_BR_EXT
+	_lock					br_ext_lock;
+	//unsigned int			macclone_completed;
+	struct nat25_network_db_entry	*nethash[NAT25_HASH_SIZE];
+	int				pppoe_connection_in_progress;
+	unsigned char			pppoe_addr[MACADDRLEN];
+	unsigned char			scdb_mac[MACADDRLEN];
+	unsigned char			scdb_ip[4];
+	struct nat25_network_db_entry	*scdb_entry;
+	unsigned char			br_mac[MACADDRLEN];
+	unsigned char			br_ip[4];
+
+	struct br_ext_info		ethBrExtInfo;
+#endif	// CONFIG_BR_EXT
+
+#ifdef CONFIG_INTEL_PROXIM
+	/* intel Proximity, should be alloc mem
+	 * in intel Proximity module and can only
+	 * be used in intel Proximity mode */
+	struct proxim proximity;
+#endif	//CONFIG_INTEL_PROXIM
+
+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
+	PLOOPBACKDATA ploopback;
+#endif
+
+        u8    fix_rate;
+#ifdef CONFIG_CAC_TEST
+	unsigned char     in_cta_test;
+#endif
+	/* This flag is used to dynamically enabling debug message if
+	  	certain sympton happen. Use iwpriv command to enable it */
+#if defined(CONFIG_DEBUG_DYNAMIC)	
+	u8	debug_level;
+#endif
+
+};
+
+#define adapter_to_dvobj(adapter) (adapter->dvobj)
+#define adapter_to_pwrctl(adapter) (&adapter->pwrctrlpriv)
+
+int rtw_handle_dualmac(_adapter *adapter, bool init);
+
+__inline static u8 *myid(struct eeprom_priv *peepriv)
+{
+	return (peepriv->mac_addr);
+}
+
+#if 0 //#if (CONFIG_LWIP_LAYER == 0)
+// For FPGA test program
+#define _htons(x) (x)
+#define _htons(x) (x)
+#define _htons(x) (x)
+#define _htons(x) (x)
+#endif
+
+//fast reconnection function prototype
+typedef int (*init_done_ptr)(void);
+#endif //__DRV_TYPES_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/ethernet.h

@@ -0,0 +1,42 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+/*! \file */ 
+#ifndef __INC_ETHERNET_H
+#define __INC_ETHERNET_H
+
+#define ETHERNET_ADDRESS_LENGTH				6		//!< Ethernet Address Length
+#define ETHERNET_HEADER_SIZE				14		//!< Ethernet Header Length
+#define LLC_HEADER_SIZE						6		//!< LLC Header Length
+#define TYPE_LENGTH_FIELD_SIZE				2		//!< Type/Length Size
+#define MINIMUM_ETHERNET_PACKET_SIZE		60		//!< Minimum Ethernet Packet Size
+#define MAXIMUM_ETHERNET_PACKET_SIZE		1514	//!< Maximum Ethernet Packet Size
+
+#define RT_ETH_IS_MULTICAST(_pAddr)	((((u8 *)(_pAddr))[0]&0x01)!=0)		//!< Is Multicast Address?
+#define RT_ETH_IS_BROADCAST(_pAddr)	(										\
+											((u8 *)(_pAddr))[0]==0xff	&& 		\
+											((u8 *)(_pAddr))[1]==0xff	&&		\
+											((u8 *)(_pAddr))[2]==0xff	&&		\
+											((u8 *)(_pAddr))[3]==0xff	&&		\
+											((u8 *)(_pAddr))[4]==0xff	&&		\
+											((u8 *)(_pAddr))[5]==0xff		)	//!< Is Broadcast Address?
+
+
+#endif // #ifndef __INC_ETHERNET_H
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_com.h

@@ -0,0 +1,287 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __HAL_COMMON_H__
+#define __HAL_COMMON_H__
+
+#include "HalVerDef.h"
+#include "hal_pg.h"
+#include "hal_intf.h"
+#include "hal_phy.h"
+#include "hal_phy_reg.h"
+#include "hal_com_reg.h"
+#include "hal_com_phycfg.h"
+
+//----------------------------------------------------------------------------
+//       Rate Definition
+//----------------------------------------------------------------------------
+//CCK
+#define	RATR_1M					0x00000001
+#define	RATR_2M					0x00000002
+#define	RATR_55M					0x00000004
+#define	RATR_11M					0x00000008
+//OFDM 		
+#define	RATR_6M					0x00000010
+#define	RATR_9M					0x00000020
+#define	RATR_12M					0x00000040
+#define	RATR_18M					0x00000080
+#define	RATR_24M					0x00000100
+#define	RATR_36M					0x00000200
+#define	RATR_48M					0x00000400
+#define	RATR_54M					0x00000800
+//MCS 1 Spatial Stream	
+#define	RATR_MCS0					0x00001000
+#define	RATR_MCS1					0x00002000
+#define	RATR_MCS2					0x00004000
+#define	RATR_MCS3					0x00008000
+#define	RATR_MCS4					0x00010000
+#define	RATR_MCS5					0x00020000
+#define	RATR_MCS6					0x00040000
+#define	RATR_MCS7					0x00080000
+//MCS 2 Spatial Stream
+#define	RATR_MCS8					0x00100000
+#define	RATR_MCS9					0x00200000
+#define	RATR_MCS10					0x00400000
+#define	RATR_MCS11					0x00800000
+#define	RATR_MCS12					0x01000000
+#define	RATR_MCS13					0x02000000
+#define	RATR_MCS14					0x04000000
+#define	RATR_MCS15					0x08000000
+
+//CCK
+#define RATE_1M						BIT(0)
+#define RATE_2M						BIT(1)
+#define RATE_5_5M					BIT(2)
+#define RATE_11M					BIT(3)
+//OFDM 
+#define RATE_6M						BIT(4)
+#define RATE_9M						BIT(5)
+#define RATE_12M					BIT(6)
+#define RATE_18M					BIT(7)
+#define RATE_24M					BIT(8)
+#define RATE_36M					BIT(9)
+#define RATE_48M					BIT(10)
+#define RATE_54M					BIT(11)
+//MCS 1 Spatial Stream
+#define RATE_MCS0					BIT(12)
+#define RATE_MCS1					BIT(13)
+#define RATE_MCS2					BIT(14)
+#define RATE_MCS3					BIT(15)
+#define RATE_MCS4					BIT(16)
+#define RATE_MCS5					BIT(17)
+#define RATE_MCS6					BIT(18)
+#define RATE_MCS7					BIT(19)
+//MCS 2 Spatial Stream
+#define RATE_MCS8					BIT(20)
+#define RATE_MCS9					BIT(21)
+#define RATE_MCS10					BIT(22)
+#define RATE_MCS11					BIT(23)
+#define RATE_MCS12					BIT(24)
+#define RATE_MCS13					BIT(25)
+#define RATE_MCS14					BIT(26)
+#define RATE_MCS15					BIT(27)
+
+// ALL CCK Rate
+#define	RATE_ALL_CCK				RATR_1M|RATR_2M|RATR_55M|RATR_11M 
+#define	RATE_ALL_OFDM_AG			RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\
+									RATR_36M|RATR_48M|RATR_54M	
+#define	RATE_ALL_OFDM_1SS			RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\
+									RATR_MCS4|RATR_MCS5|RATR_MCS6	|RATR_MCS7	
+#define	RATE_ALL_OFDM_2SS			RATR_MCS8|RATR_MCS9	|RATR_MCS10|RATR_MCS11|\
+									RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
+
+/*------------------------------ Tx Desc definition Macro ------------------------*/ 
+//#pragma mark -- Tx Desc related definition. --
+//----------------------------------------------------------------------------
+//-----------------------------------------------------------
+//	Rate
+//-----------------------------------------------------------
+// CCK Rates, TxHT = 0
+#define DESC_RATE1M				0x00
+#define DESC_RATE2M				0x01
+#define DESC_RATE5_5M				0x02
+#define DESC_RATE11M				0x03
+
+// OFDM Rates, TxHT = 0
+#define DESC_RATE6M				0x04
+#define DESC_RATE9M				0x05
+#define DESC_RATE12M				0x06
+#define DESC_RATE18M				0x07
+#define DESC_RATE24M				0x08
+#define DESC_RATE36M				0x09
+#define DESC_RATE48M				0x0a
+#define DESC_RATE54M				0x0b
+
+// MCS Rates, TxHT = 1
+#define DESC_RATEMCS0				0x0c
+#define DESC_RATEMCS1				0x0d
+#define DESC_RATEMCS2				0x0e
+#define DESC_RATEMCS3				0x0f
+#define DESC_RATEMCS4				0x10
+#define DESC_RATEMCS5				0x11
+#define DESC_RATEMCS6				0x12
+#define DESC_RATEMCS7				0x13
+#define DESC_RATEMCS8				0x14
+#define DESC_RATEMCS9				0x15
+#define DESC_RATEMCS10				0x16
+#define DESC_RATEMCS11				0x17
+#define DESC_RATEMCS12				0x18
+#define DESC_RATEMCS13				0x19
+#define DESC_RATEMCS14				0x1a
+#define DESC_RATEMCS15				0x1b
+#define DESC_RATEMCS16				0x1C
+#define DESC_RATEMCS17				0x1D
+#define DESC_RATEMCS18				0x1E
+#define DESC_RATEMCS19				0x1F
+#define DESC_RATEMCS20				0x20
+#define DESC_RATEMCS21				0x21
+#define DESC_RATEMCS22				0x22
+#define DESC_RATEMCS23				0x23
+#define DESC_RATEMCS24				0x24
+#define DESC_RATEMCS25				0x25
+#define DESC_RATEMCS26				0x26
+#define DESC_RATEMCS27				0x27
+#define DESC_RATEMCS28				0x28
+#define DESC_RATEMCS29				0x29
+#define DESC_RATEMCS30				0x2A
+#define DESC_RATEMCS31				0x2B
+
+#define DESC_RATEVHTSS1MCS0		0x2c
+#define DESC_RATEVHTSS1MCS1		0x2d
+#define DESC_RATEVHTSS1MCS2		0x2e
+#define DESC_RATEVHTSS1MCS3		0x2f
+#define DESC_RATEVHTSS1MCS4		0x30
+#define DESC_RATEVHTSS1MCS5		0x31
+#define DESC_RATEVHTSS1MCS6		0x32
+#define DESC_RATEVHTSS1MCS7		0x33
+#define DESC_RATEVHTSS1MCS8		0x34
+#define DESC_RATEVHTSS1MCS9		0x35
+#define DESC_RATEVHTSS2MCS0		0x36
+#define DESC_RATEVHTSS2MCS1		0x37
+#define DESC_RATEVHTSS2MCS2		0x38
+#define DESC_RATEVHTSS2MCS3		0x39
+#define DESC_RATEVHTSS2MCS4		0x3a
+#define DESC_RATEVHTSS2MCS5		0x3b
+#define DESC_RATEVHTSS2MCS6		0x3c
+#define DESC_RATEVHTSS2MCS7		0x3d
+#define DESC_RATEVHTSS2MCS8		0x3e
+#define DESC_RATEVHTSS2MCS9		0x3f
+#define DESC_RATEVHTSS3MCS0		0x40
+#define DESC_RATEVHTSS3MCS1		0x41
+#define DESC_RATEVHTSS3MCS2		0x42
+#define DESC_RATEVHTSS3MCS3		0x43
+#define DESC_RATEVHTSS3MCS4		0x44
+#define DESC_RATEVHTSS3MCS5		0x45
+#define DESC_RATEVHTSS3MCS6		0x46
+#define DESC_RATEVHTSS3MCS7		0x47
+#define DESC_RATEVHTSS3MCS8		0x48
+#define DESC_RATEVHTSS3MCS9		0x49
+#define DESC_RATEVHTSS4MCS0		0x4A
+#define DESC_RATEVHTSS4MCS1		0x4B
+#define DESC_RATEVHTSS4MCS2		0x4C
+#define DESC_RATEVHTSS4MCS3		0x4D
+#define DESC_RATEVHTSS4MCS4		0x4E
+#define DESC_RATEVHTSS4MCS5		0x4F
+#define DESC_RATEVHTSS4MCS6		0x50
+#define DESC_RATEVHTSS4MCS7		0x51
+#define DESC_RATEVHTSS4MCS8		0x52
+#define DESC_RATEVHTSS4MCS9		0x53
+										
+typedef enum _FIRMWARE_SOURCE {
+	FW_SOURCE_IMG_FILE = 0,
+	FW_SOURCE_HEADER_FILE = 1,		//from header file
+} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
+
+// BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
+//#define MAX_TX_QUEUE		9
+
+#define TX_SELE_HQ			BIT(0)		// High Queue
+#define TX_SELE_LQ			BIT(1)		// Low Queue
+#define TX_SELE_NQ			BIT(2)		// Normal Queue
+#define TX_SELE_EQ			BIT(3)		// Extern Queue
+
+#define PageNum_128(_Len)		(u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
+#define PageNum_256(_Len)		(u32)(((_Len)>>8) + ((_Len)&0xFF ? 1:0))
+#define PageNum_512(_Len)		(u32)(((_Len)>>9) + ((_Len)&0x1FF ? 1:0))
+#define PageNum(_Len, _Size)		(u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1:0))
+
+#define	DYNAMIC_FUNC_DISABLE		(0x0)
+#define DYNAMIC_ALL_FUNC_ENABLE		0xFFFFFFF
+
+void dump_chip_info(HAL_VERSION	ChipVersion);
+
+
+u8	//return the final channel plan decision
+hal_com_get_channel_plan(
+	IN	PADAPTER	padapter,
+	IN	u8			hw_channel_plan,	//channel plan from HW (efuse/eeprom)
+	IN	u8			sw_channel_plan,	//channel plan from SW (registry/module param)
+	IN	u8			def_channel_plan,	//channel plan used when the former two is invalid
+	IN	BOOLEAN		AutoLoadFail
+	);
+
+u8	MRateToHwRate(u8 rate);
+
+void	HalSetBrateCfg(
+	IN PADAPTER		Adapter,
+	IN u8			*mBratesOS,
+	OUT u16			*pBrateCfg);
+
+BOOLEAN
+Hal_MappingOutPipe(
+	IN	PADAPTER	pAdapter,
+	IN	u8		NumOutPipe
+	);
+
+BOOLEAN
+HAL_IsLegalChannel(
+	IN	_adapter *	Adapter,
+	IN	u32			Channel
+	);
+
+void hal_init_macaddr(_adapter *adapter);
+void SetHwReg(PADAPTER padapter, u8 variable, u8 *val);
+void GetHwReg(PADAPTER padapter, u8 variable, u8 *val);
+
+#if defined (CONFIG_RTL8188F) || defined (CONFIG_RTL8711B)
+typedef enum _RT_MEDIA_STATUS {
+	RT_MEDIA_DISCONNECT = 0,
+	RT_MEDIA_CONNECT       = 1
+} RT_MEDIA_STATUS;
+
+
+void GetHalODMVar(	
+	PADAPTER				Adapter,
+	HAL_ODM_VARIABLE		eVariable,
+	PVOID					pValue1,
+	PVOID					pValue2);
+
+void SetHalODMVar(
+	PADAPTER				Adapter,
+	HAL_ODM_VARIABLE		eVariable,
+	PVOID					pValue1,
+	BOOLEAN					bSet);
+
+u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
+u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
+void rtw_hal_wow_enable(_adapter *adapter);
+void rtw_hal_wow_disable(_adapter *adapter);
+#endif
+#endif //__HAL_COMMON_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_com_phycfg.h

@@ -0,0 +1,288 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __HAL_COM_PHYCFG_H__
+#define __HAL_COM_PHYCFG_H__
+
+#define		PathA                     			0x0	// Useless
+#define		PathB                     			0x1
+#define		PathC                     			0x2
+#define		PathD                     			0x3
+
+typedef enum _RATE_SECTION {
+	CCK = 0,
+	OFDM,
+	HT_MCS0_MCS7,
+	HT_MCS8_MCS15,
+	HT_MCS16_MCS23,
+	HT_MCS24_MCS31,
+	VHT_1SSMCS0_1SSMCS9,
+	VHT_2SSMCS0_2SSMCS9,
+	VHT_3SSMCS0_3SSMCS9,
+	VHT_4SSMCS0_4SSMCS9,
+} RATE_SECTION;
+
+typedef enum _RF_TX_NUM {
+	RF_1TX = 0,
+	RF_2TX,
+	RF_3TX,
+	RF_4TX,
+	RF_MAX_TX_NUM,
+	RF_TX_NUM_NONIMPLEMENT,
+} RF_TX_NUM;
+
+#define MAX_POWER_INDEX 		0x3F
+
+typedef enum _REGULATION_TXPWR_LMT {
+	TXPWR_LMT_FCC = 0,
+	TXPWR_LMT_MKK = 1,
+	TXPWR_LMT_ETSI = 2,
+	TXPWR_LMT_WW = 3, // WW13, The mininum of ETSI,MKK
+	TXPWR_LMT_GL = 4, // Global, The mininum of ETSI,MKK,FCC
+	TXPWR_LMT_MAX_REGULATION_NUM = 5
+} REGULATION_TXPWR_LMT;
+
+/*------------------------------Define structure----------------------------*/ 
+typedef struct _BB_REGISTER_DEFINITION{
+	u32 rfintfs;			// set software control: 
+						//		0x870~0x877[8 bytes]
+							
+	u32 rfintfo; 			// output data: 
+						//		0x860~0x86f [16 bytes]
+							
+	u32 rfintfe; 			// output enable: 
+						//		0x860~0x86f [16 bytes]
+							
+	u32 rf3wireOffset;	// LSSI data:
+						//		0x840~0x84f [16 bytes]
+
+	u32 rfHSSIPara2; 	// wire parameter control2 : 
+						//		0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
+								
+	u32 rfLSSIReadBack; 	//LSSI RF readback data SI mode
+						//		0x8a0~0x8af [16 bytes]
+
+	u32 rfLSSIReadBackPi; 	//LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
+
+}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
+
+
+//----------------------------------------------------------------------
+s32
+phy_TxPwrIdxToDbm(
+	IN	PADAPTER		Adapter,
+	IN	WIRELESS_MODE	WirelessMode,
+	IN	u8				TxPwrIdx	
+	);
+
+u8
+PHY_GetTxPowerByRateBase(
+	IN	PADAPTER		Adapter,
+	IN	u8				Band,
+	IN	u8				RfPath,
+	IN	u8				TxNum,
+	IN	RATE_SECTION	RateSection
+	);
+
+u8
+PHY_GetRateSectionIndexOfTxPowerByRate(
+	IN	PADAPTER	pAdapter,
+	IN	u32			RegAddr,
+	IN	u32			BitMask
+	);
+
+VOID
+PHY_GetRateValuesOfTxPowerByRate(
+	IN	PADAPTER	pAdapter,
+	IN	u32			RegAddr,
+	IN	u32			BitMask,
+	IN	u32			Value,
+	OUT	u8*			RateIndex,
+	OUT	s8*			PwrByRateVal,
+	OUT	u8*			RateNum
+	);
+
+u8
+PHY_GetRateIndexOfTxPowerByRate(
+	IN	u8	Rate
+	);
+
+VOID 
+PHY_SetTxPowerIndexByRateSection(
+	IN	PADAPTER		pAdapter,
+	IN	u8				RFPath,	
+	IN	u8				Channel,
+	IN	u8				RateSection
+	);
+
+s8
+PHY_GetTxPowerByRate( 
+	IN	PADAPTER	pAdapter, 
+	IN	u8			Band, 
+	IN	u8			RFPath, 
+	IN	u8			TxNum, 
+	IN	u8			RateIndex
+	);
+
+VOID
+PHY_SetTxPowerByRate( 
+	IN	PADAPTER	pAdapter, 
+	IN	u8			Band, 
+	IN	u8			RFPath, 
+	IN	u8			TxNum, 
+	IN	u8			Rate,
+	IN	s8			Value
+	);
+
+VOID
+PHY_SetTxPowerLevelByPath(
+	IN	PADAPTER	Adapter,
+	IN	u8			channel,
+	IN	u8			path
+	);
+
+VOID 
+PHY_SetTxPowerIndexByRateArray(
+	IN	PADAPTER		pAdapter,
+	IN	u8				RFPath,
+	IN	CHANNEL_WIDTH	BandWidth,	
+	IN	u8				Channel,
+	IN	u8*				Rates,
+	IN	u8				RateArraySize
+	);
+
+VOID
+PHY_InitTxPowerByRate(
+	IN	PADAPTER	pAdapter
+	);
+
+VOID
+PHY_StoreTxPowerByRate(
+	IN	PADAPTER	pAdapter,
+	IN	u32			Band,
+	IN	u32			RfPath,
+	IN	u32			TxNum,
+	IN	u32			RegAddr,
+	IN	u32			BitMask,
+	IN	u32			Data
+	);
+
+VOID
+PHY_TxPowerByRateConfiguration(
+	IN  PADAPTER			pAdapter
+	);
+
+u8
+PHY_GetTxPowerIndexBase(
+	IN	PADAPTER		pAdapter,
+	IN	u8				RFPath,
+	IN	u8				Rate,	
+	IN	CHANNEL_WIDTH	BandWidth,	
+	IN	u8				Channel,
+	OUT PBOOLEAN		bIn24G
+	);
+
+s8
+PHY_GetTxPowerLimit(
+	IN	PADAPTER		Adapter,
+	IN	u32				RegPwrTblSel,
+	IN	BAND_TYPE		Band,
+	IN	CHANNEL_WIDTH	Bandwidth,
+	IN	u8				RfPath,
+	IN	u8				DataRate,
+	IN	u8				Channel
+	);
+
+VOID
+PHY_SetTxPowerLimit(
+	IN	PADAPTER			Adapter,
+	IN	u8					Regulation,
+	IN	u8					Band,
+	IN	u8					Bandwidth,
+	IN	u8					RateSection,
+	IN	u8					RfPath,
+	IN	u8					Channel,
+	IN	u8					PowerLimit
+	);
+
+VOID 
+PHY_ConvertTxPowerLimitToPowerIndex(
+	IN	PADAPTER			Adapter
+	);
+
+VOID
+PHY_InitTxPowerLimit(
+	IN	PADAPTER			Adapter
+	);
+
+s8
+PHY_GetTxPowerTrackingOffset( 
+	PADAPTER	pAdapter,
+	u8			Rate,
+	u8			RFPath
+	);
+
+u8
+PHY_GetTxPowerIndex(
+	IN	PADAPTER			pAdapter,
+	IN	u8					RFPath,
+	IN	u8					Rate,	
+	IN	CHANNEL_WIDTH		BandWidth,	
+	IN	u8					Channel
+	);
+
+VOID
+PHY_SetTxPowerIndex(
+	IN	PADAPTER		pAdapter,
+	IN	u32				PowerIndex,
+	IN	u8				RFPath,	
+	IN	u8				Rate
+	);
+
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+#define MAX_PARA_FILE_BUF_LEN	25600
+
+#define LOAD_MAC_PARA_FILE				BIT0
+#define LOAD_BB_PARA_FILE					BIT1
+#define LOAD_BB_PG_PARA_FILE				BIT2
+#define LOAD_BB_MP_PARA_FILE				BIT3
+#define LOAD_RF_PARA_FILE					BIT4
+#define LOAD_RF_TXPWR_TRACK_PARA_FILE	BIT5
+#define LOAD_RF_TXPWR_LMT_PARA_FILE		BIT6
+
+int phy_ConfigMACWithParaFile(IN PADAPTER	Adapter, IN char*	pFileName);
+
+int phy_ConfigBBWithParaFile(IN PADAPTER	Adapter, IN char*	pFileName, IN u32	ConfigType);
+
+int phy_ConfigBBWithPgParaFile(IN PADAPTER	Adapter, IN char*	pFileName);
+
+int phy_ConfigBBWithMpParaFile(IN PADAPTER	Adapter, IN char*	pFileName);
+
+int PHY_ConfigRFWithParaFile(IN	PADAPTER	Adapter, IN char*	pFileName, IN u8	eRFPath);
+
+int PHY_ConfigRFWithTxPwrTrackParaFile(IN PADAPTER	Adapter, IN char*	pFileName);
+
+int PHY_ConfigRFWithPowerLimitTableParaFile(IN PADAPTER	Adapter, IN char*	pFileName);
+
+void phy_free_filebuf(_adapter *padapter);
+#endif //CONFIG_LOAD_PHY_PARA_FROM_FILE
+
+
+#endif //__HAL_COMMON_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_intf.h

@@ -0,0 +1,666 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __HAL_INTF_H__
+#define __HAL_INTF_H__
+
+enum RTL871X_HCI_TYPE {
+	RTW_PCIE	= BIT0,
+	RTW_USB 	= BIT1,
+	RTW_SDIO	= BIT2,
+	RTW_GSPI	= BIT3,
+	RTW_LXBUS	= BIT4,
+};
+
+enum _CHIP_TYPE {
+
+	NULL_CHIP_TYPE,	
+	RTL8188C_8192C,
+	RTL8192D,
+	RTL8723A,
+	RTL8188E,
+	RTL8192E,
+	RTL8812,
+	RTL8821, //RTL8811
+	RTL8723B,
+	RTL8195A_SOC,
+	RTL8711B_SOC,
+	RTL8188F,
+	MAX_CHIP_TYPE
+};
+
+
+typedef enum _HW_VARIABLES{
+	HW_VAR_MEDIA_STATUS,
+	HW_VAR_MEDIA_STATUS1,
+	HW_VAR_SET_OPMODE,
+	HW_VAR_MAC_ADDR,
+	HW_VAR_BSSID,
+	HW_VAR_INIT_RTS_RATE,
+	HW_VAR_BASIC_RATE,
+	HW_VAR_TXPAUSE,
+	HW_VAR_BCN_FUNC,
+	HW_VAR_CORRECT_TSF,
+	HW_VAR_CHECK_BSSID,
+	HW_VAR_MLME_DISCONNECT,
+	HW_VAR_MLME_SITESURVEY,
+	HW_VAR_MLME_JOIN,
+	HW_VAR_ON_RCR_AM,
+	HW_VAR_OFF_RCR_AM,
+	HW_VAR_BEACON_INTERVAL,
+	HW_VAR_SLOT_TIME,
+	HW_VAR_RESP_SIFS,
+	HW_VAR_ACK_PREAMBLE,
+	HW_VAR_SEC_CFG,
+	HW_VAR_SEC_DK_CFG,
+#if !defined(CONFIG_LX_HCI)
+	HW_VAR_BCN_VALID,
+#endif
+	HW_VAR_RF_TYPE,
+	HW_VAR_DM_FLAG,
+	HW_VAR_DM_FUNC_OP,
+	HW_VAR_DM_FUNC_SET,
+	HW_VAR_DM_FUNC_CLR,
+	HW_VAR_CAM_EMPTY_ENTRY,
+	HW_VAR_CAM_INVALID_ALL,
+	HW_VAR_CAM_WRITE,
+	HW_VAR_CAM_READ,
+	HW_VAR_AC_PARAM_VO,
+	HW_VAR_AC_PARAM_VI,
+	HW_VAR_AC_PARAM_BE,
+	HW_VAR_AC_PARAM_BK,
+	HW_VAR_ACM_CTRL,
+	HW_VAR_AMPDU_MIN_SPACE,
+	HW_VAR_AMPDU_FACTOR,
+	HW_VAR_RXDMA_AGG_PG_TH,
+	HW_VAR_SET_RPWM,
+	HW_VAR_GET_RPWM,
+	HW_VAR_CPWM,
+	HW_VAR_H2C_FW_PWRMODE,
+	HW_VAR_H2C_PS_TUNE_PARAM,
+	HW_VAR_H2C_FW_JOINBSSRPT,
+	HW_VAR_FWLPS_RF_ON,
+	HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
+	HW_VAR_TDLS_WRCR,
+	HW_VAR_TDLS_INIT_CH_SEN,
+	HW_VAR_TDLS_RS_RCR,
+	HW_VAR_TDLS_DONE_CH_SEN,
+	HW_VAR_INITIAL_GAIN,
+	HW_VAR_TRIGGER_GPIO_0,
+#if !defined(NOT_SUPPORT_BT)
+	HW_VAR_BT_SET_COEXIST,
+	HW_VAR_BT_ISSUE_DELBA,	
+#endif
+	HW_VAR_CURRENT_ANTENNA,
+	HW_VAR_ANTENNA_DIVERSITY_LINK,
+	HW_VAR_ANTENNA_DIVERSITY_SELECT,
+	HW_VAR_SWITCH_EPHY_WoWLAN,
+	HW_VAR_EFUSE_USAGE,
+	HW_VAR_EFUSE_BYTES,
+#if !defined(NOT_SUPPORT_BT)
+	HW_VAR_EFUSE_BT_USAGE,
+	HW_VAR_EFUSE_BT_BYTES,
+#endif
+	HW_VAR_FIFO_CLEARN_UP,
+	HW_VAR_RESTORE_HW_SEQ,
+	HW_VAR_HCI_SUS_STATE,
+	HW_VAR_CHECK_TXBUF,
+	HW_VAR_APFM_ON_MAC, //Auto FSM to Turn On, include clock, isolation, power control for MAC only
+	// The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it.
+	// Unit in microsecond. 0 means disable this function.
+#ifdef CONFIG_WOWLAN
+	HW_VAR_WOWLAN,
+	HW_VAR_WAKEUP_REASON,
+	HW_VAR_RPWM_TOG,
+#endif
+#ifdef CONFIG_GPIO_WAKEUP
+	HW_SET_GPIO_WL_CTRL,
+#endif
+	HW_VAR_NAV_UPPER,
+	HW_VAR_C2H_HANDLE,
+	HW_VAR_RPT_TIMER_SETTING,
+	HW_VAR_TX_RPT_MAX_MACID,	
+	HW_VAR_H2C_MEDIA_STATUS_RPT,
+	HW_VAR_CHK_HI_QUEUE_EMPTY,
+	HW_VAR_DL_BCN_SEL,
+	HW_VAR_PORT_SWITCH,
+//	HW_VAR_DO_IQK,
+	HW_VAR_DM_IN_LPS,
+	HW_VAR_SET_REQ_FW_PS,
+	HW_VAR_FW_PS_STATE,
+	HW_VAR_DL_RSVD_PAGE,
+	HW_VAR_MACID_SLEEP,
+	HW_VAR_MACID_WAKEUP,
+	HW_VAR_DUMP_MAC_QUEUE_INFO,
+	HW_VAR_ASIX_IOT,
+#ifdef CONFIG_PROMISC
+	HW_VAR_PROMISC,
+#endif
+}HW_VARIABLES;
+
+typedef enum _HAL_DEF_VARIABLE{
+	HAL_DEF_UNDERCORATEDSMOOTHEDPWDB,
+	HAL_DEF_IS_SUPPORT_ANT_DIV,
+	HAL_DEF_CURRENT_ANTENNA,
+	HAL_DEF_DRVINFO_SZ,
+	HAL_DEF_MAX_RECVBUF_SZ,
+	HAL_DEF_RX_PACKET_OFFSET,
+//	HAL_DEF_DBG_DUMP_RXPKT,//for dbg
+	HAL_DEF_RX_DMA_SZ_WOW,
+	HAL_DEF_RX_DMA_SZ,
+	HAL_DEF_RX_PAGE_SIZE,
+	HAL_DEF_DBG_DM_FUNC,//for dbg
+	HAL_DEF_RA_DECISION_RATE,
+	HAL_DEF_RA_SGI,
+	HAL_DEF_PT_PWR_STATUS,
+	HW_VAR_MAX_RX_AMPDU_FACTOR,
+	HW_DEF_RA_INFO_DUMP,
+	HAL_DEF_DBG_DUMP_TXPKT,
+	HW_DEF_ODM_DBG_FLAG,
+	HW_DEF_ODM_DBG_LEVEL,
+	HAL_DEF_TX_PAGE_SIZE,
+	HAL_DEF_TX_PAGE_BOUNDARY,
+	HAL_DEF_MACID_SLEEP, // Support for MACID sleep
+	HAL_DEF_DBG_RX_INFO_DUMP,
+}HAL_DEF_VARIABLE;
+
+typedef enum _HAL_ODM_VARIABLE{
+	HAL_ODM_STA_INFO,	
+//	HAL_ODM_P2P_STATE,
+//	HAL_ODM_WIFI_DISPLAY_STATE,
+	HAL_ODM_DBG_FLAG,
+//	HAL_ODM_DBG_LEVEL,
+	HAL_ODM_RX_INFO_DUMP,
+	HAL_ODM_NOISE_MONITOR,
+	HAL_ODM_REGULATION,
+}HAL_ODM_VARIABLE;
+
+typedef enum _HAL_INTF_PS_FUNC{
+	HAL_USB_SELECT_SUSPEND,
+	HAL_MAX_ID,
+}HAL_INTF_PS_FUNC;
+
+typedef s32 (*c2h_id_filter)(u8 *c2h_evt);
+
+struct hal_ops {
+	u32	(*hal_power_on)(_adapter *padapter);
+	u32	(*hal_init)(_adapter *padapter);
+	u32	(*hal_deinit)(_adapter *padapter);
+
+	void	(*free_hal_data)(_adapter *padapter);
+
+	u32	(*inirp_init)(_adapter *padapter);
+	u32	(*inirp_deinit)(_adapter *padapter);
+	void	(*irp_reset)(_adapter *padapter);
+
+	s32	(*init_xmit_priv)(_adapter *padapter);
+	void	(*free_xmit_priv)(_adapter *padapter);
+	
+	s32	(*init_recv_priv)(_adapter *padapter);
+	void	(*free_recv_priv)(_adapter *padapter);
+
+	void (*update_txdesc)(struct xmit_frame *pxmitframe, u8 *pbuf);
+
+	void	(*InitSwLeds)(_adapter *padapter);
+	void	(*DeInitSwLeds)(_adapter *padapter);
+
+	void	(*dm_init)(_adapter *padapter);
+	void	(*dm_deinit)(_adapter *padapter);
+	void	(*read_chip_version)(_adapter *padapter);
+
+	void	(*init_default_value)(_adapter *padapter);
+
+	void	(*intf_chip_configure)(_adapter *padapter);
+
+	void	(*read_adapter_info)(_adapter *padapter);
+
+	void	(*enable_interrupt)(_adapter *padapter);
+	void	(*disable_interrupt)(_adapter *padapter);
+
+	s32		(*interrupt_handler)(_adapter *padapter);
+	void	(*clear_interrupt)(_adapter *padapter);
+	
+#ifdef CONFIG_WOWLAN
+	void	(*disable_interrupt_but_cpwm2)(_adapter *padapter);
+	void (*hal_set_wowlan_fw)(_adapter *adapter, u8 sleep);
+#endif //CONFIG_WOWLAN
+
+	void	(*set_bwmode_handler)(_adapter *padapter, CHANNEL_WIDTH Bandwidth, u8 Offset);
+	void	(*set_channel_handler)(_adapter *padapter, u8 channel);
+	void	(*set_chnl_bw_handler)(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80);
+
+	void	(*hal_dm_watchdog)(_adapter *padapter);
+#if 0
+	void	(*hal_dm_watchdog_in_lps)(_adapter *padapter);
+#endif
+	void	(*SetHwRegHandler)(_adapter *padapter, u8	variable,u8* val);
+	void	(*GetHwRegHandler)(_adapter *padapter, u8	variable,u8* val);
+
+	u8	(*GetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
+	u8	(*SetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
+
+	void	(*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet);
+	void	(*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet);
+
+	void	(*UpdateRAMaskHandler)(_adapter *padapter, u32 mac_id, u8 rssi_level);
+#if 0
+	void	(*SetBeaconRelatedRegistersHandler)(_adapter *padapter);
+#endif
+
+	void	(*Add_RateATid)(_adapter *padapter, u32 bitmap, u8 *arg, u8 rssi_level);
+#ifdef CONFIG_CONCURRENT_MODE	
+	void	(*clone_haldata)(_adapter *dst_padapter, _adapter *src_padapter);
+#endif
+
+	void	(*run_thread)(_adapter *padapter);
+	void	(*cancel_thread)(_adapter *padapter);
+
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	u8	(*AntDivBeforeLinkHandler)(_adapter *padapter);
+	void	(*AntDivCompareHandler)(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
+#endif
+#if 0
+	u8	(*interface_ps_func)(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id, u8* val);
+#endif
+	s32	(*hal_xmit)(_adapter *padapter, struct xmit_frame *pxmitframe);
+	s32 (*mgnt_xmit)(_adapter *padapter, struct xmit_frame *pmgntframe);
+
+	u32	(*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask);
+	void	(*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
+	u32	(*read_rfreg)(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask);
+	void	(*write_rfreg)(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
+
+#ifdef CONFIG_HOSTAPD_MLME
+	s32	(*hostap_mgnt_xmit_entry)(_adapter *padapter, _pkt *pkt);
+#endif
+
+	void (*EfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);
+	void (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest);
+	void (*EFUSEGetEfuseDefinition)(_adapter *padapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);
+	u16	(*EfuseGetCurrentSize)(_adapter *padapter, u8 efuseType, BOOLEAN bPseudoTest);
+#if 0
+	int 	(*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
+#endif
+	int 	(*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
+	u8	(*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
+#if !defined(NOT_SUPPORT_BT)
+	BOOLEAN	(*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
+#endif
+	
+#ifdef DBG_CONFIG_ERROR_DETECT
+	void (*sreset_init_value)(_adapter *padapter);
+	void (*sreset_reset_value)(_adapter *padapter);		
+	void (*silentreset)(_adapter *padapter);
+	void (*sreset_xmit_status_check)(_adapter *padapter);
+	void (*sreset_linked_status_check) (_adapter *padapter);
+	u8 (*sreset_get_wifi_status)(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_IOL
+	int (*IOL_exec_cmds_sync)(_adapter *padapter, struct xmit_frame *xmit_frame, u32 max_wating_ms);
+#endif
+
+#if 0//def CONFIG_XMIT_THREAD_MODE
+	s32 (*xmit_thread_handler)(_adapter *padapter);
+#endif
+	void (*recv_tasklet) (void *padapter);
+
+#if 0
+	void (*hal_notch_filter)(_adapter * adapter, bool enable);
+	void (*hal_reset_security_engine)(_adapter * adapter);
+#endif	
+	s32 (*fill_h2c_cmd)(PADAPTER, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
+	void (*fill_fake_txdesc)(PADAPTER, u8 *pDesc, u32 BufferLen,
+			u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
+	u8 (*hal_get_tx_buff_rsvd_page_num)(_adapter *adapter, bool wowlan);
+};
+
+typedef	enum _RT_EEPROM_TYPE{
+	EEPROM_93C46,
+	EEPROM_93C56,
+	EEPROM_BOOT_EFUSE,
+}RT_EEPROM_TYPE,*PRT_EEPROM_TYPE;
+
+#define USB_HIGH_SPEED_BULK_SIZE	512
+#define USB_FULL_SPEED_BULK_SIZE	64
+
+#define RF_CHANGE_BY_INIT	0
+#define RF_CHANGE_BY_IPS 	BIT28
+#define RF_CHANGE_BY_PS 	BIT29
+#define RF_CHANGE_BY_HW 	BIT30
+#define RF_CHANGE_BY_SW 	BIT31
+
+typedef enum _HARDWARE_TYPE{
+	HARDWARE_TYPE_RTL8180,
+	HARDWARE_TYPE_RTL8185,
+	HARDWARE_TYPE_RTL8187,
+	HARDWARE_TYPE_RTL8188,
+	HARDWARE_TYPE_RTL8190P,
+	HARDWARE_TYPE_RTL8192E,
+	HARDWARE_TYPE_RTL819xU,
+	HARDWARE_TYPE_RTL8192SE,
+	HARDWARE_TYPE_RTL8192SU,
+	HARDWARE_TYPE_RTL8192CE,
+	HARDWARE_TYPE_RTL8192CU,
+	HARDWARE_TYPE_RTL8192DE,
+	HARDWARE_TYPE_RTL8192DU,
+	HARDWARE_TYPE_RTL8723AE,
+	HARDWARE_TYPE_RTL8723AU,
+	HARDWARE_TYPE_RTL8723AS,
+	HARDWARE_TYPE_RTL8188EE,
+	HARDWARE_TYPE_RTL8188EU,
+	HARDWARE_TYPE_RTL8188ES,
+//	NEW_GENERATION_IC
+	HARDWARE_TYPE_RTL8192EE,
+	HARDWARE_TYPE_RTL8192EU,
+	HARDWARE_TYPE_RTL8192ES,
+	HARDWARE_TYPE_RTL8812E,
+	HARDWARE_TYPE_RTL8812AU,
+	HARDWARE_TYPE_RTL8811AU,
+	HARDWARE_TYPE_RTL8821E,
+	HARDWARE_TYPE_RTL8821U,
+	HARDWARE_TYPE_RTL8821S,
+	HARDWARE_TYPE_RTL8723BE,
+	HARDWARE_TYPE_RTL8723BU,
+	HARDWARE_TYPE_RTL8723BS,
+	HARDWARE_TYPE_RTL8195A,
+	HARDWARE_TYPE_RTL8711B,
+	HARDWARE_TYPE_RTL8188FE,
+	HARDWARE_TYPE_RTL8188FU,
+	HARDWARE_TYPE_RTL8188FS,
+	
+	HARDWARE_TYPE_MAX,
+}HARDWARE_TYPE;
+
+#define IS_NEW_GENERATION_IC(_Adapter)	(((_adapter *)_Adapter)->HardwareType >=HARDWARE_TYPE_RTL8192EE)
+//
+// RTL8192C Series
+//
+#define IS_HARDWARE_TYPE_8192CE(_Adapter)	(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CE)
+#define IS_HARDWARE_TYPE_8192CU(_Adapter)	(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CU)
+#define	IS_HARDWARE_TYPE_8192C(_Adapter)			\
+(IS_HARDWARE_TYPE_8192CE(_Adapter) || IS_HARDWARE_TYPE_8192CU(_Adapter))
+
+//
+// RTL8192D Series
+//
+#define IS_HARDWARE_TYPE_8192DE(_Adapter)	(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DE)
+#define IS_HARDWARE_TYPE_8192DU(_Adapter)	(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DU)
+#define	IS_HARDWARE_TYPE_8192D(_Adapter)			\
+(IS_HARDWARE_TYPE_8192DE(_Adapter) || IS_HARDWARE_TYPE_8192DU(_Adapter))
+
+//
+// RTL8723A Series
+//
+#define IS_HARDWARE_TYPE_8723AE(_Adapter)	(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AE)
+#define IS_HARDWARE_TYPE_8723AU(_Adapter)	(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AU)
+#define IS_HARDWARE_TYPE_8723AS(_Adapter)	(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AS)
+#define	IS_HARDWARE_TYPE_8723A(_Adapter)	\
+(IS_HARDWARE_TYPE_8723AE(_Adapter) || IS_HARDWARE_TYPE_8723AU(_Adapter) || IS_HARDWARE_TYPE_8723AS(_Adapter))
+//
+// RTL8188E Series
+//
+#define IS_HARDWARE_TYPE_8188EE(_Adapter)	(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EE)
+#define IS_HARDWARE_TYPE_8188EU(_Adapter)	(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EU)
+#define IS_HARDWARE_TYPE_8188ES(_Adapter)	(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188ES)
+#define	IS_HARDWARE_TYPE_8188E(_Adapter)	\
+(IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter))
+//
+//RTL8188F Series
+//
+#define IS_HARDWARE_TYPE_8188FE(_Adapter)	(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188FE)
+#define IS_HARDWARE_TYPE_8188FU(_Adapter)	(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EU)
+#define IS_HARDWARE_TYPE_8188FS(_Adapter)	(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188FS)
+#define IS_HARDWARE_TYPE_8188F(_Adapter)	\
+(IS_HARDWARE_TYPE_8188FE(_Adapter) || IS_HARDWARE_TYPE_8188FU(_Adapter) || IS_HARDWARE_TYPE_8188FS(_Adapter))
+//
+// RTL8812 Series
+//
+#define IS_HARDWARE_TYPE_8812E(_Adapter)		(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8812E)
+#define IS_HARDWARE_TYPE_8812AU(_Adapter)	(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8812AU)
+#define IS_HARDWARE_TYPE_8812(_Adapter)			\
+(IS_HARDWARE_TYPE_8812E(_Adapter) || IS_HARDWARE_TYPE_8812AU(_Adapter))
+
+// RTL8821 Series
+#define IS_HARDWARE_TYPE_8821E(_Adapter)		(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8821E)
+#define IS_HARDWARE_TYPE_8821U(_Adapter)		(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8821U ||\
+	              								 ((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8811AU)
+#define IS_HARDWARE_TYPE_8821S(_Adapter)		(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8821S)
+#define IS_HARDWARE_TYPE_8821(_Adapter)			\
+(IS_HARDWARE_TYPE_8821E(_Adapter) || IS_HARDWARE_TYPE_8821U(_Adapter)|| IS_HARDWARE_TYPE_8821S(_Adapter))
+
+#define IS_HARDWARE_TYPE_JAGUAR(_Adapter)		\
+(IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter))
+
+//RTL8192E Series
+#define IS_HARDWARE_TYPE_8192EE(_Adapter)		(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192EE)
+#define IS_HARDWARE_TYPE_8192EU(_Adapter)		(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192EU)
+#define IS_HARDWARE_TYPE_8192ES(_Adapter)		(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192ES)
+
+#define IS_HARDWARE_TYPE_8192E(_Adapter)		\
+(IS_HARDWARE_TYPE_8192EE(_Adapter) || IS_HARDWARE_TYPE_8192EU(_Adapter) ||IS_HARDWARE_TYPE_8192ES(_Adapter))
+
+#define IS_HARDWARE_TYPE_8723BE(_Adapter)		(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723BE)
+#define IS_HARDWARE_TYPE_8723BU(_Adapter)		(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723BU)
+#define IS_HARDWARE_TYPE_8723BS(_Adapter)		(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723BS)
+
+
+#define IS_HARDWARE_TYPE_8723B(_Adapter) \
+	(IS_HARDWARE_TYPE_8723BE(_Adapter) || IS_HARDWARE_TYPE_8723BU(_Adapter) ||IS_HARDWARE_TYPE_8723BS(_Adapter))
+
+#define IS_HARDWARE_TYPE_8195A(_Adapter)		(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8195A)
+
+#define IS_HARDWARE_TYPE_8711B(_Adapter)		(((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8711B)
+
+typedef struct eeprom_priv EEPROM_EFUSE_PRIV, *PEEPROM_EFUSE_PRIV;
+#define GET_EEPROM_EFUSE_PRIV(adapter) (&adapter->eeprompriv)
+#define is_boot_from_eeprom(adapter) (adapter->eeprompriv.EepromOrEfuse)
+
+//TODO
+
+#ifdef CONFIG_WOWLAN
+typedef enum _wowlan_subcode{
+	WOWLAN_PATTERN_MATCH	= 1,
+	WOWLAN_MAGIC_PACKET		= 2,
+	WOWLAN_UNICAST			= 3,
+	WOWLAN_SET_PATTERN		= 4,
+	WOWLAN_DUMP_REG			= 5,
+	WOWLAN_ENABLE			= 6,
+	WOWLAN_DISABLE			= 7,
+	WOWLAN_STATUS			= 8,
+	WOWLAN_DEBUG_RELOAD_FW	= 9,
+	WOWLAN_DEBUG_1			=10,
+	WOWLAN_DEBUG_2			=11
+}wowlan_subcode;
+
+struct wowlan_ioctl_param{
+	unsigned int subcode;
+	unsigned int subcode_value;
+	unsigned int wakeup_reason;
+	unsigned int len;
+	unsigned char pattern[0];
+};
+
+#define Rx_Pairwisekey			0x01
+#define Rx_GTK					0x02
+#define Rx_DisAssoc				0x04
+#define Rx_DeAuth				0x08
+#define FWDecisionDisconnect	0x10
+#define Rx_MagicPkt				0x21
+#define Rx_UnicastPkt			0x22
+#define Rx_PatternPkt			0x23
+#endif // CONFIG_WOWLAN
+
+void rtw_hal_def_value_init(_adapter *padapter);
+
+void	rtw_hal_free_data(_adapter *padapter);
+
+void rtw_hal_dm_init(_adapter *padapter);
+void rtw_hal_dm_deinit(_adapter *padapter);
+#if 0
+void rtw_hal_sw_led_init(_adapter *padapter);
+void rtw_hal_sw_led_deinit(_adapter *padapter);
+#endif
+u32 rtw_hal_power_on(_adapter *padapter);
+uint rtw_hal_init(_adapter *padapter);
+uint rtw_hal_deinit(_adapter *padapter);
+void rtw_hal_stop(_adapter *padapter);
+void rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val);
+void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val);
+
+void rtw_hal_chip_configure(_adapter *padapter);
+void rtw_hal_read_chip_info(_adapter *padapter);
+void rtw_hal_read_chip_version(_adapter *padapter);
+
+u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
+u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
+
+void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet);
+void	rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet);
+	
+void rtw_hal_enable_interrupt(_adapter *padapter);
+void rtw_hal_disable_interrupt(_adapter *padapter);
+void rtw_hal_clear_interrupt(_adapter *padapter);
+#ifdef CONFIG_WOWLAN
+void rtw_hal_disable_interrupt_but_cpwm2(_adapter *padapter);
+#endif
+
+u32	rtw_hal_inirp_init(_adapter *padapter);
+u32	rtw_hal_inirp_deinit(_adapter *padapter);
+
+void	rtw_hal_irp_reset(_adapter *padapter);
+#if 0
+u8	rtw_hal_intf_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id, u8* val);
+#endif
+s32	rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
+s32	rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
+
+s32	rtw_hal_init_xmit_priv(_adapter *padapter);
+void	rtw_hal_free_xmit_priv(_adapter *padapter);
+
+#if 1
+s32	rtw_hal_init_recv_priv(_adapter *padapter);
+void	rtw_hal_free_recv_priv(_adapter *padapter);
+#endif
+
+void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level);
+void	rtw_hal_add_ra_tid(_adapter *padapter, u32 bitmap, u8 *arg, u8 rssi_level);
+void	rtw_hal_clone_data(_adapter *dst_padapter, _adapter *src_padapter);
+#ifdef CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD
+void	rtw_hal_start_thread(_adapter *padapter);
+void	rtw_hal_stop_thread(_adapter *padapter);
+#endif
+void rtw_hal_bcn_related_reg_setting(_adapter *padapter);
+
+u32	rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask);
+void	rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
+u32	rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask);
+void	rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
+
+s32	rtw_hal_interrupt_handler(_adapter *padapter);
+
+void	rtw_hal_set_bwmode(_adapter *padapter, CHANNEL_WIDTH Bandwidth, u8 Offset);
+void	rtw_hal_set_chan(_adapter *padapter, u8 channel);
+void	rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80);
+void	rtw_hal_dm_watchdog(_adapter *padapter);
+#if 1
+void rtw_hal_update_txdesc(_adapter  *padapter, struct xmit_frame *pxmitframe, u8 *pbuf);
+#endif
+s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
+
+void rtw_hal_fill_fake_txdesc(_adapter* padapter, u8* pDesc, u32 BufferLen,
+		u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
+
+u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *padapter, bool wowlan);
+
+
+void rtw_hal_set_wowlan_fw(_adapter *padapter, u8 sleep);
+
+
+c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *padapter);
+
+s32 rtw_hal_c2h_handler(_adapter *padapter, u8 *c2h_evt);
+
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+u8	rtw_hal_antdiv_before_linked(_adapter *padapter);
+void	rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
+#endif
+
+#ifdef CONFIG_HOSTAPD_MLME
+s32	rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
+#endif
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+void rtw_hal_sreset_init(_adapter *padapter);
+void rtw_hal_sreset_reset(_adapter *padapter);	
+void rtw_hal_sreset_reset_value(_adapter *padapter);
+void rtw_hal_sreset_xmit_status_check(_adapter *padapter);
+void rtw_hal_sreset_linked_status_check (_adapter *padapter);
+u8   rtw_hal_sreset_get_wifi_status(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_IOL
+int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
+#endif
+
+#if 0//def CONFIG_XMIT_THREAD_MODE
+s32 rtw_hal_xmit_thread_handler(_adapter *padapter);
+#endif
+
+s32	rtw_hal_recv_tasklet(_adapter *padapter);
+#if (RTW_NOTCH_FILTER != 0)
+void rtw_hal_notch_filter(_adapter * adapter, bool enable);
+#endif
+#if 0
+void rtw_hal_reset_security_engine(_adapter * adapter);
+#endif
+
+void decide_chip_type_by_device_id(_adapter *padapter);
+
+
+#ifdef CONFIG_RTL8723A
+void rtl8723as_set_hal_ops(PADAPTER padapter);
+#define hal_set_hal_ops(__adapter) rtl8723as_set_hal_ops(__adapter)
+#endif
+
+#ifdef CONFIG_RTL8188E
+u32 rtl8188e_set_hal_ops(PADAPTER padapter);
+#define hal_set_hal_ops(__adapter) rtl8188e_set_hal_ops(__adapter)
+#endif
+
+#ifdef CONFIG_RTL8188F
+u32 rtl8188fs_set_hal_ops(PADAPTER padapter);
+#define hal_set_hal_ops(__adapter) rtl8188fs_set_hal_ops(__adapter)
+#endif
+
+#ifdef CONFIG_RTL8195A
+u32 rtl8195ab_set_hal_ops(_adapter * padapter);
+#define hal_set_hal_ops rtl8195ab_set_hal_ops
+#define hal_interuupt_recognized InterruptRecognized8195a
+#elif defined(CONFIG_RTL8711B)
+u32 rtl8711bb_set_hal_ops(_adapter * padapter);
+#define hal_set_hal_ops rtl8711bb_set_hal_ops
+#define hal_interuupt_recognized InterruptRecognized8711b
+#endif
+
+
+#endif //__HAL_INTF_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_pg.h

@@ -0,0 +1,81 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __HAL_PG_H__
+#define __HAL_PG_H__
+
+#include <autoconf.h>
+
+//
+// For VHT series TX power by rate table.
+// VHT TX power by rate off setArray = 
+// Band:-2G&5G = 0 / 1
+// RF: at most 4*4 = ABCD=0/1/2/3
+// CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11			
+//
+#define PPG_BB_GAIN_2G_TX_OFFSET_MASK	0x0F
+#define PPG_BB_GAIN_2G_TXB_OFFSET_MASK	0xF0
+
+#define PPG_BB_GAIN_5G_TX_OFFSET_MASK	0x1F
+#define PPG_THERMAL_OFFSET_MASK			0x1F
+#define KFREE_BB_GAIN_2G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))
+#define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))
+
+
+
+#if defined(NOT_SUPPORT_5G)
+#define TX_PWR_BY_RATE_NUM_BAND			1
+#else
+#define TX_PWR_BY_RATE_NUM_BAND			2
+#endif
+
+#if defined(NOT_SUPPORT_RF_MULTIPATH) && defined(NOT_SUPPORT_VHT)
+#define TX_PWR_BY_RATE_NUM_RF			1
+#define TX_PWR_BY_RATE_NUM_RATE			20 // CCK 1M~11M, OFDM 6M~54M, MCS0~7
+#else
+#define TX_PWR_BY_RATE_NUM_RF			4
+#define TX_PWR_BY_RATE_NUM_RATE			84
+#endif
+
+#if defined(NOT_SUPPORT_RF_MULTIPATH)
+#define MAX_RF_PATH					1
+#define MAX_TX_COUNT				1
+#else
+#define MAX_RF_PATH					2	// Max 4 for ss larger than 2
+#define MAX_TX_COUNT				4	//It must always set to 4, otherwise read efuse table secquence will be wrong.
+#endif
+#define	MAX_CHNL_GROUP_24G		6 		// ch1~2, ch3~5, ch6~8,ch9~11,ch12~13,CH 14 total three groups
+#define	MAX_CHNL_GROUP_5G		14
+
+typedef struct _TxPowerInfo24G{
+	u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
+	u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
+	//If only one tx, only BW20 and OFDM are used.
+	s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+	s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+#if !defined(NOT_SUPPORT_RF_MULTIPATH)
+	s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];	
+	s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
+#endif
+}TxPowerInfo24G, *PTxPowerInfo24G;
+
+#endif
+
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_phy.h

@@ -0,0 +1,99 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __HAL_PHY_H__
+#define __HAL_PHY_H__
+
+#define	RF6052_MAX_TX_PWR			0x3F
+#define	RF6052_MAX_REG_88E			0xFF
+#define	RF6052_MAX_REG_92C			0x7F
+
+#define	RF6052_MAX_REG	\
+		(RF6052_MAX_REG_88E > RF6052_MAX_REG_92C) ? RF6052_MAX_REG_88E: RF6052_MAX_REG_92C
+
+#define GET_RF6052_REAL_MAX_REG(_Adapter)	\
+		IS_HARDWARE_TYPE_8188E(_Adapter) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C
+
+#define	RF6052_MAX_PATH				2
+
+/*--------------------------Define Parameters-------------------------------*/
+typedef enum _BAND_TYPE{
+	BAND_ON_2_4G = 0,
+	BAND_ON_5G,
+	BAND_ON_BOTH,
+	BANDMAX
+}BAND_TYPE,*PBAND_TYPE;
+
+typedef	enum _RF_TYPE{
+	RF_TYPE_MIN = 0, 	// 0
+	RF_8225=1,			// 1 11b/g RF for verification only
+	RF_8256=2,			// 2 11b/g/n 
+	RF_8258=3,			// 3 11a/b/g/n RF
+	RF_6052=4,			// 4 11b/g/n RF
+	RF_PSEUDO_11N=5,	// 5, It is a temporality RF. 
+	RF_TYPE_MAX
+}RF_TYPE_E,*PRF_TYPE_E;
+
+typedef enum _RF_PATH{
+	RF_PATH_A = 0,
+	RF_PATH_B,
+	RF_PATH_C,
+	RF_PATH_D
+}RF_PATH, *PRF_PATH;
+
+#define	TX_1S			0			
+#define	TX_2S			1			
+#define	TX_3S			2			
+#define	TX_4S			3
+
+typedef enum _BaseBand_Config_Type{
+	BaseBand_Config_PHY_REG = 0,			//Radio Path A
+	BaseBand_Config_AGC_TAB = 1,			//Radio Path B
+	BaseBand_Config_AGC_TAB_2G = 2,
+	BaseBand_Config_AGC_TAB_5G = 3,	
+	BaseBand_Config_PHY_REG_PG
+}BaseBand_Config_Type, *PBaseBand_Config_Type;
+
+typedef enum _WIRELESS_MODE {
+	WIRELESS_MODE_UNKNOWN = 0x00,
+	WIRELESS_MODE_A = 0x01,
+	WIRELESS_MODE_B = 0x02,
+	WIRELESS_MODE_G = 0x04,
+	WIRELESS_MODE_AUTO = 0x08,
+	WIRELESS_MODE_N_24G = 0x10,
+	WIRELESS_MODE_N_5G = 0x20,
+	WIRELESS_MODE_AC_5G = 0x40,
+	WIRELESS_MODE_AC_24G  = 0x80,
+	WIRELESS_MODE_AC_ONLY  = 0x100,
+} WIRELESS_MODE;
+
+typedef struct RF_Shadow_Compare_Map {
+	// Shadow register value
+	u32		Value;
+	// Compare or not flag
+	u8		Compare;
+	// Record If it had ever modified unpredicted
+	u8		ErrorOrNot;
+	// Recorver Flag
+	u8		Recorver;
+	//
+	u8		Driver_Write;
+}RF_SHADOW_T;
+
+#endif //__HAL_PHY_H__

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_phy_reg.h

@@ -0,0 +1,31 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __HAL_PHY_REG_H__
+#define __HAL_PHY_REG_H__
+
+//for PutRFRegsetting & GetRFRegSetting BitMask
+//#if (RTL92SE_FPGA_VERIFY == 1)
+//#define 		bRFRegOffsetMask	0xfff		
+//#else
+#define 		bRFRegOffsetMask	0xfffff
+//#endif
+
+#endif //__HAL_PHY_REG_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/if_ether.h

@@ -0,0 +1,115 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef _LINUX_IF_ETHER_H
+#define _LINUX_IF_ETHER_H
+
+/*
+ *	IEEE 802.3 Ethernet magic constants.  The frame sizes omit the preamble
+ *	and FCS/CRC (frame check sequence). 
+ */
+
+#define ETH_ALEN	6		/* Octets in one ethernet addr	 */
+#define ETH_HLEN	14		/* Total octets in header.	 */
+#define ETH_ZLEN	60		/* Min. octets in frame sans FCS */
+#define ETH_DATA_LEN	1500		/* Max. octets in payload	 */
+#define ETH_FRAME_LEN	1514		/* Max. octets in frame sans FCS */
+
+/*
+ *	These are the defined Ethernet Protocol ID's.
+ */
+
+#define ETH_P_LOOP	0x0060		/* Ethernet Loopback packet	*/
+#define ETH_P_PUP	0x0200		/* Xerox PUP packet		*/
+#define ETH_P_PUPAT	0x0201		/* Xerox PUP Addr Trans packet	*/
+#define ETH_P_IP	0x0800		/* Internet Protocol packet	*/
+#define ETH_P_X25	0x0805		/* CCITT X.25			*/
+#define ETH_P_ARP	0x0806		/* Address Resolution packet	*/
+#define	ETH_P_BPQ	0x08FF		/* G8BPQ AX.25 Ethernet Packet	[ NOT AN OFFICIALLY REGISTERED ID ] */
+#define ETH_P_IEEEPUP	0x0a00		/* Xerox IEEE802.3 PUP packet */
+#define ETH_P_IEEEPUPAT	0x0a01		/* Xerox IEEE802.3 PUP Addr Trans packet */
+#define ETH_P_DEC       0x6000          /* DEC Assigned proto           */
+#define ETH_P_DNA_DL    0x6001          /* DEC DNA Dump/Load            */
+#define ETH_P_DNA_RC    0x6002          /* DEC DNA Remote Console       */
+#define ETH_P_DNA_RT    0x6003          /* DEC DNA Routing              */
+#define ETH_P_LAT       0x6004          /* DEC LAT                      */
+#define ETH_P_DIAG      0x6005          /* DEC Diagnostics              */
+#define ETH_P_CUST      0x6006          /* DEC Customer use             */
+#define ETH_P_SCA       0x6007          /* DEC Systems Comms Arch       */
+#define ETH_P_RARP      0x8035		/* Reverse Addr Res packet	*/
+#define ETH_P_ATALK	0x809B		/* Appletalk DDP		*/
+#define ETH_P_AARP	0x80F3		/* Appletalk AARP		*/
+#define ETH_P_8021Q	0x8100          /* 802.1Q VLAN Extended Header  */
+#define ETH_P_IPX	0x8137		/* IPX over DIX			*/
+#define ETH_P_IPV6	0x86DD		/* IPv6 over bluebook		*/
+#define ETH_P_PPP_DISC	0x8863		/* PPPoE discovery messages     */
+#define ETH_P_PPP_SES	0x8864		/* PPPoE session messages	*/
+#define ETH_P_ATMMPOA	0x884c		/* MultiProtocol Over ATM	*/
+#define ETH_P_ATMFATE	0x8884		/* Frame-based ATM Transport
+					 * over Ethernet
+					 */
+
+/*
+ *	Non DIX types. Won't clash for 1500 types.
+ */
+ 
+#define ETH_P_802_3	0x0001		/* Dummy type for 802.3 frames  */
+#define ETH_P_AX25	0x0002		/* Dummy protocol id for AX.25  */
+#define ETH_P_ALL	0x0003		/* Every packet (be careful!!!) */
+#define ETH_P_802_2	0x0004		/* 802.2 frames 		*/
+#define ETH_P_SNAP	0x0005		/* Internal only		*/
+#define ETH_P_DDCMP     0x0006          /* DEC DDCMP: Internal only     */
+#define ETH_P_WAN_PPP   0x0007          /* Dummy type for WAN PPP frames*/
+#define ETH_P_PPP_MP    0x0008          /* Dummy type for PPP MP frames */
+#define ETH_P_LOCALTALK 0x0009		/* Localtalk pseudo type 	*/
+#define ETH_P_PPPTALK	0x0010		/* Dummy type for Atalk over PPP*/
+#define ETH_P_TR_802_2	0x0011		/* 802.2 frames 		*/
+#define ETH_P_MOBITEX	0x0015		/* Mobitex (kaz@cafe.net)	*/
+#define ETH_P_CONTROL	0x0016		/* Card specific control frames */
+#define ETH_P_IRDA	0x0017		/* Linux-IrDA			*/
+#define ETH_P_ECONET	0x0018		/* Acorn Econet			*/
+
+/*
+ *	This is an Ethernet frame header.
+ */
+//CONFIG_MEMORY_ACCESS_ALIGNED for 4byte aligned,ethdhr size is 16,leading error in wlanhdr_to_ethdr
+RTW_PACK_STRUCT_BEGIN
+struct ethhdr 
+{
+	unsigned char	h_dest[ETH_ALEN];	/* destination eth addr	*/
+	unsigned char	h_source[ETH_ALEN];	/* source ether addr	*/
+	unsigned short	h_proto;		/* packet type ID field	*/
+} RTW_PACK_STRUCT_STRUCT;
+RTW_PACK_STRUCT_END
+
+struct _vlan {
+   unsigned short       h_vlan_TCI;                // Encapsulates priority and VLAN ID
+   unsigned short       h_vlan_encapsulated_proto;
+};
+
+
+
+#define get_vlan_id(pvlan) ((_htons((unsigned short )pvlan->h_vlan_TCI)) & 0xfff)
+#define get_vlan_priority(pvlan) ((_htons((unsigned short )pvlan->h_vlan_TCI))>>13)
+#define get_vlan_encap_proto(pvlan) (_htons((unsigned short )pvlan->h_vlan_encapsulated_proto))
+
+
+#endif	/* _LINUX_IF_ETHER_H */
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/ip.h

@@ -0,0 +1,142 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef _LINUX_IP_H
+#define _LINUX_IP_H
+#include <rtw_byteorder.h>
+
+/* SOL_IP socket options */
+#ifndef IPTOS_TOS_MASK
+#define IPTOS_TOS_MASK		0x1E
+#define IPTOS_TOS(tos)		((tos)&IPTOS_TOS_MASK)
+#define	IPTOS_LOWDELAY		0x10
+#define	IPTOS_THROUGHPUT	0x08
+#define	IPTOS_RELIABILITY	0x04
+#define	IPTOS_MINCOST		0x02
+
+#define IPTOS_PREC_MASK		0xE0
+#define IPTOS_PREC(tos)		((tos)&IPTOS_PREC_MASK)
+#define IPTOS_PREC_NETCONTROL           0xe0
+#define IPTOS_PREC_INTERNETCONTROL      0xc0
+#define IPTOS_PREC_CRITIC_ECP           0xa0
+#define IPTOS_PREC_FLASHOVERRIDE        0x80
+#define IPTOS_PREC_FLASH                0x60
+#define IPTOS_PREC_IMMEDIATE            0x40
+#define IPTOS_PREC_PRIORITY             0x20
+#define IPTOS_PREC_ROUTINE              0x00
+#endif
+
+/* IP options */
+#define IPOPT_COPY		0x80
+#define IPOPT_CLASS_MASK	0x60
+#define IPOPT_NUMBER_MASK	0x1f
+
+#define	IPOPT_COPIED(o)		((o)&IPOPT_COPY)
+#define	IPOPT_CLASS(o)		((o)&IPOPT_CLASS_MASK)
+#define	IPOPT_NUMBER(o)		((o)&IPOPT_NUMBER_MASK)
+
+#define	IPOPT_CONTROL		0x00
+#define	IPOPT_RESERVED1		0x20
+#define	IPOPT_MEASUREMENT	0x40
+#define	IPOPT_RESERVED2		0x60
+
+#define IPOPT_END	(0 |IPOPT_CONTROL)
+#define IPOPT_NOOP	(1 |IPOPT_CONTROL)
+#define IPOPT_SEC	(2 |IPOPT_CONTROL|IPOPT_COPY)
+#define IPOPT_LSRR	(3 |IPOPT_CONTROL|IPOPT_COPY)
+#define IPOPT_TIMESTAMP	(4 |IPOPT_MEASUREMENT)
+#define IPOPT_RR	(7 |IPOPT_CONTROL)
+#define IPOPT_SID	(8 |IPOPT_CONTROL|IPOPT_COPY)
+#define IPOPT_SSRR	(9 |IPOPT_CONTROL|IPOPT_COPY)
+#define IPOPT_RA	(20|IPOPT_CONTROL|IPOPT_COPY)
+
+#define IPVERSION	4
+#define MAXTTL		255
+#define IPDEFTTL	64
+
+/* struct timestamp, struct route and MAX_ROUTES are removed.
+
+   REASONS: it is clear that nobody used them because:
+   - MAX_ROUTES value was wrong.
+   - "struct route" was wrong.
+   - "struct timestamp" had fatally misaligned bitfields and was completely unusable.
+ */
+
+#define IPOPT_OPTVAL 0
+#define IPOPT_OLEN   1
+#define IPOPT_OFFSET 2
+#define IPOPT_MINOFF 4
+#define MAX_IPOPTLEN 40
+#define IPOPT_NOP IPOPT_NOOP
+#define IPOPT_EOL IPOPT_END
+#define IPOPT_TS  IPOPT_TIMESTAMP
+
+#define	IPOPT_TS_TSONLY		0		/* timestamps only */
+#define	IPOPT_TS_TSANDADDR	1		/* timestamps and addresses */
+#define	IPOPT_TS_PRESPEC	3		/* specified modules only */
+
+#ifdef PLATFORM_LINUX
+
+struct ip_options {
+  __u32		faddr;				/* Saved first hop address */
+  unsigned char	optlen;
+  unsigned char srr;
+  unsigned char rr;
+  unsigned char ts;
+  unsigned char is_setbyuser:1,			/* Set by setsockopt?			*/
+                is_data:1,			/* Options in __data, rather than skb	*/
+                is_strictroute:1,		/* Strict source route			*/
+                srr_is_hit:1,			/* Packet destination addr was our one	*/
+                is_changed:1,			/* IP checksum more not valid		*/	
+                rr_needaddr:1,			/* Need to record addr of outgoing dev	*/
+                ts_needtime:1,			/* Need to record timestamp		*/
+                ts_needaddr:1;			/* Need to record addr of outgoing dev  */
+  unsigned char router_alert;
+  unsigned char __pad1;
+  unsigned char __pad2;
+  unsigned char __data[0];
+};
+
+#define optlength(opt) (sizeof(struct ip_options) + opt->optlen)
+#endif
+
+struct iphdr {
+#if defined(__LITTLE_ENDIAN_BITFIELD)
+	__u8	ihl:4,
+		version:4;
+#elif defined (__BIG_ENDIAN_BITFIELD)
+	__u8	version:4,
+  		ihl:4;
+#else
+#error	"Please fix <asm/byteorder.h>"
+#endif
+	__u8	tos;
+	__u16	tot_len;
+	__u16	id;
+	__u16	frag_off;
+	__u8	ttl;
+	__u8	protocol;
+	__u16	check;
+	__u32	saddr;
+	__u32	daddr;
+	/*The options start here. */
+};
+
+#endif	/* _LINUX_IP_H */
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/lxbus_hal.h

@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __LXBUS_HAL_H__
+#define __LXBUS_HAL_H__
+
+#endif //__LXBUS_HAL_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/lxbus_ops.h

@@ -0,0 +1,80 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __LXBUS_OPS_H__
+#define __LXBUS_OPS_H__
+
+
+#if defined(CONFIG_RTL8195A) 
+//extern u32 TxbdRxbdInitRtl8195a(PADAPTER Adapter);
+//extern u32 TxbdRxbdResetRtl8195a(PADAPTER Adapter);
+
+extern VOID InitLxDmaRtl8195a(_adapter * Adapter);
+extern u32 rtl8195a_init_desc_ring(_adapter * padapter);
+extern u32 rtl8195a_free_desc_ring(_adapter * padapter);
+extern void rtl8195a_reset_desc_ring(_adapter * padapter);
+extern void EnableDMA8195a(PADAPTER padapter);
+extern void EnableInterrupt8195a(PADAPTER padapter);
+extern void DisableDMA8195a(PADAPTER padapter);
+extern void DisableInterrupt8195a(PADAPTER padapter);
+extern s32	InterruptHandle8195a(PADAPTER Adapter);
+extern void lxbus_set_intf_ops(struct _io_ops *pops);
+extern void	rtl8195a_xmit_tasklet(void *priv);
+extern void	rtl8195a_recv_tasklet(void *priv);
+extern void	rtl8195a_prepare_bcn_tasklet(void *priv);
+extern void rtl8195a_tx_int_handler(_adapter *padapter);
+extern void InitInterrupt8195a(PADAPTER padapter);
+extern VOID UpdateInterruptMask8195a(PADAPTER Adapter, u32 *pAddMSRB, u32 *pRemoveMSR);
+
+#ifdef CONFIG_WOWLAN
+extern void ClearInterrupt8195a(PADAPTER padapter);
+#endif
+
+extern void ClearWlPmcInterrupt8195a(PADAPTER padapter);
+extern BOOLEAN	InterruptRecognized8195a(PADAPTER Adapter);
+#elif  defined(CONFIG_RTL8711B)
+
+extern u32 rtl8711b_init_desc_ring(_adapter * padapter);
+extern u32 rtl8711b_free_desc_ring(_adapter * padapter);
+extern void rtl8711b_reset_desc_ring(_adapter * padapter);
+extern void EnableDMA8711b(PADAPTER padapter);
+extern void EnableInterrupt8711b(PADAPTER padapter);
+extern void DisableDMA8711b(PADAPTER padapter);
+extern void DisableInterrupt8711b(PADAPTER padapter);
+extern s32	InterruptHandle8711b(PADAPTER Adapter);
+extern void lxbus_set_intf_ops(struct _io_ops *pops);
+extern void	rtl8711b_xmit_tasklet(void *priv);
+extern void	rtl8711b_recv_tasklet(void *priv);
+extern void	rtl8711b_prepare_bcn_tasklet(void *priv);
+extern void rtl8711b_tx_int_handler(_adapter *padapter);
+extern void InitInterrupt8711b(PADAPTER padapter);
+extern VOID UpdateInterruptMask8711b(PADAPTER Adapter, u32 *pAddMSRB, u32 *pRemoveMSR);
+
+#ifdef CONFIG_WOWLAN
+extern void ClearInterrupt8711b(PADAPTER padapter);
+extern void DisableInterruptButCpwm28711b(PADAPTER padapter);
+#endif
+
+extern void ClearWlPmcInterrupt8711b(PADAPTER padapter);
+extern BOOLEAN	InterruptRecognized8711b(PADAPTER Adapter);
+#endif
+
+
+#endif // !__LXBUS_OPS_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/lxbus_osintf.h

@@ -0,0 +1,29 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __LXBUS_OSINTF_H
+#define __LXBUS_OSINTF_H
+
+
+//void	rtw_pci_disable_aspm(_adapter *padapter);
+//void	rtw_pci_enable_aspm(_adapter *padapter);
+//void	PlatformClearPciPMEStatus(PADAPTER Adapter);
+
+#endif //__LXBUS_OSINTF_H
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/pack_begin.h

@@ -0,0 +1,33 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************
+ *                                        
+ * Define the start point of packed structure
+ *
+ ******************************************************************************/
+
+#if defined(__IAR_SYSTEMS_ICC__)
+#pragma pack(1)
+#endif
+
+#if defined(PLATFORM_WINDOWS)
+#pragma pack(push)
+#pragma pack(1)
+#endif
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/pack_end.h

@@ -0,0 +1,33 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************
+ *                                        
+ * Define the end point of packed structure
+ *
+ ******************************************************************************/
+
+#if defined(__IAR_SYSTEMS_ICC__)
+#pragma pack()
+#endif
+
+#if defined(PLATFORM_WINDOWS)
+#pragma pack(pop)
+#endif
+
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_aes.h

@@ -1,10 +1,25 @@
 /******************************************************************************
  *
- * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************
  *                                        
  * This is ROM code section. 
  *
- *
  ******************************************************************************/
 #ifndef ROM_AES_H
 #define ROM_AES_H

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_arc4.h

@@ -0,0 +1,39 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************
+ *                                        
+ * This is ROM code section. 
+ *
+ ******************************************************************************/
+#ifndef ROM_ARC4_H
+#define ROM_ARC4_H
+
+struct arc4context
+{
+	u32 x;
+	u32 y;
+	u8 state[256];
+};
+
+u32 crc32_get(u8 *buf, sint len);
+void rt_arc4_init(struct arc4context 	*parc4ctx, u8 * key,u32	key_len);
+void rt_arc4_crypt(	struct arc4context	*parc4ctx, u8 * dest, u8 * src, u32 len);
+
+
+#endif //ROM_ARC4_H

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_ieee80211.h

@@ -0,0 +1,127 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __ROM_IEEE80211_H
+#define __ROM_IEEE80211_H
+
+extern const u8 RTW_WPA_OUI_TYPE[] ;
+extern const u8 WPA_CIPHER_SUITE_NONE[];
+extern const u8 WPA_CIPHER_SUITE_WEP40[];
+extern const u8 WPA_CIPHER_SUITE_TKIP[];
+extern const u8 WPA_CIPHER_SUITE_CCMP[];
+extern const u8 WPA_CIPHER_SUITE_WEP104[];
+extern const u16 RSN_VERSION_BSD;
+extern const u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[];
+extern const u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[];
+extern const u8 RSN_CIPHER_SUITE_NONE[];
+extern const u8 RSN_CIPHER_SUITE_WEP40[];
+extern const u8 RSN_CIPHER_SUITE_TKIP[];
+extern const u8 RSN_CIPHER_SUITE_CCMP[];
+extern const u8 RSN_CIPHER_SUITE_WEP104[];
+
+/* Parsed Information Elements */
+struct rtw_ieee802_11_elems {
+	u8 *ssid;
+	u8 ssid_len;
+	u8 *supp_rates;
+	u8 supp_rates_len;
+	u8 *fh_params;
+	u8 fh_params_len;
+	u8 *ds_params;
+	u8 ds_params_len;
+	u8 *cf_params;
+	u8 cf_params_len;
+	u8 *tim;
+	u8 tim_len;
+	u8 *ibss_params;
+	u8 ibss_params_len;
+	u8 *challenge;
+	u8 challenge_len;
+	u8 *erp_info;
+	u8 erp_info_len;
+	u8 *ext_supp_rates;
+	u8 ext_supp_rates_len;
+	u8 *wpa_ie;
+	u8 wpa_ie_len;
+	u8 *rsn_ie;
+	u8 rsn_ie_len;
+	u8 *wme;
+	u8 wme_len;
+	u8 *wme_tspec;
+	u8 wme_tspec_len;
+	u8 *wps_ie;
+	u8 wps_ie_len;
+	u8 *power_cap;
+	u8 power_cap_len;
+	u8 *supp_channels;
+	u8 supp_channels_len;
+	u8 *mdie;
+	u8 mdie_len;
+	u8 *ftie;
+	u8 ftie_len;
+	u8 *timeout_int;
+	u8 timeout_int_len;
+	u8 *ht_capabilities;
+	u8 ht_capabilities_len;
+	u8 *ht_operation;
+	u8 ht_operation_len;
+	u8 *vendor_ht_cap;
+	u8 vendor_ht_cap_len;
+};
+
+typedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes;
+
+ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len,
+                struct rtw_ieee802_11_elems *elems,
+                int show_errors);
+
+u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen);
+u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, u8 *source, uint *frlen);
+u8 *rtw_get_ie(u8*pbuf, sint index, u32 *len, sint limit);
+
+void rtw_set_supported_rate(u8* SupportedRates, uint mode) ;
+
+unsigned char *rtw_get_wpa_ie(unsigned char *pie, u32 *wpa_ie_len, int limit);
+unsigned char *rtw_get_wpa2_ie(unsigned char *pie, u32 *rsn_ie_len, int limit);
+int rtw_get_wpa_cipher_suite(u8 *s);
+int rtw_get_wpa2_cipher_suite(u8 *s);
+
+int rtw_parse_wpa_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x);
+int rtw_parse_wpa2_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x);
+
+int rtw_get_sec_ie(u8 *in_ie,uint in_len,u8 *rsn_ie,u16 *rsn_len,u8 *wpa_ie,u16 *wpa_len);
+
+u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen);
+u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_attr, u32 *len_attr);
+u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_content, uint *len_content);
+
+uint rtw_get_rateset_len(u8	*rateset);
+
+int rtw_get_bit_value_from_ieee_value(u8 val);
+
+uint rtw_is_cckrates_included(u8 *rate);
+
+uint rtw_is_cckratesonly_included(u8 *rate);
+
+int rtw_check_network_type(unsigned char *rate, int ratelen, int channel);
+
+u8 key_2char2num(u8 hch, u8 lch);
+
+#endif /* __ROM_IEEE80211_H */
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_md5.h

@@ -0,0 +1,45 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************
+ *                                        
+ * This is ROM code section. 
+ *
+ ******************************************************************************/
+
+#ifndef ROM_MD5_H
+#define ROM_MD5_H
+
+#if PSK_SUPPORT_TKIP
+
+/* MD5 context. */
+typedef struct {
+  u32 state[4];                                   /* state (ABCD) */
+  u32 count[2];        /* number of bits, modulo 2^64 (lsb first) */
+  u8 buffer[64];                         /* input buffer */
+} md5_ctx;
+
+void rt_md5_init(md5_ctx *context);
+void rt_md5_append(md5_ctx *context, u8 *input, u32 inputLen);
+void rt_md5_final(u8 digest[16], md5_ctx *context);
+void rt_md5_hmac(unsigned char *text, int text_len, unsigned char *key,
+		 int key_len, void * digest);
+
+
+#endif	//#if PSK_SUPPORT_TKIP
+#endif

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rc4.h

@@ -0,0 +1,89 @@
+/* crypto/rc4/rc4.h */
+/* Copyright (C) 1995-1997 Eric Young (eay@cryptsoft.com)
+ * All rights reserved.
+ *
+ * This package is an SSL implementation written
+ * by Eric Young (eay@cryptsoft.com).
+ * The implementation was written so as to conform with Netscapes SSL.
+ *
+ * This library is free for commercial and non-commercial use as long as
+ * the following conditions are aheared to.  The following conditions
+ * apply to all code found in this distribution, be it the RC4, RSA,
+ * lhash, DES, etc., code; not just the SSL code.  The SSL documentation
+ * included with this distribution is covered by the same copyright terms
+ * except that the holder is Tim Hudson (tjh@cryptsoft.com).
+ *
+ * Copyright remains Eric Young's, and as such any Copyright notices in
+ * the code are not to be removed.
+ * If this package is used in a product, Eric Young should be given attribution
+ * as the author of the parts of the library used.
+ * This can be in the form of a textual message at program startup or
+ * in documentation (online or textual) provided with the package.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *    "This product includes cryptographic software written by
+ *     Eric Young (eay@cryptsoft.com)"
+ *    The word 'cryptographic' can be left out if the rouines from the library
+ *    being used are not cryptographic related :-).
+ * 4. If you include any Windows specific code (or a derivative thereof) from
+ *    the apps directory (application code) you must include an acknowledgement:
+ *    "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
+ *
+ * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * The licence and distribution terms for any publically available version or
+ * derivative of this code cannot be changed.  i.e. this code cannot simply be
+ * copied and put under another distribution licence
+ * [including the GNU Public Licence.]
+ */
+
+#ifndef HEADER_RC4_H
+#define HEADER_RC4_H
+
+#ifdef OPENSSL_NO_RC4
+#error RC4 is disabled.
+#endif
+
+//#include <openssl/opensslconf.h> /* RC4_INT */
+#define RC4_INT unsigned int
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+typedef struct rc4_key_st
+	{
+	RC4_INT x,y;
+	RC4_INT data[256];
+	} RC4_KEY;
+
+
+//const char *RC4_options(void);
+void RC4_set_key(RC4_KEY *key, int len, const unsigned char *data);
+void RC4(RC4_KEY *key, unsigned long len, const unsigned char *indata,
+		unsigned char *outdata);
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_message.h

@@ -0,0 +1,48 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef _ROM_RTW_MESSAGE_
+#define _ROM_RTW_MESSAGE_
+
+#include <platform_stdlib.h>
+
+typedef enum {
+#define ROM_E_RTW_MSGPOOL(name,str)  ROM_E_RTW_MSGP_##name,
+#include "rom_rtw_message_e.h"
+  ROM_E_RTW_MSGP_MAX
+} rom_e_rtw_msgp_t;
+
+#if ROM_E_RTW_MSG
+extern const char *rom_e_rtw_msgp_str_[];
+#define rom_e_rtw_msg_printf(name, fmt, args...) printf((char*)rom_e_rtw_msgp_str_[ROM_E_RTW_MSGP_##name], ## args)
+#define rom_e_rtw_msg_871X_LEVEL(name, level, fmt, args...) \
+	do {\
+		printf("\n\r");\
+		printf((char*)rom_e_rtw_msgp_str_[ROM_E_RTW_MSGP_##name], ## args);\
+	}while(0)
+#else
+#define rom_e_rtw_msg_printf(name, fmt, args...) printf(fmt, ## args)
+#define rom_e_rtw_msg_871X_LEVEL(name, level, fmt, args...) \
+	do {\
+		printf("\n\r");\
+		printf(DRIVER_PREFIX ##fmt, ## args);\
+	}while(0)
+#endif //ROM_E_RTW_MSG
+
+#endif //_ROM_RTW_MESSAGE_

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_message_e.h

@@ -0,0 +1,174 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+// Debug message
+// DBG_PWR_INDEX
+ROM_E_RTW_MSGPOOL(PWR_INDEX_1,	"BandWidth = %d, Rate = %d, Channel = %d\n\r")
+ROM_E_RTW_MSGPOOL(PWR_INDEX_2,	"Base = %d, DiffByRate = %d, limit = %d, DiffByTrack = %d, Tx Power = %d\n\n\r")
+// DBG_RX_INFO
+ROM_E_RTW_MSGPOOL(RX_INFO_1,	"============ Rx Info dump ===================\n")
+ROM_E_RTW_MSGPOOL(RX_INFO_2,	"bLinked = %d, RSSI_Min = %d(%%), CurrentIGI = 0x%x\n")
+ROM_E_RTW_MSGPOOL(RX_INFO_3,	"Cnt_Cck_fail = %d, Cnt_Ofdm_fail = %d, Total False Alarm = %d\n")
+ROM_E_RTW_MSGPOOL(RX_INFO_4,	"RxRate = 0x%x, RSSI_A = %d(%%), RSSI_B = %d(%%)\n")
+// DBG_TX_RATE
+ROM_E_RTW_MSGPOOL(TX_RATE_1,	"Rate: 0x%x\n\r")
+ROM_E_RTW_MSGPOOL(TX_RATE_2,	"%s(): mac_id=%d raid=0x%x bw=%d mask=0x%x init_rate=0x%x\n")
+// DBG_DM_RA
+ROM_E_RTW_MSGPOOL(DM_RA_1,	"==> ReadRateMask = 0x%x RAMASK[%d] = 0x%x\n")
+ROM_E_RTW_MSGPOOL(DM_RA_2,	"==> TMP_rate = %x highest_rate = 0x%02X, lowest_rate = 0x%02X\n")
+ROM_E_RTW_MSGPOOL(DM_RA_3,	"==> MacID = %d rateid = 0x%x sgi = %d bw_idx = %d\n\r")
+ROM_E_RTW_MSGPOOL(DM_RA_4,	"%s(): mac_id=%d raid=0x%x bw=%d mask=0x%x\r\n")
+// DBG_DM_DIG
+ROM_E_RTW_MSGPOOL(DM_DIG_1,	"CurrentIGI(0x%02x)\n\n")
+// DBG_PWR_TRACKING
+ROM_E_RTW_MSGPOOL(PWR_TRACKING_1,	"Thermal = 0x%02X\r\n")
+ROM_E_RTW_MSGPOOL(PWR_TRACKING_2,	"delta = %d, AVG Thermal = 0x%02X, EFUSE = 0x%02X, PackageType = 0x%02X\r\n")
+ROM_E_RTW_MSGPOOL(PWR_TRACKING_3,	"Channel = %d, CCK PwrBase = 0x%02X, HT40M PwrBase = 0x%02X, OFDMdiff = %d, 20Mdiff = %d \n\r")
+ROM_E_RTW_MSGPOOL(PWR_TRACKING_4,	"Remnant_CCKSwingIdx  = %d\n\r")
+ROM_E_RTW_MSGPOOL(PWR_TRACKING_5,	"Remnant_OFDMSwingIdx = %d\n\r")
+ROM_E_RTW_MSGPOOL(PWR_TRACKING_6,	"CCK2~11: 0x86c = 0x%08X\r\n")
+ROM_E_RTW_MSGPOOL(PWR_TRACKING_7,	"MCS7~4 : 0xe14 = 0x%08X\r\n")
+// DBG_RF_IQK
+ROM_E_RTW_MSGPOOL(RF_IQK_1,	"Path A Tx IQK Success!\n")
+ROM_E_RTW_MSGPOOL(RF_IQK_2,	"Path A Rx IQK Success!\n")
+ROM_E_RTW_MSGPOOL(RF_IQK_3,	"Path A IQK failed!\n")
+ROM_E_RTW_MSGPOOL(RF_IQK_4,	"IQK finished\n")
+ROM_E_RTW_MSGPOOL(RF_IQK_5,	"LCK finished\n")
+// DBG_DM_ADAPTIVITY
+ROM_E_RTW_MSGPOOL(DM_ADAPTIVITY_1, "IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d\n")
+ROM_E_RTW_MSGPOOL(DM_ADAPTIVITY_2, "DynamicLinkAdaptivity = %d, Adaptivity_enable = %d\n")
+ROM_E_RTW_MSGPOOL(DM_ADAPTIVITY_3, "IGI=0x%x, TH_L2H_dmc = 0x%x, TH_H2L_dmc = 0x%x\n\n")
+
+// freertos_ioctl.c
+// mac_reg_dump, bb_reg_dump, rf_reg_dump
+ROM_E_RTW_MSGPOOL(MAC_REG_DUMP_1,	"\n======= MAC REG =======\n")
+ROM_E_RTW_MSGPOOL(BB_REG_DUMP_1,	"\n======= BB REG =======\n")
+ROM_E_RTW_MSGPOOL(RF_REG_DUMP_1,	"\n======= RF REG =======\n")
+ROM_E_RTW_MSGPOOL(RF_REG_DUMP_2,	"\nRF_Path(%x)\n")
+ROM_E_RTW_MSGPOOL(REG_DUMP_1,	"0x%02x ")
+ROM_E_RTW_MSGPOOL(REG_DUMP_2,	" 0x%08x ")
+ROM_E_RTW_MSGPOOL(REG_DUMP_3,	"\n")
+// 0x70 read reg
+ROM_E_RTW_MSGPOOL(READ_REG_1,	"rtw_read8(0x%x)=0x%02x\n")
+ROM_E_RTW_MSGPOOL(READ_REG_2,	"rtw_read16(0x%x)=0x%04x\n")
+ROM_E_RTW_MSGPOOL(READ_REG_3,	"rtw_read32(0x%x)=0x%08x\n")
+// 0x71 write reg
+ROM_E_RTW_MSGPOOL(WRITE_REG_1,	"rtw_write8(0x%x)=0x%02x\n")
+ROM_E_RTW_MSGPOOL(WRITE_REG_2,	"rtw_write16(0x%x)=0x%04x\n")
+ROM_E_RTW_MSGPOOL(WRITE_REG_3,	"rtw_write32(0x%x)=0x%08x\n")
+// 0x72 read bb
+ROM_E_RTW_MSGPOOL(READ_BB_1,	"read_bbreg(0x%x)=0x%x\n")
+// 0x73 write bb
+ROM_E_RTW_MSGPOOL(WRITE_BB_1,	"write_bbreg(0x%x)=0x%x\n")
+// 0x74 read rf
+ROM_E_RTW_MSGPOOL(READ_RF_1,	"read RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n")
+// 0x75 write rf
+ROM_E_RTW_MSGPOOL(WRITE_RF_1,	"write RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n")
+// 0x17 fix channel
+ROM_E_RTW_MSGPOOL(FIX_CHANNEL_1,	"=>Fixed channel to %d\n")
+ROM_E_RTW_MSGPOOL(FIX_CHANNEL_2,	"Invalid channel number(%d)\n")
+// 0x22 enable / disable power saving mode
+ROM_E_RTW_MSGPOOL(PWR_SAVE_MODE_1,	"wlan power saving mode = %s\n")
+// 0xaa fix rate
+ROM_E_RTW_MSGPOOL(FIX_RATE_1,	"chang data rate to :0x%02x\n")
+// 0xc0 get odm dbg flag
+ROM_E_RTW_MSGPOOL(GET_ODM_DBG_FLAG_1,	"get odm dbg flag : 0x%08x\n")
+// 0xc1 set odm dbg flag
+ROM_E_RTW_MSGPOOL(SET_ODM_DBG_FLAG_1,	"set odm dbg flag : 0x%08x\n")
+// 0xcc open power index debug message (power by rate, power limit, power tracking)
+ROM_E_RTW_MSGPOOL(DUMP_PWR_IDX_1,	"Fixed rate = %d\n")
+// 0xdd dump info
+ROM_E_RTW_MSGPOOL(DUMP_INFO_1,	"Tx power:\n")
+ROM_E_RTW_MSGPOOL(DUMP_INFO_2,	"CCK 1(0xe08)= 0x%x\n")
+ROM_E_RTW_MSGPOOL(DUMP_INFO_3,	"CCK 11~2(0x86c)= 0x%x\n")
+ROM_E_RTW_MSGPOOL(DUMP_INFO_4,	"OFDM 18~6(0xe00)= 0x%x\n")
+ROM_E_RTW_MSGPOOL(DUMP_INFO_5,	"OFDM 54~24(0xe04)= 0x%x\n")
+ROM_E_RTW_MSGPOOL(DUMP_INFO_6,	"MCS 3~0(0xe10)= 0x%x\n")
+ROM_E_RTW_MSGPOOL(DUMP_INFO_7,	"MCS 7~4(0xe14)= 0x%x\n")
+ROM_E_RTW_MSGPOOL(DUMP_INFO_8,	"Country code: 0x%x\n")
+// 0xee turn on/off dynamic funcs
+ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_1,	" === DMFlag(0x%08x) === \n")
+ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_2,	"extra_arg = 0 - disable all dynamic func\n")
+ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_3,	"extra_arg = 1 - enable all dynamic func\n")
+ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_4,	"extra_arg = 2 - disable DIG\n")
+ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_5,	"extra_arg = 3 - enable DIG\n")
+ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_6,	"extra_arg = 4 - disable tx power tracking\n")
+ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_7,	"extra_arg = 5 - enable tx power tracking\n")
+ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_8,	"extra_arg = 6 - disable adaptivity\n")
+ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_9,	"extra_arg = 7 - enable adaptivity\n")
+
+// lxbus_ops.c
+ROM_E_RTW_MSGPOOL(RX_MPDU_1,	"Drop packet! crc_err = %d, icv_err = %d, rx_pkt_len = %d, skb_pkt_len = %d\n")
+
+// wlan driver DBG_871X_LEVEL
+#define ROM_E_RTW_MSGPOOL_871X(name,str) ROM_E_RTW_MSGPOOL(name,DRIVER_PREFIX str)
+// rtw_ap.c
+ROM_E_RTW_MSGPOOL_871X(AP_TIMEOUT_CHK_1,	"Asoc expire "MAC_FMT"\n")
+// rtw_intfs.c
+ROM_E_RTW_MSGPOOL_871X(INIT_DRV_SW_1,	"The driver is for MP\n")
+// rtw_ioctl_set.c
+ROM_E_RTW_MSGPOOL_871X(SET_BSSID_1,	"set BSSID: %02x:%02x:%02x:%02x:%02x:%02x\n")
+ROM_E_RTW_MSGPOOL_871X(SET_SSID_1,	"set ssid [%s] \n")
+// rtw_mlme_ext.c
+ROM_E_RTW_MSGPOOL_871X(ON_BEACON_1,	"ap has changed, disconnect now\n ")
+ROM_E_RTW_MSGPOOL_871X(ON_AUTH_1,	"+OnAuth: "MAC_FMT"\n")
+ROM_E_RTW_MSGPOOL_871X(ON_AUTH_2,	" Exceed the upper limit(%d) of supported clients...\n")
+ROM_E_RTW_MSGPOOL_871X(ON_AUTH_CLIENT_1,	"auth success, start assoc\n")
+ROM_E_RTW_MSGPOOL_871X(ON_ASSOC_REQ_1,	"+OnAssocReq\n")
+ROM_E_RTW_MSGPOOL_871X(ON_ASSOC_RSP_1,	"association success(res=%d)\n")
+ROM_E_RTW_MSGPOOL_871X(ON_DE_AUTH_1,	"ap recv deauth reason code(%d) sta:"MAC_FMT"\n")
+ROM_E_RTW_MSGPOOL_871X(ON_DE_AUTH_2,	"sta recv deauth reason code(%d) sta:"MAC_FMT"\n")
+ROM_E_RTW_MSGPOOL_871X(ON_DISASSOC_1,	"ap recv disassoc reason code(%d) sta:"MAC_FMT"\n")
+ROM_E_RTW_MSGPOOL_871X(ON_DISASSOC_2,	"sta recv disassoc reason code(%d) sta:"MAC_FMT"\n")
+ROM_E_RTW_MSGPOOL_871X(ISSUE_BEACON_1,	"beacon frame too large\n")
+ROM_E_RTW_MSGPOOL_871X(ISSUE_PROBERSP_1,	"probersp frame too large\n")
+ROM_E_RTW_MSGPOOL_871X(ISSUE_PROBEREQ_1,	"probereq frame too large\n")
+ROM_E_RTW_MSGPOOL_871X(ISSUE_AUTH_1,	"auth frame too large\n")
+ROM_E_RTW_MSGPOOL_871X(ISSUE_ASSOCRSP_1,	"assocrsp frame too large\n")
+ROM_E_RTW_MSGPOOL_871X(ISSUE_ASSOCREQ_1,	"assocreq frame too large\n")
+ROM_E_RTW_MSGPOOL_871X(ISSUE_NULLDATA_1,	"nulldata frame too large\n")
+ROM_E_RTW_MSGPOOL_871X(ISSUE_QOS_NULLDATA_1,	"qos nulldata frame too large\n")
+ROM_E_RTW_MSGPOOL_871X(ISSUE_DEAUTH_1,	"deauth frame too large\n")
+ROM_E_RTW_MSGPOOL_871X(ISSUE_ACTION_BA_1,	"action BA frame too large\n")
+ROM_E_RTW_MSGPOOL_871X(ISSUE_BSS_COEXIST_1,	"action BSSCoexist frame too large\n")
+ROM_E_RTW_MSGPOOL_871X(START_CLNT_AUTH_1,	"start auth to %02x:%02x:%02x:%02x:%02x:%02x\n")
+ROM_E_RTW_MSGPOOL_871X(LINKED_STATUS_CHK_1,	"no beacon for a long time, disconnect or roaming\n")
+ROM_E_RTW_MSGPOOL_871X(SETKEY_HDL_1,	"set group key to hw: alg:%d(WEP40-1 WEP104-5 TKIP-2 AES-4) keyid:%d\n")
+ROM_E_RTW_MSGPOOL_871X(SET_STAKEY_HDL_1,	"set pairwise key to hw: alg:%d(WEP40-1 WEP104-5 TKIP-2 AES-4)\n")
+ROM_E_RTW_MSGPOOL_871X(SET_STAKEY_HDL_2,	"set pairwise key to hw: alg:%d(WEP40-1 WEP104-5 TKIP-2 AES-4) for %x:%x:%x:%x:%x:%x\n")
+// rtw_p2p.c
+ROM_E_RTW_MSGPOOL_871X(P2P_BUILD_MGNT_FRAME_1,	"p2p mgnt frame too large\n")
+// rtw_psk.c
+ROM_E_RTW_MSGPOOL_871X(SEND_EAPOL_1,	"ap mode 4-1\n")
+ROM_E_RTW_MSGPOOL_871X(SEND_EAPOL_2,	"ap mode 4-3\n")
+ROM_E_RTW_MSGPOOL_871X(SEND_EAPOL_3,	"ap mode 2-1 to WPA_STA(%d)\n")
+ROM_E_RTW_MSGPOOL_871X(EAPOL_KEY_RECVD_1,	"ap mode 4-2\n")
+ROM_E_RTW_MSGPOOL_871X(EAPOL_KEY_RECVD_2,	"ap mode 4-4\n")
+ROM_E_RTW_MSGPOOL_871X(EAPOL_KEY_RECVD_3,	"ap mode 2-2 from WPA_STA(%d)\n")
+// rtw_recv.c
+ROM_E_RTW_MSGPOOL_871X(FREE_RECVFRAME_1,	"%s free_recvframe_cnt:%d > %d refree happen !!!!\n")
+// hal_com.c
+ROM_E_RTW_MSGPOOL_871X(VAR_PORT_SWITCH_1,	"port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n")
+ROM_E_RTW_MSGPOOL_871X(VAR_PORT_SWITCH_2,	"port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n")
+// osdep_service.c
+ROM_E_RTW_MSGPOOL_871X(DOWN_SEMA_1,	"%s(%p) failed, retry\n")
+
+
+#undef ROM_E_RTW_MSGPOOL
+#undef ROM_E_RTW_MSGPOOL_871X

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_psk.h

@@ -0,0 +1,44 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************
+ *                                        
+ * This is ROM code section. 
+ *
+ ******************************************************************************/
+#ifndef __ROM_RTW_PSK_H_
+#define __ROM_RTW_PSK_H_
+
+int rom_psk_PasswordHash (
+				unsigned char *password,
+				int passwordlength,
+				unsigned char *ssid,
+				int ssidlength,
+				unsigned char *output);
+
+void rom_psk_CalcPTK(	unsigned char *addr1, unsigned char *addr2,
+			unsigned char *nonce1, unsigned char *nonce2,
+			unsigned char *keyin, int keyinlen,
+			unsigned char *keyout, int keyoutlen);
+
+void rom_psk_CalcGTK(unsigned char *addr, unsigned char *nonce,
+				unsigned char *keyin, int keyinlen,
+				unsigned char *keyout, int keyoutlen);
+
+#endif	//__ROM_RTW_PSK_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_security.h

@@ -0,0 +1,104 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************
+ *                                        
+ * This is ROM code section. 
+ *
+ ******************************************************************************/
+#ifndef __ROM_RTW_SECURITY_H_
+#define __ROM_RTW_SECURITY_H_
+
+struct mic_data
+{
+	u32  K0, K1;         // Key
+	u32  L, R;           // Current state
+	u32  M;              // Message accumulator (single word)
+	u32     nBytesInM;      // # bytes in M
+};
+
+union  u_crc 
+{    
+	unsigned char	ch[4];    
+	int i;  
+};
+
+//===============================
+// WEP related
+//===============================
+void wep_80211_encrypt(
+	u8 *pframe, u32 wlan_hdr_len, \
+	u32 iv_len, u32 payload_len,\
+	u8* key, u32 key_len);
+
+u8 wep_80211_decrypt(
+	u8 *pframe, u32 wlan_hdr_len, 
+	u32 iv_len, u32 payload_len,
+	u8* key, u32 key_len,
+	union u_crc *pcrc\
+	);
+
+//===============================
+// TKIP related
+//===============================
+void tkip_80211_encrypt(
+	u8 *pframe, u32 wlan_hdr_len, \
+	u32 iv_len, u32 payload_len,\
+	u8* key, u32 key_len,\
+	u8* ta);
+
+u8 tkip_80211_decrypt(
+	u8 *pframe, u32 wlan_hdr_len, \
+	u32 iv_len, u32 payload_len,\
+	u8* key, u32 key_len,\
+	u8* ta, union u_crc *pcrc);
+
+void tkip_micappendbyte(struct mic_data *pmicdata, u8 b );
+void rtw_secmicsetkey(struct mic_data *pmicdata, u8 * key);
+void rtw_secmicappend(struct mic_data *pmicdata, u8 * src, u32 nbytes );
+void rtw_secgetmic(struct mic_data *pmicdata, u8 * dst );
+void rtw_seccalctkipmic(u8 * key,u8 *header,u8 *data,u32 data_len,u8 *mic_code, u8 pri);
+void tkip_phase1(u16 *p1k,const u8 *tk,const u8 *ta,u32 iv32);
+void tkip_phase2(u8 *rc4key,const u8 *tk,const u16 *p1k,u16 iv16);
+
+
+//===============================
+// AES related
+//===============================
+void aes1_encrypt(u8 *key, u8 *data, u8 *ciphertext);
+void aesccmp_construct_mic_iv(
+	u8 *mic_iv, sint qc_exists, sint a4_exists, 
+	u8 *mpdu, uint payload_length,u8 *pn_vector);
+void aesccmp_construct_mic_header1(u8 *mic_header1, sint header_length, u8 *mpdu);
+void aesccmp_construct_mic_header2(
+	u8 *mic_header2, u8 *mpdu, sint a4_exists, sint qc_exists);
+void aesccmp_construct_ctr_preload(
+	u8 *ctr_preload, sint a4_exists, sint qc_exists,
+	u8 *mpdu, u8 *pn_vector, sint c);
+
+u32 aes_80211_encrypt(
+	u8 *pframe, u32 wlan_hdr_len, \
+	u32 payload_len, u8 *key, \
+	u32 frame_type, u8 *mic);
+
+u32 aes_80211_decrypt(
+	u8 *pframe, u32 wlan_hdr_len, \
+	u32 payload_len, u8 *key, \
+	u32 frame_type, u8 *mic);
+#endif	//__ROM_RTW_SECURITY_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_sha1.h

@@ -0,0 +1,71 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef _ROM_SHA1_
+#define _ROM_SHA1_
+
+
+#ifndef _SHA_enum_
+#define _SHA_enum_
+enum
+{
+    shaSuccess = 0,
+    shaNull,            /* Null pointer parameter */
+    shaInputTooLong,    /* input data too long */
+    shaStateError       /* called Input after Result */
+};
+#endif
+
+
+#define SHA1HashSize 20
+
+/*
+ *  This structure will hold context information for the SHA-1
+ *  hashing operation
+ */
+typedef struct SHA1Context
+{
+    u32 Intermediate_Hash[SHA1HashSize/4]; /* Message Digest  */
+
+    u32 Length_Low;            /* Message length in bits      */
+    u32 Length_High;           /* Message length in bits      */
+
+                               /* Index into message block array   */
+    u16 Message_Block_Index;
+    u8 Message_Block[64];      /* 512-bit message blocks      */
+
+    int Computed;               /* Is the digest computed?         */
+    int Corrupted;             /* Is the message digest corrupted? */
+} SHA1Context;
+
+
+/*
+ *  Function Prototypes
+ */
+
+
+int rt_sha1_init(  SHA1Context *);
+int rt_sha1_update(  SHA1Context *, const u8 *, unsigned int);
+int rt_sha1_finish( SHA1Context *, u8 Message_Digest[SHA1HashSize]);
+
+void rt_hmac_sha1(unsigned char *text, int text_len, unsigned char *key,
+		 int key_len, unsigned char *digest);
+
+
+#endif //_ROM_SHA1_

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtl8195a_hal.h

@@ -0,0 +1,618 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __RTL8195A_HAL_H__
+#define __RTL8195A_HAL_H__
+
+#include "drv_types.h"
+#include "rtl8195a/rtl8195a_pmu_task.h"
+#include "hal_data.h"
+
+#include "rtl8195a/rtl8195a_spec.h"
+#include "rtl8195a/rtl8195a_rf.h"
+#include "rtl8195a/rtl8195a_dm.h"
+#include "rtl8195a/rtl8195a_recv.h"
+#include "rtl8195a/rtl8195a_xmit.h"
+#include "rtl8195a/rtl8195a_cmd.h"
+#include "rtl8195a/rtl8195a_pmu_cmd.h"
+#include "rtl8195a/rtl8195a_led.h"
+#include "rtl8195a/Hal8195APwrSeq.h"
+#include "rtl8195a/Hal8195APhyReg.h"
+#include "rtl8195a/Hal8195APhyCfg.h"
+#include "rtl8195a/rom_Hal8195APhyCfg.h"
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+#include "rtl8195a/rtl8195a_sreset.h"
+#endif
+
+#include "../src/hal/OUTSRC/phydm_precomp.h"
+
+#if (RTL8195A_SUPPORT==1)
+	//2TODO: We should define 8192S firmware related macro settings here!!
+	#define RTL819X_DEFAULT_RF_TYPE			RF_1T2R
+	#define RTL819X_TOTAL_RF_PATH				2
+
+//---------------------------------------------------------------------
+//		RTL8723BS From file
+//---------------------------------------------------------------------
+	#define RTL8723B_FW_IMG					"rtl8723B\\rtl8723bfw.bin"
+	#define RTL8195A_PHY_REG					"rtl8195A\\PHY_REG_1T.txt"
+	#define RTL8195A_PHY_RADIO_A			"rtl8195A\\radio_a_1T.txt"
+	#define RTL8195A_PHY_RADIO_B			"rtl8195A\\radio_b_1T.txt"
+	#define RTL8195A_TXPWR_TRACK			"rtl8195A\\TxPowerTrack.txt" 
+	#define RTL8195A_AGC_TAB					"rtl8195A\\AGC_TAB_1T.txt"
+	#define RTL8195A_PHY_MACREG				"rtl87195A\\MAC_REG.txt"
+	#define RTL8195A_PHY_REG_PG				"rtl8195A\\PHY_REG_PG.txt"
+	#define RTL8195A_PHY_REG_MP				"rtl8195A\\PHY_REG_MP.txt"
+	#define RTL8195A_TXPWR_LMT 				"rtl8195A\\TXPWR_LMT.txt"
+
+//---------------------------------------------------------------------
+//		RTL8723BS From header
+//---------------------------------------------------------------------
+
+	//#define Rtl8723B_FwImageArray				Array_MP_8723B_FW_NIC
+	//#define Rtl8723B_FwImgArrayLength			ArrayLength_MP_8723B_FW_NIC
+	//#define Rtl8723B_FwWoWImageArray			Array_MP_8723B_FW_WoWLAN
+	//#define Rtl8723B_FwWoWImgArrayLength		ArrayLength_MP_8723B_FW_WoWLAN
+
+	#define Rtl8723B_PHY_REG_Array_PG 			Rtl8723SPHY_REG_Array_PG
+	#define Rtl8723B_PHY_REG_Array_PGLength	Rtl8723SPHY_REG_Array_PGLength
+
+#if MP_DRIVER == 1
+	#define Rtl8723B_FwBTImgArray				Rtl8723BFwBTImgArray
+	#define Rtl8723B_FwBTImgArrayLength		Rtl8723BFwBTImgArrayLength
+
+	#define Rtl8723B_FwMPImageArray			Rtl8723BFwMPImgArray
+	#define Rtl8723B_FwMPImgArrayLength		Rtl8723BMPImgArrayLength
+
+	#define Rtl8723B_PHY_REG_Array_MP			Rtl8723B_PHYREG_Array_MP
+	#define Rtl8723B_PHY_REG_Array_MPLength	Rtl8723B_PHYREG_Array_MPLength
+#endif
+
+#endif // RTL8195A_SUPPORT
+
+#define FW_8723B_SIZE			0x8000
+#define FW_8723B_START_ADDRESS	0x1000
+#define FW_8723B_END_ADDRESS		0x1FFF //0x5FFF
+
+#define IS_FW_HEADER_EXIST_8723B(_pFwHdr)	((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x5300)
+
+typedef struct _RT_FIRMWARE {
+	FIRMWARE_SOURCE	eFWSource;
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8*			szFwBuffer;
+#else
+	u8			szFwBuffer[FW_8723B_SIZE];
+#endif
+	u32			ulFwLength;
+
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8*			szBTFwBuffer;
+#else
+	u8			szBTFwBuffer[FW_8723B_SIZE];
+#endif
+	u32			ulBTFwLength;
+
+#ifdef CONFIG_WOWLAN
+	u8*			szWoWLANFwBuffer;
+	u32			ulWoWLANFwLength;
+#endif //CONFIG_WOWLAN
+} RT_FIRMWARE_8723B, *PRT_FIRMWARE_8723B;
+
+//
+// This structure must be cared byte-ordering
+//
+// Added by tynli. 2009.12.04.
+typedef struct _RT_8723B_FIRMWARE_HDR
+{
+	// 8-byte alinment required
+
+	//--- LONG WORD 0 ----
+	u16		Signature;	// 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
+	u8		Category;	// AP/NIC and USB/PCI
+	u8		Function;	// Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
+	u16		Version;		// FW Version
+	u8		Subversion;	// FW Subversion, default 0x00
+	u16		Rsvd1;
+
+
+	//--- LONG WORD 1 ----
+	u8		Month;	// Release time Month field
+	u8		Date;	// Release time Date field
+	u8		Hour;	// Release time Hour field
+	u8		Minute;	// Release time Minute field
+	u16		RamCodeSize;	// The size of RAM code
+	u16		Rsvd2;
+
+	//--- LONG WORD 2 ----
+	u32		SvnIdx;	// The SVN entry index
+	u32		Rsvd3;
+
+	//--- LONG WORD 3 ----
+	u32		Rsvd4;
+	u32		Rsvd5;
+}RT_8723B_FIRMWARE_HDR, *PRT_8723B_FIRMWARE_HDR;
+
+#define DRIVER_EARLY_INT_TIME_8195A         0x05 // 5ms
+#define BCN_DMA_ATIME_INT_TIME_8195A        0x02 // 2ms
+
+// for 8195A
+// TX 32K, RX 16K, Page size 128B for TX, 8B for RX
+#define PAGE_SIZE_TX_8195A                  128
+#define PAGE_SIZE_RX_8195A                  8
+
+#define RX_DMA_SIZE_8195A                   0x4000	// 16K
+#define RX_DMA_RESERVED_SIZE_8195A          0x80	// 128B, reserved for tx report
+#define RX_DMA_BOUNDARY_8195A               (RX_DMA_SIZE_8195A - RX_DMA_RESERVED_SIZE_8195A - 1)
+
+
+// Note: We will divide number of page equally for each queue other than public queue!
+
+//For General Reserved Page Number(Beacon Queue is reserved page)
+//Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1
+#ifdef CONFIG_WLAN_HAL_TEST
+#define BCNQ_PAGE_NUM_8195A             0x00
+#else
+#define BCNQ_PAGE_NUM_8195A             0x08
+#endif
+
+#ifdef CONFIG_CONCURRENT_MODE
+#define BCNQ1_PAGE_NUM_8195A            0x04
+#else
+#define BCNQ1_PAGE_NUM_8195A            0x00
+#endif
+
+//For WoWLan , more reserved page
+//ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2
+#ifdef CONFIG_WOWLAN
+#define WOWLAN_PAGE_NUM_8195A           0x07
+#else
+#define WOWLAN_PAGE_NUM_8195A           0x00
+#endif
+
+#ifdef CONFIG_WLAN_HAL_TEST
+#define TX_TOTAL_PAGE_NUMBER_8195A      0x40
+#define TX_PAGE_BOUNDARY_8195A          (TX_TOTAL_PAGE_NUMBER_8195A + 1)
+#else
+#define TX_TOTAL_PAGE_NUMBER_8195A      (0xFF - BCNQ_PAGE_NUM_8195A - BCNQ1_PAGE_NUM_8195A - WOWLAN_PAGE_NUM_8195A)
+#define TX_PAGE_BOUNDARY_8195A          (TX_TOTAL_PAGE_NUMBER_8195A + 1)
+#endif
+
+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER TX_TOTAL_PAGE_NUMBER_8195A
+#define WMM_NORMAL_TX_PAGE_BOUNDARY		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1)
+
+// For Normal Chip Setting
+// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8195A
+#ifdef CONFIG_WLAN_HAL_TEST
+#define NORMAL_PAGE_NUM_HPQ_8195A		0x10
+#define NORMAL_PAGE_NUM_LPQ_8195A		0x10
+#define NORMAL_PAGE_NUM_NPQ_8195A		0x10
+#else
+#define NORMAL_PAGE_NUM_HPQ_8195A		0x0C
+#define NORMAL_PAGE_NUM_LPQ_8195A		0x02
+#define NORMAL_PAGE_NUM_NPQ_8195A		0x02
+#endif
+
+// Note: For Normal Chip Setting, modify later
+#define WMM_NORMAL_PAGE_NUM_HPQ_8195A   0x30
+#define WMM_NORMAL_PAGE_NUM_LPQ_8195A   0x20
+#define WMM_NORMAL_PAGE_NUM_NPQ_8195A   0x20
+
+#include "HalVerDef.h"
+#include "hal_com.h"
+
+#define EFUSE_OOB_PROTECT_BYTES 		(52+28+16+32) // Security + RF + MAC + OTP = 128
+
+#define HWSET_MAX_SIZE_8195A            512
+#define EFUSE_REAL_CONTENT_LEN_8195A    256
+#define EFUSE_MAP_LEN_8195A             512
+#define EFUSE_MAX_SECTION_8195A			64
+
+#define EFUSE_IC_ID_OFFSET			506	//For some inferiority IC purpose. added by Roger, 2009.09.02.
+#define AVAILABLE_EFUSE_ADDR(addr) 	(addr < EFUSE_REAL_CONTENT_LEN_8195A)
+
+#define EFUSE_ACCESS_ON			0x69	// For RTL8723 only.
+#define EFUSE_ACCESS_OFF			0x00	// For RTL8723 only.
+
+#ifdef CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD
+#define LITTLE_WIFI_STACKSIZE           512
+#ifdef PLATFORM_CMSIS_RTOS
+#define LITTLE_WIFI_TASK_PRIORITY       3 // osPriorityRealtime
+#ifdef CONFIG_POWER_SAVING
+#define CHECK_IN_REQ_STATE_STACKSIZE        256
+#define CHECK_IN_REQ_STATE_TASK_PRIORITY    0//osPriorityNormal
+
+#ifdef TDMA_POWER_SAVING
+#define TDMA_CHANGE_STATE_STACKSIZE         256
+#define TDMA_CHANGE_STATE_TASK_PRIORITY     2//osPriorityRealtime
+#endif //#ifdef TDMA_POWER_SAVING
+
+#endif
+#else
+#define LITTLE_WIFI_TASK_PRIORITY       6//TASK_PRORITY_LOW
+
+#ifdef CONFIG_POWER_SAVING
+#define CHECK_IN_REQ_STATE_STACKSIZE        256
+#define CHECK_IN_REQ_STATE_TASK_PRIORITY    1
+
+#ifdef TDMA_POWER_SAVING
+#define TDMA_CHANGE_STATE_STACKSIZE         256
+#define TDMA_CHANGE_STATE_TASK_PRIORITY     3
+#endif //#ifdef TDMA_POWER_SAVING
+
+#endif
+#endif
+#endif
+
+#define LX_DMA_IMR_DISABLED 0
+#define FW_IMR_DISABLED     0
+#define WL_PMC_IMR_DISABLED 0
+
+
+//========================================================
+//			EFUSE for BT definition
+//========================================================
+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
+#define EFUSE_BT_REAL_CONTENT_LEN		1536	// 512*3
+#define EFUSE_BT_MAP_LEN				1024	// 1k bytes
+#define EFUSE_BT_MAX_SECTION			128		// 1024/8
+
+#define EFUSE_PROTECT_BYTES_BANK		16
+
+#define GET_RF_TYPE(priv)			(GET_HAL_DATA(priv)->rf_type)
+
+// Description: Determine the types of C2H events that are the same in driver and Fw.
+// Fisrt constructed by tynli. 2009.10.09.
+typedef enum _C2H_EVT
+{
+	C2H_DBG = 0,
+	C2H_TSF = 1,
+	C2H_AP_RPT_RSP = 2,
+	C2H_CCX_TX_RPT = 3,	// The FW notify the report of the specific tx packet.
+	C2H_BT_RSSI = 4,
+	C2H_BT_OP_MODE = 5,
+	C2H_EXT_RA_RPT = 6,
+	C2H_8723B_BT_INFO = 9,
+	C2H_HW_INFO_EXCH = 10,
+	C2H_8723B_BT_MP_INFO = 11,
+	MAX_C2HEVENT
+} C2H_EVT;
+
+typedef _PACKED struct _C2H_EVT_HDR
+{
+	u8	CmdID;
+	u8	CmdLen;
+	u8	CmdSeq;
+} C2H_EVT_HDR, *PC2H_EVT_HDR;
+
+typedef enum tag_Package_Definition
+{
+	PACKAGE_DEFAULT,
+	PACKAGE_QFN56,
+	PACKAGE_QFN48,
+	PACKAGE_BGA96,
+	PACKAGE_QFN88,
+	PACKAGE_QFN216
+}PACKAGE_TYPE_E;
+
+typedef enum tag_ChipID_Definition
+{
+	CHIPID_8711AM = 0xFF,
+	CHIPID_8195AM = 0xFE,
+	CHIPID_8711AF = 0xFD,
+	CHIPID_8710AF = 0xFC,
+	CHIPID_8711AN = 0xFB,
+	CHIPID_8710AM = 0xFA
+}CHIP_TD_E;
+
+
+#define INCLUDE_MULTI_FUNC_BT(_Adapter)		(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
+#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
+
+//========================================================
+//			TXBD and RXBD definition
+//========================================================
+#ifdef CONFIG_MP_INCLUDED	// For MP Tx no idle
+#define TX_VIQ_DESC_NUM         4
+#define TX_VOQ_DESC_NUM         4
+#define TX_BKQ_DESC_NUM         4
+#define TX_BEQ_DESC_NUM         32
+#else
+#define TX_VIQ_DESC_NUM         4
+#define TX_VOQ_DESC_NUM         4
+#define TX_BKQ_DESC_NUM         4
+#define TX_BEQ_DESC_NUM         4
+#endif
+#define TX_BCNQ_DESC_NUM        2
+#define TX_MGQ_DESC_NUM         4
+#define TX_H0Q_DESC_NUM         2
+#define TX_H1Q_DESC_NUM         2
+#define TX_H2Q_DESC_NUM         2
+#define TX_H3Q_DESC_NUM         2
+#define TX_H4Q_DESC_NUM         2
+#define TX_H5Q_DESC_NUM         2
+#define TX_H6Q_DESC_NUM         2
+#define TX_H7Q_DESC_NUM         2
+#define RX_Q_DESC_NUM           4  //16 Reduce rx desc number due to memory limitation
+
+#define SET_VIQ_DES_NUM     (TX_VIQ_DESC_NUM<<16)
+#define SET_VOQ_DES_NUM     (TX_VOQ_DESC_NUM)
+#define SET_RXQ_DES_NUM     (RX_Q_DESC_NUM<<16)
+#define SET_MGQ_DES_NUM     (TX_MGQ_DESC_NUM)
+#define SET_BKQ_DES_NUM     (TX_BKQ_DESC_NUM<<16)
+#define SET_BEQ_DES_NUM     (TX_BEQ_DESC_NUM)
+#define SET_H1Q_DES_NUM     (TX_H1Q_DESC_NUM<<16)
+#define SET_H0Q_DES_NUM     (TX_H0Q_DESC_NUM)
+#define SET_H3Q_DES_NUM     (TX_H3Q_DESC_NUM<<16)
+#define SET_H2Q_DES_NUM     (TX_H2Q_DESC_NUM)
+#define SET_H5Q_DES_NUM     (TX_H5Q_DESC_NUM<<16)
+#define SET_H4Q_DES_NUM     (TX_H4Q_DESC_NUM)
+#define SET_H7Q_DES_NUM     (TX_H7Q_DESC_NUM<<16)
+#define SET_H6Q_DES_NUM     (TX_H6Q_DESC_NUM)
+
+#define TX_DESC_MODE        1
+
+//0: 2 segment 
+//1: 4 segment 
+//2: 8 segment 
+//#define TX_DESC_MODE            2
+
+#define MAX_TXBD_SEQMENT_NUM    ((TX_DESC_MODE)? (4*TX_DESC_MODE): 2)
+#define TXBD_SEGMENT_SIZE		8
+
+
+
+typedef struct _RXBD_ELEMENT_ {
+    u32         Dword0;
+    u32         PhyAddr;
+}RXBD_ELEMENT,*PRXBD_ELEMENT;
+
+
+typedef struct _TXBD_ELEMENT_ {
+    u32         Dword0;
+    u32         AddrLow;
+}TXBD_ELEMENT,*PTXBD_ELEMENT;
+
+typedef struct _LX_DMA_ELEMENT_ {
+    u32         QueueTRxBdBase;
+    u32         HwIndex;
+    u32         HostIndex;
+    u32         AvaliableCnt;
+}LX_DMA_ELEMENT, *PLX_DMA_ELEMENT;
+#if 1
+
+typedef enum _LX_DMA_QUEUE_TYPE_{
+    VO_QUEUE = 0,
+    VI_QUEUE = 1,
+    BE_QUEUE = 2,
+    BK_QUEUE = 3,
+    MG_QUEUE = 4,
+    RX_QUEUE = 5,
+    H0_QUEUE = 6,
+    H1_QUEUE = 7,
+    H2_QUEUE = 8,
+    H3_QUEUE = 9,
+    H4_QUEUE = 10,
+    H5_QUEUE = 11,
+    H6_QUEUE = 12,
+    H7_QUEUE = 13,
+    BCN_QUEUE = 14,
+    MAX_TX_QUEUE = 15,
+    ERROR_QUEUE = 16,
+}LX_DMA_QUEUE_TYPE, *PLX_DMA_QUEUE_TYPE;
+
+typedef struct _TX_FREE_QUEUE_ {
+    _queue               FreeQueue;
+    u32                  Qlen;
+}TX_FREE_QUEUE, *PTX_FREE_QUEUE;
+
+typedef struct _LX_DMA_MANAGER_ {
+    LX_DMA_ELEMENT       QueueTRxBd[MAX_TX_QUEUE];
+    u32                  QueueMaxValue[MAX_TX_QUEUE];
+    u32                  RxBdSkb[RX_Q_DESC_NUM];
+    u32                  RxLen;
+    u32                  RemainLen;
+    u16                  RxAggregateNum;
+    u16                  RxExpectTag;
+    u16                  RxSegFlow;
+    u16                  Flagls;
+    TX_FREE_QUEUE        TxFreeQueue[MAX_TX_QUEUE];
+    
+}LX_DMA_MANAGER, *PLX_DMA_MANAGER;
+
+#else
+
+typedef struct _LX_DMA_MANAGER_ {
+    u32                 *pVoqTXBD;
+    u32                 *pViqTXBD;
+    u32                 *pBeqTXBD;
+    u32                 *pBkqTXBD;
+    u32                 *pBcnqTXBD;
+    u32                 *pMgqTXBD;
+    u32                 *pH0qTXBD;
+    u32                 *pH1qTXBD;
+    u32                 *pH2qTXBD;
+    u32                 *pH3qTXBD;
+    u32                 *pH4qTXBD;
+    u32                 *pH5qTXBD;
+    u32                 *pH6qTXBD;
+    u32                 *pH7qTXBD;
+    u32                 *pExViqTXBD;
+    u32                 *pExVoqTXBD;
+    u32                 *pExBeqTXBD;
+    u32                 *pExBkqTXBD;
+    u32                 *pExMgqTXBD;
+    u32                 *pRXBD;
+//    u4Byte                  RxAggBufEntry[RX_Q_DESC_NUM];
+//    u4Byte                  RxAggLenEntry[RX_Q_DESC_NUM];
+    u32                  RxLen;
+    u32                  RemainLen;
+    u16                  ViqTxWritePoint;
+    u16                  ViqTxReadPoint;
+    u16                  VoqTxWritePoint;
+    u16                  VoqTxReadPoint;
+    u16                  BeqTxWritePoint;
+    u16                  BeqTxReadPoint;
+    u16                  BkqTxWritePoint;
+    u16                  BkqTxReadPoint;
+    u16                  RxWritePoint;
+    u16                  RxReadPoint;
+    u16                  RxAggregateNum;
+    u16                  RxExpectTag;
+    u16                  RxSegFlow;
+    u16                  Flagls;
+}LX_DMA_MANAGER, *PLX_DMA_MANAGER;
+#endif
+
+// rtl8723a_hal_init.c
+s32 rtl8195a_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
+void rtl8195a_FirmwareSelfReset(PADAPTER padapter);
+void rtl8195a_InitializeFirmwareVars(PADAPTER padapter);
+
+void rtl8195a_InitAntenna_Selection(PADAPTER padapter);
+void rtl8195a_DeinitAntenna_Selection(PADAPTER padapter);
+void rtl8195a_CheckAntenna_Selection(PADAPTER padapter);
+void rtl8195a_init_default_value(PADAPTER padapter);
+
+s32 rtl8195a_InitLLTTable(PADAPTER padapter);
+
+s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
+s32 CardDisableWithoutHWSM(PADAPTER padapter);
+
+// EFuse
+//u8 GetEEPROMSize8195a(PADAPTER padapter);
+void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
+void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
+void Hal_EfuseParseTxPowerInfo_8195A(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseBTCoexistInfo_8195A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseEEPROMVer_8195A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseChnlPlan_8195A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseCustomerID_8195A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseAntennaDiversity_8195A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseXtal_8195A(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
+void Hal_EfuseParseThermalMeter_8195A(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
+
+u8 rtw_flash_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
+u8 rtw_flash_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
+u8 rtw_config_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data, u8 efuse);
+u8 rtw_config_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data, u8 efuse);
+
+void rtl8195a_set_hal_ops(struct hal_ops *pHalFunc);
+void lxbus_set_intf_ops(struct _io_ops	*pops);
+void SetHwReg8195A(PADAPTER padapter, u8 variable, u8 *val);
+void GetHwReg8195A(PADAPTER padapter, u8 variable, u8 *val);
+u8 SetHalDefVar8195A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+u8 GetHalDefVar8195A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+void SetHalODMVar8195A( PADAPTER Adapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet);
+void GetHalODMVar8195A(PADAPTER Adapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN	bSet);
+
+// register
+void rtl8195a_InitBeaconParameters(PADAPTER padapter);
+void rtl8195a_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
+void	_InitBurstPktLen_8195AB(PADAPTER Adapter);
+#ifdef CONFIG_WOWLAN
+void _8051Reset8195a(PADAPTER padapter);
+void Hal_DetectWoWMode(PADAPTER pAdapter);
+#endif //CONFIG_WOWLAN
+
+void rtl8195a_start_thread(_adapter *padapter);
+void rtl8195a_stop_thread(_adapter *padapter);
+
+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
+void rtl8195ab_init_checkbthang_workqueue(_adapter * adapter);
+void rtl8195ab_free_checkbthang_workqueue(_adapter * adapter);
+void rtl8195ab_cancle_checkbthang_workqueue(_adapter * adapter);
+void rtl8195ab_hal_check_bt_hang(_adapter * adapter);
+#endif
+
+#ifdef CONFIG_WOWLAN
+void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip);
+void rtw_get_sec_iv(PADAPTER padapter, u8*pcur_dot11txpn, u8 *StaAddr);
+#endif
+
+#ifdef CONFIG_GPIO_WAKEUP
+void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
+#endif
+
+#ifdef CONFIG_RF_GAIN_OFFSET
+void Hal_ReadRFGainOffset(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail);
+#endif //CONFIG_RF_GAIN_OFFSET
+
+
+//1TODO: Chris
+#if 1
+
+//=============
+// [1] Rx Buffer Descriptor (for PCIE) buffer descriptor architecture
+//DWORD 0
+#define SET_RX_BUFFER_DESC_DATA_LENGTH_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 0, 14, __Value)
+#define SET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc,__Value)	SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 14, 1, __Value)
+#define SET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 15, 1, __Value)
+#define SET_RX_BUFFER_DESC_RX_TAG_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 16, 13, __Value)
+
+#define GET_RX_BUFFER_DESC_OWN_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE( __pRxStatusDesc, 31, 1)
+#define GET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE( __pRxStatusDesc, 14, 1)
+#define GET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE( __pRxStatusDesc, 15, 1)
+#define GET_RX_BUFFER_DESC_RX_TAG_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE( __pRxStatusDesc, 16, 13)
+#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc)LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 14) 
+
+
+//DWORD 1
+#define SET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE( __pRxStatusDesc+4, 0, 32, __Value)
+#define GET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE( __pRxStatusDesc+4, 0, 32)
+
+//DWORD 2
+#define SET_RX_BUFFER_PHYSICAL_HIGH_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE( __pRxStatusDesc+8, 0, 32, __Value)
+
+
+//=====Tx Desc Buffer content
+
+// config element for each tx buffer 
+/*
+#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 0, 16, __Valeu)
+#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 31, 1, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+4, 0, 32, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)
+*/
+#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
+#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)
+
+// Dword 0
+#define SET_TX_BUFF_DESC_LEN_0_92E(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Valeu)
+#define SET_TX_BUFF_DESC_PSB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
+#define SET_TX_BUFF_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+// Dword 1
+#define SET_TX_BUFF_DESC_ADDR_LOW_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
+#define GET_TX_DESC_TX_BUFFER_ADDRESS_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0,32)
+
+
+// Dword 2
+#define SET_TX_BUFF_DESC_ADDR_HIGH_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value)
+// Dword 3, RESERVED 
+
+
+#define SET_TX_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+
+#endif
+
+#endif
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtl8711b_hal.h

@@ -0,0 +1,595 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __RTL8711B_HAL_H__
+#define __RTL8711B_HAL_H__
+
+#include "drv_types.h"
+//#include "rtl8711b/rtl8711b_pmu_task.h"
+#include "hal_data.h"
+
+#include "rtl8711b/rtl8711b_spec.h"
+#include "rtl8711b/rtl8711b_rf.h"
+#include "rtl8711b/rtl8711b_dm.h"
+#include "rtl8711b/rtl8711b_recv.h"
+#include "rtl8711b/rtl8711b_xmit.h"
+#include "rtl8711b/rtl8711b_cmd.h"
+//#include "rtl8711b/rtl8711b_pmu_cmd.h"
+#include "rtl8711b/rtl8711b_led.h"
+#include "rtl8711b/Hal8711BPwrSeq.h"
+#include "rtl8711b/Hal8711BPhyReg.h"
+#include "rtl8711b/Hal8711BPhyCfg.h"
+#include "rtl8711b/rom_Hal8711BPhyCfg.h"
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+#include "rtl8711b/rtl8711b_sreset.h"
+#endif
+
+#include "../src/hal/OUTSRC/phydm_precomp.h"
+
+#if (RTL8711B_SUPPORT==1)
+	//2TODO: We should define 8192S firmware related macro settings here!!
+	#define RTL819X_DEFAULT_RF_TYPE			RF_1T2R
+	#define RTL819X_TOTAL_RF_PATH				2
+
+//---------------------------------------------------------------------
+//		RTL8723BS From file
+//---------------------------------------------------------------------
+	#define RTL8723B_FW_IMG					"rtl8723B\\rtl8723bfw.bin"
+	#define RTL8711B_PHY_REG					"rtl8711B\\PHY_REG_1T.txt"
+	#define RTL8711B_PHY_RADIO_A			"rtl8711B\\radio_a_1T.txt"
+	#define RTL8711B_PHY_RADIO_B			"rtl8711B\\radio_b_1T.txt"
+	#define RTL8711B_TXPWR_TRACK			"rtl8711B\\TxPowerTrack.txt" 
+	#define RTL8711B_AGC_TAB					"rtl8711B\\AGC_TAB_1T.txt"
+	#define RTL8711B_PHY_MACREG				"rtl87195A\\MAC_REG.txt"
+	#define RTL8711B_PHY_REG_PG				"rtl8711B\\PHY_REG_PG.txt"
+	#define RTL8711B_PHY_REG_MP				"rtl8711B\\PHY_REG_MP.txt"
+	#define RTL8711B_TXPWR_LMT 				"rtl8711B\\TXPWR_LMT.txt"
+
+//---------------------------------------------------------------------
+//		RTL8723BS From header
+//---------------------------------------------------------------------
+
+	//#define Rtl8723B_FwImageArray				Array_MP_8723B_FW_NIC
+	//#define Rtl8723B_FwImgArrayLength			ArrayLength_MP_8723B_FW_NIC
+	//#define Rtl8723B_FwWoWImageArray			Array_MP_8723B_FW_WoWLAN
+	//#define Rtl8723B_FwWoWImgArrayLength		ArrayLength_MP_8723B_FW_WoWLAN
+
+	#define Rtl8711B_PHY_REG_Array_PG 			Rtl8723SPHY_REG_Array_PG
+	#define Rtl8711B_PHY_REG_Array_PGLength	Rtl8723SPHY_REG_Array_PGLength
+
+#if MP_DRIVER == 1
+	#define Rtl8711B_FwBTImgArray				Rtl8723BFwBTImgArray
+	#define Rtl8711B_FwBTImgArrayLength		Rtl8723BFwBTImgArrayLength
+
+	#define Rtl8711B_FwMPImageArray			Rtl8723BFwMPImgArray
+	#define Rtl8711B_FwMPImgArrayLength		Rtl8723BMPImgArrayLength
+
+	#define Rtl8711B_PHY_REG_Array_MP			Rtl8723B_PHYREG_Array_MP
+	#define Rtl8711B_PHY_REG_Array_MPLength	Rtl8723B_PHYREG_Array_MPLength
+#endif
+
+#endif // RTL8711B_SUPPORT
+
+#define FW_8711B_SIZE			0x8000
+#define FW_8711B_START_ADDRESS	0x1000
+#define FW_8711B_END_ADDRESS		0x1FFF //0x5FFF
+
+#define IS_FW_HEADER_EXIST_8711B(_pFwHdr)	((GET_FIRMWARE_HDR_SIGNATURE(_pFwHdr)&0xFFF0) == 0x10B0)
+
+typedef struct _RT_FIRMWARE {
+	FIRMWARE_SOURCE	eFWSource;
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8*			szFwBuffer;
+#else
+	u8			szFwBuffer[FW_8711B_SIZE];
+#endif
+	u32			ulFwLength;
+
+#ifdef CONFIG_EMBEDDED_FWIMG
+	u8*			szBTFwBuffer;
+#else
+	u8			szBTFwBuffer[FW_8711B_SIZE];
+#endif
+	u32			ulBTFwLength;
+
+#ifdef CONFIG_WOWLAN
+	u8*			szWoWLANFwBuffer;
+	u32			ulWoWLANFwLength;
+#endif //CONFIG_WOWLAN
+} RT_FIRMWARE_8711B, *PRT_FIRMWARE_8711B;
+
+//
+// This structure must be cared byte-ordering
+//
+// Added by tynli. 2009.12.04.
+typedef struct _RT_8723B_FIRMWARE_HDR
+{
+	// 8-byte alinment required
+
+	//--- LONG WORD 0 ----
+	u16		Signature;	// 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
+	u8		Category;	// AP/NIC and USB/PCI
+	u8		Function;	// Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
+	u16		Version;		// FW Version
+	u8		Subversion;	// FW Subversion, default 0x00
+	u16		Rsvd1;
+
+
+	//--- LONG WORD 1 ----
+	u8		Month;	// Release time Month field
+	u8		Date;	// Release time Date field
+	u8		Hour;	// Release time Hour field
+	u8		Minute;	// Release time Minute field
+	u16		RamCodeSize;	// The size of RAM code
+	u16		Rsvd2;
+
+	//--- LONG WORD 2 ----
+	u32		SvnIdx;	// The SVN entry index
+	u32		Rsvd3;
+
+	//--- LONG WORD 3 ----
+	u32		Rsvd4;
+	u32		Rsvd5;
+}RT_8723B_FIRMWARE_HDR, *PRT_8723B_FIRMWARE_HDR;
+
+#define DRIVER_EARLY_INT_TIME_8711B         0x05 // 5ms
+#define BCN_DMA_ATIME_INT_TIME_8711B        0x02 // 2ms
+
+// for 8711B
+// TX 32K, RX 16K, Page size 128B for TX, 8B for RX
+#define PAGE_SIZE_TX_8711B                  128
+#define PAGE_SIZE_RX_8711B                  8
+
+#define RX_DMA_SIZE_8711B                   0x4000	// 16K
+#define RX_DMA_RESERVED_SIZE_8711B          0x80	// 128B, reserved for tx report
+#define RX_DMA_BOUNDARY_8711B               (RX_DMA_SIZE_8711B - RX_DMA_RESERVED_SIZE_8711B - 1)
+
+// Note: We will divide number of page equally for each queue other than public queue!
+
+//For General Reserved Page Number(Beacon Queue is reserved page)
+//Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1
+#ifdef CONFIG_WLAN_HAL_TEST
+#define BCNQ_PAGE_NUM_8711B             0x00
+#else
+#define BCNQ_PAGE_NUM_8711B             0x08
+#endif
+
+#ifdef CONFIG_CONCURRENT_MODE
+#define BCNQ1_PAGE_NUM_8711B            0x04
+#else
+#define BCNQ1_PAGE_NUM_8711B            0x00
+#endif
+
+//For WoWLan , more reserved page
+//ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2
+#ifdef CONFIG_WOWLAN
+#define WOWLAN_PAGE_NUM_8711B           0x07
+#else
+#define WOWLAN_PAGE_NUM_8711B           0x00
+#endif
+
+#ifdef CONFIG_WLAN_HAL_TEST
+#define TX_TOTAL_PAGE_NUMBER_8711B      (0xF8 - BCNQ_PAGE_NUM_8711B - BCNQ1_PAGE_NUM_8711B - WOWLAN_PAGE_NUM_8711B)
+//#define TX_TOTAL_PAGE_NUMBER_8711B      0x40
+#define TX_PAGE_BOUNDARY_8711B          (TX_TOTAL_PAGE_NUMBER_8711B + 1)
+#else
+#define TX_TOTAL_PAGE_NUMBER_8711B      (0xFF - BCNQ_PAGE_NUM_8711B - BCNQ1_PAGE_NUM_8711B - WOWLAN_PAGE_NUM_8711B)
+#define TX_PAGE_BOUNDARY_8711B          (TX_TOTAL_PAGE_NUMBER_8711B + 1)
+#endif
+
+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER TX_TOTAL_PAGE_NUMBER_8711B
+#define WMM_NORMAL_TX_PAGE_BOUNDARY		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1)
+
+// For Normal Chip Setting
+// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8711B
+#ifdef CONFIG_WLAN_HAL_TEST
+#define NORMAL_PAGE_NUM_HPQ_8711B		0x10
+#define NORMAL_PAGE_NUM_LPQ_8711B		0x10
+#define NORMAL_PAGE_NUM_NPQ_8711B		0x10
+#else
+#define NORMAL_PAGE_NUM_HPQ_8711B		0x0C
+#define NORMAL_PAGE_NUM_LPQ_8711B		0x02
+#define NORMAL_PAGE_NUM_NPQ_8711B		0x02
+#endif
+
+#ifdef CONFIG_WLAN_HAL_TEST
+#define WMM_NORMAL_PAGE_NUM_HPQ_8711B   0x10
+#define WMM_NORMAL_PAGE_NUM_LPQ_8711B   0x10
+#define WMM_NORMAL_PAGE_NUM_NPQ_8711B   0x10
+#else
+// Note: For Normal Chip Setting, modify later
+#define WMM_NORMAL_PAGE_NUM_HPQ_8711B   0x30
+#define WMM_NORMAL_PAGE_NUM_LPQ_8711B   0x20
+#define WMM_NORMAL_PAGE_NUM_NPQ_8711B   0x20
+#endif
+
+#include "HalVerDef.h"
+#include "hal_com.h"
+
+#define LX_DMA_IMR_DISABLED 0
+#define FW_IMR_DISABLED     0
+#define WL_PMC_IMR_DISABLED 0
+
+
+//========================================================
+//			EFUSE for BT definition
+//========================================================
+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
+#define EFUSE_BT_REAL_CONTENT_LEN		1536	// 512*3
+#define EFUSE_BT_MAP_LEN				1024	// 1k bytes
+#define EFUSE_BT_MAX_SECTION			128		// 1024/8
+
+#define EFUSE_PROTECT_BYTES_BANK		16
+
+#define GET_RF_TYPE(priv)			(GET_HAL_DATA(priv)->rf_type)
+
+// Description: Determine the types of C2H events that are the same in driver and Fw.
+// Fisrt constructed by tynli. 2009.10.09.
+typedef enum _C2H_EVT
+{
+	C2H_DBG = 0,
+	C2H_TSF = 1,
+	C2H_AP_RPT_RSP = 2,
+	C2H_CCX_TX_RPT = 3,	// The FW notify the report of the specific tx packet.
+	C2H_BT_RSSI = 4,
+	C2H_BT_OP_MODE = 5,
+	C2H_EXT_RA_RPT = 6,
+	C2H_8723B_BT_INFO = 9,
+	C2H_HW_INFO_EXCH = 10,
+	C2H_8723B_BT_MP_INFO = 11,
+	MAX_C2HEVENT
+} C2H_EVT;
+
+typedef _PACKED struct _C2H_EVT_HDR
+{
+	u8	CmdID;
+	u8	CmdLen;
+	u8	CmdSeq;
+} C2H_EVT_HDR, *PC2H_EVT_HDR;
+
+typedef enum tag_Package_Definition
+{
+	PACKAGE_QFN32,
+	PACKAGE_QFN48_MCM,
+	PACKAGE_QFN48,
+	PACKAGE_QFN68,
+}PACKAGE_TYPE_E;
+
+typedef enum tag_ChipID_Definition
+{
+	CHIPID_8710BN = 0xFF, /* PACKAGE_QFN32 */
+	CHIPID_8710BU = 0xFE, /* PACKAGE_QFN48_MCM */
+	CHIPID_8711BN = 0xFD, /* PACKAGE_QFN48 */
+	CHIPID_8711BG = 0xFC, /* PACKAGE_QFN68 */
+}CHIP_TD_E;
+
+
+#define INCLUDE_MULTI_FUNC_BT(_Adapter)		(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
+#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
+
+//========================================================
+//			TXBD and RXBD definition
+//========================================================
+#ifdef CONFIG_MP_INCLUDED	// For MP Tx no idle
+#define TX_VIQ_DESC_NUM         4
+#define TX_VOQ_DESC_NUM         4
+#define TX_BKQ_DESC_NUM         4
+#define TX_BEQ_DESC_NUM         32
+#else
+#define TX_VIQ_DESC_NUM         4
+#define TX_VOQ_DESC_NUM         4
+#define TX_BKQ_DESC_NUM         4
+#define TX_BEQ_DESC_NUM         4
+#endif
+#ifdef CONFIG_CONCURRENT_MODE
+#define TX_BCNQ_DESC_NUM        4
+#else
+#define TX_BCNQ_DESC_NUM        2
+#endif
+#define TX_MGQ_DESC_NUM         4
+#define TX_H0Q_DESC_NUM         2
+#define TX_H1Q_DESC_NUM         2
+#define TX_H2Q_DESC_NUM         2
+#define TX_H3Q_DESC_NUM         2
+#define TX_H4Q_DESC_NUM         2
+#define TX_H5Q_DESC_NUM         2
+#define TX_H6Q_DESC_NUM         2
+#define TX_H7Q_DESC_NUM         2
+#define RX_Q_DESC_NUM           4  //16 Reduce rx desc number due to memory limitation
+
+#define SET_VIQ_DES_NUM     (TX_VIQ_DESC_NUM<<16)
+#define SET_VOQ_DES_NUM     (TX_VOQ_DESC_NUM)
+#define SET_RXQ_DES_NUM     (RX_Q_DESC_NUM<<16)
+#define SET_MGQ_DES_NUM     (TX_MGQ_DESC_NUM)
+#define SET_BKQ_DES_NUM     (TX_BKQ_DESC_NUM<<16)
+#define SET_BEQ_DES_NUM     (TX_BEQ_DESC_NUM)
+#define SET_H1Q_DES_NUM     (TX_H1Q_DESC_NUM<<16)
+#define SET_H0Q_DES_NUM     (TX_H0Q_DESC_NUM)
+#define SET_H3Q_DES_NUM     (TX_H3Q_DESC_NUM<<16)
+#define SET_H2Q_DES_NUM     (TX_H2Q_DESC_NUM)
+#define SET_H5Q_DES_NUM     (TX_H5Q_DESC_NUM<<16)
+#define SET_H4Q_DES_NUM     (TX_H4Q_DESC_NUM)
+#define SET_H7Q_DES_NUM     (TX_H7Q_DESC_NUM<<16)
+#define SET_H6Q_DES_NUM     (TX_H6Q_DESC_NUM)
+
+#define TX_DESC_MODE        1
+
+//0: 2 segment 
+//1: 4 segment 
+//2: 8 segment 
+//#define TX_DESC_MODE            2
+
+#define MAX_TXBD_SEQMENT_NUM    ((TX_DESC_MODE)? (4*TX_DESC_MODE): 2)
+#define TXBD_SEGMENT_SIZE		8
+
+
+
+typedef struct _RXBD_ELEMENT_ {
+    u32         Dword0;
+    u32         PhyAddr;
+}RXBD_ELEMENT,*PRXBD_ELEMENT;
+
+
+typedef struct _TXBD_ELEMENT_ {
+    u32         Dword0;
+    u32         AddrLow;
+}TXBD_ELEMENT,*PTXBD_ELEMENT;
+
+typedef struct _LX_DMA_ELEMENT_ {
+    u32         QueueTRxBdBase;
+    u32         HwIndex;
+    u32         HostIndex;
+    u32         AvaliableCnt;
+}LX_DMA_ELEMENT, *PLX_DMA_ELEMENT;
+#if 1
+
+typedef enum _LX_DMA_QUEUE_TYPE_{
+    VO_QUEUE = 0,
+    VI_QUEUE = 1,
+    BE_QUEUE = 2,
+    BK_QUEUE = 3,
+    MG_QUEUE = 4,
+    RX_QUEUE = 5,
+    H0_QUEUE = 6,
+    H1_QUEUE = 7,
+    H2_QUEUE = 8,
+    H3_QUEUE = 9,
+    H4_QUEUE = 10,
+    H5_QUEUE = 11,
+    H6_QUEUE = 12,
+    H7_QUEUE = 13,
+    BCN_QUEUE = 14,
+    MAX_TX_QUEUE = 15,
+    ERROR_QUEUE = 16,
+}LX_DMA_QUEUE_TYPE, *PLX_DMA_QUEUE_TYPE;
+
+typedef struct _TX_FREE_QUEUE_ {
+    _queue               FreeQueue;
+    u32                  Qlen;
+}TX_FREE_QUEUE, *PTX_FREE_QUEUE;
+
+typedef struct _LX_DMA_MANAGER_ {
+    LX_DMA_ELEMENT       QueueTRxBd[MAX_TX_QUEUE];
+    u32                  QueueMaxValue[MAX_TX_QUEUE];
+    u32                  RxBdSkb[RX_Q_DESC_NUM];
+    u32                  RxLen;
+    u32                  RemainLen;
+    u16                  RxAggregateNum;
+    u16                  RxExpectTag;
+    u16                  RxSegFlow;
+    u16                  Flagls;
+    TX_FREE_QUEUE        TxFreeQueue[MAX_TX_QUEUE];
+    
+}LX_DMA_MANAGER, *PLX_DMA_MANAGER;
+
+#else
+
+typedef struct _LX_DMA_MANAGER_ {
+    u32                 *pVoqTXBD;
+    u32                 *pViqTXBD;
+    u32                 *pBeqTXBD;
+    u32                 *pBkqTXBD;
+    u32                 *pBcnqTXBD;
+    u32                 *pMgqTXBD;
+    u32                 *pH0qTXBD;
+    u32                 *pH1qTXBD;
+    u32                 *pH2qTXBD;
+    u32                 *pH3qTXBD;
+    u32                 *pH4qTXBD;
+    u32                 *pH5qTXBD;
+    u32                 *pH6qTXBD;
+    u32                 *pH7qTXBD;
+    u32                 *pExViqTXBD;
+    u32                 *pExVoqTXBD;
+    u32                 *pExBeqTXBD;
+    u32                 *pExBkqTXBD;
+    u32                 *pExMgqTXBD;
+    u32                 *pRXBD;
+//    u4Byte                  RxAggBufEntry[RX_Q_DESC_NUM];
+//    u4Byte                  RxAggLenEntry[RX_Q_DESC_NUM];
+    u32                  RxLen;
+    u32                  RemainLen;
+    u16                  ViqTxWritePoint;
+    u16                  ViqTxReadPoint;
+    u16                  VoqTxWritePoint;
+    u16                  VoqTxReadPoint;
+    u16                  BeqTxWritePoint;
+    u16                  BeqTxReadPoint;
+    u16                  BkqTxWritePoint;
+    u16                  BkqTxReadPoint;
+    u16                  RxWritePoint;
+    u16                  RxReadPoint;
+    u16                  RxAggregateNum;
+    u16                  RxExpectTag;
+    u16                  RxSegFlow;
+    u16                  Flagls;
+}LX_DMA_MANAGER, *PLX_DMA_MANAGER;
+#endif
+
+// rtl8723a_hal_init.c
+s32 rtl8711b_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
+void rtl8711b_FirmwareSelfReset(PADAPTER padapter);
+void rtl8711b_InitializeFirmwareVars(PADAPTER padapter);
+
+void rtl8711b_InitAntenna_Selection(PADAPTER padapter);
+void rtl8711b_DeinitAntenna_Selection(PADAPTER padapter);
+void rtl8711b_CheckAntenna_Selection(PADAPTER padapter);
+void rtl8711b_init_default_value(PADAPTER padapter);
+
+s32 rtl8711b_InitLLTTable(PADAPTER padapter);
+
+s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
+s32 CardDisableWithoutHWSM(PADAPTER padapter);
+
+// EFuse
+//u8 GetEEPROMSize8711b(PADAPTER padapter);
+void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
+void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
+void Hal_EfuseParseTxPowerInfo_8711B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseBTCoexistInfo_8711B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseEEPROMVer_8711B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseChnlPlan_8711B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseCustomerID_8711B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseAntennaDiversity_8711B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
+void Hal_EfuseParseXtal_8711B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
+void Hal_EfuseParseThermalMeter_8711B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
+
+#ifdef CONFIG_C2H_PACKET_EN
+void C2HPacketHandler_8711B(PADAPTER padapter, u8 *pbuffer, u16 length);
+#endif
+
+u8 rtw_flash_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
+u8 rtw_flash_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
+u8 rtw_config_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data, u8 efuse);
+u8 rtw_config_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data, u8 efuse);
+
+void rtl8711b_set_hal_ops(struct hal_ops *pHalFunc);
+void lxbus_set_intf_ops(struct _io_ops	*pops);
+void SetHwReg8711B(PADAPTER padapter, u8 variable, u8 *val);
+void GetHwReg8711B(PADAPTER padapter, u8 variable, u8 *val);
+u8 SetHalDefVar8711B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+u8 GetHalDefVar8711B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
+void SetHalODMVar8711B( PADAPTER Adapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet);
+void GetHalODMVar8711B(PADAPTER Adapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN	bSet);
+
+// register
+void rtl8711b_InitBeaconParameters(PADAPTER padapter);
+void rtl8711b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
+void	_InitBurstPktLen_8711BB(PADAPTER Adapter);
+#ifdef CONFIG_WOWLAN
+void _8051Reset8711b(PADAPTER padapter);
+void Hal_DetectWoWMode(PADAPTER pAdapter);
+#endif //CONFIG_WOWLAN
+
+void rtl8711b_start_thread(_adapter *padapter);
+void rtl8711b_stop_thread(_adapter *padapter);
+
+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
+void rtl8711bb_init_checkbthang_workqueue(_adapter * adapter);
+void rtl8711bb_free_checkbthang_workqueue(_adapter * adapter);
+void rtl8711bb_cancle_checkbthang_workqueue(_adapter * adapter);
+void rtl8711bb_hal_check_bt_hang(_adapter * adapter);
+#endif
+
+#ifdef CONFIG_WOWLAN
+void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip);
+void rtw_get_sec_iv(PADAPTER padapter, u8*pcur_dot11txpn, u8 *StaAddr);
+#endif
+
+u32 rtl8710b_wlan_suspend(u32 expected_idle_time, void *param);
+u32 rtl8710b_wlan_late_resume(u32 expected_idle_time, void *param);
+u32 rtl8710b_wlan_resume(u32 expected_idle_time, void *param);
+
+#ifdef CONFIG_GPIO_WAKEUP
+void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
+#endif
+
+void CCX_FwC2HTxRpt_8711B(PADAPTER padapter, u8 *pdata, u8 len);
+s32 c2h_id_filter_ccx_8711B(u8 *buf);
+s32 c2h_handler_8711B(PADAPTER padapter, u8 *pC2hEvent);
+u8 MRateToHwRate8723B(u8  rate);
+u8 HwRateToMRate8723B(u8	 rate);
+
+#ifdef CONFIG_RF_GAIN_OFFSET
+void Hal_ReadRFGainOffset(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail);
+#endif //CONFIG_RF_GAIN_OFFSET
+
+
+//1TODO: Chris
+#if 1
+
+//=============
+// [1] Rx Buffer Descriptor (for PCIE) buffer descriptor architecture
+//DWORD 0
+#define SET_RX_BUFFER_DESC_DATA_LENGTH_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 0, 14, __Value)
+#define SET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc,__Value)	SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 14, 1, __Value)
+#define SET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 15, 1, __Value)
+#define SET_RX_BUFFER_DESC_RX_TAG_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 16, 13, __Value)
+
+#define GET_RX_BUFFER_DESC_OWN_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE( __pRxStatusDesc, 31, 1)
+#define GET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE( __pRxStatusDesc, 14, 1)
+#define GET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE( __pRxStatusDesc, 15, 1)
+#define GET_RX_BUFFER_DESC_RX_TAG_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE( __pRxStatusDesc, 16, 13)
+#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc)LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 14) 
+
+
+//DWORD 1
+#define SET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE( __pRxStatusDesc+4, 0, 32, __Value)
+#define GET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE( __pRxStatusDesc+4, 0, 32)
+
+//DWORD 2
+#define SET_RX_BUFFER_PHYSICAL_HIGH_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE( __pRxStatusDesc+8, 0, 32, __Value)
+
+
+//=====Tx Desc Buffer content
+
+// config element for each tx buffer 
+/*
+#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 0, 16, __Valeu)
+#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 31, 1, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+4, 0, 32, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)
+*/
+#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
+#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
+#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)
+
+// Dword 0
+#define SET_TX_BUFF_DESC_LEN_0_92E(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Valeu)
+#define SET_TX_BUFF_DESC_PSB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
+#define SET_TX_BUFF_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+// Dword 1
+#define SET_TX_BUFF_DESC_ADDR_LOW_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
+#define GET_TX_DESC_TX_BUFFER_ADDRESS_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0,32)
+
+
+// Dword 2
+#define SET_TX_BUFF_DESC_ADDR_HIGH_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value)
+// Dword 3, RESERVED 
+
+
+#define SET_TX_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
+
+#endif
+
+#endif
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_ap.h

@@ -0,0 +1,65 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __RTW_AP_H_
+#define __RTW_AP_H_
+
+//#include <drv_types.h>
+
+
+#ifdef CONFIG_AP_MODE
+
+//external function
+extern void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta);
+extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta);
+
+
+void init_mlme_ap_info(_adapter *padapter);
+void free_mlme_ap_info(_adapter *padapter);
+//void update_BCNTIM(_adapter *padapter);
+void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len);
+void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index);
+void update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx);
+void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level);
+void expire_timeout_chk(_adapter *padapter);
+void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta);
+int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf,  int len);
+void rtw_set_macaddr_acl(_adapter *padapter, int mode);
+int rtw_acl_add_sta(_adapter *padapter, u8 *addr);
+int rtw_acl_remove_sta(_adapter *padapter, u8 *addr);
+int rtw_generate_bcn_ie(_adapter *adapter, u8 *ssid, u16 ssid_len, u8 *ie);
+#if USE_DEDICATED_BCN_TX
+struct xmit_frame *alloc_bcn_xmitframe(_adapter *padapter);
+#endif
+
+#ifdef CONFIG_NATIVEAP_MLME
+void associated_clients_update(_adapter *padapter, u8 updated);
+void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta);
+u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta);
+void sta_info_update(_adapter *padapter, struct sta_info *psta);
+void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta);
+u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, u16 reason);
+int rtw_sta_flush(_adapter *padapter);
+void start_ap_mode(_adapter *padapter);
+void stop_ap_mode(_adapter *padapter);
+#endif
+#endif //end of CONFIG_AP_MODE
+
+#endif
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_byteorder.h

@@ -0,0 +1,53 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef _RTL871X_BYTEORDER_H_
+#define _RTL871X_BYTEORDER_H_
+
+#include <drv_conf.h>
+
+#if defined (CONFIG_LITTLE_ENDIAN) && defined (CONFIG_BIG_ENDIAN)
+#error "Shall be CONFIG_LITTLE_ENDIAN or CONFIG_BIG_ENDIAN, but not both!\n"
+#endif
+
+#if defined (CONFIG_LITTLE_ENDIAN)
+#ifndef CONFIG_PLATFORM_MSTAR389
+#  include <byteorder/little_endian.h>
+#endif
+#elif defined (CONFIG_BIG_ENDIAN)
+#  include <byteorder/big_endian.h>
+#else
+#  error "Must be LITTLE/BIG Endian Host"
+#endif
+
+#ifdef CONFIG_BIG_ENDIAN
+#define _htons(x) (x)
+#define _ntohs(x) (x)
+#define _htonl(x) (x)
+#define _ntohl(x) (x)
+#else /* !CONFIG_BIG_ENDIAN */
+u16 _htons(u16 x);
+u16 _ntohs(u16 x);
+u32 _htonl(u32 x);
+u32 _ntohl(u32 x);
+#endif /* CONFIG_BIG_ENDIAN */
+
+
+#endif /* _RTL871X_BYTEORDER_H_ */
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_debug.h

@@ -181,7 +181,7 @@ extern void rtl871x_cedbg(const char *fmt, ...);
 	#define _dbgdump	printk
 #elif defined PLATFORM_ECOS
 	#define _dbgdump	diag_printf
-#elif defined PLATFORM_FREERTOS
+#elif defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
 	#define _dbgdump	printf("\n\r"); printf
 #elif defined PLATFORM_FREEBSD
 	#define _dbgdump	printf
@@ -194,7 +194,7 @@ extern void rtl871x_cedbg(const char *fmt, ...);
 #define DEBUG_LEVEL	(_drv_err_)
 #if 	defined (_dbgdump)
 	#undef DBG_871X_LEVEL
-#if defined (__ICCARM__) || defined (__CC_ARM) || defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
+#if defined (__ICCARM__) || defined (__CC_ARM) ||defined(__GNUC__)|| defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
 	#define DBG_871X_LEVEL(level, ...)     \
 	do {\
 		_dbgdump(DRIVER_PREFIX __VA_ARGS__);\

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_eeprom.h

@@ -0,0 +1,158 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __RTW_EEPROM_H__
+#define __RTW_EEPROM_H__
+
+#define	RTL8712_EEPROM_ID			0x8712
+//#define	EEPROM_MAX_SIZE			256
+
+#define	HWSET_MAX_SIZE_512		512
+#define	EEPROM_MAX_SIZE			HWSET_MAX_SIZE_512
+
+#define	CLOCK_RATE					50			//100us		
+
+//- EEPROM opcodes
+#define EEPROM_READ_OPCODE		06
+#define EEPROM_WRITE_OPCODE		05
+#define EEPROM_ERASE_OPCODE		07
+#define EEPROM_EWEN_OPCODE		19      // Erase/write enable
+#define EEPROM_EWDS_OPCODE		16      // Erase/write disable
+
+//Country codes
+#define USA							0x555320
+#define EUROPE						0x1 //temp, should be provided later	
+#define JAPAN						0x2 //temp, should be provided later
+
+#define	EEPROM_CID_DEFAULT			0x0
+#define	EEPROM_CID_ALPHA				0x1
+#define	EEPROM_CID_Senao				0x3
+#define	EEPROM_CID_NetCore				0x5
+#define	EEPROM_CID_CAMEO				0X8
+#define	EEPROM_CID_SITECOM				0x9
+#define	EEPROM_CID_COREGA				0xB
+#define	EEPROM_CID_EDIMAX_BELKIN		0xC
+#define	EEPROM_CID_SERCOMM_BELKIN		0xE
+#define	EEPROM_CID_CAMEO1				0xF
+#define	EEPROM_CID_WNC_COREGA		0x12
+#define	EEPROM_CID_CLEVO				0x13
+#define	EEPROM_CID_WHQL				0xFE // added by chiyoko for dtm, 20090108
+
+//
+// Customer ID, note that: 
+// This variable is initiailzed through EEPROM or registry, 
+// however, its definition may be different with that in EEPROM for 
+// EEPROM size consideration. So, we have to perform proper translation between them.
+// Besides, CustomerID of registry has precedence of that of EEPROM.
+// defined below. 060703, by rcnjko.
+//
+typedef enum _RT_CUSTOMER_ID
+{
+	RT_CID_DEFAULT = 0,
+	RT_CID_8187_ALPHA0 = 1,
+	RT_CID_8187_SERCOMM_PS = 2,
+	RT_CID_8187_HW_LED = 3,
+	RT_CID_8187_NETGEAR = 4,
+	RT_CID_WHQL = 5,
+	RT_CID_819x_CAMEO  = 6, 
+	RT_CID_819x_RUNTOP = 7,
+	RT_CID_819x_Senao = 8,
+	RT_CID_TOSHIBA = 9,	// Merge by Jacken, 2008/01/31.
+	RT_CID_819x_Netcore = 10,
+	RT_CID_Nettronix = 11,
+	RT_CID_DLINK = 12,
+	RT_CID_PRONET = 13,
+	RT_CID_COREGA = 14,
+	RT_CID_CHINA_MOBILE = 15,
+	RT_CID_819x_ALPHA = 16,
+	RT_CID_819x_Sitecom = 17,
+	RT_CID_CCX = 18, // It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17.
+	RT_CID_819x_Lenovo = 19,	
+	RT_CID_819x_QMI = 20,
+	RT_CID_819x_Edimax_Belkin = 21,		
+	RT_CID_819x_Sercomm_Belkin = 22,			
+	RT_CID_819x_CAMEO1 = 23,
+	RT_CID_819x_MSI = 24,
+	RT_CID_819x_Acer = 25,
+	RT_CID_819x_AzWave_ASUS = 26,
+	RT_CID_819x_AzWave = 27, // For AzWave in PCIe, The ID is AzWave use and not only Asus
+	RT_CID_819x_HP = 28,
+	RT_CID_819x_WNC_COREGA = 29,
+	RT_CID_819x_Arcadyan_Belkin = 30,
+	RT_CID_819x_SAMSUNG = 31,
+	RT_CID_819x_CLEVO = 32,
+	RT_CID_819x_DELL = 33,
+	RT_CID_819x_PRONETS = 34,
+	RT_CID_819x_Edimax_ASUS = 35,
+	RT_CID_819x_CAMEO_NETGEAR = 36,
+	RT_CID_PLANEX = 37,
+	RT_CID_CC_C = 38,
+	RT_CID_819x_Xavi = 39,
+	RT_CID_819x_FUNAI_TV = 40,
+	RT_CID_819x_ALPHA_WD=41,
+}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
+
+struct eeprom_priv 
+{    
+	u8		bautoload_fail_flag;
+	//u8		bempty;
+	//u8		sys_config;
+	u8		mac_addr[6];	//PermanentAddress
+	//u8		config0;
+//	u16		channel_plan;
+	u16		CustomerID;
+	//u8		country_string[3];	
+	//u8		tx_power_b[15];
+	//u8		tx_power_g[15];
+	//u8		tx_power_a[201];
+
+	u8		EepromOrEfuse;
+#ifdef CONFIG_MEMORY_ACCESS_ALIGNED
+	u8		rsvd;	//For byte aligned. By Fangyuan, 141201
+#endif
+	u8		efuse_eeprom_data[HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
+
+#ifdef CONFIG_RF_GAIN_OFFSET
+	u8		EEPROMRFGainOffset;
+	u8		EEPROMRFGainVal;
+#endif //CONFIG_RF_GAIN_OFFSET
+};
+
+//TODO
+#if 0
+
+extern void eeprom_write16(_adapter *padapter, u16 reg, u16 data);
+extern u16 eeprom_read16(_adapter *padapter, u16 reg);
+extern void read_eeprom_content(_adapter *padapter);
+extern void eeprom_read_sz(_adapter * padapter, u16 reg,u8* data, u32 sz); 
+
+extern void read_eeprom_content_by_attrib(_adapter *	padapter	);
+
+#ifdef PLATFORM_LINUX
+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
+extern int isAdaptorInfoFileValid(void);
+extern int storeAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv);
+extern int retriveAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv);
+#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE
+#endif //PLATFORM_LINUX
+
+#endif	//#if 0
+
+#endif  //__RTL871X_EEPROM_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_efuse.h

@@ -0,0 +1,163 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __RTW_EFUSE_H__
+#define __RTW_EFUSE_H__
+
+#if (RTL8195A_SUPPORT == 1)
+#include "rtl8195a.h"
+#endif
+#if (RTL8711B_SUPPORT == 1)
+#include "ameba_soc.h"
+#endif
+/*--------------------------Define efuse Parameters-------------------------*/
+#define	EFUSE_ERROE_HANDLE		1
+
+#define	PG_STATE_HEADER 		0x01
+#define	PG_STATE_WORD_0			0x02
+#define	PG_STATE_WORD_1			0x04
+#define	PG_STATE_WORD_2			0x08
+#define	PG_STATE_WORD_3			0x10
+#define	PG_STATE_DATA			0x20
+
+#define	PG_SWBYTE_H				0x01
+#define	PG_SWBYTE_L				0x02
+
+#define	PGPKT_DATA_SIZE			8
+
+#define	EFUSE_WIFI				0
+#define	EFUSE_BT				1
+
+enum _EFUSE_DEF_TYPE {
+	TYPE_EFUSE_MAX_SECTION				= 0,
+	TYPE_EFUSE_REAL_CONTENT_LEN			= 1,
+	TYPE_AVAILABLE_EFUSE_BYTES_BANK		= 2,
+	TYPE_AVAILABLE_EFUSE_BYTES_TOTAL	= 3,
+	TYPE_EFUSE_MAP_LEN					= 4,
+	TYPE_EFUSE_PROTECT_BYTES_BANK		= 5,
+	TYPE_EFUSE_CONTENT_LEN_BANK			= 6,
+};
+
+#define EFUSE_MAP_SIZE			512
+#define EFUSE_MAX_SIZE			256
+
+#define	EFUSE_MAX_MAP_LEN		512
+#define	EFUSE_MAX_HW_SIZE		256
+#define	EFUSE_MAX_SECTION_BASE	16
+
+#define EXT_HEADER(header) ((header & 0x1F ) == 0x0F)
+#define ALL_WORDS_DISABLED(wde)	((wde & 0x0F) == 0x0F)
+#define GET_HDR_OFFSET_2_0(header) ( (header & 0xE0) >> 5)
+
+#define		EFUSE_REPEAT_THRESHOLD_		3
+#define		EFUSE_MAX_WORD_UNIT			4
+
+//=============================================
+//	The following is for BT Efuse definition
+//=============================================
+#define		EFUSE_BT_MAX_MAP_LEN	1024
+#define		EFUSE_MAX_BANK			4
+#define		EFUSE_MAX_BT_BANK		(EFUSE_MAX_BANK-1)
+//=============================================
+
+/*--------------------------Define flash Parameters-------------------------*/
+#if CONFIG_ADAPTOR_INFO_CACHING_FLASH
+#if defined CONFIG_RTL8195A || defined(CONFIG_RTL8711B)
+	#define FLASH_MAX_SIZE			FLASH_CAL_DATA_SIZE
+	#define FLASH_MAGIC_NUMBER		0x8195 // magic number
+	#define FLASH_HEADER_SIZE		4 // 2: address, 2: length
+#endif
+#endif // CONFIG_ADAPTOR_INFO_CACHING_FLASH
+/*------------------------------Define structure----------------------------*/ 
+typedef struct PG_PKT_STRUCT_A{
+	u8 offset;
+	u8 word_en;
+	u8 data[8];	
+	u8 word_cnts;
+}PGPKT_STRUCT,*PPGPKT_STRUCT;
+
+#ifdef HAL_EFUSE_MEMORY
+typedef struct _EFUSE_HAL{
+	u8	fakeEfuseBank;
+	u32	fakeEfuseUsedBytes;
+	u8	fakeEfuseContent[EFUSE_MAX_HW_SIZE];
+	u8	fakeEfuseInitMap[EFUSE_MAX_MAP_LEN];
+	u8	fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN];
+	
+	u16	BTEfuseUsedBytes;
+	u8	BTEfuseUsedPercentage;
+	u8	BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
+	u8	BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN];
+	u8	BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN];
+
+	u16	fakeBTEfuseUsedBytes;
+	u8	fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
+	u8	fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN];
+	u8	fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN];
+}EFUSE_HAL, *PEFUSE_HAL;
+#endif // HAL_EFUSE_MEMORY
+
+/*------------------------Export global variable----------------------------*/
+#if CONFIG_FAKE_EFUSE
+extern u8 fakeEfuseBank;
+extern u32 fakeEfuseUsedBytes;
+extern u8 fakeEfuseContent[];
+extern u8 fakeEfuseInitMap[];
+extern u8 fakeEfuseModifiedMap[];
+#endif
+
+#ifdef CONFIG_BT_COEXIST
+extern u32 BTEfuseUsedBytes;
+extern u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
+extern u8 BTEfuseInitMap[];
+extern u8 BTEfuseModifiedMap[];
+#if CONFIG_FAKE_EFUSE
+extern u32 fakeBTEfuseUsedBytes;
+extern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
+extern u8 fakeBTEfuseInitMap[];
+extern u8 fakeBTEfuseModifiedMap[];
+#endif
+#endif
+
+/*------------------------Export global variable----------------------------*/
+
+u8	efuse_GetCurrentSize(_adapter * padapter, u16 *size);
+u8	rtw_efuse_access(_adapter * padapter, u8 bRead, u16 start_addr, u16 cnts, u8 *data);
+u8	rtw_efuse_map_read(_adapter * padapter, u16 addr, u16 cnts, u8 *data);
+u8	rtw_efuse_map_write(_adapter * padapter, u16 addr, u16 cnts, u8 *data);
+u8	rtw_BT_efuse_map_read(_adapter * padapter, u16 addr, u16 cnts, u8 *data);
+u8 	rtw_BT_efuse_map_write(_adapter * padapter, u16 addr, u16 cnts, u8 *data);
+
+u16	Efuse_GetCurrentSize(_adapter * pAdapter, u8 efuseType, BOOLEAN bPseudoTest);
+u8	Efuse_CalculateWordCnts(u8 word_en);
+void	EFUSE_GetEfuseDefinition(_adapter * pAdapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);
+u8	efuse_OneByteRead(_adapter * pAdapter, u16 addr, u8 *data, BOOLEAN	 bPseudoTest);
+u8	efuse_OneByteWrite(_adapter * pAdapter, u16 addr, u8 data, BOOLEAN	 bPseudoTest);
+
+void	Efuse_PowerSwitch(_adapter * pAdapter,u8	bWrite,u8	 PwrState);
+//int 	Efuse_PgPacketRead(_adapter * pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
+int 	Efuse_PgPacketWrite(_adapter * pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
+void	efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata);
+u8	Efuse_WordEnableDataWrite(_adapter * pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
+
+void	EFUSE_ShadowMapUpdate(_adapter * pAdapter, u8 efuseType, BOOLEAN bPseudoTest);
+void	EFUSE_ShadowRead(_adapter * pAdapter, u8 Type, u16 Offset, u32 *Value);
+
+#endif
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_event.h

@@ -0,0 +1,151 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef _RTW_EVENT_H_
+#define _RTW_EVENT_H_
+
+#ifndef CONFIG_RTL8711FW
+#ifdef PLATFORM_LINUX
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26))
+#include <asm/semaphore.h>
+#else
+#include <linux/semaphore.h>
+#endif
+#include <linux/sem.h>
+#endif
+#endif//CONFIG_RTL8711FW
+
+
+
+#ifdef CONFIG_H2CLBK
+#include <h2clbk.h>
+#endif
+
+/*
+Used to report a bss has been scanned
+
+*/
+struct survey_event	{
+	WLAN_BSSID_EX bss;
+};
+
+/*
+Used to report that the requested site survey has been done.
+
+bss_cnt indicates the number of bss that has been reported.
+
+
+*/
+struct surveydone_event {
+	unsigned int	bss_cnt;	
+	
+};
+
+/*
+Used to report the link result of joinning the given bss
+
+
+join_res:
+-1: authentication fail
+-2: association fail
+> 0: TID
+
+*/
+struct joinbss_event {
+	//struct	wlan_network	network;
+	int join_res;
+};
+
+/*
+Used to report a given STA has joinned the created BSS.
+It is used in AP/Ad-HoC(M) mode.
+
+
+*/
+struct stassoc_event {
+	unsigned char macaddr[6];
+	unsigned char rsvd[2];
+	int    cam_id;
+	
+};
+
+struct stadel_event {
+ unsigned char macaddr[6];
+ unsigned char rsvd[2]; //for reason
+ int mac_id;
+};
+
+struct addba_event
+{
+ 	unsigned int tid;
+};
+
+
+#ifdef CONFIG_H2CLBK
+struct c2hlbk_event{
+	unsigned char mac[6];
+	unsigned short	s0;
+	unsigned short	s1;
+	unsigned int	w0;
+	unsigned char	b0;
+	unsigned short  s2;
+	unsigned char	b1;
+	unsigned int	w1;	
+};
+#endif//CONFIG_H2CLBK
+
+#define GEN_EVT_CODE(event)	event ## _EVT_
+
+struct fwevent {
+	u32	parmsize;
+	void (*event_callback)(_adapter *dev, u8 *pbuf);
+};
+
+//TODO
+#if 0
+
+#define C2HEVENT_SZ			32	
+
+struct event_node{
+	unsigned char *node;
+	unsigned char evt_code;
+	unsigned short evt_sz;
+	volatile int	*caller_ff_tail;
+	int	caller_ff_sz;
+};
+
+struct c2hevent_queue {
+	volatile int	head;
+	volatile int	tail;
+	struct	event_node	nodes[C2HEVENT_SZ];
+	unsigned char	seq;
+};
+
+#define NETWORK_QUEUE_SZ	4
+
+struct network_queue {
+	volatile int	head;
+	volatile int	tail;
+	WLAN_BSSID_EX networks[NETWORK_QUEUE_SZ];	
+};
+
+#endif	//#if 0
+
+#endif // _WLANEVENT_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_ht.h

@@ -0,0 +1,66 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef _RTW_HT_H_
+#define _RTW_HT_H_
+
+#include "wifi.h"
+
+struct ht_priv
+{
+	u32	ht_option;	
+	u32	ampdu_enable;//for enable Tx A-MPDU
+	//u8	baddbareq_issued[16];
+	//u32	tx_amsdu_enable;//for enable Tx A-MSDU
+	//u32	tx_amdsu_maxlen; // 1: 8k, 0:4k ; default:8k, for tx
+	//u32	rx_ampdu_maxlen; //for rx reordering ctrl win_sz, updated when join_callback.
+	
+	u8	bwmode;//
+	u8	ch_offset;//PRIME_CHNL_OFFSET
+	u8	sgi;//short GI
+
+	//for processing Tx A-MPDU
+	u8	agg_enable_bitmap;
+	//u8	ADDBA_retry_count;
+	u8	candidate_tid_bitmap;
+
+	u8	stbc_cap;
+	
+	struct rtw_ieee80211_ht_cap ht_cap;
+	
+};
+
+#define	STBC_HT_ENABLE_RX			BIT0
+#define	STBC_HT_ENABLE_TX			BIT1
+#define	STBC_HT_TEST_TX_ENABLE		BIT2
+#define	STBC_HT_CAP_TX				BIT3
+
+typedef enum AGGRE_SIZE{
+	HT_AGG_SIZE_8K = 0,
+	HT_AGG_SIZE_16K = 1,
+	HT_AGG_SIZE_32K = 2,
+	HT_AGG_SIZE_64K = 3,
+	VHT_AGG_SIZE_128K = 4,
+	VHT_AGG_SIZE_256K = 5,
+	VHT_AGG_SIZE_512K = 6,
+	VHT_AGG_SIZE_1024K = 7,
+}AGGRE_SIZE_E, *PAGGRE_SIZE_E;
+
+#endif	//_RTL871X_HT_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_intfs.h

@@ -0,0 +1,39 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef _RTW_INTFS_H_
+#define _RTW_INTFS_H_
+
+extern u8 rtw_init_default_value(_adapter *padapter);
+#ifdef CONFIG_WOWLAN
+void rtw_cancel_dynamic_chk_timer(_adapter *padapter);
+#endif
+extern void rtw_cancel_all_timer(_adapter *padapter);
+
+extern u8 rtw_init_drv_sw(_adapter *padapter);
+extern u8 rtw_free_drv_sw(_adapter *padapter);
+extern u8 rtw_reset_drv_sw(_adapter *padapter);
+
+extern int rtw_drv_init(ADAPTER *padapter);
+extern void rtw_drv_deinit(ADAPTER *Adapter);
+
+extern u32 rtw_start_drv_threads(_adapter *padapter);
+extern void rtw_stop_drv_threads (_adapter *padapter);
+
+#endif //_RTW_INTFS_H_

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_io.h

@@ -0,0 +1,140 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef _RTW_IO_H_
+#define _RTW_IO_H_
+
+//IO Bus domain address mapping
+#define DEFUALT_OFFSET					0x0   
+#define WLAN_LOCAL_OFFSET    			0x10250000
+#define WLAN_IOREG_OFFSET   			0x10260000
+#define FW_FIFO_OFFSET 	    			0x10270000
+#define TX_HIQ_OFFSET	    				0x10310000
+#define TX_MIQ_OFFSET					0x1032000
+#define TX_LOQ_OFFSET					0x10330000
+#define RX_RXOFF_OFFSET	    			0x10340000
+
+struct fifo_more_data {
+	u32 more_data;
+	u32 len;
+};
+
+struct dvobj_priv;
+
+typedef struct _io_ops {
+		int (*init_io_priv)(struct dvobj_priv *pdvobj);
+		int (*write8_endian)(struct dvobj_priv *pdvobj, u32 addr, u32 buf, u32 big);
+
+		u8 (*_read8)(struct dvobj_priv *pdvobj, u32 addr, s32 *err);		
+		u16 (*_read16)(struct dvobj_priv *pdvobj, u32 addr, s32 *err);		
+		u32 (*_read32)(struct dvobj_priv *pdvobj, u32 addr, s32 *err);
+
+		s32  (*_write8)(struct dvobj_priv *pdvobj, u32 addr, u8 buf, s32 *err);		
+		s32  (*_write16)(struct dvobj_priv *pdvobj, u32 addr,u16 buf, s32 *err);		
+		s32  (*_write32)(struct dvobj_priv *pdvobj, u32 addr, u32 buf, s32 *err);
+
+		int (*read_rx_fifo)(struct dvobj_priv *pdvobj, u32 addr, u8 *buf, u32 len, struct fifo_more_data *more_data);
+		int (*write_tx_fifo)(struct dvobj_priv *pdvobj, u32 addr, u8 *buf, u32 len);		
+} IO_OPS_T;
+
+struct bus_transfer {
+	void	*tx_buf;
+	void	*rx_buf;
+	unsigned	int len;
+};
+
+typedef struct _bus_drv_ops {
+		int (*bus_drv_init)(ADAPTER *Adapter);
+		int (*bus_send_msg)(PADAPTER Adapter, struct bus_transfer xfers[], u32 RegAction);
+} BUS_DRV_OPS_T;
+
+/*
+struct	intf_hdl {
+
+	u32	intf_option;
+	u32	bus_status;
+	u32	do_flush;
+	u8	*adapter;
+	u8	*intf_dev;	
+	struct intf_priv	*pintfpriv;
+	u8	cnt;
+	void (*intf_hdl_init)(u8 *priv);
+	void (*intf_hdl_unload)(u8 *priv);
+	void (*intf_hdl_open)(u8 *priv);
+	void (*intf_hdl_close)(u8 *priv);
+	struct	_io_ops	io_ops;
+	//u8 intf_status;//moved to struct intf_priv
+	u16 len;
+	u16 done_len;	
+
+	_adapter *padapter;
+	struct dvobj_priv *pintf_dev;//	pointer to &(padapter->dvobjpriv);
+	
+	struct _io_ops	io_ops;
+
+};
+*/
+
+struct io_priv{
+	struct _io_ops	io_ops;
+};
+
+
+extern u8 rtw_read8(ADAPTER *adapter, u32 addr);
+extern u16 rtw_read16(ADAPTER *adapter, u32 addr);
+extern u32 rtw_read32(ADAPTER *adapter, u32 addr);
+extern s32 rtw_write8(ADAPTER *adapter, u32 addr, u8 val);
+extern s32 rtw_write16(ADAPTER *adapter, u32 addr, u16 val);
+extern s32 rtw_write32(ADAPTER *adapter, u32 addr, u32 val);
+
+#define PlatformEFIOWrite1Byte(_a,_b,_c)		\
+	rtw_write8(_a,_b,_c)
+#define PlatformEFIOWrite2Byte(_a,_b,_c)		\
+	rtw_write16(_a,_b,_c)
+#define PlatformEFIOWrite4Byte(_a,_b,_c)		\
+	rtw_write32(_a,_b,_c)
+
+#define PlatformEFIORead1Byte(_a,_b)		\
+		rtw_read8(_a,_b)
+#define PlatformEFIORead2Byte(_a,_b)		\
+		rtw_read16(_a,_b)
+#define PlatformEFIORead4Byte(_a,_b)		\
+		rtw_read32(_a,_b)
+
+extern IO_OPS_T io_ops;
+
+extern u32 rtw_write_port(
+	ADAPTER *adapter,
+	u32 addr,
+	u32 cnt,
+	u8 *mem);
+extern u32 rtw_read_port(
+	ADAPTER *adapter,
+	u32 addr,
+	u32 cnt,
+	u8 *mem,
+	struct fifo_more_data *more_data);
+extern void rtw_set_chip_endian(PADAPTER padapter);
+extern int rtw_get_chip_endian(PADAPTER padapter);
+
+int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(struct _io_ops *pops));
+
+#endif	//_RTW_IO_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_ioctl_set.h

@@ -0,0 +1,75 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __RTW_IOCTL_SET_H_
+#define __RTW_IOCTL_SET_H_
+
+
+#ifdef PLATFORM_OS_XP
+typedef struct _NDIS_802_11_PMKID {
+	u32	Length;
+	u32	BSSIDInfoCount;
+	BSSIDInfo BSSIDInfo[1];
+} NDIS_802_11_PMKID, *PNDIS_802_11_PMKID;
+#endif
+
+
+#ifdef PLATFORM_WINDOWS
+typedef u8 NDIS_802_11_PMKID_VALUE[16];
+
+typedef struct _BSSIDInfo {
+	NDIS_802_11_MAC_ADDRESS  BSSID;
+	NDIS_802_11_PMKID_VALUE  PMKID;
+} BSSIDInfo, *PBSSIDInfo;
+
+u8 rtw_set_802_11_reload_defaults(_adapter * padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults);
+u8 rtw_set_802_11_test(_adapter * padapter, NDIS_802_11_TEST * test);
+u8 rtw_set_802_11_pmkid(_adapter *pdapter, NDIS_802_11_PMKID *pmkid);
+
+u8 rtw_pnp_set_power_sleep(_adapter* padapter);
+u8 rtw_pnp_set_power_wakeup(_adapter* padapter);
+
+void rtw_pnp_resume_wk(void *context);
+void rtw_pnp_sleep_wk(void * context);
+
+#endif
+
+u8 rtw_set_802_11_add_key(_adapter * padapter, NDIS_802_11_KEY * key);
+u8 rtw_set_802_11_authentication_mode(_adapter *pdapter, NDIS_802_11_AUTHENTICATION_MODE authmode);
+u8 rtw_set_802_11_bssid(_adapter* padapter, u8 *bssid);
+u8 rtw_set_802_11_add_wep(_adapter * padapter, NDIS_802_11_WEP * wep);
+u8 rtw_set_802_11_disassociate(_adapter * padapter);
+u8 rtw_set_802_11_bssid_list_scan(_adapter* padapter, NDIS_802_11_SSID *pssid, int ssid_max_num);
+u8 rtw_set_802_11_infrastructure_mode(_adapter * padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype);
+u8 rtw_set_802_11_remove_wep(_adapter * padapter, u32 keyindex);
+u8 rtw_set_802_11_ssid(_adapter * padapter, NDIS_802_11_SSID * ssid);
+u8 rtw_set_802_11_connect(_adapter* padapter, u8 *bssid, NDIS_802_11_SSID *ssid);
+u8 rtw_set_802_11_remove_key(_adapter * padapter, NDIS_802_11_REMOVE_KEY * key);
+
+u8 rtw_validate_bssid(u8 *bssid);
+u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid);
+
+u16 rtw_get_cur_max_rate(_adapter *adapter);
+//int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode);
+int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan);
+int rtw_set_country(_adapter *adapter, const char *country_code);
+//int rtw_set_band(_adapter *adapter, enum _BAND band);
+
+#endif
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_led.h

@@ -0,0 +1,250 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __RTW_LED_H_
+#define __RTW_LED_H_
+
+//TODO
+#if 0
+
+//#include <drv_types.h>
+
+#define MSECS(t)        (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000)
+
+#define LED_BLINK_NORMAL_INTERVAL	100
+#define LED_BLINK_SLOWLY_INTERVAL	200
+#define LED_BLINK_LONG_INTERVAL	400
+
+#define LED_BLINK_NO_LINK_INTERVAL_ALPHA		1000
+#define LED_BLINK_LINK_INTERVAL_ALPHA			500		//500
+#define LED_BLINK_SCAN_INTERVAL_ALPHA		180 	//150
+#define LED_BLINK_FASTER_INTERVAL_ALPHA		50
+#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA	5000
+
+#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX  100
+#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX  2000
+
+#define LED_BLINK_SLOWLY_INTERVAL_PORNET 1000
+#define LED_BLINK_NORMAL_INTERVAL_PORNET 100
+
+#define LED_BLINK_FAST_INTERVAL_BITLAND 30
+
+// 060403, rcnjko: Customized for AzWave.
+#define LED_CM2_BLINK_ON_INTERVAL			250
+#define LED_CM2_BLINK_OFF_INTERVAL		4750
+
+#define LED_CM8_BLINK_INTERVAL			500		//for QMI
+#define LED_CM8_BLINK_OFF_INTERVAL	3750	//for QMI
+
+// 080124, lanhsin: Customized for RunTop
+#define LED_RunTop_BLINK_INTERVAL			300
+
+// 060421, rcnjko: Customized for Sercomm Printer Server case.
+#define LED_CM3_BLINK_INTERVAL				1500
+
+#endif	//#if 0
+
+typedef enum _LED_CTL_MODE{
+	LED_CTL_POWER_ON = 1,
+	LED_CTL_LINK = 2,
+	LED_CTL_NO_LINK = 3,
+	LED_CTL_TX = 4,
+	LED_CTL_RX = 5,
+	LED_CTL_SITE_SURVEY = 6,
+	LED_CTL_POWER_OFF = 7,
+	LED_CTL_START_TO_LINK = 8,
+	LED_CTL_START_WPS = 9,
+	LED_CTL_STOP_WPS = 10,
+	LED_CTL_START_WPS_BOTTON = 11, //added for runtop
+	LED_CTL_STOP_WPS_FAIL = 12, //added for ALPHA	
+	LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, //added for BELKIN
+	LED_CTL_CONNECTION_NO_TRANSFER = 14,
+}LED_CTL_MODE;
+
+//TODO
+#if 0
+
+typedef enum _LED_STATE_871x{
+	LED_UNKNOWN = 0,
+	RTW_LED_ON = 1,
+	RTW_LED_OFF = 2,
+	LED_BLINK_NORMAL = 3,
+	LED_BLINK_SLOWLY = 4,
+	LED_BLINK_POWER_ON = 5,
+	LED_BLINK_SCAN = 6, // LED is blinking during scanning period, the # of times to blink is depend on time for scanning.
+	LED_BLINK_NO_LINK = 7, // LED is blinking during no link state.
+	LED_BLINK_StartToBlink = 8,// Customzied for Sercomm Printer Server case
+	LED_BLINK_TXRX = 9,
+	LED_BLINK_WPS = 10,	// LED is blinkg during WPS communication	
+	LED_BLINK_WPS_STOP = 11,	//for ALPHA	
+	LED_BLINK_WPS_STOP_OVERLAP = 12,	//for BELKIN
+	LED_BLINK_RUNTOP = 13, // Customized for RunTop
+	LED_BLINK_CAMEO = 14,
+	LED_BLINK_XAVI = 15,
+	LED_BLINK_ALWAYS_ON = 16,	
+}LED_STATE_871x;
+
+typedef enum _LED_PIN_871x{
+	LED_PIN_NULL = 0,
+	LED_PIN_LED0 = 1,
+	LED_PIN_LED1 = 2,
+	LED_PIN_LED2 = 3,
+	LED_PIN_GPIO0 = 4,
+}LED_PIN_871x;
+
+typedef struct _LED_871x{
+	_adapter				*padapter;
+	
+	LED_PIN_871x		LedPin;	// Identify how to implement this SW led.
+	LED_STATE_871x		CurrLedState; // Current LED state.
+	LED_STATE_871x		BlinkingLedState; // Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are.
+	
+	u8					bLedOn; // true if LED is ON, false if LED is OFF.
+
+	u8					bLedBlinkInProgress; // true if it is blinking, false o.w..
+
+	u8					bLedWPSBlinkInProgress;
+
+	u32					BlinkTimes; // Number of times to toggle led state for blinking.
+
+	_timer				BlinkTimer; // Timer object for led blinking.
+
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	u8					bSWLedCtrl;
+
+	// ALPHA, added by chiyoko, 20090106
+	u8					bLedNoLinkBlinkInProgress;
+	u8					bLedLinkBlinkInProgress;
+	u8					bLedStartToLinkBlinkInProgress;
+	u8					bLedScanBlinkInProgress;
+	
+	#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)|| defined PLATFORM_FREEBSD
+	_workitem			BlinkWorkItem; // Workitem used by BlinkTimer to manipulate H/W to blink LED.
+	#endif
+#endif //defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	
+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI)
+	u8					bLedSlowBlinkInProgress;//added by vivi, for led new mode
+#endif
+
+} LED_871x, *PLED_871x;
+
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+
+#define IS_LED_WPS_BLINKING(_LED_871x)	(((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS \
+					|| ((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS_STOP \
+					|| ((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress)
+
+#define IS_LED_BLINKING(_LED_871x) 	(((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress \
+					||((PLED_871x)_LED_871x)->bLedScanBlinkInProgress)
+
+//================================================================================
+// LED customization.
+//================================================================================
+
+typedef	enum _LED_STRATEGY_871x{
+	SW_LED_MODE0 = 0, // SW control 1 LED via GPIO0. It is default option.
+	SW_LED_MODE1= 1, // 2 LEDs, through LED0 and LED1. For ALPHA.
+	SW_LED_MODE2 = 2, // SW control 1 LED via GPIO0, customized for AzWave 8187 minicard.
+	SW_LED_MODE3 = 3, // SW control 1 LED via GPIO0, customized for Sercomm Printer Server case.
+	SW_LED_MODE4 = 4, //for Edimax / Belkin
+	SW_LED_MODE5 = 5, //for Sercomm / Belkin
+	SW_LED_MODE6 = 6, //for 88CU minicard, porting from ce SW_LED_MODE7
+	HW_LED = 50, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.)
+	LED_ST_NONE = 99,
+}LED_STRATEGY_871x, *PLED_STRATEGY_871x;
+
+void
+LedControl871x(
+	_adapter				*padapter,
+	LED_CTL_MODE		LedAction
+	);
+#endif //defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+
+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI)
+//================================================================================
+// LED customization.
+//================================================================================
+
+typedef	enum _LED_STRATEGY_871x{
+	SW_LED_MODE0 = 0, // SW control 1 LED via GPIO0. It is default option.
+	SW_LED_MODE1 = 1, // SW control for PCI Express
+	SW_LED_MODE2 = 2, // SW control for Cameo.
+	SW_LED_MODE3 = 3, // SW contorl for RunTop.
+	SW_LED_MODE4 = 4, // SW control for Netcore
+	SW_LED_MODE5 = 5, //added by vivi, for led new mode, DLINK
+	SW_LED_MODE6 = 6, //added by vivi, for led new mode, PRONET
+	SW_LED_MODE7 = 7, //added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec
+	SW_LED_MODE8 = 8, //added by chiyokolin, for QMI
+	SW_LED_MODE9 = 9, //added by chiyokolin, for BITLAND, PCI Express Minicard Spec Rev.1.1 
+	SW_LED_MODE10 = 10, //added by chiyokolin, for Edimax-ASUS
+	HW_LED = 50, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
+	LED_ST_NONE = 99,
+}LED_STRATEGY_871x, *PLED_STRATEGY_871x;
+#endif //defined(CONFIG_PCI_HCI)
+
+struct led_priv{
+	/* add for led controll */
+	LED_871x			SwLed0;
+	LED_871x			SwLed1;
+	LED_STRATEGY_871x	LedStrategy;
+	u8					bRegUseLed;
+	void (*LedControlHandler)(_adapter *padapter, LED_CTL_MODE LedAction);
+	/* add for led controll */
+};
+
+#endif	//#if 0
+
+#ifdef CONFIG_SW_LED
+#define rtw_led_control(adapter, LedAction) \
+	do { \
+		if((adapter)->ledpriv.LedControlHandler) \
+			(adapter)->ledpriv.LedControlHandler((adapter), (LedAction)); \
+	} while(0)
+#else //CONFIG_SW_LED
+#define rtw_led_control(adapter, LedAction)
+#endif //CONFIG_SW_LED
+
+//TODO
+#if 0
+
+void BlinkTimerCallback(void *data);
+void BlinkWorkItemCallback(struct work_struct *work);
+
+void ResetLedStatus(PLED_871x pLed);
+
+void
+InitLed871x(
+	_adapter			*padapter,
+	PLED_871x		pLed,
+	LED_PIN_871x	LedPin
+	);
+
+void
+DeInitLed871x(
+	PLED_871x			pLed
+	);
+
+//hal...
+extern void BlinkHandler(PLED_871x	 pLed);
+
+#endif	//#if 0
+
+#endif //__RTW_LED_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_mlme.h

@@ -0,0 +1,795 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __RTW_MLME_H_
+#define __RTW_MLME_H_
+
+#ifdef CONFIG_INTEL_WIDI
+#include <rtw_intel_widi.h>
+#endif
+
+#if defined(PLATFORM_ECOS)
+#define	MAX_BSS_CNT	10	//alloc less wlan_network due to memory limitation - Alex Fang
+#elif defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
+#define	MAX_BSS_CNT	1	//alloc less wlan_network due to memory limitation - Alex Fang
+#else
+#define	MAX_BSS_CNT	128
+#endif
+//#define   MAX_JOIN_TIMEOUT	2000
+//#define   MAX_JOIN_TIMEOUT	2500
+#define   MAX_JOIN_TIMEOUT	6500
+
+#ifdef CONFIG_MULTICAST
+#define MULTICAST_LIST_SIZE		4
+#endif
+
+//	Commented by Albert 20101105
+//	Increase the scanning timeout because of increasing the SURVEY_TO value.
+
+#define 	SCANNING_TIMEOUT 	8000
+
+#define	SCAN_INTERVAL	(30) // unit:2sec, 30*2=60sec
+
+#ifdef PALTFORM_OS_WINCE
+#define	SCANQUEUE_LIFETIME 12000000 // unit:us
+#else
+#define	SCANQUEUE_LIFETIME 20 // unit:sec
+#endif
+
+#define 	WIFI_NULL_STATE		0x00000000
+#define	WIFI_ASOC_STATE		0x00000001		// Under Linked state...
+#define 	WIFI_REASOC_STATE	       0x00000002
+#define	WIFI_SLEEP_STATE	       0x00000004
+#define	WIFI_STATION_STATE	0x00000008
+#define	WIFI_AP_STATE				0x00000010
+#define	WIFI_ADHOC_STATE			0x00000020
+#define   WIFI_ADHOC_MASTER_STATE 0x00000040
+#define   WIFI_UNDER_LINKING		0x00000080
+//#define WIFI_UNDER_CMD			0x00000200
+// ========== P2P Section Start ===============
+#define	WIFI_P2P_LISTEN_STATE		0x00010000
+#define	WIFI_P2P_GROUP_FORMATION_STATE		0x00020000
+// ========== P2P Section End ===============
+#define WIFI_UNDER_WPS			0x00000100
+#define WIFI_SITE_MONITOR		0x00000800		//to indicate the station is under site surveying
+
+#ifdef WDS
+#define	WIFI_WDS				0x00001000
+#define	WIFI_WDS_RX_BEACON	0x00002000		// already rx WDS AP beacon
+#endif
+#ifdef AUTO_CONFIG
+#define	WIFI_AUTOCONF			0x00004000
+#define	WIFI_AUTOCONF_IND	0x00008000
+#endif
+
+//#ifdef UNDER_MPTEST
+#define	WIFI_MP_STATE						0x00010000
+#define	WIFI_MP_CTX_BACKGROUND			0x00020000	// in continous tx background
+#define	WIFI_MP_CTX_ST					0x00040000	// in continous tx with single-tone
+#define	WIFI_MP_CTX_BACKGROUND_PENDING	0x00080000	// pending in continous tx background due to out of skb
+#define	WIFI_MP_CTX_CCK_HW				0x00100000	// in continous tx
+#define	WIFI_MP_CTX_CCK_CS				0x00200000	// in continous tx with carrier suppression
+#define   WIFI_MP_LPBK_STATE				0x00400000
+//#endif
+
+//#define _FW_UNDER_CMD		WIFI_UNDER_CMD
+#define _FW_UNDER_LINKING	WIFI_UNDER_LINKING
+#define _FW_LINKED			WIFI_ASOC_STATE
+#define _FW_UNDER_SURVEY	WIFI_SITE_MONITOR
+
+enum dot11AuthAlgrthmNum {
+ dot11AuthAlgrthm_Open = 0,
+ dot11AuthAlgrthm_Shared,
+ dot11AuthAlgrthm_8021X,
+ dot11AuthAlgrthm_Auto,
+ dot11AuthAlgrthm_WAPI,
+ dot11AuthAlgrthm_MaxNum
+};
+
+// Scan type including active and passive scan.
+typedef enum _RT_SCAN_TYPE
+{
+	SCAN_PASSIVE,
+	SCAN_ACTIVE,
+	SCAN_MIX,
+} RT_SCAN_TYPE, *PRT_SCAN_TYPE;
+
+/*
+
+there are several "locks" in mlme_priv,
+since mlme_priv is a shared resource between many threads,
+like ISR/Call-Back functions, the OID handlers, and even timer functions.
+
+
+Each _queue has its own locks, already.
+Other items are protected by mlme_priv.lock.
+
+To avoid possible dead lock, any thread trying to modifiying mlme_priv
+SHALL not lock up more than one locks at a time!
+
+*/
+
+
+#define traffic_threshold	10
+#define	traffic_scan_period	500
+
+struct sitesurvey_ctrl {
+	u64	last_tx_pkts;
+	uint	last_rx_pkts;
+	sint	traffic_busy;
+	_timer	sitesurvey_ctrl_timer;
+};
+
+typedef struct _RT_LINK_DETECT_T{
+	u32			NumTxOkInPeriod;
+	u32			NumRxOkInPeriod;
+	u32			NumRxUnicastOkInPeriod;
+	BOOLEAN			bBusyTraffic;
+	BOOLEAN			bTxBusyTraffic;
+	BOOLEAN			bRxBusyTraffic;
+	BOOLEAN			bHigherBusyTraffic;	// For interrupt migration purpose.
+	BOOLEAN			bHigherBusyRxTraffic;	// We may disable Tx interrupt according as Rx traffic.
+	BOOLEAN			bHigherBusyTxTraffic;	// We may disable Tx interrupt according as Tx traffic.
+} RT_LINK_DETECT_T, *PRT_LINK_DETECT_T;
+
+//TODO
+#if 0
+
+struct profile_info {
+	u8	ssidlen;
+	u8	ssid[ WLAN_SSID_MAXLEN ];
+	u8	peermac[ ETH_ALEN ];
+};
+
+struct tx_invite_req_info{
+	u8					token;
+	u8					benable;
+	u8					go_ssid[ WLAN_SSID_MAXLEN ];
+	u8					ssidlen;
+	u8					go_bssid[ ETH_ALEN ];
+	u8					peer_macaddr[ ETH_ALEN ];
+	u8					operating_ch;	//	This information will be set by using the p2p_set op_ch=x
+	u8					peer_ch;		//	The listen channel for peer P2P device
+
+};
+
+struct tx_invite_resp_info{
+	u8					token;	//	Used to record the dialog token of p2p invitation request frame.
+};
+
+#ifdef CONFIG_WFD
+
+struct wifi_display_info{
+	u16					wfd_enable;			//	Eanble/Disable the WFD function.
+	u16					rtsp_ctrlport;		//	TCP port number at which the this WFD device listens for RTSP messages
+	u16					peer_rtsp_ctrlport;	//	TCP port number at which the peer WFD device listens for RTSP messages
+											//	This filed should be filled when receiving the gropu negotiation request
+
+	u8					peer_session_avail;	//	WFD session is available or not for the peer wfd device.
+											//	This variable will be set when sending the provisioning discovery request to peer WFD device.
+											//	And this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command.
+	u8					ip_address[4];
+	u8					peer_ip_address[4];
+	u8					wfd_pc;				//	WFD preferred connection
+											//	0 -> Prefer to use the P2P for WFD connection on peer side.
+											//	1 -> Prefer to use the TDLS for WFD connection on peer side.
+											
+	u8					wfd_device_type;	//	WFD Device Type
+											//	0 -> WFD Source Device
+											//	1 -> WFD Primary Sink Device
+
+};
+#endif //CONFIG_WFD
+
+struct tx_provdisc_req_info{
+	u16					wps_config_method_request;	//	Used when sending the provisioning request frame
+	u16					peer_channel_num[2];		//	The channel number which the receiver stands.
+	NDIS_802_11_SSID	ssid;
+	u8					peerDevAddr[ ETH_ALEN ];		//	Peer device address
+	u8					peerIFAddr[ ETH_ALEN ];		//	Peer interface address
+	u8					benable;					//	This provision discovery request frame is trigger to send or not
+};
+
+struct rx_provdisc_req_info{	//When peer device issue prov_disc_req first, we should store the following informations
+	u8					peerDevAddr[ ETH_ALEN ];		//	Peer device address
+	u8					strconfig_method_desc_of_prov_disc_req[4];	//	description for the config method located in the provisioning discovery request frame.	
+																	//	The UI must know this information to know which config method the remote p2p device is requiring.
+};
+
+struct tx_nego_req_info{
+	u16					peer_channel_num[2];		//	The channel number which the receiver stands.
+	u8					peerDevAddr[ ETH_ALEN ];		//	Peer device address
+	u8					benable;					//	This negoitation request frame is trigger to send or not
+};
+
+struct group_id_info{
+	u8					go_device_addr[ ETH_ALEN ];	//	The GO's device address of this P2P group
+	u8					ssid[ WLAN_SSID_MAXLEN ];	//	The SSID of this P2P group
+};
+
+#ifdef CONFIG_IOCTL_CFG80211
+struct cfg80211_wifidirect_info{
+	_timer					remain_on_ch_timer;
+	u8						restore_channel;
+	struct ieee80211_channel	remain_on_ch_channel;
+	enum nl80211_channel_type	remain_on_ch_type;
+	u64						remain_on_ch_cookie;
+	struct net_device 			*remain_on_ch_dev;
+	bool is_ro_ch;
+};
+#endif //CONFIG_IOCTL_CFG80211
+
+#endif
+
+struct wifidirect_info{
+	enum P2P_ROLE			role;
+	enum P2P_STATE			p2p_state;
+	u8						baction_tx_pending;
+	u8						pending_peer[ETH_ALEN];
+	struct xmit_frame			*pending_action;
+	_timer					pre_tx_scan_timer;
+	
+#if 0
+	_adapter*				padapter;
+	_timer					find_phase_timer;
+	_timer					restore_p2p_state_timer;
+	
+	//	Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer.
+	_timer					pre_tx_scan_timer;
+#ifdef CONFIG_CONCURRENT_MODE
+	//	Used to switch the channel between legacy AP and listen state.
+	_timer					ap_p2p_switch_timer;
+#endif
+	struct tx_provdisc_req_info	tx_prov_disc_info;
+	struct rx_provdisc_req_info rx_prov_disc_info;
+	struct tx_invite_req_info	invitereq_info;
+	struct profile_info			profileinfo[ P2P_MAX_PERSISTENT_GROUP_NUM ];	//	Store the profile information of persistent group
+	struct tx_invite_resp_info	inviteresp_info;
+	struct tx_nego_req_info	nego_req_info;
+	struct group_id_info		groupid_info;	//	Store the group id information when doing the group negotiation handshake.
+#ifdef CONFIG_WFD
+	struct wifi_display_info		*wfd_info;
+#endif	
+	enum P2P_ROLE			role;
+	enum P2P_STATE			pre_p2p_state;
+	enum P2P_STATE			p2p_state;
+	u8 						device_addr[ETH_ALEN];	//	The device address should be the mac address of this device.
+	u8						interface_addr[ETH_ALEN];
+	u8						social_chan[4];
+	u8						listen_channel;
+	u8						operating_channel;
+	u8						listen_dwell;		//	This value should be between 1 and 3
+	u8						support_rate[8];
+	u8						p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN];
+	u8						intent;		//	should only include the intent value.
+	u8						p2p_peer_interface_addr[ ETH_ALEN ];
+	u8						p2p_peer_device_addr[ ETH_ALEN ];
+	u8						peer_intent;	//	Included the intent value and tie breaker value.
+	u8						device_name[ WPS_MAX_DEVICE_NAME_LEN ];	//	Device name for displaying on searching device screen
+	u8						device_name_len;
+	u8						profileindex;	//	Used to point to the index of profileinfo array
+	u8						peer_operating_ch;
+	u8						find_phase_state_exchange_cnt;
+	u16						device_password_id_for_nego;	//	The device password ID for group negotation
+	u8						negotiation_dialog_token;
+	u8						nego_ssid[ WLAN_SSID_MAXLEN ];	//	SSID information for group negotitation
+	u8						nego_ssidlen;
+	u8 						p2p_group_ssid[WLAN_SSID_MAXLEN];
+	u8 						p2p_group_ssid_len;
+	u8						persistent_supported;		//	Flag to know the persistent function should be supported or not.
+														//	In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI.
+														//	0: disable
+														//	1: enable
+	u8						session_available;			//	Flag to set the WFD session available to enable or disable "by Sigma"
+														//	In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI.
+														//	0: disable
+														//	1: enable
+
+	u8						wfd_tdls_enable;			//	Flag to enable or disable the TDLS by WFD Sigma
+														//	0: disable
+														//	1: enable
+	u8						wfd_tdls_weaksec;			//	Flag to enable or disable the weak security function for TDLS by WFD Sigma
+														//	0: disable
+														//	In this case, the driver can't issue the tdsl setup request frame.
+														//	1: enable
+														//	In this case, the driver can issue the tdls setup request frame
+														//	even the current security is weak security.
+
+	enum	P2P_WPSINFO		ui_got_wps_info;			//	This field will store the WPS value (PIN value or PBC) that UI had got from the user.
+	u16						supported_wps_cm;			//	This field describes the WPS config method which this driver supported.
+														//	The value should be the combination of config method defined in page104 of WPS v2.0 spec.	
+	uint						channel_list_attr_len;		//	This field will contain the length of body of P2P Channel List attribute of group negotitation response frame.
+	u8						channel_list_attr[100];		//	This field will contain the body of P2P Channel List attribute of group negotitation response frame.
+														//	We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame.
+#ifdef CONFIG_CONCURRENT_MODE
+	u16						ext_listen_interval;	//	The interval to be available with legacy AP (ms)
+	u16						ext_listen_period;	//	The time period to be available for P2P listen state (ms)
+#endif
+	u8						p2p_ps_enable;
+	enum P2P_PS				p2p_ps; // indicate p2p ps state
+	u8						noa_index; // Identifies and instance of Notice of Absence timing.
+	u8						ctwindow; // Client traffic window. A period of time in TU after TBTT.
+	u8						opp_ps; // opportunistic power save.
+	u8						noa_num; // number of NoA descriptor in P2P IE.
+	u8						noa_count[P2P_MAX_NOA_NUM]; // Count for owner, Type of client.
+	u32						noa_duration[P2P_MAX_NOA_NUM]; // Max duration for owner, preferred or min acceptable duration for client.
+	u32						noa_interval[P2P_MAX_NOA_NUM]; // Length of interval for owner, preferred or max acceptable interval of client.
+	u32						noa_start_time[P2P_MAX_NOA_NUM]; // schedule expressed in terms of the lower 4 bytes of the TSF timer.
+#endif
+};
+#if 0
+struct tdls_ss_record{	//signal strength record
+	u8		macaddr[ETH_ALEN];
+	u8		RxPWDBAll;
+	u8		is_tdls_sta;	// _TRUE: direct link sta, _FALSE: else
+};
+
+struct tdls_info{
+	u8					ap_prohibited;
+	uint					setup_state;
+	u8					sta_cnt;
+	u8					sta_maximum;	// 1:tdls sta is equal (NUM_STA-1), reach max direct link number; 0: else;
+	struct tdls_ss_record	ss_record;
+	u8					macid_index;	//macid entry that is ready to write
+	u8					clear_cam;	//cam entry that is trying to clear, using it in direct link teardown
+	u8					ch_sensing;
+	u8					cur_channel;
+	u8					candidate_ch;
+	u8					collect_pkt_num[MAX_CHANNEL_NUM];
+	_lock				cmd_lock;
+	_lock				hdl_lock;
+	u8					watchdog_count;
+	u8					dev_discovered;		//WFD_TDLS: for sigma test
+	u8					enable;
+#ifdef CONFIG_WFD
+	struct wifi_display_info		*wfd_info;
+#endif		
+};
+
+#endif	//#if 0
+
+struct mlme_priv {
+
+	_lock	lock;
+	sint	fw_state;	//shall we protect this variable? maybe not necessarily...
+	u8 bScanInProcess;
+	u8	to_join; //flag
+	#ifdef CONFIG_LAYER2_ROAMING
+	u8 to_roaming; // roaming trying times
+	#endif
+
+	u8		*nic_hdl;		//can be removed
+
+	//u8		not_indic_disco;
+	_list		*pscanned;
+	_queue	free_bss_pool;
+	_queue	scanned_queue;
+	u8		*free_bss_buf;
+	u16		num_of_scanned;
+	
+#if SUPPORT_SCAN_BUF	// Cloud 2013/12/20
+	u8		*scan_buf;
+	u32		scan_buf_len;
+	u16		scan_cnt;
+	u16		scan_type;
+#endif
+
+	NDIS_802_11_SSID	assoc_ssid;
+	u8	assoc_bssid[6];
+
+	struct wlan_network	cur_network;
+
+	//uint wireless_mode; no used, remove it
+
+	u32	scan_interval;
+
+	_timer assoc_timer;
+
+	u8 assoc_by_bssid;
+	u8 assoc_by_rssi;
+
+	_timer scan_to_timer; // driver itself handles scan_timeout status.
+	u32 scan_start_time; // used to evaluate the time spent in scanning
+
+	#ifdef CONFIG_SET_SCAN_DENY_TIMER
+	_timer set_scan_deny_timer;
+	ATOMIC_T set_scan_deny; //0: allowed, 1: deny
+	#endif
+
+	struct qos_priv qospriv;
+
+#ifdef CONFIG_80211N_HT
+
+	/* Number of non-HT AP/stations */
+	u16 num_sta_no_ht; //int num_sta_no_ht;
+
+	/* Number of HT AP/stations 20 MHz */
+	//int num_sta_ht_20mhz; 
+
+
+	u16 num_FortyMHzIntolerant; //int num_FortyMHzIntolerant;
+
+	struct ht_priv	htpriv;
+
+#endif
+
+	RT_LINK_DETECT_T	LinkDetectInfo;
+	_timer	dynamic_chk_timer; //dynamic/periodic check timer
+
+ 	u8 	key_mask; //use for ips to set wep key after ips_leave
+	u8	acm_mask; // for wmm acm mask
+	u8	ChannelPlan;
+	RT_SCAN_TYPE 	scan_mode; // active: 1, passive: 0
+
+#ifdef CONFIG_WPS	
+	u8 *wps_probe_req_ie;
+	u32 wps_probe_req_ie_len;
+	u8 *wps_assoc_req_ie;
+	u32 wps_assoc_req_ie_len;
+#endif	
+
+#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
+	/* Number of associated Non-ERP stations (i.e., stations using 802.11b
+	 * in 802.11g BSS) */
+	u16 num_sta_non_erp;
+
+	/* Number of associated stations that do not support Short Slot Time */
+	u16 num_sta_no_short_slot_time;
+
+	/* Number of associated stations that do not support Short Preamble */
+	u16 num_sta_no_short_preamble;
+
+	//int olbc; /* Overlapping Legacy BSS Condition */
+
+	/* Number of HT associated stations that do not support greenfield */
+	u16 num_sta_ht_no_gf;
+
+	/* Number of associated non-HT stations */
+	//int num_sta_no_ht;
+
+	/* Number of HT associated stations 20 MHz */
+	u16 num_sta_ht_20mhz;
+
+	/* Overlapping BSS information */
+	u8 olbc_ht;
+	
+#ifdef CONFIG_80211N_HT
+	u16 ht_op_mode;
+#endif /* CONFIG_80211N_HT */	
+
+#ifdef CONFIG_WPS	
+	u8 *wps_beacon_ie;	
+	u8 *wps_probe_resp_ie;
+	u8 *wps_assoc_resp_ie; // for CONFIG_IOCTL_CFG80211, this IE could include p2p ie
+
+	u32 wps_beacon_ie_len;
+	u32 wps_probe_resp_ie_len;
+	u32 wps_assoc_resp_ie_len;
+	
+
+#ifdef CONFIG_P2P_NEW
+	u8 *p2p_beacon_ie;
+	u8 *p2p_probe_req_ie;
+	u8 *p2p_probe_resp_ie;	
+//	u8 *p2p_go_probe_resp_ie; //for GO	
+	u8 *p2p_assoc_req_ie;
+	u8 *p2p_assoc_rsp_ie;
+
+	u32 p2p_beacon_ie_len;
+	u32 p2p_probe_req_ie_len;
+	u32 p2p_probe_resp_ie_len;
+//	u32 p2p_go_probe_resp_ie_len; //for GO
+	u32 p2p_assoc_req_ie_len;
+	u32 p2p_assoc_rsp_ie_len;
+#endif //CONFIG_P2P
+#endif //CONFIG_WPS
+	
+	_lock	bcn_update_lock;
+	u8		update_bcn;
+#if USE_DEDICATED_BCN_TX
+	//Dedicated xmit frame and buffer for beacon update - Alex Fang
+	struct xmit_frame bcn_xmit_frame;
+	struct xmit_buf bcn_xmit_buf;
+	//u8 bcn_buf[256];
+	u8 bcn_buf[320];  //p2p go beacon size is about 272+32 bytes
+#endif
+#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
+
+#ifdef RTK_DMP_PLATFORM
+	// DMP kobject_hotplug function  signal need in passive level
+	_workitem	Linkup_workitem;
+	_workitem	Linkdown_workitem;
+#endif
+
+#ifdef CONFIG_INTEL_WIDI
+	int	widi_state;
+	int	listen_state;
+	_timer	listen_timer;
+	ATOMIC_T	rx_probe_rsp; // 1:receive probe respone from RDS source.
+	u8	*l2sdTaBuffer;
+	u8	channel_idx;
+	u8	group_cnt;	//In WiDi 3.5, they specified another scan algo. for WFD/RDS co-existed
+	u8	sa_ext[L2SDTA_SERVICE_VE_LEN];
+#endif // CONFIG_INTEL_WIDI
+
+#ifdef CONFIG_CONCURRENT_MODE
+	u8	scanning_via_buddy_intf;
+#endif
+
+#ifdef CONFIG_FTP_PROTECT
+	u8	ftp_lock_flag;
+#endif //CONFIG_FTP_PROTECT
+
+#ifdef CONFIG_MULTICAST
+	u32 multicast_list[MULTICAST_LIST_SIZE];
+#endif
+	//For fast reconnection to keep frame info temporarily
+	union recv_frame *p_copy_recv_frame;
+};
+
+#ifdef CONFIG_AP_MODE
+
+struct hostapd_priv
+{
+	_adapter *padapter;
+
+#ifdef CONFIG_HOSTAPD_MLME
+	struct net_device *pmgnt_netdev;
+	struct usb_anchor anchored;
+#endif	
+	
+};
+
+extern int hostapd_mode_init(_adapter *padapter);
+extern void hostapd_mode_unload(_adapter *padapter);
+#endif
+
+
+extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf);
+extern void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf);
+extern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf);
+extern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf);
+extern void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf);
+extern void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf);
+extern void rtw_atimdone_event_callback(_adapter *adapter, u8 *pbuf);
+extern void rtw_cpwm_event_callback(_adapter *adapter, u8 *pbuf);
+
+#ifdef PLATFORM_WINDOWS
+extern thread_return event_thread(void *context);
+
+extern void rtw_join_timeout_handler (
+	IN	PVOID					SystemSpecific1,
+	IN	PVOID					FunctionContext,
+	IN	PVOID					SystemSpecific2,
+	IN	PVOID					SystemSpecific3
+	);
+
+extern void _rtw_scan_timeout_handler (
+	IN	PVOID					SystemSpecific1,
+	IN	PVOID					FunctionContext,
+	IN	PVOID					SystemSpecific2,
+	IN	PVOID					SystemSpecific3
+	);
+
+#endif
+
+#if defined (PLATFORM_LINUX)|| defined (PLATFORM_FREEBSD)
+extern int event_thread(void *context);
+extern void rtw_join_timeout_handler(void* FunctionContext);
+extern void _rtw_scan_timeout_handler(void* FunctionContext);
+#endif
+
+extern void rtw_free_network_queue(_adapter *adapter,u8 isfreeall);
+extern int rtw_init_mlme_priv(_adapter *adapter);// (struct mlme_priv *pmlmepriv);
+
+extern void rtw_free_mlme_priv (struct mlme_priv *pmlmepriv);
+
+
+extern sint rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv);
+extern sint rtw_set_key(_adapter *adapter,struct security_priv *psecuritypriv,sint keyid, u8 set_tx);
+extern sint rtw_set_auth(_adapter *adapter,struct security_priv *psecuritypriv);
+extern sint rtw_linked_check(_adapter *padapter);
+
+__inline static u8 *get_bssid(struct mlme_priv *pmlmepriv)
+{	//if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid
+	// if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address
+	return pmlmepriv->cur_network.network.MacAddress;
+}
+
+__inline static sint check_fwstate(struct mlme_priv *pmlmepriv, sint state)
+{
+	if (pmlmepriv->fw_state & state)
+		return _TRUE;
+
+	return _FALSE;
+}
+
+__inline static sint get_fwstate(struct mlme_priv *pmlmepriv)
+{
+	return pmlmepriv->fw_state;
+}
+
+/*
+ * No Limit on the calling context,
+ * therefore set it to be the critical section...
+ *
+ * ### NOTE:#### (!!!!)
+ * MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock
+ */
+__inline static void set_fwstate(struct mlme_priv *pmlmepriv, sint state)
+{
+	pmlmepriv->fw_state |= state;
+	//FOR HW integration
+	if(_FW_UNDER_SURVEY==state){
+		pmlmepriv->bScanInProcess = _TRUE;
+	}
+}
+
+__inline static void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state)
+{
+	pmlmepriv->fw_state &= ~state;
+	//FOR HW integration
+	if(_FW_UNDER_SURVEY==state){
+		pmlmepriv->bScanInProcess = _FALSE;
+	}
+}
+
+/*
+ * No Limit on the calling context,
+ * therefore set it to be the critical section...
+ */
+__inline static void clr_fwstate(struct mlme_priv *pmlmepriv, sint state)
+{
+	_irqL irqL;
+
+	rtw_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	if (check_fwstate(pmlmepriv, state) == _TRUE)
+		pmlmepriv->fw_state ^= state;
+	rtw_exit_critical_bh(&pmlmepriv->lock, &irqL);
+}
+
+__inline static void clr_fwstate_ex(struct mlme_priv *pmlmepriv, sint state)
+{
+	_irqL irqL;
+
+	rtw_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	_clr_fwstate_(pmlmepriv, state);
+	rtw_exit_critical_bh(&pmlmepriv->lock, &irqL);
+}
+
+__inline static void up_scanned_network(struct mlme_priv *pmlmepriv)
+{
+	_irqL irqL;
+
+	rtw_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	pmlmepriv->num_of_scanned++;
+	rtw_exit_critical_bh(&pmlmepriv->lock, &irqL);
+}
+
+#ifdef CONFIG_CONCURRENT_MODE
+sint rtw_buddy_adapter_up(_adapter *padapter);
+sint check_buddy_fwstate(_adapter *padapter, sint state);
+#endif //CONFIG_CONCURRENT_MODE
+
+__inline static void down_scanned_network(struct mlme_priv *pmlmepriv)
+{
+	_irqL irqL;
+
+	rtw_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	pmlmepriv->num_of_scanned--;
+	rtw_exit_critical_bh(&pmlmepriv->lock, &irqL);
+}
+
+__inline static void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint val)
+{
+	_irqL irqL;
+
+	rtw_enter_critical_bh(&pmlmepriv->lock, &irqL);
+	pmlmepriv->num_of_scanned = val;
+	rtw_exit_critical_bh(&pmlmepriv->lock, &irqL);
+}
+
+extern u16 rtw_get_capability(WLAN_BSSID_EX *bss);
+extern void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target);
+extern void rtw_disconnect_hdl_under_linked(_adapter* adapter, struct sta_info *psta, u8 free_assoc);
+extern void rtw_generate_random_ibss(u8 *pibss);
+extern struct wlan_network* rtw_find_network(_queue *scanned_queue, u8 *addr);
+extern struct wlan_network* rtw_get_oldest_wlan_network(_queue *scanned_queue);
+
+extern void rtw_free_assoc_resources(_adapter* adapter, int lock_scanned_queue);
+extern void rtw_indicate_disconnect(_adapter* adapter);
+extern void rtw_indicate_connect(_adapter* adapter);
+void rtw_indicate_scan_done( _adapter *padapter, bool aborted);
+void rtw_scan_abort(_adapter *adapter);
+
+extern int rtw_restruct_sec_ie(_adapter *adapter,u8 *in_ie,u8 *out_ie,uint in_len);
+extern int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len);
+//extern void rtw_init_registrypriv_dev_network(_adapter *adapter);
+
+//extern void rtw_update_registrypriv_dev_network(_adapter *adapter);
+
+extern void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter);
+
+extern void _rtw_join_timeout_handler(_adapter *adapter);
+extern void rtw_scan_timeout_handler(_adapter *adapter);
+
+extern void rtw_dynamic_check_timer_handlder(_adapter *adapter);
+#ifdef CONFIG_SET_SCAN_DENY_TIMER
+extern void rtw_set_scan_deny_timer_hdl(_adapter *adapter);
+void rtw_set_scan_deny(struct mlme_priv *mlmepriv, u32 ms);
+#endif
+
+
+extern int _rtw_init_mlme_priv(_adapter *padapter);
+
+void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv);
+
+extern void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv);
+
+extern int _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork);
+
+extern struct wlan_network* _rtw_dequeue_network(_queue *queue);
+
+extern struct wlan_network* _rtw_alloc_network(struct mlme_priv *pmlmepriv);
+
+
+extern void _rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 isfreeall);
+extern void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork);
+
+
+extern struct wlan_network* _rtw_find_network(_queue *scanned_queue, u8 *addr);
+
+extern void _rtw_free_network_queue(_adapter* padapter, u8 isfreeall);
+
+extern sint rtw_if_up(_adapter *padapter);
+
+
+u8 *rtw_get_capability_from_ie(u8 *ie);
+u8 *rtw_get_timestampe_from_ie(u8 *ie);
+u8 *rtw_get_beacon_interval_from_ie(u8 *ie);
+
+
+void rtw_joinbss_reset(_adapter *padapter);
+
+#ifdef CONFIG_80211N_HT
+unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len);
+void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len);
+void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe);
+#endif
+
+int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork);
+int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst);
+
+#ifdef CONFIG_LAYER2_ROAMING
+void rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network);
+void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network);
+#endif
+
+
+#ifdef CONFIG_INTEL_PROXIM
+void rtw_proxim_enable(_adapter *padapter);
+void rtw_proxim_disable(_adapter *padapter);
+void rtw_proxim_send_packet(_adapter *padapter,u8 *pbuf,u16 len,u8 hw_rate);
+#endif //CONFIG_INTEL_PROXIM
+
+extern void rtw_os_indicate_disconnect( _adapter *adapter );
+extern void rtw_os_indicate_scan_done( _adapter *padapter, bool aborted);
+extern void rtw_reset_securitypriv( _adapter *adapter );
+#endif //__RTL871X_MLME_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_mp.h

@@ -0,0 +1,722 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef _RTW_MP_H_
+#define _RTW_MP_H_
+
+#ifndef PLATFORM_WINDOWS
+//	00 - Success
+//	11 - Error
+#define STATUS_SUCCESS				(0x00000000L)
+#define STATUS_PENDING				(0x00000103L)
+
+#define STATUS_UNSUCCESSFUL			(0xC0000001L)
+#define STATUS_INSUFFICIENT_RESOURCES		(0xC000009AL)
+#define STATUS_NOT_SUPPORTED			(0xC00000BBL)
+
+#define NDIS_STATUS_SUCCESS			((NDIS_STATUS)STATUS_SUCCESS)
+#define NDIS_STATUS_PENDING			((NDIS_STATUS)STATUS_PENDING)
+#define NDIS_STATUS_NOT_RECOGNIZED		((NDIS_STATUS)0x00010001L)
+#define NDIS_STATUS_NOT_COPIED			((NDIS_STATUS)0x00010002L)
+#define NDIS_STATUS_NOT_ACCEPTED		((NDIS_STATUS)0x00010003L)
+#define NDIS_STATUS_CALL_ACTIVE			((NDIS_STATUS)0x00010007L)
+
+#define NDIS_STATUS_FAILURE			((NDIS_STATUS)STATUS_UNSUCCESSFUL)
+#define NDIS_STATUS_RESOURCES			((NDIS_STATUS)STATUS_INSUFFICIENT_RESOURCES)
+#define NDIS_STATUS_CLOSING			((NDIS_STATUS)0xC0010002L)
+#define NDIS_STATUS_BAD_VERSION			((NDIS_STATUS)0xC0010004L)
+#define NDIS_STATUS_BAD_CHARACTERISTICS		((NDIS_STATUS)0xC0010005L)
+#define NDIS_STATUS_ADAPTER_NOT_FOUND		((NDIS_STATUS)0xC0010006L)
+#define NDIS_STATUS_OPEN_FAILED			((NDIS_STATUS)0xC0010007L)
+#define NDIS_STATUS_DEVICE_FAILED		((NDIS_STATUS)0xC0010008L)
+#define NDIS_STATUS_MULTICAST_FULL		((NDIS_STATUS)0xC0010009L)
+#define NDIS_STATUS_MULTICAST_EXISTS		((NDIS_STATUS)0xC001000AL)
+#define NDIS_STATUS_MULTICAST_NOT_FOUND		((NDIS_STATUS)0xC001000BL)
+#define NDIS_STATUS_REQUEST_ABORTED		((NDIS_STATUS)0xC001000CL)
+#define NDIS_STATUS_RESET_IN_PROGRESS		((NDIS_STATUS)0xC001000DL)
+#define NDIS_STATUS_CLOSING_INDICATING		((NDIS_STATUS)0xC001000EL)
+#define NDIS_STATUS_NOT_SUPPORTED		((NDIS_STATUS)STATUS_NOT_SUPPORTED)
+#define NDIS_STATUS_INVALID_PACKET		((NDIS_STATUS)0xC001000FL)
+#define NDIS_STATUS_OPEN_LIST_FULL		((NDIS_STATUS)0xC0010010L)
+#define NDIS_STATUS_ADAPTER_NOT_READY		((NDIS_STATUS)0xC0010011L)
+#define NDIS_STATUS_ADAPTER_NOT_OPEN		((NDIS_STATUS)0xC0010012L)
+#define NDIS_STATUS_NOT_INDICATING		((NDIS_STATUS)0xC0010013L)
+#define NDIS_STATUS_INVALID_LENGTH		((NDIS_STATUS)0xC0010014L)
+#define NDIS_STATUS_INVALID_DATA		((NDIS_STATUS)0xC0010015L)
+#define NDIS_STATUS_BUFFER_TOO_SHORT		((NDIS_STATUS)0xC0010016L)
+#define NDIS_STATUS_INVALID_OID			((NDIS_STATUS)0xC0010017L)
+#define NDIS_STATUS_ADAPTER_REMOVED		((NDIS_STATUS)0xC0010018L)
+#define NDIS_STATUS_UNSUPPORTED_MEDIA		((NDIS_STATUS)0xC0010019L)
+#define NDIS_STATUS_GROUP_ADDRESS_IN_USE	((NDIS_STATUS)0xC001001AL)
+#define NDIS_STATUS_FILE_NOT_FOUND		((NDIS_STATUS)0xC001001BL)
+#define NDIS_STATUS_ERROR_READING_FILE		((NDIS_STATUS)0xC001001CL)
+#define NDIS_STATUS_ALREADY_MAPPED		((NDIS_STATUS)0xC001001DL)
+#define NDIS_STATUS_RESOURCE_CONFLICT		((NDIS_STATUS)0xC001001EL)
+#define NDIS_STATUS_NO_CABLE			((NDIS_STATUS)0xC001001FL)
+
+#define NDIS_STATUS_INVALID_SAP			((NDIS_STATUS)0xC0010020L)
+#define NDIS_STATUS_SAP_IN_USE			((NDIS_STATUS)0xC0010021L)
+#define NDIS_STATUS_INVALID_ADDRESS		((NDIS_STATUS)0xC0010022L)
+#define NDIS_STATUS_VC_NOT_ACTIVATED		((NDIS_STATUS)0xC0010023L)
+#define NDIS_STATUS_DEST_OUT_OF_ORDER		((NDIS_STATUS)0xC0010024L)  // cause 27
+#define NDIS_STATUS_VC_NOT_AVAILABLE		((NDIS_STATUS)0xC0010025L)  // cause 35,45
+#define NDIS_STATUS_CELLRATE_NOT_AVAILABLE	((NDIS_STATUS)0xC0010026L)  // cause 37
+#define NDIS_STATUS_INCOMPATABLE_QOS		((NDIS_STATUS)0xC0010027L)  // cause 49
+#define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED	((NDIS_STATUS)0xC0010028L)  // cause 93
+#define NDIS_STATUS_NO_ROUTE_TO_DESTINATION	((NDIS_STATUS)0xC0010029L)  // cause 3
+#endif /* #ifndef PLATFORM_WINDOWS */
+
+#if 0
+#define MPT_NOOP			0
+#define MPT_READ_MAC_1BYTE		1
+#define MPT_READ_MAC_2BYTE		2
+#define MPT_READ_MAC_4BYTE		3
+#define MPT_WRITE_MAC_1BYTE		4
+#define MPT_WRITE_MAC_2BYTE		5
+#define MPT_WRITE_MAC_4BYTE		6
+#define MPT_READ_BB_CCK			7
+#define MPT_WRITE_BB_CCK		8
+#define MPT_READ_BB_OFDM		9
+#define MPT_WRITE_BB_OFDM		10
+#define MPT_READ_RF			11
+#define MPT_WRITE_RF			12
+#define MPT_READ_EEPROM_1BYTE		13
+#define MPT_WRITE_EEPROM_1BYTE		14
+#define MPT_READ_EEPROM_2BYTE		15
+#define MPT_WRITE_EEPROM_2BYTE		16
+#define MPT_SET_CSTHRESHOLD		21
+#define MPT_SET_INITGAIN		22
+#define MPT_SWITCH_BAND			23
+#define MPT_SWITCH_CHANNEL		24
+#define MPT_SET_DATARATE		25
+#define MPT_SWITCH_ANTENNA		26
+#define MPT_SET_TX_POWER		27
+#define MPT_SET_CONT_TX			28
+#define MPT_SET_SINGLE_CARRIER		29
+#define MPT_SET_CARRIER_SUPPRESSION	30
+#define MPT_GET_RATE_TABLE		31
+#define MPT_READ_TSSI			32
+#define MPT_GET_THERMAL_METER		33
+#endif
+
+typedef enum _ANTENNA_PATH{
+		ANTENNA_NONE	= 0x00,
+		ANTENNA_D		,
+		ANTENNA_C		,
+		ANTENNA_CD		,
+		ANTENNA_B		,
+		ANTENNA_BD		,
+		ANTENNA_BC		,
+		ANTENNA_BCD 	,
+		ANTENNA_A		,
+		ANTENNA_AD		,
+		ANTENNA_AC		,
+		ANTENNA_ACD 	,
+		ANTENNA_AB		,
+		ANTENNA_ABD 	,
+		ANTENNA_ABC 	,
+		ANTENNA_ABCD
+} ANTENNA_PATH;
+
+
+#define MAX_MP_XMITBUF_SZ 	2048
+#define NR_MP_XMITFRAME		8
+
+struct mp_xmit_frame
+{
+	_list	list;
+
+	struct pkt_attrib attrib;
+
+	_pkt *pkt;
+
+	int frame_tag;
+
+	_adapter *padapter;
+
+#ifdef CONFIG_USB_HCI
+
+	//insert urb, irp, and irpcnt info below...
+	//max frag_cnt = 8
+
+	u8 *mem_addr;
+	u32 sz[8];
+
+#if defined(PLATFORM_OS_XP) || defined(PLATFORM_LINUX)
+	PURB pxmit_urb[8];
+#endif
+
+#ifdef PLATFORM_OS_XP
+	PIRP pxmit_irp[8];
+#endif
+
+	u8 bpending[8];
+	s32 ac_tag[8];
+	s32 last[8];
+	uint irpcnt;
+	uint fragcnt;
+#endif /* CONFIG_USB_HCI */
+
+	uint mem[(MAX_MP_XMITBUF_SZ >> 2)];
+};
+
+struct mp_wiparam
+{
+	u32 bcompleted;
+	u32 act_type;
+	u32 io_offset;
+	u32 io_value;
+};
+
+typedef void(*wi_act_func)(void* padapter);
+
+#ifdef PLATFORM_WINDOWS
+struct mp_wi_cntx
+{
+	u8 bmpdrv_unload;
+
+	// Work Item
+	NDIS_WORK_ITEM mp_wi;
+	NDIS_EVENT mp_wi_evt;
+	_lock mp_wi_lock;
+	u8 bmp_wi_progress;
+	wi_act_func curractfunc;
+	// Variable needed in each implementation of CurrActFunc.
+	struct mp_wiparam param;
+};
+#endif
+
+struct mp_tx
+{
+	u8 stop;
+	u32 count, sended;
+	u8 payload;
+	struct pkt_attrib attrib;
+	struct tx_desc desc;
+	u8 *pallocated_buf;
+	u8 *buf;
+	u32 buf_size, write_size;
+	//_thread_hdl_	PktTxThread;
+	struct task_struct	MpXmitThread;
+};
+
+#define MP_MAX_LINES		1000
+#define MP_MAX_LINES_BYTES	256
+
+
+typedef void (*MPT_WORK_ITEM_HANDLER)(IN void *Adapter);
+typedef struct _MPT_CONTEXT
+{
+	// Indicate if we have started Mass Production Test.
+	BOOLEAN			bMassProdTest;
+
+	// Indicate if the driver is unloading or unloaded.
+	BOOLEAN			bMptDrvUnload;
+
+	_sema			MPh2c_Sema;
+	_timer			MPh2c_timeout_timer;
+// Event used to sync H2c for BT control
+
+	BOOLEAN		MptH2cRspEvent;
+	BOOLEAN		MptBtC2hEvent;
+	BOOLEAN		bMPh2c_timeout;
+
+	/* 8190 PCI does not support NDIS_WORK_ITEM. */
+	// Work Item for Mass Production Test.
+	//NDIS_WORK_ITEM	MptWorkItem;
+//	RT_WORK_ITEM		MptWorkItem;
+	// Event used to sync the case unloading driver and MptWorkItem is still in progress.
+//	NDIS_EVENT		MptWorkItemEvent;
+	// To protect the following variables.
+//	NDIS_SPIN_LOCK		MptWorkItemSpinLock;
+	// Indicate a MptWorkItem is scheduled and not yet finished.
+	BOOLEAN			bMptWorkItemInProgress;
+	// An instance which implements function and context of MptWorkItem.
+	MPT_WORK_ITEM_HANDLER	CurrMptAct;
+
+	// 1=Start, 0=Stop from UI.
+	u32			MptTestStart;
+	// _TEST_MODE, defined in MPT_Req2.h
+	u32			MptTestItem;
+	// Variable needed in each implementation of CurrMptAct.
+	u32			MptActType; 	// Type of action performed in CurrMptAct.
+	// The Offset of IO operation is depend of MptActType.
+	u32			MptIoOffset;
+	// The Value of IO operation is depend of MptActType.
+	u32			MptIoValue;
+	// The RfPath of IO operation is depend of MptActType.
+	u32			MptRfPath;
+
+	WIRELESS_MODE		MptWirelessModeToSw;	// Wireless mode to switch.
+	u8			MptChannelToSw; 	// Channel to switch.
+	u8			MptInitGainToSet; 	// Initial gain to set.
+	//u32			bMptAntennaA; 		// TRUE if we want to use antenna A.
+	u32			MptBandWidth;		// bandwidth to switch.
+	u32			MptRateIndex;		// rate index.
+	// Register value kept for Single Carrier Tx test.
+	u8			btMpCckTxPower;
+	// Register value kept for Single Carrier Tx test.
+	u8			btMpOfdmTxPower;
+	// For MP Tx Power index
+	u8			TxPwrLevel[2];	// rf-A, rf-B
+
+	// Content of RCR Regsiter for Mass Production Test.
+	u32			MptRCR;
+	// TRUE if we only receive packets with specific pattern.
+	BOOLEAN			bMptFilterPattern;
+ 	// Rx OK count, statistics used in Mass Production Test.
+ 	u32			MptRxOkCnt;
+ 	// Rx CRC32 error count, statistics used in Mass Production Test.
+ 	u32			MptRxCrcErrCnt;
+
+	BOOLEAN			bCckContTx;	// TRUE if we are in CCK Continuous Tx test.
+ 	BOOLEAN			bOfdmContTx;	// TRUE if we are in OFDM Continuous Tx test.
+	BOOLEAN			bStartContTx; 	// TRUE if we have start Continuous Tx test.
+	// TRUE if we are in Single Carrier Tx test.
+	BOOLEAN			bSingleCarrier;
+	// TRUE if we are in Carrier Suppression Tx Test.
+	BOOLEAN			bCarrierSuppression;
+	//TRUE if we are in Single Tone Tx test.
+	BOOLEAN			bSingleTone;
+
+	// ACK counter asked by K.Y..
+	BOOLEAN			bMptEnableAckCounter;
+	u32			MptAckCounter;
+
+	// SD3 Willis For 8192S to save 1T/2T RF table for ACUT	Only fro ACUT delete later ~~~!
+	//s8		BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT];
+	//s8			BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES];
+	//s32			RfReadLine[2];
+
+	u8		APK_bound[2];	//for APK	path A/path B
+	BOOLEAN		bMptIndexEven;
+
+	u8		backup0xc50;
+	u8		backup0xc58;
+	u8		backup0xc30;
+	u8 		backup0x52_RF_A;
+	u8 		backup0x52_RF_B;
+
+	u8			h2cReqNum;
+	u8			c2hBuf[20];
+
+	u8          btInBuf[100];
+	u32			mptOutLen;
+	u8          mptOutBuf[100];
+
+}MPT_CONTEXT, *PMPT_CONTEXT;
+//#endif
+
+//#define RTPRIV_IOCTL_MP 					( SIOCIWFIRSTPRIV + 0x17)
+enum {
+	WRITE_REG = 1,
+	READ_REG,
+	WRITE_RF,
+	READ_RF,
+	MP_START,
+	MP_STOP,
+	MP_RATE,
+	MP_CHANNEL,
+	MP_BANDWIDTH,
+	MP_TXPOWER,
+	MP_ANT_TX,
+	MP_ANT_RX,
+	MP_CTX,
+	MP_QUERY,
+	MP_ARX,
+	MP_PSD,
+	MP_PWRTRK,
+	MP_THER,
+	MP_IOCTL,
+	EFUSE_GET,
+	EFUSE_SET,
+	CONFIG_GET,
+	CONFIG_SET,
+	MP_RESET_STATS,
+	MP_DUMP,
+	MP_PHYPARA,
+	MP_SetRFPathSwh,
+	MP_QueryDrvStats,
+	MP_SetBT,
+	TEST_CFG,
+	MP_NULL,
+	MP_GET_TXPOWER_INX,
+	MP_SET_PREAMBLE,
+	MP_DISABLE_BT_COEXIST,
+	MP_PwrCtlDM,
+	MP_IQK,
+	MP_LCK,
+	MP_DRV_ABILITY
+};
+
+struct mp_priv
+{
+	_adapter *papdater;
+
+	//Testing Flag
+	u32 mode;//0 for normal type packet, 1 for loopback packet (16bytes TXCMD)
+
+	u32 prev_fw_state;
+
+	//OID cmd handler
+	struct mp_wiparam workparam;
+//	u8 act_in_progress;
+
+	//Tx Section
+	u8 TID;
+	u32 tx_pktcount;
+	struct mp_tx tx;
+
+	//Rx Section
+	u8 rx_pkt_by_mac;
+	u32 rx_pktcount;
+	u32 rx_crcerrpktcount;
+	u32 rx_macpktcount;
+	u32 rx_pktloss;
+	
+	struct recv_stat rxstat;
+
+	//RF/BB relative
+	u8 channel;
+	u8 bandwidth;
+	u8 prime_channel_offset;
+	u8 txpoweridx;
+	u8 txpoweridx_b;
+	u8 rateidx;
+	u32 preamble;
+//	u8 modem;
+	u32 CrystalCap;
+//	u32 curr_crystalcap;
+
+	u16 antenna_tx;
+	u16 antenna_rx;
+//	u8 curr_rfpath;
+
+	u8 check_mp_pkt;
+
+	u8 bSetTxPower;
+	u8 bCCKTxPowerAdjust;
+	u8 bFAStatistics;
+//	uint ForcedDataRate;
+	u8 mp_dm;
+	struct wlan_network mp_network;
+	NDIS_802_11_MAC_ADDRESS network_macaddr;
+
+#ifdef PLATFORM_WINDOWS
+	u32 rx_testcnt;
+	u32 rx_testcnt1;
+	u32 rx_testcnt2;
+	u32 tx_testcnt;
+	u32 tx_testcnt1;
+
+	struct mp_wi_cntx wi_cntx;
+
+	u8 h2c_result;
+	u8 h2c_seqnum;
+	u16 h2c_cmdcode;
+	u8 h2c_resp_parambuf[512];
+	_lock h2c_lock;
+	_lock wkitm_lock;
+	u32 h2c_cmdcnt;
+	NDIS_EVENT h2c_cmd_evt;
+	NDIS_EVENT c2h_set;
+	NDIS_EVENT h2c_clr;
+	NDIS_EVENT cpwm_int;
+
+	NDIS_EVENT scsir_full_evt;
+	NDIS_EVENT scsiw_empty_evt;
+#endif
+
+	u8 *pallocated_mp_xmitframe_buf;
+	u8 *pmp_xmtframe_buf;
+	_queue free_mp_xmitqueue;
+	u32 free_mp_xmitframe_cnt;
+
+	MPT_CONTEXT MptCtx;
+};
+
+typedef struct _IOCMD_STRUCT_ {
+	u8	cmdclass;
+	u16	value;
+	u8	index;
+}IOCMD_STRUCT;
+
+struct rf_reg_param {
+	u32 path;
+	u32 offset;
+	u32 value;
+};
+
+struct bb_reg_param {
+	u32 offset;
+	u32 value;
+};
+//=======================================================================
+
+#define LOWER 	_TRUE
+#define RAISE	_FALSE
+
+/* Hardware Registers */
+#if 0
+#if 0
+#define IOCMD_CTRL_REG			0x102502C0
+#define IOCMD_DATA_REG			0x102502C4
+#else
+#define IOCMD_CTRL_REG			0x10250370
+#define IOCMD_DATA_REG			0x10250374
+#endif
+
+#define IOCMD_GET_THERMAL_METER		0xFD000028
+
+#define IOCMD_CLASS_BB_RF		0xF0
+#define IOCMD_BB_READ_IDX		0x00
+#define IOCMD_BB_WRITE_IDX		0x01
+#define IOCMD_RF_READ_IDX		0x02
+#define IOCMD_RF_WRIT_IDX		0x03
+#endif
+#define BB_REG_BASE_ADDR		0x800
+
+/* MP variables */
+#if 0
+#define _2MAC_MODE_	0
+#define _LOOPBOOK_MODE_	1
+#endif
+typedef enum _MP_MODE_ {
+	MP_OFF,
+	MP_ON,
+	MP_ERR,
+	MP_CONTINUOUS_TX,
+	MP_SINGLE_CARRIER_TX,
+	MP_CARRIER_SUPPRISSION_TX,
+	MP_SINGLE_TONE_TX,
+	MP_PACKET_TX,
+	MP_PACKET_RX
+} MP_MODE;
+
+
+#define MAX_RF_PATH_NUMS	MAX_RF_PATH
+
+
+extern u8 mpdatarate[NumRates];
+
+/* MP set force data rate base on the definition. */
+typedef enum _MPT_RATE_INDEX
+{
+	/* CCK rate. */
+	MPT_RATE_1M,	/* 0 */
+	MPT_RATE_2M,
+	MPT_RATE_55M,
+	MPT_RATE_11M,	/* 3 */
+
+	/* OFDM rate. */
+	MPT_RATE_6M,	/* 4 */
+	MPT_RATE_9M,
+	MPT_RATE_12M,
+	MPT_RATE_18M,
+	MPT_RATE_24M,
+	MPT_RATE_36M,
+	MPT_RATE_48M,
+	MPT_RATE_54M,	/* 11 */
+
+	/* HT rate. */
+	MPT_RATE_MCS0,	/* 12 */
+	MPT_RATE_MCS1,
+	MPT_RATE_MCS2,
+	MPT_RATE_MCS3,
+	MPT_RATE_MCS4,
+	MPT_RATE_MCS5,
+	MPT_RATE_MCS6,
+	MPT_RATE_MCS7,	/* 19 */
+	MPT_RATE_MCS8,
+	MPT_RATE_MCS9,
+	MPT_RATE_MCS10,
+	MPT_RATE_MCS11,
+	MPT_RATE_MCS12,
+	MPT_RATE_MCS13,
+	MPT_RATE_MCS14,
+	MPT_RATE_MCS15,	/* 27 */
+	MPT_RATE_LAST
+}MPT_RATE_E, *PMPT_RATE_E;
+
+#define MAX_TX_PWR_INDEX_N_MODE 64	// 0x3F
+
+typedef enum _POWER_MODE_ {
+	POWER_LOW = 0,
+	POWER_NORMAL
+}POWER_MODE;
+
+
+#define RX_PKT_BROADCAST	1
+#define RX_PKT_DEST_ADDR	2
+#define RX_PKT_PHY_MATCH	3
+
+#if 0
+#define RPTMaxCount 0x000FFFFF;
+
+// parameter 1 : BitMask
+// 	bit 0  : OFDM PPDU
+//	bit 1  : OFDM False Alarm
+//	bit 2  : OFDM MPDU OK
+//	bit 3  : OFDM MPDU Fail
+//	bit 4  : CCK PPDU
+//	bit 5  : CCK False Alarm
+//	bit 6  : CCK MPDU ok
+//	bit 7  : CCK MPDU fail
+//	bit 8  : HT PPDU counter
+//	bit 9  : HT false alarm
+//	bit 10 : HT MPDU total
+//	bit 11 : HT MPDU OK
+//	bit 12 : HT MPDU fail
+//	bit 15 : RX full drop
+typedef enum _RXPHY_BITMASK_
+{
+	OFDM_PPDU_BIT = 0,
+	OFDM_FALSE_BIT,
+	OFDM_MPDU_OK_BIT,
+	OFDM_MPDU_FAIL_BIT,
+	CCK_PPDU_BIT,
+	CCK_FALSE_BIT,
+	CCK_MPDU_OK_BIT,
+	CCK_MPDU_FAIL_BIT,
+	HT_PPDU_BIT,
+	HT_FALSE_BIT,
+	HT_MPDU_BIT,
+	HT_MPDU_OK_BIT,
+	HT_MPDU_FAIL_BIT,
+} RXPHY_BITMASK;
+#endif
+
+typedef enum _ENCRY_CTRL_STATE_ {
+	HW_CONTROL,		//hw encryption& decryption
+	SW_CONTROL,		//sw encryption& decryption
+	HW_ENCRY_SW_DECRY,	//hw encryption & sw decryption
+	SW_ENCRY_HW_DECRY	//sw encryption & hw decryption
+}ENCRY_CTRL_STATE;
+
+typedef enum _PREAMBLE {
+		Long_Preamble	= 0x01,
+		Short_Preamble		  ,
+		Long_GI 			  ,
+		Short_GI
+} PREAMBLE;
+
+
+
+//=======================================================================
+//extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv);
+//extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe);
+
+extern s32 init_mp_priv(_adapter * padapter);
+extern void free_mp_priv(struct mp_priv *pmp_priv);
+extern s32 MPT_InitializeAdapter(_adapter * padapter, u8 Channel);
+extern void MPT_DeInitAdapter(_adapter * padapter);
+extern s32 mp_start_test(_adapter * padapter);
+extern void mp_stop_test(_adapter * padapter);
+
+//=======================================================================
+//extern void	IQCalibrateBcut(_adapter * pAdapter);
+
+//extern u32	bb_reg_read(_adapter * Adapter, u16 offset);
+//extern u8	bb_reg_write(_adapter * Adapter, u16 offset, u32 value);
+//extern u32	rf_reg_read(_adapter * Adapter, u8 path, u8 offset);
+//extern u8	rf_reg_write(_adapter * Adapter, u8 path, u8 offset, u32 value);
+
+//extern u32	get_bb_reg(_adapter * Adapter, u16 offset, u32 bitmask);
+//extern u8	set_bb_reg(_adapter * Adapter, u16 offset, u32 bitmask, u32 value);
+//extern u32	get_rf_reg(_adapter * Adapter, u8 path, u8 offset, u32 bitmask);
+//extern u8	set_rf_reg(_adapter * Adapter, u8 path, u8 offset, u32 bitmask, u32 value);
+
+extern u32 _read_rfreg(_adapter * padapter, u8 rfpath, u32 addr, u32 bitmask);
+extern void _write_rfreg(_adapter * padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val);
+
+extern u32 read_macreg(_adapter *padapter, u32 addr, u32 sz);
+extern void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz);
+extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask);
+extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val);
+extern u32 read_rfreg(_adapter * padapter, u8 rfpath, u32 addr);
+extern void write_rfreg(_adapter * padapter, u8 rfpath, u32 addr, u32 val);
+
+extern void	SetChannel(_adapter * pAdapter);
+extern void	SetBandwidth(_adapter * pAdapter);
+extern void	SetTxPower(_adapter * pAdapter);
+extern void	SetAntennaPathPower(_adapter * pAdapter);
+//extern void	SetTxAGCOffset(_adapter * pAdapter, u32 ulTxAGCOffset);
+extern void	SetDataRate(_adapter * pAdapter);
+
+extern void	SetAntenna(_adapter * pAdapter);
+
+//extern void	SetCrystalCap(_adapter * pAdapter);
+
+extern s32	SetThermalMeter(_adapter * pAdapter, u8 target_ther);
+extern void	GetThermalMeter(_adapter * pAdapter, u8 *value);
+
+extern void	SetContinuousTx(_adapter * pAdapter, u8 bStart);
+extern void	SetSingleCarrierTx(_adapter * pAdapter, u8 bStart);
+extern void	SetSingleToneTx(_adapter * pAdapter, u8 bStart);
+extern void	SetCarrierSuppressionTx(_adapter * pAdapter, u8 bStart);
+extern void PhySetTxPowerLevel(_adapter * pAdapter);
+
+extern void	fill_txdesc_for_mp(_adapter * padapter, struct tx_desc *ptxdesc);
+extern void	SetPacketTx(_adapter * padapter);
+extern void	SetPacketRx(_adapter * pAdapter, u8 bStartRx);
+
+extern void	ResetPhyRxPktCount(_adapter * pAdapter);
+extern u32	GetPhyRxPktReceived(_adapter * pAdapter);
+extern u32	GetPhyRxPktCRC32Error(_adapter * pAdapter);
+
+extern s32	SetPowerTracking(_adapter * padapter, u8 enable);
+extern void	GetPowerTracking(_adapter * padapter, u8 *enable);
+
+extern u32	mp_query_psd(_adapter * pAdapter, u8 *data);
+
+
+extern void Hal_SetAntenna(_adapter * pAdapter);
+extern void Hal_SetBandwidth(_adapter * pAdapter);
+
+extern void Hal_SetTxPower(_adapter * pAdapter);
+extern void Hal_SetCarrierSuppressionTx(_adapter * pAdapter, u8 bStart);
+extern void Hal_SetSingleToneTx ( _adapter * pAdapter , u8 bStart );
+extern void Hal_SetSingleCarrierTx (_adapter * pAdapter, u8 bStart);
+extern void Hal_SetContinuousTx (_adapter * pAdapter, u8 bStart);
+extern void Hal_SetBandwidth(_adapter * pAdapter);
+
+extern void Hal_SetDataRate(_adapter * pAdapter);
+extern void Hal_SetChannel(_adapter * pAdapter);
+extern void Hal_SetAntennaPathPower(_adapter * pAdapter);
+extern s32 Hal_SetThermalMeter(_adapter * pAdapter, u8 target_ther);
+extern s32 Hal_SetPowerTracking(_adapter * padapter, u8 enable);
+extern void Hal_GetPowerTracking(_adapter * padapter, u8 * enable);
+extern void Hal_GetThermalMeter(_adapter * pAdapter, u8 *value);
+extern void Hal_mpt_SwitchRfSetting(_adapter * pAdapter);
+extern void Hal_MPT_CCKTxPowerAdjust(_adapter * Adapter);
+extern void Hal_MPT_CCKTxPowerAdjustbyIndex(_adapter * pAdapter, BOOLEAN beven);
+extern void Hal_SetCCKTxPower(_adapter * pAdapter, u8 * TxPower);
+extern void Hal_SetOFDMTxPower(_adapter * pAdapter, u8 * TxPower);
+extern void Hal_TriggerRFThermalMeter(_adapter * pAdapter);
+extern u8 Hal_ReadRFThermalMeter(_adapter * pAdapter);
+extern void Hal_SetCCKContinuousTx(_adapter * pAdapter, u8 bStart);
+extern void Hal_SetOFDMContinuousTx(_adapter * pAdapter, u8 bStart);
+extern void Hal_ProSetCrystalCap (_adapter * pAdapter , u32 CrystalCapVal);
+extern void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv);
+extern void MP_PHY_SetRFPathSwitch(_adapter * pAdapter ,BOOLEAN bMain);
+extern u32 mpt_ProQueryCalTxPower(_adapter * pAdapter, u8 RfPath);
+extern void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart);
+
+#endif //_RTW_MP_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_p2p.h

@@ -0,0 +1,58 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef _RTW_P2P_H_
+#define _RTW_P2P_H_
+
+#define P2P_WILDCARD_SSID "DIRECT-"
+#define P2P_WILDCARD_SSID_LEN 7
+
+#define P2P_SEND_ACTION_AFTER_PROBE_RSP 1
+
+#define RTW_P2P_SEND_ACTION_SUCCESS	0
+#define RTW_P2P_SEND_ACTION_FAILED		2
+
+static inline bool rtw_p2p_chk_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
+{
+	return wdinfo->p2p_state == state;
+}
+static inline bool rtw_p2p_chk_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role)
+{
+	return wdinfo->role == role;
+}
+
+extern void rtw_p2p_remain_on_channel(_adapter *padapter, u8 channel, u8 wait_time);
+extern void rtw_p2p_cancel_remain_on_channel(_adapter *padapter);
+extern void rtw_p2p_special_scan_param(_adapter *padapter, u8 channel, u8 *mac);
+extern void rtw_p2p_set_p2p_role(_adapter *padapter, u32 role);
+extern void rtw_p2p_set_p2p_state(_adapter *padapter, u32 state);
+extern int rtw_p2p_send_mgnt(_adapter *padapter, u8 *data, u16 len, u16 flags);
+extern void rtw_p2p_indicate_mgnt(_adapter *padapter, u8 *data, u16 len, u8 channel);
+extern void rtw_indicate_sta_assoc(_adapter *padapter, u8 *addr, u8 *buf, u16 len);
+extern void rtw_p2p_indicate_sta_disassoc(_adapter *padapter, u8 *addr);
+extern void rtw_p2p_indicate_send_action_done(_adapter *padapter, u16 status);
+
+extern int rtw_p2p_init_mlme_ext(_adapter *padapter);
+extern void rtw_p2p_deinit_mlme_ext(_adapter *padapter);
+extern int rtw_init_p2p_wdinfo(_adapter *padapter);
+extern void rtw_deinit_p2p_wdinfo(_adapter *padapter);
+extern void rtw_p2p_pre_tx_scan_cmd_callback(_adapter *padapter);
+
+#endif //_RTW_P2P_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_promisc.h

@@ -0,0 +1,38 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef _RTW_PROMISC_H_
+#define _RTW_PROMISC_H_
+#include <drv_types.h>
+#ifdef CONFIG_PROMISC
+void promisc_deinit(_adapter *padapter);
+//void promisc_set_enable(_adapter *padapter, u8 enabled, u8 len_used);
+int promisc_recv_func(_adapter *padapter, union recv_frame *rframe);
+#endif
+int promisc_set(rtw_rcr_level_t enabled, void (*callback)(unsigned char*, unsigned int, void*), unsigned char len_used);
+unsigned char is_promisc_enabled(void);
+int promisc_get_fixed_channel(void * fixed_bssid, u8 * ssid, int *ssid_length);
+void promisc_issue_probereq(void);
+void promisc_issue_probersp(unsigned char *da);
+void promisc_stop_tx_beacn(void);
+void promisc_resume_tx_beacn(void);
+void promisc_get_ap_info(rtw_result_t (*func)(char *ssid, u8 ssid_len, s16 rssi, char channel, char security));
+#endif	//_RTW_PROMISC_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_psk.h

@@ -0,0 +1,341 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef _RTW_PSK_H_
+#define _RTW_PSK_H_
+
+#define GMK_LEN					32
+#define GTK_LEN					32
+#define PMK_LEN					32
+#define KEY_NONCE_LEN			32
+#define NumGroupKey				4
+#define KEY_RC_LEN				8
+#define KEY_IV_LEN				16
+#define KEY_RSC_LEN				8
+#define KEY_ID_LEN				8
+#define KEY_MIC_LEN				16
+#define KEY_MATERIAL_LEN		2
+#define PTK_LEN_EAPOLMIC        16
+#define PTK_LEN_EAPOLENC        16
+#define PTK_LEN_TKIP           	64
+#define PTK_LEN_CCMP            48
+#define LIB1X_ETHER_EAPOL_TYPE	0x888E
+
+#define DescTypePos				0
+#define KeyInfoPos				1
+#define KeyLenPos				3
+#define ReplayCounterPos		5
+#define KeyNoncePos				13
+#define KeyIVPos				45
+#define KeyRSCPos				61
+#define KeyIDPos				69
+#define KeyMICPos				77
+#define KeyDataLenPos			93
+#define KeyDataPos				95
+#define LIB1X_EAPOL_VER				1	//0000 0001B
+#define LIB1X_EAPOL_EAPPKT			0       //0000 0000B
+#define LIB1X_EAPOL_START			1	//0000 0001B
+#define LIB1X_EAPOL_LOGOFF			2       //0000 0010B
+#define LIB1X_EAPOL_KEY				3	//0000 0011B
+#define LIB1X_EAPOL_ENCASFALERT			4	//0000 0100B
+
+
+#define A_SHA_DIGEST_LEN		20
+#define ETHER_HDRLEN			14
+#define LIB1X_EAPOL_HDRLEN		4
+#define INFO_ELEMENT_SIZE       128
+#define MAX_EAPOLMSG_LEN        512
+#define MAX_EAPOLKEYMSG_LEN		(MAX_EAPOLMSG_LEN-(ETHER_HDRLEN+LIB1X_EAPOL_HDRLEN))
+#define EAPOLMSG_HDRLEN			95      //EAPOL-key payload length without KeyData
+#define WPA_ELEMENT_ID			0xDD
+#define WPA2_ELEMENT_ID			0x30
+
+#ifndef TRUE
+#define TRUE					1
+#endif
+#ifndef FALSE
+#define FALSE					0
+#endif
+
+#define ETHER_ADDRLEN					6
+#define PMK_EXPANSION_CONST				"Pairwise key expansion"
+#define PMK_EXPANSION_CONST_SIZE		22
+#define GMK_EXPANSION_CONST				"Group key expansion"
+#define GMK_EXPANSION_CONST_SIZE		19
+#define RANDOM_EXPANSION_CONST			"Init Counter"
+#define RANDOM_EXPANSION_CONST_SIZE		12
+
+#define	WLAN_REASON_MIC_FAILURE				14
+#define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT	15
+
+/*
+	2008-12-16, For Corega CG-WLCB54GL 54Mbps NIC interoperability issue.
+	The behavior of this NIC when it connect to the other AP with WPA/TKIP is:
+		AP	<----------------------> 	STA
+			....................
+			------------> Assoc Rsp (ok)
+			------------> EAPOL-key (4-way msg 1)
+			<------------ unknown TKIP encryption data
+			------------> EAPOL-key (4-way msg 1)
+			<------------ unknown TKIP encryption data
+			.....................
+			<------------ disassoc (code=8, STA is leaving) when the 5 seconds timer timeout counting from Assoc_Rsp is got.
+			....................
+			------------> Assoc Rsp (ok)
+			<-----------> EAPOL-key (4-way handshake success)
+
+	If MAX_RESEND_NUM=3, our AP will send disassoc (code=15, 4-way timeout) to STA before STA sending disassoc to AP.
+	And this NIC will always can not connect to our AP.
+	set MAX_RESEND_NUM=5 can fix this issue.
+ */
+//#define MAX_RESEND_NUM	3
+#define MAX_RESEND_NUM		5
+#define RESEND_TIME			1000
+
+#define GK_REKEY_TIME		3600000		//Set rekey period to 1 hour
+
+typedef enum {
+	desc_type_RSN	= 2,
+	desc_type_WPA	= 254
+} DescTypeRSN;
+
+typedef enum {
+	type_Group	= 0,
+	type_Pairwise	= 1
+} KeyType;
+
+typedef enum {
+	key_desc_ver1 	= 1,
+	key_desc_ver2 	= 2
+} KeyDescVer;
+
+enum {
+	PSK_WPA		= 1,
+	PSK_WPA2	= 2
+};
+
+enum {
+	PSK_STATE_IDLE,
+	PSK_STATE_PTKSTART,
+	PSK_STATE_PTKINITNEGOTIATING,
+	PSK_STATE_PTKINITDONE,
+};
+
+enum {
+	PSK_GSTATE_REKEYNEGOTIATING,
+	PSK_GSTATE_REKEYESTABLISHED,
+	PSK_GSTATE_KEYERROR,
+};
+
+typedef	struct _OCTET_STRING {
+	unsigned char	*Octet;
+	int		Length;
+} OCTET_STRING;
+
+typedef union _LARGE_INTEGER {
+	unsigned char 	charData[8];
+	struct {
+		unsigned long 	HighPart;
+		unsigned long 	LowPart;
+	} field;
+} LARGE_INTEGER, *PLARGE_INTEGER;
+
+typedef union _OCTET16_INTEGER {
+	unsigned char 	charData[16];
+	struct {
+		LARGE_INTEGER	HighPart;
+		LARGE_INTEGER	LowPart;
+	} field;
+} OCTET16_INTEGER;
+
+typedef union  _OCTET32_INTEGER {
+	unsigned char	charData[32];
+	struct {
+		OCTET16_INTEGER	HighPart;
+		OCTET16_INTEGER	LowPart;
+	} field;
+} OCTET32_INTEGER;
+
+// group key info
+typedef struct _wpa_global_info {
+	OCTET32_INTEGER		Counter;
+//Save PSK to global array
+//	unsigned char		PSK[A_SHA_DIGEST_LEN * 2];
+	int					GTKAuthenticator;
+	int					GKeyDoneStations;
+	int					GInitAKeys;
+	int					GUpdateStationKeys;
+	int					GkeyReady;
+	OCTET_STRING		AuthInfoElement;
+	unsigned char		AuthInfoBuf[INFO_ELEMENT_SIZE];
+	unsigned char		MulticastCipher;
+	OCTET_STRING		GNonce;
+	unsigned char		GNonceBuf[KEY_NONCE_LEN];
+	unsigned char		GTK[NumGroupKey][GTK_LEN];
+	unsigned char		GMK[GMK_LEN];
+	int					GN;
+	int					GM;
+	int					GTKRekey;
+#ifdef CONFIG_GK_REKEY
+	struct timer_list	GKRekeyTimer;
+#endif
+} WPA_GLOBAL_INFO;
+
+// wpa sta info
+typedef struct _wpa_sta_info {
+	int					state;
+	int					gstate;
+	int					RSNEnabled;		// bit0-WPA, bit1-WPA2
+	int					PInitAKeys;
+	unsigned char		UnicastCipher;
+	LARGE_INTEGER		CurrentReplayCounter;
+	LARGE_INTEGER		ReplayCounterStarted; // david+1-12-2007
+	OCTET_STRING		ANonce;
+	OCTET_STRING		SNonce;
+	unsigned char		AnonceBuf[KEY_NONCE_LEN];
+	unsigned char		SnonceBuf[KEY_NONCE_LEN];
+	unsigned char		PMK[PMK_LEN];
+ 	unsigned char		PTK[PTK_LEN_TKIP];
+	OCTET_STRING		EAPOLMsgRecvd;
+	OCTET_STRING		EAPOLMsgSend;
+	OCTET_STRING		EapolKeyMsgRecvd;
+	OCTET_STRING		EapolKeyMsgSend;
+	
+	unsigned char		eapSendBuf[MAX_EAPOLMSG_LEN];
+//	unsigned char		eapRecvdBuf[MAX_EAPOLMSG_LEN];
+	struct timer_list	resendTimer;
+	int					resendCnt;
+	int					clientHndshkProcessing;
+	int					clientHndshkDone;
+	int 				clientGkeyUpdate;
+	LARGE_INTEGER		clientMICReportReplayCounter;
+} WPA_STA_INFO;
+
+typedef struct _LIB1X_EAPOL_KEY
+{
+ 	unsigned char		key_desc_ver;
+ 	unsigned char		key_info[2];
+ 	unsigned char		key_len[2];
+ 	unsigned char		key_replay_counter[KEY_RC_LEN];
+ 	unsigned char		key_nounce[KEY_NONCE_LEN];
+ 	unsigned char		key_iv[KEY_IV_LEN];
+ 	unsigned char		key_rsc[KEY_RSC_LEN];
+ 	unsigned char		key_id[KEY_ID_LEN];
+ 	unsigned char		key_mic[KEY_MIC_LEN];
+ 	unsigned char		key_data_len[KEY_MATERIAL_LEN];
+ 	unsigned char		*key_data;
+} lib1x_eapol_key;
+
+struct lib1x_eapol
+{
+ 	unsigned char		protocol_version;
+ 	unsigned char		packet_type;			// This makes it odd in number !
+ 	unsigned short		packet_body_length;
+};
+
+struct wlan_ethhdr_t
+{
+	unsigned char		daddr[WLAN_ETHADDR_LEN];
+	unsigned char		saddr[WLAN_ETHADDR_LEN];
+	unsigned short		type;
+};
+
+typedef enum{
+        DOT11_PortStatus_Unauthorized,
+        DOT11_PortStatus_Authorized,
+        DOT11_PortStatus_Guest
+}DOT11_PORT_STATUS;
+
+#ifdef CONFIG_MOVE_PSK_TO_ROM
+static __inline__ OCTET_STRING SubStr(OCTET_STRING f, unsigned short s, unsigned short l)
+{
+	OCTET_STRING res;
+
+	res.Length = l;
+	res.Octet = f.Octet + s;
+
+	return res;
+}
+#endif
+
+#define SetSubStr(f,a,l)					memcpy(f.Octet+l,a.Octet,a.Length)
+#define GetKeyInfo0(f, mask) 				((f.Octet[KeyInfoPos + 1] & mask) ? 1 : 0)
+#define SetKeyInfo0(f,mask,b)				(f.Octet[KeyInfoPos + 1] = (f.Octet[KeyInfoPos + 1] & ~mask) | ( b?mask:0x0) )
+#define GetKeyInfo1(f, mask)				((f.Octet[KeyInfoPos] & mask) ? 1 : 0)
+#define SetKeyInfo1(f,mask,b)				(f.Octet[KeyInfoPos] = (f.Octet[KeyInfoPos] & ~mask) | ( b?mask:0x0) )
+
+// EAPOLKey
+#define Message_DescType(f)				(f.Octet[DescTypePos])
+#define Message_setDescType(f, type)		(f.Octet[DescTypePos] = type)
+// Key Information Filed
+#define Message_KeyDescVer(f)			(f.Octet[KeyInfoPos+1] & 0x07)
+#define Message_setKeyDescVer(f, v)		(f.Octet[KeyInfoPos+1] &= 0xf8) , f.Octet[KeyInfoPos+1] |= (v & 0x07)
+#define Message_KeyType(f)				GetKeyInfo0(f, 0x08)
+#define Message_setKeyType(f, b)			SetKeyInfo0(f,0x08,b)
+#define Message_KeyIndex(f)				((f.Octet[KeyInfoPos+1] & 0x30) >> 4) & 0x03
+#define Message_setKeyIndex(f, v)			(f.Octet[KeyInfoPos+1] &= 0xcf), f.Octet[KeyInfoPos+1] |= ((v<<4) & 0x30)
+#define Message_setInstall(f, b)			SetKeyInfo0(f,0x40,b)
+#define Message_setKeyAck(f, b)			SetKeyInfo0(f,0x80,b)
+
+#define Message_KeyMIC(f)				GetKeyInfo1(f, 0x01)
+#define Message_setKeyMIC(f, b)			SetKeyInfo1(f,0x01,b)
+#define Message_Secure(f)				GetKeyInfo1(f,0x02)
+#define Message_setSecure(f, b)			SetKeyInfo1(f,0x02,b)
+#define Message_Error(f)					GetKeyInfo1(f,0x04)
+#define Message_setError(f, b)				SetKeyInfo1(f,0x04,b)
+#define Message_Request(f)				GetKeyInfo1(f,0x08)
+#define Message_setRequest(f, b)			SetKeyInfo1(f,0x08,b)
+#define Message_setReserved(f, v)			(f.Octet[KeyInfoPos] |= (v<<4&0xff))
+#define Message_KeyLength(f)				((unsigned short)(f.Octet[KeyLenPos] <<8) + (unsigned short)(f.Octet[KeyLenPos+1]))
+#define Message_setKeyLength(f, v)		(f.Octet[KeyLenPos] = (v&0xff00) >>8 ,  f.Octet[KeyLenPos+1] = (v&0x00ff))
+
+#define Message_KeyNonce(f)				SubStr(f, KeyNoncePos, KEY_NONCE_LEN)
+#define Message_setKeyNonce(f, v)			SetSubStr(f, v, KeyNoncePos)
+#define Message_EqualKeyNonce(f1, f2)		memcmp(f1.Octet + KeyNoncePos, f2.Octet, KEY_NONCE_LEN)? 0:1
+#define Message_setKeyIV(f, v)			SetSubStr(f, v, KeyIVPos)
+#define Message_setKeyRSC(f, v)			SetSubStr(f, v, KeyRSCPos)
+#define Message_setKeyID(f, v)			SetSubStr(f, v, KeyIDPos)
+#define Message_setMIC(f, v)				SetSubStr(f, v, KeyMICPos)
+#define Message_KeyDataLength(f)			((unsigned short)(f.Octet[KeyDataLenPos] <<8) + (unsigned short)(f.Octet[KeyDataLenPos+1]))
+#define Message_setKeyDataLength(f, v)	(f.Octet[KeyDataLenPos] = (v&0xff00) >>8 ,  f.Octet[KeyDataLenPos+1] = (v&0x00ff))
+#define Message_setKeyData(f, v)			SetSubStr(f, v, KeyDataPos);
+
+#define Message_CopyReplayCounter(f1, f2)	memcpy(f1.Octet + ReplayCounterPos, f2.Octet + ReplayCounterPos, KEY_RC_LEN)
+#define Message_DefaultReplayCounter(li)	(((li.field.HighPart == 0xffffffff) && (li.field.LowPart == 0xffffffff) ) ?1:0)
+
+#define GET_MY_HWADDR(padapter)		((padapter)->eeprompriv.mac_addr)
+#define LargeIntegerOverflow(x)			(x.field.HighPart == 0xffffffff) && (x.field.LowPart == 0xffffffff)
+#define LargeIntegerZero(x)				memset(&x.charData, 0, 8)
+#define Octet16IntegerOverflow(x)			LargeIntegerOverflow(x.field.HighPart) && LargeIntegerOverflow(x.field.LowPart)
+#define Octet16IntegerZero(x)				memset(&x.charData, 0, 16)
+#define SetNonce(ocDst, oc32Counter)		SetEAPOL_KEYIV(ocDst, oc32Counter)
+
+void ClientSendEAPOL(_adapter *padapter, struct sta_info *psta, int resend);
+void SendEAPOL(_adapter *padapter, struct sta_info *psta, int resend);
+void EAPOLKeyRecvd(_adapter *padapter, struct sta_info *psta);
+void ClientEAPOLKeyRecvd(_adapter *padapter, struct sta_info *psta);
+void init_wpa_sta_info(_adapter *padapter, struct sta_info *psta);
+void psk_init(_adapter *padapter, unsigned char *pie, unsigned short ielen);
+void psk_derive(_adapter *padapter, unsigned char *passphrase, unsigned char *ssid);
+u16 psk_strip_rsn_pairwise(u8 *ie, u16 ie_len);
+u16 psk_strip_wpa_pairwise(u8 *ie, u16 ie_len);
+
+#endif // _RTW_PSK_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_pwrctrl.h

@@ -0,0 +1,386 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __RTW_PWRCTRL_H_
+#define __RTW_PWRCTRL_H_
+
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+#include <linux/earlysuspend.h>
+#endif //CONFIG_HAS_EARLYSUSPEND
+
+#define FW_PWR0		0	
+#define FW_PWR1 	1
+#define FW_PWR2 	2
+#define FW_PWR3 	3
+
+
+#define HW_PWR0		7	
+#define HW_PWR1 	6
+#define HW_PWR2 	2
+#define HW_PWR3		0
+#define HW_PWR4		8
+
+#define FW_PWRMSK	0x7
+
+
+#define XMIT_ALIVE	BIT(0)
+#define RECV_ALIVE	BIT(1)
+#define CMD_ALIVE	BIT(2)
+#define EVT_ALIVE	BIT(3)
+
+
+enum Power_Mgnt
+{
+	PS_MODE_ACTIVE	= 0	,
+	PS_MODE_MIN		,
+	PS_MODE_MAX		,
+	PS_MODE_DTIM		,
+	PS_MODE_VOIP		,
+	PS_MODE_UAPSD_WMM	,
+	PS_MODE_UAPSD		,
+	PS_MODE_IBSS		,
+	PS_MODE_WWLAN		,
+	PM_Radio_Off		,
+	PM_Card_Disable		,
+	PS_MODE_NUM
+};
+
+
+/*
+	BIT[2:0] = HW state
+	BIT[3] = Protocol PS state,   0: register active state , 1: register sleep state
+	BIT[4] = sub-state
+*/
+
+#define PS_DPS				BIT(0)
+#define PS_LCLK				(PS_DPS)
+#define PS_RF_OFF			BIT(1)
+#define PS_ALL_ON			BIT(2)
+#define PS_ST_ACTIVE		BIT(3)
+
+#define PS_ISR_ENABLE		BIT(4)
+#define PS_IMR_ENABLE		BIT(5)
+#define PS_ACK				BIT(6)
+#define PS_TOGGLE			BIT(7)
+
+#define PS_STATE_MASK		(0x0F)
+#define PS_STATE_HW_MASK	(0x07)
+#define PS_SEQ_MASK			(0xc0)
+
+#define PS_STATE(x)		(PS_STATE_MASK & (x))
+#define PS_STATE_HW(x)	(PS_STATE_HW_MASK & (x))
+#define PS_SEQ(x)		(PS_SEQ_MASK & (x))
+
+#define PS_STATE_S0		(PS_DPS)
+#define PS_STATE_S1		(PS_LCLK)
+#define PS_STATE_S2		(PS_RF_OFF)
+#define PS_STATE_S3		(PS_ALL_ON)
+#define PS_STATE_S4		((PS_ST_ACTIVE) | (PS_ALL_ON))
+
+
+#define PS_IS_RF_ON(x)	((x) & (PS_ALL_ON))
+#define PS_IS_ACTIVE(x)	((x) & (PS_ST_ACTIVE))
+#define CLR_PS_STATE(x)	((x) = ((x) & (0xF0)))
+
+
+struct reportpwrstate_parm {
+	unsigned char mode;
+	unsigned char state; //the CPWM value
+	unsigned short rsvd;
+}; 
+
+
+typedef _sema _pwrlock;
+
+
+__inline static void _init_pwrlock(_pwrlock *plock)
+{
+	rtw_init_sema(plock, 1);
+}
+
+__inline static void _free_pwrlock(_pwrlock *plock)
+{
+	rtw_free_sema(plock);
+}
+
+
+__inline static void _enter_pwrlock(_pwrlock *plock)
+{
+	rtw_down_sema(plock);
+}
+
+
+__inline static void _exit_pwrlock(_pwrlock *plock)
+{
+	rtw_up_sema(plock);
+}
+
+#define LPS_DELAY_TIME	1 // 1 sec
+
+#define EXE_PWR_NONE	0x01
+#define EXE_PWR_IPS		0x02
+#define EXE_PWR_LPS		0x04
+
+// RF state.
+typedef enum _rt_rf_power_state
+{
+	rf_on,		// RF is on after RFSleep or RFOff
+	rf_sleep,	// 802.11 Power Save mode
+	rf_off,		// HW/SW Radio OFF or Inactive Power Save
+	//=====Add the new RF state above this line=====//
+	rf_max
+}rt_rf_power_state;
+
+// RF Off Level for IPS or HW/SW radio off
+#define	RT_RF_OFF_LEVL_ASPM			BIT(0)	// PCI ASPM
+#define	RT_RF_OFF_LEVL_CLK_REQ		BIT(1)	// PCI clock request
+#define	RT_RF_OFF_LEVL_PCI_D3			BIT(2)	// PCI D3 mode
+#define	RT_RF_OFF_LEVL_HALT_NIC		BIT(3)	// NIC halt, re-initialize hw parameters
+#define	RT_RF_OFF_LEVL_FREE_FW		BIT(4)	// FW free, re-download the FW
+#define	RT_RF_OFF_LEVL_FW_32K		BIT(5)	// FW in 32k
+#define	RT_RF_PS_LEVEL_ALWAYS_ASPM	BIT(6)	// Always enable ASPM and Clock Req in initialization.
+#define	RT_RF_LPS_DISALBE_2R			BIT(30)	// When LPS is on, disable 2R if no packet is received or transmittd.
+#define	RT_RF_LPS_LEVEL_ASPM			BIT(31)	// LPS with ASPM
+
+#define	RT_IN_PS_LEVEL(ppsc, _PS_FLAG)		((ppsc->cur_ps_level & _PS_FLAG) ? _TRUE : _FALSE)
+#define	RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG)	(ppsc->cur_ps_level &= (~(_PS_FLAG)))
+#define	RT_SET_PS_LEVEL(ppsc, _PS_FLAG)		(ppsc->cur_ps_level |= _PS_FLAG)
+
+
+enum _PS_BBRegBackup_ {
+	PSBBREG_RF0 = 0,
+	PSBBREG_RF1,
+	PSBBREG_RF2,
+	PSBBREG_AFE0,
+	PSBBREG_TOTALCNT
+};
+
+enum { // for ips_mode
+	IPS_NONE=0,
+	IPS_NORMAL,
+	IPS_LEVEL_2,
+	IPS_NUM
+};
+
+struct pwrctrl_priv
+{
+	_pwrlock	lock;
+	volatile u8 rpwm; // requested power state for fw
+	volatile u8 cpwm; // fw current power state. updated when 1. read from HCPWM 2. driver lowers power level
+	volatile u8 tog; // toggling
+	volatile u8 cpwm_tog; // toggling
+
+	u8	pwr_mode;
+	u8	smart_ps;
+	u8	bcn_ant_mode;
+
+	u32	alives;
+	u64  wowlan_fw_iv;
+//TODO
+//	_workitem cpwm_event;
+#ifdef CONFIG_LPS_RPWM_TIMER
+	u8 brpwmtimeout;
+	_workitem rpwmtimeoutwi;
+	_timer pwr_rpwm_timer;
+#endif // CONFIG_LPS_RPWM_TIMER
+	u8	bpower_saving;
+
+	u8	b_hw_radio_off;
+	u8	reg_rfoff;
+	u8	reg_pdnmode; //powerdown mode
+	u32	rfoff_reason;
+
+	//RF OFF Level
+	u32	cur_ps_level;
+	u32	reg_rfps_level;
+
+
+
+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI)
+	//just for PCIE ASPM
+	u8	b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00. 
+	u8	b_support_backdoor;
+
+	//just for PCIE ASPM
+	u8	const_amdpci_aspm;
+#endif
+
+	uint 	ips_enter_cnts;
+	uint 	ips_leave_cnts;
+
+	u8	ps_enable;
+	u8	ips_mode; 
+	u8	ips_org_mode; 
+	u8	ips_mode_req; // used to accept the mode setting request, will update to ipsmode later
+	uint bips_processing;
+	u32 ips_deny_time; /* will deny IPS when system time is smaller than this */
+	u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */
+
+	u8	bLeisurePs;
+	u8	LpsIdleCount;
+	u8	power_mgnt;
+	u8	org_power_mgnt;
+	u8	bFwCurrentInPSMode;
+	u32	DelayLPSLastTimeStamp;
+	u8 	btcoex_rfon;
+	s32		pnp_current_pwr_state;
+	u8		pnp_bstop_trx;
+
+
+	u8		bInternalAutoSuspend;
+	u8		bInSuspend;
+#ifdef	CONFIG_BT_COEXIST
+	u8		bAutoResume;
+	u8		autopm_cnt;
+#endif
+	u8		bSupportRemoteWakeup;	
+#ifdef CONFIG_WOWLAN
+	u8      wowlan_txpause_status;
+	u8		wowlan_mode;
+	u8		wowlan_pattern;
+	u8		wowlan_magic;
+	u8		wowlan_unicast;
+	u8		wowlan_pattern_idx;
+	u8		wowlan_wake_reason;
+	u32		wowlan_pattern_context[8][5];
+#endif // CONFIG_WOWLAN
+	_timer 	pwr_state_check_timer;
+	int		pwr_state_check_interval;
+	u8		pwr_state_check_cnts;
+
+	int 		ps_flag;
+	
+	rt_rf_power_state	rf_pwrstate;//cur power state
+	//rt_rf_power_state 	current_rfpwrstate;
+	rt_rf_power_state	change_rfpwrstate;
+
+	u8		wepkeymask;
+	u8		bHWPowerdown;//if support hw power down
+	u8		bHWPwrPindetect;
+	u8		bkeepfwalive;		
+	u8		brfoffbyhw;
+	unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
+
+	#ifdef CONFIG_RESUME_IN_WORKQUEUE
+	struct workqueue_struct *rtw_workqueue;
+	_workitem resume_work;
+	#endif
+
+	#ifdef CONFIG_HAS_EARLYSUSPEND
+	struct early_suspend early_suspend;
+	u8 do_late_resume;
+	#endif //CONFIG_HAS_EARLYSUSPEND
+	
+	#ifdef CONFIG_ANDROID_POWER
+	android_early_suspend_t early_suspend;
+	u8 do_late_resume;
+	#endif
+
+	#ifdef CONFIG_INTEL_PROXIM
+	u8	stored_power_mgnt;
+	#endif
+
+	#ifdef TDMA_POWER_SAVING
+	u8	tdma_slot_period;
+    u8	tdma_rfon_period_len_1;
+    u8	tdma_rfon_period_len_2;
+    u8	tdma_rfon_period_len_3;
+	#endif
+
+	u8	lps_dtim;
+};
+
+#define rtw_get_ips_mode_req(pwrctrlpriv) \
+	(pwrctrlpriv)->ips_mode_req
+
+#define rtw_ips_mode_req(pwrctrlpriv, ips_mode) \
+	(pwrctrlpriv)->ips_mode_req = (ips_mode)
+
+#define RTW_PWR_STATE_CHK_INTERVAL 2000
+
+#define _rtw_set_pwr_state_check_timer(pwrctrlpriv, ms) \
+	do { \
+		/*DBG_871X("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctrlpriv), (ms));*/ \
+		rtw_set_timer(&(pwrctrlpriv)->pwr_state_check_timer, (ms)); \
+	} while(0)
+	
+#define rtw_set_pwr_state_check_timer(pwrctrlpriv) \
+	_rtw_set_pwr_state_check_timer((pwrctrlpriv), (pwrctrlpriv)->pwr_state_check_interval)
+
+extern void rtw_init_pwrctrl_priv(_adapter *adapter);
+extern void rtw_free_pwrctrl_priv(_adapter * adapter);
+
+#ifdef CONFIG_LPS_LCLK
+extern s32 rtw_register_tx_alive(PADAPTER padapter);
+extern void rtw_unregister_tx_alive(PADAPTER padapter);
+extern s32 rtw_register_rx_alive(PADAPTER padapter);
+extern void rtw_unregister_rx_alive(PADAPTER padapter);
+extern s32 rtw_register_cmd_alive(PADAPTER padapter);
+extern void rtw_unregister_cmd_alive(PADAPTER padapter);
+extern s32 rtw_register_evt_alive(PADAPTER padapter);
+extern void rtw_unregister_evt_alive(PADAPTER padapter);
+extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate);
+extern void LPS_Leave_check(PADAPTER padapter);
+#endif
+
+extern void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode);
+extern void rtw_set_rpwm(_adapter * padapter, u8 val8);
+extern void LeaveAllPowerSaveMode(PADAPTER Adapter);
+#ifdef CONFIG_IPS
+void ips_enter(_adapter * padapter);
+int ips_leave(_adapter * padapter);
+#endif
+
+void rtw_ps_processor(_adapter*padapter);
+
+#ifdef CONFIG_AUTOSUSPEND
+int autoresume_enter(_adapter* padapter);
+#endif
+#ifdef SUPPORT_HW_RFOFF_DETECTED
+rt_rf_power_state RfOnOffDetect(IN	PADAPTER pAdapter );
+#endif
+
+
+#ifdef CONFIG_LPS
+s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms);
+void LPS_Enter(PADAPTER padapter);
+void LPS_Leave(PADAPTER padapter);
+#endif
+
+#ifdef CONFIG_RESUME_IN_WORKQUEUE
+void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv);
+#endif //CONFIG_RESUME_IN_WORKQUEUE
+
+#if defined(CONFIG_HAS_EARLYSUSPEND ) || defined(CONFIG_ANDROID_POWER)
+#define rtw_is_earlysuspend_registered(pwrpriv) (pwrpriv)->early_suspend.suspend
+void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv);
+void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv);
+#endif //CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER
+//TODO
+//u8 rtw_interface_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id,u8* val);
+int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller);
+#define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__)
+int rtw_pm_set_ips(_adapter *padapter, u8 mode);
+int rtw_pm_set_lps(_adapter *padapter, u8 mode);
+int rtw_pm_set_tdma_param(_adapter *padapter, u8 tdma_slot_period, u8 tdma_rfon_period_len_1, u8 tdma_rfon_period_len_2, u8 tdma_rfon_period_len_3);
+int rtw_pm_set_lps_dtim(_adapter *padapter, u8 lps_dtim);
+u8 rtw_pm_get_lps_dtim(_adapter *padapter);
+#endif  //__RTL871X_PWRCTRL_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_qos.h

@@ -0,0 +1,33 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef _RTW_QOS_H_
+#define _RTW_QOS_H_
+
+struct	qos_priv	{
+	
+	u32	  qos_option;	//bit mask option: u-apsd, s-apsd, ts, block ack...		
+
+};
+
+
+#endif	//_RTL871X_QOS_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_recv.h

@@ -0,0 +1,918 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef _RTW_RECV_H_
+#define _RTW_RECV_H_
+#include <hal_pg.h>
+
+#if defined(PLATFORM_ECOS)
+#define NR_RECVFRAME 16	//Decrease recv frame due to memory limitation - Alex Fang
+#elif defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
+#ifdef CONFIG_RECV_REORDERING_CTRL
+#define NR_RECVFRAME 16	//Increase recv frame due to rx reorder - Andy Sun
+#else
+#if WIFI_LOGO_CERTIFICATION
+    #define NR_RECVFRAME 8	//Decrease recv frame due to memory limitation - Alex Fang
+#else
+#ifndef CONFIG_HIGH_TP
+    #define NR_RECVFRAME 2	//Decrease recv frame due to memory limitation - YangJue
+#else
+    #define NR_RECVFRAME 256
+#endif
+#endif
+#endif
+#else
+#define NR_RECVFRAME 256
+#endif
+
+#ifdef PLATFORM_OS_XP
+	#define NR_RECVBUFF (16)
+#elif defined(PLATFORM_OS_CE)
+	#define NR_RECVBUFF (4)
+#elif defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
+#ifndef CONFIG_HIGH_TP
+//	#define NR_RECVBUFF (8)	//Decrease recv buffer due to memory limitation - Alex Fang
+	#define NR_RECVBUFF (1)	//Decrease recv buffer due to memory limitation - YangJue
+#else
+	#define NR_RECVBUFF (32)
+#endif
+#else
+	#if (defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI)
+		#define NR_RECVBUFF (32)
+	#else
+		#define NR_RECVBUFF (4)
+	#endif
+
+	#define NR_PREALLOC_RECV_SKB (8)
+#endif
+
+#define RECV_BULK_IN_ADDR		0x80
+#define RECV_INT_IN_ADDR		0x81
+
+#define PHY_RSSI_SLID_WIN_MAX			100
+#define PHY_LINKQUALITY_SLID_WIN_MAX		20
+
+// Rx smooth factor
+#define Rx_Smooth_Factor (20)
+
+#define RXFRAME_ALIGN	8
+#define RXFRAME_ALIGN_SZ	(1<<RXFRAME_ALIGN)
+
+#define DRVINFO_SZ	4 // unit is 8bytes
+
+#define MAX_RXFRAME_CNT	512
+#define MAX_RX_NUMBLKS		(32)
+#define RECVFRAME_HDR_ALIGN 128
+
+#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
+
+#define RX_MPDU_QUEUE				0
+#define RX_CMD_QUEUE				1
+#define RX_MAX_QUEUE				2
+
+#define MAX_SUBFRAME_COUNT	64
+
+//for Rx reordering buffer control
+struct recv_reorder_ctrl
+{
+	_adapter	*padapter;
+	u8 enable;
+	u16 indicate_seq;//=wstart_b, init_value=0xffff
+	u16 wend_b;
+	u8 wsize_b;
+	_queue pending_recvframe_queue;
+	_timer reordering_ctrl_timer;
+};
+
+struct	stainfo_rxcache	{
+	u16 	tid_rxseq[16];
+/*
+	unsigned short 	tid0_rxseq;
+	unsigned short 	tid1_rxseq;
+	unsigned short 	tid2_rxseq;
+	unsigned short 	tid3_rxseq;
+	unsigned short 	tid4_rxseq;
+	unsigned short 	tid5_rxseq;
+	unsigned short 	tid6_rxseq;
+	unsigned short 	tid7_rxseq;
+	unsigned short 	tid8_rxseq;
+	unsigned short 	tid9_rxseq;
+	unsigned short 	tid10_rxseq;
+	unsigned short 	tid11_rxseq;
+	unsigned short 	tid12_rxseq;
+	unsigned short 	tid13_rxseq;
+	unsigned short 	tid14_rxseq;
+	unsigned short 	tid15_rxseq;
+*/
+};
+
+struct smooth_rssi_data {
+	u32	elements[100];	//array to store values
+	u32	index;			//index to current array to store
+	u32	total_num;		//num of valid elements
+	u32	total_val;		//sum of valid elements
+};
+
+struct signal_stat {
+	u8	update_req;		//used to indicate 
+	u8	avg_val;		//avg of valid elements
+	u32	total_num;		//num of valid elements
+	u32	total_val;		//sum of valid elements	
+};
+
+
+#if (RTL8195A_SUPPORT==1)
+/* struct phy_info must be same with ODM ODM_PHY_INFO_T, see rtl8195a_query_rx_phy_status() */
+struct phy_info
+{
+	u8		RxPWDBAll;
+	u8		SignalQuality;	 						// in 0-100 index. 
+	u8		RxMIMOSignalStrength[MAX_RF_PATH];		// in 0~100 index
+	s8		RecvSignalPower;						// Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures.
+	u8		SignalStrength; 						// in 0-100 index.
+	#if ((RTL8195A_SUPPORT == 0) && (RTL8711B_SUPPORT == 0))
+		s8		RxMIMOSignalQuality[MAX_RF_PATH];	// per-path's EVM
+		s8		RxPower;							// in dBm Translate from PWdB
+		u8		BTRxRSSIPercentage; 
+		s8		RxPwr[MAX_RF_PATH];				// per-path's pwdb
+		u8		RxSNR[MAX_RF_PATH];				// per-path's SNR	
+		u8		btCoexPwrAdjust;
+	#endif
+	#if (ODM_IC_11AC_SERIES_SUPPORT)
+		u8		RxMIMOEVMdbm[MAX_RF_PATH];		// per-path's EVM dbm
+		s16		Cfo_short[MAX_RF_PATH]; 		// per-path's Cfo_short
+		s16		Cfo_tail[MAX_RF_PATH];			// per-path's Cfo_tail
+		u8		BandWidth;
+	#endif
+};
+#elif(RTL8188F_SUPPORT == 1)
+struct phy_info
+{
+	u8		RxPWDBAll;
+
+	u8		SignalQuality;	 // in 0-100 index.
+	s8		RxMIMOSignalQuality[MAX_RF_PATH];	//per-path's EVM
+	u8		RxMIMOEVMdbm[MAX_RF_PATH]; 		//per-path's EVM dbm
+	u8		RxMIMOSignalStrength[MAX_RF_PATH];// in 0~100 index
+	u16		Cfo_short[MAX_RF_PATH]; 			// per-path's Cfo_short
+	u16		Cfo_tail[MAX_RF_PATH];			// per-path's Cfo_tail
+
+	s8		RxPower; // in dBm Translate from PWdB
+	s8		RecvSignalPower;// Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures.
+	u8		BTRxRSSIPercentage;
+	u8		SignalStrength; // in 0-100 index.
+	s8		RxPwr[MAX_RF_PATH];				//per-path's pwdb
+	u8		RxSNR[MAX_RF_PATH];				//per-path's SNR
+	u8		BandWidth;
+	u8		btCoexPwrAdjust;
+};
+#elif(RTL8711B_SUPPORT == 1)
+struct phy_info
+{
+	u8		RxPWDBAll;
+	
+	u8		SignalQuality;				/* in 0-100 index. */
+	s8		RxMIMOSignalQuality[4];		/* per-path's EVM */
+	u8		RxMIMOEVMdbm[4];			/* per-path's EVM dbm */
+	u8		RxMIMOSignalStrength[4];	/* in 0~100 index */
+	s16		Cfo_short[4];				/* per-path's Cfo_short */
+	s16		Cfo_tail[4];					/* per-path's Cfo_tail */
+	s8		RxPower;					/* in dBm Translate from PWdB */
+	s8		RecvSignalPower;			/* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */
+	u8		BTRxRSSIPercentage;
+	u8		SignalStrength;				/* in 0-100 index. */
+	s8		RxPwr[4];					/* per-path's pwdb */
+	s8		RxSNR[4];					/* per-path's SNR	*/
+	u8		RxCount:2;					/* RX path counter---*/
+	u8		BandWidth:2;
+	u8		rxsc:4;						/* sub-channel---*/
+	u8		btCoexPwrAdjust;
+	u8		channel;						/* channel number---*/
+	u8		bMuPacket;					/* is MU packet or not---*/
+	u8		bBeamformed;				/* BF packet---*/
+};
+#else
+#define MAX_PATH_NUM_92CS		2
+struct phy_info //ODM_PHY_INFO_T
+{	
+	u8		RxPWDBAll;	
+	u8		SignalQuality;	 // in 0-100 index. 
+	u8		RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; //EVM
+	u8		RxMIMOSignalStrength[MAX_PATH_NUM_92CS];// in 0~100 index
+	s8		RxPower; // in dBm Translate from PWdB
+	s8		RecvSignalPower;// Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures.
+	u8		BTRxRSSIPercentage;	
+	u8		SignalStrength; // in 0-100 index.
+	u8		RxPwr[MAX_PATH_NUM_92CS];//per-path's pwdb
+	u8		RxSNR[MAX_PATH_NUM_92CS];//per-path's SNR
+};
+#endif
+
+struct rx_pkt_attrib	{
+	u16	pkt_len;
+	u8	physt;
+	u8	drvinfo_sz;
+	u8	shift_sz;
+	u8	hdrlen; //the WLAN Header Len
+	u8 	to_fr_ds;
+	u8 	amsdu;
+	u8	qos;
+	u8	priority;
+	u8	pw_save;
+	u8	mdata;
+	u16	seq_num;
+	u8	frag_num;
+	u8	mfrag;
+	u8	order;
+	u8	privacy; //in frame_ctrl field
+	u8	bdecrypted;
+	u8	encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith
+	u8	iv_len;
+	u8	icv_len;
+	u8	crc_err;
+	u8	icv_err;
+
+	u16 eth_type;
+
+	u8 	dst[ETH_ALEN];
+	u8 	src[ETH_ALEN];
+	u8 	ta[ETH_ALEN];
+	u8 	ra[ETH_ALEN];
+	u8 	bssid[ETH_ALEN];
+	
+	u8 ack_policy;
+	
+//#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
+	u8	tcpchk_valid; // 0: invalid, 1: valid
+	u8	ip_chkrpt; //0: incorrect, 1: correct
+	u8	tcp_chkrpt; //0: incorrect, 1: correct
+//#endif
+	u8 	key_index;
+
+	u8	mcs_rate;
+	u8	rxht;
+	u8 	sgi;
+	u8 	pkt_rpt_type;
+	u32	MacIDValidEntry[2];	// 64 bits present 64 entry.
+
+
+	u8   data_rate;
+/*
+	u8	signal_qual;
+	s8	rx_mimo_signal_qual[2];
+	u8	signal_strength;
+	u32	RxPWDBAll;	
+	s32	RecvSignalPower;
+*/
+	struct phy_info phy_info;	
+};
+
+//These definition is used for Rx packet reordering.
+#define SN_LESS(a, b)		(((a-b)&0x800)!=0)
+#define SN_EQUAL(a, b)	(a == b)
+//#define REORDER_WIN_SIZE	128
+//#define REORDER_ENTRY_NUM	128
+#define REORDER_WAIT_TIME	(30) // (ms)
+
+#define RECVBUFF_ALIGN_SZ 8
+
+#define RXDESC_SIZE	24
+#define RXDESC_OFFSET RXDESC_SIZE
+
+struct recv_stat
+{
+	unsigned int rxdw0;
+
+	unsigned int rxdw1;
+
+	unsigned int rxdw2;
+
+	unsigned int rxdw3;
+
+	unsigned int rxdw4;
+
+	unsigned int rxdw5;
+
+#ifdef CONFIG_PCI_HCI
+	unsigned int rxdw6;
+
+	unsigned int rxdw7;
+#endif
+};
+
+
+struct recv_buf_stat {
+	unsigned int rxdw0;
+
+	unsigned int rxdw1;
+};
+
+#define EOR BIT(30)
+
+#if defined(CONFIG_LX_HCI)
+#define LX_MAX_RX_QUEUE		1// MSDU packet queue, Rx Command Queue
+#define LX_MAX_RX_COUNT		4//RX_Q_DESC_NUM// 128
+
+struct rtw_rx_ring {
+#if ((RTL8195A_SUPPORT ==1) ||(RTL8711B_SUPPORT == 1))
+	struct recv_buf_stat	*desc;
+#else
+	struct recv_stat	*desc;
+#endif
+
+	dma_addr_t		dma;
+	unsigned int		idx;
+	struct sk_buff	*rx_buf[LX_MAX_RX_COUNT];
+};
+#endif
+
+
+/*
+accesser of recv_priv: rtw_recv_entry(dispatch / passive level); recv_thread(passive) ; returnpkt(dispatch)
+; halt(passive) ;
+
+using enter_critical section to protect
+*/
+struct recv_priv
+{
+	_lock	lock;
+
+	//_queue	blk_strms[MAX_RX_NUMBLKS];    // keeping the block ack frame until return ack
+	_queue	free_recv_queue;
+	_queue	recv_pending_queue;
+	_queue	uc_swdec_pending_queue;
+
+
+	u8 *pallocated_frame_buf;
+	u8 *precv_frame_buf;
+
+	uint free_recvframe_cnt;
+
+	_adapter	*adapter;
+
+#ifdef PLATFORM_WINDOWS
+	_nic_hdl  RxPktPoolHdl;
+	_nic_hdl  RxBufPoolHdl;
+
+#ifdef PLATFORM_OS_XP
+	PMDL	pbytecnt_mdl;
+#endif
+	uint	counter; //record the number that up-layer will return to drv; only when counter==0 can we  release recv_priv
+	NDIS_EVENT 	recv_resource_evt ;
+#endif
+
+	u32	bIsAnyNonBEPkts;
+	u64	rx_bytes;
+	u64	rx_pkts;
+	u64	rx_drop;
+	u64 rx_overflow;
+	u64	last_rx_bytes;
+
+	uint  rx_icv_err;
+	uint  rx_largepacket_crcerr;
+	uint  rx_smallpacket_crcerr;
+	uint  rx_middlepacket_crcerr;
+
+#ifdef CONFIG_USB_HCI
+	//u8 *pallocated_urb_buf;
+	_sema allrxreturnevt;
+	uint	ff_hwaddr;
+	u8	rx_pending_cnt;
+
+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
+#ifdef PLATFORM_LINUX
+	PURB	int_in_urb;
+#endif
+
+	u8	*int_in_buf;
+#endif //CONFIG_USB_INTERRUPT_IN_PIPE
+
+#endif
+#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
+#ifdef PLATFORM_FREEBSD
+	struct task irq_prepare_beacon_tasklet;
+	struct task recv_tasklet;
+#else //PLATFORM_FREEBSD
+	struct tasklet_struct irq_prepare_beacon_tasklet;
+	struct tasklet_struct recv_tasklet;
+#endif //PLATFORM_FREEBSD
+	struct sk_buff_head free_recv_skb_queue;
+	struct sk_buff_head rx_skb_queue;
+#ifdef CONFIG_RX_INDICATE_QUEUE
+	struct task rx_indicate_tasklet;
+	struct ifqueue rx_indicate_queue;
+#endif	// CONFIG_RX_INDICATE_QUEUE
+
+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
+	_queue	recv_buf_pending_queue;
+#endif	// CONFIG_USE_USB_BUFFER_ALLOC_RX
+#endif //defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
+
+	u8 *pallocated_recv_buf;
+	u8 *precv_buf;    // 4 alignment
+	_queue	free_recv_buf_queue;
+	u32	free_recv_buf_queue_cnt;
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	_queue	recv_buf_pending_queue;
+#endif
+
+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI)
+	// Rx
+	struct rtw_rx_ring	rx_ring[LX_MAX_RX_QUEUE];
+	int 	rxringcount;
+	u16	rxbuffersize;
+#endif
+
+	//For display the phy informatiom
+	u8 is_signal_dbg;	// for debug
+	u8 signal_strength_dbg;	// for debug
+	s8 rssi;
+	s8 rxpwdb;
+	u8 signal_strength;
+	u8 signal_qual;
+	u8 noise;
+	int RxSNRdB[2];
+	s8 RxRssi[2];
+	int FalseAlmCnt_all;
+
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	_timer signal_stat_timer;
+	u32 signal_stat_sampling_interval;
+	//u32 signal_stat_converging_constant;
+	struct signal_stat signal_qual_data;
+	struct signal_stat signal_strength_data;
+#else //CONFIG_NEW_SIGNAL_STAT_PROCESS
+	struct smooth_rssi_data signal_qual_data;
+	struct smooth_rssi_data signal_strength_data;
+#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
+
+#ifdef CONFIG_PROMISC
+	u8 promisc_enabled;
+	u8 promisc_len_used;
+	_list promisc_list;
+	_lock promisc_lock;
+	u32 promisc_bk_rcr;
+	u16 promisc_bk_rxfltmap2;
+	u8 promisc_mgntframe_enabled;
+#endif
+};
+
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+#define rtw_set_signal_stat_timer(recvpriv) rtw_set_timer(&(recvpriv)->signal_stat_timer, (recvpriv)->signal_stat_sampling_interval)
+#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
+
+struct sta_recv_priv {
+
+	_lock	lock;
+	sint	option;
+
+	//_queue	blk_strms[MAX_RX_NUMBLKS];
+	_queue defrag_q;	 //keeping the fragment frame until defrag
+
+	struct	stainfo_rxcache rxcache;
+
+	//uint	sta_rx_bytes;
+	//uint	sta_rx_pkts;
+	//uint	sta_rx_fail;
+
+};
+
+struct recv_buf
+{
+	_list list;
+
+//	_lock recvbuf_lock;
+
+//	u32	ref_cnt;
+
+	PADAPTER adapter;
+
+//	u8	*pbuf;
+//	u8	*pallocated_buf;
+
+	u32	len;
+	u8	*phead;
+	u8	*pdata;
+	u8	*ptail;
+	u8	*pend;
+
+#ifdef CONFIG_USB_HCI
+
+	#if defined(PLATFORM_OS_XP)||defined(PLATFORM_LINUX)||defined(PLATFORM_FREEBSD)
+	PURB	purb;
+	dma_addr_t dma_transfer_addr;	/* (in) dma addr for transfer_buffer */
+	u32 alloc_sz;
+	#endif
+
+	#ifdef PLATFORM_OS_XP
+	PIRP		pirp;
+	#endif
+
+	#ifdef PLATFORM_OS_CE
+	USB_TRANSFER	usb_transfer_read_port;
+	#endif
+
+	u8  irp_pending;
+	int  transfer_len;
+
+#endif
+
+#if defined(PLATFORM_LINUX) || defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
+	_pkt	*pskb;
+//	u8	reuse;
+#endif
+#ifdef PLATFORM_FREEBSD //skb solution
+	struct sk_buff *pskb;
+	u8	reuse;
+#endif //PLATFORM_FREEBSD //skb solution
+};
+
+/*
+	head  ----->
+
+		data  ----->
+
+			payload
+
+		tail  ----->
+
+
+	end   ----->
+
+	len = (unsigned int )(tail - data);
+
+*/
+struct recv_frame_hdr
+{
+	_list	list;
+#ifndef CONFIG_BSD_RX_USE_MBUF
+	struct sk_buff	 *pkt;
+	struct sk_buff	 *pkt_newalloc;
+#else // CONFIG_BSD_RX_USE_MBUF
+	_pkt	*pkt;
+	_pkt *pkt_newalloc;
+#endif // CONFIG_BSD_RX_USE_MBUF
+
+	_adapter  *adapter;
+
+	u8 fragcnt;
+
+	int frame_tag;
+
+	struct rx_pkt_attrib attrib;
+
+	uint  len;
+	u8 *rx_head;
+	u8 *rx_data;
+	u8 *rx_tail;
+	u8 *rx_end;
+
+	void *precvbuf;
+
+
+	//
+	struct sta_info *psta;
+#ifdef CONFIG_RECV_REORDERING_CTRL
+	//for A-MPDU Rx reordering buffer control
+	struct recv_reorder_ctrl *preorder_ctrl;
+#endif
+#ifdef CONFIG_WAPI_SUPPORT
+	u8 UserPriority;
+	u8 WapiTempPN[16];
+	u8 WapiSrcAddr[6];
+	u8 bWapiCheckPNInDecrypt;
+	u8 bIsWaiPacket;
+#endif
+
+};
+
+union recv_frame{
+
+	union{
+		_list list;
+		struct recv_frame_hdr hdr;
+		uint mem[RECVFRAME_HDR_ALIGN>>2];
+	}u;
+
+	//uint mem[MAX_RXSZ>>2];
+
+};
+
+typedef enum _RX_PACKET_TYPE{
+	NORMAL_RX,//Normal rx packet
+	TX_REPORT1,//CCX
+	TX_REPORT2,//TX RPT
+	HIS_REPORT,// USB HISR RPT
+	C2H_PACKET
+}RX_PACKET_TYPE, *PRX_PACKET_TYPE;
+
+extern union recv_frame *_rtw_alloc_recvframe (_queue *pfree_recv_queue);  //get a free recv_frame from pfree_recv_queue
+extern void rtw_init_recvframe(union recv_frame *precvframe ,struct recv_priv *precvpriv);
+extern int	 rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue);
+
+#define rtw_dequeue_recvframe(queue) rtw_alloc_recvframe(queue)
+extern int _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue);
+
+#ifdef CONFIG_TRACE_SKB
+int __rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue);
+union recv_frame *__rtw_alloc_recvframe (_queue *pfree_recv_queue);  //get a free recv_frame from pfree_recv_queue
+
+#define rtw_enqueue_recvframe(precvframe, queue, Q) \
+	do{\
+		set_skb_list_flag(precvframe->u.hdr.pkt, SKBLIST_RECVFRAME_##Q);\
+		__rtw_enqueue_recvframe(precvframe, queue);\
+	}while (0)
+#define rtw_alloc_recvframe(queue, precvframe, Q) \
+	(\
+		precvframe = __rtw_alloc_recvframe(queue),\
+		precvframe ? clear_skb_list_flag(precvframe->u.hdr.pkt, SKBLIST_RECVFRAME_##Q):0,\
+		precvframe\
+	)
+#else
+extern int rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue);
+extern union recv_frame *rtw_alloc_recvframe (_queue *pfree_recv_queue);  //get a free recv_frame from pfree_recv_queue
+#endif
+
+extern void rtw_free_recvframe_queue(_queue *pframequeue,  _queue *pfree_recv_queue);
+u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter);
+
+#ifdef CONFIG_TRACE_SKB
+sint _rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue);
+sint _rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue);
+struct recv_buf *_rtw_dequeue_recvbuf (_queue *queue);
+
+#define rtw_enqueue_recvbuf_to_head(precvbuf, queue, Q) \
+	do{\
+		set_skb_list_flag(precvbuf->pskb, SKBLIST_RECVBUF_##Q);\
+		_rtw_enqueue_recvbuf_to_head(precvbuf, queue);\
+	}while (0)
+#define rtw_enqueue_recvbuf(precvbuf, queue, Q) \
+	do{\
+		set_skb_list_flag(precvbuf->pskb, SKBLIST_RECVBUF_##Q);\
+		_rtw_enqueue_recvbuf(precvbuf, queue);\
+	}while (0)
+#define rtw_dequeue_recvbuf(queue, precvbuf, Q) \
+	(\
+		precvbuf = _rtw_dequeue_recvbuf(queue),\
+		precvbuf ? clear_skb_list_flag(precvbuf->pskb, SKBLIST_RECVBUF_##Q):0,\
+		precvbuf\
+	)
+
+#else
+sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue);
+sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue);
+struct recv_buf *rtw_dequeue_recvbuf (_queue *queue);
+#endif
+
+void rtw_reordering_ctrl_timeout_handler(void *pcontext);
+
+
+__inline static u8 *get_rxmem(union recv_frame *precvframe)
+{
+	//always return rx_head...
+	if(precvframe==NULL)
+		return NULL;
+
+	return precvframe->u.hdr.rx_head;
+}
+
+__inline static u8 *get_rx_status(union recv_frame *precvframe)
+{
+
+	return get_rxmem(precvframe);
+
+}
+
+
+
+__inline static u8 *get_recvframe_data(union recv_frame *precvframe)
+{
+
+	//alwasy return rx_data
+	if(precvframe==NULL)
+		return NULL;
+
+	return precvframe->u.hdr.rx_data;
+
+}
+
+//TODO
+#if 0
+
+__inline static u8 *recvframe_push(union recv_frame *precvframe, sint sz)
+{
+	// append data before rx_data
+
+	/* add data to the start of recv_frame
+ *
+ *      This function extends the used data area of the recv_frame at the buffer
+ *      start. rx_data must be still larger than rx_head, after pushing.
+ */
+
+	if(precvframe==NULL)
+		return NULL;
+
+
+	precvframe->u.hdr.rx_data -= sz ;
+	if( precvframe->u.hdr.rx_data < precvframe->u.hdr.rx_head )
+	{
+		precvframe->u.hdr.rx_data += sz ;
+		return NULL;
+	}
+
+	precvframe->u.hdr.len +=sz;
+
+	return precvframe->u.hdr.rx_data;
+
+}
+
+#endif	//#if 0
+
+__inline static u8 *recvframe_pull(union recv_frame *precvframe, sint sz)
+{
+	// rx_data += sz; move rx_data sz bytes  hereafter
+
+	//used for extract sz bytes from rx_data, update rx_data and return the updated rx_data to the caller
+
+
+	if(precvframe==NULL)
+		return NULL;
+
+
+	precvframe->u.hdr.rx_data += sz;
+
+	if(precvframe->u.hdr.rx_data > precvframe->u.hdr.rx_tail)
+	{
+		precvframe->u.hdr.rx_data -= sz;
+		return NULL;
+	}
+
+	precvframe->u.hdr.len -=sz;
+
+	return precvframe->u.hdr.rx_data;
+
+}
+
+__inline static u8 *recvframe_put(union recv_frame *precvframe, sint sz)
+{
+	// rx_tai += sz; move rx_tail sz bytes  hereafter
+
+	//used for append sz bytes from ptr to rx_tail, update rx_tail and return the updated rx_tail to the caller
+	//after putting, rx_tail must be still larger than rx_end. 	
+
+	if(precvframe==NULL)
+		return NULL;
+
+	precvframe->u.hdr.rx_tail += sz;
+
+	if(precvframe->u.hdr.rx_tail > precvframe->u.hdr.rx_end)
+	{
+		precvframe->u.hdr.rx_tail -= sz;
+		return NULL;
+	}
+
+	precvframe->u.hdr.len +=sz;
+
+	return precvframe->u.hdr.rx_tail;
+
+}
+
+
+
+__inline static u8 *recvframe_pull_tail(union recv_frame *precvframe, sint sz)
+{
+	// rmv data from rx_tail (by yitsen)
+
+	//used for extract sz bytes from rx_end, update rx_end and return the updated rx_end to the caller
+	//after pulling, rx_end must be still larger than rx_data.
+
+	if(precvframe==NULL)
+		return NULL;
+
+	precvframe->u.hdr.rx_tail -= sz;
+
+	if(precvframe->u.hdr.rx_tail < precvframe->u.hdr.rx_data)
+	{
+		precvframe->u.hdr.rx_tail += sz;
+		return NULL;
+	}
+
+	precvframe->u.hdr.len -=sz;
+
+	return precvframe->u.hdr.rx_tail;
+
+}
+
+__inline static _buffer * get_rxbuf_desc(union recv_frame *precvframe)
+{
+	_buffer * buf_desc = NULL;
+
+	if(precvframe==NULL)
+		return NULL;
+#ifdef PLATFORM_WINDOWS
+	NdisQueryPacket(precvframe->u.hdr.pkt, NULL, NULL, &buf_desc, NULL);
+#endif
+
+	return buf_desc;
+}
+
+
+__inline static union recv_frame *rxmem_to_recvframe(u8 *rxmem)
+{
+	//due to the design of 2048 bytes alignment of recv_frame, we can reference the union recv_frame
+	//from any given member of recv_frame.
+	// rxmem indicates the any member/address in recv_frame
+
+	return (union recv_frame*)(((SIZE_PTR)rxmem >> RXFRAME_ALIGN) << RXFRAME_ALIGN);
+
+}
+
+__inline static union recv_frame *pkt_to_recvframe(_pkt *pkt)
+{
+
+	u8 * buf_star = NULL;
+	union recv_frame * precv_frame = NULL;
+#ifdef PLATFORM_WINDOWS
+	_buffer * buf_desc;
+	uint len;
+
+	NdisQueryPacket(pkt, NULL, NULL, &buf_desc, &len);
+	NdisQueryBufferSafe(buf_desc, &buf_star, &len, HighPagePriority);
+#endif
+	precv_frame = rxmem_to_recvframe((unsigned char*)buf_star);
+
+	return precv_frame;
+}
+
+__inline static u8 *pkt_to_recvmem(_pkt *pkt)
+{
+	// return the rx_head
+
+	union recv_frame * precv_frame = pkt_to_recvframe(pkt);
+
+	return 	precv_frame->u.hdr.rx_head;
+
+}
+
+__inline static u8 *pkt_to_recvdata(_pkt *pkt)
+{
+	// return the rx_data
+
+	union recv_frame * precv_frame =pkt_to_recvframe(pkt);
+
+	return 	precv_frame->u.hdr.rx_data;
+
+}
+
+
+__inline static sint get_recvframe_len(union recv_frame *precvframe)
+{
+	return precvframe->u.hdr.len;
+}
+
+
+__inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex)
+{
+	s32	SignalPower; // in dBm.
+
+#ifndef CONFIG_SKIP_SIGNAL_SCALE_MAPPING
+	// Translate to dBm (x=0.9y-95).
+	SignalPower = (s32)((SignalStrengthIndex *18) /20); 
+	SignalPower -= 95; 
+#else
+	/* Translate to dBm (x=y-100) */
+	SignalPower = SignalStrengthIndex - 100;
+#endif
+
+	return SignalPower;
+}
+
+
+struct sta_info;
+
+extern void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv);
+extern void  mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame);
+int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe);
+
+void rtw_rxhandler(_adapter * padapter, struct recv_buf *precvbuf);
+u32 rtw_free_buf_pending_queue(_adapter *adapter);
+
+#endif
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_rf.h

@@ -0,0 +1,175 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef	__RTW_RF_H_ 
+#define __RTW_RF_H_
+
+
+#define OFDM_PHY		1
+#define MIXED_PHY		2
+#define CCK_PHY		3
+
+#define NumRates	(13)
+
+// slot time for 11g
+#define SHORT_SLOT_TIME					9
+#define NON_SHORT_SLOT_TIME				20
+
+#define RTL8711_RF_MAX_SENS 6
+#define RTL8711_RF_DEF_SENS 4
+
+//
+// We now define the following channels as the max channels in each channel plan.
+// 2G, total 14 chnls
+// {1,2,3,4,5,6,7,8,9,10,11,12,13,14}
+// 5G, total 24 chnls
+// {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}
+#define	MAX_CHANNEL_NUM_2G				14
+#define	MAX_CHANNEL_NUM_5G				24
+#if defined(NOT_SUPPORT_5G)
+#define	MAX_CHANNEL_NUM					14
+#else
+#define	MAX_CHANNEL_NUM					38//14+24
+#endif
+
+//#define NUM_REGULATORYS	21
+#define NUM_REGULATORYS	1
+
+//Country codes
+#define USA							0x555320
+#define EUROPE						0x1 //temp, should be provided later	
+#define JAPAN						0x2 //temp, should be provided later	
+
+struct	regulatory_class {
+	u32	starting_freq;					//MHz, 
+	u8	channel_set[MAX_CHANNEL_NUM];
+	u8	channel_cck_power[MAX_CHANNEL_NUM];//dbm
+	u8	channel_ofdm_power[MAX_CHANNEL_NUM];//dbm
+	u8	txpower_limit;  				//dbm
+	u8	channel_spacing;				//MHz
+	u8	modem;
+};
+
+typedef enum _CAPABILITY{
+	cESS			= 0x0001,
+	cIBSS			= 0x0002,
+	cPollable		= 0x0004,
+	cPollReq			= 0x0008,
+	cPrivacy		= 0x0010,
+	cShortPreamble	= 0x0020,
+	cPBCC			= 0x0040,
+	cChannelAgility	= 0x0080,
+	cSpectrumMgnt	= 0x0100,
+	cQos			= 0x0200,	// For HCCA, use with CF-Pollable and CF-PollReq
+	cShortSlotTime	= 0x0400,
+	cAPSD			= 0x0800,
+	cRM				= 0x1000,	// RRM (Radio Request Measurement)
+	cDSSS_OFDM	= 0x2000,
+	cDelayedBA		= 0x4000,
+	cImmediateBA	= 0x8000,
+}CAPABILITY, *PCAPABILITY;
+
+enum	_REG_PREAMBLE_MODE{
+	PREAMBLE_LONG	= 1,
+	PREAMBLE_AUTO	= 2,
+	PREAMBLE_SHORT	= 3,
+};
+
+
+enum _RTL8712_RF_MIMO_CONFIG_{
+ RTL8712_RFCONFIG_1T=0x10,
+ RTL8712_RFCONFIG_2T=0x20,
+ RTL8712_RFCONFIG_1R=0x01,
+ RTL8712_RFCONFIG_2R=0x02,
+ RTL8712_RFCONFIG_1T1R=0x11,
+ RTL8712_RFCONFIG_1T2R=0x12,
+ RTL8712_RFCONFIG_TURBO=0x92,
+ RTL8712_RFCONFIG_2T2R=0x22
+};
+
+
+typedef enum _RF90_RADIO_PATH{
+	RF90_PATH_A = 0,			//Radio Path A
+	RF90_PATH_B = 1,			//Radio Path B
+	RF90_PATH_C = 2,			//Radio Path C
+	RF90_PATH_D = 3 		//Radio Path D
+	//RF90_PATH_MAX 			//Max RF number 90 support
+}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
+
+// Bandwidth Offset
+#define HAL_PRIME_CHNL_OFFSET_DONT_CARE	0
+#define HAL_PRIME_CHNL_OFFSET_LOWER	1
+#define HAL_PRIME_CHNL_OFFSET_UPPER	2
+
+// Represent Channel Width in HT Capabilities
+//
+typedef enum _CHANNEL_WIDTH{
+	CHANNEL_WIDTH_20 = 0,
+	CHANNEL_WIDTH_40 = 1,
+	CHANNEL_WIDTH_80 = 2,
+	CHANNEL_WIDTH_160 = 3,
+	CHANNEL_WIDTH_80_80 = 4,
+	CHANNEL_WIDTH_MAX = 5,
+}CHANNEL_WIDTH, *PCHANNEL_WIDTH;
+
+//
+// Represent Extention Channel Offset in HT Capabilities
+// This is available only in 40Mhz mode.
+//
+typedef enum _EXTCHNL_OFFSET{
+	EXTCHNL_OFFSET_NO_EXT = 0,
+	EXTCHNL_OFFSET_UPPER = 1,
+	EXTCHNL_OFFSET_NO_DEF = 2,
+	EXTCHNL_OFFSET_LOWER = 3,
+}EXTCHNL_OFFSET, *PEXTCHNL_OFFSET;
+
+typedef enum _VHT_DATA_SC{
+	VHT_DATA_SC_DONOT_CARE = 0,
+	VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
+	VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
+	VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
+	VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
+	VHT_DATA_SC_20_RECV1 = 5,
+	VHT_DATA_SC_20_RECV2 = 6,
+	VHT_DATA_SC_20_RECV3 = 7,
+	VHT_DATA_SC_20_RECV4 = 8,
+	VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
+	VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
+}VHT_DATA_SC, *PVHT_DATA_SC_E;
+
+
+
+/* 2007/11/15 MH Define different RF type. */
+typedef	enum _RT_RF_TYPE_DEFINITION
+{
+	RF_1T2R = 0,
+	RF_2T4R = 1,
+	RF_2T2R = 2,
+	RF_1T1R = 3,
+	RF_2T2R_GREEN = 4,
+	RF_819X_MAX_TYPE = 5,
+}RT_RF_TYPE_DEF_E;
+
+
+u32 rtw_ch2freq(u32 ch);
+u32 rtw_freq2ch(u32 freq);
+
+
+#endif //_RTL8711_RF_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_security.h

@@ -0,0 +1,446 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __RTW_SECURITY_H_
+#define __RTW_SECURITY_H_
+
+
+#define _NO_PRIVACY_		0x0
+#define _WEP40_				0x1
+#define _TKIP_				0x2
+#define _TKIP_WTMIC_		0x3
+#define _AES_				0x4
+#define _WEP104_			0x5
+#define _WEP_WPA_MIXED_		0x07  // WEP + WPA
+#define _SMS4_				0x06
+
+#define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_))
+
+#define _WPA_IE_ID_	0xdd
+#define _WPA2_IE_ID_	0x30
+
+#define SHA256_MAC_LEN 32
+#define AES_BLOCK_SIZE 16
+#define AES_PRIV_SIZE (4 * 44)
+#define _AES_IV_LEN_ 8
+
+typedef enum {
+	ENCRYP_PROTOCOL_OPENSYS,   //open system
+	ENCRYP_PROTOCOL_WEP,       //WEP
+	ENCRYP_PROTOCOL_WPA,       //WPA
+	ENCRYP_PROTOCOL_WPA2,      //WPA2
+	ENCRYP_PROTOCOL_WAPI,      //WAPI: Not support in this version
+	ENCRYP_PROTOCOL_MAX
+}ENCRYP_PROTOCOL_E;
+
+
+#ifndef Ndis802_11AuthModeWPA2
+#define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1)
+#endif
+
+#ifndef Ndis802_11AuthModeWPA2PSK
+#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2)
+#endif
+
+union pn48	{
+	
+	u64	val;
+	
+#ifdef CONFIG_LITTLE_ENDIAN
+
+struct {
+  u8 TSC0;
+  u8 TSC1;
+  u8 TSC2;
+  u8 TSC3;
+  u8 TSC4;
+  u8 TSC5;
+  u8 TSC6;
+  u8 TSC7;
+} _byte_;
+ 
+#elif defined(CONFIG_BIG_ENDIAN)
+
+struct {
+  u8 TSC7;
+  u8 TSC6;
+  u8 TSC5;
+  u8 TSC4;
+  u8 TSC3;
+  u8 TSC2;
+  u8 TSC1;
+  u8 TSC0;
+} _byte_;
+ 
+#endif
+
+};
+
+union Keytype {
+        u8   skey[16];
+        u32  lkey[4];
+};
+
+
+typedef struct _RT_PMKID_LIST
+{
+	u8						bUsed;
+	u8 						Bssid[6];
+	u8						PMKID[16];
+	u8						SsidBuf[33];
+	u8*						ssid_octet;
+	u16 						ssid_length;
+} RT_PMKID_LIST, *PRT_PMKID_LIST;
+
+
+struct security_priv
+{
+	u32	  dot11AuthAlgrthm;		// 802.11 auth, could be open, shared, 8021x and authswitch 
+	u32	  dot11PrivacyAlgrthm;	// This specify the privacy for shared auth. algorithm.
+
+	/* WEP */
+	u32	  dot11PrivacyKeyIndex;	// this is only valid for legendary wep, 0~3 for key id. (tx key index)
+	union Keytype dot11DefKey[4];			// this is only valid for def. key	
+	u32 	dot11DefKeylen[4];
+
+	u32 dot118021XGrpPrivacy;	// This specify the privacy algthm. used for Grp key 
+	u32	dot118021XGrpKeyid;		// key id used for Grp Key ( tx key index)
+	union Keytype	dot118021XGrpKey[4];	// 802.1x Group Key, for inx0 and inx1	
+	union Keytype	dot118021XGrptxmickey[4];
+	union Keytype	dot118021XGrprxmickey[4];
+	union pn48		dot11Grptxpn;			// PN48 used for Grp Key xmit.
+	union pn48		dot11Grprxpn;			// PN48 used for Grp Key recv.
+
+#ifdef CONFIG_AP_MODE
+	//extend security capabilities for AP_MODE 
+	unsigned int dot8021xalg;//0:disable, 1:psk, 2:802.1x
+	unsigned int wpa_psk;//0:disable, bit(0): WPA, bit(1):WPA2
+	unsigned int wpa_group_cipher;
+	unsigned int wpa2_group_cipher;
+	unsigned int wpa_pairwise_cipher;
+	unsigned int wpa2_pairwise_cipher;	
+#endif
+
+#ifdef CONFIG_WPS
+	u8 wps_ie[MAX_WPS_IE_LEN];//added in assoc req
+	int wps_ie_len;
+#endif	
+	
+	u8	binstallGrpkey;
+	u8	busetkipkey;
+	//_timer tkip_timer;
+	u8	bcheck_grpkey;
+	u8	bgrpkey_handshake;
+	
+	//u8	packet_cnt;//unused, removed
+	
+	s32	sw_encrypt;//from registry_priv
+	s32	sw_decrypt;//from registry_priv
+	
+	s32 	hw_decrypted;//if the rx packets is hw_decrypted==_FALSE, it means the hw has not been ready.
+
+
+	//keeps the auth_type & enc_status from upper layer ioctl(wpa_supplicant or wzc)
+	u32 ndisauthtype;	// NDIS_802_11_AUTHENTICATION_MODE
+	u32 ndisencryptstatus;	// NDIS_802_11_ENCRYPTION_STATUS
+
+	//WLAN_BSSID_EX sec_bss;  //for joinbss (h2c buffer) usage //YJ,del,140410
+
+	NDIS_802_11_WEP ndiswep;
+#ifdef PLATFORM_WINDOWS
+	u8 KeyMaterial[16];// variable length depending on above field.
+#endif
+
+//TODO
+#if 0	//Remove unused wpa2 data - Alex Fang
+	u8 assoc_info[600];
+	u8 szofcapability[256]; //for wpa2 usage
+	u8 oidassociation[512]; //for wpa/wpa2 usage
+	u8 authenticator_ie[256];  //store ap security information element
+#endif
+	u8 supplicant_ie[256];  //store sta security information element
+
+
+	//for tkip countermeasure
+	u32 last_mic_err_time;	
+	u8	btkip_countermeasure;
+	u8	btkip_wait_report;
+	u32 btkip_countermeasure_time;
+#ifdef CONFIG_WPA2_PREAUTH
+	//---------------------------------------------------------------------------
+	// For WPA2 Pre-Authentication.
+	//---------------------------------------------------------------------------
+	//u8				RegEnablePreAuth;				// Default value: Pre-Authentication enabled or not, from registry "EnablePreAuth". Added by Annie, 2005-11-01.
+	//u8				EnablePreAuthentication;		// Current Value: Pre-Authentication enabled or not.
+	RT_PMKID_LIST		PMKIDList[NUM_PMKID_CACHE];		// Renamed from PreAuthKey[NUM_PRE_AUTH_KEY]. Annie, 2006-10-13.
+	u8					PMKIDIndex;
+	//u32				PMKIDCount;						// Added by Annie, 2006-10-13.
+	//u8				szCapability[256];				// For WPA2-PSK using zero-config, by Annie, 2005-09-20.
+#endif
+
+#ifdef CONFIG_INCLUDE_WPA_PSK
+	WPA_GLOBAL_INFO		wpa_global_info;
+#if defined(CONFIG_AP_MODE) && defined(CONFIG_MULTIPLE_WPA_STA)
+//	WPA_STA_INFO		wpa_sta_info[AP_STA_NUM];
+	u8					*palloc_wpastainfo_buf;
+	u32					alloc_wpastainfo_size;
+	WPA_STA_INFO		*wpa_sta_info[NUM_STA-2];
+#else
+	WPA_STA_INFO		wpa_sta_info;
+#endif
+	u8 wpa_passphrase[IW_PASSPHRASE_MAX_SIZE + 1];
+#endif
+#ifdef CONFIG_WPS
+	u8	wps_phase;
+#endif
+};
+
+struct sha256_state {
+	u64 length;
+	u32 state[8], curlen;
+	u8 buf[64];
+};
+
+
+#define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst)\
+do{\
+	switch(psecuritypriv->dot11AuthAlgrthm)\
+	{\
+		case dot11AuthAlgrthm_Open:\
+		case dot11AuthAlgrthm_Shared:\
+		case dot11AuthAlgrthm_Auto:\
+			encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\
+			break;\
+		case dot11AuthAlgrthm_8021X:\
+			if(bmcst)\
+				encry_algo = (u8)psecuritypriv->dot118021XGrpPrivacy;\
+			else\
+				encry_algo =(u8) psta->dot118021XPrivacy;\
+			break;\
+	     case dot11AuthAlgrthm_WAPI:\
+		     encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\
+		     break;\
+	}\
+}while(0)
+
+
+#define SET_ICE_IV_LEN( iv_len, icv_len, encrypt)\
+do{\
+	switch(encrypt)\
+	{\
+		case _WEP40_:\
+		case _WEP104_:\
+			iv_len = 4;\
+			icv_len = 4;\
+			break;\
+		case _TKIP_:\
+			iv_len = 8;\
+			icv_len = 4;\
+			break;\
+		case _AES_:\
+			iv_len = 8;\
+			icv_len = 8;\
+			break;\
+		case _SMS4_:\
+			iv_len = 18;\
+			icv_len = 16;\
+			break;\
+		default:\
+			iv_len = 0;\
+			icv_len = 0;\
+			break;\
+	}\
+}while(0)
+
+
+#define GET_TKIP_PN(iv,dot11txpn)\
+do{\
+	dot11txpn._byte_.TSC0=iv[2];\
+	dot11txpn._byte_.TSC1=iv[0];\
+	dot11txpn._byte_.TSC2=iv[4];\
+	dot11txpn._byte_.TSC3=iv[5];\
+	dot11txpn._byte_.TSC4=iv[6];\
+	dot11txpn._byte_.TSC5=iv[7];\
+}while(0)
+
+
+#define ROL32( A, n )	( ((A) << (n)) | ( ((A)>>(32-(n)))  & ( (1UL << (n)) - 1 ) ) )
+#define ROR32( A, n ) 	ROL32( (A), 32-(n) )
+
+extern const u32 Te0[256];
+extern const u32 Te1[256];
+extern const u32 Te2[256];
+extern const u32 Te3[256];
+extern const u32 Te4[256];
+extern const u32 Td0[256];
+extern const u32 Td1[256];
+extern const u32 Td2[256];
+extern const u32 Td3[256];
+extern const u32 Td4[256];
+extern const u32 rcon[10];
+extern const u8 Td4s[256];
+extern const u8 rcons[10];
+
+#define RCON(i) (rcons[(i)] << 24)
+
+static inline u32 rotr(u32 val, int bits)
+{
+	return (val >> bits) | (val << (32 - bits));
+}
+
+#define TE0(i) Te0[((i) >> 24) & 0xff]
+#define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8)
+#define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16)
+#define TE3(i) rotr(Te0[(i) & 0xff], 24)
+#define TE41(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000)
+#define TE42(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000)
+#define TE43(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00)
+#define TE44(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff)
+#define TE421(i) ((Te0[((i) >> 16) & 0xff] << 8) & 0xff000000)
+#define TE432(i) (Te0[((i) >> 8) & 0xff] & 0x00ff0000)
+#define TE443(i) (Te0[(i) & 0xff] & 0x0000ff00)
+#define TE414(i) ((Te0[((i) >> 24) & 0xff] >> 8) & 0x000000ff)
+#define TE4(i) ((Te0[(i)] >> 8) & 0x000000ff)
+
+#define TD0(i) Td0[((i) >> 24) & 0xff]
+#define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8)
+#define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16)
+#define TD3(i) rotr(Td0[(i) & 0xff], 24)
+#define TD41(i) (Td4s[((i) >> 24) & 0xff] << 24)
+#define TD42(i) (Td4s[((i) >> 16) & 0xff] << 16)
+#define TD43(i) (Td4s[((i) >> 8) & 0xff] << 8)
+#define TD44(i) (Td4s[(i) & 0xff])
+#define TD0_(i) Td0[(i) & 0xff]
+#define TD1_(i) rotr(Td0[(i) & 0xff], 8)
+#define TD2_(i) rotr(Td0[(i) & 0xff], 16)
+#define TD3_(i) rotr(Td0[(i) & 0xff], 24)
+
+#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \
+			((u32)(pt)[2] <<  8) ^ ((u32)(pt)[3]))
+
+#define PUTU32(ct, st) { \
+(ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \
+(ct)[2] = (u8)((st) >>  8); (ct)[3] = (u8)(st); }
+
+#define WPA_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \
+			 (((u32) (a)[2]) << 8) | ((u32) (a)[3]))
+
+#define WPA_PUT_LE16(a, val)			\
+	do {					\
+		(a)[1] = ((u16) (val)) >> 8;	\
+		(a)[0] = ((u16) (val)) & 0xff;	\
+	} while (0)
+
+#define WPA_PUT_BE32(a, val)					\
+	do {							\
+		(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
+		(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
+		(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
+		(a)[3] = (u8) (((u32) (val)) & 0xff);		\
+	} while (0)
+
+#define WPA_PUT_BE64(a, val)				\
+	do {						\
+		(a)[0] = (u8) (((u64) (val)) >> 56);	\
+		(a)[1] = (u8) (((u64) (val)) >> 48);	\
+		(a)[2] = (u8) (((u64) (val)) >> 40);	\
+		(a)[3] = (u8) (((u64) (val)) >> 32);	\
+		(a)[4] = (u8) (((u64) (val)) >> 24);	\
+		(a)[5] = (u8) (((u64) (val)) >> 16);	\
+		(a)[6] = (u8) (((u64) (val)) >> 8);	\
+		(a)[7] = (u8) (((u64) (val)) & 0xff);	\
+	} while (0)
+	
+/* ===== start - public domain SHA256 implementation ===== */
+
+/* This is based on SHA256 implementation in LibTomCrypt that was released into
+ * public domain by Tom St Denis. */
+
+/* the K array */
+static const unsigned long K[64] = {
+	0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL,
+	0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL,
+	0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL,
+	0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL,
+	0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL,
+	0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL,
+	0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL,
+	0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL,
+	0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL,
+	0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL,
+	0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL,
+	0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL,
+	0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL
+};
+
+
+/* Various logical functions */
+#define RORc(x, y) \
+( ((((unsigned long) (x) & 0xFFFFFFFFUL) >> (unsigned long) ((y) & 31)) | \
+   ((unsigned long) (x) << (unsigned long) (32 - ((y) & 31)))) & 0xFFFFFFFFUL)
+#define Ch(x,y,z)       (z ^ (x & (y ^ z)))
+#define Maj(x,y,z)      (((x | y) & z) | (x & y)) 
+#define S(x, n)         RORc((x), (n))
+#define R(x, n)         (((x)&0xFFFFFFFFUL)>>(n))
+#define Sigma0(x)       (S(x, 2) ^ S(x, 13) ^ S(x, 22))
+#define Sigma1(x)       (S(x, 6) ^ S(x, 11) ^ S(x, 25))
+#define Gamma0(x)       (S(x, 7) ^ S(x, 18) ^ R(x, 3))
+#define Gamma1(x)       (S(x, 17) ^ S(x, 19) ^ R(x, 10))
+#ifndef MIN
+#define MIN(x, y) (((x) < (y)) ? (x) : (y))
+#endif
+
+u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe);
+u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe);
+void rtw_wep_encrypt(_adapter *padapter, u8  *pxmitframe);
+
+u32 rtw_aes_decrypt(_adapter *padapter, u8  *precvframe);
+u32 rtw_tkip_decrypt(_adapter *padapter, u8  *precvframe);
+void rtw_wep_decrypt(_adapter *padapter, u8  *precvframe);
+
+#ifdef CONFIG_TDLS
+void wpa_tdls_generate_tpk(_adapter *padapter, struct sta_info *psta);
+int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq, 
+						u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie,
+						u8 *mic);
+int tdls_verify_mic(u8 *kck, u8 trans_seq, 
+						u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie);
+#endif //CONFIG_TDLS
+
+#ifdef PLATFORM_WINDOWS
+void rtw_use_tkipkey_handler (
+	IN	PVOID					SystemSpecific1,
+	IN	PVOID					FunctionContext,
+	IN	PVOID					SystemSpecific2,
+	IN	PVOID					SystemSpecific3
+	);
+#endif
+#ifdef PLATFORM_LINUX
+void rtw_use_tkipkey_handler(void* FunctionContext);
+#endif
+
+#ifdef PLATFORM_FREEBSD
+void rtw_use_tkipkey_handler(void* FunctionContext);
+#endif //PLATFORM_FREEBSD
+
+u32	rtw_init_sec_priv(_adapter *padapter);
+void	rtw_free_sec_priv(struct security_priv *psecpriv);
+
+#endif	//__RTL871X_SECURITY_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_xmit.h

@@ -0,0 +1,839 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef _RTW_XMIT_H_
+#define _RTW_XMIT_H_
+
+/*---------------------------------------
+  Define MAX_XMITBUF_SZ
+---------------------------------------*/
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_LX_HCI)
+
+#ifdef CONFIG_TX_AGGREGATION	//effect only for SDIO and GSPI Interface
+#define MAX_XMITBUF_SZ	(20480)	// 20k
+#else
+#if defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
+
+	#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+		#define HAL_INTERFACE_OVERHEAD_XMIT_BUF 12	//HAL_INTERFACE_CMD (4) + HAL_INTERFACE_STATUS (8)
+	#elif defined(CONFIG_LX_HCI)
+		#define HAL_INTERFACE_OVERHEAD_XMIT_BUF 0
+	#endif
+
+// Consideration for MAX_XMITBUF_SZ size
+// 	Check more detail information in MAX_SKB_BUF_SIZE	
+//	Tx: [INTF_CMD][TX_DESC][WLAN_HDR][QoS][IV][SNAP][Data][MIC][ICV][INTF_STATUS]
+//	HAL_INTERFACE_OVERHEAD: HAL_INTERFACE_CMD is 4/0 for SPI/PCIE, HAL_INTERFACE_STATUS is 8/0 for SPI/PCIE
+//	WLAN_MAX_ETHFRM_LEN : May not be required because WLAN_HEADER +SNAP can totally 
+//			cover ethernet header.Keep in only for safety.
+
+#ifndef CONFIG_DONT_CARE_TP
+#define MAX_XMITBUF_SZ		(HAL_INTERFACE_OVERHEAD_XMIT_BUF+\
+							TXDESC_SIZE+\
+							WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN +\
+							SKB_RESERVED_FOR_SAFETY)
+#else
+#define MAX_XMITBUF_SZ		(HAL_INTERFACE_OVERHEAD_XMIT_BUF+\
+							TXDESC_SIZE+\
+							WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_TX_ETHFRM_LEN +\
+							SKB_RESERVED_FOR_SAFETY)
+#endif
+
+
+#else // Other OS
+#define MAX_XMITBUF_SZ (12288)  //12k 1536*8
+#endif	//#ifdef PLATFORM_ECOS || defined(PLATFORM_FREERTOS)
+#endif	//#ifdef CONFIG_TX_AGGREGATION
+
+#elif defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
+	#errof "Undefined bus interface for MAX_XMITBUF_SZ"
+#endif	//interface define. SDIO/GSPI/LXbus/PCI/USB
+
+
+
+/*--------------------------------------------------------------*/
+/*  Define MAX_XMITBUF_SZ										*/
+/*--------------------------------------------------------------*/
+#if (defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI)
+
+#if defined(PLATFORM_ECOS)
+#define NR_XMITBUFF	(8)	
+#elif defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
+#ifndef CONFIG_HIGH_TP
+#define NR_XMITBUFF	(2)	//Decrease recv frame (8->2) due to memory limitation - YangJue
+#else 
+#define NR_XMITBUFF (128)
+#endif
+#else
+#define NR_XMITBUFF	(128)
+#endif	//#ifdef PLATFORM_ECOS
+
+#elif defined(CONFIG_LX_HCI)
+#define NR_XMITBUFF	(8)
+
+#elif defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
+	#errof "Undefined bus interface for MAX_XMITBUF_SZ"
+#endif //interface define
+
+
+/*--------------------------------------------------------------*/
+/*  Define XMITBUF_ALIGN_SZ										*/
+/*--------------------------------------------------------------*/
+#if defined(PLATFORM_OS_CE) || defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined(PLATFORM_CMSIS_RTOS)
+#define XMITBUF_ALIGN_SZ 4
+#else
+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI)
+#define XMITBUF_ALIGN_SZ 4
+#else
+#define XMITBUF_ALIGN_SZ 512
+#endif
+#endif
+
+#define MAX_CMDBUF_SZ	(5120)	//(4096)
+/*--------------------------------------------------------------*/
+/*  Define xmit extension buff, size/numbers							*/
+/*--------------------------------------------------------------*/
+#define MAX_XMIT_EXTBUF_SZ	(1536)
+
+#if defined(PLATFORM_ECOS)
+#define NR_XMIT_EXTBUFF		(16)	//Decrease ext xmit buffer due to memory limitation - Alex Fang
+#elif defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
+#define NR_XMIT_EXTBUFF		(8)	//Decrease ext xmit buffer due to memory limitation - Alex Fang
+#else
+#define NR_XMIT_EXTBUFF		(32)
+#endif	//#ifdef	PLATFORM_ECOS
+
+#define MAX_NUMBLKS		(1)
+
+#define XMIT_VO_QUEUE (0)
+#define XMIT_VI_QUEUE (1)
+#define XMIT_BE_QUEUE (2)
+#define XMIT_BK_QUEUE (3)
+
+#define VO_QUEUE_INX		0
+#define VI_QUEUE_INX		1
+#define BE_QUEUE_INX		2
+#define BK_QUEUE_INX		3
+#define BCN_QUEUE_INX		4
+#define MGT_QUEUE_INX		5
+#define HIGH_QUEUE_INX		6
+#define TXCMD_QUEUE_INX		7
+#ifdef CONFIG_WLAN_HAL_TEST
+#define HIGH1_QUEUE_INX		8
+#define HIGH2_QUEUE_INX		9
+#define HIGH3_QUEUE_INX		10
+#define HIGH4_QUEUE_INX		11
+#define HIGH5_QUEUE_INX		12
+#define HIGH6_QUEUE_INX		13
+#define HIGH7_QUEUE_INX		14
+#define HW_QUEUE_ENTRY		15
+#else
+#define HW_QUEUE_ENTRY		8
+#endif
+
+#define WEP_IV(pattrib_iv, dot11txpn, keyidx)\
+do{\
+	pattrib_iv[0] = dot11txpn._byte_.TSC0;\
+	pattrib_iv[1] = dot11txpn._byte_.TSC1;\
+	pattrib_iv[2] = dot11txpn._byte_.TSC2;\
+	pattrib_iv[3] = ((keyidx & 0x3)<<6);\
+	dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0: (dot11txpn.val+1);\
+}while(0)
+
+
+#define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\
+do{\
+	pattrib_iv[0] = dot11txpn._byte_.TSC1;\
+	pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\
+	pattrib_iv[2] = dot11txpn._byte_.TSC0;\
+	pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\
+	pattrib_iv[4] = dot11txpn._byte_.TSC2;\
+	pattrib_iv[5] = dot11txpn._byte_.TSC3;\
+	pattrib_iv[6] = dot11txpn._byte_.TSC4;\
+	pattrib_iv[7] = dot11txpn._byte_.TSC5;\
+	dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0: (dot11txpn.val+1);\
+}while(0)
+
+#define AES_IV(pattrib_iv, dot11txpn, keyidx)\
+do{\
+	pattrib_iv[0] = dot11txpn._byte_.TSC0;\
+	pattrib_iv[1] = dot11txpn._byte_.TSC1;\
+	pattrib_iv[2] = 0;\
+	pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\
+	pattrib_iv[4] = dot11txpn._byte_.TSC2;\
+	pattrib_iv[5] = dot11txpn._byte_.TSC3;\
+	pattrib_iv[6] = dot11txpn._byte_.TSC4;\
+	pattrib_iv[7] = dot11txpn._byte_.TSC5;\
+	dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0: (dot11txpn.val+1);\
+}while(0)
+
+
+#define HWXMIT_ENTRY	4
+
+#if  defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)|| defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B) ||defined(CONFIG_RTL8188F)
+#define TXDESC_SIZE 40
+#else
+#define TXDESC_SIZE 32
+#endif
+
+#ifdef CONFIG_TX_EARLY_MODE
+#define EARLY_MODE_INFO_SIZE	8
+#endif
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+#define TXDESC_OFFSET TXDESC_SIZE
+
+#endif
+
+#ifdef CONFIG_USB_HCI
+#define PACKET_OFFSET_SZ (8)
+#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
+#endif
+
+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI)
+#if  defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B)// buffer descriptor architecture
+#define TXDESC_OFFSET TXDESC_SIZE
+#else
+#define TXDESC_OFFSET 0
+#endif
+#define TX_DESC_NEXT_DESC_OFFSET	40
+#endif
+
+#define TX_FRAGMENTATION_THRESHOLD 			2346
+
+// Suppose (TX_DESC_MODE=1) ==> Segment number for each tx_buf_desc is 4. 2X4 = 8 (double words).
+struct tx_buf_desc {	
+	unsigned int txdw0;	
+	unsigned int txdw1;	
+	unsigned int txdw2;	
+	unsigned int txdw3;	
+	unsigned int txdw4;	
+	unsigned int txdw5;	
+	unsigned int txdw6;	
+	unsigned int txdw7;
+};
+
+struct tx_desc{
+
+	//DWORD 0
+	unsigned int txdw0;
+
+	unsigned int txdw1;
+
+	unsigned int txdw2;
+
+	unsigned int txdw3;
+
+	unsigned int txdw4;
+
+	unsigned int txdw5;
+
+	unsigned int txdw6;
+
+	unsigned int txdw7;
+#ifdef CONFIG_PCI_HCI
+	unsigned int txdw8;
+
+	unsigned int txdw9;
+
+	unsigned int txdw10;
+
+	unsigned int txdw11;
+
+	// 2008/05/15 MH Because PCIE HW memory R/W 4K limit. And now,  our descriptor
+	// size is 40 bytes. If you use more than 102 descriptor( 103*40>4096), HW will execute
+	// memoryR/W CRC error. And then all DMA fetch will fail. We must decrease descriptor
+	// number or enlarge descriptor size as 64 bytes.
+	unsigned int txdw12;
+
+	unsigned int txdw13;
+
+	unsigned int txdw14;
+
+	unsigned int txdw15;
+#endif
+#if defined(CONFIG_LX_HCI)||defined(CONFIG_RTL8188F) 
+    unsigned int txdw8;
+
+    unsigned int txdw9;
+#endif
+};
+
+
+union txdesc {
+	struct tx_desc txdesc;
+	unsigned int value[TXDESC_SIZE>>2];
+};
+
+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI)
+#ifdef CONFIG_WLAN_HAL_TEST    
+#define PCI_MAX_TX_QUEUE_COUNT	 HW_QUEUE_ENTRY
+#else
+#define PCI_MAX_TX_QUEUE_COUNT	8
+#endif
+
+struct rtw_tx_ring {
+
+#if ((RTL8195A_SUPPORT ==1) ||(RTL8711B_SUPPORT == 1))
+	struct tx_buf_desc	*desc;
+#else
+	struct tx_desc	*desc;
+#endif
+	dma_addr_t		dma;
+	unsigned int		idx;
+	unsigned int		entries;
+	_queue			queue;
+	u32				qlen;
+};
+#endif
+
+struct	hw_xmit	{
+	//_lock xmit_lock;
+	//_list	pending;
+	_queue *sta_queue;
+	//struct hw_txqueue *phwtxqueue;
+	//sint	txcmdcnt;
+	int	accnt;
+};
+
+#if 0
+struct pkt_attrib
+{
+	u8	type;
+	u8	subtype;
+	u8	bswenc;
+	u8	dhcp_pkt;
+	u16	ether_type;
+	int	pktlen;		//the original 802.3 pkt raw_data len (not include ether_hdr data)
+	int	pkt_hdrlen;	//the original 802.3 pkt header len
+	int	hdrlen;		//the WLAN Header Len
+	int	nr_frags;
+	int	last_txcmdsz;
+	int	encrypt;	//when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith
+	u8	iv[8];
+	int	iv_len;
+	u8	icv[8];
+	int	icv_len;
+	int	priority;
+	int	ack_policy;
+	int	mac_id;
+	int	vcs_mode;	//virtual carrier sense method
+
+	u8 	dst[ETH_ALEN];
+	u8	src[ETH_ALEN];
+	u8	ta[ETH_ALEN];
+	u8 	ra[ETH_ALEN];
+
+	u8	key_idx;
+
+	u8	qos_en;
+	u8	ht_en;
+	u8	raid;//rate adpative id
+	u8	bwmode;
+	u8	ch_offset;//PRIME_CHNL_OFFSET
+	u8	sgi;//short GI
+	u8	ampdu_en;//tx ampdu enable
+	u8	mdata;//more data bit
+	u8	eosp;
+
+	u8	pctrl;//per packet txdesc control enable
+	u8	triggered;//for ap mode handling Power Saving sta
+
+	u32	qsel;
+	u16	seqnum;
+
+	struct sta_info * psta;
+#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
+	u8	hw_tcp_csum;
+#endif
+};
+#else
+//reduce size
+struct pkt_attrib
+{
+	u8	type;
+	u8	subtype;
+	u8	bswenc;
+	u8	dhcp_pkt;
+	u16	ether_type;
+	u16	seqnum;
+	u16	pkt_hdrlen;	//the original 802.3 pkt header len
+	u16	hdrlen;		//the WLAN Header Len
+	u32	pktlen;		//the original 802.3 pkt raw_data len (not include ether_hdr data)
+	u32	last_txcmdsz;
+	u8	encrypt;	//when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith
+	u8	iv_len;
+	u8	icv_len;
+	u8	iv[18];
+	u8	icv[16];
+	u8	priority;
+	u8	ack_policy;
+	u8	mac_id;
+	u8	vcs_mode;	//virtual carrier sense method
+	u8 	dst[ETH_ALEN];
+	u8	src[ETH_ALEN];
+	u8	ta[ETH_ALEN];
+	u8 	ra[ETH_ALEN];
+	u8	key_idx;
+	u8	qos_en;
+	u8	ht_en;
+	u8	raid;//rate adpative id
+	u8	bwmode;
+	u8	ch_offset;//PRIME_CHNL_OFFSET
+	u8	sgi;//short GI
+	u8	ampdu_en;//tx ampdu enable
+	u8	mdata;//more data bit
+	u8	pctrl;//per packet txdesc control enable
+	u8	triggered;//for ap mode handling Power Saving sta
+	u8	qsel;
+	u8	eosp;
+	u8	rate;
+	u8	intel_proxim;
+	u8 	retry_ctrl;
+	struct sta_info * psta;
+#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
+	u8	hw_tcp_csum;
+#endif
+};
+#endif
+
+#ifdef PLATFORM_FREEBSD
+#define ETH_ALEN	6		/* Octets in one ethernet addr	 */
+#define ETH_HLEN	14		/* Total octets in header.	 */
+#define ETH_P_IP	0x0800		/* Internet Protocol packet	*/
+
+/*struct rtw_ieee80211_hdr {
+	uint16_t frame_control;
+	uint16_t duration_id;
+	u8 addr1[6];
+	u8 addr2[6];
+	u8 addr3[6];
+	uint16_t seq_ctrl;
+	u8 addr4[6];
+} ;*/
+#endif //PLATFORM_FREEBSD
+
+#define WLANHDR_OFFSET	64
+
+#define NULL_FRAMETAG		(0x0)
+#define DATA_FRAMETAG		0x01
+#define L2_FRAMETAG		0x02
+#define MGNT_FRAMETAG		0x03
+#define AMSDU_FRAMETAG		0x04
+
+#define EII_FRAMETAG		0x05
+#define IEEE8023_FRAMETAG  	0x06
+
+#define MP_FRAMETAG		0x07
+
+#define TXAGG_FRAMETAG 		0x08
+
+enum {
+	XMITBUF_DATA = 0,
+	XMITBUF_MGNT = 1,
+	XMITBUF_CMD = 2,
+};
+
+struct  submit_ctx{
+	u32 submit_time; /* */
+	u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */
+	int status; /* status for operation */
+#ifdef PLATFORM_LINUX
+	struct completion done;
+#endif
+};
+
+enum {
+	RTW_SCTX_DONE_SUCCESS = 0,
+	RTW_SCTX_DONE_UNKNOWN,
+	RTW_SCTX_DONE_BUF_ALLOC,
+	RTW_SCTX_DONE_BUF_FREE,
+	RTW_SCTX_DONE_WRITE_PORT_ERR,
+	RTW_SCTX_DONE_TX_DESC_NA,
+	RTW_SCTX_DONE_TX_DENY,
+};
+
+
+void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms);
+int rtw_sctx_wait(struct submit_ctx *sctx);
+void rtw_sctx_done_err(struct submit_ctx **sctx, int status);
+void rtw_sctx_done(struct submit_ctx **sctx);
+
+typedef struct _XIMT_BUF_ {    
+	u32     AllocatBufAddr;    
+	u32     BufAddr;    
+	u32     BufLen;
+}XIMT_BUF, *PXIMT_BUF;
+
+struct xmit_buf
+{
+	_list	list;
+
+	_adapter *padapter;
+
+#if USE_SKB_AS_XMITBUF
+	_pkt *pkt;
+#else
+	u8 *pallocated_buf;
+#endif
+	u8 *pbuf;
+
+	void *priv_data;
+
+	u16 buf_tag; // 0: Normal xmitbuf, 1: extension xmitbuf, 2:cmd xmitbuf
+	u16 flags;
+	u32 alloc_sz;
+
+	u32  len;
+
+	struct submit_ctx *sctx;
+
+#ifdef CONFIG_USB_HCI
+
+	//u32 sz[8];
+	u32	ff_hwaddr;
+
+#if defined(PLATFORM_OS_XP)||defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
+	PURB	pxmit_urb[8];
+	dma_addr_t dma_transfer_addr;	/* (in) dma addr for transfer_buffer */
+#endif
+
+#ifdef PLATFORM_OS_XP
+	PIRP		pxmit_irp[8];
+#endif
+
+#ifdef PLATFORM_OS_CE
+	USB_TRANSFER	usb_transfer_write_port;
+#endif
+
+	u8 bpending[8];
+
+	sint last[8];
+
+#endif
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	u8 *phead;
+	u8 *pdata;
+	u8 *ptail;
+	u8 *pend;
+	u32 ff_hwaddr;
+	u8	pg_num;	
+	u8	agg_num;
+#ifdef PLATFORM_OS_XP
+	PMDL pxmitbuf_mdl;
+	PIRP  pxmitbuf_irp;
+	PSDBUS_REQUEST_PACKET pxmitbuf_sdrp;
+#endif
+#endif
+
+#if defined(DBG_XMIT_BUF )|| defined(DBG_XMIT_BUF_EXT)
+	u8 no;
+#endif
+
+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI)
+#if ((RTL8195A_SUPPORT ==1) ||(RTL8711B_SUPPORT == 1))
+	XIMT_BUF BufInfo[4];    
+	u32 BlockNum;
+#endif
+#endif
+};
+
+
+struct xmit_frame
+{
+	_list	list;
+
+	struct pkt_attrib attrib;
+
+	_pkt *pkt;
+
+	int	frame_tag;
+
+	_adapter *padapter;
+
+	u8	*buf_addr;
+
+	struct xmit_buf *pxmitbuf;
+
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+	u8	pg_num;
+	u8	agg_num;
+#endif
+
+#ifdef CONFIG_USB_HCI
+#ifdef CONFIG_USB_TX_AGGREGATION
+	u8	agg_num;
+#endif
+	s8	pkt_offset;
+#ifdef CONFIG_RTL8192D
+	u8	EMPktNum;
+	u16	EMPktLen[5];//The max value by HW
+#endif
+#endif
+
+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI)
+#if ((RTL8195A_SUPPORT ==1) ||(RTL8711B_SUPPORT == 1))
+	u32 TxDexAddr;    
+	u32 HdrLen;    
+	u32 PayLoadAddr;    
+	u32 PayLoadLen;    
+	u32 TotalLen;    
+	u32 BlockNum;    
+	XIMT_BUF BufInfo[4];    
+	BOOLEAN NoCoalesce;
+#endif
+#endif
+};
+
+struct tx_servq {
+	_list	tx_pending;
+	_queue	sta_pending;
+	int qcnt;
+};
+
+struct sta_xmit_priv
+{
+	_lock	lock;
+	sint	option;
+	sint	apsd_setting;	//When bit mask is on, the associated edca queue supports APSD.
+
+
+	//struct tx_servq blk_q[MAX_NUMBLKS];
+	struct tx_servq	be_q;			//priority == 0,3
+	struct tx_servq	bk_q;			//priority == 1,2
+	struct tx_servq	vi_q;			//priority == 4,5
+	struct tx_servq	vo_q;			//priority == 6,7
+	_list 	legacy_dz;
+	_list  apsd;
+
+	u16 txseq_tid[16];
+
+	//uint	sta_tx_bytes;
+	//u64	sta_tx_pkts;
+	//uint	sta_tx_fail;
+
+
+};
+
+
+struct	hw_txqueue	{
+	volatile sint	head;
+	volatile sint	tail;
+	volatile sint 	free_sz;	//in units of 64 bytes
+	volatile sint      free_cmdsz;
+	volatile sint	 txsz[8];
+	uint	ff_hwaddr;
+	uint	cmd_hwaddr;
+	sint	ac_tag;
+};
+
+struct agg_pkt_info{
+	u16 offset;
+	u16 pkt_len;
+};
+
+
+struct	xmit_priv	{
+
+	_lock	lock;
+
+	//_queue	blk_strms[MAX_NUMBLKS];
+	_queue	be_pending;
+	_queue	bk_pending;
+	_queue	vi_pending;
+	_queue	vo_pending;
+	_queue	bm_pending;
+
+	//_queue	legacy_dz_queue;
+	//_queue	apsd_queue;
+
+	u8 *pallocated_frame_buf;
+	u8 *pxmit_frame_buf;
+	uint free_xmitframe_cnt;
+
+	//uint mapping_addr;
+	//uint pkt_sz;
+
+	_queue	free_xmit_queue;
+
+	//struct	hw_txqueue	be_txqueue;
+	//struct	hw_txqueue	bk_txqueue;
+	//struct	hw_txqueue	vi_txqueue;
+	//struct	hw_txqueue	vo_txqueue;
+	//struct	hw_txqueue	bmc_txqueue;
+
+	_adapter	*adapter;
+
+	u8   	vcs_setting;
+	u8	vcs;
+	u8	vcs_type;
+	//u16  rts_thresh;
+
+	u64	tx_bytes;
+	u64	tx_pkts;
+	u64	tx_drop;
+	u64	last_tx_bytes;
+	u64	last_tx_pkts;
+
+	struct hw_xmit *hwxmits;
+	u8	hwxmit_entry;
+
+#ifdef CONFIG_USB_HCI
+	_sema	tx_retevt;//all tx return event;
+	u8		txirp_cnt;//
+
+#ifdef PLATFORM_OS_CE
+	USB_TRANSFER	usb_transfer_write_port;
+//	USB_TRANSFER	usb_transfer_write_mem;
+#endif
+#ifdef PLATFORM_LINUX
+	struct tasklet_struct xmit_tasklet;
+#endif
+#ifdef PLATFORM_FREEBSD
+	struct task xmit_tasklet;
+#endif
+	//per AC pending irp
+	int beq_cnt;
+	int bkq_cnt;
+	int viq_cnt;
+	int voq_cnt;
+
+#endif
+
+#if defined(CONFIG_PCI_HCI)  || defined(CONFIG_LX_HCI)
+	// Tx
+	struct rtw_tx_ring	tx_ring[PCI_MAX_TX_QUEUE_COUNT];
+	int	txringcount[PCI_MAX_TX_QUEUE_COUNT];
+	u8 	beaconDMAing;		//flag of indicating beacon is transmiting to HW by DMA
+#ifdef PLATFORM_LINUX
+	struct tasklet_struct xmit_tasklet;
+#endif
+#endif
+
+	_queue free_xmitbuf_queue;
+	_queue pending_xmitbuf_queue;
+	u8 *pallocated_xmitbuf;
+	u8 *pxmitbuf;
+	uint free_xmitbuf_cnt;
+#if USE_XMIT_EXTBUFF
+	_queue free_xmit_extbuf_queue;
+	u8 *pallocated_xmit_extbuf;
+	u8 *pxmit_extbuf;
+	uint free_xmit_extbuf_cnt;
+#endif
+	u16	nqos_ssn;
+	#ifdef CONFIG_TX_EARLY_MODE
+
+	#define MAX_AGG_PKT_NUM 256 //Max tx ampdu coounts		
+	
+	struct agg_pkt_info agg_pkt[MAX_AGG_PKT_NUM];
+	#endif
+};
+
+#ifdef CONFIG_TRACE_SKB
+extern struct xmit_buf *_rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv, u32 size);
+
+//extern struct xmit_frame *_rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv);
+//extern s32 _rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe);
+//extern void _rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue);
+
+#define rtw_alloc_xmitbuf_ext(pxmitpriv, pxmitbuf, size) \
+	(\
+		pxmitbuf = _rtw_alloc_xmitbuf_ext(pxmitpriv, size),\
+		pxmitbuf ? set_skb_list_flag(pxmitbuf->pkt, SKBLIST_XMITEXTBUF):0,\
+		pxmitbuf\
+	)
+#else
+extern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv, u32 size);
+#endif
+extern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+
+extern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv);
+extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+
+extern struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv);
+extern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe);
+extern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue);
+struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac);
+extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
+extern struct xmit_frame* rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry);
+
+void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz);
+extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len);
+extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib);
+extern s32 rtw_put_snap(u8 *data, u16 h_proto);
+
+extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe);
+extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib);
+#define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib)
+extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe);
+#ifdef CONFIG_TDLS
+s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, u8 action);
+#endif
+s32 _rtw_init_hw_txqueue(struct hw_txqueue* phw_txqueue, u8 ac_tag);
+void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv);
+
+
+s32 rtw_txframes_pending(_adapter *padapter);
+s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib);
+void rtw_txframes_update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitframe);
+void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry);
+
+
+s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter);
+void _rtw_free_xmit_priv (struct xmit_priv *pxmitpriv);
+
+
+void rtw_alloc_hwxmits(_adapter *padapter);
+void rtw_free_hwxmits(_adapter *padapter);
+
+
+s32 rtw_xmit(_adapter *padapter, _pkt **pkt);
+
+#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS)
+sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe);
+void stop_sta_xmit(_adapter *padapter, struct sta_info *psta);
+void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta);
+void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta);
+#endif
+
+u8	qos_acm(u8 acm_mask, u8 priority);
+
+s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe);
+s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe);
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+void	enqueue_pending_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
+struct xmit_buf*	dequeue_pending_xmitbuf(struct xmit_priv *pxmitpriv);
+struct xmit_buf*	dequeue_pending_xmitbuf_under_survey(struct xmit_priv *pxmitpriv);
+sint	check_pending_xmitbuf(struct xmit_priv *pxmitpriv);
+thread_return	rtw_xmit_thread(thread_context context);
+#endif
+
+u32	rtw_get_ff_hwaddr(struct xmit_frame	*pxmitframe);
+
+extern s32 rtw_xmit_mgnt(_adapter * padapter, struct xmit_frame *pmgntframe);
+extern s32 rtw_xmit_data(PADAPTER padapter, struct xmit_frame *pxmitframe);
+extern s32 rtw_xmit_xmitbuf(_adapter * padapter, struct xmit_buf *pxmitbuf);
+extern u32 ffaddr2deviceId(struct dvobj_priv *pdvobj, u32 addr);
+extern unsigned int nr_xmitframe;
+extern unsigned int nr_xmitbuff;
+#endif	//_RTL871X_XMIT_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/sta_info.h

@@ -0,0 +1,400 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __STA_INFO_H_
+#define __STA_INFO_H_
+
+#define IBSS_START_MAC_ID	2
+
+#if 0 //move to wifi.h
+#if defined(PLATFORM_ECOS)
+#define NUM_STA 10	//Decrease STA due to memory limitation - Alex Fang
+#elif defined(PLATFORM_FREERTOS)
+//Decrease STA due to memory limitation - Alex Fang
+#ifdef CONFIG_AP_MODE
+#define NUM_STA (2 + AP_STA_NUM)	//2 + supported clients
+#else
+#define NUM_STA 2	//Client mode sta for AP and broadcast
+#endif
+#else
+#define NUM_STA 32
+#endif
+#endif
+
+#define NUM_ACL 16
+
+//if mode ==0, then the sta is allowed once the addr is hit.
+//if mode ==1, then the sta is rejected once the addr is non-hit.
+struct rtw_wlan_acl_node {
+        _list		        list;
+        u8       addr[ETH_ALEN];
+        u8       valid;
+};
+
+//mode=0, disable
+//mode=1, accept unless in deny list
+//mode=2, deny unless in accept list
+struct wlan_acl_pool {
+	int mode;
+	int num;
+	struct rtw_wlan_acl_node aclnode[NUM_ACL];
+	_queue	acl_node_q;
+};
+
+typedef struct _RSSI_STA{
+	s32	UndecoratedSmoothedPWDB;
+	s32	UndecoratedSmoothedCCK;
+	s32	UndecoratedSmoothedOFDM;
+	u64	PacketMap;
+	u8	ValidBit;
+	u32	OFDM_pkt;
+}RSSI_STA, *PRSSI_STA;
+
+struct	stainfo_stats	{
+
+	//u64	rx_pkts;
+	u64 rx_mgnt_pkts;
+	u64 rx_ctrl_pkts;
+	u64 rx_data_pkts;
+
+	//u64	last_rx_pkts;
+	u64	last_rx_mgnt_pkts;
+	u64	last_rx_ctrl_pkts;
+	u64	last_rx_data_pkts;
+	
+	u64	rx_bytes;
+//	u64	rx_drops;
+
+	u64	tx_pkts;
+	u64	tx_bytes;
+//	u64  tx_drops;
+
+};
+
+#ifdef CONFIG_TDLS
+struct TDLS_PeerKey {
+	u8 kck[16]; /* TPK-KCK */
+	u8 tk[16]; /* TPK-TK; only CCMP will be used */
+} ;
+#endif //CONFIG_TDLS
+
+struct sta_info {
+
+	_lock	lock;
+	_list	list; //free_sta_queue
+	_list	hash_list; //sta_hash
+	//_list asoc_list; //20061114
+	//_list sleep_list;//sleep_q
+	//_list wakeup_list;//wakeup_q
+	_adapter *padapter;
+	
+	struct sta_xmit_priv sta_xmitpriv;
+	struct sta_recv_priv sta_recvpriv;
+	
+	_queue sleep_q;
+	unsigned int sleepq_len;
+	
+	uint state;
+	uint aid;
+	uint mac_id;
+	uint qos_option;
+	u8	hwaddr[ETH_ALEN];
+
+	uint	ieee8021x_blocked;	//0: allowed, 1:blocked 
+	uint	dot118021XPrivacy; //aes, tkip...
+	union Keytype	dot11tkiptxmickey;
+	union Keytype	dot11tkiprxmickey;
+	union Keytype	dot118021x_UncstKey;	
+	union pn48		dot11txpn;			// PN48 used for Unicast xmit.
+	union pn48		dot11rxpn;			// PN48 used for Unicast recv.
+
+
+	u8	bssrateset[16];
+	u32	bssratelen;
+	s32  rssi;
+	s32	signal_quality;
+	
+	u8	cts2self;
+	u8	rtsen;
+
+	u8	raid;
+	u8 	init_rate;
+	u32	ra_mask;
+	u8	wireless_mode;	// NETWORK_TYPE
+	struct stainfo_stats sta_stats;
+
+#ifdef CONFIG_TDLS
+	u32	tdls_sta_state;
+	u8	dialog;
+	u8	SNonce[32];
+	u8	ANonce[32];
+	u32	TDLS_PeerKey_Lifetime;
+	u16	TPK_count;
+	_timer	TPK_timer;
+	struct TDLS_PeerKey	tpk;
+	u16	stat_code;
+	u8	off_ch;
+	u16	ch_switch_time;
+	u16	ch_switch_timeout;
+	u8	option;
+	_timer	option_timer;
+	_timer	base_ch_timer;
+	_timer	off_ch_timer;
+
+	_timer handshake_timer;
+	_timer alive_timer1;
+	_timer alive_timer2;
+	u8 timer_flag;
+	u8 alive_count;
+#endif //CONFIG_TDLS
+
+	//for A-MPDU TX, ADDBA timeout check	
+	_timer addba_retry_timer;
+#ifdef CONFIG_RECV_REORDERING_CTRL
+	//for A-MPDU Rx reordering buffer control 
+	struct recv_reorder_ctrl recvreorder_ctrl[16];
+#endif
+	//for A-MPDU Tx
+	//unsigned char		ampdu_txen_bitmap;
+	u16	BA_starting_seqctrl[16];
+	
+
+#ifdef CONFIG_80211N_HT
+	struct ht_priv	htpriv;	
+#endif
+	
+	//Notes:	
+	//STA_Mode:
+	//curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO	
+	//scan_q: AP CAP/INFO
+
+	//AP_Mode:
+	//curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO
+	//sta_info: (AP & STA) CAP/INFO
+		
+#ifdef CONFIG_AP_MODE
+
+	_list asoc_list;
+	_list auth_list;
+	 
+	unsigned int expire_to;
+#ifdef CONFIG_AP_POLLING_CLIENT_ALIVE
+	unsigned int tx_null0;
+	unsigned int tx_null0_fail;
+	unsigned int tx_null0_retry;
+#endif
+	unsigned int auth_seq;
+	unsigned int authalg;
+	unsigned char chg_txt[128];
+
+	u16 capability;	
+	u32 flags;	
+
+	int dot8021xalg;//0:disable, 1:psk, 2:802.1x
+	int wpa_psk;//0:disable, bit(0): WPA, bit(1):WPA2
+	int wpa_group_cipher;
+	int wpa2_group_cipher;
+	int wpa_pairwise_cipher;
+	int wpa2_pairwise_cipher;	
+
+	u8 bpairwise_key_installed;
+
+#ifdef CONFIG_NATIVEAP_MLME
+	u8 wpa_ie[32];
+
+	u8 nonerp_set;
+	u8 no_short_slot_time_set;
+	u8 no_short_preamble_set;
+	u8 no_ht_gf_set;
+	u8 no_ht_set;
+	u8 ht_20mhz_set;
+#endif	// CONFIG_NATIVEAP_MLME
+
+	unsigned int tx_ra_bitmap;
+	u8 qos_info;
+
+	u8 max_sp_len;
+	u8 uapsd_bk;//BIT(0): Delivery enabled, BIT(1): Trigger enabled
+	u8 uapsd_be;
+	u8 uapsd_vi;
+	u8 uapsd_vo;	
+
+	u8 has_legacy_ac;
+	unsigned int sleepq_ac_len;
+
+#ifdef CONFIG_P2P
+	//p2p priv data
+	u8 is_p2p_device;
+	u8 p2p_status_code;
+
+	//p2p client info
+	u8 dev_addr[ETH_ALEN];
+	//u8 iface_addr[ETH_ALEN];//= hwaddr[ETH_ALEN]
+	u8 dev_cap;
+	u16 config_methods;
+	u8 primary_dev_type[8];
+	u8 num_of_secdev_type;
+	u8 secdev_types_list[32];// 32/8 == 4;
+	u16 dev_name_len;
+	u8 dev_name[32];	
+#endif //CONFIG_P2P
+
+#ifdef CONFIG_TX_MCAST2UNI
+	u8 under_exist_checking;
+#endif	// CONFIG_TX_MCAST2UNI
+	
+#endif	// CONFIG_AP_MODE	
+
+#ifdef CONFIG_IOCTL_CFG80211
+	u8 *passoc_req;
+	u32 assoc_req_len;
+#endif
+
+	//for DM
+	RSSI_STA	 rssi_stat;
+	
+	//
+	// ================ODM Relative Info=======================
+	// Please be care, dont declare too much structure here. It will cost memory * STA support num.
+	//
+	//
+	// 2011/10/20 MH Add for ODM STA info.	
+	//
+	// Driver Write
+	u8		bValid;				// record the sta status link or not?
+	//u8		WirelessMode;		// 
+	u8		IOTPeer;			// Enum value.	HT_IOT_PEER_E
+	u8		rssi_level;			//for Refresh RA mask
+	// ODM Write
+	//1 PHY_STATUS_INFO
+	u8		RSSI_Path[4];		// 
+	u8		RSSI_Ave;
+	u8		RXEVM[4];
+	u8		RXSNR[4];
+
+	// ODM Write
+	//1 TX_INFO (may changed by IC)
+	//TX_INFO_T		pTxInfo;				// Define in IC folder. Move lower layer.
+	//
+	// ================ODM Relative Info=======================
+	//
+};
+
+#define sta_rx_pkts(sta) \
+	(sta->sta_stats.rx_mgnt_pkts \
+	+ sta->sta_stats.rx_ctrl_pkts \
+	+ sta->sta_stats.rx_data_pkts)
+
+#define sta_last_rx_pkts(sta) \
+	(sta->sta_stats.last_rx_mgnt_pkts \
+	+ sta->sta_stats.last_rx_ctrl_pkts \
+	+ sta->sta_stats.last_rx_data_pkts)
+
+#define sta_update_last_rx_pkts(sta) \
+	do { \
+		sta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \
+		sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \
+		sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \
+	} while(0)
+
+#define STA_RX_PKTS_ARG(sta) \
+	sta->sta_stats.rx_mgnt_pkts \
+	, sta->sta_stats.rx_ctrl_pkts \
+	, sta->sta_stats.rx_data_pkts
+
+#define STA_LAST_RX_PKTS_ARG(sta) \
+	sta->sta_stats.last_rx_mgnt_pkts \
+	, sta->sta_stats.last_rx_ctrl_pkts \
+	, sta->sta_stats.last_rx_data_pkts
+
+#define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)"
+	
+struct	sta_priv {
+	
+	u8 *pallocated_stainfo_buf;
+	u32 allocated_stainfo_size;
+	u8 *pstainfo_buf;
+	_queue	free_sta_queue;
+	
+	_lock sta_hash_lock;
+	_list   sta_hash[NUM_STA];
+	int asoc_sta_count;
+	_queue sleep_q;
+	_queue wakeup_q;
+	
+	_adapter *padapter;
+	
+
+#ifdef CONFIG_AP_MODE
+	_list asoc_list;
+	_list auth_list;
+	_lock asoc_list_lock;
+	_lock auth_list_lock;
+
+	unsigned int auth_to;  //sec, time to expire in authenticating.
+	unsigned int assoc_to; //sec, time to expire before associating.
+	unsigned int expire_to; //sec , time to expire after associated.
+	
+	/* pointers to STA info; based on allocated AID or NULL if AID free
+	 * AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1
+	 * and so on
+	 */
+	struct sta_info *sta_aid[NUM_STA];
+
+	u16 sta_dz_bitmap;//only support 15 stations, staion aid bitmap for sleeping sta.
+	u16 tim_bitmap;//only support 15 stations, aid=0~15 mapping bit0~bit15	
+
+	u16 max_num_sta;
+//TODO: AP
+//	struct wlan_acl_pool acl_list;
+#endif		
+	
+};
+
+
+__inline static u32 wifi_mac_hash(u8 *mac)
+{
+        u32 x;
+
+        x = mac[0];
+        x = (x << 2) ^ mac[1];
+        x = (x << 2) ^ mac[2];
+        x = (x << 2) ^ mac[3];
+        x = (x << 2) ^ mac[4];
+        x = (x << 2) ^ mac[5];
+
+        x ^= x >> 8;
+        x  = x & (NUM_STA - 1);
+		
+        return x;
+}
+
+
+extern u32	_rtw_init_sta_priv(_adapter *padapter);
+extern u32	_rtw_free_sta_priv(struct sta_priv *pstapriv);
+extern struct sta_info *rtw_alloc_stainfo(struct	sta_priv *pstapriv, u8 *hwaddr);
+extern u32	rtw_free_stainfo(_adapter *padapter , struct sta_info *psta);
+extern void rtw_free_all_stainfo(_adapter *padapter);
+extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr);
+extern u32 rtw_init_bcmc_stainfo(_adapter* padapter);
+extern struct sta_info* rtw_get_bcmc_stainfo(_adapter* padapter);
+extern u8 rtw_access_ctrl(_adapter *padapter, u8 *mac_addr);
+
+#endif //_STA_INFO_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_constants.h

@@ -1,3 +1,25 @@
+/******************************************************************************
+ * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************
+  * @file    wifi_constants.h
+  * @author
+  * @version
+  * @brief   This file provides the data types used for wlan API.
+  ******************************************************************************
+  */
+
 #ifndef _WIFI_CONSTANTS_H
 #define _WIFI_CONSTANTS_H
 
@@ -27,6 +49,9 @@ extern "C" {
 
 #define MCSSET_LEN			16
 
+/**
+  * @brief  The enumeration lists the results of the function.
+  */
 typedef enum
 {
     RTW_SUCCESS                      = 0,    /**< Success */
@@ -88,6 +113,11 @@ typedef enum
     RTW_DISABLED                     = -43   /**< Disabled in this build */
 } rtw_result_t;
 
+/**
+  * @brief  The enumeration lists the possible security types to set when connection.\n
+  *			Station mode supports OPEN, WEP, and WPA2.\n
+  *			AP mode support OPEN and WPA2.
+  */
 typedef enum {
     RTW_SECURITY_OPEN           = 0,                                                /**< Open security                           */
     RTW_SECURITY_WEP_PSK        = WEP_ENABLED,                                      /**< WEP Security with open authentication   */
@@ -125,11 +155,17 @@ typedef enum {
 	RTW_TRUE  = 1
 } rtw_bool_t;
 
+/**
+  * @brief  The enumeration lists the band types.
+  */
 typedef enum {
 	RTW_802_11_BAND_5GHZ   = 0, /**< Denotes 5GHz radio band   */
 	RTW_802_11_BAND_2_4GHZ = 1  /**< Denotes 2.4GHz radio band */
 } rtw_802_11_band_t;
 
+/**
+  * @brief  The enumeration lists all the country codes able to set to Wi-Fi driver.
+  */
 typedef enum {
 	/* CHANNEL PLAN */
 	RTW_COUNTRY_WORLD1,	// 0x20
@@ -328,21 +364,26 @@ typedef enum {
 
 }rtw_country_code_t;
 
+/**
+  * @brief  The enumeration lists the adaptivity types.
+  */
 typedef enum {
 	RTW_ADAPTIVITY_DISABLE = 0,
 	RTW_ADAPTIVITY_NORMAL,			// CE
 	RTW_ADAPTIVITY_CARRIER_SENSE	// MKK
 } rtw_adaptivity_mode_t;
 
-
+/**
+  * @brief  The enumeration lists the supported operation mode by WIFI driver,
+  *			including station and AP mode.
+  */
 typedef enum {
 	RTW_MODE_NONE = 0,
 	RTW_MODE_STA,
 	RTW_MODE_AP,
 	RTW_MODE_STA_AP,
 	RTW_MODE_PROMISC,
-	RTW_MODE_P2P,
+	RTW_MODE_P2P
-	RTW_MODE_MAX
 }rtw_mode_t;
 
 typedef enum {
@@ -351,17 +392,26 @@ typedef enum {
 	RTW_SCAN_ONE
 }rtw_scan_mode_t;
 
+/**
+  * @brief  The enumeration lists the status to describe the connection link.
+  */
 typedef enum {
 	RTW_LINK_DISCONNECTED = 0,
 	RTW_LINK_CONNECTED
 } rtw_link_status_t;
 
+/**
+  * @brief  The enumeration lists the scan types.
+  */
 typedef enum {
     RTW_SCAN_TYPE_ACTIVE              = 0x00,  /**< Actively scan a network by sending 802.11 probe(s)         */
     RTW_SCAN_TYPE_PASSIVE             = 0x01,  /**< Passively scan a network by listening for beacons from APs */
     RTW_SCAN_TYPE_PROHIBITED_CHANNELS = 0x04   /**< Passively scan on channels not enabled by the country code */
 } rtw_scan_type_t;
 
+/**
+  * @brief  The enumeration lists the bss types.
+  */
 typedef enum {
     RTW_BSS_TYPE_INFRASTRUCTURE = 0, /**< Denotes infrastructure network                  */
     RTW_BSS_TYPE_ADHOC          = 1, /**< Denotes an 802.11 ad-hoc IBSS network           */
@@ -388,33 +438,45 @@ typedef enum {
     RTW_WPS_TYPE_NONE                   = 0x0006 
 } rtw_wps_type_t;
 
+/**
+  * @brief  The enumeration lists all the network bgn mode.
+  */
 typedef enum {
     RTW_NETWORK_B   = 1,
 	RTW_NETWORK_BG  = 3,
 	RTW_NETWORK_BGN = 11
 } rtw_network_mode_t;
 
+/**
+  * @brief  The enumeration lists the interfaces.
+  */
 typedef enum {
     RTW_STA_INTERFACE     = 0, /**< STA or Client Interface  */
-    RTW_AP_INTERFACE      = 1, /**< softAP Interface         */
+    RTW_AP_INTERFACE      = 1, /**< SoftAP Interface         */
 } rtw_interface_t;
 
 /**
- * Enumeration of packet filter rules
+  * @brief  The enumeration lists the packet filter rules.
   */
 typedef enum {
-	RTW_POSITIVE_MATCHING  = 0, /**< Specifies that a filter should match a given pattern     */
+	RTW_POSITIVE_MATCHING  = 0, /**< Receive the data matching with this pattern and discard the other data   */
-	RTW_NEGATIVE_MATCHING  = 1  /**< Specifies that a filter should NOT match a given pattern */
+	RTW_NEGATIVE_MATCHING  = 1  /**< Discard the data matching with this pattern and receive the other data */
 } rtw_packet_filter_rule_e;
 
+/**
+  * @brief  The enumeration lists the promisc levels.
+  */
 typedef enum {
-	RTW_PROMISC_DISABLE = 0,  /**< disable the promisc */
+	RTW_PROMISC_DISABLE = 0,  /**< Disable the promisc */
-	RTW_PROMISC_ENABLE = 1,   /**< fetch all ethernet packets */
+	RTW_PROMISC_ENABLE = 1,   /**< Fetch all ethernet packets */
-	RTW_PROMISC_ENABLE_1 = 2, /**< fetch only B/M packets */
+	RTW_PROMISC_ENABLE_1 = 2, /**< Fetch only B/M packets */
-	RTW_PROMISC_ENABLE_2 = 3, /**< fetch all 802.11 packets*/
+	RTW_PROMISC_ENABLE_2 = 3, /**< Fetch all 802.11 packets*/
-	RTW_PROMISC_ENABLE_3 = 4, /**< fetch only B/M 802.11 packets*/
+	RTW_PROMISC_ENABLE_3 = 4, /**< Fetch only B/M 802.11 packets*/
 } rtw_rcr_level_t;
 
+/**
+  * @brief  The enumeration lists the disconnect reasons.
+  */
 typedef enum{
 	RTW_NO_ERROR = 0,
 	RTW_NONE_NETWORK = 1,
@@ -432,6 +494,9 @@ typedef enum {
 	RTW_TX_PWR_PERCENTAGE_12_5 = 4, /* 12.5% */
 }rtw_tx_pwr_percentage_t;
 
+/**
+  * @brief  The enumeration is event type indicated from wlan driver.
+  */
 typedef enum _WIFI_EVENT_INDICATE{
 	WIFI_EVENT_CONNECT = 0,
 	WIFI_EVENT_DISCONNECT = 1,
@@ -451,6 +516,7 @@ typedef enum _WIFI_EVENT_INDICATE{
 	WIFI_EVENT_BEACON_AFTER_DHCP = 15,
 	WIFI_EVENT_MAX,
 }WIFI_EVENT_INDICATE;
+//rtw_event_indicate_e;
 #ifdef	__cplusplus
 }
 #endif

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_structures.h

@@ -1,3 +1,25 @@
+/******************************************************************************
+ * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************
+  * @file    wifi_structures.h
+  * @author
+  * @version
+  * @brief   This file provides the data structures used for wlan API.
+  ******************************************************************************
+  */
+
 #ifndef _WIFI_STRUCTURES_H
 #define _WIFI_STRUCTURES_H
 
@@ -11,6 +33,10 @@ extern "C" {
 #if defined(__IAR_SYSTEMS_ICC__)
 #pragma pack(1)
 #endif
+
+/**
+  * @brief  The structure is used to describe the SSID.
+  */
 typedef struct rtw_ssid {
     unsigned char len;     /**< SSID length */
     unsigned char val[33]; /**< SSID name (AP name)  */
@@ -22,6 +48,10 @@ typedef struct rtw_ssid {
 #if defined(__IAR_SYSTEMS_ICC__)
 #pragma pack(1)
 #endif
+
+/**
+  * @brief  The structure is used to describe the unique 6-byte MAC address.
+  */
 typedef struct rtw_mac {
     unsigned char octet[6]; /**< Unique 6-byte MAC address */
 } rtw_mac_t;
@@ -29,6 +59,11 @@ typedef struct rtw_mac {
 #pragma pack()
 #endif
 
+/**
+  * @brief  The structure is used to describe the setting about SSID,
+  *			security type, password and default channel, used to start AP mode.
+  * @note  The data length of string pointed by ssid and password should not exceed 32.
+  */
 typedef struct rtw_ap_info {
 	rtw_ssid_t 			ssid;
 	rtw_security_t		security_type;
@@ -37,6 +72,11 @@ typedef struct rtw_ap_info {
 	int					channel;
 }rtw_ap_info_t;
 
+/**
+  * @brief  The structure is used to describe the station mode setting about SSID, 
+  *			security type and password, used when connecting to an AP.
+  * @note  The data length of string pointed by ssid and password should not exceed 32.
+  */
 typedef struct rtw_network_info {
 	rtw_ssid_t 			ssid;
 	rtw_mac_t			bssid;
@@ -46,9 +86,13 @@ typedef struct rtw_network_info {
 	int					key_id;
 }rtw_network_info_t;
 
-#if defined(__IAR_SYSTEMS_ICC__)
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
 #pragma pack(1)
 #endif
+
+/**
+  * @brief  The structure is used to describe the scan result of the AP.
+  */
 typedef struct rtw_scan_result {
     rtw_ssid_t              SSID;             /**< Service Set Identification (i.e. Name of Access Point)                    */
     rtw_mac_t               BSSID;            /**< Basic Service Set Identification (i.e. MAC address of Access Point)       */
@@ -59,10 +103,13 @@ typedef struct rtw_scan_result {
     unsigned int                      channel;          /**< Radio channel that the AP beacon was received on                          */
     rtw_802_11_band_t       band;             /**< Radio band                                                                */                                        
 } rtw_scan_result_t;
-#if defined(__IAR_SYSTEMS_ICC__)
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
 #pragma pack()
 #endif
 
+/**
+  * @brief  The structure is used to describe the data needed by scan result handler function.
+  */
 typedef struct rtw_scan_handler_result {
     rtw_scan_result_t ap_details;
     rtw_bool_t        scan_complete;
@@ -70,9 +117,13 @@ typedef struct rtw_scan_handler_result {
 
 } rtw_scan_handler_result_t;
 
-#if defined(__IAR_SYSTEMS_ICC__)
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
 #pragma pack(1)
 #endif
+
+/**
+  * @brief  The structure is used to store the WIFI setting gotten from WIFI driver.
+  */
 typedef struct rtw_wifi_setting {
 	rtw_mode_t		mode;
 	unsigned char 		ssid[33];
@@ -81,10 +132,13 @@ typedef struct rtw_wifi_setting {
 	unsigned char 		password[65];
 	unsigned char		key_idx;
 }rtw_wifi_setting_t;
-#if defined(__IAR_SYSTEMS_ICC__)
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
 #pragma pack()
 #endif
 
+/**
+  * @brief  The structure is used to describe the setting when configure the network.
+  */
 typedef struct rtw_wifi_config {
 	unsigned int		boot_mode;
 	unsigned char 		ssid[32];
@@ -95,19 +149,27 @@ typedef struct rtw_wifi_config {
 	unsigned char		channel;
 } rtw_wifi_config_t;
 
+/**
+  * @brief  The structure is used to describe the maclist.
+  */
 typedef struct
 {
     unsigned int    count;         /**< Number of MAC addresses in the list    */
     rtw_mac_t mac_list[1];   /**< Variable length array of MAC addresses */
 } rtw_maclist_t;
 
+/**
+  * @brief  The structure is used to describe the bss info of the network.\n
+  *			It include the version, BSSID, beacon_period, capability, SSID,
+  *			channel, atm_window, dtim_period, RSSI e.g.
+  */
 typedef struct {
-    unsigned int      version;                /* version field */
+    unsigned int      version;                /**< version field */
-    unsigned int      length;                 /* byte length of data in this record,   */
+    unsigned int      length;                 /**< byte length of data in this record,   */
                                           /* starting at version and including IEs */
     rtw_mac_t     BSSID;
-    unsigned short      beacon_period;          /* units are Kusec */
+    unsigned short      beacon_period;          /**< units are Kusec */
-    unsigned short      capability;             /* Capability information */
+    unsigned short      capability;             /**< Capability information */
     unsigned char       SSID_len;
     unsigned char       SSID[32];
     unsigned char       channel;
@@ -116,18 +178,21 @@ typedef struct {
 //        uint8_t   rates[16];              /* rates in 500kbps units w/hi bit set if basic */
 //    } rateset;                            /* supported rates */
 //    rtw_chanspec_t  chanspec;              /* chanspec for bss */
-    unsigned short      atim_window;            /* units are Kusec */
+    unsigned short      atim_window;            /**< units are Kusec */
-    unsigned char       dtim_period;            /* DTIM period */
+    unsigned char       dtim_period;            /**< DTIM period */
-    signed short       RSSI;                   /* receive signal strength (in dBm) */
+    signed short       RSSI;                   /**< receive signal strength (in dBm) */
 
-    unsigned char       n_cap;                  /* BSS is 802.11N Capable */
+    unsigned char       n_cap;                  /**< BSS is 802.11N Capable */
-    unsigned int      nbss_cap;               /* 802.11N BSS Capabilities (based on HT_CAP_*) */
+    unsigned int      nbss_cap;               /**< 802.11N BSS Capabilities (based on HT_CAP_*) */
-    unsigned char       basic_mcs[MCSSET_LEN];  /* 802.11N BSS required MCS set */
+    unsigned char       basic_mcs[MCSSET_LEN];  /**< 802.11N BSS required MCS set */
 
-    unsigned short      ie_offset;              /* offset at which IEs start, from beginning */
+    unsigned short      ie_offset;              /**< offset at which IEs start, from beginning */
-    unsigned int      ie_length;              /* byte length of Information Elements */
+    unsigned int      ie_length;             /**< byte length of Information Elements */
 } rtw_bss_info_t;
 
+/**
+  * @brief  The structure is used to set WIFI packet filter pattern.
+  */
 typedef struct {
 	unsigned short	offset;     /**< Offset in bytes to start filtering (referenced to the start of the ethernet packet) */
 	unsigned short	mask_size;  /**< Size of the mask in bytes */
@@ -159,7 +224,6 @@ typedef struct rtw_mac_filter_list{
 	unsigned char mac_addr[6];
 }rtw_mac_filter_list_t;
 
-
 #ifdef	__cplusplus
 }
 #endif

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_basic_types.h

@@ -0,0 +1,610 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __WLAN_BASIC_TYPES_H__
+#define __WLAN_BASIC_TYPES_H__
+
+
+/* ================================================
+  * Sections (1) rtl8195a and (2) other MCU based wlan driver
+  * For 8195a, some of the definitions are already defined in system wise "basic_types.h"
+  *================================================ */
+#define _SUCCESS		1
+#define _PASS		1
+#define _FAIL		0
+
+//ERRNO Define
+#define  EPERM     1  /* Operation not permitted */
+#define  ENOENT     2  /* No such file or directory */
+#define  ESRCH     3  /* No such process */
+#define  EINTR     4  /* Interrupted system call */
+#define  EIO     5  /* I/O error */
+#define  ENXIO     6  /* No such device or address */
+#define  E2BIG     7  /* Arg list too long */
+#define  ENOEXEC     8  /* Exec format error */
+#define  EBADF     9  /* Bad file number */
+#define  ECHILD    10  /* No child processes */
+#define  EAGAIN    11  /* Try again */
+#define  ENOMEM    12  /* Out of memory */
+#define  EACCES    13  /* Permission denied */
+#define  EFAULT    14  /* Bad address */
+#define  ENOTBLK    15  /* Block device required */
+#define  EBUSY    16  /* Device or resource busy */
+#define  EEXIST    17  /* File exists */
+#define  EXDEV    18  /* Cross-device link */
+#define  ENODEV    19  /* No such device */
+#define  ENOTDIR    20  /* Not a directory */
+#define  EISDIR    21  /* Is a directory */
+#define  EINVAL    22  /* Invalid argument */
+#define  ENFILE    23  /* File table overflow */
+#define  EMFILE    24  /* Too many open files */
+#define  ENOTTY    25  /* Not a typewriter */
+#define  ETXTBSY    26  /* Text file busy */
+#define  EFBIG    27  /* File too large */
+#define  ENOSPC    28  /* No space left on device */
+#define  ESPIPE    29  /* Illegal seek */
+#define  EROFS    30  /* Read-only file system */
+#define  EMLINK    31  /* Too many links */
+#define  EPIPE    32  /* Broken pipe */
+#define  EDOM    33  /* Math argument out of domain of func */
+#define  ERANGE    34  /* Math result not representable */
+#define  EDEADLK    35  /* Resource deadlock would occur */
+#define  ENAMETOOLONG  36  /* File name too long */
+#define  ENOLCK    37  /* No record locks available */
+#define  ENOSYS    38  /* Function not implemented */
+#define  ENOTEMPTY  39  /* Directory not empty */
+#define  ELOOP    40  /* Too many symbolic links encountered */
+#define  EWOULDBLOCK  EAGAIN  /* Operation would block */
+#define  ENOMSG    42  /* No message of desired type */
+#define  EIDRM    43  /* Identifier removed */
+#define  ECHRNG    44  /* Channel number out of range */
+#define  EL2NSYNC  45  /* Level 2 not synchronized */
+#define  EL3HLT    46  /* Level 3 halted */
+#define  EL3RST    47  /* Level 3 reset */
+#define  ELNRNG    48  /* Link number out of range */
+#define  EUNATCH    49  /* Protocol driver not attached */
+#define  ENOCSI    50  /* No CSI structure available */
+#define  EL2HLT    51  /* Level 2 halted */
+#define  EBADE    52  /* Invalid exchange */
+#define  EBADR    53  /* Invalid request descriptor */
+#define  EXFULL    54  /* Exchange full */
+#define  ENOANO    55  /* No anode */
+#define  EBADRQC    56  /* Invalid request code */
+#define  EBADSLT    57  /* Invalid slot */
+
+#define  EDEADLOCK  EDEADLK
+
+#define  EBFONT    59  /* Bad font file format */
+#define  ENOSTR    60  /* Device not a stream */
+#define  ENODATA    61  /* No data available */
+#define  ETIME    62  /* Timer expired */
+#define  ENOSR    63  /* Out of streams resources */
+#define  ENONET    64  /* Machine is not on the network */
+#define  ENOPKG    65  /* Package not installed */
+#define  EREMOTE    66  /* Object is remote */
+#define  ENOLINK    67  /* Link has been severed */
+#define  EADV    68  /* Advertise error */
+#define  ESRMNT    69  /* Srmount error */
+#define  ECOMM    70  /* Communication error on send */
+#define  EPROTO    71  /* Protocol error */
+#define  EMULTIHOP  72  /* Multihop attempted */
+#define  EDOTDOT    73  /* RFS specific error */
+#define  EBADMSG    74  /* Not a data message */
+#define  EOVERFLOW  75  /* Value too large for defined data type */
+#define  ENOTUNIQ  76  /* Name not unique on network */
+#define  EBADFD    77  /* File descriptor in bad state */
+#define  EREMCHG    78  /* Remote address changed */
+#define  ELIBACC    79  /* Can not access a needed shared library */
+#define  ELIBBAD    80  /* Accessing a corrupted shared library */
+#define  ELIBSCN    81  /* .lib section in a.out corrupted */
+#define  ELIBMAX    82  /* Attempting to link in too many shared libraries */
+#define  ELIBEXEC  83  /* Cannot exec a shared library directly */
+#define  EILSEQ    84  /* Illegal byte sequence */
+#define  ERESTART  85  /* Interrupted system call should be restarted */
+#define  ESTRPIPE  86  /* Streams pipe error */
+#define  EUSERS    87  /* Too many users */
+#define  ENOTSOCK  88  /* Socket operation on non-socket */
+#define  EDESTADDRREQ  89  /* Destination address required */
+#define  EMSGSIZE  90  /* Message too long */
+#define  EPROTOTYPE  91  /* Protocol wrong type for socket */
+#define  ENOPROTOOPT  92  /* Protocol not available */
+#define  EPROTONOSUPPORT  93  /* Protocol not supported */
+#define  ESOCKTNOSUPPORT  94  /* Socket type not supported */
+#define  EOPNOTSUPP  95  /* Operation not supported on transport endpoint */
+#define  EPFNOSUPPORT  96  /* Protocol family not supported */
+#define  EAFNOSUPPORT  97  /* Address family not supported by protocol */
+#define  EADDRINUSE  98  /* Address already in use */
+#define  EADDRNOTAVAIL  99  /* Cannot assign requested address */
+#define  ENETDOWN  100  /* Network is down */
+#define  ENETUNREACH  101  /* Network is unreachable */
+#define  ENETRESET  102  /* Network dropped connection because of reset */
+#define  ECONNABORTED  103  /* Software caused connection abort */
+#define  ECONNRESET  104  /* Connection reset by peer */
+#define  ENOBUFS    105  /* No buffer space available */
+#define  EISCONN    106  /* Transport endpoint is already connected */
+#define  ENOTCONN  107  /* Transport endpoint is not connected */
+#define  ESHUTDOWN  108  /* Cannot send after transport endpoint shutdown */
+#define  ETOOMANYREFS  109  /* Too many references: cannot splice */
+#define  ETIMEDOUT  110  /* Connection timed out */
+#define  ECONNREFUSED  111  /* Connection refused */
+#define  EHOSTDOWN  112  /* Host is down */
+#define  EHOSTUNREACH  113  /* No route to host */
+#define  EALREADY  114  /* Operation already in progress */
+#define  EINPROGRESS  115  /* Operation now in progress */
+#define  ESTALE    116  /* Stale NFS file handle */
+#define  EUCLEAN    117  /* Structure needs cleaning */
+#define  ENOTNAM    118  /* Not a XENIX named type file */
+#define  ENAVAIL    119  /* No XENIX semaphores available */
+#define  EISNAM    120  /* Is a named type file */
+#define  EREMOTEIO  121  /* Remote I/O error */
+#define  EDQUOT    122  /* Quota exceeded */
+
+#define  ENOMEDIUM  123  /* No medium found */
+#define  EMEDIUMTYPE  124  /* Wrong medium type */
+
+
+#define ENSROK    0 /* DNS server returned answer with no data */
+#define ENSRNODATA  160 /* DNS server returned answer with no data */
+#define ENSRFORMERR 161 /* DNS server claims query was misformatted */
+#define ENSRSERVFAIL 162  /* DNS server returned general failure */
+#define ENSRNOTFOUND 163  /* Domain name not found */
+#define ENSRNOTIMP  164 /* DNS server does not implement requested operation */
+#define ENSRREFUSED 165 /* DNS server refused query */
+#define ENSRBADQUERY 166  /* Misformatted DNS query */
+#define ENSRBADNAME 167 /* Misformatted domain name */
+#define ENSRBADFAMILY 168 /* Unsupported address family */
+#define ENSRBADRESP 169 /* Misformatted DNS reply */
+#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */
+#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */
+#define ENSROF    172 /* End of file */
+#define ENSRFILE  173 /* Error reading file */
+#define ENSRNOMEM 174 /* Out of memory */
+#define ENSRDESTRUCTION 175 /* Application terminated lookup */
+#define ENSRQUERYDOMAINTOOLONG  176 /* Domain name is too long */
+#define ENSRCNAMELOOP 177 /* Domain name is too long */
+
+
+
+
+
+
+
+/* ================================================
+  * Sections only for other MCU based wlan driver
+  *========================================== ======*/
+ #if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B)
+#include <drv_conf.h>
+
+#define SUCCESS	0
+#define FAIL	(-1)
+
+#ifndef TRUE
+	#define _TRUE	1
+#else
+	#define _TRUE	TRUE	
+#endif
+		
+#ifndef FALSE		
+	#define _FALSE	0
+#else
+	#define _FALSE	FALSE	
+#endif
+
+//
+// pack & weak attribute
+//
+#if defined (__ICCARM__)
+
+#define RTW_PACK_STRUCT_BEGIN
+#define RTW_PACK_STRUCT_STRUCT 
+#define RTW_PACK_STRUCT_END
+#define RTW_PACK_STRUCT_USE_INCLUDES
+
+#define RTW_WEAK					__weak
+
+#elif defined (__CC_ARM)
+
+#define RTW_PACK_STRUCT_BEGIN	__packed
+#define RTW_PACK_STRUCT_STRUCT 
+#define RTW_PACK_STRUCT_END
+
+#define RTW_WEAK					 __weak 
+
+#elif defined (__GNUC__)
+
+#define RTW_PACK_STRUCT_BEGIN
+#define RTW_PACK_STRUCT_STRUCT 	__attribute__ ((__packed__))
+#define RTW_PACK_STRUCT_END
+
+#define RTW_WEAK					__attribute__ ((weak))
+
+#elif defined(PLATFORM_WINDOWS)
+
+#define RTW_PACK_STRUCT_BEGIN
+#define RTW_PACK_STRUCT_STRUCT 
+#define RTW_PACK_STRUCT_END
+#define RTW_PACK_STRUCT_USE_INCLUDES
+#endif
+
+#ifndef BIT
+	#define BIT(x)	((u32)1 << (x))
+#endif
+
+#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B)
+#define BIT0	0x00000001
+#define BIT1	0x00000002
+#define BIT2	0x00000004
+#define BIT3	0x00000008
+#define BIT4	0x00000010
+#define BIT5	0x00000020
+#define BIT6	0x00000040
+#define BIT7	0x00000080
+#define BIT8	0x00000100
+#define BIT9	0x00000200
+#define BIT10	0x00000400
+#define BIT11	0x00000800
+#define BIT12	0x00001000
+#define BIT13	0x00002000
+#define BIT14	0x00004000
+#define BIT15	0x00008000
+#define BIT16	0x00010000
+#define BIT17	0x00020000
+#define BIT18	0x00040000
+#define BIT19	0x00080000
+#define BIT20	0x00100000
+#define BIT21	0x00200000
+#define BIT22	0x00400000
+#define BIT23	0x00800000
+#define BIT24	0x01000000
+#define BIT25	0x02000000
+#define BIT26	0x04000000
+#define BIT27	0x08000000
+#define BIT28	0x10000000
+#define BIT29	0x20000000
+#define BIT30	0x40000000
+#define BIT31	0x80000000
+#define BIT32	0x0100000000
+#define BIT33	0x0200000000
+#define BIT34	0x0400000000
+#define BIT35	0x0800000000
+#define BIT36	0x1000000000
+#endif
+
+
+#ifdef PLATFORM_ECOS
+
+	#define IN
+	#define OUT
+	#define VOID void
+	#define NDIS_OID uint
+	#define NDIS_STATUS uint
+
+	typedef unsigned int		uint;
+	typedef	signed int		sint;
+
+	#ifndef	PVOID
+	typedef void *			PVOID;
+	#endif
+
+
+	typedef unsigned int		__kernel_size_t;
+	typedef int			__kernel_ssize_t;
+
+	typedef	__kernel_size_t		SIZE_T;	
+	typedef	__kernel_ssize_t	SSIZE_T;
+	#define FIELD_OFFSET(s,field)	((SSIZE_T)&((s*)(0))->field)
+
+#endif
+
+
+#ifdef PLATFORM_WINDOWS
+
+	typedef signed char s8;
+	typedef unsigned char u8;
+
+	typedef signed short s16;
+	typedef unsigned short u16;
+
+	typedef signed long s32;
+	typedef unsigned long u32;
+	
+	typedef unsigned int	uint;
+	typedef	signed int		sint;
+
+
+	typedef signed long long s64;
+	typedef unsigned long long u64;
+
+	#ifdef NDIS50_MINIPORT
+	
+		#define NDIS_MAJOR_VERSION       5
+		#define NDIS_MINOR_VERSION       0
+
+	#endif
+
+	#ifdef NDIS51_MINIPORT
+
+		#define NDIS_MAJOR_VERSION       5
+		#define NDIS_MINOR_VERSION       1
+
+	#endif
+
+	typedef NDIS_PROC proc_t;
+
+	typedef LONG atomic_t;
+
+#endif
+
+
+#ifdef PLATFORM_LINUX
+
+	#include <linux/types.h>
+	#define IN
+	#define OUT
+	#define VOID void
+	#define NDIS_OID uint
+	#define NDIS_STATUS uint
+
+	typedef	signed int sint;
+
+	#ifndef	PVOID
+	typedef void * PVOID;
+	//#define PVOID	(void *)
+	#endif
+
+	typedef void (*proc_t)(void*);
+
+	typedef 	__kernel_size_t	SIZE_T;	
+	typedef	__kernel_ssize_t	SSIZE_T;
+	#define FIELD_OFFSET(s,field)	((SSIZE_T)&((s*)(0))->field)
+	
+#endif
+
+
+#ifdef PLATFORM_FREEBSD
+	typedef signed char s8;
+	typedef unsigned char u8;
+
+	typedef signed short s16;
+	typedef unsigned short u16;
+
+	typedef signed int s32;
+	typedef unsigned int u32;
+	
+	typedef unsigned int	uint;
+	typedef	signed int		sint;
+	typedef long atomic_t;
+
+	typedef signed long long s64;
+	typedef unsigned long long u64;
+	#define IN
+	#define OUT
+	#define VOID void
+	#define NDIS_OID uint
+	#define NDIS_STATUS uint
+	
+	#ifndef	PVOID
+	typedef void * PVOID;
+	//#define PVOID	(void *)
+	#endif
+	typedef u32 dma_addr_t;
+
+	typedef void (*proc_t)(void*);
+  
+  typedef unsigned int __kernel_size_t;
+  typedef int __kernel_ssize_t;
+  
+	typedef 	__kernel_size_t	SIZE_T;	
+	typedef	__kernel_ssize_t	SSIZE_T;
+	#define FIELD_OFFSET(s,field)	((SSIZE_T)&((s*)(0))->field)
+	
+#endif
+
+
+#define MEM_ALIGNMENT_OFFSET	(sizeof (SIZE_T))
+#define MEM_ALIGNMENT_PADDING	(sizeof(SIZE_T) - 1)
+
+#define SIZE_PTR SIZE_T
+#define SSIZE_PTR SSIZE_T
+
+//port from fw by thomas
+// TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness
+
+/*
+ *	Call endian free function when
+ *		1. Read/write packet content.
+ *		2. Before write integer to IO.
+ *		3. After read integer from IO.
+*/
+
+//
+// Byte Swapping routine.
+//
+#define EF1Byte	
+#define EF2Byte 	le16_to_cpu
+#define EF4Byte	le32_to_cpu
+
+//
+// Read LE format data from memory
+//
+#define ReadEF1Byte(_ptr)		EF1Byte(*((u8 *)(_ptr)))
+#define ReadEF2Byte(_ptr)		EF2Byte(*((u16 *)(_ptr)))
+#define ReadEF4Byte(_ptr)		EF4Byte(*((u32 *)(_ptr)))
+
+//
+// Write LE data to memory
+//
+#define WriteEF1Byte(_ptr, _val)	(*((u8 *)(_ptr)))=EF1Byte(_val)
+#define WriteEF2Byte(_ptr, _val)	(*((u16 *)(_ptr)))=EF2Byte(_val)
+#define WriteEF4Byte(_ptr, _val)	(*((u32 *)(_ptr)))=EF4Byte(_val)									
+
+//
+//	Example:
+//		BIT_LEN_MASK_32(0) => 0x00000000
+//		BIT_LEN_MASK_32(1) => 0x00000001
+//		BIT_LEN_MASK_32(2) => 0x00000003
+//		BIT_LEN_MASK_32(32) => 0xFFFFFFFF
+//
+#define BIT_LEN_MASK_32(__BitLen) \
+	(0xFFFFFFFF >> (32 - (__BitLen)))
+//
+//	Example:
+//		BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
+//		BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
+//
+#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \
+	(BIT_LEN_MASK_32(__BitLen) << (__BitOffset)) 
+
+//
+//	Description:
+//		Return 4-byte value in host byte ordering from
+//		4-byte pointer in litten-endian system.
+//
+#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
+	(EF4Byte(*((u32 *)(__pStart))))
+
+//
+//	Description:
+//		Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to
+//		4-byte value in host byte ordering.
+//
+#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
+	( \
+		( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \
+		& \
+		BIT_LEN_MASK_32(__BitLen) \
+	)
+
+//
+//	Description:
+//		Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering  
+//		and return the result in 4-byte value in host byte ordering.
+//
+#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
+	( \
+		LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
+		& \
+		( ~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \
+	)
+
+//
+//	Description:
+//		Set subfield of little-endian 4-byte value to specified value.	
+//
+#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
+	*((u32 *)(__pStart)) = \
+		EF4Byte( \
+			LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
+			| \
+			( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \
+		);
+
+		
+#define BIT_LEN_MASK_16(__BitLen) \
+		(0xFFFF >> (16 - (__BitLen)))
+		
+#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \
+	(BIT_LEN_MASK_16(__BitLen) << (__BitOffset))
+	
+#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
+	(EF2Byte(*((u16 *)(__pStart))))
+	
+#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
+	( \
+		( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \
+		& \
+		BIT_LEN_MASK_16(__BitLen) \
+	)
+	
+#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
+	( \
+		LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
+		& \
+		( ~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \
+	)
+
+#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
+	*((u16 *)(__pStart)) = \
+		EF2Byte( \
+			LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
+			| \
+			( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \
+		);
+			
+#define BIT_LEN_MASK_8(__BitLen) \
+		(0xFF >> (8 - (__BitLen)))
+
+#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \
+	(BIT_LEN_MASK_8(__BitLen) << (__BitOffset))
+
+#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
+	(EF1Byte(*((u8 *)(__pStart))))
+
+#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
+	( \
+		( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \
+		& \
+		BIT_LEN_MASK_8(__BitLen) \
+	)
+
+#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
+	( \
+		LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
+		& \
+		( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \
+	)
+
+#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
+	*((u8 *)(__pStart)) = \
+		EF1Byte( \
+			LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
+			| \
+			( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \
+		);
+
+//pclint
+#define LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \
+	( \
+		LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
+	)
+
+//pclint
+#define SET_BITS_TO_LE_1BYTE_8BIT(__pStart, __BitOffset, __BitLen, __Value) \
+{ \
+	*((u8*)(__pStart)) = \
+		EF1Byte( \
+			LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \
+			| \
+			((u8)__Value) \
+		); \
+}
+
+// Get the N-bytes aligment offset from the current length
+#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))
+
+typedef unsigned char	BOOLEAN,*PBOOLEAN;
+
+#define TEST_FLAG(__Flag,__testFlag)		(((__Flag) & (__testFlag)) != 0)
+
+
+
+#endif//! defined(CONFIG_PLATFORM_8195A)
+
+#endif //__WLAN_BASIC_TYPES_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_bssdef.h

@@ -0,0 +1,756 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __WLAN_BSSDEF_H__
+#define __WLAN_BSSDEF_H__
+
+
+#define MAX_IE_SZ	768 //384//
+
+#if defined(PLATFORM_LINUX) || defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined(PLATFORM_CMSIS_RTOS)
+#define NDIS_802_11_LENGTH_SSID         32
+#define NDIS_802_11_LENGTH_RATES        8
+#define NDIS_802_11_LENGTH_RATES_EX     16
+
+typedef unsigned char   NDIS_802_11_MAC_ADDRESS[6];
+typedef long    		NDIS_802_11_RSSI;           // in dBm
+typedef unsigned char   NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES];        // Set of 8 data rates
+typedef unsigned char   NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX];  // Set of 16 data rates
+
+
+typedef  u32  NDIS_802_11_KEY_INDEX;
+typedef unsigned long long NDIS_802_11_KEY_RSC;
+
+
+typedef struct _NDIS_802_11_SSID
+{
+  u32  SsidLength;
+  u8  Ssid[NDIS_802_11_LENGTH_SSID+4];
+}
+#ifdef __CC_ARM	
+__attribute__((packed))
+#endif
+NDIS_802_11_SSID, *PNDIS_802_11_SSID;
+
+typedef enum _NDIS_802_11_NETWORK_TYPE
+{
+    Ndis802_11FH,
+    Ndis802_11DS,
+    Ndis802_11OFDM5,
+    Ndis802_11OFDM24,
+    Ndis802_11NetworkTypeMax    // not a real type, defined as an upper bound
+} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE;
+
+typedef struct _NDIS_802_11_CONFIGURATION_FH
+{
+    u32           Length;             // Length of structure
+    u32           HopPattern;         // As defined by 802.11, MSB set
+    u32           HopSet;             // to one if non-802.11
+    u32           DwellTime;          // units are Kusec
+}
+#ifdef __CC_ARM	
+__attribute__((packed))
+#endif
+NDIS_802_11_CONFIGURATION_FH, *PNDIS_802_11_CONFIGURATION_FH;
+ 
+
+/*
+	FW will only save the channel number in DSConfig.
+	ODI Handler will convert the channel number to freq. number.	
+*/
+typedef struct _NDIS_802_11_CONFIGURATION
+{
+    u32           Length;             // Length of structure
+    u32           BeaconPeriod;       // units are Kusec
+    u32           ATIMWindow;         // units are Kusec
+    u32           DSConfig;           // Frequency, units are kHz
+    NDIS_802_11_CONFIGURATION_FH    FHConfig;
+}
+#ifdef __CC_ARM	
+__attribute__((packed))
+#endif
+NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION;
+
+
+
+typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE
+{
+    Ndis802_11IBSS,
+    Ndis802_11Infrastructure,
+    Ndis802_11AutoUnknown,
+    Ndis802_11InfrastructureMax,     // Not a real value, defined as upper bound
+    Ndis802_11APMode
+} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
+
+
+
+
+
+typedef struct _NDIS_802_11_FIXED_IEs
+{
+  u8  Timestamp[8];
+  u16  BeaconInterval;
+  u16  Capabilities;
+} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs;
+
+
+
+typedef struct _NDIS_802_11_VARIABLE_IEs
+{
+  u8  ElementID;
+  u8  Length;
+  u8  data[1];
+} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs;
+
+
+
+/*
+
+
+
+Length is the 4 bytes multiples of the sume of
+	sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + sizeof (NDIS_802_11_SSID) + sizeof (u32)
++   sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + sizeof (NDIS_802_11_CONFIGURATION)
++   sizeof (NDIS_802_11_RATES_EX) + IELength
+
+Except the IELength, all other fields are fixed length. Therefore, we can define a marco to present the
+partial sum.
+
+*/
+#if 0
+typedef struct _NDIS_WLAN_BSSID_EX
+{
+  u32  Length;
+  NDIS_802_11_MAC_ADDRESS  MacAddress;
+  u8  Reserved[2];//[0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity;
+  NDIS_802_11_SSID  Ssid;
+  u32  Privacy;
+  NDIS_802_11_RSSI  Rssi;
+  NDIS_802_11_NETWORK_TYPE  NetworkTypeInUse;
+  NDIS_802_11_CONFIGURATION  Configuration;
+  NDIS_802_11_NETWORK_INFRASTRUCTURE  InfrastructureMode;
+  NDIS_802_11_RATES_EX  SupportedRates;
+  u32  IELength;
+  u8  IEs[MAX_IE_SZ];	//(timestamp, beacon interval, and capability information)
+} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX;
+
+
+typedef struct _NDIS_802_11_BSSID_LIST_EX
+{
+  u32  NumberOfItems;
+  NDIS_WLAN_BSSID_EX  Bssid[1];
+} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX;
+#endif
+
+typedef enum _NDIS_802_11_AUTHENTICATION_MODE
+{
+    Ndis802_11AuthModeOpen,
+    Ndis802_11AuthModeShared,
+    Ndis802_11AuthModeAutoSwitch,
+    Ndis802_11AuthModeWPA,
+    Ndis802_11AuthModeWPAPSK,
+    Ndis802_11AuthModeWPANone,
+    Ndis802_11AuthModeWAPI,
+    Ndis802_11AuthModeMax               // Not a real mode, defined as upper bound
+} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;
+
+typedef enum _NDIS_802_11_WEP_STATUS
+{
+    Ndis802_11WEPEnabled,
+    Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
+    Ndis802_11WEPDisabled,
+    Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled,
+    Ndis802_11WEPKeyAbsent,
+    Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,
+    Ndis802_11WEPNotSupported,
+    Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,
+    Ndis802_11Encryption2Enabled,
+    Ndis802_11Encryption2KeyAbsent,
+    Ndis802_11Encryption3Enabled,
+    Ndis802_11Encryption3KeyAbsent,
+    Ndis802_11_EncrypteionWAPI
+} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,
+  NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;
+
+
+#define NDIS_802_11_AI_REQFI_CAPABILITIES      1
+#define NDIS_802_11_AI_REQFI_LISTENINTERVAL    2
+#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS  4
+
+#define NDIS_802_11_AI_RESFI_CAPABILITIES      1
+#define NDIS_802_11_AI_RESFI_STATUSCODE        2
+#define NDIS_802_11_AI_RESFI_ASSOCIATIONID     4
+
+typedef struct _NDIS_802_11_AI_REQFI
+{
+    u16 Capabilities;
+    u16 ListenInterval;
+    NDIS_802_11_MAC_ADDRESS  CurrentAPAddress;
+} NDIS_802_11_AI_REQFI, *PNDIS_802_11_AI_REQFI;
+
+typedef struct _NDIS_802_11_AI_RESFI
+{
+    u16 Capabilities;
+    u16 StatusCode;
+    u16 AssociationId;
+} NDIS_802_11_AI_RESFI, *PNDIS_802_11_AI_RESFI;
+
+typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION
+{
+    u32                   Length;
+    u16                  AvailableRequestFixedIEs;
+    NDIS_802_11_AI_REQFI    RequestFixedIEs;
+    u32                   RequestIELength;
+    u32                   OffsetRequestIEs;
+    u16                  AvailableResponseFixedIEs;
+    NDIS_802_11_AI_RESFI    ResponseFixedIEs;
+    u32                   ResponseIELength;
+    u32                   OffsetResponseIEs;
+} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION;
+
+typedef enum _NDIS_802_11_RELOAD_DEFAULTS
+{
+   Ndis802_11ReloadWEPKeys
+} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS;
+
+
+// Key mapping keys require a BSSID
+typedef struct _NDIS_802_11_KEY
+{
+    u32           Length;             // Length of this structure
+    u32           KeyIndex;           
+    u32           KeyLength;          // length of key in bytes
+    NDIS_802_11_MAC_ADDRESS BSSID;
+    NDIS_802_11_KEY_RSC KeyRSC;
+    u8           KeyMaterial[32];     // variable length depending on above field
+} NDIS_802_11_KEY, *PNDIS_802_11_KEY;
+
+typedef struct _NDIS_802_11_REMOVE_KEY
+{
+    u32                   Length;        // Length of this structure
+    u32                   KeyIndex;           
+    NDIS_802_11_MAC_ADDRESS BSSID;      
+} NDIS_802_11_REMOVE_KEY, *PNDIS_802_11_REMOVE_KEY;
+
+typedef struct _NDIS_802_11_WEP
+{
+    u32     Length;        // Length of this structure
+    u32     KeyIndex;      // 0 is the per-client key, 1-N are the global keys
+    u32     KeyLength;     // length of key in bytes
+    u8     KeyMaterial[16];// variable length depending on above field
+} NDIS_802_11_WEP, *PNDIS_802_11_WEP;
+
+typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST
+{
+    u32 Length;            // Length of structure
+    NDIS_802_11_MAC_ADDRESS Bssid;
+    u32 Flags;
+} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST;
+
+typedef enum _NDIS_802_11_STATUS_TYPE
+{
+	Ndis802_11StatusType_Authentication,
+	Ndis802_11StatusType_MediaStreamMode,
+	Ndis802_11StatusType_PMKID_CandidateList,		
+	Ndis802_11StatusTypeMax    // not a real type, defined as an upper bound
+} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE;
+
+typedef struct _NDIS_802_11_STATUS_INDICATION
+{
+    NDIS_802_11_STATUS_TYPE StatusType;
+} NDIS_802_11_STATUS_INDICATION, *PNDIS_802_11_STATUS_INDICATION;
+
+// mask for authentication/integrity fields
+#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS        0x0f
+#define NDIS_802_11_AUTH_REQUEST_REAUTH			0x01
+#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE		0x02
+#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR		0x06
+#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR		0x0E
+
+// MIC check time, 60 seconds.
+#define MIC_CHECK_TIME	60000000
+
+typedef struct _NDIS_802_11_AUTHENTICATION_EVENT
+{
+    NDIS_802_11_STATUS_INDICATION       Status;
+    NDIS_802_11_AUTHENTICATION_REQUEST  Request[1];
+} NDIS_802_11_AUTHENTICATION_EVENT, *PNDIS_802_11_AUTHENTICATION_EVENT;
+        
+typedef struct _NDIS_802_11_TEST
+{
+    u32 Length;
+    u32 Type;
+    union
+    {
+        NDIS_802_11_AUTHENTICATION_EVENT AuthenticationEvent;
+        NDIS_802_11_RSSI RssiTrigger;
+    }tt;
+} NDIS_802_11_TEST, *PNDIS_802_11_TEST;
+
+
+#endif //end of #ifdef PLATFORM_LINUX
+
+#ifdef PLATFORM_FREEBSD
+
+#define NDIS_802_11_LENGTH_SSID         32
+#define NDIS_802_11_LENGTH_RATES        8
+#define NDIS_802_11_LENGTH_RATES_EX     16
+
+typedef unsigned char   NDIS_802_11_MAC_ADDRESS[6];
+typedef long    		NDIS_802_11_RSSI;           // in dBm
+typedef unsigned char   NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES];        // Set of 8 data rates
+typedef unsigned char   NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX];  // Set of 16 data rates
+
+
+typedef  u32  NDIS_802_11_KEY_INDEX;
+typedef unsigned long long NDIS_802_11_KEY_RSC;
+
+
+typedef struct _NDIS_802_11_SSID
+{
+  u32  SsidLength;
+  u8  Ssid[32];
+} NDIS_802_11_SSID, *PNDIS_802_11_SSID;
+
+typedef enum _NDIS_802_11_NETWORK_TYPE
+{
+    Ndis802_11FH,
+    Ndis802_11DS,
+    Ndis802_11OFDM5,
+    Ndis802_11OFDM24,
+    Ndis802_11NetworkTypeMax    // not a real type, defined as an upper bound
+} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE;
+
+typedef struct _NDIS_802_11_CONFIGURATION_FH
+{
+    u32           Length;             // Length of structure
+    u32           HopPattern;         // As defined by 802.11, MSB set
+    u32           HopSet;             // to one if non-802.11
+    u32           DwellTime;          // units are Kusec
+} NDIS_802_11_CONFIGURATION_FH, *PNDIS_802_11_CONFIGURATION_FH;
+ 
+
+/*
+	FW will only save the channel number in DSConfig.
+	ODI Handler will convert the channel number to freq. number.	
+*/
+typedef struct _NDIS_802_11_CONFIGURATION
+{
+    u32           Length;             // Length of structure
+    u32           BeaconPeriod;       // units are Kusec
+    u32           ATIMWindow;         // units are Kusec
+    u32           DSConfig;           // Frequency, units are kHz
+    NDIS_802_11_CONFIGURATION_FH    FHConfig;
+} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION;
+
+
+
+typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE
+{
+    Ndis802_11IBSS,
+    Ndis802_11Infrastructure,
+    Ndis802_11AutoUnknown,
+    Ndis802_11InfrastructureMax,     // Not a real value, defined as upper bound
+    Ndis802_11APMode
+} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
+
+
+
+
+
+typedef struct _NDIS_802_11_FIXED_IEs
+{
+  u8  Timestamp[8];
+  u16  BeaconInterval;
+  u16  Capabilities;
+} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs;
+
+
+
+typedef struct _NDIS_802_11_VARIABLE_IEs
+{
+  u8  ElementID;
+  u8  Length;
+  u8  data[1];
+} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs;
+
+
+
+/*
+
+
+
+Length is the 4 bytes multiples of the sume of
+	sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + sizeof (NDIS_802_11_SSID) + sizeof (u32)
++   sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + sizeof (NDIS_802_11_CONFIGURATION)
++   sizeof (NDIS_802_11_RATES_EX) + IELength
+
+Except the IELength, all other fields are fixed length. Therefore, we can define a marco to present the
+partial sum.
+
+*/
+#if 0
+typedef struct _NDIS_WLAN_BSSID_EX
+{
+  u32  Length;
+  NDIS_802_11_MAC_ADDRESS  MacAddress;
+  u8  Reserved[2];//[0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity;
+  NDIS_802_11_SSID  Ssid;
+  u32  Privacy;
+  NDIS_802_11_RSSI  Rssi;
+  NDIS_802_11_NETWORK_TYPE  NetworkTypeInUse;
+  NDIS_802_11_CONFIGURATION  Configuration;
+  NDIS_802_11_NETWORK_INFRASTRUCTURE  InfrastructureMode;
+  NDIS_802_11_RATES_EX  SupportedRates;
+  u32  IELength;
+  u8  IEs[MAX_IE_SZ];	//(timestamp, beacon interval, and capability information)
+} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX;
+
+
+typedef struct _NDIS_802_11_BSSID_LIST_EX
+{
+  u32  NumberOfItems;
+  NDIS_WLAN_BSSID_EX  Bssid[1];
+} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX;
+#endif
+
+typedef enum _NDIS_802_11_AUTHENTICATION_MODE
+{
+    Ndis802_11AuthModeOpen,
+    Ndis802_11AuthModeShared,
+    Ndis802_11AuthModeAutoSwitch,
+    Ndis802_11AuthModeWPA,
+    Ndis802_11AuthModeWPAPSK,
+    Ndis802_11AuthModeWPANone,
+    Ndis802_11AuthModeMax               // Not a real mode, defined as upper bound
+} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;
+
+typedef enum _NDIS_802_11_WEP_STATUS
+{
+    Ndis802_11WEPEnabled,
+    Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
+    Ndis802_11WEPDisabled,
+    Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled,
+    Ndis802_11WEPKeyAbsent,
+    Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,
+    Ndis802_11WEPNotSupported,
+    Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,
+    Ndis802_11Encryption2Enabled,
+    Ndis802_11Encryption2KeyAbsent,
+    Ndis802_11Encryption3Enabled,
+    Ndis802_11Encryption3KeyAbsent
+} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,
+  NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;
+
+
+#define NDIS_802_11_AI_REQFI_CAPABILITIES      1
+#define NDIS_802_11_AI_REQFI_LISTENINTERVAL    2
+#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS  4
+
+#define NDIS_802_11_AI_RESFI_CAPABILITIES      1
+#define NDIS_802_11_AI_RESFI_STATUSCODE        2
+#define NDIS_802_11_AI_RESFI_ASSOCIATIONID     4
+
+typedef struct _NDIS_802_11_AI_REQFI
+{
+    u16 Capabilities;
+    u16 ListenInterval;
+    NDIS_802_11_MAC_ADDRESS  CurrentAPAddress;
+} NDIS_802_11_AI_REQFI, *PNDIS_802_11_AI_REQFI;
+
+typedef struct _NDIS_802_11_AI_RESFI
+{
+    u16 Capabilities;
+    u16 StatusCode;
+    u16 AssociationId;
+} NDIS_802_11_AI_RESFI, *PNDIS_802_11_AI_RESFI;
+
+typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION
+{
+    u32                   Length;
+    u16                  AvailableRequestFixedIEs;
+    NDIS_802_11_AI_REQFI    RequestFixedIEs;
+    u32                   RequestIELength;
+    u32                   OffsetRequestIEs;
+    u16                  AvailableResponseFixedIEs;
+    NDIS_802_11_AI_RESFI    ResponseFixedIEs;
+    u32                   ResponseIELength;
+    u32                   OffsetResponseIEs;
+} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION;
+
+typedef enum _NDIS_802_11_RELOAD_DEFAULTS
+{
+   Ndis802_11ReloadWEPKeys
+} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS;
+
+
+// Key mapping keys require a BSSID
+typedef struct _NDIS_802_11_KEY
+{
+    u32           Length;             // Length of this structure
+    u32           KeyIndex;           
+    u32           KeyLength;          // length of key in bytes
+    NDIS_802_11_MAC_ADDRESS BSSID;
+    NDIS_802_11_KEY_RSC KeyRSC;
+    u8           KeyMaterial[32];     // variable length depending on above field
+} NDIS_802_11_KEY, *PNDIS_802_11_KEY;
+
+typedef struct _NDIS_802_11_REMOVE_KEY
+{
+    u32                   Length;        // Length of this structure
+    u32                   KeyIndex;           
+    NDIS_802_11_MAC_ADDRESS BSSID;      
+} NDIS_802_11_REMOVE_KEY, *PNDIS_802_11_REMOVE_KEY;
+
+typedef struct _NDIS_802_11_WEP
+{
+    u32     Length;        // Length of this structure
+    u32     KeyIndex;      // 0 is the per-client key, 1-N are the global keys
+    u32     KeyLength;     // length of key in bytes
+    u8     KeyMaterial[16];// variable length depending on above field
+} NDIS_802_11_WEP, *PNDIS_802_11_WEP;
+
+typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST
+{
+    u32 Length;            // Length of structure
+    NDIS_802_11_MAC_ADDRESS Bssid;
+    u32 Flags;
+} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST;
+
+typedef enum _NDIS_802_11_STATUS_TYPE
+{
+	Ndis802_11StatusType_Authentication,
+	Ndis802_11StatusType_MediaStreamMode,
+	Ndis802_11StatusType_PMKID_CandidateList,		
+	Ndis802_11StatusTypeMax    // not a real type, defined as an upper bound
+} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE;
+
+typedef struct _NDIS_802_11_STATUS_INDICATION
+{
+    NDIS_802_11_STATUS_TYPE StatusType;
+} NDIS_802_11_STATUS_INDICATION, *PNDIS_802_11_STATUS_INDICATION;
+
+// mask for authentication/integrity fields
+#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS        0x0f
+#define NDIS_802_11_AUTH_REQUEST_REAUTH			0x01
+#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE		0x02
+#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR		0x06
+#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR		0x0E
+
+// MIC check time, 60 seconds.
+#define MIC_CHECK_TIME	60000000
+
+typedef struct _NDIS_802_11_AUTHENTICATION_EVENT
+{
+    NDIS_802_11_STATUS_INDICATION       Status;
+    NDIS_802_11_AUTHENTICATION_REQUEST  Request[1];
+} NDIS_802_11_AUTHENTICATION_EVENT, *PNDIS_802_11_AUTHENTICATION_EVENT;
+        
+typedef struct _NDIS_802_11_TEST
+{
+    u32 Length;
+    u32 Type;
+    union
+    {
+        NDIS_802_11_AUTHENTICATION_EVENT AuthenticationEvent;
+        NDIS_802_11_RSSI RssiTrigger;
+    }tt;
+} NDIS_802_11_TEST, *PNDIS_802_11_TEST;
+
+
+#endif //PLATFORM_FREEBSD
+
+typedef struct _WLAN_PHY_INFO
+{
+	u8	SignalStrength;		//(in percentage)
+  	u8	SignalQuality;		//(in percentage)
+  	u8	Optimum_antenna;  	//for Antenna diversity
+  	u8  	Reserved_0;
+}
+#ifdef __CC_ARM	
+__attribute__((packed))
+#endif
+WLAN_PHY_INFO,*PWLAN_PHY_INFO;
+
+typedef struct _WLAN_BCN_INFO
+{
+	/* these infor get from rtw_get_encrypt_info when
+	 * 	 * translate scan to UI */
+	u8	encryp_protocol;	//ENCRYP_PROTOCOL_E: OPEN/WEP/WPA/WPA2/WAPI
+	int	group_cipher;		//WPA/WPA2 group cipher
+	int	pairwise_cipher;	//WPA/WPA2/WEP pairwise cipher
+	int	is_8021x;
+
+	/* bwmode 20/40 and ch_offset UP/LOW */
+	unsigned short 	ht_cap_info;
+	unsigned char	ht_info_infos_0;
+} WLAN_BCN_INFO,*PWLAN_BCN_INFO;
+
+/* temporally add #pragma pack for structure alignment issue of
+*   WLAN_BSSID_EX and get_WLAN_BSSID_EX_sz()
+*/
+#ifdef RTW_PACK_STRUCT_USE_INCLUDES
+#  include "pack_begin.h"
+#endif
+RTW_PACK_STRUCT_BEGIN
+typedef struct _WLAN_BSSID_EX
+{
+  u32					Length;
+  NDIS_802_11_MAC_ADDRESS		MacAddress;
+ #ifdef CONFIG_P2P_NEW
+  u8					Reserved[1];		//[0]: IS beacon frame
+  u8					bP2pNetwork;
+ #else
+  u8					Reserved[2];		//[0]: IS beacon frame
+ #endif
+  NDIS_802_11_SSID			Ssid;
+  u32					Privacy;
+  NDIS_802_11_RSSI			Rssi;			//(in dBM,raw data ,get from PHY)
+  NDIS_802_11_NETWORK_TYPE		NetworkTypeInUse;
+  NDIS_802_11_CONFIGURATION		Configuration;
+  NDIS_802_11_NETWORK_INFRASTRUCTURE	InfrastructureMode;
+  NDIS_802_11_RATES_EX  		SupportedRates;
+  WLAN_PHY_INFO				PhyInfo;
+  u32  				IELength;
+  u8  				IEs[MAX_IE_SZ];		//(timestamp, beacon interval, and capability information)
+}
+RTW_PACK_STRUCT_STRUCT
+WLAN_BSSID_EX, *PWLAN_BSSID_EX;
+RTW_PACK_STRUCT_END
+#ifdef RTW_PACK_STRUCT_USE_INCLUDES
+#  include "pack_end.h"
+#endif
+
+
+__inline  static uint get_WLAN_BSSID_EX_sz(WLAN_BSSID_EX *bss)
+{
+#if 0
+	uint t_len;
+	
+	t_len = sizeof (u32) 
+		+ sizeof (NDIS_802_11_MAC_ADDRESS) 
+		+ 2 
+		+ sizeof (NDIS_802_11_SSID) 
+		+ sizeof (u32) 
+		+ sizeof (NDIS_802_11_RSSI) 
+		+ sizeof (NDIS_802_11_NETWORK_TYPE)
+		+ sizeof (NDIS_802_11_CONFIGURATION)
+		+ sizeof (NDIS_802_11_NETWORK_INFRASTRUCTURE)
+		+ sizeof (NDIS_802_11_RATES_EX)
+		//all new member add here
+		+ sizeof(WLAN_PHY_INFO)
+		//all new member add here
+		+ sizeof (u32)
+		+ bss->IELength;	
+	return t_len;
+#else
+	return (sizeof(WLAN_BSSID_EX) -MAX_IE_SZ + bss->IELength);
+#endif
+}
+
+struct	wlan_network {
+	_list	list;	
+	int	network_type;	//refer to ieee80211.h for WIRELESS_11A/B/G
+	int	fixed;			// set to fixed when not to be removed as site-surveying
+	unsigned long	last_scanned; //timestamp for the network
+	int	aid;			//will only be valid when a BSS is joinned.
+	int	join_res;
+	WLAN_BSSID_EX	network; //must be the last item
+	WLAN_BCN_INFO	BcnInfo;
+#ifdef PLATFORM_WINDOWS	
+	unsigned char  iebuf[MAX_IE_SZ];
+#endif
+
+};
+
+enum VRTL_CARRIER_SENSE
+{
+    DISABLE_VCS,	
+    ENABLE_VCS,	
+    AUTO_VCS
+};
+
+enum VCS_TYPE
+{
+    NONE_VCS,	
+    RTS_CTS,
+    CTS_TO_SELF 
+};
+
+
+
+
+#define PWR_CAM 0
+#define PWR_MINPS 1
+#define PWR_MAXPS 2
+#define PWR_UAPSD 3
+#define PWR_VOIP 4
+
+
+enum UAPSD_MAX_SP
+{
+	NO_LIMIT,
+       TWO_MSDU,
+       FOUR_MSDU,
+       SIX_MSDU
+};
+
+
+#define NUM_PRE_AUTH_KEY 16
+#define NUM_PMKID_CACHE NUM_PRE_AUTH_KEY
+
+/*
+* 	WPA2
+*/
+
+#ifndef PLATFORM_OS_CE
+typedef struct _PMKID_CANDIDATE {
+    NDIS_802_11_MAC_ADDRESS BSSID;
+    u32 Flags;
+} PMKID_CANDIDATE, *PPMKID_CANDIDATE;
+
+typedef struct _NDIS_802_11_PMKID_CANDIDATE_LIST
+{
+    u32 Version;       // Version of the structure
+    u32 NumCandidates; // No. of pmkid candidates
+    PMKID_CANDIDATE CandidateList[1];
+} NDIS_802_11_PMKID_CANDIDATE_LIST, *PNDIS_802_11_PMKID_CANDIDATE_LIST;
+
+
+typedef struct _NDIS_802_11_AUTHENTICATION_ENCRYPTION
+{
+	NDIS_802_11_AUTHENTICATION_MODE AuthModeSupported;
+	NDIS_802_11_ENCRYPTION_STATUS EncryptStatusSupported;
+	
+} NDIS_802_11_AUTHENTICATION_ENCRYPTION, *PNDIS_802_11_AUTHENTICATION_ENCRYPTION;
+
+typedef struct _NDIS_802_11_CAPABILITY 
+{
+	u32  Length;
+	u32  Version;
+	u32  NoOfPMKIDs;
+	u32  NoOfAuthEncryptPairsSupported;
+	NDIS_802_11_AUTHENTICATION_ENCRYPTION AuthenticationEncryptionSupported[1];
+	
+} NDIS_802_11_CAPABILITY, *PNDIS_802_11_CAPABILITY;
+#endif
+
+
+#endif //#ifndef WLAN_BSSDEF_H_
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_lib.h

@@ -245,7 +245,7 @@ extern u8 rtw_cancel_timer(_timer *ptimer);
 extern BOOL rltk_get_idx_bydev(struct net_device *dev);
 extern int rltk_wlan_init(int idx_wlan, rtw_mode_t mode); 
 extern void rltk_wlan_deinit(); 
-extern void rltk_wlan_start(int idx_wlan);
+extern int rltk_wlan_start(int idx_wlan);
 extern int rltk_wlan_check_isup(int idx);
 extern void rltk_wlan_tx_inc(int idx); 
 extern void rltk_wlan_tx_dec(int idx); 

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/HalPhyRf.h

@@ -0,0 +1,102 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+ #ifndef __HAL_PHY_RF_H__
+ #define __HAL_PHY_RF_H__
+ 
+typedef enum _SPUR_CAL_METHOD {
+	PLL_RESET,
+	AFE_PHASE_SEL
+} SPUR_CAL_METHOD;
+
+typedef enum _PWRTRACK_CONTROL_METHOD {
+	BBSWING,
+	TXAGC,
+	MIX_MODE
+} PWRTRACK_METHOD;
+
+typedef VOID 	(*FuncSetPwr)(PDM_ODM_T, PWRTRACK_METHOD, u1Byte, u1Byte);
+typedef VOID 	(*FuncIQK)(PDM_ODM_T, u1Byte, u1Byte, u1Byte);
+#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B)
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+typedef VOID 	(*FuncLCK)(PDM_ODM_T); 
+#else
+typedef VOID 	(*FuncLCK)(PADAPTER); 
+#endif
+#else
+typedef VOID 	(*FuncLCK)(PDM_ODM_T);
+#endif
+typedef VOID  	(*FuncSwing)(PDM_ODM_T, ps1Byte*, ps1Byte*, ps1Byte*, ps1Byte*);
+typedef VOID	(*FuncSwingXtal)(PDM_ODM_T, ps1Byte*, ps1Byte*);
+typedef VOID 	(*FuncSetXtal)(PDM_ODM_T);
+
+
+typedef struct _TXPWRTRACK_CFG {
+	u1Byte 		SwingTableSize_CCK;	
+	u1Byte 		SwingTableSize_OFDM;
+	u1Byte 		Threshold_IQK;	
+	u1Byte 		AverageThermalNum;
+	u1Byte 		RfPathCount;
+	u4Byte 		ThermalRegAddr;	
+	FuncSetPwr 	ODM_TxPwrTrackSetPwr;
+	FuncIQK 	DoIQK;
+	FuncLCK		PHY_LCCalibrate;
+	FuncSwing	GetDeltaSwingTable;
+	FuncSwingXtal		GetDeltaSwingXtalTable;
+	FuncSetXtal		ODM_TxXtalTrackSetXtal;
+} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG;
+
+void ConfigureTxpowerTrack(
+	IN 	PDM_ODM_T		pDM_Odm,
+	OUT	PTXPWRTRACK_CFG	pConfig
+	);
+
+
+VOID
+ODM_ClearTxPowerTrackingState(
+	IN PDM_ODM_T		pDM_Odm
+	);
+
+VOID
+ODM_TXPowerTrackingCallback_ThermalMeter(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	IN PDM_ODM_T		pDM_Odm
+#else
+	IN PADAPTER	Adapter
+#endif
+	);
+
+
+
+#define ODM_TARGET_CHNL_NUM_2G_5G	59
+
+
+VOID
+ODM_ResetIQKResult(
+	IN PDM_ODM_T	pDM_Odm 
+);
+u1Byte 
+ODM_GetRightChnlPlaceforIQK(
+    IN u1Byte chnl
+);
+
+								
+#endif	// #ifndef __HAL_PHY_RF_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/PhyDM_Adaptivity.h

@@ -0,0 +1,162 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__PHYDMADAPTIVITY_H__
+#define    __PHYDMADAPTIVITY_H__
+
+#define ADAPTIVITY_VERSION	"8.4"
+
+#define PwdBUpperBound	7
+#define DFIRloss	5
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+typedef enum _tag_PhyDM_REGULATION_Type {
+	REGULATION_FCC = 0,
+	REGULATION_MKK = 1,
+	REGULATION_ETSI = 2,
+	REGULATION_WW = 3,	
+	
+	MAX_REGULATION_NUM = 4
+} PhyDM_REGULATION_TYPE;
+#endif
+
+
+typedef enum tag_PhyDM_TRx_MUX_Type
+{
+	PhyDM_SHUTDOWN			= 0,
+	PhyDM_STANDBY_MODE		= 1,
+	PhyDM_TX_MODE			= 2,
+	PhyDM_RX_MODE			= 3
+}PhyDM_Trx_MUX_Type;
+
+typedef enum tag_PhyDM_MACEDCCA_Type
+{
+	PhyDM_IGNORE_EDCCA			= 0,
+	PhyDM_DONT_IGNORE_EDCCA	= 1
+}PhyDM_MACEDCCA_Type;
+
+typedef struct _ADAPTIVITY_STATISTICS {
+	s1Byte			TH_L2H_ini_mode2;
+	s1Byte			TH_EDCCA_HL_diff_mode2;
+	s1Byte			TH_EDCCA_HL_diff_backup;
+	s1Byte			IGI_Base;
+	u1Byte			IGI_target;
+	u1Byte			NHMWait;
+	s1Byte			H2L_lb;
+	s1Byte			L2H_lb;
+	BOOLEAN			bFirstLink;
+	BOOLEAN			bCheck;
+	BOOLEAN			DynamicLinkAdaptivity;
+	u1Byte			APNumTH;
+	u1Byte			AdajustIGILevel;
+    BOOLEAN			bStopEDCCA;
+} ADAPTIVITY_STATISTICS, *PADAPTIVITY_STATISTICS;
+
+VOID
+Phydm_CheckAdaptivity(
+	IN		PVOID			pDM_VOID
+	);
+
+VOID
+Phydm_CheckEnvironment(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID
+Phydm_NHMCounterStatisticsInit(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID
+Phydm_NHMCounterStatistics(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID
+Phydm_NHMCounterStatisticsReset(
+	IN		PVOID			pDM_VOID
+);
+
+VOID
+Phydm_GetNHMCounterStatistics(
+	IN		PVOID			pDM_VOID
+);
+
+VOID
+Phydm_MACEDCCAState(
+	IN	PVOID					pDM_VOID,
+	IN	PhyDM_MACEDCCA_Type		State
+);
+
+VOID
+Phydm_SetEDCCAThreshold(
+	IN		PVOID		pDM_VOID,
+	IN		s1Byte		H2L,
+	IN		s1Byte		L2H
+);
+
+VOID
+Phydm_SetTRxMux(
+	IN		PVOID			pDM_VOID,
+	IN		PhyDM_Trx_MUX_Type			txMode,
+	IN		PhyDM_Trx_MUX_Type			rxMode
+);	
+
+BOOLEAN
+Phydm_CalNHMcnt(
+	IN		PVOID		pDM_VOID
+);
+
+VOID
+Phydm_SearchPwdBLowerBound(
+	IN		PVOID					pDM_VOID
+);
+
+VOID 
+Phydm_AdaptivityInit(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID
+Phydm_Adaptivity(
+	IN		PVOID					pDM_VOID,
+	IN		u1Byte					IGI
+	);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+VOID
+Phydm_DisableEDCCA(
+	IN		PVOID					pDM_VOID
+);
+
+VOID
+Phydm_DynamicEDCCA(
+	IN		PVOID					pDM_VOID
+);
+
+VOID
+Phydm_AdaptivityBSOD(
+	IN		PVOID					pDM_VOID
+);
+
+#endif
+
+
+#endif

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/mp_precomp.h

@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+//#include <Precomp.h>
+//#include "phydm_precomp.h"
+//#include "../phydm_precomp.h"
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_ACS.h

@@ -0,0 +1,97 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__PHYDMACS_H__
+#define    __PHYDMACS_H__
+
+#include "phydm_types.h"
+
+#define ACS_VERSION	"1.1"	/*20150729 by YuChen*/
+#define CLM_VERSION "1.0"
+
+#define ODM_MAX_CHANNEL_2G			14
+#define ODM_MAX_CHANNEL_5G			24
+
+// For phydm_AutoChannelSelectSettingAP()
+#define STORE_DEFAULT_NHM_SETTING               0
+#define RESTORE_DEFAULT_NHM_SETTING             1
+#define ACS_NHM_SETTING                         2
+
+#define	ODM_REG_CLM_TIME_PERIOD_11AC	0x990
+#define	ODM_REG_CLM_TIME_PERIOD_11N	    0x894
+#define	ODM_REG_CLM_RESULT_11AC			0xfa4
+#define	ODM_REG_CLM_RESULT_11N			0x8d0
+#define	ODM_REG_CLM_11AC			    0x994
+#define	ODM_REG_CLM_11N					0x890
+#define	ODM_REG_CLM_READY_11N			0x8b4
+
+typedef struct _ACS_
+{
+	BOOLEAN		bForceACSResult;
+	u1Byte		CleanChannel_2G;
+	u1Byte		CleanChannel_5G;
+	u2Byte		Channel_Info_2G[2][ODM_MAX_CHANNEL_2G];		//Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times
+	u2Byte		Channel_Info_5G[2][ODM_MAX_CHANNEL_5G];	
+
+#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )    
+    u1Byte              ACS_Step;
+    // NHM Count 0-11
+    u1Byte              NHM_Cnt[14][11];
+
+    // AC-Series, for storing previous setting
+    u4Byte              Reg0x990; 
+    u4Byte              Reg0x994;
+    u4Byte              Reg0x998;
+    u4Byte              Reg0x99C;
+    u1Byte              Reg0x9A0;   // u1Byte
+
+    // N-Series, for storing previous setting
+    u4Byte              Reg0x890; 
+    u4Byte              Reg0x894;
+    u4Byte              Reg0x898;
+    u4Byte              Reg0x89C;
+    u1Byte              Reg0xE28;   // u1Byte
+#endif
+
+}ACS, *PACS;
+
+VOID
+phydm_CLMInit(
+	IN		PVOID			pDM_VOID,
+	IN		u2Byte			sampleNum
+);
+
+VOID
+phydm_CLMtrigger(
+	IN		PVOID			pDM_VOID
+);
+
+BOOLEAN
+phydm_checkCLMready(
+	IN		PVOID			pDM_VOID
+);
+
+u2Byte
+phydm_getCLMresult(
+	IN		PVOID			pDM_VOID
+);
+
+
+#endif  //#ifndef	__PHYDMACS_H__

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_AntDect.h

@@ -0,0 +1,76 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__PHYDMANTDECT_H__
+#define    __PHYDMANTDECT_H__
+
+#define ANTDECT_VERSION	"1.0"
+
+#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))
+//1 [1. Single Tone Method] ===================================================
+
+
+
+VOID
+ODM_SingleDualAntennaDefaultSetting(
+	IN		PDM_ODM_T		pDM_Odm
+	);
+
+BOOLEAN
+ODM_SingleDualAntennaDetection(
+	IN		PDM_ODM_T		pDM_Odm,
+	IN		u1Byte			mode
+	);
+
+//1 [2. Scan AP RSSI Method] ==================================================
+
+VOID
+odm_SwAntDetectInit(
+	IN 		PDM_ODM_T 		pDM_Odm
+	);
+
+
+#define SwAntDivCheckBeforeLink	ODM_SwAntDivCheckBeforeLink
+
+BOOLEAN 
+ODM_SwAntDivCheckBeforeLink(
+	IN		PDM_ODM_T		pDM_Odm
+	);
+
+
+
+
+//1 [3. PSD Method] ==========================================================
+
+
+VOID
+ODM_SingleDualAntennaDetection_PSD(
+	IN	 PDM_ODM_T 	pDM_Odm
+);
+
+
+
+
+
+
+#endif
+#endif
+
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_AntDiv.h

@@ -0,0 +1,144 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__PHYDMANTDIV_H__
+#define    __PHYDMANTDIV_H__
+
+#define ANTDIV_VERSION	"1.0"
+
+#define ANT1_2G 0 // = ANT2_5G
+#define ANT2_2G 1 // = ANT1_5G
+
+//Antenna Diversty Control Type
+#define	ODM_AUTO_ANT	0
+#define	ODM_FIX_MAIN_ANT	1
+#define	ODM_FIX_AUX_ANT	2
+
+#define	TX_BY_REG	0
+
+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
+#define ODM_RTL8881A 0   //Just for windows driver to jointly use ODM-driver
+#endif
+
+#define ODM_ANTDIV_SUPPORT		(ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
+#define ODM_N_ANTDIV_SUPPORT		(ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)
+#define ODM_AC_ANTDIV_SUPPORT		(ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
+#define ODM_SMART_ANT_SUPPORT		(ODM_RTL8188E|ODM_RTL8192E)
+
+#define ODM_ANTDIV_2G_SUPPORT_IC			(ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A)
+#define ODM_ANTDIV_5G_SUPPORT_IC			(ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
+#define ODM_ANTDIV_2G	BIT0
+#define ODM_ANTDIV_5G	BIT1
+
+#define ANTDIV_ON 1
+#define ANTDIV_OFF 0
+
+#define SwAntDivRestAfterLink	ODM_SwAntDivRestAfterLink
+VOID ODM_SwAntDivRestAfterLink(	IN	PDM_ODM_T	pDM_Odm);
+
+VOID
+odm_AntennaDiversityReset(
+	IN		PDM_ODM_T		pDM_Odm 
+);
+
+VOID
+ODM_AntDivInit(
+	IN		 PDM_ODM_T		pDM_Odm 
+);
+
+VOID
+ODM_AntDiv(
+	IN		PDM_ODM_T		pDM_Odm
+);
+
+#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
+
+VOID
+ODM_UpdateRxIdleAnt(
+	IN	 	PDM_ODM_T 		pDM_Odm, 
+	IN		 u1Byte			Ant
+);
+
+#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+VOID
+ODM_SW_AntDiv_Callback(
+	IN 	PRT_TIMER			pTimer
+);
+
+VOID
+ODM_SW_AntDiv_WorkitemCallback(
+    	IN 	PVOID            pContext
+);
+#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+VOID
+ODM_SW_AntDiv_Callback(void *FunctionContext);
+#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#endif
+
+#if(RTL8188E_SUPPORT == 1  || RTL8192E_SUPPORT == 1)
+#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
+VOID
+odm_FastAntTraining(
+	IN		PDM_ODM_T		pDM_Odm
+);
+
+VOID
+odm_FastAntTrainingCallback(
+	IN		PDM_ODM_T		pDM_Odm
+);
+
+VOID
+odm_FastAntTrainingWorkItemCallback(
+	IN		PDM_ODM_T		pDM_Odm
+);
+#endif
+#endif
+
+VOID
+ODM_Process_RSSIForAntDiv(	
+	IN OUT	PDM_ODM_T					pDM_Odm,
+	IN		PODM_PHY_INFO_T				pPhyInfo,
+	IN		PODM_PACKET_INFO_T			pPktinfo
+);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
+VOID
+ODM_SetTxAntByTxInfo(
+	IN		PDM_ODM_T		pDM_Odm,
+	IN		pu1Byte			pDesc,
+	IN		u1Byte			macId	
+);
+
+#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
+VOID
+ODM_SetTxAntByTxInfo(
+	//IN		PDM_ODM_T		pDM_Odm,
+	struct	rtl8192cd_priv		*priv,
+	struct 	tx_desc			*pdesc,
+	struct	tx_insn			*txcfg,
+	unsigned short			aid	
+);
+
+#endif
+
+#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
+#endif //#ifndef	__ODMANTDIV_H__

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_CfoTracking.h

@@ -0,0 +1,73 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef	__PHYDMCFOTRACK_H__
+#define    __PHYDMCFOTRACK_H__
+
+#define CFO_TRACKING_VERSION	"1.0"
+
+//#define		CFO_TH_XTAL_HIGH			20			// kHz
+//#define		CFO_TH_XTAL_LOW			10			// kHz
+//#define		CFO_TH_ATC					80			// kHz
+
+#if ((RTL8195A_SUPPORT==0) && (RTL8711B_SUPPORT == 0))
+typedef struct _CFO_TRACKING_
+{
+	BOOLEAN			bATCStatus;
+	BOOLEAN			largeCFOHit;
+	BOOLEAN			bAdjust;
+	u1Byte			CrystalCap;
+	u1Byte			DefXCap;
+	int				CFO_tail[2];
+	int				CFO_ave_pre;
+	u4Byte			packetCount;
+	u4Byte			packetCount_pre;
+	BOOLEAN			bForceXtalCap;
+	BOOLEAN			bReset;
+	u1Byte			CFO_TH_XTAL_HIGH;
+	u1Byte			CFO_TH_XTAL_LOW;
+	u1Byte			CFO_TH_ATC;
+}CFO_TRACKING, *PCFO_TRACKING;
+#endif
+
+VOID
+ODM_CfoTrackingReset(
+	IN		PVOID					pDM_VOID
+);
+
+VOID
+ODM_CfoTrackingInit(
+	IN		PVOID					pDM_VOID
+);
+
+VOID
+ODM_CfoTracking(
+	IN		PVOID					pDM_VOID
+);
+
+VOID
+ODM_ParsingCFO(
+	IN		PVOID					pDM_VOID,
+	IN		PVOID					pPktinfo_VOID,
+	IN     	s1Byte* 					pcfotail,
+	IN		u1Byte			            num_ss
+);
+
+#endif

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DIG.h

@@ -0,0 +1,476 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__ODMDIG_H__
+#define    __ODMDIG_H__
+
+typedef struct _Dynamic_Initial_Gain_Threshold_
+{
+	BOOLEAN		bStopDIG;		// for debug
+	BOOLEAN		bPauseDIG;
+	BOOLEAN		bIgnoreDIG;
+	BOOLEAN		bPSDInProgress;
+
+	u1Byte		Dig_Enable_Flag;
+	u1Byte		Dig_Ext_Port_Stage;
+	
+	int		   	RssiLowThresh;
+	int		    	RssiHighThresh;
+
+	u4Byte		FALowThresh;
+	u4Byte		FAHighThresh;
+
+	u1Byte		CurSTAConnectState;
+	u1Byte		PreSTAConnectState;
+	u1Byte		CurMultiSTAConnectState;
+
+	u1Byte		PreIGValue;
+	u1Byte		CurIGValue;
+	u1Byte		BackupIGValue;		//MP DIG
+	u1Byte		BT30_CurIGI;
+	u1Byte		IGIBackup;
+
+	s1Byte		BackoffVal;
+	s1Byte		BackoffVal_range_max;
+	s1Byte		BackoffVal_range_min;
+	u1Byte		rx_gain_range_max;
+	u1Byte		rx_gain_range_min;
+	u1Byte		Rssi_val_min;
+
+	u1Byte		PreCCK_CCAThres;
+	u1Byte		CurCCK_CCAThres;
+	u1Byte		PreCCKPDState;
+	u1Byte		CurCCKPDState;
+	u1Byte		CCKPDBackup;
+
+	u1Byte		LargeFAHit;
+	u1Byte		ForbiddenIGI;
+	u4Byte		Recover_cnt;
+
+	u1Byte		DIG_Dynamic_MIN_0;
+	u1Byte		DIG_Dynamic_MIN_1;
+	BOOLEAN		bMediaConnect_0;
+	BOOLEAN		bMediaConnect_1;
+
+	u4Byte		AntDiv_RSSI_max;
+	u4Byte		RSSI_max;
+
+	u1Byte		*pbP2pLinkInProgress;
+    u4Byte		cckFaMa;
+
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+	BOOLEAN		bTpTarget;
+	BOOLEAN		bNoiseEst;
+	u4Byte		TpTrainTH_min;
+	u1Byte		IGIOffset_A;
+	u1Byte		IGIOffset_B;
+#endif
+}DIG_T,*pDIG_T;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP|ODM_ADSL))
+typedef struct _FALSE_ALARM_STATISTICS{
+	u4Byte	Cnt_Parity_Fail;
+	u4Byte	Cnt_Rate_Illegal;
+	u4Byte	Cnt_Crc8_fail;
+	u4Byte	Cnt_Mcs_fail;
+	u4Byte	Cnt_Ofdm_fail;
+	u4Byte	Cnt_Ofdm_fail_pre;	//For RTL8881A
+	u4Byte	Cnt_Cck_fail;
+	u4Byte	Cnt_all;
+	u4Byte	Cnt_Fast_Fsync;
+	u4Byte	Cnt_SB_Search_fail;
+	u4Byte	Cnt_OFDM_CCA;
+	u4Byte	Cnt_CCK_CCA;
+	u4Byte	Cnt_CCA_all;
+	u4Byte	Cnt_BW_USC;	//Gary
+	u4Byte	Cnt_BW_LSC;	//Gary
+}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
+#endif
+
+typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
+{
+	DIG_TYPE_THRESH_HIGH	= 0,
+	DIG_TYPE_THRESH_LOW	= 1,
+	DIG_TYPE_BACKOFF		= 2,
+	DIG_TYPE_RX_GAIN_MIN	= 3,
+	DIG_TYPE_RX_GAIN_MAX	= 4,
+	DIG_TYPE_ENABLE 		= 5,
+	DIG_TYPE_DISABLE 		= 6,	
+	DIG_OP_TYPE_MAX
+}DM_DIG_OP_E;
+
+typedef enum tag_ODM_PauseDIG_Type {
+	ODM_PAUSE_DIG    		= 	BIT0,
+	ODM_RESUME_DIG  		= 	BIT1
+} ODM_Pause_DIG_TYPE;
+
+typedef enum tag_ODM_PauseCCKPD_Type {
+	ODM_PAUSE_CCKPD    	= 	BIT0,
+	ODM_RESUME_CCKPD  	= 	BIT1
+} ODM_Pause_CCKPD_TYPE;
+
+typedef enum tag_ODM_TRx_MUX_Type
+{
+	ODM_SHUTDOWN			= 0,
+	ODM_STANDBY_MODE		= 1,
+	ODM_TX_MODE			= 2,
+	ODM_RX_MODE			= 3
+}ODM_Trx_MUX_Type;
+
+typedef enum tag_ODM_MACEDCCA_Type
+{
+	ODM_IGNORE_EDCCA			= 0,
+	ODM_DONT_IGNORE_EDCCA	= 1
+}ODM_MACEDCCA_Type;
+
+/*
+typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition
+{
+	CCK_PD_STAGE_LowRssi = 0,
+	CCK_PD_STAGE_HighRssi = 1,
+	CCK_PD_STAGE_MAX = 3,
+}DM_CCK_PDTH_E;
+
+typedef enum tag_DIG_EXT_PORT_ALGO_Definition
+{
+	DIG_EXT_PORT_STAGE_0 = 0,
+	DIG_EXT_PORT_STAGE_1 = 1,
+	DIG_EXT_PORT_STAGE_2 = 2,
+	DIG_EXT_PORT_STAGE_3 = 3,
+	DIG_EXT_PORT_STAGE_MAX = 4,
+}DM_DIG_EXT_PORT_ALG_E;
+
+typedef enum tag_DIG_Connect_Definition
+{
+	DIG_STA_DISCONNECT = 0,	
+	DIG_STA_CONNECT = 1,
+	DIG_STA_BEFORE_CONNECT = 2,
+	DIG_MultiSTA_DISCONNECT = 3,
+	DIG_MultiSTA_CONNECT = 4,
+	DIG_CONNECT_MAX
+}DM_DIG_CONNECT_E;
+
+
+#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
+
+#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER)	\
+	DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT)
+
+#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER)	\
+	DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT)
+*/
+#define		DM_DIG_THRESH_HIGH			40
+#define		DM_DIG_THRESH_LOW			35
+
+#define		DM_FALSEALARM_THRESH_LOW	400
+#define		DM_FALSEALARM_THRESH_HIGH	1000
+
+#define		DM_DIG_MAX_NIC				0x3e
+#define		DM_DIG_MIN_NIC				0x20 //0x1e
+#define		DM_DIG_MAX_OF_MIN_NIC		0x3e
+
+#define		DM_DIG_MAX_AP					0x3e
+#define		DM_DIG_MIN_AP					0x1c
+#define		DM_DIG_MAX_OF_MIN			0x2A	//0x32
+#define		DM_DIG_MIN_AP_DFS				0x20
+
+#define		DM_DIG_MAX_NIC_HP			0x46
+#define		DM_DIG_MIN_NIC_HP				0x2e
+
+#define		DM_DIG_MAX_AP_HP				0x42
+#define		DM_DIG_MIN_AP_HP				0x30
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+#define		DM_DIG_MAX_AP_COVERAGR		0x26
+#define		DM_DIG_MIN_AP_COVERAGE		0x1c
+#define		DM_DIG_MAX_OF_MIN_COVERAGE	0x22
+
+#define		DM_DIG_TP_Target_TH0			500
+#define		DM_DIG_TP_Target_TH1			1000
+#define		DM_DIG_TP_Training_Period		10
+#endif
+
+//vivi 92c&92d has different definition, 20110504
+//this is for 92c
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_IOT))
+	#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
+	#define		DM_DIG_FA_TH0				0x80//0x20
+	#else
+	#define		DM_DIG_FA_TH0				0x200//0x20
+	#endif
+#else
+	#define		DM_DIG_FA_TH0				0x200//0x20
+#endif
+
+#define		DM_DIG_FA_TH1					0x300
+#define		DM_DIG_FA_TH2					0x400
+//this is for 92d
+#define		DM_DIG_FA_TH0_92D				0x100
+#define		DM_DIG_FA_TH1_92D				0x400
+#define		DM_DIG_FA_TH2_92D				0x600
+
+#define		DM_DIG_BACKOFF_MAX			12
+#define		DM_DIG_BACKOFF_MIN			-4
+#define		DM_DIG_BACKOFF_DEFAULT		10
+
+#define 		DM_DIG_FA_TH0_LPS				4 //-> 4 in lps
+#define 		DM_DIG_FA_TH1_LPS				15 //-> 15 lps
+#define 		DM_DIG_FA_TH2_LPS				30 //-> 30 lps
+#define 		RSSI_OFFSET_DIG				0x05
+
+
+VOID
+odm_CheckAdaptivity(
+	IN		PVOID			pDM_VOID
+	);
+
+VOID
+odm_CheckEnvironment(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID
+ODM_ChangeDynamicInitGainThresh(
+	IN		PVOID					pDM_VOID,
+	IN		u4Byte  					DM_Type,
+	IN		u4Byte 					DM_Value
+	);
+
+VOID
+odm_NHMCounterStatisticsInit(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID
+odm_NHMCounterStatistics(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID
+odm_NHMBBInit(
+	IN		PVOID					pDM_VOID
+);
+
+VOID
+odm_NHMBB(
+	IN		PVOID					pDM_VOID
+);
+
+VOID
+odm_NHMCounterStatisticsReset(
+	IN		PVOID			pDM_VOID
+);
+
+VOID
+odm_GetNHMCounterStatistics(
+	IN		PVOID			pDM_VOID
+);
+
+VOID
+odm_MACEDCCAState(
+	IN		PVOID					pDM_VOID,
+	IN	ODM_MACEDCCA_Type		State
+);
+
+VOID 
+odm_SetEDCCAThreshold(
+	IN		PVOID		pDM_VOID,
+	IN		s1Byte		H2L,
+	IN		s1Byte		L2H
+);
+
+VOID
+odm_SetTRxMux(
+	IN		PVOID			pDM_VOID,
+	IN		ODM_Trx_MUX_Type			txMode,
+	IN		ODM_Trx_MUX_Type			rxMode
+);	
+
+BOOLEAN
+odm_CalNHMcnt(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID
+odm_SearchPwdBLowerBound(
+	IN		PVOID					pDM_VOID
+);
+
+VOID 
+odm_AdaptivityInit(
+	IN		PVOID					pDM_VOID
+	);
+
+BOOLEAN
+odm_Adaptivity(
+	IN		PVOID					pDM_VOID,
+	IN		u1Byte					IGI
+	);
+
+VOID
+ODM_Write_DIG(
+	IN		PVOID					pDM_VOID, 	
+	IN		u1Byte					CurrentIGI
+	);
+
+VOID
+odm_PauseDIG(
+	IN		PVOID					pDM_VOID,
+	IN		ODM_Pause_DIG_TYPE		PauseType,
+	IN		u1Byte					IGIValue
+	);
+
+VOID
+odm_DIGInit(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID	
+odm_DIG(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID
+odm_DIGbyRSSI_LPS(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID
+odm_DigForBtHsMode(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID 
+odm_FalseAlarmCounterStatistics(
+	IN		PVOID					pDM_VOID
+	);
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_IOT)
+VOID
+odm_FAThresholdCheck(
+	IN		PVOID					pDM_VOID,
+	OUT		u4Byte*					dm_FA_thres
+	);
+#else
+VOID
+odm_FAThresholdCheck(
+	IN		PVOID					pDM_VOID,
+	IN		BOOLEAN					bDFSBand,
+	IN		BOOLEAN					bPerformance,
+	IN		u4Byte					RxTp,
+	IN		u4Byte					TxTp,
+	OUT		u4Byte*					dm_FA_thres
+	);
+#endif
+u1Byte
+odm_ForbiddenIGICheck(
+	IN		PVOID					pDM_VOID,
+	IN		u1Byte					DIG_Dynamic_MIN,
+	IN		u1Byte					CurrentIGI
+	);
+
+VOID
+odm_InbandNoiseCalculate (	
+	IN		PVOID					pDM_VOID
+	);
+
+BOOLEAN 
+odm_DigAbort(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID
+odm_PauseCCKPacketDetection(
+	IN		PVOID					pDM_VOID,
+	IN		ODM_Pause_CCKPD_TYPE	PauseType,
+	IN		u1Byte					CCKPDThreshold
+	);
+
+VOID 
+odm_CCKPacketDetectionThresh(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID 
+ODM_Write_CCK_CCA_Thres(
+	IN		PVOID					pDM_VOID, 
+	IN		u1Byte					CurCCK_CCAThres
+	);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+VOID
+odm_DisableEDCCA(
+	IN		PVOID					pDM_VOID
+);
+
+VOID
+odm_DynamicEDCCA(
+	IN		PVOID					pDM_VOID
+);
+
+VOID
+odm_MPT_DIGCallback(
+	PRT_TIMER						pTimer
+);
+
+VOID
+odm_MPT_DIGWorkItemCallback(
+    IN 		PVOID            			pContext
+    );
+
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+VOID
+odm_MPT_DIGCallback(
+	IN		PVOID					pDM_VOID
+);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL))
+VOID
+ODM_MPT_DIG(
+	IN		PVOID					pDM_VOID
+);
+#endif
+
+
+#endif
+
+VOID
+odm_DIGInit_8195A(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID	
+odm_DIG_8195A(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID 
+odm_FalseAlarmCounterStatistics_8195A(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID 
+odm_CCKPacketDetectionThresh_8195A(
+	IN		PVOID					pDM_VOID
+	);

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DynamicBBPowerSaving.h

@@ -0,0 +1,63 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__PHYDMDYNAMICBBPOWERSAVING_H__
+#define    __PHYDMDYNAMICBBPOWERSAVING_H__
+
+#define DYNAMIC_BBPWRSAV_VERSION	"1.0"
+
+typedef struct _Dynamic_Power_Saving_
+{
+	u1Byte		PreCCAState;
+	u1Byte		CurCCAState;
+
+	u1Byte		PreRFState;
+	u1Byte		CurRFState;
+
+	int		    Rssi_val_min;
+	
+	u1Byte		initialize;
+	u4Byte		Reg874,RegC70,Reg85C,RegA74;
+	
+}PS_T,*pPS_T;
+
+#define dm_RF_Saving	ODM_RF_Saving
+
+void ODM_RF_Saving(
+	IN		PVOID					pDM_VOID,
+	IN	u1Byte		bForceInNormal 
+	);
+
+VOID 
+odm_DynamicBBPowerSavingInit(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID 
+odm_DynamicBBPowerSaving(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID
+odm_1R_CCA(
+	IN		PVOID					pDM_VOID
+	);
+
+#endif

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DynamicTxPower.h

@@ -0,0 +1,89 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__PHYDMDYNAMICTXPOWER_H__
+#define    __PHYDMDYNAMICTXPOWER_H__
+
+#define DYNAMIC_TXPWR_VERSION	"1.0"
+
+#define		TX_POWER_NEAR_FIELD_THRESH_LVL2	74
+#define		TX_POWER_NEAR_FIELD_THRESH_LVL1	67
+#define		TX_POWER_NEAR_FIELD_THRESH_AP		0x3F
+#define		TX_POWER_NEAR_FIELD_THRESH_8812	60
+
+#define		TxHighPwrLevel_Normal		0	
+#define		TxHighPwrLevel_Level1		1
+#define		TxHighPwrLevel_Level2		2
+#define		TxHighPwrLevel_BT1			3
+#define		TxHighPwrLevel_BT2			4
+#define		TxHighPwrLevel_15			5
+#define		TxHighPwrLevel_35			6
+#define		TxHighPwrLevel_50			7
+#define		TxHighPwrLevel_70			8
+#define		TxHighPwrLevel_100			9
+
+VOID 
+odm_DynamicTxPowerInit(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID
+odm_DynamicTxPowerRestorePowerIndex(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID 
+odm_DynamicTxPowerNIC(
+	IN		PVOID					pDM_VOID
+	);
+
+#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
+VOID
+odm_DynamicTxPowerSavePowerIndex(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID
+odm_DynamicTxPowerWritePowerIndex(
+	IN		PVOID					pDM_VOID, 
+	IN 	u1Byte		Value);
+
+VOID 
+odm_DynamicTxPower_92C(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID 
+odm_DynamicTxPower_92D(
+	IN		PVOID					pDM_VOID
+	);
+#endif
+
+VOID 
+odm_DynamicTxPower(
+	IN		PVOID					pDM_VOID
+	);
+
+VOID 
+odm_DynamicTxPowerAP(
+	IN		PVOID					pDM_VOID
+	);
+
+#endif

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_EdcaTurboCheck.h

@@ -0,0 +1,152 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__PHYDMEDCATURBOCHECK_H__
+#define    __PHYDMEDCATURBOCHECK_H__
+
+#define EDCATURBO_VERSION	"1.0"
+
+typedef struct _EDCA_TURBO_
+{
+	BOOLEAN bCurrentTurboEDCA;
+	BOOLEAN bIsCurRDLState;
+
+	#if(DM_ODM_SUPPORT_TYPE == ODM_CE	)
+	u4Byte	prv_traffic_idx; // edca turbo
+	#endif
+
+}EDCA_T,*pEDCA_T;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
+static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] = 
+// UNKNOWN		REALTEK_90	REALTEK_92SE	BROADCOM		RALINK		ATHEROS		CISCO		MERU        MARVELL	92U_AP		SELF_AP(DownLink/Tx)
+{ 0x5e4322, 		0xa44f, 		0x5e4322,		0x5ea32b,  		0x5ea422, 	0x5ea322,	0x3ea430,	0x5ea42b, 0x5ea44f,	0x5e4322,	0x5e4322};
+
+
+static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] = 
+// UNKNOWN		REALTEK_90	REALTEK_92SE	BROADCOM		RALINK		ATHEROS		CISCO		MERU,       MARVELL	92U_AP		SELF_AP(UpLink/Rx)
+{ 0xa44f, 		0x5ea44f, 	0x5e4322, 		0x5ea42b, 		0xa44f, 		0xa630, 		0x5ea630,	0x5ea42b, 0xa44f,		0xa42b,		0xa42b};
+
+static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] = 
+// UNKNOWN		REALTEK_90	REALTEK_92SE	BROADCOM		RALINK		ATHEROS		CISCO		MERU,       MARVELL	92U_AP		SELF_AP
+{ 0x4322, 		0xa44f, 		0x5e4322,		0xa42b, 			0x5e4322, 	0x4322, 		0xa42b,		0x5ea42b, 0xa44f,		0x5e4322,	0x5ea42b};
+
+
+//============================================================
+// EDCA Paramter for AP/ADSL   by Mingzhi 2011-11-22
+//============================================================
+#elif (DM_ODM_SUPPORT_TYPE &ODM_ADSL)
+enum qos_prio { BK, BE, VI, VO, VI_AG, VO_AG };
+
+static const struct ParaRecord rtl_ap_EDCA[] =
+{
+//ACM,AIFSN, ECWmin, ECWmax, TXOplimit
+     {0,     7,      4,      10,     0},            //BK
+     {0,     3,      4,      6,      0},             //BE
+     {0,     1,      3,      4,      188},         //VI
+     {0,     1,      2,      3,      102},         //VO
+     {0,     1,      3,      4,      94},          //VI_AG
+     {0,     1,      2,      3,      47},          //VO_AG
+};
+
+static const struct ParaRecord rtl_sta_EDCA[] =
+{
+//ACM,AIFSN, ECWmin, ECWmax, TXOplimit
+     {0,     7,      4,      10,     0},
+     {0,     3,      4,      10,     0},
+     {0,     2,      3,      4,      188},
+     {0,     2,      2,      3,      102},
+     {0,     2,      3,      4,      94},
+     {0,     2,      2,      3,      47},
+};
+#endif
+
+
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+#ifdef WIFI_WMM
+VOID
+ODM_IotEdcaSwitch(
+	IN		PVOID					pDM_VOID,
+	IN	unsigned char		enable
+	);
+#endif
+
+BOOLEAN
+ODM_ChooseIotMainSTA(
+	IN		PVOID					pDM_VOID,
+	IN	PSTA_INFO_T		pstat
+	);
+#endif
+
+VOID
+odm_EdcaTurboCheck(
+	IN 	PVOID	 	pDM_VOID
+	);
+VOID
+ODM_EdcaTurboInit(
+	IN 	PVOID	 	pDM_VOID
+);
+
+#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
+VOID
+odm_EdcaTurboCheckMP(
+	IN 	PVOID	 	pDM_VOID
+	);
+
+//check if edca turbo is disabled
+BOOLEAN
+odm_IsEdcaTurboDisable(
+	IN 	PVOID	 	pDM_VOID
+);
+//choose edca paramter for special IOT case
+VOID 
+ODM_EdcaParaSelByIot(
+	IN		PVOID					pDM_VOID,
+	OUT	u4Byte		*EDCA_BE_UL,
+	OUT u4Byte		*EDCA_BE_DL
+	);
+//check if it is UL or DL
+VOID
+odm_EdcaChooseTrafficIdx( 
+	IN 	PVOID	 	pDM_VOID,
+	IN	u8Byte  			cur_tx_bytes,  
+	IN	u8Byte  			cur_rx_bytes, 
+	IN	BOOLEAN 		bBiasOnRx,
+	OUT BOOLEAN 		*pbIsCurRDLState
+	);
+
+#elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
+VOID
+odm_EdcaTurboCheckCE(
+	IN 	PVOID	 	pDM_VOID
+	);
+#else
+VOID 
+odm_IotEngine(
+	IN 	PVOID	 	pDM_VOID
+	);
+
+VOID
+odm_EdcaParaInit(
+	IN 	PVOID	 	pDM_VOID
+	);
+#endif
+
+#endif

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_HWConfig.h

@@ -0,0 +1,508 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef	__HALHWOUTSRC_H__
+#define __HALHWOUTSRC_H__
+
+
+/*--------------------------Define -------------------------------------------*/ 
+//#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
+#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \
+                                                                              sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
+#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \
+                                                                              sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
+
+#define AGC_DIFF_CONFIG(ic, band) do {\
+                                            if (pDM_Odm->bIsMPChip)\
+                                    		    AGC_DIFF_CONFIG_MP(ic,band);\
+                                            else\
+                                                AGC_DIFF_CONFIG_TC(ic,band);\
+                                    } while(0)
+
+
+//============================================================
+// structure and define
+//============================================================
+
+typedef struct _Phy_Rx_AGC_Info
+{
+	#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)	
+		u1Byte	gain:7,trsw:1;			
+	#else			
+		u1Byte	trsw:1,gain:7;
+	#endif
+} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T;
+
+typedef struct _Phy_Status_Rpt_8192cd
+{
+	PHY_RX_AGC_INFO_T path_agc[2];
+	u1Byte 	ch_corr[2];									
+	u1Byte	cck_sig_qual_ofdm_pwdb_all;
+	u1Byte	cck_agc_rpt_ofdm_cfosho_a;
+	u1Byte	cck_rpt_b_ofdm_cfosho_b;
+	u1Byte 	rsvd_1;//ch_corr_msb;
+	u1Byte 	noise_power_db_msb;
+	s1Byte	path_cfotail[2];	
+	u1Byte	pcts_mask[2];	
+	s1Byte	stream_rxevm[2];	
+	u1Byte	path_rxsnr[2];
+	u1Byte 	noise_power_db_lsb;
+	u1Byte	rsvd_2[3];
+	u1Byte 	stream_csi[2];
+	u1Byte 	stream_target_csi[2];
+	s1Byte 	sig_evm;
+	u1Byte 	rsvd_3;	
+
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)	
+	u1Byte 	antsel_rx_keep_2:1;	//ex_intf_flg:1;
+	u1Byte 	sgi_en:1;
+	u1Byte 	rxsc:2;	
+	u1Byte 	idle_long:1;
+	u1Byte 	r_ant_train_en:1;
+	u1Byte 	ant_sel_b:1;
+	u1Byte 	ant_sel:1;	
+#else	// _BIG_ENDIAN_	
+	u1Byte 	ant_sel:1;	
+	u1Byte 	ant_sel_b:1;
+	u1Byte 	r_ant_train_en:1;
+	u1Byte 	idle_long:1;
+	u1Byte 	rxsc:2;
+	u1Byte 	sgi_en:1;
+	u1Byte 	antsel_rx_keep_2:1;	//ex_intf_flg:1;
+#endif
+} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
+
+
+typedef struct _Phy_Status_Rpt_8812
+{
+#if 0
+	PHY_RX_AGC_INFO_T path_agc[2];
+	u1Byte 	ch_num[2];									
+	u1Byte	cck_sig_qual_ofdm_pwdb_all;
+	u1Byte	cck_agc_rpt_ofdm_cfosho_a;
+	u1Byte	cck_bb_pwr_ofdm_cfosho_b;
+	u1Byte    cck_rx_path;	//CCK_RX_PATH [3:0] (with regA07[3:0] definition)	
+	u1Byte 	rsvd_1;	
+	u1Byte	path_cfotail[2];	
+	u1Byte	pcts_mask[2];	
+	s1Byte	stream_rxevm[2];	
+	u1Byte	path_rxsnr[2];
+	u1Byte	rsvd_2[2];	
+	u1Byte 	stream_snr[2];	
+	u1Byte 	stream_csi[2];
+	u1Byte	rsvd_3[2];
+	s1Byte 	sig_evm;
+	u1Byte 	rsvd_4;	
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)	
+	u1Byte 	antidx_anta:3;
+	u1Byte 	antidx_antb:3;
+	u1Byte 	rsvd_5:2;
+#else	// _BIG_ENDIAN_	
+	u1Byte 	rsvd_5:2;
+	u1Byte 	antidx_antb:3;
+	u1Byte 	antidx_anta:3;	
+#endif
+#endif
+
+	//2012.05.24 LukeLee: This structure should take big/little endian in consideration later.....
+	
+	//DWORD 0
+	u1Byte			gain_trsw[2];
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)	
+	u2Byte			chl_num:10;
+	u2Byte			sub_chnl:4;
+	u2Byte			r_RFMOD:2;
+#else	// _BIG_ENDIAN_	
+	u2Byte			r_RFMOD:2;
+	u2Byte			sub_chnl:4;
+	u2Byte			chl_num:10;
+#endif
+
+	//DWORD 1
+	u1Byte			pwdb_all;
+	u1Byte			cfosho[4];	// DW 1 byte 1 DW 2 byte 0
+
+	//DWORD 2
+	s1Byte			cfotail[4];	// DW 2 byte 1 DW 3 byte 0
+
+	//DWORD 3
+	s1Byte			rxevm[2];	// DW 3 byte 1 DW 3 byte 2
+	s1Byte			rxsnr[2];	// DW 3 byte 3 DW 4 byte 0
+
+	//DWORD 4
+	u1Byte			PCTS_MSK_RPT[2];	
+	u1Byte			pdsnr[2];	// DW 4 byte 3 DW 5 Byte 0
+
+	//DWORD 5
+	u1Byte			csi_current[2];
+	u1Byte			rx_gain_c;
+
+	//DWORD 6
+	u1Byte			rx_gain_d;
+	s1Byte			sigevm;
+	u1Byte			resvd_0;
+	u1Byte			antidx_anta:3;
+	u1Byte			antidx_antb:3;
+	u1Byte			resvd_1:2;
+} PHY_STATUS_RPT_8812_T,*PPHY_STATUS_RPT_8812_T;
+
+
+VOID
+odm_Init_RSSIForDM(
+	IN OUT	PDM_ODM_T	pDM_Odm
+	);
+
+VOID
+ODM_PhyStatusQuery(
+	IN OUT	PDM_ODM_T					pDM_Odm,
+	OUT		PODM_PHY_INFO_T			pPhyInfo,
+	IN 		pu1Byte						pPhyStatus,	
+	IN		PODM_PACKET_INFO_T			pPktinfo
+	);
+
+VOID
+ODM_MacStatusQuery(
+	IN OUT	PDM_ODM_T					pDM_Odm,
+	IN 		pu1Byte						pMacStatus,
+	IN		u1Byte						MacID,	
+	IN		BOOLEAN						bPacketMatchBSSID,
+	IN		BOOLEAN						bPacketToSelf,
+	IN		BOOLEAN						bPacketBeacon
+	);
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP|ODM_IOT))
+
+HAL_STATUS
+ODM_ConfigRFWithTxPwrTrackHeaderFile(
+	IN 	PDM_ODM_T	        	pDM_Odm
+    );
+    
+HAL_STATUS
+ODM_ConfigRFWithHeaderFile(
+	IN 	PDM_ODM_T	        	pDM_Odm,
+	IN 	ODM_RF_Config_Type 		ConfigType,
+	IN 	ODM_RF_RADIO_PATH_E 	eRFPath
+	);
+
+HAL_STATUS
+ODM_ConfigBBWithHeaderFile(
+	IN  	PDM_ODM_T	                pDM_Odm,
+	IN	ODM_BB_Config_Type		ConfigType
+    );
+
+HAL_STATUS
+ODM_ConfigMACWithHeaderFile(
+	IN  	PDM_ODM_T	pDM_Odm
+    );
+
+HAL_STATUS
+ODM_ConfigFWWithHeaderFile(
+	IN 	PDM_ODM_T			pDM_Odm,
+	IN 	ODM_FW_Config_Type 	ConfigType,
+	OUT u1Byte				*pFirmware,
+	OUT u4Byte				*pSize
+	);
+
+u4Byte 
+ODM_GetHWImgVersion(
+	IN	PDM_ODM_T	pDM_Odm
+	);
+
+s4Byte
+odm_SignalScaleMapping(	
+	IN OUT PDM_ODM_T pDM_Odm,
+	IN	s4Byte CurrSig 
+	);
+
+#endif
+
+#if(ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
+//For New RX PHY Status Report Format, include 8723D/8710B 
+VOID
+phydm_RxPhyStatusNewType(
+	IN		PDM_ODM_T					pPhydm,
+	IN		pu1Byte						pPhyStatus,
+	IN		PODM_PACKET_INFO_T			pPktinfo,
+	OUT		PODM_PHY_INFO_T			pPhyInfo
+);
+
+typedef struct _Phy_Status_Rpt_Jaguar2_Type0 {
+	/* DW0 */
+	u1Byte		page_num;
+	u1Byte		pwdb;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u1Byte		gain: 6;
+	u1Byte		rsvd_0: 1;
+	u1Byte		trsw: 1;
+#else
+	u1Byte		trsw: 1;
+	u1Byte		rsvd_0: 1;
+	u1Byte		gain: 6;
+#endif
+	u1Byte		rsvd_1;
+
+	/* DW1 */
+	u1Byte		rsvd_2;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u1Byte		rxsc: 4;
+	u1Byte		agc_table: 4;
+#else
+	u1Byte		agc_table: 4;
+	u1Byte		rxsc: 4;
+#endif
+	u1Byte		channel;
+	u1Byte		band;
+
+	/* DW2 */
+	u2Byte		length;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u1Byte		antidx_a: 3;
+	u1Byte		antidx_b: 3;
+	u1Byte		rsvd_3: 2;
+	u1Byte		antidx_c: 3;
+	u1Byte		antidx_d: 3;
+	u1Byte		rsvd_4:2;
+#else
+	u1Byte		rsvd_3: 2;
+	u1Byte		antidx_b: 3;
+	u1Byte		antidx_a: 3;
+	u1Byte		rsvd_4:2;
+	u1Byte		antidx_d: 3;
+	u1Byte		antidx_c: 3;
+#endif
+
+	/* DW3 */
+	u1Byte		signal_quality;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u1Byte		vga:5;
+	u1Byte		lna_l:3;
+	u1Byte		bb_power:6;
+	u1Byte		rsvd_9:1;
+	u1Byte		lna_h:1;
+#else
+	u1Byte		lna_l:3;
+	u1Byte		vga:5;
+	u1Byte		lna_h:1;
+	u1Byte		rsvd_9:1;
+	u1Byte		bb_power:6;
+#endif
+	u1Byte		rsvd_5;
+
+	/* DW4 */
+	u4Byte		rsvd_6;
+
+	/* DW5 */
+	u4Byte		rsvd_7;
+
+	/* DW6 */
+	u4Byte		rsvd_8;
+} PHY_STATUS_RPT_JAGUAR2_TYPE0, *PPHY_STATUS_RPT_JAGUAR2_TYPE0; //for CCK Format
+
+typedef struct _Phy_Status_Rpt_Jaguar2_Type1 {
+	/* DW0 and DW1 */
+	u1Byte		page_num;
+	u1Byte		pwdb[4];
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u1Byte		l_rxsc: 4;
+	u1Byte		ht_rxsc: 4;
+#else
+	u1Byte		ht_rxsc: 4;
+	u1Byte		l_rxsc: 4;
+#endif
+	u1Byte		channel;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u1Byte		band: 2;
+	u1Byte		rsvd_0: 1;
+	u1Byte		hw_antsw_occu: 1;
+	u1Byte		gnt_bt: 1;
+	u1Byte		ldpc: 1;
+	u1Byte		stbc: 1;
+	u1Byte		beamformed: 1;
+#else
+	u1Byte		beamformed: 1;
+	u1Byte		stbc: 1;
+	u1Byte		ldpc: 1;
+	u1Byte		gnt_bt: 1;
+	u1Byte		hw_antsw_occu: 1;
+	u1Byte		rsvd_0: 1;
+	u1Byte		band: 2;
+#endif
+
+	/* DW2 */
+	u2Byte		lsig_length;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u1Byte		antidx_a: 3;
+	u1Byte		antidx_b: 3;
+	u1Byte		rsvd_1: 2;
+	u1Byte		antidx_c: 3;
+	u1Byte		antidx_d: 3;
+	u1Byte		rsvd_2: 2;
+#else
+	u1Byte		rsvd_1: 2;
+	u1Byte		antidx_b: 3;
+	u1Byte		antidx_a: 3;
+	u1Byte		rsvd_2: 2;
+	u1Byte		antidx_d: 3;
+	u1Byte		antidx_c: 3;
+#endif
+
+	/* DW3 */
+	u1Byte		paid;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u1Byte		paid_msb: 1;
+	u1Byte		gid: 6;
+	u1Byte		rsvd_3: 1;
+#else
+	u1Byte		rsvd_3: 1;
+	u1Byte		gid: 6;
+	u1Byte		paid_msb: 1;
+#endif
+	u1Byte		intf_pos;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u1Byte		intf_pos_msb: 1;
+	u1Byte		rsvd_4: 2;
+	u1Byte		nb_intf_flag: 1;
+	u1Byte		rf_mode: 2;
+	u1Byte		rsvd_5: 2;
+#else
+	u1Byte		rsvd_5: 2;
+	u1Byte		rf_mode: 2;
+	u1Byte		nb_intf_flag: 1;
+	u1Byte		rsvd_4: 2;
+	u1Byte		intf_pos_msb: 1;
+#endif
+
+	/* DW4 */
+	s1Byte		rxevm[4];			/* s(8,1) */
+
+	/* DW5 */
+	s1Byte		cfo_tail[4];			/* s(8,7) */
+
+	/* DW6 */
+	s1Byte		rxsnr[4];			/* s(8,1) */
+} PHY_STATUS_RPT_JAGUAR2_TYPE1, *PPHY_STATUS_RPT_JAGUAR2_TYPE1;//for OFDM Format
+
+typedef struct _Phy_Status_Rpt_Jaguar2_Type2 {
+	/* DW0 ane DW1 */
+	u1Byte		page_num;
+	u1Byte		pwdb[4];
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)	
+	u1Byte		l_rxsc: 4;
+	u1Byte		ht_rxsc: 4;
+#else
+	u1Byte		ht_rxsc: 4;
+	u1Byte		l_rxsc: 4;
+#endif
+	u1Byte		channel;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u1Byte		band: 2;
+	u1Byte		rsvd_0: 1;
+	u1Byte		hw_antsw_occu: 1;
+	u1Byte		gnt_bt: 1;
+	u1Byte		ldpc: 1;
+	u1Byte		stbc: 1;
+	u1Byte		beamformed: 1;
+#else
+	u1Byte		beamformed: 1;
+	u1Byte		stbc: 1;
+	u1Byte		ldpc: 1;
+	u1Byte		gnt_bt: 1;
+	u1Byte		hw_antsw_occu: 1;
+	u1Byte		rsvd_0: 1;
+	u1Byte		band: 2;
+#endif
+
+	/* DW2 */
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u1Byte		shift_l_map: 6;
+	u1Byte		rsvd_1: 2;
+#else
+	u1Byte		rsvd_1: 2;
+	u1Byte		shift_l_map: 6;
+#endif
+	u1Byte		cnt_pw2cca;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u1Byte		agc_table_a: 4;
+	u1Byte		agc_table_b: 4;
+	u1Byte		agc_table_c: 4;
+	u1Byte		agc_table_d: 4;
+#else
+	u1Byte		agc_table_b: 4;
+	u1Byte		agc_table_a: 4;
+	u1Byte		agc_table_d: 4;
+	u1Byte		agc_table_c: 4;
+#endif
+
+	/* DW3 ~ DW6*/
+	u1Byte		cnt_cca2agc_rdy;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u1Byte		gain_a: 6;
+	u1Byte		rsvd_2: 1;
+	u1Byte		trsw_a: 1;
+	u1Byte		gain_b: 6;
+	u1Byte		rsvd_3: 1;
+	u1Byte		trsw_b: 1;
+	u1Byte		gain_c: 6;
+	u1Byte		rsvd_4: 1;
+	u1Byte		trsw_c: 1;
+	u1Byte		gain_d: 6;
+	u1Byte		rsvd_5: 1;
+	u1Byte		trsw_d: 1;
+	u1Byte		aagc_step_a: 2;
+	u1Byte		aagc_step_b: 2;
+	u1Byte		aagc_step_c: 2;
+	u1Byte		aagc_step_d: 2;
+#else
+	u1Byte		trsw_a: 1;
+	u1Byte		rsvd_2: 1;
+	u1Byte		gain_a: 6;
+	u1Byte		trsw_b: 1;
+	u1Byte		rsvd_3: 1;
+	u1Byte		gain_b: 6;
+	u1Byte		trsw_c: 1;
+	u1Byte		rsvd_4: 1;
+	u1Byte		gain_c: 6;
+	u1Byte		trsw_d: 1;
+	u1Byte		rsvd_5: 1;
+	u1Byte		gain_d: 6;
+	u1Byte		aagc_step_d: 2;
+	u1Byte		aagc_step_c: 2;
+	u1Byte		aagc_step_b: 2;
+	u1Byte		aagc_step_a: 2;
+#endif
+	u1Byte		ht_aagc_gain[4];
+	u1Byte		dagc_gain[4];
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u1Byte		counter: 6;
+	u1Byte		rsvd_6: 2;
+	u1Byte		syn_count: 5;
+	u1Byte		rsvd_7:3;
+#else
+	u1Byte		rsvd_6: 2;
+	u1Byte		counter: 6;
+	u1Byte		rsvd_7:3;
+	u1Byte		syn_count: 5;
+#endif
+} PHY_STATUS_RPT_JAGUAR2_TYPE2, *PPHY_STATUS_RPT_JAGUAR2_TYPE2;//for debug mode: AGC&SBD
+
+#endif
+
+#endif /*#ifndef	__HALHWOUTSRC_H__*/
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_NoiseMonitor.h

@@ -0,0 +1,49 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ *****************************************************************************/
+#ifndef	__ODMNOISEMONITOR_H__
+#define __ODMNOISEMONITOR_H__
+
+#define	ODM_MAX_CHANNEL_NUM					38//14+24
+struct noise_level
+{
+	//u1Byte				value_a, value_b;
+	u1Byte				value[MAX_RF_PATH];
+	//s1Byte				sval_a, sval_b;
+	s1Byte				sval[MAX_RF_PATH];
+	
+	//s4Byte				noise_a=0, noise_b=0,sum_a=0, sum_b=0;
+	//s4Byte				noise[ODM_RF_PATH_MAX];
+	s4Byte				sum[MAX_RF_PATH];
+	//u1Byte				valid_cnt_a=0, valid_cnt_b=0, 
+	u1Byte				valid[MAX_RF_PATH];
+	u1Byte				valid_cnt[MAX_RF_PATH];
+
+};
+
+
+typedef struct _ODM_NOISE_MONITOR_
+{
+	s1Byte			noise[MAX_RF_PATH];
+	s2Byte			noise_all;	
+}ODM_NOISE_MONITOR;
+
+s2Byte ODM_InbandNoise_Monitor(PVOID pDM_VOID,u8 bPauseDIG,u8 IGIValue,u32 max_time);
+
+#endif

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_PathDiv.h

@@ -0,0 +1,193 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__PHYDMPATHDIV_H__
+#define    __PHYDMPATHDIV_H__
+
+#define PATHDIV_VERSION	"1.0"
+
+VOID	
+odm_PathDiversityInit(
+	IN	PVOID	pDM_VOID
+	);
+
+VOID    
+odm_PathDiversity(
+	IN	PVOID	pDM_VOID
+	);
+
+#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 
+
+//#define   PATHDIV_ENABLE 	 1
+#define dm_PathDiv_RSSI_Check	ODM_PathDivChkPerPktRssi
+#define PathDivCheckBeforeLink8192C	ODM_PathDiversityBeforeLink92C
+
+typedef struct _PathDiv_Parameter_define_
+{
+	u4Byte org_5g_RegE30;
+	u4Byte org_5g_RegC14;
+	u4Byte org_5g_RegCA0;
+	u4Byte swt_5g_RegE30;
+	u4Byte swt_5g_RegC14;
+	u4Byte swt_5g_RegCA0;
+	//for 2G IQK information
+	u4Byte org_2g_RegC80;
+	u4Byte org_2g_RegC4C;
+	u4Byte org_2g_RegC94;
+	u4Byte org_2g_RegC14;
+	u4Byte org_2g_RegCA0;
+
+	u4Byte swt_2g_RegC80;
+	u4Byte swt_2g_RegC4C;
+	u4Byte swt_2g_RegC94;
+	u4Byte swt_2g_RegC14;
+	u4Byte swt_2g_RegCA0;
+}PATHDIV_PARA,*pPATHDIV_PARA;
+
+VOID	
+odm_PathDiversityInit_92C(
+	IN	PADAPTER	Adapter
+	);
+
+VOID	
+odm_2TPathDiversityInit_92C(
+	IN	PADAPTER	Adapter
+	);
+
+VOID	
+odm_1TPathDiversityInit_92C(	
+	IN	PADAPTER	Adapter
+	);
+
+BOOLEAN
+odm_IsConnected_92C(
+	IN	PADAPTER	Adapter
+	);
+
+BOOLEAN 
+ODM_PathDiversityBeforeLink92C(
+	//IN	PADAPTER	Adapter
+	IN		PDM_ODM_T		pDM_Odm
+	);
+
+VOID	
+odm_PathDiversityAfterLink_92C(
+	IN	PADAPTER	Adapter
+	);
+
+VOID
+odm_SetRespPath_92C(	
+	IN	PADAPTER	Adapter, 	
+	IN	u1Byte	DefaultRespPath
+	);
+
+VOID	
+odm_OFDMTXPathDiversity_92C(
+	IN	PADAPTER	Adapter
+	);
+
+VOID	
+odm_CCKTXPathDiversity_92C(	
+	IN	PADAPTER	Adapter
+	);
+
+VOID	
+odm_ResetPathDiversity_92C(	
+	IN	PADAPTER	Adapter
+	);
+
+VOID
+odm_CCKTXPathDiversityCallback(
+	PRT_TIMER		pTimer
+	);
+
+VOID
+odm_CCKTXPathDiversityWorkItemCallback(
+	IN PVOID            pContext
+	);
+
+VOID
+odm_PathDivChkAntSwitchCallback(
+	PRT_TIMER		pTimer
+	);
+
+VOID
+odm_PathDivChkAntSwitchWorkitemCallback(
+	IN PVOID            pContext
+	);
+
+
+VOID 
+odm_PathDivChkAntSwitch(
+	PDM_ODM_T    pDM_Odm
+	);
+
+VOID
+ODM_CCKPathDiversityChkPerPktRssi(
+	PADAPTER		Adapter,
+	BOOLEAN			bIsDefPort,
+	BOOLEAN			bMatchBSSID,
+	PRT_WLAN_STA	pEntry,
+	PRT_RFD			pRfd,
+	pu1Byte			pDesc
+	);
+
+VOID 
+ODM_PathDivChkPerPktRssi(
+	PADAPTER		Adapter,
+	BOOLEAN			bIsDefPort,
+	BOOLEAN			bMatchBSSID,
+	PRT_WLAN_STA	pEntry,
+	PRT_RFD			pRfd	
+	);
+
+VOID
+ODM_PathDivRestAfterLink(
+	IN	PDM_ODM_T		pDM_Odm
+	);
+
+VOID
+ODM_FillTXPathInTXDESC(
+		IN	PADAPTER	Adapter,
+		IN	PRT_TCB		pTcb,
+		IN	pu1Byte		pDesc
+	);
+
+VOID
+odm_PathDivInit_92D(
+	IN	PDM_ODM_T 	pDM_Odm
+	);
+
+u1Byte
+odm_SwAntDivSelectScanChnl(
+	IN	PADAPTER	Adapter
+	);
+
+VOID
+odm_SwAntDivConstructScanChnl(
+	IN	PADAPTER	Adapter,
+	IN	u1Byte		ScanChnl
+	);
+	
+ #endif       //#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 
+ 
+ 
+ #endif		 //#ifndef  __ODMPATHDIV_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_PowerTracking.h

@@ -0,0 +1,306 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__PHYDMPOWERTRACKING_H__
+#define    __PHYDMPOWERTRACKING_H__
+
+#define POWRTRACKING_VERSION	"1.0"
+
+#define		DPK_DELTA_MAPPING_NUM	13
+#define		index_mapping_HP_NUM	15	
+#define	OFDM_TABLE_SIZE 	43
+#define	CCK_TABLE_SIZE			33
+#define TXSCALE_TABLE_SIZE 		37
+#define TXPWR_TRACK_TABLE_SIZE 	30
+#define DELTA_SWINGIDX_SIZE     30
+#define BAND_NUM 				4
+#define CCK_TABLE_SIZE_8711B	41
+
+#define AVG_THERMAL_NUM		8
+#define HP_THERMAL_NUM		8
+#define IQK_MAC_REG_NUM		4
+#define IQK_ADDA_REG_NUM		16
+#define IQK_BB_REG_NUM_MAX	10
+#if (RTL8192D_SUPPORT==1) 
+#define IQK_BB_REG_NUM		10
+#else
+#define IQK_BB_REG_NUM		9
+#endif
+
+
+#define IQK_Matrix_REG_NUM	8
+#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8195A) || defined (CONFIG_RTL8711B)
+#define IQK_Matrix_Settings_NUM	14
+#else
+#define IQK_Matrix_Settings_NUM	14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G
+#endif
+
+//extern	u4Byte OFDMSwingTable[OFDM_TABLE_SIZE];
+//extern	u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
+//extern	u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
+#if (RTL8195A_SUPPORT == 1)
+extern const u1Byte CCKSwingTable_Ch1_Ch13_8195A[CCK_TABLE_SIZE][9];
+extern const u1Byte CCKSwingTable_Ch14_8195A[CCK_TABLE_SIZE][9];
+extern const u1Byte CCKFCCTable_8195A[16];
+extern const u1Byte CCKCETable_8195A[16];
+extern const u1Byte CCKFCCTable_Ch14_8195A[16];
+#endif
+
+#if (RTL8711B_SUPPORT == 1)
+
+extern const u1Byte CCKFCCTable_8711B[16];
+extern const u1Byte CCKCETable_8711B[16];
+extern const u1Byte CCKFCCTable_Ch14_8711B[16];
+extern const u4Byte CCKSwingTable_Ch1_Ch14_8711B[CCK_TABLE_SIZE_8711B];
+#endif
+
+extern const u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE];
+extern const u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
+extern const u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8];
+//extern  u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
+
+// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table.
+//static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};
+//static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11}; 
+
+#define dm_CheckTXPowerTracking 	ODM_TXPowerTrackingCheck
+
+typedef struct _IQK_MATRIX_REGS_SETTING{
+	BOOLEAN 	bIQKDone;
+#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B)
+	s4Byte		Value[1][IQK_Matrix_REG_NUM];
+#else
+	s4Byte		Value[3][IQK_Matrix_REG_NUM];
+	BOOLEAN 	bBWIqkResultSaved[3];	
+#endif
+}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;
+
+typedef struct ODM_RF_Calibration_Structure
+{
+	//for tx power tracking
+	
+	u4Byte	RegA24; // for TempCCK
+	s4Byte	RegE94;
+	s4Byte 	RegE9C;
+	s4Byte	RegEB4;
+	s4Byte	RegEBC;	
+
+	u1Byte  	TXPowercount;
+	BOOLEAN bTXPowerTrackingInit; 
+	BOOLEAN bTXPowerTracking;
+	u1Byte  	TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
+	u1Byte  	TM_Trigger;
+    	u1Byte  	InternalPA5G[2];	//pathA / pathB
+	
+	u1Byte  	ThermalMeter[2];    // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
+	u1Byte  	ThermalValue;
+	u1Byte  	ThermalValue_LCK;
+	u1Byte  	ThermalValue_IQK;
+	u1Byte	ThermalValue_DPK;		
+	u1Byte	ThermalValue_AVG[AVG_THERMAL_NUM];
+	u1Byte	ThermalValue_AVG_index;		
+	u1Byte	ThermalValue_RxGain;
+	u1Byte	ThermalValue_Crystal;
+	u1Byte	ThermalValue_DPKstore;
+	u1Byte	ThermalValue_DPKtrack;
+	BOOLEAN	TxPowerTrackingInProgress;
+	
+	BOOLEAN	bReloadtxpowerindex;	
+	u1Byte 	bRfPiEnable;
+	u4Byte 	TXPowerTrackingCallbackCnt; //cosa add for debug
+
+
+	//------------------------- Tx power Tracking -------------------------//
+	u1Byte 	bCCKinCH14;
+	u1Byte 	CCK_index[MAX_RF_PATH];
+	s1Byte	PowerIndexOffset_CCK[MAX_RF_PATH];
+	s1Byte	DeltaPowerIndex_CCK[MAX_RF_PATH];
+	s1Byte	DeltaPowerIndexLast_CCK[MAX_RF_PATH];
+	u1Byte 	OFDM_index[MAX_RF_PATH];
+	s1Byte	PowerIndexOffset_OFDM[MAX_RF_PATH];
+	s1Byte	DeltaPowerIndex_OFDM[MAX_RF_PATH];
+	s1Byte	DeltaPowerIndexLast_OFDM[MAX_RF_PATH];	
+	BOOLEAN bTxPowerChanged;
+	s1Byte	XtalOffset;
+	s1Byte	XtalOffsetLast;
+		
+	u1Byte 	ThermalValue_HP[HP_THERMAL_NUM];
+	u1Byte 	ThermalValue_HP_index;
+	IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
+	u1Byte	Delta_LCK;
+	s1Byte  BBSwingDiff2G, BBSwingDiff5G; // Unit: dB
+	s1Byte  DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
+#if !defined(NOT_SUPPORT_RF_MULTIPATH)
+	s1Byte  DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE];
+#endif
+	s1Byte  DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
+#if !defined(NOT_SUPPORT_RF_MULTIPATH)
+	s1Byte  DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE];
+#endif
+#if !defined(NOT_SUPPORT_5G)
+	s1Byte  DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
+#endif	
+//	u1Byte  DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
+//	u1Byte  DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
+
+	s1Byte  DeltaSwingTableXtal_P[DELTA_SWINGIDX_SIZE];
+	s1Byte  DeltaSwingTableXtal_N[DELTA_SWINGIDX_SIZE];
+
+    
+    
+	//--------------------------------------------------------------------//	
+	
+	//for IQK	
+	u4Byte 	RegC04;
+	u4Byte 	Reg874;
+	u4Byte 	RegC08;
+	u4Byte 	RegB68;
+	u4Byte 	RegB6C;
+	u4Byte 	Reg870;
+	u4Byte 	Reg860;
+	u4Byte 	Reg864;
+	
+	BOOLEAN	bIQKInitialized;
+	BOOLEAN bLCKInProgress;
+	BOOLEAN	bAntennaDetected;
+	BOOLEAN	bNeedIQK;
+	BOOLEAN	bIQKInProgress;	
+	u1Byte	Delta_IQK;
+	u4Byte	ADDA_backup[IQK_ADDA_REG_NUM];
+	u4Byte	IQK_MAC_backup[IQK_MAC_REG_NUM];
+	u4Byte	IQK_BB_backup_recover[9];
+	u4Byte	IQK_BB_backup[IQK_BB_REG_NUM];	
+	u4Byte 	TxIQC_8723B[2][3][2]; // { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}
+	u4Byte 	RxIQC_8723B[2][2][2]; // { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}
+
+	// <James> IQK time measurement 
+	u8Byte	IQK_StartTime;
+	u8Byte	IQK_ProgressingTime;
+	u4Byte	LOK_Result;
+
+	//for APK
+	u4Byte 	APKoutput[2][2]; //path A/B; output1_1a/output1_2a
+	u1Byte 	bAPKdone;
+	u1Byte 	bAPKThermalMeterIgnore;
+	
+	// DPK
+	BOOLEAN bDPKFail;	
+	u1Byte 	bDPdone;
+	u1Byte 	bDPPathAOK;
+	u1Byte 	bDPPathBOK;
+
+	u4Byte	TxLOK[2];
+	u4Byte  DpkTxAGC;
+	s4Byte  DpkGain;
+	u4Byte  DpkThermal[4];
+}ODM_RF_CAL_T,*PODM_RF_CAL_T;
+
+
+VOID	
+ODM_TXPowerTrackingCheck(
+	IN 	PVOID	 	pDM_VOID
+	);
+
+
+VOID
+odm_TXPowerTrackingInit(
+	IN 	PVOID	 	pDM_VOID
+	);
+
+VOID
+odm_TXPowerTrackingCheckAP(
+	IN 	PVOID	 	pDM_VOID
+	);
+
+VOID
+odm_TXPowerTrackingThermalMeterInit(
+	IN 	PVOID	 	pDM_VOID
+	);
+
+VOID
+odm_TXPowerTrackingInit(
+	IN 	PVOID	 	pDM_VOID
+	);
+
+VOID
+odm_TXPowerTrackingCheckMP(
+	IN 	PVOID	 	pDM_VOID
+	);
+
+
+VOID
+odm_TXPowerTrackingCheckCE(
+	IN 	PVOID	 	pDM_VOID
+	);
+
+VOID
+odm_TXPowerTrackingCheckIOT(
+	IN 	PVOID	 	pDM_VOID
+	);
+
+#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 
+
+VOID 
+odm_TXPowerTrackingCallbackThermalMeter92C(
+            IN PADAPTER	Adapter
+            );
+
+VOID
+odm_TXPowerTrackingCallbackRXGainThermalMeter92D(
+	IN PADAPTER 	Adapter
+	);
+
+VOID
+odm_TXPowerTrackingCallbackThermalMeter92D(
+            IN PADAPTER	Adapter
+            );
+
+VOID
+odm_TXPowerTrackingDirectCall92C(
+            IN	PADAPTER		Adapter
+            );
+
+VOID
+odm_TXPowerTrackingThermalMeterCheck(
+	IN	PADAPTER		Adapter
+	);
+
+#endif
+
+#endif

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RXHP.h

@@ -0,0 +1,105 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef	__PHYDMRXHP_H__
+#define    __PHYDMRXHP_H__
+
+#define RXHP_VERSION	"1.0"
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+#define	AFH_PSD		1	//0:normal PSD scan, 1: only do 20 pts PSD
+#define	MODE_40M		0	//0:20M, 1:40M
+#define	PSD_TH2		3  
+#define	PSD_CHMIN		20   // Minimum channel number for BT AFH
+#define	SIR_STEP_SIZE	3
+#define   Smooth_Size_1 	5
+#define	Smooth_TH_1	3
+#define   Smooth_Size_2 	10
+#define	Smooth_TH_2	4
+#define   Smooth_Size_3 	20
+#define	Smooth_TH_3	4
+#define   Smooth_Step_Size 5
+#define	Adaptive_SIR	1
+#define	PSD_RESCAN		4
+#define	PSD_SCAN_INTERVAL	700 //ms
+
+typedef struct _RX_High_Power_
+{
+	u1Byte		RXHP_flag;
+	u1Byte		PSD_func_trigger;
+	u1Byte		PSD_bitmap_RXHP[80];
+	u1Byte		Pre_IGI;
+	u1Byte		Cur_IGI;
+	u1Byte		Pre_pw_th;
+	u1Byte		Cur_pw_th;
+	BOOLEAN		First_time_enter;
+	BOOLEAN		RXHP_enable;
+	u1Byte		TP_Mode;
+	RT_TIMER	PSDTimer;
+	#if USE_WORKITEM
+	RT_WORK_ITEM		PSDTimeWorkitem;
+	#endif
+}RXHP_T, *pRXHP_T;
+
+#define	dm_PSDMonitorCallback	odm_PSDMonitorCallback
+VOID	odm_PSDMonitorCallback(PRT_TIMER		pTimer);
+
+VOID
+odm_PSDMonitorInit(
+	IN		PVOID			pDM_VOID
+	);
+
+void	odm_RXHPInit(
+	IN		PVOID			pDM_VOID);
+
+void odm_RXHP(
+	IN		PVOID			pDM_VOID);
+
+VOID
+odm_PSD_RXHPCallback(
+	PRT_TIMER		pTimer
+);
+
+ VOID
+ODM_PSDDbgControl(
+	IN	PADAPTER	Adapter,
+	IN	u4Byte		mode,
+	IN	u4Byte		btRssi
+	);
+
+ VOID
+odm_PSD_RXHPCallback(
+	PRT_TIMER		pTimer
+);
+
+VOID
+odm_PSD_RXHPWorkitemCallback(
+    IN PVOID            pContext
+    );
+
+VOID
+odm_PSDMonitorWorkItemCallback(
+    IN PVOID            pContext
+    );
+
+ #endif
+
+ #endif
+ 

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RaInfo.h

@@ -0,0 +1,210 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__PHYDMRAINFO_H__
+#define    __PHYDMRAINFO_H__
+
+#define RAINFO_VERSION	"1.0"
+
+#define	H2C_0X42_LENGTH	5
+#define	H2C_MAX_LENGTH	7
+
+#define	RA_FLOOR_UP_GAP		3
+#define	RA_FLOOR_TABLE_SIZE	7
+
+#define	ACTIVE_TP_THRESHOLD	150
+#define	RA_RETRY_DESCEND_NUM	2
+#define	RA_RETRY_LIMIT_LOW	4
+#define	RA_RETRY_LIMIT_HIGH	32
+
+#define RAINFO_BE_RX_STATE			BIT0  // 1:RX    //ULDL
+#define RAINFO_STBC_STATE			BIT1
+//#define RAINFO_LDPC_STATE 			BIT2
+#define RAINFO_NOISY_STATE 			BIT2    // set by Noisy_Detection
+#define RAINFO_SHURTCUT_STATE 		BIT3
+#define RAINFO_SHURTCUT_FLAG 		BIT4
+#define RAINFO_INIT_RSSI_RATE_STATE  BIT5
+#define RAINFO_BF_STATE 				BIT6
+#define RAINFO_BE_TX_STATE 			BIT7 // 1:TX
+
+#define AP_InitRateAdaptiveState	ODM_RateAdaptiveStateApInit
+
+#define		DM_RATR_STA_INIT			0
+#define		DM_RATR_STA_HIGH			1
+#define 		DM_RATR_STA_MIDDLE		2
+#define 		DM_RATR_STA_LOW			3
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+#define		DM_RATR_STA_ULTRA_LOW	4
+#endif
+
+#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_IOT))
+typedef struct _Rate_Adaptive_Table_{
+	u1Byte		firstconnect;
+	#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
+	BOOLEAN		PT_collision_pre;
+	#endif
+
+    	//u1Byte	link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];
+	u1Byte	highest_client_tx_order;
+	u2Byte	highest_client_tx_rate_order;
+	u1Byte	power_tracking_flag;
+	u1Byte	RA_threshold_offset;
+	u1Byte	RA_offset_direction;
+    
+}RA_T, *pRA_T;
+#endif
+
+typedef struct _ODM_RATE_ADAPTIVE
+{
+	u1Byte				Type;				// DM_Type_ByFW/DM_Type_ByDriver
+	u1Byte				HighRSSIThresh;		// if RSSI > HighRSSIThresh	=> RATRState is DM_RATR_STA_HIGH
+	u1Byte				LowRSSIThresh;		// if RSSI <= LowRSSIThresh	=> RATRState is DM_RATR_STA_LOW
+	u1Byte				RATRState;			// Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
+
+	#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_IOT))
+	u1Byte				LdpcThres;			// if RSSI > LdpcThres => switch from LPDC to BCC
+	BOOLEAN				bLowerRtsRate;
+	#endif
+
+	#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	u1Byte				RtsThres;
+	#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_IOT))
+	BOOLEAN				bUseLdpc;
+	#else
+	u1Byte				UltraLowRSSIThresh;
+	u4Byte				LastRATR;			// RATR Register Content
+	#endif
+
+} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
+
+VOID
+odm_RSSIMonitorInit(
+	IN		PVOID		pDM_VOID
+	);
+
+VOID
+odm_RSSIMonitorCheck(
+	IN	 	PVOID	 	 pDM_VOID
+	);
+
+#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
+VOID
+odm_RSSIDumpToRegister(
+	IN	PVOID	pDM_VOID
+	);
+#endif
+
+VOID
+odm_RSSIMonitorCheckMP(
+	IN		PVOID	 	pDM_VOID
+	);
+
+VOID 
+odm_RSSIMonitorCheckCE(
+	IN		PVOID		pDM_VOID
+	);
+
+VOID 
+odm_RSSIMonitorCheckIOT(
+	IN		PVOID		pDM_VOID
+	);
+
+VOID 
+odm_RSSIMonitorCheckAP(
+	IN		PVOID		 pDM_VOID
+	);
+
+
+VOID
+odm_RateAdaptiveMaskInit(
+	IN	PVOID	pDM_VOID	
+	);
+
+VOID
+odm_RefreshRateAdaptiveMask(
+	IN	PVOID	pDM_VOID
+	);
+
+VOID
+odm_RefreshRateAdaptiveMaskMP(
+	IN	PVOID	pDM_VOID
+	);
+
+VOID
+odm_RefreshRateAdaptiveMaskCE(
+	IN	PVOID	pDM_VOID	
+	);
+
+VOID
+odm_RefreshRateAdaptiveMaskIOT(
+	IN	PVOID	pDM_VOID	
+	);
+
+VOID
+odm_RefreshRateAdaptiveMaskAPADSL(
+	IN	PVOID	pDM_VOID
+	);
+
+BOOLEAN 
+ODM_RAStateCheck(
+	IN		PVOID			pDM_VOID,
+	IN		s4Byte			RSSI,
+	IN		BOOLEAN			bForceUpdate,
+	OUT		pu1Byte			pRATRState
+	);
+	
+VOID
+odm_RefreshBasicRateMask(
+	IN	PVOID	pDM_VOID
+	);
+
+VOID
+phydm_ra_info_init(
+	IN	PVOID	pDM_VOID
+	);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+VOID
+ODM_DynamicARFBSelect(
+	IN		PVOID			pDM_VOID,
+	IN 		u1Byte			rate,
+	IN  	BOOLEAN			Collision_State	
+	);
+	
+VOID
+ODM_RateAdaptiveStateApInit(	
+	IN	PVOID		PADAPTER_VOID,
+	IN	PRT_WLAN_STA  	pEntry
+	);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_IOT))
+u4Byte 
+ODM_Get_Rate_Bitmap(
+	IN	PVOID		pDM_VOID,	
+	IN	u4Byte		macid,
+	IN	u4Byte 		ra_mask,	
+	IN	u1Byte 		rssi_level
+	);
+#endif
+
+#endif //#ifndef	__ODMRAINFO_H__
+
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RegDefine11AC.h

@@ -0,0 +1,81 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__ODM_REGDEFINE11AC_H__
+#define __ODM_REGDEFINE11AC_H__
+
+//2 RF REG LIST
+
+
+
+//2 BB REG LIST
+//PAGE 8
+#define	ODM_REG_CCK_RPT_FORMAT_11AC	0x804
+#define	ODM_REG_BB_RX_PATH_11AC			0x808
+#define	ODM_REG_BB_TX_PATH_11AC			0x80c
+#define	ODM_REG_BB_ATC_11AC				0x860
+#define	ODM_REG_EDCCA_POWER_CAL		0x8dc
+#define	ODM_REG_DBG_RPT_11AC			0x8fc
+//PAGE 9
+#define	ODM_REG_EDCCA_DOWN_OPT			0x900
+#define	ODM_REG_ACBB_EDCCA_ENHANCE		0x944
+#define	ODM_REG_OFDM_FA_RST_11AC		0x9A4
+#define	ODM_REG_NHM_TIMER_11AC			0x990
+#define	ODM_REG_NHM_TH9_TH10_11AC		0x994
+#define	ODM_REG_NHM_TH3_TO_TH0_11AC	0x998
+#define	ODM_REG_NHM_TH7_TO_TH4_11AC	0x99c
+#define	ODM_REG_NHM_TH8_11AC			0x9a0
+#define	ODM_REG_NHM_9E8_11AC			0x9e8
+//PAGE A
+#define	ODM_REG_CCK_CCA_11AC				0xA0A
+#define	ODM_REG_CCK_FA_RST_11AC			0xA2C
+#define	ODM_REG_CCK_FA_11AC				0xA5C
+//PAGE B
+#define	ODM_REG_RST_RPT_11AC				0xB58
+//PAGE C
+#define	ODM_REG_TRMUX_11AC				0xC08
+#define	ODM_REG_IGI_A_11AC				0xC50
+//PAGE E
+#define	ODM_REG_IGI_B_11AC				0xE50
+#define	ODM_REG_TRMUX_11AC_B			0xE08
+//PAGE F
+#define	ODM_REG_CCK_CCA_CNT_11AC		0xF08
+#define	ODM_REG_OFDM_FA_11AC			0xF48
+#define	ODM_REG_RPT_11AC					0xfa0
+#define	ODM_REG_NHM_CNT_11AC			0xfa8
+//PAGE 18
+#define	ODM_REG_IGI_C_11AC				0x1850
+//PAGE 1A
+#define	ODM_REG_IGI_D_11AC				0x1A50
+
+//2 MAC REG LIST
+#define	ODM_REG_RESP_TX_11AC				0x6D8
+
+
+
+//DIG Related
+#define	ODM_BIT_IGI_11AC					0xFFFFFFFF
+#define	ODM_BIT_CCK_RPT_FORMAT_11AC		BIT16
+#define	ODM_BIT_BB_RX_PATH_11AC			0xF
+#define	ODM_BIT_BB_TX_PATH_11AC			0xF
+#define	ODM_BIT_BB_ATC_11AC				BIT14
+
+#endif
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RegDefine11N.h

@@ -0,0 +1,186 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+ 
+#ifndef	__ODM_REGDEFINE11N_H__
+#define __ODM_REGDEFINE11N_H__
+
+
+//2 RF REG LIST
+#define	ODM_REG_RF_MODE_11N				0x00
+#define	ODM_REG_RF_0B_11N				0x0B
+#define	ODM_REG_CHNBW_11N				0x18
+#define	ODM_REG_T_METER_11N				0x24
+#define	ODM_REG_RF_25_11N				0x25
+#define	ODM_REG_RF_26_11N				0x26
+#define	ODM_REG_RF_27_11N				0x27
+#define	ODM_REG_RF_2B_11N				0x2B
+#define	ODM_REG_RF_2C_11N				0x2C
+#define	ODM_REG_RXRF_A3_11N				0x3C
+#define	ODM_REG_T_METER_92D_11N			0x42
+#define	ODM_REG_T_METER_88E_11N			0x42
+
+
+
+//2 BB REG LIST
+//PAGE 8
+#define	ODM_REG_BB_CTRL_11N				0x800
+#define	ODM_REG_RF_PIN_11N				0x804
+#define	ODM_REG_PSD_CTRL_11N				0x808
+#define	ODM_REG_TX_ANT_CTRL_11N			0x80C
+#define	ODM_REG_BB_PWR_SAV5_11N			0x818
+#define	ODM_REG_CCK_RPT_FORMAT_11N		0x824
+#define	ODM_REG_CCK_RPT_FORMAT_11N_B	0x82C
+#define	ODM_REG_RX_DEFUALT_A_11N		0x858
+#define	ODM_REG_RX_DEFUALT_B_11N		0x85A
+#define	ODM_REG_BB_PWR_SAV3_11N			0x85C
+#define	ODM_REG_ANTSEL_CTRL_11N			0x860
+#define	ODM_REG_RX_ANT_CTRL_11N			0x864
+#define	ODM_REG_PIN_CTRL_11N				0x870
+#define	ODM_REG_BB_PWR_SAV1_11N			0x874
+#define	ODM_REG_ANTSEL_PATH_11N			0x878
+#define	ODM_REG_BB_3WIRE_11N			0x88C
+#define	ODM_REG_SC_CNT_11N				0x8C4
+#define	ODM_REG_PSD_DATA_11N			0x8B4
+#define	ODM_REG_PSD_DATA_11N			0x8B4
+#define	ODM_REG_NHM_TIMER_11N			0x894
+#define	ODM_REG_NHM_TH9_TH10_11N		0x890
+#define	ODM_REG_NHM_TH3_TO_TH0_11N		0x898
+#define	ODM_REG_NHM_TH7_TO_TH4_11N		0x89c
+#define	ODM_REG_NHM_CNT_11N				0x8d8
+//PAGE 9
+#define	ODM_REG_DBG_RPT_11N				0x908
+#define	ODM_REG_BB_TX_PATH_11N			0x90c
+#define	ODM_REG_ANT_MAPPING1_11N		0x914
+#define	ODM_REG_ANT_MAPPING2_11N		0x918
+#define	ODM_REG_EDCCA_DOWN_OPT_11N	0x948
+
+//PAGE A
+#define	ODM_REG_CCK_ANTDIV_PARA1_11N	0xA00
+#define	ODM_REG_CCK_CCA_11N				0xA0A
+#define	ODM_REG_CCK_ANTDIV_PARA2_11N	0xA0C
+#define	ODM_REG_CCK_ANTDIV_PARA3_11N	0xA10
+#define	ODM_REG_CCK_ANTDIV_PARA4_11N	0xA14
+#define	ODM_REG_CCK_FILTER_PARA1_11N	0xA22
+#define	ODM_REG_CCK_FILTER_PARA2_11N	0xA23
+#define	ODM_REG_CCK_FILTER_PARA3_11N	0xA24
+#define	ODM_REG_CCK_FILTER_PARA4_11N	0xA25
+#define	ODM_REG_CCK_FILTER_PARA5_11N	0xA26
+#define	ODM_REG_CCK_FILTER_PARA6_11N	0xA27
+#define	ODM_REG_CCK_FILTER_PARA7_11N	0xA28
+#define	ODM_REG_CCK_FILTER_PARA8_11N	0xA29
+#define	ODM_REG_CCK_FA_RST_11N			0xA2C
+#define	ODM_REG_CCK_FA_MSB_11N			0xA58
+#define	ODM_REG_CCK_FA_LSB_11N			0xA5C
+#define	ODM_REG_CCK_CCA_CNT_11N			0xA60
+#define	ODM_REG_BB_PWR_SAV4_11N			0xA74
+//PAGE B
+#define	ODM_REG_LNA_SWITCH_11N			0xB2C
+#define	ODM_REG_PATH_SWITCH_11N			0xB30
+#define	ODM_REG_RSSI_CTRL_11N			0xB38
+#define	ODM_REG_CONFIG_ANTA_11N			0xB68
+#define	ODM_REG_RSSI_BT_11N				0xB9C
+//PAGE C
+#define	ODM_REG_OFDM_FA_HOLDC_11N		0xC00
+#define	ODM_REG_BB_RX_PATH_11N			0xC04
+#define	ODM_REG_TRMUX_11N				0xC08
+#define	ODM_REG_OFDM_FA_RSTC_11N		0xC0C
+#define	ODM_REG_RXIQI_MATRIX_11N		0xC14
+#define	ODM_REG_TXIQK_MATRIX_LSB1_11N	0xC4C
+#define	ODM_REG_IGI_A_11N				0xC50
+#define	ODM_REG_ANTDIV_PARA2_11N		0xC54
+#define	ODM_REG_IGI_B_11N					0xC58
+#define	ODM_REG_ANTDIV_PARA3_11N		0xC5C
+#define   ODM_REG_L1SBD_PD_CH_11N			0XC6C
+#define	ODM_REG_BB_PWR_SAV2_11N		0xC70
+#define	ODM_REG_RX_OFF_11N				0xC7C
+#define	ODM_REG_TXIQK_MATRIXA_11N		0xC80
+#define	ODM_REG_TXIQK_MATRIXB_11N		0xC88
+#define	ODM_REG_TXIQK_MATRIXA_LSB2_11N	0xC94
+#define	ODM_REG_TXIQK_MATRIXB_LSB2_11N	0xC9C
+#define	ODM_REG_RXIQK_MATRIX_LSB_11N	0xCA0
+#define	ODM_REG_ANTDIV_PARA1_11N		0xCA4
+#define	ODM_REG_OFDM_FA_TYPE1_11N		0xCF0
+//PAGE D
+#define	ODM_REG_OFDM_FA_RSTD_11N		0xD00
+#define	ODM_REG_BB_ATC_11N				0xD2C
+#define	ODM_REG_OFDM_FA_TYPE2_11N		0xDA0
+#define	ODM_REG_OFDM_FA_TYPE3_11N		0xDA4
+#define	ODM_REG_OFDM_FA_TYPE4_11N		0xDA8
+#define	ODM_REG_RPT_11N					0xDF4
+//PAGE E
+#define	ODM_REG_TXAGC_A_6_18_11N		0xE00
+#define	ODM_REG_TXAGC_A_24_54_11N		0xE04
+#define	ODM_REG_TXAGC_A_1_MCS32_11N	0xE08
+#define	ODM_REG_TXAGC_A_MCS0_3_11N		0xE10
+#define	ODM_REG_TXAGC_A_MCS4_7_11N		0xE14
+#define	ODM_REG_TXAGC_A_MCS8_11_11N	0xE18
+#define	ODM_REG_TXAGC_A_MCS12_15_11N	0xE1C
+#define	DOM_REG_EDCCA_DCNF_11N			0xE24
+#define	ODM_REG_FPGA0_IQK_11N			0xE28
+#define	ODM_REG_TXIQK_TONE_A_11N		0xE30
+#define	ODM_REG_RXIQK_TONE_A_11N		0xE34
+#define	ODM_REG_TXIQK_PI_A_11N			0xE38
+#define	ODM_REG_RXIQK_PI_A_11N			0xE3C
+#define	ODM_REG_TXIQK_11N				0xE40
+#define	ODM_REG_RXIQK_11N				0xE44
+#define	ODM_REG_IQK_AGC_PTS_11N			0xE48
+#define	ODM_REG_IQK_AGC_RSP_11N			0xE4C
+#define	ODM_REG_BLUETOOTH_11N			0xE6C
+#define	ODM_REG_RX_WAIT_CCA_11N			0xE70
+#define	ODM_REG_TX_CCK_RFON_11N			0xE74
+#define	ODM_REG_TX_CCK_BBON_11N			0xE78
+#define	ODM_REG_OFDM_RFON_11N			0xE7C
+#define	ODM_REG_OFDM_BBON_11N			0xE80
+#define 	ODM_REG_TX2RX_11N				0xE84
+#define	ODM_REG_TX2TX_11N				0xE88
+#define	ODM_REG_RX_CCK_11N				0xE8C
+#define	ODM_REG_RX_OFDM_11N				0xED0
+#define	ODM_REG_RX_WAIT_RIFS_11N		0xED4
+#define	ODM_REG_RX2RX_11N				0xED8
+#define	ODM_REG_STANDBY_11N				0xEDC
+#define	ODM_REG_SLEEP_11N				0xEE0
+#define	ODM_REG_PMPD_ANAEN_11N			0xEEC
+#define	ODM_REG_IGI_C_11N					0xF84
+#define	ODM_REG_IGI_D_11N				0xF88
+
+//2 MAC REG LIST
+#define	ODM_REG_BB_RST_11N				0x02
+#define	ODM_REG_ANTSEL_PIN_11N			0x4C
+#define	ODM_REG_EARLY_MODE_11N			0x4D0
+#define	ODM_REG_RSSI_MONITOR_11N		0x4FE
+#define	ODM_REG_EDCA_VO_11N				0x500
+#define	ODM_REG_EDCA_VI_11N				0x504
+#define	ODM_REG_EDCA_BE_11N				0x508
+#define	ODM_REG_EDCA_BK_11N				0x50C
+#define	ODM_REG_TXPAUSE_11N				0x522
+#define	ODM_REG_RESP_TX_11N				0x6D8
+#define	ODM_REG_ANT_TRAIN_PARA1_11N	0x7b0
+#define	ODM_REG_ANT_TRAIN_PARA2_11N	0x7b4
+
+
+//DIG Related
+#define	ODM_BIT_IGI_11N					0x0000007F
+#define	ODM_BIT_CCK_RPT_FORMAT_11N		BIT9
+#define	ODM_BIT_BB_RX_PATH_11N			0xF
+#define	ODM_BIT_BB_TX_PATH_11N			0xF
+#define	ODM_BIT_BB_ATC_11N				BIT11
+
+#endif
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_debug.h

@@ -0,0 +1,900 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef	__ODM_DBG_H__
+#define __ODM_DBG_H__
+
+
+//-----------------------------------------------------------------------------
+//	Define the debug levels
+//
+//	1.	DBG_TRACE and DBG_LOUD are used for normal cases.
+//	So that, they can help SW engineer to develope or trace states changed 
+//	and also help HW enginner to trace every operation to and from HW, 
+//	e.g IO, Tx, Rx. 
+//
+//	2.	DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, 
+//	which help us to debug SW or HW.
+//
+//-----------------------------------------------------------------------------
+//
+//	Never used in a call to ODM_RT_TRACE()!
+//
+#define ODM_DBG_OFF					1
+
+//
+//	Fatal bug. 
+//	For example, Tx/Rx/IO locked up, OS hangs, memory access violation, 
+//	resource allocation failed, unexpected HW behavior, HW BUG and so on.
+//
+#define ODM_DBG_SERIOUS				2
+
+//
+//	Abnormal, rare, or unexpeted cases.
+//	For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
+//
+#define ODM_DBG_WARNING				3
+
+//
+//	Normal case with useful information about current SW or HW state. 
+//	For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, 
+//	SW protocol state change, dynamic mechanism state change and so on.
+//
+#define ODM_DBG_LOUD					4
+
+//
+//	Normal case with detail execution flow or information.
+//
+#define ODM_DBG_TRACE					5
+
+//-----------------------------------------------------------------------------
+// Define the tracing components
+//
+//-----------------------------------------------------------------------------
+//BB Functions
+#define ODM_COMP_DIG				BIT0	
+#define ODM_COMP_RA_MASK			BIT1	
+#define ODM_COMP_DYNAMIC_TXPWR		BIT2
+#define ODM_COMP_FA_CNT				BIT3
+#define ODM_COMP_RSSI_MONITOR		BIT4
+#define ODM_COMP_CCK_PD				BIT5
+#define ODM_COMP_ANT_DIV			BIT6
+#define ODM_COMP_PWR_SAVE			BIT7
+#define ODM_COMP_PWR_TRAIN			BIT8
+#define ODM_COMP_RATE_ADAPTIVE		BIT9
+#define ODM_COMP_PATH_DIV			BIT10
+#define ODM_COMP_PSD				BIT11
+#define ODM_COMP_DYNAMIC_PRICCA		BIT12
+#define ODM_COMP_RXHP				BIT13			
+#define ODM_COMP_MP					BIT14
+#define ODM_COMP_CFO_TRACKING		BIT15
+#define ODM_COMP_ACS					BIT16
+#define PHYDM_COMP_ADAPTIVITY		BIT17
+
+//MAC Functions
+#define ODM_COMP_EDCA_TURBO			BIT18
+#define ODM_COMP_EARLY_MODE			BIT19
+//RF Functions
+#define ODM_COMP_TX_PWR_TRACK		BIT24
+#define ODM_COMP_RX_GAIN_TRACK		BIT25
+#define ODM_COMP_CALIBRATION		BIT26
+//Common Functions
+#define ODM_COMP_INIT				BIT29
+#define ODM_COMP_COMMON				BIT30
+#define ODM_COMP_FIX				BIT31
+
+/*------------------------Export Marco Definition---------------------------*/
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	#define RT_PRINTK				DbgPrint
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	#define DbgPrint	printk
+	#define RT_PRINTK(fmt, args...)	DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
+	#define	RT_DISP(dbgtype, dbgflag, printstr)
+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+	#define DbgPrint	printf
+	#define RT_PRINTK(fmt, args...)	DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
+	#define	RT_DISP(dbgtype, dbgflag, printstr)
+#else
+	#define DbgPrint	panic_printk
+	#define RT_PRINTK(fmt, args...)	DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
+#endif
+
+#ifndef ASSERT
+	#define ASSERT(expr)
+#endif
+
+#if DBG
+#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)									\
+		if(((comp) & ROMInfo.DebugComponents) && (level <= ROMInfo.DebugLevel || level == ODM_DBG_SERIOUS))	\
+		{																			\
+			RT_PRINTK fmt;															\
+		}
+
+#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)									\
+		if(((comp) & ROMInfo.DebugComponents) && (level <= ROMInfo.DebugLevel))	\
+		{																			\
+			RT_PRINTK fmt;															\
+		}
+
+#define ODM_RT_ASSERT(pDM_Odm, expr, fmt)											\
+		if(!(expr)) {																	\
+			DbgPrint( "Assertion failed! %s at ......\n", #expr);								\
+			DbgPrint( "      ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__);			\
+			RT_PRINTK fmt;															\
+			ASSERT(FALSE);															\
+		}
+#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); }
+#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); }
+#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); }
+
+#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)							\
+			if(((comp) & ROMInfo.DebugComponents) && (level <= ROMInfo.DebugLevel))	\
+			{																		\
+				int __i;																\
+				pu1Byte	__ptr = (pu1Byte)ptr;											\
+				DbgPrint("[ODM] ");													\
+				DbgPrint(title_str);													\
+				DbgPrint(" ");														\
+				for( __i=0; __i<6; __i++ )												\
+					DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-");						\
+				DbgPrint("\n");														\
+			}
+#else
+#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)
+#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)
+#define ODM_RT_ASSERT(pDM_Odm, expr, fmt)
+#define ODM_dbg_enter()
+#define ODM_dbg_exit()
+#define ODM_dbg_trace(str)
+#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)
+#endif
+
+
+VOID 
+ODM_InitDebugSetting(
+	IN		PDM_ODM_T		pDM_Odm
+	);
+
+
+
+#if 0
+#if DBG
+#define DbgPrint printk
+
+#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)								\
+			{																		\
+				char			*szTitle = _TitleString;									\
+				pu1Byte		pbtHexData = _HexData;									\
+				u4Byte		u4bHexDataLen = _HexDataLen;							\
+				u4Byte		__i;														\
+				DbgPrint("%s", szTitle);													\
+				for (__i=0;__i<u4bHexDataLen;__i++)									\
+				{																	\
+					if ((__i & 15) == 0) 												\
+					{																\
+						DbgPrint("\n");												\
+					}																\
+					DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? "  " : " ") );		\
+				}																	\
+				DbgPrint("\n");														\
+			}
+
+// RT_PRINT_XXX macros: implemented for debugging purpose.
+// Added by Annie, 2005-11-21.
+#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)			\
+			if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel))	\
+			{																		\
+				int __i;																\
+				pu1Byte	ptr = (pu1Byte)_HexData;										\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				for( __i=0; __i<(int)_HexDataLen; __i++ )								\
+				{																	\
+					DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?"  ":" ");			\
+					if (((__i + 1) % 16) == 0)	DbgPrint("\n");							\
+				}																	\
+				DbgPrint("\n");														\
+			}
+
+#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)								\
+			if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel))	\
+			{																		\
+				int __i;																\
+				pu1Byte	ptr = (pu1Byte)_Ptr;											\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				DbgPrint(" ");															\
+				for( __i=0; __i<6; __i++ )												\
+					DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-");							\
+				DbgPrint("\n");														\
+			}
+
+#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)					\
+			if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel))	\
+			{																		\
+				int __i, __j;															\
+				pu1Byte	ptr = (pu1Byte)_Ptr;											\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				DbgPrint("\n");														\
+				for( __i=0; __i<(int)_AddNum; __i++ )									\
+				{																	\
+					for( __j=0; __j<6; __j++ )											\
+						DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-");				\
+					DbgPrint("\n");													\
+				}																	\
+			}
+
+// Added by Annie, 2005-11-22.
+#define	MAX_STR_LEN	64
+#define	PRINTABLE(_ch)	(_ch>=' ' &&_ch<='~' )	// I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
+
+#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)							\
+			if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel))	\
+			{																		\
+				int		__i;															\
+				u1Byte	buffer[MAX_STR_LEN];											\
+				int	length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ;				\
+				PlatformZeroMemory( buffer, MAX_STR_LEN );							\
+				PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length );						\
+				for( __i=0; __i<MAX_STR_LEN; __i++ )									\
+				{																	\
+					if( !PRINTABLE(buffer[__i]) )	buffer[__i] = '?';						\
+				}																	\
+				buffer[length] = '\0';													\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				DbgPrint(": %d, <%s>\n", _Len, buffer);									\
+			}
+			
+#else	// of #if DBG
+#define DbgPrint(...)	
+#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
+#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
+#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
+#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
+#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
+#endif	// of #if DBG
+
+#endif	
+
+
+#if 0
+/* Define debug print header for every service module.*/
+typedef struct tag_ODM_DBGP_Service_Module_Header_Name_Structure
+{
+	const char 	*pMANS;
+	const char 	*pRTOS;
+	const char 	*pALM;
+	const char 	*pPEM;
+	const char 	*pCMPK;
+	const char 	*pRAPD;
+	const char 	*pTXPB;
+	const char 	*pQUMG;
+}ODM_DBGP_HEAD_T;
+
+
+/* Define different debug flag for dedicated service modules in debug flag array. */
+// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
+typedef enum tag_ODM_DBGP_Flag_Type_Definition
+{
+	ODM_FTX				= 0,
+	ODM_FRX				,	
+	ODM_FPHY				,
+	ODM_FPWR				,
+	ODM_FDM				,
+	ODM_FC2H				,
+	ODM_FBT				,
+	ODM_DBGP_TYPE_MAX
+}ODM_DBGP_FLAG_E;
+
+
+// Define TX relative debug bit				--> FTX
+#define		ODM_TX_DESC			BIT0
+#define		ODM_TX_DESC_TID		BIT1
+#define		ODM_TX_PATH			BIT2
+
+// Define RX relative debug  bit				--> FRX
+#define		ODM_RX_DATA				BIT0	
+#define		ODM_RX_PHY_STS			BIT1
+#define		ODM_RX_PHY_SS				BIT2
+#define		ODM_RX_PHY_SQ				BIT3
+#define		ODM_RX_PHY_ASTS			BIT4
+#define		ODM_RX_ERR_LEN			BIT5
+#define		ODM_RX_DEFRAG				BIT6
+#define		ODM_RX_ERR_RATE			BIT7
+#define		ODM_RX_PATH				BIT8
+#define		ODM_RX_BEACON				BIT9
+
+// Define PHY-BB/RF/MAC check module bit		--> FPHY
+#define		ODM_PHY_BBR				BIT0
+#define		ODM_PHY_BBW				BIT1
+#define		ODM_PHY_RFR				BIT2
+#define		ODM_PHY_RFW				BIT3
+#define		ODM_PHY_MACR				BIT4
+#define		ODM_PHY_MACW				BIT5
+#define		ODM_PHY_ALLR				BIT6
+#define		ODM_PHY_ALLW				BIT7
+#define		ODM_PHY_TXPWR			BIT8
+#define		ODM_PHY_PWRDIFF			BIT9
+#define		ODM_PHY_SICR				BIT10
+#define		ODM_PHY_SICW				BIT11
+
+
+
+
+extern	u4Byte ODM_GlobalDebugLevel;
+
+
+#if DBG
+extern	u8Byte ODM_GlobalDebugComponents;
+#endif
+#endif
+#if 0
+
+//-----------------------------------------------------------------------------
+//	Define the debug levels
+//
+//	1.	DBG_TRACE and DBG_LOUD are used for normal cases.
+//	So that, they can help SW engineer to develope or trace states changed 
+//	and also help HW enginner to trace every operation to and from HW, 
+//	e.g IO, Tx, Rx. 
+//
+//	2.	DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, 
+//	which help us to debug SW or HW.
+//
+//-----------------------------------------------------------------------------
+//
+//	Never used in a call to ODM_RT_TRACE(pDM_Odm,)!
+//
+#define DBG_OFF					0
+
+//
+//	Deprecated! Don't use it! 
+//	TODO: fix related debug message!
+//
+//#define DBG_SEC					1
+
+//
+//	Fatal bug. 
+//	For example, Tx/Rx/IO locked up, OS hangs, memory access violation, 
+//	resource allocation failed, unexpected HW behavior, HW BUG and so on.
+//
+#define DBG_SERIOUS				2
+
+//
+//	Abnormal, rare, or unexpeted cases.
+//	For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
+//
+#define DBG_WARNING				3
+
+//
+//	Normal case with useful information about current SW or HW state. 
+//	For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, 
+//	SW protocol state change, dynamic mechanism state change and so on.
+//
+#define DBG_LOUD				4
+
+//
+//	Normal case with detail execution flow or information.
+//
+#define DBG_TRACE				5
+
+
+
+//-----------------------------------------------------------------------------
+// Define the tracing components
+//
+//-----------------------------------------------------------------------------
+#define COMP_TRACE				BIT0		// For function call tracing.
+#define COMP_DBG				BIT1		// Only for temporary debug message.
+#define COMP_INIT				BIT2		// during driver initialization / halt / reset.
+#define COMP_OID_QUERY				BIT3		// Query OID.
+#define COMP_OID_SET				BIT4		// Set OID.
+#define COMP_RECV				BIT5		// Reveive part data path.
+#define COMP_SEND				BIT6		// Send part path.
+#define COMP_IO					BIT7		// I/O Related. Added by Annie, 2006-03-02.
+#define COMP_POWER				BIT8		// 802.11 Power Save mode or System/Device Power state related.
+#define COMP_MLME				BIT9		// 802.11 link related: join/start BSS, leave BSS.
+#define COMP_SCAN				BIT10	// For site survey.
+#define COMP_SYSTEM				BIT11	// For general platform function.
+#define COMP_SEC				BIT12	// For Security.
+#define COMP_AP					BIT13	// For AP mode related.
+#define COMP_TURBO				BIT14	// For Turbo Mode related. By Annie, 2005-10-21.
+#define COMP_QOS				BIT15	// For QoS.
+#define COMP_AUTHENTICATOR			BIT16	// For AP mode Authenticator. Added by Annie, 2006-01-30.
+#define COMP_BEACON				BIT17	// For Beacon related, by rcnjko.
+#define COMP_ANTENNA				BIT18	// For Antenna diversity related, by rcnjko. 
+#define COMP_RATE				BIT19	// For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS				0x00000080	// Event handling
+#define COMP_EVENTS				BIT20	// Event handling
+#define COMP_FPGA				BIT21	// For FPGA verfication 
+#define COMP_RM					BIT22	// For Radio Measurement. 
+#define COMP_MP					BIT23	// For mass production test, by shien chang, 2006.07.13
+#define COMP_RXDESC				BIT24	// Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
+#define COMP_CKIP				BIT25	// For CCX 1 S13: CKIP. Added by Annie, 2006-08-14.
+#define COMP_DIG				BIT26	// For DIG, 2006.09.25, by rcnjko.
+#define COMP_TXAGC				BIT27	// For Tx power, 060928, by rcnjko. 
+#define COMP_HIPWR				BIT28	// For High Power Mechanism, 060928, by rcnjko. 
+#define COMP_HALDM				BIT29	// For HW Dynamic Mechanism, 061010, by rcnjko. 
+#define COMP_RSNA				BIT30	// For RSNA IBSS , 061201, by CCW. 
+#define COMP_INDIC				BIT31	// For link indication
+#define COMP_LED				BIT32	// For LED.
+#define COMP_RF					BIT33	// For RF.
+//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
+//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
+//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
+
+#define COMP_HT					BIT34	// For 802.11n HT related information. by Emily 2006-8-11
+#define COMP_POWER_TRACKING			BIT35	//FOR 8190 TX POWER TRACKING
+#define COMP_RX_REORDER				BIT36	// 8190 Rx Reorder
+#define COMP_AMSDU				BIT37	// For A-MSDU Debugging
+#define COMP_WPS				BIT38   //WPS Debug Message 
+#define COMP_RATR				BIT39	
+#define COMP_RESET				BIT40
+// For debug command to print on dbgview!!
+#define COMP_CMD				BIT41
+#define COMP_EFUSE				BIT42
+#define COMP_MESH_INTERWORKING 			BIT43
+#define COMP_CCX				BIT44	//CCX Debug Flag
+#define	COMP_IOCTL				BIT45	// IO Control
+#define COMP_GP					BIT46	// For generic parser.
+#define COMP_TXAGG				BIT47
+#define COMP_HVL                            	BIT48     // For Ndis 6.2 Context Swirch and Hardware Virtualiztion Layer
+#define COMP_TEST				BIT49
+#define COMP_BB_POWERSAVING	BIT50
+#define COMP_SWAS				BIT51	// For SW Antenna Switch
+#define COMP_P2P				BIT52
+#define COMP_MUX				BIT53
+#define COMP_FUNC				BIT54
+#define COMP_TDLS				BIT55
+#define COMP_OMNIPEEK			BIT56
+#define COMP_DUALMACSWITCH	BIT60	// 2010/12/27 Add for Dual mac mode debug
+#define COMP_EASY_CONCURRENT	BIT61	// 2010/12/27 Add for easy cncurrent mode debug
+#define COMP_PSD				BIT63	//2011/3/9 Add for WLAN PSD for BT AFH
+
+#define COMP_DFS                                BIT62
+
+#define	COMP_ALL				UINT64_C(0xFFFFFFFFFFFFFFFF) // All components
+// For debug print flag to use
+/*------------------------------Define structure----------------------------*/
+/* 2007/07/13 MH  *//*------For DeBuG Print modeue------*/
+
+/* Defnie structure to store different debug flag variable. Every debug flag 
+     is a UINT32 integer and you can assign 32 different events. */
+typedef struct tag_DBGP_Debug_Flag_Structure
+{
+	u4Byte	Mans;			/* Main Scheduler module. */
+	u4Byte	Rtos;			/* RTOS module. */
+	u4Byte	Alarm;		/* Alarm module. */	
+	u4Byte	Pm;			/* Performance monitor module. */	
+}DBGP_FLAG_T;
+
+/* Define debug print header for every service module.*/
+typedef struct tag_DBGP_Service_Module_Header_Name_Structure
+{
+	const char 	*pMANS;
+	const char 	*pRTOS;
+	const char 	*pALM;
+	const char 	*pPEM;
+	const char 	*pCMPK;
+	const char 	*pRAPD;
+	const char 	*pTXPB;
+	const char 	*pQUMG;
+}DBGP_HEAD_T;
+
+
+/* Define different debug flag for dedicated service modules in debug flag array. */
+// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
+typedef enum tag_DBGP_Flag_Type_Definition
+{
+	FQoS				= 0,	
+	FTX					= 1,
+	FRX					= 2,	
+	FSEC				= 3,
+	FMGNT				= 4,
+	FMLME				= 5,
+	FRESOURCE			= 6,
+	FBEACON				= 7,
+	FISR				= 8,
+	FPHY				= 9,
+	FMP					= 10,
+	FEEPROM			= 11,
+	FPWR				= 12,
+	FDM					= 13,
+	FDBG_CTRL			= 14,
+	FC2H				= 15,
+	FBT					= 16,
+	FINIT				= 17,
+	FIOCTL				= 18,
+	FSHORT_CUT			= 19,
+	DBGP_TYPE_MAX
+}DBGP_FLAG_E;
+
+
+// Define Qos Relative debug flag bit		--> FQoS
+#define		QoS_INIT			BIT0
+#define		QoS_VISTA			BIT1
+
+// Define TX relative debug bit				--> FTX
+#define		TX_DESC			BIT0
+#define		TX_DESC_TID		BIT1
+#define		TX_PATH			BIT2
+
+// Define RX relative debug  bit				--> FRX
+#define		RX_DATA				BIT0	
+#define		RX_PHY_STS				BIT1
+#define		RX_PHY_SS				BIT2
+#define		RX_PHY_SQ				BIT3
+#define		RX_PHY_ASTS			BIT4
+#define		RX_ERR_LEN			BIT5
+#define		RX_DEFRAG			BIT6
+#define		RX_ERR_RATE			BIT7
+#define		RX_PATH				BIT8
+#define		RX_BEACON				BIT9
+
+// Define Security relative debug  bit			--> FSEC
+
+// Define MGNT relative debug bit			--> FMGNT
+
+// Define MLME relative debug bit				--> FMLME
+#define		MEDIA_STS			BIT0
+#define		LINK_STS			BIT1
+
+// Define OS resource check module bit		--> FRESOURCE
+#define		OS_CHK				BIT0
+
+// Define beacon content check module bit		--> FBEACON
+#define		BCN_SHOW			BIT0
+#define		BCN_PEER			BIT1
+
+// Define ISR/IMR check module bit		--> FISR
+#define		ISR_CHK				BIT0
+
+// Define PHY-BB/RF/MAC check module bit		--> FPHY
+#define		PHY_BBR				BIT0
+#define		PHY_BBW				BIT1
+#define		PHY_RFR				BIT2
+#define		PHY_RFW				BIT3
+#define		PHY_MACR				BIT4
+#define		PHY_MACW				BIT5
+#define		PHY_ALLR				BIT6
+#define		PHY_ALLW				BIT7
+#define		PHY_TXPWR				BIT8
+#define		PHY_PWRDIFF			BIT9
+#define		PHY_SICR				BIT10
+#define		PHY_SICW				BIT11
+
+// Define MPT driver check module bit		--> FMP
+#define		MP_RX					BIT0
+#define		MP_SWICH_CH			BIT1
+
+// Define EEPROM and EFUSE  check module bit		--> FEEPROM
+#define		EEPROM_W					BIT0
+#define		EFUSE_PG					BIT1
+#define		EFUSE_READ_ALL			BIT2
+#define		EFUSE_ANALYSIS				BIT3
+#define		EFUSE_PG_DETAIL			BIT4
+
+// Define power save  check module bit		--> FPWR
+#define		LPS					BIT0
+#define		IPS					BIT1
+#define		PWRSW				BIT2
+#define		PWRHW				BIT3
+#define		PWRHAL				BIT4
+
+// Define Dynamic Mechanism check module bit		--> FDM
+#define		WA_IOT				BIT0
+#define		DM_PWDB			BIT1
+#define		DM_Monitor			BIT2
+#define		DM_DIG				BIT3
+#define		DM_EDCA_Turbo		BIT4
+#define		DM_BT30			BIT5
+
+// Define Dbg Control module bit		--> FDBG_CTRL
+#define		DBG_CTRL_TRACE			BIT0
+#define		DBG_CTRL_INBAND_NOISE	BIT1
+
+// Define FW C2H Cmd check module bit		--> FC2H
+#define		C2H_Summary				BIT0
+#define		C2H_PacketData				BIT1
+#define		C2H_ContentData			BIT2
+// Define BT Cmd check module bit		--> FBT
+#define		BT_TRACE					BIT0
+#define		BT_RFPoll					BIT1
+
+// Define init check for module bit		--> FINIT
+#define		INIT_EEPROM				BIT0
+#define		INIT_TxPower				BIT1
+#define		INIT_IQK					BIT2
+#define		INIT_RF						BIT3
+
+// Define IOCTL Cmd check module bit		--> FIOCTL
+// section 1 : IRP related
+#define		IOCTL_IRP						BIT0
+#define		IOCTL_IRP_DETAIL				BIT1
+#define		IOCTL_IRP_STATISTICS			BIT2
+#define		IOCTL_IRP_HANDLE				BIT3
+// section 2 : HCI command/event
+#define		IOCTL_BT_HCICMD				BIT8
+#define		IOCTL_BT_HCICMD_DETAIL		BIT9
+#define		IOCTL_BT_HCICMD_EXT			BIT10
+#define		IOCTL_BT_EVENT					BIT11
+#define		IOCTL_BT_EVENT_DETAIL			BIT12
+#define		IOCTL_BT_EVENT_PERIODICAL		BIT13
+// section 3 : BT tx/rx data and throughput
+#define		IOCTL_BT_TX_ACLDATA			BIT16
+#define		IOCTL_BT_TX_ACLDATA_DETAIL	BIT17
+#define		IOCTL_BT_RX_ACLDATA			BIT18
+#define		IOCTL_BT_RX_ACLDATA_DETAIL	BIT19
+#define		IOCTL_BT_TP					BIT20
+// section 4 : BT connection state machine.
+#define 		IOCTL_STATE					BIT21	
+#define		IOCTL_BT_LOGO					BIT22
+// section 5 : BT function trace
+#define		IOCTL_CALLBACK_FUN			BIT24
+#define		IOCTL_PARSE_BT_PKT			BIT25
+#define		IOCTL_BT_TX_PKT				BIT26
+#define		IOCTL_BT_FLAG_MON				BIT27
+
+//
+// Define init check for module bit		--> FSHORT_CUT
+// 2011/07/20 MH Add for short but definition.
+//
+#define		SHCUT_TX				BIT0
+#define		SHCUT_RX				BIT1
+
+
+/* 2007/07/13 MH  *//*------For DeBuG Print modeue------*/
+/*------------------------------Define structure----------------------------*/
+
+
+/*------------------------Export Marco Definition---------------------------*/
+#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
+#define RT_PRINTK(fmt, args...)    printk( "%s(): " fmt, __FUNCTION__, ## args);
+
+#if DBG
+#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt)											\
+		if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel))	\
+		{																	\
+			RT_PRINTK fmt;													\
+		}
+
+#define RT_TRACE_F(comp, level, fmt)											\
+		if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel))	\
+		{																	\
+			RT_PRINTK fmt;													\
+		}
+
+#define RT_ASSERT(expr,fmt)													\
+		if(!(expr)) {															\
+			printk( "Assertion failed! %s at ......\n", #expr);							\
+			printk( "      ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__);	\
+		}
+#define dbg_enter() { printk("==> %s\n", __FUNCTION__); }
+#define dbg_exit() { printk("<== %s\n", __FUNCTION__); }
+#define dbg_trace(str) { printk("%s:%s\n", __FUNCTION__, str); }
+#else
+#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt)
+#define RT_TRACE_F(comp, level, fmt)
+#define RT_ASSERT(expr, fmt)
+#define dbg_enter()
+#define dbg_exit()
+#define dbg_trace(str)
+#endif
+
+#if DBG
+#define DbgPrint printk
+
+#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)								\
+			{																		\
+				char			*szTitle = _TitleString;									\
+				pu1Byte		pbtHexData = _HexData;									\
+				u4Byte		u4bHexDataLen = _HexDataLen;							\
+				u4Byte		__i;														\
+				DbgPrint("%s", szTitle);													\
+				for (__i=0;__i<u4bHexDataLen;__i++)									\
+				{																	\
+					if ((__i & 15) == 0) 												\
+					{																\
+						DbgPrint("\n");												\
+					}																\
+					DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? "  " : " ") );		\
+				}																	\
+				DbgPrint("\n");														\
+			}
+
+// RT_PRINT_XXX macros: implemented for debugging purpose.
+// Added by Annie, 2005-11-21.
+#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)			\
+			if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel))	\
+			{																		\
+				int __i;																\
+				pu1Byte	ptr = (pu1Byte)_HexData;										\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				for( __i=0; __i<(int)_HexDataLen; __i++ )								\
+				{																	\
+					DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?"  ":" ");			\
+					if (((__i + 1) % 16) == 0)	DbgPrint("\n");							\
+				}																	\
+				DbgPrint("\n");														\
+			}
+
+#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)								\
+			if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel))	\
+			{																		\
+				int __i;																\
+				pu1Byte	ptr = (pu1Byte)_Ptr;											\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				DbgPrint(" ");															\
+				for( __i=0; __i<6; __i++ )												\
+					DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-");							\
+				DbgPrint("\n");														\
+			}
+
+#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)					\
+			if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel))	\
+			{																		\
+				int __i, __j;															\
+				pu1Byte	ptr = (pu1Byte)_Ptr;											\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				DbgPrint("\n");														\
+				for( __i=0; __i<(int)_AddNum; __i++ )									\
+				{																	\
+					for( __j=0; __j<6; __j++ )											\
+						DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-");				\
+					DbgPrint("\n");													\
+				}																	\
+			}
+
+// Added by Annie, 2005-11-22.
+#define	MAX_STR_LEN	64
+#define	PRINTABLE(_ch)	(_ch>=' ' &&_ch<='~' )	// I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
+
+#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)							\
+			if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel))	\
+			{																		\
+				int		__i;															\
+				u1Byte	buffer[MAX_STR_LEN];											\
+				int	length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ;				\
+				PlatformZeroMemory( buffer, MAX_STR_LEN );							\
+				PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length );						\
+				for( __i=0; __i<MAX_STR_LEN; __i++ )									\
+				{																	\
+					if( !PRINTABLE(buffer[__i]) )	buffer[__i] = '?';						\
+				}																	\
+				buffer[length] = '\0';													\
+				DbgPrint("Rtl819x: ");													\
+				DbgPrint(_TitleString);												\
+				DbgPrint(": %d, <%s>\n", _Len, buffer);									\
+			}
+			
+#else	// of #if DBG
+#define DbgPrint(...)	
+#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
+#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
+#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
+#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
+#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
+#endif	// of #if DBG
+
+
+
+#endif	// #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
+
+#define		DEBUG_PRINT				1
+
+// Please add new OS's print API by yourself
+
+//#if (RT_PLATFORM==PLATFORM_WINDOWS) 
+#if (DEBUG_PRINT == 1) && DBG
+#define	RT_DISP(dbgtype, dbgflag, printstr)\
+{\
+	if (DBGP_Type[dbgtype] & dbgflag)\
+	{\
+		DbgPrint printstr;\
+	}\
+}
+
+#define	RT_DISP_ADDR(dbgtype, dbgflag, printstr, _Ptr)\
+{\
+	if (DBGP_Type[dbgtype] & dbgflag)\
+	{\
+				int __i;						\
+				pu1Byte	ptr = (pu1Byte)_Ptr;	\
+				DbgPrint printstr;				\
+				DbgPrint(" ");					\
+				for( __i=0; __i<6; __i++ )		\
+					DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-");		\
+				DbgPrint("\n");							\
+	}\
+}
+
+#define RT_DISP_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)\
+{\
+	if (DBGP_Type[dbgtype] & dbgflag)\
+	{\
+		int __i;									\
+		pu1Byte	ptr = (pu1Byte)_HexData;			\
+		DbgPrint(_TitleString);					\
+		for( __i=0; __i<(int)_HexDataLen; __i++ )	\
+		{										\
+			DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?"  ":" ");\
+			if (((__i + 1) % 16) == 0)	DbgPrint("\n");\
+		}										\
+		DbgPrint("\n");							\
+	}\
+}
+
+#define FunctionIn(_comp)		ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("==========> %s\n",  __FUNCTION__))
+#define FunctionOut(_comp)		ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("<========== %s\n",  __FUNCTION__))
+
+
+#else
+
+#define	RT_DISP(dbgtype, dbgflag, printstr)
+#define	RT_DISP_ADDR(dbgtype, dbgflag, printstr, _Ptr)
+#define   RT_DISP_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)
+
+#define FunctionIn(_comp)
+#define FunctionOut(_comp)
+#endif
+/*------------------------Export Marco Definition---------------------------*/
+
+
+/*------------------------Export global variable----------------------------*/
+extern	u4Byte			DBGP_Type[DBGP_TYPE_MAX];
+extern	DBGP_HEAD_T	DBGP_Head;
+
+/*------------------------Export global variable----------------------------*/
+
+
+/*--------------------------Exported Function prototype---------------------*/
+extern	void	DBGP_Flag_Init(void);
+extern	void	DBG_PrintAllFlag(void);
+extern	void	DBG_PrintAllComp(void);
+extern	void	DBG_PrintFlagEvent(u1Byte	DbgFlag);
+extern	void	DBG_DumpMem(const u1Byte DbgComp, 
+							const u1Byte DbgLevel, 
+							pu1Byte pMem, 
+							u2Byte Len);
+
+/*--------------------------Exported Function prototype---------------------*/
+
+
+
+
+
+
+
+
+
+extern u4Byte GlobalDebugLevel;
+extern u8Byte GlobalDebugComponents;
+
+
+#endif
+
+
+#endif	// __ODM_DBG_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_interface.h

@@ -0,0 +1,413 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef	__ODM_INTERFACE_H__
+#define __ODM_INTERFACE_H__
+
+
+
+//
+// =========== Constant/Structure/Enum/... Define
+//
+
+
+
+//
+// =========== Macro Define
+//
+
+#define _reg_all(_name)			ODM_##_name
+#define _reg_ic(_name, _ic)		ODM_##_name##_ic
+#define _bit_all(_name)			BIT_##_name
+#define _bit_ic(_name, _ic)		BIT_##_name##_ic
+
+// _cat: implemented by Token-Pasting Operator.
+#if 0
+#define _cat(_name, _ic_type, _func)								\
+	( 															\
+		_func##_all(_name)										\
+	)
+#endif
+
+/*===================================
+
+#define ODM_REG_DIG_11N		0xC50
+#define ODM_REG_DIG_11AC	0xDDD
+
+ODM_REG(DIG,_pDM_Odm)
+=====================================*/
+
+#define _reg_11N(_name)			ODM_REG_##_name##_11N 
+#define _reg_11AC(_name)		ODM_REG_##_name##_11AC
+#define _bit_11N(_name)			ODM_BIT_##_name##_11N 
+#define _bit_11AC(_name)		ODM_BIT_##_name##_11AC
+
+#ifdef __ECOS
+#define _rtk_cat(_name, _ic_type, _func)		\
+	( 															\
+		((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name):		\
+		_func##_11AC(_name)									\
+	)
+#else
+
+#define _cat(_name, _ic_type, _func)									\
+	( 															\
+		((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name):		\
+		_func##_11AC(_name)									\
+	)
+#endif
+/* 
+// only sample code
+//#define _cat(_name, _ic_type, _func)									\
+//	( 															\
+//		((_ic_type) & ODM_RTL8192C)? _func##_ic(_name, _8192C):		\
+//		((_ic_type) & ODM_RTL8192D)? _func##_ic(_name, _8192D):		\
+//		((_ic_type) & ODM_RTL8192S)? _func##_ic(_name, _8192S):		\
+//		((_ic_type) & ODM_RTL8723A)? _func##_ic(_name, _8723A):		\
+//		((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E):		\
+//		_func##_ic(_name, _8195)									\
+//	)
+*/
+
+// _name: name of register or bit.
+// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" 
+//        gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType.
+#ifdef __ECOS
+#define ODM_REG(_name, _pDM_Odm)	_rtk_cat(_name, _pDM_Odm->SupportICType, _reg)
+#define ODM_BIT(_name, _pDM_Odm)	_rtk_cat(_name, _pDM_Odm->SupportICType, _bit)
+#else
+#define ODM_REG(_name, _pDM_Odm)	_cat(_name, _pDM_Odm->SupportICType, _reg)
+#define ODM_BIT(_name, _pDM_Odm)	_cat(_name, _pDM_Odm->SupportICType, _bit)
+#endif
+typedef enum _ODM_H2C_CMD 
+{
+	/*ODM_H2C_RSSI_REPORT = 0,
+	ODM_H2C_PSD_RESULT=1,	
+	ODM_H2C_PathDiv = 2,
+	ODM_H2C_WIFI_CALIBRATION = 3,
+	ODM_H2C_IQ_CALIBRATION = 4,
+	ODM_H2C_RA_PARA_ADJUST=5,
+	ODM_MAX_H2CCMD*/
+	PHYDM_H2C_TXBF			= 0x41,
+	ODM_H2C_RSSI_REPORT		= 0x42,
+	ODM_H2C_IQ_CALIBRATION	= 0x45,
+	ODM_H2C_RA_PARA_ADJUST	= 0x47,
+	PHYDM_H2C_DYNAMIC_TX_PATH = 0x48,
+	PHYDM_H2C_FW_TRACE_EN	= 0x49,
+	ODM_H2C_WIFI_CALIBRATION	= 0x6d,
+	PHYDM_H2C_MU				= 0x4a,
+	ODM_MAX_H2CCMD
+}ODM_H2C_CMD;
+
+
+//
+// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem.
+// Suggest HW team to use thread instead of workitem. Windows also support the feature.
+//
+#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
+typedef  void *PRT_WORK_ITEM ;
+typedef  void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE;
+typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext);
+
+#if 0
+typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE;
+
+typedef struct _RT_WORK_ITEM
+{
+	
+	RT_WORKITEM_HANDLE			Handle;			// Platform-dependent handle for this workitem, e.g. Ndis Workitem object.
+	PVOID						Adapter;		// Pointer to Adapter object.
+	PVOID						pContext;		// Parameter to passed to CallBackFunc(). 
+	RT_WORKITEM_CALL_BACK		CallbackFunc;	// Callback function of the workitem.
+	u1Byte						RefCount;		// 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled. 
+	PVOID						pPlatformExt;	// Pointer to platform-dependent extension.	
+	BOOLEAN						bFree;
+	char						szID[36];		// An identity string of this workitem.
+}RT_WORK_ITEM, *PRT_WORK_ITEM;
+
+#endif
+
+
+#endif
+
+//
+// =========== Extern Variable ??? It should be forbidden.
+//
+
+
+//
+// =========== EXtern Function Prototype
+//
+
+
+u1Byte
+ODM_Read1Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr
+	);
+
+u2Byte
+ODM_Read2Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr
+	);
+
+u4Byte
+ODM_Read4Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr
+	);
+
+VOID
+ODM_Write1Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr,
+	IN	u1Byte			Data
+	);
+
+VOID
+ODM_Write2Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr,
+	IN	u2Byte			Data
+	);
+
+VOID
+ODM_Write4Byte(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u4Byte			RegAddr,
+	IN	u4Byte			Data
+	);
+
+VOID
+ODM_SetMACReg(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	u4Byte		RegAddr,
+	IN	u4Byte		BitMask,
+	IN	u4Byte		Data
+	);
+
+u4Byte 
+ODM_GetMACReg(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	u4Byte		RegAddr,
+	IN	u4Byte		BitMask
+	);
+
+VOID
+ODM_SetBBReg(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	u4Byte		RegAddr,
+	IN	u4Byte		BitMask,
+	IN	u4Byte		Data
+	);
+
+u4Byte 
+ODM_GetBBReg(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	u4Byte		RegAddr,
+	IN	u4Byte		BitMask
+	);
+
+VOID
+ODM_SetRFReg(	
+	IN 	PDM_ODM_T			pDM_Odm,
+	IN	ODM_RF_RADIO_PATH_E	eRFPath,
+	IN	u4Byte				RegAddr,
+	IN	u4Byte				BitMask,
+	IN	u4Byte				Data
+	);
+
+u4Byte 
+ODM_GetRFReg(	
+	IN 	PDM_ODM_T			pDM_Odm,
+	IN	ODM_RF_RADIO_PATH_E	eRFPath,
+	IN	u4Byte				RegAddr,
+	IN	u4Byte				BitMask
+	);
+
+
+//
+// Memory Relative Function.
+//
+VOID
+ODM_AllocateMemory(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	OUT	PVOID		*pPtr,
+	IN	u4Byte		length
+	);
+VOID
+ODM_FreeMemory(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	OUT	PVOID		pPtr,
+	IN	u4Byte		length
+	);
+
+VOID
+ODM_MoveMemory(	
+	IN 	PDM_ODM_T	pDM_Odm,
+	OUT PVOID		pDest,
+	IN  PVOID		pSrc,
+	IN  u4Byte		Length
+	);
+
+s4Byte ODM_CompareMemory(
+	IN 	PDM_ODM_T	pDM_Odm,
+	IN	PVOID           pBuf1,
+      IN	PVOID           pBuf2,
+      IN	u4Byte          length
+       );
+
+void ODM_Memory_Set
+	(IN 	PDM_ODM_T	pDM_Odm,
+		IN  PVOID	pbuf,
+		IN  s1Byte	value,
+		IN  u4Byte	length);
+	
+//
+// ODM MISC-spin lock relative API.
+//
+#if( DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL|ODM_CE))
+VOID
+ODM_AcquireSpinLock(	
+	IN 	PDM_ODM_T			pDM_Odm,
+	IN	RT_SPINLOCK_TYPE	type
+	);
+
+VOID
+ODM_ReleaseSpinLock(	
+	IN 	PDM_ODM_T			pDM_Odm,
+	IN	RT_SPINLOCK_TYPE	type
+	);
+#endif
+
+//
+// ODM MISC-workitem relative API.
+//
+VOID
+ODM_InitializeWorkItem(	
+	IN 	PDM_ODM_T					pDM_Odm,
+	IN	PRT_WORK_ITEM				pRtWorkItem,
+	IN	RT_WORKITEM_CALL_BACK		RtWorkItemCallback,
+	IN	PVOID						pContext,
+	IN	const char*					szID
+	);
+
+VOID
+ODM_StartWorkItem(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	);
+
+VOID
+ODM_StopWorkItem(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	);
+
+VOID
+ODM_FreeWorkItem(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	);
+
+VOID
+ODM_ScheduleWorkItem(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	);
+
+VOID
+ODM_IsWorkItemScheduled(	
+	IN	PRT_WORK_ITEM	pRtWorkItem
+	);
+
+//
+// ODM Timer relative API.
+//
+VOID
+ODM_StallExecution(	
+	IN	u4Byte	usDelay
+	);
+
+VOID
+ODM_delay_ms(IN u4Byte	ms);
+
+
+
+VOID
+ODM_delay_us(IN u4Byte	us);
+
+VOID
+ODM_sleep_ms(IN u4Byte	ms);
+
+VOID
+ODM_sleep_us(IN u4Byte	us);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP|ODM_ADSL))
+VOID
+ODM_SetTimer(	
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	PRT_TIMER 		pTimer, 
+	IN	u4Byte 			msDelay
+	);
+
+VOID
+ODM_InitializeTimer(
+	IN 	PDM_ODM_T			pDM_Odm,
+	IN	PRT_TIMER 			pTimer, 
+	IN	RT_TIMER_CALL_BACK	CallBackFunc, 
+	IN	PVOID				pContext,
+	IN	const char*			szID
+	);
+
+VOID
+ODM_CancelTimer(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	PRT_TIMER		pTimer
+	);
+
+VOID
+ODM_ReleaseTimer(
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	PRT_TIMER		pTimer
+	);
+#endif
+
+//
+// ODM FW relative API.
+//
+VOID
+ODM_FillH2CCmd(
+	IN	PDM_ODM_T		pDM_Odm,
+	IN	u1Byte 			ElementID,
+	IN	u4Byte 			CmdLen,
+	IN	pu1Byte			pCmdBuffer
+);
+
+u8Byte
+ODM_GetCurrentTime(	
+	IN 	PDM_ODM_T		pDM_Odm
+	);
+u8Byte
+ODM_GetProgressingTime(	
+	IN 	PDM_ODM_T		pDM_Odm,
+	IN	u8Byte			Start_Time
+	);
+
+#endif	// __ODM_INTERFACE_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_precomp.h

@@ -0,0 +1,349 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef	__ODM_PRECOMP_H__
+#define __ODM_PRECOMP_H__
+
+#include "phydm_types.h"
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#include "Precomp.h"		// We need to include mp_precomp.h due to batch file setting.
+
+#else
+
+#define		TEST_FALG___		1
+
+#endif
+
+//2 Config Flags and Structs - defined by each ODM Type
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	#include "../8192cd_cfg.h"
+	#include "../odm_inc.h"
+
+	#include "../8192cd.h"
+	#include "../8192cd_util.h"
+	#ifdef _BIG_ENDIAN_
+	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_BIG
+	#else
+	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_LITTLE
+	#endif
+
+	#ifdef AP_BUILD_WORKAROUND
+	#include "../8192cd_headers.h"
+	#include "../8192cd_debug.h"		
+	#endif
+	
+#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
+	// Flags
+	#include "../8192cd_cfg.h"		// OUTSRC needs ADSL config flags.
+	#include "../odm_inc.h"			// OUTSRC needs some extra flags.
+	// Data Structure
+	#include "../common_types.h"	// OUTSRC and rtl8192cd both needs basic type such as UINT8 and BIT0.
+	#include "../8192cd.h"			// OUTSRC needs basic ADSL struct definition.
+	#include "../8192cd_util.h"		// OUTSRC needs basic I/O function.
+	#ifdef _BIG_ENDIAN_
+	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_BIG
+	#else
+	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_LITTLE
+	#endif
+
+	#ifdef ADSL_AP_BUILD_WORKAROUND
+	// NESTED_INC: Functions defined outside should not be included!! Marked by Annie, 2011-10-14.
+	#include "../8192cd_headers.h"
+	#include "../8192cd_debug.h"	
+	#endif	
+	
+#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE)
+#define BEAMFORMING_SUPPORT 0
+#elif (DM_ODM_SUPPORT_TYPE ==ODM_IOT)
+#define BEAMFORMING_SUPPORT 0
+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	#include "mp_precomp.h"
+	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_LITTLE
+#endif
+
+
+//2 Hardware Parameter Files
+
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+#if (RTL8192C_SUPPORT==1)
+	#include "rtl8192c/Hal8192CEFWImg_AP.h"
+	#include "rtl8192c/Hal8192CEPHYImg_AP.h"
+	#include "rtl8192c/Hal8192CEMACImg_AP.h"
+#endif
+#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
+	#include "rtl8192c/Hal8192CEFWImg_ADSL.h"
+	#include "rtl8192c/Hal8192CEPHYImg_ADSL.h"
+	#include "rtl8192c/Hal8192CEMACImg_ADSL.h"
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	#if(RTL8192CE_SUPPORT ==1)
+	#include "rtl8192c/Hal8192CEFWImg_CE.h"
+	#include "rtl8192c/Hal8192CEPHYImg_CE.h"
+	#include "rtl8192c/Hal8192CEMACImg_CE.h"
+	#endif
+	
+	#if(RTL8192CU_SUPPORT ==1)
+	#include "rtl8192c/Hal8192CUFWImg_CE.h"
+	#include "rtl8192c/Hal8192CUPHYImg_CE.h"
+	#include "rtl8192c/Hal8192CUMACImg_CE.h"
+	#endif
+	
+	#if(RTL8192DE_SUPPORT ==1)
+	#include "rtl8192d/Hal8192DEFWImg_CE.h"
+	#include "rtl8192d/Hal8192DEPHYImg_CE.h"
+	#include "rtl8192d/Hal8192DEMACImg_CE.h"	
+	#endif
+	
+	#if(RTL8192DU_SUPPORT ==1)
+	#include "rtl8192d/Hal8192DUFWImg_CE.h"
+	#include "rtl8192d/Hal8192DUPHYImg_CE.h"
+	#include "rtl8192d/Hal8192DUMACImg_CE.h"
+	#endif
+	
+	#if(RTL8723AS_SUPPORT==1)
+	#include "rtl8723a/Hal8723SHWImg_CE.h"
+	#endif
+	
+	#if(RTL8723AU_SUPPORT==1)
+	#include "rtl8723a/Hal8723UHWImg_CE.h"
+	#endif
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+#endif
+
+
+//2 OutSrc Header Files
+#if (RTL8188E_SUPPORT==1)
+// Old ODM 
+#include "rtl8188e\odm.h"
+#include "rtl8188e\odm_HWConfig.h"
+#include "rtl8188e\odm_debug.h"
+#include "rtl8188e\odm_RegDefine11AC.h"
+#include "rtl8188e\odm_RegDefine11N.h"
+#include "rtl8188e\odm_interface.h"
+#include "rtl8188e\odm_reg.h"
+#include "rtl8188e\Hal8188EAdaptivity.h"
+#else
+// new ODM
+#include "phydm.h"
+#include "phydm_HWConfig.h"
+#include "phydm_debug.h"
+#include "phydm_RegDefine11AC.h"
+#include "phydm_RegDefine11N.h"
+#include "phydm_AntDiv.h"
+#include "phydm_EdcaTurboCheck.h"
+#include "phydm_DIG.h"
+#include "PhyDM_Adaptivity.h"
+#include "phydm_PathDiv.h"
+#include "phydm_RaInfo.h"
+#include "phydm_DynamicBBPowerSaving.h"
+#include "phydm_DynamicTxPower.h"
+#include "phydm_CfoTracking.h"
+#include "phydm_NoiseMonitor.h"
+#include "phydm_interface.h"
+#include "phydm_reg.h"
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+#if (RTL8192C_SUPPORT==1)
+	#include "rtl8192c/HalDMOutSrc8192C_AP.h"
+#endif
+#if (RTL8188E_SUPPORT==1)
+		#include "rtl8188e/Hal8188ERateAdaptive.h"//for  RA,Power training
+#endif
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
+	#include "rtl8192c/HalDMOutSrc8192C_ADSL.h"
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	//#include "hal_com.h"
+	#include "HalPhyRf.h"
+	#if (RTL8192C_SUPPORT==1) 
+		#ifdef CONFIG_INTEL_PROXIM
+		#include "../proxim/intel_proxim.h"	
+		#endif	
+		#include  "rtl8192c/HalDMOutSrc8192C_CE.h"
+		#include <rtl8192c_hal.h>
+	#endif
+	
+	#if (RTL8192D_SUPPORT==1)
+		#include  "rtl8192d/HalDMOutSrc8192D_CE.h"
+		#include  "rtl8192d_hal.h"
+	#endif
+	
+	#if (RTL8723A_SUPPORT==1)
+		#include "rtl8192c/HalDMOutSrc8192C_CE.h" //for IQK,LCK,Power-tracking
+		#include "../rtl8723a/rtl8723a_hal.h"  
+	#endif
+	
+	#if (RTL8188E_SUPPORT==1)
+		#include "rtl8188e/HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking
+		#include "rtl8188e/Hal8188ERateAdaptive.h"//for  RA,Power training
+		#include "../rtl8188e/rtl8188e_hal.h"  	
+	#endif
+
+	#if (RTL8192E_SUPPORT==1)
+		#include "rtl8192e/HalPhyRf_8192e.h"//for IQK,LCK,Power-tracking		
+		#include "rtl8192e_hal.h"  			
+	#endif
+
+	#if (RTL8812A_SUPPORT==1)
+		#include "rtl8812a/HalPhyRf_8812A.h"//for IQK,LCK,Power-tracking
+		#include "rtl8812a_hal.h"
+	#endif
+
+	#if (RTL8821A_SUPPORT==1)
+		#include "rtl8821a/HalPhyRf_8821A.h"//for IQK,LCK,Power-tracking
+		#include "rtl8812a/HalPhyRf_8812A.h"//for IQK,LCK,Power-tracking
+		#include "rtl8812a_hal.h"		
+	#endif
+
+	#if (RTL8723B_SUPPORT==1)
+		#include "rtl8723b/HalPhyRf_8723B.h"//for IQK,LCK,Power-tracking
+		#include "rtl8723b_hal.h"
+	#endif
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+	#include "HalPhyRf.h"
+	#if (RTL8195A_SUPPORT==1)
+		#include "rtl8195a/HalPhyRf_8195A.h"//for IQK,LCK,Power-tracking
+		#include "rtl8195a_hal.h"
+	#endif
+
+	#if (RTL8711B_SUPPORT==1)
+        #include "rtl8711b/HalPhyRf_8711b.h"//for IQK,LCK,Power-tracking
+        #include "rtl8711b_hal.h"
+   	 #endif
+#endif
+
+
+#if (RTL8192C_SUPPORT==1) 
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+#include "rtl8192c/Hal8192CHWImg_MAC.h"
+#include "rtl8192c/Hal8192CHWImg_RF.h"
+#include "rtl8192c/Hal8192CHWImg_BB.h"
+#include "rtl8192c/Hal8192CHWImg_FW.h"
+#endif
+#include "rtl8192c/phydm_RTL8192C.h"
+#endif
+#if (RTL8192D_SUPPORT==1) 
+#include "rtl8192d/phydm_RTL8192D.h"
+#endif
+
+#if (RTL8723A_SUPPORT==1) 
+#include "rtl8723a/HalHWImg8723A_MAC.h"
+#include "rtl8723a/HalHWImg8723A_RF.h"
+#include "rtl8723a/HalHWImg8723A_BB.h"
+#include "rtl8723a/HalHWImg8723A_FW.h"
+#include "rtl8723a/phydm_RegConfig8723A.h"
+#endif
+
+#if (RTL8188E_SUPPORT==1) 
+#include "rtl8188e/HalHWImg8188E_MAC.h"
+#include "rtl8188e/HalHWImg8188E_RF.h"
+#include "rtl8188e/HalHWImg8188E_BB.h"
+#include "rtl8188e/HalHWImg8188E_FW.h"
+#include "rtl8188e/Hal8188EReg.h"
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+#include "rtl8188e/HalPhyRf_8188e.h"
+#endif
+
+#if (TEST_CHIP_SUPPORT == 1) 
+#include "rtl8188e/HalHWImg8188E_TestChip_MAC.h"
+#include "rtl8188e/HalHWImg8188E_TestChip_RF.h"
+#include "rtl8188e/HalHWImg8188E_TestChip_BB.h"
+#endif
+
+
+#include "rtl8188e/odm_RegConfig8188E.h"
+#include "rtl8188e/odm_RTL8188E.h"
+#endif
+
+#if (RTL8192E_SUPPORT==1) 
+#include "rtl8192e/HalHWImg8192E_MAC.h"
+#include "rtl8192e/HalHWImg8192E_RF.h"
+#include "rtl8192e/HalHWImg8192E_BB.h"
+#include "rtl8192e/HalHWImg8192E_FW.h"
+#include "rtl8192e/Hal8192EReg.h"
+#include "rtl8192e/phydm_RegConfig8192E.h"
+#include "rtl8192e/phydm_RTL8192E.h"
+#endif
+
+#if (RTL8723B_SUPPORT==1) 
+#include "rtl8723b/HalHWImg8723B_MAC.h"
+#include "rtl8723b/HalHWImg8723B_RF.h"
+#include "rtl8723b/HalHWImg8723B_BB.h"
+#include "rtl8723b/HalHWImg8723B_FW.h"
+#include "rtl8723b/HalHWImg8723B_MP.h"
+#include "rtl8723b/Hal8723BReg.h"
+#include "rtl8723b/phydm_RTL8723B.h"
+#include "rtl8723b/phydm_RegConfig8723B.h"
+#endif
+
+#if (RTL8812A_SUPPORT==1) 
+#include "rtl8812a/HalHWImg8812A_MAC.h"
+#include "rtl8812a/HalHWImg8812A_RF.h"
+#include "rtl8812a/HalHWImg8812A_BB.h"
+#include "rtl8812a/HalHWImg8812A_FW.h"
+#include "rtl8812a/phydm_RegConfig8812A.h"
+#include "rtl8812a/phydm_RTL8812A.h"
+#endif
+
+
+#if (RTL8821A_SUPPORT==1) 
+#include "rtl8821a/HalHWImg8821A_MAC.h"
+#include "rtl8821a/HalHWImg8821A_RF.h"
+#include "rtl8821a/HalHWImg8821A_BB.h"
+#include "rtl8821a/HalHWImg8821A_FW.h"
+#include "rtl8821a/phydm_RegConfig8821A.h"
+#include "rtl8821a/phydm_RTL8821A.h"
+#endif
+
+#if (RTL8195A_SUPPORT==1) 
+#include "rtl8195a/halhwimg8195a_mac.h"
+#include "rtl8195a/halhwimg8195a_rf.h"
+#include "rtl8195a/halhwimg8195a_bb.h"
+#include "rtl8195a/Hal8195AReg.h"
+#include "rtl8195a/phydm_RTL8195A.h"
+#include "rtl8195a/phydm_RegConfig8195A.h"
+#include "rtl8195a/ROM_RTL8195A_PHYDM.h"
+#include "rtl8195a/Hal8195ARateAdaptive.h"
+#endif
+
+#if (RTL8711B_SUPPORT==1) 
+#include "rtl8711b/HalHWImg8711B_MAC.h"
+#include "rtl8711b/HalHWImg8711B_RF.h"
+#include "rtl8711b/HalHWImg8711B_BB.h"
+#include "rtl8711b/HalHWImg8711B_FW.h"
+#include "rtl8711b/HalHWImg8711B_MP.h"
+#include "rtl8711b/Hal8711BReg.h"
+#include "rtl8711b/phydm_RTL8711B.h"
+#include "rtl8711b/phydm_RegConfig8711B.h"
+#include "rtl8711b/ROM_RTL8711B_PHYDM.h"
+#include "rtl8711b/Hal8711BRateAdaptive.h"
+#endif
+
+#endif	// __ODM_PRECOMP_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_reg.h

@@ -0,0 +1,208 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+//============================================================
+// File Name: odm_reg.h
+//
+// Description:
+//
+// This file is for general register definition.
+//
+//
+//============================================================
+#ifndef	__HAL_ODM_REG_H__
+#define __HAL_ODM_REG_H__
+
+//
+// Register Definition
+//
+
+//MAC REG
+#define	ODM_BB_RESET					0x002
+#define	ODM_DUMMY						0x4fe
+#define	RF_T_METER_OLD				0x24
+#define	RF_T_METER_NEW				0x42
+
+#define	ODM_EDCA_VO_PARAM			0x500
+#define	ODM_EDCA_VI_PARAM			0x504
+#define	ODM_EDCA_BE_PARAM			0x508
+#define	ODM_EDCA_BK_PARAM			0x50C
+#define	ODM_TXPAUSE					0x522
+
+//BB REG
+#define	ODM_FPGA_PHY0_PAGE8			0x800
+#define	ODM_PSD_SETTING				0x808
+#define	ODM_AFE_SETTING				0x818
+#define	ODM_TXAGC_B_6_18				0x830
+#define	ODM_TXAGC_B_24_54			0x834
+#define	ODM_TXAGC_B_MCS32_5			0x838
+#define	ODM_TXAGC_B_MCS0_MCS3		0x83c
+#define	ODM_TXAGC_B_MCS4_MCS7		0x848
+#define	ODM_TXAGC_B_MCS8_MCS11		0x84c
+#define	ODM_ANALOG_REGISTER			0x85c
+#define	ODM_RF_INTERFACE_OUTPUT		0x860
+#define	ODM_TXAGC_B_MCS12_MCS15	0x868
+#define	ODM_TXAGC_B_11_A_2_11		0x86c
+#define	ODM_AD_DA_LSB_MASK			0x874
+#define	ODM_ENABLE_3_WIRE			0x88c
+#define	ODM_PSD_REPORT				0x8b4
+#define	ODM_R_ANT_SELECT				0x90c
+#define	ODM_CCK_ANT_SELECT			0xa07
+#define	ODM_CCK_PD_THRESH			0xa0a
+#define	ODM_CCK_RF_REG1				0xa11
+#define	ODM_CCK_MATCH_FILTER			0xa20
+#define	ODM_CCK_RAKE_MAC				0xa2e
+#define	ODM_CCK_CNT_RESET			0xa2d
+#define	ODM_CCK_TX_DIVERSITY			0xa2f
+#define	ODM_CCK_FA_CNT_MSB			0xa5b
+#define	ODM_CCK_FA_CNT_LSB			0xa5c
+#define	ODM_CCK_NEW_FUNCTION		0xa75
+#define	ODM_OFDM_PHY0_PAGE_C		0xc00
+#define	ODM_OFDM_RX_ANT				0xc04
+#define	ODM_R_A_RXIQI					0xc14
+#define	ODM_R_A_AGC_CORE1			0xc50
+#define	ODM_R_A_AGC_CORE2			0xc54
+#define	ODM_R_B_AGC_CORE1			0xc58
+#define	ODM_R_AGC_PAR					0xc70
+#define	ODM_R_HTSTF_AGC_PAR			0xc7c
+#define	ODM_TX_PWR_TRAINING_A		0xc90
+#define	ODM_TX_PWR_TRAINING_B		0xc98
+#define	ODM_OFDM_FA_CNT1				0xcf0
+#define	ODM_OFDM_PHY0_PAGE_D		0xd00
+#define	ODM_OFDM_FA_CNT2				0xda0
+#define	ODM_OFDM_FA_CNT3				0xda4
+#define	ODM_OFDM_FA_CNT4				0xda8
+#define	ODM_TXAGC_A_6_18				0xe00
+#define	ODM_TXAGC_A_24_54			0xe04
+#define	ODM_TXAGC_A_1_MCS32			0xe08
+#define	ODM_TXAGC_A_MCS0_MCS3		0xe10
+#define	ODM_TXAGC_A_MCS4_MCS7		0xe14
+#define	ODM_TXAGC_A_MCS8_MCS11		0xe18
+#define	ODM_TXAGC_A_MCS12_MCS15		0xe1c
+
+//RF REG
+#define	ODM_GAIN_SETTING				0x00
+#define	ODM_CHANNEL					0x18
+#define	ODM_RF_T_METER				0x24
+#define	ODM_RF_T_METER_92D			0x42
+#define	ODM_RF_T_METER_88E			0x42
+#define	ODM_RF_T_METER_92E			0x42
+#define	ODM_RF_T_METER_8812			0x42
+
+//Ant Detect Reg
+#define	ODM_DPDT						0x300
+
+//PSD Init
+#define	ODM_PSDREG					0x808
+
+//92D Path Div
+#define	PATHDIV_REG					0xB30
+#define	PATHDIV_TRI					0xBA0
+
+
+//
+// Bitmap Definition
+//
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))
+// TX AGC 
+#define		rTxAGC_A_CCK11_CCK1_JAguar	0xc20
+#define		rTxAGC_A_Ofdm18_Ofdm6_JAguar	0xc24
+#define		rTxAGC_A_Ofdm54_Ofdm24_JAguar	0xc28
+#define		rTxAGC_A_MCS3_MCS0_JAguar	0xc2c
+#define		rTxAGC_A_MCS7_MCS4_JAguar	0xc30
+#define		rTxAGC_A_MCS11_MCS8_JAguar	0xc34
+#define		rTxAGC_A_MCS15_MCS12_JAguar	0xc38
+#define		rTxAGC_A_Nss1Index3_Nss1Index0_JAguar	0xc3c
+#define		rTxAGC_A_Nss1Index7_Nss1Index4_JAguar	0xc40
+#define		rTxAGC_A_Nss2Index1_Nss1Index8_JAguar	0xc44
+#define		rTxAGC_A_Nss2Index5_Nss2Index2_JAguar	0xc48
+#define		rTxAGC_A_Nss2Index9_Nss2Index6_JAguar	0xc4c
+#if defined(CONFIG_WLAN_HAL_8814AE)
+#define		rTxAGC_A_MCS19_MCS16_JAguar	0xcd8
+#define		rTxAGC_A_MCS23_MCS20_JAguar	0xcdc
+#define		rTxAGC_A_Nss3Index3_Nss3Index0_JAguar	0xce0
+#define		rTxAGC_A_Nss3Index7_Nss3Index4_JAguar	0xce4
+#define		rTxAGC_A_Nss3Index9_Nss3Index8_JAguar	0xce8
+#endif
+#define		rTxAGC_B_CCK11_CCK1_JAguar	0xe20
+#define		rTxAGC_B_Ofdm18_Ofdm6_JAguar	0xe24
+#define		rTxAGC_B_Ofdm54_Ofdm24_JAguar	0xe28
+#define		rTxAGC_B_MCS3_MCS0_JAguar	0xe2c
+#define		rTxAGC_B_MCS7_MCS4_JAguar	0xe30
+#define		rTxAGC_B_MCS11_MCS8_JAguar	0xe34
+#define		rTxAGC_B_MCS15_MCS12_JAguar	0xe38
+#define		rTxAGC_B_Nss1Index3_Nss1Index0_JAguar	0xe3c
+#define		rTxAGC_B_Nss1Index7_Nss1Index4_JAguar	0xe40
+#define		rTxAGC_B_Nss2Index1_Nss1Index8_JAguar	0xe44
+#define		rTxAGC_B_Nss2Index5_Nss2Index2_JAguar	0xe48
+#define		rTxAGC_B_Nss2Index9_Nss2Index6_JAguar	0xe4c
+#if defined(CONFIG_WLAN_HAL_8814AE)
+#define		rTxAGC_B_MCS19_MCS16_JAguar	0xed8
+#define		rTxAGC_B_MCS23_MCS20_JAguar	0xedc
+#define		rTxAGC_B_Nss3Index3_Nss3Index0_JAguar	0xee0
+#define		rTxAGC_B_Nss3Index7_Nss3Index4_JAguar	0xee4
+#define		rTxAGC_B_Nss3Index9_Nss3Index8_JAguar	0xee8
+#define		rTxAGC_C_CCK11_CCK1_JAguar	0x1820
+#define		rTxAGC_C_Ofdm18_Ofdm6_JAguar	0x1824
+#define		rTxAGC_C_Ofdm54_Ofdm24_JAguar	0x1828
+#define		rTxAGC_C_MCS3_MCS0_JAguar	0x182c
+#define		rTxAGC_C_MCS7_MCS4_JAguar	0x1830
+#define		rTxAGC_C_MCS11_MCS8_JAguar	0x1834
+#define		rTxAGC_C_MCS15_MCS12_JAguar	0x1838
+#define		rTxAGC_C_Nss1Index3_Nss1Index0_JAguar	0x183c
+#define		rTxAGC_C_Nss1Index7_Nss1Index4_JAguar	0x1840
+#define		rTxAGC_C_Nss2Index1_Nss1Index8_JAguar	0x1844
+#define		rTxAGC_C_Nss2Index5_Nss2Index2_JAguar	0x1848
+#define		rTxAGC_C_Nss2Index9_Nss2Index6_JAguar	0x184c
+#define		rTxAGC_C_MCS19_MCS16_JAguar	0x18d8
+#define		rTxAGC_C_MCS23_MCS20_JAguar	0x18dc
+#define		rTxAGC_C_Nss3Index3_Nss3Index0_JAguar	0x18e0
+#define		rTxAGC_C_Nss3Index7_Nss3Index4_JAguar	0x18e4
+#define		rTxAGC_C_Nss3Index9_Nss3Index8_JAguar	0x18e8
+#define		rTxAGC_D_CCK11_CCK1_JAguar	0x1a20
+#define		rTxAGC_D_Ofdm18_Ofdm6_JAguar	0x1a24
+#define		rTxAGC_D_Ofdm54_Ofdm24_JAguar	0x1a28
+#define		rTxAGC_D_MCS3_MCS0_JAguar	0x1a2c
+#define		rTxAGC_D_MCS7_MCS4_JAguar	0x1a30
+#define		rTxAGC_D_MCS11_MCS8_JAguar	0x1a34
+#define		rTxAGC_D_MCS15_MCS12_JAguar	0x1a38
+#define		rTxAGC_D_Nss1Index3_Nss1Index0_JAguar	0x1a3c
+#define		rTxAGC_D_Nss1Index7_Nss1Index4_JAguar	0x1a40
+#define		rTxAGC_D_Nss2Index1_Nss1Index8_JAguar	0x1a44
+#define		rTxAGC_D_Nss2Index5_Nss2Index2_JAguar	0x1a48
+#define		rTxAGC_D_Nss2Index9_Nss2Index6_JAguar	0x1a4c
+#define		rTxAGC_D_MCS19_MCS16_JAguar	0x1ad8
+#define		rTxAGC_D_MCS23_MCS20_JAguar	0x1adc
+#define		rTxAGC_D_Nss3Index3_Nss3Index0_JAguar	0x1ae0
+#define		rTxAGC_D_Nss3Index7_Nss3Index4_JAguar	0x1ae4
+#define		rTxAGC_D_Nss3Index9_Nss3Index8_JAguar	0x1ae8
+#endif
+
+#define		bTxAGC_byte0_Jaguar	0xff
+#define		bTxAGC_byte1_Jaguar	0xff00
+#define		bTxAGC_byte2_Jaguar	0xff0000
+#define		bTxAGC_byte3_Jaguar	0xff000000
+#endif
+
+#define	BIT_FA_RESET					BIT0
+
+
+
+#endif
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_types.h

@@ -0,0 +1,442 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __ODM_TYPES_H__
+#define __ODM_TYPES_H__
+
+#define ODM_RATEMCS15_SG		0x1c
+#define ODM_RATEMCS32			0x20
+
+
+// CCK Rates, TxHT = 0
+#define ODM_RATE1M				0x00
+#define ODM_RATE2M				0x01
+#define ODM_RATE5_5M			0x02
+#define ODM_RATE11M				0x03
+// OFDM Rates, TxHT = 0
+#define ODM_RATE6M				0x04
+#define ODM_RATE9M				0x05
+#define ODM_RATE12M				0x06
+#define ODM_RATE18M				0x07
+#define ODM_RATE24M				0x08
+#define ODM_RATE36M				0x09
+#define ODM_RATE48M				0x0A
+#define ODM_RATE54M				0x0B
+// MCS Rates, TxHT = 1
+#define ODM_RATEMCS0			0x0C
+#define ODM_RATEMCS1			0x0D
+#define ODM_RATEMCS2			0x0E
+#define ODM_RATEMCS3			0x0F
+#define ODM_RATEMCS4			0x10
+#define ODM_RATEMCS5			0x11
+#define ODM_RATEMCS6			0x12
+#define ODM_RATEMCS7			0x13
+#define ODM_RATEMCS8			0x14
+#define ODM_RATEMCS9			0x15
+#define ODM_RATEMCS10			0x16
+#define ODM_RATEMCS11			0x17
+#define ODM_RATEMCS12			0x18
+#define ODM_RATEMCS13			0x19
+#define ODM_RATEMCS14			0x1A
+#define ODM_RATEMCS15			0x1B
+#define ODM_RATEMCS16			0x1C
+#define ODM_RATEMCS17			0x1D
+#define ODM_RATEMCS18			0x1E
+#define ODM_RATEMCS19			0x1F
+#define ODM_RATEMCS20			0x20
+#define ODM_RATEMCS21			0x21
+#define ODM_RATEMCS22			0x22
+#define ODM_RATEMCS23			0x23
+#define ODM_RATEMCS24			0x24
+#define ODM_RATEMCS25			0x25
+#define ODM_RATEMCS26			0x26
+#define ODM_RATEMCS27			0x27
+#define ODM_RATEMCS28			0x28
+#define ODM_RATEMCS29			0x29
+#define ODM_RATEMCS30			0x2A
+#define ODM_RATEMCS31			0x2B
+#define ODM_RATEVHTSS1MCS0		0x2C
+#define ODM_RATEVHTSS1MCS1		0x2D
+#define ODM_RATEVHTSS1MCS2		0x2E
+#define ODM_RATEVHTSS1MCS3		0x2F
+#define ODM_RATEVHTSS1MCS4		0x30
+#define ODM_RATEVHTSS1MCS5		0x31
+#define ODM_RATEVHTSS1MCS6		0x32
+#define ODM_RATEVHTSS1MCS7		0x33
+#define ODM_RATEVHTSS1MCS8		0x34
+#define ODM_RATEVHTSS1MCS9		0x35
+#define ODM_RATEVHTSS2MCS0		0x36
+#define ODM_RATEVHTSS2MCS1		0x37
+#define ODM_RATEVHTSS2MCS2		0x38
+#define ODM_RATEVHTSS2MCS3		0x39
+#define ODM_RATEVHTSS2MCS4		0x3A
+#define ODM_RATEVHTSS2MCS5		0x3B
+#define ODM_RATEVHTSS2MCS6		0x3C
+#define ODM_RATEVHTSS2MCS7		0x3D
+#define ODM_RATEVHTSS2MCS8		0x3E
+#define ODM_RATEVHTSS2MCS9		0x3F
+#define ODM_RATEVHTSS3MCS0		0x40
+#define ODM_RATEVHTSS3MCS1		0x41
+#define ODM_RATEVHTSS3MCS2		0x42
+#define ODM_RATEVHTSS3MCS3		0x43
+#define ODM_RATEVHTSS3MCS4		0x44
+#define ODM_RATEVHTSS3MCS5		0x45
+#define ODM_RATEVHTSS3MCS6		0x46
+#define ODM_RATEVHTSS3MCS7		0x47
+#define ODM_RATEVHTSS3MCS8		0x48
+#define ODM_RATEVHTSS3MCS9		0x49
+#define ODM_RATEVHTSS4MCS0		0x4A
+#define ODM_RATEVHTSS4MCS1		0x4B
+#define ODM_RATEVHTSS4MCS2		0x4C
+#define ODM_RATEVHTSS4MCS3		0x4D
+#define ODM_RATEVHTSS4MCS4		0x4E
+#define ODM_RATEVHTSS4MCS5		0x4F
+#define ODM_RATEVHTSS4MCS6		0x50
+#define ODM_RATEVHTSS4MCS7		0x51
+#define ODM_RATEVHTSS4MCS8		0x52
+#define ODM_RATEVHTSS4MCS9		0x53
+
+
+//
+// Define Different SW team support
+//
+#define	ODM_AP		 	0x01	//BIT0 
+#define	ODM_ADSL	 	0x02	//BIT1
+#define	ODM_CE		 	0x04	//BIT2
+#define	ODM_WIN		 	0x08	//BIT3
+#define	ODM_IOT		 	0x10	//BIT4
+
+#define	DM_ODM_SUPPORT_TYPE			ODM_IOT
+
+// Deifne HW endian support
+#define	ODM_ENDIAN_BIG	0
+#define	ODM_ENDIAN_LITTLE	1
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#define GET_PDM_ODM(__pAdapter)	((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->DM_OutSrc)))
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_IOT))
+#define GET_PDM_ODM(__pAdapter)	((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->odmpriv)))
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
+#define 	RT_PCI_INTERFACE				1
+#define 	RT_USB_INTERFACE				2
+#define 	RT_SDIO_INTERFACE				3
+#define 	RT_LXBUS_INTERFACE				4
+#endif
+
+typedef enum _HAL_STATUS{
+	HAL_STATUS_SUCCESS,
+	HAL_STATUS_FAILURE,
+	/*RT_STATUS_PENDING,
+	RT_STATUS_RESOURCE,
+	RT_STATUS_INVALID_CONTEXT,
+	RT_STATUS_INVALID_PARAMETER,
+	RT_STATUS_NOT_SUPPORT,
+	RT_STATUS_OS_API_FAILED,*/
+}HAL_STATUS,*PHAL_STATUS;
+
+
+#if( (DM_ODM_SUPPORT_TYPE == ODM_AP) ||(DM_ODM_SUPPORT_TYPE == ODM_ADSL) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
+
+#define		VISTA_USB_RX_REVISE			0
+
+//
+// Declare for ODM spin lock defintion temporarily fro compile pass.
+//
+typedef enum _RT_SPINLOCK_TYPE{
+	RT_TX_SPINLOCK = 1,
+	RT_RX_SPINLOCK = 2,
+	RT_RM_SPINLOCK = 3,
+	RT_CAM_SPINLOCK = 4,
+	RT_SCAN_SPINLOCK = 5,
+	RT_LOG_SPINLOCK = 7, 
+	RT_BW_SPINLOCK = 8,
+	RT_CHNLOP_SPINLOCK = 9,
+	RT_RF_OPERATE_SPINLOCK = 10,
+	RT_INITIAL_SPINLOCK = 11,
+	RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30.
+#if VISTA_USB_RX_REVISE
+	RT_USBRX_CONTEXT_SPINLOCK = 13,
+	RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR
+#endif
+	//Shall we define Ndis 6.2 SpinLock Here ?
+	RT_PORT_SPINLOCK=16,
+	RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09.
+
+	RT_BTData_SPINLOCK=25,
+
+	RT_WAPI_OPTION_SPINLOCK=26,
+	RT_WAPI_RX_SPINLOCK=27,
+
+      // add for 92D CCK control issue  
+	RT_CCK_PAGEA_SPINLOCK = 28,
+	RT_BUFFER_SPINLOCK = 29,
+	RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
+	RT_GEN_TEMP_BUF_SPINLOCK = 31,
+	RT_AWB_SPINLOCK = 32,
+	RT_FW_PS_SPINLOCK = 33,
+	RT_HW_TIMER_SPIN_LOCK = 34,
+	RT_MPT_WI_SPINLOCK = 35,
+	RT_P2P_SPIN_LOCK = 36,	// Protect P2P context
+	RT_DBG_SPIN_LOCK = 37,
+	RT_IQK_SPINLOCK = 38,
+	RT_PENDED_OID_SPINLOCK = 39,
+	RT_CHNLLIST_SPINLOCK = 40,	
+	RT_INDIC_SPINLOCK = 41,	//protect indication	
+}RT_SPINLOCK_TYPE;
+
+#endif
+
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	#define	STA_INFO_T			RT_WLAN_STA
+	#define	PSTA_INFO_T			PRT_WLAN_STA
+
+//    typedef unsigned long		u4Byte,*pu4Byte;
+#define CONFIG_HW_ANTENNA_DIVERSITY 
+#define CONFIG_SW_ANTENNA_DIVERSITY 
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+	// To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
+	#define ADSL_AP_BUILD_WORKAROUND
+	#define AP_BUILD_WORKAROUND
+	//
+#ifdef CONFIG_ANT_SWITCH
+	#define CONFIG_HW_ANTENNA_DIVERSITY 
+	#if ( defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) )
+		#define CONFIG_NOT_SUPPORT_ANTDIV 
+	#elif( !defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) )
+		#define CONFIG_2G_SUPPORT_ANTDIV
+	#elif( defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY) )
+		#define CONFIG_5G_SUPPORT_ANTDIV
+	#elif( !defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY) )
+		#define CONFIG_2G5G_SUPPORT_ANTDIV 
+	#endif
+#endif
+
+	#ifdef AP_BUILD_WORKAROUND
+	#include "../typedef.h"
+	#else
+	typedef void					VOID,*PVOID;
+	typedef unsigned char			BOOLEAN,*PBOOLEAN;
+	typedef unsigned char			u1Byte,*pu1Byte;
+	typedef unsigned short			u2Byte,*pu2Byte;
+	typedef unsigned int			u4Byte,*pu4Byte;
+	typedef unsigned long long		u8Byte,*pu8Byte;
+	typedef char					s1Byte,*ps1Byte;
+	typedef short					s2Byte,*ps2Byte;
+	typedef long					s4Byte,*ps4Byte;
+	typedef long long				s8Byte,*ps8Byte;
+	#endif
+
+	typedef struct rtl8192cd_priv	*prtl8192cd_priv;
+	typedef struct stat_info		STA_INFO_T,*PSTA_INFO_T;
+	typedef struct timer_list		RT_TIMER, *PRT_TIMER;
+	typedef  void *				RT_TIMER_CALL_BACK;
+
+	#define DEV_BUS_TYPE		RT_PCI_INTERFACE
+
+	#define _TRUE				1
+	#define _FALSE				0
+	
+#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
+
+	// To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
+	#define ADSL_AP_BUILD_WORKAROUND
+	#define ADSL_BUILD_WORKAROUND
+	//
+
+	typedef unsigned char			BOOLEAN,*PBOOLEAN;
+	typedef unsigned char			u1Byte,*pu1Byte;
+	typedef unsigned short			u2Byte,*pu2Byte;
+	typedef unsigned int			u4Byte,*pu4Byte;
+	typedef unsigned long long		u8Byte,*pu8Byte;
+	typedef char					s1Byte,*ps1Byte;
+	typedef short					s2Byte,*ps2Byte;
+	typedef long					s4Byte,*ps4Byte;
+	typedef long long				s8Byte,*ps8Byte;
+
+	typedef struct rtl8192cd_priv	*prtl8192cd_priv;
+	typedef struct stat_info		STA_INFO_T,*PSTA_INFO_T;
+	typedef struct timer_list		RT_TIMER, *PRT_TIMER;
+	typedef  void *				RT_TIMER_CALL_BACK;
+	
+	#define DEV_BUS_TYPE		RT_PCI_INTERFACE
+
+	#define _TRUE				1
+	#define _FALSE				0
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	#include <drv_types.h>
+
+#if 0
+	typedef u8					u1Byte, *pu1Byte;
+	typedef u16					u2Byte,*pu2Byte;
+	typedef u32					u4Byte,*pu4Byte;
+	typedef u64					u8Byte,*pu8Byte;
+	typedef s8					s1Byte,*ps1Byte;
+	typedef s16					s2Byte,*ps2Byte;
+	typedef s32					s4Byte,*ps4Byte;
+	typedef s64					s8Byte,*ps8Byte;
+#else
+	#define u1Byte		u8
+	#define pu1Byte 		u8*	
+
+	#define u2Byte 		u16
+	#define pu2Byte 		u16*		
+
+	#define u4Byte 		u32
+	#define pu4Byte 		u32*	
+
+	#define u8Byte 		u64
+	#define pu8Byte 		u64*
+
+	#define s1Byte 		s8
+	#define ps1Byte 		s8*	
+
+	#define s2Byte 		s16
+	#define ps2Byte 		s16*	
+
+	#define s4Byte 		s32
+	#define ps4Byte 		s32*	
+
+	#define s8Byte 		s64
+	#define ps8Byte 		s64*	
+	
+#endif
+	#ifdef CONFIG_USB_HCI
+		#define DEV_BUS_TYPE  	RT_USB_INTERFACE
+	#elif defined(CONFIG_PCI_HCI)
+		#define DEV_BUS_TYPE  	RT_PCI_INTERFACE
+	#elif defined(CONFIG_SDIO_HCI)
+		#define DEV_BUS_TYPE  	RT_SDIO_INTERFACE
+	#elif defined(CONFIG_GSPI_HCI)
+		#define DEV_BUS_TYPE  	RT_SDIO_INTERFACE
+    #elif defined(CONFIG_LX_HCI)
+        #define DEV_BUS_TYPE    RT_PCI_INTERFACE
+	#endif
+	
+
+	#if defined(CONFIG_LITTLE_ENDIAN)	
+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_LITTLE
+	#elif defined (CONFIG_BIG_ENDIAN)
+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_BIG
+	#endif
+	
+	typedef struct timer_list		RT_TIMER, *PRT_TIMER;
+	typedef  void *				RT_TIMER_CALL_BACK;
+	#define	STA_INFO_T			struct sta_info
+	#define	PSTA_INFO_T		struct sta_info *
+		
+
+
+#ifndef TRUE
+	#define TRUE 	_TRUE	
+#endif
+#ifndef FALSE
+	#define FALSE	_FALSE
+#endif
+
+
+	#define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value)
+	#define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value)
+	#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value)
+
+	//define useless flag to avoid compile warning
+	#define	USE_WORKITEM 0
+	#define	FOR_BRAZIL_PRETEST 0
+	#define	FPGA_TWO_MAC_VERIFICATION	0
+	#define	RTL8881A_SUPPORT	0
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+	#include <drv_types.h>
+    
+	#define RA_MASK_PHYDMLIZE_CE	1
+    
+	typedef unsigned char			u1Byte,*pu1Byte;
+	typedef unsigned short			u2Byte,*pu2Byte;
+	typedef unsigned int			u4Byte,*pu4Byte;
+	typedef unsigned long long		u8Byte,*pu8Byte;
+	typedef signed char			s1Byte,*ps1Byte; /* GCC ROM char = unsigned char */
+	typedef signed short			s2Byte,*ps2Byte;
+	typedef signed long			s4Byte,*ps4Byte;
+	typedef long long			s8Byte,*ps8Byte;
+
+	typedef struct sta_info			STA_INFO_T,*PSTA_INFO_T;
+
+	#if defined(CONFIG_GSPI_HCI)
+		#define DEV_BUS_TYPE  	RT_SDIO_INTERFACE
+    #elif defined(CONFIG_LX_HCI)
+        #define DEV_BUS_TYPE    RT_LXBUS_INTERFACE
+	#endif
+	
+	// Array_MP_8195A_TXPWR_LMT[]
+	typedef enum _ODM_PW_LMT_REGULATION_TYPE{
+		PW_LMT_REGU_NULL = 0,
+		PW_LMT_REGU_FCC = 1,
+		PW_LMT_REGU_ETSI = 2,
+		PW_LMT_REGU_MKK = 3,
+		PW_LMT_REGU_WW13 = 4
+	}ODM_PW_LMT_REGULATION_TYPE;
+
+	typedef enum _ODM_PW_LMT_BAND_TYPE{
+		PW_LMT_BAND_NULL = 0,
+		PW_LMT_BAND_2_4G = 1,
+		PW_LMT_BAND_5G = 2
+	}ODM_PW_LMT_BAND_TYPE;
+
+	typedef enum _ODM_PW_LMT_BANDWIDTH_TYPE{
+		PW_LMT_BW_NULL = 0,
+		PW_LMT_BW_20M = 1,
+		PW_LMT_BW_40M = 2,
+		PW_LMT_BW_80M = 3
+	}ODM_PW_LMT_BANDWIDTH_TYPE;
+
+	typedef enum _ODM_PW_LMT_RATESECTION_TYPE{
+		PW_LMT_RS_NULL = 0,
+		PW_LMT_RS_CCK = 1,
+		PW_LMT_RS_OFDM = 2,
+		PW_LMT_RS_HT = 3,
+		PW_LMT_RS_VHT = 4
+	}ODM_PW_LMT_RATESECTION_TYPE;
+
+	typedef enum _ODM_PW_LMT_RFPATH_TYPE{
+		PW_LMT_PH_NULL = 0,
+		PW_LMT_PH_1T = 1,
+		PW_LMT_PH_2T = 2,
+		PW_LMT_PH_3T = 3,
+		PW_LMT_PH_4T = 4
+	}ODM_PW_LMT_RFPATH_TYPE;
+
+    	#if defined(CONFIG_LITTLE_ENDIAN)	
+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_LITTLE
+	#elif defined (CONFIG_BIG_ENDIAN)
+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_BIG
+	#endif
+    
+#endif
+
+#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
+#define COND_ELSE  2
+#define COND_ENDIF 3
+
+#endif // __ODM_TYPES_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rom_odm_interface.h

@@ -0,0 +1,59 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+
+#ifndef	__ROM_ODM_INTERFACE_H__
+#define __ROM_ODM_INTERFACE_H__
+
+#include "hal_api.h"
+
+//
+// =========== Macro Define
+//
+#define ODM_Read1Byte(pDM_Odm, RegAddr) HAL_READ8(WIFI_REG_BASE, RegAddr)
+#define ODM_Read2Byte(pDM_Odm, RegAddr) HAL_READ16(WIFI_REG_BASE, RegAddr)
+#define ODM_Read4Byte(pDM_Odm, RegAddr) HAL_READ32(WIFI_REG_BASE, RegAddr)
+#define ODM_Write1Byte(pDM_Odm, RegAddr, Data) HAL_WRITE8(WIFI_REG_BASE, RegAddr, Data)
+#define ODM_Write2Byte(pDM_Odm, RegAddr, Data) HAL_WRITE16(WIFI_REG_BASE, addr, value)
+#define ODM_Write4Byte(pDM_Odm, RegAddr, Data) HAL_WRITE32(WIFI_REG_BASE, addr, value)
+#if (RTL8195A_SUPPORT == 1)
+#define ODM_GetMACReg(pDM_Odm,RegAddr, BitMask) PHY_QueryBBReg_8195A((pDM_Odm->Adapter), (RegAddr), (BitMask))
+#define ODM_SetMACReg(pDM_Odm, RegAddr, BitMask, Data) PHY_SetBBReg_8195A((pDM_Odm->Adapter), (RegAddr), (BitMask), (Data))
+#define ODM_GetBBReg(pDM_Odm, RegAddr, BitMask) PHY_QueryBBReg_8195A((pDM_Odm->Adapter), (RegAddr), (BitMask))
+#define ODM_SetBBReg(pDM_Odm, RegAddr, BitMask, Data) PHY_SetBBReg_8195A((pDM_Odm->Adapter), (RegAddr), (BitMask), (Data))
+#endif
+
+#if (RTL8711B_SUPPORT ==1)
+#define ODM_GetMACReg(pDM_Odm,RegAddr, BitMask) PHY_QueryBBReg_8711B((pDM_Odm->Adapter), (RegAddr), (BitMask))
+#define ODM_SetMACReg(pDM_Odm, RegAddr, BitMask, Data) PHY_SetBBReg_8711B((pDM_Odm->Adapter), (RegAddr), (BitMask), (Data))
+#define ODM_GetBBReg(pDM_Odm, RegAddr, BitMask) PHY_QueryBBReg_8711B((pDM_Odm->Adapter), (RegAddr), (BitMask))
+#define ODM_SetBBReg(pDM_Odm, RegAddr, BitMask, Data) PHY_SetBBReg_8711B((pDM_Odm->Adapter), (RegAddr), (BitMask), (Data))
+#endif
+//
+// =========== Extern Variable
+//
+
+//
+// =========== EXtern Function Prototype
+//
+
+
+#endif	// __ROM_ODM_INTERFACE_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/Hal8195ARateAdaptive.h

@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __HALCOM_RATE_ADAPTIVE_RAM_H__
+#define __HALCOM_RATE_ADAPTIVE_RAM_H__
+
+#if RATE_ADAPTIVE_SUPPORT
+
+/*--------------------------Define -------------------------------------------*/
+
+#define FIRST_MACID 0 // This is the connection of STA to AP
+// Rate index mapping
+#define RATE_CCK_1M         ODM_RATE1M		
+#define RATE_CCK_2M         ODM_RATE2M		
+#define RATE_CCK_5M         ODM_RATE5_5M	
+#define RATE_CCK_11M        ODM_RATE11M		
+#define RATE_OFDM_6M        ODM_RATE6M		
+#define RATE_OFDM_9M        ODM_RATE9M		
+#define RATE_OFDM_12M       ODM_RATE12M		
+#define RATE_OFDM_18M       ODM_RATE18M		
+#define RATE_OFDM_24M       ODM_RATE24M		
+#define RATE_OFDM_36M       ODM_RATE36M		
+#define RATE_OFDM_48M       ODM_RATE48M		
+#define RATE_OFDM_54M       ODM_RATE54M		
+#define RATE_HT_MCS0        ODM_RATEMCS0	
+#define RATE_HT_MCS1        ODM_RATEMCS1	
+#define RATE_HT_MCS2        ODM_RATEMCS2	
+#define RATE_HT_MCS3        ODM_RATEMCS3	
+#define RATE_HT_MCS4        ODM_RATEMCS4	
+#define RATE_HT_MCS5        ODM_RATEMCS5	
+#define RATE_HT_MCS6        ODM_RATEMCS6	
+#define RATE_HT_MCS7        ODM_RATEMCS7	
+#define RATE_HT_MCS8        ODM_RATEMCS8	
+#define RATE_HT_MCS9        ODM_RATEMCS9	
+#define RATE_HT_MCS10       ODM_RATEMCS10 
+#define RATE_HT_MCS11       ODM_RATEMCS11 
+#define RATE_HT_MCS12       ODM_RATEMCS12 
+#define RATE_HT_MCS13       ODM_RATEMCS13 
+#define RATE_HT_MCS14       ODM_RATEMCS14 
+#define RATE_HT_MCS15       ODM_RATEMCS15 
+
+#define MACID_NUM                   128
+
+
+
+// TX report format
+#define TXRPT_SIZE          16
+//offset 0
+#define TXRPT_DATARATE      (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6)
+#define TXRPT_SGI           BIT7
+//offset 1
+#define TXRPT_PWRSTS        (BIT0|BIT1|BIT2)
+#define TXRPT_TRYNESSCNT    (BIT3|BIT4|BIT5|BIT6)
+#define TXRPT_TRYRATE       BIT7
+//offset 2
+#define TXRPT_TRYRESULT     BIT6
+#define TXRPT_TRYFINISH     BIT7
+//offset 3
+#define TXRPT_PAUSERPT      BIT6
+#define TXRPT_RESETRPT      BIT7
+//offset 4
+
+//offset 5
+#define TXRPT_BW            (BIT0|BIT1)
+#define TXRPT_PKTDROP       BIT2
+
+
+
+#define RATE_UP 1
+#define RATE_DOWN 2
+
+#define  RSSI_TH1 45
+#define  RSSI_TH2 25
+
+#define PERENTRY        27
+#define RETRYSIZE       5
+#define RATESIZE        20
+#define RAMASK_SIZE         8
+
+#define SS_PT_TH_High   66
+#define SS_PT_TH_low    57
+#define SS_PT_off       48
+#define SS_RA_INIT_RATE_RSSI       30
+#define STEP_DROP       1
+#define CONFIG_SGI      0
+#define TRY_WAITING   10
+
+// RA mask
+#define Mask_length_REG         8
+#define Rate_id_NUM             9 // 6 rate id from reg
+#define ARFB_table_NUM          7
+
+#define TRY_NESS_CNT_IDX_SIZE   16
+
+/*------------------------------Define Enum-----------------------------------*/
+typedef enum _RTL8195_RATEID_IDX_ {
+    MODE_BGN_40M_2SS    = 0,
+    MODE_BGN_40M_1SS    = 1,
+    MODE_BGN_20M_2SS_BN = 2,
+    MODE_BGN_20M_1SS_BN = 3,
+    MODE_GN_N2SS        = 4,
+    MODE_GN_N1SS        = 5,
+    MODE_BG             = 6,
+    MODE_G              = 7,
+    MODE_B              = 8
+} RTL8195_RATEID_IDX, *PRTL8195_RATEID_IDX;
+
+typedef enum _VHT_HT_SWITCH_ {
+    TYPE_HT             = 0,
+    TYPE_VHT            = 1,
+    TYPE_MIX1           = 2,
+    TYPE_MIX2           = 3
+} VHT_SEL_SWITCH, *PVHT_SEL_SWITCH;
+
+/*--------------------------Define MACRO--------------------------------------*/
+#define TRYING_DISABLE          0
+#define TRYING_ENABLE           1
+
+//RA MASK: INIT_RATE_MASK
+
+//if VHT_HT_SWITCH = 1, it means VHT. 
+//Bit[51:12] : VHT 1SS ~ VHT 4SS
+//if VHT_HT_SWITCH = 0, it means HT. 
+//Bit[43:12] : HT 1SS ~ HT4SS
+
+//offset6
+//#define VHT_HT_SWITCH       BIT4
+
+
+// H2C CMD
+//offset0
+#define H2CID13_MACID           0x7F
+//offset1
+#define H2CID13_RATEID          0x1F
+#define H2CID13_SGI             BIT7
+
+
+
+//offset2
+#define H2CID13_BW              (BIT0|BIT1)
+#define H2CID13_enldpc          BIT2
+#define H2CID13_NOUPDATE        BIT3
+#define H2CID13_VHT_EN          (BIT5|BIT4)
+#define H2CID13_DISPT           BIT6
+#define H2CID13_DISRA           BIT7
+
+//H2C AP_Req_Tx_Rpt
+#define H2CID43_RTY_OK_TOTAL BIT0
+#define H2CID43_RTY_CNT_MACID   BIT1
+
+
+//RAInfo
+#define MASK_RA_ULDL_STATE      BIT0
+#define MASK_RA_STBC_STATE      BIT1
+#define MASK_RA_LDPC_CAP_STATE  BIT2
+#define MASK_RA_SHORTCUT_STATE  BIT3
+#define MASK_RA_SHORTCUT_FLAG   BIT4
+#define MASK_RA_INIT_RATE_RSSI_STATE BIT5
+#define MASK_RA_BF_STATE		BIT6
+#define MASK_RA_DELAY_RATE		BIT7
+
+
+
+#define RA_ULDL_STATE_SHT       0
+#define RA_STBC_STATE_SHT	    1
+#define RA_LDPC_CAP_STATE_SHT	2
+#define RA_SHORTCUT_STATE_SHT   3
+#define RA_SHORTCUT_FLAG_SHT    4
+#define RA_INIT_RATE_RSSI_SHT	  5
+#define RA_BF_STATE_SHT			6
+#define RA_DELAY_RATE_SHT		7
+
+/*------------------------Export global variable------------------------------*/
+//2 Rate Adaptive
+//HW Statistic
+//extern MEMTYPE_XDATA u16        TOTAL[MACID_NUM];
+//extern MEMTYPE_XDATA u1Byte         DROP[MACID_NUM];
+//extern MEMTYPE_XDATA u16        RTY[MACID_NUM][5];
+
+//extern MEMTYPE_XDATA STAINFO_RA stainfo_ra[MACID_NUM];
+//extern MEMTYPE_XDATA u16        Nsc[MACID_NUM];
+//extern MEMTYPE_XDATA u1Byte         RSSI[MACID_NUM];  // add by Gary
+//extern MEMTYPE_XDATA u1Byte         BUPDATE[MACID_NUM]; 
+
+/*------------------------------Function declaration--------------------------*/
+VOID
+InitBBNHM(
+    void
+);
+
+VOID
+BBNHM(
+    void
+);
+
+VOID 
+ODM_InitRAInfo(
+    IN   PDM_ODM_T		pDM_Odm 
+);
+
+VOID 
+H2CHDL_Set_MACID_Config(
+	IN   	PDM_ODM_T		pDM_Odm,
+	IN	u1Byte 			*pbuf
+);
+
+VOID
+H2CHDL_SetRssiSingle(
+    u1Byte  *pbuf
+);
+
+
+VOID
+H2CHDL_APReqTxrpt(
+    u1Byte  *pbuf
+);
+
+VOID
+H2CHDL_InitRateCollect(
+    u1Byte *pbuf
+);
+
+
+VOID
+TryDone(
+    	IN   	PDM_ODM_T		pDM_Odm,
+	IN	PODM_RA_INFO_T 	pRaInfo
+);
+
+VOID 
+RateDownTrying(
+	IN   	PDM_ODM_T	pDM_Odm,
+	IN 	PODM_RA_INFO_T pRaInfo
+);
+
+VOID
+RateDecisionRAM8195A(
+    IN   	PDM_ODM_T	pDM_Odm,
+    IN	PODM_RA_INFO_T pRaInfo
+);
+
+VOID 
+GetRATRfromREG(
+    IN u16 reg_addr,
+    IN u1Byte macid
+);
+
+VOID 
+PHY_DM_RA_SetRSSI_8195A(
+	IN 	PDM_ODM_T 		pDM_Odm, 
+	IN 	u1Byte 			MacID, 
+	IN 	u1Byte 			Rssi
+	);
+
+#if 0
+extern void 
+Rate_trying_decision(
+    IN u1Byte   macid, 
+    IN u1Byte   rate, 
+    IN u1Byte   datarc, 
+    IN u1Byte   aggnum
+);
+#endif
+
+
+//debug
+VOID
+ArfrRefresh(
+	IN   	PDM_ODM_T		pDM_Odm,
+	IN	PODM_RA_INFO_T 	pRaInfo
+);
+
+#endif  //#if CONFIG_RATE_ADAPTIVE
+
+#endif  //#ifndef   __HALCOM_RATE_ADAPTIVE_RAM_H__
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/HalPhyRf_8195A.h

@@ -0,0 +1,127 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __HAL_PHY_RF_8195A_H__
+#define __HAL_PHY_RF_8195A_H__
+
+
+/*--------------------------Define Parameters-------------------------------*/
+#define	IQK_DELAY_TIME_8195A		10		//ms
+#define IQK_DEFERRED_TIME_8195A		4
+#define	index_mapping_NUM_8195A		15
+#define AVG_THERMAL_NUM_8195A		4
+#define	RF_T_METER_8195A			0x42	//
+
+
+void ConfigureTxpowerTrack_8195A(
+	PTXPWRTRACK_CFG	pConfig
+	);
+
+void DoIQK_8195A(
+	PDM_ODM_T	pDM_Odm,
+	u1Byte 		DeltaThermalIndex,
+	u1Byte		ThermalValue,	
+	u1Byte 		Threshold
+	);
+
+VOID
+ODM_TxPwrTrackSetPwr_8195A(
+	PDM_ODM_T			pDM_Odm,
+	PWRTRACK_METHOD 	Method,
+	u1Byte 				RFPath,
+	u1Byte 				ChannelMappedIndex
+	);
+
+VOID
+ODM_TxXtalTrackSetXtal_8195A(
+	PDM_ODM_T			pDM_Odm
+);
+
+
+//1 7.	IQK
+
+void	
+PHY_IQCalibrate_8195A(	
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	IN PDM_ODM_T		pDM_Odm,
+#else
+	IN PADAPTER	Adapter,
+#endif
+	IN	BOOLEAN 	bReCovery,
+	IN	BOOLEAN 	bRestore);
+
+
+//
+// LC calibrate
+//
+void	
+PHY_LCCalibrate_8195A(
+	IN PDM_ODM_T		pDM_Odm
+);
+
+
+VOID
+_PHY_SaveADDARegisters_8195A(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	IN PDM_ODM_T		pDM_Odm,
+#else
+	IN	PADAPTER	pAdapter,
+#endif
+	IN	pu4Byte		ADDAReg,
+	IN	pu4Byte		ADDABackup,
+	IN	u4Byte		RegisterNum
+	);
+
+VOID
+_PHY_PathADDAOn_8195A(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	IN PDM_ODM_T		pDM_Odm,
+#else
+	IN	PADAPTER	pAdapter,
+#endif
+	IN	pu4Byte		ADDAReg,
+	IN	BOOLEAN		isPathAOn,
+	IN	BOOLEAN		is2T
+	);
+
+VOID
+_PHY_MACSettingCalibration_8195A(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	IN PDM_ODM_T		pDM_Odm,
+#else
+	IN	PADAPTER	pAdapter,
+#endif
+	IN	pu4Byte		MACReg,
+	IN	pu4Byte		MACBackup	
+	);
+
+
+VOID
+_PHY_PathAStandBy(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+	IN PDM_ODM_T		pDM_Odm
+#else
+	IN	PADAPTER	pAdapter
+#endif
+	);
+
+								
+#endif	// #ifndef __HAL_PHY_RF_8188E_H__								
+

RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/ROM_RTL8195A_PHYDM.h

@@ -0,0 +1,128 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef	__ROM_RTL8195A_PHYDM_H__
+#define __ROM_RTL8195A_PHYDM_H__
+
+typedef struct _FALSE_ALARM_STATISTICS{
+	u4Byte	Cnt_Parity_Fail;
+	u4Byte	Cnt_Rate_Illegal;
+	u4Byte	Cnt_Crc8_fail;
+	u4Byte	Cnt_Mcs_fail;
+	u4Byte	Cnt_Ofdm_fail;
+	u4Byte	Cnt_Ofdm_fail_pre;	//For RTL8881A
+	u4Byte	Cnt_Cck_fail;
+	u4Byte	Cnt_all;
+	u4Byte	Cnt_Fast_Fsync;
+	u4Byte	Cnt_SB_Search_fail;
+	u4Byte	Cnt_OFDM_CCA;
+	u4Byte	Cnt_CCK_CCA;
+	u4Byte	Cnt_CCA_all;
+	u4Byte	Cnt_BW_USC;	//Gary
+	u4Byte	Cnt_BW_LSC;	//Gary
+}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
+
+typedef struct _CFO_TRACKING_
+{
+	BOOLEAN			bATCStatus;
+	BOOLEAN			largeCFOHit;
+	BOOLEAN			bAdjust;
+	u1Byte			CrystalCap;
+	u1Byte			DefXCap;
+	int				CFO_tail[2];
+	int				CFO_ave_pre;
+	u4Byte			packetCount;
+	u4Byte			packetCount_pre;
+	BOOLEAN			bForceXtalCap;
+	BOOLEAN			bReset;
+	u1Byte			CFO_TH_XTAL_HIGH;
+	u1Byte			CFO_TH_XTAL_LOW;
+	u1Byte			CFO_TH_ATC;
+}CFO_TRACKING, *PCFO_TRACKING;
+
+typedef struct _ROM_INFO{
+	u1Byte	EEPROMVersion;
+	u1Byte	CrystalCap;
+	u8Byte	DebugComponents;
+	u4Byte	DebugLevel;
+}ROM_INFO, *PROM_INFO;
+
+extern FALSE_ALARM_STATISTICS 	FalseAlmCnt;
+extern CFO_TRACKING    			DM_CfoTrack;
+extern ROM_INFO					ROMInfo;
+
+u1Byte
+ROM_odm_QueryRxPwrPercentage(
+	IN		s1Byte		AntPower
+);
+
+
+u1Byte 
+ROM_odm_EVMdbToPercentage(
+    IN		s1Byte Value
+);
+
+s4Byte
+ROM_odm_SignalScaleMapping_8195A(	
+	IN u1Byte SupportInterface,
+	IN s4Byte CurrSig 
+);
+
+VOID
+ROM_odm_FalseAlarmCounterStatistics(
+	IN		PVOID					pDM_VOID
+);
+
+VOID 
+ROM_odm_SetEDCCAThreshold(
+	IN		PVOID		pDM_VOID,
+	IN		s1Byte		H2L,
+	IN		s1Byte		L2H
+);
+
+VOID
+ROM_odm_SetTRxMux(
+	IN		PVOID			pDM_VOID,
+	IN		ODM_Trx_MUX_Type			txMode,
+	IN		ODM_Trx_MUX_Type			rxMode
+);	
+
+
+VOID
+ROM_odm_SetCrystalCap(
+	IN		PVOID					pDM_VOID,
+	IN		u1Byte					CrystalCap
+);
+
+u1Byte
+ROM_odm_GetDefaultCrytaltalCap(
+	IN		PVOID					pDM_VOID
+);
+
+VOID
+ROM_ODM_CfoTrackingReset(
+	IN		PVOID					pDM_VOID
+);
+
+VOID
+ROM_odm_CfoTrackingFlow(
+	IN		PVOID					pDM_VOID
+);
+
+#endif