diff --git a/RTL00_SDKV35a/component/common/api/network/include/util.h b/RTL00_SDKV35a/component/common/api/network/include/util.h index 1572c8f..377c9c8 100644 --- a/RTL00_SDKV35a/component/common/api/network/include/util.h +++ b/RTL00_SDKV35a/component/common/api/network/include/util.h @@ -15,6 +15,7 @@ typedef enum _WIFI_EVENT_INDICATE{ WIFI_EVENT_DISCONNECT = 1, WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2, }WIFI_EVENT_INDICATE; +rtw_event_indicate_t int wext_get_ssid(const char *ifname, __u8 *ssid); int wext_set_ssid(const char *ifname, const __u8 *ssid, __u16 ssid_len); diff --git a/RTL00_SDKV35a/component/common/api/platform/platform_stdlib.h b/RTL00_SDKV35a/component/common/api/platform/platform_stdlib.h index fe3123e..364ccab 100644 --- a/RTL00_SDKV35a/component/common/api/platform/platform_stdlib.h +++ b/RTL00_SDKV35a/component/common/api/platform/platform_stdlib.h @@ -1,17 +1,38 @@ /****************************************************************************** + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. * - * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at * + * http://www.apache.org/licenses/LICENSE-2.0 * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. ******************************************************************************/ #ifndef __PLATFORM_STDLIB_H__ #define __PLATFORM_STDLIB_H__ #define USE_CLIB_PATCH 0 #if defined (__GNUC__) +/* build rom should set USE_RTL_ROM_CLIB=0 */ +#ifndef CONFIG_MBED_ENABLED +#include +#endif +#endif + +#ifdef CONFIG_BUILD_ROM +#define USE_RTL_ROM_CLIB 0 +#else +#define BUFFERED_PRINTF 0 +#ifndef CONFIG_MBED_ENABLED #define USE_RTL_ROM_CLIB 1 #else -#define USE_RTL_ROM_CLIB 1 +#define USE_RTL_ROM_CLIB 0 +#endif #endif #if defined(CONFIG_PLATFORM_8195A) @@ -59,7 +80,12 @@ #endif #if USE_RTL_ROM_CLIB +#if BUFFERED_PRINTF + extern int buffered_printf(const char* fmt, ...); + #define printf buffered_printf +#else #define printf rtl_printf +#endif #define sprintf rtl_sprintf #define snprintf rtl_snprintf #define memchr rtl_memchr @@ -67,7 +93,6 @@ #define memcpy rtl_memcpy #define memmove rtl_memmove #define memset rtl_memset - #define bzero(s,l) rtl_memset(s,0,l) #define strcat rtl_strcat #define strchr rtl_strchr #define strcmp(s1, s2) rtl_strcmp((const char *)s1, (const char *)s2) @@ -85,12 +110,12 @@ extern char* DiagStrtokPatch(char *str, const char* delim); extern char* DiagStrstrPatch(char *string, char *substring); extern int DiagSnPrintfPatch(char *buf, size_t size, const char *fmt, ...); - extern int DiagPrintfPatch(const char *fmt, ...); - extern int DiagSPrintfPatch(u8 *buf, const char *fmt, ...); + extern u32 DiagPrintfPatch(const char *fmt, ...); + extern u32 DiagSPrintfPatch(u8 *buf, const char *fmt, ...); #define printf DiagPrintfPatch #define sprintf DiagSPrintfPatch #define snprintf DiagSnPrintfPatch - #define strstr(a, b) DiagStrstrPatch((char *)(a), (char *)(b)) + #define strstr(a, b) DiagStrstrPatch((char *)(a), (char *)(b)) #define strtok DiagStrtokPatch #else #define printf DiagPrintf @@ -125,25 +150,27 @@ //extern int DiagSscanfPatch(const char *buf, const char *fmt, ...); //#define sscanf DiagSscanfPatch #define sscanf sscanf // use libc sscanf - #endif + #endif #endif #endif // defined (__IARSTDLIB__) // // memory management // +#ifndef CONFIG_MBED_ENABLED extern void *pvPortMalloc( size_t xWantedSize ); extern void vPortFree( void *pv ); -#undef malloc #define malloc pvPortMalloc -#undef free #define free vPortFree +#endif #elif defined (CONFIG_PLATFORM_8711B) + #if defined (__IARSTDLIB__) #include #include #include #include + #include /* va_list */ #include "diag.h" #define strsep(str, delim) _strsep(str, delim) @@ -151,18 +178,24 @@ extern void vPortFree( void *pv ); #include #include #include + #include /* va_list */ #include "diag.h" #include "strproc.h" + #include "memproc.h" #include "basic_types.h" - #include "hal_misc.h" +#if USE_RTL_ROM_CLIB + #include "rtl_lib.h" + #include "rom_libc_string.h" +#endif #undef printf #undef sprintf #undef snprintf - #undef atoi + #undef memchr #undef memcmp #undef memcpy #undef memset + #undef memmove #undef strcmp #undef strcpy #undef strlen @@ -170,63 +203,61 @@ extern void vPortFree( void *pv ); #undef strncpy #undef strsep #undef strtok - -#if USE_RTL_ROM_CLIB - #undef memchr - #undef memmove #undef strcat #undef strchr #undef strncat #undef strstr + #undef atol + #undef atoi + #undef strpbrk - #define printf rtl_printf - #define sprintf rtl_sprintf - #define snprintf rtl_snprintf - #define memchr rtl_memchr - #define memcmp rtl_memcmp - #define memcpy rtl_memcpy - #define memmove rtl_memmove - #define memset rtl_memset - #define strcat rtl_strcat - #define strchr rtl_strchr - #define strcmp(s1, s2) rtl_strcmp((const char *)s1, (const char *)s2) - #define strcpy rtl_strcpy - #define strlen(str) rtl_strlen((const char *)str) - #define strncat rtl_strncat - #define strncmp(s1, s2, n) rtl_strncmp((const char *)s1, (const char *)s2, n) - #define strncpy rtl_strncpy - #define strstr rtl_strstr - #define strsep rtl_strsep - #define strtok rtl_strtok +#if USE_RTL_ROM_CLIB +#if BUFFERED_PRINTF + extern int buffered_printf(const char* fmt, ...); + #define printf buffered_printf #else - #define printf DiagPrintf - #define sprintf(fmt, arg...) DiagSPrintf((u8*)fmt, ##arg) -#if defined (__GNUC__) - #define snprintf DiagSnPrintf // NULL function - #define strstr(str1, str2) prvStrStr(str1, str2) // NULL function + #define printf rtl_printf #endif - #define strtok(str, delim) _strsep(str, delim) - + #define sprintf rtl_sprintf + #define snprintf rtl_snprintf + #define vsnprintf rtl_vsnprintf +#else + #define printf DiagPrintf + #define sprintf(fmt, arg...) DiagSPrintf((u8*)fmt, ##arg) + #define snprintf DiagSnPrintf // NULL function + #define vsnprintf(buf, size, fmt, ap) VSprintf(buf, fmt, ap) +#endif + #define memchr __rtl_memchr_v1_00 #define memcmp(dst, src, sz) _memcmp(dst, src, sz) #define memcpy(dst, src, sz) _memcpy(dst, src, sz) + #define memmove __rtl_memmove_v1_00 #define memset(dst, val, sz) _memset(dst, val, sz) + #define strchr(s, c) _strchr(s, c) // for B-cut ROM #define strcmp(str1, str2) prvStrCmp((const unsigned char *) str1, (const unsigned char *) str2) #define strcpy(dest, src) _strcpy(dest, src) - #define strlen(str) prvStrLen((const unsigned char *) str) + #define strlen(str) prvStrLen((const unsigned char *) str) + #define strsep(str, delim) _strsep(str, delim) + #define strstr(str1, str2) prvStrStr(str1, str2) // NULL function + #define strtok(str, delim) prvStrtok(str, delim)//_strsep(str, delim) + #define strcat __rtl_strcat_v1_00 + #define strncmp(str1, str2, cnt) _strncmp(str1, str2, cnt) #define strncpy(dest, src, count) _strncpy(dest, src, count) - #define strsep(str, delim) _strsep(str, delim) - + #define strncat __rtl_strncat_v1_00 + + #define atol(str) strtol(str,NULL,10) #define atoi(str) prvAtoi(str) - #define strpbrk(cs, ct) _strpbrk(cs, ct) // for B-cut ROM - + #define strpbrk(cs, ct) _strpbrk(cs, ct) // for B-cut ROM #if defined (__GNUC__) #undef sscanf - #define sscanf _sscanf + #define sscanf _sscanf_patch + #define rand Rand #endif + //extern int _sscanf_patch(const char *buf, const char *fmt, ...); + //#define sscanf _sscanf_patch + -#endif #endif // defined (__IARSTDLIB__) // @@ -245,3 +276,4 @@ extern void vPortFree( void *pv ); #endif //__PLATFORM_STDLIB_H__ + diff --git a/RTL00_SDKV35a/component/common/api/wifi/wifi_conf.h b/RTL00_SDKV35a/component/common/api/wifi/wifi_conf.h index 8f2ebcb..7d95edd 100644 --- a/RTL00_SDKV35a/component/common/api/wifi/wifi_conf.h +++ b/RTL00_SDKV35a/component/common/api/wifi/wifi_conf.h @@ -1,6 +1,6 @@ //----------------------------------------------------------------------------// -#ifndef __WIFI_API_H -#define __WIFI_API_H +#ifndef __WIFI_CONF_API_H +#define __WIFI_CONF_API_H #include "FreeRTOS.h" #include "wifi_constants.h" @@ -705,6 +705,6 @@ int wifi_remove_packet_filter(unsigned char filter_id); } #endif -#endif // __WIFI_API_H +#endif // __WIFI_CONF_API_H //----------------------------------------------------------------------------// diff --git a/RTL00_SDKV35a/component/common/api/wifi_api.c b/RTL00_SDKV35a/component/common/api/wifi_api.c index 43d6c86..fb5f554 100644 --- a/RTL00_SDKV35a/component/common/api/wifi_api.c +++ b/RTL00_SDKV35a/component/common/api/wifi_api.c @@ -367,38 +367,40 @@ extern int lwip_init_done; void _LwIP_Init(void) { - int idx; - debug_printf("LwIP Init (%d)\n", wifi_mode); - /* Create tcp_ip stack thread */ - tcpip_init( NULL, NULL ); + if(!lwip_init_done) { + int idx; + debug_printf("LwIP Init (%d)\n", wifi_mode); + /* Create tcp_ip stack thread */ + tcpip_init( NULL, NULL ); - chk_ap_netif_num(); // Исполняется после _wifi_on() - for(int idx = 0; idx < NET_IF_NUM; idx++) { - xnetif[idx].name[0] = 'r'; - xnetif[idx].name[1] = '0' + idx; + chk_ap_netif_num(); // Исполняется после _wifi_on() + for(int idx = 0; idx < NET_IF_NUM; idx++) { + xnetif[idx].name[0] = 'r'; + xnetif[idx].name[1] = '0' + idx; + } + netif_add(&xnetif[WLAN_ST_NETIF_NUM], (struct netif *)&wifi_st_dhcp.ip, (struct netif *)&wifi_st_dhcp.mask, (struct netif *)&wifi_st_dhcp.gw, NULL, ðernetif_init, &tcpip_input); + netif_add(&xnetif[WLAN_AP_NETIF_NUM], (struct netif *)&wifi_ap_dhcp.ip, (struct netif *)&wifi_ap_dhcp.mask, (struct netif *)&wifi_ap_dhcp.gw, NULL, ðernetif_init, &tcpip_input); + #if CONFIG_ETHERNET // && NET_IF_NUM > 2 + { + struct ip_addr ipaddr; + struct ip_addr netmask; + struct ip_addr gw; + ipaddr.addr = DEF_EH_IP; + netmask.addr = DEF_EH_MSK; + gw.addr = DEF_EH_GW; + netif_add(&xnetif[2], &ipaddr, &netmask, &gw, NULL, ðernetif_mii_init, &tcpip_input); + } + #endif + /* Registers the default network interface. */ + netif_set_default(&xnetif[0]); + /* When the netif is fully configured this function must be called.*/ + for(idx = 0; idx < NET_IF_NUM; idx++) { + netif_set_up(&xnetif[idx]); + } + info_printf("interface %d is initialized\n", idx); + wifi_mode = 0; + lwip_init_done = 1; } - netif_add(&xnetif[WLAN_ST_NETIF_NUM], (struct netif *)&wifi_st_dhcp.ip, (struct netif *)&wifi_st_dhcp.mask, (struct netif *)&wifi_st_dhcp.gw, NULL, ðernetif_init, &tcpip_input); - netif_add(&xnetif[WLAN_AP_NETIF_NUM], (struct netif *)&wifi_ap_dhcp.ip, (struct netif *)&wifi_ap_dhcp.mask, (struct netif *)&wifi_ap_dhcp.gw, NULL, ðernetif_init, &tcpip_input); -#if CONFIG_ETHERNET // && NET_IF_NUM > 2 - { - struct ip_addr ipaddr; - struct ip_addr netmask; - struct ip_addr gw; - ipaddr.addr = DEF_EH_IP; - netmask.addr = DEF_EH_MSK; - gw.addr = DEF_EH_GW; - netif_add(&xnetif[2], &ipaddr, &netmask, &gw, NULL, ðernetif_mii_init, &tcpip_input); - } -#endif - /* Registers the default network interface. */ - netif_set_default(&xnetif[0]); - /* When the netif is fully configured this function must be called.*/ - for(idx = 0; idx < NET_IF_NUM; idx++) { - netif_set_up(&xnetif[idx]); - } - info_printf("interface %d is initialized\n", idx); - wifi_mode = 0; - lwip_init_done = 1; } int wifi_run(rtw_mode_t mode) { @@ -406,6 +408,9 @@ int wifi_run(rtw_mode_t mode) { #if CONFIG_DEBUG_LOG > 4 debug_printf("\n%s(%d), %d\n", __func__, mode, wifi_run_mode); #endif + if(mode != RTW_MODE_NONE) { + _LwIP_Init(); + }; if(wifi_run_mode & RTW_MODE_AP) { info_printf("Deinit old AP...\n"); LwIP_DHCP(WLAN_AP_NETIF_NUM, DHCP_STOP); @@ -414,12 +419,12 @@ int wifi_run(rtw_mode_t mode) { #endif dhcps_deinit(); wifi_run_mode &= ~RTW_MODE_AP; - } + }; if(wifi_run_mode & RTW_MODE_STA) { info_printf("Deinit old ST...\n"); LwIP_DHCP(WLAN_ST_NETIF_NUM, DHCP_STOP); wifi_run_mode &= ~RTW_MODE_STA; - } + }; // if(mode != wifi_mode) // wifi_mode = mode; // chk_ap_netif_num(); @@ -469,7 +474,7 @@ error_end: connect_close(); #endif wifi_off(); - } + }; chk_ap_netif_num(); return ret; } @@ -484,10 +489,6 @@ void wifi_init_thrd(void) { p_wlan_autoreconnect_hdl = NULL; if (wifi_cfg.mode != RTW_MODE_NONE) { wifi_mode = wifi_cfg.mode; - if(!lwip_init_done) { - /* Initilaize the LwIP stack */ - _LwIP_Init(); - }; user_start(); #if CONFIG_WIFI_IND_USE_THREAD wifi_manager_init(); diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/HalPwrSeqCmd.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/HalPwrSeqCmd.h new file mode 100644 index 0000000..51b8210 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/HalPwrSeqCmd.h @@ -0,0 +1,136 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HALPWRSEQCMD_H__ +#define __HALPWRSEQCMD_H__ + +/*---------------------------------------------*/ +//3 The value of cmd: 4 bits +/*---------------------------------------------*/ +#define PWR_CMD_READ 0x00 + // offset: the read register offset + // msk: the mask of the read value + // value: N/A, left by 0 + // note: dirver shall implement this function by read & msk + +#define PWR_CMD_WRITE 0x01 + // offset: the read register offset + // msk: the mask of the write bits + // value: write value + // note: driver shall implement this cmd by read & msk after write + +#define PWR_CMD_POLLING 0x02 + // offset: the read register offset + // msk: the mask of the polled value + // value: the value to be polled, masked by the msd field. + // note: driver shall implement this cmd by + // do{ + // if( (Read(offset) & msk) == (value & msk) ) + // break; + // } while(not timeout); + +#define PWR_CMD_DELAY 0x03 + // offset: the value to delay + // msk: N/A + // value: the unit of delay, 0: us, 1: ms + +#define PWR_CMD_END 0x04 + // offset: N/A + // msk: N/A + // value: N/A + +/*---------------------------------------------*/ +//3 The value of base: 4 bits +/*---------------------------------------------*/ + // define the base address of each block +#define PWR_BASEADDR_MAC 0x00 +#define PWR_BASEADDR_USB 0x01 +#define PWR_BASEADDR_PCIE 0x02 +#define PWR_BASEADDR_SDIO 0x03 + +/*---------------------------------------------*/ +//3 The value of interface_msk: 4 bits +/*---------------------------------------------*/ +#define PWR_INTF_SDIO_MSK BIT(0) +#define PWR_INTF_USB_MSK BIT(1) +#define PWR_INTF_PCI_MSK BIT(2) +#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) + +/*---------------------------------------------*/ +//3 The value of fab_msk: 4 bits +/*---------------------------------------------*/ +#define PWR_FAB_TSMC_MSK BIT(0) +#define PWR_FAB_UMC_MSK BIT(1) +#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) + +/*---------------------------------------------*/ +//3 The value of cut_msk: 8 bits +/*---------------------------------------------*/ +#define PWR_CUT_TESTCHIP_MSK BIT(0) +#define PWR_CUT_A_MSK BIT(1) +#define PWR_CUT_B_MSK BIT(2) +#define PWR_CUT_C_MSK BIT(3) +#define PWR_CUT_D_MSK BIT(4) +#define PWR_CUT_E_MSK BIT(5) +#define PWR_CUT_F_MSK BIT(6) +#define PWR_CUT_G_MSK BIT(7) +#define PWR_CUT_ALL_MSK 0xFF + + +typedef enum _PWRSEQ_CMD_DELAY_UNIT_ +{ + PWRSEQ_DELAY_US, + PWRSEQ_DELAY_MS, +} PWRSEQ_DELAY_UNIT; + +typedef struct _WL_PWR_CFG_ +{ + u16 offset; + u8 cut_msk; + u8 fab_msk:4; + u8 interface_msk:4; + u8 base:4; + u8 cmd:4; + u8 msk; + u8 value; +} WLAN_PWR_CFG, *PWLAN_PWR_CFG; + + +#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset +#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk +#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk +#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk +#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base +#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd +#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk +#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value + + +//================================================================================ +// Prototype of protected function. +//================================================================================ +u8 HalPwrSeqCmdParsing( + _adapter * padapter, + u8 CutVersion, + u8 FabVersion, + u8 InterfaceType, + WLAN_PWR_CFG PwrCfgCmd[]); + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/HalVerDef.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/HalVerDef.h new file mode 100644 index 0000000..bdb0f06 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/HalVerDef.h @@ -0,0 +1,178 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_VERSION_DEF_H__ +#define __HAL_VERSION_DEF_H__ + +#ifndef TRUE +#define TRUE _TRUE +#endif +#ifndef FALSE +#define FALSE _FALSE +#endif + +// HAL_IC_TYPE_E +typedef enum tag_HAL_IC_Type_Definition +{ + CHIP_8192S = 0, + CHIP_8188C = 1, + CHIP_8192C = 2, + CHIP_8192D = 3, + CHIP_8723A = 4, + CHIP_8188E = 5, + CHIP_8812 = 6, + CHIP_8821 = 7, + CHIP_8723B = 8, + CHIP_8192E = 9, + CHIP_8195A = 10, + CHIP_8710B = 11, + CHIP_8188F = 12, +}HAL_IC_TYPE_E; + +//HAL_CHIP_TYPE_E +typedef enum tag_HAL_CHIP_Type_Definition +{ + TEST_CHIP = 0, + NORMAL_CHIP = 1, + FPGA = 2, +}HAL_CHIP_TYPE_E; + +//HAL_CUT_VERSION_E +typedef enum tag_HAL_Cut_Version_Definition +{ + A_CUT_VERSION = 0, + B_CUT_VERSION = 1, + C_CUT_VERSION = 2, + D_CUT_VERSION = 3, + E_CUT_VERSION = 4, + F_CUT_VERSION = 5, + G_CUT_VERSION = 6, + H_CUT_VERSION = 7, + I_CUT_VERSION = 8, + J_CUT_VERSION = 9, + K_CUT_VERSION = 10, +}HAL_CUT_VERSION_E; + +// HAL_Manufacturer +typedef enum tag_HAL_Manufacturer_Version_Definition +{ + CHIP_VENDOR_TSMC = 0, + CHIP_VENDOR_UMC = 1, + CHIP_VENDOR_SMIC = 2, +}HAL_VENDOR_E; + +typedef enum tag_HAL_RF_Type_Definition +{ + RF_TYPE_1T1R = 0, + RF_TYPE_1T2R = 1, + RF_TYPE_2T2R = 2, + RF_TYPE_2T3R = 3, + RF_TYPE_2T4R = 4, + RF_TYPE_3T3R = 5, + RF_TYPE_3T4R = 6, + RF_TYPE_4T4R = 7, +}HAL_RF_TYPE_E; + +typedef struct tag_HAL_VERSION +{ + HAL_IC_TYPE_E ICType; + HAL_CHIP_TYPE_E ChipType; + HAL_CUT_VERSION_E CUTVersion; + HAL_VENDOR_E VendorType; + HAL_RF_TYPE_E RFType; + u8 ROMVer; +}HAL_VERSION,*PHAL_VERSION; + +//VERSION_8192C VersionID; +//HAL_VERSION VersionID; + +// Get element +#define GET_CVID_IC_TYPE(version) ((HAL_IC_TYPE_E)((version).ICType) ) +#define GET_CVID_CHIP_TYPE(version) ((HAL_CHIP_TYPE_E)((version).ChipType) ) +#define GET_CVID_RF_TYPE(version) ((HAL_RF_TYPE_E)((version).RFType)) +#define GET_CVID_MANUFACTUER(version) ((HAL_VENDOR_E)((version).VendorType)) +#define GET_CVID_CUT_VERSION(version) ((HAL_CUT_VERSION_E)((version).CUTVersion)) +#define GET_CVID_ROM_VERSION(version) (((version).ROMVer) & ROM_VERSION_MASK) + +//---------------------------------------------------------------------------- +//Common Macro. -- +//---------------------------------------------------------------------------- +//HAL_VERSION VersionID + +// HAL_IC_TYPE_E +#define IS_81XXC(version) (((GET_CVID_IC_TYPE(version) == CHIP_8192C)||(GET_CVID_IC_TYPE(version) == CHIP_8188C))? TRUE : FALSE) +#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723A)? TRUE : FALSE) +#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192D)? TRUE : FALSE) +#define IS_8188E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188E)? TRUE : FALSE) +#define IS_8192E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192E)? TRUE : FALSE) +#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812)? TRUE : FALSE) +#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821)? TRUE : FALSE) +#define IS_8723B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723B)? TRUE : FALSE) +#define IS_8710B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8710B)? TRUE : FALSE) +#define IS_8188F(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188F)? TRUE : FALSE) + +//HAL_CHIP_TYPE_E +#define IS_TEST_CHIP(version) ((GET_CVID_CHIP_TYPE(version)==TEST_CHIP)? TRUE: FALSE) +#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version)==NORMAL_CHIP)? TRUE: FALSE) + +//HAL_CUT_VERSION_E +#define IS_A_CUT(version) ((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? TRUE : FALSE) +#define IS_B_CUT(version) ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? TRUE : FALSE) +#define IS_C_CUT(version) ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE) +#define IS_D_CUT(version) ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE) +#define IS_E_CUT(version) ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE) +#define IS_I_CUT(version) ((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? TRUE : FALSE) +#define IS_J_CUT(version) ((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? TRUE : FALSE) +#define IS_K_CUT(version) ((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? TRUE : FALSE) + +//HAL_VENDOR_E +#define IS_CHIP_VENDOR_TSMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC)? TRUE: FALSE) +#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC)? TRUE: FALSE) +#define IS_CHIP_VENDOR_SMIC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_SMIC)? TRUE: FALSE) + +//HAL_RF_TYPE_E +#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R)? TRUE : FALSE ) +#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? TRUE : FALSE) +#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? TRUE : FALSE) + + +//---------------------------------------------------------------------------- +//Chip version Macro. -- +//---------------------------------------------------------------------------- +#define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version)))? TRUE: FALSE) + +#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE) +#define IS_81xxC_VENDOR_UMC_A_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE): FALSE) +#define IS_81xxC_VENDOR_UMC_B_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE): FALSE) +#define IS_81xxC_VENDOR_UMC_C_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE): FALSE) + +#define IS_NORMAL_CHIP92D(version) (( IS_92D(version))?((GET_CVID_CHIP_TYPE(version)==NORMAL_CHIP)? TRUE: FALSE):FALSE) + +#define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? TRUE: FALSE) : FALSE) +#define IS_92D_C_CUT(version) ((IS_92D(version)) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE) +#define IS_92D_D_CUT(version) ((IS_92D(version)) ? (IS_D_CUT(version) ? TRUE : FALSE) : FALSE) +#define IS_92D_E_CUT(version) ((IS_92D(version)) ? (IS_E_CUT(version) ? TRUE : FALSE) : FALSE) + +#define IS_8723A_A_CUT(version) ((IS_8723_SERIES(version)) ? ( IS_A_CUT(version)?TRUE : FALSE) : FALSE) +#define IS_8723A_B_CUT(version) ((IS_8723_SERIES(version)) ? ( IS_B_CUT(version)?TRUE : FALSE) : FALSE) + +#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ((IS_8188E(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE) + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/autoconf.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/autoconf.h index c271d04..c2505cf 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/autoconf.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/autoconf.h @@ -1,3 +1,22 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ #ifndef WLANCONFIG_H #define WLANCONFIG_H @@ -21,11 +40,12 @@ #endif #ifndef CONFIG_INIC_EN -#define CONFIG_INIC_EN 0//For iNIC project +#define CONFIG_INIC_EN 0 //For iNIC project +#endif + #if CONFIG_INIC_EN #define CONFIG_LWIP_LAYER 0 #endif -#endif #define CONFIG_LITTLE_ENDIAN #define CONFIG_80211N_HT @@ -61,8 +81,11 @@ #endif // CONFIG_PLATFORM_AMEBA_X //#define CONFIG_DONT_CARE_TP +//#define CONFIG_HIGH_TP //#define CONFIG_MEMORY_ACCESS_ALIGNED +#ifndef PLATFORM_CMSIS_RTOS // unsupported feature #define CONFIG_POWER_SAVING +#endif #ifdef CONFIG_POWER_SAVING #define CONFIG_IPS #define CONFIG_LPS @@ -86,7 +109,7 @@ #if defined(CONFIG_PLATFORM_AMEBA_X) #if !defined(CONFIG_PLATFORM_8711B) - #define CONFIG_USE_TCM_HEAP 1 /* USE TCM HEAP */ + #define CONFIG_USE_TCM_HEAP 1 /* USE TCM HEAP */ #endif #define CONFIG_RECV_TASKLET_THREAD #define CONFIG_XMIT_TASKLET_THREAD @@ -128,14 +151,16 @@ #define NOT_SUPPORT_VHT #define NOT_SUPPORT_40M #define NOT_SUPPORT_80M +#ifndef CONFIG_PLATFORM_8711B #define NOT_SUPPORT_BBSWING +#endif #define NOT_SUPPORT_OLD_CHANNEL_PLAN #define NOT_SUPPORT_BT #define CONFIG_WIFI_SPEC 0 #define CONFIG_FAKE_EFUSE 0 #if CONFIG_FAKE_EFUSE - #define FAKE_CHIPID CHIPID_8711AN + #define FAKE_CHIPID CHIPID_8710BN #endif #define CONFIG_AUTO_RECONNECT 1 @@ -156,9 +181,6 @@ /* For promiscuous mode */ #define CONFIG_PROMISC -#ifdef CONFIG_PROMISC -//#define CONFIG_PROMISC_SCAN_CONCURENT -#endif #define PROMISC_DENY_PAIRWISE 0 @@ -176,9 +198,7 @@ #endif /* For STA+AP Concurrent MODE */ -#if !defined(CONFIG_PLATFORM_8711B) #define CONFIG_CONCURRENT_MODE -#endif #ifdef CONFIG_CONCURRENT_MODE #if defined(CONFIG_PLATFORM_8195A) #define CONFIG_RUNTIME_PORT_SWITCH @@ -210,8 +230,9 @@ #endif // enable 1X code in lib_wlan as default (increase 380 bytes) +#ifndef PLATFORM_CMSIS_RTOS // unsupported feature #define CONFIG_EAP - +#endif #if CONFIG_TLS || CONFIG_PEAP || CONFIG_TTLS #define EAP_REMOVE_UNUSED_CODE 1 #endif @@ -233,7 +254,7 @@ /****************** End of EAP configurations *******************/ /* For WPS and P2P */ -// #define CONFIG_WPS +#define CONFIG_WPS #if 0 #define CONFIG_WPS_AP #define CONFIG_P2P_NEW @@ -243,6 +264,7 @@ #endif #define CONFIG_NEW_SIGNAL_STAT_PROCESS +#define CONFIG_SKIP_SIGNAL_SCALE_MAPPING /* For AP_MODE */ #define CONFIG_AP_MODE @@ -259,6 +281,10 @@ extern unsigned int g_ap_sta_num; #define AP_STA_NUM 3//g_ap_sta_num #endif #ifdef CONFIG_AP_MODE +#if defined(CONFIG_PLATFORM_8195A) + //softap sent qos null0 polling client alive or not + #define CONFIG_AP_POLLING_CLIENT_ALIVE +#endif #define CONFIG_NATIVEAP_MLME #if defined(CONFIG_PLATFORM_AMEBA_X) #define CONFIG_INTERRUPT_BASED_TXBCN @@ -318,20 +344,27 @@ extern unsigned int g_ap_sta_num; //Control wifi mcu function #define CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD #define CONFIG_ODM_REFRESH_RAMASK - #define CONFIG_ANTENNA_DIVERSITY #endif #endif // #ifdef CONFIG_MP_INCLUDED #if defined(CONFIG_PLATFORM_AMEBA_X) #if defined(CONFIG_PLATFORM_8195A) - #ifndef CONFIG_RTL8195A - #define CONFIG_RTL8195A - #endif + #undef CONFIG_RTL8195A + #define CONFIG_RTL8195A #endif #if defined(CONFIG_PLATFORM_8711B) #ifndef CONFIG_RTL8711B - #define CONFIG_RTL8711B + #define CONFIG_RTL8711B #endif + #undef CONFIG_ADAPTOR_INFO_CACHING_FLASH + #define CONFIG_ADAPTOR_INFO_CACHING_FLASH 0 + //#undef CONFIG_EAP + //#undef CONFIG_IPS + #define CONFIG_8710B_MOVE_TO_ROM + #define CONFIG_EFUSE_SEPARATE + #define CONFIG_MOVE_PSK_TO_ROM + #define CONFIG_WOWLAN + #define CONFIG_TRAFFIC_PROTECT #endif #elif defined(CONFIG_HARDWARE_8188F) #define CONFIG_RTL8188F @@ -385,8 +418,7 @@ extern unsigned int g_ap_sta_num; #define DBG_TX_RATE 1 // DebugComponents: bit9 #define DBG_DM_RA 1 // DebugComponents: bit9 #define DBG_DM_DIG 1 // DebugComponents: bit0 - #define DBG_DM_ANT_DIV 1 // DebugComponents: bit6 - #define DBG_DM_ADAPTIVITY 1 // DebugComponents: bit17 + #define DBG_DM_ADAPTIVITY 1 // DebugComponents: bit16 // RF #define DBG_PWR_TRACKING 1 // DebugComponents: bit24 #define DBG_RF_IQK 1 // DebugComponents: bit26 @@ -398,6 +430,9 @@ extern unsigned int g_ap_sta_num; /* For DM support */ #if defined(CONFIG_RTL8188F) #define RATE_ADAPTIVE_SUPPORT 0 +#elif defined(CONFIG_PLATFORM_8711B) +#define RATE_ADAPTIVE_SUPPORT 1 +#define CONFIG_ODM_REFRESH_RAMASK #else #define RATE_ADAPTIVE_SUPPORT 1 #endif @@ -431,8 +466,8 @@ extern unsigned int g_ap_sta_num; #if (SKB_PRE_ALLOCATE_RX == 1) #define EXCHANGE_LXBUS_RX_SKB 0 #endif -#if defined(CONFIG_PLATFORM_8711B) -//Enable mac loopback for test mode (Ameba) +#ifdef CONFIG_FPGA + //Enable mac loopback for test mode (Ameba) #define CONFIG_TWO_MAC_DRIVER // for test mode #endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/byteorder/generic.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/byteorder/generic.h new file mode 100644 index 0000000..13fdbf3 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/byteorder/generic.h @@ -0,0 +1,223 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_BYTEORDER_GENERIC_H +#define _LINUX_BYTEORDER_GENERIC_H + +/* + * linux/byteorder_generic.h + * Generic Byte-reordering support + * + * Francois-Rene Rideau 19970707 + * gathered all the good ideas from all asm-foo/byteorder.h into one file, + * cleaned them up. + * I hope it is compliant with non-GCC compilers. + * I decided to put __BYTEORDER_HAS_U64__ in byteorder.h, + * because I wasn't sure it would be ok to put it in types.h + * Upgraded it to 2.1.43 + * Francois-Rene Rideau 19971012 + * Upgraded it to 2.1.57 + * to please Linus T., replaced huge #ifdef's between little/big endian + * by nestedly #include'd files. + * Francois-Rene Rideau 19971205 + * Made it to 2.1.71; now a facelift: + * Put files under include/linux/byteorder/ + * Split swab from generic support. + * + * TODO: + * = Regular kernel maintainers could also replace all these manual + * byteswap macros that remain, disseminated among drivers, + * after some grep or the sources... + * = Linus might want to rename all these macros and files to fit his taste, + * to fit his personal naming scheme. + * = it seems that a few drivers would also appreciate + * nybble swapping support... + * = every architecture could add their byteswap macro in asm/byteorder.h + * see how some architectures already do (i386, alpha, ppc, etc) + * = cpu_to_beXX and beXX_to_cpu might some day need to be well + * distinguished throughout the kernel. This is not the case currently, + * since little endian, big endian, and pdp endian machines needn't it. + * But this might be the case for, say, a port of Linux to 20/21 bit + * architectures (and F21 Linux addict around?). + */ + +/* + * The following macros are to be defined by : + * + * Conversion of long and short int between network and host format + * ntohl(__u32 x) + * ntohs(__u16 x) + * htonl(__u32 x) + * htons(__u16 x) + * It seems that some programs (which? where? or perhaps a standard? POSIX?) + * might like the above to be functions, not macros (why?). + * if that's true, then detect them, and take measures. + * Anyway, the measure is: define only ___ntohl as a macro instead, + * and in a separate file, have + * unsigned long inline ntohl(x){return ___ntohl(x);} + * + * The same for constant arguments + * __constant_ntohl(__u32 x) + * __constant_ntohs(__u16 x) + * __constant_htonl(__u32 x) + * __constant_htons(__u16 x) + * + * Conversion of XX-bit integers (16- 32- or 64-) + * between native CPU format and little/big endian format + * 64-bit stuff only defined for proper architectures + * cpu_to_[bl]eXX(__uXX x) + * [bl]eXX_to_cpu(__uXX x) + * + * The same, but takes a pointer to the value to convert + * cpu_to_[bl]eXXp(__uXX x) + * [bl]eXX_to_cpup(__uXX x) + * + * The same, but change in situ + * cpu_to_[bl]eXXs(__uXX x) + * [bl]eXX_to_cpus(__uXX x) + * + * See asm-foo/byteorder.h for examples of how to provide + * architecture-optimized versions + * + */ + + +#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) || defined(PLATFORM_FREEBSD) || defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) +/* + * inside the kernel, we can use nicknames; + * outside of it, we must avoid POSIX namespace pollution... + */ + +//TODO +#if 0 + +#define cpu_to_le64 __cpu_to_le64 +#define le64_to_cpu __le64_to_cpu + +#endif //#if 0 + +#define cpu_to_le32 __cpu_to_le32 +#define le32_to_cpu __le32_to_cpu +#define cpu_to_le16 __cpu_to_le16 +#define le16_to_cpu __le16_to_cpu +#define cpu_to_be64 __cpu_to_be64 +#define be64_to_cpu __be64_to_cpu +#define cpu_to_be32 __cpu_to_be32 +#define be32_to_cpu __be32_to_cpu +#define cpu_to_be16 __cpu_to_be16 +#define be16_to_cpu __be16_to_cpu +#define cpu_to_le64p __cpu_to_le64p +#define le64_to_cpup __le64_to_cpup +#define cpu_to_le32p __cpu_to_le32p +#define le32_to_cpup __le32_to_cpup +#define cpu_to_le16p __cpu_to_le16p +#define le16_to_cpup __le16_to_cpup +#define cpu_to_be64p __cpu_to_be64p +#define be64_to_cpup __be64_to_cpup +#define cpu_to_be32p __cpu_to_be32p +#define be32_to_cpup __be32_to_cpup +#define cpu_to_be16p __cpu_to_be16p +#define be16_to_cpup __be16_to_cpup +#define cpu_to_le64s __cpu_to_le64s +#define le64_to_cpus __le64_to_cpus +#define cpu_to_le32s __cpu_to_le32s +#define le32_to_cpus __le32_to_cpus +#define cpu_to_le16s __cpu_to_le16s +#define le16_to_cpus __le16_to_cpus +#define cpu_to_be64s __cpu_to_be64s +#define be64_to_cpus __be64_to_cpus +#define cpu_to_be32s __cpu_to_be32s +#define be32_to_cpus __be32_to_cpus +#define cpu_to_be16s __cpu_to_be16s +#define be16_to_cpus __be16_to_cpus +#endif + +//TODO +#if 0 + +/* + * Handle ntohl and suches. These have various compatibility + * issues - like we want to give the prototype even though we + * also have a macro for them in case some strange program + * wants to take the address of the thing or something.. + * + * Note that these used to return a "long" in libc5, even though + * long is often 64-bit these days.. Thus the casts. + * + * They have to be macros in order to do the constant folding + * correctly - if the argument passed into a inline function + * it is no longer constant according to gcc.. + */ + +#undef ntohl +#undef ntohs +#undef htonl +#undef htons + +/* + * Do the prototypes. Somebody might want to take the + * address or some such sick thing.. + */ +#if defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) +extern __u32 ntohl(__u32); +extern __u32 htonl(__u32); +#else //defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) +#ifndef PLATFORM_FREEBSD +extern unsigned long int ntohl(unsigned long int); +extern unsigned long int htonl(unsigned long int); +#endif +#endif +#ifndef PLATFORM_FREEBSD +extern unsigned short int ntohs(unsigned short int); +extern unsigned short int htons(unsigned short int); +#endif + +#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) || defined(PLATFORM_MPIXEL) + +#define ___htonl(x) __cpu_to_be32(x) +#define ___htons(x) __cpu_to_be16(x) +#define ___ntohl(x) __be32_to_cpu(x) +#define ___ntohs(x) __be16_to_cpu(x) + +#if defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) +#define htonl(x) ___htonl(x) +#define ntohl(x) ___ntohl(x) +#else +#define htonl(x) ((unsigned long)___htonl(x)) +#define ntohl(x) ((unsigned long)___ntohl(x)) +#endif +#define htons(x) ___htons(x) +#define ntohs(x) ___ntohs(x) + +#endif /* OPTIMIZE */ + + +#if defined (PLATFORM_WINDOWS) + +#define htonl(x) __cpu_to_be32(x) +#define ntohl(x) __be32_to_cpu(x) +#define htons(x) __cpu_to_be16(x) +#define ntohs(x) __be16_to_cpu(x) + +#endif + +#endif //#if 0 + +#endif /* _LINUX_BYTEORDER_GENERIC_H */ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/byteorder/little_endian.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/byteorder/little_endian.h new file mode 100644 index 0000000..6c12102 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/byteorder/little_endian.h @@ -0,0 +1,97 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H +#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H + +#ifndef __LITTLE_ENDIAN +#define __LITTLE_ENDIAN 1234 +#endif +#ifndef __LITTLE_ENDIAN_BITFIELD +#define __LITTLE_ENDIAN_BITFIELD +#endif + +#include + +#ifndef __constant_htonl + +//TODO +#if 0 + +#define __constant_htonl(x) ___constant_swab32((x)) +#define __constant_ntohl(x) ___constant_swab32((x)) +#define __constant_htons(x) ___constant_swab16((x)) +#define __constant_ntohs(x) ___constant_swab16((x)) +#define __constant_cpu_to_le64(x) ((__u64)(x)) +#define __constant_le64_to_cpu(x) ((__u64)(x)) +#define __constant_cpu_to_le32(x) ((__u32)(x)) +#define __constant_le32_to_cpu(x) ((__u32)(x)) +#define __constant_cpu_to_le16(x) ((__u16)(x)) +#define __constant_le16_to_cpu(x) ((__u16)(x)) +#define __constant_cpu_to_be64(x) ___constant_swab64((x)) +#define __constant_be64_to_cpu(x) ___constant_swab64((x)) +#define __constant_cpu_to_be32(x) ___constant_swab32((x)) +#define __constant_be32_to_cpu(x) ___constant_swab32((x)) +#define __constant_cpu_to_be16(x) ___constant_swab16((x)) +#define __constant_be16_to_cpu(x) ___constant_swab16((x)) +#define __cpu_to_le64(x) ((__u64)(x)) +#define __le64_to_cpu(x) ((__u64)(x)) + +#endif //#if 0 + +#define __cpu_to_le32(x) ((__u32)(x)) +#define __le32_to_cpu(x) ((__u32)(x)) +#define __cpu_to_le16(x) ((__u16)(x)) +#define __le16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_be64(x) __swab64((x)) +#define __be64_to_cpu(x) __swab64((x)) +#define __cpu_to_be32(x) __swab32((x)) +#define __be32_to_cpu(x) __swab32((x)) +#define __cpu_to_be16(x) __swab16((x)) +#define __be16_to_cpu(x) __swab16((x)) +#define __cpu_to_le64p(x) (*(__u64*)(x)) +#define __le64_to_cpup(x) (*(__u64*)(x)) +#define __cpu_to_le32p(x) (*(__u32*)(x)) +#define __le32_to_cpup(x) (*(__u32*)(x)) +#define __cpu_to_le16p(x) (*(__u16*)(x)) +#define __le16_to_cpup(x) (*(__u16*)(x)) +#define __cpu_to_be64p(x) __swab64p((x)) +#define __be64_to_cpup(x) __swab64p((x)) +#define __cpu_to_be32p(x) __swab32p((x)) +#define __be32_to_cpup(x) __swab32p((x)) +#define __cpu_to_be16p(x) __swab16p((x)) +#define __be16_to_cpup(x) __swab16p((x)) +#define __cpu_to_le64s(x) do {} while (0) +#define __le64_to_cpus(x) do {} while (0) +#define __cpu_to_le32s(x) do {} while (0) +#define __le32_to_cpus(x) do {} while (0) +#define __cpu_to_le16s(x) do {} while (0) +#define __le16_to_cpus(x) do {} while (0) +#define __cpu_to_be64s(x) __swab64s((x)) +#define __be64_to_cpus(x) __swab64s((x)) +#define __cpu_to_be32s(x) __swab32s((x)) +#define __be32_to_cpus(x) __swab32s((x)) +#define __cpu_to_be16s(x) __swab16s((x)) +#define __be16_to_cpus(x) __swab16s((x)) +#endif // __constant_htonl + +#include + +#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/byteorder/swab.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/byteorder/swab.h new file mode 100644 index 0000000..a956a0b --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/byteorder/swab.h @@ -0,0 +1,145 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_BYTEORDER_SWAB_H +#define _LINUX_BYTEORDER_SWAB_H +/* +#if !defined(CONFIG_PLATFORM_MSTAR_TITANIA12) && !defined(PLATFORM_ECOS) && \ + !defined(CONFIG_PLATFORM_8195A) +*/ +#if !defined(CONFIG_PLATFORM_MSTAR_TITANIA12) && !defined(PLATFORM_ECOS) + +#if !defined(PLATFORM_FREERTOS) && !defined (PLATFORM_CMSIS_RTOS) +#ifndef __u16 +typedef unsigned short __u16; +#endif + +#ifndef __u32 +typedef unsigned int __u32; +#endif + +#ifndef __u8 +typedef unsigned char __u8; +#endif + +#ifndef __u64 +typedef unsigned long long __u64; +#endif +#endif +__inline static __u16 ___swab16(__u16 x) +{ + __u16 __x = x; + return + ((__u16)( + (((__u16)(__x) & (__u16)0x00ffU) << 8) | + (((__u16)(__x) & (__u16)0xff00U) >> 8) )); + +} + +__inline static __u32 ___swab32(__u32 x) +{ + __u32 __x = (x); + return ((__u32)( + (((__u32)(__x) & (__u32)0x000000ffUL) << 24) | + (((__u32)(__x) & (__u32)0x0000ff00UL) << 8) | + (((__u32)(__x) & (__u32)0x00ff0000UL) >> 8) | + (((__u32)(__x) & (__u32)0xff000000UL) >> 24) )); +} + +__inline static __u64 ___swab64(__u64 x) +{ + __u64 __x = (x); + + return + ((__u64)( \ + (__u64)(((__u64)(__x) & (__u64)0x00000000000000ffULL) << 56) | \ + (__u64)(((__u64)(__x) & (__u64)0x000000000000ff00ULL) << 40) | \ + (__u64)(((__u64)(__x) & (__u64)0x0000000000ff0000ULL) << 24) | \ + (__u64)(((__u64)(__x) & (__u64)0x00000000ff000000ULL) << 8) | \ + (__u64)(((__u64)(__x) & (__u64)0x000000ff00000000ULL) >> 8) | \ + (__u64)(((__u64)(__x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ + (__u64)(((__u64)(__x) & (__u64)0x00ff000000000000ULL) >> 40) | \ + (__u64)(((__u64)(__x) & (__u64)0xff00000000000000ULL) >> 56) )); \ +} +#endif // CONFIG_PLATFORM_MSTAR_TITANIA12 + +#ifndef __arch__swab16 +__inline static __u16 __arch__swab16(__u16 x) +{ + return ___swab16(x); +} + +#endif + +#ifndef __arch__swab32 +__inline static __u32 __arch__swab32(__u32 x) +{ + __u32 __tmp = (x) ; + return ___swab32(__tmp); +} +#endif + +#ifndef __arch__swab64 + +__inline static __u64 __arch__swab64(__u64 x) +{ + __u64 __tmp = (x) ; + return ___swab64(__tmp); +} + + +#endif + +#ifndef __swab16 +#define __swab16(x) __fswab16(x) +#define __swab32(x) __fswab32(x) +#define __swab64(x) __fswab64(x) +#endif // __swab16 + +#ifdef PLATFORM_FREEBSD +__inline static __u16 __fswab16(__u16 x) +#else +__inline static __u16 __fswab16(__u16 x) +#endif //PLATFORM_FREEBSD +{ + return __arch__swab16(x); +} +#ifdef PLATFORM_FREEBSD +__inline static __u32 __fswab32(__u32 x) +#else +__inline static __u32 __fswab32(__u32 x) +#endif //PLATFORM_FREEBSD +{ + return __arch__swab32(x); +} + +#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) +#define swab16 __swab16 +#define swab32 __swab32 +#define swab64 __swab64 +#define swab16p __swab16p +#define swab32p __swab32p +#define swab64p __swab64p +#define swab16s __swab16s +#define swab32s __swab32s +#define swab64s __swab64s +#endif + +#endif /* _LINUX_BYTEORDER_SWAB_H */ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/drv_types.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/drv_types.h new file mode 100644 index 0000000..49bedcc --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/drv_types.h @@ -0,0 +1,863 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/*------------------------------------------------------------------------------- + + For type defines and data structure defines + +--------------------------------------------------------------------------------*/ + + +#ifndef __DRV_TYPES_H__ +#define __DRV_TYPES_H__ + +#include + + +#ifdef PLATFORM_OS_XP +#include +#endif + +#ifdef PLATFORM_OS_CE +#include +#endif + +#ifdef PLATFORM_LINUX +#include +#endif + + +#if defined (__ICCARM__) +#define _PACKED __packed +#define _WEAK __weak +#else +#define _PACKED __attribute__ ((packed)) +#define _WEAK __attribute__ ((weak)) +#endif + +// Assign memory sectinon usage +#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) +#include +//#include "rtl_utility_ram.h" +#include "platform/platform_stdlib.h" +#else +#define SRAM_BD_DATA_SECTION +#define WLAN_ROM_TEXT_SECTION +#define WLAN_ROM_DATA_SECTION +#define _LONG_CALL_ +#endif + +#ifdef CONFIG_TRACE_SKB +#define SKBLIST_ALL 0xFFFFFFFF +// receive +#define SKBLIST_RECVBUF_MASK 0x0000000F +#define SKBLIST_RECVBUF 0x00000001 +#define SKBLIST_RECVBUF_FREEQUEUE 0x00000002 +#define SKBLIST_RECVBUF_PENDINGQUEUE 0x00000004 + +#define SKBLIST_RECVFRAME_MASK 0x000000F0 +#define SKBLIST_RECVFRAME 0x00000010 +#define SKBLIST_RECVFRAME_FREEQUEUE 0x00000020 +#define SKBLIST_RECVFRAME_SWDECQUEUE 0x00000040 +#ifdef CONFIG_RECV_REORDERING_CTRL +#define SKBLIST_RECVFRAME_REORDERQUEUE 0x00000080 +#endif + +// transmit +#define SKBLIST_XMITBUF_MASK 0x0000FF00 +#define SKBLIST_XMITBUF 0x00000100 +#define SKBLIST_XMITEXTBUF 0x00000200 +#define SKBLIST_XMITBUF_FREEQUEUE 0x00000400 +#define SKBLIST_XMITEXTBUF_FREEQUEUE 0x00000800 +#define SKBLIST_XMITBUF_PENDINGQUEUE 0x00001000 +#ifdef CONFIG_SDIO_TX_MULTI_QUEUE +#define SKBLIST_XMITBUF_PENDING0QUEUE 0x00002000 +#define SKBLIST_XMITBUF_PENDING1QUEUE 0x00004000 +#define SKBLIST_XMITBUF_PENDING2QUEUE 0x00008000 +#endif + +#define SKBLIST_XMITFRAME_MASK 0x0FFF0000 +#define SKBLIST_XMITFRAME 0x00010000 +#define SKBLIST_XMITFRAME_FREEQUEUE 0x00020000 +#define SKBLIST_XMITFRAME_SLEEPQUEUE 0x00040000 +#define SKBLIST_XMITFRAME_VOQUEUE 0x00100000 +#define SKBLIST_XMITFRAME_VIQUEUE 0x00200000 +#define SKBLIST_XMITFRAME_BEQUEUE 0x00400000 +#define SKBLIST_XMITFRAME_BKQUEUE 0x00800000 +#define SKBLIST_XMITFRAME_BMQUEUE 0x01000000 + +#define SKBLIST_POOL 0x10000000 +#endif + +enum _NIC_VERSION { + + RTL8711_NIC, + RTL8712_NIC, + RTL8713_NIC, + RTL8716_NIC + +}; + +typedef struct _ADAPTER _adapter, ADAPTER,*PADAPTER; + +#include "wireless.h" +#include +#include +#include +#include +#include + +#include + +#ifdef CONFIG_80211N_HT +#include +#endif + +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_INCLUDE_WPA_PSK +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_P2P_NEW +#include +#endif +//#include +#include +#include + +#include + +#include + +#ifdef CONFIG_WAPI_SUPPORT +#include +#endif + +#ifdef CONFIG_DRVEXT_MODULE +#include +#endif + +#ifdef CONFIG_MP_INCLUDED +#include +#endif + +#ifdef CONFIG_BR_EXT +#include +#endif // CONFIG_BR_EXT + +#ifdef CONFIG_IOCTL_CFG80211 + #include "ioctl_cfg80211.h" +#endif //CONFIG_IOCTL_CFG80211 + +#define SPEC_DEV_ID_NONE BIT(0) +#define SPEC_DEV_ID_DISABLE_HT BIT(1) +#define SPEC_DEV_ID_ENABLE_PS BIT(2) +#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3) +#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4) +#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5) + +struct specific_device_id{ + + u32 flags; + + u16 idVendor; + u16 idProduct; + +}; + +struct registry_priv +{ + u8 chip_version; +// u8 rfintfs; +// u8 lbkmode; + u8 hci; + NDIS_802_11_SSID ssid; +// u8 network_mode; //infra, ad-hoc, auto + u8 channel;//ad-hoc support requirement + u8 wireless_mode;//A, B, G, auto + u8 scan_mode;//active, passive +// u8 radio_enable; +// u8 preamble;//long, short, auto + u8 vrtl_carrier_sense;//Enable, Disable, Auto + u8 vcs_type;//RTS/CTS, CTS-to-self + u16 rts_thresh; +// u8 adhoc_tx_pwr; + u8 soft_ap; + u8 power_mgnt; + u8 ps_enable; + u8 ips_mode; + u8 smart_ps; +// u8 long_retry_lmt; +// u8 short_retry_lmt; +// u16 busy_thresh; +// u8 ack_policy; + u8 mp_mode; + u8 software_encrypt; + u8 software_decrypt; + #ifdef CONFIG_TX_EARLY_MODE + u8 early_mode; + #endif + u8 acm_method; + //UAPSD + u8 wmm_enable; + u8 uapsd_enable; +// u8 uapsd_max_sp; +// u8 uapsd_acbk_en; +// u8 uapsd_acbe_en; +// u8 uapsd_acvi_en; +// u8 uapsd_acvo_en; + +// WLAN_BSSID_EX dev_network; + u32 beacon_period; + +#ifdef CONFIG_80211N_HT + u8 ht_enable; +#if !defined(NOT_SUPPORT_40M) + u8 cbw40_enable; +#endif + u8 ampdu_enable;//for tx + u8 rx_stbc; + u8 ampdu_amsdu;//A-MPDU Supports A-MSDU is permitted +#endif + //u8 lowrate_two_xmit; + + u8 rf_config ; +// u8 low_power ; + u8 power_percentage_idx; + + u8 wifi_spec;// !turbo_mode + + u8 channel_plan; +#ifdef CONFIG_BT_COEXIST + u8 btcoex; + u8 bt_iso; + u8 bt_sco; + u8 bt_ampdu; +#endif +#if RX_AGGREGATION + BOOLEAN bAcceptAddbaReq; +#endif +// u8 antdiv_cfg; +// u8 antdiv_type; + +#ifdef CONFIG_AUTOSUSPEND + u8 usbss_enable;//0:disable,1:enable +#endif +#ifdef SUPPORT_HW_RFOFF_DETECTED + u8 hwpdn_mode;//0:disable,1:enable,2:decide by EFUSE config + u8 hwpwrp_detect;//0:disable,1:enable +#endif +#ifdef CONFIG_SUPPORT_HW_WPS_PBC + u8 hw_wps_pbc;//0:disable,1:enable +#endif + +#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE + char adaptor_info_caching_file_path[PATH_LENGTH_MAX]; +#endif + +#ifdef CONFIG_LAYER2_ROAMING + u8 max_roaming_times; // the max number driver will try to roaming +#endif + +#ifdef CONFIG_IOL + bool force_iol; //enable iol without other concern +#endif + +#ifdef CONFIG_80211D + u8 enable80211d; +#endif + + u8 ifname[16]; + u8 if2name[16]; + +#if (RTW_NOTCH_FILTER != 0) + u8 notch_filter; +#endif + +#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV + u8 force_ant;//0 normal,1 main,2 aux + u8 force_igi;//0 normal +#endif + + //define for tx power adjust + u8 RegEnableTxPowerLimit; + u8 RegEnableTxPowerByRate; +#ifdef CONFIG_RF_GAIN_OFFSET + u8 RegEnableKFree; +#endif + u8 RegPowerBase; + u8 RegPwrTblSel; + + u8 adaptivity_en; + u8 adaptivity_mode; + u8 adaptivity_dml; + u8 adaptivity_dc_backoff; + s8 adaptivity_th_l2h_ini; +// u8 nhm_en; +}; + +//For registry parameters +#define RGTRY_OFT(field) ((u32)FIELD_OFFSET(struct registry_priv,field)) +#define RGTRY_SZ(field) sizeof(((struct registry_priv*) 0)->field) +#define BSSID_OFT(field) ((u32)FIELD_OFFSET(WLAN_BSSID_EX,field)) +#define BSSID_SZ(field) sizeof(((PWLAN_BSSID_EX) 0)->field) + +#define MAX_CONTINUAL_URB_ERR 4 + +#ifdef CONFIG_CONCURRENT_MODE +#define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER) +#define get_iface_type(adapter) (adapter->iface_type) +#else +#define is_primary_adapter(adapter) (1) +#define get_iface_type(adapter) (IFACE_PORT0) +#endif + +enum _IFACE_TYPE { + IFACE_PORT0, //mapping to port0 for C/D series chips + IFACE_PORT1, //mapping to port1 for C/D series chip + MAX_IFACE_PORT, +}; + +enum _ADAPTER_TYPE { + PRIMARY_ADAPTER, + SECONDARY_ADAPTER, + MAX_ADAPTER, +}; + +struct dvobj_priv +{ + void *if1; +#ifdef CONFIG_CONCURRENT_MODE + void *if2; +#endif + + //For 92D, DMDP have 2 interface. + //u8 InterfaceNumber; + //u8 NumInterfaces; +#ifdef CONFIG_CONCURRENT_MODE + void *padapters[MAX_IFACE_PORT]; + u8 iface_nums; // total number of ifaces used runtime +#endif + //In /Out Pipe information + //int RtInPipe[2]; + u8 RtOutPipe[3];//int RtOutPipe[3]; + u8 Queue2Pipe[HW_QUEUE_ENTRY];//for out pipe mapping + + //u8 irq_alloc; + +/*-------- below is for SDIO INTERFACE --------*/ +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + // + // SDIO ISR Related + // + u32 sdio_himr; + + // + // SDIO Tx FIFO related. + // + // HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg + u8 SdioTxFIFOFreePage[TX_FREE_PG_QUEUE]; + _lock SdioTxFIFOFreePageLock; + + // + // SDIO Rx FIFO related. + // + u16 SdioRxFIFOSize; + +#ifdef INTF_DATA + INTF_DATA intf_data; +#endif +#endif //CONFIG_SDIO_HCI + +/*-------- below is for USB INTERFACE --------*/ + +#ifdef CONFIG_USB_HCI + + u8 irq_alloc; + u8 nr_endpoint; + u8 ishighspeed; + u8 RtNumInPipes; + u8 RtNumOutPipes; + int ep_num[5]; //endpoint number + + int RegUsbSS; + + _sema usb_suspend_sema; + +#ifdef CONFIG_USB_VENDOR_REQ_MUTEX + _mutex usb_vendor_req_mutex; +#endif + +#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC + u8 * usb_alloc_vendor_req_buf; + u8 * usb_vendor_req_buf; +#endif + +#ifdef PLATFORM_WINDOWS + //related device objects + PDEVICE_OBJECT pphysdevobj;//pPhysDevObj; + PDEVICE_OBJECT pfuncdevobj;//pFuncDevObj; + PDEVICE_OBJECT pnextdevobj;//pNextDevObj; + + u8 nextdevstacksz;//unsigned char NextDeviceStackSize; //= (CHAR)CEdevice->pUsbDevObj->StackSize + 1; + + //urb for control diescriptor request + +#ifdef PLATFORM_OS_XP + struct _URB_CONTROL_DESCRIPTOR_REQUEST descriptor_urb; + PUSB_CONFIGURATION_DESCRIPTOR pconfig_descriptor;//UsbConfigurationDescriptor; +#endif + +#ifdef PLATFORM_OS_CE + WCHAR active_path[MAX_ACTIVE_REG_PATH]; // adapter regpath + USB_EXTENSION usb_extension; + + _nic_hdl pipehdls_r8192c[0x10]; +#endif + + u32 config_descriptor_len;//u32 UsbConfigurationDescriptorLength; +#endif//PLATFORM_WINDOWS + +#ifdef PLATFORM_LINUX + struct usb_interface *pusbintf; + struct usb_device *pusbdev; +#endif//PLATFORM_LINUX + +#ifdef PLATFORM_FREEBSD + struct usb_interface *pusbintf; + struct usb_device *pusbdev; +#endif//PLATFORM_FREEBSD + ATOMIC_T continual_urb_error; +#endif//CONFIG_USB_HCI + +/*-------- below is for PCIE INTERFACE --------*/ + +#ifdef CONFIG_PCI_HCI + u8 irq_alloc; + +#ifdef PLATFORM_LINUX + struct pci_dev *ppcidev; + + //PCI MEM map + unsigned long pci_mem_end; /* shared mem end */ + unsigned long pci_mem_start; /* shared mem start */ + + //PCI IO map + unsigned long pci_base_addr; /* device I/O address */ + + //PciBridge + struct pci_priv pcipriv; + + u16 irqline; + u8 irq_enabled; + RT_ISR_CONTENT isr_content; + _lock irq_th_lock; + + //ASPM + u8 const_pci_aspm; + u8 const_amdpci_aspm; + u8 const_hwsw_rfoff_d3; + u8 const_support_pciaspm; + // pci-e bridge */ + u8 const_hostpci_aspm_setting; + // pci-e device */ + u8 const_devicepci_aspm_setting; + u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00. + u8 b_support_backdoor; + u8 bdma64; +#endif//PLATFORM_LINUX + +#if defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) + u8 irq_enabled; + _lock irq_th_lock; +#endif //PLATFORM_FREERTOS + +#endif//CONFIG_PCI_HCI + +#ifdef CONFIG_LX_HCI + u8 irq_alloc; +#if defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) + u8 irq_enabled; + _lock irq_th_lock; +#endif //PLATFORM_FREERTOS +#endif + +}; + +#ifdef PLATFORM_LINUX +static struct device *dvobj_to_dev(struct dvobj_priv *dvobj) +{ + /* todo: get interface type from dvobj and the return the dev accordingly */ +#ifdef RTW_DVOBJ_CHIP_HW_TYPE +#endif + +#ifdef CONFIG_USB_HCI + return &dvobj->pusbintf->dev; +#endif +#ifdef CONFIG_SDIO_HCI + return &dvobj->intf_data.func->dev; +#endif +#ifdef CONFIG_GSPI_HCI + return &dvobj->intf_data.func->dev; +#endif +#ifdef CONFIG_PCI_HCI + return &dvobj->ppcidev->dev; +#endif +} +#endif + +#ifdef CONFIG_CONCURRENT_MODE +struct co_data_priv{ + + //george@20120518 + //current operating channel/bw/ch_offset + //save the correct ch/bw/ch_offset whatever the inputted values are + //when calling set_channel_bwmode() at concurrent mode + //for debug check or reporting to layer app (such as wpa_supplicant for nl80211) + u8 co_ch; + u8 co_bw; + u8 co_ch_offset; + u8 rsvd; + +}; +#endif //CONFIG_CONCURRENT_MODE + +typedef enum _DRIVER_STATE{ + DRIVER_NORMAL = 0, + DRIVER_DISAPPEAR = 1, + DRIVER_REPLACE_DONGLE = 2, +}DRIVER_STATE; + +#ifdef CONFIG_INTEL_PROXIM +struct proxim { + bool proxim_support; + bool proxim_on; + + void *proximity_priv; + int (*proxim_rx)(_adapter *padapter, + union recv_frame *precv_frame); + u8 (*proxim_get_var)(_adapter* padapter, u8 type); +}; +#endif //CONFIG_INTEL_PROXIM + +#ifdef CONFIG_MAC_LOOPBACK_DRIVER +typedef struct loopbackdata +{ + _sema sema; + _thread_hdl_ lbkthread; + u8 bstop; + u32 cnt; + u16 size; + u16 txsize; + u8 txbuf[0x8000]; + u16 rxsize; + u8 rxbuf[0x8000]; + u8 msg[100]; + +}LOOPBACKDATA, *PLOOPBACKDATA; +#endif + +struct _ADAPTER{ +#ifdef CONFIG_EASY_REPLACEMENT + int DriverState;// for disable driver using module, use dongle to replace module. + int bDongle;//build-in module or external dongle + +#endif +#ifdef PLATFORM_LINUX + int pid[3];//process id from UI, 0:wps, 1:hostapd, 2:dhcpcd +#endif + +#ifdef CONFIG_PROC_DEBUG + u16 chip_type; +#endif + + u16 HardwareType; + u16 interface_type;//USB,SDIO,SPI,PCI + u32 work_mode; //STA, AP, STA+AP, PROMISC, P2P + + struct dvobj_priv *dvobj; + struct mlme_priv mlmepriv; + struct mlme_ext_priv mlmeextpriv; + struct cmd_priv cmdpriv; + struct evt_priv evtpriv; + //struct io_queue *pio_queue; + struct io_priv iopriv; + struct xmit_priv xmitpriv; + struct recv_priv recvpriv; + struct sta_priv stapriv; + struct security_priv securitypriv; + struct registry_priv registrypriv; + struct pwrctrl_priv pwrctrlpriv; + struct eeprom_priv eeprompriv; +//TODO +// struct led_priv ledpriv; + + +#ifdef CONFIG_MP_INCLUDED + struct mp_priv mppriv; +#endif + +#ifdef CONFIG_DRVEXT_MODULE + struct drvext_priv drvextpriv; +#endif + +#if defined(CONFIG_HOSTAPD_MLME) && defined (CONFIG_AP_MODE) + struct hostapd_priv *phostapdpriv; +#endif + +#ifdef CONFIG_IOCTL_CFG80211 +#ifdef CONFIG_P2P + struct cfg80211_wifidirect_info cfg80211_wdinfo; +#endif //CONFIG_P2P +#endif //CONFIG_IOCTL_CFG80211 + +#ifdef CONFIG_P2P_NEW + struct wifidirect_info wdinfo; +#endif //CONFIG_P2P + +#ifdef CONFIG_TDLS + struct tdls_info tdlsinfo; +#endif //CONFIG_TDLS + +#ifdef CONFIG_WAPI_SUPPORT + u8 WapiSupport; + RT_WAPI_T wapiInfo; +#endif + + +#ifdef CONFIG_WFD + struct wifi_display_info wfd_info; +#endif //CONFIG_WFD + + PVOID HalData; + u32 hal_data_sz; + struct hal_ops HalFunc; + + s32 bDriverStopped; + s32 bSurpriseRemoved; + s32 bCardDisableWOHSM; + u8 RxStop; //Used to stop rx thread as early as possible + + u32 IsrContent; + u32 ImrContent; + + u8 EepromAddressSize; + u8 hw_init_completed; + u8 bDriverIsGoingToUnload; + u8 init_adpt_in_progress; + u8 bMpDriver; + +#ifdef CONFIG_AP_MODE + u8 bForwardingDisabled; +#endif + +#if defined(CONFIG_EVENT_THREAD_MODE) + _thread_hdl_ evtThread; +#endif +#if defined(CONFIG_ISR_THREAD_MODE_POLLING) || defined(CONFIG_ISR_THREAD_MODE_INTERRUPT) + struct task_struct isrThread; +#endif + struct task_struct cmdThread; +#ifdef CONFIG_XMIT_THREAD_MODE + struct task_struct xmitThread; +#endif +#if defined(CONFIG_RECV_THREAD_MODE) + struct task_struct recvThread; +#endif +#ifdef CONFIG_RECV_TASKLET_THREAD + struct task_struct recvtasklet_thread; +#endif +#ifdef CONFIG_XMIT_TASKLET_THREAD +#ifdef PLATFORM_LINUX + struct tasklet_struct xmit_tasklet; +#else + struct task_struct xmittasklet_thread; +#endif +#endif +#ifdef CONFIG_SDIO_XMIT_THREAD + struct task_struct SdioXmitThread; +#endif //CONFIG_XMIT_TASKLET_THREAD + + +#if !defined(PLATFORM_LINUX) && !defined(PLATFORM_ECOS) && !defined(PLATFORM_FREERTOS) && !defined(PLATFORM_CMSIS_RTOS) + NDIS_STATUS (*dvobj_init)(struct dvobj_priv *dvobj); + void (*dvobj_deinit)(struct dvobj_priv *dvobj); +#endif + + void (*intf_start)(_adapter * adapter); + void (*intf_stop)(_adapter * adapter); + +#ifdef PLATFORM_WINDOWS + _nic_hdl hndis_adapter;//hNdisAdapter(NDISMiniportAdapterHandle); + _nic_hdl hndis_config;//hNdisConfiguration; + NDIS_STRING fw_img; + + u32 NdisPacketFilter; + u8 MCList[MAX_MCAST_LIST_NUM][6]; + u32 MCAddrCount; +#endif //end of PLATFORM_WINDOWS + +#ifdef PLATFORM_ECOS + _nic_hdl pnetdev; + int bup; + struct net_device_stats stats; +#endif //#ifdef PLATFORM_ECOS + +#if defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) + _nic_hdl pnetdev; + int bup; + struct net_device_stats stats; +#endif //#ifdef PLATFORM_FREERTOS + +#ifdef PLATFORM_LINUX + _nic_hdl pnetdev; + + // used by rtw_rereg_nd_name related function + struct rereg_nd_name_data { + _nic_hdl old_pnetdev; + char old_ifname[IFNAMSIZ]; + u8 old_ips_mode; + u8 old_bRegUseLed; + } rereg_nd_name_priv; + + int bup; + struct net_device_stats stats; + struct iw_statistics iwstats; + struct proc_dir_entry *dir_dev;// for proc directory + +#ifdef CONFIG_IOCTL_CFG80211 + struct wireless_dev *rtw_wdev; +#endif //CONFIG_IOCTL_CFG80211 + +#endif //end of PLATFORM_LINUX + +#ifdef PLATFORM_FREEBSD + _nic_hdl pifp; + int bup; + _lock glock; +#endif //PLATFORM_FREEBSD + u8 net_closed; + + u8 bFWReady; + //u8 bBTFWReady; + //u8 bReadPortCancel; + //u8 bWritePortCancel; + u8 bLinkInfoDump; + u8 bRxRSSIDisplay; +#ifdef CONFIG_AUTOSUSPEND + u8 bDisableAutosuspend; +#endif + + _adapter *pbuddy_adapter; + + _mutex *hw_init_mutex; +#if defined(CONFIG_CONCURRENT_MODE) + u8 isprimary; //is primary adapter or not + u8 adapter_type; + u8 iface_type; //interface port type + + //for global synchronization + _mutex *ph2c_fwcmd_mutex; + _mutex *psetch_mutex; + _mutex *psetbw_mutex; + + struct co_data_priv *pcodatapriv;//data buffer shared among interfaces +#endif + +#ifdef CONFIG_BR_EXT + _lock br_ext_lock; + //unsigned int macclone_completed; + struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE]; + int pppoe_connection_in_progress; + unsigned char pppoe_addr[MACADDRLEN]; + unsigned char scdb_mac[MACADDRLEN]; + unsigned char scdb_ip[4]; + struct nat25_network_db_entry *scdb_entry; + unsigned char br_mac[MACADDRLEN]; + unsigned char br_ip[4]; + + struct br_ext_info ethBrExtInfo; +#endif // CONFIG_BR_EXT + +#ifdef CONFIG_INTEL_PROXIM + /* intel Proximity, should be alloc mem + * in intel Proximity module and can only + * be used in intel Proximity mode */ + struct proxim proximity; +#endif //CONFIG_INTEL_PROXIM + +#ifdef CONFIG_MAC_LOOPBACK_DRIVER + PLOOPBACKDATA ploopback; +#endif + + u8 fix_rate; +#ifdef CONFIG_CAC_TEST + unsigned char in_cta_test; +#endif + /* This flag is used to dynamically enabling debug message if + certain sympton happen. Use iwpriv command to enable it */ +#if defined(CONFIG_DEBUG_DYNAMIC) + u8 debug_level; +#endif + +}; + +#define adapter_to_dvobj(adapter) (adapter->dvobj) +#define adapter_to_pwrctl(adapter) (&adapter->pwrctrlpriv) + +int rtw_handle_dualmac(_adapter *adapter, bool init); + +__inline static u8 *myid(struct eeprom_priv *peepriv) +{ + return (peepriv->mac_addr); +} + +#if 0 //#if (CONFIG_LWIP_LAYER == 0) +// For FPGA test program +#define _htons(x) (x) +#define _htons(x) (x) +#define _htons(x) (x) +#define _htons(x) (x) +#endif + +//fast reconnection function prototype +typedef int (*init_done_ptr)(void); +#endif //__DRV_TYPES_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/ethernet.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/ethernet.h new file mode 100644 index 0000000..e6c220e --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/ethernet.h @@ -0,0 +1,42 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/*! \file */ +#ifndef __INC_ETHERNET_H +#define __INC_ETHERNET_H + +#define ETHERNET_ADDRESS_LENGTH 6 //!< Ethernet Address Length +#define ETHERNET_HEADER_SIZE 14 //!< Ethernet Header Length +#define LLC_HEADER_SIZE 6 //!< LLC Header Length +#define TYPE_LENGTH_FIELD_SIZE 2 //!< Type/Length Size +#define MINIMUM_ETHERNET_PACKET_SIZE 60 //!< Minimum Ethernet Packet Size +#define MAXIMUM_ETHERNET_PACKET_SIZE 1514 //!< Maximum Ethernet Packet Size + +#define RT_ETH_IS_MULTICAST(_pAddr) ((((u8 *)(_pAddr))[0]&0x01)!=0) //!< Is Multicast Address? +#define RT_ETH_IS_BROADCAST(_pAddr) ( \ + ((u8 *)(_pAddr))[0]==0xff && \ + ((u8 *)(_pAddr))[1]==0xff && \ + ((u8 *)(_pAddr))[2]==0xff && \ + ((u8 *)(_pAddr))[3]==0xff && \ + ((u8 *)(_pAddr))[4]==0xff && \ + ((u8 *)(_pAddr))[5]==0xff ) //!< Is Broadcast Address? + + +#endif // #ifndef __INC_ETHERNET_H + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_com.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_com.h new file mode 100644 index 0000000..d096386 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_com.h @@ -0,0 +1,287 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_COMMON_H__ +#define __HAL_COMMON_H__ + +#include "HalVerDef.h" +#include "hal_pg.h" +#include "hal_intf.h" +#include "hal_phy.h" +#include "hal_phy_reg.h" +#include "hal_com_reg.h" +#include "hal_com_phycfg.h" + +//---------------------------------------------------------------------------- +// Rate Definition +//---------------------------------------------------------------------------- +//CCK +#define RATR_1M 0x00000001 +#define RATR_2M 0x00000002 +#define RATR_55M 0x00000004 +#define RATR_11M 0x00000008 +//OFDM +#define RATR_6M 0x00000010 +#define RATR_9M 0x00000020 +#define RATR_12M 0x00000040 +#define RATR_18M 0x00000080 +#define RATR_24M 0x00000100 +#define RATR_36M 0x00000200 +#define RATR_48M 0x00000400 +#define RATR_54M 0x00000800 +//MCS 1 Spatial Stream +#define RATR_MCS0 0x00001000 +#define RATR_MCS1 0x00002000 +#define RATR_MCS2 0x00004000 +#define RATR_MCS3 0x00008000 +#define RATR_MCS4 0x00010000 +#define RATR_MCS5 0x00020000 +#define RATR_MCS6 0x00040000 +#define RATR_MCS7 0x00080000 +//MCS 2 Spatial Stream +#define RATR_MCS8 0x00100000 +#define RATR_MCS9 0x00200000 +#define RATR_MCS10 0x00400000 +#define RATR_MCS11 0x00800000 +#define RATR_MCS12 0x01000000 +#define RATR_MCS13 0x02000000 +#define RATR_MCS14 0x04000000 +#define RATR_MCS15 0x08000000 + +//CCK +#define RATE_1M BIT(0) +#define RATE_2M BIT(1) +#define RATE_5_5M BIT(2) +#define RATE_11M BIT(3) +//OFDM +#define RATE_6M BIT(4) +#define RATE_9M BIT(5) +#define RATE_12M BIT(6) +#define RATE_18M BIT(7) +#define RATE_24M BIT(8) +#define RATE_36M BIT(9) +#define RATE_48M BIT(10) +#define RATE_54M BIT(11) +//MCS 1 Spatial Stream +#define RATE_MCS0 BIT(12) +#define RATE_MCS1 BIT(13) +#define RATE_MCS2 BIT(14) +#define RATE_MCS3 BIT(15) +#define RATE_MCS4 BIT(16) +#define RATE_MCS5 BIT(17) +#define RATE_MCS6 BIT(18) +#define RATE_MCS7 BIT(19) +//MCS 2 Spatial Stream +#define RATE_MCS8 BIT(20) +#define RATE_MCS9 BIT(21) +#define RATE_MCS10 BIT(22) +#define RATE_MCS11 BIT(23) +#define RATE_MCS12 BIT(24) +#define RATE_MCS13 BIT(25) +#define RATE_MCS14 BIT(26) +#define RATE_MCS15 BIT(27) + +// ALL CCK Rate +#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M +#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\ + RATR_36M|RATR_48M|RATR_54M +#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\ + RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 +#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\ + RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 + +/*------------------------------ Tx Desc definition Macro ------------------------*/ +//#pragma mark -- Tx Desc related definition. -- +//---------------------------------------------------------------------------- +//----------------------------------------------------------- +// Rate +//----------------------------------------------------------- +// CCK Rates, TxHT = 0 +#define DESC_RATE1M 0x00 +#define DESC_RATE2M 0x01 +#define DESC_RATE5_5M 0x02 +#define DESC_RATE11M 0x03 + +// OFDM Rates, TxHT = 0 +#define DESC_RATE6M 0x04 +#define DESC_RATE9M 0x05 +#define DESC_RATE12M 0x06 +#define DESC_RATE18M 0x07 +#define DESC_RATE24M 0x08 +#define DESC_RATE36M 0x09 +#define DESC_RATE48M 0x0a +#define DESC_RATE54M 0x0b + +// MCS Rates, TxHT = 1 +#define DESC_RATEMCS0 0x0c +#define DESC_RATEMCS1 0x0d +#define DESC_RATEMCS2 0x0e +#define DESC_RATEMCS3 0x0f +#define DESC_RATEMCS4 0x10 +#define DESC_RATEMCS5 0x11 +#define DESC_RATEMCS6 0x12 +#define DESC_RATEMCS7 0x13 +#define DESC_RATEMCS8 0x14 +#define DESC_RATEMCS9 0x15 +#define DESC_RATEMCS10 0x16 +#define DESC_RATEMCS11 0x17 +#define DESC_RATEMCS12 0x18 +#define DESC_RATEMCS13 0x19 +#define DESC_RATEMCS14 0x1a +#define DESC_RATEMCS15 0x1b +#define DESC_RATEMCS16 0x1C +#define DESC_RATEMCS17 0x1D +#define DESC_RATEMCS18 0x1E +#define DESC_RATEMCS19 0x1F +#define DESC_RATEMCS20 0x20 +#define DESC_RATEMCS21 0x21 +#define DESC_RATEMCS22 0x22 +#define DESC_RATEMCS23 0x23 +#define DESC_RATEMCS24 0x24 +#define DESC_RATEMCS25 0x25 +#define DESC_RATEMCS26 0x26 +#define DESC_RATEMCS27 0x27 +#define DESC_RATEMCS28 0x28 +#define DESC_RATEMCS29 0x29 +#define DESC_RATEMCS30 0x2A +#define DESC_RATEMCS31 0x2B + +#define DESC_RATEVHTSS1MCS0 0x2c +#define DESC_RATEVHTSS1MCS1 0x2d +#define DESC_RATEVHTSS1MCS2 0x2e +#define DESC_RATEVHTSS1MCS3 0x2f +#define DESC_RATEVHTSS1MCS4 0x30 +#define DESC_RATEVHTSS1MCS5 0x31 +#define DESC_RATEVHTSS1MCS6 0x32 +#define DESC_RATEVHTSS1MCS7 0x33 +#define DESC_RATEVHTSS1MCS8 0x34 +#define DESC_RATEVHTSS1MCS9 0x35 +#define DESC_RATEVHTSS2MCS0 0x36 +#define DESC_RATEVHTSS2MCS1 0x37 +#define DESC_RATEVHTSS2MCS2 0x38 +#define DESC_RATEVHTSS2MCS3 0x39 +#define DESC_RATEVHTSS2MCS4 0x3a +#define DESC_RATEVHTSS2MCS5 0x3b +#define DESC_RATEVHTSS2MCS6 0x3c +#define DESC_RATEVHTSS2MCS7 0x3d +#define DESC_RATEVHTSS2MCS8 0x3e +#define DESC_RATEVHTSS2MCS9 0x3f +#define DESC_RATEVHTSS3MCS0 0x40 +#define DESC_RATEVHTSS3MCS1 0x41 +#define DESC_RATEVHTSS3MCS2 0x42 +#define DESC_RATEVHTSS3MCS3 0x43 +#define DESC_RATEVHTSS3MCS4 0x44 +#define DESC_RATEVHTSS3MCS5 0x45 +#define DESC_RATEVHTSS3MCS6 0x46 +#define DESC_RATEVHTSS3MCS7 0x47 +#define DESC_RATEVHTSS3MCS8 0x48 +#define DESC_RATEVHTSS3MCS9 0x49 +#define DESC_RATEVHTSS4MCS0 0x4A +#define DESC_RATEVHTSS4MCS1 0x4B +#define DESC_RATEVHTSS4MCS2 0x4C +#define DESC_RATEVHTSS4MCS3 0x4D +#define DESC_RATEVHTSS4MCS4 0x4E +#define DESC_RATEVHTSS4MCS5 0x4F +#define DESC_RATEVHTSS4MCS6 0x50 +#define DESC_RATEVHTSS4MCS7 0x51 +#define DESC_RATEVHTSS4MCS8 0x52 +#define DESC_RATEVHTSS4MCS9 0x53 + +typedef enum _FIRMWARE_SOURCE { + FW_SOURCE_IMG_FILE = 0, + FW_SOURCE_HEADER_FILE = 1, //from header file +} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE; + +// BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. +//#define MAX_TX_QUEUE 9 + +#define TX_SELE_HQ BIT(0) // High Queue +#define TX_SELE_LQ BIT(1) // Low Queue +#define TX_SELE_NQ BIT(2) // Normal Queue +#define TX_SELE_EQ BIT(3) // Extern Queue + +#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0)) +#define PageNum_256(_Len) (u32)(((_Len)>>8) + ((_Len)&0xFF ? 1:0)) +#define PageNum_512(_Len) (u32)(((_Len)>>9) + ((_Len)&0x1FF ? 1:0)) +#define PageNum(_Len, _Size) (u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1:0)) + +#define DYNAMIC_FUNC_DISABLE (0x0) +#define DYNAMIC_ALL_FUNC_ENABLE 0xFFFFFFF + +void dump_chip_info(HAL_VERSION ChipVersion); + + +u8 //return the final channel plan decision +hal_com_get_channel_plan( + IN PADAPTER padapter, + IN u8 hw_channel_plan, //channel plan from HW (efuse/eeprom) + IN u8 sw_channel_plan, //channel plan from SW (registry/module param) + IN u8 def_channel_plan, //channel plan used when the former two is invalid + IN BOOLEAN AutoLoadFail + ); + +u8 MRateToHwRate(u8 rate); + +void HalSetBrateCfg( + IN PADAPTER Adapter, + IN u8 *mBratesOS, + OUT u16 *pBrateCfg); + +BOOLEAN +Hal_MappingOutPipe( + IN PADAPTER pAdapter, + IN u8 NumOutPipe + ); + +BOOLEAN +HAL_IsLegalChannel( + IN _adapter * Adapter, + IN u32 Channel + ); + +void hal_init_macaddr(_adapter *adapter); +void SetHwReg(PADAPTER padapter, u8 variable, u8 *val); +void GetHwReg(PADAPTER padapter, u8 variable, u8 *val); + +#if defined (CONFIG_RTL8188F) || defined (CONFIG_RTL8711B) +typedef enum _RT_MEDIA_STATUS { + RT_MEDIA_DISCONNECT = 0, + RT_MEDIA_CONNECT = 1 +} RT_MEDIA_STATUS; + + +void GetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + PVOID pValue2); + +void SetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + BOOLEAN bSet); + +u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value); +u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value); +void rtw_hal_wow_enable(_adapter *adapter); +void rtw_hal_wow_disable(_adapter *adapter); +#endif +#endif //__HAL_COMMON_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_com_phycfg.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_com_phycfg.h new file mode 100644 index 0000000..5cb5366 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_com_phycfg.h @@ -0,0 +1,288 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_COM_PHYCFG_H__ +#define __HAL_COM_PHYCFG_H__ + +#define PathA 0x0 // Useless +#define PathB 0x1 +#define PathC 0x2 +#define PathD 0x3 + +typedef enum _RATE_SECTION { + CCK = 0, + OFDM, + HT_MCS0_MCS7, + HT_MCS8_MCS15, + HT_MCS16_MCS23, + HT_MCS24_MCS31, + VHT_1SSMCS0_1SSMCS9, + VHT_2SSMCS0_2SSMCS9, + VHT_3SSMCS0_3SSMCS9, + VHT_4SSMCS0_4SSMCS9, +} RATE_SECTION; + +typedef enum _RF_TX_NUM { + RF_1TX = 0, + RF_2TX, + RF_3TX, + RF_4TX, + RF_MAX_TX_NUM, + RF_TX_NUM_NONIMPLEMENT, +} RF_TX_NUM; + +#define MAX_POWER_INDEX 0x3F + +typedef enum _REGULATION_TXPWR_LMT { + TXPWR_LMT_FCC = 0, + TXPWR_LMT_MKK = 1, + TXPWR_LMT_ETSI = 2, + TXPWR_LMT_WW = 3, // WW13, The mininum of ETSI,MKK + TXPWR_LMT_GL = 4, // Global, The mininum of ETSI,MKK,FCC + TXPWR_LMT_MAX_REGULATION_NUM = 5 +} REGULATION_TXPWR_LMT; + +/*------------------------------Define structure----------------------------*/ +typedef struct _BB_REGISTER_DEFINITION{ + u32 rfintfs; // set software control: + // 0x870~0x877[8 bytes] + + u32 rfintfo; // output data: + // 0x860~0x86f [16 bytes] + + u32 rfintfe; // output enable: + // 0x860~0x86f [16 bytes] + + u32 rf3wireOffset; // LSSI data: + // 0x840~0x84f [16 bytes] + + u32 rfHSSIPara2; // wire parameter control2 : + // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] + + u32 rfLSSIReadBack; //LSSI RF readback data SI mode + // 0x8a0~0x8af [16 bytes] + + u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B + +}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; + + +//---------------------------------------------------------------------- +s32 +phy_TxPwrIdxToDbm( + IN PADAPTER Adapter, + IN WIRELESS_MODE WirelessMode, + IN u8 TxPwrIdx + ); + +u8 +PHY_GetTxPowerByRateBase( + IN PADAPTER Adapter, + IN u8 Band, + IN u8 RfPath, + IN u8 TxNum, + IN RATE_SECTION RateSection + ); + +u8 +PHY_GetRateSectionIndexOfTxPowerByRate( + IN PADAPTER pAdapter, + IN u32 RegAddr, + IN u32 BitMask + ); + +VOID +PHY_GetRateValuesOfTxPowerByRate( + IN PADAPTER pAdapter, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Value, + OUT u8* RateIndex, + OUT s8* PwrByRateVal, + OUT u8* RateNum + ); + +u8 +PHY_GetRateIndexOfTxPowerByRate( + IN u8 Rate + ); + +VOID +PHY_SetTxPowerIndexByRateSection( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Channel, + IN u8 RateSection + ); + +s8 +PHY_GetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 TxNum, + IN u8 RateIndex + ); + +VOID +PHY_SetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 TxNum, + IN u8 Rate, + IN s8 Value + ); + +VOID +PHY_SetTxPowerLevelByPath( + IN PADAPTER Adapter, + IN u8 channel, + IN u8 path + ); + +VOID +PHY_SetTxPowerIndexByRateArray( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel, + IN u8* Rates, + IN u8 RateArraySize + ); + +VOID +PHY_InitTxPowerByRate( + IN PADAPTER pAdapter + ); + +VOID +PHY_StoreTxPowerByRate( + IN PADAPTER pAdapter, + IN u32 Band, + IN u32 RfPath, + IN u32 TxNum, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data + ); + +VOID +PHY_TxPowerByRateConfiguration( + IN PADAPTER pAdapter + ); + +u8 +PHY_GetTxPowerIndexBase( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel, + OUT PBOOLEAN bIn24G + ); + +s8 +PHY_GetTxPowerLimit( + IN PADAPTER Adapter, + IN u32 RegPwrTblSel, + IN BAND_TYPE Band, + IN CHANNEL_WIDTH Bandwidth, + IN u8 RfPath, + IN u8 DataRate, + IN u8 Channel + ); + +VOID +PHY_SetTxPowerLimit( + IN PADAPTER Adapter, + IN u8 Regulation, + IN u8 Band, + IN u8 Bandwidth, + IN u8 RateSection, + IN u8 RfPath, + IN u8 Channel, + IN u8 PowerLimit + ); + +VOID +PHY_ConvertTxPowerLimitToPowerIndex( + IN PADAPTER Adapter + ); + +VOID +PHY_InitTxPowerLimit( + IN PADAPTER Adapter + ); + +s8 +PHY_GetTxPowerTrackingOffset( + PADAPTER pAdapter, + u8 Rate, + u8 RFPath + ); + +u8 +PHY_GetTxPowerIndex( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel + ); + +VOID +PHY_SetTxPowerIndex( + IN PADAPTER pAdapter, + IN u32 PowerIndex, + IN u8 RFPath, + IN u8 Rate + ); + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE +#define MAX_PARA_FILE_BUF_LEN 25600 + +#define LOAD_MAC_PARA_FILE BIT0 +#define LOAD_BB_PARA_FILE BIT1 +#define LOAD_BB_PG_PARA_FILE BIT2 +#define LOAD_BB_MP_PARA_FILE BIT3 +#define LOAD_RF_PARA_FILE BIT4 +#define LOAD_RF_TXPWR_TRACK_PARA_FILE BIT5 +#define LOAD_RF_TXPWR_LMT_PARA_FILE BIT6 + +int phy_ConfigMACWithParaFile(IN PADAPTER Adapter, IN char* pFileName); + +int phy_ConfigBBWithParaFile(IN PADAPTER Adapter, IN char* pFileName, IN u32 ConfigType); + +int phy_ConfigBBWithPgParaFile(IN PADAPTER Adapter, IN char* pFileName); + +int phy_ConfigBBWithMpParaFile(IN PADAPTER Adapter, IN char* pFileName); + +int PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN char* pFileName, IN u8 eRFPath); + +int PHY_ConfigRFWithTxPwrTrackParaFile(IN PADAPTER Adapter, IN char* pFileName); + +int PHY_ConfigRFWithPowerLimitTableParaFile(IN PADAPTER Adapter, IN char* pFileName); + +void phy_free_filebuf(_adapter *padapter); +#endif //CONFIG_LOAD_PHY_PARA_FROM_FILE + + +#endif //__HAL_COMMON_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_com_reg.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_com_reg.h index 7c9dde0..4e176f4 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_com_reg.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_com_reg.h @@ -20,6 +20,7 @@ #ifndef __HAL_COMMON_REG_H__ #define __HAL_COMMON_REG_H__ + #define MAC_ADDR_LEN 6 #define HAL_NAV_UPPER_UNIT 128 // micro-second @@ -39,21 +40,20 @@ // //----------------------------------------------------- #define REG_SYS_ISO_CTRL 0x0000 -#define REG_SYS_FUNC_EN 0x0002 +#define REG_SYS_FUNC_EN 0x0002 #define REG_APS_FSMCO 0x0004 #define REG_SYS_CLKR 0x0008 -#define REG_SYS_CLK_CTRL REG_SYS_CLKR #define REG_9346CR 0x000A -#define REG_SYS_EEPROM_CTRL 0x000A +#define REG_SYS_EEPROM_CTRL 0x000A #define REG_EE_VPD 0x000C #define REG_AFE_MISC 0x0010 #define REG_SPS0_CTRL 0x0011 #define REG_SPS0_CTRL_6 0x0016 #define REG_POWER_OFF_IN_PROCESS 0x0017 -#define REG_SPS_OCP_CFG 0x0018 +#define REG_SPS_OCP_CFG 0x0018 #define REG_RSV_CTRL 0x001C #define REG_RF_CTRL 0x001F -#define REG_LDOA15_CTRL 0x0020 +#define REG_LDOA15_CTRL 0x0020 #define REG_LDOV12D_CTRL 0x0021 #define REG_LDOHCI12_CTRL 0x0022 #define REG_LPLDO_CTRL 0x0023 @@ -67,9 +67,9 @@ #define REG_PWR_DATA 0x0038 #define REG_CAL_TIMER 0x003C #define REG_ACLK_MON 0x003E -#define REG_GPIO_MUXCFG 0x0040 +#define REG_GPIO_MUXCFG 0x0040 #define REG_GPIO_IO_SEL 0x0042 -#define REG_MAC_PINMUX_CFG 0x0043 +#define REG_MAC_PINMUX_CFG 0x0043 #define REG_GPIO_PIN_CTRL 0x0044 #define REG_GPIO_INTM 0x0048 #define REG_LEDCFG0 0x004C @@ -80,18 +80,18 @@ #define REG_FSISR 0x0054 #define REG_HSIMR 0x0058 #define REG_HSISR 0x005c -#define REG_GPIO_PIN_CTRL_2 0x0060 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. +#define REG_GPIO_PIN_CTRL_2 0x0060 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. #define REG_GPIO_IO_SEL_2 0x0062 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. -#define REG_MULTI_FUNC_CTRL 0x0068 // RTL8723 WIFI/BT/GPS Multi-Function control source. +#define REG_MULTI_FUNC_CTRL 0x0068 // RTL8723 WIFI/BT/GPS Multi-Function control source. #define REG_GSSR 0x006c #define REG_AFE_XTAL_CTRL_EXT 0x0078 //RTL8188E #define REG_XCK_OUT_CTRL 0x007c //RTL8188E -#define REG_MCUFWDL 0x0080 +#define REG_MCUFWDL 0x0080 #define REG_WOL_EVENT 0x0081 //RTL8188E #define REG_MCUTSTCFG 0x0084 #define REG_FDHM0 0x0088 #define REG_HOST_SUSP_CNT 0x00BC // RTL8192C Host suspend counter on FPGA platform -#define REG_SYSTEM_ON_CTRL 0x00CC // For 8723AE Reset after S3 +#define REG_SYSTEM_ON_CTRL 0x00CC // For 8723AE Reset after S3 #define REG_EFUSE_ACCESS 0x00CF // Efuse access protection for RTL8723 #define REG_BIST_SCAN 0x00D0 #define REG_BIST_RPT 0x00D4 @@ -101,13 +101,17 @@ #define REG_PCIE_MIO_INTD 0x00E8 #define REG_HPON_FSM 0x00EC #define REG_SYS_CFG 0x00F0 -#define REG_GPIO_OUTSTS 0x00F4 // For RTL8723 only. +#define REG_GPIO_OUTSTS 0x00F4 // For RTL8723 only. #define REG_TYPE_ID 0x00FC -// -// 2010/12/29 MH Add for 92D -// -#define REG_MAC_PHY_CTRL_NORMAL 0x00f8 + +#define REG_WL_CLK_CTRL 0x0002 +#define REG_WL_FUNC_EN 0x0004 +#define REG_WL_PMC_CTRL 0x0020 +#define REG_WL_AFE_CTRL 0x0050 +#define REG_WL_PMC_IMR 0x0080 +#define REG_WL_PMC_ISR 0x0084 + //----------------------------------------------------- // @@ -117,7 +121,7 @@ #define REG_CR 0x0100 #define REG_PBP 0x0104 #define REG_PKT_BUFF_ACCESS_CTRL 0x0106 -#define REG_TRXDMA_CTRL 0x010C +#define REG_TRXDMA_CTRL 0x010C #define REG_TRXFF_BNDY 0x0114 #define REG_TRXFF_STATUS 0x0118 #define REG_RXFF_PTR 0x011C @@ -130,25 +134,25 @@ #define REG_FWISR 0x0134 #define REG_FTIMR 0x0138 #define REG_FTISR 0x013C //RTL8192C -#define REG_PKTBUF_DBG_CTRL 0x0140 +#define REG_PKTBUF_DBG_CTRL 0x0140 #define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) #define REG_PKTBUF_DBG_DATA_L 0x0144 -#define REG_PKTBUF_DBG_DATA_H 0x0148 +#define REG_PKTBUF_DBG_DATA_H 0x0148 #define REG_TC0_CTRL 0x0150 #define REG_TC1_CTRL 0x0154 #define REG_TC2_CTRL 0x0158 #define REG_TC3_CTRL 0x015C #define REG_TC4_CTRL 0x0160 -#define REG_TCUNIT_BASE 0x0164 -#define REG_MBIST_START 0x0174 +#define REG_TCUNIT_BASE 0x0164 +#define REG_MBIST_START 0x0174 #define REG_MBIST_DONE 0x0178 #define REG_MBIST_FAIL 0x017C #define REG_32K_CTRL 0x0194 //RTL8188E -#define REG_C2HEVT_MSG_NORMAL 0x01A0 +#define REG_C2HEVT_MSG_NORMAL 0x01A0 #define REG_C2HEVT_CLEAR 0x01AF #define REG_MCUTST_1 0x01c0 -#define REG_MCUTST_WOWLAN 0x01C7 // Defined after 8188E series. +#define REG_MCUTST_WOWLAN 0x01C7 // Defined after 8188E series. #define REG_FMETHR 0x01C8 #define REG_HMETFR 0x01CC #define REG_HMEBOX_0 0x01D0 @@ -156,10 +160,6 @@ #define REG_HMEBOX_2 0x01D8 #define REG_HMEBOX_3 0x01DC #define REG_LLT_INIT 0x01E0 -#define REG_HMEBOX_EXT_0 0x01F0 -#define REG_HMEBOX_EXT_1 0x01F4 -#define REG_HMEBOX_EXT_2 0x01F8 -#define REG_HMEBOX_EXT_3 0x01FC //----------------------------------------------------- // @@ -174,14 +174,17 @@ #define REG_RQPN_NPQ 0x0214 #define REG_AUTO_LLT 0x0224 + //----------------------------------------------------- // // 0x0280h ~ 0x02FFh RXDMA Configuration // //----------------------------------------------------- -#define REG_RXDMA_AGG_PG_TH 0x0280 +#define REG_RXDMA_AGG_PG_TH 0x0280 #define REG_RXPKT_NUM 0x0284 #define REG_RXDMA_STATUS 0x0288 +#define REG_C2H_PKT_8723B 0x0294 + //----------------------------------------------------- // @@ -189,62 +192,110 @@ // //----------------------------------------------------- #define REG_PCIE_CTRL_REG 0x0300 -#define REG_INT_MIG 0x0304 /* Interrupt Migration */ -#define REG_BCNQ_DESA 0x0308 /* TX Beacon Descriptor Address */ -#define REG_HQ_DESA 0x0310 /* TX High Queue Descriptor Address */ -#define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descriptor Address */ -#define REG_VOQ_DESA 0x0320 /* TX VO Queue Descriptor Address */ -#define REG_VIQ_DESA 0x0328 /* TX VI Queue Descriptor Address */ -#define REG_BEQ_DESA 0x0330 /* TX BE Queue Descriptor Address */ -#define REG_BKQ_DESA 0x0338 /* TX BK Queue Descriptor Address */ -#define REG_RX_DESA 0x0340 /* RX Queue Descriptor Address */ +#define REG_INT_MIG 0x0304 // Interrupt Migration +#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address +#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address +#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address +#define REG_VOQ_DESA 0x0320 // TX VO Queue Descriptor Address +#define REG_VIQ_DESA 0x0328 // TX VI Queue Descriptor Address +#define REG_BEQ_DESA 0x0330 // TX BE Queue Descriptor Address +#define REG_BKQ_DESA 0x0338 // TX BK Queue Descriptor Address +#define REG_RX_DESA 0x0340 // RX Queue Descriptor Address //sherry added for DBI Read/Write 20091126 -#define REG_DBI_WDATA 0x0348 /* Backdoor REG for Access Configuration */ -#define REG_DBI_RDATA 0x034C /* Backdoor REG for Access Configuration */ -#define REG_DBI_CTRL 0x0350 /* Backdoor REG for Access Configuration */ -#define REG_DBI_FLAG 0x0352 /* Backdoor REG for Access Configuration */ -#define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */ -#define REG_DBG_SEL 0x0360 /* Debug Selection Register */ -#define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */ -#define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */ +#define REG_DBI_WDATA 0x0348 // Backdoor REG for Access Configuration +#define REG_DBI_RDATA 0x034C //Backdoor REG for Access Configuration +#define REG_DBI_CTRL 0x0350 //Backdoor REG for Access Configuration +#define REG_DBI_FLAG 0x0352 //Backdoor REG for Access Configuration +#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY +#define REG_DBG_SEL 0x0360 // Debug Selection Register +#define REG_PCIE_HRPWM 0x0361 //PCIe RPWM +#define REG_PCIE_HCPWM 0x0363 //PCIe CPWM #define REG_WATCH_DOG 0x0368 -#define REG_RX_RXBD_NUM 0x0382 -// RTL8723 series ------------------------------- -#define REG_PCIE_HISR_EN 0x0394 /* PCIE Local Interrupt Enable Register */ -#define REG_PCIE_HISR 0x03A0 -#define REG_PCIE_HISRE 0x03A4 -#define REG_PCIE_HIMR 0x03A8 -#define REG_PCIE_HIMRE 0x03AC +// For new buffer descriptor ring architecture -#define REG_USB_HIMR 0xFE38 -#define REG_USB_HIMRE 0xFE3C -#define REG_USB_HISR 0xFE78 -#define REG_USB_HISRE 0xFE7C +#define REG_LX_CTRL1 0x0300 // 4 Bytes + +#define REG_BCNQ_TXBD_DESA 0x0308 // 8 Bytes +#define REG_MGQ_TXBD_DESA 0x0310 // 8 Bytes +#define REG_VOQ_TXBD_DESA 0x0318 // 8 Bytes +#define REG_VIQ_TXBD_DESA 0x0320 // 8 Bytes +#define REG_BEQ_TXBD_DESA 0x0328 // 8 Bytes +#define REG_BKQ_TXBD_DESA 0x0330 // 8 Bytes +#define REG_RXQ_RXBD_DESA 0x0338 // 8 Bytes +#define REG_HI0Q_TXBD_DESA 0x0340 // 8 Bytes +#define REG_HI1Q_TXBD_DESA 0x0348 // 8 Bytes +#define REG_HI2Q_TXBD_DESA 0x0350 // 8 Bytes +#define REG_HI3Q_TXBD_DESA 0x0358 // 8 Bytes +#define REG_HI4Q_TXBD_DESA 0x0360 // 8 Bytes +#define REG_HI5Q_TXBD_DESA 0x0368 // 8 Bytes +#define REG_HI6Q_TXBD_DESA 0x0370 // 8 Bytes +#define REG_HI7Q_TXBD_DESA 0x0378 // 8 Bytes + +#define REG_MGQ_TXBD_NUM 0x0380 // 2 Bytes +#define REG_RX_RXBD_NUM 0x0382 // 2 Bytes +#define REG_VOQ_TXBD_NUM 0x0384 // 2 Bytes +#define REG_VIQ_TXBD_NUM 0x0386 // 2 Bytes +#define REG_BEQ_TXBD_NUM 0x0388 // 2 Bytes +#define REG_BKQ_TXBD_NUM 0x038A // 2 Bytes +#define REG_HI0Q_TXBD_NUM 0x038C // 2 Bytes +#define REG_HI1Q_TXBD_NUM 0x038E // 2 Bytes +#define REG_HI2Q_TXBD_NUM 0x0390 // 2 Bytes +#define REG_HI3Q_TXBD_NUM 0x0392 // 2 Bytes +#define REG_HI4Q_TXBD_NUM 0x0394 // 2 Bytes +#define REG_HI5Q_TXBD_NUM 0x0396 // 2 Bytes +#define REG_HI6Q_TXBD_NUM 0x0398 // 2 Bytes +#define REG_HI7Q_TXBD_NUM 0x039A // 2 Bytes + +#define REG_BD_RWPTR_CLR 0x039C // 4 Bytes +#define REG_VOQ_TXBD_IDX 0x03A0 // 4 Bytes +#define REG_VIQ_TXBD_IDX 0x03A4 // 4 Bytes +#define REG_BEQ_TXBD_IDX 0x03A8 // 4 Bytes +#define REG_BKQ_TXBD_IDX 0x03AC // 4 Bytes +#define REG_MGQ_TXBD_IDX 0x03B0 // 4 Bytes +#define REG_RXQ_RXBD_IDX 0x03B4 // 4 Bytes +#define REG_HI0Q_TXBD_IDX 0x03B8 // 4 Bytes +#define REG_HI1Q_TXBD_IDX 0x03BC // 4 Bytes +#define REG_HI2Q_TXBD_IDX 0x03C0 // 4 Bytes +#define REG_HI3Q_TXBD_IDX 0x03C4 // 4 Bytes +#define REG_HI4Q_TXBD_IDX 0x03C8 // 4 Bytes +#define REG_HI5Q_TXBD_IDX 0x03CC // 4 Bytes +#define REG_HI6Q_TXBD_IDX 0x03D0 // 4 Bytes +#define REG_HI7Q_TXBD_IDX 0x03D4 // 4 Bytes + +//CPWM &RPWM +#define REG_LX_HRPWM_8711B 0x03D9 // 1 Bytes +#define REG_LX_HCPWM_8711B 0x03DA // 1 Bytes //from 0x14c + +#define REG_LX_CTRL2 0x03DB // 1 Bytes + +#define REG_LX_HRPWM2_8711B 0x03DC // 2 Bytes //REG_LX_HCPWM1_8711B +#define REG_LX_HCPWM2_8711B 0x03DE // 2 Bytes +#define REG_LX_H2C_MSG_V1 0x03E0 // 4 Bytes +#define REG_LX_C2H_MSG_V1 0x03E4 // 4 Bytes + + +#define REG_LX_DMA_ISR 0x03E8 // 4 Bytes +#define REG_LX_DMA_IMR 0x03EC // 4 Bytes +#define REG_LX_DMA_DBG 0x03F0 // 4 Bytes + +#define REG_BUS_MIX_CFG 0x03F8 // 4 Bytes# +#define REG_BUS_MIX_CFG1 0x03FC // 4 Bytes //----------------------------------------------------- // // 0x0400h ~ 0x047Fh Protocol Configuration // //----------------------------------------------------- - -/* 92C, 92D */ -#define REG_VOQ_INFO 0x0400 -#define REG_VIQ_INFO 0x0404 -#define REG_BEQ_INFO 0x0408 -#define REG_BKQ_INFO 0x040C - -/* 88E, 8723A, 8812A, 8821A, 92E, 8723B */ -#define REG_Q0_INFO 0x400 -#define REG_Q1_INFO 0x404 -#define REG_Q2_INFO 0x408 -#define REG_Q3_INFO 0x40C - -#define REG_MGQ_INFO 0x0410 -#define REG_HGQ_INFO 0x0414 -#define REG_BCNQ_INFO 0x0418 -#define REG_TXPKT_EMPTY 0x041A -#define REG_CPU_MGQ_INFORMATION 0x041C +#define REG_VOQ_INFORMATION 0x0400 +#define REG_VIQ_INFORMATION 0x0404 +#define REG_BEQ_INFORMATION 0x0408 +#define REG_BKQ_INFORMATION 0x040C +#define REG_MGQ_INFORMATION 0x0410 +#define REG_HGQ_INFORMATION 0x0414 +#define REG_BCNQ_INFORMATION 0x0418 +#define REG_TXPKT_EMPTY 0x041A +#define REG_CPU_MGQ_INFORMATION 0x041C #define REG_FWHW_TXQ_CTRL 0x0420 #define REG_HWSEQ_CTRL 0x0423 #define REG_BCNQ_BDNY 0x0424 @@ -263,54 +314,36 @@ #define REG_BCNQ1_BDNY 0x0457 #define REG_AGGLEN_LMT 0x0458 -#define REG_AMPDU_MIN_SPACE 0x045C -#define REG_WMAC_LBK_BF_HD 0x045D +#define REG_AMPDU_MIN_SPACE 0x045C +#define REG_WMAC_LBK_BF_HD 0x045D #define REG_FAST_EDCA_CTRL 0x0460 #define REG_RD_RESP_PKT_TH 0x0463 -/* 8723A, 8812A, 8821A, 92E, 8723B */ -#define REG_Q4_INFO 0x468 -#define REG_Q5_INFO 0x46C -#define REG_Q6_INFO 0x470 -#define REG_Q7_INFO 0x474 - #define REG_INIRTS_RATE_SEL 0x0480 -#define REG_INIDATA_RATE_SEL 0x0484 - -/* 8723B, 92E, 8812A, 8821A*/ +//#define REG_INIDATA_RATE_SEL 0x0484 #define REG_MACID_SLEEP_3 0x0484 #define REG_MACID_SLEEP_1 0x0488 #define REG_POWER_STAGE1 0x04B4 #define REG_POWER_STAGE2 0x04B8 -#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 -#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 +#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 #define REG_STBC_SETTING 0x04C4 #define REG_QUEUE_CTRL 0x04C6 #define REG_SINGLE_AMPDU_CTRL 0x04c7 -#define REG_PROT_MODE_CTRL 0x04C8 +#define REG_PROT_MODE_CTRL 0x04C8 #define REG_MAX_AGGR_NUM 0x04CA #define REG_RTS_MAX_AGGR_NUM 0x04CB #define REG_BAR_MODE_CTRL 0x04CC -#define REG_RA_TRY_RATE_AGG_LMT 0x04CF - -/* 8723A */ -#define REG_MACID_DROP 0x04D0 - -/* 88E */ -#define REG_EARLY_MODE_CONTROL 0x04D0 - -/* 8723B, 92E, 8812A, 8821A */ -#define REG_MACID_SLEEP_2 0x04D0 - -/* 8723A, 8723B, 92E, 8812A, 8821A */ -#define REG_MACID_SLEEP 0x04D4 - +#define REG_RA_TRY_RATE_AGG_LMT 0x04CF +//#define REG_EARLY_MODE_CONTROL 0x04D0 +#define REG_MACID_SLEEP_2 0x04D0 +#define REG_MACID_SLEEP 0x04D4 #define REG_NQOS_SEQ 0x04DC -#define REG_QOS_SEQ 0x04DE -#define REG_NEED_CPU_HANDLE 0x04E0 +#define REG_QOS_SEQ 0x04DE +#define REG_NEED_CPU_HANDLE 0x04E0 #define REG_PKT_LOSE_RPT 0x04E1 -#define REG_PTCL_ERR_STATUS 0x04E2 +#define REG_PTCL_ERR_STATUS 0x04E2 #define REG_TX_RPT_CTRL 0x04EC #define REG_TX_RPT_TIME 0x04F0 // 2 byte #define REG_DUMMY 0x04FC @@ -325,12 +358,12 @@ #define REG_EDCA_BE_PARAM 0x0508 #define REG_EDCA_BK_PARAM 0x050C #define REG_BCNTCFG 0x0510 -#define REG_PIFS 0x0512 +#define REG_PIFS 0x0512 #define REG_RDG_PIFS 0x0513 #define REG_SIFS_CTX 0x0514 #define REG_SIFS_TRX 0x0516 #define REG_TSFTR_SYN_OFFSET 0x0518 -#define REG_AGGR_BREAK_TIME 0x051A +#define REG_AGGR_BREAK_TIME 0x051A #define REG_SLOT 0x051B #define REG_TX_PTCL_CTRL 0x0520 #define REG_TXPAUSE 0x0522 @@ -361,9 +394,9 @@ #define REG_BCN_INTERVAL 0x0554 // The same as REG_MBSSID_BCN_SPACE #define REG_DRVERLYINT 0x0558 #define REG_BCNDMATIM 0x0559 -#define REG_ATIMWND 0x055A +#define REG_ATIMWND 0x055A #define REG_USTIME_TSF 0x055C -#define REG_BCN_MAX_ERR 0x055D +#define REG_BCN_MAX_ERR 0x055D #define REG_RXTSF_OFFSET_CCK 0x055E #define REG_RXTSF_OFFSET_OFDM 0x055F #define REG_TSFTR 0x0560 @@ -375,17 +408,17 @@ #define REG_TIMER1 0x0588 #define REG_ACMHWCTRL 0x05C0 #define REG_NOA_DESC_SEL 0x05CF -#define REG_NOA_DESC_DURATION 0x05E0 +#define REG_NOA_DESC_DURATION 0x05E0 #define REG_NOA_DESC_INTERVAL 0x05E4 -#define REG_NOA_DESC_START 0x05E8 -#define REG_NOA_DESC_COUNT 0x05EC +#define REG_NOA_DESC_START 0x05E8 +#define REG_NOA_DESC_COUNT 0x05EC #define REG_DMC 0x05F0 //Dual MAC Co-Existence Register #define REG_SCH_TX_CMD 0x05F8 -#define REG_FW_RESET_TSF_CNT_1 0x05FC -#define REG_FW_RESET_TSF_CNT_0 0x05FD -#define REG_FW_BCN_DIS_CNT 0x05FE +#define REG_FW_RESET_TSF_CNT_1 0x05FC +#define REG_FW_RESET_TSF_CNT_0 0x05FD +#define REG_FW_BCN_DIS_CNT 0x05FE //----------------------------------------------------- // @@ -397,7 +430,7 @@ #define REG_TCR 0x0604 #define REG_RCR 0x0608 #define REG_RX_PKT_LIMIT 0x060C -#define REG_RX_DLK_TIME 0x060D +#define REG_RX_DLK_TIME 0x060D #define REG_RX_DRVINFO_SZ 0x060F #define REG_MACID 0x0610 @@ -405,34 +438,35 @@ #define REG_MAR 0x0620 #define REG_MBIDCAMCFG 0x0628 -#define REG_PNO_STATUS 0x0631 -#define REG_USTIME_EDCA 0x0638 +#define REG_USTIME_EDCA 0x0638 #define REG_MAC_SPEC_SIFS 0x063A // 20100719 Joseph: Hardware register definition change. (HW datasheet v54) #define REG_RESP_SIFS_CCK 0x063C // [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK -#define REG_RESP_SIFS_OFDM 0x063E // [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK +#define REG_RESP_SIFS_OFDM 0x063E // [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK #define REG_ACKTO 0x0640 #define REG_CTS2TO 0x0641 -#define REG_EIFS 0x0642 +#define REG_EIFS 0x0642 + +#define REG_PORT_CTRL 0x076D //RXERR_RPT #define RXERR_TYPE_OFDM_PPDU 0 #define RXERR_TYPE_OFDM_FALSE_ALARM 1 #define RXERR_TYPE_OFDM_MPDU_OK 2 -#define RXERR_TYPE_OFDM_MPDU_FAIL 3 +#define RXERR_TYPE_OFDM_MPDU_FAIL 3 #define RXERR_TYPE_CCK_PPDU 4 -#define RXERR_TYPE_CCK_FALSE_ALARM 5 -#define RXERR_TYPE_CCK_MPDU_OK 6 +#define RXERR_TYPE_CCK_FALSE_ALARM 5 +#define RXERR_TYPE_CCK_MPDU_OK 6 #define RXERR_TYPE_CCK_MPDU_FAIL 7 #define RXERR_TYPE_HT_PPDU 8 -#define RXERR_TYPE_HT_FALSE_ALARM 9 +#define RXERR_TYPE_HT_FALSE_ALARM 9 #define RXERR_TYPE_HT_MPDU_TOTAL 10 #define RXERR_TYPE_HT_MPDU_OK 11 #define RXERR_TYPE_HT_MPDU_FAIL 12 #define RXERR_TYPE_RX_FULL_DROP 15 -#define RXERR_COUNTER_MASK 0xFFFFF +#define RXERR_COUNTER_MASK 0xFFFFF #define RXERR_RPT_RST BIT(27) #define _RXERR_RPT_SEL(type) ((type) << 28) @@ -459,7 +493,7 @@ // Security #define REG_CAMCMD 0x0670 #define REG_CAMWRITE 0x0674 -#define REG_CAMREAD 0x0678 +#define REG_CAMREAD 0x0678 #define REG_CAMDBG 0x067C #define REG_SECCFG 0x0680 @@ -467,27 +501,30 @@ #define REG_WOW_CTRL 0x0690 #define REG_PS_RX_INFO 0x0692 #define REG_UAPSD_TID 0x0693 -#define REG_WKFMCAM_CMD 0x0698 -#define REG_WKFMCAM_NUM REG_WKFMCAM_CMD -#define REG_WKFMCAM_RWD 0x069C +#define REG_WKFMCAM_CMD 0x0698 +#define REG_WKFMCAM_NUM REG_WKFMCAM_CMD +#define REG_WKFMCAM_RWD 0x069C #define REG_RXFLTMAP0 0x06A0 #define REG_RXFLTMAP1 0x06A2 #define REG_RXFLTMAP2 0x06A4 -#define REG_BCN_PSR_RPT 0x06A8 +#define REG_BCN_PSR_RPT 0x06A8 #define REG_BT_COEX_TABLE 0x06C0 // Hardware Port 2 #define REG_MACID1 0x0700 #define REG_BSSID1 0x0708 +/* port0 & port1 enable */ +#define REG_PORT_CTRL 0x76D + //----------------------------------------------------- // // 0xFE00h ~ 0xFE55h USB Configuration // //----------------------------------------------------- #define REG_USB_INFO 0xFE17 -#define REG_USB_SPECIAL_OPTION 0xFE55 -#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B #define REG_USB_AGG_TO 0xFE5C #define REG_USB_AGG_TH 0xFE5D @@ -508,19 +545,21 @@ #define REG_TEST_SIE_CHIRP_K 0xFE65 #define REG_TEST_SIE_PHY 0xFE66 // 0xFE66~0xFE6B #define REG_TEST_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 -#define REG_TEST_SIE_STRING 0xFE80 // 0xFE80~0xFEB9 +#define REG_TEST_SIE_STRING 0xFE80 // 0xFE80~0xFEB9 + // For normal chip #define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61 #define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63 -#define REG_NORMAL_SIE_OPTIONAL 0xFE64 +#define REG_NORMAL_SIE_OPTIONAL 0xFE64 #define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67 -#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B +#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B #define REG_NORMAL_SIE_OPTIONAL2 0xFE6C #define REG_NORMAL_SIE_GPS_EP 0xFE6D // 0xFE6D, for RTL8723 only. -#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 +#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 #define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF + //----------------------------------------------------- // // Redifine 8192C register definition for compatibility @@ -535,7 +574,7 @@ #define MSR (REG_CR + 2) // Media Status register //#define ISR REG_HISR -#define TSFR REG_TSFTR // Timing Sync Function Timer Register. +#define TSFR REG_TSFTR // Timing Sync Function Timer Register. #define TSFR1 REG_TSFTR1 // HW Port 1 TSF Register #define PBP REG_PBP @@ -544,6 +583,7 @@ #define IDR0 REG_MACID // MAC ID Register, Offset 0x0050-0x0053 #define IDR4 (REG_MACID + 4) // MAC ID Register, Offset 0x0054-0x0055 + // // 9. Security Control Registers (Offset: ) // @@ -551,14 +591,14 @@ #define WCAMI REG_CAMWRITE // Software write CAM input content #define RCAMO REG_CAMREAD // Software read/write CAM config #define CAMDBG REG_CAMDBG -#define SECR REG_SECCFG //Security Configuration Register +#define SECR REG_SECCFG //Security Configuration Register // Unused register #define UnusedRegister 0x1BF #define DCAM UnusedRegister #define PSR UnusedRegister #define BBAddr UnusedRegister -#define PhyDataR UnusedRegister +#define PhyDataR UnusedRegister // Min Spacing related settings. #define MAX_MSS_DENSITY_2T 0x13 @@ -615,13 +655,13 @@ // 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) //---------------------------------------------------------------------------- /* - Network Type - 00: No link - 01: Link in ad hoc network - 10: Link in infrastructure network - 11: AP mode - Default: 00b. - */ +Network Type +00: No link +01: Link in ad hoc network +10: Link in infrastructure network +11: AP mode +Default: 00b. +*/ #define MSR_NOLINK 0x00 #define MSR_ADHOC 0x01 #define MSR_INFRA 0x02 @@ -630,14 +670,14 @@ //---------------------------------------------------------------------------- // USB INTR CONTENT //---------------------------------------------------------------------------- -#define USB_C2H_CMDID_OFFSET 0 +#define USB_C2H_CMDID_OFFSET 0 #define USB_C2H_SEQ_OFFSET 1 -#define USB_C2H_EVENT_OFFSET 2 -#define USB_INTR_CPWM_OFFSET 16 +#define USB_C2H_EVENT_OFFSET 2 +#define USB_INTR_CPWM_OFFSET 16 #define USB_INTR_CONTENT_C2H_OFFSET 0 #define USB_INTR_CONTENT_CPWM1_OFFSET 16 #define USB_INTR_CONTENT_CPWM2_OFFSET 20 -#define USB_INTR_CONTENT_HISR_OFFSET 48 +#define USB_INTR_CONTENT_HISR_OFFSET 48 #define USB_INTR_CONTENT_HISRE_OFFSET 52 #define USB_INTR_CONTENT_LENGTH 56 @@ -667,7 +707,6 @@ #define RRSR_CCK_RATES (RRSR_11M|RRSR_5_5M|RRSR_2M|RRSR_1M) #define RRSR_OFDM_RATES (RRSR_54M|RRSR_48M|RRSR_36M|RRSR_24M|RRSR_18M|RRSR_12M|RRSR_9M|RRSR_6M) - // WOL bit information #define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 @@ -679,13 +718,13 @@ // Rate Definition //---------------------------------------------------------------------------- //CCK -#define RATR_1M 0x00000001 -#define RATR_2M 0x00000002 +#define RATR_1M 0x00000001 +#define RATR_2M 0x00000002 #define RATR_55M 0x00000004 #define RATR_11M 0x00000008 //OFDM -#define RATR_6M 0x00000010 -#define RATR_9M 0x00000020 +#define RATR_6M 0x00000010 +#define RATR_9M 0x00000020 #define RATR_12M 0x00000040 #define RATR_18M 0x00000080 #define RATR_24M 0x00000100 @@ -744,14 +783,15 @@ #define RATE_MCS14 BIT(26) #define RATE_MCS15 BIT(27) + // ALL CCK Rate #define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M #define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\ - RATR_36M|RATR_48M|RATR_54M + RATR_36M|RATR_48M|RATR_54M #define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\ - RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 + RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 #define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\ - RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 + RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 #define RATE_BITMAP_ALL 0xFFFFF @@ -763,7 +803,7 @@ // BW_OPMODE bits (Offset 0x603, 8bit) //---------------------------------------------------------------------------- #define BW_OPMODE_20MHZ BIT2 -#define BW_OPMODE_5G BIT1 +#define BW_OPMODE_5G BIT1 //---------------------------------------------------------------------------- // CAM Config Setting (offset 0x680, 1 byte) @@ -772,7 +812,7 @@ #define CAM_NOTVALID 0x0000 #define CAM_USEDK BIT5 -#define CAM_CONTENT_COUNT 8 +#define CAM_CONTENT_COUNT 8 #define CAM_NONE 0x0 #define CAM_WEP40 0x01 @@ -780,10 +820,10 @@ #define CAM_AES 0x04 #define CAM_WEP104 0x05 #define CAM_SMS4 0x6 - -#define TOTAL_CAM_ENTRY 32 + +#define TOTAL_CAM_ENTRY 32 #define HALF_CAM_ENTRY 16 - + #define CAM_CONFIG_USEDK _TRUE #define CAM_CONFIG_NO_USEDK _FALSE @@ -791,13 +831,17 @@ #define CAM_READ 0x00000000 #define CAM_POLLINIG BIT31 +#define SCR_UseDK 0x01 +#define SCR_TxSecEnable 0x02 +#define SCR_RxSecEnable 0x04 + // // 10. Power Save Control Registers // -#define WOW_PMEN BIT0 // Power management Enable. -#define WOW_WOMEN BIT1 // WoW function on or off. -#define WOW_MAGIC BIT2 // Magic packet -#define WOW_UWF BIT3 // Unicast Wakeup frame. +#define WOW_PMEN BIT0 // Power management Enable. +#define WOW_WOMEN BIT1 // WoW function on or off. +#define WOW_MAGIC BIT2 // Magic packet +#define WOW_UWF BIT3 // Unicast Wakeup frame. // // 12. Host Interrupt Status Registers @@ -833,7 +877,7 @@ #define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup #define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt #define IMR_TBDOK BIT7 // Transmit Beacon OK interrup -#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt +#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt #define IMR_TBDER BIT5 // For 92C,Transmit Beacon Error Interrupt #define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt #define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt @@ -843,14 +887,14 @@ // 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) #define IMR_TSF_BIT32_TOGGLE BIT15 -#define IMR_BcnInt_E BIT12 +#define IMR_BcnInt_E BIT12 #define IMR_TXERR BIT11 #define IMR_RXERR BIT10 #define IMR_C2HCMD BIT9 #define IMR_CPWM BIT8 //RSVD [2-7] #define IMR_OCPINT BIT1 -#define IMR_WLANOFF BIT0 +#define IMR_WLANOFF BIT0 //---------------------------------------------------------------------------- // 8723E series PCIE Host IMR/ISR bit @@ -858,12 +902,12 @@ // IMR DW0 Bit 0-31 #define PHIMR_TIMEOUT2 BIT31 #define PHIMR_TIMEOUT1 BIT30 -#define PHIMR_PSTIMEOUT BIT29 +#define PHIMR_PSTIMEOUT BIT29 #define PHIMR_GTINT4 BIT28 #define PHIMR_GTINT3 BIT27 #define PHIMR_TXBCNERR BIT26 #define PHIMR_TXBCNOK BIT25 -#define PHIMR_TSF_BIT32_TOGGLE BIT24 +#define PHIMR_TSF_BIT32_TOGGLE BIT24 #define PHIMR_BCNDMAINT3 BIT23 #define PHIMR_BCNDMAINT2 BIT22 #define PHIMR_BCNDMAINT1 BIT21 @@ -874,18 +918,18 @@ #define PHIMR_BCNDOK0 BIT16 #define PHIMR_HSISR_IND_ON BIT15 #define PHIMR_BCNDMAINT_E BIT14 -#define PHIMR_ATIMEND_E BIT13 -#define PHIMR_ATIM_CTW_END BIT12 -#define PHIMR_HISRE_IND BIT11 // RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) +#define PHIMR_ATIMEND_E BIT13 +#define PHIMR_ATIM_CTW_END BIT12 +#define PHIMR_HISRE_IND BIT11 // RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) #define PHIMR_C2HCMD BIT10 -#define PHIMR_CPWM2 BIT9 +#define PHIMR_CPWM2 BIT9 #define PHIMR_CPWM BIT8 #define PHIMR_HIGHDOK BIT7 // High Queue DMA OK Interrupt #define PHIMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt #define PHIMR_BKDOK BIT5 // AC_BK DMA OK Interrupt #define PHIMR_BEDOK BIT4 // AC_BE DMA OK Interrupt #define PHIMR_VIDOK BIT3 // AC_VI DMA OK Interrupt -#define PHIMR_VODOK BIT2 // AC_VO DMA Interrupt +#define PHIMR_VODOK BIT2 // AC_VO DMA Interrupt #define PHIMR_RDU BIT1 // Receive Descriptor Unavailable #define PHIMR_ROK BIT0 // Receive DMA OK Interrupt @@ -909,12 +953,12 @@ #define UHIMR_TIMEOUT2 BIT31 #define UHIMR_TIMEOUT1 BIT30 -#define UHIMR_PSTIMEOUT BIT29 +#define UHIMR_PSTIMEOUT BIT29 #define UHIMR_GTINT4 BIT28 #define UHIMR_GTINT3 BIT27 #define UHIMR_TXBCNERR BIT26 #define UHIMR_TXBCNOK BIT25 -#define UHIMR_TSF_BIT32_TOGGLE BIT24 +#define UHIMR_TSF_BIT32_TOGGLE BIT24 #define UHIMR_BCNDMAINT3 BIT23 #define UHIMR_BCNDMAINT2 BIT22 #define UHIMR_BCNDMAINT1 BIT21 @@ -923,20 +967,20 @@ #define UHIMR_BCNDOK2 BIT18 #define UHIMR_BCNDOK1 BIT17 #define UHIMR_BCNDOK0 BIT16 -#define UHIMR_HSISR_IND BIT15 +#define UHIMR_HSISR_IND BIT15 #define UHIMR_BCNDMAINT_E BIT14 //RSVD BIT13 #define UHIMR_CTW_END BIT12 //RSVD BIT11 #define UHIMR_C2HCMD BIT10 -#define UHIMR_CPWM2 BIT9 +#define UHIMR_CPWM2 BIT9 #define UHIMR_CPWM BIT8 #define UHIMR_HIGHDOK BIT7 // High Queue DMA OK Interrupt #define UHIMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt -#define UHIMR_BKDOK BIT5 // AC_BK DMA OK Interrupt -#define UHIMR_BEDOK BIT4 // AC_BE DMA OK Interrupt +#define UHIMR_BKDOK BIT5 // AC_BK DMA OK Interrupt +#define UHIMR_BEDOK BIT4 // AC_BE DMA OK Interrupt #define UHIMR_VIDOK BIT3 // AC_VI DMA OK Interrupt -#define UHIMR_VODOK BIT2 // AC_VO DMA Interrupt +#define UHIMR_VODOK BIT2 // AC_VO DMA Interrupt #define UHIMR_RDU BIT1 // Receive Descriptor Unavailable #define UHIMR_ROK BIT0 // Receive DMA OK Interrupt @@ -950,7 +994,7 @@ #define UHIMR_BCNDOK5 BIT17 #define UHIMR_BCNDOK4 BIT16 // bit14-15: RSVD -#define UHIMR_ATIMEND_E BIT13 +#define UHIMR_ATIMEND_E BIT13 #define UHIMR_ATIMEND BIT12 #define UHIMR_TXERR BIT11 #define UHIMR_RXERR BIT10 @@ -960,6 +1004,7 @@ #define UHIMR_OCPINT BIT1 // bit0: RSVD + #define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF // The value when the NIC is unplugged for PCI. #define HAL_NIC_UNPLUG_PCI_ISR 0xEAEAEAEA // The value when the NIC is unplugged for PCI in PCI interrupt (page 3). @@ -975,17 +1020,17 @@ #define IMR_TBDER_88E BIT26 // Transmit Beacon0 Error #define IMR_TBDOK_88E BIT25 // Transmit Beacon0 OK #define IMR_TSF_BIT32_TOGGLE_88E BIT24 // TSF Timer BIT32 toggle indication interrupt -#define IMR_BCNDMAINT0_88E BIT20 // Beacon DMA Interrupt 0 +#define IMR_BCNDMAINT0_88E BIT20 // Beacon DMA Interrupt 0 #define IMR_BCNDERR0_88E BIT16 // Beacon Queue DMA Error 0 #define IMR_HSISR_IND_ON_INT_88E BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) -#define IMR_BCNDMAINT_E_88E BIT14 // Beacon DMA Interrupt Extension for Win7 -#define IMR_ATIMEND_88E BIT12 // CTWidnow End or ATIM Window End +#define IMR_BCNDMAINT_E_88E BIT14 // Beacon DMA Interrupt Extension for Win7 +#define IMR_ATIMEND_88E BIT12 // CTWidnow End or ATIM Window End #define IMR_HISR1_IND_INT_88E BIT11 // HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) #define IMR_C2HCMD_88E BIT10 // CPU to Host Command INT Status, Write 1 clear #define IMR_CPWM2_88E BIT9 // CPU power Mode exchange INT Status, Write 1 clear #define IMR_CPWM_88E BIT8 // CPU power Mode exchange INT Status, Write 1 clear -#define IMR_HIGHDOK_88E BIT7 // High Queue DMA OK -#define IMR_MGNTDOK_88E BIT6 // Management Queue DMA OK +#define IMR_HIGHDOK_88E BIT7 // High Queue DMA OK +#define IMR_MGNTDOK_88E BIT6 // Management Queue DMA OK #define IMR_BKDOK_88E BIT5 // AC_BK DMA OK #define IMR_BEDOK_88E BIT4 // AC_BE DMA OK #define IMR_VIDOK_88E BIT3 // AC_VI DMA OK @@ -994,20 +1039,20 @@ #define IMR_ROK_88E BIT0 // Receive DMA OK // IMR DW1(0x00B4-00B7) Bit 0-31 -#define IMR_BCNDMAINT7_88E BIT27 // Beacon DMA Interrupt 7 -#define IMR_BCNDMAINT6_88E BIT26 // Beacon DMA Interrupt 6 -#define IMR_BCNDMAINT5_88E BIT25 // Beacon DMA Interrupt 5 -#define IMR_BCNDMAINT4_88E BIT24 // Beacon DMA Interrupt 4 -#define IMR_BCNDMAINT3_88E BIT23 // Beacon DMA Interrupt 3 -#define IMR_BCNDMAINT2_88E BIT22 // Beacon DMA Interrupt 2 -#define IMR_BCNDMAINT1_88E BIT21 // Beacon DMA Interrupt 1 -#define IMR_BCNDOK7_88E BIT20 // Beacon Queue DMA OK Interrup 7 -#define IMR_BCNDOK6_88E BIT19 // Beacon Queue DMA OK Interrup 6 -#define IMR_BCNDOK5_88E BIT18 // Beacon Queue DMA OK Interrup 5 -#define IMR_BCNDOK4_88E BIT17 // Beacon Queue DMA OK Interrup 4 -#define IMR_BCNDOK3_88E BIT16 // Beacon Queue DMA OK Interrup 3 -#define IMR_BCNDOK2_88E BIT15 // Beacon Queue DMA OK Interrup 2 -#define IMR_BCNDOK1_88E BIT14 // Beacon Queue DMA OK Interrup 1 +#define IMR_BCNDMAINT7_88E BIT27 // Beacon DMA Interrupt 7 +#define IMR_BCNDMAINT6_88E BIT26 // Beacon DMA Interrupt 6 +#define IMR_BCNDMAINT5_88E BIT25 // Beacon DMA Interrupt 5 +#define IMR_BCNDMAINT4_88E BIT24 // Beacon DMA Interrupt 4 +#define IMR_BCNDMAINT3_88E BIT23 // Beacon DMA Interrupt 3 +#define IMR_BCNDMAINT2_88E BIT22 // Beacon DMA Interrupt 2 +#define IMR_BCNDMAINT1_88E BIT21 // Beacon DMA Interrupt 1 +#define IMR_BCNDOK7_88E BIT20 // Beacon Queue DMA OK Interrup 7 +#define IMR_BCNDOK6_88E BIT19 // Beacon Queue DMA OK Interrup 6 +#define IMR_BCNDOK5_88E BIT18 // Beacon Queue DMA OK Interrup 5 +#define IMR_BCNDOK4_88E BIT17 // Beacon Queue DMA OK Interrup 4 +#define IMR_BCNDOK3_88E BIT16 // Beacon Queue DMA OK Interrup 3 +#define IMR_BCNDOK2_88E BIT15 // Beacon Queue DMA OK Interrup 2 +#define IMR_BCNDOK1_88E BIT14 // Beacon Queue DMA OK Interrup 1 #define IMR_ATIMEND_E_88E BIT13 // ATIM Window End Extension for Win7 #define IMR_TXERR_88E BIT11 // Tx Error Flag Interrupt Status, write 1 clear. #define IMR_RXERR_88E BIT10 // Rx Error Flag INT Status, Write 1 clear @@ -1015,36 +1060,36 @@ #define IMR_RXFOVW_88E BIT8 // Receive FIFO Overflow /*=================================================================== - ===================================================================== - Here the register defines are for 92C. When the define is as same with 92C, - we will use the 92C's define for the consistency - So the following defines for 92C is not entire!!!!!! - ===================================================================== - =====================================================================*/ +===================================================================== +Here the register defines are for 92C. When the define is as same with 92C, +we will use the 92C's define for the consistency +So the following defines for 92C is not entire!!!!!! +===================================================================== +=====================================================================*/ /* - Based on Datasheet V33---090401 - Register Summary - Current IOREG MAP - 0x0000h ~ 0x00FFh System Configuration (256 Bytes) - 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) - 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) - 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) - 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) - 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) - 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) - 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) - 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) - */ -//---------------------------------------------------------------------------- -// 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) -//---------------------------------------------------------------------------- +Based on Datasheet V33---090401 +Register Summary +Current IOREG MAP +0x0000h ~ 0x00FFh System Configuration (256 Bytes) +0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) +0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) +0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) +0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) +0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) +0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) +0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) +0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) +*/ + //---------------------------------------------------------------------------- + // 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) + //---------------------------------------------------------------------------- // Note: // The the bits of stoping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong, // the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3. // 8723 and 88E may be not correct either in the eralier version. Confirmed with DD Tim. // By Bruce, 2011-09-22. #define StopBecon BIT6 -#define StopHigh BIT5 +#define StopHigh BIT5 #define StopMgt BIT4 #define StopBK BIT3 #define StopBE BIT2 @@ -1059,34 +1104,36 @@ #define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet. #define RCR_APP_PHYST_RXFF BIT28 // PHY Status is appended before RX packet in RXFF #define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. -#define RCR_VHT_DACK BIT26 /* This bit to control response type for vht single mpdu data packet. 1. ACK as response 0. BA as response */ -#define RCR_TCPOFLD_EN BIT25 /* Enable TCP checksum offload */ +#define RCR_NONQOS_VHT BIT26 // Reserved +#define RCR_RSVD_BIT25 BIT25 // Reserved #define RCR_ENMBID BIT24 // Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. #define RCR_LSIGEN BIT23 // Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. #define RCR_MFBEN BIT22 // Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. -#define RCR_DISCHKPPDLLEN BIT21 /* Do not check PPDU while the PPDU length is smaller than 14 byte. */ -#define RCR_PKTCTL_DLEN BIT20 /* While rx path dead lock occurs, reset rx path */ -#define RCR_DISGCLK BIT19 /* Disable macrx clock gating control (no used) */ +#define RCR_RSVD_BIT21 BIT21 // Reserved +#define RCR_RSVD_BIT20 BIT20 // Reserved +#define RCR_RSVD_BIT19 BIT19 // Reserved #define RCR_TIM_PARSER_EN BIT18 // RX Beacon TIM Parser. -#define RCR_BC_MD_EN BIT17 /* Broadcast data packet more data bit check interrupt enable.*/ -#define RCR_UC_MD_EN BIT16 /* Unicast data packet more data bit check interrupt enable. */ -#define RCR_RXSK_PERPKT BIT15 /* Executing key search per MPDU */ +#define RCR_BM_DATA_EN BIT17 // Broadcast data packet interrupt enable. +#define RCR_UC_DATA_EN BIT16 // Unicast data packet interrupt enable. +#define RCR_RSVD_BIT15 BIT15 // Reserved #define RCR_HTC_LOC_CTRL BIT14 // MFC<--HTC=1 MFC-->HTC=0 #define RCR_AMF BIT13 // Accept management type frame #define RCR_ACF BIT12 // Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. #define RCR_ADF BIT11 // Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). -#define RCR_DISDECMYPKT BIT10 /* This bit determines whether hw need to do decryption.1: If A1 match, do decryption.0: Do decryption. */ -#define RCR_AICV BIT9 // Accept ICV error packet +#define RCR_RSVD_BIT10 BIT10 // Reserved +#define RCR_AICV BIT9 // Accept ICV error packet #define RCR_ACRC32 BIT8 // Accept CRC32 error packet #define RCR_CBSSID_BCN BIT7 // Accept BSSID match packet (Rx beacon, probe rsp) -#define RCR_CBSSID_DATA BIT6 // Accept BSSID match packet (Data) -#define RCR_APWRMGT BIT5 // Accept power management packet +#define RCR_CBSSID_DATA BIT6 // Accept BSSID match packet (Data) +#define RCR_CBSSID RCR_CBSSID_DATA // Accept BSSID match packet +#define RCR_APWRMGT BIT5 // Accept power management packet #define RCR_ADD3 BIT4 // Accept address 3 match packet #define RCR_AB BIT3 // Accept broadcast packet #define RCR_AM BIT2 // Accept multicast packet #define RCR_APM BIT1 // Accept physical match packet #define RCR_AAP BIT0 // Accept all unicast packet + //----------------------------------------------------- // // 0x0000h ~ 0x00FFh System Configuration @@ -1100,27 +1147,28 @@ #define ISO_PA2PCIE BIT(3) #define ISO_PD2CORE BIT(4) #define ISO_IP2MAC BIT(5) -#define ISO_DIOP BIT(6) -#define ISO_DIOE BIT(7) +#define ISO_DIOP BIT(6) +#define ISO_DIOE BIT(7) #define ISO_EB2CORE BIT(8) -#define ISO_DIOR BIT(9) +#define ISO_DIOR BIT(9) #define PWC_EV12V BIT(15) + //2 SYS_FUNC_EN #define FEN_BBRSTB BIT(0) -#define FEN_BB_GLB_RSTn BIT(1) +#define FEN_BB_GLB_RSTn BIT(1) #define FEN_USBA BIT(2) #define FEN_UPLL BIT(3) #define FEN_USBD BIT(4) #define FEN_DIO_PCIE BIT(5) #define FEN_PCIEA BIT(6) -#define FEN_PPLL BIT(7) +#define FEN_PPLL BIT(7) #define FEN_PCIED BIT(8) #define FEN_DIOE BIT(9) #define FEN_CPUEN BIT(10) #define FEN_DCORE BIT(11) #define FEN_ELDR BIT(12) -#define FEN_EN_25_1 BIT(13) +//#define FEN_DIO_RF BIT(13) #define FEN_HWPDN BIT(14) #define FEN_MREGEN BIT(15) @@ -1158,16 +1206,19 @@ #define MACSLP BIT(4) #define LOADER_CLK_EN BIT(5) + //2 9346CR /REG_SYS_EEPROM_CTRL #define BOOT_FROM_EEPROM BIT(4) #define EEPROMSEL BIT(4) #define EEPROM_EN BIT(5) + //2 RF_CTRL #define RF_EN BIT(0) #define RF_RSTB BIT(1) #define RF_SDMRSTB BIT(2) + //2 LDOV12D_CTRL #define LDV12_EN BIT(0) #define LDV12_SDBY BIT(1) @@ -1175,17 +1226,20 @@ #define LPLDO_LSM_DIS BIT(3) #define _LDV12_VADJ(x) (((x) & 0xF) << 4) + + //2 EFUSE_TEST (For RTL8723 partially) #define EF_TRPT BIT(7) #define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 #define LDOE25_EN BIT(31) -#define EFUSE_SEL(x) (((x) & 0x3) << 8) +#define EFUSE_SEL(x) (((x) & 0x3) << 8) #define EFUSE_SEL_MASK 0x300 #define EFUSE_WIFI_SEL_0 0x0 #define EFUSE_BT_SEL_0 0x1 #define EFUSE_BT_SEL_1 0x2 #define EFUSE_BT_SEL_2 0x3 + //2 8051FWDL //2 MCUFWDL #define MCUFWDL_EN BIT(0) @@ -1196,10 +1250,10 @@ #define RFINI_RDY BIT(5) #define WINTINI_RDY BIT(6) #define RAM_DL_SEL BIT(7) -#define CPU_DL_READY BIT(15) /* add flag by gw for fw download ready 20130826 */ #define ROM_DLEN BIT(19) #define CPRST BIT(23) + //2 REG_SYS_CFG #define XCLK_VLD BIT(0) #define ACLK_VLD BIT(1) @@ -1208,10 +1262,10 @@ #define PCIRSTB BIT(4) #define V15_VLD BIT(5) #define SW_OFFLOAD_EN BIT(7) -#define SIC_IDLE BIT(8) +#define SIC_IDLE BIT(8) #define BD_MAC2 BIT(9) #define BD_MAC1 BIT(10) -#define IC_MACPHY_MODE BIT(11) +#define IC_MACPHY_MODE BIT(11) #define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) #define BT_FUNC BIT(16) #define VENDOR_ID BIT(19) @@ -1227,6 +1281,7 @@ #define RTL_ID BIT(23) // TestChip ID, 1:Test(RLE); 0:MP(RL) #define SPS_SEL BIT(24) // 1:LDO regulator mode; 0:Switching regulator mode + #define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 #define CHIP_VER_RTL_SHIFT 12 #define EXT_VENDOR_ID_SHIFT 18 @@ -1251,7 +1306,8 @@ #define UPHY_SUSB BIT(21) #define PCI_SUSEN BIT(22) #define USB_SUSEN BIT(23) -#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) +#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) + //----------------------------------------------------- // @@ -1295,14 +1351,15 @@ #define PBP_512 0x3 #define PBP_1024 0x4 + //2 TX/RXDMA -#define RXDMA_ARBBW_EN BIT(0) +#define RXDMA_ARBBW_EN BIT(0) #define RXSHFT_EN BIT(1) #define RXDMA_AGG_EN BIT(2) -#define QS_VO_QUEUE BIT(8) +#define QS_VO_QUEUE BIT(8) #define QS_VI_QUEUE BIT(9) -#define QS_BE_QUEUE BIT(10) -#define QS_BK_QUEUE BIT(11) +#define QS_BE_QUEUE BIT(10) +#define QS_BK_QUEUE BIT(11) #define QS_MANAGER_QUEUE BIT(12) #define QS_HIGH_QUEUE BIT(13) @@ -1327,8 +1384,10 @@ #define QUEUE_NORMAL 2 #define QUEUE_HIGH 3 + //2 TRXFF_BNDY + //2 LLT_INIT #define _LLT_NO_ACTIVE 0x0 #define _LLT_WRITE_ACCESS 0x1 @@ -1336,9 +1395,10 @@ #define _LLT_INIT_DATA(x) ((x) & 0xFF) #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) -#define _LLT_OP(x) (((x) & 0x3) << 30) +#define _LLT_OP(x) (((u32)(x) & 0x3) << 30) #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) + //----------------------------------------------------- // // 0x0200h ~ 0x027Fh TXDMA Configuration @@ -1347,18 +1407,21 @@ //2 RQPN #define _HPQ(x) ((x) & 0xFF) #define _LPQ(x) (((x) & 0xFF) << 8) -#define _PUBQ(x) (((x) & 0xFF) << 16) +#define _PUBQ(x) (((x) & 0xFF) << 16) #define _NPQ(x) ((x) & 0xFF) // NOTE: in RQPN_NPQ register #define _EPQ(x) (((x) & 0xFF) << 16) // NOTE: in RQPN_EPQ register + #define HPQ_PUBLIC_DIS BIT(24) #define LPQ_PUBLIC_DIS BIT(25) #define LD_RQPN BIT(31) + //2 TDECTL #define BLK_DESC_NUM_SHIFT 4 #define BLK_DESC_NUM_MASK 0xF + //2 TXDMA_OFFSET_CHK #define DROP_DATA_EN BIT(9) @@ -1374,6 +1437,7 @@ #define BIT_MASK_Tx_OQT_free_space 0xff #define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space) + //----------------------------------------------------- // // 0x0280h ~ 0x028Bh RX DMA Configuration @@ -1401,9 +1465,13 @@ // 0x0400h ~ 0x047Fh Protocol Configuration // //----------------------------------------------------- +//2 CPU_MGT_INFORMATION +#define CPUMGT_POLL BIT(5) + //2 FWHW_TXQ_CTRL #define EN_AMPDU_RTY_NEW BIT(7) + //2 SPEC SIFS #define _SPEC_SIFS_CCK(x) ((x) & 0xFF) #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) @@ -1422,18 +1490,20 @@ #define AC_PARAM_TXOP_LIMIT_OFFSET 16 #define AC_PARAM_ECW_MAX_OFFSET 12 #define AC_PARAM_ECW_MIN_OFFSET 8 -#define AC_PARAM_AIFS_OFFSET 0 +#define AC_PARAM_AIFS_OFFSET 0 + #define _LRL(x) ((x) & 0x3F) #define _SRL(x) (((x) & 0x3F) << 8) + //2 BCN_CTRL #define EN_TXBCN_RPT BIT(2) -#define EN_BCN_FUNCTION BIT(3) +#define EN_BCN_FUNCTION BIT(3) #define STOP_BCNQ BIT(6) #define DIS_RX_BSSID_FIT BIT(6) -#define DIS_ATIM BIT(0) +#define DIS_ATIM BIT(0) #define DIS_BCNQ_SUB BIT(1) #define DIS_TSF_UDT BIT(4) @@ -1441,14 +1511,15 @@ #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) #define DIS_TSF_UDT0_TEST_CHIP BIT(5) + //2 ACMHWCTRL #define AcmHw_HwEn BIT(0) -#define AcmHw_BeqEn BIT(1) +#define AcmHw_BeqEn BIT(1) #define AcmHw_ViqEn BIT(2) -#define AcmHw_VoqEn BIT(3) -#define AcmHw_BeqStatus BIT(4) +#define AcmHw_VoqEn BIT(3) +#define AcmHw_BeqStatus BIT(4) #define AcmHw_ViqStatus BIT(5) -#define AcmHw_VoqStatus BIT(6) +#define AcmHw_VoqStatus BIT(6) //2 //REG_DUAL_TSF_RST (0x553) #define DUAL_TSF_RST_P2P BIT(4) @@ -1468,26 +1539,27 @@ //2 TCR #define TSFRST BIT(0) -#define DIS_GCLK BIT(1) +#define DIS_GCLK BIT(1) #define PAD_SEL BIT(2) #define PWR_ST BIT(6) #define PWRBIT_OW_EN BIT(7) -#define ACRC BIT(8) +#define ACRC BIT(8) #define CFENDFORM BIT(9) #define ICV BIT(10) + //2 RCR #define AAP BIT(0) #define APM BIT(1) #define AM BIT(2) #define AB BIT(3) -#define ADD3 BIT(4) -#define APWRMGT BIT(5) +#define ADD3 BIT(4) +#define APWRMGT BIT(5) #define CBSSID BIT(6) #define CBSSID_DATA BIT(6) #define CBSSID_BCN BIT(7) #define ACRC32 BIT(8) -#define AICV BIT(9) +#define AICV BIT(9) #define ADF BIT(11) #define ACF BIT(12) #define AMF BIT(13) @@ -1504,6 +1576,7 @@ #define APP_MIC BIT(30) #define APP_FCS BIT(31) + //2 SECCFG #define SCR_TxUseDK BIT(0) //Force Tx Use Default Key #define SCR_RxUseDK BIT(1) //Force Rx Use Default Key @@ -1513,150 +1586,418 @@ #define SCR_NoSKMC BIT(5) //No Key Search Multicast #define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key #define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key -#define SCR_CHK_KEYID BIT(8) -#define SCR_CHK_BMC BIT(9) /* add option to support a2+keyid+bcm */ + //----------------------------------------------------- // -// SDIO Bus Specification +// 0x0300h ~ 0x03FFh PCIe/LBus // //----------------------------------------------------- -// I/O bus domain address mapping -#define SDIO_LOCAL_BASE 0x10250000 -#define WLAN_IOREG_BASE 0x10260000 -#define FIRMWARE_FIFO_BASE 0x10270000 -#define TX_HIQ_BASE 0x10310000 -#define TX_MIQ_BASE 0x10320000 -#define TX_LOQ_BASE 0x10330000 -#define TX_EPQ_BASE 0x10350000 -#define RX_RX0FF_BASE 0x10340000 -//SDIO host local register space mapping. -#define SDIO_LOCAL_MSK 0x0FFF -#define WLAN_IOREG_MSK 0x7FFF -#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0] -#define WLAN_RX0FF_MSK 0x0003 +//4 REG_LX_CTRL1(0x300) +#define BIT_WT_LIT_EDN BIT(25) +#define BIT_RD_LITT_EDN BIT(24) -#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID -#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13] -#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13] -#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13] -#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13] -#define WLAN_TX_EXQ_DEVICE_ID 3 // 0b[16], 011b[15:13] -#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13] -#define WLAN_IOREG_DEVICE_ID 8 // 1b[16] +#define BIT_SHIFT_MAX_RXDMA 20 +#define BIT_MASK_MAX_RXDMA 0x7 +#define BIT_MAX_RXDMA(x) (((x) & BIT_MASK_MAX_RXDMA)<HardwareType >=HARDWARE_TYPE_RTL8192EE) +// +// RTL8192C Series +// +#define IS_HARDWARE_TYPE_8192CE(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CE) +#define IS_HARDWARE_TYPE_8192CU(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CU) +#define IS_HARDWARE_TYPE_8192C(_Adapter) \ +(IS_HARDWARE_TYPE_8192CE(_Adapter) || IS_HARDWARE_TYPE_8192CU(_Adapter)) + +// +// RTL8192D Series +// +#define IS_HARDWARE_TYPE_8192DE(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DE) +#define IS_HARDWARE_TYPE_8192DU(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DU) +#define IS_HARDWARE_TYPE_8192D(_Adapter) \ +(IS_HARDWARE_TYPE_8192DE(_Adapter) || IS_HARDWARE_TYPE_8192DU(_Adapter)) + +// +// RTL8723A Series +// +#define IS_HARDWARE_TYPE_8723AE(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AE) +#define IS_HARDWARE_TYPE_8723AU(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AU) +#define IS_HARDWARE_TYPE_8723AS(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AS) +#define IS_HARDWARE_TYPE_8723A(_Adapter) \ +(IS_HARDWARE_TYPE_8723AE(_Adapter) || IS_HARDWARE_TYPE_8723AU(_Adapter) || IS_HARDWARE_TYPE_8723AS(_Adapter)) +// +// RTL8188E Series +// +#define IS_HARDWARE_TYPE_8188EE(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EE) +#define IS_HARDWARE_TYPE_8188EU(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EU) +#define IS_HARDWARE_TYPE_8188ES(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188ES) +#define IS_HARDWARE_TYPE_8188E(_Adapter) \ +(IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter)) +// +//RTL8188F Series +// +#define IS_HARDWARE_TYPE_8188FE(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188FE) +#define IS_HARDWARE_TYPE_8188FU(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EU) +#define IS_HARDWARE_TYPE_8188FS(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188FS) +#define IS_HARDWARE_TYPE_8188F(_Adapter) \ +(IS_HARDWARE_TYPE_8188FE(_Adapter) || IS_HARDWARE_TYPE_8188FU(_Adapter) || IS_HARDWARE_TYPE_8188FS(_Adapter)) +// +// RTL8812 Series +// +#define IS_HARDWARE_TYPE_8812E(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8812E) +#define IS_HARDWARE_TYPE_8812AU(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8812AU) +#define IS_HARDWARE_TYPE_8812(_Adapter) \ +(IS_HARDWARE_TYPE_8812E(_Adapter) || IS_HARDWARE_TYPE_8812AU(_Adapter)) + +// RTL8821 Series +#define IS_HARDWARE_TYPE_8821E(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8821E) +#define IS_HARDWARE_TYPE_8821U(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8821U ||\ + ((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8811AU) +#define IS_HARDWARE_TYPE_8821S(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8821S) +#define IS_HARDWARE_TYPE_8821(_Adapter) \ +(IS_HARDWARE_TYPE_8821E(_Adapter) || IS_HARDWARE_TYPE_8821U(_Adapter)|| IS_HARDWARE_TYPE_8821S(_Adapter)) + +#define IS_HARDWARE_TYPE_JAGUAR(_Adapter) \ +(IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter)) + +//RTL8192E Series +#define IS_HARDWARE_TYPE_8192EE(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192EE) +#define IS_HARDWARE_TYPE_8192EU(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192EU) +#define IS_HARDWARE_TYPE_8192ES(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192ES) + +#define IS_HARDWARE_TYPE_8192E(_Adapter) \ +(IS_HARDWARE_TYPE_8192EE(_Adapter) || IS_HARDWARE_TYPE_8192EU(_Adapter) ||IS_HARDWARE_TYPE_8192ES(_Adapter)) + +#define IS_HARDWARE_TYPE_8723BE(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723BE) +#define IS_HARDWARE_TYPE_8723BU(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723BU) +#define IS_HARDWARE_TYPE_8723BS(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723BS) + + +#define IS_HARDWARE_TYPE_8723B(_Adapter) \ + (IS_HARDWARE_TYPE_8723BE(_Adapter) || IS_HARDWARE_TYPE_8723BU(_Adapter) ||IS_HARDWARE_TYPE_8723BS(_Adapter)) + +#define IS_HARDWARE_TYPE_8195A(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8195A) + +#define IS_HARDWARE_TYPE_8711B(_Adapter) (((_adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8711B) + +typedef struct eeprom_priv EEPROM_EFUSE_PRIV, *PEEPROM_EFUSE_PRIV; +#define GET_EEPROM_EFUSE_PRIV(adapter) (&adapter->eeprompriv) +#define is_boot_from_eeprom(adapter) (adapter->eeprompriv.EepromOrEfuse) + +//TODO + +#ifdef CONFIG_WOWLAN +typedef enum _wowlan_subcode{ + WOWLAN_PATTERN_MATCH = 1, + WOWLAN_MAGIC_PACKET = 2, + WOWLAN_UNICAST = 3, + WOWLAN_SET_PATTERN = 4, + WOWLAN_DUMP_REG = 5, + WOWLAN_ENABLE = 6, + WOWLAN_DISABLE = 7, + WOWLAN_STATUS = 8, + WOWLAN_DEBUG_RELOAD_FW = 9, + WOWLAN_DEBUG_1 =10, + WOWLAN_DEBUG_2 =11 +}wowlan_subcode; + +struct wowlan_ioctl_param{ + unsigned int subcode; + unsigned int subcode_value; + unsigned int wakeup_reason; + unsigned int len; + unsigned char pattern[0]; +}; + +#define Rx_Pairwisekey 0x01 +#define Rx_GTK 0x02 +#define Rx_DisAssoc 0x04 +#define Rx_DeAuth 0x08 +#define FWDecisionDisconnect 0x10 +#define Rx_MagicPkt 0x21 +#define Rx_UnicastPkt 0x22 +#define Rx_PatternPkt 0x23 +#endif // CONFIG_WOWLAN + +void rtw_hal_def_value_init(_adapter *padapter); + +void rtw_hal_free_data(_adapter *padapter); + +void rtw_hal_dm_init(_adapter *padapter); +void rtw_hal_dm_deinit(_adapter *padapter); +#if 0 +void rtw_hal_sw_led_init(_adapter *padapter); +void rtw_hal_sw_led_deinit(_adapter *padapter); +#endif +u32 rtw_hal_power_on(_adapter *padapter); +uint rtw_hal_init(_adapter *padapter); +uint rtw_hal_deinit(_adapter *padapter); +void rtw_hal_stop(_adapter *padapter); +void rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val); +void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val); + +void rtw_hal_chip_configure(_adapter *padapter); +void rtw_hal_read_chip_info(_adapter *padapter); +void rtw_hal_read_chip_version(_adapter *padapter); + +u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); +u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); + +void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet); +void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet); + +void rtw_hal_enable_interrupt(_adapter *padapter); +void rtw_hal_disable_interrupt(_adapter *padapter); +void rtw_hal_clear_interrupt(_adapter *padapter); +#ifdef CONFIG_WOWLAN +void rtw_hal_disable_interrupt_but_cpwm2(_adapter *padapter); +#endif + +u32 rtw_hal_inirp_init(_adapter *padapter); +u32 rtw_hal_inirp_deinit(_adapter *padapter); + +void rtw_hal_irp_reset(_adapter *padapter); +#if 0 +u8 rtw_hal_intf_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id, u8* val); +#endif +s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe); +s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe); + +s32 rtw_hal_init_xmit_priv(_adapter *padapter); +void rtw_hal_free_xmit_priv(_adapter *padapter); + +#if 1 +s32 rtw_hal_init_recv_priv(_adapter *padapter); +void rtw_hal_free_recv_priv(_adapter *padapter); +#endif + +void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level); +void rtw_hal_add_ra_tid(_adapter *padapter, u32 bitmap, u8 *arg, u8 rssi_level); +void rtw_hal_clone_data(_adapter *dst_padapter, _adapter *src_padapter); +#ifdef CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD +void rtw_hal_start_thread(_adapter *padapter); +void rtw_hal_stop_thread(_adapter *padapter); +#endif +void rtw_hal_bcn_related_reg_setting(_adapter *padapter); + +u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask); +void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); +u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask); +void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); + +s32 rtw_hal_interrupt_handler(_adapter *padapter); + +void rtw_hal_set_bwmode(_adapter *padapter, CHANNEL_WIDTH Bandwidth, u8 Offset); +void rtw_hal_set_chan(_adapter *padapter, u8 channel); +void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80); +void rtw_hal_dm_watchdog(_adapter *padapter); +#if 1 +void rtw_hal_update_txdesc(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pbuf); +#endif +s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); + +void rtw_hal_fill_fake_txdesc(_adapter* padapter, u8* pDesc, u32 BufferLen, + u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); + +u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *padapter, bool wowlan); + + +void rtw_hal_set_wowlan_fw(_adapter *padapter, u8 sleep); + + +c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *padapter); + +s32 rtw_hal_c2h_handler(_adapter *padapter, u8 *c2h_evt); + + +#ifdef CONFIG_ANTENNA_DIVERSITY +u8 rtw_hal_antdiv_before_linked(_adapter *padapter); +void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src); +#endif + +#ifdef CONFIG_HOSTAPD_MLME +s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt); +#endif + +#ifdef DBG_CONFIG_ERROR_DETECT +void rtw_hal_sreset_init(_adapter *padapter); +void rtw_hal_sreset_reset(_adapter *padapter); +void rtw_hal_sreset_reset_value(_adapter *padapter); +void rtw_hal_sreset_xmit_status_check(_adapter *padapter); +void rtw_hal_sreset_linked_status_check (_adapter *padapter); +u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter); +#endif + +#ifdef CONFIG_IOL +int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt) +#endif + +#if 0//def CONFIG_XMIT_THREAD_MODE +s32 rtw_hal_xmit_thread_handler(_adapter *padapter); +#endif + +s32 rtw_hal_recv_tasklet(_adapter *padapter); +#if (RTW_NOTCH_FILTER != 0) +void rtw_hal_notch_filter(_adapter * adapter, bool enable); +#endif +#if 0 +void rtw_hal_reset_security_engine(_adapter * adapter); +#endif + +void decide_chip_type_by_device_id(_adapter *padapter); + + +#ifdef CONFIG_RTL8723A +void rtl8723as_set_hal_ops(PADAPTER padapter); +#define hal_set_hal_ops(__adapter) rtl8723as_set_hal_ops(__adapter) +#endif + +#ifdef CONFIG_RTL8188E +u32 rtl8188e_set_hal_ops(PADAPTER padapter); +#define hal_set_hal_ops(__adapter) rtl8188e_set_hal_ops(__adapter) +#endif + +#ifdef CONFIG_RTL8188F +u32 rtl8188fs_set_hal_ops(PADAPTER padapter); +#define hal_set_hal_ops(__adapter) rtl8188fs_set_hal_ops(__adapter) +#endif + +#ifdef CONFIG_RTL8195A +u32 rtl8195ab_set_hal_ops(_adapter * padapter); +#define hal_set_hal_ops rtl8195ab_set_hal_ops +#define hal_interuupt_recognized InterruptRecognized8195a +#elif defined(CONFIG_RTL8711B) +u32 rtl8711bb_set_hal_ops(_adapter * padapter); +#define hal_set_hal_ops rtl8711bb_set_hal_ops +#define hal_interuupt_recognized InterruptRecognized8711b +#endif + + +#endif //__HAL_INTF_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_pg.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_pg.h new file mode 100644 index 0000000..70d4734 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_pg.h @@ -0,0 +1,81 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PG_H__ +#define __HAL_PG_H__ + +#include + +// +// For VHT series TX power by rate table. +// VHT TX power by rate off setArray = +// Band:-2G&5G = 0 / 1 +// RF: at most 4*4 = ABCD=0/1/2/3 +// CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11 +// +#define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F +#define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0 + +#define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F +#define PPG_THERMAL_OFFSET_MASK 0x1F +#define KFREE_BB_GAIN_2G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) +#define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) + + + +#if defined(NOT_SUPPORT_5G) +#define TX_PWR_BY_RATE_NUM_BAND 1 +#else +#define TX_PWR_BY_RATE_NUM_BAND 2 +#endif + +#if defined(NOT_SUPPORT_RF_MULTIPATH) && defined(NOT_SUPPORT_VHT) +#define TX_PWR_BY_RATE_NUM_RF 1 +#define TX_PWR_BY_RATE_NUM_RATE 20 // CCK 1M~11M, OFDM 6M~54M, MCS0~7 +#else +#define TX_PWR_BY_RATE_NUM_RF 4 +#define TX_PWR_BY_RATE_NUM_RATE 84 +#endif + +#if defined(NOT_SUPPORT_RF_MULTIPATH) +#define MAX_RF_PATH 1 +#define MAX_TX_COUNT 1 +#else +#define MAX_RF_PATH 2 // Max 4 for ss larger than 2 +#define MAX_TX_COUNT 4 //It must always set to 4, otherwise read efuse table secquence will be wrong. +#endif +#define MAX_CHNL_GROUP_24G 6 // ch1~2, ch3~5, ch6~8,ch9~11,ch12~13,CH 14 total three groups +#define MAX_CHNL_GROUP_5G 14 + +typedef struct _TxPowerInfo24G{ + u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; + u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; + //If only one tx, only BW20 and OFDM are used. + s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; +#if !defined(NOT_SUPPORT_RF_MULTIPATH) + s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; +#endif +}TxPowerInfo24G, *PTxPowerInfo24G; + +#endif + + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_phy.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_phy.h new file mode 100644 index 0000000..1488005 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_phy.h @@ -0,0 +1,99 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_PHY_H__ +#define __HAL_PHY_H__ + +#define RF6052_MAX_TX_PWR 0x3F +#define RF6052_MAX_REG_88E 0xFF +#define RF6052_MAX_REG_92C 0x7F + +#define RF6052_MAX_REG \ + (RF6052_MAX_REG_88E > RF6052_MAX_REG_92C) ? RF6052_MAX_REG_88E: RF6052_MAX_REG_92C + +#define GET_RF6052_REAL_MAX_REG(_Adapter) \ + IS_HARDWARE_TYPE_8188E(_Adapter) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C + +#define RF6052_MAX_PATH 2 + +/*--------------------------Define Parameters-------------------------------*/ +typedef enum _BAND_TYPE{ + BAND_ON_2_4G = 0, + BAND_ON_5G, + BAND_ON_BOTH, + BANDMAX +}BAND_TYPE,*PBAND_TYPE; + +typedef enum _RF_TYPE{ + RF_TYPE_MIN = 0, // 0 + RF_8225=1, // 1 11b/g RF for verification only + RF_8256=2, // 2 11b/g/n + RF_8258=3, // 3 11a/b/g/n RF + RF_6052=4, // 4 11b/g/n RF + RF_PSEUDO_11N=5, // 5, It is a temporality RF. + RF_TYPE_MAX +}RF_TYPE_E,*PRF_TYPE_E; + +typedef enum _RF_PATH{ + RF_PATH_A = 0, + RF_PATH_B, + RF_PATH_C, + RF_PATH_D +}RF_PATH, *PRF_PATH; + +#define TX_1S 0 +#define TX_2S 1 +#define TX_3S 2 +#define TX_4S 3 + +typedef enum _BaseBand_Config_Type{ + BaseBand_Config_PHY_REG = 0, //Radio Path A + BaseBand_Config_AGC_TAB = 1, //Radio Path B + BaseBand_Config_AGC_TAB_2G = 2, + BaseBand_Config_AGC_TAB_5G = 3, + BaseBand_Config_PHY_REG_PG +}BaseBand_Config_Type, *PBaseBand_Config_Type; + +typedef enum _WIRELESS_MODE { + WIRELESS_MODE_UNKNOWN = 0x00, + WIRELESS_MODE_A = 0x01, + WIRELESS_MODE_B = 0x02, + WIRELESS_MODE_G = 0x04, + WIRELESS_MODE_AUTO = 0x08, + WIRELESS_MODE_N_24G = 0x10, + WIRELESS_MODE_N_5G = 0x20, + WIRELESS_MODE_AC_5G = 0x40, + WIRELESS_MODE_AC_24G = 0x80, + WIRELESS_MODE_AC_ONLY = 0x100, +} WIRELESS_MODE; + +typedef struct RF_Shadow_Compare_Map { + // Shadow register value + u32 Value; + // Compare or not flag + u8 Compare; + // Record If it had ever modified unpredicted + u8 ErrorOrNot; + // Recorver Flag + u8 Recorver; + // + u8 Driver_Write; +}RF_SHADOW_T; + +#endif //__HAL_PHY_H__ diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_phy_reg.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_phy_reg.h new file mode 100644 index 0000000..723eddb --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/hal_phy_reg.h @@ -0,0 +1,31 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_PHY_REG_H__ +#define __HAL_PHY_REG_H__ + +//for PutRFRegsetting & GetRFRegSetting BitMask +//#if (RTL92SE_FPGA_VERIFY == 1) +//#define bRFRegOffsetMask 0xfff +//#else +#define bRFRegOffsetMask 0xfffff +//#endif + +#endif //__HAL_PHY_REG_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/ieee80211.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/ieee80211.h new file mode 100644 index 0000000..69b98d7 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/ieee80211.h @@ -0,0 +1,1527 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __IEEE80211_H +#define __IEEE80211_H + +#ifndef CONFIG_RTL8711FW + +// #include + + #if defined PLATFORM_OS_XP + #include + #endif + #if defined PLATFORM_LINUX + #include + #endif +#else + + #include + +#endif + +#define MGMT_QUEUE_NUM 5 + +#define ETH_ALEN 6 +#define ETH_TYPE_LEN 2 +#define PAYLOAD_TYPE_LEN 1 + +#ifdef CONFIG_AP_MODE + +#define RTL_IOCTL_HOSTAPD (SIOCIWFIRSTPRIV + 28) + +/* RTL871X_IOCTL_HOSTAPD ioctl() cmd: */ +enum { + RTL871X_HOSTAPD_FLUSH = 1, + RTL871X_HOSTAPD_ADD_STA = 2, + RTL871X_HOSTAPD_REMOVE_STA = 3, + RTL871X_HOSTAPD_GET_INFO_STA = 4, + /* REMOVED: PRISM2_HOSTAPD_RESET_TXEXC_STA = 5, */ + RTL871X_HOSTAPD_GET_WPAIE_STA = 5, + RTL871X_SET_ENCRYPTION = 6, + RTL871X_GET_ENCRYPTION = 7, + RTL871X_HOSTAPD_SET_FLAGS_STA = 8, + RTL871X_HOSTAPD_GET_RID = 9, + RTL871X_HOSTAPD_SET_RID = 10, + RTL871X_HOSTAPD_SET_ASSOC_AP_ADDR = 11, + RTL871X_HOSTAPD_SET_GENERIC_ELEMENT = 12, + RTL871X_HOSTAPD_MLME = 13, + RTL871X_HOSTAPD_SCAN_REQ = 14, + RTL871X_HOSTAPD_STA_CLEAR_STATS = 15, + RTL871X_HOSTAPD_SET_BEACON=16, + RTL871X_HOSTAPD_SET_WPS_BEACON = 17, + RTL871X_HOSTAPD_SET_WPS_PROBE_RESP = 18, + RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP = 19, + RTL871X_HOSTAPD_SET_HIDDEN_SSID = 20, + RTL871X_HOSTAPD_SET_MACADDR_ACL = 21, + RTL871X_HOSTAPD_ACL_ADD_STA = 22, + RTL871X_HOSTAPD_ACL_REMOVE_STA = 23, +}; + +/* STA flags */ +#define WLAN_STA_AUTH BIT(0) +#define WLAN_STA_ASSOC BIT(1) +#define WLAN_STA_PS BIT(2) +#define WLAN_STA_TIM BIT(3) +#define WLAN_STA_PERM BIT(4) +#define WLAN_STA_AUTHORIZED BIT(5) +#define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */ +#define WLAN_STA_SHORT_PREAMBLE BIT(7) +#define WLAN_STA_PREAUTH BIT(8) +#define WLAN_STA_WME BIT(9) +#define WLAN_STA_MFP BIT(10) +#define WLAN_STA_HT BIT(11) +#define WLAN_STA_WPS BIT(12) +#define WLAN_STA_MAYBE_WPS BIT(13) +#define WLAN_STA_NONERP BIT(31) + +#endif + +#define IEEE_CMD_SET_WPA_PARAM 1 +#define IEEE_CMD_SET_WPA_IE 2 +#define IEEE_CMD_SET_ENCRYPTION 3 +#define IEEE_CMD_MLME 4 + +#define IEEE_PARAM_WPA_ENABLED 1 +#define IEEE_PARAM_TKIP_COUNTERMEASURES 2 +#define IEEE_PARAM_DROP_UNENCRYPTED 3 +#define IEEE_PARAM_PRIVACY_INVOKED 4 +#define IEEE_PARAM_AUTH_ALGS 5 +#define IEEE_PARAM_IEEE_802_1X 6 +#define IEEE_PARAM_WPAX_SELECT 7 + +#define AUTH_ALG_OPEN_SYSTEM 0x1 +#define AUTH_ALG_SHARED_KEY 0x2 +#define AUTH_ALG_LEAP 0x00000004 + +#define IEEE_MLME_STA_DEAUTH 1 +#define IEEE_MLME_STA_DISASSOC 2 + +#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2 +#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3 +#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4 +#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5 +#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6 +#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7 + + +#define IEEE_CRYPT_ALG_NAME_LEN 16 + +#define WPA_CIPHER_NONE BIT(0) +#define WPA_CIPHER_WEP40 BIT(1) +#define WPA_CIPHER_WEP104 BIT(2) +#define WPA_CIPHER_TKIP BIT(3) +#define WPA_CIPHER_CCMP BIT(4) + + + +#define WPA_SELECTOR_LEN 4 +//extern u16 RTW_WPA_VERSION ; +//extern u8 WPA_AUTH_KEY_MGMT_NONE[]; +//extern u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[]; +//extern u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[]; +//extern u8 WPA_CIPHER_SUITE_WRAP[]; + +#define RSN_HEADER_LEN 4 +#define RSN_SELECTOR_LEN 4 + +//tern u8 RSN_CIPHER_SUITE_WRAP[]; + +typedef enum _RATEID_IDX_ { + RATEID_IDX_BGN_40M_2SS = 0, + RATEID_IDX_BGN_40M_1SS = 1, + RATEID_IDX_BGN_20M_2SS_BN = 2, + RATEID_IDX_BGN_20M_1SS_BN = 3, + RATEID_IDX_GN_N2SS = 4, + RATEID_IDX_GN_N1SS = 5, + RATEID_IDX_BG = 6, + RATEID_IDX_G = 7, + RATEID_IDX_B = 8, + RATEID_IDX_VHT_2SS = 9, + RATEID_IDX_VHT_1SS = 10, +} RATEID_IDX, *PRATEID_IDX; + +enum NETWORK_TYPE +{ + WIRELESS_INVALID = 0, + //Sub-Element + WIRELESS_11B = BIT(0), // tx: cck only , rx: cck only, hw: cck + WIRELESS_11G = BIT(1), // tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm + WIRELESS_11A = BIT(2), // tx: ofdm only, rx: ofdm only, hw: ofdm only + WIRELESS_11_24N = BIT(3), // tx: MCS only, rx: MCS & cck, hw: MCS & cck + WIRELESS_11_5N = BIT(4), // tx: MCS only, rx: MCS & ofdm, hw: ofdm only + //WIRELESS_AUTO = BIT(5), + WIRELESS_11AC = BIT(6), + + //Combination + WIRELESS_11BG = (WIRELESS_11B|WIRELESS_11G), // tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm + WIRELESS_11G_24N = (WIRELESS_11G|WIRELESS_11_24N), // tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm + WIRELESS_11A_5N = (WIRELESS_11A|WIRELESS_11_5N), // tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only + WIRELESS_11BG_24N = (WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N), // tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck + WIRELESS_11AGN = (WIRELESS_11A|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), // tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only + WIRELESS_11ABGN = (WIRELESS_11A|WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), +}; + + +#define SUPPORTED_24G_NETTYPE_MSK (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N) +#define SUPPORTED_5G_NETTYPE_MSK (WIRELESS_11A | WIRELESS_11_5N) + +#define IsSupported24G(NetType) ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? _TRUE : _FALSE) +#define IsSupported5G(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? _TRUE : _FALSE) + +//TODO +#if 0 +#define IsEnableHWCCK(NetType) IsSupported24G(NetType) +#define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11_24N|SUPPORTED_5G_NETTYPE_MSK) ? _TRUE : _FALSE) + +#define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType) +#define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType) +#define IsSupportedRxMCS(NetType) IsEnableHWOFDM(NetType) + +#define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE) +#define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11A) ? _TRUE : _FALSE) +#define IsSupportedTxMCS(NetType) ((NetType) & (WIRELESS_11_24N|WIRELESS_11_5N) ? _TRUE : _FALSE) + +#endif //#if 0 + +typedef struct ieee_param { + u32 cmd; + u8 sta_addr[ETH_ALEN]; + union { + struct { + u8 name; + u32 value; + } wpa_param; + struct { + u32 len; + u8 reserved[32]; +#ifdef __CC_ARM + u8 data[1]; +#else + u8 data[0]; +#endif + } wpa_ie; + struct{ + int command; + int reason_code; + } mlme; + struct { + u8 alg[IEEE_CRYPT_ALG_NAME_LEN]; + u8 set_tx; + u32 err; + u8 idx; + u8 seq[8]; /* sequence counter (set: RX, get: TX) */ + u16 key_len; +#ifdef __CC_ARM + u8 key[1]; +#else + u8 key[0]; +#endif + } crypt; +#ifdef CONFIG_AP_MODE + struct { + u16 aid; + u16 capability; + int flags; + u8 tx_supp_rates[16]; + struct rtw_ieee80211_ht_cap ht_cap; + } add_sta; + struct { + u8 reserved[2];//for set max_num_sta +#ifdef __CC_ARM + u8 buf[1]; +#else + u8 buf[0]; +#endif + } bcn_ie; +#endif + + } u; +}ieee_param; + +//TODO +#if 0 + +#ifdef CONFIG_AP_MODE +typedef struct ieee_param_ex { + u32 cmd; + u8 sta_addr[ETH_ALEN]; + u8 data[0]; +}ieee_param_ex; + +struct sta_data{ + u16 aid; + u16 capability; + int flags; + u32 sta_set; + u8 tx_supp_rates[16]; + u32 tx_supp_rates_len; + struct rtw_ieee80211_ht_cap ht_cap; + u64 rx_pkts; + u64 rx_bytes; + u64 rx_drops; + u64 tx_pkts; + u64 tx_bytes; + u64 tx_drops; +}; +#endif + + +#if WIRELESS_EXT < 17 +#define IW_QUAL_QUAL_INVALID 0x10 +#define IW_QUAL_LEVEL_INVALID 0x20 +#define IW_QUAL_NOISE_INVALID 0x40 +#define IW_QUAL_QUAL_UPDATED 0x1 +#define IW_QUAL_LEVEL_UPDATED 0x2 +#define IW_QUAL_NOISE_UPDATED 0x4 +#endif + +#define IEEE80211_DATA_LEN 2304 +/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section + 6.2.1.1.2. + + The figure in section 7.1.2 suggests a body size of up to 2312 + bytes is allowed, which is a bit confusing, I suspect this + represents the 2304 bytes of real data, plus a possible 8 bytes of + WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */ + + +#define IEEE80211_HLEN 30 +#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) + + +/* this is stolen from ipw2200 driver */ +#define IEEE_IBSS_MAC_HASH_SIZE 31 + +struct ieee_ibss_seq { + u8 mac[ETH_ALEN]; + u16 seq_num; + u16 frag_num; + unsigned long packet_time; + _list list; +}; + +#endif //#if 0 + +#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)||defined(PLATFORM_FREEBSD) || defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined(PLATFORM_CMSIS_RTOS) + +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_begin.h" +#endif +RTW_PACK_STRUCT_BEGIN +struct rtw_ieee80211_hdr { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; + u8 addr4[ETH_ALEN]; +} RTW_PACK_STRUCT_STRUCT; +RTW_PACK_STRUCT_END +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_end.h" +#endif + +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_begin.h" +#endif +RTW_PACK_STRUCT_BEGIN +struct rtw_ieee80211_hdr_3addr { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; +} RTW_PACK_STRUCT_STRUCT; +RTW_PACK_STRUCT_END +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_end.h" +#endif + +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_begin.h" +#endif +RTW_PACK_STRUCT_BEGIN +struct rtw_ieee80211_hdr_qos { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; + u8 addr4[ETH_ALEN]; + u16 qc; +} RTW_PACK_STRUCT_STRUCT; +RTW_PACK_STRUCT_END +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_end.h" +#endif + +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_begin.h" +#endif +RTW_PACK_STRUCT_BEGIN +struct rtw_ieee80211_hdr_3addr_qos { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; + u16 qc; +} RTW_PACK_STRUCT_STRUCT; +RTW_PACK_STRUCT_END +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_end.h" +#endif + +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_begin.h" +#endif +RTW_PACK_STRUCT_BEGIN +struct eapol { + u8 snap[6]; + u16 ethertype; + u8 version; + u8 type; + u16 length; +} RTW_PACK_STRUCT_STRUCT; +RTW_PACK_STRUCT_END +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_end.h" +#endif + +#endif //defined PLATFORM_LINUX/CONFIG_RTL8711FW/PLATFORM_FREEBSD/PLATFORM_ECOSPLATFORM_FREERTOS + +//TODO +#if 0 + +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_begin.h" +#endif +struct rtw_ieee80211_hdr { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; + u8 addr4[ETH_ALEN]; +}; + +struct rtw_ieee80211_hdr_3addr { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; +}; + + +struct rtw_ieee80211_hdr_qos { + struct rtw_ieee80211_hdr wlan_hdr; + u16 qc; +}; + +struct rtw_ieee80211_hdr_3addr_qos { + struct rtw_ieee80211_hdr_3addr wlan_hdr; + u16 qc; +}; + +struct eapol { + u8 snap[6]; + u16 ethertype; + u8 version; + u8 type; + u16 length; +}; +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_end.h" +#endif + + + +enum eap_type { + EAP_PACKET = 0, + EAPOL_START, + EAPOL_LOGOFF, + EAPOL_KEY, + EAPOL_ENCAP_ASF_ALERT +}; + +#endif //#if 0 + +#define IEEE80211_3ADDR_LEN 24 +#define IEEE80211_4ADDR_LEN 30 +#define IEEE80211_FCS_LEN 4 + +#define MIN_FRAG_THRESHOLD 256U +#define MAX_FRAG_THRESHOLD 2346U + +/* Frame control field constants */ +#define RTW_IEEE80211_FCTL_VERS 0x0002 +#define RTW_IEEE80211_FCTL_FTYPE 0x000c +#define RTW_IEEE80211_FCTL_STYPE 0x00f0 +#define RTW_IEEE80211_FCTL_TODS 0x0100 +#define RTW_IEEE80211_FCTL_FROMDS 0x0200 +#define RTW_IEEE80211_FCTL_MOREFRAGS 0x0400 +#define RTW_IEEE80211_FCTL_RETRY 0x0800 +#define RTW_IEEE80211_FCTL_PM 0x1000 +#define RTW_IEEE80211_FCTL_MOREDATA 0x2000 +#define RTW_IEEE80211_FCTL_WEP 0x4000 +#define RTW_IEEE80211_FCTL_ORDER 0x8000 + +#define RTW_IEEE80211_FTYPE_MGMT 0x0000 +#define RTW_IEEE80211_FTYPE_CTL 0x0004 +#define RTW_IEEE80211_FTYPE_DATA 0x0008 + +/* management */ +#define RTW_IEEE80211_STYPE_ASSOC_REQ 0x0000 +#define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010 +#define RTW_IEEE80211_STYPE_REASSOC_REQ 0x0020 +#define RTW_IEEE80211_STYPE_REASSOC_RESP 0x0030 +#define RTW_IEEE80211_STYPE_PROBE_REQ 0x0040 +#define RTW_IEEE80211_STYPE_PROBE_RESP 0x0050 +#define RTW_IEEE80211_STYPE_BEACON 0x0080 +#define RTW_IEEE80211_STYPE_ATIM 0x0090 +#define RTW_IEEE80211_STYPE_DISASSOC 0x00A0 +#define RTW_IEEE80211_STYPE_AUTH 0x00B0 +#define RTW_IEEE80211_STYPE_DEAUTH 0x00C0 + +/* control */ +#define RTW_IEEE80211_STYPE_PSPOLL 0x00A0 +#define RTW_IEEE80211_STYPE_RTS 0x00B0 +#define RTW_IEEE80211_STYPE_CTS 0x00C0 +#define RTW_IEEE80211_STYPE_ACK 0x00D0 +#define RTW_IEEE80211_STYPE_CFEND 0x00E0 +#define RTW_IEEE80211_STYPE_CFENDACK 0x00F0 + +/* data */ +#define RTW_IEEE80211_STYPE_DATA 0x0000 +#define RTW_IEEE80211_STYPE_DATA_CFACK 0x0010 +#define RTW_IEEE80211_STYPE_DATA_CFPOLL 0x0020 +#define RTW_IEEE80211_STYPE_DATA_CFACKPOLL 0x0030 +#define RTW_IEEE80211_STYPE_NULLFUNC 0x0040 +#define RTW_IEEE80211_STYPE_CFACK 0x0050 +#define RTW_IEEE80211_STYPE_CFPOLL 0x0060 +#define RTW_IEEE80211_STYPE_CFACKPOLL 0x0070 +#define RTW_IEEE80211_QOS_DATAGRP 0x0080 +#define RTW_IEEE80211_QoS_DATAGRP RTW_IEEE80211_QOS_DATAGRP + +#define RTW_IEEE80211_SCTL_FRAG 0x000F +#define RTW_IEEE80211_SCTL_SEQ 0xFFF0 + + +#define RTW_ERP_INFO_NON_ERP_PRESENT BIT(0) +#define RTW_ERP_INFO_USE_PROTECTION BIT(1) +#define RTW_ERP_INFO_BARKER_PREAMBLE_MODE BIT(2) + +/* QoS,QOS */ +#define NORMAL_ACK 0 +#define NO_ACK 1 +#define NON_EXPLICIT_ACK 2 +#define BLOCK_ACK 3 + +#ifndef ETH_P_PAE +#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ +#endif /* ETH_P_PAE */ + +#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */ + +#define ETH_P_ECONET 0x0018 + +#ifndef ETH_P_80211_RAW +#define ETH_P_80211_RAW (ETH_P_ECONET + 1) +#endif + +/* IEEE 802.11 defines */ + +#define P80211_OUI_LEN 3 + + +#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) || defined(PLATFORM_FREEBSD) || defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined(PLATFORM_CMSIS_RTOS) +RTW_PACK_STRUCT_BEGIN +struct ieee80211_snap_hdr { + + u8 dsap; /* always 0xAA */ + u8 ssap; /* always 0xAA */ + u8 ctrl; /* always 0x03 */ + u8 oui[P80211_OUI_LEN]; /* organizational universal id */ + +} RTW_PACK_STRUCT_STRUCT; +RTW_PACK_STRUCT_END + +#endif + +#ifdef PLATFORM_WINDOWS + +#pragma pack(1) +struct ieee80211_snap_hdr { + + u8 dsap; /* always 0xAA */ + u8 ssap; /* always 0xAA */ + u8 ctrl; /* always 0x03 */ + u8 oui[P80211_OUI_LEN]; /* organizational universal id */ + +}; +#pragma pack() + +#endif + + +#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) + +#define WLAN_FC_GET_TYPE(fc) ((fc) & RTW_IEEE80211_FCTL_FTYPE) +#define WLAN_FC_GET_STYPE(fc) ((fc) & RTW_IEEE80211_FCTL_STYPE) + +#define WLAN_QC_GET_TID(qc) ((qc) & 0x0f) + +#define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG) +#define WLAN_GET_SEQ_SEQ(seq) ((seq) & RTW_IEEE80211_SCTL_SEQ) + + + +/* Authentication algorithms */ +#define WLAN_AUTH_OPEN 0 +#define WLAN_AUTH_SHARED_KEY 1 + +#define WLAN_AUTH_CHALLENGE_LEN 128 + +#define WLAN_CAPABILITY_BSS (1<<0) +#define WLAN_CAPABILITY_IBSS (1<<1) +#define WLAN_CAPABILITY_CF_POLLABLE (1<<2) +#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3) +#define WLAN_CAPABILITY_PRIVACY (1<<4) +#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5) +#define WLAN_CAPABILITY_PBCC (1<<6) +#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7) +#define WLAN_CAPABILITY_SHORT_SLOT (1<<10) + +/* Status codes */ +#define WLAN_STATUS_SUCCESS 0 +#define WLAN_STATUS_UNSPECIFIED_FAILURE 1 +#define WLAN_STATUS_CAPS_UNSUPPORTED 10 +#define WLAN_STATUS_REASSOC_NO_ASSOC 11 +#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12 +#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13 +#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14 +#define WLAN_STATUS_CHALLENGE_FAIL 15 +#define WLAN_STATUS_AUTH_TIMEOUT 16 +#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17 +#define WLAN_STATUS_ASSOC_DENIED_RATES 18 +/* 802.11b */ +#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19 +#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20 +#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21 + +/* Reason codes */ +#define WLAN_REASON_UNSPECIFIED 1 +#define WLAN_REASON_PREV_AUTH_NOT_VALID 2 +#define WLAN_REASON_DEAUTH_LEAVING 3 +#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4 +#define WLAN_REASON_DISASSOC_AP_BUSY 5 +#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 +#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 +#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 +#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 +#define WLAN_REASON_JOIN_WRONG_CHANNEL 65534 + +/* Information Element IDs */ +#define WLAN_EID_SSID 0 +#define WLAN_EID_SUPP_RATES 1 +#define WLAN_EID_FH_PARAMS 2 +#define WLAN_EID_DS_PARAMS 3 +#define WLAN_EID_CF_PARAMS 4 +#define WLAN_EID_TIM 5 +#define WLAN_EID_IBSS_PARAMS 6 +#define WLAN_EID_CHALLENGE 16 +/* EIDs defined by IEEE 802.11h - START */ +#define WLAN_EID_PWR_CONSTRAINT 32 +#define WLAN_EID_PWR_CAPABILITY 33 +#define WLAN_EID_TPC_REQUEST 34 +#define WLAN_EID_TPC_REPORT 35 +#define WLAN_EID_SUPPORTED_CHANNELS 36 +#define WLAN_EID_CHANNEL_SWITCH 37 +#define WLAN_EID_MEASURE_REQUEST 38 +#define WLAN_EID_MEASURE_REPORT 39 +#define WLAN_EID_QUITE 40 +#define WLAN_EID_IBSS_DFS 41 +/* EIDs defined by IEEE 802.11h - END */ +#define WLAN_EID_ERP_INFO 42 +#define WLAN_EID_HT_CAP 45 +#define WLAN_EID_RSN 48 +#define WLAN_EID_EXT_SUPP_RATES 50 +#define WLAN_EID_MOBILITY_DOMAIN 54 +#define WLAN_EID_FAST_BSS_TRANSITION 55 +#define WLAN_EID_TIMEOUT_INTERVAL 56 +#define WLAN_EID_RIC_DATA 57 +#define WLAN_EID_HT_OPERATION 61 +#define WLAN_EID_SECONDARY_CHANNEL_OFFSET 62 +#define WLAN_EID_20_40_BSS_COEXISTENCE 72 +#define WLAN_EID_20_40_BSS_INTOLERANT 73 +#define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74 +#define WLAN_EID_MMIE 76 +#define WLAN_EID_VENDOR_SPECIFIC 221 +#define WLAN_EID_GENERIC (WLAN_EID_VENDOR_SPECIFIC) + +#define IEEE80211_MGMT_HDR_LEN 24 +#define IEEE80211_DATA_HDR3_LEN 24 +#define IEEE80211_DATA_HDR4_LEN 30 + + +#define IEEE80211_STATMASK_SIGNAL (1<<0) +#define IEEE80211_STATMASK_RSSI (1<<1) +#define IEEE80211_STATMASK_NOISE (1<<2) +#define IEEE80211_STATMASK_RATE (1<<3) +#define IEEE80211_STATMASK_WEMASK 0x7 + + +#define IEEE80211_CCK_MODULATION (1<<0) +#define IEEE80211_OFDM_MODULATION (1<<1) + +#define IEEE80211_24GHZ_BAND (1<<0) +#define IEEE80211_52GHZ_BAND (1<<1) + +#define IEEE80211_CCK_RATE_LEN 4 +#define IEEE80211_NUM_OFDM_RATESLEN 8 + + +#define IEEE80211_CCK_RATE_1MB 0x02 +#define IEEE80211_CCK_RATE_2MB 0x04 +#define IEEE80211_CCK_RATE_5MB 0x0B +#define IEEE80211_CCK_RATE_11MB 0x16 +#define IEEE80211_OFDM_RATE_LEN 8 +#define IEEE80211_OFDM_RATE_6MB 0x0C +#define IEEE80211_OFDM_RATE_9MB 0x12 +#define IEEE80211_OFDM_RATE_12MB 0x18 +#define IEEE80211_OFDM_RATE_18MB 0x24 +#define IEEE80211_OFDM_RATE_24MB 0x30 +#define IEEE80211_OFDM_RATE_36MB 0x48 +#define IEEE80211_OFDM_RATE_48MB 0x60 +#define IEEE80211_OFDM_RATE_54MB 0x6C +#define IEEE80211_BASIC_RATE_MASK 0x80 + +#define IEEE80211_CCK_RATE_1MB_MASK (1<<0) +#define IEEE80211_CCK_RATE_2MB_MASK (1<<1) +#define IEEE80211_CCK_RATE_5MB_MASK (1<<2) +#define IEEE80211_CCK_RATE_11MB_MASK (1<<3) +#define IEEE80211_OFDM_RATE_6MB_MASK (1<<4) +#define IEEE80211_OFDM_RATE_9MB_MASK (1<<5) +#define IEEE80211_OFDM_RATE_12MB_MASK (1<<6) +#define IEEE80211_OFDM_RATE_18MB_MASK (1<<7) +#define IEEE80211_OFDM_RATE_24MB_MASK (1<<8) +#define IEEE80211_OFDM_RATE_36MB_MASK (1<<9) +#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10) +#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11) + + +#define IEEE80211_CCK_RATES_MASK 0x0000000F +#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \ + IEEE80211_CCK_RATE_2MB_MASK) +#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \ + IEEE80211_CCK_RATE_5MB_MASK | \ + IEEE80211_CCK_RATE_11MB_MASK) + +#define IEEE80211_OFDM_RATES_MASK 0x00000FF0 +#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \ + IEEE80211_OFDM_RATE_12MB_MASK | \ + IEEE80211_OFDM_RATE_24MB_MASK) +#define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \ + IEEE80211_OFDM_RATE_9MB_MASK | \ + IEEE80211_OFDM_RATE_18MB_MASK | \ + IEEE80211_OFDM_RATE_36MB_MASK | \ + IEEE80211_OFDM_RATE_48MB_MASK | \ + IEEE80211_OFDM_RATE_54MB_MASK) +#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \ + IEEE80211_CCK_DEFAULT_RATES_MASK) + +#define IEEE80211_NUM_OFDM_RATES 8 +#define IEEE80211_NUM_CCK_RATES 4 +#define IEEE80211_OFDM_SHIFT_MASK_A 4 + + +/* BIT 7 HT Rate*/ +enum MGN_RATE{ + MGN_1M = 0x02, + MGN_2M = 0x04, + MGN_5_5M = 0x0B, + MGN_6M = 0x0C, + MGN_9M = 0x12, + MGN_11M = 0x16, + MGN_12M = 0x18, + MGN_18M = 0x24, + MGN_24M = 0x30, + MGN_36M = 0x48, + MGN_48M = 0x60, + MGN_54M = 0x6C, + MGN_MCS32 = 0x7F, + MGN_MCS0, + MGN_MCS1, + MGN_MCS2, + MGN_MCS3, + MGN_MCS4, + MGN_MCS5, + MGN_MCS6, + MGN_MCS7, + MGN_MCS8, + MGN_MCS9, + MGN_MCS10, + MGN_MCS11, + MGN_MCS12, + MGN_MCS13, + MGN_MCS14, + MGN_MCS15, + MGN_MCS16, + MGN_MCS17, + MGN_MCS18, + MGN_MCS19, + MGN_MCS20, + MGN_MCS21, + MGN_MCS22, + MGN_MCS23, + MGN_MCS24, + MGN_MCS25, + MGN_MCS26, + MGN_MCS27, + MGN_MCS28, + MGN_MCS29, + MGN_MCS30, + MGN_MCS31, + MGN_VHT1SS_MCS0, + MGN_VHT1SS_MCS1, + MGN_VHT1SS_MCS2, + MGN_VHT1SS_MCS3, + MGN_VHT1SS_MCS4, + MGN_VHT1SS_MCS5, + MGN_VHT1SS_MCS6, + MGN_VHT1SS_MCS7, + MGN_VHT1SS_MCS8, + MGN_VHT1SS_MCS9, + MGN_VHT2SS_MCS0, + MGN_VHT2SS_MCS1, + MGN_VHT2SS_MCS2, + MGN_VHT2SS_MCS3, + MGN_VHT2SS_MCS4, + MGN_VHT2SS_MCS5, + MGN_VHT2SS_MCS6, + MGN_VHT2SS_MCS7, + MGN_VHT2SS_MCS8, + MGN_VHT2SS_MCS9, + MGN_VHT3SS_MCS0, + MGN_VHT3SS_MCS1, + MGN_VHT3SS_MCS2, + MGN_VHT3SS_MCS3, + MGN_VHT3SS_MCS4, + MGN_VHT3SS_MCS5, + MGN_VHT3SS_MCS6, + MGN_VHT3SS_MCS7, + MGN_VHT3SS_MCS8, + MGN_VHT3SS_MCS9, + MGN_VHT4SS_MCS0, + MGN_VHT4SS_MCS1, + MGN_VHT4SS_MCS2, + MGN_VHT4SS_MCS3, + MGN_VHT4SS_MCS4, + MGN_VHT4SS_MCS5, + MGN_VHT4SS_MCS6, + MGN_VHT4SS_MCS7, + MGN_VHT4SS_MCS8, + MGN_VHT4SS_MCS9, + MGN_UNKNOWN +}; + + +#define MGN_MCS0_SG 0xc0 +#define MGN_MCS1_SG 0xc1 +#define MGN_MCS2_SG 0xc2 +#define MGN_MCS3_SG 0xc3 +#define MGN_MCS4_SG 0xc4 +#define MGN_MCS5_SG 0xc5 +#define MGN_MCS6_SG 0xc6 +#define MGN_MCS7_SG 0xc7 +#define MGN_MCS8_SG 0xc8 +#define MGN_MCS9_SG 0xc9 +#define MGN_MCS10_SG 0xca +#define MGN_MCS11_SG 0xcb +#define MGN_MCS12_SG 0xcc +#define MGN_MCS13_SG 0xcd +#define MGN_MCS14_SG 0xce +#define MGN_MCS15_SG 0xcf + +#define IS_HT_RATE(_rate) (((_rate) & 0x80) ? _TRUE : _FALSE) +#define IS_CCK_RATE(_rate) (MGN_1M == _rate || _rate == MGN_2M || _rate == MGN_5_5M || _rate == MGN_11M ) +#define IS_OFDM_RATE(_rate) (MGN_6M <= _rate && _rate <= MGN_54M ) + + +/* NOTE: This data is for statistical purposes; not all hardware provides this + * information for frames received. Not setting these will not cause + * any adverse affects. */ +struct ieee80211_rx_stats { + //u32 mac_time[2]; + s8 rssi; + u8 signal; + u8 noise; + u8 received_channel; + u16 rate; /* in 100 kbps */ + //u8 control; + u8 mask; + u8 freq; + u16 len; +}; + +/* IEEE 802.11 requires that STA supports concurrent reception of at least + * three fragmented frames. This define can be increased to support more + * concurrent frames, but it should be noted that each entry can consume about + * 2 kB of RAM and increasing cache size will slow down frame reassembly. */ +#define IEEE80211_FRAG_CACHE_LEN 4 + +struct ieee80211_frag_entry { + u32 first_frag_time; + uint seq; + uint last_frag; + uint qos; //jackson + uint tid; //jackson + struct sk_buff *skb; + u8 src_addr[ETH_ALEN]; + u8 dst_addr[ETH_ALEN]; +}; + +#ifndef PLATFORM_FREEBSD //Baron BSD has already defined +struct ieee80211_stats { + uint tx_unicast_frames; + uint tx_multicast_frames; + uint tx_fragments; + uint tx_unicast_octets; + uint tx_multicast_octets; + uint tx_deferred_transmissions; + uint tx_single_retry_frames; + uint tx_multiple_retry_frames; + uint tx_retry_limit_exceeded; + uint tx_discards; + uint rx_unicast_frames; + uint rx_multicast_frames; + uint rx_fragments; + uint rx_unicast_octets; + uint rx_multicast_octets; + uint rx_fcs_errors; + uint rx_discards_no_buffer; + uint tx_discards_wrong_sa; + uint rx_discards_undecryptable; + uint rx_message_in_msg_fragments; + uint rx_message_in_bad_msg_fragments; +}; +#endif //PLATFORM_FREEBSD +struct ieee80211_softmac_stats{ + uint rx_ass_ok; + uint rx_ass_err; + uint rx_probe_rq; + uint tx_probe_rs; + uint tx_beacons; + uint rx_auth_rq; + uint rx_auth_rs_ok; + uint rx_auth_rs_err; + uint tx_auth_rq; + uint no_auth_rs; + uint no_ass_rs; + uint tx_ass_rq; + uint rx_ass_rq; + uint tx_probe_rq; + uint reassoc; + uint swtxstop; + uint swtxawake; +}; + +#define SEC_KEY_1 (1<<0) +#define SEC_KEY_2 (1<<1) +#define SEC_KEY_3 (1<<2) +#define SEC_KEY_4 (1<<3) +#define SEC_ACTIVE_KEY (1<<4) +#define SEC_AUTH_MODE (1<<5) +#define SEC_UNICAST_GROUP (1<<6) +#define SEC_LEVEL (1<<7) +#define SEC_ENABLED (1<<8) + +#define SEC_LEVEL_0 0 /* None */ +#define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */ +#define SEC_LEVEL_2 2 /* Level 1 + TKIP */ +#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */ +#define SEC_LEVEL_3 4 /* Level 2 + CCMP */ + +#define WEP_KEYS 4 +#define WEP_KEY_LEN 13 + + + +#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) + +struct ieee80211_security { + u16 active_key:2, + enabled:1, + auth_mode:2, + auth_algo:4, + unicast_uses_group:1; + u8 key_sizes[WEP_KEYS]; + u8 keys[WEP_KEYS][WEP_KEY_LEN]; + u8 level; + u16 flags; +} __attribute__ ((packed)); + +#endif + +#ifdef PLATFORM_WINDOWS + +#pragma pack(1) +struct ieee80211_security { + u16 active_key:2, + enabled:1, + auth_mode:2, + auth_algo:4, + unicast_uses_group:1; + u8 key_sizes[WEP_KEYS]; + u8 keys[WEP_KEYS][WEP_KEY_LEN]; + u8 level; + u16 flags; +} ; +#pragma pack() + +#endif + +/* + + 802.11 data frame from AP + + ,-------------------------------------------------------------------. +Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 | + |------|------|---------|---------|---------|------|---------|------| +Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs | + | | tion | (BSSID) | | | ence | data | | + `-------------------------------------------------------------------' + +Total: 28-2340 bytes + +*/ + +struct ieee80211_header_data { + u16 frame_ctl; + u16 duration_id; + u8 addr1[6]; + u8 addr2[6]; + u8 addr3[6]; + u16 seq_ctrl; +}; + +#define BEACON_PROBE_SSID_ID_POSITION 12 + +/* Management Frame Information Element Types */ +#define MFIE_TYPE_SSID 0 +#define MFIE_TYPE_RATES 1 +#define MFIE_TYPE_FH_SET 2 +#define MFIE_TYPE_DS_SET 3 +#define MFIE_TYPE_CF_SET 4 +#define MFIE_TYPE_TIM 5 +#define MFIE_TYPE_IBSS_SET 6 +#define MFIE_TYPE_CHALLENGE 16 +#define MFIE_TYPE_ERP 42 +#define MFIE_TYPE_RSN 48 +#define MFIE_TYPE_RATES_EX 50 +#define MFIE_TYPE_GENERIC 221 + +#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) + +struct ieee80211_info_element_hdr { + u8 id; + u8 len; +} __attribute__ ((packed)); + +struct ieee80211_info_element { + u8 id; + u8 len; + u8 data[0]; +} __attribute__ ((packed)); +#endif + +#ifdef PLATFORM_WINDOWS + +#pragma pack(1) +struct ieee80211_info_element_hdr { + u8 id; + u8 len; +} ; + +struct ieee80211_info_element { + u8 id; + u8 len; + u8 data[0]; +} ; +#pragma pack() + +#endif + + +/* + * These are the data types that can make up management packets + * + u16 auth_algorithm; + u16 auth_sequence; + u16 beacon_interval; + u16 capability; + u8 current_ap[ETH_ALEN]; + u16 listen_interval; + struct { + u16 association_id:14, reserved:2; + } __attribute__ ((packed)); + u32 time_stamp[2]; + u16 reason; + u16 status; +*/ + +#define IEEE80211_DEFAULT_TX_ESSID "Penguin" +#define IEEE80211_DEFAULT_BASIC_RATE 10 + + +#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) + + +struct ieee80211_authentication { + struct ieee80211_header_data header; + u16 algorithm; + u16 transaction; + u16 status; + //struct ieee80211_info_element_hdr info_element; +} __attribute__ ((packed)); + + +struct ieee80211_probe_response { + struct ieee80211_header_data header; + u32 time_stamp[2]; + u16 beacon_interval; + u16 capability; + struct ieee80211_info_element info_element; +} __attribute__ ((packed)); + +struct ieee80211_probe_request { + struct ieee80211_header_data header; + /*struct ieee80211_info_element info_element;*/ +} __attribute__ ((packed)); + +struct ieee80211_assoc_request_frame { + struct rtw_ieee80211_hdr_3addr header; + u16 capability; + u16 listen_interval; + //u8 current_ap[ETH_ALEN]; + struct ieee80211_info_element_hdr info_element; +} __attribute__ ((packed)); + +struct ieee80211_assoc_response_frame { + struct rtw_ieee80211_hdr_3addr header; + u16 capability; + u16 status; + u16 aid; +// struct ieee80211_info_element info_element; /* supported rates */ +} __attribute__ ((packed)); +#endif + + + +#ifdef PLATFORM_WINDOWS + +#pragma pack(1) + +struct ieee80211_authentication { + struct ieee80211_header_data header; + u16 algorithm; + u16 transaction; + u16 status; + //struct ieee80211_info_element_hdr info_element; +} ; + + +struct ieee80211_probe_response { + struct ieee80211_header_data header; + u32 time_stamp[2]; + u16 beacon_interval; + u16 capability; + struct ieee80211_info_element info_element; +} ; + +struct ieee80211_probe_request { + struct ieee80211_header_data header; + /*struct ieee80211_info_element info_element;*/ +} ; + +struct ieee80211_assoc_request_frame { + struct rtw_ieee80211_hdr_3addr header; + u16 capability; + u16 listen_interval; + //u8 current_ap[ETH_ALEN]; + struct ieee80211_info_element_hdr info_element; +} ; + +struct ieee80211_assoc_response_frame { + struct rtw_ieee80211_hdr_3addr header; + u16 capability; + u16 status; + u16 aid; +// struct ieee80211_info_element info_element; /* supported rates */ +}; + +#pragma pack() + +#endif + +/* SWEEP TABLE ENTRIES NUMBER*/ +#define MAX_SWEEP_TAB_ENTRIES 42 +#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7 +/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs + * only use 8, and then use extended rates for the remaining supported + * rates. Other APs, however, stick all of their supported rates on the + * main rates information element... */ +#define MAX_RATES_LENGTH ((u8)12) +#define MAX_RATES_EX_LENGTH ((u8)16) +#define MAX_NETWORK_COUNT 128 +#define MAX_CHANNEL_NUMBER 161 +#define IEEE80211_SOFTMAC_SCAN_TIME 400 +//(HZ / 2) +#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2) + +#define CRC_LENGTH 4U + +#define MAX_WPA_IE_LEN (256) +#define MAX_WPS_IE_LEN (512) +#define MAX_P2P_IE_LEN (256) +#define MAX_WFD_IE_LEN (128) + +#define NETWORK_EMPTY_ESSID (1<<0) +#define NETWORK_HAS_OFDM (1<<1) +#define NETWORK_HAS_CCK (1<<2) + +#define IEEE80211_DTIM_MBCAST 4 +#define IEEE80211_DTIM_UCAST 2 +#define IEEE80211_DTIM_VALID 1 +#define IEEE80211_DTIM_INVALID 0 + +#define IEEE80211_PS_DISABLED 0 +#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST +#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST +#define IW_ESSID_MAX_SIZE 32 +#define IW_PASSPHRASE_MAX_SIZE 64 +#if 0 +struct ieee80211_network { + /* These entries are used to identify a unique network */ + u8 bssid[ETH_ALEN]; + u8 channel; + /* Ensure null-terminated for any debug msgs */ + u8 ssid[IW_ESSID_MAX_SIZE + 1]; + u8 ssid_len; + u8 rssi; //relative signal strength + u8 sq; //signal quality + + /* These are network statistics */ + //struct ieee80211_rx_stats stats; + u16 capability; + u16 aid; + u8 rates[MAX_RATES_LENGTH]; + u8 rates_len; + u8 rates_ex[MAX_RATES_EX_LENGTH]; + u8 rates_ex_len; + + u8 edca_parmsets[18]; + + u8 mode; + u8 flags; + u8 time_stamp[8]; + u16 beacon_interval; + u16 listen_interval; + u16 atim_window; + u8 wpa_ie[MAX_WPA_IE_LEN]; + size_t wpa_ie_len; + u8 rsn_ie[MAX_WPA_IE_LEN]; + size_t rsn_ie_len; + u8 country[6]; + u8 dtim_period; + u8 dtim_data; + u8 power_constraint; + u8 qosinfo; + u8 qbssload[5]; + u8 network_type; + int join_res; + unsigned long last_scanned; +}; +#endif +/* +join_res: +-1: authentication fail +-2: association fail +> 0: TID +*/ + +#ifndef PLATFORM_FREEBSD //Baron BSD has already defined + +enum ieee80211_state { + + /* the card is not linked at all */ + IEEE80211_NOLINK = 0, + + /* IEEE80211_ASSOCIATING* are for BSS client mode + * the driver shall not perform RX filtering unless + * the state is LINKED. + * The driver shall just check for the state LINKED and + * defaults to NOLINK for ALL the other states (including + * LINKED_SCANNING) + */ + + /* the association procedure will start (wq scheduling)*/ + IEEE80211_ASSOCIATING, + IEEE80211_ASSOCIATING_RETRY, + + /* the association procedure is sending AUTH request*/ + IEEE80211_ASSOCIATING_AUTHENTICATING, + + /* the association procedure has successfully authentcated + * and is sending association request + */ + IEEE80211_ASSOCIATING_AUTHENTICATED, + + /* the link is ok. the card associated to a BSS or linked + * to a ibss cell or acting as an AP and creating the bss + */ + IEEE80211_LINKED, + + /* same as LINKED, but the driver shall apply RX filter + * rules as we are in NO_LINK mode. As the card is still + * logically linked, but it is doing a syncro site survey + * then it will be back to LINKED state. + */ + IEEE80211_LINKED_SCANNING, + +}; +#endif //PLATFORM_FREEBSD + +#define DEFAULT_MAX_SCAN_AGE (15 * HZ) +#define DEFAULT_FTS 2346 +#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" +#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] + +#ifdef PLATFORM_FREEBSD //Baron change func to macro +#define is_multicast_mac_addr(Addr) ((((Addr[0]) & 0x01) == 0x01) && ((Addr[0]) != 0xff)) +#define is_broadcast_mac_addr(Addr) ((((Addr[0]) & 0xff) == 0xff) && (((Addr[1]) & 0xff) == 0xff) && \ +(((Addr[2]) & 0xff) == 0xff) && (((Addr[3]) & 0xff) == 0xff) && (((Addr[4]) & 0xff) == 0xff) && \ +(((Addr[5]) & 0xff) == 0xff)) +#else +#if 0 +extern __inline int is_multicast_mac_addr(const u8 *addr) +{ + return ((addr[0] != 0xff) && (0x01 & addr[0])); +} + +extern __inline int is_broadcast_mac_addr(const u8 *addr) +{ + return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \ + (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff)); +} +#endif +#endif //PLATFORM_FREEBSD + +#define CFG_IEEE80211_RESERVE_FCS (1<<0) +#define CFG_IEEE80211_COMPUTE_FCS (1<<1) + +#define MAXTID 16 + +#define IEEE_A (1<<0) +#define IEEE_B (1<<1) +#define IEEE_G (1<<2) +#define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G) + +//Baron move to ieee80211.c +int ieee80211_is_empty_essid(const char *essid, int essid_len); +int ieee80211_get_hdrlen(u16 fc); + +#if 0 +/* Action frame categories (IEEE 802.11-2007, 7.3.1.11, Table 7-24) */ +#define WLAN_ACTION_SPECTRUM_MGMT 0 +#define WLAN_ACTION_QOS 1 +#define WLAN_ACTION_DLS 2 +#define WLAN_ACTION_BLOCK_ACK 3 +#define WLAN_ACTION_RADIO_MEASUREMENT 5 +#define WLAN_ACTION_FT 6 +#define WLAN_ACTION_SA_QUERY 8 +#define WLAN_ACTION_WMM 17 +#endif + + +/* Action category code */ +enum rtw_ieee80211_category { + RTW_WLAN_CATEGORY_SPECTRUM_MGMT = 0, + RTW_WLAN_CATEGORY_QOS = 1, + RTW_WLAN_CATEGORY_DLS = 2, + RTW_WLAN_CATEGORY_BACK = 3, + RTW_WLAN_CATEGORY_PUBLIC = 4, //IEEE 802.11 public action frames + RTW_WLAN_CATEGORY_RADIO_MEASUREMENT = 5, + RTW_WLAN_CATEGORY_FT = 6, + RTW_WLAN_CATEGORY_HT = 7, + RTW_WLAN_CATEGORY_SA_QUERY = 8, + RTW_WLAN_CATEGORY_TDLS = 12, + RTW_WLAN_CATEGORY_WMM = 17, + RTW_WLAN_CATEGORY_P2P = 0x7f,//P2P action frames +}; + +/* SPECTRUM_MGMT action code */ +enum rtw_ieee80211_spectrum_mgmt_actioncode { + RTW_WLAN_ACTION_SPCT_MSR_REQ = 0, + RTW_WLAN_ACTION_SPCT_MSR_RPRT = 1, + RTW_WLAN_ACTION_SPCT_TPC_REQ = 2, + RTW_WLAN_ACTION_SPCT_TPC_RPRT = 3, + RTW_WLAN_ACTION_SPCT_CHL_SWITCH = 4, + RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, +}; + +enum _PUBLIC_ACTION{ + ACT_PUBLIC_BSSCOEXIST = 0, // 20/40 BSS Coexistence + ACT_PUBLIC_DSE_ENABLE = 1, + ACT_PUBLIC_DSE_DEENABLE = 2, + ACT_PUBLIC_DSE_REG_LOCATION = 3, + ACT_PUBLIC_EXT_CHL_SWITCH = 4, + ACT_PUBLIC_DSE_MSR_REQ = 5, + ACT_PUBLIC_DSE_MSR_RPRT = 6, + ACT_PUBLIC_MP = 7, // Measurement Pilot + ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8, + ACT_PUBLIC_VENDOR = 9, // for WIFI_DIRECT + ACT_PUBLIC_GAS_INITIAL_REQ = 10, + ACT_PUBLIC_GAS_INITIAL_RSP = 11, + ACT_PUBLIC_GAS_COMEBACK_REQ = 12, + ACT_PUBLIC_GAS_COMEBACK_RSP = 13, + ACT_PUBLIC_TDLS_DISCOVERY_RSP = 14, + ACT_PUBLIC_LOCATION_TRACK = 15, + ACT_PUBLIC_MAX +}; + +#ifdef CONFIG_TDLS +enum TDLS_ACTION_FIELD{ + TDLS_SETUP_REQUEST = 0, + TDLS_SETUP_RESPONSE = 1, + TDLS_SETUP_CONFIRM = 2, + TDLS_TEARDOWN = 3, + TDLS_PEER_TRAFFIC_INDICATION = 4, + TDLS_CHANNEL_SWITCH_REQUEST = 5, + TDLS_CHANNEL_SWITCH_RESPONSE = 6, + TDLS_PEER_PSM_REQUEST = 7, + TDLS_PEER_PSM_RESPONSE = 8, + TDLS_PEER_TRAFFIC_RESPONSE = 9, + TDLS_DISCOVERY_REQUEST = 10, + TDLS_DISCOVERY_RESPONSE = 14, //it's used in public action frame +}; + +#define TUNNELED_PROBE_REQ 15 +#define TUNNELED_PROBE_RSP 16 +#endif //CONFIG_TDLS + +/* BACK action code */ +enum rtw_ieee80211_back_actioncode { + RTW_WLAN_ACTION_ADDBA_REQ = 0, + RTW_WLAN_ACTION_ADDBA_RESP = 1, + RTW_WLAN_ACTION_DELBA = 2, +}; + +/* HT features action code */ +enum rtw_ieee80211_ht_actioncode { + RTW_WLAN_ACTION_NOTIFY_CH_WIDTH = 0, + RTW_WLAN_ACTION_SM_PS = 1, + RTW_WLAN_ACTION_PSPM = 2, + RTW_WLAN_ACTION_PCO_PHASE = 3, + RTW_WLAN_ACTION_MIMO_CSI_MX = 4, + RTW_WLAN_ACTION_MIMO_NONCP_BF = 5, + RTW_WLAN_ACTION_MIMP_CP_BF = 6, + RTW_WLAN_ACTION_ASEL_INDICATES_FB = 7, + RTW_WLAN_ACTION_HI_INFO_EXCHG = 8, +}; + +/* BACK (block-ack) parties */ +enum rtw_ieee80211_back_parties { + RTW_WLAN_BACK_RECIPIENT = 0, + RTW_WLAN_BACK_INITIATOR = 1, + RTW_WLAN_BACK_TIMER = 2, +}; + + +#define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs) + * 00:50:F2 */ +#ifndef PLATFORM_FREEBSD //Baron BSD has defined +#define WME_OUI_TYPE 2 +#endif //PLATFORM_FREEBSD +#define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0 +#define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1 +#define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2 +#define WME_VERSION 1 + +#define WME_ACTION_CODE_SETUP_REQUEST 0 +#define WME_ACTION_CODE_SETUP_RESPONSE 1 +#define WME_ACTION_CODE_TEARDOWN 2 + +#define WME_SETUP_RESPONSE_STATUS_ADMISSION_ACCEPTED 0 +#define WME_SETUP_RESPONSE_STATUS_INVALID_PARAMETERS 1 +#define WME_SETUP_RESPONSE_STATUS_REFUSED 3 + +#define WME_TSPEC_DIRECTION_UPLINK 0 +#define WME_TSPEC_DIRECTION_DOWNLINK 1 +#define WME_TSPEC_DIRECTION_BI_DIRECTIONAL 3 + + +#define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */ + +#define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */ + +u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen); +int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len); + +int rtw_get_wapi_ie(u8 *in_ie,uint in_len,u8 *wapi_ie,u16 *wapi_len); + +u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen); + +void dump_ies(u8 *buf, u32 buf_len); +void dump_wps_ie(u8 *ie, u32 ie_len); + +#ifdef CONFIG_P2P_NEW +u8 *rtw_get_p2p_ie(u8 *in_ie, uint in_len, u8 *p2p_ie, uint *p2p_ielen); +u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_attr, u32 *len_attr); +#endif //CONFIG_P2P +#ifdef CONFIG_P2P +void dump_p2p_ie(u8 *ie, u32 ie_len); +u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_content, uint *len_content); +u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr); +void rtw_WLAN_BSSID_EX_remove_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id); +#endif + +#ifdef CONFIG_WFD +int rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen); +int rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id ,u8 *attr_content, uint *attr_contentlen); +#endif // CONFIG_WFD + +//struct registry_priv; +//int rtw_generate_ie(struct registry_priv *pregistrypriv); + +void rtw_get_bcn_info(struct wlan_network *pnetwork); + +void rtw_macaddr_cfg(u8 *mac_addr); + +u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI_20, u8 short_GI_40, unsigned char * MCS_rate); +#endif /* __IEEE80211_H */ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/if_ether.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/if_ether.h new file mode 100644 index 0000000..7e06597 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/if_ether.h @@ -0,0 +1,115 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef _LINUX_IF_ETHER_H +#define _LINUX_IF_ETHER_H + +/* + * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble + * and FCS/CRC (frame check sequence). + */ + +#define ETH_ALEN 6 /* Octets in one ethernet addr */ +#define ETH_HLEN 14 /* Total octets in header. */ +#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ +#define ETH_DATA_LEN 1500 /* Max. octets in payload */ +#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */ + +/* + * These are the defined Ethernet Protocol ID's. + */ + +#define ETH_P_LOOP 0x0060 /* Ethernet Loopback packet */ +#define ETH_P_PUP 0x0200 /* Xerox PUP packet */ +#define ETH_P_PUPAT 0x0201 /* Xerox PUP Addr Trans packet */ +#define ETH_P_IP 0x0800 /* Internet Protocol packet */ +#define ETH_P_X25 0x0805 /* CCITT X.25 */ +#define ETH_P_ARP 0x0806 /* Address Resolution packet */ +#define ETH_P_BPQ 0x08FF /* G8BPQ AX.25 Ethernet Packet [ NOT AN OFFICIALLY REGISTERED ID ] */ +#define ETH_P_IEEEPUP 0x0a00 /* Xerox IEEE802.3 PUP packet */ +#define ETH_P_IEEEPUPAT 0x0a01 /* Xerox IEEE802.3 PUP Addr Trans packet */ +#define ETH_P_DEC 0x6000 /* DEC Assigned proto */ +#define ETH_P_DNA_DL 0x6001 /* DEC DNA Dump/Load */ +#define ETH_P_DNA_RC 0x6002 /* DEC DNA Remote Console */ +#define ETH_P_DNA_RT 0x6003 /* DEC DNA Routing */ +#define ETH_P_LAT 0x6004 /* DEC LAT */ +#define ETH_P_DIAG 0x6005 /* DEC Diagnostics */ +#define ETH_P_CUST 0x6006 /* DEC Customer use */ +#define ETH_P_SCA 0x6007 /* DEC Systems Comms Arch */ +#define ETH_P_RARP 0x8035 /* Reverse Addr Res packet */ +#define ETH_P_ATALK 0x809B /* Appletalk DDP */ +#define ETH_P_AARP 0x80F3 /* Appletalk AARP */ +#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ +#define ETH_P_IPX 0x8137 /* IPX over DIX */ +#define ETH_P_IPV6 0x86DD /* IPv6 over bluebook */ +#define ETH_P_PPP_DISC 0x8863 /* PPPoE discovery messages */ +#define ETH_P_PPP_SES 0x8864 /* PPPoE session messages */ +#define ETH_P_ATMMPOA 0x884c /* MultiProtocol Over ATM */ +#define ETH_P_ATMFATE 0x8884 /* Frame-based ATM Transport + * over Ethernet + */ + +/* + * Non DIX types. Won't clash for 1500 types. + */ + +#define ETH_P_802_3 0x0001 /* Dummy type for 802.3 frames */ +#define ETH_P_AX25 0x0002 /* Dummy protocol id for AX.25 */ +#define ETH_P_ALL 0x0003 /* Every packet (be careful!!!) */ +#define ETH_P_802_2 0x0004 /* 802.2 frames */ +#define ETH_P_SNAP 0x0005 /* Internal only */ +#define ETH_P_DDCMP 0x0006 /* DEC DDCMP: Internal only */ +#define ETH_P_WAN_PPP 0x0007 /* Dummy type for WAN PPP frames*/ +#define ETH_P_PPP_MP 0x0008 /* Dummy type for PPP MP frames */ +#define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */ +#define ETH_P_PPPTALK 0x0010 /* Dummy type for Atalk over PPP*/ +#define ETH_P_TR_802_2 0x0011 /* 802.2 frames */ +#define ETH_P_MOBITEX 0x0015 /* Mobitex (kaz@cafe.net) */ +#define ETH_P_CONTROL 0x0016 /* Card specific control frames */ +#define ETH_P_IRDA 0x0017 /* Linux-IrDA */ +#define ETH_P_ECONET 0x0018 /* Acorn Econet */ + +/* + * This is an Ethernet frame header. + */ +//CONFIG_MEMORY_ACCESS_ALIGNED for 4byte aligned,ethdhr size is 16,leading error in wlanhdr_to_ethdr +RTW_PACK_STRUCT_BEGIN +struct ethhdr +{ + unsigned char h_dest[ETH_ALEN]; /* destination eth addr */ + unsigned char h_source[ETH_ALEN]; /* source ether addr */ + unsigned short h_proto; /* packet type ID field */ +} RTW_PACK_STRUCT_STRUCT; +RTW_PACK_STRUCT_END + +struct _vlan { + unsigned short h_vlan_TCI; // Encapsulates priority and VLAN ID + unsigned short h_vlan_encapsulated_proto; +}; + + + +#define get_vlan_id(pvlan) ((_htons((unsigned short )pvlan->h_vlan_TCI)) & 0xfff) +#define get_vlan_priority(pvlan) ((_htons((unsigned short )pvlan->h_vlan_TCI))>>13) +#define get_vlan_encap_proto(pvlan) (_htons((unsigned short )pvlan->h_vlan_encapsulated_proto)) + + +#endif /* _LINUX_IF_ETHER_H */ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/ip.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/ip.h new file mode 100644 index 0000000..3911608 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/ip.h @@ -0,0 +1,142 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_IP_H +#define _LINUX_IP_H +#include + +/* SOL_IP socket options */ +#ifndef IPTOS_TOS_MASK +#define IPTOS_TOS_MASK 0x1E +#define IPTOS_TOS(tos) ((tos)&IPTOS_TOS_MASK) +#define IPTOS_LOWDELAY 0x10 +#define IPTOS_THROUGHPUT 0x08 +#define IPTOS_RELIABILITY 0x04 +#define IPTOS_MINCOST 0x02 + +#define IPTOS_PREC_MASK 0xE0 +#define IPTOS_PREC(tos) ((tos)&IPTOS_PREC_MASK) +#define IPTOS_PREC_NETCONTROL 0xe0 +#define IPTOS_PREC_INTERNETCONTROL 0xc0 +#define IPTOS_PREC_CRITIC_ECP 0xa0 +#define IPTOS_PREC_FLASHOVERRIDE 0x80 +#define IPTOS_PREC_FLASH 0x60 +#define IPTOS_PREC_IMMEDIATE 0x40 +#define IPTOS_PREC_PRIORITY 0x20 +#define IPTOS_PREC_ROUTINE 0x00 +#endif + +/* IP options */ +#define IPOPT_COPY 0x80 +#define IPOPT_CLASS_MASK 0x60 +#define IPOPT_NUMBER_MASK 0x1f + +#define IPOPT_COPIED(o) ((o)&IPOPT_COPY) +#define IPOPT_CLASS(o) ((o)&IPOPT_CLASS_MASK) +#define IPOPT_NUMBER(o) ((o)&IPOPT_NUMBER_MASK) + +#define IPOPT_CONTROL 0x00 +#define IPOPT_RESERVED1 0x20 +#define IPOPT_MEASUREMENT 0x40 +#define IPOPT_RESERVED2 0x60 + +#define IPOPT_END (0 |IPOPT_CONTROL) +#define IPOPT_NOOP (1 |IPOPT_CONTROL) +#define IPOPT_SEC (2 |IPOPT_CONTROL|IPOPT_COPY) +#define IPOPT_LSRR (3 |IPOPT_CONTROL|IPOPT_COPY) +#define IPOPT_TIMESTAMP (4 |IPOPT_MEASUREMENT) +#define IPOPT_RR (7 |IPOPT_CONTROL) +#define IPOPT_SID (8 |IPOPT_CONTROL|IPOPT_COPY) +#define IPOPT_SSRR (9 |IPOPT_CONTROL|IPOPT_COPY) +#define IPOPT_RA (20|IPOPT_CONTROL|IPOPT_COPY) + +#define IPVERSION 4 +#define MAXTTL 255 +#define IPDEFTTL 64 + +/* struct timestamp, struct route and MAX_ROUTES are removed. + + REASONS: it is clear that nobody used them because: + - MAX_ROUTES value was wrong. + - "struct route" was wrong. + - "struct timestamp" had fatally misaligned bitfields and was completely unusable. + */ + +#define IPOPT_OPTVAL 0 +#define IPOPT_OLEN 1 +#define IPOPT_OFFSET 2 +#define IPOPT_MINOFF 4 +#define MAX_IPOPTLEN 40 +#define IPOPT_NOP IPOPT_NOOP +#define IPOPT_EOL IPOPT_END +#define IPOPT_TS IPOPT_TIMESTAMP + +#define IPOPT_TS_TSONLY 0 /* timestamps only */ +#define IPOPT_TS_TSANDADDR 1 /* timestamps and addresses */ +#define IPOPT_TS_PRESPEC 3 /* specified modules only */ + +#ifdef PLATFORM_LINUX + +struct ip_options { + __u32 faddr; /* Saved first hop address */ + unsigned char optlen; + unsigned char srr; + unsigned char rr; + unsigned char ts; + unsigned char is_setbyuser:1, /* Set by setsockopt? */ + is_data:1, /* Options in __data, rather than skb */ + is_strictroute:1, /* Strict source route */ + srr_is_hit:1, /* Packet destination addr was our one */ + is_changed:1, /* IP checksum more not valid */ + rr_needaddr:1, /* Need to record addr of outgoing dev */ + ts_needtime:1, /* Need to record timestamp */ + ts_needaddr:1; /* Need to record addr of outgoing dev */ + unsigned char router_alert; + unsigned char __pad1; + unsigned char __pad2; + unsigned char __data[0]; +}; + +#define optlength(opt) (sizeof(struct ip_options) + opt->optlen) +#endif + +struct iphdr { +#if defined(__LITTLE_ENDIAN_BITFIELD) + __u8 ihl:4, + version:4; +#elif defined (__BIG_ENDIAN_BITFIELD) + __u8 version:4, + ihl:4; +#else +#error "Please fix " +#endif + __u8 tos; + __u16 tot_len; + __u16 id; + __u16 frag_off; + __u8 ttl; + __u8 protocol; + __u16 check; + __u32 saddr; + __u32 daddr; + /*The options start here. */ +}; + +#endif /* _LINUX_IP_H */ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/lxbus_hal.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/lxbus_hal.h new file mode 100644 index 0000000..74a161d --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/lxbus_hal.h @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __LXBUS_HAL_H__ +#define __LXBUS_HAL_H__ + +#endif //__LXBUS_HAL_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/lxbus_ops.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/lxbus_ops.h new file mode 100644 index 0000000..aca3698 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/lxbus_ops.h @@ -0,0 +1,80 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __LXBUS_OPS_H__ +#define __LXBUS_OPS_H__ + + +#if defined(CONFIG_RTL8195A) +//extern u32 TxbdRxbdInitRtl8195a(PADAPTER Adapter); +//extern u32 TxbdRxbdResetRtl8195a(PADAPTER Adapter); + +extern VOID InitLxDmaRtl8195a(_adapter * Adapter); +extern u32 rtl8195a_init_desc_ring(_adapter * padapter); +extern u32 rtl8195a_free_desc_ring(_adapter * padapter); +extern void rtl8195a_reset_desc_ring(_adapter * padapter); +extern void EnableDMA8195a(PADAPTER padapter); +extern void EnableInterrupt8195a(PADAPTER padapter); +extern void DisableDMA8195a(PADAPTER padapter); +extern void DisableInterrupt8195a(PADAPTER padapter); +extern s32 InterruptHandle8195a(PADAPTER Adapter); +extern void lxbus_set_intf_ops(struct _io_ops *pops); +extern void rtl8195a_xmit_tasklet(void *priv); +extern void rtl8195a_recv_tasklet(void *priv); +extern void rtl8195a_prepare_bcn_tasklet(void *priv); +extern void rtl8195a_tx_int_handler(_adapter *padapter); +extern void InitInterrupt8195a(PADAPTER padapter); +extern VOID UpdateInterruptMask8195a(PADAPTER Adapter, u32 *pAddMSRB, u32 *pRemoveMSR); + +#ifdef CONFIG_WOWLAN +extern void ClearInterrupt8195a(PADAPTER padapter); +#endif + +extern void ClearWlPmcInterrupt8195a(PADAPTER padapter); +extern BOOLEAN InterruptRecognized8195a(PADAPTER Adapter); +#elif defined(CONFIG_RTL8711B) + +extern u32 rtl8711b_init_desc_ring(_adapter * padapter); +extern u32 rtl8711b_free_desc_ring(_adapter * padapter); +extern void rtl8711b_reset_desc_ring(_adapter * padapter); +extern void EnableDMA8711b(PADAPTER padapter); +extern void EnableInterrupt8711b(PADAPTER padapter); +extern void DisableDMA8711b(PADAPTER padapter); +extern void DisableInterrupt8711b(PADAPTER padapter); +extern s32 InterruptHandle8711b(PADAPTER Adapter); +extern void lxbus_set_intf_ops(struct _io_ops *pops); +extern void rtl8711b_xmit_tasklet(void *priv); +extern void rtl8711b_recv_tasklet(void *priv); +extern void rtl8711b_prepare_bcn_tasklet(void *priv); +extern void rtl8711b_tx_int_handler(_adapter *padapter); +extern void InitInterrupt8711b(PADAPTER padapter); +extern VOID UpdateInterruptMask8711b(PADAPTER Adapter, u32 *pAddMSRB, u32 *pRemoveMSR); + +#ifdef CONFIG_WOWLAN +extern void ClearInterrupt8711b(PADAPTER padapter); +extern void DisableInterruptButCpwm28711b(PADAPTER padapter); +#endif + +extern void ClearWlPmcInterrupt8711b(PADAPTER padapter); +extern BOOLEAN InterruptRecognized8711b(PADAPTER Adapter); +#endif + + +#endif // !__LXBUS_OPS_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/lxbus_osintf.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/lxbus_osintf.h new file mode 100644 index 0000000..0c80793 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/lxbus_osintf.h @@ -0,0 +1,29 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __LXBUS_OSINTF_H +#define __LXBUS_OSINTF_H + + +//void rtw_pci_disable_aspm(_adapter *padapter); +//void rtw_pci_enable_aspm(_adapter *padapter); +//void PlatformClearPciPMEStatus(PADAPTER Adapter); + +#endif //__LXBUS_OSINTF_H + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/pack_begin.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/pack_begin.h new file mode 100644 index 0000000..7f1de7c --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/pack_begin.h @@ -0,0 +1,33 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ****************************************************************************** + * + * Define the start point of packed structure + * + ******************************************************************************/ + +#if defined(__IAR_SYSTEMS_ICC__) +#pragma pack(1) +#endif + +#if defined(PLATFORM_WINDOWS) +#pragma pack(push) +#pragma pack(1) +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/pack_end.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/pack_end.h new file mode 100644 index 0000000..e34640c --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/pack_end.h @@ -0,0 +1,33 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ****************************************************************************** + * + * Define the end point of packed structure + * + ******************************************************************************/ + +#if defined(__IAR_SYSTEMS_ICC__) +#pragma pack() +#endif + +#if defined(PLATFORM_WINDOWS) +#pragma pack(pop) +#endif + + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_aes.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_aes.h index 55fd9cc..c89c6cc 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_aes.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_aes.h @@ -1,10 +1,25 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ****************************************************************************** * * This is ROM code section. * - * ******************************************************************************/ #ifndef ROM_AES_H #define ROM_AES_H diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_arc4.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_arc4.h new file mode 100644 index 0000000..1eb2391 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_arc4.h @@ -0,0 +1,39 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ****************************************************************************** + * + * This is ROM code section. + * + ******************************************************************************/ +#ifndef ROM_ARC4_H +#define ROM_ARC4_H + +struct arc4context +{ + u32 x; + u32 y; + u8 state[256]; +}; + +u32 crc32_get(u8 *buf, sint len); +void rt_arc4_init(struct arc4context *parc4ctx, u8 * key,u32 key_len); +void rt_arc4_crypt( struct arc4context *parc4ctx, u8 * dest, u8 * src, u32 len); + + +#endif //ROM_ARC4_H diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_ieee80211.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_ieee80211.h new file mode 100644 index 0000000..064729d --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_ieee80211.h @@ -0,0 +1,127 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ROM_IEEE80211_H +#define __ROM_IEEE80211_H + +extern const u8 RTW_WPA_OUI_TYPE[] ; +extern const u8 WPA_CIPHER_SUITE_NONE[]; +extern const u8 WPA_CIPHER_SUITE_WEP40[]; +extern const u8 WPA_CIPHER_SUITE_TKIP[]; +extern const u8 WPA_CIPHER_SUITE_CCMP[]; +extern const u8 WPA_CIPHER_SUITE_WEP104[]; +extern const u16 RSN_VERSION_BSD; +extern const u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[]; +extern const u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[]; +extern const u8 RSN_CIPHER_SUITE_NONE[]; +extern const u8 RSN_CIPHER_SUITE_WEP40[]; +extern const u8 RSN_CIPHER_SUITE_TKIP[]; +extern const u8 RSN_CIPHER_SUITE_CCMP[]; +extern const u8 RSN_CIPHER_SUITE_WEP104[]; + +/* Parsed Information Elements */ +struct rtw_ieee802_11_elems { + u8 *ssid; + u8 ssid_len; + u8 *supp_rates; + u8 supp_rates_len; + u8 *fh_params; + u8 fh_params_len; + u8 *ds_params; + u8 ds_params_len; + u8 *cf_params; + u8 cf_params_len; + u8 *tim; + u8 tim_len; + u8 *ibss_params; + u8 ibss_params_len; + u8 *challenge; + u8 challenge_len; + u8 *erp_info; + u8 erp_info_len; + u8 *ext_supp_rates; + u8 ext_supp_rates_len; + u8 *wpa_ie; + u8 wpa_ie_len; + u8 *rsn_ie; + u8 rsn_ie_len; + u8 *wme; + u8 wme_len; + u8 *wme_tspec; + u8 wme_tspec_len; + u8 *wps_ie; + u8 wps_ie_len; + u8 *power_cap; + u8 power_cap_len; + u8 *supp_channels; + u8 supp_channels_len; + u8 *mdie; + u8 mdie_len; + u8 *ftie; + u8 ftie_len; + u8 *timeout_int; + u8 timeout_int_len; + u8 *ht_capabilities; + u8 ht_capabilities_len; + u8 *ht_operation; + u8 ht_operation_len; + u8 *vendor_ht_cap; + u8 vendor_ht_cap_len; +}; + +typedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes; + +ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, + struct rtw_ieee802_11_elems *elems, + int show_errors); + +u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen); +u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, u8 *source, uint *frlen); +u8 *rtw_get_ie(u8*pbuf, sint index, u32 *len, sint limit); + +void rtw_set_supported_rate(u8* SupportedRates, uint mode) ; + +unsigned char *rtw_get_wpa_ie(unsigned char *pie, u32 *wpa_ie_len, int limit); +unsigned char *rtw_get_wpa2_ie(unsigned char *pie, u32 *rsn_ie_len, int limit); +int rtw_get_wpa_cipher_suite(u8 *s); +int rtw_get_wpa2_cipher_suite(u8 *s); + +int rtw_parse_wpa_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); +int rtw_parse_wpa2_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); + +int rtw_get_sec_ie(u8 *in_ie,uint in_len,u8 *rsn_ie,u16 *rsn_len,u8 *wpa_ie,u16 *wpa_len); + +u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen); +u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_attr, u32 *len_attr); +u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_content, uint *len_content); + +uint rtw_get_rateset_len(u8 *rateset); + +int rtw_get_bit_value_from_ieee_value(u8 val); + +uint rtw_is_cckrates_included(u8 *rate); + +uint rtw_is_cckratesonly_included(u8 *rate); + +int rtw_check_network_type(unsigned char *rate, int ratelen, int channel); + +u8 key_2char2num(u8 hch, u8 lch); + +#endif /* __ROM_IEEE80211_H */ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_md5.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_md5.h new file mode 100644 index 0000000..fb6e9d2 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_md5.h @@ -0,0 +1,45 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ****************************************************************************** + * + * This is ROM code section. + * + ******************************************************************************/ + +#ifndef ROM_MD5_H +#define ROM_MD5_H + +#if PSK_SUPPORT_TKIP + +/* MD5 context. */ +typedef struct { + u32 state[4]; /* state (ABCD) */ + u32 count[2]; /* number of bits, modulo 2^64 (lsb first) */ + u8 buffer[64]; /* input buffer */ +} md5_ctx; + +void rt_md5_init(md5_ctx *context); +void rt_md5_append(md5_ctx *context, u8 *input, u32 inputLen); +void rt_md5_final(u8 digest[16], md5_ctx *context); +void rt_md5_hmac(unsigned char *text, int text_len, unsigned char *key, + int key_len, void * digest); + + +#endif //#if PSK_SUPPORT_TKIP +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rc4.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rc4.h new file mode 100644 index 0000000..5c40252 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rc4.h @@ -0,0 +1,89 @@ +/* crypto/rc4/rc4.h */ +/* Copyright (C) 1995-1997 Eric Young (eay@cryptsoft.com) + * All rights reserved. + * + * This package is an SSL implementation written + * by Eric Young (eay@cryptsoft.com). + * The implementation was written so as to conform with Netscapes SSL. + * + * This library is free for commercial and non-commercial use as long as + * the following conditions are aheared to. The following conditions + * apply to all code found in this distribution, be it the RC4, RSA, + * lhash, DES, etc., code; not just the SSL code. The SSL documentation + * included with this distribution is covered by the same copyright terms + * except that the holder is Tim Hudson (tjh@cryptsoft.com). + * + * Copyright remains Eric Young's, and as such any Copyright notices in + * the code are not to be removed. + * If this package is used in a product, Eric Young should be given attribution + * as the author of the parts of the library used. + * This can be in the form of a textual message at program startup or + * in documentation (online or textual) provided with the package. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * "This product includes cryptographic software written by + * Eric Young (eay@cryptsoft.com)" + * The word 'cryptographic' can be left out if the rouines from the library + * being used are not cryptographic related :-). + * 4. If you include any Windows specific code (or a derivative thereof) from + * the apps directory (application code) you must include an acknowledgement: + * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)" + * + * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * The licence and distribution terms for any publically available version or + * derivative of this code cannot be changed. i.e. this code cannot simply be + * copied and put under another distribution licence + * [including the GNU Public Licence.] + */ + +#ifndef HEADER_RC4_H +#define HEADER_RC4_H + +#ifdef OPENSSL_NO_RC4 +#error RC4 is disabled. +#endif + +//#include /* RC4_INT */ +#define RC4_INT unsigned int + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct rc4_key_st + { + RC4_INT x,y; + RC4_INT data[256]; + } RC4_KEY; + + +//const char *RC4_options(void); +void RC4_set_key(RC4_KEY *key, int len, const unsigned char *data); +void RC4(RC4_KEY *key, unsigned long len, const unsigned char *indata, + unsigned char *outdata); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_message.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_message.h new file mode 100644 index 0000000..81115ae --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_message.h @@ -0,0 +1,48 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _ROM_RTW_MESSAGE_ +#define _ROM_RTW_MESSAGE_ + +#include + +typedef enum { +#define ROM_E_RTW_MSGPOOL(name,str) ROM_E_RTW_MSGP_##name, +#include "rom_rtw_message_e.h" + ROM_E_RTW_MSGP_MAX +} rom_e_rtw_msgp_t; + +#if ROM_E_RTW_MSG +extern const char *rom_e_rtw_msgp_str_[]; +#define rom_e_rtw_msg_printf(name, fmt, args...) printf((char*)rom_e_rtw_msgp_str_[ROM_E_RTW_MSGP_##name], ## args) +#define rom_e_rtw_msg_871X_LEVEL(name, level, fmt, args...) \ + do {\ + printf("\n\r");\ + printf((char*)rom_e_rtw_msgp_str_[ROM_E_RTW_MSGP_##name], ## args);\ + }while(0) +#else +#define rom_e_rtw_msg_printf(name, fmt, args...) printf(fmt, ## args) +#define rom_e_rtw_msg_871X_LEVEL(name, level, fmt, args...) \ + do {\ + printf("\n\r");\ + printf(DRIVER_PREFIX ##fmt, ## args);\ + }while(0) +#endif //ROM_E_RTW_MSG + +#endif //_ROM_RTW_MESSAGE_ diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_message_e.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_message_e.h new file mode 100644 index 0000000..8740be2 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_message_e.h @@ -0,0 +1,174 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +// Debug message +// DBG_PWR_INDEX +ROM_E_RTW_MSGPOOL(PWR_INDEX_1, "BandWidth = %d, Rate = %d, Channel = %d\n\r") +ROM_E_RTW_MSGPOOL(PWR_INDEX_2, "Base = %d, DiffByRate = %d, limit = %d, DiffByTrack = %d, Tx Power = %d\n\n\r") +// DBG_RX_INFO +ROM_E_RTW_MSGPOOL(RX_INFO_1, "============ Rx Info dump ===================\n") +ROM_E_RTW_MSGPOOL(RX_INFO_2, "bLinked = %d, RSSI_Min = %d(%%), CurrentIGI = 0x%x\n") +ROM_E_RTW_MSGPOOL(RX_INFO_3, "Cnt_Cck_fail = %d, Cnt_Ofdm_fail = %d, Total False Alarm = %d\n") +ROM_E_RTW_MSGPOOL(RX_INFO_4, "RxRate = 0x%x, RSSI_A = %d(%%), RSSI_B = %d(%%)\n") +// DBG_TX_RATE +ROM_E_RTW_MSGPOOL(TX_RATE_1, "Rate: 0x%x\n\r") +ROM_E_RTW_MSGPOOL(TX_RATE_2, "%s(): mac_id=%d raid=0x%x bw=%d mask=0x%x init_rate=0x%x\n") +// DBG_DM_RA +ROM_E_RTW_MSGPOOL(DM_RA_1, "==> ReadRateMask = 0x%x RAMASK[%d] = 0x%x\n") +ROM_E_RTW_MSGPOOL(DM_RA_2, "==> TMP_rate = %x highest_rate = 0x%02X, lowest_rate = 0x%02X\n") +ROM_E_RTW_MSGPOOL(DM_RA_3, "==> MacID = %d rateid = 0x%x sgi = %d bw_idx = %d\n\r") +ROM_E_RTW_MSGPOOL(DM_RA_4, "%s(): mac_id=%d raid=0x%x bw=%d mask=0x%x\r\n") +// DBG_DM_DIG +ROM_E_RTW_MSGPOOL(DM_DIG_1, "CurrentIGI(0x%02x)\n\n") +// DBG_PWR_TRACKING +ROM_E_RTW_MSGPOOL(PWR_TRACKING_1, "Thermal = 0x%02X\r\n") +ROM_E_RTW_MSGPOOL(PWR_TRACKING_2, "delta = %d, AVG Thermal = 0x%02X, EFUSE = 0x%02X, PackageType = 0x%02X\r\n") +ROM_E_RTW_MSGPOOL(PWR_TRACKING_3, "Channel = %d, CCK PwrBase = 0x%02X, HT40M PwrBase = 0x%02X, OFDMdiff = %d, 20Mdiff = %d \n\r") +ROM_E_RTW_MSGPOOL(PWR_TRACKING_4, "Remnant_CCKSwingIdx = %d\n\r") +ROM_E_RTW_MSGPOOL(PWR_TRACKING_5, "Remnant_OFDMSwingIdx = %d\n\r") +ROM_E_RTW_MSGPOOL(PWR_TRACKING_6, "CCK2~11: 0x86c = 0x%08X\r\n") +ROM_E_RTW_MSGPOOL(PWR_TRACKING_7, "MCS7~4 : 0xe14 = 0x%08X\r\n") +// DBG_RF_IQK +ROM_E_RTW_MSGPOOL(RF_IQK_1, "Path A Tx IQK Success!\n") +ROM_E_RTW_MSGPOOL(RF_IQK_2, "Path A Rx IQK Success!\n") +ROM_E_RTW_MSGPOOL(RF_IQK_3, "Path A IQK failed!\n") +ROM_E_RTW_MSGPOOL(RF_IQK_4, "IQK finished\n") +ROM_E_RTW_MSGPOOL(RF_IQK_5, "LCK finished\n") +// DBG_DM_ADAPTIVITY +ROM_E_RTW_MSGPOOL(DM_ADAPTIVITY_1, "IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d\n") +ROM_E_RTW_MSGPOOL(DM_ADAPTIVITY_2, "DynamicLinkAdaptivity = %d, Adaptivity_enable = %d\n") +ROM_E_RTW_MSGPOOL(DM_ADAPTIVITY_3, "IGI=0x%x, TH_L2H_dmc = 0x%x, TH_H2L_dmc = 0x%x\n\n") + +// freertos_ioctl.c +// mac_reg_dump, bb_reg_dump, rf_reg_dump +ROM_E_RTW_MSGPOOL(MAC_REG_DUMP_1, "\n======= MAC REG =======\n") +ROM_E_RTW_MSGPOOL(BB_REG_DUMP_1, "\n======= BB REG =======\n") +ROM_E_RTW_MSGPOOL(RF_REG_DUMP_1, "\n======= RF REG =======\n") +ROM_E_RTW_MSGPOOL(RF_REG_DUMP_2, "\nRF_Path(%x)\n") +ROM_E_RTW_MSGPOOL(REG_DUMP_1, "0x%02x ") +ROM_E_RTW_MSGPOOL(REG_DUMP_2, " 0x%08x ") +ROM_E_RTW_MSGPOOL(REG_DUMP_3, "\n") +// 0x70 read reg +ROM_E_RTW_MSGPOOL(READ_REG_1, "rtw_read8(0x%x)=0x%02x\n") +ROM_E_RTW_MSGPOOL(READ_REG_2, "rtw_read16(0x%x)=0x%04x\n") +ROM_E_RTW_MSGPOOL(READ_REG_3, "rtw_read32(0x%x)=0x%08x\n") +// 0x71 write reg +ROM_E_RTW_MSGPOOL(WRITE_REG_1, "rtw_write8(0x%x)=0x%02x\n") +ROM_E_RTW_MSGPOOL(WRITE_REG_2, "rtw_write16(0x%x)=0x%04x\n") +ROM_E_RTW_MSGPOOL(WRITE_REG_3, "rtw_write32(0x%x)=0x%08x\n") +// 0x72 read bb +ROM_E_RTW_MSGPOOL(READ_BB_1, "read_bbreg(0x%x)=0x%x\n") +// 0x73 write bb +ROM_E_RTW_MSGPOOL(WRITE_BB_1, "write_bbreg(0x%x)=0x%x\n") +// 0x74 read rf +ROM_E_RTW_MSGPOOL(READ_RF_1, "read RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n") +// 0x75 write rf +ROM_E_RTW_MSGPOOL(WRITE_RF_1, "write RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n") +// 0x17 fix channel +ROM_E_RTW_MSGPOOL(FIX_CHANNEL_1, "=>Fixed channel to %d\n") +ROM_E_RTW_MSGPOOL(FIX_CHANNEL_2, "Invalid channel number(%d)\n") +// 0x22 enable / disable power saving mode +ROM_E_RTW_MSGPOOL(PWR_SAVE_MODE_1, "wlan power saving mode = %s\n") +// 0xaa fix rate +ROM_E_RTW_MSGPOOL(FIX_RATE_1, "chang data rate to :0x%02x\n") +// 0xc0 get odm dbg flag +ROM_E_RTW_MSGPOOL(GET_ODM_DBG_FLAG_1, "get odm dbg flag : 0x%08x\n") +// 0xc1 set odm dbg flag +ROM_E_RTW_MSGPOOL(SET_ODM_DBG_FLAG_1, "set odm dbg flag : 0x%08x\n") +// 0xcc open power index debug message (power by rate, power limit, power tracking) +ROM_E_RTW_MSGPOOL(DUMP_PWR_IDX_1, "Fixed rate = %d\n") +// 0xdd dump info +ROM_E_RTW_MSGPOOL(DUMP_INFO_1, "Tx power:\n") +ROM_E_RTW_MSGPOOL(DUMP_INFO_2, "CCK 1(0xe08)= 0x%x\n") +ROM_E_RTW_MSGPOOL(DUMP_INFO_3, "CCK 11~2(0x86c)= 0x%x\n") +ROM_E_RTW_MSGPOOL(DUMP_INFO_4, "OFDM 18~6(0xe00)= 0x%x\n") +ROM_E_RTW_MSGPOOL(DUMP_INFO_5, "OFDM 54~24(0xe04)= 0x%x\n") +ROM_E_RTW_MSGPOOL(DUMP_INFO_6, "MCS 3~0(0xe10)= 0x%x\n") +ROM_E_RTW_MSGPOOL(DUMP_INFO_7, "MCS 7~4(0xe14)= 0x%x\n") +ROM_E_RTW_MSGPOOL(DUMP_INFO_8, "Country code: 0x%x\n") +// 0xee turn on/off dynamic funcs +ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_1, " === DMFlag(0x%08x) === \n") +ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_2, "extra_arg = 0 - disable all dynamic func\n") +ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_3, "extra_arg = 1 - enable all dynamic func\n") +ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_4, "extra_arg = 2 - disable DIG\n") +ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_5, "extra_arg = 3 - enable DIG\n") +ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_6, "extra_arg = 4 - disable tx power tracking\n") +ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_7, "extra_arg = 5 - enable tx power tracking\n") +ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_8, "extra_arg = 6 - disable adaptivity\n") +ROM_E_RTW_MSGPOOL(DM_FUNC_FLAG_9, "extra_arg = 7 - enable adaptivity\n") + +// lxbus_ops.c +ROM_E_RTW_MSGPOOL(RX_MPDU_1, "Drop packet! crc_err = %d, icv_err = %d, rx_pkt_len = %d, skb_pkt_len = %d\n") + +// wlan driver DBG_871X_LEVEL +#define ROM_E_RTW_MSGPOOL_871X(name,str) ROM_E_RTW_MSGPOOL(name,DRIVER_PREFIX str) +// rtw_ap.c +ROM_E_RTW_MSGPOOL_871X(AP_TIMEOUT_CHK_1, "Asoc expire "MAC_FMT"\n") +// rtw_intfs.c +ROM_E_RTW_MSGPOOL_871X(INIT_DRV_SW_1, "The driver is for MP\n") +// rtw_ioctl_set.c +ROM_E_RTW_MSGPOOL_871X(SET_BSSID_1, "set BSSID: %02x:%02x:%02x:%02x:%02x:%02x\n") +ROM_E_RTW_MSGPOOL_871X(SET_SSID_1, "set ssid [%s] \n") +// rtw_mlme_ext.c +ROM_E_RTW_MSGPOOL_871X(ON_BEACON_1, "ap has changed, disconnect now\n ") +ROM_E_RTW_MSGPOOL_871X(ON_AUTH_1, "+OnAuth: "MAC_FMT"\n") +ROM_E_RTW_MSGPOOL_871X(ON_AUTH_2, " Exceed the upper limit(%d) of supported clients...\n") +ROM_E_RTW_MSGPOOL_871X(ON_AUTH_CLIENT_1, "auth success, start assoc\n") +ROM_E_RTW_MSGPOOL_871X(ON_ASSOC_REQ_1, "+OnAssocReq\n") +ROM_E_RTW_MSGPOOL_871X(ON_ASSOC_RSP_1, "association success(res=%d)\n") +ROM_E_RTW_MSGPOOL_871X(ON_DE_AUTH_1, "ap recv deauth reason code(%d) sta:"MAC_FMT"\n") +ROM_E_RTW_MSGPOOL_871X(ON_DE_AUTH_2, "sta recv deauth reason code(%d) sta:"MAC_FMT"\n") +ROM_E_RTW_MSGPOOL_871X(ON_DISASSOC_1, "ap recv disassoc reason code(%d) sta:"MAC_FMT"\n") +ROM_E_RTW_MSGPOOL_871X(ON_DISASSOC_2, "sta recv disassoc reason code(%d) sta:"MAC_FMT"\n") +ROM_E_RTW_MSGPOOL_871X(ISSUE_BEACON_1, "beacon frame too large\n") +ROM_E_RTW_MSGPOOL_871X(ISSUE_PROBERSP_1, "probersp frame too large\n") +ROM_E_RTW_MSGPOOL_871X(ISSUE_PROBEREQ_1, "probereq frame too large\n") +ROM_E_RTW_MSGPOOL_871X(ISSUE_AUTH_1, "auth frame too large\n") +ROM_E_RTW_MSGPOOL_871X(ISSUE_ASSOCRSP_1, "assocrsp frame too large\n") +ROM_E_RTW_MSGPOOL_871X(ISSUE_ASSOCREQ_1, "assocreq frame too large\n") +ROM_E_RTW_MSGPOOL_871X(ISSUE_NULLDATA_1, "nulldata frame too large\n") +ROM_E_RTW_MSGPOOL_871X(ISSUE_QOS_NULLDATA_1, "qos nulldata frame too large\n") +ROM_E_RTW_MSGPOOL_871X(ISSUE_DEAUTH_1, "deauth frame too large\n") +ROM_E_RTW_MSGPOOL_871X(ISSUE_ACTION_BA_1, "action BA frame too large\n") +ROM_E_RTW_MSGPOOL_871X(ISSUE_BSS_COEXIST_1, "action BSSCoexist frame too large\n") +ROM_E_RTW_MSGPOOL_871X(START_CLNT_AUTH_1, "start auth to %02x:%02x:%02x:%02x:%02x:%02x\n") +ROM_E_RTW_MSGPOOL_871X(LINKED_STATUS_CHK_1, "no beacon for a long time, disconnect or roaming\n") +ROM_E_RTW_MSGPOOL_871X(SETKEY_HDL_1, "set group key to hw: alg:%d(WEP40-1 WEP104-5 TKIP-2 AES-4) keyid:%d\n") +ROM_E_RTW_MSGPOOL_871X(SET_STAKEY_HDL_1, "set pairwise key to hw: alg:%d(WEP40-1 WEP104-5 TKIP-2 AES-4)\n") +ROM_E_RTW_MSGPOOL_871X(SET_STAKEY_HDL_2, "set pairwise key to hw: alg:%d(WEP40-1 WEP104-5 TKIP-2 AES-4) for %x:%x:%x:%x:%x:%x\n") +// rtw_p2p.c +ROM_E_RTW_MSGPOOL_871X(P2P_BUILD_MGNT_FRAME_1, "p2p mgnt frame too large\n") +// rtw_psk.c +ROM_E_RTW_MSGPOOL_871X(SEND_EAPOL_1, "ap mode 4-1\n") +ROM_E_RTW_MSGPOOL_871X(SEND_EAPOL_2, "ap mode 4-3\n") +ROM_E_RTW_MSGPOOL_871X(SEND_EAPOL_3, "ap mode 2-1 to WPA_STA(%d)\n") +ROM_E_RTW_MSGPOOL_871X(EAPOL_KEY_RECVD_1, "ap mode 4-2\n") +ROM_E_RTW_MSGPOOL_871X(EAPOL_KEY_RECVD_2, "ap mode 4-4\n") +ROM_E_RTW_MSGPOOL_871X(EAPOL_KEY_RECVD_3, "ap mode 2-2 from WPA_STA(%d)\n") +// rtw_recv.c +ROM_E_RTW_MSGPOOL_871X(FREE_RECVFRAME_1, "%s free_recvframe_cnt:%d > %d refree happen !!!!\n") +// hal_com.c +ROM_E_RTW_MSGPOOL_871X(VAR_PORT_SWITCH_1, "port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n") +ROM_E_RTW_MSGPOOL_871X(VAR_PORT_SWITCH_2, "port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n") +// osdep_service.c +ROM_E_RTW_MSGPOOL_871X(DOWN_SEMA_1, "%s(%p) failed, retry\n") + + +#undef ROM_E_RTW_MSGPOOL +#undef ROM_E_RTW_MSGPOOL_871X diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_psk.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_psk.h new file mode 100644 index 0000000..14787ce --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_psk.h @@ -0,0 +1,44 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ****************************************************************************** + * + * This is ROM code section. + * + ******************************************************************************/ +#ifndef __ROM_RTW_PSK_H_ +#define __ROM_RTW_PSK_H_ + +int rom_psk_PasswordHash ( + unsigned char *password, + int passwordlength, + unsigned char *ssid, + int ssidlength, + unsigned char *output); + +void rom_psk_CalcPTK( unsigned char *addr1, unsigned char *addr2, + unsigned char *nonce1, unsigned char *nonce2, + unsigned char *keyin, int keyinlen, + unsigned char *keyout, int keyoutlen); + +void rom_psk_CalcGTK(unsigned char *addr, unsigned char *nonce, + unsigned char *keyin, int keyinlen, + unsigned char *keyout, int keyoutlen); + +#endif //__ROM_RTW_PSK_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_security.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_security.h new file mode 100644 index 0000000..28436b4 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_rtw_security.h @@ -0,0 +1,104 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ****************************************************************************** + * + * This is ROM code section. + * + ******************************************************************************/ +#ifndef __ROM_RTW_SECURITY_H_ +#define __ROM_RTW_SECURITY_H_ + +struct mic_data +{ + u32 K0, K1; // Key + u32 L, R; // Current state + u32 M; // Message accumulator (single word) + u32 nBytesInM; // # bytes in M +}; + +union u_crc +{ + unsigned char ch[4]; + int i; +}; + +//=============================== +// WEP related +//=============================== +void wep_80211_encrypt( + u8 *pframe, u32 wlan_hdr_len, \ + u32 iv_len, u32 payload_len,\ + u8* key, u32 key_len); + +u8 wep_80211_decrypt( + u8 *pframe, u32 wlan_hdr_len, + u32 iv_len, u32 payload_len, + u8* key, u32 key_len, + union u_crc *pcrc\ + ); + +//=============================== +// TKIP related +//=============================== +void tkip_80211_encrypt( + u8 *pframe, u32 wlan_hdr_len, \ + u32 iv_len, u32 payload_len,\ + u8* key, u32 key_len,\ + u8* ta); + +u8 tkip_80211_decrypt( + u8 *pframe, u32 wlan_hdr_len, \ + u32 iv_len, u32 payload_len,\ + u8* key, u32 key_len,\ + u8* ta, union u_crc *pcrc); + +void tkip_micappendbyte(struct mic_data *pmicdata, u8 b ); +void rtw_secmicsetkey(struct mic_data *pmicdata, u8 * key); +void rtw_secmicappend(struct mic_data *pmicdata, u8 * src, u32 nbytes ); +void rtw_secgetmic(struct mic_data *pmicdata, u8 * dst ); +void rtw_seccalctkipmic(u8 * key,u8 *header,u8 *data,u32 data_len,u8 *mic_code, u8 pri); +void tkip_phase1(u16 *p1k,const u8 *tk,const u8 *ta,u32 iv32); +void tkip_phase2(u8 *rc4key,const u8 *tk,const u16 *p1k,u16 iv16); + + +//=============================== +// AES related +//=============================== +void aes1_encrypt(u8 *key, u8 *data, u8 *ciphertext); +void aesccmp_construct_mic_iv( + u8 *mic_iv, sint qc_exists, sint a4_exists, + u8 *mpdu, uint payload_length,u8 *pn_vector); +void aesccmp_construct_mic_header1(u8 *mic_header1, sint header_length, u8 *mpdu); +void aesccmp_construct_mic_header2( + u8 *mic_header2, u8 *mpdu, sint a4_exists, sint qc_exists); +void aesccmp_construct_ctr_preload( + u8 *ctr_preload, sint a4_exists, sint qc_exists, + u8 *mpdu, u8 *pn_vector, sint c); + +u32 aes_80211_encrypt( + u8 *pframe, u32 wlan_hdr_len, \ + u32 payload_len, u8 *key, \ + u32 frame_type, u8 *mic); + +u32 aes_80211_decrypt( + u8 *pframe, u32 wlan_hdr_len, \ + u32 payload_len, u8 *key, \ + u32 frame_type, u8 *mic); +#endif //__ROM_RTW_SECURITY_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_sha1.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_sha1.h new file mode 100644 index 0000000..dc0dba0 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rom_sha1.h @@ -0,0 +1,71 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _ROM_SHA1_ +#define _ROM_SHA1_ + + +#ifndef _SHA_enum_ +#define _SHA_enum_ +enum +{ + shaSuccess = 0, + shaNull, /* Null pointer parameter */ + shaInputTooLong, /* input data too long */ + shaStateError /* called Input after Result */ +}; +#endif + + +#define SHA1HashSize 20 + +/* + * This structure will hold context information for the SHA-1 + * hashing operation + */ +typedef struct SHA1Context +{ + u32 Intermediate_Hash[SHA1HashSize/4]; /* Message Digest */ + + u32 Length_Low; /* Message length in bits */ + u32 Length_High; /* Message length in bits */ + + /* Index into message block array */ + u16 Message_Block_Index; + u8 Message_Block[64]; /* 512-bit message blocks */ + + int Computed; /* Is the digest computed? */ + int Corrupted; /* Is the message digest corrupted? */ +} SHA1Context; + + +/* + * Function Prototypes + */ + + +int rt_sha1_init( SHA1Context *); +int rt_sha1_update( SHA1Context *, const u8 *, unsigned int); +int rt_sha1_finish( SHA1Context *, u8 Message_Digest[SHA1HashSize]); + +void rt_hmac_sha1(unsigned char *text, int text_len, unsigned char *key, + int key_len, unsigned char *digest); + + +#endif //_ROM_SHA1_ diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtl8195a_hal.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtl8195a_hal.h new file mode 100644 index 0000000..aca8be2 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtl8195a_hal.h @@ -0,0 +1,618 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __RTL8195A_HAL_H__ +#define __RTL8195A_HAL_H__ + +#include "drv_types.h" +#include "rtl8195a/rtl8195a_pmu_task.h" +#include "hal_data.h" + +#include "rtl8195a/rtl8195a_spec.h" +#include "rtl8195a/rtl8195a_rf.h" +#include "rtl8195a/rtl8195a_dm.h" +#include "rtl8195a/rtl8195a_recv.h" +#include "rtl8195a/rtl8195a_xmit.h" +#include "rtl8195a/rtl8195a_cmd.h" +#include "rtl8195a/rtl8195a_pmu_cmd.h" +#include "rtl8195a/rtl8195a_led.h" +#include "rtl8195a/Hal8195APwrSeq.h" +#include "rtl8195a/Hal8195APhyReg.h" +#include "rtl8195a/Hal8195APhyCfg.h" +#include "rtl8195a/rom_Hal8195APhyCfg.h" + +#ifdef DBG_CONFIG_ERROR_DETECT +#include "rtl8195a/rtl8195a_sreset.h" +#endif + +#include "../src/hal/OUTSRC/phydm_precomp.h" + +#if (RTL8195A_SUPPORT==1) + //2TODO: We should define 8192S firmware related macro settings here!! + #define RTL819X_DEFAULT_RF_TYPE RF_1T2R + #define RTL819X_TOTAL_RF_PATH 2 + +//--------------------------------------------------------------------- +// RTL8723BS From file +//--------------------------------------------------------------------- + #define RTL8723B_FW_IMG "rtl8723B\\rtl8723bfw.bin" + #define RTL8195A_PHY_REG "rtl8195A\\PHY_REG_1T.txt" + #define RTL8195A_PHY_RADIO_A "rtl8195A\\radio_a_1T.txt" + #define RTL8195A_PHY_RADIO_B "rtl8195A\\radio_b_1T.txt" + #define RTL8195A_TXPWR_TRACK "rtl8195A\\TxPowerTrack.txt" + #define RTL8195A_AGC_TAB "rtl8195A\\AGC_TAB_1T.txt" + #define RTL8195A_PHY_MACREG "rtl87195A\\MAC_REG.txt" + #define RTL8195A_PHY_REG_PG "rtl8195A\\PHY_REG_PG.txt" + #define RTL8195A_PHY_REG_MP "rtl8195A\\PHY_REG_MP.txt" + #define RTL8195A_TXPWR_LMT "rtl8195A\\TXPWR_LMT.txt" + +//--------------------------------------------------------------------- +// RTL8723BS From header +//--------------------------------------------------------------------- + + //#define Rtl8723B_FwImageArray Array_MP_8723B_FW_NIC + //#define Rtl8723B_FwImgArrayLength ArrayLength_MP_8723B_FW_NIC + //#define Rtl8723B_FwWoWImageArray Array_MP_8723B_FW_WoWLAN + //#define Rtl8723B_FwWoWImgArrayLength ArrayLength_MP_8723B_FW_WoWLAN + + #define Rtl8723B_PHY_REG_Array_PG Rtl8723SPHY_REG_Array_PG + #define Rtl8723B_PHY_REG_Array_PGLength Rtl8723SPHY_REG_Array_PGLength + +#if MP_DRIVER == 1 + #define Rtl8723B_FwBTImgArray Rtl8723BFwBTImgArray + #define Rtl8723B_FwBTImgArrayLength Rtl8723BFwBTImgArrayLength + + #define Rtl8723B_FwMPImageArray Rtl8723BFwMPImgArray + #define Rtl8723B_FwMPImgArrayLength Rtl8723BMPImgArrayLength + + #define Rtl8723B_PHY_REG_Array_MP Rtl8723B_PHYREG_Array_MP + #define Rtl8723B_PHY_REG_Array_MPLength Rtl8723B_PHYREG_Array_MPLength +#endif + +#endif // RTL8195A_SUPPORT + +#define FW_8723B_SIZE 0x8000 +#define FW_8723B_START_ADDRESS 0x1000 +#define FW_8723B_END_ADDRESS 0x1FFF //0x5FFF + +#define IS_FW_HEADER_EXIST_8723B(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x5300) + +typedef struct _RT_FIRMWARE { + FIRMWARE_SOURCE eFWSource; +#ifdef CONFIG_EMBEDDED_FWIMG + u8* szFwBuffer; +#else + u8 szFwBuffer[FW_8723B_SIZE]; +#endif + u32 ulFwLength; + +#ifdef CONFIG_EMBEDDED_FWIMG + u8* szBTFwBuffer; +#else + u8 szBTFwBuffer[FW_8723B_SIZE]; +#endif + u32 ulBTFwLength; + +#ifdef CONFIG_WOWLAN + u8* szWoWLANFwBuffer; + u32 ulWoWLANFwLength; +#endif //CONFIG_WOWLAN +} RT_FIRMWARE_8723B, *PRT_FIRMWARE_8723B; + +// +// This structure must be cared byte-ordering +// +// Added by tynli. 2009.12.04. +typedef struct _RT_8723B_FIRMWARE_HDR +{ + // 8-byte alinment required + + //--- LONG WORD 0 ---- + u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut + u8 Category; // AP/NIC and USB/PCI + u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions + u16 Version; // FW Version + u8 Subversion; // FW Subversion, default 0x00 + u16 Rsvd1; + + + //--- LONG WORD 1 ---- + u8 Month; // Release time Month field + u8 Date; // Release time Date field + u8 Hour; // Release time Hour field + u8 Minute; // Release time Minute field + u16 RamCodeSize; // The size of RAM code + u16 Rsvd2; + + //--- LONG WORD 2 ---- + u32 SvnIdx; // The SVN entry index + u32 Rsvd3; + + //--- LONG WORD 3 ---- + u32 Rsvd4; + u32 Rsvd5; +}RT_8723B_FIRMWARE_HDR, *PRT_8723B_FIRMWARE_HDR; + +#define DRIVER_EARLY_INT_TIME_8195A 0x05 // 5ms +#define BCN_DMA_ATIME_INT_TIME_8195A 0x02 // 2ms + +// for 8195A +// TX 32K, RX 16K, Page size 128B for TX, 8B for RX +#define PAGE_SIZE_TX_8195A 128 +#define PAGE_SIZE_RX_8195A 8 + +#define RX_DMA_SIZE_8195A 0x4000 // 16K +#define RX_DMA_RESERVED_SIZE_8195A 0x80 // 128B, reserved for tx report +#define RX_DMA_BOUNDARY_8195A (RX_DMA_SIZE_8195A - RX_DMA_RESERVED_SIZE_8195A - 1) + + +// Note: We will divide number of page equally for each queue other than public queue! + +//For General Reserved Page Number(Beacon Queue is reserved page) +//Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 +#ifdef CONFIG_WLAN_HAL_TEST +#define BCNQ_PAGE_NUM_8195A 0x00 +#else +#define BCNQ_PAGE_NUM_8195A 0x08 +#endif + +#ifdef CONFIG_CONCURRENT_MODE +#define BCNQ1_PAGE_NUM_8195A 0x04 +#else +#define BCNQ1_PAGE_NUM_8195A 0x00 +#endif + +//For WoWLan , more reserved page +//ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2 +#ifdef CONFIG_WOWLAN +#define WOWLAN_PAGE_NUM_8195A 0x07 +#else +#define WOWLAN_PAGE_NUM_8195A 0x00 +#endif + +#ifdef CONFIG_WLAN_HAL_TEST +#define TX_TOTAL_PAGE_NUMBER_8195A 0x40 +#define TX_PAGE_BOUNDARY_8195A (TX_TOTAL_PAGE_NUMBER_8195A + 1) +#else +#define TX_TOTAL_PAGE_NUMBER_8195A (0xFF - BCNQ_PAGE_NUM_8195A - BCNQ1_PAGE_NUM_8195A - WOWLAN_PAGE_NUM_8195A) +#define TX_PAGE_BOUNDARY_8195A (TX_TOTAL_PAGE_NUMBER_8195A + 1) +#endif + +#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER TX_TOTAL_PAGE_NUMBER_8195A +#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) + +// For Normal Chip Setting +// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8195A +#ifdef CONFIG_WLAN_HAL_TEST +#define NORMAL_PAGE_NUM_HPQ_8195A 0x10 +#define NORMAL_PAGE_NUM_LPQ_8195A 0x10 +#define NORMAL_PAGE_NUM_NPQ_8195A 0x10 +#else +#define NORMAL_PAGE_NUM_HPQ_8195A 0x0C +#define NORMAL_PAGE_NUM_LPQ_8195A 0x02 +#define NORMAL_PAGE_NUM_NPQ_8195A 0x02 +#endif + +// Note: For Normal Chip Setting, modify later +#define WMM_NORMAL_PAGE_NUM_HPQ_8195A 0x30 +#define WMM_NORMAL_PAGE_NUM_LPQ_8195A 0x20 +#define WMM_NORMAL_PAGE_NUM_NPQ_8195A 0x20 + +#include "HalVerDef.h" +#include "hal_com.h" + +#define EFUSE_OOB_PROTECT_BYTES (52+28+16+32) // Security + RF + MAC + OTP = 128 + +#define HWSET_MAX_SIZE_8195A 512 +#define EFUSE_REAL_CONTENT_LEN_8195A 256 +#define EFUSE_MAP_LEN_8195A 512 +#define EFUSE_MAX_SECTION_8195A 64 + +#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02. +#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8195A) + +#define EFUSE_ACCESS_ON 0x69 // For RTL8723 only. +#define EFUSE_ACCESS_OFF 0x00 // For RTL8723 only. + +#ifdef CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD +#define LITTLE_WIFI_STACKSIZE 512 +#ifdef PLATFORM_CMSIS_RTOS +#define LITTLE_WIFI_TASK_PRIORITY 3 // osPriorityRealtime +#ifdef CONFIG_POWER_SAVING +#define CHECK_IN_REQ_STATE_STACKSIZE 256 +#define CHECK_IN_REQ_STATE_TASK_PRIORITY 0//osPriorityNormal + +#ifdef TDMA_POWER_SAVING +#define TDMA_CHANGE_STATE_STACKSIZE 256 +#define TDMA_CHANGE_STATE_TASK_PRIORITY 2//osPriorityRealtime +#endif //#ifdef TDMA_POWER_SAVING + +#endif +#else +#define LITTLE_WIFI_TASK_PRIORITY 6//TASK_PRORITY_LOW + +#ifdef CONFIG_POWER_SAVING +#define CHECK_IN_REQ_STATE_STACKSIZE 256 +#define CHECK_IN_REQ_STATE_TASK_PRIORITY 1 + +#ifdef TDMA_POWER_SAVING +#define TDMA_CHANGE_STATE_STACKSIZE 256 +#define TDMA_CHANGE_STATE_TASK_PRIORITY 3 +#endif //#ifdef TDMA_POWER_SAVING + +#endif +#endif +#endif + +#define LX_DMA_IMR_DISABLED 0 +#define FW_IMR_DISABLED 0 +#define WL_PMC_IMR_DISABLED 0 + + +//======================================================== +// EFUSE for BT definition +//======================================================== +#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512 +#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3 +#define EFUSE_BT_MAP_LEN 1024 // 1k bytes +#define EFUSE_BT_MAX_SECTION 128 // 1024/8 + +#define EFUSE_PROTECT_BYTES_BANK 16 + +#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type) + +// Description: Determine the types of C2H events that are the same in driver and Fw. +// Fisrt constructed by tynli. 2009.10.09. +typedef enum _C2H_EVT +{ + C2H_DBG = 0, + C2H_TSF = 1, + C2H_AP_RPT_RSP = 2, + C2H_CCX_TX_RPT = 3, // The FW notify the report of the specific tx packet. + C2H_BT_RSSI = 4, + C2H_BT_OP_MODE = 5, + C2H_EXT_RA_RPT = 6, + C2H_8723B_BT_INFO = 9, + C2H_HW_INFO_EXCH = 10, + C2H_8723B_BT_MP_INFO = 11, + MAX_C2HEVENT +} C2H_EVT; + +typedef _PACKED struct _C2H_EVT_HDR +{ + u8 CmdID; + u8 CmdLen; + u8 CmdSeq; +} C2H_EVT_HDR, *PC2H_EVT_HDR; + +typedef enum tag_Package_Definition +{ + PACKAGE_DEFAULT, + PACKAGE_QFN56, + PACKAGE_QFN48, + PACKAGE_BGA96, + PACKAGE_QFN88, + PACKAGE_QFN216 +}PACKAGE_TYPE_E; + +typedef enum tag_ChipID_Definition +{ + CHIPID_8711AM = 0xFF, + CHIPID_8195AM = 0xFE, + CHIPID_8711AF = 0xFD, + CHIPID_8710AF = 0xFC, + CHIPID_8711AN = 0xFB, + CHIPID_8710AM = 0xFA +}CHIP_TD_E; + + +#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) +#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) + +//======================================================== +// TXBD and RXBD definition +//======================================================== +#ifdef CONFIG_MP_INCLUDED // For MP Tx no idle +#define TX_VIQ_DESC_NUM 4 +#define TX_VOQ_DESC_NUM 4 +#define TX_BKQ_DESC_NUM 4 +#define TX_BEQ_DESC_NUM 32 +#else +#define TX_VIQ_DESC_NUM 4 +#define TX_VOQ_DESC_NUM 4 +#define TX_BKQ_DESC_NUM 4 +#define TX_BEQ_DESC_NUM 4 +#endif +#define TX_BCNQ_DESC_NUM 2 +#define TX_MGQ_DESC_NUM 4 +#define TX_H0Q_DESC_NUM 2 +#define TX_H1Q_DESC_NUM 2 +#define TX_H2Q_DESC_NUM 2 +#define TX_H3Q_DESC_NUM 2 +#define TX_H4Q_DESC_NUM 2 +#define TX_H5Q_DESC_NUM 2 +#define TX_H6Q_DESC_NUM 2 +#define TX_H7Q_DESC_NUM 2 +#define RX_Q_DESC_NUM 4 //16 Reduce rx desc number due to memory limitation + +#define SET_VIQ_DES_NUM (TX_VIQ_DESC_NUM<<16) +#define SET_VOQ_DES_NUM (TX_VOQ_DESC_NUM) +#define SET_RXQ_DES_NUM (RX_Q_DESC_NUM<<16) +#define SET_MGQ_DES_NUM (TX_MGQ_DESC_NUM) +#define SET_BKQ_DES_NUM (TX_BKQ_DESC_NUM<<16) +#define SET_BEQ_DES_NUM (TX_BEQ_DESC_NUM) +#define SET_H1Q_DES_NUM (TX_H1Q_DESC_NUM<<16) +#define SET_H0Q_DES_NUM (TX_H0Q_DESC_NUM) +#define SET_H3Q_DES_NUM (TX_H3Q_DESC_NUM<<16) +#define SET_H2Q_DES_NUM (TX_H2Q_DESC_NUM) +#define SET_H5Q_DES_NUM (TX_H5Q_DESC_NUM<<16) +#define SET_H4Q_DES_NUM (TX_H4Q_DESC_NUM) +#define SET_H7Q_DES_NUM (TX_H7Q_DESC_NUM<<16) +#define SET_H6Q_DES_NUM (TX_H6Q_DESC_NUM) + +#define TX_DESC_MODE 1 + +//0: 2 segment +//1: 4 segment +//2: 8 segment +//#define TX_DESC_MODE 2 + +#define MAX_TXBD_SEQMENT_NUM ((TX_DESC_MODE)? (4*TX_DESC_MODE): 2) +#define TXBD_SEGMENT_SIZE 8 + + + +typedef struct _RXBD_ELEMENT_ { + u32 Dword0; + u32 PhyAddr; +}RXBD_ELEMENT,*PRXBD_ELEMENT; + + +typedef struct _TXBD_ELEMENT_ { + u32 Dword0; + u32 AddrLow; +}TXBD_ELEMENT,*PTXBD_ELEMENT; + +typedef struct _LX_DMA_ELEMENT_ { + u32 QueueTRxBdBase; + u32 HwIndex; + u32 HostIndex; + u32 AvaliableCnt; +}LX_DMA_ELEMENT, *PLX_DMA_ELEMENT; +#if 1 + +typedef enum _LX_DMA_QUEUE_TYPE_{ + VO_QUEUE = 0, + VI_QUEUE = 1, + BE_QUEUE = 2, + BK_QUEUE = 3, + MG_QUEUE = 4, + RX_QUEUE = 5, + H0_QUEUE = 6, + H1_QUEUE = 7, + H2_QUEUE = 8, + H3_QUEUE = 9, + H4_QUEUE = 10, + H5_QUEUE = 11, + H6_QUEUE = 12, + H7_QUEUE = 13, + BCN_QUEUE = 14, + MAX_TX_QUEUE = 15, + ERROR_QUEUE = 16, +}LX_DMA_QUEUE_TYPE, *PLX_DMA_QUEUE_TYPE; + +typedef struct _TX_FREE_QUEUE_ { + _queue FreeQueue; + u32 Qlen; +}TX_FREE_QUEUE, *PTX_FREE_QUEUE; + +typedef struct _LX_DMA_MANAGER_ { + LX_DMA_ELEMENT QueueTRxBd[MAX_TX_QUEUE]; + u32 QueueMaxValue[MAX_TX_QUEUE]; + u32 RxBdSkb[RX_Q_DESC_NUM]; + u32 RxLen; + u32 RemainLen; + u16 RxAggregateNum; + u16 RxExpectTag; + u16 RxSegFlow; + u16 Flagls; + TX_FREE_QUEUE TxFreeQueue[MAX_TX_QUEUE]; + +}LX_DMA_MANAGER, *PLX_DMA_MANAGER; + +#else + +typedef struct _LX_DMA_MANAGER_ { + u32 *pVoqTXBD; + u32 *pViqTXBD; + u32 *pBeqTXBD; + u32 *pBkqTXBD; + u32 *pBcnqTXBD; + u32 *pMgqTXBD; + u32 *pH0qTXBD; + u32 *pH1qTXBD; + u32 *pH2qTXBD; + u32 *pH3qTXBD; + u32 *pH4qTXBD; + u32 *pH5qTXBD; + u32 *pH6qTXBD; + u32 *pH7qTXBD; + u32 *pExViqTXBD; + u32 *pExVoqTXBD; + u32 *pExBeqTXBD; + u32 *pExBkqTXBD; + u32 *pExMgqTXBD; + u32 *pRXBD; +// u4Byte RxAggBufEntry[RX_Q_DESC_NUM]; +// u4Byte RxAggLenEntry[RX_Q_DESC_NUM]; + u32 RxLen; + u32 RemainLen; + u16 ViqTxWritePoint; + u16 ViqTxReadPoint; + u16 VoqTxWritePoint; + u16 VoqTxReadPoint; + u16 BeqTxWritePoint; + u16 BeqTxReadPoint; + u16 BkqTxWritePoint; + u16 BkqTxReadPoint; + u16 RxWritePoint; + u16 RxReadPoint; + u16 RxAggregateNum; + u16 RxExpectTag; + u16 RxSegFlow; + u16 Flagls; +}LX_DMA_MANAGER, *PLX_DMA_MANAGER; +#endif + +// rtl8723a_hal_init.c +s32 rtl8195a_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw); +void rtl8195a_FirmwareSelfReset(PADAPTER padapter); +void rtl8195a_InitializeFirmwareVars(PADAPTER padapter); + +void rtl8195a_InitAntenna_Selection(PADAPTER padapter); +void rtl8195a_DeinitAntenna_Selection(PADAPTER padapter); +void rtl8195a_CheckAntenna_Selection(PADAPTER padapter); +void rtl8195a_init_default_value(PADAPTER padapter); + +s32 rtl8195a_InitLLTTable(PADAPTER padapter); + +s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU); +s32 CardDisableWithoutHWSM(PADAPTER padapter); + +// EFuse +//u8 GetEEPROMSize8195a(PADAPTER padapter); +void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent); +void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo); +void Hal_EfuseParseTxPowerInfo_8195A(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail); +void Hal_EfuseParseBTCoexistInfo_8195A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseEEPROMVer_8195A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseChnlPlan_8195A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseCustomerID_8195A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseAntennaDiversity_8195A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseXtal_8195A(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail); +void Hal_EfuseParseThermalMeter_8195A(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail); + +u8 rtw_flash_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_flash_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_config_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data, u8 efuse); +u8 rtw_config_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data, u8 efuse); + +void rtl8195a_set_hal_ops(struct hal_ops *pHalFunc); +void lxbus_set_intf_ops(struct _io_ops *pops); +void SetHwReg8195A(PADAPTER padapter, u8 variable, u8 *val); +void GetHwReg8195A(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHalDefVar8195A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); +u8 GetHalDefVar8195A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); +void SetHalODMVar8195A( PADAPTER Adapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet); +void GetHalODMVar8195A(PADAPTER Adapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet); + +// register +void rtl8195a_InitBeaconParameters(PADAPTER padapter); +void rtl8195a_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode); +void _InitBurstPktLen_8195AB(PADAPTER Adapter); +#ifdef CONFIG_WOWLAN +void _8051Reset8195a(PADAPTER padapter); +void Hal_DetectWoWMode(PADAPTER pAdapter); +#endif //CONFIG_WOWLAN + +void rtl8195a_start_thread(_adapter *padapter); +void rtl8195a_stop_thread(_adapter *padapter); + +#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) +void rtl8195ab_init_checkbthang_workqueue(_adapter * adapter); +void rtl8195ab_free_checkbthang_workqueue(_adapter * adapter); +void rtl8195ab_cancle_checkbthang_workqueue(_adapter * adapter); +void rtl8195ab_hal_check_bt_hang(_adapter * adapter); +#endif + +#ifdef CONFIG_WOWLAN +void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip); +void rtw_get_sec_iv(PADAPTER padapter, u8*pcur_dot11txpn, u8 *StaAddr); +#endif + +#ifdef CONFIG_GPIO_WAKEUP +void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue); +#endif + +#ifdef CONFIG_RF_GAIN_OFFSET +void Hal_ReadRFGainOffset(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail); +#endif //CONFIG_RF_GAIN_OFFSET + + +//1TODO: Chris +#if 1 + +//============= +// [1] Rx Buffer Descriptor (for PCIE) buffer descriptor architecture +//DWORD 0 +#define SET_RX_BUFFER_DESC_DATA_LENGTH_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 0, 14, __Value) +#define SET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc,__Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 14, 1, __Value) +#define SET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 15, 1, __Value) +#define SET_RX_BUFFER_DESC_RX_TAG_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 16, 13, __Value) + +#define GET_RX_BUFFER_DESC_OWN_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 31, 1) +#define GET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 14, 1) +#define GET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 15, 1) +#define GET_RX_BUFFER_DESC_RX_TAG_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 16, 13) +#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc)LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 14) + + +//DWORD 1 +#define SET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc+4, 0, 32, __Value) +#define GET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+4, 0, 32) + +//DWORD 2 +#define SET_RX_BUFFER_PHYSICAL_HIGH_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc+8, 0, 32, __Value) + + +//=====Tx Desc Buffer content + +// config element for each tx buffer +/* +#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 0, 16, __Valeu) +#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 31, 1, __Valeu) +#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+4, 0, 32, __Valeu) +#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu) +*/ +#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu) +#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu) +#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu) +#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu) + +// Dword 0 +#define SET_TX_BUFF_DESC_LEN_0_92E(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Valeu) +#define SET_TX_BUFF_DESC_PSB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) +#define SET_TX_BUFF_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) +// Dword 1 +#define SET_TX_BUFF_DESC_ADDR_LOW_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value) +#define GET_TX_DESC_TX_BUFFER_ADDRESS_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0,32) + + +// Dword 2 +#define SET_TX_BUFF_DESC_ADDR_HIGH_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value) +// Dword 3, RESERVED + + +#define SET_TX_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) + +#endif + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtl8711b_hal.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtl8711b_hal.h new file mode 100644 index 0000000..6f97db2 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtl8711b_hal.h @@ -0,0 +1,595 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __RTL8711B_HAL_H__ +#define __RTL8711B_HAL_H__ + +#include "drv_types.h" +//#include "rtl8711b/rtl8711b_pmu_task.h" +#include "hal_data.h" + +#include "rtl8711b/rtl8711b_spec.h" +#include "rtl8711b/rtl8711b_rf.h" +#include "rtl8711b/rtl8711b_dm.h" +#include "rtl8711b/rtl8711b_recv.h" +#include "rtl8711b/rtl8711b_xmit.h" +#include "rtl8711b/rtl8711b_cmd.h" +//#include "rtl8711b/rtl8711b_pmu_cmd.h" +#include "rtl8711b/rtl8711b_led.h" +#include "rtl8711b/Hal8711BPwrSeq.h" +#include "rtl8711b/Hal8711BPhyReg.h" +#include "rtl8711b/Hal8711BPhyCfg.h" +#include "rtl8711b/rom_Hal8711BPhyCfg.h" + +#ifdef DBG_CONFIG_ERROR_DETECT +#include "rtl8711b/rtl8711b_sreset.h" +#endif + +#include "../src/hal/OUTSRC/phydm_precomp.h" + +#if (RTL8711B_SUPPORT==1) + //2TODO: We should define 8192S firmware related macro settings here!! + #define RTL819X_DEFAULT_RF_TYPE RF_1T2R + #define RTL819X_TOTAL_RF_PATH 2 + +//--------------------------------------------------------------------- +// RTL8723BS From file +//--------------------------------------------------------------------- + #define RTL8723B_FW_IMG "rtl8723B\\rtl8723bfw.bin" + #define RTL8711B_PHY_REG "rtl8711B\\PHY_REG_1T.txt" + #define RTL8711B_PHY_RADIO_A "rtl8711B\\radio_a_1T.txt" + #define RTL8711B_PHY_RADIO_B "rtl8711B\\radio_b_1T.txt" + #define RTL8711B_TXPWR_TRACK "rtl8711B\\TxPowerTrack.txt" + #define RTL8711B_AGC_TAB "rtl8711B\\AGC_TAB_1T.txt" + #define RTL8711B_PHY_MACREG "rtl87195A\\MAC_REG.txt" + #define RTL8711B_PHY_REG_PG "rtl8711B\\PHY_REG_PG.txt" + #define RTL8711B_PHY_REG_MP "rtl8711B\\PHY_REG_MP.txt" + #define RTL8711B_TXPWR_LMT "rtl8711B\\TXPWR_LMT.txt" + +//--------------------------------------------------------------------- +// RTL8723BS From header +//--------------------------------------------------------------------- + + //#define Rtl8723B_FwImageArray Array_MP_8723B_FW_NIC + //#define Rtl8723B_FwImgArrayLength ArrayLength_MP_8723B_FW_NIC + //#define Rtl8723B_FwWoWImageArray Array_MP_8723B_FW_WoWLAN + //#define Rtl8723B_FwWoWImgArrayLength ArrayLength_MP_8723B_FW_WoWLAN + + #define Rtl8711B_PHY_REG_Array_PG Rtl8723SPHY_REG_Array_PG + #define Rtl8711B_PHY_REG_Array_PGLength Rtl8723SPHY_REG_Array_PGLength + +#if MP_DRIVER == 1 + #define Rtl8711B_FwBTImgArray Rtl8723BFwBTImgArray + #define Rtl8711B_FwBTImgArrayLength Rtl8723BFwBTImgArrayLength + + #define Rtl8711B_FwMPImageArray Rtl8723BFwMPImgArray + #define Rtl8711B_FwMPImgArrayLength Rtl8723BMPImgArrayLength + + #define Rtl8711B_PHY_REG_Array_MP Rtl8723B_PHYREG_Array_MP + #define Rtl8711B_PHY_REG_Array_MPLength Rtl8723B_PHYREG_Array_MPLength +#endif + +#endif // RTL8711B_SUPPORT + +#define FW_8711B_SIZE 0x8000 +#define FW_8711B_START_ADDRESS 0x1000 +#define FW_8711B_END_ADDRESS 0x1FFF //0x5FFF + +#define IS_FW_HEADER_EXIST_8711B(_pFwHdr) ((GET_FIRMWARE_HDR_SIGNATURE(_pFwHdr)&0xFFF0) == 0x10B0) + +typedef struct _RT_FIRMWARE { + FIRMWARE_SOURCE eFWSource; +#ifdef CONFIG_EMBEDDED_FWIMG + u8* szFwBuffer; +#else + u8 szFwBuffer[FW_8711B_SIZE]; +#endif + u32 ulFwLength; + +#ifdef CONFIG_EMBEDDED_FWIMG + u8* szBTFwBuffer; +#else + u8 szBTFwBuffer[FW_8711B_SIZE]; +#endif + u32 ulBTFwLength; + +#ifdef CONFIG_WOWLAN + u8* szWoWLANFwBuffer; + u32 ulWoWLANFwLength; +#endif //CONFIG_WOWLAN +} RT_FIRMWARE_8711B, *PRT_FIRMWARE_8711B; + +// +// This structure must be cared byte-ordering +// +// Added by tynli. 2009.12.04. +typedef struct _RT_8723B_FIRMWARE_HDR +{ + // 8-byte alinment required + + //--- LONG WORD 0 ---- + u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut + u8 Category; // AP/NIC and USB/PCI + u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions + u16 Version; // FW Version + u8 Subversion; // FW Subversion, default 0x00 + u16 Rsvd1; + + + //--- LONG WORD 1 ---- + u8 Month; // Release time Month field + u8 Date; // Release time Date field + u8 Hour; // Release time Hour field + u8 Minute; // Release time Minute field + u16 RamCodeSize; // The size of RAM code + u16 Rsvd2; + + //--- LONG WORD 2 ---- + u32 SvnIdx; // The SVN entry index + u32 Rsvd3; + + //--- LONG WORD 3 ---- + u32 Rsvd4; + u32 Rsvd5; +}RT_8723B_FIRMWARE_HDR, *PRT_8723B_FIRMWARE_HDR; + +#define DRIVER_EARLY_INT_TIME_8711B 0x05 // 5ms +#define BCN_DMA_ATIME_INT_TIME_8711B 0x02 // 2ms + +// for 8711B +// TX 32K, RX 16K, Page size 128B for TX, 8B for RX +#define PAGE_SIZE_TX_8711B 128 +#define PAGE_SIZE_RX_8711B 8 + +#define RX_DMA_SIZE_8711B 0x4000 // 16K +#define RX_DMA_RESERVED_SIZE_8711B 0x80 // 128B, reserved for tx report +#define RX_DMA_BOUNDARY_8711B (RX_DMA_SIZE_8711B - RX_DMA_RESERVED_SIZE_8711B - 1) + +// Note: We will divide number of page equally for each queue other than public queue! + +//For General Reserved Page Number(Beacon Queue is reserved page) +//Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 +#ifdef CONFIG_WLAN_HAL_TEST +#define BCNQ_PAGE_NUM_8711B 0x00 +#else +#define BCNQ_PAGE_NUM_8711B 0x08 +#endif + +#ifdef CONFIG_CONCURRENT_MODE +#define BCNQ1_PAGE_NUM_8711B 0x04 +#else +#define BCNQ1_PAGE_NUM_8711B 0x00 +#endif + +//For WoWLan , more reserved page +//ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2 +#ifdef CONFIG_WOWLAN +#define WOWLAN_PAGE_NUM_8711B 0x07 +#else +#define WOWLAN_PAGE_NUM_8711B 0x00 +#endif + +#ifdef CONFIG_WLAN_HAL_TEST +#define TX_TOTAL_PAGE_NUMBER_8711B (0xF8 - BCNQ_PAGE_NUM_8711B - BCNQ1_PAGE_NUM_8711B - WOWLAN_PAGE_NUM_8711B) +//#define TX_TOTAL_PAGE_NUMBER_8711B 0x40 +#define TX_PAGE_BOUNDARY_8711B (TX_TOTAL_PAGE_NUMBER_8711B + 1) +#else +#define TX_TOTAL_PAGE_NUMBER_8711B (0xFF - BCNQ_PAGE_NUM_8711B - BCNQ1_PAGE_NUM_8711B - WOWLAN_PAGE_NUM_8711B) +#define TX_PAGE_BOUNDARY_8711B (TX_TOTAL_PAGE_NUMBER_8711B + 1) +#endif + +#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER TX_TOTAL_PAGE_NUMBER_8711B +#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) + +// For Normal Chip Setting +// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8711B +#ifdef CONFIG_WLAN_HAL_TEST +#define NORMAL_PAGE_NUM_HPQ_8711B 0x10 +#define NORMAL_PAGE_NUM_LPQ_8711B 0x10 +#define NORMAL_PAGE_NUM_NPQ_8711B 0x10 +#else +#define NORMAL_PAGE_NUM_HPQ_8711B 0x0C +#define NORMAL_PAGE_NUM_LPQ_8711B 0x02 +#define NORMAL_PAGE_NUM_NPQ_8711B 0x02 +#endif + +#ifdef CONFIG_WLAN_HAL_TEST +#define WMM_NORMAL_PAGE_NUM_HPQ_8711B 0x10 +#define WMM_NORMAL_PAGE_NUM_LPQ_8711B 0x10 +#define WMM_NORMAL_PAGE_NUM_NPQ_8711B 0x10 +#else +// Note: For Normal Chip Setting, modify later +#define WMM_NORMAL_PAGE_NUM_HPQ_8711B 0x30 +#define WMM_NORMAL_PAGE_NUM_LPQ_8711B 0x20 +#define WMM_NORMAL_PAGE_NUM_NPQ_8711B 0x20 +#endif + +#include "HalVerDef.h" +#include "hal_com.h" + +#define LX_DMA_IMR_DISABLED 0 +#define FW_IMR_DISABLED 0 +#define WL_PMC_IMR_DISABLED 0 + + +//======================================================== +// EFUSE for BT definition +//======================================================== +#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512 +#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3 +#define EFUSE_BT_MAP_LEN 1024 // 1k bytes +#define EFUSE_BT_MAX_SECTION 128 // 1024/8 + +#define EFUSE_PROTECT_BYTES_BANK 16 + +#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type) + +// Description: Determine the types of C2H events that are the same in driver and Fw. +// Fisrt constructed by tynli. 2009.10.09. +typedef enum _C2H_EVT +{ + C2H_DBG = 0, + C2H_TSF = 1, + C2H_AP_RPT_RSP = 2, + C2H_CCX_TX_RPT = 3, // The FW notify the report of the specific tx packet. + C2H_BT_RSSI = 4, + C2H_BT_OP_MODE = 5, + C2H_EXT_RA_RPT = 6, + C2H_8723B_BT_INFO = 9, + C2H_HW_INFO_EXCH = 10, + C2H_8723B_BT_MP_INFO = 11, + MAX_C2HEVENT +} C2H_EVT; + +typedef _PACKED struct _C2H_EVT_HDR +{ + u8 CmdID; + u8 CmdLen; + u8 CmdSeq; +} C2H_EVT_HDR, *PC2H_EVT_HDR; + +typedef enum tag_Package_Definition +{ + PACKAGE_QFN32, + PACKAGE_QFN48_MCM, + PACKAGE_QFN48, + PACKAGE_QFN68, +}PACKAGE_TYPE_E; + +typedef enum tag_ChipID_Definition +{ + CHIPID_8710BN = 0xFF, /* PACKAGE_QFN32 */ + CHIPID_8710BU = 0xFE, /* PACKAGE_QFN48_MCM */ + CHIPID_8711BN = 0xFD, /* PACKAGE_QFN48 */ + CHIPID_8711BG = 0xFC, /* PACKAGE_QFN68 */ +}CHIP_TD_E; + + +#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) +#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) + +//======================================================== +// TXBD and RXBD definition +//======================================================== +#ifdef CONFIG_MP_INCLUDED // For MP Tx no idle +#define TX_VIQ_DESC_NUM 4 +#define TX_VOQ_DESC_NUM 4 +#define TX_BKQ_DESC_NUM 4 +#define TX_BEQ_DESC_NUM 32 +#else +#define TX_VIQ_DESC_NUM 4 +#define TX_VOQ_DESC_NUM 4 +#define TX_BKQ_DESC_NUM 4 +#define TX_BEQ_DESC_NUM 4 +#endif +#ifdef CONFIG_CONCURRENT_MODE +#define TX_BCNQ_DESC_NUM 4 +#else +#define TX_BCNQ_DESC_NUM 2 +#endif +#define TX_MGQ_DESC_NUM 4 +#define TX_H0Q_DESC_NUM 2 +#define TX_H1Q_DESC_NUM 2 +#define TX_H2Q_DESC_NUM 2 +#define TX_H3Q_DESC_NUM 2 +#define TX_H4Q_DESC_NUM 2 +#define TX_H5Q_DESC_NUM 2 +#define TX_H6Q_DESC_NUM 2 +#define TX_H7Q_DESC_NUM 2 +#define RX_Q_DESC_NUM 4 //16 Reduce rx desc number due to memory limitation + +#define SET_VIQ_DES_NUM (TX_VIQ_DESC_NUM<<16) +#define SET_VOQ_DES_NUM (TX_VOQ_DESC_NUM) +#define SET_RXQ_DES_NUM (RX_Q_DESC_NUM<<16) +#define SET_MGQ_DES_NUM (TX_MGQ_DESC_NUM) +#define SET_BKQ_DES_NUM (TX_BKQ_DESC_NUM<<16) +#define SET_BEQ_DES_NUM (TX_BEQ_DESC_NUM) +#define SET_H1Q_DES_NUM (TX_H1Q_DESC_NUM<<16) +#define SET_H0Q_DES_NUM (TX_H0Q_DESC_NUM) +#define SET_H3Q_DES_NUM (TX_H3Q_DESC_NUM<<16) +#define SET_H2Q_DES_NUM (TX_H2Q_DESC_NUM) +#define SET_H5Q_DES_NUM (TX_H5Q_DESC_NUM<<16) +#define SET_H4Q_DES_NUM (TX_H4Q_DESC_NUM) +#define SET_H7Q_DES_NUM (TX_H7Q_DESC_NUM<<16) +#define SET_H6Q_DES_NUM (TX_H6Q_DESC_NUM) + +#define TX_DESC_MODE 1 + +//0: 2 segment +//1: 4 segment +//2: 8 segment +//#define TX_DESC_MODE 2 + +#define MAX_TXBD_SEQMENT_NUM ((TX_DESC_MODE)? (4*TX_DESC_MODE): 2) +#define TXBD_SEGMENT_SIZE 8 + + + +typedef struct _RXBD_ELEMENT_ { + u32 Dword0; + u32 PhyAddr; +}RXBD_ELEMENT,*PRXBD_ELEMENT; + + +typedef struct _TXBD_ELEMENT_ { + u32 Dword0; + u32 AddrLow; +}TXBD_ELEMENT,*PTXBD_ELEMENT; + +typedef struct _LX_DMA_ELEMENT_ { + u32 QueueTRxBdBase; + u32 HwIndex; + u32 HostIndex; + u32 AvaliableCnt; +}LX_DMA_ELEMENT, *PLX_DMA_ELEMENT; +#if 1 + +typedef enum _LX_DMA_QUEUE_TYPE_{ + VO_QUEUE = 0, + VI_QUEUE = 1, + BE_QUEUE = 2, + BK_QUEUE = 3, + MG_QUEUE = 4, + RX_QUEUE = 5, + H0_QUEUE = 6, + H1_QUEUE = 7, + H2_QUEUE = 8, + H3_QUEUE = 9, + H4_QUEUE = 10, + H5_QUEUE = 11, + H6_QUEUE = 12, + H7_QUEUE = 13, + BCN_QUEUE = 14, + MAX_TX_QUEUE = 15, + ERROR_QUEUE = 16, +}LX_DMA_QUEUE_TYPE, *PLX_DMA_QUEUE_TYPE; + +typedef struct _TX_FREE_QUEUE_ { + _queue FreeQueue; + u32 Qlen; +}TX_FREE_QUEUE, *PTX_FREE_QUEUE; + +typedef struct _LX_DMA_MANAGER_ { + LX_DMA_ELEMENT QueueTRxBd[MAX_TX_QUEUE]; + u32 QueueMaxValue[MAX_TX_QUEUE]; + u32 RxBdSkb[RX_Q_DESC_NUM]; + u32 RxLen; + u32 RemainLen; + u16 RxAggregateNum; + u16 RxExpectTag; + u16 RxSegFlow; + u16 Flagls; + TX_FREE_QUEUE TxFreeQueue[MAX_TX_QUEUE]; + +}LX_DMA_MANAGER, *PLX_DMA_MANAGER; + +#else + +typedef struct _LX_DMA_MANAGER_ { + u32 *pVoqTXBD; + u32 *pViqTXBD; + u32 *pBeqTXBD; + u32 *pBkqTXBD; + u32 *pBcnqTXBD; + u32 *pMgqTXBD; + u32 *pH0qTXBD; + u32 *pH1qTXBD; + u32 *pH2qTXBD; + u32 *pH3qTXBD; + u32 *pH4qTXBD; + u32 *pH5qTXBD; + u32 *pH6qTXBD; + u32 *pH7qTXBD; + u32 *pExViqTXBD; + u32 *pExVoqTXBD; + u32 *pExBeqTXBD; + u32 *pExBkqTXBD; + u32 *pExMgqTXBD; + u32 *pRXBD; +// u4Byte RxAggBufEntry[RX_Q_DESC_NUM]; +// u4Byte RxAggLenEntry[RX_Q_DESC_NUM]; + u32 RxLen; + u32 RemainLen; + u16 ViqTxWritePoint; + u16 ViqTxReadPoint; + u16 VoqTxWritePoint; + u16 VoqTxReadPoint; + u16 BeqTxWritePoint; + u16 BeqTxReadPoint; + u16 BkqTxWritePoint; + u16 BkqTxReadPoint; + u16 RxWritePoint; + u16 RxReadPoint; + u16 RxAggregateNum; + u16 RxExpectTag; + u16 RxSegFlow; + u16 Flagls; +}LX_DMA_MANAGER, *PLX_DMA_MANAGER; +#endif + +// rtl8723a_hal_init.c +s32 rtl8711b_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw); +void rtl8711b_FirmwareSelfReset(PADAPTER padapter); +void rtl8711b_InitializeFirmwareVars(PADAPTER padapter); + +void rtl8711b_InitAntenna_Selection(PADAPTER padapter); +void rtl8711b_DeinitAntenna_Selection(PADAPTER padapter); +void rtl8711b_CheckAntenna_Selection(PADAPTER padapter); +void rtl8711b_init_default_value(PADAPTER padapter); + +s32 rtl8711b_InitLLTTable(PADAPTER padapter); + +s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU); +s32 CardDisableWithoutHWSM(PADAPTER padapter); + +// EFuse +//u8 GetEEPROMSize8711b(PADAPTER padapter); +void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent); +void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo); +void Hal_EfuseParseTxPowerInfo_8711B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail); +void Hal_EfuseParseBTCoexistInfo_8711B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseEEPROMVer_8711B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseChnlPlan_8711B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseCustomerID_8711B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseAntennaDiversity_8711B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseXtal_8711B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail); +void Hal_EfuseParseThermalMeter_8711B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail); + +#ifdef CONFIG_C2H_PACKET_EN +void C2HPacketHandler_8711B(PADAPTER padapter, u8 *pbuffer, u16 length); +#endif + +u8 rtw_flash_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_flash_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_config_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data, u8 efuse); +u8 rtw_config_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data, u8 efuse); + +void rtl8711b_set_hal_ops(struct hal_ops *pHalFunc); +void lxbus_set_intf_ops(struct _io_ops *pops); +void SetHwReg8711B(PADAPTER padapter, u8 variable, u8 *val); +void GetHwReg8711B(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHalDefVar8711B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); +u8 GetHalDefVar8711B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); +void SetHalODMVar8711B( PADAPTER Adapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet); +void GetHalODMVar8711B(PADAPTER Adapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet); + +// register +void rtl8711b_InitBeaconParameters(PADAPTER padapter); +void rtl8711b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode); +void _InitBurstPktLen_8711BB(PADAPTER Adapter); +#ifdef CONFIG_WOWLAN +void _8051Reset8711b(PADAPTER padapter); +void Hal_DetectWoWMode(PADAPTER pAdapter); +#endif //CONFIG_WOWLAN + +void rtl8711b_start_thread(_adapter *padapter); +void rtl8711b_stop_thread(_adapter *padapter); + +#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) +void rtl8711bb_init_checkbthang_workqueue(_adapter * adapter); +void rtl8711bb_free_checkbthang_workqueue(_adapter * adapter); +void rtl8711bb_cancle_checkbthang_workqueue(_adapter * adapter); +void rtl8711bb_hal_check_bt_hang(_adapter * adapter); +#endif + +#ifdef CONFIG_WOWLAN +void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip); +void rtw_get_sec_iv(PADAPTER padapter, u8*pcur_dot11txpn, u8 *StaAddr); +#endif + +u32 rtl8710b_wlan_suspend(u32 expected_idle_time, void *param); +u32 rtl8710b_wlan_late_resume(u32 expected_idle_time, void *param); +u32 rtl8710b_wlan_resume(u32 expected_idle_time, void *param); + +#ifdef CONFIG_GPIO_WAKEUP +void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue); +#endif + +void CCX_FwC2HTxRpt_8711B(PADAPTER padapter, u8 *pdata, u8 len); +s32 c2h_id_filter_ccx_8711B(u8 *buf); +s32 c2h_handler_8711B(PADAPTER padapter, u8 *pC2hEvent); +u8 MRateToHwRate8723B(u8 rate); +u8 HwRateToMRate8723B(u8 rate); + +#ifdef CONFIG_RF_GAIN_OFFSET +void Hal_ReadRFGainOffset(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail); +#endif //CONFIG_RF_GAIN_OFFSET + + +//1TODO: Chris +#if 1 + +//============= +// [1] Rx Buffer Descriptor (for PCIE) buffer descriptor architecture +//DWORD 0 +#define SET_RX_BUFFER_DESC_DATA_LENGTH_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 0, 14, __Value) +#define SET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc,__Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 14, 1, __Value) +#define SET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 15, 1, __Value) +#define SET_RX_BUFFER_DESC_RX_TAG_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 16, 13, __Value) + +#define GET_RX_BUFFER_DESC_OWN_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 31, 1) +#define GET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 14, 1) +#define GET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 15, 1) +#define GET_RX_BUFFER_DESC_RX_TAG_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 16, 13) +#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc)LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 14) + + +//DWORD 1 +#define SET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc+4, 0, 32, __Value) +#define GET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+4, 0, 32) + +//DWORD 2 +#define SET_RX_BUFFER_PHYSICAL_HIGH_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc+8, 0, 32, __Value) + + +//=====Tx Desc Buffer content + +// config element for each tx buffer +/* +#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 0, 16, __Valeu) +#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 31, 1, __Valeu) +#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+4, 0, 32, __Valeu) +#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu) +*/ +#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu) +#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu) +#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu) +#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu) + +// Dword 0 +#define SET_TX_BUFF_DESC_LEN_0_92E(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Valeu) +#define SET_TX_BUFF_DESC_PSB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) +#define SET_TX_BUFF_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) +// Dword 1 +#define SET_TX_BUFF_DESC_ADDR_LOW_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value) +#define GET_TX_DESC_TX_BUFFER_ADDRESS_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0,32) + + +// Dword 2 +#define SET_TX_BUFF_DESC_ADDR_HIGH_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value) +// Dword 3, RESERVED + + +#define SET_TX_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) + +#endif + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_ap.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_ap.h new file mode 100644 index 0000000..1a6e5d1 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_ap.h @@ -0,0 +1,65 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_AP_H_ +#define __RTW_AP_H_ + +//#include + + +#ifdef CONFIG_AP_MODE + +//external function +extern void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta); +extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta); + + +void init_mlme_ap_info(_adapter *padapter); +void free_mlme_ap_info(_adapter *padapter); +//void update_BCNTIM(_adapter *padapter); +void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len); +void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index); +void update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx); +void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level); +void expire_timeout_chk(_adapter *padapter); +void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta); +int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len); +void rtw_set_macaddr_acl(_adapter *padapter, int mode); +int rtw_acl_add_sta(_adapter *padapter, u8 *addr); +int rtw_acl_remove_sta(_adapter *padapter, u8 *addr); +int rtw_generate_bcn_ie(_adapter *adapter, u8 *ssid, u16 ssid_len, u8 *ie); +#if USE_DEDICATED_BCN_TX +struct xmit_frame *alloc_bcn_xmitframe(_adapter *padapter); +#endif + +#ifdef CONFIG_NATIVEAP_MLME +void associated_clients_update(_adapter *padapter, u8 updated); +void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta); +u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta); +void sta_info_update(_adapter *padapter, struct sta_info *psta); +void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta); +u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, u16 reason); +int rtw_sta_flush(_adapter *padapter); +void start_ap_mode(_adapter *padapter); +void stop_ap_mode(_adapter *padapter); +#endif +#endif //end of CONFIG_AP_MODE + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_byteorder.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_byteorder.h new file mode 100644 index 0000000..2f3b6f6 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_byteorder.h @@ -0,0 +1,53 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTL871X_BYTEORDER_H_ +#define _RTL871X_BYTEORDER_H_ + +#include + +#if defined (CONFIG_LITTLE_ENDIAN) && defined (CONFIG_BIG_ENDIAN) +#error "Shall be CONFIG_LITTLE_ENDIAN or CONFIG_BIG_ENDIAN, but not both!\n" +#endif + +#if defined (CONFIG_LITTLE_ENDIAN) +#ifndef CONFIG_PLATFORM_MSTAR389 +# include +#endif +#elif defined (CONFIG_BIG_ENDIAN) +# include +#else +# error "Must be LITTLE/BIG Endian Host" +#endif + +#ifdef CONFIG_BIG_ENDIAN +#define _htons(x) (x) +#define _ntohs(x) (x) +#define _htonl(x) (x) +#define _ntohl(x) (x) +#else /* !CONFIG_BIG_ENDIAN */ +u16 _htons(u16 x); +u16 _ntohs(u16 x); +u32 _htonl(u32 x); +u32 _ntohl(u32 x); +#endif /* CONFIG_BIG_ENDIAN */ + + +#endif /* _RTL871X_BYTEORDER_H_ */ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_cmd.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_cmd.h new file mode 100644 index 0000000..79b6ce1 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_cmd.h @@ -0,0 +1,1184 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_CMD_H_ +#define __RTW_CMD_H_ + +#include +#include + +#define C2H_MEM_SZ (16*1024) +//#define CMD_RSP_BUF 0 +//#define CMD_DBG 0 + +#ifndef CONFIG_RTL8711FW + + #include // + #include // + + #define FREE_CMDOBJ_SZ 128 + + #define MAX_CMDSZ 1024 + #define MAX_RSPSZ 512 + #define MAX_EVTSZ 1024 + +#if defined(PLATFORM_OS_CE) || defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) + #define CMDBUFF_ALIGN_SZ 4 +#else + #define CMDBUFF_ALIGN_SZ 512 +#endif + + struct cmd_obj { + _adapter *padapter; + u16 cmdcode; + u8 res; + u8 *parmbuf; + u32 cmdsz; + u8 *rsp; + u32 rspsz; + //_sema cmd_sem; + _list list; + }; + + struct cmd_priv { + //_sema cmd_done_sema; + _queue cmd_queue; +#ifdef CMD_BUF + u8 *cmd_buf; //shall be non-paged, and 4 bytes aligned + u8 *cmd_allocated_buf; +#endif +#ifdef CMD_RSP_BUF + u8 *rsp_buf; //shall be non-paged, and 4 bytes aligned + u8 *rsp_allocated_buf; + u32 rsp_cnt; +#endif +#ifdef CMD_DBG + u8 cmd_seq; + u32 cmd_issued_cnt; + u32 cmd_done_cnt; +#endif + u8 cmdthd_running; + _adapter *padapter; + }; + +#ifdef CONFIG_EVENT_THREAD_MODE + struct evt_obj { + u16 evtcode; + u8 res; + u8 *parmbuf; + u32 evtsz; + _list list; + }; +#endif + + struct evt_priv { +#ifdef CONFIG_EVENT_THREAD_MODE + _sema evt_notify; + _sema terminate_evtthread_sema; + _queue evt_queue; +#endif + +#ifdef CONFIG_H2CLBK + _sema lbkevt_done; + u8 lbkevt_limit; + u8 lbkevt_num; + u8 *cmdevt_parm; +#endif + ATOMIC_T event_seq; + u8 *evt_buf; //shall be non-paged, and 4 bytes aligned + u8 *evt_allocated_buf; + u32 evt_done_cnt; +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + u8 *c2h_mem; + u8 *allocated_c2h_mem; +#ifdef PLATFORM_OS_XP + PMDL pc2h_mdl; +#endif +#endif + + }; + +#define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \ +do {\ + rtw_init_listhead(&pcmd->list);\ + pcmd->cmdcode = code;\ + pcmd->parmbuf = (u8 *)(pparm);\ + pcmd->cmdsz = sizeof (*pparm);\ + pcmd->rsp = NULL;\ + pcmd->rspsz = 0;\ +} while(0) + +extern u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj); +extern struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv); +extern void rtw_free_cmd_obj(struct cmd_obj *pcmd); + +#ifdef CONFIG_EVENT_THREAD_MODE +extern u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj); +extern struct evt_obj *rtw_dequeue_evt(_queue *queue); +extern void rtw_free_evt_obj(struct evt_obj *pcmd); +#endif + +thread_return rtw_cmd_thread(thread_context context); + +extern u32 rtw_init_cmd_priv (struct cmd_priv *pcmdpriv); +extern void rtw_free_cmd_priv (struct cmd_priv *pcmdpriv); + +extern u32 rtw_init_evt_priv (struct evt_priv *pevtpriv); +extern void rtw_free_evt_priv (struct evt_priv *pevtpriv); +extern void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv); +extern void rtw_evt_notify_isr(struct evt_priv *pevtpriv); +#ifdef CONFIG_P2P +u8 p2p_protocol_wk_cmd(_adapter*padapter, int intCmdType ); +#endif //CONFIG_P2P + +#else /* CONFIG_RTL8711FW */ + #include +#endif /* CONFIG_RTL8711FW */ + +enum rtw_drvextra_cmd_id +{ + NONE_WK_CID, + DYNAMIC_CHK_WK_CID, + DM_CTRL_WK_CID, + PBC_POLLING_WK_CID, + POWER_SAVING_CTRL_WK_CID,//IPS,AUTOSuspend + LPS_CTRL_WK_CID, + ANT_SELECT_WK_CID, + P2P_PS_WK_CID, + //P2P_PROTO_WK_CID, + CHECK_HIQ_WK_CID,//for softap mode, check hi queue if empty + INTEl_WIDI_WK_CID, + C2H_WK_CID, + RTP_TIMER_CFG_WK_CID, + MAX_WK_CID +}; + +enum LPS_CTRL_TYPE +{ + LPS_CTRL_SCAN=0, + LPS_CTRL_JOINBSS=1, + LPS_CTRL_CONNECT=2, + LPS_CTRL_DISCONNECT=3, + LPS_CTRL_SPECIAL_PACKET=4, + LPS_CTRL_LEAVE=5, +}; + +enum RFINTFS { + SWSI, + HWSI, + HWPI, +}; + +/* +Caller Mode: Infra, Ad-HoC(C) + +Notes: To enter USB suspend mode + +Command Mode + +*/ +struct usb_suspend_parm { + u32 action;// 1: sleep, 0:resume +}; + +/* +Caller Mode: Infra, Ad-HoC + +Notes: To join a known BSS. + +Command-Event Mode + +*/ + +/* +Caller Mode: Infra, Ad-Hoc + +Notes: To join the specified bss + +Command Event Mode + +*/ +struct joinbss_parm { + WLAN_BSSID_EX network; +}; + +/* +Caller Mode: Infra, Ad-HoC(C) + +Notes: To disconnect the current associated BSS + +Command Mode + +*/ +struct disconnect_parm { + u32 rsvd; +}; + +/* +Caller Mode: AP, Ad-HoC(M) + +Notes: To create a BSS + +Command Mode +*/ +struct createbss_parm { + WLAN_BSSID_EX network; +}; + +/* +Caller Mode: AP, Ad-HoC, Infra + +Notes: To set the NIC mode of RTL8711 + +Command Mode + +The definition of mode: + +#define IW_MODE_AUTO 0 // Let the driver decides which AP to join +#define IW_MODE_ADHOC 1 // Single cell network (Ad-Hoc Clients) +#define IW_MODE_INFRA 2 // Multi cell network, roaming, .. +#define IW_MODE_MASTER 3 // Synchronisation master or Access Point +#define IW_MODE_REPEAT 4 // Wireless Repeater (forwarder) +#define IW_MODE_SECOND 5 // Secondary master/repeater (backup) +#define IW_MODE_MONITOR 6 // Passive monitor (listen only) + +*/ +struct setopmode_parm { + u8 mode; + u8 rsvd[3]; +}; + +/* +Caller Mode: AP, Ad-HoC, Infra + +Notes: To ask RTL8711 performing site-survey + +Command-Event Mode + +*/ + +#if defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) +#define RTW_SSID_SCAN_AMOUNT 1 //Reduce ssid scan amount due to memory limitation - Alex Fang +#else +#define RTW_SSID_SCAN_AMOUNT 9 // for WEXT_CSCAN_AMOUNT 9 +#endif + +struct sitesurvey_parm { + sint scan_mode; //active: 1, passive: 0 + sint bsslimit; // 1 ~ 48 + // for up to 9 probreq with specific ssid + NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; +}; + +/* +Caller Mode: Any + +Notes: To set the auth type of RTL8711. open/shared/802.1x + +Command Mode + +*/ +struct setauth_parm { + u8 mode; //0: legacy open, 1: legacy shared 2: 802.1x + u8 _1x; //0: PSK, 1: TLS + u8 rsvd[2]; +}; + +/* +Caller Mode: Infra + +a. algorithm: wep40, wep104, tkip & aes +b. keytype: grp key/unicast key +c. key contents + +when shared key ==> keyid is the camid +when 802.1x ==> keyid [0:1] ==> grp key +when 802.1x ==> keyid > 2 ==> unicast key + +*/ +struct setkey_parm { + u8 algorithm; // encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 + u8 keyid; + u8 grpkey; // 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x + u8 set_tx; // 1: main tx key for wep. 0: other key. + u8 key[16]; // this could be 40 or 104 +}; + +/* +When in AP or Ad-Hoc mode, this is used to +allocate an sw/hw entry for a newly associated sta. + +Command + +when shared key ==> algorithm/keyid + +*/ +struct set_stakey_parm { + u8 addr[ETH_ALEN]; + u8 algorithm; + u8 id;// currently for erasing cam entry if algorithm == _NO_PRIVACY_ + u8 key[16]; +}; + +struct set_stakey_rsp { + u8 addr[ETH_ALEN]; + u8 keyid; + u8 rsvd; +}; + +/* +Caller Ad-Hoc/AP + +Command -Rsp(AID == CAMID) mode + +This is to force fw to add an sta_data entry per driver's request. + +FW will write an cam entry associated with it. + +*/ +struct set_assocsta_parm { + u8 addr[ETH_ALEN]; +}; + +struct set_assocsta_rsp { + u8 cam_id; + u8 rsvd[3]; +}; + +/* + Caller Ad-Hoc/AP + + Command mode + + This is to force fw to del an sta_data entry per driver's request + + FW will invalidate the cam entry associated with it. + +*/ +struct del_assocsta_parm { + u8 addr[ETH_ALEN]; +}; + +/* +Caller Mode: AP/Ad-HoC(M) + +Notes: To notify fw that given staid has changed its power state + +Command Mode + +*/ +struct setstapwrstate_parm { + u8 staid; + u8 status; + u8 hwaddr[6]; +}; + +/* +Caller Mode: Any + +Notes: To setup the basic rate of RTL8711 + +Command Mode + +*/ +struct setbasicrate_parm { + u8 basicrates[NumRates]; +}; + +/* +Caller Mode: Any + +Notes: To read the current basic rate + +Command-Rsp Mode + +*/ +struct getbasicrate_parm { + u32 rsvd; +}; + +struct getbasicrate_rsp { + u8 basicrates[NumRates]; +}; + +/* +Caller Mode: Any + +Notes: To setup the data rate of RTL8711 + +Command Mode + +*/ +struct setdatarate_parm { +#ifdef MP_FIRMWARE_OFFLOAD + u32 curr_rateidx; +#else + u8 mac_id; + u8 datarates[NumRates]; +#endif +}; + +/* +Caller Mode: Any + +Notes: To read the current data rate + +Command-Rsp Mode + +*/ +struct getdatarate_parm { + u32 rsvd; + +}; +struct getdatarate_rsp { + u8 datarates[NumRates]; +}; + + +/* +Caller Mode: Any +AP: AP can use the info for the contents of beacon frame +Infra: STA can use the info when sitesurveying +Ad-HoC(M): Like AP +Ad-HoC(C): Like STA + + +Notes: To set the phy capability of the NIC + +Command Mode + +*/ + +struct setphyinfo_parm { + struct regulatory_class class_sets[NUM_REGULATORYS]; + u8 status; +}; + +struct getphyinfo_parm { + u32 rsvd; +}; + +struct getphyinfo_rsp { + struct regulatory_class class_sets[NUM_REGULATORYS]; + u8 status; +}; + +/* +Caller Mode: Any + +Notes: To set the channel/modem/band +This command will be used when channel/modem/band is changed. + +Command Mode + +*/ +struct setphy_parm { + u8 rfchannel; + u8 modem; +}; + +/* +Caller Mode: Any + +Notes: To get the current setting of channel/modem/band + +Command-Rsp Mode + +*/ +struct getphy_parm { + u32 rsvd; + +}; +struct getphy_rsp { + u8 rfchannel; + u8 modem; +}; + +struct readBB_parm { + u8 offset; +}; +struct readBB_rsp { + u8 value; +}; + +struct readTSSI_parm { + u8 offset; +}; +struct readTSSI_rsp { + u8 value; +}; + +struct writeBB_parm { + u8 offset; + u8 value; +}; + +struct readRF_parm { + u8 offset; +}; +struct readRF_rsp { + u32 value; +}; + +struct writeRF_parm { + u32 offset; + u32 value; +}; + +struct getrfintfs_parm { + u8 rfintfs; +}; + + +struct Tx_Beacon_param +{ + WLAN_BSSID_EX network; +}; + +/* + Notes: This command is used for H2C/C2H loopback testing + + mac[0] == 0 + ==> CMD mode, return H2C_SUCCESS. + The following condition must be ture under CMD mode + mac[1] == mac[4], mac[2] == mac[3], mac[0]=mac[5]= 0; + s0 == 0x1234, s1 == 0xabcd, w0 == 0x78563412, w1 == 0x5aa5def7; + s2 == (b1 << 8 | b0); + + mac[0] == 1 + ==> CMD_RSP mode, return H2C_SUCCESS_RSP + + The rsp layout shall be: + rsp: parm: + mac[0] = mac[5]; + mac[1] = mac[4]; + mac[2] = mac[3]; + mac[3] = mac[2]; + mac[4] = mac[1]; + mac[5] = mac[0]; + s0 = s1; + s1 = swap16(s0); + w0 = swap32(w1); + b0 = b1 + s2 = s0 + s1 + b1 = b0 + w1 = w0 + + mac[0] == 2 + ==> CMD_EVENT mode, return H2C_SUCCESS + The event layout shall be: + event: parm: + mac[0] = mac[5]; + mac[1] = mac[4]; + mac[2] = event's sequence number, starting from 1 to parm's marc[3] + mac[3] = mac[2]; + mac[4] = mac[1]; + mac[5] = mac[0]; + s0 = swap16(s0) - event.mac[2]; + s1 = s1 + event.mac[2]; + w0 = swap32(w0); + b0 = b1 + s2 = s0 + event.mac[2] + b1 = b0 + w1 = swap32(w1) - event.mac[2]; + + parm->mac[3] is the total event counts that host requested. + + + event will be the same with the cmd's param. + +*/ + +#ifdef CONFIG_H2CLBK + +struct seth2clbk_parm { + u8 mac[6]; + u16 s0; + u16 s1; + u32 w0; + u8 b0; + u16 s2; + u8 b1; + u32 w1; +}; + +struct geth2clbk_parm { + u32 rsv; +}; + +struct geth2clbk_rsp { + u8 mac[6]; + u16 s0; + u16 s1; + u32 w0; + u8 b0; + u16 s2; + u8 b1; + u32 w1; +}; + +#endif /* CONFIG_H2CLBK */ + +// CMD param Formart for driver extra cmd handler +struct drvextra_cmd_parm { + int ec_id; //extra cmd id + int type_size; // Can use this field as the type id or command size + unsigned char *pbuf; +}; + +#ifdef CONFIG_P2P_NEW +// CMD param Formart for p2p cmd handler +struct p2p_cmd_parm { + int id; //p2p cmd id + int type_size; // Can use this field as the type id or command size + unsigned char *pbuf; +}; +#endif +/*------------------- Below are used for RF/BB tunning ---------------------*/ + +struct setantenna_parm { + u8 tx_antset; + u8 rx_antset; + u8 tx_antenna; + u8 rx_antenna; +}; + +struct enrateadaptive_parm { + u32 en; +}; + +struct settxagctbl_parm { + u32 txagc[MAX_RATES_LENGTH]; +}; + +struct gettxagctbl_parm { + u32 rsvd; +}; +struct gettxagctbl_rsp { + u32 txagc[MAX_RATES_LENGTH]; +}; + +struct setagcctrl_parm { + u32 agcctrl; // 0: pure hw, 1: fw +}; + + +struct setssup_parm { + u32 ss_ForceUp[MAX_RATES_LENGTH]; +}; + +struct getssup_parm { + u32 rsvd; +}; +struct getssup_rsp { + u8 ss_ForceUp[MAX_RATES_LENGTH]; +}; + + +struct setssdlevel_parm { + u8 ss_DLevel[MAX_RATES_LENGTH]; +}; + +struct getssdlevel_parm { + u32 rsvd; +}; +struct getssdlevel_rsp { + u8 ss_DLevel[MAX_RATES_LENGTH]; +}; + +struct setssulevel_parm { + u8 ss_ULevel[MAX_RATES_LENGTH]; +}; + +struct getssulevel_parm { + u32 rsvd; +}; +struct getssulevel_rsp { + u8 ss_ULevel[MAX_RATES_LENGTH]; +}; + + +struct setcountjudge_parm { + u8 count_judge[MAX_RATES_LENGTH]; +}; + +struct getcountjudge_parm { + u32 rsvd; +}; +struct getcountjudge_rsp { + u8 count_judge[MAX_RATES_LENGTH]; +}; + + +struct setratable_parm { + u8 ss_ForceUp[NumRates]; + u8 ss_ULevel[NumRates]; + u8 ss_DLevel[NumRates]; + u8 count_judge[NumRates]; +}; + +struct getratable_parm { + uint rsvd; +}; +struct getratable_rsp { + u8 ss_ForceUp[NumRates]; + u8 ss_ULevel[NumRates]; + u8 ss_DLevel[NumRates]; + u8 count_judge[NumRates]; +}; + + +//to get TX,RX retry count +struct gettxretrycnt_parm{ + unsigned int rsvd; +}; +struct gettxretrycnt_rsp{ + unsigned long tx_retrycnt; +}; + +struct getrxretrycnt_parm{ + unsigned int rsvd; +}; +struct getrxretrycnt_rsp{ + unsigned long rx_retrycnt; +}; + +//to get BCNOK,BCNERR count +struct getbcnokcnt_parm{ + unsigned int rsvd; +}; +struct getbcnokcnt_rsp{ + unsigned long bcnokcnt; +}; + +struct getbcnerrcnt_parm{ + unsigned int rsvd; +}; +struct getbcnerrcnt_rsp{ + unsigned long bcnerrcnt; +}; + +// to get current TX power level +struct getcurtxpwrlevel_parm{ + unsigned int rsvd; +}; +struct getcurtxpwrlevel_rsp{ + unsigned short tx_power; +}; + +///TODO +#if 0 + +struct setprobereqextraie_parm { + unsigned char e_id; + unsigned char ie_len; + unsigned char ie[0]; +}; + +struct setassocreqextraie_parm { + unsigned char e_id; + unsigned char ie_len; + unsigned char ie[0]; +}; + +struct setproberspextraie_parm { + unsigned char e_id; + unsigned char ie_len; + unsigned char ie[0]; +}; + +struct setassocrspextraie_parm { + unsigned char e_id; + unsigned char ie_len; + unsigned char ie[0]; +}; + +#endif //#if 0 + +struct addBaReq_parm +{ + unsigned int tid; + u8 addr[ETH_ALEN]; +}; + +/*H2C Handler index: 46 */ +struct SetChannel_parm +{ + u32 curr_ch; +}; + +#ifdef MP_FIRMWARE_OFFLOAD +/*H2C Handler index: 47 */ +struct SetTxPower_parm +{ + u8 TxPower; +}; + +/*H2C Handler index: 48 */ +struct SwitchAntenna_parm +{ + u16 antenna_tx; + u16 antenna_rx; +// R_ANTENNA_SELECT_CCK cck_txrx; + u8 cck_txrx; +}; + +/*H2C Handler index: 49 */ +struct SetCrystalCap_parm +{ + u32 curr_crystalcap; +}; + +/*H2C Handler index: 50 */ +struct SetSingleCarrierTx_parm +{ + u8 bStart; +}; + +/*H2C Handler index: 51 */ +struct SetSingleToneTx_parm +{ + u8 bStart; + u8 curr_rfpath; +}; + +/*H2C Handler index: 52 */ +struct SetCarrierSuppressionTx_parm +{ + u8 bStart; + u32 curr_rateidx; +}; + +/*H2C Handler index: 53 */ +struct SetContinuousTx_parm +{ + u8 bStart; + u8 CCK_flag; /*1:CCK 2:OFDM*/ + u32 curr_rateidx; +}; + +/*H2C Handler index: 54 */ +struct SwitchBandwidth_parm +{ + u8 curr_bandwidth; +}; + +#endif /* MP_FIRMWARE_OFFLOAD */ + +/*H2C Handler index: 59 */ +struct SetChannelPlan_param +{ + u8 channel_plan; +}; + +//TODO +#if 0 +/*H2C Handler index: 60 */ +struct LedBlink_param +{ + PLED_871x pLed; +}; +#endif //#if 0 + +/*H2C Handler index: 61 */ +struct SetChannelSwitch_param +{ + u8 new_ch_no; +}; + +/*H2C Handler index: 62 */ +struct TDLSoption_param +{ + u8 addr[ETH_ALEN]; + u8 option; +}; + +#define GEN_CMD_CODE(cmd) cmd ## _CMD_ + + +/* + +Result: +0x00: success +0x01: sucess, and check Response. +0x02: cmd ignored due to duplicated sequcne number +0x03: cmd dropped due to invalid cmd code +0x04: reserved. + +*/ + +#define H2C_RSP_OFFSET 512 + +#define H2C_SUCCESS 0x00 +#define H2C_SUCCESS_RSP 0x01 +#define H2C_DUPLICATED 0x02 +#define H2C_DROPPED 0x03 +#define H2C_PARAMETERS_ERROR 0x04 +#define H2C_REJECTED 0x05 +#define H2C_CMD_OVERFLOW 0x06 +#define H2C_RESERVED 0x07 + +extern u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr); +extern u8 rtw_setstandby_cmd(_adapter *padapter, uint action); +extern u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *pssid, int ssid_max_num); +extern u8 rtw_createbss_cmd(_adapter *padapter); +extern u8 rtw_createbss_cmd_ex(_adapter *padapter, unsigned char *pbss, unsigned int sz); +extern u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch); +extern u8 rtw_setstakey_cmd(_adapter *padapter, u8 *psta, u8 unicast_key); +extern u8 rtw_clearstakey_cmd(_adapter *padapter, u8 *psta, u8 entry, u8 enqueue); +extern u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network* pnetwork); +extern u8 rtw_disassoc_cmd(_adapter *padapter); +extern u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype); +extern u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset); +extern u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset); +extern u8 rtw_setbbreg_cmd(_adapter * padapter, u8 offset, u8 val); +extern u8 rtw_setrfreg_cmd(_adapter * padapter, u8 offset, u32 val); +extern u8 rtw_getbbreg_cmd(_adapter * padapter, u8 offset, u8 * pval); +extern u8 rtw_getrfreg_cmd(_adapter * padapter, u8 offset, u8 * pval); +extern u8 rtw_setrfintfs_cmd(_adapter *padapter, u8 mode); +extern u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table); +extern u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval); + +extern u8 rtw_gettssi_cmd(_adapter *padapter, u8 offset,u8 *pval); +extern u8 rtw_setfwdig_cmd(_adapter*padapter, u8 type); +extern u8 rtw_setfwra_cmd(_adapter*padapter, u8 type); + +extern u8 rtw_addbareq_cmd(_adapter*padapter, u8 tid, u8 *addr); + +extern u8 rtw_dynamic_chk_wk_cmd(_adapter *adapter); +#ifdef CONFIG_P2P_NEW +u8 rtw_p2p_cmd(_adapter*padapter, int subid); +#endif +u8 rtw_lps_ctrl_wk_cmd(_adapter*padapter, u8 lps_ctrl_type, u8 enqueue); +#if (RATE_ADAPTIVE_SUPPORT==1) +u8 rtw_rpt_timer_cfg_cmd(_adapter*padapter, u16 minRptTime); +#endif + +#ifdef CONFIG_ANTENNA_DIVERSITY +extern u8 rtw_antenna_select_cmd(_adapter*padapter, u8 antenna,u8 enqueue); +#endif + +extern u8 rtw_ps_cmd(_adapter*padapter); + +#ifdef CONFIG_AP_MODE +u8 rtw_chk_hi_queue_cmd(_adapter*padapter); +#endif + +extern u8 rtw_set_chplan_cmd(_adapter*padapter, u8 chplan, u8 enaueue); +//TODO +//extern u8 rtw_led_blink_cmd(_adapter*padapter, PLED_871x pLed); +extern u8 rtw_set_csa_cmd(_adapter*padapter, u8 new_ch_no); +extern u8 rtw_tdls_cmd(_adapter*padapter, u8 *addr, u8 option); + +extern u8 rtw_c2h_wk_cmd(PADAPTER padapter); + +u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf); +#ifdef CONFIG_P2P_NEW +u8 rtw_p2p_cmd_hdl(_adapter *padapter, unsigned char *pbuf); +#endif +extern void rtw_survey_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_createbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_getbbrfreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_readtssi_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd); + +extern void rtw_setstaKey_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_getrttbl_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_set_channel_plan_cmd_callback(_adapter* padapter, struct cmd_obj *pcmd); + + +struct _cmd_callback { + u32 cmd_code; + void (*callback)(_adapter *padapter, struct cmd_obj *cmd); +}; + +enum rtw_h2c_cmd +{ + GEN_CMD_CODE(_Read_MACREG) , /*0*/ + GEN_CMD_CODE(_Write_MACREG) , + GEN_CMD_CODE(_Read_BBREG) , + GEN_CMD_CODE(_Write_BBREG) , + GEN_CMD_CODE(_Read_RFREG) , + GEN_CMD_CODE(_Write_RFREG) , /*5*/ + GEN_CMD_CODE(_Read_EEPROM) , + GEN_CMD_CODE(_Write_EEPROM) , + GEN_CMD_CODE(_Read_EFUSE) , + GEN_CMD_CODE(_Write_EFUSE) , + + GEN_CMD_CODE(_Read_CAM) , /*10*/ + GEN_CMD_CODE(_Write_CAM) , + GEN_CMD_CODE(_setBCNITV), + GEN_CMD_CODE(_setMBIDCFG), + GEN_CMD_CODE(_JoinBss), /*14*/ + GEN_CMD_CODE(_DisConnect) , /*15*/ + GEN_CMD_CODE(_CreateBss) , + GEN_CMD_CODE(_SetOpMode) , + GEN_CMD_CODE(_SiteSurvey), /*18*/ + GEN_CMD_CODE(_SetAuth) , + + GEN_CMD_CODE(_SetKey) , /*20*/ + GEN_CMD_CODE(_SetStaKey) , + GEN_CMD_CODE(_SetAssocSta) , + GEN_CMD_CODE(_DelAssocSta) , + GEN_CMD_CODE(_SetStaPwrState) , + GEN_CMD_CODE(_SetBasicRate) , /*25*/ + GEN_CMD_CODE(_GetBasicRate) , + GEN_CMD_CODE(_SetDataRate) , + GEN_CMD_CODE(_GetDataRate) , + GEN_CMD_CODE(_SetPhyInfo) , + + GEN_CMD_CODE(_GetPhyInfo) , /*30*/ + GEN_CMD_CODE(_SetPhy) , + GEN_CMD_CODE(_GetPhy) , + GEN_CMD_CODE(_readRssi) , + GEN_CMD_CODE(_readGain) , + GEN_CMD_CODE(_SetAtim) , /*35*/ + GEN_CMD_CODE(_SetPwrMode) , + GEN_CMD_CODE(_JoinbssRpt), + GEN_CMD_CODE(_SetRaTable) , + GEN_CMD_CODE(_GetRaTable) , + + GEN_CMD_CODE(_GetCCXReport), /*40*/ + GEN_CMD_CODE(_GetDTMReport), + GEN_CMD_CODE(_GetTXRateStatistics), + GEN_CMD_CODE(_SetUsbSuspend), + GEN_CMD_CODE(_SetH2cLbk), + GEN_CMD_CODE(_AddBAReq) , /*45*/ + GEN_CMD_CODE(_SetChannel), /*46*/ + GEN_CMD_CODE(_SetTxPower), + GEN_CMD_CODE(_SwitchAntenna), + GEN_CMD_CODE(_SetCrystalCap), + GEN_CMD_CODE(_SetSingleCarrierTx), /*50*/ + + GEN_CMD_CODE(_SetSingleToneTx),/*51*/ + GEN_CMD_CODE(_SetCarrierSuppressionTx), + GEN_CMD_CODE(_SetContinuousTx), + GEN_CMD_CODE(_SwitchBandwidth), /*54*/ + GEN_CMD_CODE(_TX_Beacon), /*55*/ + + GEN_CMD_CODE(_Set_MLME_EVT), /*56*/ + GEN_CMD_CODE(_Set_Drv_Extra), /*57*/ + GEN_CMD_CODE(_Set_H2C_MSG), /*58*/ + + GEN_CMD_CODE(_SetChannelPlan), /*59*/ + GEN_CMD_CODE(_LedBlink), /*60*/ + + GEN_CMD_CODE(_SetChannelSwitch), /*61*/ + GEN_CMD_CODE(_TDLS), /*62*/ + GEN_CMD_CODE(_P2P), /*63*/ + + MAX_H2CCMD +}; + +#define _GetBBReg_CMD_ _Read_BBREG_CMD_ +#define _SetBBReg_CMD_ _Write_BBREG_CMD_ +#define _GetRFReg_CMD_ _Read_RFREG_CMD_ +#define _SetRFReg_CMD_ _Write_RFREG_CMD_ + +#ifdef _RTW_CMD_C_ +const struct _cmd_callback rtw_cmd_callback[] = +{ + {GEN_CMD_CODE(_Read_MACREG), NULL}, /*0*/ + {GEN_CMD_CODE(_Write_MACREG), NULL}, +//TODO +// {GEN_CMD_CODE(_Read_BBREG), &rtw_getbbrfreg_cmdrsp_callback}, + {GEN_CMD_CODE(_Read_BBREG), NULL}, + {GEN_CMD_CODE(_Write_BBREG), NULL}, +//TODO +// {GEN_CMD_CODE(_Read_RFREG), &rtw_getbbrfreg_cmdrsp_callback}, + {GEN_CMD_CODE(_Read_RFREG), NULL}, + {GEN_CMD_CODE(_Write_RFREG), NULL}, /*5*/ + {GEN_CMD_CODE(_Read_EEPROM), NULL}, + {GEN_CMD_CODE(_Write_EEPROM), NULL}, + {GEN_CMD_CODE(_Read_EFUSE), NULL}, + {GEN_CMD_CODE(_Write_EFUSE), NULL}, + + {GEN_CMD_CODE(_Read_CAM), NULL}, /*10*/ + {GEN_CMD_CODE(_Write_CAM), NULL}, + {GEN_CMD_CODE(_setBCNITV), NULL}, + {GEN_CMD_CODE(_setMBIDCFG), NULL}, + {GEN_CMD_CODE(_JoinBss), &rtw_joinbss_cmd_callback}, /*14*/ + {GEN_CMD_CODE(_DisConnect), &rtw_disassoc_cmd_callback}, /*15*/ +//TODO +// {GEN_CMD_CODE(_CreateBss), &rtw_createbss_cmd_callback}, + {GEN_CMD_CODE(_CreateBss), NULL}, + {GEN_CMD_CODE(_SetOpMode), NULL}, + {GEN_CMD_CODE(_SiteSurvey), &rtw_survey_cmd_callback}, /*18*/ + {GEN_CMD_CODE(_SetAuth), NULL}, + + {GEN_CMD_CODE(_SetKey), NULL}, /*20*/ + {GEN_CMD_CODE(_SetStaKey), &rtw_setstaKey_cmdrsp_callback}, +//TODO +// {GEN_CMD_CODE(_SetAssocSta), &rtw_setassocsta_cmdrsp_callback}, + {GEN_CMD_CODE(_SetAssocSta), NULL}, + {GEN_CMD_CODE(_DelAssocSta), NULL}, + {GEN_CMD_CODE(_SetStaPwrState), NULL}, + {GEN_CMD_CODE(_SetBasicRate), NULL}, /*25*/ + {GEN_CMD_CODE(_GetBasicRate), NULL}, + {GEN_CMD_CODE(_SetDataRate), NULL}, + {GEN_CMD_CODE(_GetDataRate), NULL}, + {GEN_CMD_CODE(_SetPhyInfo), NULL}, + + {GEN_CMD_CODE(_GetPhyInfo), NULL}, /*30*/ + {GEN_CMD_CODE(_SetPhy), NULL}, + {GEN_CMD_CODE(_GetPhy), NULL}, + {GEN_CMD_CODE(_readRssi), NULL}, + {GEN_CMD_CODE(_readGain), NULL}, + {GEN_CMD_CODE(_SetAtim), NULL}, /*35*/ + {GEN_CMD_CODE(_SetPwrMode), NULL}, + {GEN_CMD_CODE(_JoinbssRpt), NULL}, + {GEN_CMD_CODE(_SetRaTable), NULL}, + {GEN_CMD_CODE(_GetRaTable) , NULL}, + + {GEN_CMD_CODE(_GetCCXReport), NULL}, /*40*/ + {GEN_CMD_CODE(_GetDTMReport), NULL}, + {GEN_CMD_CODE(_GetTXRateStatistics), NULL}, + {GEN_CMD_CODE(_SetUsbSuspend), NULL}, + {GEN_CMD_CODE(_SetH2cLbk), NULL}, + {GEN_CMD_CODE(_AddBAReq), NULL}, /*45*/ + {GEN_CMD_CODE(_SetChannel), NULL}, /*46*/ + {GEN_CMD_CODE(_SetTxPower), NULL}, + {GEN_CMD_CODE(_SwitchAntenna), NULL}, + {GEN_CMD_CODE(_SetCrystalCap), NULL}, + {GEN_CMD_CODE(_SetSingleCarrierTx), NULL}, /*50*/ + + {GEN_CMD_CODE(_SetSingleToneTx), NULL}, /*51*/ + {GEN_CMD_CODE(_SetCarrierSuppressionTx), NULL}, + {GEN_CMD_CODE(_SetContinuousTx), NULL}, + {GEN_CMD_CODE(_SwitchBandwidth), NULL}, /*54*/ + {GEN_CMD_CODE(_TX_Beacon), NULL},/*55*/ + + {GEN_CMD_CODE(_Set_MLME_EVT), NULL},/*56*/ + {GEN_CMD_CODE(_Set_Drv_Extra), NULL},/*57*/ + {GEN_CMD_CODE(_Set_H2C_MSG), NULL},/*58*/ + {GEN_CMD_CODE(_SetChannelPlan), rtw_set_channel_plan_cmd_callback},/*59*/ + {GEN_CMD_CODE(_LedBlink), NULL},/*60*/ + + {GEN_CMD_CODE(_SetChannelSwitch), NULL},/*61*/ + {GEN_CMD_CODE(_TDLS), NULL},/*62*/ +#ifdef CONFIG_P2P_NEW + {GEN_CMD_CODE(_P2P), NULL},/*63*/ +#endif +}; +#endif + +#endif // _CMD_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_debug.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_debug.h index 904eaa0..a7d7b7d 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_debug.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_debug.h @@ -33,39 +33,39 @@ #define _drv_debug_ 10 -#define _module_rtl871x_xmit_c_ BIT(0) -#define _module_xmit_osdep_c_ BIT(1) -#define _module_rtl871x_recv_c_ BIT(2) -#define _module_recv_osdep_c_ BIT(3) -#define _module_rtl871x_mlme_c_ BIT(4) -#define _module_mlme_osdep_c_ BIT(5) +#define _module_rtl871x_xmit_c_ BIT(0) +#define _module_xmit_osdep_c_ BIT(1) +#define _module_rtl871x_recv_c_ BIT(2) +#define _module_recv_osdep_c_ BIT(3) +#define _module_rtl871x_mlme_c_ BIT(4) +#define _module_mlme_osdep_c_ BIT(5) #define _module_rtl871x_sta_mgt_c_ BIT(6) #define _module_rtl871x_cmd_c_ BIT(7) -#define _module_cmd_osdep_c_ BIT(8) -#define _module_rtl871x_io_c_ BIT(9) -#define _module_io_osdep_c_ BIT(10) -#define _module_os_intfs_c_ BIT(11) +#define _module_cmd_osdep_c_ BIT(8) +#define _module_rtl871x_io_c_ BIT(9) +#define _module_io_osdep_c_ BIT(10) +#define _module_os_intfs_c_ BIT(11) #define _module_rtl871x_security_c_ BIT(12) -#define _module_rtl871x_eeprom_c_ BIT(13) -#define _module_hal_init_c_ BIT(14) -#define _module_hci_hal_init_c_ BIT(15) +#define _module_rtl871x_eeprom_c_ BIT(13) +#define _module_hal_init_c_ BIT(14) +#define _module_hci_hal_init_c_ BIT(15) #define _module_rtl871x_ioctl_c_ BIT(16) -#define _module_rtl871x_ioctl_set_c_ BIT(17) +#define _module_rtl871x_ioctl_set_c_ BIT(17) #define _module_rtl871x_ioctl_query_c_ BIT(18) -#define _module_rtl871x_pwrctrl_c_ BIT(19) +#define _module_rtl871x_pwrctrl_c_ BIT(19) #define _module_hci_intfs_c_ BIT(20) -#define _module_hci_ops_c_ BIT(21) -#define _module_osdep_service_c_ BIT(22) -#define _module_mp_ BIT(23) +#define _module_hci_ops_c_ BIT(21) +#define _module_osdep_service_c_ BIT(22) +#define _module_mp_ BIT(23) #define _module_hci_ops_os_c_ BIT(24) #define _module_rtl871x_ioctl_os_c BIT(25) -#define _module_rtl8712_cmd_c_ BIT(26) -#define _module_fwcmd_c_ BIT(27) -#define _module_rtl8192c_xmit_c_ BIT(28) -#define _module_hal_xmit_c_ BIT(28) -#define _module_efuse_ BIT(29) -#define _module_rtl8712_recv_c_ BIT(30) -#define _module_rtl8712_led_c_ BIT(31) +#define _module_rtl8712_cmd_c_ BIT(26) +#define _module_fwcmd_c_ BIT(27) +#define _module_rtl8192c_xmit_c_ BIT(28) +#define _module_hal_xmit_c_ BIT(28) +#define _module_efuse_ BIT(29) +#define _module_rtl8712_recv_c_ BIT(30) +#define _module_rtl8712_led_c_ BIT(31) #undef _MODULE_DEFINE_ @@ -181,7 +181,7 @@ extern void rtl871x_cedbg(const char *fmt, ...); #define _dbgdump printk #elif defined PLATFORM_ECOS #define _dbgdump diag_printf -#elif defined PLATFORM_FREERTOS +#elif defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) #define _dbgdump printf("\n\r"); printf #elif defined PLATFORM_FREEBSD #define _dbgdump printf @@ -194,7 +194,7 @@ extern void rtl871x_cedbg(const char *fmt, ...); #define DEBUG_LEVEL (_drv_err_) #if defined (_dbgdump) #undef DBG_871X_LEVEL -#if defined (__ICCARM__) || defined (__CC_ARM) || defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) +#if defined (__ICCARM__) || defined (__CC_ARM) ||defined(__GNUC__)|| defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) #define DBG_871X_LEVEL(level, ...) \ do {\ _dbgdump(DRIVER_PREFIX __VA_ARGS__);\ diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_eeprom.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_eeprom.h new file mode 100644 index 0000000..9891783 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_eeprom.h @@ -0,0 +1,158 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_EEPROM_H__ +#define __RTW_EEPROM_H__ + +#define RTL8712_EEPROM_ID 0x8712 +//#define EEPROM_MAX_SIZE 256 + +#define HWSET_MAX_SIZE_512 512 +#define EEPROM_MAX_SIZE HWSET_MAX_SIZE_512 + +#define CLOCK_RATE 50 //100us + +//- EEPROM opcodes +#define EEPROM_READ_OPCODE 06 +#define EEPROM_WRITE_OPCODE 05 +#define EEPROM_ERASE_OPCODE 07 +#define EEPROM_EWEN_OPCODE 19 // Erase/write enable +#define EEPROM_EWDS_OPCODE 16 // Erase/write disable + +//Country codes +#define USA 0x555320 +#define EUROPE 0x1 //temp, should be provided later +#define JAPAN 0x2 //temp, should be provided later + +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_ALPHA 0x1 +#define EEPROM_CID_Senao 0x3 +#define EEPROM_CID_NetCore 0x5 +#define EEPROM_CID_CAMEO 0X8 +#define EEPROM_CID_SITECOM 0x9 +#define EEPROM_CID_COREGA 0xB +#define EEPROM_CID_EDIMAX_BELKIN 0xC +#define EEPROM_CID_SERCOMM_BELKIN 0xE +#define EEPROM_CID_CAMEO1 0xF +#define EEPROM_CID_WNC_COREGA 0x12 +#define EEPROM_CID_CLEVO 0x13 +#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 + +// +// Customer ID, note that: +// This variable is initiailzed through EEPROM or registry, +// however, its definition may be different with that in EEPROM for +// EEPROM size consideration. So, we have to perform proper translation between them. +// Besides, CustomerID of registry has precedence of that of EEPROM. +// defined below. 060703, by rcnjko. +// +typedef enum _RT_CUSTOMER_ID +{ + RT_CID_DEFAULT = 0, + RT_CID_8187_ALPHA0 = 1, + RT_CID_8187_SERCOMM_PS = 2, + RT_CID_8187_HW_LED = 3, + RT_CID_8187_NETGEAR = 4, + RT_CID_WHQL = 5, + RT_CID_819x_CAMEO = 6, + RT_CID_819x_RUNTOP = 7, + RT_CID_819x_Senao = 8, + RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31. + RT_CID_819x_Netcore = 10, + RT_CID_Nettronix = 11, + RT_CID_DLINK = 12, + RT_CID_PRONET = 13, + RT_CID_COREGA = 14, + RT_CID_CHINA_MOBILE = 15, + RT_CID_819x_ALPHA = 16, + RT_CID_819x_Sitecom = 17, + RT_CID_CCX = 18, // It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. + RT_CID_819x_Lenovo = 19, + RT_CID_819x_QMI = 20, + RT_CID_819x_Edimax_Belkin = 21, + RT_CID_819x_Sercomm_Belkin = 22, + RT_CID_819x_CAMEO1 = 23, + RT_CID_819x_MSI = 24, + RT_CID_819x_Acer = 25, + RT_CID_819x_AzWave_ASUS = 26, + RT_CID_819x_AzWave = 27, // For AzWave in PCIe, The ID is AzWave use and not only Asus + RT_CID_819x_HP = 28, + RT_CID_819x_WNC_COREGA = 29, + RT_CID_819x_Arcadyan_Belkin = 30, + RT_CID_819x_SAMSUNG = 31, + RT_CID_819x_CLEVO = 32, + RT_CID_819x_DELL = 33, + RT_CID_819x_PRONETS = 34, + RT_CID_819x_Edimax_ASUS = 35, + RT_CID_819x_CAMEO_NETGEAR = 36, + RT_CID_PLANEX = 37, + RT_CID_CC_C = 38, + RT_CID_819x_Xavi = 39, + RT_CID_819x_FUNAI_TV = 40, + RT_CID_819x_ALPHA_WD=41, +}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID; + +struct eeprom_priv +{ + u8 bautoload_fail_flag; + //u8 bempty; + //u8 sys_config; + u8 mac_addr[6]; //PermanentAddress + //u8 config0; +// u16 channel_plan; + u16 CustomerID; + //u8 country_string[3]; + //u8 tx_power_b[15]; + //u8 tx_power_g[15]; + //u8 tx_power_a[201]; + + u8 EepromOrEfuse; +#ifdef CONFIG_MEMORY_ACCESS_ALIGNED + u8 rsvd; //For byte aligned. By Fangyuan, 141201 +#endif + u8 efuse_eeprom_data[HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes) + +#ifdef CONFIG_RF_GAIN_OFFSET + u8 EEPROMRFGainOffset; + u8 EEPROMRFGainVal; +#endif //CONFIG_RF_GAIN_OFFSET +}; + +//TODO +#if 0 + +extern void eeprom_write16(_adapter *padapter, u16 reg, u16 data); +extern u16 eeprom_read16(_adapter *padapter, u16 reg); +extern void read_eeprom_content(_adapter *padapter); +extern void eeprom_read_sz(_adapter * padapter, u16 reg,u8* data, u32 sz); + +extern void read_eeprom_content_by_attrib(_adapter * padapter ); + +#ifdef PLATFORM_LINUX +#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE +extern int isAdaptorInfoFileValid(void); +extern int storeAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv); +extern int retriveAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv); +#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE +#endif //PLATFORM_LINUX + +#endif //#if 0 + +#endif //__RTL871X_EEPROM_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_efuse.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_efuse.h new file mode 100644 index 0000000..d08f088 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_efuse.h @@ -0,0 +1,163 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_EFUSE_H__ +#define __RTW_EFUSE_H__ + +#if (RTL8195A_SUPPORT == 1) +#include "rtl8195a.h" +#endif +#if (RTL8711B_SUPPORT == 1) +#include "ameba_soc.h" +#endif +/*--------------------------Define efuse Parameters-------------------------*/ +#define EFUSE_ERROE_HANDLE 1 + +#define PG_STATE_HEADER 0x01 +#define PG_STATE_WORD_0 0x02 +#define PG_STATE_WORD_1 0x04 +#define PG_STATE_WORD_2 0x08 +#define PG_STATE_WORD_3 0x10 +#define PG_STATE_DATA 0x20 + +#define PG_SWBYTE_H 0x01 +#define PG_SWBYTE_L 0x02 + +#define PGPKT_DATA_SIZE 8 + +#define EFUSE_WIFI 0 +#define EFUSE_BT 1 + +enum _EFUSE_DEF_TYPE { + TYPE_EFUSE_MAX_SECTION = 0, + TYPE_EFUSE_REAL_CONTENT_LEN = 1, + TYPE_AVAILABLE_EFUSE_BYTES_BANK = 2, + TYPE_AVAILABLE_EFUSE_BYTES_TOTAL = 3, + TYPE_EFUSE_MAP_LEN = 4, + TYPE_EFUSE_PROTECT_BYTES_BANK = 5, + TYPE_EFUSE_CONTENT_LEN_BANK = 6, +}; + +#define EFUSE_MAP_SIZE 512 +#define EFUSE_MAX_SIZE 256 + +#define EFUSE_MAX_MAP_LEN 512 +#define EFUSE_MAX_HW_SIZE 256 +#define EFUSE_MAX_SECTION_BASE 16 + +#define EXT_HEADER(header) ((header & 0x1F ) == 0x0F) +#define ALL_WORDS_DISABLED(wde) ((wde & 0x0F) == 0x0F) +#define GET_HDR_OFFSET_2_0(header) ( (header & 0xE0) >> 5) + +#define EFUSE_REPEAT_THRESHOLD_ 3 +#define EFUSE_MAX_WORD_UNIT 4 + +//============================================= +// The following is for BT Efuse definition +//============================================= +#define EFUSE_BT_MAX_MAP_LEN 1024 +#define EFUSE_MAX_BANK 4 +#define EFUSE_MAX_BT_BANK (EFUSE_MAX_BANK-1) +//============================================= + +/*--------------------------Define flash Parameters-------------------------*/ +#if CONFIG_ADAPTOR_INFO_CACHING_FLASH +#if defined CONFIG_RTL8195A || defined(CONFIG_RTL8711B) + #define FLASH_MAX_SIZE FLASH_CAL_DATA_SIZE + #define FLASH_MAGIC_NUMBER 0x8195 // magic number + #define FLASH_HEADER_SIZE 4 // 2: address, 2: length +#endif +#endif // CONFIG_ADAPTOR_INFO_CACHING_FLASH +/*------------------------------Define structure----------------------------*/ +typedef struct PG_PKT_STRUCT_A{ + u8 offset; + u8 word_en; + u8 data[8]; + u8 word_cnts; +}PGPKT_STRUCT,*PPGPKT_STRUCT; + +#ifdef HAL_EFUSE_MEMORY +typedef struct _EFUSE_HAL{ + u8 fakeEfuseBank; + u32 fakeEfuseUsedBytes; + u8 fakeEfuseContent[EFUSE_MAX_HW_SIZE]; + u8 fakeEfuseInitMap[EFUSE_MAX_MAP_LEN]; + u8 fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN]; + + u16 BTEfuseUsedBytes; + u8 BTEfuseUsedPercentage; + u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; + u8 BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; + u8 BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; + + u16 fakeBTEfuseUsedBytes; + u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; + u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; + u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; +}EFUSE_HAL, *PEFUSE_HAL; +#endif // HAL_EFUSE_MEMORY + +/*------------------------Export global variable----------------------------*/ +#if CONFIG_FAKE_EFUSE +extern u8 fakeEfuseBank; +extern u32 fakeEfuseUsedBytes; +extern u8 fakeEfuseContent[]; +extern u8 fakeEfuseInitMap[]; +extern u8 fakeEfuseModifiedMap[]; +#endif + +#ifdef CONFIG_BT_COEXIST +extern u32 BTEfuseUsedBytes; +extern u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; +extern u8 BTEfuseInitMap[]; +extern u8 BTEfuseModifiedMap[]; +#if CONFIG_FAKE_EFUSE +extern u32 fakeBTEfuseUsedBytes; +extern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; +extern u8 fakeBTEfuseInitMap[]; +extern u8 fakeBTEfuseModifiedMap[]; +#endif +#endif + +/*------------------------Export global variable----------------------------*/ + +u8 efuse_GetCurrentSize(_adapter * padapter, u16 *size); +u8 rtw_efuse_access(_adapter * padapter, u8 bRead, u16 start_addr, u16 cnts, u8 *data); +u8 rtw_efuse_map_read(_adapter * padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_efuse_map_write(_adapter * padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_BT_efuse_map_read(_adapter * padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_BT_efuse_map_write(_adapter * padapter, u16 addr, u16 cnts, u8 *data); + +u16 Efuse_GetCurrentSize(_adapter * pAdapter, u8 efuseType, BOOLEAN bPseudoTest); +u8 Efuse_CalculateWordCnts(u8 word_en); +void EFUSE_GetEfuseDefinition(_adapter * pAdapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest); +u8 efuse_OneByteRead(_adapter * pAdapter, u16 addr, u8 *data, BOOLEAN bPseudoTest); +u8 efuse_OneByteWrite(_adapter * pAdapter, u16 addr, u8 data, BOOLEAN bPseudoTest); + +void Efuse_PowerSwitch(_adapter * pAdapter,u8 bWrite,u8 PwrState); +//int Efuse_PgPacketRead(_adapter * pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest); +int Efuse_PgPacketWrite(_adapter * pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); +void efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata); +u8 Efuse_WordEnableDataWrite(_adapter * pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest); + +void EFUSE_ShadowMapUpdate(_adapter * pAdapter, u8 efuseType, BOOLEAN bPseudoTest); +void EFUSE_ShadowRead(_adapter * pAdapter, u8 Type, u16 Offset, u32 *Value); + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_event.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_event.h new file mode 100644 index 0000000..83b29b9 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_event.h @@ -0,0 +1,151 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_EVENT_H_ +#define _RTW_EVENT_H_ + +#ifndef CONFIG_RTL8711FW +#ifdef PLATFORM_LINUX +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) +#include +#else +#include +#endif +#include +#endif +#endif//CONFIG_RTL8711FW + + + +#ifdef CONFIG_H2CLBK +#include +#endif + +/* +Used to report a bss has been scanned + +*/ +struct survey_event { + WLAN_BSSID_EX bss; +}; + +/* +Used to report that the requested site survey has been done. + +bss_cnt indicates the number of bss that has been reported. + + +*/ +struct surveydone_event { + unsigned int bss_cnt; + +}; + +/* +Used to report the link result of joinning the given bss + + +join_res: +-1: authentication fail +-2: association fail +> 0: TID + +*/ +struct joinbss_event { + //struct wlan_network network; + int join_res; +}; + +/* +Used to report a given STA has joinned the created BSS. +It is used in AP/Ad-HoC(M) mode. + + +*/ +struct stassoc_event { + unsigned char macaddr[6]; + unsigned char rsvd[2]; + int cam_id; + +}; + +struct stadel_event { + unsigned char macaddr[6]; + unsigned char rsvd[2]; //for reason + int mac_id; +}; + +struct addba_event +{ + unsigned int tid; +}; + + +#ifdef CONFIG_H2CLBK +struct c2hlbk_event{ + unsigned char mac[6]; + unsigned short s0; + unsigned short s1; + unsigned int w0; + unsigned char b0; + unsigned short s2; + unsigned char b1; + unsigned int w1; +}; +#endif//CONFIG_H2CLBK + +#define GEN_EVT_CODE(event) event ## _EVT_ + +struct fwevent { + u32 parmsize; + void (*event_callback)(_adapter *dev, u8 *pbuf); +}; + +//TODO +#if 0 + +#define C2HEVENT_SZ 32 + +struct event_node{ + unsigned char *node; + unsigned char evt_code; + unsigned short evt_sz; + volatile int *caller_ff_tail; + int caller_ff_sz; +}; + +struct c2hevent_queue { + volatile int head; + volatile int tail; + struct event_node nodes[C2HEVENT_SZ]; + unsigned char seq; +}; + +#define NETWORK_QUEUE_SZ 4 + +struct network_queue { + volatile int head; + volatile int tail; + WLAN_BSSID_EX networks[NETWORK_QUEUE_SZ]; +}; + +#endif //#if 0 + +#endif // _WLANEVENT_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_ht.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_ht.h new file mode 100644 index 0000000..5910986 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_ht.h @@ -0,0 +1,66 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_HT_H_ +#define _RTW_HT_H_ + +#include "wifi.h" + +struct ht_priv +{ + u32 ht_option; + u32 ampdu_enable;//for enable Tx A-MPDU + //u8 baddbareq_issued[16]; + //u32 tx_amsdu_enable;//for enable Tx A-MSDU + //u32 tx_amdsu_maxlen; // 1: 8k, 0:4k ; default:8k, for tx + //u32 rx_ampdu_maxlen; //for rx reordering ctrl win_sz, updated when join_callback. + + u8 bwmode;// + u8 ch_offset;//PRIME_CHNL_OFFSET + u8 sgi;//short GI + + //for processing Tx A-MPDU + u8 agg_enable_bitmap; + //u8 ADDBA_retry_count; + u8 candidate_tid_bitmap; + + u8 stbc_cap; + + struct rtw_ieee80211_ht_cap ht_cap; + +}; + +#define STBC_HT_ENABLE_RX BIT0 +#define STBC_HT_ENABLE_TX BIT1 +#define STBC_HT_TEST_TX_ENABLE BIT2 +#define STBC_HT_CAP_TX BIT3 + +typedef enum AGGRE_SIZE{ + HT_AGG_SIZE_8K = 0, + HT_AGG_SIZE_16K = 1, + HT_AGG_SIZE_32K = 2, + HT_AGG_SIZE_64K = 3, + VHT_AGG_SIZE_128K = 4, + VHT_AGG_SIZE_256K = 5, + VHT_AGG_SIZE_512K = 6, + VHT_AGG_SIZE_1024K = 7, +}AGGRE_SIZE_E, *PAGGRE_SIZE_E; + +#endif //_RTL871X_HT_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_intfs.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_intfs.h new file mode 100644 index 0000000..1a8594e --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_intfs.h @@ -0,0 +1,39 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_INTFS_H_ +#define _RTW_INTFS_H_ + +extern u8 rtw_init_default_value(_adapter *padapter); +#ifdef CONFIG_WOWLAN +void rtw_cancel_dynamic_chk_timer(_adapter *padapter); +#endif +extern void rtw_cancel_all_timer(_adapter *padapter); + +extern u8 rtw_init_drv_sw(_adapter *padapter); +extern u8 rtw_free_drv_sw(_adapter *padapter); +extern u8 rtw_reset_drv_sw(_adapter *padapter); + +extern int rtw_drv_init(ADAPTER *padapter); +extern void rtw_drv_deinit(ADAPTER *Adapter); + +extern u32 rtw_start_drv_threads(_adapter *padapter); +extern void rtw_stop_drv_threads (_adapter *padapter); + +#endif //_RTW_INTFS_H_ diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_io.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_io.h new file mode 100644 index 0000000..2801cce --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_io.h @@ -0,0 +1,140 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef _RTW_IO_H_ +#define _RTW_IO_H_ + +//IO Bus domain address mapping +#define DEFUALT_OFFSET 0x0 +#define WLAN_LOCAL_OFFSET 0x10250000 +#define WLAN_IOREG_OFFSET 0x10260000 +#define FW_FIFO_OFFSET 0x10270000 +#define TX_HIQ_OFFSET 0x10310000 +#define TX_MIQ_OFFSET 0x1032000 +#define TX_LOQ_OFFSET 0x10330000 +#define RX_RXOFF_OFFSET 0x10340000 + +struct fifo_more_data { + u32 more_data; + u32 len; +}; + +struct dvobj_priv; + +typedef struct _io_ops { + int (*init_io_priv)(struct dvobj_priv *pdvobj); + int (*write8_endian)(struct dvobj_priv *pdvobj, u32 addr, u32 buf, u32 big); + + u8 (*_read8)(struct dvobj_priv *pdvobj, u32 addr, s32 *err); + u16 (*_read16)(struct dvobj_priv *pdvobj, u32 addr, s32 *err); + u32 (*_read32)(struct dvobj_priv *pdvobj, u32 addr, s32 *err); + + s32 (*_write8)(struct dvobj_priv *pdvobj, u32 addr, u8 buf, s32 *err); + s32 (*_write16)(struct dvobj_priv *pdvobj, u32 addr,u16 buf, s32 *err); + s32 (*_write32)(struct dvobj_priv *pdvobj, u32 addr, u32 buf, s32 *err); + + int (*read_rx_fifo)(struct dvobj_priv *pdvobj, u32 addr, u8 *buf, u32 len, struct fifo_more_data *more_data); + int (*write_tx_fifo)(struct dvobj_priv *pdvobj, u32 addr, u8 *buf, u32 len); +} IO_OPS_T; + +struct bus_transfer { + void *tx_buf; + void *rx_buf; + unsigned int len; +}; + +typedef struct _bus_drv_ops { + int (*bus_drv_init)(ADAPTER *Adapter); + int (*bus_send_msg)(PADAPTER Adapter, struct bus_transfer xfers[], u32 RegAction); +} BUS_DRV_OPS_T; + +/* +struct intf_hdl { + + u32 intf_option; + u32 bus_status; + u32 do_flush; + u8 *adapter; + u8 *intf_dev; + struct intf_priv *pintfpriv; + u8 cnt; + void (*intf_hdl_init)(u8 *priv); + void (*intf_hdl_unload)(u8 *priv); + void (*intf_hdl_open)(u8 *priv); + void (*intf_hdl_close)(u8 *priv); + struct _io_ops io_ops; + //u8 intf_status;//moved to struct intf_priv + u16 len; + u16 done_len; + + _adapter *padapter; + struct dvobj_priv *pintf_dev;// pointer to &(padapter->dvobjpriv); + + struct _io_ops io_ops; + +}; +*/ + +struct io_priv{ + struct _io_ops io_ops; +}; + + +extern u8 rtw_read8(ADAPTER *adapter, u32 addr); +extern u16 rtw_read16(ADAPTER *adapter, u32 addr); +extern u32 rtw_read32(ADAPTER *adapter, u32 addr); +extern s32 rtw_write8(ADAPTER *adapter, u32 addr, u8 val); +extern s32 rtw_write16(ADAPTER *adapter, u32 addr, u16 val); +extern s32 rtw_write32(ADAPTER *adapter, u32 addr, u32 val); + +#define PlatformEFIOWrite1Byte(_a,_b,_c) \ + rtw_write8(_a,_b,_c) +#define PlatformEFIOWrite2Byte(_a,_b,_c) \ + rtw_write16(_a,_b,_c) +#define PlatformEFIOWrite4Byte(_a,_b,_c) \ + rtw_write32(_a,_b,_c) + +#define PlatformEFIORead1Byte(_a,_b) \ + rtw_read8(_a,_b) +#define PlatformEFIORead2Byte(_a,_b) \ + rtw_read16(_a,_b) +#define PlatformEFIORead4Byte(_a,_b) \ + rtw_read32(_a,_b) + +extern IO_OPS_T io_ops; + +extern u32 rtw_write_port( + ADAPTER *adapter, + u32 addr, + u32 cnt, + u8 *mem); +extern u32 rtw_read_port( + ADAPTER *adapter, + u32 addr, + u32 cnt, + u8 *mem, + struct fifo_more_data *more_data); +extern void rtw_set_chip_endian(PADAPTER padapter); +extern int rtw_get_chip_endian(PADAPTER padapter); + +int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(struct _io_ops *pops)); + +#endif //_RTW_IO_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_ioctl_set.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_ioctl_set.h new file mode 100644 index 0000000..8e247e3 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_ioctl_set.h @@ -0,0 +1,75 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_IOCTL_SET_H_ +#define __RTW_IOCTL_SET_H_ + + +#ifdef PLATFORM_OS_XP +typedef struct _NDIS_802_11_PMKID { + u32 Length; + u32 BSSIDInfoCount; + BSSIDInfo BSSIDInfo[1]; +} NDIS_802_11_PMKID, *PNDIS_802_11_PMKID; +#endif + + +#ifdef PLATFORM_WINDOWS +typedef u8 NDIS_802_11_PMKID_VALUE[16]; + +typedef struct _BSSIDInfo { + NDIS_802_11_MAC_ADDRESS BSSID; + NDIS_802_11_PMKID_VALUE PMKID; +} BSSIDInfo, *PBSSIDInfo; + +u8 rtw_set_802_11_reload_defaults(_adapter * padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults); +u8 rtw_set_802_11_test(_adapter * padapter, NDIS_802_11_TEST * test); +u8 rtw_set_802_11_pmkid(_adapter *pdapter, NDIS_802_11_PMKID *pmkid); + +u8 rtw_pnp_set_power_sleep(_adapter* padapter); +u8 rtw_pnp_set_power_wakeup(_adapter* padapter); + +void rtw_pnp_resume_wk(void *context); +void rtw_pnp_sleep_wk(void * context); + +#endif + +u8 rtw_set_802_11_add_key(_adapter * padapter, NDIS_802_11_KEY * key); +u8 rtw_set_802_11_authentication_mode(_adapter *pdapter, NDIS_802_11_AUTHENTICATION_MODE authmode); +u8 rtw_set_802_11_bssid(_adapter* padapter, u8 *bssid); +u8 rtw_set_802_11_add_wep(_adapter * padapter, NDIS_802_11_WEP * wep); +u8 rtw_set_802_11_disassociate(_adapter * padapter); +u8 rtw_set_802_11_bssid_list_scan(_adapter* padapter, NDIS_802_11_SSID *pssid, int ssid_max_num); +u8 rtw_set_802_11_infrastructure_mode(_adapter * padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype); +u8 rtw_set_802_11_remove_wep(_adapter * padapter, u32 keyindex); +u8 rtw_set_802_11_ssid(_adapter * padapter, NDIS_802_11_SSID * ssid); +u8 rtw_set_802_11_connect(_adapter* padapter, u8 *bssid, NDIS_802_11_SSID *ssid); +u8 rtw_set_802_11_remove_key(_adapter * padapter, NDIS_802_11_REMOVE_KEY * key); + +u8 rtw_validate_bssid(u8 *bssid); +u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid); + +u16 rtw_get_cur_max_rate(_adapter *adapter); +//int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode); +int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan); +int rtw_set_country(_adapter *adapter, const char *country_code); +//int rtw_set_band(_adapter *adapter, enum _BAND band); + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_led.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_led.h new file mode 100644 index 0000000..e6b6d8a --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_led.h @@ -0,0 +1,250 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_LED_H_ +#define __RTW_LED_H_ + +//TODO +#if 0 + +//#include + +#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000) + +#define LED_BLINK_NORMAL_INTERVAL 100 +#define LED_BLINK_SLOWLY_INTERVAL 200 +#define LED_BLINK_LONG_INTERVAL 400 + +#define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000 +#define LED_BLINK_LINK_INTERVAL_ALPHA 500 //500 +#define LED_BLINK_SCAN_INTERVAL_ALPHA 180 //150 +#define LED_BLINK_FASTER_INTERVAL_ALPHA 50 +#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA 5000 + +#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX 100 +#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX 2000 + +#define LED_BLINK_SLOWLY_INTERVAL_PORNET 1000 +#define LED_BLINK_NORMAL_INTERVAL_PORNET 100 + +#define LED_BLINK_FAST_INTERVAL_BITLAND 30 + +// 060403, rcnjko: Customized for AzWave. +#define LED_CM2_BLINK_ON_INTERVAL 250 +#define LED_CM2_BLINK_OFF_INTERVAL 4750 + +#define LED_CM8_BLINK_INTERVAL 500 //for QMI +#define LED_CM8_BLINK_OFF_INTERVAL 3750 //for QMI + +// 080124, lanhsin: Customized for RunTop +#define LED_RunTop_BLINK_INTERVAL 300 + +// 060421, rcnjko: Customized for Sercomm Printer Server case. +#define LED_CM3_BLINK_INTERVAL 1500 + +#endif //#if 0 + +typedef enum _LED_CTL_MODE{ + LED_CTL_POWER_ON = 1, + LED_CTL_LINK = 2, + LED_CTL_NO_LINK = 3, + LED_CTL_TX = 4, + LED_CTL_RX = 5, + LED_CTL_SITE_SURVEY = 6, + LED_CTL_POWER_OFF = 7, + LED_CTL_START_TO_LINK = 8, + LED_CTL_START_WPS = 9, + LED_CTL_STOP_WPS = 10, + LED_CTL_START_WPS_BOTTON = 11, //added for runtop + LED_CTL_STOP_WPS_FAIL = 12, //added for ALPHA + LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, //added for BELKIN + LED_CTL_CONNECTION_NO_TRANSFER = 14, +}LED_CTL_MODE; + +//TODO +#if 0 + +typedef enum _LED_STATE_871x{ + LED_UNKNOWN = 0, + RTW_LED_ON = 1, + RTW_LED_OFF = 2, + LED_BLINK_NORMAL = 3, + LED_BLINK_SLOWLY = 4, + LED_BLINK_POWER_ON = 5, + LED_BLINK_SCAN = 6, // LED is blinking during scanning period, the # of times to blink is depend on time for scanning. + LED_BLINK_NO_LINK = 7, // LED is blinking during no link state. + LED_BLINK_StartToBlink = 8,// Customzied for Sercomm Printer Server case + LED_BLINK_TXRX = 9, + LED_BLINK_WPS = 10, // LED is blinkg during WPS communication + LED_BLINK_WPS_STOP = 11, //for ALPHA + LED_BLINK_WPS_STOP_OVERLAP = 12, //for BELKIN + LED_BLINK_RUNTOP = 13, // Customized for RunTop + LED_BLINK_CAMEO = 14, + LED_BLINK_XAVI = 15, + LED_BLINK_ALWAYS_ON = 16, +}LED_STATE_871x; + +typedef enum _LED_PIN_871x{ + LED_PIN_NULL = 0, + LED_PIN_LED0 = 1, + LED_PIN_LED1 = 2, + LED_PIN_LED2 = 3, + LED_PIN_GPIO0 = 4, +}LED_PIN_871x; + +typedef struct _LED_871x{ + _adapter *padapter; + + LED_PIN_871x LedPin; // Identify how to implement this SW led. + LED_STATE_871x CurrLedState; // Current LED state. + LED_STATE_871x BlinkingLedState; // Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are. + + u8 bLedOn; // true if LED is ON, false if LED is OFF. + + u8 bLedBlinkInProgress; // true if it is blinking, false o.w.. + + u8 bLedWPSBlinkInProgress; + + u32 BlinkTimes; // Number of times to toggle led state for blinking. + + _timer BlinkTimer; // Timer object for led blinking. + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + u8 bSWLedCtrl; + + // ALPHA, added by chiyoko, 20090106 + u8 bLedNoLinkBlinkInProgress; + u8 bLedLinkBlinkInProgress; + u8 bLedStartToLinkBlinkInProgress; + u8 bLedScanBlinkInProgress; + + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)|| defined PLATFORM_FREEBSD + _workitem BlinkWorkItem; // Workitem used by BlinkTimer to manipulate H/W to blink LED. + #endif +#endif //defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + +#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI) + u8 bLedSlowBlinkInProgress;//added by vivi, for led new mode +#endif + +} LED_871x, *PLED_871x; + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + +#define IS_LED_WPS_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS \ + || ((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS_STOP \ + || ((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress) + +#define IS_LED_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress \ + ||((PLED_871x)_LED_871x)->bLedScanBlinkInProgress) + +//================================================================================ +// LED customization. +//================================================================================ + +typedef enum _LED_STRATEGY_871x{ + SW_LED_MODE0 = 0, // SW control 1 LED via GPIO0. It is default option. + SW_LED_MODE1= 1, // 2 LEDs, through LED0 and LED1. For ALPHA. + SW_LED_MODE2 = 2, // SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. + SW_LED_MODE3 = 3, // SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. + SW_LED_MODE4 = 4, //for Edimax / Belkin + SW_LED_MODE5 = 5, //for Sercomm / Belkin + SW_LED_MODE6 = 6, //for 88CU minicard, porting from ce SW_LED_MODE7 + HW_LED = 50, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.) + LED_ST_NONE = 99, +}LED_STRATEGY_871x, *PLED_STRATEGY_871x; + +void +LedControl871x( + _adapter *padapter, + LED_CTL_MODE LedAction + ); +#endif //defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + +#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI) +//================================================================================ +// LED customization. +//================================================================================ + +typedef enum _LED_STRATEGY_871x{ + SW_LED_MODE0 = 0, // SW control 1 LED via GPIO0. It is default option. + SW_LED_MODE1 = 1, // SW control for PCI Express + SW_LED_MODE2 = 2, // SW control for Cameo. + SW_LED_MODE3 = 3, // SW contorl for RunTop. + SW_LED_MODE4 = 4, // SW control for Netcore + SW_LED_MODE5 = 5, //added by vivi, for led new mode, DLINK + SW_LED_MODE6 = 6, //added by vivi, for led new mode, PRONET + SW_LED_MODE7 = 7, //added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec + SW_LED_MODE8 = 8, //added by chiyokolin, for QMI + SW_LED_MODE9 = 9, //added by chiyokolin, for BITLAND, PCI Express Minicard Spec Rev.1.1 + SW_LED_MODE10 = 10, //added by chiyokolin, for Edimax-ASUS + HW_LED = 50, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes) + LED_ST_NONE = 99, +}LED_STRATEGY_871x, *PLED_STRATEGY_871x; +#endif //defined(CONFIG_PCI_HCI) + +struct led_priv{ + /* add for led controll */ + LED_871x SwLed0; + LED_871x SwLed1; + LED_STRATEGY_871x LedStrategy; + u8 bRegUseLed; + void (*LedControlHandler)(_adapter *padapter, LED_CTL_MODE LedAction); + /* add for led controll */ +}; + +#endif //#if 0 + +#ifdef CONFIG_SW_LED +#define rtw_led_control(adapter, LedAction) \ + do { \ + if((adapter)->ledpriv.LedControlHandler) \ + (adapter)->ledpriv.LedControlHandler((adapter), (LedAction)); \ + } while(0) +#else //CONFIG_SW_LED +#define rtw_led_control(adapter, LedAction) +#endif //CONFIG_SW_LED + +//TODO +#if 0 + +void BlinkTimerCallback(void *data); +void BlinkWorkItemCallback(struct work_struct *work); + +void ResetLedStatus(PLED_871x pLed); + +void +InitLed871x( + _adapter *padapter, + PLED_871x pLed, + LED_PIN_871x LedPin + ); + +void +DeInitLed871x( + PLED_871x pLed + ); + +//hal... +extern void BlinkHandler(PLED_871x pLed); + +#endif //#if 0 + +#endif //__RTW_LED_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_mlme.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_mlme.h new file mode 100644 index 0000000..f80fc61 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_mlme.h @@ -0,0 +1,795 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_MLME_H_ +#define __RTW_MLME_H_ + +#ifdef CONFIG_INTEL_WIDI +#include +#endif + +#if defined(PLATFORM_ECOS) +#define MAX_BSS_CNT 10 //alloc less wlan_network due to memory limitation - Alex Fang +#elif defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) +#define MAX_BSS_CNT 1 //alloc less wlan_network due to memory limitation - Alex Fang +#else +#define MAX_BSS_CNT 128 +#endif +//#define MAX_JOIN_TIMEOUT 2000 +//#define MAX_JOIN_TIMEOUT 2500 +#define MAX_JOIN_TIMEOUT 6500 + +#ifdef CONFIG_MULTICAST +#define MULTICAST_LIST_SIZE 4 +#endif + +// Commented by Albert 20101105 +// Increase the scanning timeout because of increasing the SURVEY_TO value. + +#define SCANNING_TIMEOUT 8000 + +#define SCAN_INTERVAL (30) // unit:2sec, 30*2=60sec + +#ifdef PALTFORM_OS_WINCE +#define SCANQUEUE_LIFETIME 12000000 // unit:us +#else +#define SCANQUEUE_LIFETIME 20 // unit:sec +#endif + +#define WIFI_NULL_STATE 0x00000000 +#define WIFI_ASOC_STATE 0x00000001 // Under Linked state... +#define WIFI_REASOC_STATE 0x00000002 +#define WIFI_SLEEP_STATE 0x00000004 +#define WIFI_STATION_STATE 0x00000008 +#define WIFI_AP_STATE 0x00000010 +#define WIFI_ADHOC_STATE 0x00000020 +#define WIFI_ADHOC_MASTER_STATE 0x00000040 +#define WIFI_UNDER_LINKING 0x00000080 +//#define WIFI_UNDER_CMD 0x00000200 +// ========== P2P Section Start =============== +#define WIFI_P2P_LISTEN_STATE 0x00010000 +#define WIFI_P2P_GROUP_FORMATION_STATE 0x00020000 +// ========== P2P Section End =============== +#define WIFI_UNDER_WPS 0x00000100 +#define WIFI_SITE_MONITOR 0x00000800 //to indicate the station is under site surveying + +#ifdef WDS +#define WIFI_WDS 0x00001000 +#define WIFI_WDS_RX_BEACON 0x00002000 // already rx WDS AP beacon +#endif +#ifdef AUTO_CONFIG +#define WIFI_AUTOCONF 0x00004000 +#define WIFI_AUTOCONF_IND 0x00008000 +#endif + +//#ifdef UNDER_MPTEST +#define WIFI_MP_STATE 0x00010000 +#define WIFI_MP_CTX_BACKGROUND 0x00020000 // in continous tx background +#define WIFI_MP_CTX_ST 0x00040000 // in continous tx with single-tone +#define WIFI_MP_CTX_BACKGROUND_PENDING 0x00080000 // pending in continous tx background due to out of skb +#define WIFI_MP_CTX_CCK_HW 0x00100000 // in continous tx +#define WIFI_MP_CTX_CCK_CS 0x00200000 // in continous tx with carrier suppression +#define WIFI_MP_LPBK_STATE 0x00400000 +//#endif + +//#define _FW_UNDER_CMD WIFI_UNDER_CMD +#define _FW_UNDER_LINKING WIFI_UNDER_LINKING +#define _FW_LINKED WIFI_ASOC_STATE +#define _FW_UNDER_SURVEY WIFI_SITE_MONITOR + +enum dot11AuthAlgrthmNum { + dot11AuthAlgrthm_Open = 0, + dot11AuthAlgrthm_Shared, + dot11AuthAlgrthm_8021X, + dot11AuthAlgrthm_Auto, + dot11AuthAlgrthm_WAPI, + dot11AuthAlgrthm_MaxNum +}; + +// Scan type including active and passive scan. +typedef enum _RT_SCAN_TYPE +{ + SCAN_PASSIVE, + SCAN_ACTIVE, + SCAN_MIX, +} RT_SCAN_TYPE, *PRT_SCAN_TYPE; + +/* + +there are several "locks" in mlme_priv, +since mlme_priv is a shared resource between many threads, +like ISR/Call-Back functions, the OID handlers, and even timer functions. + + +Each _queue has its own locks, already. +Other items are protected by mlme_priv.lock. + +To avoid possible dead lock, any thread trying to modifiying mlme_priv +SHALL not lock up more than one locks at a time! + +*/ + + +#define traffic_threshold 10 +#define traffic_scan_period 500 + +struct sitesurvey_ctrl { + u64 last_tx_pkts; + uint last_rx_pkts; + sint traffic_busy; + _timer sitesurvey_ctrl_timer; +}; + +typedef struct _RT_LINK_DETECT_T{ + u32 NumTxOkInPeriod; + u32 NumRxOkInPeriod; + u32 NumRxUnicastOkInPeriod; + BOOLEAN bBusyTraffic; + BOOLEAN bTxBusyTraffic; + BOOLEAN bRxBusyTraffic; + BOOLEAN bHigherBusyTraffic; // For interrupt migration purpose. + BOOLEAN bHigherBusyRxTraffic; // We may disable Tx interrupt according as Rx traffic. + BOOLEAN bHigherBusyTxTraffic; // We may disable Tx interrupt according as Tx traffic. +} RT_LINK_DETECT_T, *PRT_LINK_DETECT_T; + +//TODO +#if 0 + +struct profile_info { + u8 ssidlen; + u8 ssid[ WLAN_SSID_MAXLEN ]; + u8 peermac[ ETH_ALEN ]; +}; + +struct tx_invite_req_info{ + u8 token; + u8 benable; + u8 go_ssid[ WLAN_SSID_MAXLEN ]; + u8 ssidlen; + u8 go_bssid[ ETH_ALEN ]; + u8 peer_macaddr[ ETH_ALEN ]; + u8 operating_ch; // This information will be set by using the p2p_set op_ch=x + u8 peer_ch; // The listen channel for peer P2P device + +}; + +struct tx_invite_resp_info{ + u8 token; // Used to record the dialog token of p2p invitation request frame. +}; + +#ifdef CONFIG_WFD + +struct wifi_display_info{ + u16 wfd_enable; // Eanble/Disable the WFD function. + u16 rtsp_ctrlport; // TCP port number at which the this WFD device listens for RTSP messages + u16 peer_rtsp_ctrlport; // TCP port number at which the peer WFD device listens for RTSP messages + // This filed should be filled when receiving the gropu negotiation request + + u8 peer_session_avail; // WFD session is available or not for the peer wfd device. + // This variable will be set when sending the provisioning discovery request to peer WFD device. + // And this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command. + u8 ip_address[4]; + u8 peer_ip_address[4]; + u8 wfd_pc; // WFD preferred connection + // 0 -> Prefer to use the P2P for WFD connection on peer side. + // 1 -> Prefer to use the TDLS for WFD connection on peer side. + + u8 wfd_device_type; // WFD Device Type + // 0 -> WFD Source Device + // 1 -> WFD Primary Sink Device + +}; +#endif //CONFIG_WFD + +struct tx_provdisc_req_info{ + u16 wps_config_method_request; // Used when sending the provisioning request frame + u16 peer_channel_num[2]; // The channel number which the receiver stands. + NDIS_802_11_SSID ssid; + u8 peerDevAddr[ ETH_ALEN ]; // Peer device address + u8 peerIFAddr[ ETH_ALEN ]; // Peer interface address + u8 benable; // This provision discovery request frame is trigger to send or not +}; + +struct rx_provdisc_req_info{ //When peer device issue prov_disc_req first, we should store the following informations + u8 peerDevAddr[ ETH_ALEN ]; // Peer device address + u8 strconfig_method_desc_of_prov_disc_req[4]; // description for the config method located in the provisioning discovery request frame. + // The UI must know this information to know which config method the remote p2p device is requiring. +}; + +struct tx_nego_req_info{ + u16 peer_channel_num[2]; // The channel number which the receiver stands. + u8 peerDevAddr[ ETH_ALEN ]; // Peer device address + u8 benable; // This negoitation request frame is trigger to send or not +}; + +struct group_id_info{ + u8 go_device_addr[ ETH_ALEN ]; // The GO's device address of this P2P group + u8 ssid[ WLAN_SSID_MAXLEN ]; // The SSID of this P2P group +}; + +#ifdef CONFIG_IOCTL_CFG80211 +struct cfg80211_wifidirect_info{ + _timer remain_on_ch_timer; + u8 restore_channel; + struct ieee80211_channel remain_on_ch_channel; + enum nl80211_channel_type remain_on_ch_type; + u64 remain_on_ch_cookie; + struct net_device *remain_on_ch_dev; + bool is_ro_ch; +}; +#endif //CONFIG_IOCTL_CFG80211 + +#endif + +struct wifidirect_info{ + enum P2P_ROLE role; + enum P2P_STATE p2p_state; + u8 baction_tx_pending; + u8 pending_peer[ETH_ALEN]; + struct xmit_frame *pending_action; + _timer pre_tx_scan_timer; + +#if 0 + _adapter* padapter; + _timer find_phase_timer; + _timer restore_p2p_state_timer; + + // Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer. + _timer pre_tx_scan_timer; +#ifdef CONFIG_CONCURRENT_MODE + // Used to switch the channel between legacy AP and listen state. + _timer ap_p2p_switch_timer; +#endif + struct tx_provdisc_req_info tx_prov_disc_info; + struct rx_provdisc_req_info rx_prov_disc_info; + struct tx_invite_req_info invitereq_info; + struct profile_info profileinfo[ P2P_MAX_PERSISTENT_GROUP_NUM ]; // Store the profile information of persistent group + struct tx_invite_resp_info inviteresp_info; + struct tx_nego_req_info nego_req_info; + struct group_id_info groupid_info; // Store the group id information when doing the group negotiation handshake. +#ifdef CONFIG_WFD + struct wifi_display_info *wfd_info; +#endif + enum P2P_ROLE role; + enum P2P_STATE pre_p2p_state; + enum P2P_STATE p2p_state; + u8 device_addr[ETH_ALEN]; // The device address should be the mac address of this device. + u8 interface_addr[ETH_ALEN]; + u8 social_chan[4]; + u8 listen_channel; + u8 operating_channel; + u8 listen_dwell; // This value should be between 1 and 3 + u8 support_rate[8]; + u8 p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN]; + u8 intent; // should only include the intent value. + u8 p2p_peer_interface_addr[ ETH_ALEN ]; + u8 p2p_peer_device_addr[ ETH_ALEN ]; + u8 peer_intent; // Included the intent value and tie breaker value. + u8 device_name[ WPS_MAX_DEVICE_NAME_LEN ]; // Device name for displaying on searching device screen + u8 device_name_len; + u8 profileindex; // Used to point to the index of profileinfo array + u8 peer_operating_ch; + u8 find_phase_state_exchange_cnt; + u16 device_password_id_for_nego; // The device password ID for group negotation + u8 negotiation_dialog_token; + u8 nego_ssid[ WLAN_SSID_MAXLEN ]; // SSID information for group negotitation + u8 nego_ssidlen; + u8 p2p_group_ssid[WLAN_SSID_MAXLEN]; + u8 p2p_group_ssid_len; + u8 persistent_supported; // Flag to know the persistent function should be supported or not. + // In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. + // 0: disable + // 1: enable + u8 session_available; // Flag to set the WFD session available to enable or disable "by Sigma" + // In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. + // 0: disable + // 1: enable + + u8 wfd_tdls_enable; // Flag to enable or disable the TDLS by WFD Sigma + // 0: disable + // 1: enable + u8 wfd_tdls_weaksec; // Flag to enable or disable the weak security function for TDLS by WFD Sigma + // 0: disable + // In this case, the driver can't issue the tdsl setup request frame. + // 1: enable + // In this case, the driver can issue the tdls setup request frame + // even the current security is weak security. + + enum P2P_WPSINFO ui_got_wps_info; // This field will store the WPS value (PIN value or PBC) that UI had got from the user. + u16 supported_wps_cm; // This field describes the WPS config method which this driver supported. + // The value should be the combination of config method defined in page104 of WPS v2.0 spec. + uint channel_list_attr_len; // This field will contain the length of body of P2P Channel List attribute of group negotitation response frame. + u8 channel_list_attr[100]; // This field will contain the body of P2P Channel List attribute of group negotitation response frame. + // We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. +#ifdef CONFIG_CONCURRENT_MODE + u16 ext_listen_interval; // The interval to be available with legacy AP (ms) + u16 ext_listen_period; // The time period to be available for P2P listen state (ms) +#endif + u8 p2p_ps_enable; + enum P2P_PS p2p_ps; // indicate p2p ps state + u8 noa_index; // Identifies and instance of Notice of Absence timing. + u8 ctwindow; // Client traffic window. A period of time in TU after TBTT. + u8 opp_ps; // opportunistic power save. + u8 noa_num; // number of NoA descriptor in P2P IE. + u8 noa_count[P2P_MAX_NOA_NUM]; // Count for owner, Type of client. + u32 noa_duration[P2P_MAX_NOA_NUM]; // Max duration for owner, preferred or min acceptable duration for client. + u32 noa_interval[P2P_MAX_NOA_NUM]; // Length of interval for owner, preferred or max acceptable interval of client. + u32 noa_start_time[P2P_MAX_NOA_NUM]; // schedule expressed in terms of the lower 4 bytes of the TSF timer. +#endif +}; +#if 0 +struct tdls_ss_record{ //signal strength record + u8 macaddr[ETH_ALEN]; + u8 RxPWDBAll; + u8 is_tdls_sta; // _TRUE: direct link sta, _FALSE: else +}; + +struct tdls_info{ + u8 ap_prohibited; + uint setup_state; + u8 sta_cnt; + u8 sta_maximum; // 1:tdls sta is equal (NUM_STA-1), reach max direct link number; 0: else; + struct tdls_ss_record ss_record; + u8 macid_index; //macid entry that is ready to write + u8 clear_cam; //cam entry that is trying to clear, using it in direct link teardown + u8 ch_sensing; + u8 cur_channel; + u8 candidate_ch; + u8 collect_pkt_num[MAX_CHANNEL_NUM]; + _lock cmd_lock; + _lock hdl_lock; + u8 watchdog_count; + u8 dev_discovered; //WFD_TDLS: for sigma test + u8 enable; +#ifdef CONFIG_WFD + struct wifi_display_info *wfd_info; +#endif +}; + +#endif //#if 0 + +struct mlme_priv { + + _lock lock; + sint fw_state; //shall we protect this variable? maybe not necessarily... + u8 bScanInProcess; + u8 to_join; //flag + #ifdef CONFIG_LAYER2_ROAMING + u8 to_roaming; // roaming trying times + #endif + + u8 *nic_hdl; //can be removed + + //u8 not_indic_disco; + _list *pscanned; + _queue free_bss_pool; + _queue scanned_queue; + u8 *free_bss_buf; + u16 num_of_scanned; + +#if SUPPORT_SCAN_BUF // Cloud 2013/12/20 + u8 *scan_buf; + u32 scan_buf_len; + u16 scan_cnt; + u16 scan_type; +#endif + + NDIS_802_11_SSID assoc_ssid; + u8 assoc_bssid[6]; + + struct wlan_network cur_network; + + //uint wireless_mode; no used, remove it + + u32 scan_interval; + + _timer assoc_timer; + + u8 assoc_by_bssid; + u8 assoc_by_rssi; + + _timer scan_to_timer; // driver itself handles scan_timeout status. + u32 scan_start_time; // used to evaluate the time spent in scanning + + #ifdef CONFIG_SET_SCAN_DENY_TIMER + _timer set_scan_deny_timer; + ATOMIC_T set_scan_deny; //0: allowed, 1: deny + #endif + + struct qos_priv qospriv; + +#ifdef CONFIG_80211N_HT + + /* Number of non-HT AP/stations */ + u16 num_sta_no_ht; //int num_sta_no_ht; + + /* Number of HT AP/stations 20 MHz */ + //int num_sta_ht_20mhz; + + + u16 num_FortyMHzIntolerant; //int num_FortyMHzIntolerant; + + struct ht_priv htpriv; + +#endif + + RT_LINK_DETECT_T LinkDetectInfo; + _timer dynamic_chk_timer; //dynamic/periodic check timer + + u8 key_mask; //use for ips to set wep key after ips_leave + u8 acm_mask; // for wmm acm mask + u8 ChannelPlan; + RT_SCAN_TYPE scan_mode; // active: 1, passive: 0 + +#ifdef CONFIG_WPS + u8 *wps_probe_req_ie; + u32 wps_probe_req_ie_len; + u8 *wps_assoc_req_ie; + u32 wps_assoc_req_ie_len; +#endif + +#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + /* Number of associated Non-ERP stations (i.e., stations using 802.11b + * in 802.11g BSS) */ + u16 num_sta_non_erp; + + /* Number of associated stations that do not support Short Slot Time */ + u16 num_sta_no_short_slot_time; + + /* Number of associated stations that do not support Short Preamble */ + u16 num_sta_no_short_preamble; + + //int olbc; /* Overlapping Legacy BSS Condition */ + + /* Number of HT associated stations that do not support greenfield */ + u16 num_sta_ht_no_gf; + + /* Number of associated non-HT stations */ + //int num_sta_no_ht; + + /* Number of HT associated stations 20 MHz */ + u16 num_sta_ht_20mhz; + + /* Overlapping BSS information */ + u8 olbc_ht; + +#ifdef CONFIG_80211N_HT + u16 ht_op_mode; +#endif /* CONFIG_80211N_HT */ + +#ifdef CONFIG_WPS + u8 *wps_beacon_ie; + u8 *wps_probe_resp_ie; + u8 *wps_assoc_resp_ie; // for CONFIG_IOCTL_CFG80211, this IE could include p2p ie + + u32 wps_beacon_ie_len; + u32 wps_probe_resp_ie_len; + u32 wps_assoc_resp_ie_len; + + +#ifdef CONFIG_P2P_NEW + u8 *p2p_beacon_ie; + u8 *p2p_probe_req_ie; + u8 *p2p_probe_resp_ie; +// u8 *p2p_go_probe_resp_ie; //for GO + u8 *p2p_assoc_req_ie; + u8 *p2p_assoc_rsp_ie; + + u32 p2p_beacon_ie_len; + u32 p2p_probe_req_ie_len; + u32 p2p_probe_resp_ie_len; +// u32 p2p_go_probe_resp_ie_len; //for GO + u32 p2p_assoc_req_ie_len; + u32 p2p_assoc_rsp_ie_len; +#endif //CONFIG_P2P +#endif //CONFIG_WPS + + _lock bcn_update_lock; + u8 update_bcn; +#if USE_DEDICATED_BCN_TX + //Dedicated xmit frame and buffer for beacon update - Alex Fang + struct xmit_frame bcn_xmit_frame; + struct xmit_buf bcn_xmit_buf; + //u8 bcn_buf[256]; + u8 bcn_buf[320]; //p2p go beacon size is about 272+32 bytes +#endif +#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + +#ifdef RTK_DMP_PLATFORM + // DMP kobject_hotplug function signal need in passive level + _workitem Linkup_workitem; + _workitem Linkdown_workitem; +#endif + +#ifdef CONFIG_INTEL_WIDI + int widi_state; + int listen_state; + _timer listen_timer; + ATOMIC_T rx_probe_rsp; // 1:receive probe respone from RDS source. + u8 *l2sdTaBuffer; + u8 channel_idx; + u8 group_cnt; //In WiDi 3.5, they specified another scan algo. for WFD/RDS co-existed + u8 sa_ext[L2SDTA_SERVICE_VE_LEN]; +#endif // CONFIG_INTEL_WIDI + +#ifdef CONFIG_CONCURRENT_MODE + u8 scanning_via_buddy_intf; +#endif + +#ifdef CONFIG_FTP_PROTECT + u8 ftp_lock_flag; +#endif //CONFIG_FTP_PROTECT + +#ifdef CONFIG_MULTICAST + u32 multicast_list[MULTICAST_LIST_SIZE]; +#endif + //For fast reconnection to keep frame info temporarily + union recv_frame *p_copy_recv_frame; +}; + +#ifdef CONFIG_AP_MODE + +struct hostapd_priv +{ + _adapter *padapter; + +#ifdef CONFIG_HOSTAPD_MLME + struct net_device *pmgnt_netdev; + struct usb_anchor anchored; +#endif + +}; + +extern int hostapd_mode_init(_adapter *padapter); +extern void hostapd_mode_unload(_adapter *padapter); +#endif + + +extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf); +extern void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_atimdone_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_cpwm_event_callback(_adapter *adapter, u8 *pbuf); + +#ifdef PLATFORM_WINDOWS +extern thread_return event_thread(void *context); + +extern void rtw_join_timeout_handler ( + IN PVOID SystemSpecific1, + IN PVOID FunctionContext, + IN PVOID SystemSpecific2, + IN PVOID SystemSpecific3 + ); + +extern void _rtw_scan_timeout_handler ( + IN PVOID SystemSpecific1, + IN PVOID FunctionContext, + IN PVOID SystemSpecific2, + IN PVOID SystemSpecific3 + ); + +#endif + +#if defined (PLATFORM_LINUX)|| defined (PLATFORM_FREEBSD) +extern int event_thread(void *context); +extern void rtw_join_timeout_handler(void* FunctionContext); +extern void _rtw_scan_timeout_handler(void* FunctionContext); +#endif + +extern void rtw_free_network_queue(_adapter *adapter,u8 isfreeall); +extern int rtw_init_mlme_priv(_adapter *adapter);// (struct mlme_priv *pmlmepriv); + +extern void rtw_free_mlme_priv (struct mlme_priv *pmlmepriv); + + +extern sint rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv); +extern sint rtw_set_key(_adapter *adapter,struct security_priv *psecuritypriv,sint keyid, u8 set_tx); +extern sint rtw_set_auth(_adapter *adapter,struct security_priv *psecuritypriv); +extern sint rtw_linked_check(_adapter *padapter); + +__inline static u8 *get_bssid(struct mlme_priv *pmlmepriv) +{ //if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid + // if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address + return pmlmepriv->cur_network.network.MacAddress; +} + +__inline static sint check_fwstate(struct mlme_priv *pmlmepriv, sint state) +{ + if (pmlmepriv->fw_state & state) + return _TRUE; + + return _FALSE; +} + +__inline static sint get_fwstate(struct mlme_priv *pmlmepriv) +{ + return pmlmepriv->fw_state; +} + +/* + * No Limit on the calling context, + * therefore set it to be the critical section... + * + * ### NOTE:#### (!!!!) + * MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock + */ +__inline static void set_fwstate(struct mlme_priv *pmlmepriv, sint state) +{ + pmlmepriv->fw_state |= state; + //FOR HW integration + if(_FW_UNDER_SURVEY==state){ + pmlmepriv->bScanInProcess = _TRUE; + } +} + +__inline static void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state) +{ + pmlmepriv->fw_state &= ~state; + //FOR HW integration + if(_FW_UNDER_SURVEY==state){ + pmlmepriv->bScanInProcess = _FALSE; + } +} + +/* + * No Limit on the calling context, + * therefore set it to be the critical section... + */ +__inline static void clr_fwstate(struct mlme_priv *pmlmepriv, sint state) +{ + _irqL irqL; + + rtw_enter_critical_bh(&pmlmepriv->lock, &irqL); + if (check_fwstate(pmlmepriv, state) == _TRUE) + pmlmepriv->fw_state ^= state; + rtw_exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +__inline static void clr_fwstate_ex(struct mlme_priv *pmlmepriv, sint state) +{ + _irqL irqL; + + rtw_enter_critical_bh(&pmlmepriv->lock, &irqL); + _clr_fwstate_(pmlmepriv, state); + rtw_exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +__inline static void up_scanned_network(struct mlme_priv *pmlmepriv) +{ + _irqL irqL; + + rtw_enter_critical_bh(&pmlmepriv->lock, &irqL); + pmlmepriv->num_of_scanned++; + rtw_exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +#ifdef CONFIG_CONCURRENT_MODE +sint rtw_buddy_adapter_up(_adapter *padapter); +sint check_buddy_fwstate(_adapter *padapter, sint state); +#endif //CONFIG_CONCURRENT_MODE + +__inline static void down_scanned_network(struct mlme_priv *pmlmepriv) +{ + _irqL irqL; + + rtw_enter_critical_bh(&pmlmepriv->lock, &irqL); + pmlmepriv->num_of_scanned--; + rtw_exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +__inline static void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint val) +{ + _irqL irqL; + + rtw_enter_critical_bh(&pmlmepriv->lock, &irqL); + pmlmepriv->num_of_scanned = val; + rtw_exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +extern u16 rtw_get_capability(WLAN_BSSID_EX *bss); +extern void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target); +extern void rtw_disconnect_hdl_under_linked(_adapter* adapter, struct sta_info *psta, u8 free_assoc); +extern void rtw_generate_random_ibss(u8 *pibss); +extern struct wlan_network* rtw_find_network(_queue *scanned_queue, u8 *addr); +extern struct wlan_network* rtw_get_oldest_wlan_network(_queue *scanned_queue); + +extern void rtw_free_assoc_resources(_adapter* adapter, int lock_scanned_queue); +extern void rtw_indicate_disconnect(_adapter* adapter); +extern void rtw_indicate_connect(_adapter* adapter); +void rtw_indicate_scan_done( _adapter *padapter, bool aborted); +void rtw_scan_abort(_adapter *adapter); + +extern int rtw_restruct_sec_ie(_adapter *adapter,u8 *in_ie,u8 *out_ie,uint in_len); +extern int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len); +//extern void rtw_init_registrypriv_dev_network(_adapter *adapter); + +//extern void rtw_update_registrypriv_dev_network(_adapter *adapter); + +extern void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter); + +extern void _rtw_join_timeout_handler(_adapter *adapter); +extern void rtw_scan_timeout_handler(_adapter *adapter); + +extern void rtw_dynamic_check_timer_handlder(_adapter *adapter); +#ifdef CONFIG_SET_SCAN_DENY_TIMER +extern void rtw_set_scan_deny_timer_hdl(_adapter *adapter); +void rtw_set_scan_deny(struct mlme_priv *mlmepriv, u32 ms); +#endif + + +extern int _rtw_init_mlme_priv(_adapter *padapter); + +void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv); + +extern void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv); + +extern int _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork); + +extern struct wlan_network* _rtw_dequeue_network(_queue *queue); + +extern struct wlan_network* _rtw_alloc_network(struct mlme_priv *pmlmepriv); + + +extern void _rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 isfreeall); +extern void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork); + + +extern struct wlan_network* _rtw_find_network(_queue *scanned_queue, u8 *addr); + +extern void _rtw_free_network_queue(_adapter* padapter, u8 isfreeall); + +extern sint rtw_if_up(_adapter *padapter); + + +u8 *rtw_get_capability_from_ie(u8 *ie); +u8 *rtw_get_timestampe_from_ie(u8 *ie); +u8 *rtw_get_beacon_interval_from_ie(u8 *ie); + + +void rtw_joinbss_reset(_adapter *padapter); + +#ifdef CONFIG_80211N_HT +unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len); +void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len); +void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe); +#endif + +int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork); +int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst); + +#ifdef CONFIG_LAYER2_ROAMING +void rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network); +void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network); +#endif + + +#ifdef CONFIG_INTEL_PROXIM +void rtw_proxim_enable(_adapter *padapter); +void rtw_proxim_disable(_adapter *padapter); +void rtw_proxim_send_packet(_adapter *padapter,u8 *pbuf,u16 len,u8 hw_rate); +#endif //CONFIG_INTEL_PROXIM + +extern void rtw_os_indicate_disconnect( _adapter *adapter ); +extern void rtw_os_indicate_scan_done( _adapter *padapter, bool aborted); +extern void rtw_reset_securitypriv( _adapter *adapter ); +#endif //__RTL871X_MLME_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_mlme_ext.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_mlme_ext.h new file mode 100644 index 0000000..b504f25 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_mlme_ext.h @@ -0,0 +1,1014 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_MLME_EXT_H_ +#define __RTW_MLME_EXT_H_ + + +// Commented by Albert 20101105 +// Increase the SURVEY_TO value from 100 to 150 ( 100ms to 150ms ) +// The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request. +// So, this driver tried to extend the dwell time for each scanning channel. +// This will increase the chance to receive the probe response from SoftAP. + +#if CONFIG_AUTO_RECONNECT + +#endif + +//TODO +#define FAST_SURVEY_TO (25) //Fast connection time, scan only partial channel +#define SURVEY_TO (100) //Reduce connection time +//#define SURVEY_TO (300) //Increase time to stay each channel - Alex Fang +#define REAUTH_TO (300) //(50) +#define REASSOC_TO (300) //(50) +//#define DISCONNECT_TO (3000) +#define ADDBA_TO (2000) + +#define LINKED_TO (1) //unit:2 sec, 1x2=2 sec + +#define REAUTH_LIMIT (4) +#define REASSOC_LIMIT (4) +#define READDBA_LIMIT (2) + +#if (defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI) + #define ROAMING_LIMIT 5 +#else + #define ROAMING_LIMIT 8 +#endif +//#define IOCMD_REG0 0x10250370 +//#define IOCMD_REG1 0x10250374 +//#define IOCMD_REG2 0x10250378 + +//#define FW_DYNAMIC_FUN_SWITCH 0x10250364 + +//#define WRITE_BB_CMD 0xF0000001 +//#define SET_CHANNEL_CMD 0xF3000000 +//#define UPDATE_RA_CMD 0xFD0000A2 + +#define _HW_STATE_NOLINK_ 0x00 +#define _HW_STATE_ADHOC_ 0x01 +#define _HW_STATE_STATION_ 0x02 +#define _HW_STATE_AP_ 0x03 +#define _HW_STATE_MONITOR_ 0x04 + + +#define _1M_RATE_ 0 +#define _2M_RATE_ 1 +#define _5M_RATE_ 2 +#define _11M_RATE_ 3 +#define _6M_RATE_ 4 +#define _9M_RATE_ 5 +#define _12M_RATE_ 6 +#define _18M_RATE_ 7 +#define _24M_RATE_ 8 +#define _36M_RATE_ 9 +#define _48M_RATE_ 10 +#define _54M_RATE_ 11 + +#define MAX_COUNTRY_NUM 250 + +extern const u8 WMM_OUI[]; +extern const u8 WPS_OUI[]; +extern const u8 WFD_OUI[]; +extern const u8 P2P_OUI[]; + +//extern const unsigned char WMM_INFO_OUI[]; +extern const u8 WMM_PARA_OUI[]; + + +// +// Channel Plan Type. +// Note: +// We just add new channel plan when the new channel plan is different from any of the following +// channel plan. +// If you just wnat to customize the acitions(scan period or join actions) about one of the channel plan, +// customize them in RT_CHANNEL_INFO in the RT_CHANNEL_LIST. +// +typedef enum _RT_CHANNEL_DOMAIN +{ + //===== old channel plan mapping =====// + RT_CHANNEL_DOMAIN_FCC = 0x00, + RT_CHANNEL_DOMAIN_IC = 0x01, + RT_CHANNEL_DOMAIN_ETSI = 0x02, + RT_CHANNEL_DOMAIN_SPAIN = 0x03, + RT_CHANNEL_DOMAIN_FRANCE = 0x04, + RT_CHANNEL_DOMAIN_MKK = 0x05, + RT_CHANNEL_DOMAIN_MKK1 = 0x06, + RT_CHANNEL_DOMAIN_ISRAEL = 0x07, + RT_CHANNEL_DOMAIN_TELEC = 0x08, + RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN = 0x09, + RT_CHANNEL_DOMAIN_WORLD_WIDE_13 = 0x0A, + RT_CHANNEL_DOMAIN_TAIWAN = 0x0B, + RT_CHANNEL_DOMAIN_CHINA = 0x0C, + RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO = 0x0D, + RT_CHANNEL_DOMAIN_KOREA = 0x0E, + RT_CHANNEL_DOMAIN_TURKEY = 0x0F, + RT_CHANNEL_DOMAIN_JAPAN = 0x10, + RT_CHANNEL_DOMAIN_FCC_NO_DFS = 0x11, + RT_CHANNEL_DOMAIN_JAPAN_NO_DFS = 0x12, + RT_CHANNEL_DOMAIN_WORLD_WIDE_5G = 0x13, + RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS = 0x14, + + //===== new channel plan mapping, (2GDOMAIN_5GDOMAIN) =====// + // 2.4 G only + RT_CHANNEL_DOMAIN_WORLD_NULL = 0x20, // ETSI, MKK ch1~13 + RT_CHANNEL_DOMAIN_ETSI1_NULL = 0x21, + RT_CHANNEL_DOMAIN_FCC1_NULL = 0x22, // FCC ch1~11 + RT_CHANNEL_DOMAIN_MKK1_NULL = 0x23, // MKK ch1~14 + RT_CHANNEL_DOMAIN_ETSI2_NULL = 0x24, + // 2.4 G + 5G type 1 + RT_CHANNEL_DOMAIN_FCC1_FCC1 = 0x25, + RT_CHANNEL_DOMAIN_WORLD_ETSI1 = 0x26, + RT_CHANNEL_DOMAIN_MKK1_MKK1 = 0x27, + RT_CHANNEL_DOMAIN_WORLD_KCC1 = 0x28, + RT_CHANNEL_DOMAIN_WORLD_FCC2 = 0x29, + RT_CHANNEL_DOMAIN_FCC2_NULL = 0x2A, // FCC ch1~13 + RT_CHANNEL_DOMAIN_WORLD_FCC3 = 0x30, + RT_CHANNEL_DOMAIN_WORLD_FCC4 = 0x31, + RT_CHANNEL_DOMAIN_WORLD_FCC5 = 0x32, + RT_CHANNEL_DOMAIN_WORLD_FCC6 = 0x33, + RT_CHANNEL_DOMAIN_FCC1_FCC7 = 0x34, + RT_CHANNEL_DOMAIN_WORLD_ETSI2 = 0x35, + RT_CHANNEL_DOMAIN_WORLD_ETSI3 = 0x36, + RT_CHANNEL_DOMAIN_MKK1_MKK2 = 0x37, + RT_CHANNEL_DOMAIN_MKK1_MKK3 = 0x38, + RT_CHANNEL_DOMAIN_FCC1_NCC1 = 0x39, + RT_CHANNEL_DOMAIN_FCC1_NCC2 = 0x40, + RT_CHANNEL_DOMAIN_GLOBAL_NULL = 0x41, + RT_CHANNEL_DOMAIN_ETSI1_ETSI4 = 0x42, + RT_CHANNEL_DOMAIN_FCC1_FCC2 = 0x43, + RT_CHANNEL_DOMAIN_FCC1_NCC3 = 0x44, + RT_CHANNEL_DOMAIN_WORLD_ETSI5 = 0x45, + RT_CHANNEL_DOMAIN_FCC1_FCC8 = 0x46, + RT_CHANNEL_DOMAIN_WORLD_ETSI6 = 0x47, // ETSI, MKK, FCC ch1~13 + RT_CHANNEL_DOMAIN_WORLD_ETSI7 = 0x48, + RT_CHANNEL_DOMAIN_WORLD_ETSI8 = 0x49, + RT_CHANNEL_DOMAIN_WORLD_ETSI9 = 0x50, + RT_CHANNEL_DOMAIN_WORLD_ETSI10 = 0x51, + RT_CHANNEL_DOMAIN_WORLD_ETSI11 = 0x52, + RT_CHANNEL_DOMAIN_FCC1_NCC4 = 0x53, + RT_CHANNEL_DOMAIN_WORLD_ETSI12 = 0x54, + RT_CHANNEL_DOMAIN_FCC1_FCC9 = 0x55, + RT_CHANNEL_DOMAIN_WORLD_ETSI13 = 0x56, + RT_CHANNEL_DOMAIN_FCC1_FCC10 = 0x57, + RT_CHANNEL_DOMAIN_MKK2_MKK4 = 0x58, // MKK ch1~13 + //===== Add new channel plan above this line===============// + RT_CHANNEL_DOMAIN_MAX, + RT_CHANNEL_DOMAIN_REALTEK_DEFINE = 0x7F, +}RT_CHANNEL_DOMAIN, *PRT_CHANNEL_DOMAIN; + +typedef enum _RT_CHANNEL_DOMAIN_2G +{ + RT_CHANNEL_DOMAIN_2G_WORLD1 = 0x00, //Worldwird 13, ch1~13 (ETSI, MKK) + RT_CHANNEL_DOMAIN_2G_ETSI1 = 0x01, //Europe, ch1~13 + RT_CHANNEL_DOMAIN_2G_FCC1 = 0x02, //US, ch1~11 + RT_CHANNEL_DOMAIN_2G_MKK1 = 0x03, //Japan, ch1~14 + RT_CHANNEL_DOMAIN_2G_ETSI2 = 0x04, //France, ch10~13 + RT_CHANNEL_DOMAIN_2G_RCC2 = 0x05, //US, ch1~13 + RT_CHANNEL_DOMAIN_2G_MKK2 = 0x06, //Japan, ch1~13 + RT_CHANNEL_DOMAIN_2G_WORLD2 = 0x07, //Worldwird 13, ch1~13 (ETSI, MKK, FCC) + //===== Add new channel plan above this line===============// + RT_CHANNEL_DOMAIN_2G_MAX, +}RT_CHANNEL_DOMAIN_2G, *PRT_CHANNEL_DOMAIN_2G; + +typedef enum _RT_CHANNEL_DOMAIN_5G +{ + RT_CHANNEL_DOMAIN_5G_NULL = 0x00, + RT_CHANNEL_DOMAIN_5G_ETSI1 = 0x01, //Europe + RT_CHANNEL_DOMAIN_5G_ETSI2 = 0x02, //Australia, New Zealand + RT_CHANNEL_DOMAIN_5G_ETSI3 = 0x03, //Russia + RT_CHANNEL_DOMAIN_5G_FCC1 = 0x04, //US + RT_CHANNEL_DOMAIN_5G_FCC2 = 0x05, //FCC o/w DFS Channels + RT_CHANNEL_DOMAIN_5G_FCC3 = 0x06, //India, Mexico + RT_CHANNEL_DOMAIN_5G_FCC4 = 0x07, //Venezuela + RT_CHANNEL_DOMAIN_5G_FCC5 = 0x08, //China + RT_CHANNEL_DOMAIN_5G_FCC6 = 0x09, //Israel + RT_CHANNEL_DOMAIN_5G_FCC7_IC1 = 0x0A, //US, Canada + RT_CHANNEL_DOMAIN_5G_KCC1 = 0x0B, //Korea + RT_CHANNEL_DOMAIN_5G_MKK1 = 0x0C, //Japan + RT_CHANNEL_DOMAIN_5G_MKK2 = 0x0D, //Japan (W52, W53) + RT_CHANNEL_DOMAIN_5G_MKK3 = 0x0E, //Japan (W56) + RT_CHANNEL_DOMAIN_5G_NCC1 = 0x0F, //Taiwan + RT_CHANNEL_DOMAIN_5G_NCC2 = 0x10, //Taiwan o/w DFS + //===== Add new channel plan above this line===============// + //===== Driver Self Defined =====// + RT_CHANNEL_DOMAIN_5G_FCC = 0x11, + RT_CHANNEL_DOMAIN_5G_JAPAN_NO_DFS = 0x12, + RT_CHANNEL_DOMAIN_5G_MAX, +}RT_CHANNEL_DOMAIN_5G, *PRT_CHANNEL_DOMAIN_5G; + +#define rtw_is_channel_plan_valid(chplan) (chplancur_network.network. YJ,del,140408 + struct FW_Sta_Info FW_sta_info[NUM_STA]; + +#ifdef CONFIG_STA_MODE_SCAN_UNDER_AP_MODE + u8 scan_cnt; +#endif //CONFIG_STA_MODE_SCAN_UNDER_AP_MODE +}; + +// The channel information about this channel including joining, scanning, and power constraints. +#define PSCAN_ENABLE 0x01 //enable for partial channel scan +#define PSCAN_FAST_SURVEY 0x02 //set to select scan time to FAST_SURVEY_TO and resend probe request +#define PSCAN_SIMPLE_CONFIG 0x04 //set to select scan time to FAST_SURVEY_TO and resend probe request +#define PSCAN_SET_SSID_DONE 0x80 //When receive probe response, this bit is set to 1 + +#define PSCAN_DISABLE_MASK 0xFE //disable PSCAN_ENABLE +#define PSCAN_CLEAR_SSID_DONE 0x7F //clear PSCAN_SET_SSID_DONE +#define PSCAN_RETRY_TIMES 7 //the retry times of resending probe request when PSCAN_FAST_SURVEY is set + +typedef struct _RT_CHANNEL_INFO +{ + u8 ChannelNum; // The channel number. + RT_SCAN_TYPE ScanType; // Scan type such as passive or active scan. + //u16 ScanPeriod; // Listen time in millisecond in this channel. + //s32 MaxTxPwrDbm; // Max allowed tx power. + //u32 ExInfo; // Extended Information for this channel. +#ifdef CONFIG_FIND_BEST_CHANNEL + u32 rx_count; +#endif + u8 pscan_config; +}RT_CHANNEL_INFO, *PRT_CHANNEL_INFO; + +extern int rtw_is_channel_set_contains_channel(RT_CHANNEL_INFO *channel_set, const u32 channel_num, int *pchannel_idx); + +#ifdef CONFIG_CUSTOM_IE +#ifndef _CUS_IE_ +#define _CUS_IE_ +typedef struct _cus_ie +{ + u8 *ie; + u8 type; +}rtw_custom_ie_t, *p_rtw_custom_ie_t; +#endif /* _CUS_IE_ */ +#endif + +struct mlme_ext_priv +{ + _adapter *padapter; + u8 mlmeext_init; + ATOMIC_T event_seq; + u16 mgnt_seq; + + //struct fw_priv fwpriv; + + u8 cur_channel; + u8 cur_bwmode; + u8 cur_ch_offset;//PRIME_CHNL_OFFSET + u8 cur_wireless_mode; // NETWORK_TYPE + u8 max_chan_nums; + RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM]; +#ifdef CONFIG_P2P_NEW + RT_CHANNEL_INFO social_channel_set[4]; + RT_CHANNEL_INFO special_channel[2]; + u8 special_mac[ETH_ALEN]; + u16 scan_mode; + u8 bremain_on_channel; + _timer remainon_timer; +#endif + u8 basicrate[NumRates]; + u8 datarate[NumRates]; + + struct ss_res sitesurvey_res; + struct mlme_ext_info mlmext_info;//for sta/adhoc mode, including current scanning/connecting/connected related info. + //for ap mode, network includes ap's cap_info + _timer survey_timer; + _timer link_timer; + //_timer ADDBA_timer; + u16 chan_scan_time; + + u8 scan_abort; + u8 tx_rate; // TXRATE when USERATE is set. + + u8 retry; //retry for issue probereq + + u64 TSFValue; + +#ifdef CONFIG_AP_MODE + unsigned char bstart_bss; +#endif + +#ifdef CONFIG_80211D + u8 update_channel_plan_by_ap_done; +#endif + //recv_decache check for Action_public frame + u16 action_public_rxseq; + + /* for softap power save */ +#ifdef CONFIG_P2P_NEW + u8 action_public_dialog_token; +#endif +#if CONFIG_AUTO_RECONNECT + _timer reconnect_timer; + u8 reconnect_deauth_filtered; + u8 reconnect_times; + u8 reconnect_cnt; + u16 reconnect_timeout; // the unit is second + u8 saved_alg; + u8 saved_essid[32+1]; + u8 saved_key[32]; + u16 saved_key_len; + u8 saved_key_idx; + u8 saved_wpa_passphrase[IW_PASSPHRASE_MAX_SIZE + 1]; + u8 saved_eap_method; + u8 auto_reconnect; +#endif + u8 partial_scan; +#ifdef CONFIG_CUSTOM_IE + p_rtw_custom_ie_t cus_ven_ie; + u8 ie_num; +#endif + +#ifdef CONFIG_CONCURRENT_MODE + u8 bChDeauthDisabled; + u8 bConcurrentFlushingSTA; +#endif +}; + +int init_mlme_ext_priv(_adapter* padapter); +int init_hw_mlme_ext(_adapter *padapter); +void free_mlme_ext_priv (struct mlme_ext_priv *pmlmeext); +extern void init_mlme_ext_timer(_adapter *padapter); +extern void init_addba_retry_timer(_adapter *padapter, struct sta_info *psta); +extern struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv); +extern struct xmit_frame *alloc_FwRsvdframe(struct xmit_priv *pxmitpriv, u32 size); +//void fill_fwpriv(_adapter * padapter, struct fw_priv *pfwpriv); + +unsigned char networktype_to_raid(unsigned char network_type); +u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen); +void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len); +void UpdateBrateTbl(_adapter *padapter,u8 *mBratesOS); +void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen); + +void Save_DM_Func_Flag(_adapter *padapter); +void Restore_DM_Func_Flag(_adapter *padapter); +void Switch_DM_Func(_adapter *padapter, u32 mode, u8 enable); + +//void Set_NETYPE1_MSR(_adapter *padapter, u8 type); +//void Set_NETYPE0_MSR(_adapter *padapter, u8 type); +void Set_MSR(_adapter *padapter, u8 type); + +u8 set_opmode(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype); +void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode); +void SelectChannel(_adapter *padapter, unsigned char channel); +void SetBWMode(_adapter *padapter, unsigned short bwmode, unsigned char channel_offset); + +unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval); + +void write_cam(_adapter *padapter, u8 entry, u16 ctrl, u8 *mac, u8 *key); +void clear_cam_entry(_adapter *padapter, u8 entry); + +void invalidate_cam_all(_adapter *padapter); +void CAM_empty_entry(PADAPTER Adapter, u8 ucIndex); + + +int allocate_fw_sta_entry(_adapter *padapter); +void flush_all_cam_entry(_adapter *padapter); + +BOOLEAN IsLegal5GChannel(PADAPTER Adapter, u8 channel); + +void site_survey(_adapter *padapter); +u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid); +void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, _adapter * padapter, bool update_ie); + +int get_bsstype(unsigned short capability); +u8* get_my_bssid(WLAN_BSSID_EX *pnetwork); +u16 get_beacon_interval(WLAN_BSSID_EX *bss); + +int is_client_associated_to_ap(_adapter *padapter); +int is_client_associated_to_ibss(_adapter *padapter); +int is_IBSS_empty(_adapter *padapter); + +unsigned char check_assoc_AP(u8 *pframe, uint len); + +int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +#ifdef CONFIG_WFD +int WFD_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +#endif +void WMMOnAssocRsp(_adapter *padapter); + +void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void HTOnAssocRsp(_adapter *padapter); + +void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void VCS_update(_adapter *padapter, struct sta_info *psta); + +void update_beacon_info(_adapter *padapter, u8 *pframe, uint len, struct sta_info *psta); +int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len); +#ifdef CONFIG_DFS +void process_csa_ie(_adapter *padapter, u8 *pframe, uint len); +#endif //CONFIG_DFS +void update_IOT_info(_adapter *padapter); +void update_capinfo(PADAPTER Adapter, u16 updateCap); +void update_wireless_mode(_adapter * padapter); +void update_tx_basic_rate(_adapter *padapter, u8 modulation); +void update_bmc_sta_support_rate(_adapter *padapter, u32 mac_id); +int update_sta_support_rate(_adapter *padapter, u8* pvar_ie, uint var_ie_len, int cam_idx); + +//for sta/adhoc mode +void update_sta_info(_adapter *padapter, struct sta_info *psta); +unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz); +unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz); +unsigned int update_MCS_rate(struct HT_caps_element *pHT_caps); +void Update_RA_Entry(_adapter *padapter, struct sta_info *psta); +void set_sta_rate(_adapter *padapter, struct sta_info *psta); + +unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason); + +unsigned char get_highest_rate_idx(u32 mask); +int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps); +unsigned int is_ap_in_tkip(_adapter *padapter); +unsigned int is_ap_in_wep(_adapter *padapter); +unsigned int should_forbid_n_rate(_adapter * padapter); + +void report_join_res(_adapter *padapter, int res); +void report_survey_event(_adapter *padapter, union recv_frame *precv_frame); +void report_surveydone_event(_adapter *padapter); +void report_del_sta_event(_adapter *padapter, unsigned char* MacAddr, unsigned short reason); +void report_add_sta_event(_adapter *padapter, unsigned char* MacAddr, int cam_idx); + +void beacon_timing_control(_adapter *padapter); +extern u8 set_tx_beacon_cmd(_adapter*padapter); +unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame); +void update_mgnt_tx_rate(_adapter *padapter, u8 rate); +void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib); +void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe); +s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms); + +#ifdef CONFIG_P2P +void issue_probersp_p2p(_adapter *padapter, unsigned char *da); +void issue_p2p_provision_request( _adapter *padapter, u8* pssid, u8 ussidlen, u8* pdev_raddr); +void issue_p2p_GO_request(_adapter *padapter, u8* raddr); +void issue_probereq_p2p(_adapter *padapter); +void issue_p2p_invitation_response(_adapter *padapter, u8* raddr, u8 dialogToken, u8 success); +void issue_p2p_invitation_request(_adapter *padapter, u8* raddr ); +#endif //CONFIG_P2P +void issue_beacon(_adapter *padapter); +void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq); +void issue_assocreq(_adapter *padapter); +void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type); +void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status); +// Added by Albert 2010/07/26 +// blnbc: 1 -> broadcast probe request +// blnbc: 0 -> unicast probe request. The address 1 will be the BSSID. +void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 blnbc); +void issue_nulldata(_adapter *padapter, unsigned int power_mode); +void issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid); +void issue_deauth(_adapter *padapter, unsigned char *da, u32 reason); +void issue_action_BA(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short status); +unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr); +unsigned int send_beacon(_adapter *padapter); + +void start_clnt_assoc(_adapter *padapter); +void start_clnt_auth(_adapter* padapter); +void start_clnt_join(_adapter* padapter); +void start_create_ibss(_adapter* padapter); + +unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame); +unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame); + +unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_public(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame); + + +void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res); +void mlmeext_sta_del_event_callback(_adapter *padapter); +void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta); + +void linked_status_chk(_adapter *padapter); + +void survey_timer_hdl (_adapter *padapter); +void link_timer_hdl (_adapter *padapter); +void addba_timer_hdl(struct sta_info *psta); +//void reauth_timer_hdl(_adapter *padapter); +//void reassoc_timer_hdl(_adapter *padapter); + +#define set_survey_timer(mlmeext, ms) \ + do { \ + /*DBG_871X("%s set_survey_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ + rtw_set_timer(&(mlmeext)->survey_timer, (ms)); \ + } while(0) + +#define set_link_timer(mlmeext, ms) \ + do { \ + /*DBG_871X("%s set_link_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ + rtw_set_timer(&(mlmeext)->link_timer, (ms)); \ + } while(0) + +//TODO +#if 0 +extern int cckrates_included(unsigned char *rate, int ratelen); +extern int cckratesonly_included(unsigned char *rate, int ratelen); +extern void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr); +#endif + +extern void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len); +extern void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext); + +#ifdef CONFIG_CONCURRENT_MODE + sint check_buddy_mlmeinfo_state(_adapter *padapter, u32 state); +int concurrent_chk_start_clnt_join(_adapter *padapter); +void concurrent_chk_joinbss_done(_adapter *padapter, int join_res); +#endif //CONFIG_CONCURRENT_MODE + + +struct cmd_hdl { + uint parmsize; + u8 (*h2cfuns)(struct _ADAPTER *padapter, u8 *pbuf); +}; + +//TODO +#if 0 + +u8 read_macreg_hdl(_adapter *padapter, u8 *pbuf); +u8 write_macreg_hdl(_adapter *padapter, u8 *pbuf); +u8 read_bbreg_hdl(_adapter *padapter, u8 *pbuf); +u8 write_bbreg_hdl(_adapter *padapter, u8 *pbuf); +u8 read_rfreg_hdl(_adapter *padapter, u8 *pbuf); +u8 write_rfreg_hdl(_adapter *padapter, u8 *pbuf); + +#endif //#if 0 + +u8 NULL_hdl(_adapter *padapter, u8 *pbuf); +u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf); +u8 disconnect_hdl(_adapter *padapter, u8 *pbuf); +u8 createbss_hdl(_adapter *padapter, u8 *pbuf); +u8 setopmode_hdl(_adapter *padapter, u8 *pbuf); +u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf); +u8 setauth_hdl(_adapter *padapter, u8 *pbuf); +u8 setkey_hdl(_adapter *padapter, u8 *pbuf); +u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf); +u8 set_assocsta_hdl(_adapter *padapter, u8 *pbuf); +u8 del_assocsta_hdl(_adapter *padapter, u8 *pbuf); +u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf); + +u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf); +u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf); +u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf); +u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf); +u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf); +u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf); //Kurt: Handling DFS channel switch announcement ie. +u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf); + +#if CONFIG_AUTO_RECONNECT +extern void reconnect_timer_hdl(void *FunctionContext); +#endif + +#define GEN_DRV_CMD_HANDLER(size, cmd) {size, &cmd ## _hdl}, +#define GEN_MLME_EXT_HANDLER(size, cmd) {size, cmd}, + +#ifdef _RTW_CMD_C_ + +const struct cmd_hdl wlancmds[] = +{ + GEN_DRV_CMD_HANDLER(0, NULL) /*0*/ + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) /*10*/ + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct joinbss_parm), join_cmd_hdl) /*14*/ + GEN_MLME_EXT_HANDLER(sizeof (struct disconnect_parm), disconnect_hdl) +//TODO +// GEN_MLME_EXT_HANDLER(sizeof (struct createbss_parm), createbss_hdl) + GEN_MLME_EXT_HANDLER(sizeof (struct createbss_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct setopmode_parm), setopmode_hdl) + GEN_MLME_EXT_HANDLER(sizeof (struct sitesurvey_parm), sitesurvey_cmd_hdl) /*18*/ + GEN_MLME_EXT_HANDLER(sizeof (struct setauth_parm), setauth_hdl) + GEN_MLME_EXT_HANDLER(sizeof (struct setkey_parm), setkey_hdl) /*20*/ + GEN_MLME_EXT_HANDLER(sizeof (struct set_stakey_parm), set_stakey_hdl) + GEN_MLME_EXT_HANDLER(sizeof (struct set_assocsta_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct del_assocsta_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct setstapwrstate_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct setbasicrate_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct getbasicrate_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct setdatarate_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct getdatarate_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct setphyinfo_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct getphyinfo_parm), NULL) /*30*/ + GEN_MLME_EXT_HANDLER(sizeof (struct setphy_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct getphy_parm), NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) /*40*/ + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) +//TODO +#if RX_AGGREGATION + GEN_MLME_EXT_HANDLER(sizeof(struct addBaReq_parm), add_ba_hdl) +#else + GEN_MLME_EXT_HANDLER(sizeof(struct addBaReq_parm), NULL) +#endif + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) /*50*/ + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(sizeof(struct Tx_Beacon_param), tx_beacon_hdl) /*55*/ + GEN_MLME_EXT_HANDLER(0, mlme_evt_hdl) /*56*/ + GEN_MLME_EXT_HANDLER(0, rtw_drvextra_cmd_hdl) /*57*/ +//TODO +// GEN_MLME_EXT_HANDLER(0, h2c_msg_hdl) /*58*/ + GEN_MLME_EXT_HANDLER(0, NULL) /*58*/ +//TODO +// GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelPlan_param), set_chplan_hdl) /*59*/ + GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelPlan_param), NULL) /*59*/ +//TODO +// GEN_MLME_EXT_HANDLER(sizeof(struct LedBlink_param), led_blink_hdl) /*60*/ + GEN_MLME_EXT_HANDLER(0, NULL) /*60*/ +//TODO +// GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelSwitch_param), set_csa_hdl) /*61*/ + GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelSwitch_param), NULL) /*61*/ +//TODO +// GEN_MLME_EXT_HANDLER(sizeof(struct TDLSoption_param), tdls_hdl) /*62*/ + GEN_MLME_EXT_HANDLER(sizeof(struct TDLSoption_param), NULL) /*62*/ +#ifdef CONFIG_P2P_NEW + GEN_MLME_EXT_HANDLER(0, rtw_p2p_cmd_hdl) /*63*/ +#endif +}; + +#endif + +struct C2HEvent_Header +{ + +#ifdef CONFIG_LITTLE_ENDIAN + + unsigned int len:16; + unsigned int ID:8; + unsigned int seq:8; + +#elif defined(CONFIG_BIG_ENDIAN) + + unsigned int seq:8; + unsigned int ID:8; + unsigned int len:16; + +#else + +# error "Must be LITTLE or BIG Endian" + +#endif + + unsigned int rsvd; + +}; + +void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf); +void rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf); + +enum rtw_c2h_event +{ + GEN_EVT_CODE(_Read_MACREG)=0, /*0*/ + GEN_EVT_CODE(_Read_BBREG), + GEN_EVT_CODE(_Read_RFREG), + GEN_EVT_CODE(_Read_EEPROM), + GEN_EVT_CODE(_Read_EFUSE), + GEN_EVT_CODE(_Read_CAM), /*5*/ + GEN_EVT_CODE(_Get_BasicRate), + GEN_EVT_CODE(_Get_DataRate), + GEN_EVT_CODE(_Survey), /*8*/ + GEN_EVT_CODE(_SurveyDone), /*9*/ + + GEN_EVT_CODE(_JoinBss) , /*10*/ + GEN_EVT_CODE(_AddSTA), + GEN_EVT_CODE(_DelSTA), + GEN_EVT_CODE(_AtimDone) , + GEN_EVT_CODE(_TX_Report), + GEN_EVT_CODE(_CCX_Report), /*15*/ + GEN_EVT_CODE(_DTM_Report), + GEN_EVT_CODE(_TX_Rate_Statistics), + GEN_EVT_CODE(_C2HLBK), + GEN_EVT_CODE(_FWDBG), + GEN_EVT_CODE(_C2HFEEDBACK), /*20*/ + GEN_EVT_CODE(_ADDBA), + GEN_EVT_CODE(_C2HBCN), + GEN_EVT_CODE(_ReportPwrState), //filen: only for PCIE, USB + GEN_EVT_CODE(_CloseRF), //filen: only for PCIE, work around ASPM + MAX_C2HEVT +}; + + +#ifdef _RTW_MLME_EXT_C_ + +const static struct fwevent wlanevents[] = +{ + {0, rtw_dummy_event_callback}, /*0*/ + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, &rtw_survey_event_callback}, /*8*/ + {sizeof (struct surveydone_event), &rtw_surveydone_event_callback}, /*9*/ + {0, &rtw_joinbss_event_callback}, /*10*/ + {sizeof(struct stassoc_event), &rtw_stassoc_event_callback}, + {sizeof(struct stadel_event), &rtw_stadel_event_callback}, +//TODO +// {0, &rtw_atimdone_event_callback}, + {0, NULL}, /*rtw_atimdone_event_callback*/ + {0, rtw_dummy_event_callback}, + {0, NULL}, /*15*/ + {0, NULL}, + {0, NULL}, + {0, NULL}, +//TODO +// {0, rtw_fwdbg_event_callback}, + {0, NULL}, /*rtw_fwdbg_event_callback*/ + {0, NULL}, /*20*/ + {0, NULL}, + {0, NULL}, +//TODO +// {0, &rtw_cpwm_event_callback}, + {0, NULL}, /*rtw_cpwm_event_callback*/ +}; + +#endif//_RTL8192C_CMD_C_ + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_mp.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_mp.h new file mode 100644 index 0000000..f8f8253 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_mp.h @@ -0,0 +1,722 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_MP_H_ +#define _RTW_MP_H_ + +#ifndef PLATFORM_WINDOWS +// 00 - Success +// 11 - Error +#define STATUS_SUCCESS (0x00000000L) +#define STATUS_PENDING (0x00000103L) + +#define STATUS_UNSUCCESSFUL (0xC0000001L) +#define STATUS_INSUFFICIENT_RESOURCES (0xC000009AL) +#define STATUS_NOT_SUPPORTED (0xC00000BBL) + +#define NDIS_STATUS_SUCCESS ((NDIS_STATUS)STATUS_SUCCESS) +#define NDIS_STATUS_PENDING ((NDIS_STATUS)STATUS_PENDING) +#define NDIS_STATUS_NOT_RECOGNIZED ((NDIS_STATUS)0x00010001L) +#define NDIS_STATUS_NOT_COPIED ((NDIS_STATUS)0x00010002L) +#define NDIS_STATUS_NOT_ACCEPTED ((NDIS_STATUS)0x00010003L) +#define NDIS_STATUS_CALL_ACTIVE ((NDIS_STATUS)0x00010007L) + +#define NDIS_STATUS_FAILURE ((NDIS_STATUS)STATUS_UNSUCCESSFUL) +#define NDIS_STATUS_RESOURCES ((NDIS_STATUS)STATUS_INSUFFICIENT_RESOURCES) +#define NDIS_STATUS_CLOSING ((NDIS_STATUS)0xC0010002L) +#define NDIS_STATUS_BAD_VERSION ((NDIS_STATUS)0xC0010004L) +#define NDIS_STATUS_BAD_CHARACTERISTICS ((NDIS_STATUS)0xC0010005L) +#define NDIS_STATUS_ADAPTER_NOT_FOUND ((NDIS_STATUS)0xC0010006L) +#define NDIS_STATUS_OPEN_FAILED ((NDIS_STATUS)0xC0010007L) +#define NDIS_STATUS_DEVICE_FAILED ((NDIS_STATUS)0xC0010008L) +#define NDIS_STATUS_MULTICAST_FULL ((NDIS_STATUS)0xC0010009L) +#define NDIS_STATUS_MULTICAST_EXISTS ((NDIS_STATUS)0xC001000AL) +#define NDIS_STATUS_MULTICAST_NOT_FOUND ((NDIS_STATUS)0xC001000BL) +#define NDIS_STATUS_REQUEST_ABORTED ((NDIS_STATUS)0xC001000CL) +#define NDIS_STATUS_RESET_IN_PROGRESS ((NDIS_STATUS)0xC001000DL) +#define NDIS_STATUS_CLOSING_INDICATING ((NDIS_STATUS)0xC001000EL) +#define NDIS_STATUS_NOT_SUPPORTED ((NDIS_STATUS)STATUS_NOT_SUPPORTED) +#define NDIS_STATUS_INVALID_PACKET ((NDIS_STATUS)0xC001000FL) +#define NDIS_STATUS_OPEN_LIST_FULL ((NDIS_STATUS)0xC0010010L) +#define NDIS_STATUS_ADAPTER_NOT_READY ((NDIS_STATUS)0xC0010011L) +#define NDIS_STATUS_ADAPTER_NOT_OPEN ((NDIS_STATUS)0xC0010012L) +#define NDIS_STATUS_NOT_INDICATING ((NDIS_STATUS)0xC0010013L) +#define NDIS_STATUS_INVALID_LENGTH ((NDIS_STATUS)0xC0010014L) +#define NDIS_STATUS_INVALID_DATA ((NDIS_STATUS)0xC0010015L) +#define NDIS_STATUS_BUFFER_TOO_SHORT ((NDIS_STATUS)0xC0010016L) +#define NDIS_STATUS_INVALID_OID ((NDIS_STATUS)0xC0010017L) +#define NDIS_STATUS_ADAPTER_REMOVED ((NDIS_STATUS)0xC0010018L) +#define NDIS_STATUS_UNSUPPORTED_MEDIA ((NDIS_STATUS)0xC0010019L) +#define NDIS_STATUS_GROUP_ADDRESS_IN_USE ((NDIS_STATUS)0xC001001AL) +#define NDIS_STATUS_FILE_NOT_FOUND ((NDIS_STATUS)0xC001001BL) +#define NDIS_STATUS_ERROR_READING_FILE ((NDIS_STATUS)0xC001001CL) +#define NDIS_STATUS_ALREADY_MAPPED ((NDIS_STATUS)0xC001001DL) +#define NDIS_STATUS_RESOURCE_CONFLICT ((NDIS_STATUS)0xC001001EL) +#define NDIS_STATUS_NO_CABLE ((NDIS_STATUS)0xC001001FL) + +#define NDIS_STATUS_INVALID_SAP ((NDIS_STATUS)0xC0010020L) +#define NDIS_STATUS_SAP_IN_USE ((NDIS_STATUS)0xC0010021L) +#define NDIS_STATUS_INVALID_ADDRESS ((NDIS_STATUS)0xC0010022L) +#define NDIS_STATUS_VC_NOT_ACTIVATED ((NDIS_STATUS)0xC0010023L) +#define NDIS_STATUS_DEST_OUT_OF_ORDER ((NDIS_STATUS)0xC0010024L) // cause 27 +#define NDIS_STATUS_VC_NOT_AVAILABLE ((NDIS_STATUS)0xC0010025L) // cause 35,45 +#define NDIS_STATUS_CELLRATE_NOT_AVAILABLE ((NDIS_STATUS)0xC0010026L) // cause 37 +#define NDIS_STATUS_INCOMPATABLE_QOS ((NDIS_STATUS)0xC0010027L) // cause 49 +#define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((NDIS_STATUS)0xC0010028L) // cause 93 +#define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((NDIS_STATUS)0xC0010029L) // cause 3 +#endif /* #ifndef PLATFORM_WINDOWS */ + +#if 0 +#define MPT_NOOP 0 +#define MPT_READ_MAC_1BYTE 1 +#define MPT_READ_MAC_2BYTE 2 +#define MPT_READ_MAC_4BYTE 3 +#define MPT_WRITE_MAC_1BYTE 4 +#define MPT_WRITE_MAC_2BYTE 5 +#define MPT_WRITE_MAC_4BYTE 6 +#define MPT_READ_BB_CCK 7 +#define MPT_WRITE_BB_CCK 8 +#define MPT_READ_BB_OFDM 9 +#define MPT_WRITE_BB_OFDM 10 +#define MPT_READ_RF 11 +#define MPT_WRITE_RF 12 +#define MPT_READ_EEPROM_1BYTE 13 +#define MPT_WRITE_EEPROM_1BYTE 14 +#define MPT_READ_EEPROM_2BYTE 15 +#define MPT_WRITE_EEPROM_2BYTE 16 +#define MPT_SET_CSTHRESHOLD 21 +#define MPT_SET_INITGAIN 22 +#define MPT_SWITCH_BAND 23 +#define MPT_SWITCH_CHANNEL 24 +#define MPT_SET_DATARATE 25 +#define MPT_SWITCH_ANTENNA 26 +#define MPT_SET_TX_POWER 27 +#define MPT_SET_CONT_TX 28 +#define MPT_SET_SINGLE_CARRIER 29 +#define MPT_SET_CARRIER_SUPPRESSION 30 +#define MPT_GET_RATE_TABLE 31 +#define MPT_READ_TSSI 32 +#define MPT_GET_THERMAL_METER 33 +#endif + +typedef enum _ANTENNA_PATH{ + ANTENNA_NONE = 0x00, + ANTENNA_D , + ANTENNA_C , + ANTENNA_CD , + ANTENNA_B , + ANTENNA_BD , + ANTENNA_BC , + ANTENNA_BCD , + ANTENNA_A , + ANTENNA_AD , + ANTENNA_AC , + ANTENNA_ACD , + ANTENNA_AB , + ANTENNA_ABD , + ANTENNA_ABC , + ANTENNA_ABCD +} ANTENNA_PATH; + + +#define MAX_MP_XMITBUF_SZ 2048 +#define NR_MP_XMITFRAME 8 + +struct mp_xmit_frame +{ + _list list; + + struct pkt_attrib attrib; + + _pkt *pkt; + + int frame_tag; + + _adapter *padapter; + +#ifdef CONFIG_USB_HCI + + //insert urb, irp, and irpcnt info below... + //max frag_cnt = 8 + + u8 *mem_addr; + u32 sz[8]; + +#if defined(PLATFORM_OS_XP) || defined(PLATFORM_LINUX) + PURB pxmit_urb[8]; +#endif + +#ifdef PLATFORM_OS_XP + PIRP pxmit_irp[8]; +#endif + + u8 bpending[8]; + s32 ac_tag[8]; + s32 last[8]; + uint irpcnt; + uint fragcnt; +#endif /* CONFIG_USB_HCI */ + + uint mem[(MAX_MP_XMITBUF_SZ >> 2)]; +}; + +struct mp_wiparam +{ + u32 bcompleted; + u32 act_type; + u32 io_offset; + u32 io_value; +}; + +typedef void(*wi_act_func)(void* padapter); + +#ifdef PLATFORM_WINDOWS +struct mp_wi_cntx +{ + u8 bmpdrv_unload; + + // Work Item + NDIS_WORK_ITEM mp_wi; + NDIS_EVENT mp_wi_evt; + _lock mp_wi_lock; + u8 bmp_wi_progress; + wi_act_func curractfunc; + // Variable needed in each implementation of CurrActFunc. + struct mp_wiparam param; +}; +#endif + +struct mp_tx +{ + u8 stop; + u32 count, sended; + u8 payload; + struct pkt_attrib attrib; + struct tx_desc desc; + u8 *pallocated_buf; + u8 *buf; + u32 buf_size, write_size; + //_thread_hdl_ PktTxThread; + struct task_struct MpXmitThread; +}; + +#define MP_MAX_LINES 1000 +#define MP_MAX_LINES_BYTES 256 + + +typedef void (*MPT_WORK_ITEM_HANDLER)(IN void *Adapter); +typedef struct _MPT_CONTEXT +{ + // Indicate if we have started Mass Production Test. + BOOLEAN bMassProdTest; + + // Indicate if the driver is unloading or unloaded. + BOOLEAN bMptDrvUnload; + + _sema MPh2c_Sema; + _timer MPh2c_timeout_timer; +// Event used to sync H2c for BT control + + BOOLEAN MptH2cRspEvent; + BOOLEAN MptBtC2hEvent; + BOOLEAN bMPh2c_timeout; + + /* 8190 PCI does not support NDIS_WORK_ITEM. */ + // Work Item for Mass Production Test. + //NDIS_WORK_ITEM MptWorkItem; +// RT_WORK_ITEM MptWorkItem; + // Event used to sync the case unloading driver and MptWorkItem is still in progress. +// NDIS_EVENT MptWorkItemEvent; + // To protect the following variables. +// NDIS_SPIN_LOCK MptWorkItemSpinLock; + // Indicate a MptWorkItem is scheduled and not yet finished. + BOOLEAN bMptWorkItemInProgress; + // An instance which implements function and context of MptWorkItem. + MPT_WORK_ITEM_HANDLER CurrMptAct; + + // 1=Start, 0=Stop from UI. + u32 MptTestStart; + // _TEST_MODE, defined in MPT_Req2.h + u32 MptTestItem; + // Variable needed in each implementation of CurrMptAct. + u32 MptActType; // Type of action performed in CurrMptAct. + // The Offset of IO operation is depend of MptActType. + u32 MptIoOffset; + // The Value of IO operation is depend of MptActType. + u32 MptIoValue; + // The RfPath of IO operation is depend of MptActType. + u32 MptRfPath; + + WIRELESS_MODE MptWirelessModeToSw; // Wireless mode to switch. + u8 MptChannelToSw; // Channel to switch. + u8 MptInitGainToSet; // Initial gain to set. + //u32 bMptAntennaA; // TRUE if we want to use antenna A. + u32 MptBandWidth; // bandwidth to switch. + u32 MptRateIndex; // rate index. + // Register value kept for Single Carrier Tx test. + u8 btMpCckTxPower; + // Register value kept for Single Carrier Tx test. + u8 btMpOfdmTxPower; + // For MP Tx Power index + u8 TxPwrLevel[2]; // rf-A, rf-B + + // Content of RCR Regsiter for Mass Production Test. + u32 MptRCR; + // TRUE if we only receive packets with specific pattern. + BOOLEAN bMptFilterPattern; + // Rx OK count, statistics used in Mass Production Test. + u32 MptRxOkCnt; + // Rx CRC32 error count, statistics used in Mass Production Test. + u32 MptRxCrcErrCnt; + + BOOLEAN bCckContTx; // TRUE if we are in CCK Continuous Tx test. + BOOLEAN bOfdmContTx; // TRUE if we are in OFDM Continuous Tx test. + BOOLEAN bStartContTx; // TRUE if we have start Continuous Tx test. + // TRUE if we are in Single Carrier Tx test. + BOOLEAN bSingleCarrier; + // TRUE if we are in Carrier Suppression Tx Test. + BOOLEAN bCarrierSuppression; + //TRUE if we are in Single Tone Tx test. + BOOLEAN bSingleTone; + + // ACK counter asked by K.Y.. + BOOLEAN bMptEnableAckCounter; + u32 MptAckCounter; + + // SD3 Willis For 8192S to save 1T/2T RF table for ACUT Only fro ACUT delete later ~~~! + //s8 BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + //s8 BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; + //s32 RfReadLine[2]; + + u8 APK_bound[2]; //for APK path A/path B + BOOLEAN bMptIndexEven; + + u8 backup0xc50; + u8 backup0xc58; + u8 backup0xc30; + u8 backup0x52_RF_A; + u8 backup0x52_RF_B; + + u8 h2cReqNum; + u8 c2hBuf[20]; + + u8 btInBuf[100]; + u32 mptOutLen; + u8 mptOutBuf[100]; + +}MPT_CONTEXT, *PMPT_CONTEXT; +//#endif + +//#define RTPRIV_IOCTL_MP ( SIOCIWFIRSTPRIV + 0x17) +enum { + WRITE_REG = 1, + READ_REG, + WRITE_RF, + READ_RF, + MP_START, + MP_STOP, + MP_RATE, + MP_CHANNEL, + MP_BANDWIDTH, + MP_TXPOWER, + MP_ANT_TX, + MP_ANT_RX, + MP_CTX, + MP_QUERY, + MP_ARX, + MP_PSD, + MP_PWRTRK, + MP_THER, + MP_IOCTL, + EFUSE_GET, + EFUSE_SET, + CONFIG_GET, + CONFIG_SET, + MP_RESET_STATS, + MP_DUMP, + MP_PHYPARA, + MP_SetRFPathSwh, + MP_QueryDrvStats, + MP_SetBT, + TEST_CFG, + MP_NULL, + MP_GET_TXPOWER_INX, + MP_SET_PREAMBLE, + MP_DISABLE_BT_COEXIST, + MP_PwrCtlDM, + MP_IQK, + MP_LCK, + MP_DRV_ABILITY +}; + +struct mp_priv +{ + _adapter *papdater; + + //Testing Flag + u32 mode;//0 for normal type packet, 1 for loopback packet (16bytes TXCMD) + + u32 prev_fw_state; + + //OID cmd handler + struct mp_wiparam workparam; +// u8 act_in_progress; + + //Tx Section + u8 TID; + u32 tx_pktcount; + struct mp_tx tx; + + //Rx Section + u8 rx_pkt_by_mac; + u32 rx_pktcount; + u32 rx_crcerrpktcount; + u32 rx_macpktcount; + u32 rx_pktloss; + + struct recv_stat rxstat; + + //RF/BB relative + u8 channel; + u8 bandwidth; + u8 prime_channel_offset; + u8 txpoweridx; + u8 txpoweridx_b; + u8 rateidx; + u32 preamble; +// u8 modem; + u32 CrystalCap; +// u32 curr_crystalcap; + + u16 antenna_tx; + u16 antenna_rx; +// u8 curr_rfpath; + + u8 check_mp_pkt; + + u8 bSetTxPower; + u8 bCCKTxPowerAdjust; + u8 bFAStatistics; +// uint ForcedDataRate; + u8 mp_dm; + struct wlan_network mp_network; + NDIS_802_11_MAC_ADDRESS network_macaddr; + +#ifdef PLATFORM_WINDOWS + u32 rx_testcnt; + u32 rx_testcnt1; + u32 rx_testcnt2; + u32 tx_testcnt; + u32 tx_testcnt1; + + struct mp_wi_cntx wi_cntx; + + u8 h2c_result; + u8 h2c_seqnum; + u16 h2c_cmdcode; + u8 h2c_resp_parambuf[512]; + _lock h2c_lock; + _lock wkitm_lock; + u32 h2c_cmdcnt; + NDIS_EVENT h2c_cmd_evt; + NDIS_EVENT c2h_set; + NDIS_EVENT h2c_clr; + NDIS_EVENT cpwm_int; + + NDIS_EVENT scsir_full_evt; + NDIS_EVENT scsiw_empty_evt; +#endif + + u8 *pallocated_mp_xmitframe_buf; + u8 *pmp_xmtframe_buf; + _queue free_mp_xmitqueue; + u32 free_mp_xmitframe_cnt; + + MPT_CONTEXT MptCtx; +}; + +typedef struct _IOCMD_STRUCT_ { + u8 cmdclass; + u16 value; + u8 index; +}IOCMD_STRUCT; + +struct rf_reg_param { + u32 path; + u32 offset; + u32 value; +}; + +struct bb_reg_param { + u32 offset; + u32 value; +}; +//======================================================================= + +#define LOWER _TRUE +#define RAISE _FALSE + +/* Hardware Registers */ +#if 0 +#if 0 +#define IOCMD_CTRL_REG 0x102502C0 +#define IOCMD_DATA_REG 0x102502C4 +#else +#define IOCMD_CTRL_REG 0x10250370 +#define IOCMD_DATA_REG 0x10250374 +#endif + +#define IOCMD_GET_THERMAL_METER 0xFD000028 + +#define IOCMD_CLASS_BB_RF 0xF0 +#define IOCMD_BB_READ_IDX 0x00 +#define IOCMD_BB_WRITE_IDX 0x01 +#define IOCMD_RF_READ_IDX 0x02 +#define IOCMD_RF_WRIT_IDX 0x03 +#endif +#define BB_REG_BASE_ADDR 0x800 + +/* MP variables */ +#if 0 +#define _2MAC_MODE_ 0 +#define _LOOPBOOK_MODE_ 1 +#endif +typedef enum _MP_MODE_ { + MP_OFF, + MP_ON, + MP_ERR, + MP_CONTINUOUS_TX, + MP_SINGLE_CARRIER_TX, + MP_CARRIER_SUPPRISSION_TX, + MP_SINGLE_TONE_TX, + MP_PACKET_TX, + MP_PACKET_RX +} MP_MODE; + + +#define MAX_RF_PATH_NUMS MAX_RF_PATH + + +extern u8 mpdatarate[NumRates]; + +/* MP set force data rate base on the definition. */ +typedef enum _MPT_RATE_INDEX +{ + /* CCK rate. */ + MPT_RATE_1M, /* 0 */ + MPT_RATE_2M, + MPT_RATE_55M, + MPT_RATE_11M, /* 3 */ + + /* OFDM rate. */ + MPT_RATE_6M, /* 4 */ + MPT_RATE_9M, + MPT_RATE_12M, + MPT_RATE_18M, + MPT_RATE_24M, + MPT_RATE_36M, + MPT_RATE_48M, + MPT_RATE_54M, /* 11 */ + + /* HT rate. */ + MPT_RATE_MCS0, /* 12 */ + MPT_RATE_MCS1, + MPT_RATE_MCS2, + MPT_RATE_MCS3, + MPT_RATE_MCS4, + MPT_RATE_MCS5, + MPT_RATE_MCS6, + MPT_RATE_MCS7, /* 19 */ + MPT_RATE_MCS8, + MPT_RATE_MCS9, + MPT_RATE_MCS10, + MPT_RATE_MCS11, + MPT_RATE_MCS12, + MPT_RATE_MCS13, + MPT_RATE_MCS14, + MPT_RATE_MCS15, /* 27 */ + MPT_RATE_LAST +}MPT_RATE_E, *PMPT_RATE_E; + +#define MAX_TX_PWR_INDEX_N_MODE 64 // 0x3F + +typedef enum _POWER_MODE_ { + POWER_LOW = 0, + POWER_NORMAL +}POWER_MODE; + + +#define RX_PKT_BROADCAST 1 +#define RX_PKT_DEST_ADDR 2 +#define RX_PKT_PHY_MATCH 3 + +#if 0 +#define RPTMaxCount 0x000FFFFF; + +// parameter 1 : BitMask +// bit 0 : OFDM PPDU +// bit 1 : OFDM False Alarm +// bit 2 : OFDM MPDU OK +// bit 3 : OFDM MPDU Fail +// bit 4 : CCK PPDU +// bit 5 : CCK False Alarm +// bit 6 : CCK MPDU ok +// bit 7 : CCK MPDU fail +// bit 8 : HT PPDU counter +// bit 9 : HT false alarm +// bit 10 : HT MPDU total +// bit 11 : HT MPDU OK +// bit 12 : HT MPDU fail +// bit 15 : RX full drop +typedef enum _RXPHY_BITMASK_ +{ + OFDM_PPDU_BIT = 0, + OFDM_FALSE_BIT, + OFDM_MPDU_OK_BIT, + OFDM_MPDU_FAIL_BIT, + CCK_PPDU_BIT, + CCK_FALSE_BIT, + CCK_MPDU_OK_BIT, + CCK_MPDU_FAIL_BIT, + HT_PPDU_BIT, + HT_FALSE_BIT, + HT_MPDU_BIT, + HT_MPDU_OK_BIT, + HT_MPDU_FAIL_BIT, +} RXPHY_BITMASK; +#endif + +typedef enum _ENCRY_CTRL_STATE_ { + HW_CONTROL, //hw encryption& decryption + SW_CONTROL, //sw encryption& decryption + HW_ENCRY_SW_DECRY, //hw encryption & sw decryption + SW_ENCRY_HW_DECRY //sw encryption & hw decryption +}ENCRY_CTRL_STATE; + +typedef enum _PREAMBLE { + Long_Preamble = 0x01, + Short_Preamble , + Long_GI , + Short_GI +} PREAMBLE; + + + +//======================================================================= +//extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv); +//extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe); + +extern s32 init_mp_priv(_adapter * padapter); +extern void free_mp_priv(struct mp_priv *pmp_priv); +extern s32 MPT_InitializeAdapter(_adapter * padapter, u8 Channel); +extern void MPT_DeInitAdapter(_adapter * padapter); +extern s32 mp_start_test(_adapter * padapter); +extern void mp_stop_test(_adapter * padapter); + +//======================================================================= +//extern void IQCalibrateBcut(_adapter * pAdapter); + +//extern u32 bb_reg_read(_adapter * Adapter, u16 offset); +//extern u8 bb_reg_write(_adapter * Adapter, u16 offset, u32 value); +//extern u32 rf_reg_read(_adapter * Adapter, u8 path, u8 offset); +//extern u8 rf_reg_write(_adapter * Adapter, u8 path, u8 offset, u32 value); + +//extern u32 get_bb_reg(_adapter * Adapter, u16 offset, u32 bitmask); +//extern u8 set_bb_reg(_adapter * Adapter, u16 offset, u32 bitmask, u32 value); +//extern u32 get_rf_reg(_adapter * Adapter, u8 path, u8 offset, u32 bitmask); +//extern u8 set_rf_reg(_adapter * Adapter, u8 path, u8 offset, u32 bitmask, u32 value); + +extern u32 _read_rfreg(_adapter * padapter, u8 rfpath, u32 addr, u32 bitmask); +extern void _write_rfreg(_adapter * padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val); + +extern u32 read_macreg(_adapter *padapter, u32 addr, u32 sz); +extern void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz); +extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask); +extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val); +extern u32 read_rfreg(_adapter * padapter, u8 rfpath, u32 addr); +extern void write_rfreg(_adapter * padapter, u8 rfpath, u32 addr, u32 val); + +extern void SetChannel(_adapter * pAdapter); +extern void SetBandwidth(_adapter * pAdapter); +extern void SetTxPower(_adapter * pAdapter); +extern void SetAntennaPathPower(_adapter * pAdapter); +//extern void SetTxAGCOffset(_adapter * pAdapter, u32 ulTxAGCOffset); +extern void SetDataRate(_adapter * pAdapter); + +extern void SetAntenna(_adapter * pAdapter); + +//extern void SetCrystalCap(_adapter * pAdapter); + +extern s32 SetThermalMeter(_adapter * pAdapter, u8 target_ther); +extern void GetThermalMeter(_adapter * pAdapter, u8 *value); + +extern void SetContinuousTx(_adapter * pAdapter, u8 bStart); +extern void SetSingleCarrierTx(_adapter * pAdapter, u8 bStart); +extern void SetSingleToneTx(_adapter * pAdapter, u8 bStart); +extern void SetCarrierSuppressionTx(_adapter * pAdapter, u8 bStart); +extern void PhySetTxPowerLevel(_adapter * pAdapter); + +extern void fill_txdesc_for_mp(_adapter * padapter, struct tx_desc *ptxdesc); +extern void SetPacketTx(_adapter * padapter); +extern void SetPacketRx(_adapter * pAdapter, u8 bStartRx); + +extern void ResetPhyRxPktCount(_adapter * pAdapter); +extern u32 GetPhyRxPktReceived(_adapter * pAdapter); +extern u32 GetPhyRxPktCRC32Error(_adapter * pAdapter); + +extern s32 SetPowerTracking(_adapter * padapter, u8 enable); +extern void GetPowerTracking(_adapter * padapter, u8 *enable); + +extern u32 mp_query_psd(_adapter * pAdapter, u8 *data); + + +extern void Hal_SetAntenna(_adapter * pAdapter); +extern void Hal_SetBandwidth(_adapter * pAdapter); + +extern void Hal_SetTxPower(_adapter * pAdapter); +extern void Hal_SetCarrierSuppressionTx(_adapter * pAdapter, u8 bStart); +extern void Hal_SetSingleToneTx ( _adapter * pAdapter , u8 bStart ); +extern void Hal_SetSingleCarrierTx (_adapter * pAdapter, u8 bStart); +extern void Hal_SetContinuousTx (_adapter * pAdapter, u8 bStart); +extern void Hal_SetBandwidth(_adapter * pAdapter); + +extern void Hal_SetDataRate(_adapter * pAdapter); +extern void Hal_SetChannel(_adapter * pAdapter); +extern void Hal_SetAntennaPathPower(_adapter * pAdapter); +extern s32 Hal_SetThermalMeter(_adapter * pAdapter, u8 target_ther); +extern s32 Hal_SetPowerTracking(_adapter * padapter, u8 enable); +extern void Hal_GetPowerTracking(_adapter * padapter, u8 * enable); +extern void Hal_GetThermalMeter(_adapter * pAdapter, u8 *value); +extern void Hal_mpt_SwitchRfSetting(_adapter * pAdapter); +extern void Hal_MPT_CCKTxPowerAdjust(_adapter * Adapter); +extern void Hal_MPT_CCKTxPowerAdjustbyIndex(_adapter * pAdapter, BOOLEAN beven); +extern void Hal_SetCCKTxPower(_adapter * pAdapter, u8 * TxPower); +extern void Hal_SetOFDMTxPower(_adapter * pAdapter, u8 * TxPower); +extern void Hal_TriggerRFThermalMeter(_adapter * pAdapter); +extern u8 Hal_ReadRFThermalMeter(_adapter * pAdapter); +extern void Hal_SetCCKContinuousTx(_adapter * pAdapter, u8 bStart); +extern void Hal_SetOFDMContinuousTx(_adapter * pAdapter, u8 bStart); +extern void Hal_ProSetCrystalCap (_adapter * pAdapter , u32 CrystalCapVal); +extern void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv); +extern void MP_PHY_SetRFPathSwitch(_adapter * pAdapter ,BOOLEAN bMain); +extern u32 mpt_ProQueryCalTxPower(_adapter * pAdapter, u8 RfPath); +extern void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart); + +#endif //_RTW_MP_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_p2p.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_p2p.h new file mode 100644 index 0000000..610a75a --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_p2p.h @@ -0,0 +1,58 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_P2P_H_ +#define _RTW_P2P_H_ + +#define P2P_WILDCARD_SSID "DIRECT-" +#define P2P_WILDCARD_SSID_LEN 7 + +#define P2P_SEND_ACTION_AFTER_PROBE_RSP 1 + +#define RTW_P2P_SEND_ACTION_SUCCESS 0 +#define RTW_P2P_SEND_ACTION_FAILED 2 + +static inline bool rtw_p2p_chk_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) +{ + return wdinfo->p2p_state == state; +} +static inline bool rtw_p2p_chk_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role) +{ + return wdinfo->role == role; +} + +extern void rtw_p2p_remain_on_channel(_adapter *padapter, u8 channel, u8 wait_time); +extern void rtw_p2p_cancel_remain_on_channel(_adapter *padapter); +extern void rtw_p2p_special_scan_param(_adapter *padapter, u8 channel, u8 *mac); +extern void rtw_p2p_set_p2p_role(_adapter *padapter, u32 role); +extern void rtw_p2p_set_p2p_state(_adapter *padapter, u32 state); +extern int rtw_p2p_send_mgnt(_adapter *padapter, u8 *data, u16 len, u16 flags); +extern void rtw_p2p_indicate_mgnt(_adapter *padapter, u8 *data, u16 len, u8 channel); +extern void rtw_indicate_sta_assoc(_adapter *padapter, u8 *addr, u8 *buf, u16 len); +extern void rtw_p2p_indicate_sta_disassoc(_adapter *padapter, u8 *addr); +extern void rtw_p2p_indicate_send_action_done(_adapter *padapter, u16 status); + +extern int rtw_p2p_init_mlme_ext(_adapter *padapter); +extern void rtw_p2p_deinit_mlme_ext(_adapter *padapter); +extern int rtw_init_p2p_wdinfo(_adapter *padapter); +extern void rtw_deinit_p2p_wdinfo(_adapter *padapter); +extern void rtw_p2p_pre_tx_scan_cmd_callback(_adapter *padapter); + +#endif //_RTW_P2P_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_promisc.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_promisc.h new file mode 100644 index 0000000..918d840 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_promisc.h @@ -0,0 +1,38 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef _RTW_PROMISC_H_ +#define _RTW_PROMISC_H_ +#include +#ifdef CONFIG_PROMISC +void promisc_deinit(_adapter *padapter); +//void promisc_set_enable(_adapter *padapter, u8 enabled, u8 len_used); +int promisc_recv_func(_adapter *padapter, union recv_frame *rframe); +#endif +int promisc_set(rtw_rcr_level_t enabled, void (*callback)(unsigned char*, unsigned int, void*), unsigned char len_used); +unsigned char is_promisc_enabled(void); +int promisc_get_fixed_channel(void * fixed_bssid, u8 * ssid, int *ssid_length); +void promisc_issue_probereq(void); +void promisc_issue_probersp(unsigned char *da); +void promisc_stop_tx_beacn(void); +void promisc_resume_tx_beacn(void); +void promisc_get_ap_info(rtw_result_t (*func)(char *ssid, u8 ssid_len, s16 rssi, char channel, char security)); +#endif //_RTW_PROMISC_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_psk.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_psk.h new file mode 100644 index 0000000..75c275d --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_psk.h @@ -0,0 +1,341 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef _RTW_PSK_H_ +#define _RTW_PSK_H_ + +#define GMK_LEN 32 +#define GTK_LEN 32 +#define PMK_LEN 32 +#define KEY_NONCE_LEN 32 +#define NumGroupKey 4 +#define KEY_RC_LEN 8 +#define KEY_IV_LEN 16 +#define KEY_RSC_LEN 8 +#define KEY_ID_LEN 8 +#define KEY_MIC_LEN 16 +#define KEY_MATERIAL_LEN 2 +#define PTK_LEN_EAPOLMIC 16 +#define PTK_LEN_EAPOLENC 16 +#define PTK_LEN_TKIP 64 +#define PTK_LEN_CCMP 48 +#define LIB1X_ETHER_EAPOL_TYPE 0x888E + +#define DescTypePos 0 +#define KeyInfoPos 1 +#define KeyLenPos 3 +#define ReplayCounterPos 5 +#define KeyNoncePos 13 +#define KeyIVPos 45 +#define KeyRSCPos 61 +#define KeyIDPos 69 +#define KeyMICPos 77 +#define KeyDataLenPos 93 +#define KeyDataPos 95 +#define LIB1X_EAPOL_VER 1 //0000 0001B +#define LIB1X_EAPOL_EAPPKT 0 //0000 0000B +#define LIB1X_EAPOL_START 1 //0000 0001B +#define LIB1X_EAPOL_LOGOFF 2 //0000 0010B +#define LIB1X_EAPOL_KEY 3 //0000 0011B +#define LIB1X_EAPOL_ENCASFALERT 4 //0000 0100B + + +#define A_SHA_DIGEST_LEN 20 +#define ETHER_HDRLEN 14 +#define LIB1X_EAPOL_HDRLEN 4 +#define INFO_ELEMENT_SIZE 128 +#define MAX_EAPOLMSG_LEN 512 +#define MAX_EAPOLKEYMSG_LEN (MAX_EAPOLMSG_LEN-(ETHER_HDRLEN+LIB1X_EAPOL_HDRLEN)) +#define EAPOLMSG_HDRLEN 95 //EAPOL-key payload length without KeyData +#define WPA_ELEMENT_ID 0xDD +#define WPA2_ELEMENT_ID 0x30 + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#define ETHER_ADDRLEN 6 +#define PMK_EXPANSION_CONST "Pairwise key expansion" +#define PMK_EXPANSION_CONST_SIZE 22 +#define GMK_EXPANSION_CONST "Group key expansion" +#define GMK_EXPANSION_CONST_SIZE 19 +#define RANDOM_EXPANSION_CONST "Init Counter" +#define RANDOM_EXPANSION_CONST_SIZE 12 + +#define WLAN_REASON_MIC_FAILURE 14 +#define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT 15 + +/* + 2008-12-16, For Corega CG-WLCB54GL 54Mbps NIC interoperability issue. + The behavior of this NIC when it connect to the other AP with WPA/TKIP is: + AP <----------------------> STA + .................... + ------------> Assoc Rsp (ok) + ------------> EAPOL-key (4-way msg 1) + <------------ unknown TKIP encryption data + ------------> EAPOL-key (4-way msg 1) + <------------ unknown TKIP encryption data + ..................... + <------------ disassoc (code=8, STA is leaving) when the 5 seconds timer timeout counting from Assoc_Rsp is got. + .................... + ------------> Assoc Rsp (ok) + <-----------> EAPOL-key (4-way handshake success) + + If MAX_RESEND_NUM=3, our AP will send disassoc (code=15, 4-way timeout) to STA before STA sending disassoc to AP. + And this NIC will always can not connect to our AP. + set MAX_RESEND_NUM=5 can fix this issue. + */ +//#define MAX_RESEND_NUM 3 +#define MAX_RESEND_NUM 5 +#define RESEND_TIME 1000 + +#define GK_REKEY_TIME 3600000 //Set rekey period to 1 hour + +typedef enum { + desc_type_RSN = 2, + desc_type_WPA = 254 +} DescTypeRSN; + +typedef enum { + type_Group = 0, + type_Pairwise = 1 +} KeyType; + +typedef enum { + key_desc_ver1 = 1, + key_desc_ver2 = 2 +} KeyDescVer; + +enum { + PSK_WPA = 1, + PSK_WPA2 = 2 +}; + +enum { + PSK_STATE_IDLE, + PSK_STATE_PTKSTART, + PSK_STATE_PTKINITNEGOTIATING, + PSK_STATE_PTKINITDONE, +}; + +enum { + PSK_GSTATE_REKEYNEGOTIATING, + PSK_GSTATE_REKEYESTABLISHED, + PSK_GSTATE_KEYERROR, +}; + +typedef struct _OCTET_STRING { + unsigned char *Octet; + int Length; +} OCTET_STRING; + +typedef union _LARGE_INTEGER { + unsigned char charData[8]; + struct { + unsigned long HighPart; + unsigned long LowPart; + } field; +} LARGE_INTEGER, *PLARGE_INTEGER; + +typedef union _OCTET16_INTEGER { + unsigned char charData[16]; + struct { + LARGE_INTEGER HighPart; + LARGE_INTEGER LowPart; + } field; +} OCTET16_INTEGER; + +typedef union _OCTET32_INTEGER { + unsigned char charData[32]; + struct { + OCTET16_INTEGER HighPart; + OCTET16_INTEGER LowPart; + } field; +} OCTET32_INTEGER; + +// group key info +typedef struct _wpa_global_info { + OCTET32_INTEGER Counter; +//Save PSK to global array +// unsigned char PSK[A_SHA_DIGEST_LEN * 2]; + int GTKAuthenticator; + int GKeyDoneStations; + int GInitAKeys; + int GUpdateStationKeys; + int GkeyReady; + OCTET_STRING AuthInfoElement; + unsigned char AuthInfoBuf[INFO_ELEMENT_SIZE]; + unsigned char MulticastCipher; + OCTET_STRING GNonce; + unsigned char GNonceBuf[KEY_NONCE_LEN]; + unsigned char GTK[NumGroupKey][GTK_LEN]; + unsigned char GMK[GMK_LEN]; + int GN; + int GM; + int GTKRekey; +#ifdef CONFIG_GK_REKEY + struct timer_list GKRekeyTimer; +#endif +} WPA_GLOBAL_INFO; + +// wpa sta info +typedef struct _wpa_sta_info { + int state; + int gstate; + int RSNEnabled; // bit0-WPA, bit1-WPA2 + int PInitAKeys; + unsigned char UnicastCipher; + LARGE_INTEGER CurrentReplayCounter; + LARGE_INTEGER ReplayCounterStarted; // david+1-12-2007 + OCTET_STRING ANonce; + OCTET_STRING SNonce; + unsigned char AnonceBuf[KEY_NONCE_LEN]; + unsigned char SnonceBuf[KEY_NONCE_LEN]; + unsigned char PMK[PMK_LEN]; + unsigned char PTK[PTK_LEN_TKIP]; + OCTET_STRING EAPOLMsgRecvd; + OCTET_STRING EAPOLMsgSend; + OCTET_STRING EapolKeyMsgRecvd; + OCTET_STRING EapolKeyMsgSend; + + unsigned char eapSendBuf[MAX_EAPOLMSG_LEN]; +// unsigned char eapRecvdBuf[MAX_EAPOLMSG_LEN]; + struct timer_list resendTimer; + int resendCnt; + int clientHndshkProcessing; + int clientHndshkDone; + int clientGkeyUpdate; + LARGE_INTEGER clientMICReportReplayCounter; +} WPA_STA_INFO; + +typedef struct _LIB1X_EAPOL_KEY +{ + unsigned char key_desc_ver; + unsigned char key_info[2]; + unsigned char key_len[2]; + unsigned char key_replay_counter[KEY_RC_LEN]; + unsigned char key_nounce[KEY_NONCE_LEN]; + unsigned char key_iv[KEY_IV_LEN]; + unsigned char key_rsc[KEY_RSC_LEN]; + unsigned char key_id[KEY_ID_LEN]; + unsigned char key_mic[KEY_MIC_LEN]; + unsigned char key_data_len[KEY_MATERIAL_LEN]; + unsigned char *key_data; +} lib1x_eapol_key; + +struct lib1x_eapol +{ + unsigned char protocol_version; + unsigned char packet_type; // This makes it odd in number ! + unsigned short packet_body_length; +}; + +struct wlan_ethhdr_t +{ + unsigned char daddr[WLAN_ETHADDR_LEN]; + unsigned char saddr[WLAN_ETHADDR_LEN]; + unsigned short type; +}; + +typedef enum{ + DOT11_PortStatus_Unauthorized, + DOT11_PortStatus_Authorized, + DOT11_PortStatus_Guest +}DOT11_PORT_STATUS; + +#ifdef CONFIG_MOVE_PSK_TO_ROM +static __inline__ OCTET_STRING SubStr(OCTET_STRING f, unsigned short s, unsigned short l) +{ + OCTET_STRING res; + + res.Length = l; + res.Octet = f.Octet + s; + + return res; +} +#endif + +#define SetSubStr(f,a,l) memcpy(f.Octet+l,a.Octet,a.Length) +#define GetKeyInfo0(f, mask) ((f.Octet[KeyInfoPos + 1] & mask) ? 1 : 0) +#define SetKeyInfo0(f,mask,b) (f.Octet[KeyInfoPos + 1] = (f.Octet[KeyInfoPos + 1] & ~mask) | ( b?mask:0x0) ) +#define GetKeyInfo1(f, mask) ((f.Octet[KeyInfoPos] & mask) ? 1 : 0) +#define SetKeyInfo1(f,mask,b) (f.Octet[KeyInfoPos] = (f.Octet[KeyInfoPos] & ~mask) | ( b?mask:0x0) ) + +// EAPOLKey +#define Message_DescType(f) (f.Octet[DescTypePos]) +#define Message_setDescType(f, type) (f.Octet[DescTypePos] = type) +// Key Information Filed +#define Message_KeyDescVer(f) (f.Octet[KeyInfoPos+1] & 0x07) +#define Message_setKeyDescVer(f, v) (f.Octet[KeyInfoPos+1] &= 0xf8) , f.Octet[KeyInfoPos+1] |= (v & 0x07) +#define Message_KeyType(f) GetKeyInfo0(f, 0x08) +#define Message_setKeyType(f, b) SetKeyInfo0(f,0x08,b) +#define Message_KeyIndex(f) ((f.Octet[KeyInfoPos+1] & 0x30) >> 4) & 0x03 +#define Message_setKeyIndex(f, v) (f.Octet[KeyInfoPos+1] &= 0xcf), f.Octet[KeyInfoPos+1] |= ((v<<4) & 0x30) +#define Message_setInstall(f, b) SetKeyInfo0(f,0x40,b) +#define Message_setKeyAck(f, b) SetKeyInfo0(f,0x80,b) + +#define Message_KeyMIC(f) GetKeyInfo1(f, 0x01) +#define Message_setKeyMIC(f, b) SetKeyInfo1(f,0x01,b) +#define Message_Secure(f) GetKeyInfo1(f,0x02) +#define Message_setSecure(f, b) SetKeyInfo1(f,0x02,b) +#define Message_Error(f) GetKeyInfo1(f,0x04) +#define Message_setError(f, b) SetKeyInfo1(f,0x04,b) +#define Message_Request(f) GetKeyInfo1(f,0x08) +#define Message_setRequest(f, b) SetKeyInfo1(f,0x08,b) +#define Message_setReserved(f, v) (f.Octet[KeyInfoPos] |= (v<<4&0xff)) +#define Message_KeyLength(f) ((unsigned short)(f.Octet[KeyLenPos] <<8) + (unsigned short)(f.Octet[KeyLenPos+1])) +#define Message_setKeyLength(f, v) (f.Octet[KeyLenPos] = (v&0xff00) >>8 , f.Octet[KeyLenPos+1] = (v&0x00ff)) + +#define Message_KeyNonce(f) SubStr(f, KeyNoncePos, KEY_NONCE_LEN) +#define Message_setKeyNonce(f, v) SetSubStr(f, v, KeyNoncePos) +#define Message_EqualKeyNonce(f1, f2) memcmp(f1.Octet + KeyNoncePos, f2.Octet, KEY_NONCE_LEN)? 0:1 +#define Message_setKeyIV(f, v) SetSubStr(f, v, KeyIVPos) +#define Message_setKeyRSC(f, v) SetSubStr(f, v, KeyRSCPos) +#define Message_setKeyID(f, v) SetSubStr(f, v, KeyIDPos) +#define Message_setMIC(f, v) SetSubStr(f, v, KeyMICPos) +#define Message_KeyDataLength(f) ((unsigned short)(f.Octet[KeyDataLenPos] <<8) + (unsigned short)(f.Octet[KeyDataLenPos+1])) +#define Message_setKeyDataLength(f, v) (f.Octet[KeyDataLenPos] = (v&0xff00) >>8 , f.Octet[KeyDataLenPos+1] = (v&0x00ff)) +#define Message_setKeyData(f, v) SetSubStr(f, v, KeyDataPos); + +#define Message_CopyReplayCounter(f1, f2) memcpy(f1.Octet + ReplayCounterPos, f2.Octet + ReplayCounterPos, KEY_RC_LEN) +#define Message_DefaultReplayCounter(li) (((li.field.HighPart == 0xffffffff) && (li.field.LowPart == 0xffffffff) ) ?1:0) + +#define GET_MY_HWADDR(padapter) ((padapter)->eeprompriv.mac_addr) +#define LargeIntegerOverflow(x) (x.field.HighPart == 0xffffffff) && (x.field.LowPart == 0xffffffff) +#define LargeIntegerZero(x) memset(&x.charData, 0, 8) +#define Octet16IntegerOverflow(x) LargeIntegerOverflow(x.field.HighPart) && LargeIntegerOverflow(x.field.LowPart) +#define Octet16IntegerZero(x) memset(&x.charData, 0, 16) +#define SetNonce(ocDst, oc32Counter) SetEAPOL_KEYIV(ocDst, oc32Counter) + +void ClientSendEAPOL(_adapter *padapter, struct sta_info *psta, int resend); +void SendEAPOL(_adapter *padapter, struct sta_info *psta, int resend); +void EAPOLKeyRecvd(_adapter *padapter, struct sta_info *psta); +void ClientEAPOLKeyRecvd(_adapter *padapter, struct sta_info *psta); +void init_wpa_sta_info(_adapter *padapter, struct sta_info *psta); +void psk_init(_adapter *padapter, unsigned char *pie, unsigned short ielen); +void psk_derive(_adapter *padapter, unsigned char *passphrase, unsigned char *ssid); +u16 psk_strip_rsn_pairwise(u8 *ie, u16 ie_len); +u16 psk_strip_wpa_pairwise(u8 *ie, u16 ie_len); + +#endif // _RTW_PSK_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_pwrctrl.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_pwrctrl.h new file mode 100644 index 0000000..c90c200 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_pwrctrl.h @@ -0,0 +1,386 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_PWRCTRL_H_ +#define __RTW_PWRCTRL_H_ + + +#ifdef CONFIG_HAS_EARLYSUSPEND +#include +#endif //CONFIG_HAS_EARLYSUSPEND + +#define FW_PWR0 0 +#define FW_PWR1 1 +#define FW_PWR2 2 +#define FW_PWR3 3 + + +#define HW_PWR0 7 +#define HW_PWR1 6 +#define HW_PWR2 2 +#define HW_PWR3 0 +#define HW_PWR4 8 + +#define FW_PWRMSK 0x7 + + +#define XMIT_ALIVE BIT(0) +#define RECV_ALIVE BIT(1) +#define CMD_ALIVE BIT(2) +#define EVT_ALIVE BIT(3) + + +enum Power_Mgnt +{ + PS_MODE_ACTIVE = 0 , + PS_MODE_MIN , + PS_MODE_MAX , + PS_MODE_DTIM , + PS_MODE_VOIP , + PS_MODE_UAPSD_WMM , + PS_MODE_UAPSD , + PS_MODE_IBSS , + PS_MODE_WWLAN , + PM_Radio_Off , + PM_Card_Disable , + PS_MODE_NUM +}; + + +/* + BIT[2:0] = HW state + BIT[3] = Protocol PS state, 0: register active state , 1: register sleep state + BIT[4] = sub-state +*/ + +#define PS_DPS BIT(0) +#define PS_LCLK (PS_DPS) +#define PS_RF_OFF BIT(1) +#define PS_ALL_ON BIT(2) +#define PS_ST_ACTIVE BIT(3) + +#define PS_ISR_ENABLE BIT(4) +#define PS_IMR_ENABLE BIT(5) +#define PS_ACK BIT(6) +#define PS_TOGGLE BIT(7) + +#define PS_STATE_MASK (0x0F) +#define PS_STATE_HW_MASK (0x07) +#define PS_SEQ_MASK (0xc0) + +#define PS_STATE(x) (PS_STATE_MASK & (x)) +#define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x)) +#define PS_SEQ(x) (PS_SEQ_MASK & (x)) + +#define PS_STATE_S0 (PS_DPS) +#define PS_STATE_S1 (PS_LCLK) +#define PS_STATE_S2 (PS_RF_OFF) +#define PS_STATE_S3 (PS_ALL_ON) +#define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON)) + + +#define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON)) +#define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE)) +#define CLR_PS_STATE(x) ((x) = ((x) & (0xF0))) + + +struct reportpwrstate_parm { + unsigned char mode; + unsigned char state; //the CPWM value + unsigned short rsvd; +}; + + +typedef _sema _pwrlock; + + +__inline static void _init_pwrlock(_pwrlock *plock) +{ + rtw_init_sema(plock, 1); +} + +__inline static void _free_pwrlock(_pwrlock *plock) +{ + rtw_free_sema(plock); +} + + +__inline static void _enter_pwrlock(_pwrlock *plock) +{ + rtw_down_sema(plock); +} + + +__inline static void _exit_pwrlock(_pwrlock *plock) +{ + rtw_up_sema(plock); +} + +#define LPS_DELAY_TIME 1 // 1 sec + +#define EXE_PWR_NONE 0x01 +#define EXE_PWR_IPS 0x02 +#define EXE_PWR_LPS 0x04 + +// RF state. +typedef enum _rt_rf_power_state +{ + rf_on, // RF is on after RFSleep or RFOff + rf_sleep, // 802.11 Power Save mode + rf_off, // HW/SW Radio OFF or Inactive Power Save + //=====Add the new RF state above this line=====// + rf_max +}rt_rf_power_state; + +// RF Off Level for IPS or HW/SW radio off +#define RT_RF_OFF_LEVL_ASPM BIT(0) // PCI ASPM +#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) // PCI clock request +#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) // PCI D3 mode +#define RT_RF_OFF_LEVL_HALT_NIC BIT(3) // NIC halt, re-initialize hw parameters +#define RT_RF_OFF_LEVL_FREE_FW BIT(4) // FW free, re-download the FW +#define RT_RF_OFF_LEVL_FW_32K BIT(5) // FW in 32k +#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) // Always enable ASPM and Clock Req in initialization. +#define RT_RF_LPS_DISALBE_2R BIT(30) // When LPS is on, disable 2R if no packet is received or transmittd. +#define RT_RF_LPS_LEVEL_ASPM BIT(31) // LPS with ASPM + +#define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) ((ppsc->cur_ps_level & _PS_FLAG) ? _TRUE : _FALSE) +#define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level &= (~(_PS_FLAG))) +#define RT_SET_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level |= _PS_FLAG) + + +enum _PS_BBRegBackup_ { + PSBBREG_RF0 = 0, + PSBBREG_RF1, + PSBBREG_RF2, + PSBBREG_AFE0, + PSBBREG_TOTALCNT +}; + +enum { // for ips_mode + IPS_NONE=0, + IPS_NORMAL, + IPS_LEVEL_2, + IPS_NUM +}; + +struct pwrctrl_priv +{ + _pwrlock lock; + volatile u8 rpwm; // requested power state for fw + volatile u8 cpwm; // fw current power state. updated when 1. read from HCPWM 2. driver lowers power level + volatile u8 tog; // toggling + volatile u8 cpwm_tog; // toggling + + u8 pwr_mode; + u8 smart_ps; + u8 bcn_ant_mode; + + u32 alives; + u64 wowlan_fw_iv; +//TODO +// _workitem cpwm_event; +#ifdef CONFIG_LPS_RPWM_TIMER + u8 brpwmtimeout; + _workitem rpwmtimeoutwi; + _timer pwr_rpwm_timer; +#endif // CONFIG_LPS_RPWM_TIMER + u8 bpower_saving; + + u8 b_hw_radio_off; + u8 reg_rfoff; + u8 reg_pdnmode; //powerdown mode + u32 rfoff_reason; + + //RF OFF Level + u32 cur_ps_level; + u32 reg_rfps_level; + + + +#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI) + //just for PCIE ASPM + u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00. + u8 b_support_backdoor; + + //just for PCIE ASPM + u8 const_amdpci_aspm; +#endif + + uint ips_enter_cnts; + uint ips_leave_cnts; + + u8 ps_enable; + u8 ips_mode; + u8 ips_org_mode; + u8 ips_mode_req; // used to accept the mode setting request, will update to ipsmode later + uint bips_processing; + u32 ips_deny_time; /* will deny IPS when system time is smaller than this */ + u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */ + + u8 bLeisurePs; + u8 LpsIdleCount; + u8 power_mgnt; + u8 org_power_mgnt; + u8 bFwCurrentInPSMode; + u32 DelayLPSLastTimeStamp; + u8 btcoex_rfon; + s32 pnp_current_pwr_state; + u8 pnp_bstop_trx; + + + u8 bInternalAutoSuspend; + u8 bInSuspend; +#ifdef CONFIG_BT_COEXIST + u8 bAutoResume; + u8 autopm_cnt; +#endif + u8 bSupportRemoteWakeup; +#ifdef CONFIG_WOWLAN + u8 wowlan_txpause_status; + u8 wowlan_mode; + u8 wowlan_pattern; + u8 wowlan_magic; + u8 wowlan_unicast; + u8 wowlan_pattern_idx; + u8 wowlan_wake_reason; + u32 wowlan_pattern_context[8][5]; +#endif // CONFIG_WOWLAN + _timer pwr_state_check_timer; + int pwr_state_check_interval; + u8 pwr_state_check_cnts; + + int ps_flag; + + rt_rf_power_state rf_pwrstate;//cur power state + //rt_rf_power_state current_rfpwrstate; + rt_rf_power_state change_rfpwrstate; + + u8 wepkeymask; + u8 bHWPowerdown;//if support hw power down + u8 bHWPwrPindetect; + u8 bkeepfwalive; + u8 brfoffbyhw; + unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT]; + + #ifdef CONFIG_RESUME_IN_WORKQUEUE + struct workqueue_struct *rtw_workqueue; + _workitem resume_work; + #endif + + #ifdef CONFIG_HAS_EARLYSUSPEND + struct early_suspend early_suspend; + u8 do_late_resume; + #endif //CONFIG_HAS_EARLYSUSPEND + + #ifdef CONFIG_ANDROID_POWER + android_early_suspend_t early_suspend; + u8 do_late_resume; + #endif + + #ifdef CONFIG_INTEL_PROXIM + u8 stored_power_mgnt; + #endif + + #ifdef TDMA_POWER_SAVING + u8 tdma_slot_period; + u8 tdma_rfon_period_len_1; + u8 tdma_rfon_period_len_2; + u8 tdma_rfon_period_len_3; + #endif + + u8 lps_dtim; +}; + +#define rtw_get_ips_mode_req(pwrctrlpriv) \ + (pwrctrlpriv)->ips_mode_req + +#define rtw_ips_mode_req(pwrctrlpriv, ips_mode) \ + (pwrctrlpriv)->ips_mode_req = (ips_mode) + +#define RTW_PWR_STATE_CHK_INTERVAL 2000 + +#define _rtw_set_pwr_state_check_timer(pwrctrlpriv, ms) \ + do { \ + /*DBG_871X("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctrlpriv), (ms));*/ \ + rtw_set_timer(&(pwrctrlpriv)->pwr_state_check_timer, (ms)); \ + } while(0) + +#define rtw_set_pwr_state_check_timer(pwrctrlpriv) \ + _rtw_set_pwr_state_check_timer((pwrctrlpriv), (pwrctrlpriv)->pwr_state_check_interval) + +extern void rtw_init_pwrctrl_priv(_adapter *adapter); +extern void rtw_free_pwrctrl_priv(_adapter * adapter); + +#ifdef CONFIG_LPS_LCLK +extern s32 rtw_register_tx_alive(PADAPTER padapter); +extern void rtw_unregister_tx_alive(PADAPTER padapter); +extern s32 rtw_register_rx_alive(PADAPTER padapter); +extern void rtw_unregister_rx_alive(PADAPTER padapter); +extern s32 rtw_register_cmd_alive(PADAPTER padapter); +extern void rtw_unregister_cmd_alive(PADAPTER padapter); +extern s32 rtw_register_evt_alive(PADAPTER padapter); +extern void rtw_unregister_evt_alive(PADAPTER padapter); +extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate); +extern void LPS_Leave_check(PADAPTER padapter); +#endif + +extern void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode); +extern void rtw_set_rpwm(_adapter * padapter, u8 val8); +extern void LeaveAllPowerSaveMode(PADAPTER Adapter); +#ifdef CONFIG_IPS +void ips_enter(_adapter * padapter); +int ips_leave(_adapter * padapter); +#endif + +void rtw_ps_processor(_adapter*padapter); + +#ifdef CONFIG_AUTOSUSPEND +int autoresume_enter(_adapter* padapter); +#endif +#ifdef SUPPORT_HW_RFOFF_DETECTED +rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter ); +#endif + + +#ifdef CONFIG_LPS +s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms); +void LPS_Enter(PADAPTER padapter); +void LPS_Leave(PADAPTER padapter); +#endif + +#ifdef CONFIG_RESUME_IN_WORKQUEUE +void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv); +#endif //CONFIG_RESUME_IN_WORKQUEUE + +#if defined(CONFIG_HAS_EARLYSUSPEND ) || defined(CONFIG_ANDROID_POWER) +#define rtw_is_earlysuspend_registered(pwrpriv) (pwrpriv)->early_suspend.suspend +void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv); +void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv); +#endif //CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER +//TODO +//u8 rtw_interface_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id,u8* val); +int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller); +#define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__) +int rtw_pm_set_ips(_adapter *padapter, u8 mode); +int rtw_pm_set_lps(_adapter *padapter, u8 mode); +int rtw_pm_set_tdma_param(_adapter *padapter, u8 tdma_slot_period, u8 tdma_rfon_period_len_1, u8 tdma_rfon_period_len_2, u8 tdma_rfon_period_len_3); +int rtw_pm_set_lps_dtim(_adapter *padapter, u8 lps_dtim); +u8 rtw_pm_get_lps_dtim(_adapter *padapter); +#endif //__RTL871X_PWRCTRL_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_qos.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_qos.h new file mode 100644 index 0000000..0d6c8c4 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_qos.h @@ -0,0 +1,33 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef _RTW_QOS_H_ +#define _RTW_QOS_H_ + +struct qos_priv { + + u32 qos_option; //bit mask option: u-apsd, s-apsd, ts, block ack... + +}; + + +#endif //_RTL871X_QOS_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_recv.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_recv.h new file mode 100644 index 0000000..523c4d0 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_recv.h @@ -0,0 +1,918 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_RECV_H_ +#define _RTW_RECV_H_ +#include + +#if defined(PLATFORM_ECOS) +#define NR_RECVFRAME 16 //Decrease recv frame due to memory limitation - Alex Fang +#elif defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) +#ifdef CONFIG_RECV_REORDERING_CTRL +#define NR_RECVFRAME 16 //Increase recv frame due to rx reorder - Andy Sun +#else +#if WIFI_LOGO_CERTIFICATION + #define NR_RECVFRAME 8 //Decrease recv frame due to memory limitation - Alex Fang +#else +#ifndef CONFIG_HIGH_TP + #define NR_RECVFRAME 2 //Decrease recv frame due to memory limitation - YangJue +#else + #define NR_RECVFRAME 256 +#endif +#endif +#endif +#else +#define NR_RECVFRAME 256 +#endif + +#ifdef PLATFORM_OS_XP + #define NR_RECVBUFF (16) +#elif defined(PLATFORM_OS_CE) + #define NR_RECVBUFF (4) +#elif defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) +#ifndef CONFIG_HIGH_TP +// #define NR_RECVBUFF (8) //Decrease recv buffer due to memory limitation - Alex Fang + #define NR_RECVBUFF (1) //Decrease recv buffer due to memory limitation - YangJue +#else + #define NR_RECVBUFF (32) +#endif +#else + #if (defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI) + #define NR_RECVBUFF (32) + #else + #define NR_RECVBUFF (4) + #endif + + #define NR_PREALLOC_RECV_SKB (8) +#endif + +#define RECV_BULK_IN_ADDR 0x80 +#define RECV_INT_IN_ADDR 0x81 + +#define PHY_RSSI_SLID_WIN_MAX 100 +#define PHY_LINKQUALITY_SLID_WIN_MAX 20 + +// Rx smooth factor +#define Rx_Smooth_Factor (20) + +#define RXFRAME_ALIGN 8 +#define RXFRAME_ALIGN_SZ (1<signal_stat_timer, (recvpriv)->signal_stat_sampling_interval) +#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS + +struct sta_recv_priv { + + _lock lock; + sint option; + + //_queue blk_strms[MAX_RX_NUMBLKS]; + _queue defrag_q; //keeping the fragment frame until defrag + + struct stainfo_rxcache rxcache; + + //uint sta_rx_bytes; + //uint sta_rx_pkts; + //uint sta_rx_fail; + +}; + +struct recv_buf +{ + _list list; + +// _lock recvbuf_lock; + +// u32 ref_cnt; + + PADAPTER adapter; + +// u8 *pbuf; +// u8 *pallocated_buf; + + u32 len; + u8 *phead; + u8 *pdata; + u8 *ptail; + u8 *pend; + +#ifdef CONFIG_USB_HCI + + #if defined(PLATFORM_OS_XP)||defined(PLATFORM_LINUX)||defined(PLATFORM_FREEBSD) + PURB purb; + dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */ + u32 alloc_sz; + #endif + + #ifdef PLATFORM_OS_XP + PIRP pirp; + #endif + + #ifdef PLATFORM_OS_CE + USB_TRANSFER usb_transfer_read_port; + #endif + + u8 irp_pending; + int transfer_len; + +#endif + +#if defined(PLATFORM_LINUX) || defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) + _pkt *pskb; +// u8 reuse; +#endif +#ifdef PLATFORM_FREEBSD //skb solution + struct sk_buff *pskb; + u8 reuse; +#endif //PLATFORM_FREEBSD //skb solution +}; + +/* + head -----> + + data -----> + + payload + + tail -----> + + + end -----> + + len = (unsigned int )(tail - data); + +*/ +struct recv_frame_hdr +{ + _list list; +#ifndef CONFIG_BSD_RX_USE_MBUF + struct sk_buff *pkt; + struct sk_buff *pkt_newalloc; +#else // CONFIG_BSD_RX_USE_MBUF + _pkt *pkt; + _pkt *pkt_newalloc; +#endif // CONFIG_BSD_RX_USE_MBUF + + _adapter *adapter; + + u8 fragcnt; + + int frame_tag; + + struct rx_pkt_attrib attrib; + + uint len; + u8 *rx_head; + u8 *rx_data; + u8 *rx_tail; + u8 *rx_end; + + void *precvbuf; + + + // + struct sta_info *psta; +#ifdef CONFIG_RECV_REORDERING_CTRL + //for A-MPDU Rx reordering buffer control + struct recv_reorder_ctrl *preorder_ctrl; +#endif +#ifdef CONFIG_WAPI_SUPPORT + u8 UserPriority; + u8 WapiTempPN[16]; + u8 WapiSrcAddr[6]; + u8 bWapiCheckPNInDecrypt; + u8 bIsWaiPacket; +#endif + +}; + +union recv_frame{ + + union{ + _list list; + struct recv_frame_hdr hdr; + uint mem[RECVFRAME_HDR_ALIGN>>2]; + }u; + + //uint mem[MAX_RXSZ>>2]; + +}; + +typedef enum _RX_PACKET_TYPE{ + NORMAL_RX,//Normal rx packet + TX_REPORT1,//CCX + TX_REPORT2,//TX RPT + HIS_REPORT,// USB HISR RPT + C2H_PACKET +}RX_PACKET_TYPE, *PRX_PACKET_TYPE; + +extern union recv_frame *_rtw_alloc_recvframe (_queue *pfree_recv_queue); //get a free recv_frame from pfree_recv_queue +extern void rtw_init_recvframe(union recv_frame *precvframe ,struct recv_priv *precvpriv); +extern int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue); + +#define rtw_dequeue_recvframe(queue) rtw_alloc_recvframe(queue) +extern int _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue); + +#ifdef CONFIG_TRACE_SKB +int __rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue); +union recv_frame *__rtw_alloc_recvframe (_queue *pfree_recv_queue); //get a free recv_frame from pfree_recv_queue + +#define rtw_enqueue_recvframe(precvframe, queue, Q) \ + do{\ + set_skb_list_flag(precvframe->u.hdr.pkt, SKBLIST_RECVFRAME_##Q);\ + __rtw_enqueue_recvframe(precvframe, queue);\ + }while (0) +#define rtw_alloc_recvframe(queue, precvframe, Q) \ + (\ + precvframe = __rtw_alloc_recvframe(queue),\ + precvframe ? clear_skb_list_flag(precvframe->u.hdr.pkt, SKBLIST_RECVFRAME_##Q):0,\ + precvframe\ + ) +#else +extern int rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue); +extern union recv_frame *rtw_alloc_recvframe (_queue *pfree_recv_queue); //get a free recv_frame from pfree_recv_queue +#endif + +extern void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue); +u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter); + +#ifdef CONFIG_TRACE_SKB +sint _rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue); +sint _rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue); +struct recv_buf *_rtw_dequeue_recvbuf (_queue *queue); + +#define rtw_enqueue_recvbuf_to_head(precvbuf, queue, Q) \ + do{\ + set_skb_list_flag(precvbuf->pskb, SKBLIST_RECVBUF_##Q);\ + _rtw_enqueue_recvbuf_to_head(precvbuf, queue);\ + }while (0) +#define rtw_enqueue_recvbuf(precvbuf, queue, Q) \ + do{\ + set_skb_list_flag(precvbuf->pskb, SKBLIST_RECVBUF_##Q);\ + _rtw_enqueue_recvbuf(precvbuf, queue);\ + }while (0) +#define rtw_dequeue_recvbuf(queue, precvbuf, Q) \ + (\ + precvbuf = _rtw_dequeue_recvbuf(queue),\ + precvbuf ? clear_skb_list_flag(precvbuf->pskb, SKBLIST_RECVBUF_##Q):0,\ + precvbuf\ + ) + +#else +sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue); +sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue); +struct recv_buf *rtw_dequeue_recvbuf (_queue *queue); +#endif + +void rtw_reordering_ctrl_timeout_handler(void *pcontext); + + +__inline static u8 *get_rxmem(union recv_frame *precvframe) +{ + //always return rx_head... + if(precvframe==NULL) + return NULL; + + return precvframe->u.hdr.rx_head; +} + +__inline static u8 *get_rx_status(union recv_frame *precvframe) +{ + + return get_rxmem(precvframe); + +} + + + +__inline static u8 *get_recvframe_data(union recv_frame *precvframe) +{ + + //alwasy return rx_data + if(precvframe==NULL) + return NULL; + + return precvframe->u.hdr.rx_data; + +} + +//TODO +#if 0 + +__inline static u8 *recvframe_push(union recv_frame *precvframe, sint sz) +{ + // append data before rx_data + + /* add data to the start of recv_frame + * + * This function extends the used data area of the recv_frame at the buffer + * start. rx_data must be still larger than rx_head, after pushing. + */ + + if(precvframe==NULL) + return NULL; + + + precvframe->u.hdr.rx_data -= sz ; + if( precvframe->u.hdr.rx_data < precvframe->u.hdr.rx_head ) + { + precvframe->u.hdr.rx_data += sz ; + return NULL; + } + + precvframe->u.hdr.len +=sz; + + return precvframe->u.hdr.rx_data; + +} + +#endif //#if 0 + +__inline static u8 *recvframe_pull(union recv_frame *precvframe, sint sz) +{ + // rx_data += sz; move rx_data sz bytes hereafter + + //used for extract sz bytes from rx_data, update rx_data and return the updated rx_data to the caller + + + if(precvframe==NULL) + return NULL; + + + precvframe->u.hdr.rx_data += sz; + + if(precvframe->u.hdr.rx_data > precvframe->u.hdr.rx_tail) + { + precvframe->u.hdr.rx_data -= sz; + return NULL; + } + + precvframe->u.hdr.len -=sz; + + return precvframe->u.hdr.rx_data; + +} + +__inline static u8 *recvframe_put(union recv_frame *precvframe, sint sz) +{ + // rx_tai += sz; move rx_tail sz bytes hereafter + + //used for append sz bytes from ptr to rx_tail, update rx_tail and return the updated rx_tail to the caller + //after putting, rx_tail must be still larger than rx_end. + + if(precvframe==NULL) + return NULL; + + precvframe->u.hdr.rx_tail += sz; + + if(precvframe->u.hdr.rx_tail > precvframe->u.hdr.rx_end) + { + precvframe->u.hdr.rx_tail -= sz; + return NULL; + } + + precvframe->u.hdr.len +=sz; + + return precvframe->u.hdr.rx_tail; + +} + + + +__inline static u8 *recvframe_pull_tail(union recv_frame *precvframe, sint sz) +{ + // rmv data from rx_tail (by yitsen) + + //used for extract sz bytes from rx_end, update rx_end and return the updated rx_end to the caller + //after pulling, rx_end must be still larger than rx_data. + + if(precvframe==NULL) + return NULL; + + precvframe->u.hdr.rx_tail -= sz; + + if(precvframe->u.hdr.rx_tail < precvframe->u.hdr.rx_data) + { + precvframe->u.hdr.rx_tail += sz; + return NULL; + } + + precvframe->u.hdr.len -=sz; + + return precvframe->u.hdr.rx_tail; + +} + +__inline static _buffer * get_rxbuf_desc(union recv_frame *precvframe) +{ + _buffer * buf_desc = NULL; + + if(precvframe==NULL) + return NULL; +#ifdef PLATFORM_WINDOWS + NdisQueryPacket(precvframe->u.hdr.pkt, NULL, NULL, &buf_desc, NULL); +#endif + + return buf_desc; +} + + +__inline static union recv_frame *rxmem_to_recvframe(u8 *rxmem) +{ + //due to the design of 2048 bytes alignment of recv_frame, we can reference the union recv_frame + //from any given member of recv_frame. + // rxmem indicates the any member/address in recv_frame + + return (union recv_frame*)(((SIZE_PTR)rxmem >> RXFRAME_ALIGN) << RXFRAME_ALIGN); + +} + +__inline static union recv_frame *pkt_to_recvframe(_pkt *pkt) +{ + + u8 * buf_star = NULL; + union recv_frame * precv_frame = NULL; +#ifdef PLATFORM_WINDOWS + _buffer * buf_desc; + uint len; + + NdisQueryPacket(pkt, NULL, NULL, &buf_desc, &len); + NdisQueryBufferSafe(buf_desc, &buf_star, &len, HighPagePriority); +#endif + precv_frame = rxmem_to_recvframe((unsigned char*)buf_star); + + return precv_frame; +} + +__inline static u8 *pkt_to_recvmem(_pkt *pkt) +{ + // return the rx_head + + union recv_frame * precv_frame = pkt_to_recvframe(pkt); + + return precv_frame->u.hdr.rx_head; + +} + +__inline static u8 *pkt_to_recvdata(_pkt *pkt) +{ + // return the rx_data + + union recv_frame * precv_frame =pkt_to_recvframe(pkt); + + return precv_frame->u.hdr.rx_data; + +} + + +__inline static sint get_recvframe_len(union recv_frame *precvframe) +{ + return precvframe->u.hdr.len; +} + + +__inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex) +{ + s32 SignalPower; // in dBm. + +#ifndef CONFIG_SKIP_SIGNAL_SCALE_MAPPING + // Translate to dBm (x=0.9y-95). + SignalPower = (s32)((SignalStrengthIndex *18) /20); + SignalPower -= 95; +#else + /* Translate to dBm (x=y-100) */ + SignalPower = SignalStrengthIndex - 100; +#endif + + return SignalPower; +} + + +struct sta_info; + +extern void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv); +extern void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame); +int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe); + +void rtw_rxhandler(_adapter * padapter, struct recv_buf *precvbuf); +u32 rtw_free_buf_pending_queue(_adapter *adapter); + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_rf.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_rf.h new file mode 100644 index 0000000..a9f8220 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_rf.h @@ -0,0 +1,175 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_RF_H_ +#define __RTW_RF_H_ + + +#define OFDM_PHY 1 +#define MIXED_PHY 2 +#define CCK_PHY 3 + +#define NumRates (13) + +// slot time for 11g +#define SHORT_SLOT_TIME 9 +#define NON_SHORT_SLOT_TIME 20 + +#define RTL8711_RF_MAX_SENS 6 +#define RTL8711_RF_DEF_SENS 4 + +// +// We now define the following channels as the max channels in each channel plan. +// 2G, total 14 chnls +// {1,2,3,4,5,6,7,8,9,10,11,12,13,14} +// 5G, total 24 chnls +// {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165} +#define MAX_CHANNEL_NUM_2G 14 +#define MAX_CHANNEL_NUM_5G 24 +#if defined(NOT_SUPPORT_5G) +#define MAX_CHANNEL_NUM 14 +#else +#define MAX_CHANNEL_NUM 38//14+24 +#endif + +//#define NUM_REGULATORYS 21 +#define NUM_REGULATORYS 1 + +//Country codes +#define USA 0x555320 +#define EUROPE 0x1 //temp, should be provided later +#define JAPAN 0x2 //temp, should be provided later + +struct regulatory_class { + u32 starting_freq; //MHz, + u8 channel_set[MAX_CHANNEL_NUM]; + u8 channel_cck_power[MAX_CHANNEL_NUM];//dbm + u8 channel_ofdm_power[MAX_CHANNEL_NUM];//dbm + u8 txpower_limit; //dbm + u8 channel_spacing; //MHz + u8 modem; +}; + +typedef enum _CAPABILITY{ + cESS = 0x0001, + cIBSS = 0x0002, + cPollable = 0x0004, + cPollReq = 0x0008, + cPrivacy = 0x0010, + cShortPreamble = 0x0020, + cPBCC = 0x0040, + cChannelAgility = 0x0080, + cSpectrumMgnt = 0x0100, + cQos = 0x0200, // For HCCA, use with CF-Pollable and CF-PollReq + cShortSlotTime = 0x0400, + cAPSD = 0x0800, + cRM = 0x1000, // RRM (Radio Request Measurement) + cDSSS_OFDM = 0x2000, + cDelayedBA = 0x4000, + cImmediateBA = 0x8000, +}CAPABILITY, *PCAPABILITY; + +enum _REG_PREAMBLE_MODE{ + PREAMBLE_LONG = 1, + PREAMBLE_AUTO = 2, + PREAMBLE_SHORT = 3, +}; + + +enum _RTL8712_RF_MIMO_CONFIG_{ + RTL8712_RFCONFIG_1T=0x10, + RTL8712_RFCONFIG_2T=0x20, + RTL8712_RFCONFIG_1R=0x01, + RTL8712_RFCONFIG_2R=0x02, + RTL8712_RFCONFIG_1T1R=0x11, + RTL8712_RFCONFIG_1T2R=0x12, + RTL8712_RFCONFIG_TURBO=0x92, + RTL8712_RFCONFIG_2T2R=0x22 +}; + + +typedef enum _RF90_RADIO_PATH{ + RF90_PATH_A = 0, //Radio Path A + RF90_PATH_B = 1, //Radio Path B + RF90_PATH_C = 2, //Radio Path C + RF90_PATH_D = 3 //Radio Path D + //RF90_PATH_MAX //Max RF number 90 support +}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E; + +// Bandwidth Offset +#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 +#define HAL_PRIME_CHNL_OFFSET_LOWER 1 +#define HAL_PRIME_CHNL_OFFSET_UPPER 2 + +// Represent Channel Width in HT Capabilities +// +typedef enum _CHANNEL_WIDTH{ + CHANNEL_WIDTH_20 = 0, + CHANNEL_WIDTH_40 = 1, + CHANNEL_WIDTH_80 = 2, + CHANNEL_WIDTH_160 = 3, + CHANNEL_WIDTH_80_80 = 4, + CHANNEL_WIDTH_MAX = 5, +}CHANNEL_WIDTH, *PCHANNEL_WIDTH; + +// +// Represent Extention Channel Offset in HT Capabilities +// This is available only in 40Mhz mode. +// +typedef enum _EXTCHNL_OFFSET{ + EXTCHNL_OFFSET_NO_EXT = 0, + EXTCHNL_OFFSET_UPPER = 1, + EXTCHNL_OFFSET_NO_DEF = 2, + EXTCHNL_OFFSET_LOWER = 3, +}EXTCHNL_OFFSET, *PEXTCHNL_OFFSET; + +typedef enum _VHT_DATA_SC{ + VHT_DATA_SC_DONOT_CARE = 0, + VHT_DATA_SC_20_UPPER_OF_80MHZ = 1, + VHT_DATA_SC_20_LOWER_OF_80MHZ = 2, + VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3, + VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4, + VHT_DATA_SC_20_RECV1 = 5, + VHT_DATA_SC_20_RECV2 = 6, + VHT_DATA_SC_20_RECV3 = 7, + VHT_DATA_SC_20_RECV4 = 8, + VHT_DATA_SC_40_UPPER_OF_80MHZ = 9, + VHT_DATA_SC_40_LOWER_OF_80MHZ = 10, +}VHT_DATA_SC, *PVHT_DATA_SC_E; + + + +/* 2007/11/15 MH Define different RF type. */ +typedef enum _RT_RF_TYPE_DEFINITION +{ + RF_1T2R = 0, + RF_2T4R = 1, + RF_2T2R = 2, + RF_1T1R = 3, + RF_2T2R_GREEN = 4, + RF_819X_MAX_TYPE = 5, +}RT_RF_TYPE_DEF_E; + + +u32 rtw_ch2freq(u32 ch); +u32 rtw_freq2ch(u32 freq); + + +#endif //_RTL8711_RF_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_security.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_security.h new file mode 100644 index 0000000..958be9d --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_security.h @@ -0,0 +1,446 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_SECURITY_H_ +#define __RTW_SECURITY_H_ + + +#define _NO_PRIVACY_ 0x0 +#define _WEP40_ 0x1 +#define _TKIP_ 0x2 +#define _TKIP_WTMIC_ 0x3 +#define _AES_ 0x4 +#define _WEP104_ 0x5 +#define _WEP_WPA_MIXED_ 0x07 // WEP + WPA +#define _SMS4_ 0x06 + +#define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_)) + +#define _WPA_IE_ID_ 0xdd +#define _WPA2_IE_ID_ 0x30 + +#define SHA256_MAC_LEN 32 +#define AES_BLOCK_SIZE 16 +#define AES_PRIV_SIZE (4 * 44) +#define _AES_IV_LEN_ 8 + +typedef enum { + ENCRYP_PROTOCOL_OPENSYS, //open system + ENCRYP_PROTOCOL_WEP, //WEP + ENCRYP_PROTOCOL_WPA, //WPA + ENCRYP_PROTOCOL_WPA2, //WPA2 + ENCRYP_PROTOCOL_WAPI, //WAPI: Not support in this version + ENCRYP_PROTOCOL_MAX +}ENCRYP_PROTOCOL_E; + + +#ifndef Ndis802_11AuthModeWPA2 +#define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1) +#endif + +#ifndef Ndis802_11AuthModeWPA2PSK +#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2) +#endif + +union pn48 { + + u64 val; + +#ifdef CONFIG_LITTLE_ENDIAN + +struct { + u8 TSC0; + u8 TSC1; + u8 TSC2; + u8 TSC3; + u8 TSC4; + u8 TSC5; + u8 TSC6; + u8 TSC7; +} _byte_; + +#elif defined(CONFIG_BIG_ENDIAN) + +struct { + u8 TSC7; + u8 TSC6; + u8 TSC5; + u8 TSC4; + u8 TSC3; + u8 TSC2; + u8 TSC1; + u8 TSC0; +} _byte_; + +#endif + +}; + +union Keytype { + u8 skey[16]; + u32 lkey[4]; +}; + + +typedef struct _RT_PMKID_LIST +{ + u8 bUsed; + u8 Bssid[6]; + u8 PMKID[16]; + u8 SsidBuf[33]; + u8* ssid_octet; + u16 ssid_length; +} RT_PMKID_LIST, *PRT_PMKID_LIST; + + +struct security_priv +{ + u32 dot11AuthAlgrthm; // 802.11 auth, could be open, shared, 8021x and authswitch + u32 dot11PrivacyAlgrthm; // This specify the privacy for shared auth. algorithm. + + /* WEP */ + u32 dot11PrivacyKeyIndex; // this is only valid for legendary wep, 0~3 for key id. (tx key index) + union Keytype dot11DefKey[4]; // this is only valid for def. key + u32 dot11DefKeylen[4]; + + u32 dot118021XGrpPrivacy; // This specify the privacy algthm. used for Grp key + u32 dot118021XGrpKeyid; // key id used for Grp Key ( tx key index) + union Keytype dot118021XGrpKey[4]; // 802.1x Group Key, for inx0 and inx1 + union Keytype dot118021XGrptxmickey[4]; + union Keytype dot118021XGrprxmickey[4]; + union pn48 dot11Grptxpn; // PN48 used for Grp Key xmit. + union pn48 dot11Grprxpn; // PN48 used for Grp Key recv. + +#ifdef CONFIG_AP_MODE + //extend security capabilities for AP_MODE + unsigned int dot8021xalg;//0:disable, 1:psk, 2:802.1x + unsigned int wpa_psk;//0:disable, bit(0): WPA, bit(1):WPA2 + unsigned int wpa_group_cipher; + unsigned int wpa2_group_cipher; + unsigned int wpa_pairwise_cipher; + unsigned int wpa2_pairwise_cipher; +#endif + +#ifdef CONFIG_WPS + u8 wps_ie[MAX_WPS_IE_LEN];//added in assoc req + int wps_ie_len; +#endif + + u8 binstallGrpkey; + u8 busetkipkey; + //_timer tkip_timer; + u8 bcheck_grpkey; + u8 bgrpkey_handshake; + + //u8 packet_cnt;//unused, removed + + s32 sw_encrypt;//from registry_priv + s32 sw_decrypt;//from registry_priv + + s32 hw_decrypted;//if the rx packets is hw_decrypted==_FALSE, it means the hw has not been ready. + + + //keeps the auth_type & enc_status from upper layer ioctl(wpa_supplicant or wzc) + u32 ndisauthtype; // NDIS_802_11_AUTHENTICATION_MODE + u32 ndisencryptstatus; // NDIS_802_11_ENCRYPTION_STATUS + + //WLAN_BSSID_EX sec_bss; //for joinbss (h2c buffer) usage //YJ,del,140410 + + NDIS_802_11_WEP ndiswep; +#ifdef PLATFORM_WINDOWS + u8 KeyMaterial[16];// variable length depending on above field. +#endif + +//TODO +#if 0 //Remove unused wpa2 data - Alex Fang + u8 assoc_info[600]; + u8 szofcapability[256]; //for wpa2 usage + u8 oidassociation[512]; //for wpa/wpa2 usage + u8 authenticator_ie[256]; //store ap security information element +#endif + u8 supplicant_ie[256]; //store sta security information element + + + //for tkip countermeasure + u32 last_mic_err_time; + u8 btkip_countermeasure; + u8 btkip_wait_report; + u32 btkip_countermeasure_time; +#ifdef CONFIG_WPA2_PREAUTH + //--------------------------------------------------------------------------- + // For WPA2 Pre-Authentication. + //--------------------------------------------------------------------------- + //u8 RegEnablePreAuth; // Default value: Pre-Authentication enabled or not, from registry "EnablePreAuth". Added by Annie, 2005-11-01. + //u8 EnablePreAuthentication; // Current Value: Pre-Authentication enabled or not. + RT_PMKID_LIST PMKIDList[NUM_PMKID_CACHE]; // Renamed from PreAuthKey[NUM_PRE_AUTH_KEY]. Annie, 2006-10-13. + u8 PMKIDIndex; + //u32 PMKIDCount; // Added by Annie, 2006-10-13. + //u8 szCapability[256]; // For WPA2-PSK using zero-config, by Annie, 2005-09-20. +#endif + +#ifdef CONFIG_INCLUDE_WPA_PSK + WPA_GLOBAL_INFO wpa_global_info; +#if defined(CONFIG_AP_MODE) && defined(CONFIG_MULTIPLE_WPA_STA) +// WPA_STA_INFO wpa_sta_info[AP_STA_NUM]; + u8 *palloc_wpastainfo_buf; + u32 alloc_wpastainfo_size; + WPA_STA_INFO *wpa_sta_info[NUM_STA-2]; +#else + WPA_STA_INFO wpa_sta_info; +#endif + u8 wpa_passphrase[IW_PASSPHRASE_MAX_SIZE + 1]; +#endif +#ifdef CONFIG_WPS + u8 wps_phase; +#endif +}; + +struct sha256_state { + u64 length; + u32 state[8], curlen; + u8 buf[64]; +}; + + +#define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst)\ +do{\ + switch(psecuritypriv->dot11AuthAlgrthm)\ + {\ + case dot11AuthAlgrthm_Open:\ + case dot11AuthAlgrthm_Shared:\ + case dot11AuthAlgrthm_Auto:\ + encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\ + break;\ + case dot11AuthAlgrthm_8021X:\ + if(bmcst)\ + encry_algo = (u8)psecuritypriv->dot118021XGrpPrivacy;\ + else\ + encry_algo =(u8) psta->dot118021XPrivacy;\ + break;\ + case dot11AuthAlgrthm_WAPI:\ + encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\ + break;\ + }\ +}while(0) + + +#define SET_ICE_IV_LEN( iv_len, icv_len, encrypt)\ +do{\ + switch(encrypt)\ + {\ + case _WEP40_:\ + case _WEP104_:\ + iv_len = 4;\ + icv_len = 4;\ + break;\ + case _TKIP_:\ + iv_len = 8;\ + icv_len = 4;\ + break;\ + case _AES_:\ + iv_len = 8;\ + icv_len = 8;\ + break;\ + case _SMS4_:\ + iv_len = 18;\ + icv_len = 16;\ + break;\ + default:\ + iv_len = 0;\ + icv_len = 0;\ + break;\ + }\ +}while(0) + + +#define GET_TKIP_PN(iv,dot11txpn)\ +do{\ + dot11txpn._byte_.TSC0=iv[2];\ + dot11txpn._byte_.TSC1=iv[0];\ + dot11txpn._byte_.TSC2=iv[4];\ + dot11txpn._byte_.TSC3=iv[5];\ + dot11txpn._byte_.TSC4=iv[6];\ + dot11txpn._byte_.TSC5=iv[7];\ +}while(0) + + +#define ROL32( A, n ) ( ((A) << (n)) | ( ((A)>>(32-(n))) & ( (1UL << (n)) - 1 ) ) ) +#define ROR32( A, n ) ROL32( (A), 32-(n) ) + +extern const u32 Te0[256]; +extern const u32 Te1[256]; +extern const u32 Te2[256]; +extern const u32 Te3[256]; +extern const u32 Te4[256]; +extern const u32 Td0[256]; +extern const u32 Td1[256]; +extern const u32 Td2[256]; +extern const u32 Td3[256]; +extern const u32 Td4[256]; +extern const u32 rcon[10]; +extern const u8 Td4s[256]; +extern const u8 rcons[10]; + +#define RCON(i) (rcons[(i)] << 24) + +static inline u32 rotr(u32 val, int bits) +{ + return (val >> bits) | (val << (32 - bits)); +} + +#define TE0(i) Te0[((i) >> 24) & 0xff] +#define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8) +#define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16) +#define TE3(i) rotr(Te0[(i) & 0xff], 24) +#define TE41(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000) +#define TE42(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000) +#define TE43(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00) +#define TE44(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff) +#define TE421(i) ((Te0[((i) >> 16) & 0xff] << 8) & 0xff000000) +#define TE432(i) (Te0[((i) >> 8) & 0xff] & 0x00ff0000) +#define TE443(i) (Te0[(i) & 0xff] & 0x0000ff00) +#define TE414(i) ((Te0[((i) >> 24) & 0xff] >> 8) & 0x000000ff) +#define TE4(i) ((Te0[(i)] >> 8) & 0x000000ff) + +#define TD0(i) Td0[((i) >> 24) & 0xff] +#define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8) +#define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16) +#define TD3(i) rotr(Td0[(i) & 0xff], 24) +#define TD41(i) (Td4s[((i) >> 24) & 0xff] << 24) +#define TD42(i) (Td4s[((i) >> 16) & 0xff] << 16) +#define TD43(i) (Td4s[((i) >> 8) & 0xff] << 8) +#define TD44(i) (Td4s[(i) & 0xff]) +#define TD0_(i) Td0[(i) & 0xff] +#define TD1_(i) rotr(Td0[(i) & 0xff], 8) +#define TD2_(i) rotr(Td0[(i) & 0xff], 16) +#define TD3_(i) rotr(Td0[(i) & 0xff], 24) + +#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \ + ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3])) + +#define PUTU32(ct, st) { \ +(ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \ +(ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); } + +#define WPA_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \ + (((u32) (a)[2]) << 8) | ((u32) (a)[3])) + +#define WPA_PUT_LE16(a, val) \ + do { \ + (a)[1] = ((u16) (val)) >> 8; \ + (a)[0] = ((u16) (val)) & 0xff; \ + } while (0) + +#define WPA_PUT_BE32(a, val) \ + do { \ + (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[3] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define WPA_PUT_BE64(a, val) \ + do { \ + (a)[0] = (u8) (((u64) (val)) >> 56); \ + (a)[1] = (u8) (((u64) (val)) >> 48); \ + (a)[2] = (u8) (((u64) (val)) >> 40); \ + (a)[3] = (u8) (((u64) (val)) >> 32); \ + (a)[4] = (u8) (((u64) (val)) >> 24); \ + (a)[5] = (u8) (((u64) (val)) >> 16); \ + (a)[6] = (u8) (((u64) (val)) >> 8); \ + (a)[7] = (u8) (((u64) (val)) & 0xff); \ + } while (0) + +/* ===== start - public domain SHA256 implementation ===== */ + +/* This is based on SHA256 implementation in LibTomCrypt that was released into + * public domain by Tom St Denis. */ + +/* the K array */ +static const unsigned long K[64] = { + 0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL, + 0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL, + 0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL, + 0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL, + 0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL, + 0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL, + 0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL, + 0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL, + 0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL, + 0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL, + 0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL, + 0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL, + 0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL +}; + + +/* Various logical functions */ +#define RORc(x, y) \ +( ((((unsigned long) (x) & 0xFFFFFFFFUL) >> (unsigned long) ((y) & 31)) | \ + ((unsigned long) (x) << (unsigned long) (32 - ((y) & 31)))) & 0xFFFFFFFFUL) +#define Ch(x,y,z) (z ^ (x & (y ^ z))) +#define Maj(x,y,z) (((x | y) & z) | (x & y)) +#define S(x, n) RORc((x), (n)) +#define R(x, n) (((x)&0xFFFFFFFFUL)>>(n)) +#define Sigma0(x) (S(x, 2) ^ S(x, 13) ^ S(x, 22)) +#define Sigma1(x) (S(x, 6) ^ S(x, 11) ^ S(x, 25)) +#define Gamma0(x) (S(x, 7) ^ S(x, 18) ^ R(x, 3)) +#define Gamma1(x) (S(x, 17) ^ S(x, 19) ^ R(x, 10)) +#ifndef MIN +#define MIN(x, y) (((x) < (y)) ? (x) : (y)) +#endif + +u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe); +u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe); +void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe); + +u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe); +u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe); +void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe); + +#ifdef CONFIG_TDLS +void wpa_tdls_generate_tpk(_adapter *padapter, struct sta_info *psta); +int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq, + u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie, + u8 *mic); +int tdls_verify_mic(u8 *kck, u8 trans_seq, + u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie); +#endif //CONFIG_TDLS + +#ifdef PLATFORM_WINDOWS +void rtw_use_tkipkey_handler ( + IN PVOID SystemSpecific1, + IN PVOID FunctionContext, + IN PVOID SystemSpecific2, + IN PVOID SystemSpecific3 + ); +#endif +#ifdef PLATFORM_LINUX +void rtw_use_tkipkey_handler(void* FunctionContext); +#endif + +#ifdef PLATFORM_FREEBSD +void rtw_use_tkipkey_handler(void* FunctionContext); +#endif //PLATFORM_FREEBSD + +u32 rtw_init_sec_priv(_adapter *padapter); +void rtw_free_sec_priv(struct security_priv *psecpriv); + +#endif //__RTL871X_SECURITY_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_xmit.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_xmit.h new file mode 100644 index 0000000..46e3379 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/rtw_xmit.h @@ -0,0 +1,839 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_XMIT_H_ +#define _RTW_XMIT_H_ + +/*--------------------------------------- + Define MAX_XMITBUF_SZ +---------------------------------------*/ +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_LX_HCI) + +#ifdef CONFIG_TX_AGGREGATION //effect only for SDIO and GSPI Interface +#define MAX_XMITBUF_SZ (20480) // 20k +#else +#if defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) + + #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + #define HAL_INTERFACE_OVERHEAD_XMIT_BUF 12 //HAL_INTERFACE_CMD (4) + HAL_INTERFACE_STATUS (8) + #elif defined(CONFIG_LX_HCI) + #define HAL_INTERFACE_OVERHEAD_XMIT_BUF 0 + #endif + +// Consideration for MAX_XMITBUF_SZ size +// Check more detail information in MAX_SKB_BUF_SIZE +// Tx: [INTF_CMD][TX_DESC][WLAN_HDR][QoS][IV][SNAP][Data][MIC][ICV][INTF_STATUS] +// HAL_INTERFACE_OVERHEAD: HAL_INTERFACE_CMD is 4/0 for SPI/PCIE, HAL_INTERFACE_STATUS is 8/0 for SPI/PCIE +// WLAN_MAX_ETHFRM_LEN : May not be required because WLAN_HEADER +SNAP can totally +// cover ethernet header.Keep in only for safety. + +#ifndef CONFIG_DONT_CARE_TP +#define MAX_XMITBUF_SZ (HAL_INTERFACE_OVERHEAD_XMIT_BUF+\ + TXDESC_SIZE+\ + WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN +\ + SKB_RESERVED_FOR_SAFETY) +#else +#define MAX_XMITBUF_SZ (HAL_INTERFACE_OVERHEAD_XMIT_BUF+\ + TXDESC_SIZE+\ + WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_TX_ETHFRM_LEN +\ + SKB_RESERVED_FOR_SAFETY) +#endif + + +#else // Other OS +#define MAX_XMITBUF_SZ (12288) //12k 1536*8 +#endif //#ifdef PLATFORM_ECOS || defined(PLATFORM_FREERTOS) +#endif //#ifdef CONFIG_TX_AGGREGATION + +#elif defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) + #errof "Undefined bus interface for MAX_XMITBUF_SZ" +#endif //interface define. SDIO/GSPI/LXbus/PCI/USB + + + +/*--------------------------------------------------------------*/ +/* Define MAX_XMITBUF_SZ */ +/*--------------------------------------------------------------*/ +#if (defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI) + +#if defined(PLATFORM_ECOS) +#define NR_XMITBUFF (8) +#elif defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) +#ifndef CONFIG_HIGH_TP +#define NR_XMITBUFF (2) //Decrease recv frame (8->2) due to memory limitation - YangJue +#else +#define NR_XMITBUFF (128) +#endif +#else +#define NR_XMITBUFF (128) +#endif //#ifdef PLATFORM_ECOS + +#elif defined(CONFIG_LX_HCI) +#define NR_XMITBUFF (8) + +#elif defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) + #errof "Undefined bus interface for MAX_XMITBUF_SZ" +#endif //interface define + + +/*--------------------------------------------------------------*/ +/* Define XMITBUF_ALIGN_SZ */ +/*--------------------------------------------------------------*/ +#if defined(PLATFORM_OS_CE) || defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined(PLATFORM_CMSIS_RTOS) +#define XMITBUF_ALIGN_SZ 4 +#else +#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI) +#define XMITBUF_ALIGN_SZ 4 +#else +#define XMITBUF_ALIGN_SZ 512 +#endif +#endif + +#define MAX_CMDBUF_SZ (5120) //(4096) +/*--------------------------------------------------------------*/ +/* Define xmit extension buff, size/numbers */ +/*--------------------------------------------------------------*/ +#define MAX_XMIT_EXTBUF_SZ (1536) + +#if defined(PLATFORM_ECOS) +#define NR_XMIT_EXTBUFF (16) //Decrease ext xmit buffer due to memory limitation - Alex Fang +#elif defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) +#define NR_XMIT_EXTBUFF (8) //Decrease ext xmit buffer due to memory limitation - Alex Fang +#else +#define NR_XMIT_EXTBUFF (32) +#endif //#ifdef PLATFORM_ECOS + +#define MAX_NUMBLKS (1) + +#define XMIT_VO_QUEUE (0) +#define XMIT_VI_QUEUE (1) +#define XMIT_BE_QUEUE (2) +#define XMIT_BK_QUEUE (3) + +#define VO_QUEUE_INX 0 +#define VI_QUEUE_INX 1 +#define BE_QUEUE_INX 2 +#define BK_QUEUE_INX 3 +#define BCN_QUEUE_INX 4 +#define MGT_QUEUE_INX 5 +#define HIGH_QUEUE_INX 6 +#define TXCMD_QUEUE_INX 7 +#ifdef CONFIG_WLAN_HAL_TEST +#define HIGH1_QUEUE_INX 8 +#define HIGH2_QUEUE_INX 9 +#define HIGH3_QUEUE_INX 10 +#define HIGH4_QUEUE_INX 11 +#define HIGH5_QUEUE_INX 12 +#define HIGH6_QUEUE_INX 13 +#define HIGH7_QUEUE_INX 14 +#define HW_QUEUE_ENTRY 15 +#else +#define HW_QUEUE_ENTRY 8 +#endif + +#define WEP_IV(pattrib_iv, dot11txpn, keyidx)\ +do{\ + pattrib_iv[0] = dot11txpn._byte_.TSC0;\ + pattrib_iv[1] = dot11txpn._byte_.TSC1;\ + pattrib_iv[2] = dot11txpn._byte_.TSC2;\ + pattrib_iv[3] = ((keyidx & 0x3)<<6);\ + dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0: (dot11txpn.val+1);\ +}while(0) + + +#define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\ +do{\ + pattrib_iv[0] = dot11txpn._byte_.TSC1;\ + pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\ + pattrib_iv[2] = dot11txpn._byte_.TSC0;\ + pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ + pattrib_iv[4] = dot11txpn._byte_.TSC2;\ + pattrib_iv[5] = dot11txpn._byte_.TSC3;\ + pattrib_iv[6] = dot11txpn._byte_.TSC4;\ + pattrib_iv[7] = dot11txpn._byte_.TSC5;\ + dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0: (dot11txpn.val+1);\ +}while(0) + +#define AES_IV(pattrib_iv, dot11txpn, keyidx)\ +do{\ + pattrib_iv[0] = dot11txpn._byte_.TSC0;\ + pattrib_iv[1] = dot11txpn._byte_.TSC1;\ + pattrib_iv[2] = 0;\ + pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ + pattrib_iv[4] = dot11txpn._byte_.TSC2;\ + pattrib_iv[5] = dot11txpn._byte_.TSC3;\ + pattrib_iv[6] = dot11txpn._byte_.TSC4;\ + pattrib_iv[7] = dot11txpn._byte_.TSC5;\ + dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0: (dot11txpn.val+1);\ +}while(0) + + +#define HWXMIT_ENTRY 4 + +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)|| defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B) ||defined(CONFIG_RTL8188F) +#define TXDESC_SIZE 40 +#else +#define TXDESC_SIZE 32 +#endif + +#ifdef CONFIG_TX_EARLY_MODE +#define EARLY_MODE_INFO_SIZE 8 +#endif + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) +#define TXDESC_OFFSET TXDESC_SIZE + +#endif + +#ifdef CONFIG_USB_HCI +#define PACKET_OFFSET_SZ (8) +#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ) +#endif + +#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI) +#if defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B)// buffer descriptor architecture +#define TXDESC_OFFSET TXDESC_SIZE +#else +#define TXDESC_OFFSET 0 +#endif +#define TX_DESC_NEXT_DESC_OFFSET 40 +#endif + +#define TX_FRAGMENTATION_THRESHOLD 2346 + +// Suppose (TX_DESC_MODE=1) ==> Segment number for each tx_buf_desc is 4. 2X4 = 8 (double words). +struct tx_buf_desc { + unsigned int txdw0; + unsigned int txdw1; + unsigned int txdw2; + unsigned int txdw3; + unsigned int txdw4; + unsigned int txdw5; + unsigned int txdw6; + unsigned int txdw7; +}; + +struct tx_desc{ + + //DWORD 0 + unsigned int txdw0; + + unsigned int txdw1; + + unsigned int txdw2; + + unsigned int txdw3; + + unsigned int txdw4; + + unsigned int txdw5; + + unsigned int txdw6; + + unsigned int txdw7; +#ifdef CONFIG_PCI_HCI + unsigned int txdw8; + + unsigned int txdw9; + + unsigned int txdw10; + + unsigned int txdw11; + + // 2008/05/15 MH Because PCIE HW memory R/W 4K limit. And now, our descriptor + // size is 40 bytes. If you use more than 102 descriptor( 103*40>4096), HW will execute + // memoryR/W CRC error. And then all DMA fetch will fail. We must decrease descriptor + // number or enlarge descriptor size as 64 bytes. + unsigned int txdw12; + + unsigned int txdw13; + + unsigned int txdw14; + + unsigned int txdw15; +#endif +#if defined(CONFIG_LX_HCI)||defined(CONFIG_RTL8188F) + unsigned int txdw8; + + unsigned int txdw9; +#endif +}; + + +union txdesc { + struct tx_desc txdesc; + unsigned int value[TXDESC_SIZE>>2]; +}; + +#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI) +#ifdef CONFIG_WLAN_HAL_TEST +#define PCI_MAX_TX_QUEUE_COUNT HW_QUEUE_ENTRY +#else +#define PCI_MAX_TX_QUEUE_COUNT 8 +#endif + +struct rtw_tx_ring { + +#if ((RTL8195A_SUPPORT ==1) ||(RTL8711B_SUPPORT == 1)) + struct tx_buf_desc *desc; +#else + struct tx_desc *desc; +#endif + dma_addr_t dma; + unsigned int idx; + unsigned int entries; + _queue queue; + u32 qlen; +}; +#endif + +struct hw_xmit { + //_lock xmit_lock; + //_list pending; + _queue *sta_queue; + //struct hw_txqueue *phwtxqueue; + //sint txcmdcnt; + int accnt; +}; + +#if 0 +struct pkt_attrib +{ + u8 type; + u8 subtype; + u8 bswenc; + u8 dhcp_pkt; + u16 ether_type; + int pktlen; //the original 802.3 pkt raw_data len (not include ether_hdr data) + int pkt_hdrlen; //the original 802.3 pkt header len + int hdrlen; //the WLAN Header Len + int nr_frags; + int last_txcmdsz; + int encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith + u8 iv[8]; + int iv_len; + u8 icv[8]; + int icv_len; + int priority; + int ack_policy; + int mac_id; + int vcs_mode; //virtual carrier sense method + + u8 dst[ETH_ALEN]; + u8 src[ETH_ALEN]; + u8 ta[ETH_ALEN]; + u8 ra[ETH_ALEN]; + + u8 key_idx; + + u8 qos_en; + u8 ht_en; + u8 raid;//rate adpative id + u8 bwmode; + u8 ch_offset;//PRIME_CHNL_OFFSET + u8 sgi;//short GI + u8 ampdu_en;//tx ampdu enable + u8 mdata;//more data bit + u8 eosp; + + u8 pctrl;//per packet txdesc control enable + u8 triggered;//for ap mode handling Power Saving sta + + u32 qsel; + u16 seqnum; + + struct sta_info * psta; +#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX + u8 hw_tcp_csum; +#endif +}; +#else +//reduce size +struct pkt_attrib +{ + u8 type; + u8 subtype; + u8 bswenc; + u8 dhcp_pkt; + u16 ether_type; + u16 seqnum; + u16 pkt_hdrlen; //the original 802.3 pkt header len + u16 hdrlen; //the WLAN Header Len + u32 pktlen; //the original 802.3 pkt raw_data len (not include ether_hdr data) + u32 last_txcmdsz; + u8 encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith + u8 iv_len; + u8 icv_len; + u8 iv[18]; + u8 icv[16]; + u8 priority; + u8 ack_policy; + u8 mac_id; + u8 vcs_mode; //virtual carrier sense method + u8 dst[ETH_ALEN]; + u8 src[ETH_ALEN]; + u8 ta[ETH_ALEN]; + u8 ra[ETH_ALEN]; + u8 key_idx; + u8 qos_en; + u8 ht_en; + u8 raid;//rate adpative id + u8 bwmode; + u8 ch_offset;//PRIME_CHNL_OFFSET + u8 sgi;//short GI + u8 ampdu_en;//tx ampdu enable + u8 mdata;//more data bit + u8 pctrl;//per packet txdesc control enable + u8 triggered;//for ap mode handling Power Saving sta + u8 qsel; + u8 eosp; + u8 rate; + u8 intel_proxim; + u8 retry_ctrl; + struct sta_info * psta; +#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX + u8 hw_tcp_csum; +#endif +}; +#endif + +#ifdef PLATFORM_FREEBSD +#define ETH_ALEN 6 /* Octets in one ethernet addr */ +#define ETH_HLEN 14 /* Total octets in header. */ +#define ETH_P_IP 0x0800 /* Internet Protocol packet */ + +/*struct rtw_ieee80211_hdr { + uint16_t frame_control; + uint16_t duration_id; + u8 addr1[6]; + u8 addr2[6]; + u8 addr3[6]; + uint16_t seq_ctrl; + u8 addr4[6]; +} ;*/ +#endif //PLATFORM_FREEBSD + +#define WLANHDR_OFFSET 64 + +#define NULL_FRAMETAG (0x0) +#define DATA_FRAMETAG 0x01 +#define L2_FRAMETAG 0x02 +#define MGNT_FRAMETAG 0x03 +#define AMSDU_FRAMETAG 0x04 + +#define EII_FRAMETAG 0x05 +#define IEEE8023_FRAMETAG 0x06 + +#define MP_FRAMETAG 0x07 + +#define TXAGG_FRAMETAG 0x08 + +enum { + XMITBUF_DATA = 0, + XMITBUF_MGNT = 1, + XMITBUF_CMD = 2, +}; + +struct submit_ctx{ + u32 submit_time; /* */ + u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */ + int status; /* status for operation */ +#ifdef PLATFORM_LINUX + struct completion done; +#endif +}; + +enum { + RTW_SCTX_DONE_SUCCESS = 0, + RTW_SCTX_DONE_UNKNOWN, + RTW_SCTX_DONE_BUF_ALLOC, + RTW_SCTX_DONE_BUF_FREE, + RTW_SCTX_DONE_WRITE_PORT_ERR, + RTW_SCTX_DONE_TX_DESC_NA, + RTW_SCTX_DONE_TX_DENY, +}; + + +void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms); +int rtw_sctx_wait(struct submit_ctx *sctx); +void rtw_sctx_done_err(struct submit_ctx **sctx, int status); +void rtw_sctx_done(struct submit_ctx **sctx); + +typedef struct _XIMT_BUF_ { + u32 AllocatBufAddr; + u32 BufAddr; + u32 BufLen; +}XIMT_BUF, *PXIMT_BUF; + +struct xmit_buf +{ + _list list; + + _adapter *padapter; + +#if USE_SKB_AS_XMITBUF + _pkt *pkt; +#else + u8 *pallocated_buf; +#endif + u8 *pbuf; + + void *priv_data; + + u16 buf_tag; // 0: Normal xmitbuf, 1: extension xmitbuf, 2:cmd xmitbuf + u16 flags; + u32 alloc_sz; + + u32 len; + + struct submit_ctx *sctx; + +#ifdef CONFIG_USB_HCI + + //u32 sz[8]; + u32 ff_hwaddr; + +#if defined(PLATFORM_OS_XP)||defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) + PURB pxmit_urb[8]; + dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */ +#endif + +#ifdef PLATFORM_OS_XP + PIRP pxmit_irp[8]; +#endif + +#ifdef PLATFORM_OS_CE + USB_TRANSFER usb_transfer_write_port; +#endif + + u8 bpending[8]; + + sint last[8]; + +#endif + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + u8 *phead; + u8 *pdata; + u8 *ptail; + u8 *pend; + u32 ff_hwaddr; + u8 pg_num; + u8 agg_num; +#ifdef PLATFORM_OS_XP + PMDL pxmitbuf_mdl; + PIRP pxmitbuf_irp; + PSDBUS_REQUEST_PACKET pxmitbuf_sdrp; +#endif +#endif + +#if defined(DBG_XMIT_BUF )|| defined(DBG_XMIT_BUF_EXT) + u8 no; +#endif + +#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI) +#if ((RTL8195A_SUPPORT ==1) ||(RTL8711B_SUPPORT == 1)) + XIMT_BUF BufInfo[4]; + u32 BlockNum; +#endif +#endif +}; + + +struct xmit_frame +{ + _list list; + + struct pkt_attrib attrib; + + _pkt *pkt; + + int frame_tag; + + _adapter *padapter; + + u8 *buf_addr; + + struct xmit_buf *pxmitbuf; + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + u8 pg_num; + u8 agg_num; +#endif + +#ifdef CONFIG_USB_HCI +#ifdef CONFIG_USB_TX_AGGREGATION + u8 agg_num; +#endif + s8 pkt_offset; +#ifdef CONFIG_RTL8192D + u8 EMPktNum; + u16 EMPktLen[5];//The max value by HW +#endif +#endif + +#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI) +#if ((RTL8195A_SUPPORT ==1) ||(RTL8711B_SUPPORT == 1)) + u32 TxDexAddr; + u32 HdrLen; + u32 PayLoadAddr; + u32 PayLoadLen; + u32 TotalLen; + u32 BlockNum; + XIMT_BUF BufInfo[4]; + BOOLEAN NoCoalesce; +#endif +#endif +}; + +struct tx_servq { + _list tx_pending; + _queue sta_pending; + int qcnt; +}; + +struct sta_xmit_priv +{ + _lock lock; + sint option; + sint apsd_setting; //When bit mask is on, the associated edca queue supports APSD. + + + //struct tx_servq blk_q[MAX_NUMBLKS]; + struct tx_servq be_q; //priority == 0,3 + struct tx_servq bk_q; //priority == 1,2 + struct tx_servq vi_q; //priority == 4,5 + struct tx_servq vo_q; //priority == 6,7 + _list legacy_dz; + _list apsd; + + u16 txseq_tid[16]; + + //uint sta_tx_bytes; + //u64 sta_tx_pkts; + //uint sta_tx_fail; + + +}; + + +struct hw_txqueue { + volatile sint head; + volatile sint tail; + volatile sint free_sz; //in units of 64 bytes + volatile sint free_cmdsz; + volatile sint txsz[8]; + uint ff_hwaddr; + uint cmd_hwaddr; + sint ac_tag; +}; + +struct agg_pkt_info{ + u16 offset; + u16 pkt_len; +}; + + +struct xmit_priv { + + _lock lock; + + //_queue blk_strms[MAX_NUMBLKS]; + _queue be_pending; + _queue bk_pending; + _queue vi_pending; + _queue vo_pending; + _queue bm_pending; + + //_queue legacy_dz_queue; + //_queue apsd_queue; + + u8 *pallocated_frame_buf; + u8 *pxmit_frame_buf; + uint free_xmitframe_cnt; + + //uint mapping_addr; + //uint pkt_sz; + + _queue free_xmit_queue; + + //struct hw_txqueue be_txqueue; + //struct hw_txqueue bk_txqueue; + //struct hw_txqueue vi_txqueue; + //struct hw_txqueue vo_txqueue; + //struct hw_txqueue bmc_txqueue; + + _adapter *adapter; + + u8 vcs_setting; + u8 vcs; + u8 vcs_type; + //u16 rts_thresh; + + u64 tx_bytes; + u64 tx_pkts; + u64 tx_drop; + u64 last_tx_bytes; + u64 last_tx_pkts; + + struct hw_xmit *hwxmits; + u8 hwxmit_entry; + +#ifdef CONFIG_USB_HCI + _sema tx_retevt;//all tx return event; + u8 txirp_cnt;// + +#ifdef PLATFORM_OS_CE + USB_TRANSFER usb_transfer_write_port; +// USB_TRANSFER usb_transfer_write_mem; +#endif +#ifdef PLATFORM_LINUX + struct tasklet_struct xmit_tasklet; +#endif +#ifdef PLATFORM_FREEBSD + struct task xmit_tasklet; +#endif + //per AC pending irp + int beq_cnt; + int bkq_cnt; + int viq_cnt; + int voq_cnt; + +#endif + +#if defined(CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI) + // Tx + struct rtw_tx_ring tx_ring[PCI_MAX_TX_QUEUE_COUNT]; + int txringcount[PCI_MAX_TX_QUEUE_COUNT]; + u8 beaconDMAing; //flag of indicating beacon is transmiting to HW by DMA +#ifdef PLATFORM_LINUX + struct tasklet_struct xmit_tasklet; +#endif +#endif + + _queue free_xmitbuf_queue; + _queue pending_xmitbuf_queue; + u8 *pallocated_xmitbuf; + u8 *pxmitbuf; + uint free_xmitbuf_cnt; +#if USE_XMIT_EXTBUFF + _queue free_xmit_extbuf_queue; + u8 *pallocated_xmit_extbuf; + u8 *pxmit_extbuf; + uint free_xmit_extbuf_cnt; +#endif + u16 nqos_ssn; + #ifdef CONFIG_TX_EARLY_MODE + + #define MAX_AGG_PKT_NUM 256 //Max tx ampdu coounts + + struct agg_pkt_info agg_pkt[MAX_AGG_PKT_NUM]; + #endif +}; + +#ifdef CONFIG_TRACE_SKB +extern struct xmit_buf *_rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv, u32 size); + +//extern struct xmit_frame *_rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv); +//extern s32 _rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe); +//extern void _rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue); + +#define rtw_alloc_xmitbuf_ext(pxmitpriv, pxmitbuf, size) \ + (\ + pxmitbuf = _rtw_alloc_xmitbuf_ext(pxmitpriv, size),\ + pxmitbuf ? set_skb_list_flag(pxmitbuf->pkt, SKBLIST_XMITEXTBUF):0,\ + pxmitbuf\ + ) +#else +extern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv, u32 size); +#endif +extern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); + +extern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv); +extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); + +extern struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv); +extern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe); +extern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue); +struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac); +extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); +extern struct xmit_frame* rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry); + +void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz); +extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len); +extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib); +extern s32 rtw_put_snap(u8 *data, u16 h_proto); + +extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe); +extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib); +#define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib) +extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); +#ifdef CONFIG_TDLS +s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, u8 action); +#endif +s32 _rtw_init_hw_txqueue(struct hw_txqueue* phw_txqueue, u8 ac_tag); +void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv); + + +s32 rtw_txframes_pending(_adapter *padapter); +s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib); +void rtw_txframes_update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitframe); +void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry); + + +s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter); +void _rtw_free_xmit_priv (struct xmit_priv *pxmitpriv); + + +void rtw_alloc_hwxmits(_adapter *padapter); +void rtw_free_hwxmits(_adapter *padapter); + + +s32 rtw_xmit(_adapter *padapter, _pkt **pkt); + +#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) +sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe); +void stop_sta_xmit(_adapter *padapter, struct sta_info *psta); +void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta); +void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta); +#endif + +u8 qos_acm(u8 acm_mask, u8 priority); + +s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe); +s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe); + +#ifdef CONFIG_XMIT_THREAD_MODE +void enqueue_pending_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); +struct xmit_buf* dequeue_pending_xmitbuf(struct xmit_priv *pxmitpriv); +struct xmit_buf* dequeue_pending_xmitbuf_under_survey(struct xmit_priv *pxmitpriv); +sint check_pending_xmitbuf(struct xmit_priv *pxmitpriv); +thread_return rtw_xmit_thread(thread_context context); +#endif + +u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe); + +extern s32 rtw_xmit_mgnt(_adapter * padapter, struct xmit_frame *pmgntframe); +extern s32 rtw_xmit_data(PADAPTER padapter, struct xmit_frame *pxmitframe); +extern s32 rtw_xmit_xmitbuf(_adapter * padapter, struct xmit_buf *pxmitbuf); +extern u32 ffaddr2deviceId(struct dvobj_priv *pdvobj, u32 addr); +extern unsigned int nr_xmitframe; +extern unsigned int nr_xmitbuff; +#endif //_RTL871X_XMIT_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/sta_info.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/sta_info.h new file mode 100644 index 0000000..3ea91a5 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/sta_info.h @@ -0,0 +1,400 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __STA_INFO_H_ +#define __STA_INFO_H_ + +#define IBSS_START_MAC_ID 2 + +#if 0 //move to wifi.h +#if defined(PLATFORM_ECOS) +#define NUM_STA 10 //Decrease STA due to memory limitation - Alex Fang +#elif defined(PLATFORM_FREERTOS) +//Decrease STA due to memory limitation - Alex Fang +#ifdef CONFIG_AP_MODE +#define NUM_STA (2 + AP_STA_NUM) //2 + supported clients +#else +#define NUM_STA 2 //Client mode sta for AP and broadcast +#endif +#else +#define NUM_STA 32 +#endif +#endif + +#define NUM_ACL 16 + +//if mode ==0, then the sta is allowed once the addr is hit. +//if mode ==1, then the sta is rejected once the addr is non-hit. +struct rtw_wlan_acl_node { + _list list; + u8 addr[ETH_ALEN]; + u8 valid; +}; + +//mode=0, disable +//mode=1, accept unless in deny list +//mode=2, deny unless in accept list +struct wlan_acl_pool { + int mode; + int num; + struct rtw_wlan_acl_node aclnode[NUM_ACL]; + _queue acl_node_q; +}; + +typedef struct _RSSI_STA{ + s32 UndecoratedSmoothedPWDB; + s32 UndecoratedSmoothedCCK; + s32 UndecoratedSmoothedOFDM; + u64 PacketMap; + u8 ValidBit; + u32 OFDM_pkt; +}RSSI_STA, *PRSSI_STA; + +struct stainfo_stats { + + //u64 rx_pkts; + u64 rx_mgnt_pkts; + u64 rx_ctrl_pkts; + u64 rx_data_pkts; + + //u64 last_rx_pkts; + u64 last_rx_mgnt_pkts; + u64 last_rx_ctrl_pkts; + u64 last_rx_data_pkts; + + u64 rx_bytes; +// u64 rx_drops; + + u64 tx_pkts; + u64 tx_bytes; +// u64 tx_drops; + +}; + +#ifdef CONFIG_TDLS +struct TDLS_PeerKey { + u8 kck[16]; /* TPK-KCK */ + u8 tk[16]; /* TPK-TK; only CCMP will be used */ +} ; +#endif //CONFIG_TDLS + +struct sta_info { + + _lock lock; + _list list; //free_sta_queue + _list hash_list; //sta_hash + //_list asoc_list; //20061114 + //_list sleep_list;//sleep_q + //_list wakeup_list;//wakeup_q + _adapter *padapter; + + struct sta_xmit_priv sta_xmitpriv; + struct sta_recv_priv sta_recvpriv; + + _queue sleep_q; + unsigned int sleepq_len; + + uint state; + uint aid; + uint mac_id; + uint qos_option; + u8 hwaddr[ETH_ALEN]; + + uint ieee8021x_blocked; //0: allowed, 1:blocked + uint dot118021XPrivacy; //aes, tkip... + union Keytype dot11tkiptxmickey; + union Keytype dot11tkiprxmickey; + union Keytype dot118021x_UncstKey; + union pn48 dot11txpn; // PN48 used for Unicast xmit. + union pn48 dot11rxpn; // PN48 used for Unicast recv. + + + u8 bssrateset[16]; + u32 bssratelen; + s32 rssi; + s32 signal_quality; + + u8 cts2self; + u8 rtsen; + + u8 raid; + u8 init_rate; + u32 ra_mask; + u8 wireless_mode; // NETWORK_TYPE + struct stainfo_stats sta_stats; + +#ifdef CONFIG_TDLS + u32 tdls_sta_state; + u8 dialog; + u8 SNonce[32]; + u8 ANonce[32]; + u32 TDLS_PeerKey_Lifetime; + u16 TPK_count; + _timer TPK_timer; + struct TDLS_PeerKey tpk; + u16 stat_code; + u8 off_ch; + u16 ch_switch_time; + u16 ch_switch_timeout; + u8 option; + _timer option_timer; + _timer base_ch_timer; + _timer off_ch_timer; + + _timer handshake_timer; + _timer alive_timer1; + _timer alive_timer2; + u8 timer_flag; + u8 alive_count; +#endif //CONFIG_TDLS + + //for A-MPDU TX, ADDBA timeout check + _timer addba_retry_timer; +#ifdef CONFIG_RECV_REORDERING_CTRL + //for A-MPDU Rx reordering buffer control + struct recv_reorder_ctrl recvreorder_ctrl[16]; +#endif + //for A-MPDU Tx + //unsigned char ampdu_txen_bitmap; + u16 BA_starting_seqctrl[16]; + + +#ifdef CONFIG_80211N_HT + struct ht_priv htpriv; +#endif + + //Notes: + //STA_Mode: + //curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO + //scan_q: AP CAP/INFO + + //AP_Mode: + //curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO + //sta_info: (AP & STA) CAP/INFO + +#ifdef CONFIG_AP_MODE + + _list asoc_list; + _list auth_list; + + unsigned int expire_to; +#ifdef CONFIG_AP_POLLING_CLIENT_ALIVE + unsigned int tx_null0; + unsigned int tx_null0_fail; + unsigned int tx_null0_retry; +#endif + unsigned int auth_seq; + unsigned int authalg; + unsigned char chg_txt[128]; + + u16 capability; + u32 flags; + + int dot8021xalg;//0:disable, 1:psk, 2:802.1x + int wpa_psk;//0:disable, bit(0): WPA, bit(1):WPA2 + int wpa_group_cipher; + int wpa2_group_cipher; + int wpa_pairwise_cipher; + int wpa2_pairwise_cipher; + + u8 bpairwise_key_installed; + +#ifdef CONFIG_NATIVEAP_MLME + u8 wpa_ie[32]; + + u8 nonerp_set; + u8 no_short_slot_time_set; + u8 no_short_preamble_set; + u8 no_ht_gf_set; + u8 no_ht_set; + u8 ht_20mhz_set; +#endif // CONFIG_NATIVEAP_MLME + + unsigned int tx_ra_bitmap; + u8 qos_info; + + u8 max_sp_len; + u8 uapsd_bk;//BIT(0): Delivery enabled, BIT(1): Trigger enabled + u8 uapsd_be; + u8 uapsd_vi; + u8 uapsd_vo; + + u8 has_legacy_ac; + unsigned int sleepq_ac_len; + +#ifdef CONFIG_P2P + //p2p priv data + u8 is_p2p_device; + u8 p2p_status_code; + + //p2p client info + u8 dev_addr[ETH_ALEN]; + //u8 iface_addr[ETH_ALEN];//= hwaddr[ETH_ALEN] + u8 dev_cap; + u16 config_methods; + u8 primary_dev_type[8]; + u8 num_of_secdev_type; + u8 secdev_types_list[32];// 32/8 == 4; + u16 dev_name_len; + u8 dev_name[32]; +#endif //CONFIG_P2P + +#ifdef CONFIG_TX_MCAST2UNI + u8 under_exist_checking; +#endif // CONFIG_TX_MCAST2UNI + +#endif // CONFIG_AP_MODE + +#ifdef CONFIG_IOCTL_CFG80211 + u8 *passoc_req; + u32 assoc_req_len; +#endif + + //for DM + RSSI_STA rssi_stat; + + // + // ================ODM Relative Info======================= + // Please be care, dont declare too much structure here. It will cost memory * STA support num. + // + // + // 2011/10/20 MH Add for ODM STA info. + // + // Driver Write + u8 bValid; // record the sta status link or not? + //u8 WirelessMode; // + u8 IOTPeer; // Enum value. HT_IOT_PEER_E + u8 rssi_level; //for Refresh RA mask + // ODM Write + //1 PHY_STATUS_INFO + u8 RSSI_Path[4]; // + u8 RSSI_Ave; + u8 RXEVM[4]; + u8 RXSNR[4]; + + // ODM Write + //1 TX_INFO (may changed by IC) + //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. + // + // ================ODM Relative Info======================= + // +}; + +#define sta_rx_pkts(sta) \ + (sta->sta_stats.rx_mgnt_pkts \ + + sta->sta_stats.rx_ctrl_pkts \ + + sta->sta_stats.rx_data_pkts) + +#define sta_last_rx_pkts(sta) \ + (sta->sta_stats.last_rx_mgnt_pkts \ + + sta->sta_stats.last_rx_ctrl_pkts \ + + sta->sta_stats.last_rx_data_pkts) + +#define sta_update_last_rx_pkts(sta) \ + do { \ + sta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \ + sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \ + sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \ + } while(0) + +#define STA_RX_PKTS_ARG(sta) \ + sta->sta_stats.rx_mgnt_pkts \ + , sta->sta_stats.rx_ctrl_pkts \ + , sta->sta_stats.rx_data_pkts + +#define STA_LAST_RX_PKTS_ARG(sta) \ + sta->sta_stats.last_rx_mgnt_pkts \ + , sta->sta_stats.last_rx_ctrl_pkts \ + , sta->sta_stats.last_rx_data_pkts + +#define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)" + +struct sta_priv { + + u8 *pallocated_stainfo_buf; + u32 allocated_stainfo_size; + u8 *pstainfo_buf; + _queue free_sta_queue; + + _lock sta_hash_lock; + _list sta_hash[NUM_STA]; + int asoc_sta_count; + _queue sleep_q; + _queue wakeup_q; + + _adapter *padapter; + + +#ifdef CONFIG_AP_MODE + _list asoc_list; + _list auth_list; + _lock asoc_list_lock; + _lock auth_list_lock; + + unsigned int auth_to; //sec, time to expire in authenticating. + unsigned int assoc_to; //sec, time to expire before associating. + unsigned int expire_to; //sec , time to expire after associated. + + /* pointers to STA info; based on allocated AID or NULL if AID free + * AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1 + * and so on + */ + struct sta_info *sta_aid[NUM_STA]; + + u16 sta_dz_bitmap;//only support 15 stations, staion aid bitmap for sleeping sta. + u16 tim_bitmap;//only support 15 stations, aid=0~15 mapping bit0~bit15 + + u16 max_num_sta; +//TODO: AP +// struct wlan_acl_pool acl_list; +#endif + +}; + + +__inline static u32 wifi_mac_hash(u8 *mac) +{ + u32 x; + + x = mac[0]; + x = (x << 2) ^ mac[1]; + x = (x << 2) ^ mac[2]; + x = (x << 2) ^ mac[3]; + x = (x << 2) ^ mac[4]; + x = (x << 2) ^ mac[5]; + + x ^= x >> 8; + x = x & (NUM_STA - 1); + + return x; +} + + +extern u32 _rtw_init_sta_priv(_adapter *padapter); +extern u32 _rtw_free_sta_priv(struct sta_priv *pstapriv); +extern struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr); +extern u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta); +extern void rtw_free_all_stainfo(_adapter *padapter); +extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr); +extern u32 rtw_init_bcmc_stainfo(_adapter* padapter); +extern struct sta_info* rtw_get_bcmc_stainfo(_adapter* padapter); +extern u8 rtw_access_ctrl(_adapter *padapter, u8 *mac_addr); + +#endif //_STA_INFO_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi.h new file mode 100644 index 0000000..1ab28fe --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi.h @@ -0,0 +1,1369 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _WIFI_H_ +#define _WIFI_H_ + +#include +#include + + +#ifdef BIT +//#error "BIT define occurred earlier elsewhere!\n" +#undef BIT +#endif +#define BIT(x) ((u32)1 << (x)) + +#if defined(PLATFORM_ECOS) +#define NUM_STA 10 //Decrease STA due to memory limitation - Alex Fang +#elif defined(PLATFORM_FREERTOS) || defined(PLATFORM_CMSIS_RTOS) +//Decrease STA due to memory limitation - Alex Fang +#ifdef CONFIG_AP_MODE +#define NUM_STA (2 + AP_STA_NUM) //2 + supported clients +#else +#define NUM_STA 2 //Client mode sta for AP and broadcast +#endif +#else +#define NUM_STA 32 +#endif + +#define WLAN_ETHHDR_LEN 14 +#define WLAN_ETHADDR_LEN 6 +#define WLAN_IEEE_OUI_LEN 3 +#define WLAN_ADDR_LEN 6 +#define WLAN_CRC_LEN 4 +#define WLAN_BSSID_LEN 6 +#define WLAN_BSS_TS_LEN 8 +#define WLAN_HDR_A3_LEN 24 +#define WLAN_HDR_A4_LEN 30 +#define WLAN_HDR_A3_QOS_LEN 26 +#define WLAN_HDR_A4_QOS_LEN 32 +#define WLAN_SSID_MAXLEN 32 +#define WLAN_DATA_MAXLEN 2312 + +#define WLAN_A3_PN_OFFSET 24 +#define WLAN_A4_PN_OFFSET 30 + +#define WLAN_MIN_ETHFRM_LEN 60 +#ifndef CONFIG_DONT_CARE_TP +#if WIFI_LOGO_CERTIFICATION +#define WLAN_MAX_ETHFRM_LEN 4000 +#else +#define WLAN_MAX_ETHFRM_LEN 1514 +#endif +#else +#define WLAN_MAX_RX_ETHFRM_LEN 1514 +#define WLAN_MAX_TX_ETHFRM_LEN 590 +#endif +#define WLAN_ETHHDR_LEN 14 +#define WLAN_SNAP_HEADER 8 +#define WLAN_MAX_IV_LEN 8 +#define WLAN_MAX_ICV_LEN 8 +#define WLAN_MAX_MIC_LEN 8 +#define WLAN_MAX_PROTOCOL_OVERHEAD (WLAN_HDR_A4_QOS_LEN+WLAN_MAX_IV_LEN\ + +WLAN_SNAP_HEADER+WLAN_MAX_MIC_LEN+WLAN_MAX_ICV_LEN) //=64 + +#define P80211CAPTURE_VERSION 0x80211001 + +// This value is tested by WiFi 11n Test Plan 5.2.3. +// This test verifies the WLAN NIC can update the NAV through sending the CTS with large duration. +#define WiFiNavUpperUs 30000 // 30 ms +// enum WLAN_IDX{ +// WLAN0_IDX = 0, +// WLAN1_IDX, +// WLAN_UNDEF = -1 +// }; + +#ifdef GREEN_HILL +#pragma pack(1) +#endif + +enum WIFI_FRAME_TYPE { + WIFI_MGT_TYPE = (0), + WIFI_CTRL_TYPE = (BIT(2)), + WIFI_DATA_TYPE = (BIT(3)), + WIFI_QOS_DATA_TYPE = (BIT(7)|BIT(3)), //!< QoS Data +}; + +enum WIFI_FRAME_SUBTYPE { + + // below is for mgt frame + WIFI_ASSOCREQ = (0 | WIFI_MGT_TYPE), + WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE), + WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE), + WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE), + WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE), + WIFI_PROBERSP = (BIT(6) | BIT(4) | WIFI_MGT_TYPE), + WIFI_BEACON = (BIT(7) | WIFI_MGT_TYPE), + WIFI_ATIM = (BIT(7) | BIT(4) | WIFI_MGT_TYPE), + WIFI_DISASSOC = (BIT(7) | BIT(5) | WIFI_MGT_TYPE), + WIFI_AUTH = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE), + WIFI_DEAUTH = (BIT(7) | BIT(6) | WIFI_MGT_TYPE), + WIFI_ACTION = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE), + + // below is for control frame + WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE), + WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), + WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE), + WIFI_ACK = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE), + WIFI_CFEND = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE), + WIFI_CFEND_CFACK = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), + + // below is for data frame + WIFI_DATA = (0 | WIFI_DATA_TYPE), + WIFI_DATA_CFACK = (BIT(4) | WIFI_DATA_TYPE), + WIFI_DATA_CFPOLL = (BIT(5) | WIFI_DATA_TYPE), + WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE), + WIFI_DATA_NULL = (BIT(6) | WIFI_DATA_TYPE), + WIFI_CF_ACK = (BIT(6) | BIT(4) | WIFI_DATA_TYPE), + WIFI_CF_POLL = (BIT(6) | BIT(5) | WIFI_DATA_TYPE), + WIFI_CF_ACKPOLL = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE), + WIFI_QOS_DATA_NULL = (BIT(6) | WIFI_QOS_DATA_TYPE), +}; + +enum WIFI_REASON_CODE { + _RSON_RESERVED_ = 0, + _RSON_UNSPECIFIED_ = 1, + _RSON_AUTH_NO_LONGER_VALID_ = 2, + _RSON_DEAUTH_STA_LEAVING_ = 3, + _RSON_INACTIVITY_ = 4, + _RSON_UNABLE_HANDLE_ = 5, + _RSON_CLS2_ = 6, + _RSON_CLS3_ = 7, + _RSON_DISAOC_STA_LEAVING_ = 8, + _RSON_ASOC_NOT_AUTH_ = 9, + + // WPA reason + _RSON_INVALID_IE_ = 13, + _RSON_MIC_FAILURE_ = 14, + _RSON_4WAY_HNDSHK_TIMEOUT_ = 15, + _RSON_GROUP_KEY_UPDATE_TIMEOUT_ = 16, + _RSON_DIFF_IE_ = 17, + _RSON_MLTCST_CIPHER_NOT_VALID_ = 18, + _RSON_UNICST_CIPHER_NOT_VALID_ = 19, + _RSON_AKMP_NOT_VALID_ = 20, + _RSON_UNSUPPORT_RSNE_VER_ = 21, + _RSON_INVALID_RSNE_CAP_ = 22, + _RSON_IEEE_802DOT1X_AUTH_FAIL_ = 23, + + //belowing are Realtek definition + _RSON_PMK_NOT_AVAILABLE_ = 24, + _RSON_TDLS_TEAR_TOOFAR_ = 25, + _RSON_TDLS_TEAR_UN_RSN_ = 26, +}; + +/* Reason codes (IEEE 802.11-2007, 7.3.1.7, Table 7-22) */ +#if 0 +#define WLAN_REASON_UNSPECIFIED 1 +#define WLAN_REASON_PREV_AUTH_NOT_VALID 2 +#define WLAN_REASON_DEAUTH_LEAVING 3 +#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4 +#define WLAN_REASON_DISASSOC_AP_BUSY 5 +#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 +#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 +#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 +#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 +#endif +/* IEEE 802.11h */ +#define WLAN_REASON_PWR_CAPABILITY_NOT_VALID 10 +#define WLAN_REASON_SUPPORTED_CHANNEL_NOT_VALID 11 +#if 0 +/* IEEE 802.11i */ +#define WLAN_REASON_INVALID_IE 13 +#define WLAN_REASON_MICHAEL_MIC_FAILURE 14 +#define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT 15 +#define WLAN_REASON_GROUP_KEY_UPDATE_TIMEOUT 16 +#define WLAN_REASON_IE_IN_4WAY_DIFFERS 17 +#define WLAN_REASON_GROUP_CIPHER_NOT_VALID 18 +#define WLAN_REASON_PAIRWISE_CIPHER_NOT_VALID 19 +#define WLAN_REASON_AKMP_NOT_VALID 20 +#define WLAN_REASON_UNSUPPORTED_RSN_IE_VERSION 21 +#define WLAN_REASON_INVALID_RSN_IE_CAPAB 22 +#define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23 +#define WLAN_REASON_CIPHER_SUITE_REJECTED 24 +#endif + +enum WIFI_STATUS_CODE { + _STATS_SUCCESSFUL_ = 0, + _STATS_FAILURE_ = 1, + _STATS_CAP_FAIL_ = 10, + _STATS_NO_ASOC_ = 11, + _STATS_OTHER_ = 12, + _STATS_NO_SUPP_ALG_ = 13, + _STATS_OUT_OF_AUTH_SEQ_ = 14, + _STATS_CHALLENGE_FAIL_ = 15, + _STATS_AUTH_TIMEOUT_ = 16, + _STATS_UNABLE_HANDLE_STA_ = 17, + _STATS_RATE_FAIL_ = 18, +}; + +/* Status codes (IEEE 802.11-2007, 7.3.1.9, Table 7-23) */ +#if 0 +#define WLAN_STATUS_SUCCESS 0 +#define WLAN_STATUS_UNSPECIFIED_FAILURE 1 +#define WLAN_STATUS_CAPS_UNSUPPORTED 10 +#define WLAN_STATUS_REASSOC_NO_ASSOC 11 +#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12 +#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13 +#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14 +#define WLAN_STATUS_CHALLENGE_FAIL 15 +#define WLAN_STATUS_AUTH_TIMEOUT 16 +#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17 +#define WLAN_STATUS_ASSOC_DENIED_RATES 18 +#endif +//entended +/* IEEE 802.11b */ +#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19 +#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20 +#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21 +/* IEEE 802.11h */ +#define WLAN_STATUS_SPEC_MGMT_REQUIRED 22 +#define WLAN_STATUS_PWR_CAPABILITY_NOT_VALID 23 +#define WLAN_STATUS_SUPPORTED_CHANNEL_NOT_VALID 24 +/* IEEE 802.11g */ +#define WLAN_STATUS_ASSOC_DENIED_NO_SHORT_SLOT_TIME 25 +#define WLAN_STATUS_ASSOC_DENIED_NO_ER_PBCC 26 +#define WLAN_STATUS_ASSOC_DENIED_NO_DSSS_OFDM 27 +/* IEEE 802.11w */ +#define WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY 30 +#define WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION 31 +/* IEEE 802.11i */ +#define WLAN_STATUS_INVALID_IE 40 +#define WLAN_STATUS_GROUP_CIPHER_NOT_VALID 41 +#define WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID 42 +#define WLAN_STATUS_AKMP_NOT_VALID 43 +#define WLAN_STATUS_UNSUPPORTED_RSN_IE_VERSION 44 +#define WLAN_STATUS_INVALID_RSN_IE_CAPAB 45 +#define WLAN_STATUS_CIPHER_REJECTED_PER_POLICY 46 +#define WLAN_STATUS_TS_NOT_CREATED 47 +#define WLAN_STATUS_DIRECT_LINK_NOT_ALLOWED 48 +#define WLAN_STATUS_DEST_STA_NOT_PRESENT 49 +#define WLAN_STATUS_DEST_STA_NOT_QOS_STA 50 +#define WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE 51 +/* IEEE 802.11r */ +#define WLAN_STATUS_INVALID_FT_ACTION_FRAME_COUNT 52 +#define WLAN_STATUS_INVALID_PMKID 53 +#define WLAN_STATUS_INVALID_MDIE 54 +#define WLAN_STATUS_INVALID_FTIE 55 + + +enum WIFI_REG_DOMAIN { + DOMAIN_FCC = 1, + DOMAIN_IC = 2, + DOMAIN_ETSI = 3, + DOMAIN_SPAIN = 4, + DOMAIN_FRANCE = 5, + DOMAIN_MKK = 6, + DOMAIN_ISRAEL = 7, + DOMAIN_MKK1 = 8, + DOMAIN_MKK2 = 9, + DOMAIN_MKK3 = 10, + DOMAIN_MAX +}; + +#define _TO_DS_ BIT(8) +#define _FROM_DS_ BIT(9) +#define _MORE_FRAG_ BIT(10) +#define _RETRY_ BIT(11) +#define _PWRMGT_ BIT(12) +#define _MORE_DATA_ BIT(13) +#define _PRIVACY_ BIT(14) +#define _ORDER_ BIT(15) + +#define SetToDs(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_TO_DS_); \ + } while(0) + +#define GetToDs(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_TO_DS_)) != 0) + +#define ClearToDs(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_TO_DS_)); \ + } while(0) + +#define SetFrDs(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_FROM_DS_); \ + } while(0) + +#define GetFrDs(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_FROM_DS_)) != 0) + +#define ClearFrDs(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_FROM_DS_)); \ + } while(0) + +#define get_tofr_ds(pframe) ((GetToDs(pframe) << 1) | GetFrDs(pframe)) + + +#define SetMFrag(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_FRAG_); \ + } while(0) + +#define GetMFrag(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_FRAG_)) != 0) + +#define ClearMFrag(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_FRAG_)); \ + } while(0) + +#define SetRetry(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_RETRY_); \ + } while(0) + +#define GetRetry(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_RETRY_)) != 0) + +#define ClearRetry(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_RETRY_)); \ + } while(0) + +#define SetPwrMgt(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_PWRMGT_); \ + } while(0) + +#define GetPwrMgt(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_PWRMGT_)) != 0) + +#define ClearPwrMgt(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_PWRMGT_)); \ + } while(0) + +#define SetMData(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_DATA_); \ + } while(0) + +#define GetMData(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_DATA_)) != 0) + +#define ClearMData(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_DATA_)); \ + } while(0) + +#define SetPrivacy(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_PRIVACY_); \ + } while(0) + +#define GetPrivacy(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_PRIVACY_)) != 0) + +#define ClearPrivacy(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_PRIVACY_)); \ + } while(0) + + +#define GetOrder(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0) + +#define GetFrameType(pbuf) (le16_to_cpu(*(unsigned short *)(pbuf)) & (BIT(3) | BIT(2))) + +#define SetFrameType(pbuf,type) \ + do { \ + *(unsigned short *)(pbuf) &= cpu_to_le16(~(BIT(3) | BIT(2))); \ + *(unsigned short *)(pbuf) |= cpu_to_le16(type); \ + } while(0) + +#define GetFrameSubType(pbuf) (cpu_to_le16(*(unsigned short *)(pbuf)) & (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))) + +#define SetFrameSubType(pbuf,type) \ + do { \ + *(unsigned short *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))); \ + *(unsigned short *)(pbuf) |= cpu_to_le16(type); \ + } while(0) + +#define GetSequence(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) >> 4) + +#define GetFragNum(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & 0x0f) + +#define GetTupleCache(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22))) + +#define SetFragNum(pbuf, num) \ + do { \ + *(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \ + ((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu(~(0x000f))) | \ + cpu_to_le16(0x0f & (num)); \ + } while(0) + +#define SetSeqNum(pbuf, num) \ + do { \ + *(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \ + ((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu((unsigned short)~0xfff0)) | \ + le16_to_cpu((unsigned short)(0xfff0 & (num << 4))); \ + } while(0) +#define GetFrameControl(pbuf)(cpu_to_le16(*(unsigned short*)((SIZE_PTR)(pbuf)))) +#define GetDuration(pbuf) (cpu_to_le16(*(unsigned short*)((SIZE_PTR)(pbuf) + 2))) +#define SetDuration(pbuf, dur) \ + do { \ + *(unsigned short *)((SIZE_PTR)(pbuf) + 2) = cpu_to_le16(0xffff & (dur)); \ + } while(0) + + +#define SetPriority(pbuf, tid) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(tid & 0xf); \ + } while(0) + +#define GetPriority(pbuf) ((le16_to_cpu(*(unsigned short *)(pbuf))) & 0xf) + +#define SetEOSP(pbuf, eosp) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16( (eosp & 1) << 4); \ + } while(0) + +#define SetAckpolicy(pbuf, ack) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16( (ack & 3) << 5); \ + } while(0) + +#define GetAckpolicy(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 5) & 0x3) + +#define GetAMsdu(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 7) & 0x1) + +#define SetAMsdu(pbuf, amsdu) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16( (amsdu & 1) << 7); \ + } while(0) + +#define GetAid(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 2)) & 0x3fff) + +#define GetTid(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + (((GetToDs(pbuf)<<1)|GetFrDs(pbuf))==3?30:24))) & 0x000f) + +#define GetAddr1Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 4)) + +#define GetAddr2Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 10)) + +#define GetAddr3Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 16)) + +#define GetAddr4Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 24)) + +#define MacAddr_isBcst(addr) \ +( \ + ( (addr[0] == 0xff) && (addr[1] == 0xff) && \ + (addr[2] == 0xff) && (addr[3] == 0xff) && \ + (addr[4] == 0xff) && (addr[5] == 0xff) ) ? _TRUE : _FALSE \ +) + +__inline static int IS_MCAST(unsigned char *da) +{ + if ((*da) & 0x01) + return _TRUE; + else + return _FALSE; +} + +__inline static unsigned char * get_ta(unsigned char *pframe) +{ + unsigned char *ta; + ta = GetAddr2Ptr(pframe); + return ta; +} + +__inline static unsigned char * get_da(unsigned char *pframe) +{ + unsigned char *da; + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); + + switch (to_fr_ds) { + case 0x00: // ToDs=0, FromDs=0 + da = GetAddr1Ptr(pframe); + break; + case 0x01: // ToDs=0, FromDs=1 + da = GetAddr1Ptr(pframe); + break; + case 0x02: // ToDs=1, FromDs=0 + da = GetAddr3Ptr(pframe); + break; + default: // ToDs=1, FromDs=1 + da = GetAddr3Ptr(pframe); + break; + } + + return da; +} + + +__inline static unsigned char * get_sa(unsigned char *pframe) +{ + unsigned char *sa; + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); + + switch (to_fr_ds) { + case 0x00: // ToDs=0, FromDs=0 + sa = GetAddr2Ptr(pframe); + break; + case 0x01: // ToDs=0, FromDs=1 + sa = GetAddr3Ptr(pframe); + break; + case 0x02: // ToDs=1, FromDs=0 + sa = GetAddr2Ptr(pframe); + break; + default: // ToDs=1, FromDs=1 + sa = GetAddr4Ptr(pframe); + break; + } + + return sa; +} + +__inline static unsigned char * get_hdr_bssid(unsigned char *pframe) +{ + unsigned char *sa; + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); + + switch (to_fr_ds) { + case 0x00: // ToDs=0, FromDs=0 + sa = GetAddr3Ptr(pframe); + break; + case 0x01: // ToDs=0, FromDs=1 + sa = GetAddr2Ptr(pframe); + break; + case 0x02: // ToDs=1, FromDs=0 + sa = GetAddr1Ptr(pframe); + break; + case 0x03: // ToDs=1, FromDs=1 + sa = GetAddr1Ptr(pframe); + break; + default: + sa =NULL; //??????? + break; + } + + return sa; +} + + +__inline static int IsFrameTypeCtrl(unsigned char *pframe) +{ + if(WIFI_CTRL_TYPE == GetFrameType(pframe)) + return _TRUE; + else + return _FALSE; +} +/*----------------------------------------------------------------------------- + Below is for the security related definition +------------------------------------------------------------------------------*/ +#define _RESERVED_FRAME_TYPE_ 0 +#define _SKB_FRAME_TYPE_ 2 +#define _PRE_ALLOCMEM_ 1 +#define _PRE_ALLOCHDR_ 3 +#define _PRE_ALLOCLLCHDR_ 4 +#define _PRE_ALLOCICVHDR_ 5 +#define _PRE_ALLOCMICHDR_ 6 + +#define _SIFSTIME_ ((priv->pmib->dot11BssType.net_work_type&WIRELESS_11A)?16:10) +#define _ACKCTSLNG_ 14 //14 bytes long, including crclng +#define _CRCLNG_ 4 + +#define _ASOCREQ_IE_OFFSET_ 4 // excluding wlan_hdr +#define _ASOCRSP_IE_OFFSET_ 6 +#define _REASOCREQ_IE_OFFSET_ 10 +#define _REASOCRSP_IE_OFFSET_ 6 +#define _PROBEREQ_IE_OFFSET_ 0 +#define _PROBERSP_IE_OFFSET_ 12 +#define _AUTH_IE_OFFSET_ 6 +#define _DEAUTH_IE_OFFSET_ 0 +#define _BEACON_IE_OFFSET_ 12 +#define _PUBLIC_ACTION_IE_OFFSET_ 8 + +#define _FIXED_IE_LENGTH_ _BEACON_IE_OFFSET_ + +#define _SSID_IE_ 0 +#define _SUPPORTEDRATES_IE_ 1 +#define _DSSET_IE_ 3 +#define _TIM_IE_ 5 +#define _IBSS_PARA_IE_ 6 +#define _COUNTRY_IE_ 7 +#define _CHLGETXT_IE_ 16 +#define _SUPPORTED_CH_IE_ 36 +#define _CH_SWTICH_ANNOUNCE_ 37 //Secondary Channel Offset +#define _RSN_IE_2_ 48 +#define _SSN_IE_1_ 221 +#define _ERPINFO_IE_ 42 +#define _EXT_SUPPORTEDRATES_IE_ 50 + +#define _HT_CAPABILITY_IE_ 45 +#define _FTIE_ 55 +#define _TIMEOUT_ITVL_IE_ 56 +#define _SRC_IE_ 59 +#define _HT_EXTRA_INFO_IE_ 61 +#define _HT_ADD_INFO_IE_ 61 //_HT_EXTRA_INFO_IE_ +#define _WAPI_IE_ 68 + + +#define EID_BSSCoexistence 72 // 20/40 BSS Coexistence +#define EID_BSSIntolerantChlReport 73 +#define _RIC_Descriptor_IE_ 75 + +#define _LINK_ID_IE_ 101 +#define _CH_SWITCH_TIMING_ 104 +#define _PTI_BUFFER_STATUS_ 106 +#define _EXT_CAP_IE_ 127 +#define _VENDOR_SPECIFIC_IE_ 221 + +#define _RESERVED47_ 47 + +/* --------------------------------------------------------------------------- + Below is the fixed elements... +-----------------------------------------------------------------------------*/ +#define _AUTH_ALGM_NUM_ 2 +#define _AUTH_SEQ_NUM_ 2 +#define _BEACON_ITERVAL_ 2 +#define _CAPABILITY_ 2 +#define _CURRENT_APADDR_ 6 +#define _LISTEN_INTERVAL_ 2 +#define _RSON_CODE_ 2 +#define _ASOC_ID_ 2 +#define _STATUS_CODE_ 2 +#define _TIMESTAMP_ 8 + +#define AUTH_ODD_TO 0 +#define AUTH_EVEN_TO 1 + +#define WLAN_ETHCONV_ENCAP 1 +#define WLAN_ETHCONV_RFC1042 2 +#define WLAN_ETHCONV_8021h 3 + +#define cap_ESS BIT(0) +#define cap_IBSS BIT(1) +#define cap_CFPollable BIT(2) +#define cap_CFRequest BIT(3) +#define cap_Privacy BIT(4) +#define cap_ShortPremble BIT(5) +#define cap_PBCC BIT(6) +#define cap_ChAgility BIT(7) +#define cap_SpecMgmt BIT(8) +#define cap_QoS BIT(9) +#define cap_ShortSlot BIT(10) + +/*----------------------------------------------------------------------------- + Below is the definition for 802.11i / 802.1x +------------------------------------------------------------------------------*/ +#define _IEEE8021X_MGT_ 1 // WPA +#define _IEEE8021X_PSK_ 2 // WPA with pre-shared key + +/* +#define _NO_PRIVACY_ 0 +#define _WEP_40_PRIVACY_ 1 +#define _TKIP_PRIVACY_ 2 +#define _WRAP_PRIVACY_ 3 +#define _CCMP_PRIVACY_ 4 +#define _WEP_104_PRIVACY_ 5 +#define _WEP_WPA_MIXED_PRIVACY_ 6 // WEP + WPA +*/ + +/*----------------------------------------------------------------------------- + Below is the definition for WMM +------------------------------------------------------------------------------*/ +#define _WMM_IE_Length_ 7 // for WMM STA +#define _WMM_Para_Element_Length_ 24 + +//TODO +#if 0 + +/*----------------------------------------------------------------------------- + Below is the definition for 802.11n +------------------------------------------------------------------------------*/ + +//#ifdef CONFIG_80211N_HT + +#define SetOrderBit(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_ORDER_); \ + } while(0) + +#define GetOrderBit(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0) + + +/** + * struct rtw_ieee80211_bar - HT Block Ack Request + * + * This structure refers to "HT BlockAckReq" as + * described in 802.11n draft section 7.2.1.7.1 + */ + #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8712FW) +struct rtw_ieee80211_bar { + unsigned short frame_control; + unsigned short duration; + unsigned char ra[6]; + unsigned char ta[6]; + unsigned short control; + unsigned short start_seq_num; +} __attribute__((packed)); + #endif + +/* 802.11 BAR control masks */ +#define IEEE80211_BAR_CTRL_ACK_POLICY_NORMAL 0x0000 +#define IEEE80211_BAR_CTRL_CBMTID_COMPRESSED_BA 0x0004 + +#endif //#if 0 + +#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8712FW) || defined(PLATFORM_FREEBSD) || defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined(PLATFORM_CMSIS_RTOS) + + + + /** + * struct rtw_ieee80211_ht_cap - HT capabilities + * + * This structure refers to "HT capabilities element" as + * described in 802.11n draft section 7.3.2.52 + */ + +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_begin.h" +#endif +RTW_PACK_STRUCT_BEGIN +struct rtw_ieee80211_ht_cap { + unsigned short cap_info; + unsigned char ampdu_params_info; + unsigned char supp_mcs_set[16]; + unsigned short extended_ht_cap_info; + unsigned int tx_BF_cap_info; + unsigned char antenna_selection_info; +}RTW_PACK_STRUCT_STRUCT; +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_end.h" +#endif + + +/** + * struct rtw_ieee80211_ht_cap - HT additional information + * + * This structure refers to "HT information element" as + * described in 802.11n draft section 7.3.2.53 + */ +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_begin.h" +#endif +RTW_PACK_STRUCT_BEGIN +struct ieee80211_ht_addt_info { + unsigned char control_chan; + unsigned char ht_param; + unsigned short operation_mode; + unsigned short stbc_param; + unsigned char basic_set[16]; +}RTW_PACK_STRUCT_STRUCT; +RTW_PACK_STRUCT_END +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_end.h" +#endif + +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_begin.h" +#endif +RTW_PACK_STRUCT_BEGIN +struct HT_caps_element +{ + union + { + struct + { + unsigned short HT_caps_info; + unsigned char AMPDU_para; + unsigned char MCS_rate[16]; + unsigned short HT_ext_caps; + unsigned int Beamforming_caps; + unsigned char ASEL_caps; + } +#ifdef __CC_ARM + __attribute__ ((packed)) +#endif + HT_cap_element; + unsigned char HT_cap[26]; + } +#ifdef __CC_ARM + __attribute__ ((packed)) +#endif + u; +}RTW_PACK_STRUCT_STRUCT; +RTW_PACK_STRUCT_END +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_end.h" +#endif + +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_begin.h" +#endif +RTW_PACK_STRUCT_BEGIN +struct HT_info_element +{ + unsigned char primary_channel; + unsigned char infos[5]; + unsigned char MCS_rate[16]; +}RTW_PACK_STRUCT_STRUCT; +RTW_PACK_STRUCT_END +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_end.h" +#endif + + +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_begin.h" +#endif +RTW_PACK_STRUCT_BEGIN +struct AC_param +{ + unsigned char ACI_AIFSN; + unsigned char CW; + unsigned short TXOP_limit; +}RTW_PACK_STRUCT_STRUCT; +RTW_PACK_STRUCT_END +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_end.h" +#endif + +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_begin.h" +#endif +RTW_PACK_STRUCT_BEGIN +struct WMM_para_element +{ + unsigned char QoS_info; + unsigned char reserved; + struct AC_param ac_param[4]; +}RTW_PACK_STRUCT_STRUCT; +RTW_PACK_STRUCT_END +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_end.h" +#endif + +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_begin.h" +#endif +RTW_PACK_STRUCT_BEGIN +struct ADDBA_request +{ + unsigned char dialog_token; + unsigned short BA_para_set; + unsigned short BA_timeout_value; + unsigned short BA_starting_seqctrl; +}RTW_PACK_STRUCT_STRUCT; +RTW_PACK_STRUCT_END +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_end.h" +#endif + +#endif //#if defined PLATFORM_LINUX/CONFIG_RTL8712FW/PLATFORM_FREEBSD/PLATFORM_ECOS/PLATFORM_FREERTOS + + +#ifdef PLATFORM_WINDOWS + +#pragma pack(1) + +struct rtw_ieee80211_ht_cap { + unsigned short cap_info; + unsigned char ampdu_params_info; + unsigned char supp_mcs_set[16]; + unsigned short extended_ht_cap_info; + unsigned int tx_BF_cap_info; + unsigned char antenna_selection_info; +}; + + +struct ieee80211_ht_addt_info { + unsigned char control_chan; + unsigned char ht_param; + unsigned short operation_mode; + unsigned short stbc_param; + unsigned char basic_set[16]; +}; + +struct HT_caps_element +{ + union + { + struct + { + unsigned short HT_caps_info; + unsigned char AMPDU_para; + unsigned char MCS_rate[16]; + unsigned short HT_ext_caps; + unsigned int Beamforming_caps; + unsigned char ASEL_caps; + } HT_cap_element; + unsigned char HT_cap[26]; + }; +}; + +struct HT_info_element +{ + unsigned char primary_channel; + unsigned char infos[5]; + unsigned char MCS_rate[16]; +}; + +struct AC_param +{ + unsigned char ACI_AIFSN; + unsigned char CW; + unsigned short TXOP_limit; +}; + +struct WMM_para_element +{ + unsigned char QoS_info; + unsigned char reserved; + struct AC_param ac_param[4]; +}; + +struct ADDBA_request +{ + unsigned char dialog_token; + unsigned short BA_para_set; + unsigned short BA_timeout_value; + unsigned short BA_starting_seqctrl; +}; + + +#pragma pack() + +#endif + +typedef enum _HT_CAP_AMPDU_FACTOR { + MAX_AMPDU_FACTOR_8K = 0, + MAX_AMPDU_FACTOR_16K = 1, + MAX_AMPDU_FACTOR_32K = 2, + MAX_AMPDU_FACTOR_64K = 3, +}HT_CAP_AMPDU_FACTOR; + +/* 802.11n HT capabilities masks */ +#define IEEE80211_HT_CAP_SUP_WIDTH 0x0002 +#define IEEE80211_HT_CAP_SM_PS 0x000C +#define IEEE80211_HT_CAP_GRN_FLD 0x0010 +#define IEEE80211_HT_CAP_SGI_20 0x0020 +#define IEEE80211_HT_CAP_SGI_40 0x0040 +#define IEEE80211_HT_CAP_TX_STBC 0x0080 +#define IEEE80211_HT_CAP_RX_STBC 0x0300 +#define IEEE80211_HT_CAP_DELAY_BA 0x0400 +#define IEEE80211_HT_CAP_MAX_AMSDU 0x0800 +#define IEEE80211_HT_CAP_DSSSCCK40 0x1000 +/* 802.11n HT capability AMPDU settings */ +#define IEEE80211_HT_CAP_AMPDU_FACTOR 0x03 +#define IEEE80211_HT_CAP_AMPDU_DENSITY 0x1C +/* 802.11n HT capability MSC set */ +#define IEEE80211_SUPP_MCS_SET_UEQM 4 +#define IEEE80211_HT_CAP_MAX_STREAMS 4 +#define IEEE80211_SUPP_MCS_SET_LEN 10 +/* maximum streams the spec allows */ +#define IEEE80211_HT_CAP_MCS_TX_DEFINED 0x01 +#define IEEE80211_HT_CAP_MCS_TX_RX_DIFF 0x02 +#define IEEE80211_HT_CAP_MCS_TX_STREAMS 0x0C +#define IEEE80211_HT_CAP_MCS_TX_UEQM 0x10 +/* 802.11n HT IE masks */ +#define IEEE80211_HT_IE_CHA_SEC_OFFSET 0x03 +#define IEEE80211_HT_IE_CHA_SEC_NONE 0x00 +#define IEEE80211_HT_IE_CHA_SEC_ABOVE 0x01 +#define IEEE80211_HT_IE_CHA_SEC_BELOW 0x03 +#define IEEE80211_HT_IE_CHA_WIDTH 0x04 +#define IEEE80211_HT_IE_HT_PROTECTION 0x0003 +#define IEEE80211_HT_IE_NON_GF_STA_PRSNT 0x0004 +#define IEEE80211_HT_IE_NON_HT_STA_PRSNT 0x0010 + +/* block-ack parameters */ +#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002 +#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C +#define RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFC0 +#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000 +#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800 + +/* + * A-PMDU buffer sizes + * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2) + */ +#define IEEE80211_MIN_AMPDU_BUF 0x8 +#define IEEE80211_MAX_AMPDU_BUF 0x40 + + +/* Spatial Multiplexing Power Save Modes */ +#define WLAN_HT_CAP_SM_PS_STATIC 0 +#define WLAN_HT_CAP_SM_PS_DYNAMIC 1 +#define WLAN_HT_CAP_SM_PS_INVALID 2 +#define WLAN_HT_CAP_SM_PS_DISABLED 3 + + +#define OP_MODE_PURE 0 +#define OP_MODE_MAY_BE_LEGACY_STAS 1 +#define OP_MODE_20MHZ_HT_STA_ASSOCED 2 +#define OP_MODE_MIXED 3 + +#define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK ((u8) BIT(0) | BIT(1)) +#define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE ((u8) BIT(0)) +#define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW ((u8) BIT(0) | BIT(1)) +#define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH ((u8) BIT(2)) +#define HT_INFO_HT_PARAM_RIFS_MODE ((u8) BIT(3)) +#define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY ((u8) BIT(4)) +#define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY ((u8) BIT(5)) + +#define HT_INFO_OPERATION_MODE_OP_MODE_MASK \ + ((u16) (0x0001 | 0x0002)) +#define HT_INFO_OPERATION_MODE_OP_MODE_OFFSET 0 +#define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT ((u8) BIT(2)) +#define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT ((u8) BIT(3)) +#define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT ((u8) BIT(4)) + +#define HT_INFO_STBC_PARAM_DUAL_BEACON ((u16) BIT(6)) +#define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT ((u16) BIT(7)) +#define HT_INFO_STBC_PARAM_SECONDARY_BCN ((u16) BIT(8)) +#define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED ((u16) BIT(9)) +#define HT_INFO_STBC_PARAM_PCO_ACTIVE ((u16) BIT(10)) +#define HT_INFO_STBC_PARAM_PCO_PHASE ((u16) BIT(11)) + + + +//#endif + +// ===============WPS Section=============== +// For WPSv1.0 +#define WPSOUI 0x0050f204 +// WPS attribute ID +#define WPS_ATTR_VER1 0x104A +#define WPS_ATTR_SIMPLE_CONF_STATE 0x1044 +#define WPS_ATTR_RESP_TYPE 0x103B +#define WPS_ATTR_UUID_E 0x1047 +#define WPS_ATTR_MANUFACTURER 0x1021 +#define WPS_ATTR_MODEL_NAME 0x1023 +#define WPS_ATTR_MODEL_NUMBER 0x1024 +#define WPS_ATTR_SERIAL_NUMBER 0x1042 +#define WPS_ATTR_PRIMARY_DEV_TYPE 0x1054 +#define WPS_ATTR_SEC_DEV_TYPE_LIST 0x1055 +#define WPS_ATTR_DEVICE_NAME 0x1011 +#define WPS_ATTR_CONF_METHOD 0x1008 +#define WPS_ATTR_RF_BANDS 0x103C +#define WPS_ATTR_DEVICE_PWID 0x1012 +#define WPS_ATTR_REQUEST_TYPE 0x103A +#define WPS_ATTR_ASSOCIATION_STATE 0x1002 +#define WPS_ATTR_CONFIG_ERROR 0x1009 +#define WPS_ATTR_VENDOR_EXT 0x1049 +#define WPS_ATTR_SELECTED_REGISTRAR 0x1041 + +// Value of WPS attribute "WPS_ATTR_DEVICE_NAME +#define WPS_MAX_DEVICE_NAME_LEN 32 + +// Value of WPS Request Type Attribute +#define WPS_REQ_TYPE_ENROLLEE_INFO_ONLY 0x00 +#define WPS_REQ_TYPE_ENROLLEE_OPEN_8021X 0x01 +#define WPS_REQ_TYPE_REGISTRAR 0x02 +#define WPS_REQ_TYPE_WLAN_MANAGER_REGISTRAR 0x03 + +// Value of WPS Response Type Attribute +#define WPS_RESPONSE_TYPE_INFO_ONLY 0x00 +#define WPS_RESPONSE_TYPE_8021X 0x01 +#define WPS_RESPONSE_TYPE_REGISTRAR 0x02 +#define WPS_RESPONSE_TYPE_AP 0x03 + +// Value of WPS WiFi Simple Configuration State Attribute +#define WPS_WSC_STATE_NOT_CONFIG 0x01 +#define WPS_WSC_STATE_CONFIG 0x02 + +// Value of WPS Version Attribute +#define WPS_VERSION_1 0x10 + +// Value of WPS Configuration Method Attribute +#define WPS_CONFIG_METHOD_FLASH 0x0001 +#define WPS_CONFIG_METHOD_ETHERNET 0x0002 +#define WPS_CONFIG_METHOD_LABEL 0x0004 +#define WPS_CONFIG_METHOD_DISPLAY 0x0008 +#define WPS_CONFIG_METHOD_E_NFC 0x0010 +#define WPS_CONFIG_METHOD_I_NFC 0x0020 +#define WPS_CONFIG_METHOD_NFC 0x0040 +#define WPS_CONFIG_METHOD_PBC 0x0080 +#define WPS_CONFIG_METHOD_KEYPAD 0x0100 +#define WPS_CONFIG_METHOD_VPBC 0x0280 +#define WPS_CONFIG_METHOD_PPBC 0x0480 +#define WPS_CONFIG_METHOD_VDISPLAY 0x2008 +#define WPS_CONFIG_METHOD_PDISPLAY 0x4008 + +// Value of Category ID of WPS Primary Device Type Attribute +#define WPS_PDT_CID_DISPLAYS 0x0007 +#define WPS_PDT_CID_MULIT_MEDIA 0x0008 +#define WPS_PDT_CID_RTK_WIDI WPS_PDT_CID_MULIT_MEDIA + +// Value of Sub Category ID of WPS Primary Device Type Attribute +#define WPS_PDT_SCID_MEDIA_SERVER 0x0005 +#define WPS_PDT_SCID_RTK_DMP WPS_PDT_SCID_MEDIA_SERVER + +// Value of Device Password ID +#define WPS_DPID_PIN 0x0000 +#define WPS_DPID_USER_SPEC 0x0001 +#define WPS_DPID_MACHINE_SPEC 0x0002 +#define WPS_DPID_REKEY 0x0003 +#define WPS_DPID_PBC 0x0004 +#define WPS_DPID_REGISTRAR_SPEC 0x0005 + +// Value of WPS RF Bands Attribute +#define WPS_RF_BANDS_2_4_GHZ 0x01 +#define WPS_RF_BANDS_5_GHZ 0x02 + +// Value of WPS Association State Attribute +#define WPS_ASSOC_STATE_NOT_ASSOCIATED 0x00 +#define WPS_ASSOC_STATE_CONNECTION_SUCCESS 0x01 +#define WPS_ASSOC_STATE_CONFIGURATION_FAILURE 0x02 +#define WPS_ASSOC_STATE_ASSOCIATION_FAILURE 0x03 +#define WPS_ASSOC_STATE_IP_FAILURE 0x04 + +// =====================P2P Section===================== +// For P2P +#define P2POUI 0x506F9A09 + +// P2P Attribute ID +#define P2P_ATTR_STATUS 0x00 +#define P2P_ATTR_MINOR_REASON_CODE 0x01 +#define P2P_ATTR_CAPABILITY 0x02 +#define P2P_ATTR_DEVICE_ID 0x03 +#define P2P_ATTR_GO_INTENT 0x04 +#define P2P_ATTR_CONF_TIMEOUT 0x05 +#define P2P_ATTR_LISTEN_CH 0x06 +#define P2P_ATTR_GROUP_BSSID 0x07 +#define P2P_ATTR_EX_LISTEN_TIMING 0x08 +#define P2P_ATTR_INTENTED_IF_ADDR 0x09 +#define P2P_ATTR_MANAGEABILITY 0x0A +#define P2P_ATTR_CH_LIST 0x0B +#define P2P_ATTR_NOA 0x0C +#define P2P_ATTR_DEVICE_INFO 0x0D +#define P2P_ATTR_GROUP_INFO 0x0E +#define P2P_ATTR_GROUP_ID 0x0F +#define P2P_ATTR_INTERFACE 0x10 +#define P2P_ATTR_OPERATING_CH 0x11 +#define P2P_ATTR_INVITATION_FLAGS 0x12 + +// Value of Status Attribute +#define P2P_STATUS_SUCCESS 0x00 +#define P2P_STATUS_FAIL_INFO_UNAVAILABLE 0x01 +#define P2P_STATUS_FAIL_INCOMPATIBLE_PARAM 0x02 +#define P2P_STATUS_FAIL_LIMIT_REACHED 0x03 +#define P2P_STATUS_FAIL_INVALID_PARAM 0x04 +#define P2P_STATUS_FAIL_REQUEST_UNABLE 0x05 +#define P2P_STATUS_FAIL_PREVOUS_PROTO_ERR 0x06 +#define P2P_STATUS_FAIL_NO_COMMON_CH 0x07 +#define P2P_STATUS_FAIL_UNKNOWN_P2PGROUP 0x08 +#define P2P_STATUS_FAIL_BOTH_GOINTENT_15 0x09 +#define P2P_STATUS_FAIL_INCOMPATIBLE_PROVSION 0x0A +#define P2P_STATUS_FAIL_USER_REJECT 0x0B + +// Value of Inviation Flags Attribute +#define P2P_INVITATION_FLAGS_PERSISTENT BIT(0) + +#define DMP_P2P_DEVCAP_SUPPORT (P2P_DEVCAP_SERVICE_DISCOVERY | \ + P2P_DEVCAP_CLIENT_DISCOVERABILITY | \ + P2P_DEVCAP_CONCURRENT_OPERATION | \ + P2P_DEVCAP_INVITATION_PROC) + +#define DMP_P2P_GRPCAP_SUPPORT (P2P_GRPCAP_INTRABSS) + +// Value of Device Capability Bitmap +#define P2P_DEVCAP_SERVICE_DISCOVERY BIT(0) +#define P2P_DEVCAP_CLIENT_DISCOVERABILITY BIT(1) +#define P2P_DEVCAP_CONCURRENT_OPERATION BIT(2) +#define P2P_DEVCAP_INFRA_MANAGED BIT(3) +#define P2P_DEVCAP_DEVICE_LIMIT BIT(4) +#define P2P_DEVCAP_INVITATION_PROC BIT(5) + +// Value of Group Capability Bitmap +#define P2P_GRPCAP_GO BIT(0) +#define P2P_GRPCAP_PERSISTENT_GROUP BIT(1) +#define P2P_GRPCAP_GROUP_LIMIT BIT(2) +#define P2P_GRPCAP_INTRABSS BIT(3) +#define P2P_GRPCAP_CROSS_CONN BIT(4) +#define P2P_GRPCAP_PERSISTENT_RECONN BIT(5) +#define P2P_GRPCAP_GROUP_FORMATION BIT(6) + +// P2P Public Action Frame ( Management Frame ) +#define P2P_PUB_ACTION_ACTION 0x09 + +// P2P Public Action Frame Type +#define P2P_GO_NEGO_REQ 0 +#define P2P_GO_NEGO_RESP 1 +#define P2P_GO_NEGO_CONF 2 +#define P2P_INVIT_REQ 3 +#define P2P_INVIT_RESP 4 +#define P2P_DEVDISC_REQ 5 +#define P2P_DEVDISC_RESP 6 +#define P2P_PROVISION_DISC_REQ 7 +#define P2P_PROVISION_DISC_RESP 8 + +// P2P Action Frame Type +#define P2P_NOTICE_OF_ABSENCE 0 +#define P2P_PRESENCE_REQUEST 1 +#define P2P_PRESENCE_RESPONSE 2 +#define P2P_GO_DISC_REQUEST 3 + + +#define P2P_MAX_PERSISTENT_GROUP_NUM 10 + +#define P2P_PROVISIONING_SCAN_CNT 3 + +#define P2P_WILDCARD_SSID_LEN 7 + +#define P2P_FINDPHASE_EX_NONE 0 // default value, used when: (1)p2p disabed or (2)p2p enabled but only do 1 scan phase +#define P2P_FINDPHASE_EX_FULL 1 // used when p2p enabled and want to do 1 scan phase and P2P_FINDPHASE_EX_MAX-1 find phase +#define P2P_FINDPHASE_EX_SOCIAL_FIRST (P2P_FINDPHASE_EX_FULL+1) +#define P2P_FINDPHASE_EX_MAX 4 +#define P2P_FINDPHASE_EX_SOCIAL_LAST P2P_FINDPHASE_EX_MAX + +#define P2P_PROVISION_TIMEOUT 5000 // 5 seconds timeout for sending the provision discovery request +#define P2P_CONCURRENT_PROVISION_TIMEOUT 3000 // 3 seconds timeout for sending the provision discovery request under concurrent mode +#define P2P_GO_NEGO_TIMEOUT 5000 // 5 seconds timeout for receiving the group negotation response +#define P2P_CONCURRENT_GO_NEGO_TIMEOUT 3000 // 3 seconds timeout for sending the negotiation request under concurrent mode +#define P2P_TX_PRESCAN_TIMEOUT 100 // 100ms +#define P2P_INVITE_TIMEOUT 5000 // 5 seconds timeout for sending the invitation request +#define P2P_CONCURRENT_INVITE_TIMEOUT 3000 // 3 seconds timeout for sending the invitation request under concurrent mode + +#define P2P_MAX_INTENT 15 + +#define P2P_MAX_NOA_NUM 2 + +// WPS Configuration Method +#define WPS_CM_NONE 0x0000 +#define WPS_CM_LABEL 0x0004 +#define WPS_CM_DISPLYA 0x0008 +#define WPS_CM_EXTERNAL_NFC_TOKEN 0x0010 +#define WPS_CM_INTEGRATED_NFC_TOKEN 0x0020 +#define WPS_CM_NFC_INTERFACE 0x0040 +#define WPS_CM_PUSH_BUTTON 0x0080 +#define WPS_CM_KEYPAD 0x0100 +#define WPS_CM_SW_PUHS_BUTTON 0x0280 +#define WPS_CM_HW_PUHS_BUTTON 0x0480 +#define WPS_CM_SW_DISPLAY_PIN 0x2008 +#define WPS_CM_LCD_DISPLAY_PIN 0x4008 + +enum gen_ie_type{ + P2PWPS_PROBE_REQ_IE = 0, + P2PWPS_PROBE_RSP_IE, + P2PWPS_BEACON_IE, + P2PWPS_ASSOC_REQ_IE, + P2PWPS_ASSOC_RSP_IE +}; + +enum P2P_ROLE { + P2P_ROLE_DISABLE = 0, + P2P_ROLE_DEVICE = 1, + P2P_ROLE_CLIENT = 2, + P2P_ROLE_GO = 3 +}; + +enum P2P_STATE { + P2P_STATE_NONE = 0, // P2P disable + P2P_STATE_IDLE = 1, // P2P had enabled and do nothing + P2P_STATE_LISTEN = 2, // In pure listen state + P2P_STATE_SCAN = 3, // In scan phase + P2P_STATE_FIND_PHASE_LISTEN = 4, // In the listen state of find phase + P2P_STATE_FIND_PHASE_SEARCH = 5, // In the search state of find phase + P2P_STATE_TX_PROVISION_DIS_REQ = 6, // In P2P provisioning discovery + P2P_STATE_RX_PROVISION_DIS_RSP = 7, + P2P_STATE_RX_PROVISION_DIS_REQ = 8, + P2P_STATE_GONEGO_ING = 9, // Doing the group owner negoitation handshake + P2P_STATE_GONEGO_OK = 10, // finish the group negoitation handshake with success + P2P_STATE_GONEGO_FAIL = 11, // finish the group negoitation handshake with failure + P2P_STATE_RECV_INVITE_REQ_MATCH = 12, // receiving the P2P Inviation request and match with the profile. + P2P_STATE_PROVISIONING_ING = 13, // Doing the P2P WPS + P2P_STATE_PROVISIONING_DONE = 14, // Finish the P2P WPS + P2P_STATE_TX_INVITE_REQ = 15, // Transmit the P2P Invitation request + P2P_STATE_RX_INVITE_RESP = 16, // Receiving the P2P Invitation response + P2P_STATE_RECV_INVITE_REQ_DISMATCH = 17, // receiving the P2P Inviation request and dismatch with the profile. + P2P_STATE_RECV_INVITE_REQ_GO = 18, // receiving the P2P Inviation request and this wifi is GO. + P2P_STATE_RECV_INVITE_REQ_JOIN = 19, // receiving the P2P Inviation request to join an existing P2P Group. + P2P_STATE_FORMATION_COMPLETE = 20, + P2P_STATE_CONNECTED = 21, +}; + +enum P2P_WPSINFO { + P2P_NO_WPSINFO = 0, + P2P_GOT_WPSINFO_PEER_DISPLAY_PIN = 1, + P2P_GOT_WPSINFO_SELF_DISPLAY_PIN = 2, + P2P_GOT_WPSINFO_PBC = 3, +}; + +#define P2P_PRIVATE_IOCTL_SET_LEN 64 + +enum P2P_PROTO_WK_ID +{ + P2P_FIND_PHASE_WK = 0, + P2P_RESTORE_STATE_WK = 1, + P2P_PRE_TX_PROVDISC_PROCESS_WK = 2, + P2P_PRE_TX_NEGOREQ_PROCESS_WK = 3, + P2P_PRE_TX_INVITEREQ_PROCESS_WK = 4, + P2P_AP_P2P_CH_SWITCH_PROCESS_WK =5, + P2P_RO_CH_WK = 6, +}; + +enum P2P_PS +{ + P2P_PS_DISABLE=0, + P2P_PS_ENABLE=1, + P2P_PS_SCAN=2, + P2P_PS_SCAN_DONE=3, + P2P_PS_ALLSTASLEEP=4, // for owner +}; + +// =====================WFD Section===================== +// For Wi-Fi Display +#define WFD_ATTR_DEVICE_INFO 0x00 +#define WFD_ATTR_ASSOC_BSSID 0x01 +#define WFD_ATTR_COUPLED_SINK_INFO 0x06 +#define WFD_ATTR_LOCAL_IP_ADDR 0x08 +#define WFD_ATTR_SESSION_INFO 0x09 +#define WFD_ATTR_ALTER_MAC 0x0a + +// For WFD Device Information Attribute +#define WFD_DEVINFO_SOURCE 0x0000 +#define WFD_DEVINFO_PSINK 0x0001 +#define WFD_DEVINFO_SSINK 0x0002 + +#define WFD_DEVINFO_SESSION_AVAIL 0x0010 +#define WFD_DEVINFO_WSD 0x0040 +#define WFD_DEVINFO_PC_TDLS 0x0080 + + +#ifdef CONFIG_TX_MCAST2UNI +#define IP_MCAST_MAC(mac) ((mac[0]==0x01)&&(mac[1]==0x00)&&(mac[2]==0x5e)) +#define ICMPV6_MCAST_MAC(mac) ((mac[0]==0x33)&&(mac[1]==0x33)&&(mac[2]!=0xff)) +#endif // CONFIG_TX_MCAST2UNI + + + +#ifdef CONFIG_WAPI_SUPPORT +#ifndef IW_AUTH_WAPI_VERSION_1 +#define IW_AUTH_WAPI_VERSION_1 0x00000008 +#endif +#ifndef IW_AUTH_KEY_MGMT_WAPI_PSK +#define IW_AUTH_KEY_MGMT_WAPI_PSK 0x04 +#endif +#ifndef IW_AUTH_WAPI_ENABLED +#define IW_AUTH_WAPI_ENABLED 0x20 +#endif +#ifndef IW_ENCODE_ALG_SM4 +#define IW_ENCODE_ALG_SM4 0x20 +#endif +#endif + +#ifndef _CUSTOM_IE_TYPE_ +#define _CUSTOM_IE_TYPE_ +typedef enum CUSTOM_IE_TYPE{ + PROBE_REQ = BIT(0), + PROBE_RSP = BIT(1), + BEACON = BIT(2), +}rtw_custom_ie_type_t; +#endif /* _CUSTOM_IE_TYPE_ */ + +#endif // _WIFI_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_constants.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_constants.h index 77bedab..859fb9d 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_constants.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_constants.h @@ -1,3 +1,25 @@ +/****************************************************************************** + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + * @file wifi_constants.h + * @author + * @version + * @brief This file provides the data types used for wlan API. + ****************************************************************************** + */ + #ifndef _WIFI_CONSTANTS_H #define _WIFI_CONSTANTS_H @@ -27,6 +49,9 @@ extern "C" { #define MCSSET_LEN 16 +/** + * @brief The enumeration lists the results of the function. + */ typedef enum { RTW_SUCCESS = 0, /**< Success */ @@ -88,6 +113,11 @@ typedef enum RTW_DISABLED = -43 /**< Disabled in this build */ } rtw_result_t; +/** + * @brief The enumeration lists the possible security types to set when connection.\n + * Station mode supports OPEN, WEP, and WPA2.\n + * AP mode support OPEN and WPA2. + */ typedef enum { RTW_SECURITY_OPEN = 0, /**< Open security */ RTW_SECURITY_WEP_PSK = WEP_ENABLED, /**< WEP Security with open authentication */ @@ -125,11 +155,17 @@ typedef enum { RTW_TRUE = 1 } rtw_bool_t; +/** + * @brief The enumeration lists the band types. + */ typedef enum { RTW_802_11_BAND_5GHZ = 0, /**< Denotes 5GHz radio band */ RTW_802_11_BAND_2_4GHZ = 1 /**< Denotes 2.4GHz radio band */ } rtw_802_11_band_t; +/** + * @brief The enumeration lists all the country codes able to set to Wi-Fi driver. + */ typedef enum { /* CHANNEL PLAN */ RTW_COUNTRY_WORLD1, // 0x20 @@ -326,42 +362,56 @@ typedef enum { RTW_COUNTRY_MAX -} rtw_country_code_t; +}rtw_country_code_t; +/** + * @brief The enumeration lists the adaptivity types. + */ typedef enum { RTW_ADAPTIVITY_DISABLE = 0, RTW_ADAPTIVITY_NORMAL, // CE RTW_ADAPTIVITY_CARRIER_SENSE // MKK } rtw_adaptivity_mode_t; - +/** + * @brief The enumeration lists the supported operation mode by WIFI driver, + * including station and AP mode. + */ typedef enum { RTW_MODE_NONE = 0, RTW_MODE_STA, RTW_MODE_AP, RTW_MODE_STA_AP, RTW_MODE_PROMISC, - RTW_MODE_P2P, - RTW_MODE_MAX -} rtw_mode_t; + RTW_MODE_P2P +}rtw_mode_t; typedef enum { RTW_SCAN_FULL = 0, RTW_SCAN_SOCIAL, RTW_SCAN_ONE -} rtw_scan_mode_t; +}rtw_scan_mode_t; +/** + * @brief The enumeration lists the status to describe the connection link. + */ typedef enum { RTW_LINK_DISCONNECTED = 0, RTW_LINK_CONNECTED } rtw_link_status_t; +/** + * @brief The enumeration lists the scan types. + */ typedef enum { RTW_SCAN_TYPE_ACTIVE = 0x00, /**< Actively scan a network by sending 802.11 probe(s) */ RTW_SCAN_TYPE_PASSIVE = 0x01, /**< Passively scan a network by listening for beacons from APs */ RTW_SCAN_TYPE_PROHIBITED_CHANNELS = 0x04 /**< Passively scan on channels not enabled by the country code */ } rtw_scan_type_t; +/** + * @brief The enumeration lists the bss types. + */ typedef enum { RTW_BSS_TYPE_INFRASTRUCTURE = 0, /**< Denotes infrastructure network */ RTW_BSS_TYPE_ADHOC = 1, /**< Denotes an 802.11 ad-hoc IBSS network */ @@ -388,33 +438,45 @@ typedef enum { RTW_WPS_TYPE_NONE = 0x0006 } rtw_wps_type_t; +/** + * @brief The enumeration lists all the network bgn mode. + */ typedef enum { RTW_NETWORK_B = 1, RTW_NETWORK_BG = 3, RTW_NETWORK_BGN = 11 } rtw_network_mode_t; +/** + * @brief The enumeration lists the interfaces. + */ typedef enum { RTW_STA_INTERFACE = 0, /**< STA or Client Interface */ - RTW_AP_INTERFACE = 1, /**< softAP Interface */ + RTW_AP_INTERFACE = 1, /**< SoftAP Interface */ } rtw_interface_t; /** - * Enumeration of packet filter rules - */ + * @brief The enumeration lists the packet filter rules. + */ typedef enum { - RTW_POSITIVE_MATCHING = 0, /**< Specifies that a filter should match a given pattern */ - RTW_NEGATIVE_MATCHING = 1 /**< Specifies that a filter should NOT match a given pattern */ + RTW_POSITIVE_MATCHING = 0, /**< Receive the data matching with this pattern and discard the other data */ + RTW_NEGATIVE_MATCHING = 1 /**< Discard the data matching with this pattern and receive the other data */ } rtw_packet_filter_rule_e; +/** + * @brief The enumeration lists the promisc levels. + */ typedef enum { - RTW_PROMISC_DISABLE = 0, /**< disable the promisc */ - RTW_PROMISC_ENABLE = 1, /**< fetch all ethernet packets */ - RTW_PROMISC_ENABLE_1 = 2, /**< fetch only B/M packets */ - RTW_PROMISC_ENABLE_2 = 3, /**< fetch all 802.11 packets*/ - RTW_PROMISC_ENABLE_3 = 4, /**< fetch only B/M 802.11 packets*/ + RTW_PROMISC_DISABLE = 0, /**< Disable the promisc */ + RTW_PROMISC_ENABLE = 1, /**< Fetch all ethernet packets */ + RTW_PROMISC_ENABLE_1 = 2, /**< Fetch only B/M packets */ + RTW_PROMISC_ENABLE_2 = 3, /**< Fetch all 802.11 packets*/ + RTW_PROMISC_ENABLE_3 = 4, /**< Fetch only B/M 802.11 packets*/ } rtw_rcr_level_t; +/** + * @brief The enumeration lists the disconnect reasons. + */ typedef enum{ RTW_NO_ERROR = 0, RTW_NONE_NETWORK = 1, @@ -422,7 +484,7 @@ typedef enum{ RTW_WRONG_PASSWORD = 3 , RTW_DHCP_FAIL = 4, RTW_UNKNOWN, -} rtw_connect_error_flag_t; +}rtw_connect_error_flag_t; typedef enum { RTW_TX_PWR_PERCENTAGE_100 = 0, /* 100%, default target output power. */ @@ -430,8 +492,11 @@ typedef enum { RTW_TX_PWR_PERCENTAGE_50 = 2, /* 50% */ RTW_TX_PWR_PERCENTAGE_25 = 3, /* 25% */ RTW_TX_PWR_PERCENTAGE_12_5 = 4, /* 12.5% */ -} rtw_tx_pwr_percentage_t; +}rtw_tx_pwr_percentage_t; +/** + * @brief The enumeration is event type indicated from wlan driver. + */ typedef enum _WIFI_EVENT_INDICATE{ WIFI_EVENT_CONNECT = 0, WIFI_EVENT_DISCONNECT = 1, @@ -451,6 +516,7 @@ typedef enum _WIFI_EVENT_INDICATE{ WIFI_EVENT_BEACON_AFTER_DHCP = 15, WIFI_EVENT_MAX, }WIFI_EVENT_INDICATE; +//rtw_event_indicate_e; #ifdef __cplusplus } #endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_structures.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_structures.h index 8bd0f20..06e5a1e 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_structures.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wifi_structures.h @@ -1,3 +1,25 @@ +/****************************************************************************** + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + * @file wifi_structures.h + * @author + * @version + * @brief This file provides the data structures used for wlan API. + ****************************************************************************** + */ + #ifndef _WIFI_STRUCTURES_H #define _WIFI_STRUCTURES_H @@ -11,6 +33,10 @@ extern "C" { #if defined(__IAR_SYSTEMS_ICC__) #pragma pack(1) #endif + +/** + * @brief The structure is used to describe the SSID. + */ typedef struct rtw_ssid { unsigned char len; /**< SSID length */ unsigned char val[33]; /**< SSID name (AP name) */ @@ -22,6 +48,10 @@ typedef struct rtw_ssid { #if defined(__IAR_SYSTEMS_ICC__) #pragma pack(1) #endif + +/** + * @brief The structure is used to describe the unique 6-byte MAC address. + */ typedef struct rtw_mac { unsigned char octet[6]; /**< Unique 6-byte MAC address */ } rtw_mac_t; @@ -29,6 +59,11 @@ typedef struct rtw_mac { #pragma pack() #endif +/** + * @brief The structure is used to describe the setting about SSID, + * security type, password and default channel, used to start AP mode. + * @note The data length of string pointed by ssid and password should not exceed 32. + */ typedef struct rtw_ap_info { rtw_ssid_t ssid; rtw_security_t security_type; @@ -37,6 +72,11 @@ typedef struct rtw_ap_info { int channel; }rtw_ap_info_t; +/** + * @brief The structure is used to describe the station mode setting about SSID, + * security type and password, used when connecting to an AP. + * @note The data length of string pointed by ssid and password should not exceed 32. + */ typedef struct rtw_network_info { rtw_ssid_t ssid; rtw_mac_t bssid; @@ -46,23 +86,30 @@ typedef struct rtw_network_info { int key_id; }rtw_network_info_t; -#if defined(__IAR_SYSTEMS_ICC__) +#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__) #pragma pack(1) #endif + +/** + * @brief The structure is used to describe the scan result of the AP. + */ typedef struct rtw_scan_result { rtw_ssid_t SSID; /**< Service Set Identification (i.e. Name of Access Point) */ rtw_mac_t BSSID; /**< Basic Service Set Identification (i.e. MAC address of Access Point) */ - signed short signal_strength; /**< Receive Signal Strength Indication in dBm. <-90=Very poor, >-30=Excellent */ + signed short signal_strength; /**< Receive Signal Strength Indication in dBm. <-90=Very poor, >-30=Excellent */ rtw_bss_type_t bss_type; /**< Network type */ rtw_security_t security; /**< Security type */ rtw_wps_type_t wps_type; /**< WPS type */ - unsigned int channel; /**< Radio channel that the AP beacon was received on */ + unsigned int channel; /**< Radio channel that the AP beacon was received on */ rtw_802_11_band_t band; /**< Radio band */ } rtw_scan_result_t; -#if defined(__IAR_SYSTEMS_ICC__) +#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__) #pragma pack() #endif +/** + * @brief The structure is used to describe the data needed by scan result handler function. + */ typedef struct rtw_scan_handler_result { rtw_scan_result_t ap_details; rtw_bool_t scan_complete; @@ -70,21 +117,28 @@ typedef struct rtw_scan_handler_result { } rtw_scan_handler_result_t; -#if defined(__IAR_SYSTEMS_ICC__) +#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__) #pragma pack(1) #endif + +/** + * @brief The structure is used to store the WIFI setting gotten from WIFI driver. + */ typedef struct rtw_wifi_setting { - rtw_mode_t mode; + rtw_mode_t mode; unsigned char ssid[33]; unsigned char channel; rtw_security_t security_type; unsigned char password[65]; unsigned char key_idx; -} rtw_wifi_setting_t; -#if defined(__IAR_SYSTEMS_ICC__) +}rtw_wifi_setting_t; +#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__) #pragma pack() #endif +/** + * @brief The structure is used to describe the setting when configure the network. + */ typedef struct rtw_wifi_config { unsigned int boot_mode; unsigned char ssid[32]; @@ -95,19 +149,27 @@ typedef struct rtw_wifi_config { unsigned char channel; } rtw_wifi_config_t; +/** + * @brief The structure is used to describe the maclist. + */ typedef struct { unsigned int count; /**< Number of MAC addresses in the list */ rtw_mac_t mac_list[1]; /**< Variable length array of MAC addresses */ } rtw_maclist_t; +/** + * @brief The structure is used to describe the bss info of the network.\n + * It include the version, BSSID, beacon_period, capability, SSID, + * channel, atm_window, dtim_period, RSSI e.g. + */ typedef struct { - unsigned int version; /* version field */ - unsigned int length; /* byte length of data in this record, */ + unsigned int version; /**< version field */ + unsigned int length; /**< byte length of data in this record, */ /* starting at version and including IEs */ rtw_mac_t BSSID; - unsigned short beacon_period; /* units are Kusec */ - unsigned short capability; /* Capability information */ + unsigned short beacon_period; /**< units are Kusec */ + unsigned short capability; /**< Capability information */ unsigned char SSID_len; unsigned char SSID[32]; unsigned char channel; @@ -116,18 +178,21 @@ typedef struct { // uint8_t rates[16]; /* rates in 500kbps units w/hi bit set if basic */ // } rateset; /* supported rates */ // rtw_chanspec_t chanspec; /* chanspec for bss */ - unsigned short atim_window; /* units are Kusec */ - unsigned char dtim_period; /* DTIM period */ - signed short RSSI; /* receive signal strength (in dBm) */ + unsigned short atim_window; /**< units are Kusec */ + unsigned char dtim_period; /**< DTIM period */ + signed short RSSI; /**< receive signal strength (in dBm) */ - unsigned char n_cap; /* BSS is 802.11N Capable */ - unsigned int nbss_cap; /* 802.11N BSS Capabilities (based on HT_CAP_*) */ - unsigned char basic_mcs[MCSSET_LEN]; /* 802.11N BSS required MCS set */ + unsigned char n_cap; /**< BSS is 802.11N Capable */ + unsigned int nbss_cap; /**< 802.11N BSS Capabilities (based on HT_CAP_*) */ + unsigned char basic_mcs[MCSSET_LEN]; /**< 802.11N BSS required MCS set */ - unsigned short ie_offset; /* offset at which IEs start, from beginning */ - unsigned int ie_length; /* byte length of Information Elements */ + unsigned short ie_offset; /**< offset at which IEs start, from beginning */ + unsigned int ie_length; /**< byte length of Information Elements */ } rtw_bss_info_t; +/** + * @brief The structure is used to set WIFI packet filter pattern. + */ typedef struct { unsigned short offset; /**< Offset in bytes to start filtering (referenced to the start of the ethernet packet) */ unsigned short mask_size; /**< Size of the mask in bytes */ @@ -159,7 +224,6 @@ typedef struct rtw_mac_filter_list{ unsigned char mac_addr[6]; }rtw_mac_filter_list_t; - #ifdef __cplusplus } #endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_basic_types.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_basic_types.h new file mode 100644 index 0000000..f7bd19f --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_basic_types.h @@ -0,0 +1,610 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __WLAN_BASIC_TYPES_H__ +#define __WLAN_BASIC_TYPES_H__ + + +/* ================================================ + * Sections (1) rtl8195a and (2) other MCU based wlan driver + * For 8195a, some of the definitions are already defined in system wise "basic_types.h" + *================================================ */ +#define _SUCCESS 1 +#define _PASS 1 +#define _FAIL 0 + +//ERRNO Define +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + + +#define ENSROK 0 /* DNS server returned answer with no data */ +#define ENSRNODATA 160 /* DNS server returned answer with no data */ +#define ENSRFORMERR 161 /* DNS server claims query was misformatted */ +#define ENSRSERVFAIL 162 /* DNS server returned general failure */ +#define ENSRNOTFOUND 163 /* Domain name not found */ +#define ENSRNOTIMP 164 /* DNS server does not implement requested operation */ +#define ENSRREFUSED 165 /* DNS server refused query */ +#define ENSRBADQUERY 166 /* Misformatted DNS query */ +#define ENSRBADNAME 167 /* Misformatted domain name */ +#define ENSRBADFAMILY 168 /* Unsupported address family */ +#define ENSRBADRESP 169 /* Misformatted DNS reply */ +#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */ +#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */ +#define ENSROF 172 /* End of file */ +#define ENSRFILE 173 /* Error reading file */ +#define ENSRNOMEM 174 /* Out of memory */ +#define ENSRDESTRUCTION 175 /* Application terminated lookup */ +#define ENSRQUERYDOMAINTOOLONG 176 /* Domain name is too long */ +#define ENSRCNAMELOOP 177 /* Domain name is too long */ + + + + + + + +/* ================================================ + * Sections only for other MCU based wlan driver + *========================================== ======*/ + #if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B) +#include + +#define SUCCESS 0 +#define FAIL (-1) + +#ifndef TRUE + #define _TRUE 1 +#else + #define _TRUE TRUE +#endif + +#ifndef FALSE + #define _FALSE 0 +#else + #define _FALSE FALSE +#endif + +// +// pack & weak attribute +// +#if defined (__ICCARM__) + +#define RTW_PACK_STRUCT_BEGIN +#define RTW_PACK_STRUCT_STRUCT +#define RTW_PACK_STRUCT_END +#define RTW_PACK_STRUCT_USE_INCLUDES + +#define RTW_WEAK __weak + +#elif defined (__CC_ARM) + +#define RTW_PACK_STRUCT_BEGIN __packed +#define RTW_PACK_STRUCT_STRUCT +#define RTW_PACK_STRUCT_END + +#define RTW_WEAK __weak + +#elif defined (__GNUC__) + +#define RTW_PACK_STRUCT_BEGIN +#define RTW_PACK_STRUCT_STRUCT __attribute__ ((__packed__)) +#define RTW_PACK_STRUCT_END + +#define RTW_WEAK __attribute__ ((weak)) + +#elif defined(PLATFORM_WINDOWS) + +#define RTW_PACK_STRUCT_BEGIN +#define RTW_PACK_STRUCT_STRUCT +#define RTW_PACK_STRUCT_END +#define RTW_PACK_STRUCT_USE_INCLUDES +#endif + +#ifndef BIT + #define BIT(x) ((u32)1 << (x)) +#endif + +#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B) +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 +#define BIT32 0x0100000000 +#define BIT33 0x0200000000 +#define BIT34 0x0400000000 +#define BIT35 0x0800000000 +#define BIT36 0x1000000000 +#endif + + +#ifdef PLATFORM_ECOS + + #define IN + #define OUT + #define VOID void + #define NDIS_OID uint + #define NDIS_STATUS uint + + typedef unsigned int uint; + typedef signed int sint; + + #ifndef PVOID + typedef void * PVOID; + #endif + + + typedef unsigned int __kernel_size_t; + typedef int __kernel_ssize_t; + + typedef __kernel_size_t SIZE_T; + typedef __kernel_ssize_t SSIZE_T; + #define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field) + +#endif + + +#ifdef PLATFORM_WINDOWS + + typedef signed char s8; + typedef unsigned char u8; + + typedef signed short s16; + typedef unsigned short u16; + + typedef signed long s32; + typedef unsigned long u32; + + typedef unsigned int uint; + typedef signed int sint; + + + typedef signed long long s64; + typedef unsigned long long u64; + + #ifdef NDIS50_MINIPORT + + #define NDIS_MAJOR_VERSION 5 + #define NDIS_MINOR_VERSION 0 + + #endif + + #ifdef NDIS51_MINIPORT + + #define NDIS_MAJOR_VERSION 5 + #define NDIS_MINOR_VERSION 1 + + #endif + + typedef NDIS_PROC proc_t; + + typedef LONG atomic_t; + +#endif + + +#ifdef PLATFORM_LINUX + + #include + #define IN + #define OUT + #define VOID void + #define NDIS_OID uint + #define NDIS_STATUS uint + + typedef signed int sint; + + #ifndef PVOID + typedef void * PVOID; + //#define PVOID (void *) + #endif + + typedef void (*proc_t)(void*); + + typedef __kernel_size_t SIZE_T; + typedef __kernel_ssize_t SSIZE_T; + #define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field) + +#endif + + +#ifdef PLATFORM_FREEBSD + typedef signed char s8; + typedef unsigned char u8; + + typedef signed short s16; + typedef unsigned short u16; + + typedef signed int s32; + typedef unsigned int u32; + + typedef unsigned int uint; + typedef signed int sint; + typedef long atomic_t; + + typedef signed long long s64; + typedef unsigned long long u64; + #define IN + #define OUT + #define VOID void + #define NDIS_OID uint + #define NDIS_STATUS uint + + #ifndef PVOID + typedef void * PVOID; + //#define PVOID (void *) + #endif + typedef u32 dma_addr_t; + + typedef void (*proc_t)(void*); + + typedef unsigned int __kernel_size_t; + typedef int __kernel_ssize_t; + + typedef __kernel_size_t SIZE_T; + typedef __kernel_ssize_t SSIZE_T; + #define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field) + +#endif + + +#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T)) +#define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1) + +#define SIZE_PTR SIZE_T +#define SSIZE_PTR SSIZE_T + +//port from fw by thomas +// TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness + +/* + * Call endian free function when + * 1. Read/write packet content. + * 2. Before write integer to IO. + * 3. After read integer from IO. +*/ + +// +// Byte Swapping routine. +// +#define EF1Byte +#define EF2Byte le16_to_cpu +#define EF4Byte le32_to_cpu + +// +// Read LE format data from memory +// +#define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr))) +#define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr))) +#define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr))) + +// +// Write LE data to memory +// +#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val) +#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val) +#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val) + +// +// Example: +// BIT_LEN_MASK_32(0) => 0x00000000 +// BIT_LEN_MASK_32(1) => 0x00000001 +// BIT_LEN_MASK_32(2) => 0x00000003 +// BIT_LEN_MASK_32(32) => 0xFFFFFFFF +// +#define BIT_LEN_MASK_32(__BitLen) \ + (0xFFFFFFFF >> (32 - (__BitLen))) +// +// Example: +// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 +// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 +// +#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \ + (BIT_LEN_MASK_32(__BitLen) << (__BitOffset)) + +// +// Description: +// Return 4-byte value in host byte ordering from +// 4-byte pointer in litten-endian system. +// +#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ + (EF4Byte(*((u32 *)(__pStart)))) + +// +// Description: +// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to +// 4-byte value in host byte ordering. +// +#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + ( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \ + & \ + BIT_LEN_MASK_32(__BitLen) \ + ) + +// +// Description: +// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering +// and return the result in 4-byte value in host byte ordering. +// +#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ + & \ + ( ~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \ + ) + +// +// Description: +// Set subfield of little-endian 4-byte value to specified value. +// +#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + *((u32 *)(__pStart)) = \ + EF4Byte( \ + LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \ + ); + + +#define BIT_LEN_MASK_16(__BitLen) \ + (0xFFFF >> (16 - (__BitLen))) + +#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \ + (BIT_LEN_MASK_16(__BitLen) << (__BitOffset)) + +#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ + (EF2Byte(*((u16 *)(__pStart)))) + +#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + ( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \ + & \ + BIT_LEN_MASK_16(__BitLen) \ + ) + +#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ + & \ + ( ~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \ + ) + +#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + *((u16 *)(__pStart)) = \ + EF2Byte( \ + LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \ + ); + +#define BIT_LEN_MASK_8(__BitLen) \ + (0xFF >> (8 - (__BitLen))) + +#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \ + (BIT_LEN_MASK_8(__BitLen) << (__BitOffset)) + +#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ + (EF1Byte(*((u8 *)(__pStart)))) + +#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + ( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \ + & \ + BIT_LEN_MASK_8(__BitLen) \ + ) + +#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ + & \ + ( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \ + ) + +#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + *((u8 *)(__pStart)) = \ + EF1Byte( \ + LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \ + ); + +//pclint +#define LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ + ) + +//pclint +#define SET_BITS_TO_LE_1BYTE_8BIT(__pStart, __BitOffset, __BitLen, __Value) \ +{ \ + *((u8*)(__pStart)) = \ + EF1Byte( \ + LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \ + | \ + ((u8)__Value) \ + ); \ +} + +// Get the N-bytes aligment offset from the current length +#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment)) + +typedef unsigned char BOOLEAN,*PBOOLEAN; + +#define TEST_FLAG(__Flag,__testFlag) (((__Flag) & (__testFlag)) != 0) + + + +#endif//! defined(CONFIG_PLATFORM_8195A) + +#endif //__WLAN_BASIC_TYPES_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_bssdef.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_bssdef.h new file mode 100644 index 0000000..8701d02 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_bssdef.h @@ -0,0 +1,756 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __WLAN_BSSDEF_H__ +#define __WLAN_BSSDEF_H__ + + +#define MAX_IE_SZ 768 //384// + +#if defined(PLATFORM_LINUX) || defined(PLATFORM_ECOS) || defined(PLATFORM_FREERTOS) || defined(PLATFORM_CMSIS_RTOS) +#define NDIS_802_11_LENGTH_SSID 32 +#define NDIS_802_11_LENGTH_RATES 8 +#define NDIS_802_11_LENGTH_RATES_EX 16 + +typedef unsigned char NDIS_802_11_MAC_ADDRESS[6]; +typedef long NDIS_802_11_RSSI; // in dBm +typedef unsigned char NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES]; // Set of 8 data rates +typedef unsigned char NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX]; // Set of 16 data rates + + +typedef u32 NDIS_802_11_KEY_INDEX; +typedef unsigned long long NDIS_802_11_KEY_RSC; + + +typedef struct _NDIS_802_11_SSID +{ + u32 SsidLength; + u8 Ssid[NDIS_802_11_LENGTH_SSID+4]; +} +#ifdef __CC_ARM +__attribute__((packed)) +#endif +NDIS_802_11_SSID, *PNDIS_802_11_SSID; + +typedef enum _NDIS_802_11_NETWORK_TYPE +{ + Ndis802_11FH, + Ndis802_11DS, + Ndis802_11OFDM5, + Ndis802_11OFDM24, + Ndis802_11NetworkTypeMax // not a real type, defined as an upper bound +} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE; + +typedef struct _NDIS_802_11_CONFIGURATION_FH +{ + u32 Length; // Length of structure + u32 HopPattern; // As defined by 802.11, MSB set + u32 HopSet; // to one if non-802.11 + u32 DwellTime; // units are Kusec +} +#ifdef __CC_ARM +__attribute__((packed)) +#endif +NDIS_802_11_CONFIGURATION_FH, *PNDIS_802_11_CONFIGURATION_FH; + + +/* + FW will only save the channel number in DSConfig. + ODI Handler will convert the channel number to freq. number. +*/ +typedef struct _NDIS_802_11_CONFIGURATION +{ + u32 Length; // Length of structure + u32 BeaconPeriod; // units are Kusec + u32 ATIMWindow; // units are Kusec + u32 DSConfig; // Frequency, units are kHz + NDIS_802_11_CONFIGURATION_FH FHConfig; +} +#ifdef __CC_ARM +__attribute__((packed)) +#endif +NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION; + + + +typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE +{ + Ndis802_11IBSS, + Ndis802_11Infrastructure, + Ndis802_11AutoUnknown, + Ndis802_11InfrastructureMax, // Not a real value, defined as upper bound + Ndis802_11APMode +} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE; + + + + + +typedef struct _NDIS_802_11_FIXED_IEs +{ + u8 Timestamp[8]; + u16 BeaconInterval; + u16 Capabilities; +} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs; + + + +typedef struct _NDIS_802_11_VARIABLE_IEs +{ + u8 ElementID; + u8 Length; + u8 data[1]; +} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs; + + + +/* + + + +Length is the 4 bytes multiples of the sume of + sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + sizeof (NDIS_802_11_SSID) + sizeof (u32) ++ sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + sizeof (NDIS_802_11_CONFIGURATION) ++ sizeof (NDIS_802_11_RATES_EX) + IELength + +Except the IELength, all other fields are fixed length. Therefore, we can define a marco to present the +partial sum. + +*/ +#if 0 +typedef struct _NDIS_WLAN_BSSID_EX +{ + u32 Length; + NDIS_802_11_MAC_ADDRESS MacAddress; + u8 Reserved[2];//[0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity; + NDIS_802_11_SSID Ssid; + u32 Privacy; + NDIS_802_11_RSSI Rssi; + NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; + NDIS_802_11_CONFIGURATION Configuration; + NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; + NDIS_802_11_RATES_EX SupportedRates; + u32 IELength; + u8 IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information) +} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX; + + +typedef struct _NDIS_802_11_BSSID_LIST_EX +{ + u32 NumberOfItems; + NDIS_WLAN_BSSID_EX Bssid[1]; +} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX; +#endif + +typedef enum _NDIS_802_11_AUTHENTICATION_MODE +{ + Ndis802_11AuthModeOpen, + Ndis802_11AuthModeShared, + Ndis802_11AuthModeAutoSwitch, + Ndis802_11AuthModeWPA, + Ndis802_11AuthModeWPAPSK, + Ndis802_11AuthModeWPANone, + Ndis802_11AuthModeWAPI, + Ndis802_11AuthModeMax // Not a real mode, defined as upper bound +} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE; + +typedef enum _NDIS_802_11_WEP_STATUS +{ + Ndis802_11WEPEnabled, + Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled, + Ndis802_11WEPDisabled, + Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled, + Ndis802_11WEPKeyAbsent, + Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent, + Ndis802_11WEPNotSupported, + Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported, + Ndis802_11Encryption2Enabled, + Ndis802_11Encryption2KeyAbsent, + Ndis802_11Encryption3Enabled, + Ndis802_11Encryption3KeyAbsent, + Ndis802_11_EncrypteionWAPI +} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS, + NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS; + + +#define NDIS_802_11_AI_REQFI_CAPABILITIES 1 +#define NDIS_802_11_AI_REQFI_LISTENINTERVAL 2 +#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS 4 + +#define NDIS_802_11_AI_RESFI_CAPABILITIES 1 +#define NDIS_802_11_AI_RESFI_STATUSCODE 2 +#define NDIS_802_11_AI_RESFI_ASSOCIATIONID 4 + +typedef struct _NDIS_802_11_AI_REQFI +{ + u16 Capabilities; + u16 ListenInterval; + NDIS_802_11_MAC_ADDRESS CurrentAPAddress; +} NDIS_802_11_AI_REQFI, *PNDIS_802_11_AI_REQFI; + +typedef struct _NDIS_802_11_AI_RESFI +{ + u16 Capabilities; + u16 StatusCode; + u16 AssociationId; +} NDIS_802_11_AI_RESFI, *PNDIS_802_11_AI_RESFI; + +typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION +{ + u32 Length; + u16 AvailableRequestFixedIEs; + NDIS_802_11_AI_REQFI RequestFixedIEs; + u32 RequestIELength; + u32 OffsetRequestIEs; + u16 AvailableResponseFixedIEs; + NDIS_802_11_AI_RESFI ResponseFixedIEs; + u32 ResponseIELength; + u32 OffsetResponseIEs; +} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION; + +typedef enum _NDIS_802_11_RELOAD_DEFAULTS +{ + Ndis802_11ReloadWEPKeys +} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS; + + +// Key mapping keys require a BSSID +typedef struct _NDIS_802_11_KEY +{ + u32 Length; // Length of this structure + u32 KeyIndex; + u32 KeyLength; // length of key in bytes + NDIS_802_11_MAC_ADDRESS BSSID; + NDIS_802_11_KEY_RSC KeyRSC; + u8 KeyMaterial[32]; // variable length depending on above field +} NDIS_802_11_KEY, *PNDIS_802_11_KEY; + +typedef struct _NDIS_802_11_REMOVE_KEY +{ + u32 Length; // Length of this structure + u32 KeyIndex; + NDIS_802_11_MAC_ADDRESS BSSID; +} NDIS_802_11_REMOVE_KEY, *PNDIS_802_11_REMOVE_KEY; + +typedef struct _NDIS_802_11_WEP +{ + u32 Length; // Length of this structure + u32 KeyIndex; // 0 is the per-client key, 1-N are the global keys + u32 KeyLength; // length of key in bytes + u8 KeyMaterial[16];// variable length depending on above field +} NDIS_802_11_WEP, *PNDIS_802_11_WEP; + +typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST +{ + u32 Length; // Length of structure + NDIS_802_11_MAC_ADDRESS Bssid; + u32 Flags; +} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST; + +typedef enum _NDIS_802_11_STATUS_TYPE +{ + Ndis802_11StatusType_Authentication, + Ndis802_11StatusType_MediaStreamMode, + Ndis802_11StatusType_PMKID_CandidateList, + Ndis802_11StatusTypeMax // not a real type, defined as an upper bound +} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE; + +typedef struct _NDIS_802_11_STATUS_INDICATION +{ + NDIS_802_11_STATUS_TYPE StatusType; +} NDIS_802_11_STATUS_INDICATION, *PNDIS_802_11_STATUS_INDICATION; + +// mask for authentication/integrity fields +#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f +#define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01 +#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02 +#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06 +#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E + +// MIC check time, 60 seconds. +#define MIC_CHECK_TIME 60000000 + +typedef struct _NDIS_802_11_AUTHENTICATION_EVENT +{ + NDIS_802_11_STATUS_INDICATION Status; + NDIS_802_11_AUTHENTICATION_REQUEST Request[1]; +} NDIS_802_11_AUTHENTICATION_EVENT, *PNDIS_802_11_AUTHENTICATION_EVENT; + +typedef struct _NDIS_802_11_TEST +{ + u32 Length; + u32 Type; + union + { + NDIS_802_11_AUTHENTICATION_EVENT AuthenticationEvent; + NDIS_802_11_RSSI RssiTrigger; + }tt; +} NDIS_802_11_TEST, *PNDIS_802_11_TEST; + + +#endif //end of #ifdef PLATFORM_LINUX + +#ifdef PLATFORM_FREEBSD + +#define NDIS_802_11_LENGTH_SSID 32 +#define NDIS_802_11_LENGTH_RATES 8 +#define NDIS_802_11_LENGTH_RATES_EX 16 + +typedef unsigned char NDIS_802_11_MAC_ADDRESS[6]; +typedef long NDIS_802_11_RSSI; // in dBm +typedef unsigned char NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES]; // Set of 8 data rates +typedef unsigned char NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX]; // Set of 16 data rates + + +typedef u32 NDIS_802_11_KEY_INDEX; +typedef unsigned long long NDIS_802_11_KEY_RSC; + + +typedef struct _NDIS_802_11_SSID +{ + u32 SsidLength; + u8 Ssid[32]; +} NDIS_802_11_SSID, *PNDIS_802_11_SSID; + +typedef enum _NDIS_802_11_NETWORK_TYPE +{ + Ndis802_11FH, + Ndis802_11DS, + Ndis802_11OFDM5, + Ndis802_11OFDM24, + Ndis802_11NetworkTypeMax // not a real type, defined as an upper bound +} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE; + +typedef struct _NDIS_802_11_CONFIGURATION_FH +{ + u32 Length; // Length of structure + u32 HopPattern; // As defined by 802.11, MSB set + u32 HopSet; // to one if non-802.11 + u32 DwellTime; // units are Kusec +} NDIS_802_11_CONFIGURATION_FH, *PNDIS_802_11_CONFIGURATION_FH; + + +/* + FW will only save the channel number in DSConfig. + ODI Handler will convert the channel number to freq. number. +*/ +typedef struct _NDIS_802_11_CONFIGURATION +{ + u32 Length; // Length of structure + u32 BeaconPeriod; // units are Kusec + u32 ATIMWindow; // units are Kusec + u32 DSConfig; // Frequency, units are kHz + NDIS_802_11_CONFIGURATION_FH FHConfig; +} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION; + + + +typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE +{ + Ndis802_11IBSS, + Ndis802_11Infrastructure, + Ndis802_11AutoUnknown, + Ndis802_11InfrastructureMax, // Not a real value, defined as upper bound + Ndis802_11APMode +} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE; + + + + + +typedef struct _NDIS_802_11_FIXED_IEs +{ + u8 Timestamp[8]; + u16 BeaconInterval; + u16 Capabilities; +} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs; + + + +typedef struct _NDIS_802_11_VARIABLE_IEs +{ + u8 ElementID; + u8 Length; + u8 data[1]; +} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs; + + + +/* + + + +Length is the 4 bytes multiples of the sume of + sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + sizeof (NDIS_802_11_SSID) + sizeof (u32) ++ sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + sizeof (NDIS_802_11_CONFIGURATION) ++ sizeof (NDIS_802_11_RATES_EX) + IELength + +Except the IELength, all other fields are fixed length. Therefore, we can define a marco to present the +partial sum. + +*/ +#if 0 +typedef struct _NDIS_WLAN_BSSID_EX +{ + u32 Length; + NDIS_802_11_MAC_ADDRESS MacAddress; + u8 Reserved[2];//[0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity; + NDIS_802_11_SSID Ssid; + u32 Privacy; + NDIS_802_11_RSSI Rssi; + NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; + NDIS_802_11_CONFIGURATION Configuration; + NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; + NDIS_802_11_RATES_EX SupportedRates; + u32 IELength; + u8 IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information) +} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX; + + +typedef struct _NDIS_802_11_BSSID_LIST_EX +{ + u32 NumberOfItems; + NDIS_WLAN_BSSID_EX Bssid[1]; +} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX; +#endif + +typedef enum _NDIS_802_11_AUTHENTICATION_MODE +{ + Ndis802_11AuthModeOpen, + Ndis802_11AuthModeShared, + Ndis802_11AuthModeAutoSwitch, + Ndis802_11AuthModeWPA, + Ndis802_11AuthModeWPAPSK, + Ndis802_11AuthModeWPANone, + Ndis802_11AuthModeMax // Not a real mode, defined as upper bound +} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE; + +typedef enum _NDIS_802_11_WEP_STATUS +{ + Ndis802_11WEPEnabled, + Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled, + Ndis802_11WEPDisabled, + Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled, + Ndis802_11WEPKeyAbsent, + Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent, + Ndis802_11WEPNotSupported, + Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported, + Ndis802_11Encryption2Enabled, + Ndis802_11Encryption2KeyAbsent, + Ndis802_11Encryption3Enabled, + Ndis802_11Encryption3KeyAbsent +} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS, + NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS; + + +#define NDIS_802_11_AI_REQFI_CAPABILITIES 1 +#define NDIS_802_11_AI_REQFI_LISTENINTERVAL 2 +#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS 4 + +#define NDIS_802_11_AI_RESFI_CAPABILITIES 1 +#define NDIS_802_11_AI_RESFI_STATUSCODE 2 +#define NDIS_802_11_AI_RESFI_ASSOCIATIONID 4 + +typedef struct _NDIS_802_11_AI_REQFI +{ + u16 Capabilities; + u16 ListenInterval; + NDIS_802_11_MAC_ADDRESS CurrentAPAddress; +} NDIS_802_11_AI_REQFI, *PNDIS_802_11_AI_REQFI; + +typedef struct _NDIS_802_11_AI_RESFI +{ + u16 Capabilities; + u16 StatusCode; + u16 AssociationId; +} NDIS_802_11_AI_RESFI, *PNDIS_802_11_AI_RESFI; + +typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION +{ + u32 Length; + u16 AvailableRequestFixedIEs; + NDIS_802_11_AI_REQFI RequestFixedIEs; + u32 RequestIELength; + u32 OffsetRequestIEs; + u16 AvailableResponseFixedIEs; + NDIS_802_11_AI_RESFI ResponseFixedIEs; + u32 ResponseIELength; + u32 OffsetResponseIEs; +} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION; + +typedef enum _NDIS_802_11_RELOAD_DEFAULTS +{ + Ndis802_11ReloadWEPKeys +} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS; + + +// Key mapping keys require a BSSID +typedef struct _NDIS_802_11_KEY +{ + u32 Length; // Length of this structure + u32 KeyIndex; + u32 KeyLength; // length of key in bytes + NDIS_802_11_MAC_ADDRESS BSSID; + NDIS_802_11_KEY_RSC KeyRSC; + u8 KeyMaterial[32]; // variable length depending on above field +} NDIS_802_11_KEY, *PNDIS_802_11_KEY; + +typedef struct _NDIS_802_11_REMOVE_KEY +{ + u32 Length; // Length of this structure + u32 KeyIndex; + NDIS_802_11_MAC_ADDRESS BSSID; +} NDIS_802_11_REMOVE_KEY, *PNDIS_802_11_REMOVE_KEY; + +typedef struct _NDIS_802_11_WEP +{ + u32 Length; // Length of this structure + u32 KeyIndex; // 0 is the per-client key, 1-N are the global keys + u32 KeyLength; // length of key in bytes + u8 KeyMaterial[16];// variable length depending on above field +} NDIS_802_11_WEP, *PNDIS_802_11_WEP; + +typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST +{ + u32 Length; // Length of structure + NDIS_802_11_MAC_ADDRESS Bssid; + u32 Flags; +} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST; + +typedef enum _NDIS_802_11_STATUS_TYPE +{ + Ndis802_11StatusType_Authentication, + Ndis802_11StatusType_MediaStreamMode, + Ndis802_11StatusType_PMKID_CandidateList, + Ndis802_11StatusTypeMax // not a real type, defined as an upper bound +} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE; + +typedef struct _NDIS_802_11_STATUS_INDICATION +{ + NDIS_802_11_STATUS_TYPE StatusType; +} NDIS_802_11_STATUS_INDICATION, *PNDIS_802_11_STATUS_INDICATION; + +// mask for authentication/integrity fields +#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f +#define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01 +#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02 +#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06 +#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E + +// MIC check time, 60 seconds. +#define MIC_CHECK_TIME 60000000 + +typedef struct _NDIS_802_11_AUTHENTICATION_EVENT +{ + NDIS_802_11_STATUS_INDICATION Status; + NDIS_802_11_AUTHENTICATION_REQUEST Request[1]; +} NDIS_802_11_AUTHENTICATION_EVENT, *PNDIS_802_11_AUTHENTICATION_EVENT; + +typedef struct _NDIS_802_11_TEST +{ + u32 Length; + u32 Type; + union + { + NDIS_802_11_AUTHENTICATION_EVENT AuthenticationEvent; + NDIS_802_11_RSSI RssiTrigger; + }tt; +} NDIS_802_11_TEST, *PNDIS_802_11_TEST; + + +#endif //PLATFORM_FREEBSD + +typedef struct _WLAN_PHY_INFO +{ + u8 SignalStrength; //(in percentage) + u8 SignalQuality; //(in percentage) + u8 Optimum_antenna; //for Antenna diversity + u8 Reserved_0; +} +#ifdef __CC_ARM +__attribute__((packed)) +#endif +WLAN_PHY_INFO,*PWLAN_PHY_INFO; + +typedef struct _WLAN_BCN_INFO +{ + /* these infor get from rtw_get_encrypt_info when + * * translate scan to UI */ + u8 encryp_protocol; //ENCRYP_PROTOCOL_E: OPEN/WEP/WPA/WPA2/WAPI + int group_cipher; //WPA/WPA2 group cipher + int pairwise_cipher; //WPA/WPA2/WEP pairwise cipher + int is_8021x; + + /* bwmode 20/40 and ch_offset UP/LOW */ + unsigned short ht_cap_info; + unsigned char ht_info_infos_0; +} WLAN_BCN_INFO,*PWLAN_BCN_INFO; + +/* temporally add #pragma pack for structure alignment issue of +* WLAN_BSSID_EX and get_WLAN_BSSID_EX_sz() +*/ +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_begin.h" +#endif +RTW_PACK_STRUCT_BEGIN +typedef struct _WLAN_BSSID_EX +{ + u32 Length; + NDIS_802_11_MAC_ADDRESS MacAddress; + #ifdef CONFIG_P2P_NEW + u8 Reserved[1]; //[0]: IS beacon frame + u8 bP2pNetwork; + #else + u8 Reserved[2]; //[0]: IS beacon frame + #endif + NDIS_802_11_SSID Ssid; + u32 Privacy; + NDIS_802_11_RSSI Rssi; //(in dBM,raw data ,get from PHY) + NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; + NDIS_802_11_CONFIGURATION Configuration; + NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; + NDIS_802_11_RATES_EX SupportedRates; + WLAN_PHY_INFO PhyInfo; + u32 IELength; + u8 IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information) +} +RTW_PACK_STRUCT_STRUCT +WLAN_BSSID_EX, *PWLAN_BSSID_EX; +RTW_PACK_STRUCT_END +#ifdef RTW_PACK_STRUCT_USE_INCLUDES +# include "pack_end.h" +#endif + + +__inline static uint get_WLAN_BSSID_EX_sz(WLAN_BSSID_EX *bss) +{ +#if 0 + uint t_len; + + t_len = sizeof (u32) + + sizeof (NDIS_802_11_MAC_ADDRESS) + + 2 + + sizeof (NDIS_802_11_SSID) + + sizeof (u32) + + sizeof (NDIS_802_11_RSSI) + + sizeof (NDIS_802_11_NETWORK_TYPE) + + sizeof (NDIS_802_11_CONFIGURATION) + + sizeof (NDIS_802_11_NETWORK_INFRASTRUCTURE) + + sizeof (NDIS_802_11_RATES_EX) + //all new member add here + + sizeof(WLAN_PHY_INFO) + //all new member add here + + sizeof (u32) + + bss->IELength; + return t_len; +#else + return (sizeof(WLAN_BSSID_EX) -MAX_IE_SZ + bss->IELength); +#endif +} + +struct wlan_network { + _list list; + int network_type; //refer to ieee80211.h for WIRELESS_11A/B/G + int fixed; // set to fixed when not to be removed as site-surveying + unsigned long last_scanned; //timestamp for the network + int aid; //will only be valid when a BSS is joinned. + int join_res; + WLAN_BSSID_EX network; //must be the last item + WLAN_BCN_INFO BcnInfo; +#ifdef PLATFORM_WINDOWS + unsigned char iebuf[MAX_IE_SZ]; +#endif + +}; + +enum VRTL_CARRIER_SENSE +{ + DISABLE_VCS, + ENABLE_VCS, + AUTO_VCS +}; + +enum VCS_TYPE +{ + NONE_VCS, + RTS_CTS, + CTS_TO_SELF +}; + + + + +#define PWR_CAM 0 +#define PWR_MINPS 1 +#define PWR_MAXPS 2 +#define PWR_UAPSD 3 +#define PWR_VOIP 4 + + +enum UAPSD_MAX_SP +{ + NO_LIMIT, + TWO_MSDU, + FOUR_MSDU, + SIX_MSDU +}; + + +#define NUM_PRE_AUTH_KEY 16 +#define NUM_PMKID_CACHE NUM_PRE_AUTH_KEY + +/* +* WPA2 +*/ + +#ifndef PLATFORM_OS_CE +typedef struct _PMKID_CANDIDATE { + NDIS_802_11_MAC_ADDRESS BSSID; + u32 Flags; +} PMKID_CANDIDATE, *PPMKID_CANDIDATE; + +typedef struct _NDIS_802_11_PMKID_CANDIDATE_LIST +{ + u32 Version; // Version of the structure + u32 NumCandidates; // No. of pmkid candidates + PMKID_CANDIDATE CandidateList[1]; +} NDIS_802_11_PMKID_CANDIDATE_LIST, *PNDIS_802_11_PMKID_CANDIDATE_LIST; + + +typedef struct _NDIS_802_11_AUTHENTICATION_ENCRYPTION +{ + NDIS_802_11_AUTHENTICATION_MODE AuthModeSupported; + NDIS_802_11_ENCRYPTION_STATUS EncryptStatusSupported; + +} NDIS_802_11_AUTHENTICATION_ENCRYPTION, *PNDIS_802_11_AUTHENTICATION_ENCRYPTION; + +typedef struct _NDIS_802_11_CAPABILITY +{ + u32 Length; + u32 Version; + u32 NoOfPMKIDs; + u32 NoOfAuthEncryptPairsSupported; + NDIS_802_11_AUTHENTICATION_ENCRYPTION AuthenticationEncryptionSupported[1]; + +} NDIS_802_11_CAPABILITY, *PNDIS_802_11_CAPABILITY; +#endif + + +#endif //#ifndef WLAN_BSSDEF_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_lib.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_lib.h index 5559791..0c5936b 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_lib.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/include/wlan_lib.h @@ -245,7 +245,7 @@ extern u8 rtw_cancel_timer(_timer *ptimer); extern BOOL rltk_get_idx_bydev(struct net_device *dev); extern int rltk_wlan_init(int idx_wlan, rtw_mode_t mode); extern void rltk_wlan_deinit(); -extern void rltk_wlan_start(int idx_wlan); +extern int rltk_wlan_start(int idx_wlan); extern int rltk_wlan_check_isup(int idx); extern void rltk_wlan_tx_inc(int idx); extern void rltk_wlan_tx_dec(int idx); diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/HalPhyRf.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/HalPhyRf.h new file mode 100644 index 0000000..0d5c32a --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/HalPhyRf.h @@ -0,0 +1,102 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + #ifndef __HAL_PHY_RF_H__ + #define __HAL_PHY_RF_H__ + +typedef enum _SPUR_CAL_METHOD { + PLL_RESET, + AFE_PHASE_SEL +} SPUR_CAL_METHOD; + +typedef enum _PWRTRACK_CONTROL_METHOD { + BBSWING, + TXAGC, + MIX_MODE +} PWRTRACK_METHOD; + +typedef VOID (*FuncSetPwr)(PDM_ODM_T, PWRTRACK_METHOD, u1Byte, u1Byte); +typedef VOID (*FuncIQK)(PDM_ODM_T, u1Byte, u1Byte, u1Byte); +#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B) +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +typedef VOID (*FuncLCK)(PDM_ODM_T); +#else +typedef VOID (*FuncLCK)(PADAPTER); +#endif +#else +typedef VOID (*FuncLCK)(PDM_ODM_T); +#endif +typedef VOID (*FuncSwing)(PDM_ODM_T, ps1Byte*, ps1Byte*, ps1Byte*, ps1Byte*); +typedef VOID (*FuncSwingXtal)(PDM_ODM_T, ps1Byte*, ps1Byte*); +typedef VOID (*FuncSetXtal)(PDM_ODM_T); + + +typedef struct _TXPWRTRACK_CFG { + u1Byte SwingTableSize_CCK; + u1Byte SwingTableSize_OFDM; + u1Byte Threshold_IQK; + u1Byte AverageThermalNum; + u1Byte RfPathCount; + u4Byte ThermalRegAddr; + FuncSetPwr ODM_TxPwrTrackSetPwr; + FuncIQK DoIQK; + FuncLCK PHY_LCCalibrate; + FuncSwing GetDeltaSwingTable; + FuncSwingXtal GetDeltaSwingXtalTable; + FuncSetXtal ODM_TxXtalTrackSetXtal; +} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; + +void ConfigureTxpowerTrack( + IN PDM_ODM_T pDM_Odm, + OUT PTXPWRTRACK_CFG pConfig + ); + + +VOID +ODM_ClearTxPowerTrackingState( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER Adapter +#endif + ); + + + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +VOID +ODM_ResetIQKResult( + IN PDM_ODM_T pDM_Odm +); +u1Byte +ODM_GetRightChnlPlaceforIQK( + IN u1Byte chnl +); + + +#endif // #ifndef __HAL_PHY_RF_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/PhyDM_Adaptivity.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/PhyDM_Adaptivity.h new file mode 100644 index 0000000..ac29d6f --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/PhyDM_Adaptivity.h @@ -0,0 +1,162 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMADAPTIVITY_H__ +#define __PHYDMADAPTIVITY_H__ + +#define ADAPTIVITY_VERSION "8.4" + +#define PwdBUpperBound 7 +#define DFIRloss 5 + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +typedef enum _tag_PhyDM_REGULATION_Type { + REGULATION_FCC = 0, + REGULATION_MKK = 1, + REGULATION_ETSI = 2, + REGULATION_WW = 3, + + MAX_REGULATION_NUM = 4 +} PhyDM_REGULATION_TYPE; +#endif + + +typedef enum tag_PhyDM_TRx_MUX_Type +{ + PhyDM_SHUTDOWN = 0, + PhyDM_STANDBY_MODE = 1, + PhyDM_TX_MODE = 2, + PhyDM_RX_MODE = 3 +}PhyDM_Trx_MUX_Type; + +typedef enum tag_PhyDM_MACEDCCA_Type +{ + PhyDM_IGNORE_EDCCA = 0, + PhyDM_DONT_IGNORE_EDCCA = 1 +}PhyDM_MACEDCCA_Type; + +typedef struct _ADAPTIVITY_STATISTICS { + s1Byte TH_L2H_ini_mode2; + s1Byte TH_EDCCA_HL_diff_mode2; + s1Byte TH_EDCCA_HL_diff_backup; + s1Byte IGI_Base; + u1Byte IGI_target; + u1Byte NHMWait; + s1Byte H2L_lb; + s1Byte L2H_lb; + BOOLEAN bFirstLink; + BOOLEAN bCheck; + BOOLEAN DynamicLinkAdaptivity; + u1Byte APNumTH; + u1Byte AdajustIGILevel; + BOOLEAN bStopEDCCA; +} ADAPTIVITY_STATISTICS, *PADAPTIVITY_STATISTICS; + +VOID +Phydm_CheckAdaptivity( + IN PVOID pDM_VOID + ); + +VOID +Phydm_CheckEnvironment( + IN PVOID pDM_VOID + ); + +VOID +Phydm_NHMCounterStatisticsInit( + IN PVOID pDM_VOID + ); + +VOID +Phydm_NHMCounterStatistics( + IN PVOID pDM_VOID + ); + +VOID +Phydm_NHMCounterStatisticsReset( + IN PVOID pDM_VOID +); + +VOID +Phydm_GetNHMCounterStatistics( + IN PVOID pDM_VOID +); + +VOID +Phydm_MACEDCCAState( + IN PVOID pDM_VOID, + IN PhyDM_MACEDCCA_Type State +); + +VOID +Phydm_SetEDCCAThreshold( + IN PVOID pDM_VOID, + IN s1Byte H2L, + IN s1Byte L2H +); + +VOID +Phydm_SetTRxMux( + IN PVOID pDM_VOID, + IN PhyDM_Trx_MUX_Type txMode, + IN PhyDM_Trx_MUX_Type rxMode +); + +BOOLEAN +Phydm_CalNHMcnt( + IN PVOID pDM_VOID +); + +VOID +Phydm_SearchPwdBLowerBound( + IN PVOID pDM_VOID +); + +VOID +Phydm_AdaptivityInit( + IN PVOID pDM_VOID + ); + +VOID +Phydm_Adaptivity( + IN PVOID pDM_VOID, + IN u1Byte IGI + ); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +Phydm_DisableEDCCA( + IN PVOID pDM_VOID +); + +VOID +Phydm_DynamicEDCCA( + IN PVOID pDM_VOID +); + +VOID +Phydm_AdaptivityBSOD( + IN PVOID pDM_VOID +); + +#endif + + +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/mp_precomp.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/mp_precomp.h new file mode 100644 index 0000000..4e376e7 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/mp_precomp.h @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//#include +//#include "phydm_precomp.h" +//#include "../phydm_precomp.h" + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm.h new file mode 100644 index 0000000..e7f015e --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm.h @@ -0,0 +1,2088 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __HALDMOUTSRC_H__ +#define __HALDMOUTSRC_H__ + + +#include "phydm_EdcaTurboCheck.h" +#include "phydm_DIG.h" +#include "phydm_PathDiv.h" +#include "phydm_RaInfo.h" +#include "phydm_DynamicBBPowerSaving.h" +#include "phydm_DynamicTxPower.h" +#include "phydm_CfoTracking.h" +#include "phydm_PowerTracking.h" +#include "PhyDM_Adaptivity.h" +#include "phydm_NoiseMonitor.h" +#if RTL8195A_SUPPORT +#include "rtl8195a/ROM_RTL8195A_PHYDM.h" +#endif + +#if RTL8711B_SUPPORT +#include "rtl8711b/ROM_RTL8711B_PHYDM.h" +#endif + +//============================================================ +// Definition +//============================================================ +// +// 2011/09/22 MH Define all team supprt ability. +// + +// +// 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. +// +//#define DM_ODM_SUPPORT_AP 0 +//#define DM_ODM_SUPPORT_ADSL 0 +//#define DM_ODM_SUPPORT_CE 0 +//#define DM_ODM_SUPPORT_MP 1 + +// +// 2011/09/28 MH Define ODM SW team support flag. +// + + + +// +// Antenna Switch Relative Definition. +// + +// +// 20100503 Joseph: +// Add new function SwAntDivCheck8192C(). +// This is the main function of Antenna diversity function before link. +// Mainly, it just retains last scan result and scan again. +// After that, it compares the scan result to see which one gets better RSSI. +// It selects antenna with better receiving power and returns better scan result. +// +#define TP_MODE 0 +#define RSSI_MODE 1 +#define TRAFFIC_LOW 0 +#define TRAFFIC_HIGH 1 + + +//============================================================ +//3 Tx Power Tracking +//3============================================================ +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define OFDM_TABLE_SIZE 43 +#define CCK_TABLE_SIZE 33 +#define TXSCALE_TABLE_SIZE 37 +#define TXPWR_TRACK_TABLE_SIZE 30 +#define DELTA_SWINGIDX_SIZE 30 +#define BAND_NUM 4 + +//============================================================ +//3 PSD Handler +//3============================================================ + +#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD +#define MODE_40M 0 //0:20M, 1:40M +#define PSD_TH2 3 +#define PSD_CHMIN 20 // Minimum channel number for BT AFH +#define SIR_STEP_SIZE 3 +#define Smooth_Size_1 5 +#define Smooth_TH_1 3 +#define Smooth_Size_2 10 +#define Smooth_TH_2 4 +#define Smooth_Size_3 20 +#define Smooth_TH_3 4 +#define Smooth_Step_Size 5 +#define Adaptive_SIR 1 +#if(RTL8723_FPGA_VERIFICATION == 1) +#define PSD_RESCAN 1 +#else +#define PSD_RESCAN 4 +#endif +#define PSD_SCAN_INTERVAL 700 //ms + + + +//8723A High Power IGI Setting +#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 +#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 +#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a +#define DM_DIG_LOW_PWR_THRESHOLD 0x14 + +//ANT Test +#define ANTTESTALL 0x00 //Ant A or B will be Testing +#define ANTTESTA 0x01 //Ant A will be Testing +#define ANTTESTB 0x02 //Ant B will be testing + +//for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define +#define MAIN_ANT 1 //Ant A or Ant Main +#define AUX_ANT 2 //AntB or Ant Aux +#define MAX_ANT 3 // 3 for AP using + + +//Antenna Diversity Type +#define SW_ANTDIV 0 +#define HW_ANTDIV 1 +//============================================================ +// structure and define +//============================================================ + +// +// 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. +// We need to remove to other position??? +// +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) +typedef struct rtl8192cd_priv { + u1Byte temp; + +}rtl8192cd_priv, *prtl8192cd_priv; +#endif + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +typedef struct _ADAPTER{ + u1Byte temp; + #ifdef AP_BUILD_WORKAROUND + HAL_DATA_TYPE* temp2; + prtl8192cd_priv priv; + #endif +}ADAPTER, *PADAPTER; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +typedef struct _WLAN_STA{ + u1Byte temp; +} WLAN_STA, *PRT_WLAN_STA; + +#endif + +//Remove DIG by Yuchen + +//Remoce BB power saving by Yuchn + +//Remove DIG by yuchen + +typedef struct _Dynamic_Primary_CCA{ + u1Byte PriCCA_flag; + u1Byte intf_flag; + u1Byte intf_type; + u1Byte DupRTS_flag; + u1Byte Monitor_flag; + u1Byte CH_offset; + u1Byte MF_state; +}Pri_CCA_T, *pPri_CCA_T; + +//Remove RA_T,*pRA_T by RS_James + +typedef struct _RX_High_Power_ +{ + u1Byte RXHP_flag; + u1Byte PSD_func_trigger; + u1Byte PSD_bitmap_RXHP[80]; + u1Byte Pre_IGI; + u1Byte Cur_IGI; + u1Byte Pre_pw_th; + u1Byte Cur_pw_th; + BOOLEAN First_time_enter; + BOOLEAN RXHP_enable; + u1Byte TP_Mode; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP|ODM_ADSL)) + RT_TIMER PSDTimer; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if USE_WORKITEM + RT_WORK_ITEM PSDTimeWorkitem; + #endif +#endif + +}RXHP_T, *pRXHP_T; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE)) + #define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of AsocEntry[].*/ + #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM +#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) + #ifdef CONFIG_CONCURRENT_MODE + #define ASSOCIATE_ENTRY_NUM NUM_STA+2 // 2 is for station mod + #else + #define ASSOCIATE_ENTRY_NUM NUM_STA//8 // Max size of AsocEntry[]. + #endif + #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM +#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + #define ASSOCIATE_ENTRY_NUM NUM_STAT + #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM+1 +#else + #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM+1// Default port only one +#endif + +//#ifdef CONFIG_ANTENNA_DIVERSITY +// This indicates two different the steps. +// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. +// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK +// with original RSSI to determine if it is necessary to switch antenna. +#define SWAW_STEP_PEAK 0 +#define SWAW_STEP_DETERMINE 1 + +#define TP_MODE 0 +#define RSSI_MODE 1 +#define TRAFFIC_LOW 0 +#define TRAFFIC_HIGH 1 +#define TRAFFIC_UltraLOW 2 + +typedef struct _SW_Antenna_Switch_ +{ + u1Byte Double_chk_flag; + u1Byte try_flag; + s4Byte PreRSSI; + u1Byte CurAntenna; + u1Byte PreAntenna; + u1Byte RSSI_Trying; + u1Byte TestMode; + u1Byte bTriggerAntennaSwitch; + u1Byte SelectAntennaMap; + u1Byte RSSI_target; + u1Byte reset_idx; + + // Before link Antenna Switch check + u1Byte SWAS_NoLink_State; + u4Byte SWAS_NoLink_BK_Reg860; + u4Byte SWAS_NoLink_BK_Reg92c; + BOOLEAN ANTA_ON; //To indicate Ant A is or not + BOOLEAN ANTB_ON; //To indicate Ant B is on or not + u1Byte Ant5G; + u1Byte Ant2G; + + s4Byte RSSI_sum_A; + s4Byte RSSI_sum_B; + s4Byte RSSI_cnt_A; + s4Byte RSSI_cnt_B; + + u8Byte lastTxOkCnt; + u8Byte lastRxOkCnt; + u8Byte TXByteCnt_A; + u8Byte TXByteCnt_B; + u8Byte RXByteCnt_A; + u8Byte RXByteCnt_B; + u1Byte TrafficLoad; + u1Byte Train_time; + u1Byte Train_time_flag; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP|ODM_ADSL)) + RT_TIMER SwAntennaSwitchTimer; +#endif +#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1) + RT_TIMER SwAntennaSwitchTimer_8723B; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if USE_WORKITEM + RT_WORK_ITEM SwAntennaSwitchWorkitem; + #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1) + RT_WORK_ITEM SwAntennaSwitchWorkitem_8723B; + #endif + #endif +#endif +/* CE Platform use +#ifdef CONFIG_SW_ANTENNA_DIVERSITY + _timer SwAntennaSwitchTimer; + u8Byte lastTxOkCnt; + u8Byte lastRxOkCnt; + u8Byte TXByteCnt_A; + u8Byte TXByteCnt_B; + u8Byte RXByteCnt_A; + u8Byte RXByteCnt_B; + u1Byte DoubleComfirm; + u1Byte TrafficLoad; + //SW Antenna Switch + + +#endif +*/ +#ifdef CONFIG_HW_ANTENNA_DIVERSITY + //Hybrid Antenna Diversity + u4Byte CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; + u4Byte CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; + u4Byte OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; + u4Byte OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; + u4Byte RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM]; + u4Byte RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM]; + u1Byte TxAnt[ASSOCIATE_ENTRY_NUM]; + u1Byte TargetSTA; + u1Byte antsel; + u1Byte RxIdleAnt; + +#endif + +}SWAT_T, *pSWAT_T; +//#endif + +//Remove Edca by YuChen + +//Remove ODM_RATE_ADAPTIVE by RS_James + +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + + +#ifdef ADSL_AP_BUILD_WORKAROUND +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms +#endif + +// +// Indicate different AP vendor for IOT issue. +// +typedef enum _HT_IOT_PEER +{ + HT_IOT_PEER_UNKNOWN = 0, + HT_IOT_PEER_REALTEK = 1, + HT_IOT_PEER_REALTEK_92SE = 2, + HT_IOT_PEER_BROADCOM = 3, + HT_IOT_PEER_RALINK = 4, + HT_IOT_PEER_ATHEROS = 5, + HT_IOT_PEER_CISCO = 6, + HT_IOT_PEER_MERU = 7, + HT_IOT_PEER_MARVELL = 8, + HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17 + HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP + HT_IOT_PEER_AIRGO = 11, + HT_IOT_PEER_INTEL = 12, + HT_IOT_PEER_RTK_APCLIENT = 13, + HT_IOT_PEER_REALTEK_81XX = 14, + HT_IOT_PEER_REALTEK_WOW = 15, + HT_IOT_PEER_MAX = 16 +}HT_IOT_PEER_E, *PHTIOT_PEER_E; +#endif//#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#define DM_Type_ByFW 0 +#define DM_Type_ByDriver 1 + +// +// Declare for common info +// +#define MAX_PATH_NUM_92CS 2 +#define MAX_PATH_NUM_8188E 1 +#define MAX_PATH_NUM_8192E 2 +#define MAX_PATH_NUM_8723B 1 +#define MAX_PATH_NUM_8812A 2 +#define MAX_PATH_NUM_8821A 1 +#define MAX_PATH_NUM_8195A MAX_RF_PATH // 1 +#define MAX_PATH_NUM_8711B 1 + +//Max RF path +#if ((RTL8195A_SUPPORT == 1) || (RTL8711B_SUPPORT == 1) ) +#define ODM_RF_PATH_MAX MAX_PATH_NUM_8195A +#else +#define ODM_RF_PATH_MAX 2 //92c-series +#endif +#define ODM_RF_PATH_MAX_JAGUAR 4 //jaguar - series + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_IOT)) +#ifdef RTK_AC_SUPPORT +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#else +#define ODM_IC_11AC_SERIES_SUPPORT 0 +#endif +#else +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#endif + +#if (RTL8711B_SUPPORT == 1) +#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1 +#else +#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 0 +#endif + +#define IQK_THRESHOLD 8 +#if 1 //(RTL8195A_SUPPORT == 1) +typedef struct _ODM_Phy_Status_Info_ +{ + // + // Be care, if you want to add any element please insert between + // RxPWDBAll & SignalStrength. + // +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + u4Byte RxPWDBAll; +#else + u1Byte RxPWDBAll; +#endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT)) +#if (RTL8195A_SUPPORT == 1) + u1Byte SignalQuality; // in 0-100 index. + u1Byte RxMIMOSignalStrength[ODM_RF_PATH_MAX]; // in 0~100 index + s1Byte RecvSignalPower; // Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. + u1Byte SignalStrength; // in 0-100 index. + #if (ODM_IC_11AC_SERIES_SUPPORT) + u1Byte RxMIMOEVMdbm[ODM_RF_PATH_MAX]; // per-path's EVM dbm + s2Byte Cfo_short[ODM_RF_PATH_MAX]; // per-path's Cfo_short + s2Byte Cfo_tail[ODM_RF_PATH_MAX]; // per-path's Cfo_tail + u1Byte BandWidth; + #endif +#elif (RTL8711B_SUPPORT == 1) + u1Byte SignalQuality; /* in 0-100 index. */ + s1Byte RxMIMOSignalQuality[4]; /* per-path's EVM */ + u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ + u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ + s2Byte Cfo_short[4]; /* per-path's Cfo_short */ + s2Byte Cfo_tail[4]; /* per-path's Cfo_tail */ + s1Byte RxPower; /* in dBm Translate from PWdB */ + s1Byte RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ + u1Byte BTRxRSSIPercentage; + u1Byte SignalStrength; /* in 0-100 index. */ + s1Byte RxPwr[4]; /* per-path's pwdb */ + s1Byte RxSNR[4]; /* per-path's SNR */ +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + u1Byte RxCount:2; /* RX path counter---*/ + u1Byte BandWidth:2; + u1Byte rxsc:4; /* sub-channel---*/ +#else + u1Byte BandWidth; +#endif + u1Byte btCoexPwrAdjust; +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + u1Byte channel; /* channel number---*/ + BOOLEAN bMuPacket; /* is MU packet or not---*/ + BOOLEAN bBeamformed; /* BF packet---*/ +#endif +#endif +#else + u1Byte SignalQuality; // in 0-100 index. + s1Byte RxMIMOSignalQuality[4]; //per-path's EVM + u1Byte RxMIMOEVMdbm[4]; //per-path's EVM dbm + u1Byte RxMIMOSignalStrength[4];// in 0~100 index + u2Byte Cfo_short[4]; // per-path's Cfo_short + u2Byte Cfo_tail[4]; // per-path's Cfo_tail + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + s1Byte RxPower; // in dBm Translate from PWdB + s1Byte RecvSignalPower; // Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. + u1Byte BTRxRSSIPercentage; + u1Byte SignalStrength; // in 0-100 index. + s1Byte RxPwr[4]; //per-path's pwdb + #endif + u1Byte RxSNR[4]; //per-path's SNR + u1Byte BandWidth; + u1Byte btCoexPwrAdjust; +#endif +}ODM_PHY_INFO_T,*PODM_PHY_INFO_T; +#else + +typedef struct _ODM_Phy_Status_Info_ { + // + // Be care, if you want to add any element please insert between + // RxPWDBAll & SignalStrength. + // +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + u4Byte RxPWDBAll; +#else + u1Byte RxPWDBAll; +#endif + u1Byte SignalQuality; /* in 0-100 index. */ + s1Byte RxMIMOSignalQuality[ODM_RF_PATH_MAX]; /* per-path's EVM */ + u1Byte RxMIMOEVMdbm[ODM_RF_PATH_MAX]; /* per-path's EVM dbm */ + u1Byte RxMIMOSignalStrength[ODM_RF_PATH_MAX]; /* in 0~100 index */ + s2Byte Cfo_short[ODM_RF_PATH_MAX]; /* per-path's Cfo_short */ + s2Byte Cfo_tail[ODM_RF_PATH_MAX]; /* per-path's Cfo_tail */ + s1Byte RxPower; /* in dBm Translate from PWdB */ + s1Byte RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ + u1Byte BTRxRSSIPercentage; + u1Byte SignalStrength; /* in 0-100 index. */ + s1Byte RxPwr[ODM_RF_PATH_MAX]; /* per-path's pwdb */ + s1Byte RxSNR[ODM_RF_PATH_MAX]; /* per-path's SNR */ +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + u1Byte RxCount:2; /* RX path counter---*/ + u1Byte BandWidth:2; + u1Byte rxsc:4; /* sub-channel---*/ +#else + u1Byte BandWidth; +#endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_IOT)) + u1Byte btCoexPwrAdjust; +#endif +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + u1Byte channel; /* channel number---*/ + BOOLEAN bMuPacket; /* is MU packet or not---*/ + BOOLEAN bBeamformed; /* BF packet---*/ +#endif +} ODM_PHY_INFO_T, *PODM_PHY_INFO_T; + +#endif +typedef struct _ODM_Per_Pkt_Info_ +{ + //u1Byte Rate; + u1Byte DataRate; + u1Byte StationID; + BOOLEAN bPacketMatchBSSID; + BOOLEAN bPacketToSelf; + BOOLEAN bPacketBeacon; +}ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T; + + +typedef struct _ODM_Phy_Dbg_Info_ +{ + //ODM Write,debug info + s1Byte RxSNRdB[4]; + u4Byte NumQryPhyStatus; + u4Byte NumQryPhyStatusCCK; + u4Byte NumQryPhyStatusOFDM; +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + u4Byte NumQryMuPkt; + u4Byte NumQryBfPkt; + u4Byte NumQryMuVhtPkt[40]; + u4Byte NumQryVhtPkt[40]; + BOOLEAN bLdpcPkt; + BOOLEAN bStbcPkt; +#endif + u1Byte NumQryBeaconPkt; + //Others + s4Byte RxEVM[4]; + +}ODM_PHY_DBG_INFO_T; + + +typedef struct _ODM_Mac_Status_Info_ +{ + u1Byte test; + +}ODM_MAC_INFO; + + +typedef enum tag_Dynamic_ODM_Support_Ability_Type +{ + // BB Team + ODM_DIG = 0x00000001, + ODM_HIGH_POWER = 0x00000002, + ODM_CCK_CCA_TH = 0x00000004, + ODM_FA_STATISTICS = 0x00000008, + ODM_RAMASK = 0x00000010, + ODM_RSSI_MONITOR = 0x00000020, + ODM_SW_ANTDIV = 0x00000040, + ODM_HW_ANTDIV = 0x00000080, + ODM_BB_PWRSV = 0x00000100, + ODM_2TPATHDIV = 0x00000200, + ODM_1TPATHDIV = 0x00000400, + ODM_PSD2AFH = 0x00000800 +}ODM_Ability_E; + +// +// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T +// Please declare below ODM relative info in your STA info structure. +// +#if 1 +typedef struct _ODM_STA_INFO{ + // Driver Write + BOOLEAN bUsed; // record the sta status link or not? + //u1Byte WirelessMode; // + u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E + + // ODM Write + //1 PHY_STATUS_INFO + u1Byte RSSI_Path[4]; // + u1Byte RSSI_Ave; + u1Byte RXEVM[4]; + u1Byte RXSNR[4]; + + // ODM Write + //1 TX_INFO (may changed by IC) + //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. +#if 0 + u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit + u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit + u1Byte ANTSEL_C; //only in Jagar: 4bit + u1Byte ANTSEL_D; //only in Jagar: 4bit + u1Byte TX_ANTL; //not in Jagar: 2bit + u1Byte TX_ANT_HT; //not in Jagar: 2bit + u1Byte TX_ANT_CCK; //not in Jagar: 2bit + u1Byte TXAGC_A; //not in Jagar: 4bit + u1Byte TXAGC_B; //not in Jagar: 4bit + u1Byte TXPWR_OFFSET; //only in Jagar: 3bit + u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK +#endif + + // + // Please use compile flag to disabe the strcutrue for other IC except 88E. + // Move To lower layer. + // + // ODM Write Wilson will handle this part(said by Luke.Lee) + //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer. +#if 0 + //1 For 88E RA (don't redefine the naming) + u1Byte rate_id; + u1Byte rate_SGI; + u1Byte rssi_sta_ra; + + u1Byte SGI_enable; + u1Byte Decision_rate; + u1Byte Pre_rate; + u1Byte Active; + + // Driver write Wilson handle. + //1 TX_RPT (don't redefine the naming) + u2Byte RTY[4]; // ??? + u2Byte TOTAL; // ??? + u2Byte DROP; // ??? + // + // Please use compile flag to disabe the strcutrue for other IC except 88E. + // +#endif + +}ODM_STA_INFO_T, *PODM_STA_INFO_T; +#endif + +// +// 2011/10/20 MH Define Common info enum for all team. +// +typedef enum _ODM_Common_Info_Definition +{ +//-------------REMOVED CASE-----------// + //ODM_CMNINFO_CCK_HP, + //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write??? + //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E + //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E +//-------------REMOVED CASE-----------// + + // + // Fixed value: + // + + //-----------HOOK BEFORE REG INIT-----------// + ODM_CMNINFO_PLATFORM = 0, + ODM_CMNINFO_ABILITY, // ODM_ABILITY_E + ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E + ODM_CMNINFO_MP_TEST_CHIP, + ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E + ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E + ODM_CMNINFO_FAB_VER, // ODM_FAB_E + ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E? + ODM_CMNINFO_RFE_TYPE, + ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E + ODM_CMNINFO_PACKAGE_TYPE, + ODM_CMNINFO_EXT_LNA, // TRUE + ODM_CMNINFO_5G_EXT_LNA, + ODM_CMNINFO_EXT_PA, + ODM_CMNINFO_5G_EXT_PA, + ODM_CMNINFO_GPA, + ODM_CMNINFO_APA, + ODM_CMNINFO_GLNA, + ODM_CMNINFO_ALNA, + ODM_CMNINFO_EXT_TRSW, + ODM_CMNINFO_PATCH_ID, //CUSTOMER ID + ODM_CMNINFO_BINHCT_TEST, + ODM_CMNINFO_BWIFI_TEST, + ODM_CMNINFO_SMART_CONCURRENT, + ODM_CMNINFO_DOMAIN_CODE_2G, + ODM_CMNINFO_DOMAIN_CODE_5G, + ODM_CMNINFO_EEPROMVERSION, + ODM_CMNINFO_CRYSTALCAP, + //-----------HOOK BEFORE REG INIT-----------// + + + // + // Dynamic value: + // +//--------- POINTER REFERENCE-----------// + ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E + ODM_CMNINFO_TX_UNI, + ODM_CMNINFO_RX_UNI, + ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E + ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E + ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E + ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E + ODM_CMNINFO_BW, // ODM_BW_E + ODM_CMNINFO_CHNL, + ODM_CMNINFO_FORCED_RATE, + + ODM_CMNINFO_DMSP_GET_VALUE, + ODM_CMNINFO_BUDDY_ADAPTOR, + ODM_CMNINFO_DMSP_IS_MASTER, + ODM_CMNINFO_SCAN, + ODM_CMNINFO_POWER_SAVING, + ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E + ODM_CMNINFO_DRV_STOP, + ODM_CMNINFO_PNP_IN, + ODM_CMNINFO_INIT_ON, + ODM_CMNINFO_ANT_TEST, + ODM_CMNINFO_NET_CLOSED, + ODM_CMNINFO_MP_MODE, + //ODM_CMNINFO_RTSTA_AID, // For win driver only? + ODM_CMNINFO_FORCED_IGI_LB, + ODM_CMNINFO_P2P_LINK, + ODM_CMNINFO_FCS_MODE, +//--------- POINTER REFERENCE-----------// + +//------------CALL BY VALUE-------------// + ODM_CMNINFO_WIFI_DIRECT, + ODM_CMNINFO_WIFI_DISPLAY, + ODM_CMNINFO_LINK_IN_PROGRESS, + ODM_CMNINFO_LINK, + ODM_CMNINFO_STATION_STATE, + ODM_CMNINFO_RSSI_MIN, + ODM_CMNINFO_DBG_COMP, // u8Byte + ODM_CMNINFO_DBG_LEVEL, // u4Byte + ODM_CMNINFO_RA_THRESHOLD_HIGH, // u1Byte + ODM_CMNINFO_RA_THRESHOLD_LOW, // u1Byte + ODM_CMNINFO_RF_ANTENNA_TYPE, // u1Byte + ODM_CMNINFO_BT_ENABLED, + ODM_CMNINFO_BT_HS_CONNECT_PROCESS, + ODM_CMNINFO_BT_HS_RSSI, + ODM_CMNINFO_BT_OPERATION, + ODM_CMNINFO_BT_LIMITED_DIG, //Need to Limited Dig or not + ODM_CMNINFO_BT_DISABLE_EDCA, + ODM_CMNINFO_NO_BEACON_IN_2S, +//------------CALL BY VALUE-------------// + + // + // Dynamic ptr array hook itms. + // + ODM_CMNINFO_STA_STATUS, + ODM_CMNINFO_PHY_STATUS, + ODM_CMNINFO_MAC_STATUS, + + ODM_CMNINFO_MAX, + + +}ODM_CMNINFO_E; + +// +// 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY +// +typedef enum _ODM_Support_Ability_Definition +{ + // + // BB ODM section BIT 0-19 + // + ODM_BB_DIG = BIT0, + ODM_BB_RA_MASK = BIT1, + ODM_BB_DYNAMIC_TXPWR = BIT2, + ODM_BB_FA_CNT = BIT3, + ODM_BB_RSSI_MONITOR = BIT4, + ODM_BB_CCK_PD = BIT5, + ODM_BB_ANT_DIV = BIT6, + ODM_BB_PWR_SAVE = BIT7, + ODM_BB_PWR_TRAIN = BIT8, + ODM_BB_RATE_ADAPTIVE = BIT9, + ODM_BB_PATH_DIV = BIT10, + ODM_BB_PSD = BIT11, + ODM_BB_RXHP = BIT12, + ODM_BB_ADAPTIVITY = BIT13, + ODM_BB_CFO_TRACKING = BIT14, + ODM_BB_NHM_CNT = BIT15, + ODM_BB_PRIMARY_CCA = BIT16, + + // + // MAC DM section BIT 20-23 + // + ODM_MAC_EDCA_TURBO = BIT20, + ODM_MAC_EARLY_MODE = BIT21, + + // + // RF ODM section BIT 24-31 + // + ODM_RF_TX_PWR_TRACK = BIT24, + ODM_RF_RX_GAIN_TRACK = BIT25, + ODM_RF_CALIBRATION = BIT26, + +}ODM_ABILITY_E; + +// ODM_CMNINFO_INTERFACE +typedef enum tag_ODM_Support_Interface_Definition +{ + ODM_ITRF_PCIE = 0x1, + ODM_ITRF_USB = 0x2, + ODM_ITRF_SDIO = 0x4, + ODM_ITRF_GSPI = 0x8, + ODM_ITRF_LXBUS = 0x10, + ODM_ITRF_ALL = 0xFF, +}ODM_INTERFACE_E; + +// ODM_CMNINFO_IC_TYPE +typedef enum tag_ODM_Support_IC_Type_Definition +{ + ODM_RTL8192S = BIT0, + ODM_RTL8192C = BIT1, + ODM_RTL8192D = BIT2, + ODM_RTL8723A = BIT3, + ODM_RTL8188E = BIT4, + ODM_RTL8812 = BIT5, + ODM_RTL8821 = BIT6, + ODM_RTL8192E = BIT7, + ODM_RTL8723B = BIT8, + ODM_RTL8814A = BIT9, + ODM_RTL8881A = BIT10, + ODM_RTL8821B = BIT11, + ODM_RTL8822B = BIT12, + ODM_RTL8195A = BIT13, + ODM_RTL8711B = BIT14 +}ODM_IC_TYPE_E; + +#define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8195A|ODM_RTL8711B) +#define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8821B|ODM_RTL8822B) + +//ODM_CMNINFO_CUT_VER +typedef enum tag_ODM_Cut_Version_Definition +{ + ODM_CUT_A = 0, + ODM_CUT_B = 1, + ODM_CUT_C = 2, + ODM_CUT_D = 3, + ODM_CUT_E = 4, + ODM_CUT_F = 5, + + ODM_CUT_I = 8, + ODM_CUT_TEST = 15, +}ODM_CUT_VERSION_E; + +// ODM_CMNINFO_FAB_VER +typedef enum tag_ODM_Fab_Version_Definition +{ + ODM_TSMC = 0, + ODM_UMC = 1, +}ODM_FAB_E; + +// ODM_CMNINFO_RF_TYPE +// +// For example 1T2R (A+AB = BIT0|BIT4|BIT5) +// +typedef enum tag_ODM_RF_Path_Bit_Definition +{ + ODM_RF_TX_A = BIT0, + ODM_RF_TX_B = BIT1, + ODM_RF_TX_C = BIT2, + ODM_RF_TX_D = BIT3, + ODM_RF_RX_A = BIT4, + ODM_RF_RX_B = BIT5, + ODM_RF_RX_C = BIT6, + ODM_RF_RX_D = BIT7, +}ODM_RF_PATH_E; + + +typedef enum tag_ODM_RF_Type_Definition +{ + ODM_1T1R = 0, + ODM_1T2R = 1, + ODM_2T2R = 2, + ODM_2T3R = 3, + ODM_2T4R = 4, + ODM_3T3R = 5, + ODM_3T4R = 6, + ODM_4T4R = 7, +}ODM_RF_TYPE_E; + + +// +// ODM Dynamic common info value definition +// + +//typedef enum _MACPHY_MODE_8192D{ +// SINGLEMAC_SINGLEPHY, +// DUALMAC_DUALPHY, +// DUALMAC_SINGLEPHY, +//}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; +// Above is the original define in MP driver. Please use the same define. THX. +typedef enum tag_ODM_MAC_PHY_Mode_Definition +{ + ODM_SMSP = 0, + ODM_DMSP = 1, + ODM_DMDP = 2, +}ODM_MAC_PHY_MODE_E; + + +typedef enum tag_BT_Coexist_Definition +{ + ODM_BT_BUSY = 1, + ODM_BT_ON = 2, + ODM_BT_OFF = 3, + ODM_BT_NONE = 4, +}ODM_BT_COEXIST_E; + +// ODM_CMNINFO_OP_MODE +typedef enum tag_Operation_Mode_Definition +{ + ODM_NO_LINK = BIT0, + ODM_LINK = BIT1, + ODM_SCAN = BIT2, + ODM_POWERSAVE = BIT3, + ODM_AP_MODE = BIT4, + ODM_CLIENT_MODE = BIT5, + ODM_AD_HOC = BIT6, + ODM_WIFI_DIRECT = BIT7, + ODM_WIFI_DISPLAY = BIT8, +}ODM_OPERATION_MODE_E; + +// ODM_CMNINFO_WM_MODE +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE|ODM_IOT)) +typedef enum tag_Wireless_Mode_Definition +{ + ODM_WM_UNKNOW = 0x0, + ODM_WM_B = BIT0, + ODM_WM_G = BIT1, + ODM_WM_A = BIT2, + ODM_WM_N24G = BIT3, + ODM_WM_N5G = BIT4, + ODM_WM_AUTO = BIT5, + ODM_WM_AC = BIT6, +}ODM_WIRELESS_MODE_E; +#else +typedef enum tag_Wireless_Mode_Definition +{ + ODM_WM_UNKNOWN = 0x00, + ODM_WM_A = BIT0, + ODM_WM_B = BIT1, + ODM_WM_G = BIT2, + ODM_WM_AUTO = BIT3, + ODM_WM_N24G = BIT4, + ODM_WM_N5G = BIT5, + ODM_WM_AC_5G = BIT6, + ODM_WM_AC_24G = BIT7, + ODM_WM_AC_ONLY = BIT8, + ODM_WM_MAX = BIT9 +}ODM_WIRELESS_MODE_E; +#endif + +// ODM_CMNINFO_BAND +typedef enum tag_Band_Type_Definition +{ + ODM_BAND_2_4G = 0, + ODM_BAND_5G, + ODM_BAND_ON_BOTH, + ODM_BANDMAX + +}ODM_BAND_TYPE_E; + +// ODM_CMNINFO_SEC_CHNL_OFFSET +typedef enum tag_Secondary_Channel_Offset_Definition +{ + ODM_DONT_CARE = 0, + ODM_BELOW = 1, + ODM_ABOVE = 2 +}ODM_SEC_CHNL_OFFSET_E; + +// ODM_CMNINFO_SEC_MODE +typedef enum tag_Security_Definition +{ + ODM_SEC_OPEN = 0, + ODM_SEC_WEP40 = 1, + ODM_SEC_TKIP = 2, + ODM_SEC_RESERVE = 3, + ODM_SEC_AESCCMP = 4, + ODM_SEC_WEP104 = 5, + ODM_WEP_WPA_MIXED = 6, // WEP + WPA + ODM_SEC_SMS4 = 7, +}ODM_SECURITY_E; + +// ODM_CMNINFO_BW +typedef enum tag_Bandwidth_Definition +{ + ODM_BW20M = 0, + ODM_BW40M = 1, + ODM_BW80M = 2, + ODM_BW160M = 3, + ODM_BW10M = 4, +}ODM_BW_E; + + +// ODM_CMNINFO_BOARD_TYPE +// For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored +// For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G +typedef enum tag_Board_Definition +{ + ODM_BOARD_DEFAULT = 0, // The DEFAULT case. + ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card. + ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card + ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT + ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA + ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA + ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW + ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA + ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA +}ODM_BOARD_TYPE_E; + +typedef enum tag_ODM_Package_Definition +{ + ODM_PACKAGE_DEFAULT = 0, + ODM_PACKAGE_QFN68 = BIT(0), + ODM_PACKAGE_TFBGA90 = BIT(1), + ODM_PACKAGE_TFBGA79 = BIT(2), +}ODM_Package_TYPE_E; + +typedef enum tag_ODM_TYPE_GPA_Definition +{ + TYPE_GPA0 = 0, + TYPE_GPA1 = BIT(1)|BIT(0) +}ODM_TYPE_GPA_E; + +typedef enum tag_ODM_TYPE_APA_Definition +{ + TYPE_APA0 = 0, + TYPE_APA1 = BIT(1)|BIT(0) +}ODM_TYPE_APA_E; + +typedef enum tag_ODM_TYPE_GLNA_Definition +{ + TYPE_GLNA0 = 0, + TYPE_GLNA1 = BIT(2)|BIT(0), + TYPE_GLNA2 = BIT(3)|BIT(1), + TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) +}ODM_TYPE_GLNA_E; + +typedef enum tag_ODM_TYPE_ALNA_Definition +{ + TYPE_ALNA0 = 0, + TYPE_ALNA1 = BIT(2)|BIT(0), + TYPE_ALNA2 = BIT(3)|BIT(1), + TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) +}ODM_TYPE_ALNA_E; + +// ODM_CMNINFO_ONE_PATH_CCA +typedef enum tag_CCA_Path +{ + ODM_CCA_2R = 0, + ODM_CCA_1R_A = 1, + ODM_CCA_1R_B = 2, +}ODM_CCA_PATH_E; + + +typedef struct _ODM_RA_Info_ +{ + u1Byte RateID; + u4Byte RateMask; + u4Byte RAUseRate; + u1Byte RateSGI; + u1Byte RssiStaRA; + u1Byte PreRssiStaRA; + u1Byte SGIEnable; + u1Byte DecisionRate; + u1Byte PreRate; + u1Byte HighestRate; + u1Byte LowestRate; + u4Byte NscUp; + u4Byte NscDown; + u2Byte RTY[5]; + u4Byte TOTAL; + u2Byte DROP; + u1Byte Active; + u2Byte RptTime; + u1Byte RAWaitingCounter; + u1Byte RAPendingCounter; +#if ((RTL8195A_SUPPORT == 1) || (RTL8711B_SUPPORT == 1)) + //---------Gary----------// //TODO: James + u1Byte RAINFO; + // BIT0: UL/DL state + // BIT1: EN_STBC + // BIT2: LDPC_CAP + // Add by Wilson 20130320 + // BIT3,BIT4 : 2SS short cut + // BIT5 : init rate by rssi + // BIT6: BF state + // BIT7: delay try rate + + u1Byte Initial_BW; + u1Byte BW_setting; + u1Byte DISPT; + u1Byte DISRA; + u1Byte Stage_RA; + u1Byte PRE_BW; + u1Byte MacID; + u1Byte Try_state; + u1Byte Try_done_cnt; + u2Byte RA_counter; + u1Byte Init_Rate_H; + u1Byte Init_Rate_M; + u1Byte Init_Rate_L; + u4Byte Total_TX; + + //2 Power Trainning + u1Byte TRAINING_RATE; + u1Byte STOP_PT_COUNTER; + u1Byte MODE_SS; + u1Byte PT_smooth_factor; +#endif + +#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~! + u1Byte PTActive; // on or off + u1Byte PTTryState; // 0 trying state, 1 for decision state + u1Byte PTStage; // 0~6 + u1Byte PTStopCount; //Stop PT counter + u1Byte PTPreRate; // if rate change do PT + u1Byte PTPreRssi; // if RSSI change 5% do PT + u1Byte PTModeSS; // decide whitch rate should do PT + u1Byte RAstage; // StageRA, decide how many times RA will be done between PT + u1Byte PTSmoothFactor; +#endif +} ODM_RA_INFO_T,*PODM_RA_INFO_T; + +// +// ODM Dynamic common info value definition +// + +typedef struct _FAST_ANTENNA_TRAINNING_ +{ + u1Byte Bssid[6]; + u1Byte antsel_rx_keep_0; + u1Byte antsel_rx_keep_1; + u1Byte antsel_rx_keep_2; + u1Byte antsel_rx_keep_3; + u4Byte antSumRSSI[7]; + u4Byte antRSSIcnt[7]; + u4Byte antAveRSSI[7]; + u1Byte FAT_State; + u4Byte TrainIdx; + u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte RxIdleAnt; + BOOLEAN bBecomeLinked; + u4Byte MinMaxRSSI; + u1Byte idx_AntDiv_counter_2G; + u1Byte idx_AntDiv_counter_5G; + u4Byte AntDiv_2G_5G; + u4Byte CCK_counter_main; + u4Byte CCK_counter_aux; + u4Byte OFDM_counter_main; + u4Byte OFDM_counter_aux; + +}FAT_T,*pFAT_T; +#if !((RTL8195A_SUPPORT == 1) || (RTL8711B_SUPPORT == 1)) +typedef struct _ROM_INFO{ + u1Byte EEPROMVersion; + u1Byte CrystalCap; + u8Byte DebugComponents; + u4Byte DebugLevel; +}ROM_INFO, *PROM_INFO; +#endif + +typedef enum _FAT_STATE +{ + FAT_NORMAL_STATE = 0, + FAT_TRAINING_STATE = 1, +}FAT_STATE_E, *PFAT_STATE_E; + +typedef enum _ANT_DIV_TYPE +{ + NO_ANTDIV = 0xFF, + CG_TRX_HW_ANTDIV = 0x01, + CGCS_RX_HW_ANTDIV = 0x02, + FIXED_HW_ANTDIV = 0x03, + CG_TRX_SMART_ANTDIV = 0x04, + CGCS_RX_SW_ANTDIV = 0x05, + S0S1_SW_ANTDIV = 0x06 //8723B intrnal switch S0 S1 +}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E; + +#if (RTL8812A_SUPPORT == 1) +typedef struct _ODM_PATH_DIVERSITY_ +{ + u1Byte RespTxPath; + u1Byte PathSel[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; +}PATHDIV_T, *pPATHDIV_T; +#endif + +typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{ + PHY_REG_PG_RELATIVE_VALUE = 0, + PHY_REG_PG_EXACT_VALUE = 1 +} PHY_REG_PG_TYPE; + + +// +// Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. +// +typedef struct _ANT_DETECTED_INFO{ + BOOLEAN bAntDetected; + u4Byte dBForAntA; + u4Byte dBForAntB; + u4Byte dBForAntO; +}ANT_DETECTED_INFO, *PANT_DETECTED_INFO; + +// +// 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. +// +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (RT_PLATFORM != PLATFORM_LINUX) +typedef +#endif +struct DM_Out_Source_Dynamic_Mechanism_Structure +#else// for AP,ADSL,CE,IOT Team +typedef struct DM_Out_Source_Dynamic_Mechanism_Structure +#endif +{ + //RT_TIMER FastAntTrainingTimer; + // + // Add for different team use temporarily + // + PADAPTER Adapter; // For CE/NIC team +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv; // For AP/ADSL team +#endif + // WHen you use Adapter or priv pointer, you must make sure the pointer is ready. + BOOLEAN odm_ready; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + rtl8192cd_priv fake_priv; +#endif +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + // ADSL_AP_BUILD_WORKAROUND + ADAPTER fake_adapter; +#endif + + PHY_REG_PG_TYPE PhyRegPgValueType; + u1Byte PhyRegPgVersion; + + u4Byte NumQryPhyStatusAll; //CCK + OFDM + u4Byte LastNumQryPhyStatusAll; + u4Byte RxPWDBAve; + BOOLEAN MPDIG_2G; //off MPDIG + u1Byte Times_2G; + +//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// + BOOLEAN bCckHighPower; + u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE + u1Byte ControlChannel; +//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// + +//--------REMOVED COMMON INFO----------// + //u1Byte PseudoMacPhyMode; + //BOOLEAN *BTCoexist; + //BOOLEAN PseudoBtCoexist; + //u1Byte OPMode; + //BOOLEAN bAPMode; + //BOOLEAN bClientMode; + //BOOLEAN bAdHocMode; + //BOOLEAN bSlaveOfDMSP; +//--------REMOVED COMMON INFO----------// + + +//1 COMMON INFORMATION + + // + // Init Value + // +//-----------HOOK BEFORE REG INIT-----------// + // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 + u1Byte SupportPlatform; + // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ KK = 1/2/3/K + u4Byte SupportAbility; + // ODM PCIE/USB/SDIO = 1/2/3 + u1Byte SupportInterface; + // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... + u4Byte SupportICType; + // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... + u1Byte CutVersion; + // Fab Version TSMC/UMC = 0/1 + u1Byte FabVersion; + // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... + u1Byte RFType; + u1Byte RFEType; + // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... + u1Byte BoardType; + u1Byte PackageType; + u1Byte TypeGLNA; + u1Byte TypeGPA; + u1Byte TypeALNA; + u1Byte TypeAPA; + // with external LNA NO/Yes = 0/1 + u1Byte ExtLNA; + u1Byte ExtLNA5G; + // with external PA NO/Yes = 0/1 + u1Byte ExtPA; + u1Byte ExtPA5G; + // with external TRSW NO/Yes = 0/1 + u1Byte ExtTRSW; + u1Byte PatchID; //Customer ID + BOOLEAN bInHctTest; + BOOLEAN bWIFITest; + + BOOLEAN bDualMacSmartConcurrent; + u4Byte BK_SupportAbility; + u1Byte AntDivType; + + u1Byte odm_Regulation2_4G; + u1Byte odm_Regulation5G; + BOOLEAN cck_new_agc; +//-----------HOOK BEFORE REG INIT-----------// + + // + // Dynamic Value + // +//--------- POINTER REFERENCE-----------// + + u1Byte u1Byte_temp; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL)) + BOOLEAN BOOLEAN_temp; +#endif + PADAPTER PADAPTER_temp; + + // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 + u1Byte *pMacPhyMode; + //TX Unicast byte count + u8Byte *pNumTxBytesUnicast; + //RX Unicast byte count + u8Byte *pNumRxBytesUnicast; + // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 + u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E + // Frequence band 2.4G/5G = 0/1 + u1Byte *pBandType; + // Secondary channel offset don't_care/below/above = 0/1/2 + u1Byte *pSecChOffset; + // Security mode Open/WEP/AES/TKIP = 0/1/2/3 + u1Byte *pSecurity; + // BW info 20M/40M/80M = 0/1/2 + u1Byte *pBandWidth; + // Central channel location Ch1/Ch2/.... + u1Byte *pChannel; //central channel number + BOOLEAN DPK_Done; + // Common info for 92D DMSP + + BOOLEAN *pbGetValueFromOtherMac; + PADAPTER *pBuddyAdapter; + BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave + // Common info for Status + BOOLEAN *pbScanInProcess; + BOOLEAN *pbPowerSaving; + // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. + u1Byte *pOnePathCCA; + //pMgntInfo->AntennaTest + u1Byte *pAntennaTest; + BOOLEAN *pbNet_closed; + u1Byte *mp_mode; + //u1Byte *pAidMap; + u1Byte *pu1ForcedIgiLb; + BOOLEAN *pIsFcsModeEnable; +//--------- POINTER REFERENCE-----------// + pu2Byte pForcedDataRate; +//------------CALL BY VALUE-------------// + BOOLEAN bLinkInProcess; + BOOLEAN bWIFI_Direct; + BOOLEAN bWIFI_Display; + BOOLEAN bLinked; + + BOOLEAN bsta_state; + u1Byte RSSI_Min; + u1Byte InterfaceIndex; // Add for 92D dual MAC: 0--Mac0 1--Mac1 + BOOLEAN bIsMPChip; + BOOLEAN bOneEntryOnly; + // Common info for BTDM + BOOLEAN bBtEnabled; // BT is disabled + BOOLEAN bBtConnectProcess; // BT HS is under connection progress. + u1Byte btHsRssi; // BT HS mode wifi rssi value. + BOOLEAN bBtHsOperation; // BT HS mode is under progress + BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo + BOOLEAN bBtLimitedDig; // BT is busy. +//------------CALL BY VALUE-------------// + u1Byte RSSI_A; + u1Byte RSSI_B; + u8Byte RSSI_TRSW; + u8Byte RSSI_TRSW_H; + u8Byte RSSI_TRSW_L; + u8Byte RSSI_TRSW_iso; + u1Byte RXAntStatus; + u1Byte TXAntStatus; + u1Byte RxRate; + BOOLEAN bNoisyState; + u1Byte TxRate; + u1Byte LinkedInterval; + u1Byte preChannel; + u4Byte TxagcOffsetValueA; + BOOLEAN IsTxagcOffsetPositiveA; + u4Byte TxagcOffsetValueB; + BOOLEAN IsTxagcOffsetPositiveB; + u8Byte lastTxOkCnt; + u8Byte lastRxOkCnt; + u4Byte BbSwingOffsetA; + BOOLEAN IsBbSwingOffsetPositiveA; + u4Byte BbSwingOffsetB; + BOOLEAN IsBbSwingOffsetPositiveB; + u1Byte antdiv_rssi; + u1Byte AntType; + u1Byte pre_AntType; + u1Byte antdiv_period; + u1Byte antdiv_select; + u1Byte NdpaPeriod; + + BOOLEAN H2C_RARpt_connect; + + //For Adaptivtiy + u2Byte NHM_cnt_0; + u2Byte NHM_cnt_1; + s1Byte TH_L2H_ini; + s1Byte TH_EDCCA_HL_diff; + s1Byte TH_L2H_ini_backup; + BOOLEAN Carrier_Sense_enable; + u1Byte Adaptivity_IGI_upper; + BOOLEAN adaptivity_flag; + u1Byte DCbackoff; + BOOLEAN Adaptivity_enable; + u1Byte APTotalNum; + BOOLEAN EDCCA_enable; + ADAPTIVITY_STATISTICS Adaptivity; + //For Adaptivtiy + + ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM]; + /*for noise detection*/ + BOOLEAN NoisyDecision; /*b_noisy*/ + BOOLEAN pre_b_noisy; + u4Byte NoisyDecision_Smooth; + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + s4Byte AccumulatePWDB[ODM_ASSOCIATE_ENTRY_NUM]; +#endif + + // + //2 Define STA info. + // _ODM_STA_INFO + // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? + PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; + +#if (RATE_ADAPTIVE_SUPPORT == 1) + u2Byte CurrminRptTime; + ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //See HalMacID support +#endif + // + // 2012/02/14 MH Add to share 88E ra with other SW team. + // We need to colelct all support abilit to a proper area. + // + BOOLEAN RaSupport88E; + + // Define ........... + + // Latest packet phy info (ODM write) + ODM_PHY_DBG_INFO_T PhyDbgInfo; + //PHY_INFO_88E PhyInfo; + + // Latest packet phy info (ODM write) + ODM_MAC_INFO *pMacInfo; + //MAC_INFO_88E MacInfo; + + // Different Team independt structure?? + + // + //TX_RTP_CMN TX_retrpo; + //TX_RTP_88E TX_retrpo; + //TX_RTP_8195 TX_retrpo; + + // + //ODM Structure + // + FAT_T DM_FatTable; + DIG_T DM_DigTable; + PS_T DM_PSTable; + Pri_CCA_T DM_PriCCA; + RXHP_T DM_RXHP_Table; +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_IOT)) + RA_T DM_RA_Table; +#endif + PROM_INFO pROMInfo; + + FALSE_ALARM_STATISTICS FalseAlmCnt; + CFO_TRACKING DM_CfoTrack; + + FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; + //#ifdef CONFIG_ANTENNA_DIVERSITY + SWAT_T DM_SWAT_Table; + BOOLEAN RSSI_test; + + //#endif + + BOOLEAN bNoBeaconIn2s; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + //Path Div Struct + PATHDIV_PARA pathIQK; +#endif + + EDCA_T DM_EDCA_Table; + u4Byte WMMEDCA_BE; +#if (RTL8812A_SUPPORT == 1) + PATHDIV_T DM_PathDiv; +#endif + // Copy from SD4 structure + // + // ================================================== + // + + //common + //u1Byte DM_Type; + //u1Byte PSD_Report_RXHP[80]; // Add By Gary + //u1Byte PSD_func_flag; // Add By Gary + //for DIG + //u1Byte bDMInitialGainEnable; + //u1Byte binitialized; // for dm_initial_gain_Multi_STA use. + //for Antenna diversity + //u8 AntDivCfg;// 0:OFF , 1:ON, 2:by efuse + //PSTA_INFO_T RSSI_target; + + BOOLEAN *pbDriverStopped; + BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep; + BOOLEAN *pinit_adpt_in_progress; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP|ODM_ADSL)) + //PSD + BOOLEAN bUserAssignLevel; + RT_TIMER PSDTimer; + u1Byte RSSI_BT; //come from BT + BOOLEAN bPSDinProcess; + BOOLEAN bPSDactive; + BOOLEAN bDMInitialGainEnable; + + //MPT DIG + RT_TIMER MPT_DIGTimer; +#endif + + //for rate adaptive, in fact, 88c/92c fw will handle this + u1Byte bUseRAMask; + + ODM_RATE_ADAPTIVE RateAdaptive; + + ANT_DETECTED_INFO AntDetectedInfo; // Antenna detected information for RSSI tool + + ODM_RF_CAL_T RFCalibrateInfo; + + // + // TX power tracking + // + u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; + u1Byte BbSwingIdxOfdmCurrent; + u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; + BOOLEAN BbSwingFlagOfdm; + u1Byte BbSwingIdxCck[MAX_RF_PATH]; + u1Byte BbSwingIdxCckCurrent; + u1Byte BbSwingIdxCckBase[MAX_RF_PATH]; + u1Byte DefaultOfdmIndex; + u1Byte DefaultCckIndex; + BOOLEAN BbSwingFlagCck; + + s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Absolute_CCKSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_CCKSwingIdx[MAX_RF_PATH]; + s1Byte Modify_TxAGC_Value; //Remnat compensate value at TxAGC + BOOLEAN Modify_TxAGC_Flag_PathA; + BOOLEAN Modify_TxAGC_Flag_PathB; + BOOLEAN Modify_TxAGC_Flag_PathA_CCK; + + // + // ODM system resource. + // + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + // + // Power Training + // + BOOLEAN bDisablePowerTraining; + u1Byte ForcePowerTrainingState; + BOOLEAN bChangeState; + u4Byte PT_score; + u8Byte OFDM_RX_Cnt; + u8Byte CCK_RX_Cnt; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP|ODM_ADSL)) + // ODM relative time. + RT_TIMER PathDivSwitchTimer; + //2011.09.27 add for Path Diversity + RT_TIMER CCKPathDiversityTimer; + RT_TIMER FastAntTrainingTimer; +#endif + + // ODM relative workitem. +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if USE_WORKITEM + RT_WORK_ITEM PathDivSwitchWorkitem; + RT_WORK_ITEM CCKPathDiversityWorkitem; + RT_WORK_ITEM FastAntTrainingWorkitem; + RT_WORK_ITEM MPT_DIGWorkitem; + RT_WORK_ITEM RaRptWorkitem; + #endif +#endif + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + +#if (RT_PLATFORM != PLATFORM_LINUX) +} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure +#else +}; +#endif + +#else// for AP,ADSL,CE Team +} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure +#endif + +typedef enum _PhyDM_Structure_Type{ + PhyDM_FalseAlmCnt, + PhyDM_CfoTrack, + PHYDM_ADAPTIVITY, + PhyDM_ROMInfo, + +}PhyDM_Structure_Type; + +typedef enum _ODM_RF_RADIO_PATH { + ODM_RF_PATH_A = 0, //Radio Path A + ODM_RF_PATH_B = 1, //Radio Path B + ODM_RF_PATH_C = 2, //Radio Path C + ODM_RF_PATH_D = 3, //Radio Path D + ODM_RF_PATH_AB, + ODM_RF_PATH_AC, + ODM_RF_PATH_AD, + ODM_RF_PATH_BC, + ODM_RF_PATH_BD, + ODM_RF_PATH_CD, + ODM_RF_PATH_ABC, + ODM_RF_PATH_ACD, + ODM_RF_PATH_BCD, + ODM_RF_PATH_ABCD, + // ODM_RF_PATH_MAX, //Max RF number 90 support +} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E; + + typedef enum _ODM_RF_CONTENT{ + odm_radioa_txt = 0x1000, + odm_radiob_txt = 0x1001, + odm_radioc_txt = 0x1002, + odm_radiod_txt = 0x1003 +} ODM_RF_CONTENT; + +typedef enum _ODM_BB_Config_Type{ + CONFIG_BB_PHY_REG, + CONFIG_BB_AGC_TAB, + CONFIG_BB_AGC_TAB_2G, + CONFIG_BB_AGC_TAB_5G, + CONFIG_BB_PHY_REG_PG, + CONFIG_BB_PHY_REG_MP, + CONFIG_BB_AGC_TAB_DIFF, +} ODM_BB_Config_Type, *PODM_BB_Config_Type; + +typedef enum _ODM_RF_Config_Type{ + CONFIG_RF_RADIO, + CONFIG_RF_TXPWR_LMT, +} ODM_RF_Config_Type, *PODM_RF_Config_Type; + +typedef enum _ODM_FW_Config_Type{ + CONFIG_FW_NIC, + CONFIG_FW_NIC_2, + CONFIG_FW_AP, + CONFIG_FW_MP, + CONFIG_FW_WoWLAN, + CONFIG_FW_WoWLAN_2, + CONFIG_FW_AP_WoWLAN, + CONFIG_FW_BT, + CONFIG_FW_ROM, +} ODM_FW_Config_Type; + +// Status code +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +typedef enum _RT_STATUS{ + RT_STATUS_SUCCESS, + RT_STATUS_FAILURE, + RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED, +}RT_STATUS,*PRT_STATUS; +#endif // end of RT_STATUS definition + +#ifdef REMOVE_PACK +#pragma pack() +#endif + +//#include "odm_function.h" + +//3=========================================================== +//3 DIG +//3=========================================================== + +//Remove DIG by Yuchen + +//3=========================================================== +//3 AGC RX High Power Mode +//3=========================================================== +#define LNA_Low_Gain_1 0x64 +#define LNA_Low_Gain_2 0x5A +#define LNA_Low_Gain_3 0x58 + +#define FA_RXHP_TH1 5000 +#define FA_RXHP_TH2 1500 +#define FA_RXHP_TH3 800 +#define FA_RXHP_TH4 600 +#define FA_RXHP_TH5 500 + +//3=========================================================== +//3 EDCA +//3=========================================================== + +//3=========================================================== +//3 Dynamic Tx Power +//3=========================================================== +//Dynamic Tx Power Control Threshold + +//Remove By YuChen + +//3=========================================================== +//3 Tx Power Tracking +//3=========================================================== +#if 0 //mask this, since these have been defined in typdef.h, vivi +#define OFDM_TABLE_SIZE 43 +#define CCK_TABLE_SIZE 33 +#endif + + +//3=========================================================== +//3 Rate Adaptive +//3=========================================================== +//Remove to odm_RaInfo.h by RS_James + +//3=========================================================== +//3 BB Power Save +//3=========================================================== + +typedef enum tag_1R_CCA_Type_Definition +{ + CCA_1R =0, + CCA_2R = 1, + CCA_MAX = 2, +}DM_1R_CCA_E; + +typedef enum tag_RF_Type_Definition +{ + RF_Save =0, + RF_Normal = 1, + RF_MAX = 2, +}DM_RF_E; + +//3=========================================================== +//3 Antenna Diversity +//3=========================================================== +typedef enum tag_SW_Antenna_Switch_Definition +{ + Antenna_A = 1, + Antenna_B = 2, + Antenna_MAX = 3, +}DM_SWAS_E; + + +// Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. +#define MAX_ANTENNA_DETECTION_CNT 10 + +// +// Extern Global Variables. +// +// +// check Sta pointer valid or not +// +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#define IS_STA_VALID(pSta) (pSta && pSta->expire_to) +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#define IS_STA_VALID(pSta) (pSta && pSta->bUsed) +#else +#define IS_STA_VALID(pSta) (pSta) +#endif +// 20100514 Joseph: Add definition for antenna switching test after link. +// This indicates two different the steps. +// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. +// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK +// with original RSSI to determine if it is necessary to switch antenna. +#define SWAW_STEP_PEAK 0 +#define SWAW_STEP_DETERMINE 1 + +//Remove DIG by yuchen + +//Remove BB power saving by Yuchen + +//Remove ODM_RAStateCheck() by RS_James + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL)) +//============================================================ +// function prototype +//============================================================ +//#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh +//void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter, +// IN INT32 DM_Type, +// IN INT32 DM_Value); + +//Remove DIG by yuchen + + +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter + ); + + +//Remove ODM_RateAdaptiveStateApInit() by RS_James + +//Remove Edca by Yuchen + + +#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink + +BOOLEAN +ODM_SwAntDivCheckBeforeLink( + IN PDM_ODM_T pDM_Odm + ); + + +#endif + + + +#if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE)) + +u4Byte ConvertTo_dB(u4Byte Value); + +u4Byte +GetPSDData( + PDM_ODM_T pDM_Odm, + unsigned int point, + u1Byte initial_gain_psd); + +#endif + +//Remove ODM_Get_Rate_Bitmap() by RS_James + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +#define dm_PSDMonitorCallback odm_PSDMonitorCallback +VOID odm_PSDMonitorCallback(PRT_TIMER pTimer); + +VOID +odm_PSDMonitorWorkItemCallback( + IN PVOID pContext + ); + +VOID +PatchDCTone( + IN PDM_ODM_T pDM_Odm, + pu4Byte PSD_report, + u1Byte initial_gain_psd +); +VOID +ODM_PSDMonitor( + IN PDM_ODM_T pDM_Odm + ); +VOID odm_PSD_Monitor(PDM_ODM_T pDM_Odm); +VOID odm_PSDMonitorInit(PDM_ODM_T pDM_Odm); + +VOID +ODM_PSDDbgControl( + IN PADAPTER Adapter, + IN u4Byte mode, + IN u4Byte btRssi + ); + +#endif // DM_ODM_SUPPORT_TYPE + + +#if (BEAMFORMING_SUPPORT == 1) +BEAMFORMING_CAP +Beamforming_GetEntryBeamCapByMacId( + IN PMGNT_INFO pMgntInfo, + IN u1Byte MacId + ); +#endif + +VOID ODM_DMInit( IN PDM_ODM_T pDM_Odm); + +VOID +ODM_DMWatchdog( + IN PDM_ODM_T pDM_Odm // For common use in the future + ); + +VOID +ODM_CmnInfoInit( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u4Byte Value + ); + +VOID +ODM_CmnInfoHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN PVOID pValue + ); + +VOID +ODM_CmnInfoPtrArrayHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u2Byte Index, + IN PVOID pValue + ); + +VOID +ODM_CmnInfoUpdate( + IN PDM_ODM_T pDM_Odm, + IN u4Byte CmnInfo, + IN u8Byte Value + ); + +VOID +ODM_InitAllTimers( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_CancelAllTimers( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_ReleaseAllTimers( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_ResetIQKResult( + IN PDM_ODM_T pDM_Odm + ); + +VOID phydm_NoisyDetection( + IN PDM_ODM_T pDM_Odm + ); + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ); +VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ); + + +//===========================================// +// Neil Chen----2011--06--15-- + +//3 Path Diversity +//=========================================================== + +#define TP_MODE 0 +#define RSSI_MODE 1 +#define TRAFFIC_LOW 0 +#define TRAFFIC_HIGH 1 + +//#define PATHDIV_ENABLE 1 +//#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi + +u8Byte +PlatformDivision64( + IN u8Byte x, + IN u8Byte y +); + + +// 20100514 Joseph: Add definition for antenna switching test after link. +// This indicates two different the steps. +// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. +// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK +// with original RSSI to determine if it is necessary to switch antenna. +#define SWAW_STEP_PEAK 0 +#define SWAW_STEP_DETERMINE 1 + +//==================================================== +//3 PathDiV End +//==================================================== + +//#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C + +#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh +//void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter, +// IN INT32 DM_Type, +// IN INT32 DM_Value); +// + + +typedef enum tag_DIG_Connect_Definition +{ + DIG_STA_DISCONNECT = 0, + DIG_STA_CONNECT = 1, + DIG_STA_BEFORE_CONNECT = 2, + DIG_MultiSTA_DISCONNECT = 3, + DIG_MultiSTA_CONNECT = 4, + DIG_CONNECT_MAX +}DM_DIG_CONNECT_E; + + + +// +// 2012/01/12 MH Check afapter status. Temp fix BSOD. +// +#define HAL_ADAPTER_STS_CHK(pDM_Odm)\ + if (pDM_Odm->Adapter == NULL)\ + {\ + return;\ + }\ + + +// +// For new definition in MP temporarily fro power tracking, +// +#define odm_TXPowerTrackingDirectCall(_Adapter) \ + IS_HARDWARE_TYPE_8192D(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92D(_Adapter) : \ + IS_HARDWARE_TYPE_8192C(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92C(_Adapter) : \ + IS_HARDWARE_TYPE_8723A(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_8723A(_Adapter) :\ + ODM_TXPowerTrackingCallback_ThermalMeter(_Adapter) + +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + +#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) + +VOID +ODM_SingleDualAntennaDefaultSetting( + IN PDM_ODM_T pDM_Odm + ); + +BOOLEAN +ODM_SingleDualAntennaDetection( + IN PDM_ODM_T pDM_Odm, + IN u1Byte mode + ); + +#endif // #if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE)) +VOID +ODM_UpdateNoisyState( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN bNoisyStateFromC2H +); + +u4Byte +Set_RA_DM_Ratrbitmap_by_Noisy( + IN PDM_ODM_T pDM_Odm, + IN WIRELESS_MODE WirelessMode, + IN u4Byte ratr_bitmap, + IN u1Byte rssi_level +); + +VOID +ODM_UpdateInitRate( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Rate + ); + +//Remove ODM_DynamicARFBSelect() by RS_James + +PVOID +PhyDM_Get_Structure( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Structure_Type +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +void odm_dtc(PDM_ODM_T pDM_Odm); +#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_ACS.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_ACS.h new file mode 100644 index 0000000..f046c49 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_ACS.h @@ -0,0 +1,97 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMACS_H__ +#define __PHYDMACS_H__ + +#include "phydm_types.h" + +#define ACS_VERSION "1.1" /*20150729 by YuChen*/ +#define CLM_VERSION "1.0" + +#define ODM_MAX_CHANNEL_2G 14 +#define ODM_MAX_CHANNEL_5G 24 + +// For phydm_AutoChannelSelectSettingAP() +#define STORE_DEFAULT_NHM_SETTING 0 +#define RESTORE_DEFAULT_NHM_SETTING 1 +#define ACS_NHM_SETTING 2 + +#define ODM_REG_CLM_TIME_PERIOD_11AC 0x990 +#define ODM_REG_CLM_TIME_PERIOD_11N 0x894 +#define ODM_REG_CLM_RESULT_11AC 0xfa4 +#define ODM_REG_CLM_RESULT_11N 0x8d0 +#define ODM_REG_CLM_11AC 0x994 +#define ODM_REG_CLM_11N 0x890 +#define ODM_REG_CLM_READY_11N 0x8b4 + +typedef struct _ACS_ +{ + BOOLEAN bForceACSResult; + u1Byte CleanChannel_2G; + u1Byte CleanChannel_5G; + u2Byte Channel_Info_2G[2][ODM_MAX_CHANNEL_2G]; //Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times + u2Byte Channel_Info_5G[2][ODM_MAX_CHANNEL_5G]; + +#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) + u1Byte ACS_Step; + // NHM Count 0-11 + u1Byte NHM_Cnt[14][11]; + + // AC-Series, for storing previous setting + u4Byte Reg0x990; + u4Byte Reg0x994; + u4Byte Reg0x998; + u4Byte Reg0x99C; + u1Byte Reg0x9A0; // u1Byte + + // N-Series, for storing previous setting + u4Byte Reg0x890; + u4Byte Reg0x894; + u4Byte Reg0x898; + u4Byte Reg0x89C; + u1Byte Reg0xE28; // u1Byte +#endif + +}ACS, *PACS; + +VOID +phydm_CLMInit( + IN PVOID pDM_VOID, + IN u2Byte sampleNum +); + +VOID +phydm_CLMtrigger( + IN PVOID pDM_VOID +); + +BOOLEAN +phydm_checkCLMready( + IN PVOID pDM_VOID +); + +u2Byte +phydm_getCLMresult( + IN PVOID pDM_VOID +); + + +#endif //#ifndef __PHYDMACS_H__ diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_AntDect.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_AntDect.h new file mode 100644 index 0000000..7dc1d6e --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_AntDect.h @@ -0,0 +1,76 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMANTDECT_H__ +#define __PHYDMANTDECT_H__ + +#define ANTDECT_VERSION "1.0" + +#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) +//1 [1. Single Tone Method] =================================================== + + + +VOID +ODM_SingleDualAntennaDefaultSetting( + IN PDM_ODM_T pDM_Odm + ); + +BOOLEAN +ODM_SingleDualAntennaDetection( + IN PDM_ODM_T pDM_Odm, + IN u1Byte mode + ); + +//1 [2. Scan AP RSSI Method] ================================================== + +VOID +odm_SwAntDetectInit( + IN PDM_ODM_T pDM_Odm + ); + + +#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink + +BOOLEAN +ODM_SwAntDivCheckBeforeLink( + IN PDM_ODM_T pDM_Odm + ); + + + + +//1 [3. PSD Method] ========================================================== + + +VOID +ODM_SingleDualAntennaDetection_PSD( + IN PDM_ODM_T pDM_Odm +); + + + + + + +#endif +#endif + + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_AntDiv.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_AntDiv.h new file mode 100644 index 0000000..f762e71 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_AntDiv.h @@ -0,0 +1,144 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMANTDIV_H__ +#define __PHYDMANTDIV_H__ + +#define ANTDIV_VERSION "1.0" + +#define ANT1_2G 0 // = ANT2_5G +#define ANT2_2G 1 // = ANT1_5G + +//Antenna Diversty Control Type +#define ODM_AUTO_ANT 0 +#define ODM_FIX_MAIN_ANT 1 +#define ODM_FIX_AUX_ANT 2 + +#define TX_BY_REG 0 + +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#define ODM_RTL8881A 0 //Just for windows driver to jointly use ODM-driver +#endif + +#define ODM_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812) +#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B) +#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812) +#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E) + +#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A) +#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812) +#define ODM_ANTDIV_2G BIT0 +#define ODM_ANTDIV_5G BIT1 + +#define ANTDIV_ON 1 +#define ANTDIV_OFF 0 + +#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink +VOID ODM_SwAntDivRestAfterLink( IN PDM_ODM_T pDM_Odm); + +VOID +odm_AntennaDiversityReset( + IN PDM_ODM_T pDM_Odm +); + +VOID +ODM_AntDivInit( + IN PDM_ODM_T pDM_Odm +); + +VOID +ODM_AntDiv( + IN PDM_ODM_T pDM_Odm +); + +#if (defined(CONFIG_HW_ANTENNA_DIVERSITY)) + +VOID +ODM_UpdateRxIdleAnt( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Ant +); + +#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +ODM_SW_AntDiv_Callback( + IN PRT_TIMER pTimer +); + +VOID +ODM_SW_AntDiv_WorkitemCallback( + IN PVOID pContext +); +#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +VOID +ODM_SW_AntDiv_Callback(void *FunctionContext); +#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#endif + +#if(RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1) +#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE)) +VOID +odm_FastAntTraining( + IN PDM_ODM_T pDM_Odm +); + +VOID +odm_FastAntTrainingCallback( + IN PDM_ODM_T pDM_Odm +); + +VOID +odm_FastAntTrainingWorkItemCallback( + IN PDM_ODM_T pDM_Odm +); +#endif +#endif + +VOID +ODM_Process_RSSIForAntDiv( + IN OUT PDM_ODM_T pDM_Odm, + IN PODM_PHY_INFO_T pPhyInfo, + IN PODM_PACKET_INFO_T pPktinfo +); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +VOID +ODM_SetTxAntByTxInfo( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pDesc, + IN u1Byte macId +); + +#else// (DM_ODM_SUPPORT_TYPE == ODM_AP) +VOID +ODM_SetTxAntByTxInfo( + //IN PDM_ODM_T pDM_Odm, + struct rtl8192cd_priv *priv, + struct tx_desc *pdesc, + struct tx_insn *txcfg, + unsigned short aid +); + +#endif + +#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY)) +#endif //#ifndef __ODMANTDIV_H__ diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_CfoTracking.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_CfoTracking.h new file mode 100644 index 0000000..3d473d5 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_CfoTracking.h @@ -0,0 +1,73 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMCFOTRACK_H__ +#define __PHYDMCFOTRACK_H__ + +#define CFO_TRACKING_VERSION "1.0" + +//#define CFO_TH_XTAL_HIGH 20 // kHz +//#define CFO_TH_XTAL_LOW 10 // kHz +//#define CFO_TH_ATC 80 // kHz + +#if ((RTL8195A_SUPPORT==0) && (RTL8711B_SUPPORT == 0)) +typedef struct _CFO_TRACKING_ +{ + BOOLEAN bATCStatus; + BOOLEAN largeCFOHit; + BOOLEAN bAdjust; + u1Byte CrystalCap; + u1Byte DefXCap; + int CFO_tail[2]; + int CFO_ave_pre; + u4Byte packetCount; + u4Byte packetCount_pre; + BOOLEAN bForceXtalCap; + BOOLEAN bReset; + u1Byte CFO_TH_XTAL_HIGH; + u1Byte CFO_TH_XTAL_LOW; + u1Byte CFO_TH_ATC; +}CFO_TRACKING, *PCFO_TRACKING; +#endif + +VOID +ODM_CfoTrackingReset( + IN PVOID pDM_VOID +); + +VOID +ODM_CfoTrackingInit( + IN PVOID pDM_VOID +); + +VOID +ODM_CfoTracking( + IN PVOID pDM_VOID +); + +VOID +ODM_ParsingCFO( + IN PVOID pDM_VOID, + IN PVOID pPktinfo_VOID, + IN s1Byte* pcfotail, + IN u1Byte num_ss +); + +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DIG.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DIG.h new file mode 100644 index 0000000..58da5f8 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DIG.h @@ -0,0 +1,476 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODMDIG_H__ +#define __ODMDIG_H__ + +typedef struct _Dynamic_Initial_Gain_Threshold_ +{ + BOOLEAN bStopDIG; // for debug + BOOLEAN bPauseDIG; + BOOLEAN bIgnoreDIG; + BOOLEAN bPSDInProgress; + + u1Byte Dig_Enable_Flag; + u1Byte Dig_Ext_Port_Stage; + + int RssiLowThresh; + int RssiHighThresh; + + u4Byte FALowThresh; + u4Byte FAHighThresh; + + u1Byte CurSTAConnectState; + u1Byte PreSTAConnectState; + u1Byte CurMultiSTAConnectState; + + u1Byte PreIGValue; + u1Byte CurIGValue; + u1Byte BackupIGValue; //MP DIG + u1Byte BT30_CurIGI; + u1Byte IGIBackup; + + s1Byte BackoffVal; + s1Byte BackoffVal_range_max; + s1Byte BackoffVal_range_min; + u1Byte rx_gain_range_max; + u1Byte rx_gain_range_min; + u1Byte Rssi_val_min; + + u1Byte PreCCK_CCAThres; + u1Byte CurCCK_CCAThres; + u1Byte PreCCKPDState; + u1Byte CurCCKPDState; + u1Byte CCKPDBackup; + + u1Byte LargeFAHit; + u1Byte ForbiddenIGI; + u4Byte Recover_cnt; + + u1Byte DIG_Dynamic_MIN_0; + u1Byte DIG_Dynamic_MIN_1; + BOOLEAN bMediaConnect_0; + BOOLEAN bMediaConnect_1; + + u4Byte AntDiv_RSSI_max; + u4Byte RSSI_max; + + u1Byte *pbP2pLinkInProgress; + u4Byte cckFaMa; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + BOOLEAN bTpTarget; + BOOLEAN bNoiseEst; + u4Byte TpTrainTH_min; + u1Byte IGIOffset_A; + u1Byte IGIOffset_B; +#endif +}DIG_T,*pDIG_T; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP|ODM_ADSL)) +typedef struct _FALSE_ALARM_STATISTICS{ + u4Byte Cnt_Parity_Fail; + u4Byte Cnt_Rate_Illegal; + u4Byte Cnt_Crc8_fail; + u4Byte Cnt_Mcs_fail; + u4Byte Cnt_Ofdm_fail; + u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A + u4Byte Cnt_Cck_fail; + u4Byte Cnt_all; + u4Byte Cnt_Fast_Fsync; + u4Byte Cnt_SB_Search_fail; + u4Byte Cnt_OFDM_CCA; + u4Byte Cnt_CCK_CCA; + u4Byte Cnt_CCA_all; + u4Byte Cnt_BW_USC; //Gary + u4Byte Cnt_BW_LSC; //Gary +}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; +#endif + +typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition +{ + DIG_TYPE_THRESH_HIGH = 0, + DIG_TYPE_THRESH_LOW = 1, + DIG_TYPE_BACKOFF = 2, + DIG_TYPE_RX_GAIN_MIN = 3, + DIG_TYPE_RX_GAIN_MAX = 4, + DIG_TYPE_ENABLE = 5, + DIG_TYPE_DISABLE = 6, + DIG_OP_TYPE_MAX +}DM_DIG_OP_E; + +typedef enum tag_ODM_PauseDIG_Type { + ODM_PAUSE_DIG = BIT0, + ODM_RESUME_DIG = BIT1 +} ODM_Pause_DIG_TYPE; + +typedef enum tag_ODM_PauseCCKPD_Type { + ODM_PAUSE_CCKPD = BIT0, + ODM_RESUME_CCKPD = BIT1 +} ODM_Pause_CCKPD_TYPE; + +typedef enum tag_ODM_TRx_MUX_Type +{ + ODM_SHUTDOWN = 0, + ODM_STANDBY_MODE = 1, + ODM_TX_MODE = 2, + ODM_RX_MODE = 3 +}ODM_Trx_MUX_Type; + +typedef enum tag_ODM_MACEDCCA_Type +{ + ODM_IGNORE_EDCCA = 0, + ODM_DONT_IGNORE_EDCCA = 1 +}ODM_MACEDCCA_Type; + +/* +typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition +{ + CCK_PD_STAGE_LowRssi = 0, + CCK_PD_STAGE_HighRssi = 1, + CCK_PD_STAGE_MAX = 3, +}DM_CCK_PDTH_E; + +typedef enum tag_DIG_EXT_PORT_ALGO_Definition +{ + DIG_EXT_PORT_STAGE_0 = 0, + DIG_EXT_PORT_STAGE_1 = 1, + DIG_EXT_PORT_STAGE_2 = 2, + DIG_EXT_PORT_STAGE_3 = 3, + DIG_EXT_PORT_STAGE_MAX = 4, +}DM_DIG_EXT_PORT_ALG_E; + +typedef enum tag_DIG_Connect_Definition +{ + DIG_STA_DISCONNECT = 0, + DIG_STA_CONNECT = 1, + DIG_STA_BEFORE_CONNECT = 2, + DIG_MultiSTA_DISCONNECT = 3, + DIG_MultiSTA_CONNECT = 4, + DIG_CONNECT_MAX +}DM_DIG_CONNECT_E; + + +#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} + +#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \ + DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT) + +#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \ + DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT) +*/ +#define DM_DIG_THRESH_HIGH 40 +#define DM_DIG_THRESH_LOW 35 + +#define DM_FALSEALARM_THRESH_LOW 400 +#define DM_FALSEALARM_THRESH_HIGH 1000 + +#define DM_DIG_MAX_NIC 0x3e +#define DM_DIG_MIN_NIC 0x20 //0x1e +#define DM_DIG_MAX_OF_MIN_NIC 0x3e + +#define DM_DIG_MAX_AP 0x3e +#define DM_DIG_MIN_AP 0x1c +#define DM_DIG_MAX_OF_MIN 0x2A //0x32 +#define DM_DIG_MIN_AP_DFS 0x20 + +#define DM_DIG_MAX_NIC_HP 0x46 +#define DM_DIG_MIN_NIC_HP 0x2e + +#define DM_DIG_MAX_AP_HP 0x42 +#define DM_DIG_MIN_AP_HP 0x30 + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#define DM_DIG_MAX_AP_COVERAGR 0x26 +#define DM_DIG_MIN_AP_COVERAGE 0x1c +#define DM_DIG_MAX_OF_MIN_COVERAGE 0x22 + +#define DM_DIG_TP_Target_TH0 500 +#define DM_DIG_TP_Target_TH1 1000 +#define DM_DIG_TP_Training_Period 10 +#endif + +//vivi 92c&92d has different definition, 20110504 +//this is for 92c +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_IOT)) + #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV + #define DM_DIG_FA_TH0 0x80//0x20 + #else + #define DM_DIG_FA_TH0 0x200//0x20 + #endif +#else + #define DM_DIG_FA_TH0 0x200//0x20 +#endif + +#define DM_DIG_FA_TH1 0x300 +#define DM_DIG_FA_TH2 0x400 +//this is for 92d +#define DM_DIG_FA_TH0_92D 0x100 +#define DM_DIG_FA_TH1_92D 0x400 +#define DM_DIG_FA_TH2_92D 0x600 + +#define DM_DIG_BACKOFF_MAX 12 +#define DM_DIG_BACKOFF_MIN -4 +#define DM_DIG_BACKOFF_DEFAULT 10 + +#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps +#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps +#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps +#define RSSI_OFFSET_DIG 0x05 + + +VOID +odm_CheckAdaptivity( + IN PVOID pDM_VOID + ); + +VOID +odm_CheckEnvironment( + IN PVOID pDM_VOID + ); + +VOID +ODM_ChangeDynamicInitGainThresh( + IN PVOID pDM_VOID, + IN u4Byte DM_Type, + IN u4Byte DM_Value + ); + +VOID +odm_NHMCounterStatisticsInit( + IN PVOID pDM_VOID + ); + +VOID +odm_NHMCounterStatistics( + IN PVOID pDM_VOID + ); + +VOID +odm_NHMBBInit( + IN PVOID pDM_VOID +); + +VOID +odm_NHMBB( + IN PVOID pDM_VOID +); + +VOID +odm_NHMCounterStatisticsReset( + IN PVOID pDM_VOID +); + +VOID +odm_GetNHMCounterStatistics( + IN PVOID pDM_VOID +); + +VOID +odm_MACEDCCAState( + IN PVOID pDM_VOID, + IN ODM_MACEDCCA_Type State +); + +VOID +odm_SetEDCCAThreshold( + IN PVOID pDM_VOID, + IN s1Byte H2L, + IN s1Byte L2H +); + +VOID +odm_SetTRxMux( + IN PVOID pDM_VOID, + IN ODM_Trx_MUX_Type txMode, + IN ODM_Trx_MUX_Type rxMode +); + +BOOLEAN +odm_CalNHMcnt( + IN PVOID pDM_VOID + ); + +VOID +odm_SearchPwdBLowerBound( + IN PVOID pDM_VOID +); + +VOID +odm_AdaptivityInit( + IN PVOID pDM_VOID + ); + +BOOLEAN +odm_Adaptivity( + IN PVOID pDM_VOID, + IN u1Byte IGI + ); + +VOID +ODM_Write_DIG( + IN PVOID pDM_VOID, + IN u1Byte CurrentIGI + ); + +VOID +odm_PauseDIG( + IN PVOID pDM_VOID, + IN ODM_Pause_DIG_TYPE PauseType, + IN u1Byte IGIValue + ); + +VOID +odm_DIGInit( + IN PVOID pDM_VOID + ); + +VOID +odm_DIG( + IN PVOID pDM_VOID + ); + +VOID +odm_DIGbyRSSI_LPS( + IN PVOID pDM_VOID + ); + +VOID +odm_DigForBtHsMode( + IN PVOID pDM_VOID + ); + +VOID +odm_FalseAlarmCounterStatistics( + IN PVOID pDM_VOID + ); + +#if (DM_ODM_SUPPORT_TYPE & ODM_IOT) +VOID +odm_FAThresholdCheck( + IN PVOID pDM_VOID, + OUT u4Byte* dm_FA_thres + ); +#else +VOID +odm_FAThresholdCheck( + IN PVOID pDM_VOID, + IN BOOLEAN bDFSBand, + IN BOOLEAN bPerformance, + IN u4Byte RxTp, + IN u4Byte TxTp, + OUT u4Byte* dm_FA_thres + ); +#endif +u1Byte +odm_ForbiddenIGICheck( + IN PVOID pDM_VOID, + IN u1Byte DIG_Dynamic_MIN, + IN u1Byte CurrentIGI + ); + +VOID +odm_InbandNoiseCalculate ( + IN PVOID pDM_VOID + ); + +BOOLEAN +odm_DigAbort( + IN PVOID pDM_VOID + ); + +VOID +odm_PauseCCKPacketDetection( + IN PVOID pDM_VOID, + IN ODM_Pause_CCKPD_TYPE PauseType, + IN u1Byte CCKPDThreshold + ); + +VOID +odm_CCKPacketDetectionThresh( + IN PVOID pDM_VOID + ); + +VOID +ODM_Write_CCK_CCA_Thres( + IN PVOID pDM_VOID, + IN u1Byte CurCCK_CCAThres + ); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +odm_DisableEDCCA( + IN PVOID pDM_VOID +); + +VOID +odm_DynamicEDCCA( + IN PVOID pDM_VOID +); + +VOID +odm_MPT_DIGCallback( + PRT_TIMER pTimer +); + +VOID +odm_MPT_DIGWorkItemCallback( + IN PVOID pContext + ); + +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +VOID +odm_MPT_DIGCallback( + IN PVOID pDM_VOID +); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL)) +VOID +ODM_MPT_DIG( + IN PVOID pDM_VOID +); +#endif + + +#endif + +VOID +odm_DIGInit_8195A( + IN PVOID pDM_VOID + ); + +VOID +odm_DIG_8195A( + IN PVOID pDM_VOID + ); + +VOID +odm_FalseAlarmCounterStatistics_8195A( + IN PVOID pDM_VOID + ); + +VOID +odm_CCKPacketDetectionThresh_8195A( + IN PVOID pDM_VOID + ); \ No newline at end of file diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DynamicBBPowerSaving.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DynamicBBPowerSaving.h new file mode 100644 index 0000000..bf473f9 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DynamicBBPowerSaving.h @@ -0,0 +1,63 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMDYNAMICBBPOWERSAVING_H__ +#define __PHYDMDYNAMICBBPOWERSAVING_H__ + +#define DYNAMIC_BBPWRSAV_VERSION "1.0" + +typedef struct _Dynamic_Power_Saving_ +{ + u1Byte PreCCAState; + u1Byte CurCCAState; + + u1Byte PreRFState; + u1Byte CurRFState; + + int Rssi_val_min; + + u1Byte initialize; + u4Byte Reg874,RegC70,Reg85C,RegA74; + +}PS_T,*pPS_T; + +#define dm_RF_Saving ODM_RF_Saving + +void ODM_RF_Saving( + IN PVOID pDM_VOID, + IN u1Byte bForceInNormal + ); + +VOID +odm_DynamicBBPowerSavingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicBBPowerSaving( + IN PVOID pDM_VOID + ); + +VOID +odm_1R_CCA( + IN PVOID pDM_VOID + ); + +#endif \ No newline at end of file diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DynamicTxPower.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DynamicTxPower.h new file mode 100644 index 0000000..9a38013 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DynamicTxPower.h @@ -0,0 +1,89 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMDYNAMICTXPOWER_H__ +#define __PHYDMDYNAMICTXPOWER_H__ + +#define DYNAMIC_TXPWR_VERSION "1.0" + +#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 +#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 +#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F +#define TX_POWER_NEAR_FIELD_THRESH_8812 60 + +#define TxHighPwrLevel_Normal 0 +#define TxHighPwrLevel_Level1 1 +#define TxHighPwrLevel_Level2 2 +#define TxHighPwrLevel_BT1 3 +#define TxHighPwrLevel_BT2 4 +#define TxHighPwrLevel_15 5 +#define TxHighPwrLevel_35 6 +#define TxHighPwrLevel_50 7 +#define TxHighPwrLevel_70 8 +#define TxHighPwrLevel_100 9 + +VOID +odm_DynamicTxPowerInit( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerRestorePowerIndex( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerNIC( + IN PVOID pDM_VOID + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +VOID +odm_DynamicTxPowerSavePowerIndex( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerWritePowerIndex( + IN PVOID pDM_VOID, + IN u1Byte Value); + +VOID +odm_DynamicTxPower_92C( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPower_92D( + IN PVOID pDM_VOID + ); +#endif + +VOID +odm_DynamicTxPower( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerAP( + IN PVOID pDM_VOID + ); + +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_EdcaTurboCheck.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_EdcaTurboCheck.h new file mode 100644 index 0000000..65be74f --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_EdcaTurboCheck.h @@ -0,0 +1,152 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMEDCATURBOCHECK_H__ +#define __PHYDMEDCATURBOCHECK_H__ + +#define EDCATURBO_VERSION "1.0" + +typedef struct _EDCA_TURBO_ +{ + BOOLEAN bCurrentTurboEDCA; + BOOLEAN bIsCurRDLState; + + #if(DM_ODM_SUPPORT_TYPE == ODM_CE ) + u4Byte prv_traffic_idx; // edca turbo + #endif + +}EDCA_T,*pEDCA_T; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] = +// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU MARVELL 92U_AP SELF_AP(DownLink/Tx) +{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322}; + + +static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] = +// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP(UpLink/Rx) +{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b}; + +static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] = +// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP +{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b}; + + +//============================================================ +// EDCA Paramter for AP/ADSL by Mingzhi 2011-11-22 +//============================================================ +#elif (DM_ODM_SUPPORT_TYPE &ODM_ADSL) +enum qos_prio { BK, BE, VI, VO, VI_AG, VO_AG }; + +static const struct ParaRecord rtl_ap_EDCA[] = +{ +//ACM,AIFSN, ECWmin, ECWmax, TXOplimit + {0, 7, 4, 10, 0}, //BK + {0, 3, 4, 6, 0}, //BE + {0, 1, 3, 4, 188}, //VI + {0, 1, 2, 3, 102}, //VO + {0, 1, 3, 4, 94}, //VI_AG + {0, 1, 2, 3, 47}, //VO_AG +}; + +static const struct ParaRecord rtl_sta_EDCA[] = +{ +//ACM,AIFSN, ECWmin, ECWmax, TXOplimit + {0, 7, 4, 10, 0}, + {0, 3, 4, 10, 0}, + {0, 2, 3, 4, 188}, + {0, 2, 2, 3, 102}, + {0, 2, 3, 4, 94}, + {0, 2, 2, 3, 47}, +}; +#endif + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#ifdef WIFI_WMM +VOID +ODM_IotEdcaSwitch( + IN PVOID pDM_VOID, + IN unsigned char enable + ); +#endif + +BOOLEAN +ODM_ChooseIotMainSTA( + IN PVOID pDM_VOID, + IN PSTA_INFO_T pstat + ); +#endif + +VOID +odm_EdcaTurboCheck( + IN PVOID pDM_VOID + ); +VOID +ODM_EdcaTurboInit( + IN PVOID pDM_VOID +); + +#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) +VOID +odm_EdcaTurboCheckMP( + IN PVOID pDM_VOID + ); + +//check if edca turbo is disabled +BOOLEAN +odm_IsEdcaTurboDisable( + IN PVOID pDM_VOID +); +//choose edca paramter for special IOT case +VOID +ODM_EdcaParaSelByIot( + IN PVOID pDM_VOID, + OUT u4Byte *EDCA_BE_UL, + OUT u4Byte *EDCA_BE_DL + ); +//check if it is UL or DL +VOID +odm_EdcaChooseTrafficIdx( + IN PVOID pDM_VOID, + IN u8Byte cur_tx_bytes, + IN u8Byte cur_rx_bytes, + IN BOOLEAN bBiasOnRx, + OUT BOOLEAN *pbIsCurRDLState + ); + +#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) +VOID +odm_EdcaTurboCheckCE( + IN PVOID pDM_VOID + ); +#else +VOID +odm_IotEngine( + IN PVOID pDM_VOID + ); + +VOID +odm_EdcaParaInit( + IN PVOID pDM_VOID + ); +#endif + +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_HWConfig.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_HWConfig.h new file mode 100644 index 0000000..6d33de1 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_HWConfig.h @@ -0,0 +1,508 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __HALHWOUTSRC_H__ +#define __HALHWOUTSRC_H__ + + +/*--------------------------Define -------------------------------------------*/ +//#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) +#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \ + sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte))) +#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \ + sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte))) + +#define AGC_DIFF_CONFIG(ic, band) do {\ + if (pDM_Odm->bIsMPChip)\ + AGC_DIFF_CONFIG_MP(ic,band);\ + else\ + AGC_DIFF_CONFIG_TC(ic,band);\ + } while(0) + + +//============================================================ +// structure and define +//============================================================ + +typedef struct _Phy_Rx_AGC_Info +{ + #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte gain:7,trsw:1; + #else + u1Byte trsw:1,gain:7; + #endif +} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T; + +typedef struct _Phy_Status_Rpt_8192cd +{ + PHY_RX_AGC_INFO_T path_agc[2]; + u1Byte ch_corr[2]; + u1Byte cck_sig_qual_ofdm_pwdb_all; + u1Byte cck_agc_rpt_ofdm_cfosho_a; + u1Byte cck_rpt_b_ofdm_cfosho_b; + u1Byte rsvd_1;//ch_corr_msb; + u1Byte noise_power_db_msb; + s1Byte path_cfotail[2]; + u1Byte pcts_mask[2]; + s1Byte stream_rxevm[2]; + u1Byte path_rxsnr[2]; + u1Byte noise_power_db_lsb; + u1Byte rsvd_2[3]; + u1Byte stream_csi[2]; + u1Byte stream_target_csi[2]; + s1Byte sig_evm; + u1Byte rsvd_3; + +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1; + u1Byte sgi_en:1; + u1Byte rxsc:2; + u1Byte idle_long:1; + u1Byte r_ant_train_en:1; + u1Byte ant_sel_b:1; + u1Byte ant_sel:1; +#else // _BIG_ENDIAN_ + u1Byte ant_sel:1; + u1Byte ant_sel_b:1; + u1Byte r_ant_train_en:1; + u1Byte idle_long:1; + u1Byte rxsc:2; + u1Byte sgi_en:1; + u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1; +#endif +} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T; + + +typedef struct _Phy_Status_Rpt_8812 +{ +#if 0 + PHY_RX_AGC_INFO_T path_agc[2]; + u1Byte ch_num[2]; + u1Byte cck_sig_qual_ofdm_pwdb_all; + u1Byte cck_agc_rpt_ofdm_cfosho_a; + u1Byte cck_bb_pwr_ofdm_cfosho_b; + u1Byte cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition) + u1Byte rsvd_1; + u1Byte path_cfotail[2]; + u1Byte pcts_mask[2]; + s1Byte stream_rxevm[2]; + u1Byte path_rxsnr[2]; + u1Byte rsvd_2[2]; + u1Byte stream_snr[2]; + u1Byte stream_csi[2]; + u1Byte rsvd_3[2]; + s1Byte sig_evm; + u1Byte rsvd_4; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_anta:3; + u1Byte antidx_antb:3; + u1Byte rsvd_5:2; +#else // _BIG_ENDIAN_ + u1Byte rsvd_5:2; + u1Byte antidx_antb:3; + u1Byte antidx_anta:3; +#endif +#endif + + //2012.05.24 LukeLee: This structure should take big/little endian in consideration later..... + + //DWORD 0 + u1Byte gain_trsw[2]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u2Byte chl_num:10; + u2Byte sub_chnl:4; + u2Byte r_RFMOD:2; +#else // _BIG_ENDIAN_ + u2Byte r_RFMOD:2; + u2Byte sub_chnl:4; + u2Byte chl_num:10; +#endif + + //DWORD 1 + u1Byte pwdb_all; + u1Byte cfosho[4]; // DW 1 byte 1 DW 2 byte 0 + + //DWORD 2 + s1Byte cfotail[4]; // DW 2 byte 1 DW 3 byte 0 + + //DWORD 3 + s1Byte rxevm[2]; // DW 3 byte 1 DW 3 byte 2 + s1Byte rxsnr[2]; // DW 3 byte 3 DW 4 byte 0 + + //DWORD 4 + u1Byte PCTS_MSK_RPT[2]; + u1Byte pdsnr[2]; // DW 4 byte 3 DW 5 Byte 0 + + //DWORD 5 + u1Byte csi_current[2]; + u1Byte rx_gain_c; + + //DWORD 6 + u1Byte rx_gain_d; + s1Byte sigevm; + u1Byte resvd_0; + u1Byte antidx_anta:3; + u1Byte antidx_antb:3; + u1Byte resvd_1:2; +} PHY_STATUS_RPT_8812_T,*PPHY_STATUS_RPT_8812_T; + + +VOID +odm_Init_RSSIForDM( + IN OUT PDM_ODM_T pDM_Odm + ); + +VOID +ODM_PhyStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ); + +VOID +ODM_MacStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + IN pu1Byte pMacStatus, + IN u1Byte MacID, + IN BOOLEAN bPacketMatchBSSID, + IN BOOLEAN bPacketToSelf, + IN BOOLEAN bPacketBeacon + ); +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP|ODM_IOT)) + +HAL_STATUS +ODM_ConfigRFWithTxPwrTrackHeaderFile( + IN PDM_ODM_T pDM_Odm + ); + +HAL_STATUS +ODM_ConfigRFWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_Config_Type ConfigType, + IN ODM_RF_RADIO_PATH_E eRFPath + ); + +HAL_STATUS +ODM_ConfigBBWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_BB_Config_Type ConfigType + ); + +HAL_STATUS +ODM_ConfigMACWithHeaderFile( + IN PDM_ODM_T pDM_Odm + ); + +HAL_STATUS +ODM_ConfigFWWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_FW_Config_Type ConfigType, + OUT u1Byte *pFirmware, + OUT u4Byte *pSize + ); + +u4Byte +ODM_GetHWImgVersion( + IN PDM_ODM_T pDM_Odm + ); + +s4Byte +odm_SignalScaleMapping( + IN OUT PDM_ODM_T pDM_Odm, + IN s4Byte CurrSig + ); + +#endif + +#if(ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) +//For New RX PHY Status Report Format, include 8723D/8710B +VOID +phydm_RxPhyStatusNewType( + IN PDM_ODM_T pPhydm, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo, + OUT PODM_PHY_INFO_T pPhyInfo +); + +typedef struct _Phy_Status_Rpt_Jaguar2_Type0 { + /* DW0 */ + u1Byte page_num; + u1Byte pwdb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte gain: 6; + u1Byte rsvd_0: 1; + u1Byte trsw: 1; +#else + u1Byte trsw: 1; + u1Byte rsvd_0: 1; + u1Byte gain: 6; +#endif + u1Byte rsvd_1; + + /* DW1 */ + u1Byte rsvd_2; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte rxsc: 4; + u1Byte agc_table: 4; +#else + u1Byte agc_table: 4; + u1Byte rxsc: 4; +#endif + u1Byte channel; + u1Byte band; + + /* DW2 */ + u2Byte length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_a: 3; + u1Byte antidx_b: 3; + u1Byte rsvd_3: 2; + u1Byte antidx_c: 3; + u1Byte antidx_d: 3; + u1Byte rsvd_4:2; +#else + u1Byte rsvd_3: 2; + u1Byte antidx_b: 3; + u1Byte antidx_a: 3; + u1Byte rsvd_4:2; + u1Byte antidx_d: 3; + u1Byte antidx_c: 3; +#endif + + /* DW3 */ + u1Byte signal_quality; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte vga:5; + u1Byte lna_l:3; + u1Byte bb_power:6; + u1Byte rsvd_9:1; + u1Byte lna_h:1; +#else + u1Byte lna_l:3; + u1Byte vga:5; + u1Byte lna_h:1; + u1Byte rsvd_9:1; + u1Byte bb_power:6; +#endif + u1Byte rsvd_5; + + /* DW4 */ + u4Byte rsvd_6; + + /* DW5 */ + u4Byte rsvd_7; + + /* DW6 */ + u4Byte rsvd_8; +} PHY_STATUS_RPT_JAGUAR2_TYPE0, *PPHY_STATUS_RPT_JAGUAR2_TYPE0; //for CCK Format + +typedef struct _Phy_Status_Rpt_Jaguar2_Type1 { + /* DW0 and DW1 */ + u1Byte page_num; + u1Byte pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte l_rxsc: 4; + u1Byte ht_rxsc: 4; +#else + u1Byte ht_rxsc: 4; + u1Byte l_rxsc: 4; +#endif + u1Byte channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte band: 2; + u1Byte rsvd_0: 1; + u1Byte hw_antsw_occu: 1; + u1Byte gnt_bt: 1; + u1Byte ldpc: 1; + u1Byte stbc: 1; + u1Byte beamformed: 1; +#else + u1Byte beamformed: 1; + u1Byte stbc: 1; + u1Byte ldpc: 1; + u1Byte gnt_bt: 1; + u1Byte hw_antsw_occu: 1; + u1Byte rsvd_0: 1; + u1Byte band: 2; +#endif + + /* DW2 */ + u2Byte lsig_length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_a: 3; + u1Byte antidx_b: 3; + u1Byte rsvd_1: 2; + u1Byte antidx_c: 3; + u1Byte antidx_d: 3; + u1Byte rsvd_2: 2; +#else + u1Byte rsvd_1: 2; + u1Byte antidx_b: 3; + u1Byte antidx_a: 3; + u1Byte rsvd_2: 2; + u1Byte antidx_d: 3; + u1Byte antidx_c: 3; +#endif + + /* DW3 */ + u1Byte paid; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte paid_msb: 1; + u1Byte gid: 6; + u1Byte rsvd_3: 1; +#else + u1Byte rsvd_3: 1; + u1Byte gid: 6; + u1Byte paid_msb: 1; +#endif + u1Byte intf_pos; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte intf_pos_msb: 1; + u1Byte rsvd_4: 2; + u1Byte nb_intf_flag: 1; + u1Byte rf_mode: 2; + u1Byte rsvd_5: 2; +#else + u1Byte rsvd_5: 2; + u1Byte rf_mode: 2; + u1Byte nb_intf_flag: 1; + u1Byte rsvd_4: 2; + u1Byte intf_pos_msb: 1; +#endif + + /* DW4 */ + s1Byte rxevm[4]; /* s(8,1) */ + + /* DW5 */ + s1Byte cfo_tail[4]; /* s(8,7) */ + + /* DW6 */ + s1Byte rxsnr[4]; /* s(8,1) */ +} PHY_STATUS_RPT_JAGUAR2_TYPE1, *PPHY_STATUS_RPT_JAGUAR2_TYPE1;//for OFDM Format + +typedef struct _Phy_Status_Rpt_Jaguar2_Type2 { + /* DW0 ane DW1 */ + u1Byte page_num; + u1Byte pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte l_rxsc: 4; + u1Byte ht_rxsc: 4; +#else + u1Byte ht_rxsc: 4; + u1Byte l_rxsc: 4; +#endif + u1Byte channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte band: 2; + u1Byte rsvd_0: 1; + u1Byte hw_antsw_occu: 1; + u1Byte gnt_bt: 1; + u1Byte ldpc: 1; + u1Byte stbc: 1; + u1Byte beamformed: 1; +#else + u1Byte beamformed: 1; + u1Byte stbc: 1; + u1Byte ldpc: 1; + u1Byte gnt_bt: 1; + u1Byte hw_antsw_occu: 1; + u1Byte rsvd_0: 1; + u1Byte band: 2; +#endif + + /* DW2 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte shift_l_map: 6; + u1Byte rsvd_1: 2; +#else + u1Byte rsvd_1: 2; + u1Byte shift_l_map: 6; +#endif + u1Byte cnt_pw2cca; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte agc_table_a: 4; + u1Byte agc_table_b: 4; + u1Byte agc_table_c: 4; + u1Byte agc_table_d: 4; +#else + u1Byte agc_table_b: 4; + u1Byte agc_table_a: 4; + u1Byte agc_table_d: 4; + u1Byte agc_table_c: 4; +#endif + + /* DW3 ~ DW6*/ + u1Byte cnt_cca2agc_rdy; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte gain_a: 6; + u1Byte rsvd_2: 1; + u1Byte trsw_a: 1; + u1Byte gain_b: 6; + u1Byte rsvd_3: 1; + u1Byte trsw_b: 1; + u1Byte gain_c: 6; + u1Byte rsvd_4: 1; + u1Byte trsw_c: 1; + u1Byte gain_d: 6; + u1Byte rsvd_5: 1; + u1Byte trsw_d: 1; + u1Byte aagc_step_a: 2; + u1Byte aagc_step_b: 2; + u1Byte aagc_step_c: 2; + u1Byte aagc_step_d: 2; +#else + u1Byte trsw_a: 1; + u1Byte rsvd_2: 1; + u1Byte gain_a: 6; + u1Byte trsw_b: 1; + u1Byte rsvd_3: 1; + u1Byte gain_b: 6; + u1Byte trsw_c: 1; + u1Byte rsvd_4: 1; + u1Byte gain_c: 6; + u1Byte trsw_d: 1; + u1Byte rsvd_5: 1; + u1Byte gain_d: 6; + u1Byte aagc_step_d: 2; + u1Byte aagc_step_c: 2; + u1Byte aagc_step_b: 2; + u1Byte aagc_step_a: 2; +#endif + u1Byte ht_aagc_gain[4]; + u1Byte dagc_gain[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte counter: 6; + u1Byte rsvd_6: 2; + u1Byte syn_count: 5; + u1Byte rsvd_7:3; +#else + u1Byte rsvd_6: 2; + u1Byte counter: 6; + u1Byte rsvd_7:3; + u1Byte syn_count: 5; +#endif +} PHY_STATUS_RPT_JAGUAR2_TYPE2, *PPHY_STATUS_RPT_JAGUAR2_TYPE2;//for debug mode: AGC&SBD + +#endif + +#endif /*#ifndef __HALHWOUTSRC_H__*/ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_NoiseMonitor.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_NoiseMonitor.h new file mode 100644 index 0000000..022cefe --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_NoiseMonitor.h @@ -0,0 +1,49 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + *****************************************************************************/ +#ifndef __ODMNOISEMONITOR_H__ +#define __ODMNOISEMONITOR_H__ + +#define ODM_MAX_CHANNEL_NUM 38//14+24 +struct noise_level +{ + //u1Byte value_a, value_b; + u1Byte value[MAX_RF_PATH]; + //s1Byte sval_a, sval_b; + s1Byte sval[MAX_RF_PATH]; + + //s4Byte noise_a=0, noise_b=0,sum_a=0, sum_b=0; + //s4Byte noise[ODM_RF_PATH_MAX]; + s4Byte sum[MAX_RF_PATH]; + //u1Byte valid_cnt_a=0, valid_cnt_b=0, + u1Byte valid[MAX_RF_PATH]; + u1Byte valid_cnt[MAX_RF_PATH]; + +}; + + +typedef struct _ODM_NOISE_MONITOR_ +{ + s1Byte noise[MAX_RF_PATH]; + s2Byte noise_all; +}ODM_NOISE_MONITOR; + +s2Byte ODM_InbandNoise_Monitor(PVOID pDM_VOID,u8 bPauseDIG,u8 IGIValue,u32 max_time); + +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_PathDiv.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_PathDiv.h new file mode 100644 index 0000000..693f413 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_PathDiv.h @@ -0,0 +1,193 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPATHDIV_H__ +#define __PHYDMPATHDIV_H__ + +#define PATHDIV_VERSION "1.0" + +VOID +odm_PathDiversityInit( + IN PVOID pDM_VOID + ); + +VOID +odm_PathDiversity( + IN PVOID pDM_VOID + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +//#define PATHDIV_ENABLE 1 +#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi +#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C + +typedef struct _PathDiv_Parameter_define_ +{ + u4Byte org_5g_RegE30; + u4Byte org_5g_RegC14; + u4Byte org_5g_RegCA0; + u4Byte swt_5g_RegE30; + u4Byte swt_5g_RegC14; + u4Byte swt_5g_RegCA0; + //for 2G IQK information + u4Byte org_2g_RegC80; + u4Byte org_2g_RegC4C; + u4Byte org_2g_RegC94; + u4Byte org_2g_RegC14; + u4Byte org_2g_RegCA0; + + u4Byte swt_2g_RegC80; + u4Byte swt_2g_RegC4C; + u4Byte swt_2g_RegC94; + u4Byte swt_2g_RegC14; + u4Byte swt_2g_RegCA0; +}PATHDIV_PARA,*pPATHDIV_PARA; + +VOID +odm_PathDiversityInit_92C( + IN PADAPTER Adapter + ); + +VOID +odm_2TPathDiversityInit_92C( + IN PADAPTER Adapter + ); + +VOID +odm_1TPathDiversityInit_92C( + IN PADAPTER Adapter + ); + +BOOLEAN +odm_IsConnected_92C( + IN PADAPTER Adapter + ); + +BOOLEAN +ODM_PathDiversityBeforeLink92C( + //IN PADAPTER Adapter + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_PathDiversityAfterLink_92C( + IN PADAPTER Adapter + ); + +VOID +odm_SetRespPath_92C( + IN PADAPTER Adapter, + IN u1Byte DefaultRespPath + ); + +VOID +odm_OFDMTXPathDiversity_92C( + IN PADAPTER Adapter + ); + +VOID +odm_CCKTXPathDiversity_92C( + IN PADAPTER Adapter + ); + +VOID +odm_ResetPathDiversity_92C( + IN PADAPTER Adapter + ); + +VOID +odm_CCKTXPathDiversityCallback( + PRT_TIMER pTimer + ); + +VOID +odm_CCKTXPathDiversityWorkItemCallback( + IN PVOID pContext + ); + +VOID +odm_PathDivChkAntSwitchCallback( + PRT_TIMER pTimer + ); + +VOID +odm_PathDivChkAntSwitchWorkitemCallback( + IN PVOID pContext + ); + + +VOID +odm_PathDivChkAntSwitch( + PDM_ODM_T pDM_Odm + ); + +VOID +ODM_CCKPathDiversityChkPerPktRssi( + PADAPTER Adapter, + BOOLEAN bIsDefPort, + BOOLEAN bMatchBSSID, + PRT_WLAN_STA pEntry, + PRT_RFD pRfd, + pu1Byte pDesc + ); + +VOID +ODM_PathDivChkPerPktRssi( + PADAPTER Adapter, + BOOLEAN bIsDefPort, + BOOLEAN bMatchBSSID, + PRT_WLAN_STA pEntry, + PRT_RFD pRfd + ); + +VOID +ODM_PathDivRestAfterLink( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_FillTXPathInTXDESC( + IN PADAPTER Adapter, + IN PRT_TCB pTcb, + IN pu1Byte pDesc + ); + +VOID +odm_PathDivInit_92D( + IN PDM_ODM_T pDM_Odm + ); + +u1Byte +odm_SwAntDivSelectScanChnl( + IN PADAPTER Adapter + ); + +VOID +odm_SwAntDivConstructScanChnl( + IN PADAPTER Adapter, + IN u1Byte ScanChnl + ); + + #endif //#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + + + #endif //#ifndef __ODMPATHDIV_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_PowerTracking.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_PowerTracking.h new file mode 100644 index 0000000..ea4350d --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_PowerTracking.h @@ -0,0 +1,306 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define POWRTRACKING_VERSION "1.0" + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define OFDM_TABLE_SIZE 43 +#define CCK_TABLE_SIZE 33 +#define TXSCALE_TABLE_SIZE 37 +#define TXPWR_TRACK_TABLE_SIZE 30 +#define DELTA_SWINGIDX_SIZE 30 +#define BAND_NUM 4 +#define CCK_TABLE_SIZE_8711B 41 + +#define AVG_THERMAL_NUM 8 +#define HP_THERMAL_NUM 8 +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 +#if (RTL8192D_SUPPORT==1) +#define IQK_BB_REG_NUM 10 +#else +#define IQK_BB_REG_NUM 9 +#endif + + +#define IQK_Matrix_REG_NUM 8 +#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8195A) || defined (CONFIG_RTL8711B) +#define IQK_Matrix_Settings_NUM 14 +#else +#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G +#endif + +//extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE]; +//extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; +//extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; +#if (RTL8195A_SUPPORT == 1) +extern const u1Byte CCKSwingTable_Ch1_Ch13_8195A[CCK_TABLE_SIZE][9]; +extern const u1Byte CCKSwingTable_Ch14_8195A[CCK_TABLE_SIZE][9]; +extern const u1Byte CCKFCCTable_8195A[16]; +extern const u1Byte CCKCETable_8195A[16]; +extern const u1Byte CCKFCCTable_Ch14_8195A[16]; +#endif + +#if (RTL8711B_SUPPORT == 1) + +extern const u1Byte CCKFCCTable_8711B[16]; +extern const u1Byte CCKCETable_8711B[16]; +extern const u1Byte CCKFCCTable_Ch14_8711B[16]; +extern const u4Byte CCKSwingTable_Ch1_Ch14_8711B[CCK_TABLE_SIZE_8711B]; +#endif + +extern const u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE]; +extern const u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; +extern const u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; +//extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; + +// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. +//static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +//static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + +#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck + +typedef struct _IQK_MATRIX_REGS_SETTING{ + BOOLEAN bIQKDone; +#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B) + s4Byte Value[1][IQK_Matrix_REG_NUM]; +#else + s4Byte Value[3][IQK_Matrix_REG_NUM]; + BOOLEAN bBWIqkResultSaved[3]; +#endif +}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; + +typedef struct ODM_RF_Calibration_Structure +{ + //for tx power tracking + + u4Byte RegA24; // for TempCCK + s4Byte RegE94; + s4Byte RegE9C; + s4Byte RegEB4; + s4Byte RegEBC; + + u1Byte TXPowercount; + BOOLEAN bTXPowerTrackingInit; + BOOLEAN bTXPowerTracking; + u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default + u1Byte TM_Trigger; + u1Byte InternalPA5G[2]; //pathA / pathB + + u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 + u1Byte ThermalValue; + u1Byte ThermalValue_LCK; + u1Byte ThermalValue_IQK; + u1Byte ThermalValue_DPK; + u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; + u1Byte ThermalValue_AVG_index; + u1Byte ThermalValue_RxGain; + u1Byte ThermalValue_Crystal; + u1Byte ThermalValue_DPKstore; + u1Byte ThermalValue_DPKtrack; + BOOLEAN TxPowerTrackingInProgress; + + BOOLEAN bReloadtxpowerindex; + u1Byte bRfPiEnable; + u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug + + + //------------------------- Tx power Tracking -------------------------// + u1Byte bCCKinCH14; + u1Byte CCK_index[MAX_RF_PATH]; + s1Byte PowerIndexOffset_CCK[MAX_RF_PATH]; + s1Byte DeltaPowerIndex_CCK[MAX_RF_PATH]; + s1Byte DeltaPowerIndexLast_CCK[MAX_RF_PATH]; + u1Byte OFDM_index[MAX_RF_PATH]; + s1Byte PowerIndexOffset_OFDM[MAX_RF_PATH]; + s1Byte DeltaPowerIndex_OFDM[MAX_RF_PATH]; + s1Byte DeltaPowerIndexLast_OFDM[MAX_RF_PATH]; + BOOLEAN bTxPowerChanged; + s1Byte XtalOffset; + s1Byte XtalOffsetLast; + + u1Byte ThermalValue_HP[HP_THERMAL_NUM]; + u1Byte ThermalValue_HP_index; + IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; + u1Byte Delta_LCK; + s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB + s1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; +#if !defined(NOT_SUPPORT_RF_MULTIPATH) + s1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; +#endif + s1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; +#if !defined(NOT_SUPPORT_RF_MULTIPATH) + s1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; +#endif +#if !defined(NOT_SUPPORT_5G) + s1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; +#endif +// u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; +// u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; + + s1Byte DeltaSwingTableXtal_P[DELTA_SWINGIDX_SIZE]; + s1Byte DeltaSwingTableXtal_N[DELTA_SWINGIDX_SIZE]; + + + + //--------------------------------------------------------------------// + + //for IQK + u4Byte RegC04; + u4Byte Reg874; + u4Byte RegC08; + u4Byte RegB68; + u4Byte RegB6C; + u4Byte Reg870; + u4Byte Reg860; + u4Byte Reg864; + + BOOLEAN bIQKInitialized; + BOOLEAN bLCKInProgress; + BOOLEAN bAntennaDetected; + BOOLEAN bNeedIQK; + BOOLEAN bIQKInProgress; + u1Byte Delta_IQK; + u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; + u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; + u4Byte IQK_BB_backup_recover[9]; + u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; + u4Byte TxIQC_8723B[2][3][2]; // { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} + u4Byte RxIQC_8723B[2][2][2]; // { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} + + // IQK time measurement + u8Byte IQK_StartTime; + u8Byte IQK_ProgressingTime; + u4Byte LOK_Result; + + //for APK + u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a + u1Byte bAPKdone; + u1Byte bAPKThermalMeterIgnore; + + // DPK + BOOLEAN bDPKFail; + u1Byte bDPdone; + u1Byte bDPPathAOK; + u1Byte bDPPathBOK; + + u4Byte TxLOK[2]; + u4Byte DpkTxAGC; + s4Byte DpkGain; + u4Byte DpkThermal[4]; +}ODM_RF_CAL_T,*PODM_RF_CAL_T; + + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckIOT( + IN PVOID pDM_VOID + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +VOID +odm_TXPowerTrackingCallbackThermalMeter92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackRXGainThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingDirectCall92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ); + +#endif + +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RXHP.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RXHP.h new file mode 100644 index 0000000..98b3aa6 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RXHP.h @@ -0,0 +1,105 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __PHYDMRXHP_H__ +#define __PHYDMRXHP_H__ + +#define RXHP_VERSION "1.0" + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD +#define MODE_40M 0 //0:20M, 1:40M +#define PSD_TH2 3 +#define PSD_CHMIN 20 // Minimum channel number for BT AFH +#define SIR_STEP_SIZE 3 +#define Smooth_Size_1 5 +#define Smooth_TH_1 3 +#define Smooth_Size_2 10 +#define Smooth_TH_2 4 +#define Smooth_Size_3 20 +#define Smooth_TH_3 4 +#define Smooth_Step_Size 5 +#define Adaptive_SIR 1 +#define PSD_RESCAN 4 +#define PSD_SCAN_INTERVAL 700 //ms + +typedef struct _RX_High_Power_ +{ + u1Byte RXHP_flag; + u1Byte PSD_func_trigger; + u1Byte PSD_bitmap_RXHP[80]; + u1Byte Pre_IGI; + u1Byte Cur_IGI; + u1Byte Pre_pw_th; + u1Byte Cur_pw_th; + BOOLEAN First_time_enter; + BOOLEAN RXHP_enable; + u1Byte TP_Mode; + RT_TIMER PSDTimer; + #if USE_WORKITEM + RT_WORK_ITEM PSDTimeWorkitem; + #endif +}RXHP_T, *pRXHP_T; + +#define dm_PSDMonitorCallback odm_PSDMonitorCallback +VOID odm_PSDMonitorCallback(PRT_TIMER pTimer); + +VOID +odm_PSDMonitorInit( + IN PVOID pDM_VOID + ); + +void odm_RXHPInit( + IN PVOID pDM_VOID); + +void odm_RXHP( + IN PVOID pDM_VOID); + +VOID +odm_PSD_RXHPCallback( + PRT_TIMER pTimer +); + + VOID +ODM_PSDDbgControl( + IN PADAPTER Adapter, + IN u4Byte mode, + IN u4Byte btRssi + ); + + VOID +odm_PSD_RXHPCallback( + PRT_TIMER pTimer +); + +VOID +odm_PSD_RXHPWorkitemCallback( + IN PVOID pContext + ); + +VOID +odm_PSDMonitorWorkItemCallback( + IN PVOID pContext + ); + + #endif + + #endif + \ No newline at end of file diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RaInfo.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RaInfo.h new file mode 100644 index 0000000..ae5371e --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RaInfo.h @@ -0,0 +1,210 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMRAINFO_H__ +#define __PHYDMRAINFO_H__ + +#define RAINFO_VERSION "1.0" + +#define H2C_0X42_LENGTH 5 +#define H2C_MAX_LENGTH 7 + +#define RA_FLOOR_UP_GAP 3 +#define RA_FLOOR_TABLE_SIZE 7 + +#define ACTIVE_TP_THRESHOLD 150 +#define RA_RETRY_DESCEND_NUM 2 +#define RA_RETRY_LIMIT_LOW 4 +#define RA_RETRY_LIMIT_HIGH 32 + +#define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL +#define RAINFO_STBC_STATE BIT1 +//#define RAINFO_LDPC_STATE BIT2 +#define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection +#define RAINFO_SHURTCUT_STATE BIT3 +#define RAINFO_SHURTCUT_FLAG BIT4 +#define RAINFO_INIT_RSSI_RATE_STATE BIT5 +#define RAINFO_BF_STATE BIT6 +#define RAINFO_BE_TX_STATE BIT7 // 1:TX + +#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit + +#define DM_RATR_STA_INIT 0 +#define DM_RATR_STA_HIGH 1 +#define DM_RATR_STA_MIDDLE 2 +#define DM_RATR_STA_LOW 3 +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#define DM_RATR_STA_ULTRA_LOW 4 +#endif + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_IOT)) +typedef struct _Rate_Adaptive_Table_{ + u1Byte firstconnect; + #if(DM_ODM_SUPPORT_TYPE==ODM_WIN) + BOOLEAN PT_collision_pre; + #endif + + //u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte highest_client_tx_order; + u2Byte highest_client_tx_rate_order; + u1Byte power_tracking_flag; + u1Byte RA_threshold_offset; + u1Byte RA_offset_direction; + +}RA_T, *pRA_T; +#endif + +typedef struct _ODM_RATE_ADAPTIVE +{ + u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver + u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH + u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW + u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW + + #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_IOT)) + u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC + BOOLEAN bLowerRtsRate; + #endif + + #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + u1Byte RtsThres; + #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_IOT)) + BOOLEAN bUseLdpc; + #else + u1Byte UltraLowRSSIThresh; + u4Byte LastRATR; // RATR Register Content + #endif + +} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE; + +VOID +odm_RSSIMonitorInit( + IN PVOID pDM_VOID + ); + +VOID +odm_RSSIMonitorCheck( + IN PVOID pDM_VOID + ); + +#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) +VOID +odm_RSSIDumpToRegister( + IN PVOID pDM_VOID + ); +#endif + +VOID +odm_RSSIMonitorCheckMP( + IN PVOID pDM_VOID + ); + +VOID +odm_RSSIMonitorCheckCE( + IN PVOID pDM_VOID + ); + +VOID +odm_RSSIMonitorCheckIOT( + IN PVOID pDM_VOID + ); + +VOID +odm_RSSIMonitorCheckAP( + IN PVOID pDM_VOID + ); + + +VOID +odm_RateAdaptiveMaskInit( + IN PVOID pDM_VOID + ); + +VOID +odm_RefreshRateAdaptiveMask( + IN PVOID pDM_VOID + ); + +VOID +odm_RefreshRateAdaptiveMaskMP( + IN PVOID pDM_VOID + ); + +VOID +odm_RefreshRateAdaptiveMaskCE( + IN PVOID pDM_VOID + ); + +VOID +odm_RefreshRateAdaptiveMaskIOT( + IN PVOID pDM_VOID + ); + +VOID +odm_RefreshRateAdaptiveMaskAPADSL( + IN PVOID pDM_VOID + ); + +BOOLEAN +ODM_RAStateCheck( + IN PVOID pDM_VOID, + IN s4Byte RSSI, + IN BOOLEAN bForceUpdate, + OUT pu1Byte pRATRState + ); + +VOID +odm_RefreshBasicRateMask( + IN PVOID pDM_VOID + ); + +VOID +phydm_ra_info_init( + IN PVOID pDM_VOID + ); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +ODM_DynamicARFBSelect( + IN PVOID pDM_VOID, + IN u1Byte rate, + IN BOOLEAN Collision_State + ); + +VOID +ODM_RateAdaptiveStateApInit( + IN PVOID PADAPTER_VOID, + IN PRT_WLAN_STA pEntry + ); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_IOT)) +u4Byte +ODM_Get_Rate_Bitmap( + IN PVOID pDM_VOID, + IN u4Byte macid, + IN u4Byte ra_mask, + IN u1Byte rssi_level + ); +#endif + +#endif //#ifndef __ODMRAINFO_H__ + + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RegDefine11AC.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RegDefine11AC.h new file mode 100644 index 0000000..9b83c55 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RegDefine11AC.h @@ -0,0 +1,81 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_REGDEFINE11AC_H__ +#define __ODM_REGDEFINE11AC_H__ + +//2 RF REG LIST + + + +//2 BB REG LIST +//PAGE 8 +#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804 +#define ODM_REG_BB_RX_PATH_11AC 0x808 +#define ODM_REG_BB_TX_PATH_11AC 0x80c +#define ODM_REG_BB_ATC_11AC 0x860 +#define ODM_REG_EDCCA_POWER_CAL 0x8dc +#define ODM_REG_DBG_RPT_11AC 0x8fc +//PAGE 9 +#define ODM_REG_EDCCA_DOWN_OPT 0x900 +#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944 +#define ODM_REG_OFDM_FA_RST_11AC 0x9A4 +#define ODM_REG_NHM_TIMER_11AC 0x990 +#define ODM_REG_NHM_TH9_TH10_11AC 0x994 +#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998 +#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c +#define ODM_REG_NHM_TH8_11AC 0x9a0 +#define ODM_REG_NHM_9E8_11AC 0x9e8 +//PAGE A +#define ODM_REG_CCK_CCA_11AC 0xA0A +#define ODM_REG_CCK_FA_RST_11AC 0xA2C +#define ODM_REG_CCK_FA_11AC 0xA5C +//PAGE B +#define ODM_REG_RST_RPT_11AC 0xB58 +//PAGE C +#define ODM_REG_TRMUX_11AC 0xC08 +#define ODM_REG_IGI_A_11AC 0xC50 +//PAGE E +#define ODM_REG_IGI_B_11AC 0xE50 +#define ODM_REG_TRMUX_11AC_B 0xE08 +//PAGE F +#define ODM_REG_CCK_CCA_CNT_11AC 0xF08 +#define ODM_REG_OFDM_FA_11AC 0xF48 +#define ODM_REG_RPT_11AC 0xfa0 +#define ODM_REG_NHM_CNT_11AC 0xfa8 +//PAGE 18 +#define ODM_REG_IGI_C_11AC 0x1850 +//PAGE 1A +#define ODM_REG_IGI_D_11AC 0x1A50 + +//2 MAC REG LIST +#define ODM_REG_RESP_TX_11AC 0x6D8 + + + +//DIG Related +#define ODM_BIT_IGI_11AC 0xFFFFFFFF +#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16 +#define ODM_BIT_BB_RX_PATH_11AC 0xF +#define ODM_BIT_BB_TX_PATH_11AC 0xF +#define ODM_BIT_BB_ATC_11AC BIT14 + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RegDefine11N.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RegDefine11N.h new file mode 100644 index 0000000..c1d91d7 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RegDefine11N.h @@ -0,0 +1,186 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_REGDEFINE11N_H__ +#define __ODM_REGDEFINE11N_H__ + + +//2 RF REG LIST +#define ODM_REG_RF_MODE_11N 0x00 +#define ODM_REG_RF_0B_11N 0x0B +#define ODM_REG_CHNBW_11N 0x18 +#define ODM_REG_T_METER_11N 0x24 +#define ODM_REG_RF_25_11N 0x25 +#define ODM_REG_RF_26_11N 0x26 +#define ODM_REG_RF_27_11N 0x27 +#define ODM_REG_RF_2B_11N 0x2B +#define ODM_REG_RF_2C_11N 0x2C +#define ODM_REG_RXRF_A3_11N 0x3C +#define ODM_REG_T_METER_92D_11N 0x42 +#define ODM_REG_T_METER_88E_11N 0x42 + + + +//2 BB REG LIST +//PAGE 8 +#define ODM_REG_BB_CTRL_11N 0x800 +#define ODM_REG_RF_PIN_11N 0x804 +#define ODM_REG_PSD_CTRL_11N 0x808 +#define ODM_REG_TX_ANT_CTRL_11N 0x80C +#define ODM_REG_BB_PWR_SAV5_11N 0x818 +#define ODM_REG_CCK_RPT_FORMAT_11N 0x824 +#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C +#define ODM_REG_RX_DEFUALT_A_11N 0x858 +#define ODM_REG_RX_DEFUALT_B_11N 0x85A +#define ODM_REG_BB_PWR_SAV3_11N 0x85C +#define ODM_REG_ANTSEL_CTRL_11N 0x860 +#define ODM_REG_RX_ANT_CTRL_11N 0x864 +#define ODM_REG_PIN_CTRL_11N 0x870 +#define ODM_REG_BB_PWR_SAV1_11N 0x874 +#define ODM_REG_ANTSEL_PATH_11N 0x878 +#define ODM_REG_BB_3WIRE_11N 0x88C +#define ODM_REG_SC_CNT_11N 0x8C4 +#define ODM_REG_PSD_DATA_11N 0x8B4 +#define ODM_REG_PSD_DATA_11N 0x8B4 +#define ODM_REG_NHM_TIMER_11N 0x894 +#define ODM_REG_NHM_TH9_TH10_11N 0x890 +#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898 +#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c +#define ODM_REG_NHM_CNT_11N 0x8d8 +//PAGE 9 +#define ODM_REG_DBG_RPT_11N 0x908 +#define ODM_REG_BB_TX_PATH_11N 0x90c +#define ODM_REG_ANT_MAPPING1_11N 0x914 +#define ODM_REG_ANT_MAPPING2_11N 0x918 +#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948 + +//PAGE A +#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 +#define ODM_REG_CCK_CCA_11N 0xA0A +#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C +#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 +#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 +#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 +#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 +#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 +#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 +#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 +#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 +#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 +#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 +#define ODM_REG_CCK_FA_RST_11N 0xA2C +#define ODM_REG_CCK_FA_MSB_11N 0xA58 +#define ODM_REG_CCK_FA_LSB_11N 0xA5C +#define ODM_REG_CCK_CCA_CNT_11N 0xA60 +#define ODM_REG_BB_PWR_SAV4_11N 0xA74 +//PAGE B +#define ODM_REG_LNA_SWITCH_11N 0xB2C +#define ODM_REG_PATH_SWITCH_11N 0xB30 +#define ODM_REG_RSSI_CTRL_11N 0xB38 +#define ODM_REG_CONFIG_ANTA_11N 0xB68 +#define ODM_REG_RSSI_BT_11N 0xB9C +//PAGE C +#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 +#define ODM_REG_BB_RX_PATH_11N 0xC04 +#define ODM_REG_TRMUX_11N 0xC08 +#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C +#define ODM_REG_RXIQI_MATRIX_11N 0xC14 +#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C +#define ODM_REG_IGI_A_11N 0xC50 +#define ODM_REG_ANTDIV_PARA2_11N 0xC54 +#define ODM_REG_IGI_B_11N 0xC58 +#define ODM_REG_ANTDIV_PARA3_11N 0xC5C +#define ODM_REG_L1SBD_PD_CH_11N 0XC6C +#define ODM_REG_BB_PWR_SAV2_11N 0xC70 +#define ODM_REG_RX_OFF_11N 0xC7C +#define ODM_REG_TXIQK_MATRIXA_11N 0xC80 +#define ODM_REG_TXIQK_MATRIXB_11N 0xC88 +#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 +#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C +#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 +#define ODM_REG_ANTDIV_PARA1_11N 0xCA4 +#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 +//PAGE D +#define ODM_REG_OFDM_FA_RSTD_11N 0xD00 +#define ODM_REG_BB_ATC_11N 0xD2C +#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 +#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 +#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 +#define ODM_REG_RPT_11N 0xDF4 +//PAGE E +#define ODM_REG_TXAGC_A_6_18_11N 0xE00 +#define ODM_REG_TXAGC_A_24_54_11N 0xE04 +#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 +#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10 +#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14 +#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 +#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C +#define DOM_REG_EDCCA_DCNF_11N 0xE24 +#define ODM_REG_FPGA0_IQK_11N 0xE28 +#define ODM_REG_TXIQK_TONE_A_11N 0xE30 +#define ODM_REG_RXIQK_TONE_A_11N 0xE34 +#define ODM_REG_TXIQK_PI_A_11N 0xE38 +#define ODM_REG_RXIQK_PI_A_11N 0xE3C +#define ODM_REG_TXIQK_11N 0xE40 +#define ODM_REG_RXIQK_11N 0xE44 +#define ODM_REG_IQK_AGC_PTS_11N 0xE48 +#define ODM_REG_IQK_AGC_RSP_11N 0xE4C +#define ODM_REG_BLUETOOTH_11N 0xE6C +#define ODM_REG_RX_WAIT_CCA_11N 0xE70 +#define ODM_REG_TX_CCK_RFON_11N 0xE74 +#define ODM_REG_TX_CCK_BBON_11N 0xE78 +#define ODM_REG_OFDM_RFON_11N 0xE7C +#define ODM_REG_OFDM_BBON_11N 0xE80 +#define ODM_REG_TX2RX_11N 0xE84 +#define ODM_REG_TX2TX_11N 0xE88 +#define ODM_REG_RX_CCK_11N 0xE8C +#define ODM_REG_RX_OFDM_11N 0xED0 +#define ODM_REG_RX_WAIT_RIFS_11N 0xED4 +#define ODM_REG_RX2RX_11N 0xED8 +#define ODM_REG_STANDBY_11N 0xEDC +#define ODM_REG_SLEEP_11N 0xEE0 +#define ODM_REG_PMPD_ANAEN_11N 0xEEC +#define ODM_REG_IGI_C_11N 0xF84 +#define ODM_REG_IGI_D_11N 0xF88 + +//2 MAC REG LIST +#define ODM_REG_BB_RST_11N 0x02 +#define ODM_REG_ANTSEL_PIN_11N 0x4C +#define ODM_REG_EARLY_MODE_11N 0x4D0 +#define ODM_REG_RSSI_MONITOR_11N 0x4FE +#define ODM_REG_EDCA_VO_11N 0x500 +#define ODM_REG_EDCA_VI_11N 0x504 +#define ODM_REG_EDCA_BE_11N 0x508 +#define ODM_REG_EDCA_BK_11N 0x50C +#define ODM_REG_TXPAUSE_11N 0x522 +#define ODM_REG_RESP_TX_11N 0x6D8 +#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 +#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 + + +//DIG Related +#define ODM_BIT_IGI_11N 0x0000007F +#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9 +#define ODM_BIT_BB_RX_PATH_11N 0xF +#define ODM_BIT_BB_TX_PATH_11N 0xF +#define ODM_BIT_BB_ATC_11N BIT11 + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_debug.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_debug.h new file mode 100644 index 0000000..366e306 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_debug.h @@ -0,0 +1,900 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __ODM_DBG_H__ +#define __ODM_DBG_H__ + + +//----------------------------------------------------------------------------- +// Define the debug levels +// +// 1. DBG_TRACE and DBG_LOUD are used for normal cases. +// So that, they can help SW engineer to develope or trace states changed +// and also help HW enginner to trace every operation to and from HW, +// e.g IO, Tx, Rx. +// +// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, +// which help us to debug SW or HW. +// +//----------------------------------------------------------------------------- +// +// Never used in a call to ODM_RT_TRACE()! +// +#define ODM_DBG_OFF 1 + +// +// Fatal bug. +// For example, Tx/Rx/IO locked up, OS hangs, memory access violation, +// resource allocation failed, unexpected HW behavior, HW BUG and so on. +// +#define ODM_DBG_SERIOUS 2 + +// +// Abnormal, rare, or unexpeted cases. +// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. +// +#define ODM_DBG_WARNING 3 + +// +// Normal case with useful information about current SW or HW state. +// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, +// SW protocol state change, dynamic mechanism state change and so on. +// +#define ODM_DBG_LOUD 4 + +// +// Normal case with detail execution flow or information. +// +#define ODM_DBG_TRACE 5 + +//----------------------------------------------------------------------------- +// Define the tracing components +// +//----------------------------------------------------------------------------- +//BB Functions +#define ODM_COMP_DIG BIT0 +#define ODM_COMP_RA_MASK BIT1 +#define ODM_COMP_DYNAMIC_TXPWR BIT2 +#define ODM_COMP_FA_CNT BIT3 +#define ODM_COMP_RSSI_MONITOR BIT4 +#define ODM_COMP_CCK_PD BIT5 +#define ODM_COMP_ANT_DIV BIT6 +#define ODM_COMP_PWR_SAVE BIT7 +#define ODM_COMP_PWR_TRAIN BIT8 +#define ODM_COMP_RATE_ADAPTIVE BIT9 +#define ODM_COMP_PATH_DIV BIT10 +#define ODM_COMP_PSD BIT11 +#define ODM_COMP_DYNAMIC_PRICCA BIT12 +#define ODM_COMP_RXHP BIT13 +#define ODM_COMP_MP BIT14 +#define ODM_COMP_CFO_TRACKING BIT15 +#define ODM_COMP_ACS BIT16 +#define PHYDM_COMP_ADAPTIVITY BIT17 + +//MAC Functions +#define ODM_COMP_EDCA_TURBO BIT18 +#define ODM_COMP_EARLY_MODE BIT19 +//RF Functions +#define ODM_COMP_TX_PWR_TRACK BIT24 +#define ODM_COMP_RX_GAIN_TRACK BIT25 +#define ODM_COMP_CALIBRATION BIT26 +//Common Functions +#define ODM_COMP_INIT BIT29 +#define ODM_COMP_COMMON BIT30 +#define ODM_COMP_FIX BIT31 + +/*------------------------Export Marco Definition---------------------------*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define RT_PRINTK DbgPrint +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #define DbgPrint printk + #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); + #define RT_DISP(dbgtype, dbgflag, printstr) +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + #define DbgPrint printf + #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); + #define RT_DISP(dbgtype, dbgflag, printstr) +#else + #define DbgPrint panic_printk + #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); +#endif + +#ifndef ASSERT + #define ASSERT(expr) +#endif + +#if DBG +#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \ + if(((comp) & ROMInfo.DebugComponents) && (level <= ROMInfo.DebugLevel || level == ODM_DBG_SERIOUS)) \ + { \ + RT_PRINTK fmt; \ + } + +#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \ + if(((comp) & ROMInfo.DebugComponents) && (level <= ROMInfo.DebugLevel)) \ + { \ + RT_PRINTK fmt; \ + } + +#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \ + if(!(expr)) { \ + DbgPrint( "Assertion failed! %s at ......\n", #expr); \ + DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \ + RT_PRINTK fmt; \ + ASSERT(FALSE); \ + } +#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); } +#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); } +#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); } + +#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \ + if(((comp) & ROMInfo.DebugComponents) && (level <= ROMInfo.DebugLevel)) \ + { \ + int __i; \ + pu1Byte __ptr = (pu1Byte)ptr; \ + DbgPrint("[ODM] "); \ + DbgPrint(title_str); \ + DbgPrint(" "); \ + for( __i=0; __i<6; __i++ ) \ + DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \ + DbgPrint("\n"); \ + } +#else +#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) +#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) +#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) +#define ODM_dbg_enter() +#define ODM_dbg_exit() +#define ODM_dbg_trace(str) +#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) +#endif + + +VOID +ODM_InitDebugSetting( + IN PDM_ODM_T pDM_Odm + ); + + + +#if 0 +#if DBG +#define DbgPrint printk + +#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \ + { \ + char *szTitle = _TitleString; \ + pu1Byte pbtHexData = _HexData; \ + u4Byte u4bHexDataLen = _HexDataLen; \ + u4Byte __i; \ + DbgPrint("%s", szTitle); \ + for (__i=0;__i=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22. + +#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \ + if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \ + { \ + int __i; \ + u1Byte buffer[MAX_STR_LEN]; \ + int length = (_Len\n", _Len, buffer); \ + } + +#else // of #if DBG +#define DbgPrint(...) +#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) +#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) +#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) +#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) +#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) +#endif // of #if DBG + +#endif + + +#if 0 +/* Define debug print header for every service module.*/ +typedef struct tag_ODM_DBGP_Service_Module_Header_Name_Structure +{ + const char *pMANS; + const char *pRTOS; + const char *pALM; + const char *pPEM; + const char *pCMPK; + const char *pRAPD; + const char *pTXPB; + const char *pQUMG; +}ODM_DBGP_HEAD_T; + + +/* Define different debug flag for dedicated service modules in debug flag array. */ +// Each module has independt 32 bit debug flag you cnn define the flag as yout require. +typedef enum tag_ODM_DBGP_Flag_Type_Definition +{ + ODM_FTX = 0, + ODM_FRX , + ODM_FPHY , + ODM_FPWR , + ODM_FDM , + ODM_FC2H , + ODM_FBT , + ODM_DBGP_TYPE_MAX +}ODM_DBGP_FLAG_E; + + +// Define TX relative debug bit --> FTX +#define ODM_TX_DESC BIT0 +#define ODM_TX_DESC_TID BIT1 +#define ODM_TX_PATH BIT2 + +// Define RX relative debug bit --> FRX +#define ODM_RX_DATA BIT0 +#define ODM_RX_PHY_STS BIT1 +#define ODM_RX_PHY_SS BIT2 +#define ODM_RX_PHY_SQ BIT3 +#define ODM_RX_PHY_ASTS BIT4 +#define ODM_RX_ERR_LEN BIT5 +#define ODM_RX_DEFRAG BIT6 +#define ODM_RX_ERR_RATE BIT7 +#define ODM_RX_PATH BIT8 +#define ODM_RX_BEACON BIT9 + +// Define PHY-BB/RF/MAC check module bit --> FPHY +#define ODM_PHY_BBR BIT0 +#define ODM_PHY_BBW BIT1 +#define ODM_PHY_RFR BIT2 +#define ODM_PHY_RFW BIT3 +#define ODM_PHY_MACR BIT4 +#define ODM_PHY_MACW BIT5 +#define ODM_PHY_ALLR BIT6 +#define ODM_PHY_ALLW BIT7 +#define ODM_PHY_TXPWR BIT8 +#define ODM_PHY_PWRDIFF BIT9 +#define ODM_PHY_SICR BIT10 +#define ODM_PHY_SICW BIT11 + + + + +extern u4Byte ODM_GlobalDebugLevel; + + +#if DBG +extern u8Byte ODM_GlobalDebugComponents; +#endif +#endif +#if 0 + +//----------------------------------------------------------------------------- +// Define the debug levels +// +// 1. DBG_TRACE and DBG_LOUD are used for normal cases. +// So that, they can help SW engineer to develope or trace states changed +// and also help HW enginner to trace every operation to and from HW, +// e.g IO, Tx, Rx. +// +// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, +// which help us to debug SW or HW. +// +//----------------------------------------------------------------------------- +// +// Never used in a call to ODM_RT_TRACE(pDM_Odm,)! +// +#define DBG_OFF 0 + +// +// Deprecated! Don't use it! +// TODO: fix related debug message! +// +//#define DBG_SEC 1 + +// +// Fatal bug. +// For example, Tx/Rx/IO locked up, OS hangs, memory access violation, +// resource allocation failed, unexpected HW behavior, HW BUG and so on. +// +#define DBG_SERIOUS 2 + +// +// Abnormal, rare, or unexpeted cases. +// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. +// +#define DBG_WARNING 3 + +// +// Normal case with useful information about current SW or HW state. +// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, +// SW protocol state change, dynamic mechanism state change and so on. +// +#define DBG_LOUD 4 + +// +// Normal case with detail execution flow or information. +// +#define DBG_TRACE 5 + + + +//----------------------------------------------------------------------------- +// Define the tracing components +// +//----------------------------------------------------------------------------- +#define COMP_TRACE BIT0 // For function call tracing. +#define COMP_DBG BIT1 // Only for temporary debug message. +#define COMP_INIT BIT2 // during driver initialization / halt / reset. +#define COMP_OID_QUERY BIT3 // Query OID. +#define COMP_OID_SET BIT4 // Set OID. +#define COMP_RECV BIT5 // Reveive part data path. +#define COMP_SEND BIT6 // Send part path. +#define COMP_IO BIT7 // I/O Related. Added by Annie, 2006-03-02. +#define COMP_POWER BIT8 // 802.11 Power Save mode or System/Device Power state related. +#define COMP_MLME BIT9 // 802.11 link related: join/start BSS, leave BSS. +#define COMP_SCAN BIT10 // For site survey. +#define COMP_SYSTEM BIT11 // For general platform function. +#define COMP_SEC BIT12 // For Security. +#define COMP_AP BIT13 // For AP mode related. +#define COMP_TURBO BIT14 // For Turbo Mode related. By Annie, 2005-10-21. +#define COMP_QOS BIT15 // For QoS. +#define COMP_AUTHENTICATOR BIT16 // For AP mode Authenticator. Added by Annie, 2006-01-30. +#define COMP_BEACON BIT17 // For Beacon related, by rcnjko. +#define COMP_ANTENNA BIT18 // For Antenna diversity related, by rcnjko. +#define COMP_RATE BIT19 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling +#define COMP_EVENTS BIT20 // Event handling +#define COMP_FPGA BIT21 // For FPGA verfication +#define COMP_RM BIT22 // For Radio Measurement. +#define COMP_MP BIT23 // For mass production test, by shien chang, 2006.07.13 +#define COMP_RXDESC BIT24 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15. +#define COMP_CKIP BIT25 // For CCX 1 S13: CKIP. Added by Annie, 2006-08-14. +#define COMP_DIG BIT26 // For DIG, 2006.09.25, by rcnjko. +#define COMP_TXAGC BIT27 // For Tx power, 060928, by rcnjko. +#define COMP_HIPWR BIT28 // For High Power Mechanism, 060928, by rcnjko. +#define COMP_HALDM BIT29 // For HW Dynamic Mechanism, 061010, by rcnjko. +#define COMP_RSNA BIT30 // For RSNA IBSS , 061201, by CCW. +#define COMP_INDIC BIT31 // For link indication +#define COMP_LED BIT32 // For LED. +#define COMP_RF BIT33 // For RF. +//1!!!!!!!!!!!!!!!!!!!!!!!!!!! +//1//1Attention Please!!!<11n or 8190 specific code should be put below this line> +//1!!!!!!!!!!!!!!!!!!!!!!!!!!! + +#define COMP_HT BIT34 // For 802.11n HT related information. by Emily 2006-8-11 +#define COMP_POWER_TRACKING BIT35 //FOR 8190 TX POWER TRACKING +#define COMP_RX_REORDER BIT36 // 8190 Rx Reorder +#define COMP_AMSDU BIT37 // For A-MSDU Debugging +#define COMP_WPS BIT38 //WPS Debug Message +#define COMP_RATR BIT39 +#define COMP_RESET BIT40 +// For debug command to print on dbgview!! +#define COMP_CMD BIT41 +#define COMP_EFUSE BIT42 +#define COMP_MESH_INTERWORKING BIT43 +#define COMP_CCX BIT44 //CCX Debug Flag +#define COMP_IOCTL BIT45 // IO Control +#define COMP_GP BIT46 // For generic parser. +#define COMP_TXAGG BIT47 +#define COMP_HVL BIT48 // For Ndis 6.2 Context Swirch and Hardware Virtualiztion Layer +#define COMP_TEST BIT49 +#define COMP_BB_POWERSAVING BIT50 +#define COMP_SWAS BIT51 // For SW Antenna Switch +#define COMP_P2P BIT52 +#define COMP_MUX BIT53 +#define COMP_FUNC BIT54 +#define COMP_TDLS BIT55 +#define COMP_OMNIPEEK BIT56 +#define COMP_DUALMACSWITCH BIT60 // 2010/12/27 Add for Dual mac mode debug +#define COMP_EASY_CONCURRENT BIT61 // 2010/12/27 Add for easy cncurrent mode debug +#define COMP_PSD BIT63 //2011/3/9 Add for WLAN PSD for BT AFH + +#define COMP_DFS BIT62 + +#define COMP_ALL UINT64_C(0xFFFFFFFFFFFFFFFF) // All components +// For debug print flag to use +/*------------------------------Define structure----------------------------*/ +/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/ + +/* Defnie structure to store different debug flag variable. Every debug flag + is a UINT32 integer and you can assign 32 different events. */ +typedef struct tag_DBGP_Debug_Flag_Structure +{ + u4Byte Mans; /* Main Scheduler module. */ + u4Byte Rtos; /* RTOS module. */ + u4Byte Alarm; /* Alarm module. */ + u4Byte Pm; /* Performance monitor module. */ +}DBGP_FLAG_T; + +/* Define debug print header for every service module.*/ +typedef struct tag_DBGP_Service_Module_Header_Name_Structure +{ + const char *pMANS; + const char *pRTOS; + const char *pALM; + const char *pPEM; + const char *pCMPK; + const char *pRAPD; + const char *pTXPB; + const char *pQUMG; +}DBGP_HEAD_T; + + +/* Define different debug flag for dedicated service modules in debug flag array. */ +// Each module has independt 32 bit debug flag you cnn define the flag as yout require. +typedef enum tag_DBGP_Flag_Type_Definition +{ + FQoS = 0, + FTX = 1, + FRX = 2, + FSEC = 3, + FMGNT = 4, + FMLME = 5, + FRESOURCE = 6, + FBEACON = 7, + FISR = 8, + FPHY = 9, + FMP = 10, + FEEPROM = 11, + FPWR = 12, + FDM = 13, + FDBG_CTRL = 14, + FC2H = 15, + FBT = 16, + FINIT = 17, + FIOCTL = 18, + FSHORT_CUT = 19, + DBGP_TYPE_MAX +}DBGP_FLAG_E; + + +// Define Qos Relative debug flag bit --> FQoS +#define QoS_INIT BIT0 +#define QoS_VISTA BIT1 + +// Define TX relative debug bit --> FTX +#define TX_DESC BIT0 +#define TX_DESC_TID BIT1 +#define TX_PATH BIT2 + +// Define RX relative debug bit --> FRX +#define RX_DATA BIT0 +#define RX_PHY_STS BIT1 +#define RX_PHY_SS BIT2 +#define RX_PHY_SQ BIT3 +#define RX_PHY_ASTS BIT4 +#define RX_ERR_LEN BIT5 +#define RX_DEFRAG BIT6 +#define RX_ERR_RATE BIT7 +#define RX_PATH BIT8 +#define RX_BEACON BIT9 + +// Define Security relative debug bit --> FSEC + +// Define MGNT relative debug bit --> FMGNT + +// Define MLME relative debug bit --> FMLME +#define MEDIA_STS BIT0 +#define LINK_STS BIT1 + +// Define OS resource check module bit --> FRESOURCE +#define OS_CHK BIT0 + +// Define beacon content check module bit --> FBEACON +#define BCN_SHOW BIT0 +#define BCN_PEER BIT1 + +// Define ISR/IMR check module bit --> FISR +#define ISR_CHK BIT0 + +// Define PHY-BB/RF/MAC check module bit --> FPHY +#define PHY_BBR BIT0 +#define PHY_BBW BIT1 +#define PHY_RFR BIT2 +#define PHY_RFW BIT3 +#define PHY_MACR BIT4 +#define PHY_MACW BIT5 +#define PHY_ALLR BIT6 +#define PHY_ALLW BIT7 +#define PHY_TXPWR BIT8 +#define PHY_PWRDIFF BIT9 +#define PHY_SICR BIT10 +#define PHY_SICW BIT11 + +// Define MPT driver check module bit --> FMP +#define MP_RX BIT0 +#define MP_SWICH_CH BIT1 + +// Define EEPROM and EFUSE check module bit --> FEEPROM +#define EEPROM_W BIT0 +#define EFUSE_PG BIT1 +#define EFUSE_READ_ALL BIT2 +#define EFUSE_ANALYSIS BIT3 +#define EFUSE_PG_DETAIL BIT4 + +// Define power save check module bit --> FPWR +#define LPS BIT0 +#define IPS BIT1 +#define PWRSW BIT2 +#define PWRHW BIT3 +#define PWRHAL BIT4 + +// Define Dynamic Mechanism check module bit --> FDM +#define WA_IOT BIT0 +#define DM_PWDB BIT1 +#define DM_Monitor BIT2 +#define DM_DIG BIT3 +#define DM_EDCA_Turbo BIT4 +#define DM_BT30 BIT5 + +// Define Dbg Control module bit --> FDBG_CTRL +#define DBG_CTRL_TRACE BIT0 +#define DBG_CTRL_INBAND_NOISE BIT1 + +// Define FW C2H Cmd check module bit --> FC2H +#define C2H_Summary BIT0 +#define C2H_PacketData BIT1 +#define C2H_ContentData BIT2 +// Define BT Cmd check module bit --> FBT +#define BT_TRACE BIT0 +#define BT_RFPoll BIT1 + +// Define init check for module bit --> FINIT +#define INIT_EEPROM BIT0 +#define INIT_TxPower BIT1 +#define INIT_IQK BIT2 +#define INIT_RF BIT3 + +// Define IOCTL Cmd check module bit --> FIOCTL +// section 1 : IRP related +#define IOCTL_IRP BIT0 +#define IOCTL_IRP_DETAIL BIT1 +#define IOCTL_IRP_STATISTICS BIT2 +#define IOCTL_IRP_HANDLE BIT3 +// section 2 : HCI command/event +#define IOCTL_BT_HCICMD BIT8 +#define IOCTL_BT_HCICMD_DETAIL BIT9 +#define IOCTL_BT_HCICMD_EXT BIT10 +#define IOCTL_BT_EVENT BIT11 +#define IOCTL_BT_EVENT_DETAIL BIT12 +#define IOCTL_BT_EVENT_PERIODICAL BIT13 +// section 3 : BT tx/rx data and throughput +#define IOCTL_BT_TX_ACLDATA BIT16 +#define IOCTL_BT_TX_ACLDATA_DETAIL BIT17 +#define IOCTL_BT_RX_ACLDATA BIT18 +#define IOCTL_BT_RX_ACLDATA_DETAIL BIT19 +#define IOCTL_BT_TP BIT20 +// section 4 : BT connection state machine. +#define IOCTL_STATE BIT21 +#define IOCTL_BT_LOGO BIT22 +// section 5 : BT function trace +#define IOCTL_CALLBACK_FUN BIT24 +#define IOCTL_PARSE_BT_PKT BIT25 +#define IOCTL_BT_TX_PKT BIT26 +#define IOCTL_BT_FLAG_MON BIT27 + +// +// Define init check for module bit --> FSHORT_CUT +// 2011/07/20 MH Add for short but definition. +// +#define SHCUT_TX BIT0 +#define SHCUT_RX BIT1 + + +/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/ +/*------------------------------Define structure----------------------------*/ + + +/*------------------------Export Marco Definition---------------------------*/ +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +#define RT_PRINTK(fmt, args...) printk( "%s(): " fmt, __FUNCTION__, ## args); + +#if DBG +#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt) \ + if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \ + { \ + RT_PRINTK fmt; \ + } + +#define RT_TRACE_F(comp, level, fmt) \ + if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \ + { \ + RT_PRINTK fmt; \ + } + +#define RT_ASSERT(expr,fmt) \ + if(!(expr)) { \ + printk( "Assertion failed! %s at ......\n", #expr); \ + printk( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \ + } +#define dbg_enter() { printk("==> %s\n", __FUNCTION__); } +#define dbg_exit() { printk("<== %s\n", __FUNCTION__); } +#define dbg_trace(str) { printk("%s:%s\n", __FUNCTION__, str); } +#else +#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt) +#define RT_TRACE_F(comp, level, fmt) +#define RT_ASSERT(expr, fmt) +#define dbg_enter() +#define dbg_exit() +#define dbg_trace(str) +#endif + +#if DBG +#define DbgPrint printk + +#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \ + { \ + char *szTitle = _TitleString; \ + pu1Byte pbtHexData = _HexData; \ + u4Byte u4bHexDataLen = _HexDataLen; \ + u4Byte __i; \ + DbgPrint("%s", szTitle); \ + for (__i=0;__i=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22. + +#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \ + if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \ + { \ + int __i; \ + u1Byte buffer[MAX_STR_LEN]; \ + int length = (_Len\n", _Len, buffer); \ + } + +#else // of #if DBG +#define DbgPrint(...) +#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) +#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) +#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) +#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) +#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) +#endif // of #if DBG + + + +#endif // #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) + +#define DEBUG_PRINT 1 + +// Please add new OS's print API by yourself + +//#if (RT_PLATFORM==PLATFORM_WINDOWS) +#if (DEBUG_PRINT == 1) && DBG +#define RT_DISP(dbgtype, dbgflag, printstr)\ +{\ + if (DBGP_Type[dbgtype] & dbgflag)\ + {\ + DbgPrint printstr;\ + }\ +} + +#define RT_DISP_ADDR(dbgtype, dbgflag, printstr, _Ptr)\ +{\ + if (DBGP_Type[dbgtype] & dbgflag)\ + {\ + int __i; \ + pu1Byte ptr = (pu1Byte)_Ptr; \ + DbgPrint printstr; \ + DbgPrint(" "); \ + for( __i=0; __i<6; __i++ ) \ + DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \ + DbgPrint("\n"); \ + }\ +} + +#define RT_DISP_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)\ +{\ + if (DBGP_Type[dbgtype] & dbgflag)\ + {\ + int __i; \ + pu1Byte ptr = (pu1Byte)_HexData; \ + DbgPrint(_TitleString); \ + for( __i=0; __i<(int)_HexDataLen; __i++ ) \ + { \ + DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" ");\ + if (((__i + 1) % 16) == 0) DbgPrint("\n");\ + } \ + DbgPrint("\n"); \ + }\ +} + +#define FunctionIn(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("==========> %s\n", __FUNCTION__)) +#define FunctionOut(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("<========== %s\n", __FUNCTION__)) + + +#else + +#define RT_DISP(dbgtype, dbgflag, printstr) +#define RT_DISP_ADDR(dbgtype, dbgflag, printstr, _Ptr) +#define RT_DISP_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen) + +#define FunctionIn(_comp) +#define FunctionOut(_comp) +#endif +/*------------------------Export Marco Definition---------------------------*/ + + +/*------------------------Export global variable----------------------------*/ +extern u4Byte DBGP_Type[DBGP_TYPE_MAX]; +extern DBGP_HEAD_T DBGP_Head; + +/*------------------------Export global variable----------------------------*/ + + +/*--------------------------Exported Function prototype---------------------*/ +extern void DBGP_Flag_Init(void); +extern void DBG_PrintAllFlag(void); +extern void DBG_PrintAllComp(void); +extern void DBG_PrintFlagEvent(u1Byte DbgFlag); +extern void DBG_DumpMem(const u1Byte DbgComp, + const u1Byte DbgLevel, + pu1Byte pMem, + u2Byte Len); + +/*--------------------------Exported Function prototype---------------------*/ + + + + + + + + + +extern u4Byte GlobalDebugLevel; +extern u8Byte GlobalDebugComponents; + + +#endif + + +#endif // __ODM_DBG_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_interface.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_interface.h new file mode 100644 index 0000000..d5732ba --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_interface.h @@ -0,0 +1,413 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __ODM_INTERFACE_H__ +#define __ODM_INTERFACE_H__ + + + +// +// =========== Constant/Structure/Enum/... Define +// + + + +// +// =========== Macro Define +// + +#define _reg_all(_name) ODM_##_name +#define _reg_ic(_name, _ic) ODM_##_name##_ic +#define _bit_all(_name) BIT_##_name +#define _bit_ic(_name, _ic) BIT_##_name##_ic + +// _cat: implemented by Token-Pasting Operator. +#if 0 +#define _cat(_name, _ic_type, _func) \ + ( \ + _func##_all(_name) \ + ) +#endif + +/*=================================== + +#define ODM_REG_DIG_11N 0xC50 +#define ODM_REG_DIG_11AC 0xDDD + +ODM_REG(DIG,_pDM_Odm) +=====================================*/ + +#define _reg_11N(_name) ODM_REG_##_name##_11N +#define _reg_11AC(_name) ODM_REG_##_name##_11AC +#define _bit_11N(_name) ODM_BIT_##_name##_11N +#define _bit_11AC(_name) ODM_BIT_##_name##_11AC + +#ifdef __ECOS +#define _rtk_cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ + _func##_11AC(_name) \ + ) +#else + +#define _cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ + _func##_11AC(_name) \ + ) +#endif +/* +// only sample code +//#define _cat(_name, _ic_type, _func) \ +// ( \ +// ((_ic_type) & ODM_RTL8192C)? _func##_ic(_name, _8192C): \ +// ((_ic_type) & ODM_RTL8192D)? _func##_ic(_name, _8192D): \ +// ((_ic_type) & ODM_RTL8192S)? _func##_ic(_name, _8192S): \ +// ((_ic_type) & ODM_RTL8723A)? _func##_ic(_name, _8723A): \ +// ((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \ +// _func##_ic(_name, _8195) \ +// ) +*/ + +// _name: name of register or bit. +// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" +// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. +#ifdef __ECOS +#define ODM_REG(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _reg) +#define ODM_BIT(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _bit) +#else +#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) +#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) +#endif +typedef enum _ODM_H2C_CMD +{ + /*ODM_H2C_RSSI_REPORT = 0, + ODM_H2C_PSD_RESULT=1, + ODM_H2C_PathDiv = 2, + ODM_H2C_WIFI_CALIBRATION = 3, + ODM_H2C_IQ_CALIBRATION = 4, + ODM_H2C_RA_PARA_ADJUST=5, + ODM_MAX_H2CCMD*/ + PHYDM_H2C_TXBF = 0x41, + ODM_H2C_RSSI_REPORT = 0x42, + ODM_H2C_IQ_CALIBRATION = 0x45, + ODM_H2C_RA_PARA_ADJUST = 0x47, + PHYDM_H2C_DYNAMIC_TX_PATH = 0x48, + PHYDM_H2C_FW_TRACE_EN = 0x49, + ODM_H2C_WIFI_CALIBRATION = 0x6d, + PHYDM_H2C_MU = 0x4a, + ODM_MAX_H2CCMD +}ODM_H2C_CMD; + + +// +// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. +// Suggest HW team to use thread instead of workitem. Windows also support the feature. +// +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +typedef void *PRT_WORK_ITEM ; +typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE; +typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext); + +#if 0 +typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE; + +typedef struct _RT_WORK_ITEM +{ + + RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object. + PVOID Adapter; // Pointer to Adapter object. + PVOID pContext; // Parameter to passed to CallBackFunc(). + RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem. + u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled. + PVOID pPlatformExt; // Pointer to platform-dependent extension. + BOOLEAN bFree; + char szID[36]; // An identity string of this workitem. +}RT_WORK_ITEM, *PRT_WORK_ITEM; + +#endif + + +#endif + +// +// =========== Extern Variable ??? It should be forbidden. +// + + +// +// =========== EXtern Function Prototype +// + + +u1Byte +ODM_Read1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +u2Byte +ODM_Read2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +u4Byte +ODM_Read4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +VOID +ODM_Write1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u1Byte Data + ); + +VOID +ODM_Write2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u2Byte Data + ); + +VOID +ODM_Write4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte Data + ); + +VOID +ODM_SetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +ODM_SetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +ODM_SetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + + +// +// Memory Relative Function. +// +VOID +ODM_AllocateMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID *pPtr, + IN u4Byte length + ); +VOID +ODM_FreeMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID pPtr, + IN u4Byte length + ); + +VOID +ODM_MoveMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID pDest, + IN PVOID pSrc, + IN u4Byte Length + ); + +s4Byte ODM_CompareMemory( + IN PDM_ODM_T pDM_Odm, + IN PVOID pBuf1, + IN PVOID pBuf2, + IN u4Byte length + ); + +void ODM_Memory_Set + (IN PDM_ODM_T pDM_Odm, + IN PVOID pbuf, + IN s1Byte value, + IN u4Byte length); + +// +// ODM MISC-spin lock relative API. +// +#if( DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL|ODM_CE)) +VOID +ODM_AcquireSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ); + +VOID +ODM_ReleaseSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ); +#endif + +// +// ODM MISC-workitem relative API. +// +VOID +ODM_InitializeWorkItem( + IN PDM_ODM_T pDM_Odm, + IN PRT_WORK_ITEM pRtWorkItem, + IN RT_WORKITEM_CALL_BACK RtWorkItemCallback, + IN PVOID pContext, + IN const char* szID + ); + +VOID +ODM_StartWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_StopWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_FreeWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_ScheduleWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_IsWorkItemScheduled( + IN PRT_WORK_ITEM pRtWorkItem + ); + +// +// ODM Timer relative API. +// +VOID +ODM_StallExecution( + IN u4Byte usDelay + ); + +VOID +ODM_delay_ms(IN u4Byte ms); + + + +VOID +ODM_delay_us(IN u4Byte us); + +VOID +ODM_sleep_ms(IN u4Byte ms); + +VOID +ODM_sleep_us(IN u4Byte us); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP|ODM_ADSL)) +VOID +ODM_SetTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN u4Byte msDelay + ); + +VOID +ODM_InitializeTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN RT_TIMER_CALL_BACK CallBackFunc, + IN PVOID pContext, + IN const char* szID + ); + +VOID +ODM_CancelTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ); + +VOID +ODM_ReleaseTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ); +#endif + +// +// ODM FW relative API. +// +VOID +ODM_FillH2CCmd( + IN PDM_ODM_T pDM_Odm, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +); + +u8Byte +ODM_GetCurrentTime( + IN PDM_ODM_T pDM_Odm + ); +u8Byte +ODM_GetProgressingTime( + IN PDM_ODM_T pDM_Odm, + IN u8Byte Start_Time + ); + +#endif // __ODM_INTERFACE_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_precomp.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_precomp.h new file mode 100644 index 0000000..84e0bf4 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_precomp.h @@ -0,0 +1,349 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_PRECOMP_H__ +#define __ODM_PRECOMP_H__ + +#include "phydm_types.h" + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting. + +#else + +#define TEST_FALG___ 1 + +#endif + +//2 Config Flags and Structs - defined by each ODM Type + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "../8192cd_cfg.h" + #include "../odm_inc.h" + + #include "../8192cd.h" + #include "../8192cd_util.h" + #ifdef _BIG_ENDIAN_ + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #else + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #endif + + #ifdef AP_BUILD_WORKAROUND + #include "../8192cd_headers.h" + #include "../8192cd_debug.h" + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL) + // Flags + #include "../8192cd_cfg.h" // OUTSRC needs ADSL config flags. + #include "../odm_inc.h" // OUTSRC needs some extra flags. + // Data Structure + #include "../common_types.h" // OUTSRC and rtl8192cd both needs basic type such as UINT8 and BIT0. + #include "../8192cd.h" // OUTSRC needs basic ADSL struct definition. + #include "../8192cd_util.h" // OUTSRC needs basic I/O function. + #ifdef _BIG_ENDIAN_ + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #else + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #endif + + #ifdef ADSL_AP_BUILD_WORKAROUND + // NESTED_INC: Functions defined outside should not be included!! Marked by Annie, 2011-10-14. + #include "../8192cd_headers.h" + #include "../8192cd_debug.h" + #endif + +#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE) +#define BEAMFORMING_SUPPORT 0 +#elif (DM_ODM_SUPPORT_TYPE ==ODM_IOT) +#define BEAMFORMING_SUPPORT 0 +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "mp_precomp.h" + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE +#endif + + +//2 Hardware Parameter Files + + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#if (RTL8192C_SUPPORT==1) + #include "rtl8192c/Hal8192CEFWImg_AP.h" + #include "rtl8192c/Hal8192CEPHYImg_AP.h" + #include "rtl8192c/Hal8192CEMACImg_AP.h" +#endif +#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL) + #include "rtl8192c/Hal8192CEFWImg_ADSL.h" + #include "rtl8192c/Hal8192CEPHYImg_ADSL.h" + #include "rtl8192c/Hal8192CEMACImg_ADSL.h" + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #if(RTL8192CE_SUPPORT ==1) + #include "rtl8192c/Hal8192CEFWImg_CE.h" + #include "rtl8192c/Hal8192CEPHYImg_CE.h" + #include "rtl8192c/Hal8192CEMACImg_CE.h" + #endif + + #if(RTL8192CU_SUPPORT ==1) + #include "rtl8192c/Hal8192CUFWImg_CE.h" + #include "rtl8192c/Hal8192CUPHYImg_CE.h" + #include "rtl8192c/Hal8192CUMACImg_CE.h" + #endif + + #if(RTL8192DE_SUPPORT ==1) + #include "rtl8192d/Hal8192DEFWImg_CE.h" + #include "rtl8192d/Hal8192DEPHYImg_CE.h" + #include "rtl8192d/Hal8192DEMACImg_CE.h" + #endif + + #if(RTL8192DU_SUPPORT ==1) + #include "rtl8192d/Hal8192DUFWImg_CE.h" + #include "rtl8192d/Hal8192DUPHYImg_CE.h" + #include "rtl8192d/Hal8192DUMACImg_CE.h" + #endif + + #if(RTL8723AS_SUPPORT==1) + #include "rtl8723a/Hal8723SHWImg_CE.h" + #endif + + #if(RTL8723AU_SUPPORT==1) + #include "rtl8723a/Hal8723UHWImg_CE.h" + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#endif + + +//2 OutSrc Header Files +#if (RTL8188E_SUPPORT==1) +// Old ODM +#include "rtl8188e\odm.h" +#include "rtl8188e\odm_HWConfig.h" +#include "rtl8188e\odm_debug.h" +#include "rtl8188e\odm_RegDefine11AC.h" +#include "rtl8188e\odm_RegDefine11N.h" +#include "rtl8188e\odm_interface.h" +#include "rtl8188e\odm_reg.h" +#include "rtl8188e\Hal8188EAdaptivity.h" +#else +// new ODM +#include "phydm.h" +#include "phydm_HWConfig.h" +#include "phydm_debug.h" +#include "phydm_RegDefine11AC.h" +#include "phydm_RegDefine11N.h" +#include "phydm_AntDiv.h" +#include "phydm_EdcaTurboCheck.h" +#include "phydm_DIG.h" +#include "PhyDM_Adaptivity.h" +#include "phydm_PathDiv.h" +#include "phydm_RaInfo.h" +#include "phydm_DynamicBBPowerSaving.h" +#include "phydm_DynamicTxPower.h" +#include "phydm_CfoTracking.h" +#include "phydm_NoiseMonitor.h" +#include "phydm_interface.h" +#include "phydm_reg.h" +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#if (RTL8192C_SUPPORT==1) + #include "rtl8192c/HalDMOutSrc8192C_AP.h" +#endif +#if (RTL8188E_SUPPORT==1) + #include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training +#endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL) + #include "rtl8192c/HalDMOutSrc8192C_ADSL.h" + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + //#include "hal_com.h" + #include "HalPhyRf.h" + #if (RTL8192C_SUPPORT==1) + #ifdef CONFIG_INTEL_PROXIM + #include "../proxim/intel_proxim.h" + #endif + #include "rtl8192c/HalDMOutSrc8192C_CE.h" + #include + #endif + + #if (RTL8192D_SUPPORT==1) + #include "rtl8192d/HalDMOutSrc8192D_CE.h" + #include "rtl8192d_hal.h" + #endif + + #if (RTL8723A_SUPPORT==1) + #include "rtl8192c/HalDMOutSrc8192C_CE.h" //for IQK,LCK,Power-tracking + #include "../rtl8723a/rtl8723a_hal.h" + #endif + + #if (RTL8188E_SUPPORT==1) + #include "rtl8188e/HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking + #include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training + #include "../rtl8188e/rtl8188e_hal.h" + #endif + + #if (RTL8192E_SUPPORT==1) + #include "rtl8192e/HalPhyRf_8192e.h"//for IQK,LCK,Power-tracking + #include "rtl8192e_hal.h" + #endif + + #if (RTL8812A_SUPPORT==1) + #include "rtl8812a/HalPhyRf_8812A.h"//for IQK,LCK,Power-tracking + #include "rtl8812a_hal.h" + #endif + + #if (RTL8821A_SUPPORT==1) + #include "rtl8821a/HalPhyRf_8821A.h"//for IQK,LCK,Power-tracking + #include "rtl8812a/HalPhyRf_8812A.h"//for IQK,LCK,Power-tracking + #include "rtl8812a_hal.h" + #endif + + #if (RTL8723B_SUPPORT==1) + #include "rtl8723b/HalPhyRf_8723B.h"//for IQK,LCK,Power-tracking + #include "rtl8723b_hal.h" + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + #include "HalPhyRf.h" + #if (RTL8195A_SUPPORT==1) + #include "rtl8195a/HalPhyRf_8195A.h"//for IQK,LCK,Power-tracking + #include "rtl8195a_hal.h" + #endif + + #if (RTL8711B_SUPPORT==1) + #include "rtl8711b/HalPhyRf_8711b.h"//for IQK,LCK,Power-tracking + #include "rtl8711b_hal.h" + #endif +#endif + + +#if (RTL8192C_SUPPORT==1) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#include "rtl8192c/Hal8192CHWImg_MAC.h" +#include "rtl8192c/Hal8192CHWImg_RF.h" +#include "rtl8192c/Hal8192CHWImg_BB.h" +#include "rtl8192c/Hal8192CHWImg_FW.h" +#endif +#include "rtl8192c/phydm_RTL8192C.h" +#endif +#if (RTL8192D_SUPPORT==1) +#include "rtl8192d/phydm_RTL8192D.h" +#endif + +#if (RTL8723A_SUPPORT==1) +#include "rtl8723a/HalHWImg8723A_MAC.h" +#include "rtl8723a/HalHWImg8723A_RF.h" +#include "rtl8723a/HalHWImg8723A_BB.h" +#include "rtl8723a/HalHWImg8723A_FW.h" +#include "rtl8723a/phydm_RegConfig8723A.h" +#endif + +#if (RTL8188E_SUPPORT==1) +#include "rtl8188e/HalHWImg8188E_MAC.h" +#include "rtl8188e/HalHWImg8188E_RF.h" +#include "rtl8188e/HalHWImg8188E_BB.h" +#include "rtl8188e/HalHWImg8188E_FW.h" +#include "rtl8188e/Hal8188EReg.h" + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +#include "rtl8188e/HalPhyRf_8188e.h" +#endif + +#if (TEST_CHIP_SUPPORT == 1) +#include "rtl8188e/HalHWImg8188E_TestChip_MAC.h" +#include "rtl8188e/HalHWImg8188E_TestChip_RF.h" +#include "rtl8188e/HalHWImg8188E_TestChip_BB.h" +#endif + + +#include "rtl8188e/odm_RegConfig8188E.h" +#include "rtl8188e/odm_RTL8188E.h" +#endif + +#if (RTL8192E_SUPPORT==1) +#include "rtl8192e/HalHWImg8192E_MAC.h" +#include "rtl8192e/HalHWImg8192E_RF.h" +#include "rtl8192e/HalHWImg8192E_BB.h" +#include "rtl8192e/HalHWImg8192E_FW.h" +#include "rtl8192e/Hal8192EReg.h" +#include "rtl8192e/phydm_RegConfig8192E.h" +#include "rtl8192e/phydm_RTL8192E.h" +#endif + +#if (RTL8723B_SUPPORT==1) +#include "rtl8723b/HalHWImg8723B_MAC.h" +#include "rtl8723b/HalHWImg8723B_RF.h" +#include "rtl8723b/HalHWImg8723B_BB.h" +#include "rtl8723b/HalHWImg8723B_FW.h" +#include "rtl8723b/HalHWImg8723B_MP.h" +#include "rtl8723b/Hal8723BReg.h" +#include "rtl8723b/phydm_RTL8723B.h" +#include "rtl8723b/phydm_RegConfig8723B.h" +#endif + +#if (RTL8812A_SUPPORT==1) +#include "rtl8812a/HalHWImg8812A_MAC.h" +#include "rtl8812a/HalHWImg8812A_RF.h" +#include "rtl8812a/HalHWImg8812A_BB.h" +#include "rtl8812a/HalHWImg8812A_FW.h" +#include "rtl8812a/phydm_RegConfig8812A.h" +#include "rtl8812a/phydm_RTL8812A.h" +#endif + + +#if (RTL8821A_SUPPORT==1) +#include "rtl8821a/HalHWImg8821A_MAC.h" +#include "rtl8821a/HalHWImg8821A_RF.h" +#include "rtl8821a/HalHWImg8821A_BB.h" +#include "rtl8821a/HalHWImg8821A_FW.h" +#include "rtl8821a/phydm_RegConfig8821A.h" +#include "rtl8821a/phydm_RTL8821A.h" +#endif + +#if (RTL8195A_SUPPORT==1) +#include "rtl8195a/halhwimg8195a_mac.h" +#include "rtl8195a/halhwimg8195a_rf.h" +#include "rtl8195a/halhwimg8195a_bb.h" +#include "rtl8195a/Hal8195AReg.h" +#include "rtl8195a/phydm_RTL8195A.h" +#include "rtl8195a/phydm_RegConfig8195A.h" +#include "rtl8195a/ROM_RTL8195A_PHYDM.h" +#include "rtl8195a/Hal8195ARateAdaptive.h" +#endif + +#if (RTL8711B_SUPPORT==1) +#include "rtl8711b/HalHWImg8711B_MAC.h" +#include "rtl8711b/HalHWImg8711B_RF.h" +#include "rtl8711b/HalHWImg8711B_BB.h" +#include "rtl8711b/HalHWImg8711B_FW.h" +#include "rtl8711b/HalHWImg8711B_MP.h" +#include "rtl8711b/Hal8711BReg.h" +#include "rtl8711b/phydm_RTL8711B.h" +#include "rtl8711b/phydm_RegConfig8711B.h" +#include "rtl8711b/ROM_RTL8711B_PHYDM.h" +#include "rtl8711b/Hal8711BRateAdaptive.h" +#endif + +#endif // __ODM_PRECOMP_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_reg.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_reg.h new file mode 100644 index 0000000..e842413 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_reg.h @@ -0,0 +1,208 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +//============================================================ +// File Name: odm_reg.h +// +// Description: +// +// This file is for general register definition. +// +// +//============================================================ +#ifndef __HAL_ODM_REG_H__ +#define __HAL_ODM_REG_H__ + +// +// Register Definition +// + +//MAC REG +#define ODM_BB_RESET 0x002 +#define ODM_DUMMY 0x4fe +#define RF_T_METER_OLD 0x24 +#define RF_T_METER_NEW 0x42 + +#define ODM_EDCA_VO_PARAM 0x500 +#define ODM_EDCA_VI_PARAM 0x504 +#define ODM_EDCA_BE_PARAM 0x508 +#define ODM_EDCA_BK_PARAM 0x50C +#define ODM_TXPAUSE 0x522 + +//BB REG +#define ODM_FPGA_PHY0_PAGE8 0x800 +#define ODM_PSD_SETTING 0x808 +#define ODM_AFE_SETTING 0x818 +#define ODM_TXAGC_B_6_18 0x830 +#define ODM_TXAGC_B_24_54 0x834 +#define ODM_TXAGC_B_MCS32_5 0x838 +#define ODM_TXAGC_B_MCS0_MCS3 0x83c +#define ODM_TXAGC_B_MCS4_MCS7 0x848 +#define ODM_TXAGC_B_MCS8_MCS11 0x84c +#define ODM_ANALOG_REGISTER 0x85c +#define ODM_RF_INTERFACE_OUTPUT 0x860 +#define ODM_TXAGC_B_MCS12_MCS15 0x868 +#define ODM_TXAGC_B_11_A_2_11 0x86c +#define ODM_AD_DA_LSB_MASK 0x874 +#define ODM_ENABLE_3_WIRE 0x88c +#define ODM_PSD_REPORT 0x8b4 +#define ODM_R_ANT_SELECT 0x90c +#define ODM_CCK_ANT_SELECT 0xa07 +#define ODM_CCK_PD_THRESH 0xa0a +#define ODM_CCK_RF_REG1 0xa11 +#define ODM_CCK_MATCH_FILTER 0xa20 +#define ODM_CCK_RAKE_MAC 0xa2e +#define ODM_CCK_CNT_RESET 0xa2d +#define ODM_CCK_TX_DIVERSITY 0xa2f +#define ODM_CCK_FA_CNT_MSB 0xa5b +#define ODM_CCK_FA_CNT_LSB 0xa5c +#define ODM_CCK_NEW_FUNCTION 0xa75 +#define ODM_OFDM_PHY0_PAGE_C 0xc00 +#define ODM_OFDM_RX_ANT 0xc04 +#define ODM_R_A_RXIQI 0xc14 +#define ODM_R_A_AGC_CORE1 0xc50 +#define ODM_R_A_AGC_CORE2 0xc54 +#define ODM_R_B_AGC_CORE1 0xc58 +#define ODM_R_AGC_PAR 0xc70 +#define ODM_R_HTSTF_AGC_PAR 0xc7c +#define ODM_TX_PWR_TRAINING_A 0xc90 +#define ODM_TX_PWR_TRAINING_B 0xc98 +#define ODM_OFDM_FA_CNT1 0xcf0 +#define ODM_OFDM_PHY0_PAGE_D 0xd00 +#define ODM_OFDM_FA_CNT2 0xda0 +#define ODM_OFDM_FA_CNT3 0xda4 +#define ODM_OFDM_FA_CNT4 0xda8 +#define ODM_TXAGC_A_6_18 0xe00 +#define ODM_TXAGC_A_24_54 0xe04 +#define ODM_TXAGC_A_1_MCS32 0xe08 +#define ODM_TXAGC_A_MCS0_MCS3 0xe10 +#define ODM_TXAGC_A_MCS4_MCS7 0xe14 +#define ODM_TXAGC_A_MCS8_MCS11 0xe18 +#define ODM_TXAGC_A_MCS12_MCS15 0xe1c + +//RF REG +#define ODM_GAIN_SETTING 0x00 +#define ODM_CHANNEL 0x18 +#define ODM_RF_T_METER 0x24 +#define ODM_RF_T_METER_92D 0x42 +#define ODM_RF_T_METER_88E 0x42 +#define ODM_RF_T_METER_92E 0x42 +#define ODM_RF_T_METER_8812 0x42 + +//Ant Detect Reg +#define ODM_DPDT 0x300 + +//PSD Init +#define ODM_PSDREG 0x808 + +//92D Path Div +#define PATHDIV_REG 0xB30 +#define PATHDIV_TRI 0xBA0 + + +// +// Bitmap Definition +// +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) +// TX AGC +#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 +#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 +#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 +#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c +#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 +#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 +#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 +#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c +#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 +#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 +#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 +#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c +#if defined(CONFIG_WLAN_HAL_8814AE) +#define rTxAGC_A_MCS19_MCS16_JAguar 0xcd8 +#define rTxAGC_A_MCS23_MCS20_JAguar 0xcdc +#define rTxAGC_A_Nss3Index3_Nss3Index0_JAguar 0xce0 +#define rTxAGC_A_Nss3Index7_Nss3Index4_JAguar 0xce4 +#define rTxAGC_A_Nss3Index9_Nss3Index8_JAguar 0xce8 +#endif +#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 +#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 +#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 +#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c +#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 +#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 +#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 +#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c +#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 +#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 +#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 +#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c +#if defined(CONFIG_WLAN_HAL_8814AE) +#define rTxAGC_B_MCS19_MCS16_JAguar 0xed8 +#define rTxAGC_B_MCS23_MCS20_JAguar 0xedc +#define rTxAGC_B_Nss3Index3_Nss3Index0_JAguar 0xee0 +#define rTxAGC_B_Nss3Index7_Nss3Index4_JAguar 0xee4 +#define rTxAGC_B_Nss3Index9_Nss3Index8_JAguar 0xee8 +#define rTxAGC_C_CCK11_CCK1_JAguar 0x1820 +#define rTxAGC_C_Ofdm18_Ofdm6_JAguar 0x1824 +#define rTxAGC_C_Ofdm54_Ofdm24_JAguar 0x1828 +#define rTxAGC_C_MCS3_MCS0_JAguar 0x182c +#define rTxAGC_C_MCS7_MCS4_JAguar 0x1830 +#define rTxAGC_C_MCS11_MCS8_JAguar 0x1834 +#define rTxAGC_C_MCS15_MCS12_JAguar 0x1838 +#define rTxAGC_C_Nss1Index3_Nss1Index0_JAguar 0x183c +#define rTxAGC_C_Nss1Index7_Nss1Index4_JAguar 0x1840 +#define rTxAGC_C_Nss2Index1_Nss1Index8_JAguar 0x1844 +#define rTxAGC_C_Nss2Index5_Nss2Index2_JAguar 0x1848 +#define rTxAGC_C_Nss2Index9_Nss2Index6_JAguar 0x184c +#define rTxAGC_C_MCS19_MCS16_JAguar 0x18d8 +#define rTxAGC_C_MCS23_MCS20_JAguar 0x18dc +#define rTxAGC_C_Nss3Index3_Nss3Index0_JAguar 0x18e0 +#define rTxAGC_C_Nss3Index7_Nss3Index4_JAguar 0x18e4 +#define rTxAGC_C_Nss3Index9_Nss3Index8_JAguar 0x18e8 +#define rTxAGC_D_CCK11_CCK1_JAguar 0x1a20 +#define rTxAGC_D_Ofdm18_Ofdm6_JAguar 0x1a24 +#define rTxAGC_D_Ofdm54_Ofdm24_JAguar 0x1a28 +#define rTxAGC_D_MCS3_MCS0_JAguar 0x1a2c +#define rTxAGC_D_MCS7_MCS4_JAguar 0x1a30 +#define rTxAGC_D_MCS11_MCS8_JAguar 0x1a34 +#define rTxAGC_D_MCS15_MCS12_JAguar 0x1a38 +#define rTxAGC_D_Nss1Index3_Nss1Index0_JAguar 0x1a3c +#define rTxAGC_D_Nss1Index7_Nss1Index4_JAguar 0x1a40 +#define rTxAGC_D_Nss2Index1_Nss1Index8_JAguar 0x1a44 +#define rTxAGC_D_Nss2Index5_Nss2Index2_JAguar 0x1a48 +#define rTxAGC_D_Nss2Index9_Nss2Index6_JAguar 0x1a4c +#define rTxAGC_D_MCS19_MCS16_JAguar 0x1ad8 +#define rTxAGC_D_MCS23_MCS20_JAguar 0x1adc +#define rTxAGC_D_Nss3Index3_Nss3Index0_JAguar 0x1ae0 +#define rTxAGC_D_Nss3Index7_Nss3Index4_JAguar 0x1ae4 +#define rTxAGC_D_Nss3Index9_Nss3Index8_JAguar 0x1ae8 +#endif + +#define bTxAGC_byte0_Jaguar 0xff +#define bTxAGC_byte1_Jaguar 0xff00 +#define bTxAGC_byte2_Jaguar 0xff0000 +#define bTxAGC_byte3_Jaguar 0xff000000 +#endif + +#define BIT_FA_RESET BIT0 + + + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_types.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_types.h new file mode 100644 index 0000000..71cbafc --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_types.h @@ -0,0 +1,442 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_TYPES_H__ +#define __ODM_TYPES_H__ + +#define ODM_RATEMCS15_SG 0x1c +#define ODM_RATEMCS32 0x20 + + +// CCK Rates, TxHT = 0 +#define ODM_RATE1M 0x00 +#define ODM_RATE2M 0x01 +#define ODM_RATE5_5M 0x02 +#define ODM_RATE11M 0x03 +// OFDM Rates, TxHT = 0 +#define ODM_RATE6M 0x04 +#define ODM_RATE9M 0x05 +#define ODM_RATE12M 0x06 +#define ODM_RATE18M 0x07 +#define ODM_RATE24M 0x08 +#define ODM_RATE36M 0x09 +#define ODM_RATE48M 0x0A +#define ODM_RATE54M 0x0B +// MCS Rates, TxHT = 1 +#define ODM_RATEMCS0 0x0C +#define ODM_RATEMCS1 0x0D +#define ODM_RATEMCS2 0x0E +#define ODM_RATEMCS3 0x0F +#define ODM_RATEMCS4 0x10 +#define ODM_RATEMCS5 0x11 +#define ODM_RATEMCS6 0x12 +#define ODM_RATEMCS7 0x13 +#define ODM_RATEMCS8 0x14 +#define ODM_RATEMCS9 0x15 +#define ODM_RATEMCS10 0x16 +#define ODM_RATEMCS11 0x17 +#define ODM_RATEMCS12 0x18 +#define ODM_RATEMCS13 0x19 +#define ODM_RATEMCS14 0x1A +#define ODM_RATEMCS15 0x1B +#define ODM_RATEMCS16 0x1C +#define ODM_RATEMCS17 0x1D +#define ODM_RATEMCS18 0x1E +#define ODM_RATEMCS19 0x1F +#define ODM_RATEMCS20 0x20 +#define ODM_RATEMCS21 0x21 +#define ODM_RATEMCS22 0x22 +#define ODM_RATEMCS23 0x23 +#define ODM_RATEMCS24 0x24 +#define ODM_RATEMCS25 0x25 +#define ODM_RATEMCS26 0x26 +#define ODM_RATEMCS27 0x27 +#define ODM_RATEMCS28 0x28 +#define ODM_RATEMCS29 0x29 +#define ODM_RATEMCS30 0x2A +#define ODM_RATEMCS31 0x2B +#define ODM_RATEVHTSS1MCS0 0x2C +#define ODM_RATEVHTSS1MCS1 0x2D +#define ODM_RATEVHTSS1MCS2 0x2E +#define ODM_RATEVHTSS1MCS3 0x2F +#define ODM_RATEVHTSS1MCS4 0x30 +#define ODM_RATEVHTSS1MCS5 0x31 +#define ODM_RATEVHTSS1MCS6 0x32 +#define ODM_RATEVHTSS1MCS7 0x33 +#define ODM_RATEVHTSS1MCS8 0x34 +#define ODM_RATEVHTSS1MCS9 0x35 +#define ODM_RATEVHTSS2MCS0 0x36 +#define ODM_RATEVHTSS2MCS1 0x37 +#define ODM_RATEVHTSS2MCS2 0x38 +#define ODM_RATEVHTSS2MCS3 0x39 +#define ODM_RATEVHTSS2MCS4 0x3A +#define ODM_RATEVHTSS2MCS5 0x3B +#define ODM_RATEVHTSS2MCS6 0x3C +#define ODM_RATEVHTSS2MCS7 0x3D +#define ODM_RATEVHTSS2MCS8 0x3E +#define ODM_RATEVHTSS2MCS9 0x3F +#define ODM_RATEVHTSS3MCS0 0x40 +#define ODM_RATEVHTSS3MCS1 0x41 +#define ODM_RATEVHTSS3MCS2 0x42 +#define ODM_RATEVHTSS3MCS3 0x43 +#define ODM_RATEVHTSS3MCS4 0x44 +#define ODM_RATEVHTSS3MCS5 0x45 +#define ODM_RATEVHTSS3MCS6 0x46 +#define ODM_RATEVHTSS3MCS7 0x47 +#define ODM_RATEVHTSS3MCS8 0x48 +#define ODM_RATEVHTSS3MCS9 0x49 +#define ODM_RATEVHTSS4MCS0 0x4A +#define ODM_RATEVHTSS4MCS1 0x4B +#define ODM_RATEVHTSS4MCS2 0x4C +#define ODM_RATEVHTSS4MCS3 0x4D +#define ODM_RATEVHTSS4MCS4 0x4E +#define ODM_RATEVHTSS4MCS5 0x4F +#define ODM_RATEVHTSS4MCS6 0x50 +#define ODM_RATEVHTSS4MCS7 0x51 +#define ODM_RATEVHTSS4MCS8 0x52 +#define ODM_RATEVHTSS4MCS9 0x53 + + +// +// Define Different SW team support +// +#define ODM_AP 0x01 //BIT0 +#define ODM_ADSL 0x02 //BIT1 +#define ODM_CE 0x04 //BIT2 +#define ODM_WIN 0x08 //BIT3 +#define ODM_IOT 0x10 //BIT4 + +#define DM_ODM_SUPPORT_TYPE ODM_IOT + +// Deifne HW endian support +#define ODM_ENDIAN_BIG 0 +#define ODM_ENDIAN_LITTLE 1 + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->DM_OutSrc))) +#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_IOT)) +#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->odmpriv))) +#endif + +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +#define RT_PCI_INTERFACE 1 +#define RT_USB_INTERFACE 2 +#define RT_SDIO_INTERFACE 3 +#define RT_LXBUS_INTERFACE 4 +#endif + +typedef enum _HAL_STATUS{ + HAL_STATUS_SUCCESS, + HAL_STATUS_FAILURE, + /*RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED,*/ +}HAL_STATUS,*PHAL_STATUS; + + +#if( (DM_ODM_SUPPORT_TYPE == ODM_AP) ||(DM_ODM_SUPPORT_TYPE == ODM_ADSL) || (DM_ODM_SUPPORT_TYPE == ODM_CE)) + +#define VISTA_USB_RX_REVISE 0 + +// +// Declare for ODM spin lock defintion temporarily fro compile pass. +// +typedef enum _RT_SPINLOCK_TYPE{ + RT_TX_SPINLOCK = 1, + RT_RX_SPINLOCK = 2, + RT_RM_SPINLOCK = 3, + RT_CAM_SPINLOCK = 4, + RT_SCAN_SPINLOCK = 5, + RT_LOG_SPINLOCK = 7, + RT_BW_SPINLOCK = 8, + RT_CHNLOP_SPINLOCK = 9, + RT_RF_OPERATE_SPINLOCK = 10, + RT_INITIAL_SPINLOCK = 11, + RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30. +#if VISTA_USB_RX_REVISE + RT_USBRX_CONTEXT_SPINLOCK = 13, + RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR +#endif + //Shall we define Ndis 6.2 SpinLock Here ? + RT_PORT_SPINLOCK=16, + RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09. + + RT_BTData_SPINLOCK=25, + + RT_WAPI_OPTION_SPINLOCK=26, + RT_WAPI_RX_SPINLOCK=27, + + // add for 92D CCK control issue + RT_CCK_PAGEA_SPINLOCK = 28, + RT_BUFFER_SPINLOCK = 29, + RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30, + RT_GEN_TEMP_BUF_SPINLOCK = 31, + RT_AWB_SPINLOCK = 32, + RT_FW_PS_SPINLOCK = 33, + RT_HW_TIMER_SPIN_LOCK = 34, + RT_MPT_WI_SPINLOCK = 35, + RT_P2P_SPIN_LOCK = 36, // Protect P2P context + RT_DBG_SPIN_LOCK = 37, + RT_IQK_SPINLOCK = 38, + RT_PENDED_OID_SPINLOCK = 39, + RT_CHNLLIST_SPINLOCK = 40, + RT_INDIC_SPINLOCK = 41, //protect indication +}RT_SPINLOCK_TYPE; + +#endif + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define STA_INFO_T RT_WLAN_STA + #define PSTA_INFO_T PRT_WLAN_STA + +// typedef unsigned long u4Byte,*pu4Byte; +#define CONFIG_HW_ANTENNA_DIVERSITY +#define CONFIG_SW_ANTENNA_DIVERSITY + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + // To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. + #define ADSL_AP_BUILD_WORKAROUND + #define AP_BUILD_WORKAROUND + // +#ifdef CONFIG_ANT_SWITCH + #define CONFIG_HW_ANTENNA_DIVERSITY + #if ( defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) ) + #define CONFIG_NOT_SUPPORT_ANTDIV + #elif( !defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) ) + #define CONFIG_2G_SUPPORT_ANTDIV + #elif( defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY) ) + #define CONFIG_5G_SUPPORT_ANTDIV + #elif( !defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY) ) + #define CONFIG_2G5G_SUPPORT_ANTDIV + #endif +#endif + + #ifdef AP_BUILD_WORKAROUND + #include "../typedef.h" + #else + typedef void VOID,*PVOID; + typedef unsigned char BOOLEAN,*PBOOLEAN; + typedef unsigned char u1Byte,*pu1Byte; + typedef unsigned short u2Byte,*pu2Byte; + typedef unsigned int u4Byte,*pu4Byte; + typedef unsigned long long u8Byte,*pu8Byte; + typedef char s1Byte,*ps1Byte; + typedef short s2Byte,*ps2Byte; + typedef long s4Byte,*ps4Byte; + typedef long long s8Byte,*ps8Byte; + #endif + + typedef struct rtl8192cd_priv *prtl8192cd_priv; + typedef struct stat_info STA_INFO_T,*PSTA_INFO_T; + typedef struct timer_list RT_TIMER, *PRT_TIMER; + typedef void * RT_TIMER_CALL_BACK; + + #define DEV_BUS_TYPE RT_PCI_INTERFACE + + #define _TRUE 1 + #define _FALSE 0 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL) + + // To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. + #define ADSL_AP_BUILD_WORKAROUND + #define ADSL_BUILD_WORKAROUND + // + + typedef unsigned char BOOLEAN,*PBOOLEAN; + typedef unsigned char u1Byte,*pu1Byte; + typedef unsigned short u2Byte,*pu2Byte; + typedef unsigned int u4Byte,*pu4Byte; + typedef unsigned long long u8Byte,*pu8Byte; + typedef char s1Byte,*ps1Byte; + typedef short s2Byte,*ps2Byte; + typedef long s4Byte,*ps4Byte; + typedef long long s8Byte,*ps8Byte; + + typedef struct rtl8192cd_priv *prtl8192cd_priv; + typedef struct stat_info STA_INFO_T,*PSTA_INFO_T; + typedef struct timer_list RT_TIMER, *PRT_TIMER; + typedef void * RT_TIMER_CALL_BACK; + + #define DEV_BUS_TYPE RT_PCI_INTERFACE + + #define _TRUE 1 + #define _FALSE 0 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include + +#if 0 + typedef u8 u1Byte, *pu1Byte; + typedef u16 u2Byte,*pu2Byte; + typedef u32 u4Byte,*pu4Byte; + typedef u64 u8Byte,*pu8Byte; + typedef s8 s1Byte,*ps1Byte; + typedef s16 s2Byte,*ps2Byte; + typedef s32 s4Byte,*ps4Byte; + typedef s64 s8Byte,*ps8Byte; +#else + #define u1Byte u8 + #define pu1Byte u8* + + #define u2Byte u16 + #define pu2Byte u16* + + #define u4Byte u32 + #define pu4Byte u32* + + #define u8Byte u64 + #define pu8Byte u64* + + #define s1Byte s8 + #define ps1Byte s8* + + #define s2Byte s16 + #define ps2Byte s16* + + #define s4Byte s32 + #define ps4Byte s32* + + #define s8Byte s64 + #define ps8Byte s64* + +#endif + #ifdef CONFIG_USB_HCI + #define DEV_BUS_TYPE RT_USB_INTERFACE + #elif defined(CONFIG_PCI_HCI) + #define DEV_BUS_TYPE RT_PCI_INTERFACE + #elif defined(CONFIG_SDIO_HCI) + #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #elif defined(CONFIG_GSPI_HCI) + #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #elif defined(CONFIG_LX_HCI) + #define DEV_BUS_TYPE RT_PCI_INTERFACE + #endif + + + #if defined(CONFIG_LITTLE_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #elif defined (CONFIG_BIG_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #endif + + typedef struct timer_list RT_TIMER, *PRT_TIMER; + typedef void * RT_TIMER_CALL_BACK; + #define STA_INFO_T struct sta_info + #define PSTA_INFO_T struct sta_info * + + + +#ifndef TRUE + #define TRUE _TRUE +#endif +#ifndef FALSE + #define FALSE _FALSE +#endif + + + #define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value) + #define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value) + #define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value) + + //define useless flag to avoid compile warning + #define USE_WORKITEM 0 + #define FOR_BRAZIL_PRETEST 0 + #define FPGA_TWO_MAC_VERIFICATION 0 + #define RTL8881A_SUPPORT 0 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + #include + + #define RA_MASK_PHYDMLIZE_CE 1 + + typedef unsigned char u1Byte,*pu1Byte; + typedef unsigned short u2Byte,*pu2Byte; + typedef unsigned int u4Byte,*pu4Byte; + typedef unsigned long long u8Byte,*pu8Byte; + typedef signed char s1Byte,*ps1Byte; /* GCC ROM char = unsigned char */ + typedef signed short s2Byte,*ps2Byte; + typedef signed long s4Byte,*ps4Byte; + typedef long long s8Byte,*ps8Byte; + + typedef struct sta_info STA_INFO_T,*PSTA_INFO_T; + + #if defined(CONFIG_GSPI_HCI) + #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #elif defined(CONFIG_LX_HCI) + #define DEV_BUS_TYPE RT_LXBUS_INTERFACE + #endif + + // Array_MP_8195A_TXPWR_LMT[] + typedef enum _ODM_PW_LMT_REGULATION_TYPE{ + PW_LMT_REGU_NULL = 0, + PW_LMT_REGU_FCC = 1, + PW_LMT_REGU_ETSI = 2, + PW_LMT_REGU_MKK = 3, + PW_LMT_REGU_WW13 = 4 + }ODM_PW_LMT_REGULATION_TYPE; + + typedef enum _ODM_PW_LMT_BAND_TYPE{ + PW_LMT_BAND_NULL = 0, + PW_LMT_BAND_2_4G = 1, + PW_LMT_BAND_5G = 2 + }ODM_PW_LMT_BAND_TYPE; + + typedef enum _ODM_PW_LMT_BANDWIDTH_TYPE{ + PW_LMT_BW_NULL = 0, + PW_LMT_BW_20M = 1, + PW_LMT_BW_40M = 2, + PW_LMT_BW_80M = 3 + }ODM_PW_LMT_BANDWIDTH_TYPE; + + typedef enum _ODM_PW_LMT_RATESECTION_TYPE{ + PW_LMT_RS_NULL = 0, + PW_LMT_RS_CCK = 1, + PW_LMT_RS_OFDM = 2, + PW_LMT_RS_HT = 3, + PW_LMT_RS_VHT = 4 + }ODM_PW_LMT_RATESECTION_TYPE; + + typedef enum _ODM_PW_LMT_RFPATH_TYPE{ + PW_LMT_PH_NULL = 0, + PW_LMT_PH_1T = 1, + PW_LMT_PH_2T = 2, + PW_LMT_PH_3T = 3, + PW_LMT_PH_4T = 4 + }ODM_PW_LMT_RFPATH_TYPE; + + #if defined(CONFIG_LITTLE_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #elif defined (CONFIG_BIG_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #endif + +#endif + +#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) +#define COND_ELSE 2 +#define COND_ENDIF 3 + +#endif // __ODM_TYPES_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rom_odm_interface.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rom_odm_interface.h new file mode 100644 index 0000000..ddf25cf --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rom_odm_interface.h @@ -0,0 +1,59 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __ROM_ODM_INTERFACE_H__ +#define __ROM_ODM_INTERFACE_H__ + +#include "hal_api.h" + +// +// =========== Macro Define +// +#define ODM_Read1Byte(pDM_Odm, RegAddr) HAL_READ8(WIFI_REG_BASE, RegAddr) +#define ODM_Read2Byte(pDM_Odm, RegAddr) HAL_READ16(WIFI_REG_BASE, RegAddr) +#define ODM_Read4Byte(pDM_Odm, RegAddr) HAL_READ32(WIFI_REG_BASE, RegAddr) +#define ODM_Write1Byte(pDM_Odm, RegAddr, Data) HAL_WRITE8(WIFI_REG_BASE, RegAddr, Data) +#define ODM_Write2Byte(pDM_Odm, RegAddr, Data) HAL_WRITE16(WIFI_REG_BASE, addr, value) +#define ODM_Write4Byte(pDM_Odm, RegAddr, Data) HAL_WRITE32(WIFI_REG_BASE, addr, value) +#if (RTL8195A_SUPPORT == 1) +#define ODM_GetMACReg(pDM_Odm,RegAddr, BitMask) PHY_QueryBBReg_8195A((pDM_Odm->Adapter), (RegAddr), (BitMask)) +#define ODM_SetMACReg(pDM_Odm, RegAddr, BitMask, Data) PHY_SetBBReg_8195A((pDM_Odm->Adapter), (RegAddr), (BitMask), (Data)) +#define ODM_GetBBReg(pDM_Odm, RegAddr, BitMask) PHY_QueryBBReg_8195A((pDM_Odm->Adapter), (RegAddr), (BitMask)) +#define ODM_SetBBReg(pDM_Odm, RegAddr, BitMask, Data) PHY_SetBBReg_8195A((pDM_Odm->Adapter), (RegAddr), (BitMask), (Data)) +#endif + +#if (RTL8711B_SUPPORT ==1) +#define ODM_GetMACReg(pDM_Odm,RegAddr, BitMask) PHY_QueryBBReg_8711B((pDM_Odm->Adapter), (RegAddr), (BitMask)) +#define ODM_SetMACReg(pDM_Odm, RegAddr, BitMask, Data) PHY_SetBBReg_8711B((pDM_Odm->Adapter), (RegAddr), (BitMask), (Data)) +#define ODM_GetBBReg(pDM_Odm, RegAddr, BitMask) PHY_QueryBBReg_8711B((pDM_Odm->Adapter), (RegAddr), (BitMask)) +#define ODM_SetBBReg(pDM_Odm, RegAddr, BitMask, Data) PHY_SetBBReg_8711B((pDM_Odm->Adapter), (RegAddr), (BitMask), (Data)) +#endif +// +// =========== Extern Variable +// + +// +// =========== EXtern Function Prototype +// + + +#endif // __ROM_ODM_INTERFACE_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/Hal8195ARateAdaptive.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/Hal8195ARateAdaptive.h new file mode 100644 index 0000000..b6d240e --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/Hal8195ARateAdaptive.h @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HALCOM_RATE_ADAPTIVE_RAM_H__ +#define __HALCOM_RATE_ADAPTIVE_RAM_H__ + +#if RATE_ADAPTIVE_SUPPORT + +/*--------------------------Define -------------------------------------------*/ + +#define FIRST_MACID 0 // This is the connection of STA to AP +// Rate index mapping +#define RATE_CCK_1M ODM_RATE1M +#define RATE_CCK_2M ODM_RATE2M +#define RATE_CCK_5M ODM_RATE5_5M +#define RATE_CCK_11M ODM_RATE11M +#define RATE_OFDM_6M ODM_RATE6M +#define RATE_OFDM_9M ODM_RATE9M +#define RATE_OFDM_12M ODM_RATE12M +#define RATE_OFDM_18M ODM_RATE18M +#define RATE_OFDM_24M ODM_RATE24M +#define RATE_OFDM_36M ODM_RATE36M +#define RATE_OFDM_48M ODM_RATE48M +#define RATE_OFDM_54M ODM_RATE54M +#define RATE_HT_MCS0 ODM_RATEMCS0 +#define RATE_HT_MCS1 ODM_RATEMCS1 +#define RATE_HT_MCS2 ODM_RATEMCS2 +#define RATE_HT_MCS3 ODM_RATEMCS3 +#define RATE_HT_MCS4 ODM_RATEMCS4 +#define RATE_HT_MCS5 ODM_RATEMCS5 +#define RATE_HT_MCS6 ODM_RATEMCS6 +#define RATE_HT_MCS7 ODM_RATEMCS7 +#define RATE_HT_MCS8 ODM_RATEMCS8 +#define RATE_HT_MCS9 ODM_RATEMCS9 +#define RATE_HT_MCS10 ODM_RATEMCS10 +#define RATE_HT_MCS11 ODM_RATEMCS11 +#define RATE_HT_MCS12 ODM_RATEMCS12 +#define RATE_HT_MCS13 ODM_RATEMCS13 +#define RATE_HT_MCS14 ODM_RATEMCS14 +#define RATE_HT_MCS15 ODM_RATEMCS15 + +#define MACID_NUM 128 + + + +// TX report format +#define TXRPT_SIZE 16 +//offset 0 +#define TXRPT_DATARATE (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6) +#define TXRPT_SGI BIT7 +//offset 1 +#define TXRPT_PWRSTS (BIT0|BIT1|BIT2) +#define TXRPT_TRYNESSCNT (BIT3|BIT4|BIT5|BIT6) +#define TXRPT_TRYRATE BIT7 +//offset 2 +#define TXRPT_TRYRESULT BIT6 +#define TXRPT_TRYFINISH BIT7 +//offset 3 +#define TXRPT_PAUSERPT BIT6 +#define TXRPT_RESETRPT BIT7 +//offset 4 + +//offset 5 +#define TXRPT_BW (BIT0|BIT1) +#define TXRPT_PKTDROP BIT2 + + + +#define RATE_UP 1 +#define RATE_DOWN 2 + +#define RSSI_TH1 45 +#define RSSI_TH2 25 + +#define PERENTRY 27 +#define RETRYSIZE 5 +#define RATESIZE 20 +#define RAMASK_SIZE 8 + +#define SS_PT_TH_High 66 +#define SS_PT_TH_low 57 +#define SS_PT_off 48 +#define SS_RA_INIT_RATE_RSSI 30 +#define STEP_DROP 1 +#define CONFIG_SGI 0 +#define TRY_WAITING 10 + +// RA mask +#define Mask_length_REG 8 +#define Rate_id_NUM 9 // 6 rate id from reg +#define ARFB_table_NUM 7 + +#define TRY_NESS_CNT_IDX_SIZE 16 + +/*------------------------------Define Enum-----------------------------------*/ +typedef enum _RTL8195_RATEID_IDX_ { + MODE_BGN_40M_2SS = 0, + MODE_BGN_40M_1SS = 1, + MODE_BGN_20M_2SS_BN = 2, + MODE_BGN_20M_1SS_BN = 3, + MODE_GN_N2SS = 4, + MODE_GN_N1SS = 5, + MODE_BG = 6, + MODE_G = 7, + MODE_B = 8 +} RTL8195_RATEID_IDX, *PRTL8195_RATEID_IDX; + +typedef enum _VHT_HT_SWITCH_ { + TYPE_HT = 0, + TYPE_VHT = 1, + TYPE_MIX1 = 2, + TYPE_MIX2 = 3 +} VHT_SEL_SWITCH, *PVHT_SEL_SWITCH; + +/*--------------------------Define MACRO--------------------------------------*/ +#define TRYING_DISABLE 0 +#define TRYING_ENABLE 1 + +//RA MASK: INIT_RATE_MASK + +//if VHT_HT_SWITCH = 1, it means VHT. +//Bit[51:12] : VHT 1SS ~ VHT 4SS +//if VHT_HT_SWITCH = 0, it means HT. +//Bit[43:12] : HT 1SS ~ HT4SS + +//offset6 +//#define VHT_HT_SWITCH BIT4 + + +// H2C CMD +//offset0 +#define H2CID13_MACID 0x7F +//offset1 +#define H2CID13_RATEID 0x1F +#define H2CID13_SGI BIT7 + + + +//offset2 +#define H2CID13_BW (BIT0|BIT1) +#define H2CID13_enldpc BIT2 +#define H2CID13_NOUPDATE BIT3 +#define H2CID13_VHT_EN (BIT5|BIT4) +#define H2CID13_DISPT BIT6 +#define H2CID13_DISRA BIT7 + +//H2C AP_Req_Tx_Rpt +#define H2CID43_RTY_OK_TOTAL BIT0 +#define H2CID43_RTY_CNT_MACID BIT1 + + +//RAInfo +#define MASK_RA_ULDL_STATE BIT0 +#define MASK_RA_STBC_STATE BIT1 +#define MASK_RA_LDPC_CAP_STATE BIT2 +#define MASK_RA_SHORTCUT_STATE BIT3 +#define MASK_RA_SHORTCUT_FLAG BIT4 +#define MASK_RA_INIT_RATE_RSSI_STATE BIT5 +#define MASK_RA_BF_STATE BIT6 +#define MASK_RA_DELAY_RATE BIT7 + + + +#define RA_ULDL_STATE_SHT 0 +#define RA_STBC_STATE_SHT 1 +#define RA_LDPC_CAP_STATE_SHT 2 +#define RA_SHORTCUT_STATE_SHT 3 +#define RA_SHORTCUT_FLAG_SHT 4 +#define RA_INIT_RATE_RSSI_SHT 5 +#define RA_BF_STATE_SHT 6 +#define RA_DELAY_RATE_SHT 7 + +/*------------------------Export global variable------------------------------*/ +//2 Rate Adaptive +//HW Statistic +//extern MEMTYPE_XDATA u16 TOTAL[MACID_NUM]; +//extern MEMTYPE_XDATA u1Byte DROP[MACID_NUM]; +//extern MEMTYPE_XDATA u16 RTY[MACID_NUM][5]; + +//extern MEMTYPE_XDATA STAINFO_RA stainfo_ra[MACID_NUM]; +//extern MEMTYPE_XDATA u16 Nsc[MACID_NUM]; +//extern MEMTYPE_XDATA u1Byte RSSI[MACID_NUM]; // add by Gary +//extern MEMTYPE_XDATA u1Byte BUPDATE[MACID_NUM]; + +/*------------------------------Function declaration--------------------------*/ +VOID +InitBBNHM( + void +); + +VOID +BBNHM( + void +); + +VOID +ODM_InitRAInfo( + IN PDM_ODM_T pDM_Odm +); + +VOID +H2CHDL_Set_MACID_Config( + IN PDM_ODM_T pDM_Odm, + IN u1Byte *pbuf +); + +VOID +H2CHDL_SetRssiSingle( + u1Byte *pbuf +); + + +VOID +H2CHDL_APReqTxrpt( + u1Byte *pbuf +); + +VOID +H2CHDL_InitRateCollect( + u1Byte *pbuf +); + + +VOID +TryDone( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo +); + +VOID +RateDownTrying( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo +); + +VOID +RateDecisionRAM8195A( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo +); + +VOID +GetRATRfromREG( + IN u16 reg_addr, + IN u1Byte macid +); + +VOID +PHY_DM_RA_SetRSSI_8195A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte Rssi + ); + +#if 0 +extern void +Rate_trying_decision( + IN u1Byte macid, + IN u1Byte rate, + IN u1Byte datarc, + IN u1Byte aggnum +); +#endif + + +//debug +VOID +ArfrRefresh( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo +); + +#endif //#if CONFIG_RATE_ADAPTIVE + +#endif //#ifndef __HALCOM_RATE_ADAPTIVE_RAM_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/Hal8195AReg.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/Hal8195AReg.h new file mode 100644 index 0000000..0ee85a6 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/Hal8195AReg.h @@ -0,0 +1,1371 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ****************************************************************************** + * + * Module: __INC_HAL8723BREG_H + * + * + * Note: 1. Define Mac register address and corresponding bit mask map + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * + *****************************************************************************/ +#ifndef __INC_HAL8195AREG_H +#define __INC_HAL8195AREG_H + + + +//============================================================ +// +//============================================================ + +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +#define REG_SYS_ISO_CTRL_8723B 0x0000 // 2 Byte +#define REG_SYS_FUNC_EN_8723B 0x0002 // 2 Byte +#define REG_APS_FSMCO_8723B 0x0004 // 4 Byte +#define REG_SYS_CLKR_8723B 0x0008 // 2 Byte +#define REG_9346CR_8723B 0x000A // 2 Byte +#define REG_EE_VPD_8723B 0x000C // 2 Byte +#define REG_AFE_MISC_8723B 0x0010 // 1 Byte +#define REG_SPS0_CTRL_8723B 0x0011 // 7 Byte +#define REG_SPS_OCP_CFG_8723B 0x0018 // 4 Byte +#define REG_RSV_CTRL_8723B 0x001C // 3 Byte +#define REG_RF_CTRL_8723B 0x001F // 1 Byte +#define REG_LPLDO_CTRL_8723B 0x0023 // 1 Byte +#define REG_AFE_XTAL_CTRL_8723B 0x0024 // 4 Byte +#define REG_AFE_PLL_CTRL_8723B 0x0028 // 4 Byte +#define REG_MAC_PLL_CTRL_EXT_8723B 0x002c // 4 Byte +#define REG_EFUSE_CTRL_8723B 0x0030 +#define REG_EFUSE_TEST_8723B 0x0034 +#define REG_PWR_DATA_8723B 0x0038 +#define REG_CAL_TIMER_8723B 0x003C +#define REG_ACLK_MON_8723B 0x003E +#define REG_GPIO_MUXCFG_8723B 0x0040 +#define REG_GPIO_IO_SEL_8723B 0x0042 +#define REG_MAC_PINMUX_CFG_8723B 0x0043 +#define REG_GPIO_PIN_CTRL_8723B 0x0044 +#define REG_GPIO_INTM_8723B 0x0048 +#define REG_LEDCFG0_8723B 0x004C +#define REG_LEDCFG1_8723B 0x004D +#define REG_LEDCFG2_8723B 0x004E +#define REG_LEDCFG3_8723B 0x004F +#define REG_FSIMR_8723B 0x0050 +#define REG_FSISR_8723B 0x0054 +#define REG_HSIMR_8723B 0x0058 +#define REG_HSISR_8723B 0x005c +#define REG_GPIO_EXT_CTRL 0x0060 +#define REG_MULTI_FUNC_CTRL_8723B 0x0068 +#define REG_GPIO_STATUS_8723B 0x006C +#define REG_SDIO_CTRL_8723B 0x0070 +#define REG_OPT_CTRL_8723B 0x0074 +#define REG_AFE_XTAL_CTRL_EXT_8723B 0x0078 +#define REG_MCUFWDL_8723B 0x0080 +#define REG_BT_PATCH_STATUS_8723B 0x0088 +#define REG_HIMR0_8723B 0x00B0 +#define REG_HISR0_8723B 0x00B4 +#define REG_HIMR1_8723B 0x00B8 +#define REG_HISR1_8723B 0x00BC +#define REG_PMC_DBG_CTRL2_8723B 0x00CC +#define REG_EFUSE_BURN_GNT_8723B 0x00CF +#define REG_HPON_FSM_8723B 0x00EC +#define REG_SYS_CFG_8723B 0x00F0 +#define REG_SYS_CFG1_8723B 0x00FC +#define REG_ROM_VERSION 0x00FD + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +#define REG_CR_8723B 0x0100 +#define REG_PBP_8723B 0x0104 +#define REG_PKT_BUFF_ACCESS_CTRL_8723B 0x0106 +#define REG_TRXDMA_CTRL_8723B 0x010C +#define REG_TRXFF_BNDY_8723B 0x0114 +#define REG_TRXFF_STATUS_8723B 0x0118 +#define REG_RXFF_PTR_8723B 0x011C +#define REG_CPWM_8723B 0x012F +#define REG_FWIMR_8723B 0x0130 +#define REG_FWISR_8723B 0x0134 +#define REG_FTIMR_8723B 0x0138 +#define REG_PKTBUF_DBG_CTRL_8723B 0x0140 +#define REG_RXPKTBUF_CTRL_8723B 0x0142 +#define REG_PKTBUF_DBG_DATA_L_8723B 0x0144 +#define REG_PKTBUF_DBG_DATA_H_8723B 0x0148 + +#define REG_TC0_CTRL_8723B 0x0150 +#define REG_TC1_CTRL_8723B 0x0154 +#define REG_TC2_CTRL_8723B 0x0158 +#define REG_TC3_CTRL_8723B 0x015C +#define REG_TC4_CTRL_8723B 0x0160 +#define REG_TCUNIT_BASE_8723B 0x0164 +#define REG_RSVD3_8723B 0x0168 +#define REG_C2HEVT_MSG_NORMAL_8723B 0x01A0 +#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 +#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 +#define REG_C2HEVT_CMD_LEN_88XX 0x01AE +#define REG_C2HEVT_CLEAR_8723B 0x01AF +#define REG_MCUTST_1_8723B 0x01C0 +#define REG_MCUTST_WOWLAN_8723B 0x01C7 +#define REG_FMETHR_8723B 0x01C8 +#define REG_HMETFR_8723B 0x01CC +#define REG_HMEBOX_0_8723B 0x01D0 +#define REG_HMEBOX_1_8723B 0x01D4 +#define REG_HMEBOX_2_8723B 0x01D8 +#define REG_HMEBOX_3_8723B 0x01DC +#define REG_LLT_INIT_8723B 0x01E0 +#define REG_HMEBOX_EXT0_8723B 0x01F0 +#define REG_HMEBOX_EXT1_8723B 0x01F4 +#define REG_HMEBOX_EXT2_8723B 0x01F8 +#define REG_HMEBOX_EXT3_8723B 0x01FC + +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +#define REG_RQPN_8723B 0x0200 +#define REG_FIFOPAGE_8723B 0x0204 +#define REG_TDECTRL_8723B 0x0208 +#define REG_TXDMA_OFFSET_CHK_8723B 0x020C +#define REG_TXDMA_STATUS_8723B 0x0210 +#define REG_RQPN_NPQ_8723B 0x0214 +#define REG_TDECTRL1_8195A 0x0228 + + +//----------------------------------------------------- +// +// 0x0280h ~ 0x02FFh RXDMA Configuration +// +//----------------------------------------------------- +#define REG_RXDMA_AGG_PG_TH_8723B 0x0280 +#define REG_FW_UPD_RDPTR_8723B 0x0284 // FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 +#define REG_RXDMA_CONTROL_8723B 0x0286 // Control the RX DMA. +#define REG_RXPKT_NUM_8723B 0x0287 // The number of packets in RXPKTBUF. +#define REG_RXDMA_STATUS_8723B 0x0288 +#define REG_RXDMA_PRO_8723B 0x0290 +#define REG_EARLY_MODE_CONTROL_8723B 0x02BC +#define REG_RSVD5_8723B 0x02F0 +#define REG_RSVD6_8723B 0x02F4 + + +//----------------------------------------------------- +// +// 0x0300h ~ 0x03FFh PCIe +// +//----------------------------------------------------- +#define REG_PCIE_CTRL_REG_8723B 0x0300 +#define REG_INT_MIG_8723B 0x0304 // Interrupt Migration +#define REG_BCNQ_DESA_8723B 0x0308 // TX Beacon Descriptor Address +#define REG_HQ_DESA_8723B 0x0310 // TX High Queue Descriptor Address +#define REG_MGQ_DESA_8723B 0x0318 // TX Manage Queue Descriptor Address +#define REG_VOQ_DESA_8723B 0x0320 // TX VO Queue Descriptor Address +#define REG_VIQ_DESA_8723B 0x0328 // TX VI Queue Descriptor Address +#define REG_BEQ_DESA_8723B 0x0330 // TX BE Queue Descriptor Address +#define REG_BKQ_DESA_8723B 0x0338 // TX BK Queue Descriptor Address +#define REG_RX_DESA_8723B 0x0340 // RX Queue Descriptor Address +#define REG_DBI_WDATA_8723B 0x0348 // DBI Write Data +#define REG_DBI_RDATA_8723B 0x034C // DBI Read Data +#define REG_DBI_ADDR_8723B 0x0350 // DBI Address +#define REG_DBI_FLAG_8723B 0x0352 // DBI Read/Write Flag +#define REG_MDIO_WDATA_8723B 0x0354 // MDIO for Write PCIE PHY +#define REG_MDIO_RDATA_8723B 0x0356 // MDIO for Reads PCIE PHY +#define REG_MDIO_CTL_8723B 0x0358 // MDIO for Control +#define REG_DBG_SEL_8723B 0x0360 // Debug Selection Register +#define REG_PCIE_HRPWM_8723B 0x0361 //PCIe RPWM +#define REG_PCIE_HCPWM_8723B 0x0363 //PCIe CPWM +#define REG_PCIE_MULTIFET_CTRL_8723B 0x036A //PCIE Multi-Fethc Control + + +// spec version 11 +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +#define REG_VOQ_INFORMATION_8723B 0x0400 +#define REG_VIQ_INFORMATION_8723B 0x0404 +#define REG_BEQ_INFORMATION_8723B 0x0408 +#define REG_BKQ_INFORMATION_8723B 0x040C +#define REG_MGQ_INFORMATION_8723B 0x0410 +#define REG_HGQ_INFORMATION_8723B 0x0414 +#define REG_BCNQ_INFORMATION_8723B 0x0418 +#define REG_TXPKT_EMPTY_8723B 0x041A + +#define REG_FWHW_TXQ_CTRL_8723B 0x0420 +#define REG_HWSEQ_CTRL_8723B 0x0423 +#define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 +#define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 +#define REG_LIFECTRL_CTRL_8723B 0x0426 +#define REG_MULTI_BCNQ_OFFSET_8723B 0x0427 +#define REG_SPEC_SIFS_8723B 0x0428 +#define REG_RL_8723B 0x042A +#define REG_TXBF_CTRL_8723B 0x042C +#define REG_DARFRC_8723B 0x0430 +#define REG_RARFRC_8723B 0x0438 +#define REG_RRSR_8723B 0x0440 +#define REG_ARFR0_8723B 0x0444 +#define REG_ARFR1_8723B 0x044C +#define REG_CCK_CHECK_8723B 0x0454 +#define REG_AMPDU_MAX_TIME_8723B 0x0456 +#define REG_TXPKTBUF_BCNQ_BDNY1_8723B 0x0457 + +#define REG_AMPDU_MAX_LENGTH_8195A 0x0458 +#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D +#define REG_NDPA_OPT_CTRL_8723B 0x045F +#define REG_FAST_EDCA_CTRL_8723B 0x0460 +#define REG_RD_RESP_PKT_TH_8723B 0x0463 +#define REG_SPC_W_PTR 0x47E +#define REG_SPC_R_PTR 0x47F +#define REG_DATA_SC_8723B 0x0483 +#define REG_TXRPT_START_OFFSET 0x04AC +#define REG_POWER_STAGE1_8723B 0x04B4 +#define REG_POWER_STAGE2_8723B 0x04B8 +#define REG_AMPDU_BURST_MODE_8723B 0x04BC +#define REG_PKT_VO_VI_LIFE_TIME_8723B 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME_8723B 0x04C2 +#define REG_STBC_SETTING_8723B 0x04C4 +#define REG_HT_SINGLE_AMPDU_8723B 0x04C7 +#define REG_PROT_MODE_CTRL_8723B 0x04C8 +#define REG_MAX_AGGR_NUM_8723B 0x04CA +#define REG_RTS_MAX_AGGR_NUM_8723B 0x04CB +#define REG_BAR_MODE_CTRL_8723B 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT_8723B 0x04CF +#define REG_MACID_PKT_DROP0_8723B 0x04D0 + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +#define REG_EDCA_VO_PARAM_8723B 0x0500 +#define REG_EDCA_VI_PARAM_8723B 0x0504 +#define REG_EDCA_BE_PARAM_8723B 0x0508 +#define REG_EDCA_BK_PARAM_8723B 0x050C +#define REG_BCNTCFG_8723B 0x0510 +#define REG_PIFS_8723B 0x0512 +#define REG_RDG_PIFS_8723B 0x0513 +#define REG_SIFS_CTX_8723B 0x0514 +#define REG_SIFS_TRX_8723B 0x0516 +#define REG_AGGR_BREAK_TIME_8723B 0x051A +#define REG_SLOT_8723B 0x051B +#define REG_TX_PTCL_CTRL_8723B 0x0520 +#define REG_TXPAUSE_8723B 0x0522 +#define REG_DIS_TXREQ_CLR_8723B 0x0523 +#define REG_RD_CTRL_8723B 0x0524 +// +// Format for offset 540h-542h: +// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. +// [7:4]: Reserved. +// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. +// [23:20]: Reserved +// Description: +// | +// |<--Setup--|--Hold------------>| +// --------------|---------------------- +// | +// TBTT +// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. +// Described by Designer Tim and Bruce, 2011-01-14. +// +#define REG_TBTT_PROHIBIT_8723B 0x0540 +#define REG_RD_NAV_NXT_8723B 0x0544 +#define REG_NAV_PROT_LEN_8723B 0x0546 +#define REG_BCN_CTRL_8723B 0x0550 +#define REG_BCN_CTRL_1_8723B 0x0551 +#define REG_MBID_NUM_8723B 0x0552 +#define REG_DUAL_TSF_RST_8723B 0x0553 +#define REG_BCN_INTERVAL_8723B 0x0554 +#define REG_DRVERLYINT_8723B 0x0558 +#define REG_BCNDMATIM_8723B 0x0559 +#define REG_ATIMWND_8723B 0x055A +#define REG_USTIME_TSF_8723B 0x055C +#define REG_BCN_MAX_ERR_8723B 0x055D +#define REG_RXTSF_OFFSET_CCK_8723B 0x055E +#define REG_RXTSF_OFFSET_OFDM_8723B 0x055F +#define REG_TSFTR_8723B 0x0560 +#define REG_CTWND_8723B 0x0572 +#define REG_BCNIVLCUNT_8723B 0x0573 +#define REG_SECONDARY_CCA_CTRL_8723B 0x0577 +#define REG_PSTIMER_8723B 0x0580 +#define REG_TIMER0_8723B 0x0584 +#define REG_TIMER1_8723B 0x0588 +#define REG_ACMHWCTRL_8723B 0x05C0 +#define REG_SCH_TXCMD_8723B 0x05F8 + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +#define REG_MAC_CR_8723B 0x0600 +#define REG_TCR_8723B 0x0604 +#define REG_RCR_8723B 0x0608 +#define REG_RX_PKT_LIMIT_8723B 0x060C +#define REG_RX_DLK_TIME_8723B 0x060D +#define REG_RX_DRVINFO_SZ_8723B 0x060F + +#define REG_MACID_8723B 0x0610 +#define REG_BSSID_8723B 0x0618 +#define REG_MAR_8723B 0x0620 +#define REG_MBIDCAMCFG_8723B 0x0628 + +#define REG_USTIME_EDCA_8723B 0x0638 +#define REG_MAC_SPEC_SIFS_8723B 0x063A +#define REG_RESP_SIFP_CCK_8723B 0x063C +#define REG_RESP_SIFS_OFDM_8723B 0x063E +#define REG_ACKTO_8723B 0x0640 +#define REG_CTS2TO_8723B 0x0641 +#define REG_EIFS_8723B 0x0642 + +#define REG_NAV_UPPER_8723B 0x0652 // unit of 128 +#define REG_RTR_8723B 0x0662 +#define REG_TRXPTCL_CTL_8723B 0x0668 + +// Security +#define REG_CAMCMD_8723B 0x0670 +#define REG_CAMWRITE_8723B 0x0674 +#define REG_CAMREAD_8723B 0x0678 +#define REG_CAMDBG_8723B 0x067C +#define REG_SECCFG_8723B 0x0680 + +// Power +#define REG_WOW_CTRL_8723B 0x0690 +#define REG_PS_RX_INFO_8723B 0x0692 +#define REG_UAPSD_TID_8723B 0x0693 +#define REG_WKFMCAM_CMD_8723B 0x0698 +#define REG_WKFMCAM_NUM_8723B 0x0698 +#define REG_WKFMCAM_RWD_8723B 0x069C +#define REG_RXFLTMAP0_8723B 0x06A0 +#define REG_RXFLTMAP1_8723B 0x06A2 +#define REG_RXFLTMAP2_8723B 0x06A4 +#define REG_BCN_PSR_RPT_8723B 0x06A8 +#define REG_BT_COEX_TABLE_8723B 0x06C0 +#define REG_BFMER0_INFO_8723B 0x06E4 +#define REG_BFMER1_INFO_8723B 0x06EC +#define REG_CSI_RPT_PARAM_BW20_8723B 0x06F4 +#define REG_CSI_RPT_PARAM_BW40_8723B 0x06F8 +#define REG_CSI_RPT_PARAM_BW80_8723B 0x06FC + +// Hardware Port 2 +#define REG_MACID1_8723B 0x0700 +#define REG_BSSID1_8723B 0x0708 +#define REG_BFMEE_SEL_8723B 0x0714 +#define REG_SND_PTCL_CTRL_8723B 0x0718 + + +//----------------------------------------------------- +// +// 0xFE00h ~ 0xFE55h USB Configuration +// +//----------------------------------------------------- +/* +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + + +// For normal chip +#define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61 +#define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63 +#define REG_NORMAL_SIE_OPTIONAL 0xFE64 +#define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67 +#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B +#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C +#define REG_NORMAL_SIE_GPS_EP 0xFE6D // 0xFE6D, for RTL8723 only. +#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 +#define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF +*/ + +//----------------------------------------------------- +// +// Redifine 8192C register definition for compatibility +// +//----------------------------------------------------- + +// TODO: use these definition when using REG_xxx naming rule. +// NOTE: DO NOT Remove these definition. Use later. +#define EFUSE_CTRL_8723B REG_EFUSE_CTRL_8723B // E-Fuse Control. +#define EFUSE_TEST_8723B REG_EFUSE_TEST_8723B // E-Fuse Test. +#define MSR_8723B (REG_CR_8723B + 2) // Media Status register +#define ISR_8723B REG_HISR0_8723B +#define TSFR_8723B REG_TSFTR_8723B // Timing Sync Function Timer Register. + +#define PBP_8723B REG_PBP_8723B + +// Redifine MACID register, to compatible prior ICs. +#define IDR0_8723B REG_MACID_8723B // MAC ID Register, Offset 0x0050-0x0053 +#define IDR4_8723B (REG_MACID_8723B + 4) // MAC ID Register, Offset 0x0054-0x0055 + + +// +// 9. Security Control Registers (Offset: ) +// +#define RWCAM_8723B REG_CAMCMD_8723B //IN 8190 Data Sheet is called CAMcmd +#define WCAMI_8723B REG_CAMWRITE_8723B // Software write CAM input content +#define RCAMO_8723B REG_CAMREAD_8723B // Software read/write CAM config +#define CAMDBG_8723B REG_CAMDBG_8723B +#define SECR_8723B REG_SECCFG_8723B //Security Configuration Register + +/* + +// Unused register +#define UnusedRegister 0x1BF +#define DCAM UnusedRegister +#define PSR UnusedRegister +#define BBAddr UnusedRegister +#define PhyDataR UnusedRegister + + + +//---------------------------------------------------------------------------- +// 8192C Cmd9346CR bits (Offset 0xA, 16bit) +//---------------------------------------------------------------------------- +#define CmdEEPROM_En BIT5 // EEPROM enable when set 1 +#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 +#define Cmd9346CR_9356SEL BIT4 + +//---------------------------------------------------------------------------- +// 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) +//---------------------------------------------------------------------------- +#define GPIOSEL_GPIO BIT0 +#define GPIOSEL_ENBT BIT5 + +//---------------------------------------------------------------------------- +// 8192C GPIO PIN Control Register (offset 0x44, 4 byte) +//---------------------------------------------------------------------------- +#define GPIO_IN REG_GPIO_PIN_CTRL_8195 // GPIO pins input value +#define GPIO_OUT (REG_GPIO_PIN_CTRL_8195+1) // GPIO pins output value +#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL_8195+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. +#define GPIO_MOD (REG_GPIO_PIN_CTRL_8195+3) +#define HAL_8192C_HW_GPIO_WPS_BIT BIT2 + +//---------------------------------------------------------------------------- +// 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) +//---------------------------------------------------------------------------- +#define HSIMR_GPIO12_0_INT_EN BIT0 +#define HSIMR_SPS_OCP_INT_EN BIT5 +#define HSIMR_RON_INT_EN BIT6 +#define HSIMR_PDN_INT_EN BIT7 +#define HSIMR_GPIO9_INT_EN BIT25 + + +//---------------------------------------------------------------------------- +// 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) +//---------------------------------------------------------------------------- +#define HSISR_GPIO12_0_INT BIT0 +#define HSISR_SPS_OCP_INT BIT5 +#define HSISR_RON_INT_EN BIT6 +#define HSISR_PDNINT BIT7 +#define HSISR_GPIO9_INT BIT25 + +//---------------------------------------------------------------------------- +// 8195 (MSR) Media Status Register (Offset 0x4C, 8 bits) +//---------------------------------------------------------------------------- +#define MSR_NOLINK 0x00 +#define MSR_ADHOC 0x01 +#define MSR_INFRA 0x02 +#define MSR_AP 0x03 + +//---------------------------------------------------------------------------- +// 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) +//---------------------------------------------------------------------------- +#define USB_INTR_CONTENT_HISR_OFFSET 48 +#define USB_INTR_CONTENT_HISRE_OFFSET 52 + + +// +// 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) +// +//---------------------------------------------------------------------------- +// 8192C Response Rate Set Register (offset 0x181, 24bits) +//---------------------------------------------------------------------------- +#define RRSR_1M BIT0 +#define RRSR_2M BIT1 +#define RRSR_5_5M BIT2 +#define RRSR_11M BIT3 +#define RRSR_6M BIT4 +#define RRSR_9M BIT5 +#define RRSR_12M BIT6 +#define RRSR_18M BIT7 +#define RRSR_24M BIT8 +#define RRSR_36M BIT9 +#define RRSR_48M BIT10 +#define RRSR_54M BIT11 +#define RRSR_MCS0 BIT12 +#define RRSR_MCS1 BIT13 +#define RRSR_MCS2 BIT14 +#define RRSR_MCS3 BIT15 +#define RRSR_MCS4 BIT16 +#define RRSR_MCS5 BIT17 +#define RRSR_MCS6 BIT18 +#define RRSR_MCS7 BIT19 + + +//---------------------------------------------------------------------------- +// 8192C Response Rate Set Register (offset 0x1BF, 8bits) +//---------------------------------------------------------------------------- +// WOL bit information +#define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 +#define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 + + +//---------------------------------------------------------------------------- +// 8192C Rate Definition +//---------------------------------------------------------------------------- +//CCK +#define RATR_1M 0x00000001 +#define RATR_2M 0x00000002 +#define RATR_55M 0x00000004 +#define RATR_11M 0x00000008 +//OFDM +#define RATR_6M 0x00000010 +#define RATR_9M 0x00000020 +#define RATR_12M 0x00000040 +#define RATR_18M 0x00000080 +#define RATR_24M 0x00000100 +#define RATR_36M 0x00000200 +#define RATR_48M 0x00000400 +#define RATR_54M 0x00000800 +//MCS 1 Spatial Stream +#define RATR_MCS0 0x00001000 +#define RATR_MCS1 0x00002000 +#define RATR_MCS2 0x00004000 +#define RATR_MCS3 0x00008000 +#define RATR_MCS4 0x00010000 +#define RATR_MCS5 0x00020000 +#define RATR_MCS6 0x00040000 +#define RATR_MCS7 0x00080000 +//MCS 2 Spatial Stream +#define RATR_MCS8 0x00100000 +#define RATR_MCS9 0x00200000 +#define RATR_MCS10 0x00400000 +#define RATR_MCS11 0x00800000 +#define RATR_MCS12 0x01000000 +#define RATR_MCS13 0x02000000 +#define RATR_MCS14 0x04000000 +#define RATR_MCS15 0x08000000 + + +// NOTE: For 92CU - Ziv +//CCK +#define RATE_1M BIT(0) +#define RATE_2M BIT(1) +#define RATE_5_5M BIT(2) +#define RATE_11M BIT(3) +//OFDM +#define RATE_6M BIT(4) +#define RATE_9M BIT(5) +#define RATE_12M BIT(6) +#define RATE_18M BIT(7) +#define RATE_24M BIT(8) +#define RATE_36M BIT(9) +#define RATE_48M BIT(10) +#define RATE_54M BIT(11) +//MCS 1 Spatial Stream +#define RATE_MCS0 BIT(12) +#define RATE_MCS1 BIT(13) +#define RATE_MCS2 BIT(14) +#define RATE_MCS3 BIT(15) +#define RATE_MCS4 BIT(16) +#define RATE_MCS5 BIT(17) +#define RATE_MCS6 BIT(18) +#define RATE_MCS7 BIT(19) +//MCS 2 Spatial Stream +#define RATE_MCS8 BIT(20) +#define RATE_MCS9 BIT(21) +#define RATE_MCS10 BIT(22) +#define RATE_MCS11 BIT(23) +#define RATE_MCS12 BIT(24) +#define RATE_MCS13 BIT(25) +#define RATE_MCS14 BIT(26) +#define RATE_MCS15 BIT(27) + + + + +// ALL CCK Rate +#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M +#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\ + RATR_36M|RATR_48M|RATR_54M +#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\ + RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 +#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\ + RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 + +#define RATE_BITMAP_ALL 0xFFFFF + +// Only use CCK 1M rate for ACK +#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 +//---------------------------------------------------------------------------- +// 8192C BW_OPMODE bits (Offset 0x203, 8bit) +//---------------------------------------------------------------------------- +#define BW_OPMODE_20MHZ BIT2 +#define BW_OPMODE_5G BIT1 + +// +// 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) +// +#define WOW_PMEN BIT0 // Power management Enable. +#define WOW_WOMEN BIT1 // WoW function on or off. +#define WOW_MAGIC BIT2 // Magic packet +#define WOW_UWF BIT3 // Unicast Wakeup frame. + +*/ + +//---------------------------------------------------------------------------- +// 8195 IMR/ISR bits (offset 0x80, 8bits) +//---------------------------------------------------------------------------- +#define IMR_WL_FTINT_MSK_8195A BIT31 //The interrupt mask from WL page 1 interrupt source +#define IMR_TSF_BIT32_TOGGLE_MSK_V1_8195A BIT10 //Enable TSF_BIT32_TOGGLE interrupt source +#define IMR_P2P_RFOFF_INT_MSK_8195A BIT9 //P2P NoA RF off time indication interrupt mask +#define IMR_P2P_RFON_INT_MSK_8195A BIT8 //P2P NoA RF on time indication interrupt mask +#define IMR_PSTIMER_MSK_8195A BIT6 //Enable PSTimer interrupt source +#define IMR_TIMEOUT1_MSK_8195A BIT5 //Enable Timer1 interrupt source +#define IMR_TIMEOUT0_MSK_8195A BIT4 //Enable Timer0 interrupt source +#define IMR_MTI_BCNIVLEAR_INT_MSK_8195A BIT1 //Enable MTI_BCNIVLEAR _INT +#define IMR_BCNERLY_MSK_8195A BIT0 //This interrupt is issued at the time set by DRVERLYINT register before TBTT time. + + +//---------------------------------------------------------------------------- +// 8195 IMR/ISR bits (offset 0x134, 8bits) +//---------------------------------------------------------------------------- +#define IMR_SOUND_DONE_MSK_8195A BIT30 //Be a beamformer, this interrupt is issued at the time after sounding finish +#define IMR_TRY_DONE_MSK_8195A BIT29 //When TRY_FINISH is deasserted, this interrupt is issued to inform MCU +#define IMR_TXRPT_CNT_FULL_MSK_8195A BIT28 +#define IMR_WLACTOFF_INT_EN_8195A BIT27 +#define IMR_WLACTON_INT_EN_8195A BIT26 +#define IMR_TXPKTIN_INT_EN_8195A BIT25 +#define IMR_TXBCN0OK_8195A BIT24 // Transmit Beacon0 OK +#define IMR_TXBCN0ERR_8195A BIT23 // Transmit Beacon0 Error +#define IMR_RX_UMD0_EN_8195A BIT22 +#define IMR_RX_UMD1_EN_8195A BIT21 +#define IMR_RX_BMD0_EN_8195A BIT20 +#define IMR_RX_BMD1_EN_8195A BIT19 +#define IMR_BCN_RX_INT_EN_8195A BIT18 +#define IMR_TBTTINT_MSK_8195A BIT17 + +#define IMR_BCNDMA7_MSK_8195A BIT15 //When BCNDMA interval arrives before TBTT7, + //this interrupt informs MCU to prepare related beacon tasks. +#define IMR_BCNDMA6_MSK_8195A BIT14 //When BCNDMA interval arrives before TBTT6, + //this interrupt informs MCU to prepare related beacon tasks. +#define IMR_BCNDMA5_MSK_8195A BIT13 //When BCNDMA interval arrives before TBTT5, + //this interrupt informs MCU to prepare related beacon tasks. +#define IMR_BCNDMA4_MSK_8195A BIT12 //When BCNDMA interval arrives before TBTT4, + //this interrupt informs MCU to prepare related beacon tasks. +#define IMR_BCNDMA3_MSK_8195A BIT11 //When BCNDMA interval arrives before TBTT3, + //this interrupt informs MCU to prepare related beacon tasks. +#define IMR_BCNDMA2_MSK_8195A BIT10 //When BCNDMA interval arrives before TBTT2, + //this interrupt informs MCU to prepare related beacon tasks. +#define IMR_BCNDMA1_MSK_8195A BIT9 //When BCNDMA interval arrives before TBTT1, + //this interrupt informs MCU to prepare related beacon tasks. +#define IMR_BCNDMA0_MSK_8195A BIT8 //When BCNDMA interval arrives before TBTT0, + //this interrupt informs MCU to prepare related beacon tasks. +#define IMR_STBY_MSK_8195A BIT7 //Lower Power Standby Interrupt mask +#define IMR_CTWEndINT_MSK_8195A BIT6 //This bit masks the CTWindow End interrupt. +#define IMR_TXFOVW_MSK_8195A BIT5 //"Transmit packet buffer Overflow.This bit is set to 1 when one or more of the hardware transmit queues is full" +#define IMR_FOVW_MSK_8195A BIT4 //"Rx packet buffer OverflowSet this bit to one when Rx packet buffer write pointer hits read pointer. " +#define IMR_RXDONE_MSK_8195A BIT3 //Rx Packet done for 8051 +#define IMR_ERRORHDL_MSK_8195A BIT2 //FWHW/ TXDMA/ RXDMA/ WMAC error status interrupt +#define IMR_TXCCX_MSK_FW_8195A BIT1 //CCX PKT TX Report Interrupt +#define IMR_TXCLOSE_MSK_8195A BIT0 //TX Finish (Ack/BA process Finish) Interrupt. + + +//---------------------------------------------------------------------------- +// 8195 IMR/ISR bits (offset 0x3EC, 8bits) +//---------------------------------------------------------------------------- +#define IMR_BCNDERR7_8195A BIT31 // Beacon Queue DMA Error +#define IMR_BCNDERR6_8195A BIT30 // Beacon Queue DMA Error +#define IMR_BCNDERR5_8195A BIT29 // Beacon Queue DMA Error +#define IMR_BCNDERR4_8195A BIT28 // Beacon Queue DMA Error +#define IMR_BCNDERR3_8195A BIT27 // Beacon Queue DMA Error +#define IMR_BCNDERR2_8195A BIT26 // Beacon Queue DMA Error +#define IMR_BCNDERR1_8195A BIT25 // Beacon Queue DMA Error +#define IMR_BCNDERR0_8195A BIT24 // Beacon Queue DMA Error +#define IMR_BCNDMAOK7_8195A BIT23 // Beacon DMA OK Interrupt 7 +#define IMR_BCNDMAOK6_8195A BIT22 // Beacon DMA OK Interrupt 6 +#define IMR_BCNDMAOK5_8195A BIT21 // Beacon DMA OK Interrupt 5 +#define IMR_BCNDMAOK4_8195A BIT20 // Beacon DMA OK Interrupt 4 +#define IMR_BCNDMAOK3_8195A BIT19 // Beacon DMA OK Interrupt 3 +#define IMR_BCNDMAOK2_8195A BIT18 // Beacon DMA OK Interrupt 2 +#define IMR_BCNDMAOK1_8195A BIT17 // Beacon DMA OK Interrupt 1 +#define IMR_BCNDMAOK0_8195A BIT16 // Beacon DMA OK Interrupt 0 +#define IMR_H7DOK_8195A BIT15 // High Queue DMA OK Interrup 7 +#define IMR_H6DOK_8195A BIT14 // High Queue DMA OK Interrup 6 +#define IMR_H5DOK_8195A BIT13 // High Queue DMA OK Interrup 5 +#define IMR_H4DOK_8195A BIT12 // High Queue DMA OK Interrup 4 +#define IMR_H3DOK_8195A BIT11 // High Queue DMA OK Interrup 3 +#define IMR_H2DOK_8195A BIT10 // High Queue DMA OK Interrup 2 +#define IMR_H1DOK_8195A BIT9 // High Queue DMA OK Interrup 1 +#define IMR_H0DOK_8195A BIT8 // High Queue DMA OK Interrup 1 +#define IMR_MGNTDOK_8195A BIT6 // Management Queue DMA OK +#define IMR_BKDOK_8195A BIT5 // AC_BK DMA OK +#define IMR_BEDOK_8195A BIT4 // AC_BE DMA OK +#define IMR_VIDOK_8195A BIT3 // AC_VI DMA OK +#define IMR_VODOK_8195A BIT2 // AC_VO DMA OK +#define IMR_RDU_8195A BIT1 // Rx Descriptor Unavailable +#define IMR_ROK_8195A BIT0 // Receive DMA OK + + + + + + + +/*=================================================================== +===================================================================== +Here the register defines are for 92C. When the define is as same with 92C, +we will use the 92C's define for the consistency +So the following defines for 92C is not entire!!!!!! +===================================================================== +=====================================================================*/ +/* +Based on Datasheet V33---090401 +Register Summary +Current IOREG MAP +0x0000h ~ 0x00FFh System Configuration (256 Bytes) +0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) +0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) +0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) +0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) +0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) +0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) +0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) +0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) +*/ +//---------------------------------------------------------------------------- +// 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) +//---------------------------------------------------------------------------- +/* +#define StopBecon BIT6 +#define StopHigh BIT5 +#define StopMgt BIT4 +#define StopVO BIT3 +#define StopVI BIT2 +#define StopBE BIT1 +#define StopBK BIT0 +*/ + + +//----------------------------------------------------- +// +// 0xFE00h ~ 0xFE55h USB Configuration +// +//----------------------------------------------------- +/*#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + +#define REG_USB_HRPWM 0xFE58 +#define REG_USB_HCPWM 0xFE57 + +//2 USB Information (0xFE17) +#define USB_IS_HIGH_SPEED 0 +#define USB_IS_FULL_SPEED 1 +#define USB_SPEED_MASK BIT(5) + +#define USB_NORMAL_SIE_EP_MASK 0xF +#define USB_NORMAL_SIE_EP_SHIFT 4 + +//2 Special Option +#define USB_AGG_EN BIT(3) + +*/ +//============================================================================ +// 8192C Regsiter Bit and Content definition +//============================================================================ +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +/* +//2 SYS_ISO_CTRL +#define ISO_MD2PP BIT(0) +#define ISO_UA2USB BIT(1) +#define ISO_UD2CORE BIT(2) +#define ISO_PA2PCIE BIT(3) +#define ISO_PD2CORE BIT(4) +#define ISO_IP2MAC BIT(5) +#define ISO_DIOP BIT(6) +#define ISO_DIOE BIT(7) +#define ISO_EB2CORE BIT(8) +#define ISO_DIOR BIT(9) +#define PWC_EV12V BIT(15) + + +//2 SYS_FUNC_EN +#define FEN_BBRSTB BIT(0) +#define FEN_BB_GLB_RSTn BIT(1) +#define FEN_USBA BIT(2) +#define FEN_UPLL BIT(3) +#define FEN_USBD BIT(4) +#define FEN_DIO_PCIE BIT(5) +#define FEN_PCIEA BIT(6) +#define FEN_PPLL BIT(7) +#define FEN_PCIED BIT(8) +#define FEN_DIOE BIT(9) +#define FEN_CPUEN BIT(10) +#define FEN_DCORE BIT(11) +#define FEN_ELDR BIT(12) +#define FEN_DIO_RF BIT(13) +#define FEN_HWPDN BIT(14) +#define FEN_MREGEN BIT(15) + +//2 APS_FSMCO +#define PFM_LDALL BIT(0) +#define PFM_ALDN BIT(1) +#define PFM_LDKP BIT(2) +#define PFM_WOWL BIT(3) +#define EnPDN BIT(4) +#define PDN_PL BIT(5) +#define APFM_ONMAC BIT(8) +#define APFM_OFF BIT(9) +#define APFM_RSM BIT(10) +#define AFSM_HSUS BIT(11) +#define AFSM_PCIE BIT(12) +#define APDM_MAC BIT(13) +#define APDM_HOST BIT(14) +#define APDM_HPDN BIT(15) +#define RDY_MACON BIT(16) +#define SUS_HOST BIT(17) +#define ROP_ALD BIT(20) +#define ROP_PWR BIT(21) +#define ROP_SPS BIT(22) +#define SOP_MRST BIT(25) +#define SOP_FUSE BIT(26) +#define SOP_ABG BIT(27) +#define SOP_AMB BIT(28) +#define SOP_RCK BIT(29) +#define SOP_A8M BIT(30) +#define XOP_BTCK BIT(31) + +//2 SYS_CLKR +#define ANAD16V_EN BIT(0) +#define ANA8M BIT(1) +#define MACSLP BIT(4) +#define LOADER_CLK_EN BIT(5) + + +//2 9346CR + +#define BOOT_FROM_EEPROM BIT(4) +#define EEPROM_EN BIT(5) + + +//2 RF_CTRL +#define RF_EN BIT(0) +#define RF_RSTB BIT(1) +#define RF_SDMRSTB BIT(2) + +//2 LDOV12D_CTRL +#define LDV12_EN BIT(0) +#define LDV12_SDBY BIT(1) +#define LPLDO_HSM BIT(2) +#define LPLDO_LSM_DIS BIT(3) +#define _LDV12_VADJ(x) (((x) & 0xF) << 4) + + +//2 EFUSE_TEST (For RTL8723 partially) +#define EF_TRPT BIT(7) +#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 +#define LDOE25_EN BIT(31) +#define EFUSE_SEL(x) (((x) & 0x3) << 8) +#define EFUSE_SEL_MASK 0x300 +#define EFUSE_WIFI_SEL_0 0x0 +#define EFUSE_BT_SEL_0 0x1 +#define EFUSE_BT_SEL_1 0x2 +#define EFUSE_BT_SEL_2 0x3 + + +//2 8051FWDL +//2 MCUFWDL +#define MCUFWDL_EN BIT(0) +#define MCUFWDL_RDY BIT(1) +#define FWDL_ChkSum_rpt BIT(2) +#define MACINI_RDY BIT(3) +#define BBINI_RDY BIT(4) +#define RFINI_RDY BIT(5) +#define WINTINI_RDY BIT(6) +#define RAM_DL_SEL BIT(7) +#define ROM_DLEN BIT(19) +#define CPRST BIT(23) + + + +//2 REG_SYS_CFG +#define XCLK_VLD BIT(0) +#define ACLK_VLD BIT(1) +#define UCLK_VLD BIT(2) +#define PCLK_VLD BIT(3) +#define PCIRSTB BIT(4) +#define V15_VLD BIT(5) +#define TRP_B15V_EN BIT(7) +#define SIC_IDLE BIT(8) +#define BD_MAC2 BIT(9) +#define BD_MAC1 BIT(10) +#define IC_MACPHY_MODE BIT(11) +#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) +#define BT_FUNC BIT(16) +#define VENDOR_ID BIT(19) +#define PAD_HWPD_IDN BIT(22) +#define TRP_VAUX_EN BIT(23) // RTL ID +#define TRP_BT_EN BIT(24) +#define BD_PKG_SEL BIT(25) +#define BD_HCI_SEL BIT(26) +#define TYPE_ID BIT(27) + +#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 +#define CHIP_VER_RTL_SHIFT 12 + +*/ +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +/* + +//2 Function Enable Registers +//2 CR 0x0100-0x0103 + + +#define HCI_TXDMA_EN BIT(0) +#define HCI_RXDMA_EN BIT(1) +#define TXDMA_EN BIT(2) +#define RXDMA_EN BIT(3) +#define PROTOCOL_EN BIT(4) +#define SCHEDULE_EN BIT(5) +#define MACTXEN BIT(6) +#define MACRXEN BIT(7) +#define ENSWBCN BIT(8) +#define ENSEC BIT(9) +#define CALTMR_EN BIT(10) // 32k CAL TMR enable + +// Network type +#define _NETTYPE(x) (((x) & 0x3) << 16) +#define MASK_NETTYPE 0x30000 +#define NT_NO_LINK 0x0 +#define NT_LINK_AD_HOC 0x1 +#define NT_LINK_AP 0x2 +#define NT_AS_AP 0x3 + + +//2 PBP - Page Size Register 0x0104 +#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) +#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) +#define _PSRX_MASK 0xF +#define _PSTX_MASK 0xF0 +#define _PSRX(x) (x) +#define _PSTX(x) ((x) << 4) + +#define PBP_64 0x0 +#define PBP_128 0x1 +#define PBP_256 0x2 +#define PBP_512 0x3 +#define PBP_1024 0x4 + + +//2 TX/RXDMA 0x010C +#define RXDMA_ARBBW_EN BIT(0) +#define RXSHFT_EN BIT(1) +#define RXDMA_AGG_EN BIT(2) +#define QS_VO_QUEUE BIT(8) +#define QS_VI_QUEUE BIT(9) +#define QS_BE_QUEUE BIT(10) +#define QS_BK_QUEUE BIT(11) +#define QS_MANAGER_QUEUE BIT(12) +#define QS_HIGH_QUEUE BIT(13) + +#define HQSEL_VOQ BIT(0) +#define HQSEL_VIQ BIT(1) +#define HQSEL_BEQ BIT(2) +#define HQSEL_BKQ BIT(3) +#define HQSEL_MGTQ BIT(4) +#define HQSEL_HIQ BIT(5) + +// For normal driver, 0x10C +#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) +#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) +#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) +#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) +#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) +#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) + +#define QUEUE_LOW 1 +#define QUEUE_NORMAL 2 +#define QUEUE_HIGH 3 + + +//2 REG_C2HEVT_CLEAR 0x01AF +#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message +#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. + + + +//2 LLT_INIT 0x01E0 +#define _LLT_NO_ACTIVE 0x0 +#define _LLT_WRITE_ACCESS 0x1 +#define _LLT_READ_ACCESS 0x2 + +#define _LLT_INIT_DATA(x) ((x) & 0xFF) +#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) +#define _LLT_OP(x) (((x) & 0x3) << 30) +#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) + +*/ +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +/* +//2 TDECTL 0x0208 +#define BLK_DESC_NUM_SHIFT 4 +#define BLK_DESC_NUM_MASK 0xF + + +//2 TXDMA_OFFSET_CHK 0x020C +#define DROP_DATA_EN BIT(9) +*/ +//----------------------------------------------------- +// +// 0x0280h ~ 0x028Bh RX DMA Configuration +// +//----------------------------------------------------- +/* +//2 REG_RXDMA_CONTROL, 0x0286h + +// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before +// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. +#define RXPKT_RELEASE_POLL BIT(0) +// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in +// this bit. FW can start releasing packets after RXDMA entering idle mode. +#define RXDMA_IDLE BIT(1) +// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host +// completed, and stop DMA packet to host. RXDMA will then report Default: 0; +#define RW_RELEASE_EN BIT(2) +*/ +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +/* +//2 FWHW_TXQ_CTRL 0x0420 +#define EN_AMPDU_RTY_NEW BIT(7) + + +//2 REG_LIFECTRL_CTRL 0x0426 +#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 +#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 +#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 +#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 + +#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. + + +//2 SPEC SIFS 0x0428 +#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) +#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) + +//2 RL 0x042A +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + +#define _LRL(x) ((x) & 0x3F) +#define _SRL(x) (((x) & 0x3F) << 8) +*/ + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +/* +//2 EDCA setting 0x050C +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + + +//2 BCN_CTRL 0x0550 +#define EN_TXBCN_RPT BIT(2) +#define EN_BCN_FUNCTION BIT(3) + +//2 TxPause 0x0522 +#define STOP_BCNQ BIT(6) +*/ + + +//2 ACMHWCTRL 0x05C0 +#define AcmHw_HwEn_8723B BIT(0) +#define AcmHw_VoqEn_8723B BIT(1) +#define AcmHw_ViqEn_8723B BIT(2) +#define AcmHw_BeqEn_8723B BIT(3) +#define AcmHw_VoqStatus_8723B BIT(5) +#define AcmHw_ViqStatus_8723B BIT(6) +#define AcmHw_BeqStatus_8723B BIT(7) + + + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- + + +//2 TCR 0x0604 +#define DIS_GCLK BIT(1) +#define PAD_SEL BIT(2) +#define PWR_ST BIT(6) +#define PWRBIT_OW_EN BIT(7) +#define ACRC BIT(8) +#define CFENDFORM BIT(9) +#define ICV BIT(10) + + +//---------------------------------------------------------------------------- +// 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) +//---------------------------------------------------------------------------- +/* +#define RCR_APPFCS BIT31 // WMAC append FCS after pauload +#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet. +#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet. +#define RCR_APP_PHYST_RXFF BIT28 // HY Status is appended before RX packet in RXFF +#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. +#define RCR_RSVD_BIT26 BIT26 // Reserved +*/ +#define RCR_TCPOFLD_EN BIT25 // Enable TCP checksum offload +/*#define RCR_ENMBID BIT24 // Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. +#define RCR_LSIGEN BIT23 // Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. +#define RCR_MFBEN BIT22 // Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. +*/ +#define RCR_MAC_RESET BIT19 // WMAC clock stop and reset after BB transmitting end, 0: enable, 1: disable. +#define RCR_TIM_PARSER_EN BIT18 // RX Beacon TIM Parser. +#define RCR_BM_DATA_EN BIT17 // Broadcast data packet interrupt enable. +#define RCR_UC_DATA_EN BIT16 // Unicast data packet interrupt enable. + +/*#define RCR_HTC_LOC_CTRL BIT14 // MFC<--HTC=1 MFC-->HTC=0 +#define RCR_AMF BIT13 // Accept management type frame +#define RCR_ACF BIT12 // Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. +#define RCR_ADF BIT11 // Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). +*/ +/*#define RCR_AICV BIT9 // Accept ICV error packet +#define RCR_ACRC32 BIT8 // Accept CRC32 error packet +#define RCR_CBSSID_BCN BIT7 // Accept BSSID match packet (Rx beacon, probe rsp) +#define RCR_CBSSID_DATA BIT6 // Accept BSSID match packet (Data) +#define RCR_CBSSID RCR_CBSSID_DATA // Accept BSSID match packet +#define RCR_APWRMGT BIT5 // Accept power management packet +#define RCR_ADD3 BIT4 // Accept address 3 match packet +#define RCR_AB BIT3 // Accept broadcast packet +#define RCR_AM BIT2 // Accept multicast packet +#define RCR_APM BIT1 // Accept physical match packet +#define RCR_AAP BIT0 // Accept all unicast packet + +#define AAP BIT(0) +#define APM BIT(1) +#define AM BIT(2) +#define AB BIT(3) +#define ADD3 BIT(4) +#define APWRMGT BIT(5) +#define CBSSID BIT(6) +#define CBSSID_DATA BIT(6) +#define CBSSID_BCN BIT(7) +#define ACRC32 BIT(8) +#define AICV BIT(9) +#define ADF BIT(11) +#define ACF BIT(12) +#define AMF BIT(13) +#define HTC_LOC_CTRL BIT(14) +#define UC_DATA_EN BIT(16) +#define BM_DATA_EN BIT(17) +#define MFBEN BIT(22) +#define LSIGEN BIT(23) +#define EnMBID BIT(24) +#define APP_BASSN BIT(27) +#define APP_PHYSTS BIT(28) +#define APP_ICV BIT(29) +#define APP_MIC BIT(30) +*/ + +//---------------------------------------------------------------------------- +// 8195 CAM Config Setting (offset 0x680, 1 byte) +//---------------------------------------------------------------------------- +/* +#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key +#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key +#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption +#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption +#define SCR_SKByA2 BIT(4) //Search kEY BY A2 +#define SCR_NoSKMC BIT(5) //No Key Search Multicast +#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key +#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key + +#define CAM_NONE 0x0 +#define CAM_WEP40 0x01 +#define CAM_TKIP 0x02 +#define CAM_AES 0x04 +#define CAM_WEP104 0x05 +#define CAM_SMS4 0x6 + +#define TOTAL_CAM_ENTRY 32 +#define HALF_CAM_ENTRY 16 + +#define CAM_CONFIG_USEDK TRUE +#define CAM_CONFIG_NO_USEDK FALSE + + +#define SCR_UseDK 0x01 +#define SCR_TxSecEnable 0x02 +#define SCR_RxSecEnable 0x04 +*/ + +//---------------------------------------------------------------------------- +// 8195 REG_BCN_PSR_RPT (Beacon Parser Report Register) (Offset 0x6A8, 32 bits) +//---------------------------------------------------------------------------- + +#define PS_TIM BIT14 +#define PS_DTIM BIT15 + +//----------------------------------------------------- +// +// 0xFE00h ~ 0xFE55h RTL8723 SDIO Configuration +// +//----------------------------------------------------- +/* +//SDIO host local register space mapping. +#define SDIO_LOCAL_MSK 0x0FFF +#define WLAN_IOREG_MSK 0x7FFF +#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0] + +#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID +#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13] +#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13] +#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13] +#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13] +#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13] +#define WLAN_IOREG_DEVICE_ID 8 // 1b[16] + +//SDIO Tx Free Page Index +#define HI_QUEUE_IDX 0 +#define MID_QUEUE_IDX 1 +#define LOW_QUEUE_IDX 2 +#define PUBLIC_QUEUE_IDX 3 + +#define SDIO_REG_TX_CTRL 0x0000 // SDIO Tx Control +#define SDIO_REG_HIMR 0x0014 // SDIO Host Interrupt Mask +#define SDIO_REG_HISR 0x0018 // SDIO Host Interrupt Service Routine +#define SDIO_REG_HCPWM 0x0019 // HCI Current Power Mode +#define SDIO_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length +#define SDIO_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page +#define SDIO_REG_HCPWM1 0x0024 // HCI Current Power Mode 1 +#define SDIO_REG_HCPWM2 0x0026 // HCI Current Power Mode 2 +#define SDIO_REG_HTSFR_INFO 0x0030 // HTSF Informaion +#define SDIO_REG_HRPWM1 0x0080 // HCI Request Power Mode 1 +#define SDIO_REG_HRPWM2 0x0082 // HCI Request Power Mode 2 +#define SDIO_REG_HPS_CLKR 0x0084 // HCI Power Save Clock +#define SDIO_REG_HSUS_CTRL 0x0086 // SDIO HCI Suspend Control +#define SDIO_REG_HIMR_ON 0x0090 //SDIO Host Extension Interrupt Mask Always +#define SDIO_REG_HISR_ON 0x0091 //SDIO Host Extension Interrupt Status Always + +#define SDIO_HIMR_DISABLED 0 + +// RTL8723/RTL8188E SDIO Host Interrupt Mask Register +#define SDIO_HIMR_RX_REQUEST_MSK BIT0 +#define SDIO_HIMR_AVAL_MSK BIT1 +#define SDIO_HIMR_TXERR_MSK BIT2 +#define SDIO_HIMR_RXERR_MSK BIT3 +#define SDIO_HIMR_TXFOVW_MSK BIT4 +#define SDIO_HIMR_RXFOVW_MSK BIT5 +#define SDIO_HIMR_TXBCNOK_MSK BIT6 +#define SDIO_HIMR_TXBCNERR_MSK BIT7 +#define SDIO_HIMR_BCNERLY_INT_MSK BIT16 +#define SDIO_HIMR_C2HCMD_MSK BIT17 +#define SDIO_HIMR_CPWM1_MSK BIT18 +#define SDIO_HIMR_CPWM2_MSK BIT19 +#define SDIO_HIMR_HSISR_IND_MSK BIT20 +#define SDIO_HIMR_GTINT3_IND_MSK BIT21 +#define SDIO_HIMR_GTINT4_IND_MSK BIT22 +#define SDIO_HIMR_PSTIMEOUT_MSK BIT23 +#define SDIO_HIMR_OCPINT_MSK BIT24 +#define SDIO_HIMR_ATIMEND_MSK BIT25 +#define SDIO_HIMR_ATIMEND_E_MSK BIT26 +#define SDIO_HIMR_CTWEND_MSK BIT27 + +//RTL8188E SDIO Specific +#define SDIO_HIMR_MCU_ERR_MSK BIT28 +#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 + +// SDIO Host Interrupt Service Routine +#define SDIO_HISR_RX_REQUEST BIT0 +#define SDIO_HISR_AVAL BIT1 +#define SDIO_HISR_TXERR BIT2 +#define SDIO_HISR_RXERR BIT3 +#define SDIO_HISR_TXFOVW BIT4 +#define SDIO_HISR_RXFOVW BIT5 +#define SDIO_HISR_TXBCNOK BIT6 +#define SDIO_HISR_TXBCNERR BIT7 +#define SDIO_HISR_BCNERLY_INT BIT16 +#define SDIO_HISR_C2HCMD BIT17 +#define SDIO_HISR_CPWM1 BIT18 +#define SDIO_HISR_CPWM2 BIT19 +#define SDIO_HISR_HSISR_IND BIT20 +#define SDIO_HISR_GTINT3_IND BIT21 +#define SDIO_HISR_GTINT4_IND BIT22 +#define SDIO_HISR_PSTIMEOUT BIT23 +#define SDIO_HISR_OCPINT BIT24 +#define SDIO_HISR_ATIMEND BIT25 +#define SDIO_HISR_ATIMEND_E BIT26 +#define SDIO_HISR_CTWEND BIT27 + +//RTL8188E SDIO Specific +#define SDIO_HISR_MCU_ERR BIT28 +#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 + + +// SDIO HCI Suspend Control Register +#define HCI_RESUME_PWR_RDY BIT1 +#define HCI_SUS_CTRL BIT0 + + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + #define MAX_TX_AGG_PACKET_NUMBER 0x8 +#else + #define MAX_TX_AGG_PACKET_NUMBER 0xFF +#endif + +*/ +#endif // #ifndef __INC_HAL8195AREG_H diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/HalPhyRf_8195A.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/HalPhyRf_8195A.h new file mode 100644 index 0000000..3f22d3f --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/HalPhyRf_8195A.h @@ -0,0 +1,127 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8195A_H__ +#define __HAL_PHY_RF_8195A_H__ + + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_8195A 10 //ms +#define IQK_DEFERRED_TIME_8195A 4 +#define index_mapping_NUM_8195A 15 +#define AVG_THERMAL_NUM_8195A 4 +#define RF_T_METER_8195A 0x42 // + + +void ConfigureTxpowerTrack_8195A( + PTXPWRTRACK_CFG pConfig + ); + +void DoIQK_8195A( + PDM_ODM_T pDM_Odm, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr_8195A( + PDM_ODM_T pDM_Odm, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +VOID +ODM_TxXtalTrackSetXtal_8195A( + PDM_ODM_T pDM_Odm +); + + +//1 7. IQK + +void +PHY_IQCalibrate_8195A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery, + IN BOOLEAN bRestore); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8195A( + IN PDM_ODM_T pDM_Odm +); + + +VOID +_PHY_SaveADDARegisters_8195A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn_8195A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration_8195A( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + + +VOID +_PHY_PathAStandBy( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ); + + +#endif // #ifndef __HAL_PHY_RF_8188E_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/ROM_RTL8195A_PHYDM.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/ROM_RTL8195A_PHYDM.h new file mode 100644 index 0000000..7123055 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/ROM_RTL8195A_PHYDM.h @@ -0,0 +1,128 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ROM_RTL8195A_PHYDM_H__ +#define __ROM_RTL8195A_PHYDM_H__ + +typedef struct _FALSE_ALARM_STATISTICS{ + u4Byte Cnt_Parity_Fail; + u4Byte Cnt_Rate_Illegal; + u4Byte Cnt_Crc8_fail; + u4Byte Cnt_Mcs_fail; + u4Byte Cnt_Ofdm_fail; + u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A + u4Byte Cnt_Cck_fail; + u4Byte Cnt_all; + u4Byte Cnt_Fast_Fsync; + u4Byte Cnt_SB_Search_fail; + u4Byte Cnt_OFDM_CCA; + u4Byte Cnt_CCK_CCA; + u4Byte Cnt_CCA_all; + u4Byte Cnt_BW_USC; //Gary + u4Byte Cnt_BW_LSC; //Gary +}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; + +typedef struct _CFO_TRACKING_ +{ + BOOLEAN bATCStatus; + BOOLEAN largeCFOHit; + BOOLEAN bAdjust; + u1Byte CrystalCap; + u1Byte DefXCap; + int CFO_tail[2]; + int CFO_ave_pre; + u4Byte packetCount; + u4Byte packetCount_pre; + BOOLEAN bForceXtalCap; + BOOLEAN bReset; + u1Byte CFO_TH_XTAL_HIGH; + u1Byte CFO_TH_XTAL_LOW; + u1Byte CFO_TH_ATC; +}CFO_TRACKING, *PCFO_TRACKING; + +typedef struct _ROM_INFO{ + u1Byte EEPROMVersion; + u1Byte CrystalCap; + u8Byte DebugComponents; + u4Byte DebugLevel; +}ROM_INFO, *PROM_INFO; + +extern FALSE_ALARM_STATISTICS FalseAlmCnt; +extern CFO_TRACKING DM_CfoTrack; +extern ROM_INFO ROMInfo; + +u1Byte +ROM_odm_QueryRxPwrPercentage( + IN s1Byte AntPower +); + + +u1Byte +ROM_odm_EVMdbToPercentage( + IN s1Byte Value +); + +s4Byte +ROM_odm_SignalScaleMapping_8195A( + IN u1Byte SupportInterface, + IN s4Byte CurrSig +); + +VOID +ROM_odm_FalseAlarmCounterStatistics( + IN PVOID pDM_VOID +); + +VOID +ROM_odm_SetEDCCAThreshold( + IN PVOID pDM_VOID, + IN s1Byte H2L, + IN s1Byte L2H +); + +VOID +ROM_odm_SetTRxMux( + IN PVOID pDM_VOID, + IN ODM_Trx_MUX_Type txMode, + IN ODM_Trx_MUX_Type rxMode +); + + +VOID +ROM_odm_SetCrystalCap( + IN PVOID pDM_VOID, + IN u1Byte CrystalCap +); + +u1Byte +ROM_odm_GetDefaultCrytaltalCap( + IN PVOID pDM_VOID +); + +VOID +ROM_ODM_CfoTrackingReset( + IN PVOID pDM_VOID +); + +VOID +ROM_odm_CfoTrackingFlow( + IN PVOID pDM_VOID +); + +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/halhwimg8195a_bb.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/halhwimg8195a_bb.h new file mode 100644 index 0000000..e352ab4 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/halhwimg8195a_bb.h @@ -0,0 +1,59 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.23*/ +#if (RTL8195A_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8195A_H +#define __INC_MP_BB_HW_IMG_8195A_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8195A_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8195A_AGC_TAB(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8195A_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8195A_PHY_REG(void); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8195A_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8195A_PHY_REG_PG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/halhwimg8195a_mac.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/halhwimg8195a_mac.h new file mode 100644 index 0000000..23cdd26 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/halhwimg8195a_mac.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.23*/ +#if (RTL8195A_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8195A_H +#define __INC_MP_MAC_HW_IMG_8195A_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8195A_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8195A_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/halhwimg8195a_rf.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/halhwimg8195a_rf.h new file mode 100644 index 0000000..fa7b2ed --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/halhwimg8195a_rf.h @@ -0,0 +1,104 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.23*/ +#if (RTL8195A_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8195A_H +#define __INC_MP_RF_HW_IMG_8195A_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8195A_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8195A_RadioA(void); + +/****************************************************************************** +* RADIO_DIFF.TXT +******************************************************************************/ + +extern u4Byte Array_MP_8195A_RADIO_DIFF_LB[50]; +extern u4Byte Array_MP_8195A_RADIO_DIFF_MB[50]; +extern u4Byte Array_MP_8195A_RADIO_DIFF_HB[50]; +void +ODM_ReadAndConfig_MP_8195A_RADIO_DIFF( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Array[], + IN u4Byte ArrayLen +); +u4Byte ODM_GetVersion_MP_8195A_RADIO_DIFF(void); + +/****************************************************************************** +* TxPowerTrack_QFN48.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8195A_TxPowerTrack_QFN48(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8195A_TxPowerTrack_QFN48(void); + +/****************************************************************************** +* TxPowerTrack_QFN56.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8195A_TxPowerTrack_QFN56(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8195A_TxPowerTrack_QFN56(void); + +/****************************************************************************** +* TxPowerTrack_TFBGA96.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8195A_TxPowerTrack_TFBGA96(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8195A_TxPowerTrack_TFBGA96(void); + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8195A_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8195A_TXPWR_LMT(void); + +/****************************************************************************** +* TxXtalTrack.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8195A_TxXtalTrack(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8195A_TxXtalTrack(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/phydm_RTL8195A.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/phydm_RTL8195A.h new file mode 100644 index 0000000..5b73912 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/phydm_RTL8195A.h @@ -0,0 +1,69 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_RTL8723B_H__ +#define __ODM_RTL8723B_H__ + +#define DM_DIG_MIN_NIC_8723 0x1C + +#if (defined(CONFIG_HW_ANTENNA_DIVERSITY)) + +VOID +ODM_AntennaDiversityInit_8723B( IN PDM_ODM_T pDM_Odm); + +VOID +ODM_AntselStatistics_8723B( + IN PDM_ODM_T pDM_Odm, + IN u1Byte antsel_tr_mux, + IN u4Byte MacId, + IN u4Byte RxPWDBAll); + +VOID +ODM_AntennaDiversity_8723B( IN PDM_ODM_T pDM_Odm); + + +VOID +ODM_UpdateRxIdleAnt_8723B(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant); + +VOID +ODM_SetTxAntByTxInfo_8723B( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pDesc, + IN u1Byte macId +); + +#endif + +VOID +odm_DIG_8723(IN PDM_ODM_T pDM_Odm); + +s1Byte +odm_CCKRSSI_8723B( + IN u1Byte LNA_idx, + IN u1Byte VGA_idx + ); + +s1Byte +odm_RSSIOFDM_8723B( + IN s1Byte rx_pwr_new + ); + + + +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/phydm_RegConfig8195A.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/phydm_RegConfig8195A.h new file mode 100644 index 0000000..4dbf0dd --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/phydm_RegConfig8195A.h @@ -0,0 +1,89 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8195A +#define __INC_ODM_REGCONFIG_H_8195A + +#if (RTL8195A_SUPPORT == 1) + +void +odm_ConfigRFReg_8195A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8195A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8195A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_ConfigBB_AGC_8195A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8195A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8195A( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_TXPWR_LMT_8195A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Regulation, + IN u1Byte Band, + IN u1Byte Bandwidth, + IN u1Byte RateSection, + IN u1Byte RfPath, + IN u1Byte Channel, + IN u1Byte PowerLimit + ); + +#endif +#endif // end of SUPPORT + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/hal_data.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/hal_data.h new file mode 100644 index 0000000..cb52109 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/hal_data.h @@ -0,0 +1,498 @@ +/****************************************************************************** + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ +#ifndef __HAL_DATA_H__ +#define __HAL_DATA_H__ + + +#include "hal_com.h" +#ifdef CONFIG_RTL8188F +#include "OUTSRC/rtl8188f/phydm_precomp.h" +#else +#include "OUTSRC/phydm_precomp.h" +#endif + +#ifdef CONFIG_RTL8723A +#include "rtl8723a/rtl8723a_hal.h" +#endif +#ifdef CONFIG_RTL8188E +#include "rtl8188e/rtl8188e_hal.h" +#endif +#ifdef CONFIG_RTL8195A +#include "rtl8195a_hal.h" +#endif +#if (CONFIG_RTL8711B ==1) +#include "rtl8711b_hal.h" +#endif +#ifdef CONFIG_RTL8188F +#include "rtl8188f/rtl8188f_hal.h" +#endif +// +// For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. +// +typedef enum _RT_MULTI_FUNC{ + RT_MULTI_FUNC_NONE = 0x00, + RT_MULTI_FUNC_WIFI = 0x01, + RT_MULTI_FUNC_BT = 0x02, + RT_MULTI_FUNC_GPS = 0x04, +}RT_MULTI_FUNC,*PRT_MULTI_FUNC; +// +// For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. +// +typedef enum _RT_POLARITY_CTL { + RT_POLARITY_LOW_ACT = 0, + RT_POLARITY_HIGH_ACT = 1, +} RT_POLARITY_CTL, *PRT_POLARITY_CTL; + +// For RTL8723 regulator mode. by tynli. 2011.01.14. +typedef enum _RT_REGULATOR_MODE { + RT_SWITCHING_REGULATOR = 0, + RT_LDO_REGULATOR = 1, +} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE; + +#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number +#define CHANNEL_MAX_NUMBER_2G 14 +#define CHANNEL_MAX_NUMBER_5G 54 // Please refer to "phy_GetChnlGroup8812A" and "Hal_ReadTxPowerInfo8812A" +#define CHANNEL_MAX_NUMBER_5G_80M 7 + +// Tx Power Limit Table Size +#define MAX_REGULATION_NUM 3 // FCC, ETSI, MKK +#define MAX_2_4G_BANDWITH_NUM 2 // 20M, 40M +#if defined(NOT_SUPPORT_RF_MULTIPATH) && defined(NOT_SUPPORT_VHT) +#define MAX_RATE_SECTION_NUM 3 // CCk, OFDM, HT +#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 3 // CCK:1,OFDM:1, HT:1(MCS0_MCS7) +#else +#define MAX_RATE_SECTION_NUM 10 +#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 // CCK:1,OFDM:1, HT:4, VHT:4 +#endif +#define MAX_5G_BANDWITH_NUM 4 +#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 // OFDM:1, HT:4, VHT:4 + +#define HCI_SUS_ENTER 0 +#define HCI_SUS_LEAVING 1 +#define HCI_SUS_LEAVE 2 +#define HCI_SUS_ENTERING 3 +#define HCI_SUS_ERR 4 + + +struct dm_priv +{ + u8 DM_Type; + u8 DMFlag; + u8 InitDMFlag; + u32 InitODMFlag; + + //* Upper and Lower Signal threshold for Rate Adaptive*/ + int UndecoratedSmoothedPWDB; + int UndecoratedSmoothedCCK; + int EntryMinUndecoratedSmoothedPWDB; + int EntryMaxUndecoratedSmoothedPWDB; + int MinUndecoratedPWDBForDM; + int LastMinUndecoratedPWDBForDM; + + + //for High Power + u8 bDynamicTxPowerEnable; + u8 LastDTPLvl; + u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 + + //for tx power tracking + u8 bTXPowerTracking; + u8 TXPowercount; + u8 bTXPowerTrackingInit; + u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default + + u8 PowerIndex_backup[6]; + + s32 OFDM_Pkt_Cnt; + + // Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas + u8 INIDATA_RATE[32]; +}; + +#ifdef CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD +#define MCUCMDQUEUEDEPTH 15 +#define MCUCMDLENGTH 2 +#define MACIDNUM 128 +typedef struct _cmd_queue_{ + u32 FwCmdContent[MCUCMDLENGTH]; +}CMD_QUEUE; +#endif + + +#ifdef CONFIG_RF_GAIN_OFFSET +#ifdef CONFIG_RTL8188F +struct kfree_data_t { + u8 flag; + s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX]; + s8 thermal; +}; + +#define KFREE_FLAG_ON BIT0 +#define KFREE_FLAG_THERMAL_K_ON BIT1 +#endif +#endif + +typedef struct hal_com_data +{ + HAL_VERSION VersionID; +// RT_MULTI_FUNC MultiFunc; // For multi-function consideration. +// RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control. + RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO + u16 CustomerID; +#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) ||defined (CONFIG_RTL8188F) + u16 ForcedDataRate;// Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. +#endif + + u16 FirmwareVersion; + u16 FirmwareVersionRev; + u16 FirmwareSubVersion; + u16 FirmwareSignature; +// u8 PGMaxGroup; + //current WIFI_PHY values + u32 ReceiveConfig; +// WIRELESS_MODE CurrentWirelessMode; + CHANNEL_WIDTH CurrentChannelBW; +#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)||defined (CONFIG_RTL8188F) + BAND_TYPE CurrentBandType; //0:2.4G, 1:5G +#endif + u8 CurrentChannel; + u8 nCur40MhzPrimeSC;// Control channel sub-carrier + u8 CurrentCenterFrequencyIndex1; +#if !defined(NOT_SUPPORT_80M) + u8 nCur80MhzPrimeSC; //used for primary 40MHz of 80MHz mode +#endif + + u16 BasicRateSet; + u8 hci_sus_state; + //rf_ctrl + u8 rf_chip; + u8 rf_type; +#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)||defined (CONFIG_RTL8188F) + u8 PackageType; + u8 ChipID; +#endif + u8 NumTotalRFPath; + + u8 BoardType; + + // + // EEPROM setting. + // +// u16 EEPROMVID; +// u16 EEPROMPID; +// u16 EEPROMSVID; +// u16 EEPROMSDID; + u8 EEPROMCustomerID; +// u8 EEPROMSubCustomerID; + u8 EEPROMVersion; + u8 EEPROMRegulatory; + +#ifdef CONFIG_RF_GAIN_OFFSET +#ifdef CONFIG_RTL8188F + struct kfree_data_t kfree_data; +#endif +#endif +// u8 bTXPowerDataReadFromEEPORM; + u8 EEPROMThermalMeter; +// u8 bAPKThermalMeterIgnore; + +// BOOLEAN EepromOrEfuse; + //u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes) + //u8 EfuseUsedPercentage; +#ifdef HAL_EFUSE_MEMORY + EFUSE_HAL EfuseHal; +#endif + //u8 bIQKInitialized; + + u8 Regulation2_4G; +#if !defined(NOT_SUPPORT_5G) + u8 Regulation5G; +#endif +#if defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B)||defined (CONFIG_RTL8188F) + s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND] + [TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RATE]; +#endif + //---------------------------------------------------------------------------------// +#if defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B)||defined (CONFIG_RTL8188F) + u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; + u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; + //If only one tx, only BW20 and OFDM are used. + s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; +#if !defined(NOT_SUPPORT_RF_MULTIPATH) + s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; +#endif + + //2 Power Limit Table + // Power Limit Table for 2.4G + s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM] + [MAX_2_4G_BANDWITH_NUM] + [MAX_RATE_SECTION_NUM] + [CHANNEL_MAX_NUMBER_2G] + [MAX_RF_PATH]; + #if !defined(NOT_SUPPORT_5G) + // Power Limit Table for 5G + s8 TxPwrLimit_5G[MAX_REGULATION_NUM] + [MAX_5G_BANDWITH_NUM] + [MAX_RATE_SECTION_NUM] + [CHANNEL_MAX_NUMBER_5G] + [MAX_RF_PATH]; + #endif + + // Store the original power by rate value of the base of each rate section of rf path A & B + u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RF] + [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; + #if !defined(NOT_SUPPORT_5G) + u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RF] + [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; + #endif +#else + u8 TxPwrLevelCck[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; + u8 TxPwrLevelHT40_1S[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr + u8 TxPwrLevelHT40_2S[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr + u8 TxPwrHt20Diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff + u8 TxPwrLegacyHtDiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff +#endif + + // For power group +// u8 PwrGroupHT20[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; +// u8 PwrGroupHT40[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; + +// u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff + // The current Tx Power Level + u8 CurrentCckTxPwrIdx; + u8 CurrentOfdm24GTxPwrIdx; + u8 CurrentBW2024GTxPwrIdx; + u8 CurrentBW4024GTxPwrIdx; + + u8 CrystalCap; + //u32 AntennaTxPath; // Antenna path Tx + //u32 AntennaRxPath; // Antenna path Rx + //u8 BluetoothCoexist; +// u8 ExternalPA; + +#if defined(CONFIG_RTL8188F) + + /* PHY DM & DM Section */ + u8 INIDATA_RATE[32/*MACID_NUM_SW_LIMIT*/]; + /* Upper and Lower Signal threshold for Rate Adaptive*/ + int EntryMinUndecoratedSmoothedPWDB; + int EntryMaxUndecoratedSmoothedPWDB; + int MinUndecoratedPWDBForDM; +#endif + + //u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. + + //u32 LedControlNum; + //u32 LedControlMode; + //u8 b1x1RecvCombine; // for 1T1R receive combining + + //u8 bCurrentTurboEDCA; +#if defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B)||defined (CONFIG_RTL8188F) + BOOLEAN bSwChnl; + BOOLEAN bSetChnlBW; + BOOLEAN bChnlBWInitialized; +#endif + +// BOOLEAN bNeedIQK; + + u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo. +#if defined(NOT_SUPPORT_RF_MULTIPATH) + BB_REGISTER_DEFINITION_T PHYRegDef[1]; //Radio A + u32 RfRegChnlVal[1]; +#else + BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D + u32 RfRegChnlVal[2]; +#endif + + //RDG enable +// BOOLEAN bRDGEnable; + +#if (defined(CONFIG_RTL8711B) || defined(CONFIG_RTL8188F)) + //for host message to fw + u8 LastHMEBoxNum; +#endif + + u8 fw_ractrl; +// u8 RegTxPause; + // Beacon function related global variable. +// u32 RegBcnCtrlVal; + u8 RegFwHwTxQCtrl; + u8 RegReg542; +// u8 RegCR_1; + u16 RegRRSR; + + struct dm_priv dmpriv; + DM_ODM_T odmpriv; + //_lock odm_stainfo_lock; +#ifdef DBG_CONFIG_ERROR_DETECT + struct sreset_priv srestpriv; +#endif + +#ifdef CONFIG_BT_COEXIST + struct btcoexist_priv bt_coexist; +#endif + +//#ifdef CONFIG_ANTENNA_DIVERSITY + u8 CurAntenna; + u8 AntDivCfg; + u8 TRxAntDivType; +//#endif + +// u8 bDumpRxPkt;//for debug +// u8 bDumpTxPkt;//for debug +// u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. + + // 2010/08/09 MH Add CU power down mode. +// BOOLEAN pwrdown; + + // Add for dual MAC 0--Mac0 1--Mac1 +// u32 interfaceIndex; + + u8 OutEpQueueSel; + u8 OutEpNumber; + + // 2010/12/10 MH Add for USB aggreation mode dynamic shceme. +// BOOLEAN UsbRxHighSpeedMode; + + // 2010/11/22 MH Add for slim combo debug mode selective. + // This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. + //BOOLEAN SlimComboDbg; + + u16 EfuseUsedBytes; + +#ifdef CONFIG_P2P + struct P2P_PS_Offload_t p2p_ps_offload; +#endif + + u8 AMPDUDensity; + + // Auto FSM to Turn On, include clock, isolation, power control for MAC only + u8 bMacPwrCtrlOn; + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + + // + // For SDIO Interface HAL related + // + + // + // SDIO ISR Related + // +// u32 IntrMask[1]; +// u32 IntrMaskToSet[1]; +// LOG_INTERRUPT InterruptLog; +// u32 sdio_himr; +// u32 sdio_hisr; + + // + // SDIO Tx FIFO related. + // + // HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg +// u8 SdioTxFIFOFreePage[TX_FREE_PG_QUEUE]; +// _lock SdioTxFIFOFreePageLock; +// _thread_hdl_ SdioXmitThread; +// _sema SdioXmitSema; +// _sema SdioXmitTerminateSema; + + // + // SDIO Rx FIFO related. + // +// u8 SdioRxFIFOCnt; +// u16 SdioRxFIFOSize; +#endif //CONFIG_SDIO_HCI + +#ifdef CONFIG_USB_HCI + u32 UsbBulkOutSize; + + // Interrupt relatd register information. + u32 IntArray[3];//HISR0,HISR1,HSISR + u32 IntrMask[3]; + //u8 C2hArray[16]; +#ifdef CONFIG_USB_TX_AGGREGATION + u8 UsbTxAggMode; + u8 UsbTxAggDescNum; +#endif +#ifdef CONFIG_USB_RX_AGGREGATION + u16 HwRxPageSize; // Hardware setting + u32 MaxUsbRxAggBlock; + + USB_RX_AGG_MODE UsbRxAggMode; + u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed + u8 UsbRxAggBlockTimeout; + u8 UsbRxAggPageCount; // 8192C DMA page count + u8 UsbRxAggPageTimeout; +#endif +#endif //CONFIG_USB_HCI + + +#if defined (CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI) +// u32 TransmitConfig; + u32 IntArray[3]; + u32 IntrMask[3]; +// u8 bDefaultAntenna; +// u8 bIQKInitialized; + +// u8 bInterruptMigration; +// u8 bDisableTxInt; +#ifdef CONFIG_SUPPORT_HW_WPS_PBC + u8 bGpioHwWpsPbc; +#endif + u16 RxExpectTag; +#ifdef CONFIG_DEBUG_DYNAMIC + struct hal_debug debug_info; +#endif + +#endif //CONFIG_PCI_HCI || CONFIG_LX_HCI + + +#ifdef CONFIG_TX_EARLY_MODE + u8 bEarlyModeEnable; +#endif + +#ifdef CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD + struct task_struct littlewifipriv; + //CMD_QUEUE FwCmdQueue[MCUCMDQUEUEDEPTH]; + //fw section + u32 WifiMcuCmdBitMap; + u8 bConnected[MACIDNUM/8]; + BOOLEAN PMUTaskRAEn; + + u8 BcnIgnoreEdccaEn; + + #ifdef CONFIG_POWER_SAVING + struct task_struct enter32kpriv; + + #ifdef TDMA_POWER_SAVING + struct task_struct TDMApriv; + #endif //#ifdef TDMA_POWER_SAVING + + PS_PARM PSParmpriv; + u8 ScanEn; + #endif //#ifdef CONFIG_POWER_SAVING +#endif + +} HAL_DATA_COMMON, *PHAL_DATA_COMMON; + +typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; +#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) + +#endif //__HAL_DATA_H__ diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8192CPhyReg.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8192CPhyReg.h new file mode 100644 index 0000000..81b226a --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8192CPhyReg.h @@ -0,0 +1,1125 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/***************************************************************************** + * + * Module: __INC_HAL8192CPHYREG_H + * + * + * Note: 1. Define PMAC/BB register map + * 2. Define RF register map + * 3. PMAC/BB register bit mask. + * 4. RF reg bit mask. + * 5. Other BB/RF relative definition. + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. + * 2. Reorganize code architecture. + * 09/25/2008 MH 1. Add RL6052 register definition + * + *****************************************************************************/ +#ifndef __INC_HAL8192CPHYREG_H +#define __INC_HAL8192CPHYREG_H + + +/*--------------------------Define Parameters-------------------------------*/ + +//============================================================ +// 8192S Regsiter offset definition +//============================================================ + +// +// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 +// 3. RF register 0x00-2E +// 4. Bit Mask for BB/RF register +// 5. Other defintion for BB/RF R/W +// + + +// +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 1. Page1(0x100) +// +#define rPMAC_Reset 0x100 +#define rPMAC_TxStart 0x104 +#define rPMAC_TxLegacySIG 0x108 +#define rPMAC_TxHTSIG1 0x10c +#define rPMAC_TxHTSIG2 0x110 +#define rPMAC_PHYDebug 0x114 +#define rPMAC_TxPacketNum 0x118 +#define rPMAC_TxIdle 0x11c +#define rPMAC_TxMACHeader0 0x120 +#define rPMAC_TxMACHeader1 0x124 +#define rPMAC_TxMACHeader2 0x128 +#define rPMAC_TxMACHeader3 0x12c +#define rPMAC_TxMACHeader4 0x130 +#define rPMAC_TxMACHeader5 0x134 +#define rPMAC_TxDataType 0x138 +#define rPMAC_TxRandomSeed 0x13c +#define rPMAC_CCKPLCPPreamble 0x140 +#define rPMAC_CCKPLCPHeader 0x144 +#define rPMAC_CCKCRC16 0x148 +#define rPMAC_OFDMRxCRC32OK 0x170 +#define rPMAC_OFDMRxCRC32Er 0x174 +#define rPMAC_OFDMRxParityEr 0x178 +#define rPMAC_OFDMRxCRC8Er 0x17c +#define rPMAC_CCKCRxRC16Er 0x180 +#define rPMAC_CCKCRxRC32Er 0x184 +#define rPMAC_CCKCRxRC32OK 0x188 +#define rPMAC_TxStatus 0x18c + +// +// 2. Page2(0x200) +// +// The following two definition are only used for USB interface. +#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. +#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. + +// +// 3. Page8(0x800) +// +#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? + +#define rFPGA0_TxInfo 0x804 // Status report?? +#define rFPGA0_PSDFunction 0x808 + +#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? + +#define rFPGA0_RFTiming1 0x810 // Useless now +#define rFPGA0_RFTiming2 0x814 + +#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c +#define rTxAGC_B_Rate18_06 0x830 +#define rTxAGC_B_Rate54_24 0x834 +#define rTxAGC_B_CCK1_55_Mcs32 0x838 +#define rTxAGC_B_Mcs03_Mcs00 0x83c + +#define rTxAGC_B_Mcs07_Mcs04 0x848 +#define rTxAGC_B_Mcs11_Mcs08 0x84c + +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 + +#define rFPGA0_RFWakeUpParameter 0x850 // Useless now +#define rFPGA0_RFSleepUpParameter 0x854 + +#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch +#define rFPGA0_XCD_SwitchControl 0x85c + +#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch +#define rFPGA0_XB_RFInterfaceOE 0x864 + +#define rTxAGC_B_Mcs15_Mcs12 0x868 +#define rTxAGC_B_CCK11_A_CCK2_11 0x86c + +#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control +#define rFPGA0_XCD_RFInterfaceSW 0x874 + +#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter +#define rFPGA0_XCD_RFParameter 0x87c + +#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? +#define rFPGA0_AnalogParameter2 0x884 +#define rFPGA0_AnalogParameter3 0x888 // Useless now +#define rFPGA0_AnalogParameter4 0x88c + +#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback +#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac + +#define rFPGA0_PSDReport 0x8b4 // Useless now +#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback +#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now + +// +// 4. Page9(0x900) +// +#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? + +#define rFPGA1_TxBlock 0x904 // Useless now +#define rFPGA1_DebugSelect 0x908 // Useless now +#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? + +// +// 5. PageA(0xA00) +// +// Set Control channel to upper or lower. These settings are required only for 40MHz +#define rCCK0_System 0xa00 + +#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI +#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain + +#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series +#define rCCK0_RxAGC2 0xa10 //AGC & DAGC + +#define rCCK0_RxHP 0xa14 + +#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold +#define rCCK0_DSPParameter2 0xa1c //SQ threshold + +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 +#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 //0xa57 +#define rCCK0_FACounterLower 0xa5c //0xa5b +#define rCCK0_FACounterUpper 0xa58 //0xa5c +// +// PageB(0xB00) +// +#define rPdp_AntA 0xb00 +#define rPdp_AntA_4 0xb04 +#define rConfig_Pmpd_AntA 0xb28 +#define rConfig_AntA 0xb68 +#define rConfig_AntB 0xb6c +#define rPdp_AntB 0xb70 +#define rPdp_AntB_4 0xb74 +#define rConfig_Pmpd_AntB 0xb98 +#define rAPK 0xbd8 + +// +// 6. PageC(0xC00) +// +#define rOFDM0_LSTF 0xc00 + +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c + +#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter +#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix +#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_XBRxIQImbalance 0xc1c +#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxIQImbalance 0xc24 +#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxIQImbalance 0xc2c + +#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain +#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. +#define rOFDM0_RxDetector3 0xc38 //Frame Sync. +#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI + +#define rOFDM0_RxDSP 0xc40 //Rx Sync Path +#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC +#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold +#define rOFDM0_ECCAThreshold 0xc4c // energy CCA + +#define rOFDM0_XAAGCCore1 0xc50 // DIG +#define rOFDM0_XAAGCCore2 0xc54 +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_XBAGCCore2 0xc5c +#define rOFDM0_XCAGCCore1 0xc60 +#define rOFDM0_XCAGCCore2 0xc64 +#define rOFDM0_XDAGCCore1 0xc68 +#define rOFDM0_XDAGCCore2 0xc6c + +#define rOFDM0_AGCParameter1 0xc70 +#define rOFDM0_AGCParameter2 0xc74 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_HTSTFAGC 0xc7c + +#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG +#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XBTxAFE 0xc8c +#define rOFDM0_XCTxIQImbalance 0xc90 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxIQImbalance 0xc98 +#define rOFDM0_XDTxAFE 0xc9c + +#define rOFDM0_RxIQExtAnta 0xca0 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_TxCoeff6 0xcb8 +#define rOFDM0_RxHPParameter 0xce0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 + +// +// 7. PageD(0xD00) +// +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 + +#define rOFDM1_CFO 0xd08 // No setting now +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_TRxMesaure1 0xd34 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 + +#define rOFDM_PHYCounter1 0xda0 //cca, parity fail +#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail +#define rOFDM_PHYCounter3 0xda8 //MCS not support + +#define rOFDM_ShortCFOAB 0xdac // No setting now +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM_PWMeasure1 0xdc4 +#define rOFDM_PWMeasure2 0xdc8 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + + +// +// 8. PageE(0xE00) +// +#define rTxAGC_A_Rate18_06 0xe00 +#define rTxAGC_A_Rate54_24 0xe04 +#define rTxAGC_A_CCK1_Mcs32 0xe08 +#define rTxAGC_A_Mcs03_Mcs00 0xe10 +#define rTxAGC_A_Mcs07_Mcs04 0xe14 +#define rTxAGC_A_Mcs11_Mcs08 0xe18 +#define rTxAGC_A_Mcs15_Mcs12 0xe1c + +#define rFPGA0_IQK 0xe28 +#define rTx_IQK_Tone_A 0xe30 +#define rRx_IQK_Tone_A 0xe34 +#define rTx_IQK_PI_A 0xe38 +#define rRx_IQK_PI_A 0xe3c + +#define rTx_IQK 0xe40 +#define rRx_IQK 0xe44 +#define rIQK_AGC_Pts 0xe48 +#define rIQK_AGC_Rsp 0xe4c +#define rTx_IQK_Tone_B 0xe50 +#define rRx_IQK_Tone_B 0xe54 +#define rTx_IQK_PI_B 0xe58 +#define rRx_IQK_PI_B 0xe5c +#define rIQK_AGC_Cont 0xe60 + +#define rBlue_Tooth 0xe6c +#define rRx_Wait_CCA 0xe70 +#define rTx_CCK_RFON 0xe74 +#define rTx_CCK_BBON 0xe78 +#define rTx_OFDM_RFON 0xe7c +#define rTx_OFDM_BBON 0xe80 +#define rTx_To_Rx 0xe84 +#define rTx_To_Tx 0xe88 +#define rRx_CCK 0xe8c + +#define rTx_Power_Before_IQK_A 0xe94 +#define rTx_Power_After_IQK_A 0xe9c + +#define rRx_Power_Before_IQK_A 0xea0 +#define rRx_Power_Before_IQK_A_2 0xea4 +#define rRx_Power_After_IQK_A 0xea8 +#define rRx_Power_After_IQK_A_2 0xeac + +#define rTx_Power_Before_IQK_B 0xeb4 +#define rTx_Power_After_IQK_B 0xebc + +#define rRx_Power_Before_IQK_B 0xec0 +#define rRx_Power_Before_IQK_B_2 0xec4 +#define rRx_Power_After_IQK_B 0xec8 +#define rRx_Power_After_IQK_B_2 0xecc + +#define rRx_OFDM 0xed0 +#define rRx_Wait_RIFS 0xed4 +#define rRx_TO_Rx 0xed8 +#define rStandby 0xedc +#define rSleep 0xee0 +#define rPMPD_ANAEN 0xeec + +// +// 7. RF Register 0x00-0x2E (RF 8256) +// RF-0222D 0x00-3F +// +//Zebra1 +#define rZebra1_HSSIEnable 0x0 // Useless now +#define rZebra1_TRxEnable1 0x1 +#define rZebra1_TRxEnable2 0x2 +#define rZebra1_AGC 0x4 +#define rZebra1_ChargePump 0x5 +#define rZebra1_Channel 0x7 // RF channel switch + +//#endif +#define rZebra1_TxGain 0x8 // Useless now +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb +#define rZebra1_RxHPFCorner 0xc + +//Zebra4 +#define rGlobalCtrl 0 // Useless now +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 + +//RTL8258 +#define rRTL8258_TxLPF 0x11 // Useless now +#define rRTL8258_RxLPF 0x13 +#define rRTL8258_RSSILPF 0xa + +// +// RL6052 Register definition +// +#define RF_AC 0x00 // + +#define RF_IQADJ_G1 0x01 // +#define RF_IQADJ_G2 0x02 // +#define RF_BS_PA_APSET_G1_G4 0x03 +#define RF_BS_PA_APSET_G5_G8 0x04 +#define RF_POW_TRSW 0x05 // + +#define RF_GAIN_RX 0x06 // +#define RF_GAIN_TX 0x07 // + +#define RF_TXM_IDAC 0x08 // +#define RF_IPA_G 0x09 // +#define RF_TXBIAS_G 0x0A +#define RF_TXPA_AG 0x0B +#define RF_IPA_A 0x0C // +#define RF_TXBIAS_A 0x0D +#define RF_BS_PA_APSET_G9_G11 0x0E +#define RF_BS_IQGEN 0x0F // + +#define RF_MODE1 0x10 // +#define RF_MODE2 0x11 // + +#define RF_RX_AGC_HP 0x12 // +#define RF_TX_AGC 0x13 // +#define RF_BIAS 0x14 // +#define RF_IPA 0x15 // +#define RF_TXBIAS 0x16 // +#define RF_POW_ABILITY 0x17 // +#define RF_MODE_AG 0x18 // +#define rRfChannel 0x18 // RF channel and BW switch +#define RF_CHNLBW 0x18 // RF channel and BW switch +#define RF_TOP 0x19 // + +#define RF_RX_G1 0x1A // +#define RF_RX_G2 0x1B // + +#define RF_RX_BB2 0x1C // +#define RF_RX_BB1 0x1D // + +#define RF_RCK1 0x1E // +#define RF_RCK2 0x1F // + +#define RF_TX_G1 0x20 // +#define RF_TX_G2 0x21 // +#define RF_TX_G3 0x22 // + +#define RF_TX_BB1 0x23 // + +#define RF_T_METER 0x24 // + +#define RF_SYN_G1 0x25 // RF TX Power control +#define RF_SYN_G2 0x26 // RF TX Power control +#define RF_SYN_G3 0x27 // RF TX Power control +#define RF_SYN_G4 0x28 // RF TX Power control +#define RF_SYN_G5 0x29 // RF TX Power control +#define RF_SYN_G6 0x2A // RF TX Power control +#define RF_SYN_G7 0x2B // RF TX Power control +#define RF_SYN_G8 0x2C // RF TX Power control + +#define RF_RCK_OS 0x30 // RF TX PA control + +#define RF_TXPA_G1 0x31 // RF TX PA control +#define RF_TXPA_G2 0x32 // RF TX PA control +#define RF_TXPA_G3 0x33 // RF TX PA control + +#define RF_MIXER_BW 0x87 // RF Mixer bandwidth + +// +//Bit Mask +// +// 1. Page1(0x100) +#define bBBResetB 0x100 // Useless now? +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 + +#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) + +// 2. Page8(0x800) +#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 + +#define bOFDMRxADCPhase 0x10000 // Useless now +#define bOFDMTxDACPhase 0x40000 +#define bXATxAGC 0x3f + +#define bAntennaSelect 0x0300 + +#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 + +#define bPAStart 0xf0000000 // Useless now +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +#define bPAEnd 0xf //Reg0x814 +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +#define bCCAMask 0x000000f0 //T2R +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +#define bContTxHSSI 0x400 //chane gain at continue Tx +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 + +#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 +#define b3WireAddressLength 0x400 + +#define b3WireRFPowerDown 0x1 // Useless now +//#define bHWSISelect 0x8 +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +#define bRFSI_3Wire 0xf + +#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW + +#define bRFSI_TRSW 0x20 // Useless now +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 +#define bHTSIG2_NumOfHTLTF 0x300 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 + +#define bLSSIReadAddress 0x7f800000 // T65 RF + +#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal + +#define bLSSIReadBackData 0xfffff // T65 RF + +#define bLSSIReadOKFlag 0x1000 // Useless now +#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 + +#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ + +#define b80MClkDelay 0x18000000 // Useless +#define bAFEWatchDogEnable 0x20000000 + +#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap +#define bXtalCap23 0x3 +#define bXtalCap92x 0x0f000000 +#define bXtalCap 0x0f000000 + +#define bIntDifClkEnable 0x400 // Useless +#define bExtSigClkEnable 0x800 +#define bBandgapMbiasPowerUp 0x10000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 +#define bCCKRxAGCFormat 0x200 +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + +// 3. Page9(0x900) +#define bOFDMTxSC 0x30000000 // Useless +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +#define bDebugPage 0xfff //reset debug page and also HWord, LWord +#define bDebugItem 0xff //reset debug page and LWord +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + +// 4. PageA(0xA00) +#define bCCKBBMode 0x3 // Useless +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 + +#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch + +#define bCCKScramble 0x8 // Useless +#define bCCKAntDiversity 0x8000 +#define bCCKCarrierRecovery 0x4000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 +#define bCCKTxDACPhase 0x4 +#define bCCKRxADCPhase 0x20000000 //r_rx_clk +#define bCCKr_cp_mode0 0x0100 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +#define bCCKRxRFSettle 0x1f //AGCsamp_dly +#define bCCKFixedRxAGC 0x8000 +//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 +#define bCCKRxAGCReportType 0x0300 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCSatLevel 0x1f000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 +#define bCCKRxRxReport_SQLoss 0x20000000 +#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Lockedbit 0x08000000 +#define bCCKRxReport_RateError 0x04000000 +#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxFACounterLower 0xff +#define bCCKRxFACounterUpper 0xff000000 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 +#define bCCKRxFalseAlarmEnable 0x8000 +#define bCCKFACounterFreeze 0x4000 +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + +// 5. PageC(0xC00) +#define bNumOfSTF 0x3 // Useless +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +#define bRSSI_H 0x7f0000 //the threshold for high power +#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +//#define bRxMF_Hold 0x3800 +#define bRxPD_Delay_TH 0x8000 +#define bRxProcess_Delay 0xf0000 +#define bRxSearchrange_GI2_Early 0x700000 +#define bRxFrame_Guard_Counter_L 0x3800000 +#define bRxSGI_Guard_L 0xc000000 +#define bRxSGI_Search_L 0x30000000 +#define bRxSGI_TH 0xc0000000 +#define bDFSCnt0 0xff +#define bDFSCnt1 0xff00 +#define bDFSFlag 0xf0000 +#define bMFWeightSum 0x300000 +#define bMinIdxTH 0x7f000000 +#define bDAFormat 0x40000 +#define bTxChEmuEnable 0x01000000 +#define bTRSWIsolation_A 0x7f +#define bTRSWIsolation_B 0x7f00 +#define bTRSWIsolation_C 0x7f0000 +#define bTRSWIsolation_D 0x7f000000 +#define bExtLNAGain 0x7c00 + +// 6. PageE(0xE00) +#define bSTBCEn 0x4 // Useless +#define bAntennaMapping 0x10 +#define bNss 0x20 +#define bCFOAntSumD 0x200 +#define bPHYCounterReset 0x8000000 +#define bCFOReportGet 0x4000000 +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 +//#define bRxPath1 0x01 +//#define bRxPath2 0x02 +//#define bRxPath3 0x04 +//#define bRxPath4 0x08 +//#define bTxPath1 0x10 +//#define bTxPath2 0x20 +#define bHTDetect 0x100 +#define bCFOEn 0x10000 +#define bCFOValue 0xfff00000 +#define bSigTone_Re 0x3f +#define bSigTone_Im 0x7f00 +#define bCounter_CCA 0xffff +#define bCounter_ParityFail 0xffff0000 +#define bCounter_RateIllegal 0xffff +#define bCounter_CRC8Fail 0xffff0000 +#define bCounter_MCSNoSupport 0xffff +#define bCounter_FastSync 0xffff +#define bShortCFO 0xfff +#define bShortCFOTLength 12 //total +#define bShortCFOFLength 11 //fraction +#define bLongCFO 0x7ff +#define bLongCFOTLength 11 +#define bLongCFOFLength 11 +#define bTailCFO 0x1fff +#define bTailCFOTLength 13 +#define bTailCFOFLength 12 +#define bmax_en_pwdB 0xffff +#define bCC_power_dB 0xffff0000 +#define bnoise_pwdB 0xffff +#define bPowerMeasTLength 10 +#define bPowerMeasFLength 3 +#define bRx_HT_BW 0x1 +#define bRxSC 0x6 +#define bRx_HT 0x8 +#define bNB_intf_det_on 0x1 +#define bIntf_win_len_cfg 0x30 +#define bNB_Intf_TH_cfg 0x1c0 +#define bRFGain 0x3f +#define bTableSel 0x40 +#define bTRSW 0x80 +#define bRxSNR_A 0xff +#define bRxSNR_B 0xff00 +#define bRxSNR_C 0xff0000 +#define bRxSNR_D 0xff000000 +#define bSNREVMTLength 8 +#define bSNREVMFLength 1 +#define bCSI1st 0xff +#define bCSI2nd 0xff00 +#define bRxEVM1st 0xff0000 +#define bRxEVM2nd 0xff000000 +#define bSIGEVM 0xff +#define bPWDB 0xff00 +#define bSGIEN 0x10000 + +#define bSFactorQAM1 0xf // Useless +#define bSFactorQAM2 0xf0 +#define bSFactorQAM3 0xf00 +#define bSFactorQAM4 0xf000 +#define bSFactorQAM5 0xf0000 +#define bSFactorQAM6 0xf0000 +#define bSFactorQAM7 0xf00000 +#define bSFactorQAM8 0xf000000 +#define bSFactorQAM9 0xf0000000 +#define bCSIScheme 0x100000 + +#define bNoiseLvlTopSet 0x3 // Useless +#define bChSmooth 0x4 +#define bChSmoothCfg1 0x38 +#define bChSmoothCfg2 0x1c0 +#define bChSmoothCfg3 0xe00 +#define bChSmoothCfg4 0x7000 +#define bMRCMode 0x800000 +#define bTHEVMCfg 0x7000000 + +#define bLoopFitType 0x1 // Useless +#define bUpdCFO 0x40 +#define bUpdCFOOffData 0x80 +#define bAdvUpdCFO 0x100 +#define bAdvTimeCtrl 0x800 +#define bUpdClko 0x1000 +#define bFC 0x6000 +#define bTrackingMode 0x8000 +#define bPhCmpEnable 0x10000 +#define bUpdClkoLTF 0x20000 +#define bComChCFO 0x40000 +#define bCSIEstiMode 0x80000 +#define bAdvUpdEqz 0x100000 +#define bUChCfg 0x7000000 +#define bUpdEqz 0x8000000 + +//Rx Pseduo noise +#define bRxPesudoNoiseOn 0x20000000 // Useless +#define bRxPesudoNoise_A 0xff +#define bRxPesudoNoise_B 0xff00 +#define bRxPesudoNoise_C 0xff0000 +#define bRxPesudoNoise_D 0xff000000 +#define bPesudoNoiseState_A 0xffff +#define bPesudoNoiseState_B 0xffff0000 +#define bPesudoNoiseState_C 0xffff +#define bPesudoNoiseState_D 0xffff0000 + +//7. RF Register +//Zebra1 +#define bZebra1_HSSIEnable 0x8 // Useless +#define bZebra1_TRxControl 0xc00 +#define bZebra1_TRxGainSetting 0x07f +#define bZebra1_RxCorner 0xc00 +#define bZebra1_TxChargePump 0x38 +#define bZebra1_RxChargePump 0x7 +#define bZebra1_ChannelNum 0xf80 +#define bZebra1_TxLPFBW 0x400 +#define bZebra1_RxLPFBW 0x600 + +//Zebra4 +#define bRTL8256RegModeCtrl1 0x100 // Useless +#define bRTL8256RegModeCtrl0 0x40 +#define bRTL8256_TxLPFBW 0x18 +#define bRTL8256_RxLPFBW 0x600 + +//RTL8258 +#define bRTL8258_TxLPFBW 0xc // Useless +#define bRTL8258_RxLPFBW 0xc00 +#define bRTL8258_RSSILPFBW 0xc0 + + +// +// Other Definition +// + +//byte endable for sb_write +#define bByte0 0x1 // Useless +#define bByte1 0x2 +#define bByte2 0x4 +#define bByte3 0x8 +#define bWord0 0x3 +#define bWord1 0xc +#define bDWord 0xf + +//for PutRegsetting & GetRegSetting BitMask +#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff +#define bMask12Bits 0xfff +#define bMaskH4Bits 0xf0000000 +#define bMaskOFDM_D 0xffc00000 +#define bMaskCCK 0x3f3f3f3f + +//for PutRFRegsetting & GetRFRegSetting BitMask +//#define bMask12Bits 0xfffff // RF Reg mask bits +//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF +#define bRFRegOffsetMask 0xfffff + +#define bEnable 0x1 // Useless +#define bDisable 0x0 + +#define LeftAntenna 0x0 // Useless +#define RightAntenna 0x1 + +#define tCheckTxStatus 500 //500ms // Useless +#define tUpdateRxCounter 100 //100ms + +#define rateCCK 0 // Useless +#define rateOFDM 1 +#define rateHT 2 + +//define Register-End +#define bPMAC_End 0x1ff // Useless +#define bFPGAPHY0_End 0x8ff +#define bFPGAPHY1_End 0x9ff +#define bCCKPHY0_End 0xaff +#define bOFDMPHY0_End 0xcff +#define bOFDMPHY1_End 0xdff + +//define max debug item in each debug page +//#define bMaxItem_FPGA_PHY0 0x9 +//#define bMaxItem_FPGA_PHY1 0x3 +//#define bMaxItem_PHY_11B 0x16 +//#define bMaxItem_OFDM_PHY0 0x29 +//#define bMaxItem_OFDM_PHY1 0x0 + +#define bPMACControl 0x0 // Useless +#define bWMACControl 0x1 +#define bWNICControl 0x2 + +#define PathA 0x0 // Useless +#define PathB 0x1 +#define PathC 0x2 +#define PathD 0x3 + +/*--------------------------Define Parameters-------------------------------*/ + + +#endif //__INC_HAL8192SPHYREG_H + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8195APhyCfg.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8195APhyCfg.h new file mode 100644 index 0000000..c8e7b4c --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8195APhyCfg.h @@ -0,0 +1,186 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_HAL8195APHYCFG_H__ +#define __INC_HAL8195APHYCFG_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define LOOP_LIMIT 5 +#define MAX_STALL_TIME 50 //us +#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) +#define MAX_TXPWR_IDX_NMODE_92S 63 +#define Reset_Cnt_Limit 3 + +#if defined (CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI) +#define MAX_AGGR_NUM 0x0B +#else +#define MAX_AGGR_NUM 0x07 +#endif // CONFIG_PCI_HCI + + +/*--------------------------Define Parameters End-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ + +/* BB/RF related */ + +typedef struct _R_ANTENNA_SELECT_OFDM{ + u32 r_tx_antenna:4; + u32 r_ant_l:4; + u32 r_ant_non_ht:4; + u32 r_ant_ht1:4; + u32 r_ant_ht2:4; + u32 r_ant_ht_s1:4; + u32 r_ant_non_ht_s1:4; + u32 OFDM_TXSC:2; + u32 Reserved:2; +}R_ANTENNA_SELECT_OFDM; + +typedef struct _R_ANTENNA_SELECT_CCK{ + u8 r_cckrx_enable_2:2; + u8 r_cckrx_enable:2; + u8 r_ccktx_enable:4; +}R_ANTENNA_SELECT_CCK; + +/*------------------------------Define structure End----------------------------*/ + +/*--------------------------Exported Function prototype---------------------*/ + +u32 +PHY_QueryBBReg_8195A( + IN PADAPTER Adapter, + IN u32 RegAddr, + IN u32 BitMask + ); + +VOID +PHY_SetBBReg_8195A( + IN PADAPTER Adapter, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data + ); + +u32 +PHY_QueryRFReg_8195A( + IN PADAPTER Adapter, + IN u32 eRFPath, + IN u32 RegAddr, + IN u32 BitMask + ); + +VOID +PHY_SetRFReg_8195A( + IN PADAPTER Adapter, + IN u32 eRFPath, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data + ); + +u32 PHY_QueryBBReg_8195A_Safe( + IN PADAPTER Adapter, + IN u32 RegAddr, + IN u32 BitMask +); + +VOID PHY_SetBBReg_8195A_Safe( + IN PADAPTER Adapter, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data +); + +#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) PHY_QueryBBReg_8195A_Safe((Adapter), (RegAddr), (BitMask)) +#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) PHY_SetBBReg_8195A_Safe((Adapter), (RegAddr), (BitMask), (Data)) +#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) PHY_QueryRFReg_8195A((Adapter), (eRFPath), (RegAddr), (BitMask)) +#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) PHY_SetRFReg_8195A((Adapter), (eRFPath), (RegAddr), (BitMask), (Data)) + +#define PHY_SetMacReg PHY_SetBBReg +#define PHY_QueryMacReg PHY_QueryBBReg +/* MAC/BB/RF HAL config */ +int PHY_BBConfig8195A(PADAPTER Adapter ); + +int PHY_RFConfig8195A(PADAPTER Adapter ); + +s32 PHY_MACConfig8195A(PADAPTER padapter); + +#ifdef CONFIG_SUDO_PHY_SETTING +int PHY_SudoPhyConfig8195A(PADAPTER Adapter); +#endif + +int +PHY_ConfigRFWithParaFile_8195A( + IN PADAPTER Adapter, + IN u8* pFileName, + RF_PATH eRFPath +); +int +PHY_ConfigRFWithHeaderFile_8723B( + IN PADAPTER Adapter, + RF_PATH eRFPath +); + +u8 +PHY_GetTxPowerIndex_8195A( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel + ); + +VOID +PHY_SetTxPowerLevel8195A( + IN PADAPTER Adapter, + IN u8 channel + ); + +VOID +PHY_SetBWMode8195A( + IN PADAPTER Adapter, + IN CHANNEL_WIDTH Bandwidth, // 20M or 40M + IN unsigned char Offset // Upper, Lower, or Don't care +); + +VOID +PHY_SwChnl8195A( // Call after initialization + IN PADAPTER Adapter, + IN u8 channel + ); + +VOID +PHY_SetSwChnlBWMode8195A( + IN PADAPTER Adapter, + IN u8 channel, + IN CHANNEL_WIDTH Bandwidth, + IN u8 Offset40, + IN u8 Offset80 +); + +VOID PHY_SetRFPathSwitch_8723B( + IN PADAPTER pAdapter, + IN BOOLEAN bMain + ); + +/*--------------------------Exported Function prototype End---------------------*/ + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8195APhyReg.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8195APhyReg.h new file mode 100644 index 0000000..1ae9e30 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8195APhyReg.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_HAL8195APHYREG_H__ +#define __INC_HAL8195APHYREG_H__ + +// +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// Page1(0x100) +// +#define rPMAC_Reset 0x100 + +// +// Page8(0x800) +// +#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? +#define rFPGA0_TxInfo 0x804 // Status report?? +#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? +#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c +#define rTxAGC_B_Rate18_06 0x830 +#define rTxAGC_B_Rate54_24 0x834 +#define rTxAGC_B_CCK1_55_Mcs32 0x838 +#define rTxAGC_B_Mcs03_Mcs00 0x83c +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 +#define rTxAGC_B_Mcs07_Mcs04 0x848 +#define rTxAGC_B_Mcs11_Mcs08 0x84c +#define rFPGA0_XCD_SwitchControl 0x85c +#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch +#define rFPGA0_XB_RFInterfaceOE 0x864 +#define rTxAGC_B_CCK11_A_CCK2_11 0x86c +#define rTxAGC_B_Mcs15_Mcs12 0x868 +#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control +#define rFPGA0_XCD_RFInterfaceSW 0x874 +#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter +#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback +#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac +#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback +#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback + +// +// Page9(0x900) +// +#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? +#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? +#define rS0S1_PathSwitch 0x948 +#define rRXDFIR_Filter 0x954 + +// +// PageA(0xA00) +// +// Set Control channel to upper or lower. These settings are required only for 40MHz +#define rCCK0_System 0xa00 +#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI + +// +// PageB(0xB00) +// +#define rPdp_AntA 0xb00 +#define rPdp_AntA_4 0xb04 +#define rPdp_AntA_8 0xb08 +#define rPdp_AntA_C 0xb0c +#define rPdp_AntA_10 0xb10 +#define rPdp_AntA_14 0xb14 +#define rPdp_AntA_18 0xb18 +#define rPdp_AntA_1C 0xb1c +#define rPdp_AntA_20 0xb20 +#define rPdp_AntA_24 0xb24 + +#define rConfig_Pmpd_AntA 0xb28 +#define rConfig_ram64x16 0xb2c + +#define rBndA 0xb30 +#define rHssiPar 0xb34 + +#define rConfig_AntA 0xb68 +#define rConfig_AntB 0xb6c + +#define rPdp_AntB 0xb70 +#define rPdp_AntB_4 0xb74 +#define rPdp_AntB_8 0xb78 +#define rPdp_AntB_C 0xb7c +#define rPdp_AntB_10 0xb80 +#define rPdp_AntB_14 0xb84 +#define rPdp_AntB_18 0xb88 +#define rPdp_AntB_1C 0xb8c +#define rPdp_AntB_20 0xb90 +#define rPdp_AntB_24 0xb94 + +#define rConfig_Pmpd_AntB 0xb98 + +#define rBndB 0xba0 + +#define rAPK 0xbd8 +#define rPm_Rx0_AntA 0xbdc +#define rPm_Rx1_AntA 0xbe0 +#define rPm_Rx2_AntA 0xbe4 +#define rPm_Rx3_AntA 0xbe8 +#define rPm_Rx0_AntB 0xbec +#define rPm_Rx1_AntB 0xbf0 +#define rPm_Rx2_AntB 0xbf4 +#define rPm_Rx3_AntB 0xbf8 + +// +// PageC(0xC00) +// +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_XARxAFE 0xc10 // RxIQ DC offset, Rx digital filter, DC notch filter +#define rOFDM0_XARxIQImbalance 0xc14 // RxIQ imblance matrix +#define rOFDM0_XBRxIQImbalance 0xc1c +#define rOFDM0_RxDetector1 0xc30 // PD,BW & SBD // DM tune init gain +#define rOFDM0_ECCAThreshold 0xc4c // energy CCA +#define rOFDM0_XAAGCCore1 0xc50 // DIG +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxAFE 0xc9c +#define rOFDM0_RxIQExtAnta 0xca0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 // Double ADC + +// +// PageD(0xD00) +// +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 + +// +// PageE(0xE00) +// +#define rTxAGC_A_Rate18_06 0xe00 +#define rTxAGC_A_Rate54_24 0xe04 +#define rTxAGC_A_CCK1_Mcs32 0xe08 +#define rTxAGC_A_Mcs03_Mcs00 0xe10 +#define rTxAGC_A_Mcs07_Mcs04 0xe14 +#define rTxAGC_A_Mcs11_Mcs08 0xe18 +#define rTxAGC_A_Mcs15_Mcs12 0xe1c +#define rFPGA0_IQK 0xe28 +#define rTx_IQK_Tone_A 0xe30 +#define rRx_IQK_Tone_A 0xe34 +#define rTx_IQK_PI_A 0xe38 +#define rRx_IQK_PI_A 0xe3c +#define rTx_IQK 0xe40 +#define rRx_IQK 0xe44 +#define rIQK_AGC_Pts 0xe48 +#define rIQK_AGC_Rsp 0xe4c +#define rTx_IQK_Tone_B 0xe50 +#define rRx_IQK_Tone_B 0xe54 +#define rTx_IQK_PI_B 0xe58 +#define rRx_IQK_PI_B 0xe5c +#define rIQK_AGC_Cont 0xe60 +#define rBlue_Tooth 0xe6c +#define rRx_Wait_CCA 0xe70 // Rx ADC clock +#define rTx_CCK_RFON 0xe74 +#define rTx_CCK_BBON 0xe78 +#define rTx_OFDM_RFON 0xe7c +#define rTx_OFDM_BBON 0xe80 +#define rTx_To_Rx 0xe84 +#define rTx_To_Tx 0xe88 +#define rRx_CCK 0xe8c +#define rTx_Power_Before_IQK_A 0xe94 +#define rTx_Power_After_IQK_A 0xe9c +#define rRx_Power_Before_IQK_A_2 0xea4 +#define rRx_Power_After_IQK_A_2 0xeac +#define rTx_Power_Before_IQK_B 0xeb4 +#define rTx_Power_After_IQK_B 0xebc +#define rRx_Power_Before_IQK_B 0xec0 +#define rRx_Power_Before_IQK_B_2 0xec4 +#define rRx_Power_After_IQK_B 0xec8 +#define rRx_Power_After_IQK_B_2 0xecc +#define rRx_OFDM 0xed0 +#define rRx_Wait_RIFS 0xed4 +#define rRx_TO_Rx 0xed8 +#define rStandby 0xedc +#define rSleep 0xee0 +#define rPMPD_ANAEN 0xeec + + +//for PutRegsetting & GetRegSetting BitMask +#define bMaskH3Bytes 0xffffff00 + +// +// RL6052 Register definition +// +#define RF_AC 0x00 // +#define RF_TXM_IDAC 0x08 // +#define RF_CHNLBW 0x18 // RF channel and BW switch +#define RF_RCK_OS 0x30 // RF TX PA control +#define RF_TXPA_G1 0x31 // RF TX PA control +#define RF_TXPA_G2 0x32 // RF TX PA control +#define RF_WE_LUT 0xEF + +// +//Bit Mask +// +// 1. Page1(0x100) +#define bBBResetB 0x100 // Useless now? + +// 2. Page8(0x800) +#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 +#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 +#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 +#define b3WireAddressLength 0x400 +#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW +#define bLSSIReadAddress 0x7f800000 // T65 RF +#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal +#define bLSSIReadBackData 0xfffff // T65 RF + +// 3. Page9(0x900) + +// 4. PageA(0xA00) +#define bCCKBBMode 0x3 +#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch +#define bCCKScramble 0x8 +#define bCCKTxRate 0x3000 + + +// 5. PageC(0xC00) + +// 6. PageE(0xE00) +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 + +// +// Other Definition +// + +//for PutRegsetting & GetRegSetting BitMask +#define bMaskByte0 0xff +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff +#define bMask12Bits 0xfff +#define bMaskH4Bits 0xf0000000 + +#define bEnable 0x1 +#define bDisable 0x0 + + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8195APwrSeq.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8195APwrSeq.h new file mode 100644 index 0000000..2de0a12 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8195APwrSeq.h @@ -0,0 +1,397 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef REALTEK_POWER_SEQUENCE_8195A +#define REALTEK_POWER_SEQUENCE_8195A + +#include "HalPwrSeqCmd.h" + +/* + Check document WM-20130111-JackieLau-RTL8723B_Power_Architecture v02.vsd + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transision from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END +*/ +#define RTL8195A_TRANS_CARDEMU_TO_ACT_STEPS 4 +#define RTL8195A_TRANS_ACT_TO_CARDEMU_STEPS 4 +#define RTL8195A_TRANS_CARDEMU_TO_SUS_STEPS 7 +#define RTL8195A_TRANS_SUS_TO_CARDEMU_STEPS 15 +#define RTL8195A_TRANS_CARDEMU_TO_PDN_STEPS 15 +#define RTL8195A_TRANS_PDN_TO_CARDEMU_STEPS 15 +#define RTL8195A_TRANS_ACT_TO_LPS_STEPS 15 +#define RTL8195A_TRANS_LPS_TO_ACT_STEPS 15 +#define RTL8195A_TRANS_ACT_TO_SWLPS_STEPS 22 +#define RTL8195A_TRANS_SWLPS_TO_ACT_STEPS 15 +#define RTL8195A_TRANS_END_STEPS 1 +//1TODO:chris +#if 1 +#define RTL8195A_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ + {0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ + + +#define RTL8195A_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1|BIT2), 0},/*0x04[24:26] = 0 turn off RF*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1), 0},/*0x04[16:17] = 0 BB reset*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x20[1] = 1 turn off MAC by HW state machine*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x20[1] = 0 polling until return 0 to disable*/ \ + +#define RTL8195A_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8195A_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ + +#define RTL8195A_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + +#define RTL8195A_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + + +#define RTL8195A_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ + +#define RTL8195A_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ + +#define RTL8195A_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ + {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ + + +#define RTL8195A_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ + {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + + + #define RTL8195A_TRANS_ACT_TO_SWLPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*enable 32 K source*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*disable security engine*/ \ + {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x40},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TSF*/ \ + {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*Reset MCUFWDL register*/ \ + {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \ + {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},/*Reset CPU IO Wrapper*/ \ + {0x0287, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*polling RXFF packet number = 0 */ \ + {0x0286, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA idle */ \ + {0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Clear FW RPWM interrupt */\ + {0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Set FW RPWM interrupt source*/\ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to 32K*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF stable*/\ + {0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Set FW LPS*/ \ + {0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/*polling FW LPS ready */ + + +#define RTL8195A_TRANS_SWLPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0},/*switch TSF to 32K*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1, enable security engine*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x09}, /*. reset MAC rx state machine*/\ + {0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x86}, /*. reset MAC rx state machine*/\ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/ \ + {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \ + {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/ \ + {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/ \ + {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + + + +#else + +#define RTL8723B_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ + {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ + {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ + {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \ + {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \ + {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ + {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\ + {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ + {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ + {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\ + {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\ + {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/ + +#define RTL8723B_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ + {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\ + {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ + {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/ \ + {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \ + + +#define RTL8723B_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8723B_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ + +#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ + {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ + + +#define RTL8723B_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ + +#define RTL8723B_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ + +#define RTL8723B_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ + {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ + + +#define RTL8723B_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ + {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + + + #define RTL8723B_TRANS_ACT_TO_SWLPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*enable 32 K source*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*disable security engine*/ \ + {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x40},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TSF*/ \ + {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*Reset MCUFWDL register*/ \ + {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \ + {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},/*Reset CPU IO Wrapper*/ \ + {0x0287, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*polling RXFF packet number = 0 */ \ + {0x0286, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA idle */ \ + {0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Clear FW RPWM interrupt */\ + {0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Set FW RPWM interrupt source*/\ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to 32K*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF stable*/\ + {0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Set FW LPS*/ \ + {0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/*polling FW LPS ready */ + + +#define RTL8723B_TRANS_SWLPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0},/*switch TSF to 32K*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1, enable security engine*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x09}, /*. reset MAC rx state machine*/\ + {0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x86}, /*. reset MAC rx state machine*/\ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/ \ + {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \ + {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/ \ + {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/ \ + {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + + +#endif + + + +#define RTL8195A_TRANS_END \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // + + +extern WLAN_PWR_CFG rtl8195A_power_on_flow[RTL8195A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8195A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8195A_radio_off_flow[RTL8195A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8195A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8195A_card_disable_flow[RTL8195A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8195A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8195A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8195A_card_enable_flow[RTL8195A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8195A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8195A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8195A_suspend_flow[RTL8195A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8195A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8195A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8195A_resume_flow[RTL8195A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8195A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8195A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8195A_hwpdn_flow[RTL8195A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8195A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8195A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8195A_enter_lps_flow[RTL8195A_TRANS_ACT_TO_LPS_STEPS+RTL8195A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8195A_leave_lps_flow[RTL8195A_TRANS_LPS_TO_ACT_STEPS+RTL8195A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8195A_enter_swlps_flow[RTL8195A_TRANS_ACT_TO_SWLPS_STEPS+RTL8195A_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8195A_leave_swlps_flow[RTL8195A_TRANS_SWLPS_TO_ACT_STEPS+RTL8195A_TRANS_END_STEPS]; +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rom_Hal8195APhyCfg.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rom_Hal8195APhyCfg.h new file mode 100644 index 0000000..5dce5ce --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rom_Hal8195APhyCfg.h @@ -0,0 +1,56 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ROM_HAL8195APHYCFG_H__ +#define __ROM_HAL8195APHYCFG_H__ + +/*--------------------------Define Parameters-------------------------------*/ + +/*--------------------------Define Parameters End-------------------------------*/ + +/*------------------------------Define structure----------------------------*/ + +/*------------------------------Define structure End----------------------------*/ + +/*--------------------------Exported Function prototype---------------------*/ + +u32 +phy_CalculateBitShift( + u32 BitMask + ); + +u32 +PHY_QueryBBReg_8195A( + IN PADAPTER Adapter, + IN u32 RegAddr, + IN u32 BitMask + ); + +VOID +PHY_SetBBReg_8195A( + IN PADAPTER Adapter, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data + ); + +/*--------------------------Exported Function prototype End---------------------*/ + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_cmd.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_cmd.h new file mode 100644 index 0000000..3ef53e9 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_cmd.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8195A_CMD_H__ +#define __RTL8195A_CMD_H__ + +//---------------------------------------------------------------------------------------------------------// +//---------------------------------- H2C CMD DEFINITION ------------------------------------------------// +//---------------------------------------------------------------------------------------------------------// + +enum h2c_cmd_8195A{ + //Common Class: 000 + H2C_8195A_RSVD_PAGE = 0x00, + H2C_8195A_MEDIA_STATUS_RPT = 0x01, + H2C_8195A_SCAN_ENABLE = 0x02, + H2C_8195A_KEEP_ALIVE = 0x03, + H2C_8195A_DISCON_DECISION = 0x04, + H2C_8195A_PSD_OFFLOAD = 0x05, + H2C_8195A_AP_OFFLOAD = 0x08, + H2C_8195A_BCN_RSVDPAGE = 0x09, + H2C_8195A_PROBERSP_RSVDPAGE = 0x0A, + H2C_8195A_FCS_RSVDPAGE = 0x10, + H2C_8195A_FCS_INFO = 0x11, + + //PoweSave Class: 001 + H2C_8195A_SET_PWR_MODE = 0x20, + H2C_8195A_PS_TUNING_PARA = 0x21, + H2C_8195A_PS_TUNING_PARA2 = 0x22, + H2C_8195A_P2P_LPS_PARAM = 0x23, + H2C_8195A_P2P_PS_OFFLOAD = 0x24, + H2C_8195A_PS_SCAN_ENABLE = 0x25, + H2C_8195A_SAP_PS_ = 0x26, + H2C_8195A_INACTIVE_PS_ = 0x27, //Inactive_PS + H2C_8195A_FWLPS_IN_IPS_ = 0x28, + + + //Dynamic Mechanism Class: 010 + H2C_8195A_MACID_CFG = 0x40, + H2C_8195A_TXBF = 0x41, + H2C_8195A_RSSI_SETTING = 0x42, + H2C_8195A_AP_REQ_TXRPT = 0x43, + H2C_8195A_INIT_RATE_COLLECT = 0x44, + + //BT Class: 011 + H2C_8195A_B_TYPE_TDMA = 0x60, + H2C_8195A_BT_INFO = 0x61, + H2C_8195A_FORCE_BT_TXPWR = 0x62, + H2C_8195A_BT_IGNORE_WLANACT = 0x63, + H2C_8195A_DAC_SWING_VALUE = 0x64, + H2C_8195A_ANT_SEL_RSV = 0x65, + H2C_8195A_WL_OPMODE = 0x66, + H2C_8195A_BT_MP_OPER = 0x67, + H2C_8195A_BT_CONTROL = 0x68, + H2C_8195A_BT_WIFI_CTRL = 0x69, + H2C_8195A_BT_FW_PATCH = 0x6A, + + //WOWLAN Class: 100 + H2C_8195A_WOWLAN = 0x80, + H2C_8195A_REMOTE_WAKE_CTRL = 0x81, + H2C_8195A_AOAC_GLOBAL_INFO = 0x82, + H2C_8195A_AOAC_RSVD_PAGE = 0x83, + H2C_8195A_AOAC_RSVD_PAGE2 = 0x84, + H2C_8195A_D0_SCAN_OFFLOAD_INFO = 0x85, + H2C_8195A_D0_SCAN_OFFLOAD_CTRL = 0x86, + H2C_8195A_CHNL_SWITCH_OFFLOAD = 0x87, + + H2C_8195A_RESET_TSF = 0xC0, + H2C_8195A_BCN_IGNORE_EDCCA = 0xC2, + + H2C_8195A_MAXID, +}; + +#define H2C_8195A_RSVDPAGE_LOC_LEN 5 +#define H2C_8195A_MEDIA_STATUS_RPT_LEN 3 +#define H2C_8195A_KEEP_ALIVE_CTRL_LEN 2 +#define H2C_8195A_DISCON_DECISION_LEN 3 +//#define H2C_8195A_AP_OFFLOAD_LEN 3 +#define H2C_8195A_PWRMODE_LEN 11 +#define H2C_8195A_PSTUNEPARAM_LEN 4 +#define H2C_8195A_MACID_CFG_LEN 7 +#define H2C_8195A_BTMP_OPER_LEN 4 +#define H2C_8195A_WOWLAN_LEN 3 +#define H2C_8195A_REMOTE_WAKE_CTRL_LEN 1 +#define H2C_8195A_AOAC_GLOBAL_INFO_LEN 2 +#define H2C_8195A_AOAC_RSVDPAGE_LOC_LEN 7 +//#define H2C_8723B_SCAN_OFFLOAD_CTRL_LEN 4 +#define H2C_8195A_BT_FW_PATCH_LEN 6 +#define H2C_8195A_RSSI_SETTING_LEN 4 +#define H2C_8195A_AP_REQ_TXRPT_LEN 2 +#define H2C_8195A_FORCE_BT_TXPWR_LEN 3 +#define H2C_8195A_BCN_IGNORE_EDCCA_LEN 1 + + +#ifdef CONFIG_WOWLAN +#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 ) +#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5]) +#define cpIpAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3]) + +// +// ARP packet +// +// LLC Header +#define GET_ARP_PKT_LLC_TYPE(__pHeader) ReadEF2Byte( ((u8*)(__pHeader)) + 6) + +//ARP element +#define GET_ARP_PKT_OPERATION(__pHeader) ReadEF2Byte( ((u8*)(__pHeader)) + 6) +#define GET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr((u8*)(_val), ((u8*)(__pHeader))+8) +#define GET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr((u8*)(_val), ((u8*)(__pHeader))+14) +#define GET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr((u8*)(_val), ((u8*)(__pHeader))+18) +#define GET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr((u8*)(_val), ((u8*)(__pHeader))+24) + +#define SET_ARP_PKT_HW(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 0, __Value) +#define SET_ARP_PKT_PROTOCOL(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 2, __Value) +#define SET_ARP_PKT_HW_ADDR_LEN(__pHeader, __Value) WriteEF1Byte( ((u8*)(__pHeader)) + 4, __Value) +#define SET_ARP_PKT_PROTOCOL_ADDR_LEN(__pHeader, __Value) WriteEF1Byte( ((u8*)(__pHeader)) + 5, __Value) +#define SET_ARP_PKT_OPERATION(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 6, __Value) +#define SET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+8, (u8*)(_val)) +#define SET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+14, (u8*)(_val)) +#define SET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+18, (u8*)(_val)) +#define SET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+24, (u8*)(_val)) + +#define FW_WOWLAN_FUN_EN BIT(0) +#define FW_WOWLAN_PATTERN_MATCH BIT(1) +#define FW_WOWLAN_MAGIC_PKT BIT(2) +#define FW_WOWLAN_UNICAST BIT(3) +#define FW_WOWLAN_ALL_PKT_DROP BIT(4) +#define FW_WOWLAN_GPIO_ACTIVE BIT(5) +#define FW_WOWLAN_REKEY_WAKEUP BIT(6) +#define FW_WOWLAN_DEAUTH_WAKEUP BIT(7) + +#define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0) +#define FW_FW_PARSE_MAGIC_PKT BIT(1) + +#define FW_REMOTE_WAKE_CTRL_EN BIT(0) +#define FW_REALWOWLAN_EN BIT(5) + +#endif //CONFIG_WOWLAN + +//---------------------------------------------------------------------------------------------------------// +//---------------------------------- H2C CMD CONTENT --------------------------------------------------// +//---------------------------------------------------------------------------------------------------------// +//_RSVDPAGE_LOC_CMD_0x00 +#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8723B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8723B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) + +//_MEDIA_STATUS_RPT_PARM_CMD_0x01 +#define SET_8723B_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8723B_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8723B_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) + +//_KEEP_ALIVE_CMD_0x03 +#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8723B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) + +//_DISCONNECT_DECISION_CMD_0x04 +#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8723B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) + +// _PWR_MOD_CMD_0x20 +#define SET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_TDMA_SLOT_LEN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+7, 0, 8, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_TDMA_PERIOD_LEN_1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+8, 0, 8, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_TDMA_PERIOD_LEN_2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+9, 0, 8, __Value) +#define SET_8723B_H2CCMD_PWRMODE_PARM_TDMA_PERIOD_LEN_3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+10, 0, 8, __Value) + +#define GET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) + +// _PS_TUNE_PARAM_CMD_0x21 +#define SET_8723B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value) +#define SET_8723B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value) +#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) + +//_MACID_CFG_CMD_0x40 +#define SET_8723B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value) +#define SET_8723B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value) +#define SET_8723B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value) +#define SET_8723B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value) +#define SET_8723B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value) +#define SET_8723B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value) +#define SET_8723B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value) +#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) +#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) +#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value) +#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value) + +//_RSSI_SETTING_CMD_0x42 +#define SET_8723B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value) +#define SET_8723B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) + +// _AP_REQ_TXRPT_CMD_0x43 +#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) + +// _FORCE_BT_TXPWR_CMD_0x62 +#define SET_8723B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value) + +// _FORCE_BT_MP_OPER_CMD_0x67 +#define SET_8723B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_8723B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) +#define SET_8723B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) +#define SET_8723B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) + +// _BT_FW_PATCH_0x6A +#define SET_8723B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value) +#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) + +// _WoWLAN PARAM_CMD_0x80 +#define SET_8723B_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 7, __Value) +#define SET_8723B_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 7, 1, __Value) +#define SET_8723B_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) + +// _REMOTE_WAKEUP_CMD_0x81 +#define SET_8723B_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) +#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value) +#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 1, __Value) + +// AOAC_GLOBAL_INFO_0x82 +#define SET_8723B_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) + +// AOAC_RSVDPAGE_LOC_0x83 +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_REQ(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) +#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_NETWORK_LIST(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 8, __Value) + +//---------------------------------------------------------------------------------------------------------// +//------------------------------------------- Structure --------------------------------------------------// +//---------------------------------------------------------------------------------------------------------// +typedef struct _RSVDPAGE_LOC { + u8 LocProbeRsp; + u8 LocPsPoll; + u8 LocNullData; + u8 LocQosNull; + u8 LocBTQosNull; +#ifdef CONFIG_WOWLAN + u8 LocRemoteCtrlInfo; + u8 LocArpRsp; + u8 LocNbrAdv; + u8 LocGTKRsp; + u8 LocGTKInfo; + u8 LocProbeReq; + u8 LocNetList; +#endif //CONFIG_WOWLAN +} RSVDPAGE_LOC_8195A, *PRSVDPAGE_LOC_8195A; + + +//---------------------------------------------------------------------------------------------------------// +//---------------------------------- Function Statement --------------------------------------------------// +//---------------------------------------------------------------------------------------------------------// + +// host message to firmware cmd +void rtl8195a_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); +void rtl8195a_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); +#ifdef CONFIG_BT_COEXIST +void rtl8195a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(PADAPTER padapter); +#endif +void rtl8195a_set_rssi_cmd(PADAPTER padapter, u8 *param); +void rtl8195a_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8* arg, u8 rssi_level); +void rtl8195a_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); +//s32 rtl8723b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); +void rtl8195a_set_FwPsTuneParam_cmd(PADAPTER padapter); +void rtl8195a_set_FwMacIdConfig_cmd(_adapter* padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask); +void rtl8195a_set_FwMediaStatusRpt_cmd(PADAPTER padapter, u8 mstatus, u8 macid); +void rtl8195a_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); +void rtl8195a_download_rsvd_page(PADAPTER padapter, u8 mstatus); +#ifdef CONFIG_P2P +void rtl8195a_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); +#endif //CONFIG_P2P + +void CheckFwRsvdPageContent(PADAPTER padapter); + +#ifdef CONFIG_WOWLAN +void rtl8195a_set_wowlan_cmd(_adapter* padapter, u8 enable); +void SetFwRelatedForWoWLAN8195a(_adapter* padapter, u8 bHostIsGoingtoSleep); +#endif//CONFIG_WOWLAN + +void rtl8195a_set_FwPwrModeInIPS_cmd(PADAPTER padapter); + +#ifdef CONFIG_TSF_RESET_OFFLOAD +u8 rtl8195a_reset_tsf(_adapter *padapter, u8 reset_port); +#endif // CONFIG_TSF_RESET_OFFLOAD +s32 FillH2CCmd8195A(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); + +#define FillH2CCmd FillH2CCmd8195A +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_dm.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_dm.h new file mode 100644 index 0000000..3bafb95 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_dm.h @@ -0,0 +1,81 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8195A_DM_H__ +#define __RTL8195A_DM_H__ +enum{ + UP_LINK, + DOWN_LINK, +}; + +enum{ + LLT, + TXRPT, + RXBUFF, + TXBUFF, +}; + +//============================================================ +// Description: +// +// This file is for 8723B dynamic mechanism only +// +// +//============================================================ + +//0x8000: TXRPT:2K +//max macid : 128 +//TXRPT SIZE 16 bytes +//0x8800: Rate Mask:1K +//Ramask size 8bytes + + +#define DYNAMIC_FUNC_BT BIT(0) + + +#define REPORT_OFFSET 0x8100 +#define RAMASK_OFFSET 0x8900 +#define LLT_H_ADDR 0x650 +#define TXREPORT_H_ADDR 0x660 +#define RXBUFF_H_ADDR 0x670 +#define TXBUFF_H_ADDR 0x680 + + + +//============================================================ +// structure and define +//============================================================ + +//============================================================ +// function prototype +//============================================================ + +void rtl8195a_init_dm_priv(PADAPTER padapter); +void rtl8195a_deinit_dm_priv(PADAPTER padapter); + +void rtl8195a_InitHalDm(PADAPTER padapter); +void rtl8195a_HalDmWatchDog(PADAPTER padapter); +void rtl8195a_HalDmWatchDog_in_LPS(PADAPTER padapter); +void rtl8195a_hal_dm_in_lps(PADAPTER padapter); +u8 ReadTxrpt8(IN PADAPTER padapter, IN u8 Macid, IN u8 Offset); +VOID WriteTxrpt8(IN PADAPTER padapter, IN u8 Macid, IN u8 Offset, IN u8 Val); +BOOLEAN GetMediaStatusCommon(IN PADAPTER pAdapter, IN u8 macid); +VOID GetTxrptStatistic(IN PDM_ODM_T pDM_Odm, IN PODM_RA_INFO_T pRaInfo,IN u8 Reset_var); +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_led.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_led.h new file mode 100644 index 0000000..700e32f --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_led.h @@ -0,0 +1,35 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8195A_LED_H__ +#define __RTL8195A_LED_H__ + +#include +#include +#include + + +//================================================================================ +// Interface to manipulate LED objects. +//================================================================================ +void rtl8195a_InitSwLeds(PADAPTER padapter); +void rtl8195a_DeInitSwLeds(PADAPTER padapter); + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_pmu_cmd.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_pmu_cmd.h new file mode 100644 index 0000000..eb79ded --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_pmu_cmd.h @@ -0,0 +1,130 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8195A_PMU_CMD_H__ +#define __RTL8195A_PMU_CMD_H__ + +typedef enum _RT_MEDIA_STATUS{ + RT_MEDIA_DISCONNECT = 0, + RT_MEDIA_CONNECT = 1 +}RT_MEDIA_STATUS; + +typedef enum _H2C_CMD_ { + //1 Class1: Common + H2CID_RSVDPAGE = 0x00, + H2CID_JOININFO = 0x01, + H2CID_SCAN = 0x02, + H2CID_KEEP_ALIVE = 0x03, + H2CID_DISCONNECT_DECISION = 0x04, + H2CID_PSD_OFFLOAD = 0x05, + rsvd2 = 0x06, + rsvd3 = 0x07, + H2CID_AP_OFFLOAD = 0x08, + H2CID_BCN_RsvdPage = 0x09, + H2CID_Probersp_RsvdPage = 0x0A, + H2CID_AP_OFFLOAD_STAINFO = 0x0B, + + H2CID_FAST_CS_RSVDPAGE = 0x10, + H2CID_FAST_CHANNEL_SWITCH = 0x11, + H2CID_BB_GAIN_REPORT = 0x12, + H2CID_GPIO_CTRL = 0x13, + H2CID_HW_INFO = 0x14, + + //1 Class2: Power Save + H2CID_SETPWRMODE = 0x20, + H2CID_PSTURNINGPARM = 0x21, + H2CID_PSTURNINGPARM2 = 0x22, + H2CID_PSLPSPARM = 0x23, + H2CID_P2PPS_OFFLOAD = 0x24, + H2CID_PS_SCAN = 0x25, + H2CID_SAPPS = 0x26, + H2CID_INACTIVE_PS = 0x27, + H2CID_NOLINK_PS = 0x28, + + //1 Class3: Dynamic Mechaism + H2CID_MACID_CFG = 0x40, + H2CID_TxBF = 0x41, + H2CID_RSSI_SETTING = 0x42, + H2CID_AP_REQ_TXRPT = 0x43, + H2CID_INIT_RATE_COLLECT = 0x44, + H2CID_IQK_OFFLOAD = 0x45, + + //1 Class4: BT Coex + H2CID_B_TYPE_TDMA = 0x60, + H2CID_BT_INFO = 0x61, + H2CID_FORCE_BT_TXPWR = 0x62, + H2CID_BT_IGNORE_WLANACT = 0x63, + H2CID_DAC_SWING_VALUE = 0x64, + H2CID_ANT_SEL_REVERSE = 0x65, + H2CID_WL_OPMODE = 0x66, + H2CID_BT_MP_OPERATION = 0x67, + H2CID_BT_CONTROL = 0x68, + H2CID_BT_WIFICTRL = 0x69, + H2CID_BT_PATCH_DOWNLOAD = 0x6A, + H2CID_BT_SCO_eSCO_OPERATION = 0x6B, + H2CID_BT_Page_Scan_Interval = 0x6C, + H2CID_WL_Calibraion = 0x6D, + H2CID_GNT_BT_CTRL = 0x6E, + H2CID_BT_ONLY_TEST = 0x6F, + + //1 Class5: WOWLAN + H2CID_WoWLAN = 0x80, + H2CID_RemoteWakeCtrl = 0x81, + H2CID_AOAC_Global_info = 0x82, + H2CID_AOAC_Rsvdpage1 = 0x83, + H2CID_AOAC_Rsvdpage2 = 0x84, + H2CID_D0_Scan_offload_info = 0x85, + H2CID_D0_Scan_offload_ctrl = 0x86, + H2CID_Switch_channel = 0x87, + H2CID_AOAC_Rsvdpage3 = 0x88, + H2CID_GPIO_WF_Customize = 0x89, + H2CID_P2P_RsvdPage = 0x8A, + H2CID_P2P_Offload = 0x8B, + + //1 Class6: LTECOEX + H2CID_LTECOEX_EN = 0xA0, + H2CID_WLAN_High_Priority = 0xA1, + + //1 Class7: Patch + H2CID_TSF_RESET = 0xC0, + H2CID_BB_NHM = 0xC1, + H2CID_BCN_IGNORE_EDCCA = 0xC2, + + //1 Class8: Testing + H2CID_H2C2HLB = 0xE0 + +} H2C_CMD, *PH2C_CMD; + +typedef struct _H2CParam_JoinInfo_ { + BOOLEAN bConnected:1; + BOOLEAN bMacid_ind:1; + u8 rsvd:6; + u8 macid; + u8 macid_end; +}H2CParam_JoinInfo, *PH2CParam_JoinInfo; + +typedef struct _H2CParam_RsvdPage_ { + RSVDPAGE_LOC_8195A RsvdPageLoc; + u8 *ReservedPagePacket; + u32 TotalPacketLen; +} H2CParam_RsvdPage, *PH2CParam_RsvdPage; + +u32 H2CCmdCommon(PADAPTER padapter, u8 ElementID, u8 *pCmdBuffer); + +#endif //__RTL8195A_PMU_CMD_H__ \ No newline at end of file diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_pmu_task.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_pmu_task.h new file mode 100644 index 0000000..c44f33d --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_pmu_task.h @@ -0,0 +1,491 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8195A_PMU_TASK_H__ +#define __RTL8195A_PMU_TASK_H__ +#ifdef CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD +//BitMAPDefine +#define RATEADAPTIVE BIT0 +#define H2CEVENT BIT1 +#define C2HEVENT BIT2 +#define RATRYDONE BIT3 +#define REMOTEWAKEEVENT BIT4 +#define APOFFLOADEVENT BIT5 +#define MAILBOXEVENT BIT6 +#define SWTIMEREVENT BIT7 + +#define BBNHMEVENT BIT8 +#define DBGPKTEVENT BIT9 +#define SIDEBANDWoWLAN BIT10 + +#if 0 +#ifdef CONFIG_POWER_SAVING +#define BCNEARLY BIT11 +#define MTIBCNIVLEAR BIT12 +#define BCNRX BIT13 +#define RXBMD1 BIT14 +#define RXBMD0 BIT15 +#define RXUMD1 BIT16 +#define RXUMD0 BIT17 +#define TXPKTIN BIT18 +#define GTIMER6TO BIT19 +#define GTIMER7TO BIT20 +#endif //#ifdef CONFIG_POWER_SAVING +#endif + +//BT mailbox +#define SETDATA BIT2 +#define SETACK BIT1 +#define GETDATA BIT0 + +/*--------------------------Define -------------------------------------------*/ +#ifdef CONFIG_POWER_SAVING +#define MACID_CLIENT 0 +#endif //#ifdef CONFIG_POWER_SAVING + +/*------------------------------Define Enum-----------------------------------*/ +#ifdef CONFIG_POWER_SAVING + +//REGDUMP_FW_ERR0 +typedef enum _FW_ERR0_STATUS_ +{ + FES0_H2C_CMDID = BIT0, + FES0_H2C_PTR = BIT1, + FES0_BB_RW = BIT2, + FES0_TXPKT_TXPAUSE = BIT3, + FES0_TSF_STABLE = BIT4, + FES0_TXSM_STABLE = BIT5, + FES0_RPWM_STABLE = BIT6, + FES0_C2H_TIMEOUT_ERR = BIT7, + +}FW_ERR0_STATUS, *PFW_ERR0_STATUS; + + +//TxPauseReasonCode +typedef enum _TRPC_ { + TPRC_ISSUENULLDATA_1 = 0x26, + TPRC_ISSUENULLDATA_2 = 0x27, + TPRC_PSS2TS3 = 0x2B, + TPRC_PSS0TS1 = 0x2C, + TPRC_PSS2TS4 = 0x2D, + TPRC_PSS2TS5 = 0x2E, + TPRC_PSS0TS6 = 0x2F, +} TRPC, *PTRPC; + + +typedef enum _PS_MODE_SETTING_SELECTION_ +{ + MODE_SETTING_ACTIVE = 0, + MODE_SETTING_LEGACY = 1, + MODE_SETTING_WMMPS = 2, + #ifdef TDMA_POWER_SAVING + MODE_SETTING_TDMA = 3 + #endif //#ifdef TDMA_POWER_SAVING +}PS_MODE_SETTING_SELECTION, *PPS_MODE_SETTING_SELECTION; + +typedef enum _RxListenBeaconMode_ +{ + RLBM_MIN = 0, + RLBM_MAX = 1, + RLBM_SELF_DEFINED = 2 + +}RxListenBeaconMode, *PRxListenBeaconMode; + +typedef enum _SMART_PS_MODE_FOR_LEGACY_ +{ + SMART_PS_MODE_LEGACY_PWR1 = 0, // TRX all use PS_POLL + SMART_PS_MODE_TX_PWR0 = 1, // TX: pwr bit = 0, RX: PS_POLL + SMART_PS_MODE_TRX_PWR0 = 2 // TX: pwr bit = 0, RX: NULL(0) +}SMART_PS_MODE_FOR_LEGACY, *PSMART_PS_MODE_FOR_LEGACY; + +#endif //#ifdef CONFIG_POWER_SAVING + +/*--------------------------Define MACRO--------------------------------------*/ + +#define HAL_WL_READ32(addr) \ + HAL_READ32(WIFI_REG_BASE, addr) +#define HAL_WL_WRITE32(addr, value) \ + HAL_WRITE32(WIFI_REG_BASE, addr, value) +#define HAL_WL_READ16(addr) \ + HAL_READ16(WIFI_REG_BASE, addr) +#define HAL_WL_WRITE16(addr, value) \ + HAL_WRITE16(WIFI_REG_BASE, addr, value) +#define HAL_WL_READ8(addr) \ + HAL_READ8(WIFI_REG_BASE, addr) +#define HAL_WL_WRITE8(addr, value) \ + HAL_WRITE8(WIFI_REG_BASE, addr, value) + +#ifdef CONFIG_POWER_SAVING +#define mtou(x) ((x)<<10) //ms->us + +#define WAIT_TSF_STABLE_BREAK_CNT 5000 +#define WAIT_TSF_STABLE_CNT 50 +#define WAIT_TSF_STABLE_ONCE_TIME 20 +#define TSFIS32K 1 +#define TSFIS40M 0 +#define GET_TSF_STATE() (((HAL_WL_READ16(0xF0) & BIT8) && (HAL_WL_READ16(0xF0) & BIT9)) ? TSFIS32K : TSFIS40M) + + +#define REG_ARFR5_8723B 0x04A4 +#define WAIT_TXSM_STABLE_CNT 1000 +#define WAIT_TXSM_STABLE_ONCE_TIME 50 + +#define MODE_TIMER 1 +#define MODE_COUNTER 0 + + +#define GTIMER6 6 +#define GTIMER7 7 + +#define TIMER_BCNTO GTIMER6 //6 +#define TIMER_DTIM GTIMER6 //6 +#define TIMER_CHECKSTATE GTIMER6 //6 +#define TIMER_PSTRX GTIMER7 //7 +#ifdef TDMA_POWER_SAVING +#define TIMER_TDMA GTIMER7 //7 +#endif //#ifdef TDMA_POWER_SAVING + +#define RTY_LMT_NULLDATA 8 +#define RTY_LMT_PSPOLL 24 +#define RTY_LMT_MORE_NULLDATA 24 + + +/* + PS_RX_INFO[7:0]: Power Save RX Information Register + initial value: 0x00 + REG III.220 (Offset 0x 0692h) PS_RX_INFO Register Definition +*/ +#define RXDATAIN0 BIT0 //PSTX +#define RXDATAIN1 BIT1 //PSRX +#define RXDATAIN2 BIT2 +#define RXMGTIN0 BIT3 +#define RXCTRLIN0 BIT4 + +//CPWM Definition +#define CLK_DOWN_RDY BIT4 + +//Power Save Tuning Parameter +//#if IS_CATEGORY_WOWLAN(CONFIG_CATEGORY_SEL) +//#define DEFAULT_BCN_TO_LIMIT 5 // 1 +//#define DEFAULT_BCN_TO_PERIOD 8 //5 +//#else +#define DEFAULT_BCN_TO_LIMIT 2 // 1 +#define DEFAULT_BCN_TO_PERIOD 4 //5 +//#endif + +#define DEFAULT_BCN_TO_TIMES_LIMIT 2 // 20140806 +#define DEFAULT_DTIM_TIMEOUT 15 // 7 // 7 ms +#define DEFAULT_PS_TIMEOUT 15 // 20 // 20 ms +#define DEFAULT_PS_DTIM_PERIOD 7 +#define DEFAULT_PS_DRV_EARLY 2 +#define DEFAULT_ENTER32K_TIMER 1000 //us +//#define PS_DRV_BCN_SHIFT_MAX DEFAULT_PS_DRV_EARLY-1 + + +#define NULL_DATA0_ALLOW 1 +#define NULL_DATA0_DENY 0 + +#define PS_RF_OFF_8723B 0 +#define PS_GO_ON BIT0 +#define PS_TX_NULL BIT1 +#define PS_RF_ON BIT2 +#define PS_REGISTER_ACTIVE BIT3 +//#define PS_ACK BIT6 +//#define PS_TOGGLE BIT7 + + +#define PS_STATE_MASK (0x0F) +//#define PS_STATE(x) (PS_STATE_MASK & (x)) +#define PS_IS_TX_NULL(x) ((x) & PS_TX_NULL ) +//#define PS_IS_ACK(x) ((x) & PS_ACK ) +#define PS_IS_CLK_ON(x) ((x) & (PS_RF_OFF_8723B |PS_ALL_ON )) +#define PS_IS_RF_OFF(x) ((x)|PS_RF_OFF_8723B) +//#define PS_IS_RF_ON(x) ((x) & (PS_RF_ON)) +//#define PS_IS_ACTIVE(x) ((x) & (PS_REGISTER_ACTIVE)) + +#define PS_STATUS_S0 (PS_REGISTER_ACTIVE | PS_RF_ON) //(1,1,0) all on = register active + rf on +#define PS_STATUS_S1 (PS_REGISTER_ACTIVE | PS_RF_ON | PS_TX_NULL) //(1,1,1) all on + tx null(1) +#define PS_STATUS_S2 (PS_RF_ON) //(0,1,0) register sleep + rf on +#define PS_STATUS_S3 (PS_RF_ON | PS_TX_NULL) //(0,1,1) register sleep + rf on + tx null(0) +#define PS_STATUS_S4 0 //(0,0,0) all OFF +#define PS_STATUS_S5 (PS_TX_NULL ) //(0,0,1) SCAN = register sleep + rf on + scan enable +#define PS_STATUS_S6 (PS_REGISTER_ACTIVE) //(1,0,0) NoA off = register active + rf off + + +/* DATA FIN Condition Flags */ +#define STA_DATA_OPEN BIT0 // indicate that FW open due to TIM = 1 condition. (PS-POLL as trigger frame) +#define BC_DATA_OPEN BIT1 // indicate that FW open due to DTIM = 1 condition. (BC & MC) +#define QOS_DATA_OPEN BIT2 // indicate that FW open due to UAPSD trigger condition. (QNULL) + +#define ALL_80211_DATA_OPEN (STA_DATA_OPEN | BC_DATA_OPEN | QOS_DATA_OPEN) +#define IS_80211_DATA_OPEN(x) ((x) & ALL_80211_DATA_OPEN) + +#define C2H_DATA_OPEN BIT3 // indicate that FW open due to C2H event +#define IS_C2H_DATA_OPEN(x) ((x) & C2H_DATA_OPEN) + +#define BCN_DATA_OPEN BIT4 +#define APP_DATA_OPEN BIT5 + +#define SET_DATA_OPEN(x, type) ((x) |= (type)) +#define CLR_DATA_OPEN(x, type) ((x) &= (~type)) +#define IS_DATA_OPEN(x, type) ((x) & (type)) + +//pwr state +#define PS_TYPE_32KPERMISSION 0 +#define PS_TYPE_CURRENT_PS_STATE 1 +#define PS_TYPE_LASTRPWM 2 + +#define CCXRPT_START_ADDR 0x0000 +#define SW_DEFINE_NULL0 0x123 +#define SW_DEFINE_NULL1 0x321 +#define SW_DEFINE_OFFSET 6 +#define RETRY_OVER BIT7 + +#define CCXRPT_OFFSET(x) (x << 3) + +#define WLAN_ENTERCRITICAL() __disable_irq() +#define WLAN_EXITCRITICAL() __enable_irq() + +#endif //#ifdef CONFIG_POWER_SAVING + +/*------------------------------Define Struct---------------------------------*/ +#ifdef CONFIG_POWER_SAVING +typedef struct _PS_PARM_ { + + u8 Enter32KHzPermission; + u8 bAllQueueUAPSD; + u8 ps_dtim_flag; // indicate dtim of current beacon. + u8 pstrx_rxcnt_period; + u8 NoConnect32k; + u8 ack_last_rpwm; + u8 TxNull0; + u8 TxNull1; + + u8 TxNull0ok; + u8 TxNull1ok; + u8 RfOffLicenseForBCNRx; //filen: After we received ps_bcn_cnt beacons, we can sleep(rf off). + u8 BCNAggEn; + u8 IsGoingTo32K; + u8 bMaxTrackingBcnMode; + u8 BcnTraceDone; + +/* + filen: to indicate whether it is smart power saving or not + 0: Legacy PS + 1: Smart PS(RX use ps_poll) + 2: Smart PS (RX use null_data(0)) +*/ + u8 smart_ps:4; //enum SMART_PS_MODE + u8 RLBM:4; // RX BCN MODE (min, max, active, ...) + u8 AwakeInterval; + u8 ps_mode; // ps type (avtive, legacy, wmmps) + u8 ClkRequestEnable; + u8 last_rpwm; + u8 current_ps_state; + u8 ps_data_open; + u8 ps_bcn_pass_time; // fw will only report one beacon information to driver after ps_bcn_pass_time ms. Unit: 100ms + + u8 ps_dtim_period; + u8 ps_dtim_cnt; + u8 ps_bcn_to; // beacon timeout (ms). + u8 bcn_to_cnt; // indicate the total number of contnuous BCN_TO we have received. + u8 bcn_to_times_cnt; //20140806 + u8 min_rate_in_rrsr; +// u8 lps_control; + u16 ps_drv_early_itv; +// u32 RFECtrl; + u32 null1_ok_cnt; + #ifdef TDMA_POWER_SAVING + u8 SlotPeriod; + u8 FirstOnPeriod; + u8 SecondOnPeriod; + u8 ThirdOnPeriod; + u8 CurrentSlot; + BOOLEAN TDMAOnPeriod; + #endif // #ifdef TDMA_POWER_SAVING + +#if 0 + u8 BcnAheadShift; + u8 BcnEarlyShift; + u8 BcnEarlyShiftMax; + u8 DefaultBcnEarly; + u8 RxBcnCount; + u8 TBTTCount; + u8 CurrentEarly; + u8 CurrentTimeOut; + u8 ReachBcnLimitCount; + u8 BcnDelayInAheadGroupOfAP; + u8 BcnDelayInRearGroupOfAP; + u8 BcnDelay[BCN_CALCULATION_MAX]; + u8 XtalDelay; + + u16 TSFOnTBTT; //unit in TU + u32 TSFOnRxBcn; + u32 TSFOnBcnEarly; +#endif + +#if 0 +#if CONFIG_BCNEARLY_ADJUST + u8 BcnEalyIndex; + u8 BcnEarlyAdjustPosition; + u8 BcnAdjustTogo; + u8 RxBcnArray[BCN_ADJUST_COUNT]; +#endif +#endif +}PS_PARM, *PPS_PARM; + +typedef struct _LEGACY_PS_PPARM_ { + u8 ps_mode:7; + u8 ClkRequestEnable:1; + u8 RLBM:4; //RX Listen BCN Mode + u8 smart_ps:4; + u8 AwakeInterval; //Unit: beacon interval, this field is only valid in PS Self-Defined mode + u8 bAllQueueUAPSD:1; // 1: all queue are uapsd 0: not all queue are uapsd + u8 bMaxTrackingBcnMode:1; + u8 rsvd:6; +//#if CONFIG_FAST_CPWM + u8 PwrState; +//#else +// u8 permission32k:1; +// u8 rsvd1:7; +//#endif + + u8 LowPwrRxBCN :1; + u8 AntAutoSwitch :1; + u8 PSAllowBTHighPri:1; + u8 ProtectBCN :1; + u8 SilencePeriod :1; + u8 FastBTConnect :1; + u8 TwoAntennaEn :1; + u8 rsvd2 :1; + u8 AdoptUserSetting:1; + u8 DrvBcnEarlyShift :3; + u8 DrvBcnTimeOut :4; + #ifdef TDMA_POWER_SAVING + u8 SlotPeriod; + u8 FirstOnPeriod; + u8 SecondOnPeriod; + u8 ThirdOnPeriod; + #endif //#ifdef TDMA_POWER_SAVING +}LEGACY_PS_PARM, *PLEGACY_PS_PARM; + +//H2C Index: 0x20 +typedef struct _H2CParam_SetPwrMode_parm_ { + LEGACY_PS_PARM PwrModeParm; +}H2CParam_PwrMode, *PH2CParam_PwrMode; + +#endif //#ifdef CONFIG_POWER_SAVING + +/*------------------------------Function declaration--------------------------*/ + +#ifdef CONFIG_POWER_SAVING +#if 0 +extern void ClockDown(PADAPTER padapter); +extern void ClockUp(PADAPTER padapter); +extern void PrintBcnFunction(void); +extern void DisDbgMsg(void); +extern void EnDbgMsg(void); +extern void UpChGain(void); +extern void StartCount(PADAPTER padapter); +extern void StopCount(PADAPTER padapter); +extern void IssueNullDataTest(PADAPTER padapter); +extern void ShowPowerState(PADAPTER padapter); +#endif +#ifdef TDMA_POWER_SAVING +extern void TDMAChangeStateTask(PADAPTER padapter); +#endif //#ifdef TDMA_POWER_SAVING +extern void EnterPS(PADAPTER padapter); +extern void GTimer6Handle(VOID *Data); +extern void GTimer7Handle(VOID *Data); +extern void InitGTimer1ms(PADAPTER padapter, u8 IRQDis, u8 TimerID, u32 Period); +extern void DeInitGTimer1ms(PADAPTER padapter, u8 TimerID); +extern void ChangeTransmiteRate(u16 offset, u8 rate); +extern void PowerBitSetting(BOOLEAN bPowerBit, u16 offset); +extern void ChkandChangePS(PPS_PARM pPSParm, BOOLEAN bPowerBit); +extern u16 IssueRsvdPagePacketSetting(u8 PageNum, BOOLEAN bHwSEQEn, u8 RtyLmt); +extern void InitRsvdPgPkt(void); +extern BOOLEAN IssueNullData(PPS_PARM pPSParm, BOOLEAN bPowerBit, u8 RtyLmt); +extern void IssuePSPoll(void); +extern BOOLEAN WaitTxStateMachineOk(void); +extern void WriteTxPause(u8 value, u8 rcode); +extern void PsCloseRF(void); +extern void PsOpenRF(void); +extern void SetPwrStateReg(PPS_PARM pPSParm, u8 PwrStateType, u8 value); +extern BOOLEAN ChkTxQueueIsEmpty(void); +extern void InitPS(PADAPTER padapter); +extern void ResetPSParm(PADAPTER padapter); +extern void Legacy_PS_Setting(PADAPTER padapter); +extern void PSModeSetting(PADAPTER padapter, u8 on); +extern void ConfigListenBeaconPeriod(PPS_PARM pPSParm, u8 RLBM, u8 AwakeInterval); +extern void PSSetMode(PADAPTER padapter, PLEGACY_PS_PARM pparm); +extern BOOLEAN PS_S2_Condition_Match(PPS_PARM pPSParm); +extern BOOLEAN PS_S4_Condition_Match(PADAPTER padapter); +extern BOOLEAN PS_32K_Condition_Match(void); +extern void PS_S2ToS3ToS0State(PADAPTER padapter, u8 nulldata0Allow); +extern void PS_S2ToS0State(PPS_PARM pPSParm); +extern void PS_S3ToS2orS0State(PPS_PARM pPSParm); +extern void PS_S0ToS1ToS2State(PADAPTER padapter); +extern void PS_S1ToS0orS2State(PPS_PARM pPSParm); +extern void PS_S2ToS4State(PADAPTER padapter); +extern void PS_S2ToS5State(PPS_PARM pPSParm); +extern void PS_S4ToS2State(PPS_PARM pPSParm, u8 ReleaseTxPause); +extern void PS_S5ToS2State(PPS_PARM pPSParm); +extern void PS_S0ToS6State(PADAPTER padapter); +extern void PS_S6ToS0State(PPS_PARM pPSParm); +extern void CheckTSFIsStable(u8 ReqState); +extern void WaitHWStateReady(void); +extern void SysClkDown(PPS_PARM pPSParm); +extern void SysClkUp(PPS_PARM pPSParm); +extern void SleepTo32K(PPS_PARM pPSParm); +extern void Change_PS_State(PADAPTER padapter, u8 request_ps_state, u8 nulldata0Allow); +extern void ChangePSStateByRPWM(PADAPTER padapter); +extern void SetSmartPSTimer(PADAPTER padapter); +extern void SmartPS2InitTimerAndToGetRxPkt(PADAPTER padapter); +extern void PS_OnBeacon(PADAPTER padapter); +extern void PSBcnEarlyProcess(PADAPTER padapter); +extern void PSMtiBcnEarlyProcess(PADAPTER padapter); +extern void PSRxBcnProcess(PADAPTER padapter); +extern void TxPktInPSOn(PADAPTER padapter); +extern void PsBcnToProcess(PADAPTER padapter); +extern BOOL RPWMProcess(PADAPTER padapter, BOOLEAN benter32k); +extern void ISR_MtiBcnEarly(PADAPTER padapter); +extern void ISR_BcnEarly(PADAPTER padapter); +extern void ISR_RxBcn(PADAPTER padapter); +extern void ISR_RxBCMD1(PADAPTER padapter); +extern void ISR_RxBCMD0(PADAPTER padapter); +extern void ISR_RxUCMD1(PADAPTER padapter); +extern void ISR_RxUCMD0(PADAPTER padapter); +extern void ISR_TxPktIn(PADAPTER padapter); +extern void ISR_TXCCX(PADAPTER padapter); +extern void H2CHDL_SetPwrMode(PADAPTER padapter, u8* pCmdBuffer); +extern void CheckInReqStateTask(PADAPTER padapter); +extern void HalSetRPWM(PADAPTER padapter, BOOLEAN benter32k); +extern u32 HalGetNullTxRpt(PADAPTER padapter); +//extern thread_return HalEnter32KThreadRtl8195a(thread_context context); +#endif //#ifdef CONFIG_POWER_SAVING + +extern void ISR_TBTT(PADAPTER padapter); +extern void H2CHDL_BcnIgnoreEDCCA(PADAPTER padapter, u8* pCmdBuffer); + +void PMUTask(PADAPTER padapter); +void PMUInitial(PADAPTER padapter); + +#endif //CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD +#endif //__RTL8195A_PMU_TASK_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_recv.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_recv.h new file mode 100644 index 0000000..7fad730 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_recv.h @@ -0,0 +1,232 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8195A_RECV_H__ +#define __RTL8195A_RECV_H__ + +#ifdef CONFIG_WLAN_HAL_TEST +#define MAX_RECVBUF_SZ 1200//(RX_DMA_SIZE_8195A - RX_DMA_RESERVED_SIZE_8195A) +#else +#if (SKB_PRE_ALLOCATE_RX==1) +#define MAX_RECVBUF_SZ MAX_SKB_BUF_SIZE //1650 //(RX_DMA_SIZE_8195A - RX_DMA_RESERVED_SIZE_8195A) +#else +#define MAX_RECVBUF_SZ (HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\ + RXDESC_SIZE +\ + (MAX_RX_PKT_LIMIT * 512) +\ + SKB_RESERVED_FOR_SAFETY) // 0+32+24+512*4+0 = 2104 +#endif +#endif + +//DWORD 0 +#define SET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 0, 14, __Value) +#define SET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 30, 1, __Value) +#define SET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 31, 1, __Value) + +#define GET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 14) +#define GET_RX_STATUS_DESC_CRC32_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 14, 1) +#define GET_RX_STATUS_DESC_ICV_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 15, 1) +#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 16, 4) +#define GET_RX_STATUS_DESC_SECURITY_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 20, 3) +#define GET_RX_STATUS_DESC_QOS_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 23, 1) +#define GET_RX_STATUS_DESC_SHIFT_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 24, 2) +#define GET_RX_STATUS_DESC_PHY_STATUS_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 26, 1) +#define GET_RX_STATUS_DESC_SWDEC_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 27, 1) +#define GET_RX_STATUS_DESC_LAST_SEG_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 28, 1) +#define GET_RX_STATUS_DESC_FIRST_SEG_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 29, 1) +#define GET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 30, 1) +#define GET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 31, 1) + +//DWORD 1 +#define GET_RX_STATUS_DESC_MACID_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) +#define GET_RX_STATUS_DESC_TID_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) +#define GET_RX_STATUS_DESC_AMSDU_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) +#define GET_RX_STATUS_DESC_RXID_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 14, 1) +#define GET_RX_STATUS_DESC_PAGGR_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 15, 1) +#define GET_RX_STATUS_DESC_A1_FIT_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 16, 4) +#define GET_RX_STATUS_DESC_CHKERR_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 20, 1) +#define GET_RX_STATUS_DESC_IPVER_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) +#define GET_RX_STATUS_DESC_IS_TCPUDP__8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) +#define GET_RX_STATUS_DESC_CHK_VLD_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) +#define GET_RX_STATUS_DESC_PAM_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 24, 1) +#define GET_RX_STATUS_DESC_PWR_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 25, 1) +#define GET_RX_STATUS_DESC_MORE_DATA_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 26, 1) +#define GET_RX_STATUS_DESC_MORE_FRAG_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 27, 1) +#define GET_RX_STATUS_DESC_TYPE_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 28, 2) +#define GET_RX_STATUS_DESC_MC_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 30, 1) +#define GET_RX_STATUS_DESC_BC_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 31, 1) + +//DWORD 2 +#define GET_RX_STATUS_DESC_SEQ_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 0, 12) +#define GET_RX_STATUS_DESC_FRAG_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 12, 4) +#define GET_RX_STATUS_DESC_RX_IS_QOS_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 16, 1) +#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 18, 6) +#define GET_RX_STATUS_DESC_RPT_SEL_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 28, 1) + +//DWORD 3 +#define GET_RX_STATUS_DESC_RX_RATE_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 0, 7) +#define GET_RX_STATUS_DESC_HTC_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 10, 1) +#define GET_RX_STATUS_DESC_EOSP_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 11, 1) +#define GET_RX_STATUS_DESC_BSSID_FIT_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 12, 2) +#ifdef CONFIG_USB_RX_AGGREGATION +#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 16, 8) +#endif +#define GET_RX_STATUS_DESC_PATTERN_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 29, 1) +#define GET_RX_STATUS_DESC_UNICAST_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 30, 1) +#define GET_RX_STATUS_DESC_MAGIC_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 31, 1) + +//DWORD 6 +#define GET_RX_STATUS_DESC_SPLCP_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 0, 1) +#define GET_RX_STATUS_DESC_LDPC_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 1, 1) +#define GET_RX_STATUS_DESC_STBC_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 2, 1) +#define GET_RX_STATUS_DESC_BW_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 4, 2) + +//DWORD 5 +#define GET_RX_STATUS_DESC_TSFL_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32) + +#define GET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) +#define GET_RX_STATUS_DESC_BUFF_ADDR64_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) + +#define SET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value) + +typedef struct rxreport_8723b +{ + //DWORD 0 + u32 pktlen:14; + u32 crc32:1; + u32 icverr:1; + u32 drvinfosize:4; + u32 security:3; + u32 qos:1; + u32 shift:2; + u32 physt:1; + u32 swdec:1; + u32 rsvd0028:2; + u32 eor:1; + u32 rsvd0031:1; + + //DWORD 1 + u32 macid:7; + u32 rsvd0407:1; + u32 tid:4; + u32 macid_vld:1; + u32 amsdu:1; + u32 rxid_match:1; + u32 paggr:1; + u32 a1fit:4; + u32 chkerr:1; //20 + u32 rx_ipv:1; + u32 rx_is_tcp_udp:1; + u32 chk_vld:1; //23 + u32 pam:1; + u32 pwr:1; + u32 md:1; + u32 mf:1; + u32 type:2; + u32 mc:1; + u32 bc:1; + + //DWORD 2 + u32 seq:12; + u32 frag:4; + u32 rx_is_qos:1; + u32 rsvd0817:1; + u32 wlanhd_iv_len:6; + u32 hwrsvd0824:4; + u32 c2h_ind:1; + u32 rsvd0829:2; + u32 fcs_ok:1; + + //DWORD 3 + u32 rx_rate:7; + u32 rsvd1207:3; + u32 htc:1; + u32 esop:1; + u32 bssid_fit:2; + u32 rsvd1214:2; + u32 dma_agg_num:8; + u32 rsvd1224:5; + u32 patternmatch:1; + u32 unicastwake:1; + u32 magicwake:1; + + //DWORD 4 + u32 splcp:1; //Ofdm sgi or cck_splcp + u32 ldpc:1; + u32 stbc:1; + u32 not_sounding:1; + u32 bw:2; + u32 rsvd1606:26; + + //DWORD 5 + u32 tsfl; +} RXREPORT, *PRXREPORT; + +typedef struct phystatus_8723b +{ + u32 rxgain_a:7; + u32 trsw_a:1; + u32 rxgain_b:7; + u32 trsw_b:1; + u32 chcorr_l:16; + + u32 sigqualcck:8; + u32 cfo_a:8; + u32 cfo_b:8; + u32 chcorr_h:8; + + u32 noisepwrdb_h:8; + u32 cfo_tail_a:8; + u32 cfo_tail_b:8; + u32 rsvd0824:8; + + u32 rsvd1200:8; + u32 rxevm_a:8; + u32 rxevm_b:8; + u32 rxsnr_a:8; + + u32 rxsnr_b:8; + u32 noisepwrdb_l:8; + u32 rsvd1616:8; + u32 postsnr_a:8; + + u32 postsnr_b:8; + u32 csi_a:8; + u32 csi_b:8; + u32 targetcsi_a:8; + + u32 targetcsi_b:8; + u32 sigevm:8; + u32 maxexpwr:8; + u32 exintflag:1; + u32 sgien:1; + u32 rxsc:2; + u32 idlelong:1; + u32 anttrainen:1; + u32 antselb:1; + u32 antsel:1; +} PHYSTATUS, *PPHYSTATUS; + + +s32 rtl8195a_init_recv_priv(PADAPTER padapter); +void rtl8195a_free_recv_priv(PADAPTER padapter); +void rtl8195a_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc); +void rtl8195a_query_rx_phy_status(union recv_frame *precvframe, u8 *pphy_status); + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_rf.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_rf.h new file mode 100644 index 0000000..f02cdea --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_rf.h @@ -0,0 +1,32 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8195A_RF_H__ +#define __RTL8195A_RF_H__ + + +int PHY_RF6052_Config8195A( IN PADAPTER Adapter ); + +VOID +PHY_RF6052SetBandwidth8195A( + IN PADAPTER Adapter, + IN CHANNEL_WIDTH Bandwidth); + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_spec.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_spec.h new file mode 100644 index 0000000..e6136e7 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_spec.h @@ -0,0 +1,345 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + *******************************************************************************/ +#ifndef __RTL8195A_SPEC_H__ +#define __RTL8195A_SPEC_H__ + +#include + + +#define HAL_NAV_UPPER_UNIT_8723B 128 // micro-second + +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +#define REG_BT_WIFI_ANTENNA_SWITCH_8723B 0x0038 +#define REG_PAD_CTRL1_8723B 0x0064 +#define REG_AFE_CTRL_4_8723B 0x0078 +#define REG_HMEBOX_DBG_0_8723B 0x0088 +#define REG_HMEBOX_DBG_1_8723B 0x008A +#define REG_HMEBOX_DBG_2_8723B 0x008C +#define REG_HMEBOX_DBG_3_8723B 0x008E + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +#define REG_C2HEVT_CMD_ID_8723B 0x01A0 +#define REG_C2HEVT_CMD_LEN_8723B 0x01AE +#ifdef CONFIG_WOWLAN +#define REG_WOWLAN_WAKE_REASON 0x01C7 +#endif + +#define REG_HMEBOX_EXT0_8723B 0x01F0 +#define REG_HMEBOX_EXT1_8723B 0x01F4 +#define REG_HMEBOX_EXT2_8723B 0x01F8 +#define REG_HMEBOX_EXT3_8723B 0x01FC + +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- + +//----------------------------------------------------- +// +// 0x0280h ~ 0x02FFh RXDMA Configuration +// +//----------------------------------------------------- +#define REG_RXDMA_MODE_CTRL_8723B 0x0290 + +//----------------------------------------------------- +// +// 0x0300h ~ 0x03FFh PCIe +// +//----------------------------------------------------- + +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +#define REG_TXPKTBUF_BCNQ_BDNY_8195A 0x0424 +#define REG_TXPKTBUF_MGQ_BDNY_8195A 0x0425 +#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8195A 0x045D +#ifdef CONFIG_WOWLAN +#define REG_TXPKTBUF_IV_LOW 0x0484 +#define REG_TXPKTBUF_IV_HIGH 0x0488 +#endif + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +#define REG_SECONDARY_CCA_CTRL_8723B 0x0577 + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- + + +//============================================================ +// SDIO Bus Specification +//============================================================ + +//----------------------------------------------------- +// SDIO CMD Address Mapping +//----------------------------------------------------- + +//----------------------------------------------------- +// I/O bus domain (Host) +//----------------------------------------------------- + +//----------------------------------------------------- +// SDIO register +//----------------------------------------------------- +#define SDIO_REG_HCPWM1_8723B 0x025 // HCI Current Power Mode 1 + + +//============================================================================ +// 8723 Regsiter Bit and Content definition +//============================================================================ + +//2 HSISR +// interrupt mask which needs to clear +#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ + HSISR_SPS_OCP_INT |\ + HSISR_RON_INT |\ + HSISR_PDNINT |\ + HSISR_GPIO9_INT) + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- + +#define RXDMA_AGG_MODE_EN BIT(1) +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- + +//----------------------------------------------------- +// +// 0x0280h ~ 0x02FFh RXDMA Configuration +// +//----------------------------------------------------- +#ifdef CONFIG_WOWLAN +#define RXPKT_RELEASE_POLL BIT(16) +#define RXDMA_IDLE BIT(17) +#define RW_RELEASE_EN BIT(18) +#endif + +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- + +#endif + +//==================================================== +// EEPROM/Efuse PG Offset for 8195A +//==================================================== +// 0x10 ~ 0x63 = TX power area. +#define EEPROM_TX_PWR_INX_8195A 0x20 +#define EEPROM_ChannelPlan_8195A 0xC8 +#define EEPROM_XTAL_8195A 0xC9 +#define EEPROM_THERMAL_METER_8195A 0xCA + +#define EEPROM_IQK_LCK_8195A 0xCB +#define EEPROM_2G_5G_PA_TYPE_8195A 0xCC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8195A 0xCD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8195A 0xCE + +#define EEPROM_RF_BOARD_OPTION_8195A 0x131 + +#define EEPROM_FEATURE_OPTION_8195A 0x132 +#define EEPROM_RF_BT_SETTING_8195A 0x133 + +#define EEPROM_VERSION_8195A 0x134 +#define EEPROM_CustomID_8195A 0x135 + +#define EEPROM_TX_BBSWING_2G_8195A 0x136 +#define EEPROM_TX_PWR_CAL_RATE_8195A 0x138 +#define EEPROM_RF_ANTENNA_OPT_8195A 0x139 +#define EEPROM_RFE_OPTION_8195A 0x13A + +//RTL8723BU +#define EEPROM_MAC_ADDR_8723BU 0x107 +#define EEPROM_VID_8723BU 0x100 +#define EEPROM_PID_8723BU 0x102 +#define EEPROM_PA_TYPE_8723BU 0xBC +#define EEPROM_LNA_TYPE_2G_8723BU 0xBD + +//RTL8723BS +#define EEPROM_MAC_ADDR_8723BS 0x11A +#define EEPROM_MAC_ADDR_8195A 0x11A + +#define EEPROM_Voltage_ADDR_8723B 0x8 + +#define EEPROM_TX_KFREE_8195A 0xEE + +#define EEPROM_PACKAGE_TYPE_8195A 0xF8 + +//==================================================== +// EEPROM/Efuse Value Type +//==================================================== +#define EETYPE_TX_PWR 0x0 +//==================================================== +// EEPROM/Efuse Default Value +//==================================================== +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_DEFAULT_EXT 0xFF // Reserved for Realtek +#define EEPROM_CID_TOSHIBA 0x4 +#define EEPROM_CID_CCX 0x10 +#define EEPROM_CID_QMI 0x0D +#define EEPROM_CID_WHQL 0xFE + +#define EEPROM_CHANNEL_PLAN_FCC 0x0 +#define EEPROM_CHANNEL_PLAN_IC 0x1 +#define EEPROM_CHANNEL_PLAN_ETSI 0x2 +#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 +#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 +#define EEPROM_CHANNEL_PLAN_MKK 0x5 +#define EEPROM_CHANNEL_PLAN_MKK1 0x6 +#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 +#define EEPROM_CHANNEL_PLAN_TELEC 0x8 +#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 +#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA +#define EEPROM_CHANNEL_PLAN_NCC_TAIWAN 0xB +#define EEPROM_CHANNEL_PLAN_CHIAN 0XC +#define EEPROM_CHANNEL_PLAN_SINGAPORE_INDIA_MEXICO 0XD +#define EEPROM_CHANNEL_PLAN_KOREA 0xE +#define EEPROM_CHANNEL_PLAN_TURKEY 0xF +#define EEPROM_CHANNEL_PLAN_JAPAN 0x10 +#define EEPROM_CHANNEL_PLAN_FCC_NO_DFS 0x11 +#define EEPROM_CHANNEL_PLAN_JAPAN_NO_DFS 0x12 +#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_5G 0x13 +#define EEPROM_CHANNEL_PLAN_TAIWAN_NO_DFS 0x14 + +#define EEPROM_USB_OPTIONAL1 0xE +#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 + +#define RTL_EEPROM_ID 0x8129 +#define EEPROM_Default_TSSI 0x0 +#define EEPROM_Default_BoardType 0x02 +#define EEPROM_Default_ThermalMeter 0x12 +#define EEPROM_Default_ThermalMeter_92SU 0x7 +#define EEPROM_Default_ThermalMeter_88E 0x18 +#define EEPROM_Default_ThermalMeter_8812 0x18 +#define EEPROM_Default_ThermalMeter_8192E 0x1A +#define EEPROM_Default_ThermalMeter_8723B 0x18 +#define EEPROM_Default_ThermalMeter_8195A 0x1A + + +#define EEPROM_Default_CrystalCap 0x0 +#define EEPROM_Default_CrystalCap_8723B 0x20 +#define EEPROM_Default_CrystalCap_8195A 0x20 +#define EEPROM_Default_CrystalFreq 0x0 +#define EEPROM_Default_TxPowerLevel_92C 0x22 +#define EEPROM_Default_TxPowerLevel_2G 0x2C +#define EEPROM_Default_TxPowerLevel_5G 0x22 +#define EEPROM_Default_TxPowerLevel 0x22 +#define EEPROM_Default_HT40_2SDiff 0x0 +#define EEPROM_Default_HT20_Diff 2 +#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 +#define EEPROM_Default_LegacyHTTxPowerDiff_92C 0x3 +#define EEPROM_Default_LegacyHTTxPowerDiff_92D 0x4 +#define EEPROM_Default_HT40_PwrMaxOffset 0 +#define EEPROM_Default_HT20_PwrMaxOffset 0 + +#define EEPROM_Default_PID 0x1234 +#define EEPROM_Default_VID 0x5678 +#define EEPROM_Default_CustomerID 0xAB +#define EEPROM_Default_CustomerID_8188E 0x00 +#define EEPROM_Default_SubCustomerID 0xCD +#define EEPROM_Default_Version 0 + +#define EEPROM_Default_externalPA_C9 0x00 +#define EEPROM_Default_externalPA_CC 0xFF +#define EEPROM_Default_internalPA_SP3T_C9 0xAA +#define EEPROM_Default_internalPA_SP3T_CC 0xAF +#define EEPROM_Default_internalPA_SPDT_C9 0xAA +#ifdef CONFIG_PCI_HCI +#define EEPROM_Default_internalPA_SPDT_CC 0xA0 +#else +#define EEPROM_Default_internalPA_SPDT_CC 0xFA +#endif +#define EEPROM_Default_PAType 0 +#define EEPROM_Default_LNAType 0 + +//New EFUSE deafult value +#define EEPROM_DEFAULT_24G_CCK_INDEX 0x20 +#define EEPROM_DEFAULT_24G_40M_INDEX 0x20 +#define EEPROM_DEFAULT_24G_HT20_DIFF 0X00 +#define EEPROM_DEFAULT_24G_OFDM_DIFF 0X02 + +#define EEPROM_DEFAULT_5G_INDEX 0X2A +#define EEPROM_DEFAULT_5G_HT20_DIFF 0X00 +#define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04 + +#define EEPROM_DEFAULT_DIFF 0XFE +#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F +#define EEPROM_DEFAULT_BOARD_OPTION 0x01 // Enable power by rate and power limit +#define EEPROM_DEFAULT_RFE_OPTION 0x04 +#define EEPROM_DEFAULT_FEATURE_OPTION 0x00 +#define EEPROM_DEFAULT_BT_OPTION 0x10 +#define EEPROM_DEFAULT_TX_CALIBRATE_RATE 0x00 + + + + + + +#ifdef CONFIG_USB_HCI +//should be renamed and moved to another file +typedef enum _BOARD_TYPE_8192CUSB{ + BOARD_USB_DONGLE = 0, // USB dongle + BOARD_USB_High_PA = 1, // USB dongle with high power PA + BOARD_MINICARD = 2, // Minicard + BOARD_USB_SOLO = 3, // USB solo-Slim module + BOARD_USB_COMBO = 4, // USB Combo-Slim module +} BOARD_TYPE_8723BUSB, *PBOARD_TYPE_8723BUSB; + +#endif + +#if defined (CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI) +#define RT_BCN_INT_MASKS (IMR_BcnInt | IMR_TBDOK | IMR_TBDER) +#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK) +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_sreset.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_sreset.h new file mode 100644 index 0000000..e990627 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_sreset.h @@ -0,0 +1,30 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTL8195A_SRESET_H_ +#define _RTL8195A_SRESET_H_ + +#include + +#ifdef DBG_CONFIG_ERROR_DETECT +extern void rtl8723b_sreset_xmit_status_check(_adapter *padapter); +extern void rtl8723b_sreset_linked_status_check(_adapter *padapter); +#endif +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_xmit.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_xmit.h new file mode 100644 index 0000000..c5925fb --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_xmit.h @@ -0,0 +1,473 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8195A_XMIT_H__ +#define __RTL8195A_XMIT_H__ + +// +// Queue Select Value in TxDesc +// +#define QSLT_BK 0x2//0x01 +#define QSLT_BE 0x0 +#define QSLT_VI 0x5//0x4 +#define QSLT_VO 0x7//0x6 +#define QSLT_BEACON 0x10 +#define QSLT_HIGH 0x11 +#define QSLT_MGNT 0x12 +#define QSLT_CMD 0x13 + +#define MAX_TID (15) + +//OFFSET 0 +#define OFFSET_SZ 0 +#define OFFSET_SHT 16 +#define BMC BIT(24) +#define LSG BIT(26) +#define FSG BIT(27) +#define OWN BIT(31) + + +//OFFSET 4 +#define PKT_OFFSET_SZ 0 +#define BK BIT(6) +#define QSEL_SHT 8 +#define Rate_ID_SHT 16 +#define NAVUSEHDR BIT(20) +#define PKT_OFFSET_SHT 26 +#define HWPC BIT(31) + +//OFFSET 8 +#define AGG_EN BIT(29) + +//OFFSET 12 +#define SEQ_SHT 16 + +//OFFSET 16 +#define QoS BIT(6) +#define HW_SEQ_EN BIT(7) +#define USERATE BIT(8) +#define DISDATAFB BIT(10) +#define DATA_SHORT BIT(24) +#define DATA_BW BIT(25) + +//OFFSET 20 +#define SGI BIT(6) + +// +//defined for TX DESC Operation +// +typedef struct txdesc_8723b +{ + // Offset 0 + u32 pktlen:16; + u32 offset:8; + u32 bmc:1; + u32 htc:1; + u32 rsvd0026:1; + u32 rsvd0027:1; + u32 linip:1; + u32 noacm:1; + u32 gf:1; + u32 rsvd0031:1; + + // Offset 4 + u32 macid:7; + u32 rsvd0407:1; + u32 qsel:5; + u32 rdg_nav_ext:1; + u32 lsig_txop_en:1; + u32 pifs:1; + u32 rate_id:5; + u32 en_desc_id:1; + u32 sectype:2; + u32 pkt_offset:5; // unit: 8 bytes + u32 moredata:1; + u32 txop_ps_cap:1; + u32 txop_ps_mode:1; + + // Offset 8 + u32 p_aid:9; + u32 rsvd0809:1; + u32 cca_rts:2; + u32 agg_en:1; + u32 rdg_en:1; + u32 null_0:1; + u32 null_1:1; + u32 bk:1; + u32 morefrag:1; + u32 raw:1; + u32 spe_rpt:1; + u32 ampdu_density:3; + u32 bt_null:1; + u32 g_id:6; + u32 rsvd0830:2; + + // Offset 12 + u32 wheader_len:4; + u32 chk_en:1; + u32 early_rate:1; + u32 hw_ssn_sel:2; + u32 userate:1; + u32 disrtsfb:1; + u32 disdatafb:1; + u32 cts2self:1; + u32 rtsen:1; + u32 hw_rts_en:1; + u32 port_id:1; + u32 navusehdr:1; + u32 use_max_len:1; + u32 max_agg_num:5; + u32 ndpa:2; + u32 ampdu_max_time:8; + + // Offset 16 + u32 datarate:7; + u32 try_rate:1; + u32 data_ratefb_lmt:5; + u32 rts_ratefb_lmt:4; + u32 rty_lmt_en:1; + u32 data_rt_lmt:6; + u32 rtsrate:5; + u32 pcts_en:1; + u32 pcts_mask_idx:2; + + // Offset 20 + u32 data_sc:4; + u32 data_short:1; + u32 data_bw:2; + u32 data_ldpc:1; + u32 data_stbc:2; + u32 vcs_stbc:2; + u32 rts_short:1; + u32 rts_sc:4; + u32 rsvd2016:7; + u32 tx_ant:4; + u32 txpwr_offset:3; + u32 rsvd2031:1; + + // Offset 24 + u32 sw_define:12; + u32 mbssid:4; + u32 antsel_A:3; + u32 antsel_B:3; + u32 antsel_C:3; + u32 antsel_D:3; + u32 rsvd2428:4; + + // Offset 28 + u32 checksum:16; + u32 rsvd2816:8; + u32 usb_txagg_num:8; + + // Offset 32 + u32 rts_rc:6; + u32 bar_rty_th:2; + u32 data_rc:6; + u32 rsvd3214:1; + u32 en_hwseq:1; + u32 nextneadpage:8; + u32 tailpage:8; + + // Offset 36 + u32 padding_len:11; + u32 txbf_path:1; + u32 seq:12; + u32 final_data_rate:8; +}TXDESC_8723B, *PTXDESC_8723B; + +#ifndef __INC_HAL8723BDESC_H +#define __INC_HAL8723BDESC_H + +#define RX_STATUS_DESC_SIZE_8723B 24 +#define RX_DRV_INFO_SIZE_UNIT_8723B 8 + + +//DWORD 0 +#define SET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 0, 14, __Value) +#define SET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 30, 1, __Value) +#define SET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 31, 1, __Value) + +#define GET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 14) +#define GET_RX_STATUS_DESC_CRC32_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 14, 1) +#define GET_RX_STATUS_DESC_ICV_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 15, 1) +#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 16, 4) +#define GET_RX_STATUS_DESC_SECURITY_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 20, 3) +#define GET_RX_STATUS_DESC_QOS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 23, 1) +#define GET_RX_STATUS_DESC_SHIFT_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 24, 2) +#define GET_RX_STATUS_DESC_PHY_STATUS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 26, 1) +#define GET_RX_STATUS_DESC_SWDEC_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 27, 1) +#define GET_RX_STATUS_DESC_LAST_SEG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 28, 1) +#define GET_RX_STATUS_DESC_FIRST_SEG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 29, 1) +#define GET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 30, 1) +#define GET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 31, 1) + +//DWORD 1 +#define GET_RX_STATUS_DESC_MACID_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) +#define GET_RX_STATUS_DESC_TID_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) +#define GET_RX_STATUS_DESC_AMSDU_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) +#define GET_RX_STATUS_DESC_RXID_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 14, 1) +#define GET_RX_STATUS_DESC_PAGGR_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 15, 1) +#define GET_RX_STATUS_DESC_A1_FIT_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 16, 4) +#define GET_RX_STATUS_DESC_CHKERR_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 20, 1) +#define GET_RX_STATUS_DESC_IPVER_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) +#define GET_RX_STATUS_DESC_IS_TCPUDP__8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) +#define GET_RX_STATUS_DESC_CHK_VLD_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) +#define GET_RX_STATUS_DESC_PAM_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 24, 1) +#define GET_RX_STATUS_DESC_PWR_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 25, 1) +#define GET_RX_STATUS_DESC_MORE_DATA_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 26, 1) +#define GET_RX_STATUS_DESC_MORE_FRAG_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 27, 1) +#define GET_RX_STATUS_DESC_TYPE_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 28, 2) +#define GET_RX_STATUS_DESC_MC_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 30, 1) +#define GET_RX_STATUS_DESC_BC_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 31, 1) + +//DWORD 2 +#define GET_RX_STATUS_DESC_SEQ_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 0, 12) +#define GET_RX_STATUS_DESC_FRAG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 12, 4) +#define GET_RX_STATUS_DESC_RX_IS_QOS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 16, 1) +#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 18, 6) +#define GET_RX_STATUS_DESC_RPT_SEL_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 28, 1) + +//DWORD 3 +#define GET_RX_STATUS_DESC_RX_RATE_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 0, 7) +#define GET_RX_STATUS_DESC_HTC_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 10, 1) +#define GET_RX_STATUS_DESC_EOSP_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 11, 1) +#define GET_RX_STATUS_DESC_BSSID_FIT_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 12, 2) +#ifdef CONFIG_USB_RX_AGGREGATION +#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 16, 8) +#endif +#define GET_RX_STATUS_DESC_PATTERN_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 29, 1) +#define GET_RX_STATUS_DESC_UNICAST_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 30, 1) +#define GET_RX_STATUS_DESC_MAGIC_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 31, 1) + +//DWORD 6 +#define GET_RX_STATUS_DESC_SPLCP_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 0, 1) +#define GET_RX_STATUS_DESC_LDPC_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 1, 1) +#define GET_RX_STATUS_DESC_STBC_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 2, 1) +#define GET_RX_STATUS_DESC_BW_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 4, 2) + +//DWORD 5 +#define GET_RX_STATUS_DESC_TSFL_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32) + +#define GET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) +#define GET_RX_STATUS_DESC_BUFF_ADDR64_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) + +#define SET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value) + + +// Dword 0 +#define GET_TX_DESC_OWN_8723B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) + +#define SET_TX_DESC_PKT_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) +#define SET_TX_DESC_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) +#define SET_TX_DESC_BMC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) +#define SET_TX_DESC_HTC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) +#define SET_TX_DESC_LAST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value) +#define SET_TX_DESC_FIRST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) +#define SET_TX_DESC_LINIP_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value) +#define SET_TX_DESC_NO_ACM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) +#define SET_TX_DESC_GF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) +#define SET_TX_DESC_OWN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) + +// Dword 1 +#define SET_TX_DESC_MACID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) +#define SET_TX_DESC_QUEUE_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) +#define SET_TX_DESC_RDG_NAV_EXT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) +#define SET_TX_DESC_LSIG_TXOP_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) +#define SET_TX_DESC_PIFS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) +#define SET_TX_DESC_RATE_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) +#define SET_TX_DESC_EN_DESC_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) +#define SET_TX_DESC_SEC_TYPE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) +#define SET_TX_DESC_PKT_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) + + +// Dword 2 +#define SET_TX_DESC_PAID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) +#define SET_TX_DESC_CCA_RTS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) +#define SET_TX_DESC_AGG_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) +#define SET_TX_DESC_RDG_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) +#define SET_TX_DESC_AGG_BREAK_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) +#define SET_TX_DESC_MORE_FRAG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) +#define SET_TX_DESC_RAW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) +#define SET_TX_DESC_SPE_RPT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) +#define SET_TX_DESC_AMPDU_DENSITY_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) +#define SET_TX_DESC_BT_INT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) +#define SET_TX_DESC_GID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value) + + +// Dword 3 +#define SET_TX_DESC_WHEADER_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value) +#define SET_TX_DESC_CHK_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value) +#define SET_TX_DESC_EARLY_MODE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) +#define SET_TX_DESC_HWSEQ_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) +#define SET_TX_DESC_USE_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) +#define SET_TX_DESC_DISABLE_RTS_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) +#define SET_TX_DESC_DISABLE_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) +#define SET_TX_DESC_CTS2SELF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) +#define SET_TX_DESC_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) +#define SET_TX_DESC_HW_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) +#define SET_TX_DESC_NAV_USE_HDR_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) +#define SET_TX_DESC_USE_MAX_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) +#define SET_TX_DESC_MAX_AGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) +#define SET_TX_DESC_NDPA_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) +#define SET_TX_DESC_AMPDU_MAX_TIME_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) + +// Dword 4 +#define SET_TX_DESC_TX_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) +#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) +#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) +#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) +#define SET_TX_DESC_DATA_RETRY_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) +#define SET_TX_DESC_RTS_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) + + +// Dword 5 +#define SET_TX_DESC_DATA_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) +#define SET_TX_DESC_DATA_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) +#define SET_TX_DESC_DATA_BW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) +#define SET_TX_DESC_DATA_LDPC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) +#define SET_TX_DESC_DATA_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) +#define SET_TX_DESC_CTROL_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) +#define SET_TX_DESC_RTS_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) +#define SET_TX_DESC_RTS_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) + + +// Dword 6 +#define SET_TX_DESC_SW_DEFINE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) +#define SET_TX_DESC_ANTSEL_A_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) +#define SET_TX_DESC_ANTSEL_B_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value) +#define SET_TX_DESC_ANTSEL_C_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value) +#define SET_TX_DESC_ANTSEL_D_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) + +// Dword 7 +#if(DEV_BUS_TYPE == RT_PCI_INTERFACE) +#define SET_TX_DESC_TX_BUFFER_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) +#else +#define SET_TX_DESC_TX_DESC_CHECKSUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) +#endif +#define SET_TX_DESC_USB_TXAGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) +#if(DEV_BUS_TYPE == RT_SDIO_INTERFACE) +#define SET_TX_DESC_SDIO_TXSEQ_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) +#endif + +// Dword 8 +#define SET_TX_DESC_HWSEQ_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) + +// Dword 9 +#define SET_TX_DESC_SEQ_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) + +// Dword 10 +#define SET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value) + + +// Dword 11 +#define SET_TX_DESC_NEXT_DESC_ADDRESS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value) + + +#define SET_EARLYMODE_PKTNUM_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) +#define SET_EARLYMODE_LEN0_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) +#define SET_EARLYMODE_LEN1_1_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) +#define SET_EARLYMODE_LEN1_2_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) +#define SET_EARLYMODE_LEN2_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) +#define SET_EARLYMODE_LEN3_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) + +#endif +//----------------------------------------------------------- +// +// Rate +// +//----------------------------------------------------------- +// CCK Rates, TxHT = 0 +#define DESC8723B_RATE1M 0x00 +#define DESC8723B_RATE2M 0x01 +#define DESC8723B_RATE5_5M 0x02 +#define DESC8723B_RATE11M 0x03 + +// OFDM Rates, TxHT = 0 +#define DESC8723B_RATE6M 0x04 +#define DESC8723B_RATE9M 0x05 +#define DESC8723B_RATE12M 0x06 +#define DESC8723B_RATE18M 0x07 +#define DESC8723B_RATE24M 0x08 +#define DESC8723B_RATE36M 0x09 +#define DESC8723B_RATE48M 0x0a +#define DESC8723B_RATE54M 0x0b + +// MCS Rates, TxHT = 1 +#define DESC8723B_RATEMCS0 0x0c +#define DESC8723B_RATEMCS1 0x0d +#define DESC8723B_RATEMCS2 0x0e +#define DESC8723B_RATEMCS3 0x0f +#define DESC8723B_RATEMCS4 0x10 +#define DESC8723B_RATEMCS5 0x11 +#define DESC8723B_RATEMCS6 0x12 +#define DESC8723B_RATEMCS7 0x13 +#define DESC8723B_RATEMCS8 0x14 +#define DESC8723B_RATEMCS9 0x15 +#define DESC8723B_RATEMCS10 0x16 +#define DESC8723B_RATEMCS11 0x17 +#define DESC8723B_RATEMCS12 0x18 +#define DESC8723B_RATEMCS13 0x19 +#define DESC8723B_RATEMCS14 0x1a +#define DESC8723B_RATEMCS15 0x1b +#define DESC8723B_RATEVHTSS1MCS0 0x2c +#define DESC8723B_RATEVHTSS1MCS1 0x2d +#define DESC8723B_RATEVHTSS1MCS2 0x2e +#define DESC8723B_RATEVHTSS1MCS3 0x2f +#define DESC8723B_RATEVHTSS1MCS4 0x30 +#define DESC8723B_RATEVHTSS1MCS5 0x31 +#define DESC8723B_RATEVHTSS1MCS6 0x32 +#define DESC8723B_RATEVHTSS1MCS7 0x33 +#define DESC8723B_RATEVHTSS1MCS8 0x34 +#define DESC8723B_RATEVHTSS1MCS9 0x35 +#define DESC8723B_RATEVHTSS2MCS0 0x36 +#define DESC8723B_RATEVHTSS2MCS1 0x37 +#define DESC8723B_RATEVHTSS2MCS2 0x38 +#define DESC8723B_RATEVHTSS2MCS3 0x39 +#define DESC8723B_RATEVHTSS2MCS4 0x3a +#define DESC8723B_RATEVHTSS2MCS5 0x3b +#define DESC8723B_RATEVHTSS2MCS6 0x3c +#define DESC8723B_RATEVHTSS2MCS7 0x3d +#define DESC8723B_RATEVHTSS2MCS8 0x3e +#define DESC8723B_RATEVHTSS2MCS9 0x3f + + +#define RX_HAL_IS_CCK_RATE_8723B(pDesc)\ + (GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE1M ||\ + GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE2M ||\ + GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE5_5M ||\ + GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE11M) + + +void rtl8195a_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem); +void rtl8195a_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); + +s32 rtl8195ab_init_xmit_priv(PADAPTER padapter); +void rtl8195ab_free_xmit_priv(PADAPTER padapter); +s32 rtl8195ab_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe); +s32 rtl8195ab_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe); +s32 rtl8195ab_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); +void rtl8195ab_xmitframe_resume(_adapter *padapter); +u32 GetDmaTxbdIdx(u32 ff_hwaddr); +struct xmit_buf * rtl8195a_dequeue_xmitbuf(struct rtw_tx_ring *ring); +BOOLEAN FreeXimtBuf(struct xmit_buf *pxmitbuf); +u8 check_tx_desc_resource(_adapter *padapter, int prio); + + +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_intf.c b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_intf.c new file mode 100644 index 0000000..4bbb072 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_intf.c @@ -0,0 +1,493 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _GSPI_INTF_C_ + +#include + +#ifdef CONFIG_GSPI_HCI + +struct dvobj_priv *gspi_dvobj_init(void) +{ +// int status = _FAIL; + struct dvobj_priv *dvobj = NULL; + PGSPI_DATA pgspi_data; + +_func_enter_; + + dvobj = (struct dvobj_priv*)rtw_zmalloc(sizeof(*dvobj)); + if (NULL == dvobj) { + goto exit; + } + + pgspi_data = &dvobj->intf_data; + + rtw_mutex_init(&pgspi_data->spi_mutex); + //pgspi_data->block_transfer_len = 512; //512 blocks r/w is not required for GSPI interface + //pgspi_data->tx_block_mode = 0; + //pgspi_data->rx_block_mode = 0; + +// status = _SUCCESS; + +#if 0 +free_dvobj: + if (status != _SUCCESS && dvobj) { + rtw_mfree((u8*)dvobj, sizeof(*dvobj)); + dvobj = NULL; + } +#endif +exit: +_func_exit_; + + return dvobj; +} + +void gspi_dvobj_deinit(struct dvobj_priv *dvobj) +{ +//TODO +// struct dvobj_priv *dvobj = spi_get_drvdata(spi); + +_func_enter_; +//TODO +// spi_set_drvdata(spi, NULL); + if (dvobj) { +//TODO +// gspi_deinit(dvobj); + rtw_mutex_free(&dvobj->intf_data.spi_mutex); + rtw_mfree((u8*)dvobj, sizeof(*dvobj)); + } + +_func_exit_; +} + +s32 gspi_dvobj_xmit_mgnt(_adapter * padapter, struct xmit_frame *pmgntframe) +{ + s32 ret = _SUCCESS; + struct pkt_attrib *pattrib; + struct xmit_buf *pxmitbuf; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + u8 *pframe = NULL; + + RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("+rtw_xmit_mgnt()\n")); + + pattrib = &pmgntframe->attrib; + pxmitbuf = pmgntframe->pxmitbuf; + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + rtw_hal_update_txdesc(padapter, pmgntframe, pmgntframe->buf_addr); + + pxmitbuf->len = TXDESC_SIZE + pattrib->last_txcmdsz; + //pxmitbuf->pg_num = (pxmitbuf->len + 127)/128; // 128 is tx page size + //pxmitbuf->ptail = pmgntframe->buf_addr + pxmitbuf->len; + pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pmgntframe); + + rtw_count_tx_stats(padapter, pmgntframe, pattrib->last_txcmdsz); + + //RT_TRACE(_module_rtl871x_xmit_c_, _drv_always_, ("+rtw_xmit_mgnt(): type=%d\n", GetFrameSubType(pframe))); + if(GetFrameSubType(pframe)==WIFI_BEACON) //dump beacon directly + { +//When using dedicated xmit frame for issue bcn on ap mode +//free xmit frame for bcn reserved page on station mode - Alex Fang +#if USE_DEDICATED_BCN_TX + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) { + rtw_free_xmitframe(pxmitpriv, pmgntframe); + pxmitbuf->priv_data = NULL; + } + rtw_write_port(padapter, ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr), pxmitbuf->len, pxmitbuf->pbuf); + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); +#else + rtw_free_xmitframe(pxmitpriv, pmgntframe); + pxmitbuf->priv_data = NULL; + rtw_xmit_xmitbuf(padapter, pxmitbuf); +#endif + } + else + { + rtw_free_xmitframe(pxmitpriv, pmgntframe); + pxmitbuf->priv_data = NULL; + rtw_xmit_xmitbuf(padapter, pxmitbuf); + } + + if (ret != _SUCCESS) + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN); + + RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("-rtw_xmit_mgnt\n")); + return ret; +} + +//#include +s32 gspi_dvobj_xmit_data(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + _irqL irql; + s32 err; + +#ifdef CONFIG_80211N_HT + if ((pxmitframe->frame_tag == DATA_FRAMETAG) && + (pxmitframe->attrib.ether_type != 0x0806) && + (pxmitframe->attrib.ether_type != 0x888e) && + (pxmitframe->attrib.dhcp_pkt != 1)) + { + if (padapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE) + rtw_issue_addbareq_cmd(padapter, pxmitframe); + } +#endif + +#if USE_SKB_AS_XMITBUF + rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); +#endif + + rtw_enter_critical_bh(&pxmitpriv->lock, &irql); +#if 1 //FIX_XMITFRAME_FAULT, move from rtw_xmit(). +#ifdef CONFIG_AP_MODE + if(xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) + { + rtw_exit_critical_bh(&pxmitpriv->lock, &irql); + return 1; + } +#endif +#endif + err = rtw_xmitframe_enqueue(padapter, pxmitframe); + rtw_exit_critical_bh(&pxmitpriv->lock, &irql); + + if (err != _SUCCESS) { + RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmit_data(): enqueue xmitframe fail\n")); + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + // Trick, make the statistics correct + pxmitpriv->tx_pkts--; + pxmitpriv->tx_drop++; + return _TRUE; + } + + rtw_count_tx_stats(padapter, pxmitframe, pxmitframe->attrib.last_txcmdsz); +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->adapter_type > PRIMARY_ADAPTER){ + padapter = padapter->pbuddy_adapter; + } +#endif + + rtw_wakeup_task(&padapter->xmitThread); + + return _FALSE; +} + +const struct host_ctrl_intf_ops hci_ops = { + gspi_dvobj_init, + gspi_dvobj_deinit, + NULL, + NULL +}; + + +//TODO +#if 0 + +unsigned int oob_irq; +static irqreturn_t spi_interrupt_thread(int irq, void *data) +{ + struct dvobj_priv *dvobj; + PGSPI_DATA pgspi_data; + + + dvobj = (struct dvobj_priv*)data; + pgspi_data = &dvobj->intf_data; + + //spi_int_hdl(padapter); + if (pgspi_data->priv_wq) + queue_delayed_work(pgspi_data->priv_wq, &pgspi_data->irq_work, 0); + + return IRQ_HANDLED; +} + +static u8 gspi_alloc_irq(struct dvobj_priv *dvobj) +{ + PGSPI_DATA pgspi_data; + struct spi_device *spi; + int err; + + + pgspi_data = &dvobj->intf_data; + spi = pgspi_data->func; + + err = request_irq(oob_irq, spi_interrupt_thread, + IRQF_TRIGGER_FALLING,//IRQF_TRIGGER_HIGH;//|IRQF_ONESHOT, + DRV_NAME, dvobj); + //err = request_threaded_irq(oob_irq, NULL, spi_interrupt_thread, + // IRQF_TRIGGER_FALLING, + // DRV_NAME, dvobj); + if (err < 0) { + DBG_871X("Oops: can't allocate irq %d err:%d\n", oob_irq, err); + goto exit; + } + enable_irq_wake(oob_irq); + disable_irq(oob_irq); + +exit: + return err?_FAIL:_SUCCESS; +} + +#endif //#if 0 +//TODO +#if 0 + +static void spi_irq_work(void *data) +{ + struct delayed_work *dwork; + PGSPI_DATA pgspi; + struct dvobj_priv *dvobj; + + + dwork = container_of(data, struct delayed_work, work); + pgspi = container_of(dwork, GSPI_DATA, irq_work); + + dvobj = spi_get_drvdata(pgspi->func); + if (!dvobj->if1) { + DBG_871X("%s if1 == NULL !!\n", __FUNCTION__); + return; + } + spi_int_hdl(dvobj->if1); +} + +#endif //#if 0 + + +//TODO +#if 0 + +static int rtw_gspi_suspend(struct spi_device *spi, pm_message_t mesg) +{ + struct dvobj_priv *dvobj = spi_get_drvdata(spi); + PADAPTER padapter = (_adapter *)dvobj->if1; + struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct net_device *pnetdev = padapter->pnetdev; + int ret = 0; + + u32 start_time = rtw_get_current_time(); + + _func_enter_; + + DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); + + pwrpriv->bInSuspend = _TRUE; + + while (pwrpriv->bips_processing == _TRUE) + rtw_msleep_os(1); + + if((!padapter->bup) || (padapter->bDriverStopped)||(padapter->bSurpriseRemoved)) + { + DBG_871X("%s bup=%d bDriverStopped=%d bSurpriseRemoved = %d\n", __FUNCTION__ + ,padapter->bup, padapter->bDriverStopped,padapter->bSurpriseRemoved); + goto exit; + } + + rtw_cancel_all_timer(padapter); + LeaveAllPowerSaveMode(padapter); + + //padapter->net_closed = _TRUE; + //s1. + if(pnetdev) + { + netif_carrier_off(pnetdev); + rtw_netif_stop_queue(pnetdev); + } +#ifdef CONFIG_WOWLAN + padapter->pwrctrlpriv.bSupportWakeOnWlan=_TRUE; +#else + //s2. + //s2-1. issue rtw_disassoc_cmd to fw + disconnect_hdl(padapter, NULL); + //rtw_disassoc_cmd(padapter); +#endif + +#ifdef CONFIG_LAYER2_ROAMING_RESUME + if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED) ) + { + DBG_871X("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n",__FUNCTION__, + pmlmepriv->cur_network.network.Ssid.Ssid, + MAC_ARG(pmlmepriv->cur_network.network.MacAddress), + pmlmepriv->cur_network.network.Ssid.SsidLength, + pmlmepriv->assoc_ssid.SsidLength); + + pmlmepriv->to_roaming = 1; + } +#endif + + //s2-2. indicate disconnect to os + rtw_indicate_disconnect(padapter); + //s2-3. + rtw_free_assoc_resources(padapter, 1); + + //s2-4. + rtw_free_network_queue(padapter, _TRUE); + + rtw_led_control(padapter, LED_CTL_POWER_OFF); + + rtw_dev_unload(padapter); + + if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) + rtw_indicate_scan_done(padapter, 1); + + if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) + rtw_indicate_disconnect(padapter); + + // interface deinit + gspi_deinit(dvobj); + RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("%s: deinit GSPI complete!\n", __FUNCTION__)); + + rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_OFF); + rtw_mdelay_os(1); +exit: + DBG_871X("<=== %s return %d.............. in %dms\n", __FUNCTION__ + , ret, rtw_get_passing_time_ms(start_time)); + + _func_exit_; + return ret; +} + +extern int pm_netdev_open(struct net_device *pnetdev,u8 bnormal); +int rtw_resume_process(_adapter *padapter) +{ + struct net_device *pnetdev; + struct pwrctrl_priv *pwrpriv; + u8 is_pwrlock_hold_by_caller; + u8 is_directly_called_by_auto_resume; + int ret = 0; + u32 start_time = rtw_get_current_time(); + + _func_enter_; + + DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); + + rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_ON); + rtw_mdelay_os(1); + + rtw_set_chip_endian(adapter); + + if (padapter) { + pnetdev = padapter->pnetdev; + pwrpriv = &padapter->pwrctrlpriv; + } else { + ret = -1; + goto exit; + } + + // interface init + if (gspi_init(adapter_to_dvobj(padapter)) != _SUCCESS) + { + ret = -1; + RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: initialize SDIO Failed!!\n", __FUNCTION__)); + goto exit; + } + rtw_hal_disable_interrupt(padapter); + if (gspi_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) + { + ret = -1; + RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: gspi_alloc_irq Failed!!\n", __FUNCTION__)); + goto exit; + } + + rtw_reset_drv_sw(padapter); + pwrpriv->bkeepfwalive = _FALSE; + + DBG_871X("bkeepfwalive(%x)\n",pwrpriv->bkeepfwalive); + if(pm_netdev_open(pnetdev,_TRUE) != 0) { + ret = -1; + goto exit; + } + + netif_device_attach(pnetdev); + netif_carrier_on(pnetdev); + + if( padapter->pid[1]!=0) { + DBG_871X("pid[1]:%d\n",padapter->pid[1]); + rtw_signal_process(padapter->pid[1], SIGUSR2); + } + + #ifdef CONFIG_LAYER2_ROAMING_RESUME + rtw_roaming(padapter, NULL); + #endif + + #ifdef CONFIG_RESUME_IN_WORKQUEUE + rtw_unlock_suspend(); + #endif //CONFIG_RESUME_IN_WORKQUEUE + + pwrpriv->bInSuspend = _FALSE; +exit: + DBG_871X("<=== %s return %d.............. in %dms\n", __FUNCTION__ + , ret, rtw_get_passing_time_ms(start_time)); + + _func_exit_; + + return ret; +} + +static int rtw_gspi_resume(struct spi_device *spi) +{ + struct dvobj_priv *dvobj = spi_get_drvdata(spi); + PADAPTER padapter = (_adapter *)dvobj->if1; + struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; + int ret = 0; + + + DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); + + if(pwrpriv->bInternalAutoSuspend ){ + ret = rtw_resume_process(padapter); + } else { +#ifdef CONFIG_RESUME_IN_WORKQUEUE + rtw_resume_in_workqueue(pwrpriv); +#elif defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) + if(rtw_is_earlysuspend_registered(pwrpriv)) { + //jeff: bypass resume here, do in late_resume + pwrpriv->do_late_resume = _TRUE; + } else { + ret = rtw_resume_process(padapter); + } +#else // Normal resume process + ret = rtw_resume_process(padapter); +#endif //CONFIG_RESUME_IN_WORKQUEUE + } + + DBG_871X("<======== %s return %d\n", __FUNCTION__, ret); + return ret; + +} + + +static struct spi_driver rtw_spi_drv = { + .probe = rtw_drv_probe, + .remove = rtw_dev_remove, + .suspend = rtw_gspi_suspend, + .resume = rtw_gspi_resume, + .driver = { + .name = "wlan_spi", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + } + +}; + +#endif //#if 0 +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_io.c b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_io.c new file mode 100644 index 0000000..f042c3f --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_io.c @@ -0,0 +1,566 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + *******************************************************************************/ +#define _GSPI_IO_C_ + +#include + +#ifdef CONFIG_GSPI_HCI + +u8 spi_read8(struct dvobj_priv *pdvobj, u32 addr, s32 *err); +u16 spi_read16(struct dvobj_priv *pdvobj, u32 addr, s32 *err); +u32 spi_read32(struct dvobj_priv *pdvobj, u32 addr, s32 *err); +s32 spi_write8(struct dvobj_priv *pdvobj, u32 addr, u8 buf, s32 *err); +s32 spi_write16(struct dvobj_priv *pdvobj, u32 addr, u16 buf, s32 *err); +s32 spi_write32(struct dvobj_priv *pdvobj, u32 addr, u32 buf, s32 *err); + +static u32 rtw_spi_transfer( + struct dvobj_priv *pdvobj, + bool pool, + u8* buf, + u32 buf_len) +{ + _mutex *spi_mutex; + u32 ret_value = _SUCCESS; + + spi_mutex = &(pdvobj->intf_data.spi_mutex); + + rtw_enter_critical_mutex(spi_mutex, NULL); + if(!WLAN_BSP_Transfer(buf, buf_len)) + ret_value = _FAIL; + rtw_exit_critical_mutex(spi_mutex, NULL); + + return ret_value; +} +static int addr_convert(u32 addr) +{ + u32 domain_id = 0 ; + u32 temp_addr = addr&0xffff0000; + + if (temp_addr == 0 ) { + domain_id = WLAN_IOREG_DOMAIN; + return domain_id; + } + + switch (temp_addr) { + case WLAN_LOCAL_OFFSET: + domain_id = SPI_LOCAL_DOMAIN; + break; + case WLAN_IOREG_OFFSET: + domain_id = WLAN_IOREG_DOMAIN; + break; + case FW_FIFO_OFFSET: + domain_id = FW_FIFO_DOMAIN; + break; + case TX_HIQ_OFFSET: + domain_id = TX_HIQ_DOMAIN; + break; + case TX_MIQ_OFFSET: + domain_id = TX_MIQ_DOMAIN; + break; + case TX_LOQ_OFFSET: + domain_id = TX_LOQ_DOMAIN; + break; + case RX_RXOFF_OFFSET: + domain_id = RX_RXFIFO_DOMAIN; + break; + default: + break; + } + + return domain_id; +} + +/* + * Description: + * Translate sdio fifo address to Domain ID in each WLAN FIFO + */ +static u32 hwaddr2txfifo(u32 addr) +{ + u32 fifo_domain_id; + switch (addr) + { + case WLAN_TX_HIQ_DEVICE_ID: + fifo_domain_id = TX_HIQ_DOMAIN; + break; + + case WLAN_TX_MIQ_DEVICE_ID: + fifo_domain_id = TX_MIQ_DOMAIN; + break; + + case WLAN_TX_LOQ_DEVICE_ID: + fifo_domain_id = TX_LOQ_DOMAIN; + break; + default: + fifo_domain_id = TX_LOQ_DOMAIN; + break; + } + + return fifo_domain_id; +} + +static u32 buf_endian_reverse(u32 src) +{ + return (((src&0x000000ff)<<24)|((src&0x0000ff00)<<8)| + ((src&0x00ff0000)>>8)|((src&0xff000000)>>24)); +} + +// +// Description: +// Query SDIO Local register to query current the number of Free TxPacketBuffer page. +// +// Assumption: +// 1. Running at PASSIVE_LEVEL +// 2. RT_TX_SPINLOCK is NOT acquired. +// +// Created by Roger, 2011.01.28. +// +#ifdef CONFIG_RTL8188F +u8 spi_query_status_info(struct dvobj_priv *pdvobj) +{ + pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX] = spi_read8(pdvobj, LOCAL_REG_FREE_TXPG, NULL); + pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX] =spi_read8(pdvobj, LOCAL_REG_FREE_TXPG+2, NULL); + pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX] = spi_read8(pdvobj, LOCAL_REG_FREE_TXPG+4, NULL); + pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] = spi_read8(pdvobj, LOCAL_REG_FREE_TXPG+6, NULL); + RT_TRACE(_module_hci_ops_c_, _drv_notice_, + ("%s: Free page for HIQ(%x),MIDQ(%x),LOWQ(%x),PUBQ(%x)\n", + __FUNCTION__, + pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX])); + //_exit_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql); + + return _TRUE; +} +#else +u8 spi_query_status_info(struct dvobj_priv *pdvobj) +{ + u32 NumOfFreePage; + + NumOfFreePage = spi_read32(pdvobj, LOCAL_REG_FREE_TXPG, NULL); + +// _enter_critical_bh(&pdvobj->SdioTxFIFOFreePageLock, &irql); + rtw_memcpy(pdvobj->SdioTxFIFOFreePage, &NumOfFreePage, 4); + + RT_TRACE(_module_hci_ops_c_, _drv_notice_, + ("%s: Free page for HIQ(%x),MIDQ(%x),LOWQ(%x),PUBQ(%x)\n", + __FUNCTION__, + pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX])); +// _exit_critical_bh(&pdvobj->SdioTxFIFOFreePageLock, &irql); + + return _TRUE; +} + +#endif +static void spi_get_status_info(struct dvobj_priv *pdvobj, unsigned char *status) +{ +#ifdef CONFIG_MEMORY_ACCESS_ALIGNED + u32 local_status[2]; + u8 *pstatus = (u8*)(&local_status[0]); + + memcpy(pstatus, status, GSPI_STATUS_LEN); +#else + u8 *pstatus = status; +#endif + +#ifdef CONFIG_RTL8188F + pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] = GET_STATUS_PUB_PAGE_NUM(pstatus)*2; +#else + pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] = GET_STATUS_PUB_PAGE_NUM(pstatus); +#endif + + pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX] = GET_STATUS_HI_PAGE_NUM(pstatus); + pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX] = GET_STATUS_MID_PAGE_NUM(pstatus); + pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX] = GET_STATUS_LOW_PAGE_NUM(pstatus); + + RT_TRACE(_module_hci_ops_c_, _drv_dump_, + ("%s: Free page for HIQ(%x),MIDQ(%x),LOWQ(%x),PUBQ(%x)\n", + __FUNCTION__, + pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX])); +} + +static int spi_read_write_reg(struct dvobj_priv *pdvobj, int write_flag, u32 addr, char * buf, int len, u32 eddien) +{ + int fun = 1, domain_id = 0x0; //LOCAL + unsigned int cmd = 0 ; + int byte_en = 0 ;//,i = 0 ; + int ret = 1; + unsigned char status[8] = {0}; + unsigned int data_tmp = 0; + u32 force_bigendian = eddien; + + u32 spi_buf[4] = {0}; + bool polled = TRUE; + + if (len!=1 && len!=2 && len != 4) { + return -1; + } + + domain_id = addr_convert(addr); + + addr &= 0x7fff; + len &= 0xff; + if (write_flag) //write register + { + int remainder = addr % 4; + u32 val32 = *(u32 *)buf; + switch(len) { + case 1: + byte_en = (0x1 << remainder); + data_tmp = (val32& 0xff)<< (remainder*8); + break; + case 2: + byte_en = (0x3 << remainder); + data_tmp = (val32 & 0xffff)<< (remainder*8); + break; + case 4: + byte_en = 0xf; + data_tmp = val32 & 0xffffffff; + break; + default: + byte_en = 0xf; + data_tmp = val32 & 0xffffffff; + break; + } + } + else //read register + { + switch(len) { + case 1: + byte_en = 0x1; + break; + case 2: + byte_en = 0x3; + break; + case 4: + byte_en = 0xf; + break; + default: + byte_en = 0xf; + break; + } + + if(domain_id == SPI_LOCAL_DOMAIN) + byte_en = 0; + } + + //addr = 0xF0 4byte: 0x2800f00f + REG_LEN_FORMAT(&cmd, byte_en); + REG_ADDR_FORMAT(&cmd, (addr&0xfffffffc)); + REG_DOMAIN_ID_FORMAT(&cmd, domain_id); + REG_FUN_FORMAT(&cmd, fun); + REG_RW_FORMAT(&cmd, write_flag); + + if (force_bigendian) { + cmd = buf_endian_reverse(cmd); + } + + if (!write_flag && (domain_id!= RX_RXFIFO_DOMAIN)) { + u32 read_data = 0; + + rtw_memset(spi_buf, 0x00, sizeof(spi_buf)); + + spi_buf[0] = cmd; + spi_buf[1] = 0; + spi_buf[2] = 0; + spi_buf[3] = 0; + + rtw_spi_transfer(pdvobj, polled, (u8*)spi_buf, sizeof(spi_buf)); + + rtw_memcpy(status, (u8 *) &spi_buf[1], sizeof(status)); + read_data = EF4Byte(spi_buf[3]); + + //add for 8810 +#ifdef CONFIG_BIG_ENDIAN + if (!force_bigendian) + read_data = buf_endian_reverse(read_data); +#else + if (force_bigendian) + read_data = buf_endian_reverse(read_data); +#endif + *(u32*)buf = read_data; + } else if (write_flag ) { + +#ifdef CONFIG_BIG_ENDIAN + if (!force_bigendian) + data_tmp = buf_endian_reverse(data_tmp); +#else + if (force_bigendian) + data_tmp = buf_endian_reverse(data_tmp); +#endif + + spi_buf[0] = cmd; + spi_buf[1] = data_tmp; + spi_buf[2] = 0; + spi_buf[3] = 0; + + rtw_spi_transfer(pdvobj, polled, (u8*)spi_buf, sizeof(spi_buf)); + + rtw_memcpy(status, (u8 *) &spi_buf[2], sizeof(status)); + } + + spi_get_status_info(pdvobj, (unsigned char*)status); + + return ret; +} + +static int spi_io_priv(struct dvobj_priv *pdvobj) +{ + //struct dvobj_priv *pdvobj = &Adapter->dvobjpriv; + + return _SUCCESS; +} + +static int spi_write8_endian(struct dvobj_priv *pdvobj, u32 addr, u32 buf, u32 big) +{ + return spi_read_write_reg(pdvobj,1,addr,(char *)&buf,1, big); +} + +u8 spi_read8(struct dvobj_priv *pdvobj, u32 addr, s32 *err) +{ + u32 ret = 0; + int val32 = 0 , remainder = 0 ; + s32 _err = 0; + + _err = spi_read_write_reg(pdvobj,0,addr&0xFFFFFFFC,(char *)&ret,4,0); + remainder = addr % 4; + val32 = ret; + val32 = (val32& (0xff<< (remainder<<3)))>>(remainder<<3); + + if (err) + *err = _err; + + return (u8)val32; + +} + +u16 spi_read16(struct dvobj_priv *pdvobj, u32 addr, s32 *err) +{ + u32 ret = 0; + int val32 = 0 , remainder = 0 ; + s32 _err = 0; + + _err = spi_read_write_reg(pdvobj,0,addr&0xFFFFFFFC,(char *)&ret,4,0); + remainder = addr % 4; + val32 = ret; + val32 = (val32& (0xffff<< (remainder<<3)))>>(remainder<<3); + + if (err) + *err = _err; + + return (u16)val32; +} + +u32 spi_read32(struct dvobj_priv *pdvobj, u32 addr, s32 *err) +{ + u32 ret = 0; + s32 _err = 0; + + _err = spi_read_write_reg(pdvobj,0,addr&0xFFFFFFFC,(char *)&ret,4,0); + if (err) + *err = _err; + + return ret; +} + +s32 spi_write8(struct dvobj_priv *pdvobj, u32 addr, u8 buf, s32 *err) +{ + int ret = 0; + + ret = spi_read_write_reg(pdvobj,1,addr,(char *)&buf,1,0); + if (err) + *err = ret; + return ret; +} + +s32 spi_write16(struct dvobj_priv *pdvobj, u32 addr, u16 buf, s32 *err) +{ + int ret = 0; + + ret = spi_read_write_reg(pdvobj,1,addr,(char *)&buf,2,0); + if (err) + *err = ret; + return ret; +} + +s32 spi_write32(struct dvobj_priv *pdvobj, u32 addr, u32 buf, s32 *err) +{ + int ret = 0; + + ret = spi_read_write_reg(pdvobj, 1,addr,(char *)&buf,4,0); + if (err) + *err = ret; + return ret; +} + +static int spi_read_rx_fifo(struct dvobj_priv *pdvobj, u32 addr, u8 *buf, u32 len, struct fifo_more_data *pmore_data) +{ + int fun = 1, domain_id = RX_RXFIFO_DOMAIN; + unsigned int cmd = 0; + unsigned char *status = buf + len; + u8 *spi_buf = (u8 *) (buf - GSPI_CMD_LEN); + int spi_buf_len = 0; + bool polled = TRUE; + bool use_alloc = FALSE; + u32 max_skb_len = 0; + +#ifndef CONFIG_DONT_CARE_TP + max_skb_len = MAX_SKB_BUF_SIZE; +#else + max_skb_len = MAX_RX_SKB_BUF_SIZE; +#endif + + if(((GSPI_CMD_LEN + len + GSPI_STATUS_LEN) > max_skb_len) || (!buf)) { + #if !defined(CONFIG_MP_INCLUDED) || !defined(CONFIG_MP_IWPRIV_SUPPORT) // Cloud 2013/09/06 + DBG_871X("data len=%d, MAX_SKB_BUF_SIZE(%d) is not enough, change to dynamic alloc\n", len, max_skb_len); + #endif + use_alloc = TRUE; + spi_buf_len = GSPI_CMD_LEN + len + GSPI_STATUS_LEN; + spi_buf = rtw_malloc(spi_buf_len); + + if(spi_buf == NULL) { + DBG_871X("Failed to alloc %d bytes\n", len); + return _FAIL; + } + else { + buf = spi_buf + GSPI_CMD_LEN; + status = spi_buf + GSPI_CMD_LEN + len; + } + } + + FIFO_LEN_FORMAT(&cmd, len); //TX Agg len + FIFO_DOMAIN_ID_FORMAT(&cmd, domain_id); + FIFO_FUN_FORMAT(&cmd, fun); + FIFO_RW_FORMAT(&cmd, 0); //read + + rtw_memset(status, 0x00, GSPI_STATUS_LEN); + rtw_memset(buf, 0x0, len); + +#ifdef CONFIG_MEMORY_ACCESS_ALIGNED + memcpy(spi_buf, (u8 *)&cmd, sizeof(int)); +#else + *((u32 *) spi_buf) = cmd; +#endif + + rtw_spi_transfer(pdvobj, polled, (u8 *) spi_buf, GSPI_CMD_LEN + len + GSPI_STATUS_LEN); + + spi_get_status_info(pdvobj, status); + pmore_data->more_data = GET_STATUS_HISR_LOW8BIT(status) & BIT(0); + pmore_data->len = GET_STATUS_RX_LENGTH(status); + + if(use_alloc) { + //Drop the data + rtw_mfree(spi_buf, spi_buf_len); + return _FAIL; + } + + return _SUCCESS; +} + +static int spi_write_tx_fifo(struct dvobj_priv *pdvobj, u32 addr, u8 *buf, u32 len) +{ + int fun = 1; //TX_HIQ_FIFO + unsigned int cmd = 0; + unsigned char *status = buf + len; + u8 *spi_buf = (u8 *) (buf - GSPI_CMD_LEN); + u32 page_num = 0; + u32 wait_num = 100; + bool polled = TRUE; + u32 fifo = 0; + +_func_enter_; + fifo = hwaddr2txfifo(addr); + + spi_query_status_info(pdvobj); + if (fifo == TX_HIQ_DOMAIN) + page_num = pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX]; + else if (fifo == TX_LOQ_DOMAIN) + page_num = pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX]; + else + page_num = pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX]; + + while (page_num + pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] < 15) { + DBG_871X("Oops: spi_write_tx_fifo(): page_num is %d, padapter->pub_page is %d, wait_num is %d", + page_num, pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX], wait_num); + + rtw_msleep_os(1); + //rtw_udelay_os(20); + spi_read32(pdvobj, 0x608, NULL); + + if (fifo == TX_HIQ_DOMAIN) + page_num = pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX]; + else if (fifo == TX_LOQ_DOMAIN) + page_num = pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX]; + else + page_num = pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX]; + + if (wait_num <= 2) { + DBG_871X("%s(): wait_num is <= 2 drop", __FUNCTION__); + return _FAIL; + } + wait_num --; + } + + FIFO_LEN_FORMAT(&cmd, len); //TX Agg len + FIFO_DOMAIN_ID_FORMAT(&cmd, fifo); + FIFO_FUN_FORMAT(&cmd, fun); + FIFO_RW_FORMAT(&cmd, (unsigned int) 1); //write + + //DBG_871X("%s(): len = %d\n", __FUNCTION__, len); + //RT_PRINT_DATA(_module_hal_xmit_c_, _drv_always_, "Tx:\n", buf, GSPI_CMD_LEN + len); + rtw_memset(status, 0x00, GSPI_STATUS_LEN); + +#ifdef CONFIG_MEMORY_ACCESS_ALIGNED + memcpy(spi_buf, (u8 *)&cmd, sizeof(int)); +#else + *((u32 *) spi_buf) = cmd; +#endif + + rtw_spi_transfer(pdvobj, polled, (u8 *) spi_buf, GSPI_CMD_LEN + len + GSPI_STATUS_LEN); + + spi_get_status_info(pdvobj, status); + +_func_exit_; + + return _SUCCESS; +} + +void spi_set_intf_ops(struct _io_ops *pops) +{ + pops->init_io_priv = &spi_io_priv; + pops->write8_endian = &spi_write8_endian; + + pops->_read8 = &spi_read8; + pops->_read16 = &spi_read16; + pops->_read32 = &spi_read32; + + pops->_write8 = &spi_write8; + pops->_write16 = &spi_write16; + pops->_write32 = &spi_write32; + + pops->read_rx_fifo = &spi_read_rx_fifo; + pops->write_tx_fifo = &spi_write_tx_fifo; +} +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_isr.c b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_isr.c new file mode 100644 index 0000000..741a879 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_isr.c @@ -0,0 +1,236 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + ******************************************************************************/ +#define _GSPI_ISR_C_ + +#include + +#ifdef CONFIG_GSPI_HCI + +extern struct recv_buf* rtw_recv_rxfifo(_adapter * padapter, u32 size, struct fifo_more_data* more_data); +u8 spi_read8(struct dvobj_priv *pdvobj, u32 addr, s32 *err); +u16 spi_read16(struct dvobj_priv *pdvobj, u32 addr, s32 *err); +u32 spi_read32(struct dvobj_priv *pdvobj, u32 addr, s32 *err); +s32 spi_write8(struct dvobj_priv *pdvobj, u32 addr, u8 buf, s32 *err); +s32 spi_write16(struct dvobj_priv *pdvobj, u32 addr, u16 buf, s32 *err); +s32 spi_write32(struct dvobj_priv *pdvobj, u32 addr, u32 buf, s32 *err); + +void spi_int_dpc(PADAPTER padapter, u32 sdio_hisr) +{ + struct dvobj_priv *pdvobj = padapter->dvobj; + +#ifdef CONFIG_LPS_LCLK + if (sdio_hisr & HCI_HISR_CPWM1) + { + struct reportpwrstate_parm report; + + report.state = spi_read8(pdvobj, LOCAL_REG_HCPWM1, NULL); + if(report.state == 0xEA) + report.state = PS_STATE_S0; + else + report.state = PS_STATE_S2; + cpwm_int_hdl(padapter, &report); + } +#endif + + if (sdio_hisr & HCI_HISR_TXERR) + { + u32 status; + + status = rtw_read32(padapter, REG_TXDMA_STATUS); + rtw_write32(padapter, REG_TXDMA_STATUS, status); + RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, status)); + } + +#ifdef CONFIG_INTERRUPT_BASED_TXBCN + + #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT + if (sdio_hisr & HCI_HISR_BCNERLY_INT) + #endif + #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR + if (sdio_hisr & (HCI_HISR_TXBCNOK|HCI_HISR_TXBCNERR)) + #endif + { + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + #if 0 //for debug + if (sdio_hisr & SDIO_HISR_BCNERLY_INT) + DBG_8192C("%s: SDIO_HISR_BCNERLY_INT\n", __func__); + + if (sdio_hisr & SDIO_HISR_TXBCNOK) + DBG_8192C("%s: SDIO_HISR_TXBCNOK\n", __func__); + + if (sdio_hisr & SDIO_HISR_TXBCNERR) { + u1Byte v422, v550, v419; + v422 = rtw_read8(padapter, 0x422); + v419 = rtw_read8(padapter, 0x419); + v550 = rtw_read8(padapter, 0x550); + + DBG_8192C("%s: SDIO_HISR_TXBCNERR 422=%02x, 419=%02x, 550=%02x\n", __func__, v422, v419, v550); + } + #endif + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) + { + //send_beacon(padapter); + if(pmlmepriv->update_bcn == _TRUE) + { + //tx_beacon_hdl(padapter, NULL); + set_tx_beacon_cmd(padapter); + } + } + +#if 0//def CONFIG_CONCURRENT_MODE + if(check_buddy_fwstate(padapter, WIFI_AP_STATE)) + { + //send_beacon(padapter); + if(padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE) + { + //tx_beacon_hdl(padapter, NULL); + set_tx_beacon_cmd(padapter->pbuddy_adapter); + } + } +#endif + } +#endif //CONFIG_INTERRUPT_BASED_TXBCN + + if (sdio_hisr & HCI_HISR_C2HCMD) + { + RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: C2H Command\n", __func__)); +//TODO +// rtw_c2h_wk_cmd(padapter); + } + + if (sdio_hisr & HCI_HISR_RX_REQUEST)// || sdio_hisr & SPI_HISR_RXFOVW) + { + struct recv_buf *precvbuf; + struct fifo_more_data more_data = {0}; + + //RT_TRACE(_module_hci_ops_c_,_drv_info_, ("%s: RX Request, size=%d\n", __func__, pdvobj->SdioRxFIFOSize)); + + sdio_hisr ^= HCI_HISR_RX_REQUEST; + + do { + more_data.more_data = 0; + more_data.len = 0; + + if (pdvobj->SdioRxFIFOSize == 0) + { + u16 val = 0; + s32 ret; + + RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s, %d, read RXFIFOsize again size=%d\n", __FUNCTION__, __LINE__, pdvobj->SdioRxFIFOSize)); + + val = spi_read16(pdvobj, LOCAL_REG_RX0_REQ_LEN_1_BYTE, &ret); + if (!ret) { + pdvobj->SdioRxFIFOSize = val; + RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: RX_REQUEST, read RXFIFOsize again size=%d\n", __func__, pdvobj->SdioRxFIFOSize)); + } else { + RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: RX_REQUEST, read RXFIFOsize ERROR!!\n", __func__)); + } + RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s, %d, read RXFIFOsize again size=%d\n", __FUNCTION__, __LINE__, pdvobj->SdioRxFIFOSize)); + } + + if (pdvobj->SdioRxFIFOSize != 0) + { +#ifdef RTL8723A_SDIO_LOOPBACK + sd_recv_loopback(padapter, pdvobj->SdioRxFIFOSize); +#else + if (sdio_hisr & HCI_HISR_RXFOVW) + RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s RXFOVW RX\n", __func__)); + + precvbuf = rtw_recv_rxfifo(padapter, pdvobj->SdioRxFIFOSize, &more_data); + if (precvbuf) + rtw_rxhandler(padapter, precvbuf); + + if (more_data.more_data) { + pdvobj->SdioRxFIFOSize = more_data.len; + } else { + pdvobj->SdioRxFIFOSize = 0; + } +#endif + //If Rx_request ISR is set, execute receive tasklet (sdio_hisr & SPI_HISR_RX_REQUEST) +#if defined(CONFIG_ISR_THREAD_MODE_INTERRUPT) && defined(CONFIG_RECV_TASKLET_THREAD) + rtw_wakeup_task(&padapter->recvtasklet_thread); +#endif + } + +#ifdef CONFIG_INTERRUPT_BASED_TXBCN +{ + //Prevent BCN update not realtime in ap mode - Alex Fang + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + if((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) && (pmlmepriv->update_bcn == _TRUE)) + break; +} +#endif + } while (more_data.more_data); +#ifdef PLATFORM_LINUX +#ifdef CONFIG_GSPI_HCI + tasklet_schedule(&padapter->recvpriv.recv_tasklet); +#endif +#endif + } +} + + +void spi_int_hdl(PADAPTER padapter) +{ + struct dvobj_priv *pdvobj = padapter->dvobj; + u32 sdio_hisr = 0; + s32 ret; + + if ((padapter->bDriverStopped == _TRUE) || + (padapter->bSurpriseRemoved == _TRUE)) + return; + + sdio_hisr = spi_read32(pdvobj, LOCAL_REG_HISR, &ret); + if (!ret) { + RT_TRACE(_module_hci_ops_c_, _drv_err_, ("%s: read SDIO_REG_HISR FAIL!!\n", __func__)); + return; + } + pdvobj->SdioRxFIFOSize = spi_read16(pdvobj, LOCAL_REG_RX0_REQ_LEN_1_BYTE, &ret); + + if (!ret) { + RT_TRACE(_module_hci_ops_c_, _drv_err_, ("%s: read SPI_REG_RX0_REQ_LEN FAIL!!\n", __func__)); + return; + } + + if (sdio_hisr & pdvobj->sdio_himr) + { + u32 v32; + + sdio_hisr &= pdvobj->sdio_himr; + + // clear HISR + v32 = sdio_hisr & MASK_SPI_HISR_CLEAR; + if (v32) { + spi_write32(pdvobj, LOCAL_REG_HISR, v32, &ret); + } + + spi_int_dpc(padapter, sdio_hisr); + } else { + RT_TRACE(_module_hci_ops_c_, _drv_err_, + ("%s: HISR(0x%08x) and HIMR(0x%08x) not match!\n", + __FUNCTION__, sdio_hisr, pdvobj->sdio_himr)); + if(sdio_hisr) + spi_write32(pdvobj, LOCAL_REG_HISR, sdio_hisr, &ret); + } +} + +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_spec.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_spec.h new file mode 100644 index 0000000..1018d94 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_spec.h @@ -0,0 +1,257 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + *******************************************************************************/ + +#ifndef __GSPI_SPEC_H__ +#define __GSPI_SPEC_H__ + + +#define SPI_LOCAL_DOMAIN 0x0 +#define WLAN_IOREG_DOMAIN 0x8 +#define FW_FIFO_DOMAIN 0x4 +#define TX_HIQ_DOMAIN 0xc +#define TX_MIQ_DOMAIN 0xd +#define TX_LOQ_DOMAIN 0xe +#define RX_RXFIFO_DOMAIN 0x1f + +//IO Bus domain address mapping +#define DEFUALT_OFFSET 0x0 +#define LOCAL_OFFSET 0x10250000 +#define SPI_LOCAL_OFFSET 0x10250000 +#define WLAN_IOREG_OFFSET 0x10260000 +#define FW_FIFO_OFFSET 0x10270000 +#define TX_HIQ_OFFSET 0x10310000 +#define TX_MIQ_OFFSET 0x1032000 +#define TX_LOQ_OFFSET 0x10330000 +#define RX_RXOFF_OFFSET 0x10340000 + +#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13] +#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13] +#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13] +#define WLAN_TX_EXQ_DEVICE_ID 3 // 0b[16], 011b[15:13] +#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13] +#define WLAN_IOREG_DEVICE_ID 8 // 1b[16] + +//SPI Tx Free Page Index +#define HI_QUEUE_IDX 0 +#define MID_QUEUE_IDX 1 +#define LOW_QUEUE_IDX 2 +#define PUBLIC_QUEUE_IDX 3 + +#define MAX_TX_QUEUE 3 // HIQ, MIQ and LOQ +#define MAX_RX_QUEUE 1 + +//SPI Local registers +#ifdef CONFIG_RTL8188F +#define SPI_REG_TX_CTRL 0x0000 // SPI Tx Control +#define SPI_REG_STATUS_RECOVERY 0x0004 +#define SPI_REG_INT_TIMEOUT 0x0006 +#define SPI_REG_HIMR 0x0014 // SPI Host Interrupt Mask +#define SPI_REG_HISR 0x0018 // SPI Host Interrupt Service Routine +#define SPI_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length +#define SPI_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page +#define SPI_REG_HTSFR_INFO 0x0030 // HTSF Informaion +#define SPI_REG_HCPWM1 0x0038 // HCI Current Power Mode 1 +#define SPI_REG_HCPWM2 0x003A // HCI Current Power Mode 2 +#define SPI_REG_HRPWM1 0x0080 // HCI Request Power Mode 1 need check for 8188f??? +#define SPI_REG_HPS_CLKR 0x0084 // HCI Power Save Clock +#define SPI_REG_HSUS_CTRL 0x0086 // SPI HCI Suspend Control +#else +#define SPI_REG_TX_CTRL 0x0000 // SPI Tx Control +#define SPI_REG_STATUS_RECOVERY 0x0004 +#define SPI_REG_INT_TIMEOUT 0x0006 +#define SPI_REG_HIMR 0x0014 // SPI Host Interrupt Mask +#define SPI_REG_HISR 0x0018 // SPI Host Interrupt Service Routine +#define SPI_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length +#define SPI_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page +#define SPI_REG_HCPWM1 0x0024 // HCI Current Power Mode 1 +#define SPI_REG_HCPWM2 0x0026 // HCI Current Power Mode 2 +#define SPI_REG_HTSFR_INFO 0x0030 // HTSF Informaion +#define SPI_REG_HRPWM1 0x0080 // HCI Request Power Mode 1 +#define SPI_REG_HRPWM2 0x0082 // HCI Request Power Mode 2 +#define SPI_REG_HPS_CLKR 0x0084 // HCI Power Save Clock +#define SPI_REG_HSUS_CTRL 0x0086 // SPI HCI Suspend Control +#define SPI_REG_HIMR_ON 0x0090 //SPI Host Extension Interrupt Mask Always +#define SPI_REG_HISR_ON 0x0091 //SPI Host Extension Interrupt Status Always +#define SPI_REG_CFG 0x00F0 //SPI Configuration Register +#endif + +#define LOCAL_REG_TX_CTRL (SPI_REG_TX_CTRL |SPI_LOCAL_OFFSET) +#define LOCAL_REG_STATUS_RECOVERY (SPI_REG_STATUS_RECOVERY |SPI_LOCAL_OFFSET) +#define LOCAL_REG_INT_TIMEOUT (SPI_REG_INT_TIMEOUT |SPI_LOCAL_OFFSET) +#define LOCAL_REG_HIMR (SPI_REG_HIMR |SPI_LOCAL_OFFSET) +#define LOCAL_REG_HISR (SPI_REG_HISR |SPI_LOCAL_OFFSET) +#define LOCAL_REG_RX0_REQ_LEN_1_BYTE (SPI_REG_RX0_REQ_LEN |SPI_LOCAL_OFFSET) +#define LOCAL_REG_FREE_TXPG (SPI_REG_FREE_TXPG |SPI_LOCAL_OFFSET) +#define LOCAL_REG_HRPWM1 (SPI_REG_HRPWM1 |SPI_LOCAL_OFFSET) +#define LOCAL_REG_HCPWM1 (SPI_REG_HCPWM1 |SPI_LOCAL_OFFSET) +#define LOCAL_REG_SUSPEND_NORMAL (SPI_REG_HSUS_CTRL|SPI_LOCAL_OFFSET) +#define HCI_HIMR_DISABLED 0 + +//SPI HIMR MASK diff with SDIO +#ifdef CONFIG_RTL8188F +#define HCI_HISR_RX_REQUEST BIT(0) +#define HCI_HISR_AVAL BIT(1) +#define HCI_HISR_TXERR BIT(2) +#define HCI_HISR_RXERR BIT(3) +#define HCI_HISR_TXFOVW BIT(4) +#define HCI_HISR_RXFOVW BIT(5) +#define HCI_HISR_TXBCNOK BIT(6) +#define HCI_HISR_TXBCNERR BIT(7) +#define HCI_HISR_BCNERLY_INT BIT(16) +#define HCI_HISR_C2HCMD BIT(17) +#define HCI_HISR_CPWM1 BIT(18) +#define HCI_HISR_CPWM2 BIT(19) +#define HCI_HISR_HSISR_IND BIT(20) +#define HCI_HISR_GTINT3_IND BIT(21) +#define HCI_HISR_GTINT4_IND BIT(22) +#define HCI_HISR_PSTIMEOUT BIT(23) +#define HCI_HISR_OCPINT BIT(24) +#define HCI_HISR_ATIMEND BIT(25) +#define HCI_HISR_ATIMEND_E BIT(26) +#define HCI_HISR_CTWEND BIT(27) +#define HCI_HISR_TSF_BIT32_TOGGLE BIT(29) +#define HCI_HISR_PSTIMEOUT_E BIT(30) +//SPI HIMR MASK diff with SDIO +#define HCI_HIMR_RX_REQUEST BIT(0) +#define HCI_HIMR_AVAL BIT(1) +#define HCI_HIMR_TXERR BIT(2) +#define HCI_HIMR_RXERR BIT(3) +#define HCI_HIMR_TXFOVW BIT(4) +#define HCI_HIMR_RXFOVW BIT(5) +#define HCI_HIMR_TXBCNOK BIT(6) +#define HCI_HIMR_TXBCNERR BIT(7) +#define HCI_HIMR_BCNERLY_INT BIT(16) +#define HCI_HIMR_C2HCMD BIT(17) +#define HCI_HIMR_CPWM1 BIT(18) +#define HCI_HIMR_CPWM2 BIT(19) +#define HCI_HIMR_HSISR_IND BIT(20) +#define HCI_HIMR_GTINT3_IND BIT(21) +#define HCI_HIMR_GTINT4_IND BIT(22) +#define HCI_HIMR_PSTIMEOUT BIT(23) +#define HCI_HIMR_OCPINT BIT(24) +#define HCI_HIMR_ATIMEND BIT(25) +#define HCI_HIMR_ATIMEND_E BIT(26) +#define HCI_HIMR_CTWEND BIT(27) +#define HCI_HIMR_TSF_BIT32_TOGGLE BIT(29) +#define HCI_HIMR_PSTIMEOUT_E BIT(30) +#else +#define HCI_HISR_RX_REQUEST BIT(0) +#define HCI_HISR_AVAL BIT(1) +#define HCI_HISR_TXERR BIT(2) +#define HCI_HISR_RXERR BIT(3) +#define HCI_HISR_TXFOVW BIT(4) +#define HCI_HISR_RXFOVW BIT(5) +#define HCI_HISR_TXBCNOK BIT(6) +#define HCI_HISR_TXBCNERR BIT(7) +#define HCI_HISR_BCNERLY_INT BIT(16) +#define HCI_HISR_ATIMEND BIT(17) +#define HCI_HISR_ATIMEND_E BIT(18) +#define HCI_HISR_CTWEND BIT(19) +#define HCI_HISR_C2HCMD BIT(20) +#define HCI_HISR_CPWM1 BIT(21) +#define HCI_HISR_CPWM2 BIT(22) +#define HCI_HISR_HSISR_IND BIT(23) +#define HCI_HISR_GTINT3_IND BIT(24) +#define HCI_HISR_GTINT4_IND BIT(25) +#define HCI_HISR_PSTIMEOUT BIT(26) +#define HCI_HISR_OCPINT BIT(27) +#define HCI_HISR_TSF_BIT32_TOGGLE BIT(29) +//SPI HIMR MASK diff with SDIO +#define HCI_HIMR_RX_REQUEST BIT(0) +#define HCI_HIMR_AVAL BIT(1) +#define HCI_HIMR_TXERR BIT(2) +#define HCI_HIMR_RXERR BIT(3) +#define HCI_HIMR_TXFOVW BIT(4) +#define HCI_HIMR_RXFOVW BIT(5) +#define HCI_HIMR_TXBCNOK BIT(6) +#define HCI_HIMR_TXBCNERR BIT(7) +#define HCI_HIMR_BCNERLY_INT BIT(16) +#define HCI_HIMR_ATIMEND BIT(17) +#define HCI_HIMR_ATIMEND_E BIT(18) +#define HCI_HIMR_CTWEND BIT(19) +#define HCI_HIMR_C2HCMD BIT(20) +#define HCI_HIMR_CPWM1 BIT(21) +#define HCI_HIMR_CPWM2 BIT(22) +#define HCI_HIMR_HSISR_IND BIT(23) +#define HCI_HIMR_GTINT3_IND BIT(24) +#define HCI_HIMR_GTINT4_IND BIT(25) +#define HCI_HIMR_PSTIMEOUT BIT(26) +#define HCI_HIMR_OCPINT BIT(27) +#define HCI_HIMR_TSF_BIT32_TOGGLE BIT(29) +#endif +#define MASK_SPI_HISR_CLEAR (HCI_HIMR_TXERR |\ + HCI_HIMR_RXERR |\ + HCI_HIMR_TXFOVW |\ + HCI_HIMR_RXFOVW |\ + HCI_HIMR_TXBCNOK |\ + HCI_HIMR_TXBCNERR |\ + HCI_HIMR_C2HCMD |\ + HCI_HIMR_CPWM1 |\ + HCI_HIMR_CPWM2 |\ + HCI_HIMR_HSISR_IND |\ + HCI_HIMR_GTINT3_IND |\ + HCI_HIMR_GTINT4_IND |\ + HCI_HIMR_PSTIMEOUT |\ + HCI_HIMR_OCPINT) + +#define REG_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)//(x<<(unsigned int)24) +#define REG_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16) +#define REG_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0) +#define REG_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5) +#define REG_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7) + +#define FIFO_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)//(x<<(unsigned int)24) +//#define FIFO_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16) +#define FIFO_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0) +#define FIFO_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5) +#define FIFO_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7) + + +//get status dword0 +#define GET_STATUS_PUB_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 24, 8) +#define GET_STATUS_HI_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 18, 6) +#define GET_STATUS_MID_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 12, 6) +#define GET_STATUS_LOW_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 6, 6) +#define GET_STATUS_HISR_HI6BIT(status) LE_BITS_TO_4BYTE(status, 0, 6) + +//get status dword1 +#define GET_STATUS_HISR_MID8BIT(status) LE_BITS_TO_4BYTE(status + 4, 24, 8) +#define GET_STATUS_HISR_LOW8BIT(status) LE_BITS_TO_4BYTE(status + 4, 16, 8) +#define GET_STATUS_ERROR(status) LE_BITS_TO_4BYTE(status + 4, 17, 1) +#define GET_STATUS_INT(status) LE_BITS_TO_4BYTE(status + 4, 16, 1) +#define GET_STATUS_RX_LENGTH(status) LE_BITS_TO_4BYTE(status + 4, 0, 16) + + +#define RXDESC_SIZE 24 + +#define TX_FREE_PG_QUEUE 4 // The number of Tx FIFO free page +#define TX_FIFO_PAGE_SZ 128 + +struct spi_more_data { + unsigned long more_data; + unsigned long len; +}; + +extern BUS_DRV_OPS_T bus_driver_ops; + +extern u8 spi_query_status_info(struct dvobj_priv *pdvobj); + +extern void spi_set_intf_ops(struct _io_ops *pops); + +#endif //__GSPI_SPEC_H__ diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/hci_intfs.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/hci_intfs.h new file mode 100644 index 0000000..bc205b5 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/hci_intfs.h @@ -0,0 +1,68 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _HCI_INTFS_H_ +#define _HCI_INTFS_H_ + +#include + +struct host_ctrl_intf_ops +{ + struct dvobj_priv * (*dvobj_init)(void); + void (*dvobj_deinit)(struct dvobj_priv *dvobj); + void (*dvobj_request_irq)(struct dvobj_priv *dvobj); + void (*dvobj_free_irq)(struct dvobj_priv *dvobj); +}; + +extern struct dvobj_priv *hci_dvobj_init(void); +extern void hci_dvobj_deinit(struct dvobj_priv *dvobj); +extern void hci_dvobj_request_irq(struct dvobj_priv *dvobj); +extern void hci_dvobj_free_irq(struct dvobj_priv *dvobj); + +#if defined(CONFIG_GSPI_HCI) +#define hci_bus_intf_type RTW_GSPI +#define hci_set_intf_ops spi_set_intf_ops +#define hci_intf_start rtw_hal_enable_interrupt +#define hci_intf_stop rtw_hal_disable_interrupt +extern s32 gspi_dvobj_xmit_mgnt(_adapter * padapter, struct xmit_frame *pmgntframe); +extern s32 gspi_dvobj_xmit_data(_adapter *padapter, struct xmit_frame *pxmitframe); +#endif + +#if defined(CONFIG_SDIO_HCI) +#define hci_bus_intf_type RTW_SDIO +#define hci_set_intf_ops sdio_set_intf_ops +#define hci_intf_start rtw_hal_enable_interrupt +#define hci_intf_stop rtw_hal_disable_interrupt +extern s32 sdio_dvobj_xmit_mgnt(_adapter * padapter, struct xmit_frame *pmgntframe); +extern s32 sdio_dvobj_xmit_data(_adapter *padapter, struct xmit_frame *pxmitframe); + +#endif + +#if defined(CONFIG_LX_HCI) +#define hci_bus_intf_type RTW_LXBUS +#define hci_set_intf_ops lxbus_set_intf_ops +#define hci_intf_start rtw_hal_enable_interrupt +#define hci_intf_stop hci_lxbus_intf_stop +void hci_lxbus_intf_stop(_adapter *padapter); +u32 lextra_bus_dma_Interrupt (void* data); +#endif + + +#endif //_HCI_INTFS_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/hci_spec.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/hci_spec.h new file mode 100644 index 0000000..8843305 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/hci_spec.h @@ -0,0 +1,433 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HCI_SPEC_H__ +#define __HCI_SPEC_H__ + + +#if defined(CONFIG_GSPI_HCI) +#include "gspi/gspi_spec.h" + +// SPI Header Files +#ifdef PLATFORM_LINUX +#include +#endif + +#define GSPI_CMD_LEN 4 +#define HAL_INTERFACE_CMD_LEN GSPI_CMD_LEN +#define GSPI_STATUS_LEN 8 +#define HAL_INTERFACE_CMD_STATUS_LEN GSPI_STATUS_LEN +#define HAL_INTERFACE_OVERHEAD (HAL_INTERFACE_CMD_LEN+HAL_INTERFACE_OVERHEAD) +//reserve tx headroom in case of softap forwarding unicase packet +#define RX_RESERV_HEADROOM (SKB_WLAN_TX_EXTRA_LEN>RX_DRIVER_INFO+RXDESC_SIZE)?(SKB_WLAN_TX_EXTRA_LEN-RX_DRIVER_INFO-RXDESC_SIZE):0 +typedef struct gspi_data +{ + //u8 func_number; + + //u8 tx_block_mode; + //u8 rx_block_mode; + u16 block_transfer_len; //u32 block_transfer_len; + +#ifdef PLATFORM_LINUX + struct spi_device *func; + + struct workqueue_struct *priv_wq; + struct delayed_work irq_work; +#endif + +#if defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) + _mutex spi_mutex; +#endif +} GSPI_DATA, *PGSPI_DATA; + +#define INTF_DATA GSPI_DATA + +//extern void spi_set_intf_ops(struct _io_ops *pops); +extern void spi_int_hdl(PADAPTER padapter); +#define rtw_hci_interrupt_handler(__adapter) spi_int_hdl(__adapter) + +#elif defined(CONFIG_SDIO_HCI) +#include "sdio/sdio_spec.h" + +#define GSPI_CMD_LEN 0 +#define HAL_INTERFACE_CMD_LEN GSPI_CMD_LEN +#define GSPI_STATUS_LEN 8 +#define HAL_INTERFACE_CMD_STATUS_LEN GSPI_STATUS_LEN +#define HAL_INTERFACE_OVERHEAD (HAL_INTERFACE_CMD_LEN+HAL_INTERFACE_OVERHEAD) +#define RX_RESERV_HEADROOM (SKB_WLAN_TX_EXTRA_LEN>RX_DRIVER_INFO+RXDESC_SIZE)?(SKB_WLAN_TX_EXTRA_LEN-RX_DRIVER_INFO-RXDESC_SIZE):0 + +typedef struct gspi_data +{ + //u8 func_number; + + //u8 tx_block_mode; + //u8 rx_block_mode; + u16 block_transfer_len; //u32 block_transfer_len; + +#ifdef PLATFORM_LINUX + struct spi_device *func; + + struct workqueue_struct *priv_wq; + struct delayed_work irq_work; +#endif + + struct sdio_func *func; + +#if defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) + _mutex spi_mutex; +#endif +} GSPI_DATA, *PGSPI_DATA; + +#define INTF_DATA GSPI_DATA + +//extern void spi_set_intf_ops(struct _io_ops *pops); +extern void spi_int_hdl(PADAPTER padapter); +#define rtw_hci_interrupt_handler(__adapter) spi_int_hdl(__adapter) + +#elif defined(CONFIG_USB_HCI) +#include +#include + +#elif defined(CONFIG_PCI_HCI) +#include +#ifdef PLATFORM_LINUX +#include +#endif + +#define INTF_CMD_LEN 0 + +#define INTEL_VENDOR_ID 0x8086 +#define SIS_VENDOR_ID 0x1039 +#define ATI_VENDOR_ID 0x1002 +#define ATI_DEVICE_ID 0x7914 +#define AMD_VENDOR_ID 0x1022 + +#define PCI_MAX_BRIDGE_NUMBER 255 +#define PCI_MAX_DEVICES 32 +#define PCI_MAX_FUNCTION 8 + +#define PCI_CONF_ADDRESS 0x0CF8 // PCI Configuration Space Address +#define PCI_CONF_DATA 0x0CFC // PCI Configuration Space Data + +#define PCI_CLASS_BRIDGE_DEV 0x06 +#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04 + +#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10 + +#define U1DONTCARE 0xFF +#define U2DONTCARE 0xFFFF +#define U4DONTCARE 0xFFFFFFFF + +#define PCI_VENDER_ID_REALTEK 0x10ec + +#define HAL_HW_PCI_8180_DEVICE_ID 0x8180 +#define HAL_HW_PCI_8185_DEVICE_ID 0x8185 //8185 or 8185b +#define HAL_HW_PCI_8188_DEVICE_ID 0x8188 //8185b +#define HAL_HW_PCI_8198_DEVICE_ID 0x8198 //8185b +#define HAL_HW_PCI_8190_DEVICE_ID 0x8190 //8190 +#define HAL_HW_PCI_8723E_DEVICE_ID 0x8723 //8723E +#define HAL_HW_PCI_8192_DEVICE_ID 0x8192 //8192 PCI-E +#define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192 //8192 SE +#define HAL_HW_PCI_8174_DEVICE_ID 0x8174 //8192 SE +#define HAL_HW_PCI_8173_DEVICE_ID 0x8173 //8191 SE Crab +#define HAL_HW_PCI_8172_DEVICE_ID 0x8172 //8191 SE RE +#define HAL_HW_PCI_8171_DEVICE_ID 0x8171 //8191 SE Unicron +#define HAL_HW_PCI_0045_DEVICE_ID 0x0045 //8190 PCI for Ceraga +#define HAL_HW_PCI_0046_DEVICE_ID 0x0046 //8190 Cardbus for Ceraga +#define HAL_HW_PCI_0044_DEVICE_ID 0x0044 //8192e PCIE for Ceraga +#define HAL_HW_PCI_0047_DEVICE_ID 0x0047 //8192e Express Card for Ceraga +#define HAL_HW_PCI_700F_DEVICE_ID 0x700F +#define HAL_HW_PCI_701F_DEVICE_ID 0x701F +#define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304 +#define HAL_HW_PCI_8192CET_DEVICE_ID 0x8191 //8192ce +#define HAL_HW_PCI_8192CE_DEVICE_ID 0x8178 //8192ce +#define HAL_HW_PCI_8191CE_DEVICE_ID 0x8177 //8192ce +#define HAL_HW_PCI_8188CE_DEVICE_ID 0x8176 //8192ce +#define HAL_HW_PCI_8192CU_DEVICE_ID 0x8191 //8192ce +#define HAL_HW_PCI_8192DE_DEVICE_ID 0x8193 //8192de +#define HAL_HW_PCI_002B_DEVICE_ID 0x002B //8192de, provided by HW SD +#define HAL_HW_PCI_8188EE_DEVICE_ID 0x8179 + +#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 //8190 support 16 pages of IO registers +#define HAL_HW_PCI_REVISION_ID_8190PCI 0x00 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000 //8192 support 16 pages of IO registers +#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE 0x4000 //8192 support 16 pages of IO registers +#define HAL_HW_PCI_REVISION_ID_8192SE 0x10 +#define HAL_HW_PCI_REVISION_ID_8192CE 0x1 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE 0x4000 //8192 support 16 pages of IO registers +#define HAL_HW_PCI_REVISION_ID_8192DE 0x0 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE 0x4000 //8192 support 16 pages of IO registers + +enum pci_bridge_vendor { + PCI_BRIDGE_VENDOR_INTEL = 0x0,//0b'0000,0001 + PCI_BRIDGE_VENDOR_ATI, //= 0x02,//0b'0000,0010 + PCI_BRIDGE_VENDOR_AMD, //= 0x04,//0b'0000,0100 + PCI_BRIDGE_VENDOR_SIS ,//= 0x08,//0b'0000,1000 + PCI_BRIDGE_VENDOR_UNKNOWN, //= 0x40,//0b'0100,0000 + PCI_BRIDGE_VENDOR_MAX ,//= 0x80 +} ; + +// copy this data structor defination from MSDN SDK +typedef struct _PCI_COMMON_CONFIG { + u16 VendorID; + u16 DeviceID; + u16 Command; + u16 Status; + u8 RevisionID; + u8 ProgIf; + u8 SubClass; + u8 BaseClass; + u8 CacheLineSize; + u8 LatencyTimer; + u8 HeaderType; + u8 BIST; + + union { + struct _PCI_HEADER_TYPE_0 { + u32 BaseAddresses[6]; + u32 CIS; + u16 SubVendorID; + u16 SubSystemID; + u32 ROMBaseAddress; + u8 CapabilitiesPtr; + u8 Reserved1[3]; + u32 Reserved2; + + u8 InterruptLine; + u8 InterruptPin; + u8 MinimumGrant; + u8 MaximumLatency; + } type0; +#if 0 + struct _PCI_HEADER_TYPE_1 { + u32 BaseAddresses[PCI_TYPE1_ADDRESSES]; + u8 PrimaryBusNumber; + u8 SecondaryBusNumber; + u8 SubordinateBusNumber; + u8 SecondaryLatencyTimer; + u8 IOBase; + u8 IOLimit; + u16 SecondaryStatus; + u16 MemoryBase; + u16 MemoryLimit; + u16 PrefetchableMemoryBase; + u16 PrefetchableMemoryLimit; + u32 PrefetchableMemoryBaseUpper32; + u32 PrefetchableMemoryLimitUpper32; + u16 IOBaseUpper; + u16 IOLimitUpper; + u32 Reserved2; + u32 ExpansionROMBase; + u8 InterruptLine; + u8 InterruptPin; + u16 BridgeControl; + } type1; + + struct _PCI_HEADER_TYPE_2 { + u32 BaseAddress; + u8 CapabilitiesPtr; + u8 Reserved2; + u16 SecondaryStatus; + u8 PrimaryBusNumber; + u8 CardbusBusNumber; + u8 SubordinateBusNumber; + u8 CardbusLatencyTimer; + u32 MemoryBase0; + u32 MemoryLimit0; + u32 MemoryBase1; + u32 MemoryLimit1; + u16 IOBase0_LO; + u16 IOBase0_HI; + u16 IOLimit0_LO; + u16 IOLimit0_HI; + u16 IOBase1_LO; + u16 IOBase1_HI; + u16 IOLimit1_LO; + u16 IOLimit1_HI; + u8 InterruptLine; + u8 InterruptPin; + u16 BridgeControl; + u16 SubVendorID; + u16 SubSystemID; + u32 LegacyBaseAddress; + u8 Reserved3[56]; + u32 SystemControl; + u8 MultiMediaControl; + u8 GeneralStatus; + u8 Reserved4[2]; + u8 GPIO0Control; + u8 GPIO1Control; + u8 GPIO2Control; + u8 GPIO3Control; + u32 IRQMuxRouting; + u8 RetryStatus; + u8 CardControl; + u8 DeviceControl; + u8 Diagnostic; + } type2; +#endif + } u; + + u8 DeviceSpecific[108]; +} PCI_COMMON_CONFIG , *PPCI_COMMON_CONFIG; + +typedef struct _RT_PCI_CAPABILITIES_HEADER { + u8 CapabilityID; + u8 Next; +} RT_PCI_CAPABILITIES_HEADER, *PRT_PCI_CAPABILITIES_HEADER; + +struct pci_priv{ + BOOLEAN pci_clk_req; + + u8 pciehdr_offset; + // PCIeCap is only differece between B-cut and C-cut. + // Configuration Space offset 72[7:4] + // 0: A/B cut + // 1: C cut and later. + u8 pcie_cap; + u8 linkctrl_reg; + + u8 busnumber; + u8 devnumber; + u8 funcnumber; + + u8 pcibridge_busnum; + u8 pcibridge_devnum; + u8 pcibridge_funcnum; + u8 pcibridge_vendor; + u16 pcibridge_vendorid; + u16 pcibridge_deviceid; + u8 pcibridge_pciehdr_offset; + u8 pcibridge_linkctrlreg; + + u8 amd_l1_patch; +}; + +typedef struct _RT_ISR_CONTENT +{ + union{ + u32 IntArray[2]; + u32 IntReg4Byte; + u16 IntReg2Byte; + }; +}RT_ISR_CONTENT, *PRT_ISR_CONTENT; + +//#define RegAddr(addr) (addr + 0xB2000000UL) +//some platform macros will def here +static inline void NdisRawWritePortUlong(u32 port, u32 val) +{ + outl(val, port); + //writel(val, (u8 *)RegAddr(port)); +} + +static inline void NdisRawWritePortUchar(u32 port, u8 val) +{ + outb(val, port); + //writeb(val, (u8 *)RegAddr(port)); +} + +static inline void NdisRawReadPortUchar(u32 port, u8 *pval) +{ + *pval = inb(port); + //*pval = readb((u8 *)RegAddr(port)); +} + +static inline void NdisRawReadPortUshort(u32 port, u16 *pval) +{ + *pval = inw(port); + //*pval = readw((u8 *)RegAddr(port)); +} + +static inline void NdisRawReadPortUlong(u32 port, u32 *pval) +{ + *pval = inl(port); + //*pval = readl((u8 *)RegAddr(port)); +} +#elif defined(CONFIG_LX_HCI) +#define GSPI_CMD_LEN 0 +#define GSPI_STATUS_LEN 0 +#include "lxbus/lxbus_spec.h" +#endif // interface define + +#if 0 //TODO +struct intf_priv { + + u8 *intf_dev; + u32 max_iosz; //USB2.0: 128, USB1.1: 64, SDIO:64 + u32 max_xmitsz; //USB2.0: unlimited, SDIO:512 + u32 max_recvsz; //USB2.0: unlimited, SDIO:512 + + volatile u8 *io_rwmem; + volatile u8 *allocated_io_rwmem; + u32 io_wsz; //unit: 4bytes + u32 io_rsz;//unit: 4bytes + u8 intf_status; + + void (*_bus_io)(u8 *priv); + +/* +Under Sync. IRP (SDIO/USB) +A protection mechanism is necessary for the io_rwmem(read/write protocol) + +Under Async. IRP (SDIO/USB) +The protection mechanism is through the pending queue. +*/ + + _mutex ioctl_mutex; + + +#ifdef PLATFORM_LINUX + #ifdef CONFIG_USB_HCI + // when in USB, IO is through interrupt in/out endpoints + struct usb_device *udev; + PURB piorw_urb; + u8 io_irp_cnt; + u8 bio_irp_pending; + _sema io_retevt; + _timer io_timer; + u8 bio_irp_timeout; + u8 bio_timer_cancel; + #endif +#endif + +#ifdef PLATFORM_OS_XP + #ifdef CONFIG_SDIO_HCI + // below is for io_rwmem... + PMDL pmdl; + PSDBUS_REQUEST_PACKET sdrp; + PSDBUS_REQUEST_PACKET recv_sdrp; + PSDBUS_REQUEST_PACKET xmit_sdrp; + + PIRP piorw_irp; + + #endif + #ifdef CONFIG_USB_HCI + PURB piorw_urb; + PIRP piorw_irp; + u8 io_irp_cnt; + u8 bio_irp_pending; + _sema io_retevt; + #endif +#endif + +}; +#endif +#endif //__HCI_SPEC_H__ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/lxbus/lxbus_spec.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/lxbus/lxbus_spec.h new file mode 100644 index 0000000..e12b099 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/lxbus/lxbus_spec.h @@ -0,0 +1,55 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __LXBUS_SPEC_H__ +#define __LXBUS_SPEC_H__ + +#include +//#include + + +#define HAL_INTERFACE_CMD_LEN 0 +#define HAL_INTERFACE_CMD_STATUS_LEN 0 +#define HAL_INTERFACE_OVERHEAD (HAL_INTERFACE_CMD_LEN+HAL_INTERFACE_CMD_STATUS_LEN) + +/* + * The following data structure is used for 8195a debug, and should not + * declared this parameter in release version to save sram usage + * It is used for debugging tx/rx and r/w pointer + */ +struct hal_debug +{ + unsigned int int_count; + unsigned int crc_err; + u16 last_write_be; + u16 last_write_mgt; + u16 last_closed_be; + u16 last_closed_mgt; + +}; + + +// The following section should be removed? +#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13] +#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13] +#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13] +#define SDIO_MAX_TX_QUEUE 3 // HIQ, MIQ and LOQ + +#endif //__LXBUS_SPEC_H__ diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_drvio.c b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_drvio.c new file mode 100644 index 0000000..2909340 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_drvio.c @@ -0,0 +1,818 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + *******************************************************************************/ +#define _GSPI_IO_C_ + +#include + +#ifdef CONFIG_SDIO_HCI +#include "wifi_io.h" //from sdio_host driver +//#include +//#include +//#define SDIO_CMD52_IO + +//SDIO host local register space mapping. +#define SDIO_LOCAL_MSK 0x0FFF +#define WLAN_IOREG_MSK 0x7FFF +#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0] +#define WLAN_RX0FF_MSK 0x0003 + +#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID +#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13] +#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13] +#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13] +#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13] +#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13] +#define WLAN_IOREG_DEVICE_ID 8 // 1b[16] + +// +// Description: +// Query SDIO Local register to query current the number of Free TxPacketBuffer page. +// +// Assumption: +// 1. Running at PASSIVE_LEVEL +// 2. RT_TX_SPINLOCK is NOT acquired. +// +// Created by Roger, 2011.01.28. +// +#ifdef CONFIG_RTL8188F +u8 spi_query_status_info(struct dvobj_priv *pdvobj) +{ + + ADAPTER *padapter = pdvobj->if1; + pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX] = rtw_read8(padapter, LOCAL_REG_FREE_TXPG); + pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX] = rtw_read8(padapter, LOCAL_REG_FREE_TXPG+2); + pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX] = rtw_read8(padapter, LOCAL_REG_FREE_TXPG+4); + pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] = rtw_read8(padapter, LOCAL_REG_FREE_TXPG+6); + RT_TRACE(_module_hci_ops_c_, _drv_notice_, + ("%s: Free page for HIQ(%x),MIDQ(%x),LOWQ(%x),PUBQ(%x)\n", + __FUNCTION__, + pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX])); + //_exit_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql); + + return _TRUE; +} +#else +u8 spi_query_status_info(struct dvobj_priv *pdvobj) +{ + u32 NumOfFreePage; + ADAPTER *padapter = pdvobj->if1; + + NumOfFreePage = rtw_read32(padapter, LOCAL_REG_FREE_TXPG); + +// _enter_critical_bh(&pdvobj->SdioTxFIFOFreePageLock, &irql); + rtw_memcpy(pdvobj->SdioTxFIFOFreePage, &NumOfFreePage, 4); + + RT_TRACE(_module_hci_ops_c_, _drv_notice_, + ("%s: Free page for HIQ(%x),MIDQ(%x),LOWQ(%x),PUBQ(%x)\n", + __FUNCTION__, + pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX], + pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX])); +// _exit_critical_bh(&pdvobj->SdioTxFIFOFreePageLock, &irql); + + return _TRUE; +} +#endif +static unsigned char get_deviceid(unsigned int addr) +{ + unsigned char devideId; + unsigned short pseudoId; + + + pseudoId = (unsigned short)(addr >> 16); + switch (pseudoId) + { + case 0x1025: + devideId = SDIO_LOCAL_DEVICE_ID; + break; + + case 0x1026: + devideId = WLAN_IOREG_DEVICE_ID; + break; + +// case 0x1027: +// devideId = SDIO_FIRMWARE_FIFO; +// break; + + case 0x1031: + devideId = WLAN_TX_HIQ_DEVICE_ID; + break; + + case 0x1032: + devideId = WLAN_TX_MIQ_DEVICE_ID; + break; + + case 0x1033: + devideId = WLAN_TX_LOQ_DEVICE_ID; + break; + + case 0x1034: + devideId = WLAN_RX0FF_DEVICE_ID; + break; + + default: +// devideId = (u8)((addr >> 13) & 0xF); + devideId = WLAN_IOREG_DEVICE_ID; + break; + } + + return devideId; +} + +static unsigned int _cvrt2ftaddr(const unsigned int addr, unsigned char *pdeviceId, unsigned short *poffset) +{ + unsigned char deviceId; + unsigned short offset; + unsigned int ftaddr; + + + deviceId = get_deviceid(addr); + offset = 0; + + switch (deviceId) + { + case SDIO_LOCAL_DEVICE_ID: + offset = addr & SDIO_LOCAL_MSK; + break; + + case WLAN_TX_HIQ_DEVICE_ID: + case WLAN_TX_MIQ_DEVICE_ID: + case WLAN_TX_LOQ_DEVICE_ID: + offset = addr & WLAN_FIFO_MSK; + break; + + case WLAN_RX0FF_DEVICE_ID: + offset = addr & WLAN_RX0FF_MSK; + break; + + case WLAN_IOREG_DEVICE_ID: + default: + deviceId = WLAN_IOREG_DEVICE_ID; + offset = addr & WLAN_IOREG_MSK; + break; + } + ftaddr = (deviceId << 13) | offset; + + if (pdeviceId) *pdeviceId = deviceId; + if (poffset) *poffset = offset; + + return ftaddr; +} + +unsigned char sdio_read8(ADAPTER *Adapter, unsigned int addr, int *err) +{ + struct dvobj_priv *psdiodev; + unsigned int ftaddr; + unsigned char val; + +_func_enter_; + + psdiodev = adapter_to_dvobj(Adapter); + ftaddr = _cvrt2ftaddr(addr, NULL, NULL); + + rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func); + val = rtw_sdio_bus_ops.readb(psdiodev->intf_data.func, ftaddr, err); + rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func); + + if(err && *err) + DBG_871X( "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr); + +_func_exit_; + + return val; + +} + +unsigned short sdio_read16(ADAPTER *Adapter, unsigned int addr, int *err) +{ + struct dvobj_priv *psdiodev; + unsigned int ftaddr; + unsigned short val; + +_func_enter_; + + psdiodev = adapter_to_dvobj(Adapter); + + if (addr & 1) + DBG_871X( "sdio_read16 addr is wrong addr:0x%08x\n", addr); + + ftaddr = _cvrt2ftaddr(addr, NULL, NULL); + rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func); + val = rtw_sdio_bus_ops.readw(psdiodev->intf_data.func, ftaddr, err); + rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func); + + if(err && *err) + DBG_871X( "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr); + +_func_exit_; + + return val; +} + +unsigned int sdio_read32(ADAPTER *Adapter, unsigned int addr, int *err) +{ + struct dvobj_priv *psdiodev; + unsigned int ftaddr; + unsigned int val; + +_func_enter_; + + psdiodev = adapter_to_dvobj(Adapter); + + if (addr & 3) + DBG_871X( "sdio_read32 addr is wrong addr:0x%08x\n", addr); + + ftaddr = _cvrt2ftaddr(addr, NULL, NULL); + rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func); + val = rtw_sdio_bus_ops.readl(psdiodev->intf_data.func, ftaddr, err); + rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func); + if(err && *err) + DBG_871X( "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr); + +_func_exit_; + + return val; + +} + + +unsigned int sdio_write8(ADAPTER *Adapter, unsigned int addr, unsigned int buf, int*err) +{ + struct dvobj_priv *psdiodev; + unsigned int ftaddr; + unsigned int val = 0; + +_func_enter_; + + psdiodev = adapter_to_dvobj(Adapter); + + ftaddr = _cvrt2ftaddr(addr, NULL, NULL); + + rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func); + rtw_sdio_bus_ops.writeb(psdiodev->intf_data.func, buf&0xFF,ftaddr, err); + rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func); + + if(err && *err) + DBG_871X( "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr); + +_func_exit_; + + return val; +} + +unsigned int sdio_write16(ADAPTER *Adapter, unsigned int addr,unsigned int buf, int *err) +{ + struct dvobj_priv *psdiodev; + unsigned int ftaddr; + unsigned int val = 0; + +_func_enter_; + + psdiodev = adapter_to_dvobj(Adapter); + + if (addr & 1) + DBG_871X( "sdio_write16 addr is wrong addr:0x%08x\n", addr); + + ftaddr = _cvrt2ftaddr(addr, NULL, NULL); + rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func); + rtw_sdio_bus_ops.writew(psdiodev->intf_data.func, buf&0xFFFF,ftaddr, err); + rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func); + if(err && *err) + DBG_871X( "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr); + +_func_exit_; + + return val; +} + +unsigned int sdio_write32(ADAPTER *Adapter, unsigned int addr, unsigned int buf, int *err) +{ + struct dvobj_priv *psdiodev; + unsigned int ftaddr; + unsigned int val = 0; + +_func_enter_; + + psdiodev = adapter_to_dvobj(Adapter); + + if (addr & 3) + DBG_871X( "sdio_write32 addr is wrong addr:0x%08x\n", addr); + + ftaddr = _cvrt2ftaddr(addr, NULL, NULL); + rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func); + rtw_sdio_bus_ops.writel(psdiodev->intf_data.func, buf&0xFFFFFFFF,ftaddr, err); + rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func); + + if(err && *err) + DBG_871X( "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr); + +_func_exit_; + + return val; +} + +unsigned int _fifoqueue2ftaddr(unsigned int fifo, unsigned int addr) +{ + unsigned int cmdaddr = TX_HIQ_DOMAIN; + + switch(fifo) { + case TX_LOQ_DOMAIN: + cmdaddr = ((WLAN_TX_LOQ_DEVICE_ID << 13) | (addr & WLAN_FIFO_MSK)); + break; + case TX_HIQ_DOMAIN: + cmdaddr = ((WLAN_TX_HIQ_DEVICE_ID << 13) | (addr & WLAN_FIFO_MSK)); + break; + case TX_MIQ_DOMAIN: + cmdaddr = ((WLAN_TX_MIQ_DEVICE_ID << 13) | (addr & WLAN_FIFO_MSK)); + break; + case RX_RXFIFO_DOMAIN: + cmdaddr = ((WLAN_RX0FF_DEVICE_ID << 13) | (addr & WLAN_RX0FF_MSK)); + break; + default: + cmdaddr = ((WLAN_TX_MIQ_DEVICE_ID << 13) | (addr & WLAN_FIFO_MSK)); + break; + + } + return cmdaddr; +} + +void sdio_write_tx_fifo(ADAPTER *Adapter, unsigned char *buf, int reallen, unsigned int fifo) +{ + struct dvobj_priv *psdiodev; + unsigned int ftaddr; + unsigned char *mem = buf; + int free_mem = 0; + int status; + unsigned int cnt = (unsigned int)reallen; + unsigned int page_num = 0; + unsigned int wait_num = 100; + unsigned int use_page = 0; + +_func_enter_; + use_page = (cnt + TX_FIFO_PAGE_SZ - 1) / TX_FIFO_PAGE_SZ; + + if (cnt > 512) + cnt = _RND(cnt, 512); + else + cnt = _RND(cnt, 4); + + if (((u32)buf) % 4) { + mem = rtw_zmalloc(cnt); + while(!mem) { + DBG_871X("rtw_zmalloc fail, cannot write tx fifo now\n"); + rtw_yield_os(); + mem = rtw_zmalloc(cnt); + } + + free_mem = 1; + //DBG_871X("sdio_write_tx_fifo tem_buf:%p ", mem); + rtw_memcpy(mem, buf, reallen); + + } else { + mem = buf; + } + + if (((u32)mem) % 4) { + DBG_871X("sdio_write_tx_fifo: Oops mem %p not 4 byte Alignment this will cause DMA wrong \n", mem); + } + + psdiodev = adapter_to_dvobj(Adapter); + + + if (fifo == TX_HIQ_DOMAIN) + page_num = psdiodev->SdioTxFIFOFreePage[HI_QUEUE_IDX]; + else if (fifo == TX_LOQ_DOMAIN) + page_num = psdiodev->SdioTxFIFOFreePage[LOW_QUEUE_IDX]; + else + page_num = psdiodev->SdioTxFIFOFreePage[MID_QUEUE_IDX]; + + if (page_num + psdiodev->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] < use_page) { + spi_query_status_info(Adapter->dvobj); + } + + while (page_num + psdiodev->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] < use_page) { + DBG_871X("Oops: spi_write_tx_fifo(): page_num is %d, padapter->pub_page is %d, wait_num is %d", + page_num, psdiodev->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX], wait_num); + + rtw_msleep_os(1); + //rtw_udelay_os(20); + spi_query_status_info(Adapter->dvobj); + + if (fifo == TX_HIQ_DOMAIN) + page_num = psdiodev->SdioTxFIFOFreePage[HI_QUEUE_IDX]; + else if (fifo == TX_LOQ_DOMAIN) + page_num = psdiodev->SdioTxFIFOFreePage[LOW_QUEUE_IDX]; + else + page_num = psdiodev->SdioTxFIFOFreePage[MID_QUEUE_IDX]; + + if (wait_num <= 2) { + DBG_871X("%s(): wait_num is <= 2 drop", __FUNCTION__); + return; + } + wait_num --; + } + + if (fifo == TX_HIQ_DOMAIN) { + if (use_page <= page_num) { + psdiodev->SdioTxFIFOFreePage[HI_QUEUE_IDX] -= page_num; + } else { + psdiodev->SdioTxFIFOFreePage[HI_QUEUE_IDX] = 0; + psdiodev->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] -= use_page - psdiodev->SdioTxFIFOFreePage[HI_QUEUE_IDX]; + } + } else if (fifo == TX_LOQ_DOMAIN) { + if (use_page <= page_num) { + psdiodev->SdioTxFIFOFreePage[LOW_QUEUE_IDX] -= page_num; + } else { + psdiodev->SdioTxFIFOFreePage[LOW_QUEUE_IDX] = 0; + psdiodev->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] -= use_page - psdiodev->SdioTxFIFOFreePage[LOW_QUEUE_IDX]; + } + } else { + if (use_page <= page_num) { + psdiodev->SdioTxFIFOFreePage[MID_QUEUE_IDX] -= page_num; + } else { + psdiodev->SdioTxFIFOFreePage[MID_QUEUE_IDX] = 0; + psdiodev->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] -= use_page - psdiodev->SdioTxFIFOFreePage[MID_QUEUE_IDX]; + } + } + + //must reallen here or tx will wrong when RND(512) + ftaddr = _fifoqueue2ftaddr(fifo, reallen >> 2); + + rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func); + status = rtw_sdio_bus_ops.memcpy_toio(psdiodev->intf_data.func, ftaddr, mem, cnt); + rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func); + + if (free_mem) { + rtw_mfree(mem, cnt); + } + + if (status) { + DBG_871X("sdio_write_tx_fifo:status:%x ftaddr:%x Length:%d fifo:%x ", status, ftaddr, cnt, fifo); + } + +_func_exit_; + + return; +} + +void sdio_read_rx_fifo(ADAPTER *Adapter, unsigned char *buf, int reallen) +{ + struct dvobj_priv *psdiodev; + unsigned int ftaddr; + unsigned char *mem = buf; + int free_mem = 0; + int status; + unsigned int cnt = (unsigned int)reallen; + static unsigned int sdio_rxfifo_cnt = 0; + unsigned int fifo = RX_RXFIFO_DOMAIN; + +_func_enter_; + + if (cnt > 512) + cnt = _RND(cnt, 512); + else + cnt = _RND(cnt, 4); + + mem = rtw_zmalloc(cnt); + if (mem) { + free_mem = 1; + //DBG_871X("sdio_read_rx_fifo tem_buf:%p ", mem); + } else { + //DBG_871X("sdio_read_rx_fifo tem_buf:Oops %p ", mem); + mem = buf; + } + + if (mem == NULL) { + DBG_871X("sdio_read_rx_fifo: Oops mem is NULL \n"); + return; + } + + if (((u32)mem) % 4) { + DBG_871X("sdio_read_rx_fifo: Oops mem %p not 4 byte Alignment this will cause DMA wrong \n", mem); + } + + psdiodev = adapter_to_dvobj(Adapter); + + ftaddr = _fifoqueue2ftaddr(fifo, sdio_rxfifo_cnt++); + + rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func); + status = rtw_sdio_bus_ops.memcpy_fromio(psdiodev->intf_data.func, mem, ftaddr, cnt); + rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func); + + if (free_mem) { + if (buf) + rtw_memcpy(buf, mem, reallen); + rtw_mfree(mem, cnt); + } + + if (status) { + //error + DBG_871X("rtw_sdio_read_rx_fifo error 0x%x\n" + "***** Addr = %x *****\n" + "***** Length = %d *****\n", status, ftaddr, cnt); + } + + +_func_exit_; + + return; +} + + +void sdio_cmd52_read(ADAPTER *Adapter, u32 addr, u32 cnt, u8 *pdata, int *err) +{ + int i = 0; + + for (i = 0; i < cnt; i++) { + pdata[i] = sdio_read8(Adapter, addr + i, err); + if (err && *err) + break; + } +} + +void sdio_cmd52_write(ADAPTER *Adapter, u32 addr, u32 cnt, u8 *pdata, int *err) +{ + int i = 0; + + for (i = 0; i < cnt; i++) { + sdio_write8(Adapter, addr + i, pdata[i], err); + if (err && *err) + break; + } +} + +u8 _sdio_read8(struct dvobj_priv *pdvobj, u32 addr, s32 *err) +{ + u8 val; + ADAPTER *Adapter = pdvobj->if1; + +_func_enter_; + + val = sdio_read8(Adapter, addr, err); + +_func_exit_; + + return val; +} + +u16 _sdio_read16(struct dvobj_priv *pdvobj, u32 addr, s32 *err) +{ + u8 bMacPwrCtrlOn = _FALSE; + u16 val; + u8 cmd52_io = 0; + ADAPTER *Adapter = pdvobj->if1; + +_func_enter_; + /* we should use CMD 52 before bMacPwrCtrlOn */ + rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); + cmd52_io = !bMacPwrCtrlOn; +#ifdef SDIO_CMD52_IO + cmd52_io = 1; +#endif + if (cmd52_io) { + sdio_cmd52_read(Adapter, addr, 2, (u8*)&val, err); + val = le16_to_cpu(val); + return val; + } + + val = sdio_read16(Adapter, addr, err); + +_func_exit_; + + return val; +} + +u32 _sdio_read32(struct dvobj_priv *pdvobj, u32 addr, s32 *err) +{ + u8 bMacPwrCtrlOn = _FALSE; + u32 val; + u8 cmd52_io = 0; + ADAPTER *Adapter = pdvobj->if1; + +_func_enter_; + + /* we should use CMD 52 before bMacPwrCtrlOn */ + rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); + cmd52_io = !bMacPwrCtrlOn; +#ifdef SDIO_CMD52_IO + cmd52_io = 1; +#endif + if (cmd52_io) { + sdio_cmd52_read(Adapter, addr, 4, (u8*)&val, err); + val = le32_to_cpu(val); + return val; + } + + val = sdio_read32(Adapter, addr, err); + +_func_exit_; + + return val; +} + +s32 _sdio_write8(struct dvobj_priv *pdvobj, u32 addr, u8 val, s32 *err) +{ + ADAPTER *Adapter = pdvobj->if1; + +_func_enter_; + + sdio_write8(Adapter, addr, (u32)val, err); + +_func_exit_; + + return _SUCCESS; +} + +s32 _sdio_write16(struct dvobj_priv *pdvobj, u32 addr, u16 val, s32 *err) +{ + u8 bMacPwrCtrlOn = _FALSE; + u8 cmd52_io = 0; + ADAPTER *Adapter = pdvobj->if1; + +_func_enter_; + /* we should use CMD 52 before bMacPwrCtrlOn */ + rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); + cmd52_io = !bMacPwrCtrlOn; +#ifdef SDIO_CMD52_IO + cmd52_io = 1; +#endif + if (cmd52_io) { + val = cpu_to_le16(val); + sdio_cmd52_write(Adapter, addr, 2, (u8*)&val, err); + return _SUCCESS; + } + + sdio_write16(Adapter, addr, (u32)val, err); + +_func_exit_; + + return _SUCCESS; +} + +s32 _sdio_write32(struct dvobj_priv *pdvobj, u32 addr, u32 val, s32 *err) +{ + u8 bMacPwrCtrlOn = _FALSE; + u8 cmd52_io = 0; + ADAPTER *Adapter = pdvobj->if1; + +_func_enter_; + /* we should use CMD 52 before bMacPwrCtrlOn */ + rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); + cmd52_io = !bMacPwrCtrlOn; +#ifdef SDIO_CMD52_IO + cmd52_io = 1; +#endif + if (cmd52_io) { + val = cpu_to_le32(val); + sdio_cmd52_write(Adapter, addr, 4, (u8*)&val, err); + return _SUCCESS; + } + + sdio_write32(Adapter, addr, val, err); + +_func_exit_; + + return _SUCCESS; +} + +/* + * Description: + * Read from RX FIFO + * Round read size to block size, + * and make sure data transfer will be done in one command. + * + * Parameters: + * pintfhdl a pointer of intf_hdl + * addr port ID + * cnt size to read + * rmem address to put data + * + * Return: + * _SUCCESS(1) Success + * _FAIL(0) Fail + */ +static int _sdio_read_rx_fifo(struct dvobj_priv *pdvobj, u32 addr, u8 *mem, u32 cnt, struct fifo_more_data *pmore_data) +{ + ADAPTER *Adapter = pdvobj->if1; + + //struct spi_more_data more_data = {0}; + + //DBG_8192C("%s \n", __func__); + rtw_memset(pmore_data, 0, sizeof(struct fifo_more_data)); + + sdio_read_rx_fifo(Adapter, mem, cnt); + + return _SUCCESS; +} + +/* + * Description: + * Translate sdio fifo address to Domain ID in each WLAN FIFO + */ +static u32 hwaddr2txfifo(u32 addr) +{ + u32 fifo_domain_id; + switch (addr) + { + case WLAN_TX_HIQ_DEVICE_ID: + fifo_domain_id = TX_HIQ_DOMAIN; + break; + + case WLAN_TX_MIQ_DEVICE_ID: + fifo_domain_id = TX_MIQ_DOMAIN; + break; + + case WLAN_TX_LOQ_DEVICE_ID: + fifo_domain_id = TX_LOQ_DOMAIN; + break; + default: + fifo_domain_id = TX_LOQ_DOMAIN; + break; + } + + return fifo_domain_id; +} + + +static int _sdio_write_tx_fifo(struct dvobj_priv *pdvobj, u32 addr, u8 *mem, u32 cnt) +{ + u8 remain_len = 0; + u32 w_sz = cnt; + ADAPTER *Adapter = pdvobj->if1; + + remain_len = w_sz%4; + if (remain_len != 0) + w_sz += 4 -remain_len; + +#if 0//ndef LZM_TEST + if (1) { + int i = 0; + for(i = 0; i < w_sz; i += 4) { + DBG_871X("_sdio_write_port[%d]: 0x%08x ", i, *(u32*)(mem + i)); + } + } +#endif + +#if 0 + { + static u32 write_test = 0; + u32 now_time = 0; + write_test++; + if(write_test==1000) { + now_time = xTaskGetTickCount() * portTICK_RATE_MS; + DBG_8192C("%s fifo:%d cnt:%d w_sz:%d mem:%p, now time:%d\n", __func__, addr, cnt, w_sz, mem, now_time); + write_test = 0; + } + } +#endif + sdio_write_tx_fifo(Adapter, mem, w_sz, hwaddr2txfifo(addr)); + + return _SUCCESS; +} + +static int sdio_io_priv(struct dvobj_priv *pdvobj) +{ + ADAPTER *Adapter = pdvobj->if1; + //struct dvobj_priv *pdvobj = &Adapter->dvobjpriv; + + return _SUCCESS; +} + +void sdio_set_intf_ops(struct _io_ops *pops) +{ + pops->init_io_priv = &sdio_io_priv; + pops->write8_endian = NULL; + + pops->_read8 = &_sdio_read8; + pops->_read16 = &_sdio_read16; + pops->_read32 = &_sdio_read32; + + pops->_write8 = &_sdio_write8; + pops->_write16 = &_sdio_write16; + pops->_write32 = &_sdio_write32; + + pops->read_rx_fifo = &_sdio_read_rx_fifo; + pops->write_tx_fifo = &_sdio_write_tx_fifo; +} + +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_intf.c b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_intf.c new file mode 100644 index 0000000..3a83d9b --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_intf.c @@ -0,0 +1,264 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _GSPI_INTF_C_ + +#include + +#ifdef CONFIG_SDIO_HCI +#include "wifi_io.h" //from sdio_driver + +#ifndef CONFIG_SDIO_HCI +#error "CONFIG_SDIO_HCI should be on!\n" +#endif + +struct dvobj_priv *gspi_dvobj_init(void) +{ +// int status = _FAIL; + struct dvobj_priv *dvobj = NULL; + PGSPI_DATA pgspi_data; + +_func_enter_; + + dvobj = (struct dvobj_priv*)rtw_zmalloc(sizeof(*dvobj)); + if (NULL == dvobj) { + goto exit; + } + + pgspi_data = &dvobj->intf_data; + + rtw_mutex_init(&pgspi_data->spi_mutex); + //pgspi_data->block_transfer_len = 512; //512 blocks r/w is not required for GSPI interface + //pgspi_data->tx_block_mode = 0; + //pgspi_data->rx_block_mode = 0; + +// status = _SUCCESS; + + if(wifi_sdio_func) { + DBG_871X("[gspi_dvobj_init] get wifi_func:%p\n", wifi_sdio_func); + dvobj->intf_data.func = wifi_sdio_func; + } else { + DBG_871X("[gspi_dvobj_init] Oops: get wifi sdio function fail"); + } + +exit: +_func_exit_; + + return dvobj; +} + +void gspi_dvobj_deinit(struct dvobj_priv *dvobj) +{ +//TODO +// struct dvobj_priv *dvobj = spi_get_drvdata(spi); + +_func_enter_; +//TODO +// spi_set_drvdata(spi, NULL); + if (dvobj) { +//TODO +// gspi_deinit(dvobj); + rtw_mutex_free(&dvobj->intf_data.spi_mutex); + rtw_mfree((u8*)dvobj, sizeof(*dvobj)); + } + +_func_exit_; +} + +void sdio_dvobj_interrupt_entry(struct sdio_func *func) +{ + //DBG_871X("[sdio_wifi_interrupt_entry] func :%p\n", func); + + //sdio irq have claim host, we should release it + //and claim it after SDIO IO, or SDIO IO will deadlock + rtw_sdio_bus_ops.release_host(func); + rtw_hci_interrupt_handler(func->drv_priv); + rtw_sdio_bus_ops.claim_host(func); +} + +void sdio_dvobj_request_irq(struct dvobj_priv *dvobj) +{ +_func_enter_; + if(dvobj->intf_data.func) { + dvobj->intf_data.func->drv_priv = (void*)dvobj->if1; + + rtw_sdio_bus_ops.claim_host(dvobj->intf_data.func); + rtw_sdio_bus_ops.claim_irq(dvobj->intf_data.func, sdio_dvobj_interrupt_entry); + rtw_sdio_bus_ops.release_host(dvobj->intf_data.func); + } + +_func_exit_; +} + +void sdio_dvobj_free_irq(struct dvobj_priv *dvobj) +{ +_func_enter_; + if(dvobj->intf_data.func) { + dvobj->intf_data.func->drv_priv = (void*)dvobj->if1; + + rtw_sdio_bus_ops.claim_host(dvobj->intf_data.func); + rtw_sdio_bus_ops.release_irq(dvobj->intf_data.func); + rtw_sdio_bus_ops.release_host(dvobj->intf_data.func); + } + +_func_exit_; +} + + +static inline u32 ffaddr2deviceId(struct dvobj_priv *pdvobj, u32 addr) +{ + return pdvobj->Queue2Pipe[addr]; +} + +static s32 rtw_xmit_xmitbuf(_adapter * padapter, struct xmit_buf *pxmitbuf) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + u32 deviceId; + + RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("@@@rtw_xmit_xmitbuf(): pxmitbuf->len=%d\n", pxmitbuf->len)); + //translate queue index to Device Id + deviceId = ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr); + + rtw_write_port(padapter, deviceId, pxmitbuf->len, (u8*)pxmitbuf->pbuf); + + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + return _SUCCESS; +} + +s32 sdio_dvobj_xmit_mgnt(_adapter * padapter, struct xmit_frame *pmgntframe) +{ + s32 ret = _SUCCESS; + struct pkt_attrib *pattrib; + struct xmit_buf *pxmitbuf; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + u8 *pframe = NULL; + + RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("+rtw_xmit_mgnt()\n")); + + pattrib = &pmgntframe->attrib; + pxmitbuf = pmgntframe->pxmitbuf; + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + //rtw_hal_update_txdesc(padapter, pmgntframe, pmgntframe->buf_addr); + + pxmitbuf->len = TXDESC_SIZE + pattrib->last_txcmdsz; + //pxmitbuf->pg_num = (pxmitbuf->len + 127)/128; // 128 is tx page size + //pxmitbuf->ptail = pmgntframe->buf_addr + pxmitbuf->len; + pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pmgntframe); + + rtw_count_tx_stats(padapter, pmgntframe, pattrib->last_txcmdsz); + + //RT_TRACE(_module_rtl871x_xmit_c_, _drv_always_, ("+rtw_xmit_mgnt(): type=%d\n", GetFrameSubType(pframe))); + if(GetFrameSubType(pframe)==WIFI_BEACON) //dump beacon directly + { +//When using dedicated xmit frame for issue bcn on ap mode +//free xmit frame for bcn reserved page on station mode - Alex Fang +#if USE_DEDICATED_BCN_TX + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) { + rtw_free_xmitframe(pxmitpriv, pmgntframe); + pxmitbuf->priv_data = NULL; + } + rtw_write_port(padapter, ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr), pxmitbuf->len, pxmitbuf->pbuf); + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); +#else + rtw_free_xmitframe(pxmitpriv, pmgntframe); + pxmitbuf->priv_data = NULL; + rtw_xmit_xmitbuf(padapter, pxmitbuf); +#endif + } + else + { + rtw_free_xmitframe(pxmitpriv, pmgntframe); + pxmitbuf->priv_data = NULL; + rtw_xmit_xmitbuf(padapter, pxmitbuf); + } + + if (ret != _SUCCESS) + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN); + + RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("-rtw_xmit_mgnt\n")); + return ret; +} + +s32 sdio_dvobj_xmit_data(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + _irqL irql; + s32 err; + +#ifdef CONFIG_80211N_HT + if ((pxmitframe->frame_tag == DATA_FRAMETAG) && + (pxmitframe->attrib.ether_type != 0x0806) && + (pxmitframe->attrib.ether_type != 0x888e) && + (pxmitframe->attrib.dhcp_pkt != 1)) + { + if (padapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE) + rtw_issue_addbareq_cmd(padapter, pxmitframe); + } +#endif + +#if USE_SKB_AS_XMITBUF + rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); +#endif + + rtw_enter_critical_bh(&pxmitpriv->lock, &irql); +#if 1 //FIX_XMITFRAME_FAULT, move from rtw_xmit(). +#ifdef CONFIG_AP_MODE + if(xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) + { + rtw_exit_critical_bh(&pxmitpriv->lock, &irql); + return 1; + } +#endif +#endif + err = rtw_xmitframe_enqueue(padapter, pxmitframe); + rtw_exit_critical_bh(&pxmitpriv->lock, &irql); + + if (err != _SUCCESS) { + RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmit_data(): enqueue xmitframe fail\n")); + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + // Trick, make the statistics correct + pxmitpriv->tx_pkts--; + pxmitpriv->tx_drop++; + return _TRUE; + } +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->adapter_type > PRIMARY_ADAPTER){ + padapter = padapter->pbuddy_adapter; + } +#endif + + rtw_wakeup_task(&padapter->xmitThread); + + return _FALSE; +} + +const struct host_ctrl_intf_ops hci_ops = { + gspi_dvobj_init, + gspi_dvobj_deinit, + sdio_dvobj_request_irq, + sdio_dvobj_free_irq +}; +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_isr.c b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_isr.c new file mode 100644 index 0000000..870008f --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_isr.c @@ -0,0 +1,223 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + *******************************************************************************/ +#define _GSPI_ISR_C_ + +#include + +#ifdef CONFIG_SDIO_HCI +extern struct recv_buf* rtw_recv_rxfifo(_adapter * padapter, u32 size, struct fifo_more_data* more_data); + +void spi_int_dpc(PADAPTER padapter, u32 sdio_hisr) +{ + struct dvobj_priv *pdvobj = padapter->dvobj; + +#ifdef CONFIG_LPS_LCLK + if (sdio_hisr & HCI_HISR_CPWM1) + { + struct reportpwrstate_parm report; + + report.state = rtw_read8(padapter, LOCAL_REG_HCPWM1); + cpwm_int_hdl(padapter, &report); + } +#endif + + if (sdio_hisr & HCI_HISR_TXERR) + { + u32 status; + + status = rtw_read32(padapter, REG_TXDMA_STATUS); + rtw_write32(padapter, REG_TXDMA_STATUS, status); + RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, status)); + } + +#ifdef CONFIG_INTERRUPT_BASED_TXBCN + + #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT + if (sdio_hisr & HCI_HISR_BCNERLY_INT) + #endif + #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR + if (sdio_hisr & (HCI_HISR_TXBCNOK|HCI_HISR_TXBCNERR)) + #endif + { + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + #if 0 //for debug + if (sdio_hisr & SDIO_HISR_BCNERLY_INT) + DBG_8192C("%s: SDIO_HISR_BCNERLY_INT\n", __func__); + + if (sdio_hisr & SDIO_HISR_TXBCNOK) + DBG_8192C("%s: SDIO_HISR_TXBCNOK\n", __func__); + + if (sdio_hisr & SDIO_HISR_TXBCNERR) { + u1Byte v422, v550, v419; + v422 = rtw_read8(padapter, 0x422); + v419 = rtw_read8(padapter, 0x419); + v550 = rtw_read8(padapter, 0x550); + + DBG_8192C("%s: SDIO_HISR_TXBCNERR 422=%02x, 419=%02x, 550=%02x\n", __func__, v422, v419, v550); + } + #endif + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) + { + //send_beacon(padapter); + if(pmlmepriv->update_bcn == _TRUE) + { + //tx_beacon_hdl(padapter, NULL); + set_tx_beacon_cmd(padapter); + } + } + +#ifdef CONFIG_CONCURRENT_MODE + if(check_buddy_fwstate(padapter, WIFI_AP_STATE)) + { + //send_beacon(padapter); + if(padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE) + { + //tx_beacon_hdl(padapter, NULL); + set_tx_beacon_cmd(padapter->pbuddy_adapter); + } + } +#endif + } +#endif //CONFIG_INTERRUPT_BASED_TXBCN + + if (sdio_hisr & HCI_HISR_C2HCMD) + { + RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: C2H Command\n", __func__)); +//TODO +// rtw_c2h_wk_cmd(padapter); + } + + if (sdio_hisr & HCI_HISR_RX_REQUEST)// || sdio_hisr & SPI_HISR_RXFOVW) + { + struct recv_buf *precvbuf; + struct fifo_more_data more_data = {0}; + + //RT_TRACE(_module_hci_ops_c_,_drv_info_, ("%s: RX Request, size=%d\n", __func__, pdvobj->SdioRxFIFOSize)); + + sdio_hisr ^= HCI_HISR_RX_REQUEST; + + do { + more_data.more_data = 0; + more_data.len = 0; + + if (pdvobj->SdioRxFIFOSize == 0) + { + u16 val = 0; + //s32 ret; //LZM_TODO + + RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s, %d, read RXFIFOsize again size=%d\n", __FUNCTION__, __LINE__, pdvobj->SdioRxFIFOSize)); + + val = rtw_read16(padapter, LOCAL_REG_RX0_REQ_LEN_1_BYTE); + //if (!ret) { + pdvobj->SdioRxFIFOSize = val; + RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: RX_REQUEST, read RXFIFOsize again size=%d\n", __func__, pdvobj->SdioRxFIFOSize)); + //} else { + // RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: RX_REQUEST, read RXFIFOsize ERROR!!\n", __func__)); + //} + RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s, %d, read RXFIFOsize again size=%d\n", __FUNCTION__, __LINE__, pdvobj->SdioRxFIFOSize)); + } + + if (pdvobj->SdioRxFIFOSize != 0) + { +#ifdef RTL8723A_SDIO_LOOPBACK + sd_recv_loopback(padapter, pdvobj->SdioRxFIFOSize); +#else + if (sdio_hisr & HCI_HISR_RXFOVW) + RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s RXFOVW RX\n", __func__)); + + precvbuf = rtw_recv_rxfifo(padapter, pdvobj->SdioRxFIFOSize, &more_data); + if (precvbuf) + rtw_rxhandler(padapter, precvbuf); + + if (more_data.more_data) { + pdvobj->SdioRxFIFOSize = more_data.len; + } else { + pdvobj->SdioRxFIFOSize = 0; + } +#endif + //If Rx_request ISR is set, execute receive tasklet (sdio_hisr & SPI_HISR_RX_REQUEST) +#if defined(CONFIG_ISR_THREAD_MODE_INTERRUPT) && defined(CONFIG_RECV_TASKLET_THREAD) + rtw_wakeup_task(&padapter->recvtasklet_thread); +#endif + } + +#ifdef CONFIG_INTERRUPT_BASED_TXBCN +{ + //Prevent BCN update not realtime in ap mode - Alex Fang + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + if((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) && (pmlmepriv->update_bcn == _TRUE)) + break; +} +#endif + } while (more_data.more_data || pdvobj->SdioRxFIFOSize); +#ifdef PLATFORM_LINUX +#ifdef CONFIG_GSPI_HCI + tasklet_schedule(&padapter->recvpriv.recv_tasklet); +#endif +#endif + } +} + + +void spi_int_hdl(PADAPTER padapter) +{ + struct dvobj_priv *pdvobj = padapter->dvobj; + u32 sdio_hisr = 0; + //s32 ret; + + if ((padapter->bDriverStopped == _TRUE) || + (padapter->bSurpriseRemoved == _TRUE)) + return; + + sdio_hisr = rtw_read32(padapter, LOCAL_REG_HISR);//, &ret); + //if (!ret) { + // RT_TRACE(_module_hci_ops_c_, _drv_err_, ("%s: read SDIO_REG_HISR FAIL!!\n", __func__)); + // return; + //} + pdvobj->SdioRxFIFOSize = rtw_read16(padapter, LOCAL_REG_RX0_REQ_LEN_1_BYTE);//, &ret); + + //if (!ret) { + // RT_TRACE(_module_hci_ops_c_, _drv_err_, ("%s: read SPI_REG_RX0_REQ_LEN FAIL!!\n", __func__)); + // return; + //} + + if (sdio_hisr & pdvobj->sdio_himr) + { + u32 v32; + + sdio_hisr &= pdvobj->sdio_himr; + + // clear HISR + v32 = sdio_hisr & MASK_SPI_HISR_CLEAR; + if (v32) { + rtw_write32(padapter, LOCAL_REG_HISR, v32);//, &ret); + } + + spi_int_dpc(padapter, sdio_hisr); + } else { + //RT_TRACE(_module_hci_ops_c_, _drv_err_, + // ("%s: HISR(0x%08x) and HIMR(0x%08x) not match!\n", + // __FUNCTION__, sdio_hisr, pdvobj->sdio_himr)); + } +} + +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_spec.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_spec.h new file mode 100644 index 0000000..5b3b8d5 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_spec.h @@ -0,0 +1,193 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + *******************************************************************************/ + +#ifndef __GSDIO_SPEC_H__ +#define __GSDIO_SPEC_H__ + + +#define SPI_LOCAL_DOMAIN 0x0 +#define WLAN_IOREG_DOMAIN 0x8 +#define FW_FIFO_DOMAIN 0x4 +#define TX_HIQ_DOMAIN 0xc +#define TX_MIQ_DOMAIN 0xd +#define TX_LOQ_DOMAIN 0xe +#define RX_RXFIFO_DOMAIN 0x1f + +//IO Bus domain address mapping +#define DEFUALT_OFFSET 0x0 +#define SPI_LOCAL_OFFSET 0x10250000 +#define WLAN_IOREG_OFFSET 0x10260000 +#define FW_FIFO_OFFSET 0x10270000 +#define TX_HIQ_OFFSET 0x10310000 +#define TX_MIQ_OFFSET 0x1032000 +#define TX_LOQ_OFFSET 0x10330000 +#define RX_RXOFF_OFFSET 0x10340000 + +#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13] +#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13] +#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13] +#define WLAN_TX_EXQ_DEVICE_ID 3 // 0b[16], 011b[15:13] +#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13] +#define WLAN_IOREG_DEVICE_ID 8 // 1b[16] + +//SPI Tx Free Page Index +#define HI_QUEUE_IDX 0 +#define MID_QUEUE_IDX 1 +#define LOW_QUEUE_IDX 2 +#define PUBLIC_QUEUE_IDX 3 + +#define MAX_TX_QUEUE 3 // HIQ, MIQ and LOQ +#define MAX_RX_QUEUE 1 + +//SPI Local registers +#define SPI_REG_TX_CTRL (SPI_LOCAL_OFFSET | 0x0000) // SPI Tx Control +#define SPI_REG_STATUS_RECOVERY (SPI_LOCAL_OFFSET | 0x0004) +#define SPI_REG_INT_TIMEOUT (SPI_LOCAL_OFFSET | 0x0006) +#define SPI_REG_HIMR (SPI_LOCAL_OFFSET | 0x0014) // SPI Host Interrupt Mask +#define SPI_REG_HISR (SPI_LOCAL_OFFSET | 0x0018) // SPI Host Interrupt Service Routine +#define SPI_REG_RX0_REQ_LEN (SPI_LOCAL_OFFSET | 0x001C) // RXDMA Request Length +#define SPI_REG_FREE_TXPG (SPI_LOCAL_OFFSET | 0x0020) // Free Tx Buffer Page +#define SPI_REG_HCPWM1 (SPI_LOCAL_OFFSET | 0x0024) // HCI Current Power Mode 1 +#define SPI_REG_HCPWM2 (SPI_LOCAL_OFFSET | 0x0026) // HCI Current Power Mode 2 +#define SPI_REG_HTSFR_INFO (SPI_LOCAL_OFFSET | 0x0030) // HTSF Informaion +#define SPI_REG_HRPWM1 (SPI_LOCAL_OFFSET | 0x0080) // HCI Request Power Mode 1 +#define SPI_REG_HRPWM2 (SPI_LOCAL_OFFSET | 0x0082) // HCI Request Power Mode 2 +#define SPI_REG_HPS_CLKR (SPI_LOCAL_OFFSET | 0x0084) // HCI Power Save Clock +#define SPI_REG_HSUS_CTRL (SPI_LOCAL_OFFSET | 0x0086) // SPI HCI Suspend Control +#define SPI_REG_HIMR_ON (SPI_LOCAL_OFFSET | 0x0090) //SPI Host Extension Interrupt Mask Always +#define SPI_REG_HISR_ON (SPI_LOCAL_OFFSET | 0x0091) //SPI Host Extension Interrupt Status Always +#define SPI_REG_CFG (SPI_LOCAL_OFFSET | 0x00F0) //SPI Configuration Register + +#define LOCAL_REG_TX_CTRL (SPI_REG_TX_CTRL |SPI_LOCAL_OFFSET) +#define LOCAL_REG_STATUS_RECOVERY (SPI_REG_STATUS_RECOVERY |SPI_LOCAL_OFFSET) +#define LOCAL_REG_INT_TIMEOUT (SPI_REG_INT_TIMEOUT |SPI_LOCAL_OFFSET) +#define LOCAL_REG_HIMR (SPI_REG_HIMR |SPI_LOCAL_OFFSET) +#define LOCAL_REG_HISR (SPI_REG_HISR |SPI_LOCAL_OFFSET) +#define LOCAL_REG_RX0_REQ_LEN_1_BYTE (SPI_REG_RX0_REQ_LEN |SPI_LOCAL_OFFSET) +#define LOCAL_REG_FREE_TXPG (SPI_REG_FREE_TXPG |SPI_LOCAL_OFFSET) +#define LOCAL_REG_HRPWM1 (SPI_REG_HRPWM1 |SPI_LOCAL_OFFSET) +#define LOCAL_REG_HCPWM1 (SPI_REG_HCPWM1 |SPI_LOCAL_OFFSET) + +#define HCI_HIMR_DISABLED 0 + +//SPI HIMR MASK diff with SDIO +#define HCI_HISR_RX_REQUEST BIT(0) +#define HCI_HISR_AVAL BIT(1) +#define HCI_HISR_TXERR BIT(2) +#define HCI_HISR_RXERR BIT(3) +#define HCI_HISR_TXFOVW BIT(4) +#define HCI_HISR_RXFOVW BIT(5) +#define HCI_HISR_TXBCNOK BIT(6) +#define HCI_HISR_TXBCNERR BIT(7) +#define HCI_HISR_BCNERLY_INT BIT(16) +#define HCI_HISR_C2HCMD BIT(17) +#define HCI_HISR_CPWM1 BIT(18) +#define HCI_HISR_CPWM2 BIT(19) +#define HCI_HISR_HSISR_IND BIT(20) +#define HCI_HISR_GTINT3_IND BIT(21) +#define HCI_HISR_GTINT4_IND BIT(22) +#define HCI_HISR_PSTIMEOUT BIT(23) +#define HCI_HISR_OCPINT BIT(24) +#define HCI_HISR_ATIMEND BIT(25) +#define HCI_HISR_ATIMEND_E BIT(26) +#define HCI_HISR_CTWEND BIT(27) + +//SPI HIMR MASK diff with SDIO +#define HCI_HIMR_RX_REQUEST BIT(0) +#define HCI_HIMR_AVAL BIT(1) +#define HCI_HIMR_TXERR BIT(2) +#define HCI_HIMR_RXERR BIT(3) +#define HCI_HIMR_TXFOVW BIT(4) +#define HCI_HIMR_RXFOVW BIT(5) +#define HCI_HIMR_TXBCNOK BIT(6) +#define HCI_HIMR_TXBCNERR BIT(7) +#define HCI_HIMR_BCNERLY_INT BIT(16) +#define HCI_HIMR_ATIMEND BIT(17) +#define HCI_HIMR_ATIMEND_E BIT(18) +#define HCI_HIMR_CTWEND BIT(19) +#define HCI_HIMR_C2HCMD BIT(20) +#define HCI_HIMR_CPWM1 BIT(21) +#define HCI_HIMR_CPWM2 BIT(22) +#define HCI_HIMR_HSISR_IND BIT(23) +#define HCI_HIMR_GTINT3_IND BIT(24) +#define HCI_HIMR_GTINT4_IND BIT(25) +#define HCI_HIMR_PSTIMEOUT BIT(26) +#define HCI_HIMR_OCPINT BIT(27) +#define HCI_HIMR_TSF_BIT32_TOGGLE BIT(29) + +#define MASK_SPI_HISR_CLEAR (HCI_HIMR_TXERR |\ + HCI_HIMR_RXERR |\ + HCI_HIMR_TXFOVW |\ + HCI_HIMR_RXFOVW |\ + HCI_HIMR_TXBCNOK |\ + HCI_HIMR_TXBCNERR |\ + HCI_HIMR_C2HCMD |\ + HCI_HIMR_CPWM1 |\ + HCI_HIMR_CPWM2 |\ + HCI_HIMR_HSISR_IND |\ + HCI_HIMR_GTINT3_IND |\ + HCI_HIMR_GTINT4_IND |\ + HCI_HIMR_PSTIMEOUT |\ + HCI_HIMR_OCPINT) + +#define REG_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)//(x<<(unsigned int)24) +#define REG_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16) +#define REG_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0) +#define REG_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5) +#define REG_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7) + +#define FIFO_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)//(x<<(unsigned int)24) +//#define FIFO_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16) +#define FIFO_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0) +#define FIFO_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5) +#define FIFO_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7) + + +//get status dword0 +#define GET_STATUS_PUB_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 24, 8) +#define GET_STATUS_HI_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 18, 6) +#define GET_STATUS_MID_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 12, 6) +#define GET_STATUS_LOW_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 6, 6) +#define GET_STATUS_HISR_HI6BIT(status) LE_BITS_TO_4BYTE(status, 0, 6) + +//get status dword1 +#define GET_STATUS_HISR_MID8BIT(status) LE_BITS_TO_4BYTE(status + 4, 24, 8) +#define GET_STATUS_HISR_LOW8BIT(status) LE_BITS_TO_4BYTE(status + 4, 16, 8) +#define GET_STATUS_ERROR(status) LE_BITS_TO_4BYTE(status + 4, 17, 1) +#define GET_STATUS_INT(status) LE_BITS_TO_4BYTE(status + 4, 16, 1) +#define GET_STATUS_RX_LENGTH(status) LE_BITS_TO_4BYTE(status + 4, 0, 16) + + +#define RXDESC_SIZE 24 + +#define TX_FREE_PG_QUEUE 4 // The number of Tx FIFO free page +#define TX_FIFO_PAGE_SZ 128 + +struct spi_more_data { + unsigned long more_data; + unsigned long len; +}; + +extern BUS_DRV_OPS_T bus_driver_ops; + +extern u8 spi_query_status_info(struct dvobj_priv *pdvobj); + +extern void sdio_set_intf_ops(struct _io_ops *pops); + +#endif //__GSPI_SPEC_H__ diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_intfs.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_intfs.h new file mode 100644 index 0000000..46b3453 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_intfs.h @@ -0,0 +1,161 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __FREERTOS_INTFS_H_ +#define __FREERTOS_INTFS_H_ + +//TODO +#if 0 + +struct intf_priv { + + u8 *intf_dev; + u32 max_iosz; //USB2.0: 128, USB1.1: 64, SDIO:64 + u32 max_xmitsz; //USB2.0: unlimited, SDIO:512 + u32 max_recvsz; //USB2.0: unlimited, SDIO:512 + + volatile u8 *io_rwmem; + volatile u8 *allocated_io_rwmem; + u32 io_wsz; //unit: 4bytes + u32 io_rsz;//unit: 4bytes + u8 intf_status; + + void (*_bus_io)(u8 *priv); + +/* +Under Sync. IRP (SDIO/USB) +A protection mechanism is necessary for the io_rwmem(read/write protocol) + +Under Async. IRP (SDIO/USB) +The protection mechanism is through the pending queue. +*/ + + _mutex ioctl_mutex; + + +#ifdef PLATFORM_LINUX + #ifdef CONFIG_USB_HCI + // when in USB, IO is through interrupt in/out endpoints + struct usb_device *udev; + PURB piorw_urb; + u8 io_irp_cnt; + u8 bio_irp_pending; + _sema io_retevt; + _timer io_timer; + u8 bio_irp_timeout; + u8 bio_timer_cancel; + #endif +#endif + +#ifdef PLATFORM_OS_XP + #ifdef CONFIG_SDIO_HCI + // below is for io_rwmem... + PMDL pmdl; + PSDBUS_REQUEST_PACKET sdrp; + PSDBUS_REQUEST_PACKET recv_sdrp; + PSDBUS_REQUEST_PACKET xmit_sdrp; + + PIRP piorw_irp; + + #endif + #ifdef CONFIG_USB_HCI + PURB piorw_urb; + PIRP piorw_irp; + u8 io_irp_cnt; + u8 bio_irp_pending; + _sema io_retevt; + #endif +#endif + +}; + + +#ifdef CONFIG_R871X_TEST +int rtw_start_pseudo_adhoc(_adapter *padapter); +int rtw_stop_pseudo_adhoc(_adapter *padapter); +#endif + +#endif //#if 0 + +typedef struct _driver_priv { + int drv_registered; + + _mutex hw_init_mutex; +#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_DUALMAC_CONCURRENT) + //global variable + _mutex h2c_fwcmd_mutex; + _mutex setch_mutex; + _mutex setbw_mutex; +#endif +} drv_priv, *pdrv_priv; + + +struct net_device *rtw_init_netdev(_adapter *padapter); +void rtw_os_indicate_disconnect( _adapter *adapter ); + +#ifdef CONFIG_PROC_DEBUG +void rtw_proc_init_one(struct net_device *dev); +void rtw_proc_remove_one(struct net_device *dev); +#else +//static void should be declared in .c file +//proc is not supported in freertos +//static void rtw_proc_init_one(struct net_device *dev){} +//static void rtw_proc_remove_one(struct net_device *dev){} +#define rtw_proc_init_one(dev) +#define rtw_proc_remove_one(dev) +#endif + +extern int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen); +extern void rtw_os_indicate_connect(_adapter *adapter); +extern void indicate_wx_custom_event(_adapter *padapter, char *msg); +extern int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname); +extern void netdev_lwip_post_sleep_processing(void); +extern void wireless_send_event(struct net_device *dev, unsigned int cmd, union iwreq_data *wrqu, char *extra); + +#ifdef CONFIG_CONCURRENT_MODE +struct _io_ops; +_adapter *rtw_drv_if2_init(_adapter *primary_padapter, char *name, void (*set_intf_ops)(struct _io_ops *pops)); +void rtw_drv_if2_free(_adapter *pbuddy_padapter); +#endif + +#if defined(CONFIG_ISR_THREAD_MODE_POLLING) || defined(CONFIG_ISR_THREAD_MODE_INTERRUPT) +extern thread_return rtw_interrupt_thread(thread_context context); +#endif + +#ifdef CONFIG_RECV_TASKLET_THREAD +extern thread_return rtw_recv_tasklet(thread_context context); +#endif + +#ifdef CONFIG_XMIT_TASKLET_THREAD +extern thread_return rtw_xmit_tasklet(thread_context context); +#endif + +extern struct net_device *rtw_drv_probe(struct net_device* parent_dev, u32 mode); //Wlan driver init entry +extern void rtw_drv_entry(void); +extern void rtw_drv_halt(void); +extern int rtw_dev_remove(struct net_device *pnetdev); +extern int rtw_ioctl(struct net_device *dev, struct iwreq *rq, int cmd); + +#if defined(CONFIG_LX_HCI) +u32 lextra_bus_dma_Interrupt (void* data); +#endif + +#endif //__FREERTOS_INTFS_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_recv.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_recv.h new file mode 100644 index 0000000..3cd391c --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_recv.h @@ -0,0 +1,55 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __FREERTOS_RECV_H_ +#define __FREERTOS_RECV_H_ + +extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter); +extern void _rtw_free_recv_priv (struct recv_priv *precvpriv); + + +extern s32 rtw_recv_entry(union recv_frame *precv_frame); +extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame); +extern void rtw_recv_returnpacket(IN _nic_hdl cnxt, IN _pkt *preturnedpkt); + +extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame); +#if BAD_MIC_COUNTERMEASURE +extern void rtw_handle_tkip_mic_err(_adapter *padapter,u8 bgroup); +#endif + +int rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter); +void rtw_free_recv_priv (struct recv_priv *precvpriv); + + +int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter); +int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe); +void rtw_os_recv_resource_free(struct recv_priv *precvpriv); + + +int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf); +int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf); + +void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf); + +void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl); + +void rltk_netif_rx(struct sk_buff *skb); + +#endif //__FREERTOS_RECV_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_skbuff.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_skbuff.h new file mode 100644 index 0000000..1daf180 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_skbuff.h @@ -0,0 +1,72 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _FREERTOS_SKBUFF_H_ +#define _FREERTOS_SKBUFF_H_ + +#if (RTL8195A_SUPPORT == 1) +// For Lextra(PCI-E like interface), RX buffer along with its skb is required to be +// pre-allocation and set into rx buffer descriptor ring during initialization. + #if (SKB_PRE_ALLOCATE_RX==1) + #define MAX_SKB_BUF_NUM (8 + 4) //tx+rx (8 + RX_Q_DESC_NUM) Reduce rx skb number due to memory limitation + #define MAX_LOCAL_SKB_NUM (10 + 18) //tx+rx + #else + #if WIFI_LOGO_CERTIFICATION + #define MAX_SKB_BUF_NUM 10 //tx+rx, ping 10k test + #elif defined(CONFIG_INIC_EN)&&(CONFIG_INIC_EN==1) //For iNIC throughput request + #define MAX_SKB_BUF_NUM 59 + #else + #define MAX_SKB_BUF_NUM 8 //tx+rx + #endif + #define MAX_LOCAL_SKB_NUM (MAX_SKB_BUF_NUM + 2) //tx+rx, +2: AP mode broadcast + #endif +#elif (RTL8711B_SUPPORT == 1) + #if (SKB_PRE_ALLOCATE_RX==1) + #define MAX_SKB_BUF_NUM (8 + 4) //tx+rx (8 + RX_Q_DESC_NUM) Reduce rx skb number due to memory limitation + #define MAX_LOCAL_SKB_NUM (10 + 18) //tx+rx + #else + #if WIFI_LOGO_CERTIFICATION + #define MAX_SKB_BUF_NUM 10 //tx+rx, ping 10k test + #elif defined(CONFIG_INIC_EN)&&(CONFIG_INIC_EN==1) //For iNIC throughput request + #define MAX_SKB_BUF_NUM 59 + #else + #define MAX_SKB_BUF_NUM 8 //tx+rx + #endif + #define MAX_LOCAL_SKB_NUM (MAX_SKB_BUF_NUM + 2) //tx+rx, +2: AP mode broadcast + #endif +#else +#ifndef CONFIG_DONT_CARE_TP +#ifndef CONFIG_HIGH_TP +#define MAX_LOCAL_SKB_NUM 10 +#define MAX_SKB_BUF_NUM 7 +#else +#define MAX_LOCAL_SKB_NUM 100 +#define MAX_SKB_BUF_NUM 100 +#endif +#else +#define MAX_LOCAL_SKB_NUM 10 +#define MAX_TX_SKB_BUF_NUM 6 +#define MAX_RX_SKB_BUF_NUM 1 +#endif +#endif + +extern int max_local_skb_num; +extern int max_skb_buf_num; + +#endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_xmit.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_xmit.h new file mode 100644 index 0000000..279c012 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_xmit.h @@ -0,0 +1,62 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __FREERTOS_XMIT_H_ +#define __FREERTOS_XMIT_H_ + +struct pkt_file { + _pkt *pkt; + SIZE_T pkt_len; //the remainder length of the open_file + _buffer *cur_buffer; + u8 *buf_start; + u8 *cur_addr; + SIZE_T buf_len; +}; + +//Decrease xmit frame due to memory limitation - Alex Fang +#if USE_XMIT_EXTBUFF +#define NR_XMITFRAME 16 //NR_XMITBUFF + NR_XMIT_EXTBUFF +#else +#ifndef CONFIG_HIGH_TP +//#define NR_XMITFRAME 8 +#define NR_XMITFRAME 6 //Decrease recv frame due to memory limitation - YangJue +#else +#define NR_XMITFRAME 100 +#endif +#endif + +extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); +extern void rtw_os_xmit_schedule(_adapter *padapter); + +extern int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 alloc_sz); +extern void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 free_sz); + +extern void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib); + +extern uint rtw_remainder_len(struct pkt_file *pfile); +extern void _rtw_open_pktfile(_pkt *pkt, struct pkt_file *pfile); +extern uint _rtw_pktfile_read (struct pkt_file *pfile, u8 *rmem, uint rlen); +extern sint rtw_endofpktfile (struct pkt_file *pfile); + +extern void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt); +extern void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe); + + +#endif //__FREERTOS_XMIT_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h index bc4dbf4..c58d89f 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h @@ -1,10 +1,27 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ****************************************************************************** + * Wrapper provide a linux-like interface + ************************************************************************/ #ifndef __WRAPPER_H__ #define __WRAPPER_H__ -/************************************************************************** - * Wrapper provide a linux-like interface - * - * Copyright (c) 2013 Realtek Semiconductor Corp. - ************************************************************************/ + //----- ------------------------------------------------------------------ // Include Files @@ -13,8 +30,11 @@ #include #include "wireless.h" #include +#ifdef PLATFORM_FREERTOS #include "freertos_service.h" - +#elif defined(PLATFORM_CMSIS_RTOS) +#include "rtx_service.h" +#endif #ifndef __LIST_H #warning "DLIST_NOT_DEFINE!!!!!!" //----- ------------------------------------------------------------------ @@ -392,27 +412,27 @@ struct net_device_stats { }; struct net_device { - char name[16]; //+0 - void *priv; //+16 _adapter /* pointer to private data */ - unsigned char dev_addr[6]; //+20 /* set during bootup */ - int (*init)(void); //+28 - int (*open)(struct net_device *dev); //+32 - int (*stop)(struct net_device *dev); //+36 - int (*hard_start_xmit)(struct sk_buff *skb, struct net_device *dev); //+40 - int (*do_ioctl)(struct net_device *dev, struct iwreq *ifr, int cmd); //+44 - struct net_device_stats* (*get_stats)(struct net_device *dev); //+48 + char name[16]; + void *priv; /* pointer to private data */ + unsigned char dev_addr[6]; /* set during bootup */ + int (*init)(void); + int (*open)(struct net_device *dev); + int (*stop)(struct net_device *dev); + int (*hard_start_xmit)(struct sk_buff *skb, struct net_device *dev); + int (*do_ioctl)(struct net_device *dev, struct iwreq *ifr, int cmd); + struct net_device_stats* (*get_stats)(struct net_device *dev); }; typedef struct { - struct net_device *dev; //+0 /* Binding wlan driver netdev */ - void *skb; //+4 /* pending Rx packet */ - unsigned int tx_busy; //+8 - unsigned int rx_busy; //+12 - unsigned char enable; //+16 - unsigned char mac[6]; //+17..23 + struct net_device *dev; /* Binding wlan driver netdev */ + void *skb; /* pending Rx packet */ + unsigned int tx_busy; + unsigned int rx_busy; + unsigned char enable; + unsigned char mac[6]; } Rltk_wlan_t; -#define netdev_priv(dev) dev->priv +#define netdev_priv(dev) dev->priv extern struct net_device *alloc_etherdev(int sizeof_priv); void free_netdev(struct net_device *dev); @@ -424,13 +444,13 @@ int dev_alloc_name(struct net_device *net_dev, const char *ifname); //----- ------------------------------------------------------------------ void init_timer(struct timer_list *timer); void mod_timer(struct timer_list *timer, u32 delay_time_ms); -void cancel_timer_ex(struct timer_list * timer); +void cancel_timer_ex(struct timer_list * timer); void del_timer_sync(struct timer_list * timer); void init_timer_wrapper(void); void deinit_timer_wrapper(void); void rtw_init_timer(_timer *ptimer, void *adapter, TIMER_FUN pfunc,void* cntx, const char *name); -void rtw_set_timer(_timer *ptimer, u32 delay_time); +void rtw_set_timer(_timer *ptimer,u32 delay_time); u8 rtw_cancel_timer(_timer *ptimer); void rtw_del_timer(_timer *ptimer); diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c index 3ebfe7f..249b007 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c @@ -22,16 +22,24 @@ #include #include #include +#if !DEVICE_EMAC #include #include +#endif #include #include + //----- ------------------------------------------------------------------ // External Reference //----- ------------------------------------------------------------------ #if (CONFIG_LWIP_LAYER == 1) -extern struct netif xnetif[]; //LWIP netif +#if DEVICE_EMAC + extern struct netif *xnetif[]; +#else + extern struct netif xnetif[]; //LWIP netif #endif +#endif + /** * rltk_wlan_set_netif_info - set netif hw address and register dev pointer to netif device @@ -46,9 +54,13 @@ extern struct netif xnetif[]; //LWIP netif void rltk_wlan_set_netif_info(int idx_wlan, void * dev, unsigned char * dev_addr) { #if (CONFIG_LWIP_LAYER == 1) +#if DEVICE_EMAC + rtw_memcpy(xnetif[idx_wlan]->hwaddr, dev_addr, 6); +#else rtw_memcpy(xnetif[idx_wlan].hwaddr, dev_addr, 6); xnetif[idx_wlan].state = dev; #endif +#endif } /** @@ -62,45 +74,47 @@ void rltk_wlan_set_netif_info(int idx_wlan, void * dev, unsigned char * dev_addr */ int rltk_wlan_send(int idx, struct eth_drv_sg *sg_list, int sg_len, int total_len) { +#if (CONFIG_LWIP_LAYER == 1) struct eth_drv_sg *last_sg; - struct sk_buff *skb = NULL; - int ret = 0; + struct sk_buff *skb = NULL; + int ret = 0; if(idx == -1){ DBG_ERR("netif is DOWN"); return -1; } DBG_TRACE("%s is called", __FUNCTION__); - - save_and_cli(); + + save_and_cli(); if(rltk_wlan_check_isup(idx)) - rltk_wlan_tx_inc(idx); + rltk_wlan_tx_inc(idx); else { DBG_ERR("netif is DOWN"); restore_flags(); return -1; } - restore_flags(); + restore_flags(); - skb = rltk_wlan_alloc_skb(total_len); - if (skb == NULL) { + skb = rltk_wlan_alloc_skb(total_len); + if (skb == NULL) { //DBG_ERR("rltk_wlan_alloc_skb() for data len=%d failed!", total_len); - ret = -1; - goto exit; - } + ret = -1; + goto exit; + } for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) { rtw_memcpy(skb->tail, (void *)(sg_list->buf), sg_list->len); - skb_put(skb, sg_list->len); - } + skb_put(skb, sg_list->len); + } - rltk_wlan_send_skb(idx, skb); + rltk_wlan_send_skb(idx, skb); exit: - save_and_cli(); - rltk_wlan_tx_dec(idx); - restore_flags(); - return ret; + save_and_cli(); + rltk_wlan_tx_dec(idx); + restore_flags(); + return ret; +#endif } /** @@ -113,43 +127,56 @@ exit: */ void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len) { +#if (CONFIG_LWIP_LAYER == 1) struct eth_drv_sg *last_sg; - struct sk_buff *skb; - + struct sk_buff *skb; + DBG_TRACE("%s is called", __FUNCTION__); + + if (!rltk_wlan_check_isup(idx)) + return; + if(idx == -1){ DBG_ERR("skb is NULL"); return; } - skb = rltk_wlan_get_recv_skb(idx); + + skb = rltk_wlan_get_recv_skb(idx); DBG_ASSERT(skb, "No pending rx skb"); for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) { - if (sg_list->buf != 0) { + if (sg_list->buf != 0) { rtw_memcpy((void *)(sg_list->buf), skb->data, sg_list->len); - skb_pull(skb, sg_list->len); - } - } + skb_pull(skb, sg_list->len); + } + } +#endif } int netif_is_valid_IP(int idx, unsigned char *ip_dest) { #if CONFIG_LWIP_LAYER == 1 - struct netif * pnetif = &xnetif[idx]; - struct ip_addr addr = { 0 }; -#ifdef CONFIG_MEMORY_ACCESS_ALIGNED - unsigned int temp; - memcpy(&temp, ip_dest, sizeof(unsigned int)); - u32_t *ip_dest_addr = &temp; +#if DEVICE_EMAC + struct netif *pnetif = xnetif[idx]; #else - u32_t *ip_dest_addr = (u32_t*)ip_dest; + struct netif *pnetif = &xnetif[idx]; #endif - addr.addr = *ip_dest_addr; - + + ip_addr_t addr = { 0 }; + +#ifdef CONFIG_MEMORY_ACCESS_ALIGNED + unsigned int temp; + memcpy(&temp, ip_dest, sizeof(unsigned int)); + u32_t *ip_dest_addr = &temp; +#else + u32_t *ip_dest_addr = (u32_t*)ip_dest; +#endif + addr.addr = *ip_dest_addr; + if(pnetif->ip_addr.addr == 0) - return 1; + return 1; - if(ip_addr_ismulticast(&addr) || ip_addr_isbroadcast(&addr,pnetif)){ + if(ip_addr_ismulticast(&addr) || ip_addr_isbroadcast(&addr,pnetif)){ return 1; } @@ -163,34 +190,43 @@ int netif_is_valid_IP(int idx, unsigned char *ip_dest) #endif #ifdef CONFIG_DONT_CARE_TP if(pnetif->flags & NETIF_FLAG_IPSWITCH) - return 1; + return 1; else #endif - return 0; + return 0; } -int netif_get_idx(struct netif* pnetif) +int netif_get_idx(struct netif *pnetif) { -#if CONFIG_LWIP_LAYER == 1 - int idx = pnetif - xnetif; - - switch(idx) { - case 0: - return 0; - case 1: - return 1; - default: - return -1; - } +#if (CONFIG_LWIP_LAYER == 1) +#if DEVICE_EMAC + if (pnetif == xnetif[0]) + return 0; +#else + int idx = pnetif - xnetif; + + switch(idx) { + case 0: + return 0; + case 1: + return 1; + default: + return -1; + } +#endif #else - return -1; + return -1; #endif } unsigned char *netif_get_hwaddr(int idx_wlan) { #if (CONFIG_LWIP_LAYER == 1) +#if DEVICE_EMAC + return xnetif[idx_wlan]->hwaddr; +#else return xnetif[idx_wlan].hwaddr; +#endif #else return NULL; #endif @@ -199,7 +235,11 @@ unsigned char *netif_get_hwaddr(int idx_wlan) void netif_rx(int idx, unsigned int len) { #if (CONFIG_LWIP_LAYER == 1) - ethernetif_recv(&xnetif[idx], len); +#if DEVICE_EMAC + wlan_emac_recv(xnetif[idx], len); +#else + ethernetif_recv(&xnetif[idx], len); +#endif #endif #if (CONFIG_INIC_EN == 1) inic_netif_rx(idx, len); @@ -209,14 +249,30 @@ void netif_rx(int idx, unsigned int len) void netif_post_sleep_processing(void) { #if (CONFIG_LWIP_LAYER == 1) +#if DEVICE_EMAC +#else lwip_POST_SLEEP_PROCESSING(); //For FreeRTOS tickless to enable Lwip ARP timer when leaving IPS - Alex Fang #endif +#endif } void netif_pre_sleep_processing(void) { #if (CONFIG_LWIP_LAYER == 1) - lwip_PRE_SLEEP_PROCESSING(); +#if DEVICE_EMAC +#else + lwip_PRE_SLEEP_PROCESSING(); +#endif #endif } +#ifdef CONFIG_WOWLAN +unsigned char *rltk_wlan_get_ip(int idx){ +#if (CONFIG_LWIP_LAYER == 1) + return LwIP_GetIP(&xnetif[idx]); +#else + return NULL; +#endif +} +#endif + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.h index 16107d2..2553c99 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.h @@ -1,3 +1,18 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #ifndef __LWIP_INTF_H__ #define __LWIP_INTF_H__ @@ -7,18 +22,23 @@ extern "C" { #include #include -#include "ethernetif.h" -#if 0 // moved to ethernetif.h by jimmy 12/2/2015 + +struct netif; + //----- ------------------------------------------------------------------ // Ethernet Buffer //----- ------------------------------------------------------------------ +#if DEVICE_EMAC struct eth_drv_sg { - unsigned int buf; - unsigned int len; + unsigned int buf; + unsigned int len; }; #define MAX_ETH_DRV_SG 32 #define MAX_ETH_MSG 1540 +extern void wlan_emac_recv(struct netif *netif, int len); +#else +#include "ethernetif.h" // moved to ethernetif.h by jimmy 12/2/2015 #endif //----- ------------------------------------------------------------------ // Wlan Interface Provided @@ -37,7 +57,7 @@ unsigned char rltk_wlan_running(unsigned char idx); // interface is up. 0: inte //----- ------------------------------------------------------------------ // Network Interface provided //----- ------------------------------------------------------------------ -struct netif; + int netif_is_valid_IP(int idx,unsigned char * ip_dest); int netif_get_idx(struct netif *pnetif); unsigned char *netif_get_hwaddr(int idx_wlan); @@ -45,11 +65,18 @@ void netif_rx(int idx, unsigned int len); void netif_post_sleep_processing(void); void netif_pre_sleep_processing(void); #if (CONFIG_LWIP_LAYER == 1) +#if !DEVICE_EMAC extern void ethernetif_recv(struct netif *netif, int total_len); +#endif extern void lwip_PRE_SLEEP_PROCESSING(void); extern void lwip_POST_SLEEP_PROCESSING(void); #endif //CONFIG_LWIP_LAYER == 1 + +#ifdef CONFIG_WOWLAN +extern unsigned char *rltk_wlan_get_ip(int idx); +#endif + #ifdef __cplusplus } #endif diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/netdev.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/netdev.h new file mode 100644 index 0000000..ae5046a --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/netdev.h @@ -0,0 +1,113 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __NETDEV_H_ +#define __NETDEV_H_ + +/* Define compilor specific symbol */ +// +// inline function +// + +#if defined ( __ICCARM__ ) +#define __inline__ inline +#define __inline inline +#define __inline_definition //In dialect C99, inline means that a function's definition is provided + //only for inlining, and that there is another definition + //(without inline) somewhere else in the program. + //That means that this program is incomplete, because if + //add isn't inlined (for example, when compiling without optimization), + //then main will have an unresolved reference to that other definition. + + // Do not inline function is the function body is defined .c file and this + // function will be called somewhere else, otherwise there is compile error +#elif defined ( __CC_ARM ) +#define __inline__ __inline //__linine__ is not supported in keil compilor, use __inline instead +#define inline __inline +#define __inline_definition // for dialect C99 +#elif defined ( __GNUC__ ) +#define __inline__ inline +#define __inline inline +#define __inline_definition inline +#endif + +#include +#include +#if defined( PLATFORM_FREERTOS) +#include "freertos_service.h" +#elif defined( PLATFORM_ECOS) +#include "ecos/ecos_service.h" +#elif defined(PLATFORM_CMSIS_RTOS) +#include "rtx_service.h" +#endif + + +// rtl8195a uses receive_tasklet for wps +// 8189em uses interrupt_thread for wps +#if defined(CONFIG_WPS) +#define RECV_STACK_FOR_WPS 448//512//384 //Change to 512 for WPS (IAR STM32) stack overflow +#else +#define RECV_STACK_FOR_WPS 0 +#endif + +#ifdef CONFIG_DONT_CARE_TP +#define XMIT_STACKSIZE 192 //256 +#define CMD_STACKSIZE 384 //512 +#else +#define XMIT_STACKSIZE 256 +#define CMD_STACKSIZE 512 //1024 +#endif //CONFIG_DONT_CARE_TP + +#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) +#define RECV_STACKSIZE 256 +#else //CONFIG_PLATFORM_8195A +#ifdef CONFIG_INCLUDE_WPA_PSK +#if PSK_SUPPORT_TKIP +#define RECV_STACKSIZE (512 + 256 + 128 + RECV_STACK_FOR_WPS) +#else +#define RECV_STACKSIZE (512 + 256 + RECV_STACK_FOR_WPS ) +#endif +#else +#define RECV_STACKSIZE (512 + 256 + RECV_STACK_FOR_WPS) //Can be reduced +#endif +#endif //CONFIG_PLATFORM_8195A + +#define XMIT_TASKLET_STACKSIZE 256 +#define RECV_TASKLET_STACKSIZE (1024 + RECV_STACK_FOR_WPS) +#define SDIOXMIT_STACKSIZE 256 + + +struct rtw_netdev_priv_indicator { + void *priv; + u32 sizeof_priv; +}; + +#define rtw_netdev_priv(netdev) ( ((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv ) + +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) adapter->pnetdev->name +#define FUNC_NDEV_FMT "%s" +#define FUNC_NDEV_ARG(ndev) __func__ +#define FUNC_ADPT_FMT "%s(%s)" +#define FUNC_ADPT_ARG(adapter) __func__, adapter->pnetdev->name + +#include "wifi_constants.h" +#include "wifi_structures.h" +int rtw_if_wifi_thread(char *name); +#endif //#ifndef __OSDEP_SERVICE_H_ diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/osdep_intf.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/osdep_intf.h new file mode 100644 index 0000000..3096bb8 --- /dev/null +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/osdep_intf.h @@ -0,0 +1,116 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __OSDEP_INTF_H_ +#define __OSDEP_INTF_H_ + +typedef struct net_device * _nic_hdl; +struct iw_request_info { + u16 cmd; /* Wireless Extension command */ + u16 flags; /* More to come ;-) */ +}; +typedef int (*iw_handler)(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); + +struct pkt_buff { + _list list; + u32 len; + unsigned char *data; +}; + +#if defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS) + +#include "freertos/wrapper.h" +#include "freertos/freertos_intfs.h" +#include "freertos/freertos_xmit.h" +#include "freertos/freertos_recv.h" + +#elif defined(PLATFORM_ECOS) + +#include "ecos/ecos_xmit.h" +#include "ecos/ecos_recv.h" +#include "ecos/ecos_mlme.h" +#include "ecos/ecos_intfs.h" + +#ifdef CONFIG_PROC_DEBUG //need move to ecos/ecos_intfs.h +void rtw_proc_init_one(struct net_device *dev); +void rtw_proc_remove_one(struct net_device *dev); +#else +static void rtw_proc_init_one(struct net_device *dev){} +static void rtw_proc_remove_one(struct net_device *dev){} +#endif //CONFIG_PROC_DEBUG + +#elif defined(PLATFORM_LINUX) +int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); + +int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname); +struct net_device *rtw_init_netdev(_adapter *padapter); + +#ifdef CONFIG_PROC_DEBUG +void rtw_proc_init_one(struct net_device *dev); +void rtw_proc_remove_one(struct net_device *dev); +#else +static void rtw_proc_init_one(struct net_device *dev){} +static void rtw_proc_remove_one(struct net_device *dev){} +#endif //CONFIG_PROC_DEBUG +#endif + +#ifdef CONFIG_CONCURRENT_MODE +struct _io_ops; +_adapter *rtw_drv_if2_init(_adapter *primary_padapter, char *name, void (*set_intf_ops)(struct _io_ops *pops)); +void rtw_drv_if2_free(_adapter *pbuddy_padapter); +#endif + +struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv); +struct net_device * rtw_alloc_etherdev(int sizeof_priv); +void rtw_free_netdev(struct net_device * netdev); + +int rtw_netif_queue_stopped(struct net_device *pnetdev); +void rtw_netif_wake_queue(struct net_device *pnetdev); +void rtw_netif_start_queue(struct net_device *pnetdev); +void rtw_netif_stop_queue(struct net_device *pnetdev); + +struct pkt_buff *rtw_alloc_pktbuf(unsigned int size); +void rtw_free_pktbuf(struct pkt_buff *skb); + +#if 0 +int RTW_STATUS_CODE(int error_code); + +//flags used for rtw_update_mem_stat() +enum { + MEM_STAT_VIR_ALLOC_SUCCESS, + MEM_STAT_VIR_ALLOC_FAIL, + MEM_STAT_VIR_FREE, + MEM_STAT_PHY_ALLOC_SUCCESS, + MEM_STAT_PHY_ALLOC_FAIL, + MEM_STAT_PHY_FREE, + MEM_STAT_TX, //used to distinguish TX/RX, asigned from caller + MEM_STAT_TX_ALLOC_SUCCESS, + MEM_STAT_TX_ALLOC_FAIL, + MEM_STAT_TX_FREE, + MEM_STAT_RX, //used to distinguish TX/RX, asigned from caller + MEM_STAT_RX_ALLOC_SUCCESS, + MEM_STAT_RX_ALLOC_FAIL, + MEM_STAT_RX_FREE +}; +#endif + +#endif //_OSDEP_INTF_H_ + diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/skbuff.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/skbuff.h index e1e224c..aab44fe 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/skbuff.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/skbuff.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ #ifndef __SKBUFF_H__ #define __SKBUFF_H__ @@ -27,9 +42,9 @@ struct sk_buff { const char *funcname[TRACE_SKB_DEPTH]; unsigned int list_idx; /* Trace the List we are on */ #endif -#ifdef CONFIG_DONT_CARE_TP +//#ifdef CONFIG_DONT_CARE_TP int dyalloc_flag; -#endif +//#endif }; unsigned char *skb_put(struct sk_buff *skb, unsigned int len); diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wireless.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wireless.h index c3865a6..ac98859 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wireless.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wireless.h @@ -268,43 +268,43 @@ typedef long long __i64; /* Wireless Identification */ #define SIOCSIWCOMMIT 0x8B00 /* Commit pending changes to driver */ -#define SIOCGIWNAME 0x8B01 /* get name == wireless protocol */ +#define SIOCGIWNAME 0x8B01 /* get name == wireless protocol */ /* SIOCGIWNAME is used to verify the presence of Wireless Extensions. * Common values : "IEEE 802.11-DS", "IEEE 802.11-FH", "IEEE 802.11b"... * Don't put the name of your driver there, it's useless. */ /* Basic operations */ -#define SIOCSIWNWID 0x8B02 /* set network id (pre-802.11) */ -#define SIOCGIWNWID 0x8B03 /* get network id (the cell) */ -#define SIOCSIWFREQ 0x8B04 /* set channel/frequency (Hz) */ -#define SIOCGIWFREQ 0x8B05 /* get channel/frequency (Hz) */ -#define SIOCSIWMODE 0x8B06 /* set operation mode */ -#define SIOCGIWMODE 0x8B07 /* get operation mode */ -#define SIOCSIWSENS 0x8B08 /* set sensitivity (dBm) */ -#define SIOCGIWSENS 0x8B09 /* get sensitivity (dBm) */ +#define SIOCSIWNWID 0x8B02 /* set network id (pre-802.11) */ +#define SIOCGIWNWID 0x8B03 /* get network id (the cell) */ +#define SIOCSIWFREQ 0x8B04 /* set channel/frequency (Hz) */ +#define SIOCGIWFREQ 0x8B05 /* get channel/frequency (Hz) */ +#define SIOCSIWMODE 0x8B06 /* set operation mode */ +#define SIOCGIWMODE 0x8B07 /* get operation mode */ +#define SIOCSIWSENS 0x8B08 /* set sensitivity (dBm) */ +#define SIOCGIWSENS 0x8B09 /* get sensitivity (dBm) */ /* Informative stuff */ #define SIOCSIWRANGE 0x8B0A /* Unused */ #define SIOCGIWRANGE 0x8B0B /* Get range of parameters */ -#define SIOCSIWPRIV 0x8B0C /* Unused */ -#define SIOCGIWPRIV 0x8B0D /* get private ioctl interface info */ +#define SIOCSIWPRIV 0x8B0C /* Unused */ +#define SIOCGIWPRIV 0x8B0D /* get private ioctl interface info */ #define SIOCSIWSTATS 0x8B0E /* Unused */ #define SIOCGIWSTATS 0x8B0F /* Get /proc/net/wireless stats */ /* SIOCGIWSTATS is strictly used between user space and the kernel, and * is never passed to the driver (i.e. the driver will never see it). */ /* Spy support (statistics per MAC address - used for Mobile IP support) */ -#define SIOCSIWSPY 0x8B10 /* set spy addresses */ -#define SIOCGIWSPY 0x8B11 /* get spy info (quality of link) */ +#define SIOCSIWSPY 0x8B10 /* set spy addresses */ +#define SIOCGIWSPY 0x8B11 /* get spy info (quality of link) */ #define SIOCSIWTHRSPY 0x8B12 /* set spy threshold (spy event) */ #define SIOCGIWTHRSPY 0x8B13 /* get spy threshold */ /* Access Point manipulation */ -#define SIOCSIWAP 0x8B14 /* set access point MAC addresses */ -#define SIOCGIWAP 0x8B15 /* get access point MAC addresses */ +#define SIOCSIWAP 0x8B14 /* set access point MAC addresses */ +#define SIOCGIWAP 0x8B15 /* get access point MAC addresses */ #define SIOCGIWAPLIST 0x8B17 /* Deprecated in favor of scanning */ -#define SIOCSIWSCAN 0x8B18 /* trigger scanning (list cells) */ -#define SIOCGIWSCAN 0x8B19 /* get scanning results */ +#define SIOCSIWSCAN 0x8B18 /* trigger scanning (list cells) */ +#define SIOCGIWSCAN 0x8B19 /* get scanning results */ /* 802.11 specific support */ #define SIOCSIWESSID 0x8B1A /* set ESSID (network name) */ @@ -316,12 +316,12 @@ typedef long long __i64; * point to a string in user space, like it is done for RANGE... */ /* Other parameters useful in 802.11 and some other devices */ -#define SIOCSIWRATE 0x8B20 /* set default bit rate (bps) */ -#define SIOCGIWRATE 0x8B21 /* get default bit rate (bps) */ -#define SIOCSIWRTS 0x8B22 /* set RTS/CTS threshold (bytes) */ -#define SIOCGIWRTS 0x8B23 /* get RTS/CTS threshold (bytes) */ -#define SIOCSIWFRAG 0x8B24 /* set fragmentation thr (bytes) */ -#define SIOCGIWFRAG 0x8B25 /* get fragmentation thr (bytes) */ +#define SIOCSIWRATE 0x8B20 /* set default bit rate (bps) */ +#define SIOCGIWRATE 0x8B21 /* get default bit rate (bps) */ +#define SIOCSIWRTS 0x8B22 /* set RTS/CTS threshold (bytes) */ +#define SIOCGIWRTS 0x8B23 /* get RTS/CTS threshold (bytes) */ +#define SIOCSIWFRAG 0x8B24 /* set fragmentation thr (bytes) */ +#define SIOCGIWFRAG 0x8B25 /* get fragmentation thr (bytes) */ #define SIOCSIWTXPOW 0x8B26 /* set transmit power (dBm) */ #define SIOCGIWTXPOW 0x8B27 /* get transmit power (dBm) */ #define SIOCSIWRETRY 0x8B28 /* set retry limits and lifetime */ @@ -348,11 +348,11 @@ typedef long long __i64; #define SIOCGIWGENIE 0x8B31 /* get generic IE */ /* WPA : IEEE 802.11 MLME requests */ -#define SIOCSIWMLME 0x8B16 /* request MLME operation; uses +#define SIOCSIWMLME 0x8B16 /* request MLME operation; uses * struct iw_mlme */ /* WPA : Authentication mode parameters */ -#define SIOCSIWAUTH 0x8B32 /* set authentication mode params */ -#define SIOCGIWAUTH 0x8B33 /* get authentication mode params */ +#define SIOCSIWAUTH 0x8B32 /* set authentication mode params */ +#define SIOCGIWAUTH 0x8B33 /* get authentication mode params */ /* WPA : Extended version of encoding configuration */ #define SIOCSIWENCODEEXT 0x8B34 /* set encoding token & mode */ @@ -375,8 +375,8 @@ typedef long long __i64; * If you don't follow those rules, DaveM is going to hate you (reason : * it make mixed 32/64bit operation impossible). */ -#define SIOCIWFIRSTPRIV 0x8BE0 -#define SIOCIWLASTPRIV 0x8BFF +#define SIOCIWFIRSTPRIV 0x8BE0 +#define SIOCIWLASTPRIV 0x8BFF #define SIOCSIWPRIVADAPTIVITY 0x8BFB #define SIOCGIWPRIVPASSPHRASE 0x8BFC @@ -412,7 +412,7 @@ typedef long long __i64; #define IWEVTXDROP 0x8C00 /* Packet dropped to excessive retry */ #define IWEVQUAL 0x8C01 /* Quality part of statistics (scan) */ #define IWEVCUSTOM 0x8C02 /* Driver specific ascii string */ -#define IWEVREGISTERED 0x8C03 /* Discovered a new node (AP mode) */ +#define IWEVREGISTERED 0x8C03 /* Discovered a new node (AP mode) */ #define IWEVEXPIRED 0x8C04 /* Expired a node (AP mode) */ #define IWEVGENIE 0x8C05 /* Generic IE (WPA, RSN, WMM, ..) * (scan results); This includes id and @@ -443,7 +443,7 @@ typedef long long __i64; * pre-authentication * (struct iw_pmkid_cand) */ -#define IWEVFIRST 0x8C00 +#define IWEVFIRST 0x8C00 #define IW_EVENT_IDX(cmd) ((cmd) - IWEVFIRST) /* Indicate Mgnt Frame and Action Frame to uplayer*/ @@ -490,11 +490,11 @@ typedef long long __i64; * a few of them in the struct iw_range. */ /* Maximum of address that you may set with SPY */ -#define IW_MAX_SPY 8 +#define IW_MAX_SPY 8 /* Maximum of address that you may get in the list of access points in range */ -#define IW_MAX_AP 64 +#define IW_MAX_AP 64 /* Maximum size of the ESSID and NICKN strings */ #define IW_ESSID_MAX_SIZE 32 @@ -503,7 +503,7 @@ typedef long long __i64; #define IW_MODE_AUTO 0 /* Let the driver decides */ #define IW_MODE_ADHOC 1 /* Single cell network */ #define IW_MODE_INFRA 2 /* Multi cell network, roaming, ... */ -#define IW_MODE_MASTER 3 /* Synchronization master or Access Point */ +#define IW_MODE_MASTER 3 /* Synchronisation master or Access Point */ #define IW_MODE_REPEAT 4 /* Wireless Repeater (forwarder) */ #define IW_MODE_SECOND 5 /* Secondary master/repeater (backup) */ #define IW_MODE_MONITOR 6 /* Passive monitor (listen only) */ @@ -512,13 +512,13 @@ typedef long long __i64; #define IW_QUAL_QUAL_UPDATED 0x01 /* Value was updated since last read */ #define IW_QUAL_LEVEL_UPDATED 0x02 #define IW_QUAL_NOISE_UPDATED 0x04 -#define IW_QUAL_ALL_UPDATED 0x07 -#define IW_QUAL_DBM 0x08 /* Level + Noise are dBm */ +#define IW_QUAL_ALL_UPDATED 0x07 +#define IW_QUAL_DBM 0x08 /* Level + Noise are dBm */ #define IW_QUAL_QUAL_INVALID 0x10 /* Driver doesn't provide value */ #define IW_QUAL_LEVEL_INVALID 0x20 #define IW_QUAL_NOISE_INVALID 0x40 -#define IW_QUAL_RCPI 0x80 /* Level + Noise are 802.11k RCPI */ -#define IW_QUAL_ALL_INVALID 0x70 +#define IW_QUAL_RCPI 0x80 /* Level + Noise are 802.11k RCPI */ +#define IW_QUAL_ALL_INVALID 0x70 /* Frequency flags */ #define IW_FREQ_AUTO 0x00 /* Let the driver decides */ @@ -532,32 +532,32 @@ typedef long long __i64; #define IW_ENCODING_TOKEN_MAX 64 /* 512 bits (for now) */ /* Flags for encoding (along with the token) */ -#define IW_ENCODE_INDEX 0x00FF /* Token index (if needed) */ -#define IW_ENCODE_FLAGS 0xFF00 /* Flags defined below */ -#define IW_ENCODE_MODE 0xF000 /* Modes defined below */ -#define IW_ENCODE_DISABLED 0x8000 /* Encoding disabled */ -#define IW_ENCODE_ENABLED 0x0000 /* Encoding enabled */ +#define IW_ENCODE_INDEX 0x00FF /* Token index (if needed) */ +#define IW_ENCODE_FLAGS 0xFF00 /* Flags defined below */ +#define IW_ENCODE_MODE 0xF000 /* Modes defined below */ +#define IW_ENCODE_DISABLED 0x8000 /* Encoding disabled */ +#define IW_ENCODE_ENABLED 0x0000 /* Encoding enabled */ #define IW_ENCODE_RESTRICTED 0x4000 /* Refuse non-encoded packets */ -#define IW_ENCODE_OPEN 0x2000 /* Accept non-encoded packets */ -#define IW_ENCODE_NOKEY 0x0800 /* Key is write only, so not present */ -#define IW_ENCODE_TEMP 0x0400 /* Temporary key */ +#define IW_ENCODE_OPEN 0x2000 /* Accept non-encoded packets */ +#define IW_ENCODE_NOKEY 0x0800 /* Key is write only, so not present */ +#define IW_ENCODE_TEMP 0x0400 /* Temporary key */ /* Power management flags available (along with the value, if any) */ -#define IW_POWER_ON 0x0000 /* No details... */ -#define IW_POWER_TYPE 0xF000 /* Type of parameter */ -#define IW_POWER_PERIOD 0x1000 /* Value is a period/duration of */ -#define IW_POWER_TIMEOUT 0x2000 /* Value is a timeout (to go asleep) */ -#define IW_POWER_SAVING 0x4000 /* Value is relative (how aggressive)*/ -#define IW_POWER_MODE 0x0F00 /* Power Management mode */ -#define IW_POWER_UNICAST_R 0x0100 /* Receive only unicast messages */ +#define IW_POWER_ON 0x0000 /* No details... */ +#define IW_POWER_TYPE 0xF000 /* Type of parameter */ +#define IW_POWER_PERIOD 0x1000 /* Value is a period/duration of */ +#define IW_POWER_TIMEOUT 0x2000 /* Value is a timeout (to go asleep) */ +#define IW_POWER_SAVING 0x4000 /* Value is relative (how aggressive)*/ +#define IW_POWER_MODE 0x0F00 /* Power Management mode */ +#define IW_POWER_UNICAST_R 0x0100 /* Receive only unicast messages */ #define IW_POWER_MULTICAST_R 0x0200 /* Receive only multicast messages */ -#define IW_POWER_ALL_R 0x0300 /* Receive all messages though PM */ -#define IW_POWER_FORCE_S 0x0400 /* Force PM procedure for sending unicast */ -#define IW_POWER_REPEATER 0x0800 /* Repeat broadcast messages in PM period */ -#define IW_POWER_MODIFIER 0x000F /* Modify a parameter */ -#define IW_POWER_MIN 0x0001 /* Value is a minimum */ -#define IW_POWER_MAX 0x0002 /* Value is a maximum */ -#define IW_POWER_RELATIVE 0x0004 /* Value is not in seconds/ms/us */ +#define IW_POWER_ALL_R 0x0300 /* Receive all messages though PM */ +#define IW_POWER_FORCE_S 0x0400 /* Force PM procedure for sending unicast */ +#define IW_POWER_REPEATER 0x0800 /* Repeat broadcast messages in PM period */ +#define IW_POWER_MODIFIER 0x000F /* Modify a parameter */ +#define IW_POWER_MIN 0x0001 /* Value is a minimum */ +#define IW_POWER_MAX 0x0002 /* Value is a maximum */ +#define IW_POWER_RELATIVE 0x0004 /* Value is not in seconds/ms/us */ /* Transmit Power flags available */ #define IW_TXPOW_TYPE 0x00FF /* Type of value */ @@ -567,7 +567,7 @@ typedef long long __i64; #define IW_TXPOW_RANGE 0x1000 /* Range of value between min/max */ /* Retry limits and lifetime flags available */ -#define IW_RETRY_ON 0x0000 /* No details... */ +#define IW_RETRY_ON 0x0000 /* No details... */ #define IW_RETRY_TYPE 0xF000 /* Type of parameter */ #define IW_RETRY_LIMIT 0x1000 /* Maximum number of retries*/ #define IW_RETRY_LIFETIME 0x2000 /* Maximum duration of retries in us */ @@ -589,8 +589,8 @@ typedef long long __i64; #define IW_SCAN_ALL_RATE 0x0040 /* Scan all Bit-Rates */ #define IW_SCAN_THIS_RATE 0x0080 /* Scan only this Bit-Rate */ /* struct iw_scan_req scan_type */ -#define IW_SCAN_TYPE_ACTIVE 0 -#define IW_SCAN_TYPE_PASSIVE 1 +#define IW_SCAN_TYPE_ACTIVE 0 +#define IW_SCAN_TYPE_PASSIVE 1 /* Maximum size of returned data */ #define IW_SCAN_MAX_DATA 4096 /* In bytes */ @@ -627,14 +627,14 @@ typedef long long __i64; /* IW_AUTH_WPA_VERSION values (bit field) */ #define IW_AUTH_WPA_VERSION_DISABLED 0x00000001 -#define IW_AUTH_WPA_VERSION_WPA 0x00000002 -#define IW_AUTH_WPA_VERSION_WPA2 0x00000004 +#define IW_AUTH_WPA_VERSION_WPA 0x00000002 +#define IW_AUTH_WPA_VERSION_WPA2 0x00000004 /* IW_AUTH_PAIRWISE_CIPHER and IW_AUTH_GROUP_CIPHER values (bit field) */ -#define IW_AUTH_CIPHER_NONE 0x00000001 +#define IW_AUTH_CIPHER_NONE 0x00000001 #define IW_AUTH_CIPHER_WEP40 0x00000002 -#define IW_AUTH_CIPHER_TKIP 0x00000004 -#define IW_AUTH_CIPHER_CCMP 0x00000008 +#define IW_AUTH_CIPHER_TKIP 0x00000004 +#define IW_AUTH_CIPHER_CCMP 0x00000008 #define IW_AUTH_CIPHER_WEP104 0x00000010 /* IW_AUTH_KEY_MGMT values (bit field) */ @@ -644,7 +644,7 @@ typedef long long __i64; /* IW_AUTH_80211_AUTH_ALG values (bit field) */ #define IW_AUTH_ALG_OPEN_SYSTEM 0x00000001 #define IW_AUTH_ALG_SHARED_KEY 0x00000002 -#define IW_AUTH_ALG_LEAP 0x00000004 +#define IW_AUTH_ALG_LEAP 0x00000004 /* IW_AUTH_ROAMING_CONTROL values */ #define IW_AUTH_ROAMING_ENABLE 0 /* driver/firmware based roaming */ @@ -666,15 +666,15 @@ typedef long long __i64; /* IWEVMICHAELMICFAILURE : struct iw_michaelmicfailure ->flags */ #define IW_MICFAILURE_KEY_ID 0x00000003 /* Key ID 0..3 */ -#define IW_MICFAILURE_GROUP 0x00000004 +#define IW_MICFAILURE_GROUP 0x00000004 #define IW_MICFAILURE_PAIRWISE 0x00000008 #define IW_MICFAILURE_STAKEY 0x00000010 -#define IW_MICFAILURE_COUNT 0x00000060 /* 1 or 2 (0 = count not supported) +#define IW_MICFAILURE_COUNT 0x00000060 /* 1 or 2 (0 = count not supported) */ /* Bit field values for enc_capa in struct iw_range */ -#define IW_ENC_CAPA_WPA 0x00000001 -#define IW_ENC_CAPA_WPA2 0x00000002 +#define IW_ENC_CAPA_WPA 0x00000001 +#define IW_ENC_CAPA_WPA2 0x00000002 #define IW_ENC_CAPA_CIPHER_TKIP 0x00000004 #define IW_ENC_CAPA_CIPHER_CCMP 0x00000008 @@ -698,8 +698,8 @@ typedef long long __i64; /* Modulations bitmasks */ #define IW_MODUL_ALL 0x00000000 /* Everything supported */ -#define IW_MODUL_FH 0x00000001 /* Frequency Hopping */ -#define IW_MODUL_DS 0x00000002 /* Original Direct Sequence */ +#define IW_MODUL_FH 0x00000001 /* Frequency Hopping */ +#define IW_MODUL_DS 0x00000002 /* Original Direct Sequence */ #define IW_MODUL_CCK 0x00000004 /* 802.11b : 5.5 + 11 Mb/s */ #define IW_MODUL_11B (IW_MODUL_DS | IW_MODUL_CCK) #define IW_MODUL_PBCC 0x00000008 /* TI : 5.5 + 11 + 22 Mb/s */ @@ -714,8 +714,8 @@ typedef long long __i64; #define IW_MODUL_CUSTOM 0x40000000 /* Driver specific */ /* Bitrate flags available */ -#define IW_BITRATE_TYPE 0x00FF /* Type of value */ -#define IW_BITRATE_UNICAST 0x0001 /* Maximum/Fixed unicast bitrate */ +#define IW_BITRATE_TYPE 0x00FF /* Type of value */ +#define IW_BITRATE_UNICAST 0x0001 /* Maximum/Fixed unicast bitrate */ #define IW_BITRATE_BROADCAST 0x0002 /* Fixed broadcast bitrate */ /****************************** TYPES ******************************/ @@ -808,7 +808,7 @@ struct iw_missed */ struct iw_thrspy { - struct sockaddr_t addr; /* Source address (hw/mac) */ + struct sockaddr_t addr; /* Source address (hw/mac) */ struct iw_quality qual; /* Quality of the link */ struct iw_quality low; /* Low threshold */ struct iw_quality high; /* High threshold */ diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wlan_intf.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wlan_intf.h index 02d6def..b586e0c 100644 --- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wlan_intf.h +++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/wlan_intf.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * Copyright (c) 2013-2016 Realtek Semiconductor Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ #ifndef __WLAN_INTF_H__ #define __WLAN_INTF_H__ @@ -37,15 +52,13 @@ struct sk_buff { */ /************************************************************/ -// #include "wrapper.h" -//extern Rltk_wlan_t rltk_wlan_info[2]; - //----- ------------------------------------------------------------------ // Wlan Interface opened for upper layer //----- ------------------------------------------------------------------ int rltk_wlan_init(int idx_wlan, rtw_mode_t mode); //return 0: success. -1:fail void rltk_wlan_deinit(void); -void rltk_wlan_start(int idx_wlan); +void rltk_wlan_deinit_fastly(void); +int rltk_wlan_start(int idx_wlan); void rltk_wlan_statistic(unsigned char idx); unsigned char rltk_wlan_running(unsigned char idx); // interface is up. 0: interface is down int rltk_wlan_control(unsigned long cmd, void *data); @@ -58,6 +71,7 @@ int rltk_wlan_set_wps_phase(unsigned char is_trigger_wps); int rtw_ps_enable(int enable); int rltk_wlan_is_connected_to_ap(void); + #ifdef __cplusplus } #endif diff --git a/RTL00_SDKV35a/component/os/rtx/rtx_service.c b/RTL00_SDKV35a/component/os/rtx/rtx_service.c new file mode 100644 index 0000000..4946662 --- /dev/null +++ b/RTL00_SDKV35a/component/os/rtx/rtx_service.c @@ -0,0 +1,1109 @@ +/* RTX includes */ +#include "osdep_service.h" +#include "tcm_heap.h" +#include +//#include //malloc(), free() +//#include //memcpy(), memcmp(), memset() +#include "platform_stdlib.h" +//#include +//#include +/********************* os depended utilities ********************/ + +#ifndef USE_MUTEX_FOR_SPINLOCK +#define USE_MUTEX_FOR_SPINLOCK 1 +#endif + +#define USE_HEAP_INFO 0 + +#define OS_TICK 1000 +#define OS_TICK_RATE_MS (1000/OS_TICK) + +//----------------------------------------------------------------------- +// Private Variables +//----------------------------------------------------------------------- +static unsigned long CriticalNesting = 0; + +//----------------------------------------------------------------------- +// Misc Function +//----------------------------------------------------------------------- +int osdep_print = 0; +#define _func_enter_ do{\ + if(osdep_print)\ + printf("enter %s\r\n", __FUNCTION__);\ + }while(0) +#define _func_exit_ do{\ + if(osdep_print)\ + printf("exit %s\r\n", __FUNCTION__);\ + }while(0) + +void save_and_cli() +{ +_func_enter_; + __disable_irq(); +_func_exit_; +} + +void restore_flags() +{ +_func_enter_; + __enable_irq(); +_func_exit_; +} + +void cli() +{ +_func_enter_; + __disable_irq(); +_func_exit_; +} + +/* Not needed on 64bit architectures */ +static unsigned int __div64_32(u64 *n, unsigned int base) +{ + u64 rem = *n; + u64 b = base; + u64 res, d = 1; + unsigned int high = rem >> 32; +_func_enter_; + /* Reduce the thing a bit first */ + res = 0; + if (high >= base) { + high /= base; + res = (u64) high << 32; + rem -= (u64) (high * base) << 32; + } + + while ((u64)b > 0 && b < rem) { + b = b+b; + d = d+d; + } + + do { + if (rem >= b) { + rem -= b; + res += d; + } + b >>= 1; + d >>= 1; + } while (d); +_func_exit_; + *n = res; + return rem; +} + +/********************* os depended service ********************/ +#if USE_HEAP_INFO +static uint32_t osFreeBytesRemaining=0x400; +#endif +static void _rtx_memset(void *pbuf, int c, u32 sz); +u8* _rtx_malloc(u32 sz) +{ +_func_enter_; + void *p = NULL; + p = malloc(sz); + if(p != NULL){ +#if USE_HEAP_INFO + osFreeBytesRemaining-=sz; +#endif + } +_func_exit_; + return p; +} + +u8* _rtx_zmalloc(u32 sz) +{ +_func_enter_; + u8 *pbuf = _rtx_malloc(sz); + + if (pbuf != NULL){ +#if USE_HEAP_INFO + osFreeBytesRemaining-=sz; +#endif + _rtx_memset(pbuf, 0, sz); + } +_func_exit_; + return pbuf; +} + +static void (*ext_free)( void *p ) = NULL; +static uint32_t ext_upper = 0; +static uint32_t ext_lower = 0; +void rtw_set_mfree_ext( void (*free)( void *p ), uint32_t upper, uint32_t lower ) +{ + ext_free = free; + ext_upper = upper; + ext_lower = lower; +} + +void _rtx_mfree(u8 *pbuf, u32 sz) +{ +_func_enter_; + if( ((uint32_t)pbuf >= ext_lower) && ((uint32_t)pbuf < ext_upper) ){ + if(ext_free) + ext_free(pbuf); + }else{ + free(pbuf); + } +#if USE_HEAP_INFO + osFreeBytesRemaining+=sz; +#endif +} + +static void _rtx_memcpy(void* dst, void* src, u32 sz) +{ +_func_enter_; + memcpy(dst, src, sz); +_func_exit_; +} + +static int _rtx_memcmp(void *dst, void *src, u32 sz) +{ +_func_enter_; +//under Linux/GNU/GLibc, the return value of memcmp for two same mem. chunk is 0 + if (!(memcmp(dst, src, sz))) + return _SUCCESS; +_func_exit_; + return _FAIL; +} + +static void _rtx_memset(void *pbuf, int c, u32 sz) +{ +_func_enter_; + memset(pbuf, c, sz); +_func_exit_; +} + +static void _rtx_init_sema(_sema *sem, int init_val) +{ +_func_enter_; + rtx_sema_t *p_sem = (rtx_sema_t *)_rtx_zmalloc(sizeof(rtx_sema_t)); + if(p_sem == NULL){ + goto err_exit; + } +#ifdef CMSIS_OS_RTX + p_sem->def.semaphore = p_sem->data; +#endif + *sem = (_sema)p_sem; + p_sem->id = osSemaphoreCreate(&p_sem->def, init_val); + if (p_sem->id == NULL){ + goto err_exit; + } +_func_exit_; + return; +err_exit: + DBG_ERR("error"); + if(p_sem) + _rtx_mfree((u8 *)p_sem, sizeof(rtx_sema_t)); + *sem = NULL; + return; +} + +static void _rtx_free_sema(_sema *sema) +{ +_func_enter_; + if(*sema){ + rtx_sema_t *p_sem = (rtx_sema_t *)(*sema); + osSemaphoreDelete(p_sem->id); + if(p_sem) + _rtx_mfree((u8 *)p_sem, sizeof(rtx_sema_t)); + *sema = NULL; + }else + DBG_ERR("NULL pointer get"); +_func_exit_; +} + +static void _rtx_up_sema(_sema *sema) +{ + if(*sema){ + rtx_sema_t *p_sem = (rtx_sema_t *)(*sema); + osStatus status = osSemaphoreRelease(p_sem->id); + if ( status != osOK){ + DBG_ERR("error %d", status); + } + }else + DBG_ERR("NULL pointer get"); +_func_exit_; +} + +static void _rtx_up_sema_from_isr(_sema *sema) +{ +_func_enter_; + if(*sema){ + rtx_sema_t *p_sem = (rtx_sema_t *)*sema; + osStatus status = osSemaphoreRelease(p_sem->id); + if (status != osOK){ + DBG_ERR("error %d", status); + } + }else + DBG_ERR("NULL pointer get"); +_func_exit_; +} + +static u32 _rtx_down_sema(_sema *sema, u32 timeout_ms) +{ + if(*sema){ + rtx_sema_t *p_sem = (rtx_sema_t *)*sema; + if(timeout_ms == RTW_MAX_DELAY) { + timeout_ms = osWaitForever; + } else { + timeout_ms = rtw_ms_to_systime(timeout_ms); + } + + if (osSemaphoreWait(p_sem->id, (timeout_ms != 0)?(timeout_ms):(osWaitForever)) >= 0) + return _TRUE; + } + return _FALSE; +} + +static void _rtx_mutex_init(_mutex *mutex) +{ +_func_enter_; + rtx_mutex_t *p_mut = (rtx_mutex_t *)_rtx_zmalloc(sizeof(rtx_mutex_t)); + if(p_mut == NULL) + goto err_exit; +#ifdef CMSIS_OS_RTX + p_mut->def.mutex = (void *)p_mut->data; +#endif + *mutex = (_mutex)p_mut; + p_mut->id = osMutexCreate(&p_mut->def); + if (p_mut->id == NULL) + goto err_exit; +_func_exit_; + return; +err_exit: + DBG_ERR("error"); + if(p_mut) + _rtx_mfree((u8 *)p_mut, sizeof(rtx_mutex_t)); + *mutex = NULL; + return; +} + +static void _rtx_mutex_free(_mutex *pmutex) +{ +_func_enter_; + if(*pmutex){ + rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex); + osMutexDelete(p_mut->id); + if(p_mut) + _rtx_mfree((u8 *)p_mut, sizeof(rtx_mutex_t)); + } +_func_exit_; +} + +static void _rtx_mutex_get(_mutex *pmutex) +{ +_func_enter_; + if(*pmutex){ + rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex); + if (osMutexWait(p_mut->id, 60 * 1000 / OS_TICK_RATE_MS) != osOK) + DBG_ERR("%s(%p) failed, retry\n", __FUNCTION__, p_mut); + } +_func_exit_; +} + +static int _rtx_mutex_get_timeout(_mutex *pmutex, u32 timeout_ms) +{ +_func_enter_; + if(*pmutex){ + rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex); + if(timeout_ms == RTW_MAX_DELAY) { + timeout_ms = osWaitForever; + } else { + timeout_ms = rtw_ms_to_systime(timeout_ms); + } + if(osMutexWait(p_mut->id, timeout_ms / OS_TICK_RATE_MS) == osOK){ + return _SUCCESS; + } + } +_func_exit_; + DBG_ERR("%s(%p) failed, retry\n", __FUNCTION__, pmutex); + return _FAIL; +} + +static void _rtx_mutex_put(_mutex *pmutex) +{ +_func_enter_; + if(*pmutex){ + rtx_mutex_t *p_mut = (rtx_mutex_t *)(*pmutex); + if (osMutexRelease(p_mut->id) != osOK) + DBG_ERR("\r\ninternal counter of mutex is 0 or calling task is not the owner of the mutex"); + } +_func_exit_; +} + +static void _rtx_enter_critical(_lock *plock, _irqL *pirqL) +{ +_func_enter_; + CriticalNesting++; + if(CriticalNesting == 1){ + rt_tsk_lock();//tsk_lock & tsk_unlock should not be called nested + } +_func_exit_; +} + +void mbed_die(void){ + DBG_ERR(" %p die here", osThreadGetId()); + __disable_irq(); + while(1); +} + +static void _rtx_exit_critical(_lock *plock, _irqL *pirqL) +{ +_func_enter_; + if(CriticalNesting == 0){ + DBG_ERR("die here"); + HALT(); + } + CriticalNesting--; + if(CriticalNesting == 0){ + rt_tsk_unlock(); + } +_func_exit_; +} + +static void _rtx_enter_critical_from_isr(_lock *plock, _irqL *pirqL) +{ +_func_enter_; + __disable_irq(); +_func_exit_; +} + +static void _rtx_exit_critical_from_isr(_lock *plock, _irqL *pirqL) +{ +_func_enter_; + __enable_irq(); +_func_exit_; +} + +static int _rtx_enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ +_func_enter_; + while(_rtx_mutex_get_timeout(pmutex, 60 * 1000 / OS_TICK_RATE_MS) != _SUCCESS) + DBG_ERR("\n\r[%p] %s(%p) failed, retry\n", osThreadGetId(), __FUNCTION__, pmutex); +_func_exit_; + return _SUCCESS; +} + +static void _rtx_exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ +_func_enter_; + _rtx_mutex_put(pmutex); +_func_exit_; +} + +static void _rtx_spinlock_init(_lock *plock) +{ +_func_enter_; +#if USE_MUTEX_FOR_SPINLOCK + _rtx_mutex_init(plock); +#endif +_func_exit_; +} + +static void _rtx_spinlock_free(_lock *plock) +{ +_func_enter_; +#if USE_MUTEX_FOR_SPINLOCK + if(plock != NULL){ + _rtx_mutex_free(plock); + } +#endif +_func_exit_; +} + +static void _rtx_spinlock(_lock *plock) +{ +_func_enter_; +#if USE_MUTEX_FOR_SPINLOCK + _rtx_mutex_get(plock); +#endif +_func_exit_; +} + +static void _rtx_spinunlock(_lock *plock) +{ +_func_enter_; +#if USE_MUTEX_FOR_SPINLOCK + _rtx_mutex_put(plock); +#endif +_func_exit_; +} + +static void _rtx_spinlock_irqsave(_lock *plock, _irqL *irqL) +{ +_func_enter_; + _rtx_enter_critical(plock, irqL); +#if USE_MUTEX_FOR_SPINLOCK + _rtx_spinlock(plock); +#endif +_func_exit_; +} + +static void _rtx_spinunlock_irqsave(_lock *plock, _irqL *irqL) +{ +_func_enter_; +#if USE_MUTEX_FOR_SPINLOCK + _rtx_spinunlock(plock); +#endif + _rtx_exit_critical(plock, irqL); +_func_exit_; +} + +static int _rtx_init_xqueue( _xqueue* queue, const char* name, u32 message_size, u32 number_of_messages ) +{ +_func_enter_; + rtx_mbox_t *mbox = (rtx_mbox_t *)_rtx_zmalloc(sizeof(rtx_mbox_t)); + if (mbox == NULL ){ + goto err_exit; + } +#ifdef CMSIS_OS_RTX + mbox->os_mailQ_q = (uint32_t)_rtx_zmalloc((4+number_of_messages)*sizeof(uint32_t)); + mbox->os_mailQ_m = (uint32_t)_rtx_zmalloc((3 + (message_size+3)/4)*number_of_messages); + if((mbox->os_mailQ_q == 0) || (mbox->os_mailQ_m == 0)) + goto err_exit; + mbox->os_mailQ_p[0] = (void *)mbox->os_mailQ_q; + mbox->os_mailQ_p[1] = (void *)mbox->os_mailQ_m; + mbox->def.pool = mbox->os_mailQ_p; + mbox->def.queue_sz = number_of_messages; + mbox->def.item_sz = message_size; +#endif + *queue = (_xqueue)mbox; + mbox->id = osMailCreate(&mbox->def, NULL); + if(mbox->id == NULL) + goto err_exit; +_func_exit_; + return _SUCCESS; +err_exit: + DBG_ERR("%s error\r\n", __FUNCTION__); + if(mbox){ + if(mbox->os_mailQ_q) + _rtx_mfree((u8 *)mbox->os_mailQ_q, ((4+number_of_messages)*sizeof(uint32_t))); + if(mbox->os_mailQ_m) + _rtx_mfree((u8 *)mbox->os_mailQ_m, ((3 + (message_size+3)/4)*number_of_messages)); + _rtx_mfree((u8 *)mbox, sizeof(rtx_mbox_t)); + *queue = NULL; + } + return _FAIL; +} + +static int _rtx_push_to_xqueue( _xqueue* queue, void* message, u32 timeout_ms ) +{ +_func_enter_; + void *mptr; + rtx_mbox_t *mbox; + if(timeout_ms == RTW_MAX_DELAY) { + timeout_ms = osWaitForever; + } else { + timeout_ms = rtw_ms_to_systime(timeout_ms); + } + + if (*queue != NULL){ + mbox = (rtx_mbox_t *)(*queue); + mptr = osMailAlloc(mbox->id, timeout_ms); // Allocate memory + _rtx_memcpy(mptr, message, mbox->def.item_sz); + if(osMailPut(mbox->id, mptr) != osOK ){ + DBG_ERR("%s error\n", __FUNCTION__); + return _FAIL; + } + } +_func_exit_; + return _SUCCESS; +} + +static int _rtx_pop_from_xqueue( _xqueue* queue, void* message, u32 timeout_ms ) +{ +_func_enter_; + if(timeout_ms == RTW_WAIT_FOREVER) { + timeout_ms = osWaitForever; + } else { + timeout_ms = rtw_ms_to_systime(timeout_ms); + } + if (*queue != NULL){ + rtx_mbox_t *mbox = (rtx_mbox_t *)(*queue); + osEvent evt; + evt = osMailGet(mbox->id, timeout_ms ); + if (evt.status == osEventMail) { + _rtx_memcpy(message, evt.value.p, mbox->def.item_sz); + osMailFree(mbox->id, evt.value.p); +_func_exit_; + return _SUCCESS; + } + } + DBG_ERR("[%p] %s error", osThreadGetId(), __FUNCTION__); + return _FAIL; +} + +static int _rtx_deinit_xqueue( _xqueue* queue ) +{ +_func_enter_; + if(*queue != NULL){ + rtx_mbox_t *mbox = (rtx_mbox_t *)(*queue); + + if(mbox->os_mailQ_q) + _rtx_mfree((u8 *)mbox->os_mailQ_q, ((4+mbox->def.queue_sz)*sizeof(uint32_t))); + if(mbox->os_mailQ_m) + _rtx_mfree((u8 *)mbox->os_mailQ_m, ((3 + (mbox->def.item_sz+3)/4)*mbox->def.queue_sz)); + _rtx_mfree((u8 *)mbox, sizeof(rtx_mbox_t)); + *queue = NULL; + } +_func_exit_; + return 0; +} + +static u32 _rtx_get_current_time(void) +{ +_func_enter_; + return rt_time_get(); +_func_exit_; +} + +static u32 _rtx_systime_to_ms(u32 systime) +{ + return systime * OS_TICK_RATE_MS; +} + +static u32 _rtx_systime_to_sec(u32 systime) +{ + return systime / OS_TICK; +} + +static u32 _rtx_ms_to_systime(u32 ms) +{ + return ms / OS_TICK_RATE_MS; +} + +static u32 _rtx_sec_to_systime(u32 sec) +{ + return sec * OS_TICK; +} + +static void _rtx_msleep_os(int ms) +{ +_func_enter_; + osDelay(ms); +_func_exit_; +} + +static void _rtx_usleep_os(int us) +{ +_func_enter_; +#if defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F10X_XL) + // FreeRTOS does not provide us level delay. Use busy wait + WLAN_BSP_UsLoop(us); +#elif defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) + //DBG_ERR("%s: Please Implement micro-second delay\n", __FUNCTION__); + HalDelayUs(us); +#else +// #error "Please implement hardware dependent micro second level sleep here" +#endif +_func_exit_; +} + +static void _rtx_mdelay_os(int ms) +{ +_func_enter_; + osDelay(ms); +_func_exit_; +} + +static void _rtx_udelay_os(int us) +{ +_func_enter_; +#if defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F10X_XL) + // FreeRTOS does not provide us level delay. Use busy wait + WLAN_BSP_UsLoop(us); +#elif defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) + //RtlUdelayOS(us); + HalDelayUs(us); +#else +// #error "Please implement hardware dependent micro second level sleep here" +#endif +_func_exit_; +} + +static void _rtx_yield_os(void) +{ +_func_enter_; + osThreadYield(); +_func_exit_; +} + +static void _rtx_ATOMIC_SET(ATOMIC_T *v, int i) +{ + atomic_set(v,i); +} + +static int _rtx_ATOMIC_READ(ATOMIC_T *v) +{ + return atomic_read(v); +} + +static void _rtx_ATOMIC_ADD(ATOMIC_T *v, int i) +{ + save_and_cli(); + v->counter += i; + restore_flags(); +} + +static void _rtx_ATOMIC_SUB(ATOMIC_T *v, int i) +{ + save_and_cli(); + v->counter -= i; + restore_flags(); +} + +static void _rtx_ATOMIC_INC(ATOMIC_T *v) +{ + save_and_cli(); + v->counter++; + restore_flags(); +} + +static void _rtx_ATOMIC_DEC(ATOMIC_T *v) +{ + save_and_cli(); + v->counter--; + restore_flags(); +} + +static int _rtx_ATOMIC_ADD_RETURN(ATOMIC_T *v, int i) +{ + int temp; + + save_and_cli(); + temp = v->counter; + temp += i; + v->counter = temp; + restore_flags(); + + return temp; +} + +static int _rtx_ATOMIC_SUB_RETURN(ATOMIC_T *v, int i) +{ + int temp; + + save_and_cli(); + temp = v->counter; + temp -= i; + v->counter = temp; + restore_flags(); + + return temp; +} + +static int _rtx_ATOMIC_INC_RETURN(ATOMIC_T *v) +{ + return _rtx_ATOMIC_ADD_RETURN(v, 1); +} + +static int _rtx_ATOMIC_DEC_RETURN(ATOMIC_T *v) +{ + return _rtx_ATOMIC_SUB_RETURN(v, 1); +} + +static u64 _rtx_modular64(u64 n, u64 base) +{ + unsigned int __base = (base); + unsigned int __rem; +_func_enter_; + if (((n) >> 32) == 0) { + __rem = (unsigned int)(n) % __base; + (n) = (unsigned int)(n) / __base; + } + else + __rem = __div64_32(&(n), __base); +_func_exit_; + return __rem; +} + +/* Refer to ecos bsd tcpip codes */ +static int _rtx_arc4random(void) +{ +_func_enter_; + u32 res = _rtx_get_current_time(); + static unsigned long seed = 0xDEADB00B; + seed = ((seed & 0x007F00FF) << 7) ^ + ((seed & 0x0F80FF00) >> 8) ^ // be sure to stir those low bits + (res << 13) ^ (res >> 9); // using the clock too! +_func_exit_; + return (int)seed; +} + +static int _rtx_get_random_bytes(void *buf, u32 len) +{ +#if 1 //becuase of 4-byte align, we use the follow code style. + unsigned int ranbuf; + unsigned int *lp; + int i, count; + count = len / sizeof(unsigned int); + lp = (unsigned int *) buf; +_func_enter_; + for(i = 0; i < count; i ++) { + lp[i] = _rtx_arc4random(); + len -= sizeof(unsigned int); + } + + if(len > 0) { + ranbuf = _rtx_arc4random(); + _rtx_memcpy(&lp[i], &ranbuf, len); + } +_func_exit_; + return 0; +#else + unsigned long ranbuf, *lp; + lp = (unsigned long *)buf; + while (len > 0) { + ranbuf = _rtx_arc4random(); + *lp++ = ranbuf; //this op need the pointer is 4Byte-align! + len -= sizeof(ranbuf); + } + return 0; +#endif +} + +static u32 _rtx_GetFreeHeapSize(void) +{ +#if USE_HEAP_INFO + return osFreeBytesRemaining; +#else + return 0; +#endif +} + + +#if CONFIG_USE_TCM_HEAP +void *tcm_heap_malloc(int size); +#endif +static int _rtx_create_task(struct task_struct *ptask, const char *name, + u32 stack_size, u32 priority, thread_func_t func, void *thctx) +{ +_func_enter_; + rtx_thread_data_t *thread_hdl = NULL; + u32 stacksize = stack_size * 4; //sizeof(DWORD) + if(!func) + goto err_exit; + thread_hdl = (rtx_thread_data_t *)_rtx_zmalloc(sizeof(rtx_thread_data_t)); + if(thread_hdl == NULL) + goto err_exit; +#ifdef CMSIS_OS_RTX +#ifndef __MBED_CMSIS_RTOS_CA9 + thread_hdl->def.stack_pointer = (void *)_rtx_malloc(stacksize); + if(thread_hdl->def.stack_pointer == NULL) + goto err_exit; +#endif + if(priority > osPriorityRealtime){ + DBG_ERR("[%s]priority is higher than osPriorityRealtime", name); + priority = osPriorityRealtime; + } + thread_hdl->def.pthread = (os_pthread)func; + thread_hdl->def.tpriority = (osPriority)priority; + thread_hdl->def.stacksize = stacksize; +#endif + ptask->task = (_thread_hdl_)thread_hdl; + ptask->task_name = name; + ptask->blocked = 0; + ptask->callback_running = 0; + + _rtx_init_sema(&ptask->wakeup_sema, 0); + _rtx_init_sema(&ptask->terminate_sema, 0); + //rtw_init_queue(&wq->work_queue); + + thread_hdl->id = osThreadCreate(&thread_hdl->def, thctx); + if(thread_hdl->id == NULL) + goto err_exit; + return _SUCCESS; +err_exit: + if(thread_hdl){ + _rtx_free_sema(&ptask->wakeup_sema); + _rtx_free_sema(&ptask->terminate_sema); + _rtx_memset((u8 *)ptask, 0, sizeof(*ptask)); +#ifndef __MBED_CMSIS_RTOS_CA9 + if(thread_hdl->def.stack_pointer) + _rtx_mfree((void *)thread_hdl->def.stack_pointer, thread_hdl->def.stacksize); +#endif + _rtx_mfree((u8 *)thread_hdl, sizeof(rtx_thread_data_t)); + } + DBG_ERR("Create Task \"%s\" Failed! \n", ptask->task_name); + return _FAIL; +} + +static void _rtx_delete_task(struct task_struct *ptask) +{ +_func_enter_; + rtx_thread_data_t *thread_hdl = (rtx_thread_data_t *)ptask->task; + if (!thread_hdl){ + DBG_ERR("_rtx_delete_task(): ptask is NULL!\n"); + return; + } + + ptask->blocked = 1; + + _rtx_up_sema(&ptask->wakeup_sema); + _rtx_down_sema(&ptask->terminate_sema, TIMER_MAX_DELAY); + + osThreadTerminate(thread_hdl->id); +#ifndef __MBED_CMSIS_RTOS_CA9 + if(thread_hdl->def.stack_pointer) + _rtx_mfree((void *)thread_hdl->def.stack_pointer, thread_hdl->def.stacksize); +#endif + _rtx_mfree((u8 *)thread_hdl, sizeof(rtx_thread_data_t)); + + //rtw_deinit_queue(&wq->work_queue); + _rtx_free_sema(&ptask->wakeup_sema); + _rtx_free_sema(&ptask->terminate_sema); + + ptask->task = NULL; + + DBG_TRACE("Delete Task \"%s\"\n", ptask->task_name); +_func_exit_; +} + +void _rtx_wakeup_task(struct task_struct *ptask) +{ +_func_enter_; + if(ptask) + _rtx_up_sema(&ptask->wakeup_sema); +_func_exit_; +} + +static void _rtx_thread_enter(char *name) +{ +_func_enter_; + DBG_INFO("\n\rRTKTHREAD %s\n", name); +_func_exit_; +} + +static void _rtx_thread_exit(void) +{ +_func_enter_; + osThreadId id = osThreadGetId(); + osThreadTerminate(id); +_func_exit_; +} + +/***************************************************** +************timer data block, defined in rt_CMSIS.c********* + +// Timer definitions +#define osTimerInvalid 0 +#define osTimerStopped 1 +#define osTimerRunning 2 + +// Timer structures + +typedef struct os_timer_cb_ { // Timer Control Block + struct os_timer_cb_ *next; // Pointer to next active Timer, (u8 *)data[0:3] + uint8_t state; // Timer State, (u8 *)data[4] + uint8_t type; // Timer Type (Periodic/One-shot), (u8 *)data[5] + uint16_t reserved; // Reserved, (u8 *)data[6:7] + uint16_t tcnt; // Timer Delay Count, (u8 *)data[8:9] + uint16_t icnt; // Timer Initial Count, (u8 *)data[10:11] + void *arg; // Timer Function Argument, (u8 *)data[12:15] + osTimerDef_t *timer; // Pointer to Timer definition, (u8 *)data[16:19] +} os_timer_cb; +*****************************************************/ +_timerHandle _rtx_timerCreate( const signed char *pcTimerName, + osdepTickType xTimerPeriodInTicks, + u32 uxAutoReload, + void * pvTimerID, + TIMER_FUN pxCallbackFunction ) +{ +_func_enter_; + rtx_tmr_t *tmr = (rtx_tmr_t *)_rtx_zmalloc(sizeof(rtx_tmr_t)); + os_timer_type type = (uxAutoReload == _TRUE)?osTimerPeriodic:osTimerOnce; + if(tmr == NULL) + goto err_exit; +#ifdef CMSIS_OS_RTX + tmr->def.ptimer = (os_ptimer)pxCallbackFunction; + tmr->def.timer = (void *)tmr->data; +#endif + if(pvTimerID == NULL) + pvTimerID = (void *)tmr; + tmr->id = osTimerCreate(&tmr->def, type, pvTimerID); + if(tmr->id == NULL) + goto err_exit; +_func_exit_; + return (_timerHandle)tmr; +err_exit: + DBG_ERR("error"); + if(tmr) + _rtx_mfree((u8 *)tmr, sizeof(rtx_tmr_t)); + return NULL; +} + +u32 _rtx_timerDelete( _timerHandle xTimer, + osdepTickType xBlockTime ) +{ +_func_enter_; + rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer; + osStatus status = osTimerDelete(tmr->id); + _rtx_mfree((u8 *)tmr, sizeof(rtx_tmr_t)); + if(status != osOK){ + DBG_ERR("error %d", status); + return _FAIL; + } +_func_exit_; + return _SUCCESS; +} + +u32 _rtx_timerIsTimerActive( _timerHandle xTimer ) +{ +_func_enter_; + rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer; + u8 *data = (u8 *)tmr->data; +_func_exit_; + switch(data[4]){ + case 2U: + return _TRUE; + default: + return _FALSE; + } +} + +u32 _rtx_timerStop( _timerHandle xTimer, + osdepTickType xBlockTime ) +{ +_func_enter_; + rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer; + osStatus status = osTimerStop(tmr->id); +_func_exit_; + if(status == osOK) + return _SUCCESS; + + DBG_ERR("error %d\n", status); + return _FAIL; +} + +u32 _rtx_timerChangePeriod( _timerHandle xTimer, + osdepTickType xNewPeriod, + osdepTickType xBlockTime ) +{ +_func_enter_; + rtx_tmr_t *tmr = (rtx_tmr_t *) xTimer; + osStatus ret; + + if(xNewPeriod == 0) + xNewPeriod += 1; + xNewPeriod = _rtx_systime_to_ms(xNewPeriod); + ret = osTimerStart(tmr->id, xNewPeriod); +_func_exit_; + if(ret == osOK) + return _SUCCESS; + + DBG_ERR("%s error\n", __FUNCTION__); + return _FAIL; +} + +//void _rtx_acquire_wakelock() +//{ +//#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1) +// acquire_wakelock(WAKELOCK_WLAN); +//#endif +//} + +//void _rtx_release_wakelock() +//{ +//#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1) +// release_wakelock(WAKELOCK_WLAN); +//#endif +//} + +u8 _rtx_get_scheduler_state(void) +{ +_func_enter_; + int32_t state = osKernelRunning(); + u8 state_out = OS_SCHEDULER_NOT_STARTED; + switch(state){ + case 1: state = OS_SCHEDULER_RUNNING; break; + case 0: state = OS_SCHEDULER_SUSPENDED; break; + default: break; + } +_func_exit_; + return state_out; +} + +const struct osdep_service_ops osdep_service = { + _rtx_malloc, //rtw_vmalloc + _rtx_zmalloc, //rtw_zvmalloc + _rtx_mfree, //rtw_vmfree + _rtx_malloc, //rtw_malloc + _rtx_zmalloc, //rtw_zmalloc + _rtx_mfree, //rtw_mfree + _rtx_memcpy, //rtw_memcpy + _rtx_memcmp, //rtw_memcmp + _rtx_memset, //rtw_memset + _rtx_init_sema, //rtw_init_sema + _rtx_free_sema, //rtw_free_sema + _rtx_up_sema, //rtw_up_sema + _rtx_up_sema_from_isr,//rtw_up_sema_from_isr + _rtx_down_sema, //rtw_down_sema + _rtx_mutex_init, //rtw_mutex_init + _rtx_mutex_free, //rtw_mutex_free + _rtx_mutex_get, //rtw_mutex_get + _rtx_mutex_get_timeout, //rtw_mutex_get_timeout + _rtx_mutex_put, //rtw_mutex_put + _rtx_enter_critical, //rtw_enter_critical + _rtx_exit_critical, //rtw_exit_critical + _rtx_enter_critical_from_isr, //rtw_enter_critical_from_isr + _rtx_exit_critical_from_isr, //rtw_exit_critical_from_isr + NULL, //rtw_enter_critical_bh + NULL, //rtw_exit_critical_bh + _rtx_enter_critical_mutex, //rtw_enter_critical_mutex + _rtx_exit_critical_mutex, //rtw_exit_critical_mutex + _rtx_spinlock_init, //rtw_spinlock_init + _rtx_spinlock_free, //rtw_spinlock_free + _rtx_spinlock, //rtw_spin_lock + _rtx_spinunlock, //rtw_spin_unlock + _rtx_spinlock_irqsave, //rtw_spinlock_irqsave + _rtx_spinunlock_irqsave, //rtw_spinunlock_irqsave + _rtx_init_xqueue,//rtw_init_xqueue + _rtx_push_to_xqueue,//rtw_push_to_xqueue + _rtx_pop_from_xqueue,//rtw_pop_from_xqueue + _rtx_deinit_xqueue,//rtw_deinit_xqueue + _rtx_get_current_time, //rtw_get_current_time + _rtx_systime_to_ms, //rtw_systime_to_ms + _rtx_systime_to_sec, //rtw_systime_to_sec + _rtx_ms_to_systime, //rtw_ms_to_systime + _rtx_sec_to_systime, //rtw_sec_to_systime + _rtx_msleep_os, //rtw_msleep_os + _rtx_usleep_os, //rtw_usleep_os + _rtx_mdelay_os, //rtw_mdelay_os + _rtx_udelay_os, //rtw_udelay_os + _rtx_yield_os, //rtw_yield_os + + _rtx_ATOMIC_SET, //ATOMIC_SET + _rtx_ATOMIC_READ, //ATOMIC_READ + _rtx_ATOMIC_ADD, //ATOMIC_ADD + _rtx_ATOMIC_SUB, //ATOMIC_SUB + _rtx_ATOMIC_INC, //ATOMIC_INC + _rtx_ATOMIC_DEC, //ATOMIC_DEC + _rtx_ATOMIC_ADD_RETURN, //ATOMIC_ADD_RETURN + _rtx_ATOMIC_SUB_RETURN, //ATOMIC_SUB_RETURN + _rtx_ATOMIC_INC_RETURN, //ATOMIC_INC_RETURN + _rtx_ATOMIC_DEC_RETURN, //ATOMIC_DEC_RETURN + + _rtx_modular64, //rtw_modular64 + _rtx_get_random_bytes, //rtw_get_random_bytes + _rtx_GetFreeHeapSize, //rtw_getFreeHeapSize + + _rtx_create_task, //rtw_create_task + _rtx_delete_task, //rtw_delete_task + _rtx_wakeup_task, //rtw_wakeup_task + + _rtx_thread_enter, //rtw_thread_enter + _rtx_thread_exit, //rtw_thread_exit + + _rtx_timerCreate, //rtw_timerCreate, + _rtx_timerDelete, //rtw_timerDelete, + _rtx_timerIsTimerActive, //rtw_timerIsTimerActive, + _rtx_timerStop, //rtw_timerStop, + _rtx_timerChangePeriod, //rtw_timerChangePeriod + + NULL, // rtw_acquire_wakelock + NULL, // rtw_release_wakelock + NULL, //rtw_wakelock_timeout + + _rtx_get_scheduler_state // rtw_get_scheduler_state +}; + diff --git a/RTL00_SDKV35a/component/os/rtx/rtx_service.h b/RTL00_SDKV35a/component/os/rtx/rtx_service.h new file mode 100644 index 0000000..4396aea --- /dev/null +++ b/RTL00_SDKV35a/component/os/rtx/rtx_service.h @@ -0,0 +1,309 @@ +#ifndef _RTX_SERVICE_H_ +#define _RTX_SERVICE_H_ + +//----------------------------------------------------------------------- +// Include Files +//----------------------------------------------------------------------- +#include "wireless.h" +#include "dlist.h" +#include +#include +#include "RTX_Config.h" +#include +#include +#include + +// -------------------------------------------- +// Platform dependent include file +// -------------------------------------------- +#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) +//#include "platform_stdlib.h" +//#include "basic_types.h" +#include +#else +// other MCU may use standard library +#include +#endif + + +#if (defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI) || defined(CONFIG_LX_HCI) +/* For SPI interface transfer and us delay implementation */ +#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B) +#include +#endif +#endif + + +// -------------------------------------------- +// Platform dependent type define +// -------------------------------------------- +#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B) +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +typedef signed char s8; +typedef signed short s16; +typedef signed int s32; +typedef signed long long s64; +typedef unsigned long long u64; +typedef unsigned int uint; +typedef signed int sint; + +#ifndef bool +typedef int bool; +#define true 1 +#define false 0 +#endif + +#define IN +#define OUT +#define VOID void +#define NDIS_OID uint +#define NDIS_STATUS uint +#ifndef PVOID +typedef void * PVOID; +#endif + +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef __kernel_size_t SIZE_T; +typedef __kernel_ssize_t SSIZE_T; + +#endif //CONFIG_PLATFORM_8195A + +// === SEMAPHORE === +typedef struct { + osSemaphoreId id; + osSemaphoreDef_t def; +#ifdef CMSIS_OS_RTX + uint32_t data[2]; +#endif +} rtx_sema_t; + +// === THREAD === +typedef struct { + osThreadId id; + osThreadDef_t def; +} rtx_thread_data_t; + +// === MUTEX === +typedef struct { + osMutexId id; + osMutexDef_t def; +#ifdef CMSIS_OS_RTX +#if defined(__MBED_CMSIS_RTOS_CA9) || defined(__MBED_CMSIS_RTOS_CM) + int32_t data[4]; +#else + int32_t data[3]; +#endif +#endif +} rtx_mutex_t; + +// === MAIL BOX === +#define RTX_MB_SIZE 8 + +typedef struct { + osMessageQId id; + osMessageQDef_t def; +#ifdef CMSIS_OS_RTX + uint32_t queue; /* The (queue_size+4)*sizeof(uint32_t) is required for RTX OS_MCB overhead. */ +#endif +} rtx_mqueue_t; + +typedef struct { + osMailQId id; + osMailQDef_t def; +#ifdef CMSIS_OS_RTX + uint32_t os_mailQ_q; /* memory block, (4+queue_size)*sizeof(uint32_t)*/ + uint32_t os_mailQ_m; /* memory block, (3 + (item_size+3)/4)*queue_size*/ + void * os_mailQ_p[2]; +#endif +} rtx_mbox_t; + +typedef struct{ + osTimerId id; + osTimerDef_t def; +#if defined(CMSIS_OS_RTX) && !defined(__MBED_CMSIS_RTOS_CM) + uint32_t data[5]; +#else + uint32_t data[6]; +#endif +}rtx_tmr_t; + +#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field) + +// os types +typedef char osdepCHAR; +typedef float osdepFLOAT; +typedef double osdepDOUBLE; +typedef long osdepLONG; +typedef short osdepSHORT; +typedef unsigned long osdepSTACK_TYPE; +typedef long osdepBASE_TYPE; +typedef unsigned long osdepTickType; + +typedef void * _timerHandle; +typedef void * _sema; +typedef void * _mutex; +typedef void * _lock; +typedef void * _queueHandle; +typedef void * _xqueue; +typedef struct timer_list _timer; + +typedef struct sk_buff _pkt; +typedef unsigned char _buffer; + +#ifndef __LIST_H +#warning "DLIST_NOT_DEFINE!!!!!!" +struct list_head { + struct list_head *next, *prev; +}; +#endif + +struct __queue { + struct list_head queue; + _lock lock; +}; + +typedef struct __queue _queue; +typedef struct list_head _list; +typedef unsigned long _irqL; + +typedef void* _thread_hdl_; +typedef void thread_return; +typedef void* thread_context; + +#define ATOMIC_T atomic_t +#define HZ configTICK_RATE_HZ + +#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) +/* emulate a modern version */ +#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 17) + +static __inline _list *get_next(_list *list) +{ + return list->next; +} + +static __inline _list *get_list_head(_queue *queue) +{ + return (&(queue->queue)); +} + +#define LIST_CONTAINOR(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)((char *)&((type *)ptr)->member - (char *)ptr))) +//#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n)) +#define container_of(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) +#define TASK_PRORITY_LOW osPriorityAboveNormal//osPriorityNormal +#define TASK_PRORITY_MIDDLE osPriorityHigh//osPriorityAboveNormal +#define TASK_PRORITY_HIGH osPriorityRealtime//osPriorityHigh +#define TASK_PRORITY_SUPER osPriorityRealtime +#define TASK_PRORITY_IDEL osPriorityIdle + + +#define TIMER_MAX_DELAY 0xFFFFFFFF +void save_and_cli(void); +void restore_flags(void); +void cli(void); + +//----- ------------------------------------------------------------------ +// Common Definition +//----- ------------------------------------------------------------------ + +#define __init +#define __exit +#define __devinit +#define __devexit + +#define KERN_ERR +#define KERN_INFO +#define KERN_NOTICE + +#define GFP_KERNEL 1 +#define GFP_ATOMIC 1 + +#define SET_MODULE_OWNER(some_struct) do { } while (0) +#define SET_NETDEV_DEV(dev, obj) do { } while (0) +#define register_netdev(dev) (0) +#define unregister_netdev(dev) do { } while (0) +#define netif_queue_stopped(dev) (0) +#define netif_wake_queue(dev) do { } while (0) +#define printk printf + +#define DBG_ERR(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args) +#if WLAN_INTF_DBG +#define DBG_TRACE(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args) +#define DBG_INFO(fmt, args...) printf("\n\r[%s] " fmt, __FUNCTION__, ## args) +#else +#define DBG_TRACE(fmt, args...) +#define DBG_INFO(fmt, args...) +#endif +#define HALT() do { cli(); for(;;);} while(0) +#define ASSERT(x) do { \ + if((x) == 0) \ + printf("\n\rAssert(" #x ") failed on line %d in file %s", __LINE__, __FILE__); \ + HALT(); \ + } while(0) + +#undef DBG_ASSERT +#define DBG_ASSERT(x, msg) do { \ + if((x) == 0) \ + printf("\n\r%s, Assert(" #x ") failed on line %d in file %s", msg, __LINE__, __FILE__); \ + } while(0) + +//----- ------------------------------------------------------------------ +// Atomic Operation +//----- ------------------------------------------------------------------ +#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B) // for 8195A, it is defined in ..system../basic_types.h +typedef struct { volatile int counter; } atomic_t; +#endif + + +/* + * atomic_read - read atomic variable + * @v: pointer of type atomic_t + * + * Atomically reads the value of @v. Note that the guaranteed + * useful range of an atomic_t is only 24 bits. + */ +#define atomic_read(v) ((v)->counter) + +/* + * atomic_set - set atomic variable + * @v: pointer of type atomic_t + * @i: required value + * + * Atomically sets the value of @v to @i. Note that the guaranteed + * useful range of an atomic_t is only 24 bits. + */ +#define atomic_set(v,i) ((v)->counter = (i)) + + /* + * These inlines deal with timer wrapping correctly. You are + * strongly encouraged to use them + * 1. Because people otherwise forget + * 2. Because if the timer wrap changes in future you wont have to + * alter your driver code. + * + * time_after(a,b) returns true if the time a is after time b. + * + * Do this with "<0" and ">=0" to only test the sign of the result. A + * good compiler would generate better code (and a really good compiler + * wouldn't care). Gcc is currently neither. + */ + #define time_after(a,b) ((long)(b) - (long)(a) < 0) + #define time_before(a,b) time_after(b,a) + + #define time_after_eq(a,b) ((long)(a) - (long)(b) >= 0) + #define time_before_eq(a,b) time_after_eq(b,a) + + +extern void rtw_init_listhead(_list *list); +extern u32 rtw_is_list_empty(_list *phead); +extern void rtw_list_insert_head(_list *plist, _list *phead); +extern void rtw_list_insert_tail(_list *plist, _list *phead); +extern void rtw_list_delete(_list *plist); +#define vPortExitCritical save_and_cli +#endif /* _RTX_SERVICE_H_ */ + diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/include/rtl_lib.h b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/include/rtl_lib.h index 5d81df9..13c7e8f 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/include/rtl_lib.h +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/include/rtl_lib.h @@ -10,6 +10,7 @@ #include #include +#include extern int __rtl_errno; @@ -23,10 +24,10 @@ void init_rom_libgloss_ram_map(void); // extern int rtl_printf(IN const char* fmt, ...); -extern int rtl_vprintf(const char *fmt, void *param); +extern int rtl_vprintf(const char *fmt, va_list param); extern int rtl_sprintf(char* str, const char* fmt, ...); extern int rtl_snprintf(char* str, size_t size, const char* fmt, ...); -extern int rtl_vsnprintf(char *str, size_t size, const char *fmt, void *param); +extern int rtl_vsnprintf(char *str, size_t size, const char *fmt, va_list param); // // RTL library functions for string diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/include/rtl_rr_libc.h b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/include/rtl_rr_libc.h new file mode 100644 index 0000000..e548044 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/include/rtl_rr_libc.h @@ -0,0 +1,166 @@ +/* +* RAM->ROM Calls +*/ + +#ifndef _INC_RTL_RR_LIBC_ +#define _INC_RTL_RR_LIBC_ + +//#undef malloc +#define malloc(size) pvPortMalloc(size) +//#undef free +#define free(pbuf) vPortFree(pbuf) +//extern void* pvPortReAlloc( void *pv, size_t xWantedSize ) +#define realloc(pv, xWantedSize) pvPortReAlloc(pv, xWantedSize) + +#define calloc(nelements, elementSize) calloc_freertos(nelements, elementSize) + +#define snprintf rtl_snprintf +#define sprintf rtl_sprintf +#define printf rtl_printf +#define vprintf rtl_vprintf +#define vsnprintf rtl_vsnprintf +#define vfprintf rtl_vfprintf +#define memchr rtl_memchr +#define memcmp rtl_memcmp +#define memcpy rtl_memcpy +#define memmove rtl_memmove +#define memset rtl_memset +#define strcat rtl_strcat +#define strchr rtl_strchr +#define strcmp rtl_strcmp +#define strcpy rtl_strcpy +#define strlen rtl_strlen +#define strncat rtl_strncat +#define strncmp rtl_strncmp +#define strncpy rtl_strncpy +#define strstr rtl_strstr +#define strsep rtl_strsep +#define strtok rtl_strtok + +#if 0 // __aeabi_ +#define dtoi rtl_dtoi +#define dtoui rtl_dtoui +#define i2f rtl_i2f +#define i2d rtl_i2d +#define ui2f rtl_ui2f +#define ui2d rtl_ui2d +#define itoa rtl_itoa +#define ltoa rtl_ltoa +#define utoa rtl_utoa +#define ultoa rtl_ultoa +#define ftol rtl_ftol +#define ftod rtl_ftod +#define dtof rtl_dtof +#define fadd rtl_fadd +#define fsub rtl_fsub +#define fmul rtl_fmul +#define fdiv rtl_fdiv +#define dadd rtl_dadd +#define dsub rtl_dsub +#define dmul rtl_dmul +#define ddiv rtl_ddiv +#define dcmpeq rtl_dcmpeq +#define dcmplt rtl_dcmplt +#define dcmple rtl_dcmple +#define dcmpgt rtl_dcmpgt +#define fcmplt rtl_fcmplt +#define fcmpgt rtl_fcmpgt + +#define fabsf rtl_fabsf +#define fabs rtl_fabs +#define cos_f32 rtl_cos_f32 +#define sin_f32 rtl_sin_f32 +#endif + +#if 0 +extern void *calloc_freertos(size_t nelements, size_t elementSize); +// ram_libc.c +extern void rtl_libc_init(void); +extern int rtl_snprintf(char *str, size_t size, const char *fmt, ...); +extern int rtl_sprintf(char *str, const char *fmt, ...); +extern int rtl_printf(const char *fmt, ...); +extern int rtl_vprintf(const char *fmt, void *param); +extern int rtl_vsnprintf(char *str, size_t size, const char *fmt, void *param); +extern int rtl_vfprintf(FILE *fp, const char *fmt0, va_list ap); +extern void * rtl_memchr(const void * src_void , int c , size_t length); +extern int rtl_memcmp(const void *m1, const void *m2, size_t n); +extern void * rtl_memcpy(void *dst0, const void *src0, size_t len0); +extern void * rtl_memmove(void *dst_void, const void *src_void, size_t length); +extern void * rtl_memset(void *m, int c, size_t n); +extern char * rtl_strcat(char *s1, const char *s2); +extern char * rtl_strchr(const char *s1, int i); +extern int rtl_strcmp(const char *s1, const char *s2); +extern char * rtl_strcpy(char *dst0, const char *src0); +extern size_t rtl_strlen(const char *str); +extern char * rtl_strncat(char *s1, const char *s2, size_t n); +extern int rtl_strncmp(const char *s1, const char *s2, size_t n); +extern char * rtl_strncpy(char *dst0, const char *src0, size_t count); +extern char * rtl_strstr(const char *searchee, const char *lookfor); +extern char * rtl_strsep(char **source_ptr, const char *delim); +extern char * rtl_strtok(char *s, const char *delim); + +//rtl_eabi_cast_ram.c +extern int rtl_dtoi(double d); +extern int rtl_dtoui(double d); +extern float rtl_i2f(int val); +extern int rtl_i2d(int val); +extern float rtl_ui2f(unsigned int val); +extern int rtl_ui2d(unsigned int val); +extern char *rtl_itoa(int value, char *string, int radix); +extern char *rtl_ltoa(int value, char *string, int radix); +extern char *rtl_utoa(unsigned int value, char *string, int radix); +extern char *rtl_ultoa(unsigned int value, char *string, int radix); +extern int rtl_ftol(float f); +extern int rtl_ftod(float f); +extern float rtl_dtof(double d); +extern float rtl_fadd(float a, float b); +extern float rtl_fsub(float a, float b); +extern float rtl_fmul(float a, float b); +extern float rtl_fdiv(float a, float b); +extern int rtl_dadd(double a, double b); +extern int rtl_dsub(double a, double b); +extern int rtl_dmul(double a, double b); +extern int rtl_ddiv(double a, double b); +extern int rtl_dcmpeq(double a, double b); +extern int rtl_dcmplt(double a, double b); +extern int rtl_dcmple(double a, double b); +extern int rtl_dcmpgt(double a, double b); +extern int rtl_fcmplt(float a, float b); +extern int rtl_fcmpgt(float a, float b); + +// rtl_math_ram.c +extern float rtl_fabsf(float a); +extern int rtl_fabs(double a); +extern float rtl_cos_f32(float a); +extern float rtl_sin_f32(float a); + +// ram_pvvx_libc.c +extern int snprintf(char *str, size_t size, const char *fmt, ...); +extern int sprintf(char *str, const char *fmt, ...); +extern int printf(const char *fmt, ...); +extern int vprintf(const char * fmt, __VALIST param); +extern int vsnprintf(char *str, size_t size, const char *fmt, __VALIST param); +extern int vfprintf(FILE *fp, const char *fmt0, va_list ap); +extern void * memchr(const void * src_void , int c , size_t length); +extern int memcmp(const void *m1, const void *m2, size_t n); +extern void * memcpy(void *dst0, const void *src0, size_t len0); +extern void * memmove(void *dst_void, const void *src_void, size_t length); +extern void * memset(void *m, int c, size_t n); +extern char * strcat(char *s1, const char *s2); +extern char * strchr(const char *s1, int i); +extern int strcmp(const char *s1, const char *s2); +extern char * strcpy(char *dst0, const char *src0); +extern size_t strlen(const char *str); +extern char * strncat(char *s1, const char *s2, size_t n); +extern int strncmp(const char *s1, const char *s2, size_t n); +extern char * strncpy(char *dst0, const char *src0, size_t count); +extern char * strstr(const char *searchee, const char *lookfor); +extern char * strsep(char **source_ptr, const char *delim); +extern char * strtok(char *s, const char *delim); +extern int sscanf(const char *buf, const char *fmt, ...); +extern char toupper(char ch); +extern int _stricmp (const char *s1, const char *s2); +extern unsigned long long __aeabi_llsr(unsigned long long val, unsigned int shift); +#endif + +#endif // _INC_RTL_RR_LIBC_ \ No newline at end of file diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/c_stdio.c b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/c_stdio.c new file mode 100644 index 0000000..4ff3a67 --- /dev/null +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/c_stdio.c @@ -0,0 +1,1093 @@ + +#include "platform_autoconf.h" +#if 1 //def ENAC_FLOAT +#include +#include +#include "libc/rom/string/rom_libc_string.h" + +#define memchr __rtl_memchr_v1_00 +#define memcmp __rtl_memcmp_v1_00 +#define memcpy __rtl_memcpy_v1_00 +#define memmove __rtl_memmove_v1_00 +#define memset __rtl_memset_v1_00 +#define strcat __rtl_strcat_v1_00 +#define strchr __rtl_strchr_v1_00 +#define strcmp __rtl_strcmp_v1_00 +#define strcpy __rtl_strcpy_v1_00 +#define strlen __rtl_strlen_v1_00 +#define strncat __rtl_strncat_v1_00 +#define strncmp __rtl_strncmp_v1_00 +#define strncpy __rtl_strncpy_v1_00 +#define strstr __rtl_strstr_v1_00 +#define strsep __rtl_strsep_v1_00 +#define strtok __rtl_strtok_v1_00 + +static char toupper(char ch) { + return ((ch >= 'a' && ch <= 'z') ? ch - 'a' + 'A' : ch); +}; + +#define NEWFP 1 +#define ENDIAN_LITTLE 1234 +#define ENDIAN_BIG 4321 +#define ENDIAN_PDP 3412 +#define ENDIAN ENDIAN_LITTLE + +/* $Id: strichr.c,v 1.1.1.1 2006/08/23 17:03:06 pefo Exp $ */ + +/* + * Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Opsycon AB. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +//#include + +char * +strichr(char *p, int c) +{ + char *t; + + if (p != NULL) { + for(t = p; *t; t++); + for (; t >= p; t--) { + *(t + 1) = *t; + } + *p = c; + } + return (p); +} + +/* $Id: str_fmt.c,v 1.1.1.1 2006/08/23 17:03:06 pefo Exp $ */ + +/* + * Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Opsycon AB. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +//#include + +#define FMT_RJUST 0 +#define FMT_LJUST 1 +#define FMT_RJUST0 2 +#define FMT_CENTER 3 + +/* + * Format string by inserting blanks. + */ + +void +str_fmt(char *p, int size, int fmt) +{ + int n, m, len; + + len = strlen (p); + switch (fmt) { + case FMT_RJUST: + for (n = size - len; n > 0; n--) + strichr (p, ' '); + break; + case FMT_LJUST: + for (m = size - len; m > 0; m--) + strcat (p, " "); + break; + case FMT_RJUST0: + for (n = size - len; n > 0; n--) + strichr (p, '0'); + break; + case FMT_CENTER: + m = (size - len) / 2; + n = size - (len + m); + for (; m > 0; m--) + strcat (p, " "); + for (; n > 0; n--) + strichr (p, ' '); + break; + } +} + +/* $Id: strtoupp.c,v 1.1.1.1 2006/08/23 17:03:06 pefo Exp $ */ + +/* + * Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Opsycon AB. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +//#include +//#include +/* + * strtoupper() + */ +void +strtoupper(char *p) +{ + if(!p) + return; + for (; *p; p++) + *p = toupper (*p); +} + +/* $Id: atob.c,v 1.1.1.1 2006/08/23 17:03:06 pefo Exp $ */ + +/* + * Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Opsycon AB. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +//#include +//#include +//#include + +//typedef int int32_t; +typedef unsigned int u_int32_t; +typedef unsigned int u_int; +typedef unsigned long u_long; +typedef int32_t register_t; +typedef long long quad_t; +typedef unsigned long long u_quad_t; +typedef double rtype; + +#ifndef __P +#define __P(args) args +#endif + +static char * _getbase __P((char *, int *)); +static int _atob __P((unsigned long long *, char *p, int)); + +static char * +_getbase(char *p, int *basep) +{ + if (p[0] == '0') { + switch (p[1]) { + case 'x': + *basep = 16; + break; + case 't': case 'n': + *basep = 10; + break; + case 'o': + *basep = 8; + break; + default: + *basep = 10; + return (p); + } + return (p + 2); + } + *basep = 10; + return (p); +} + + +/* + * _atob(vp,p,base) + */ +static int +_atob (u_quad_t *vp, char *p, int base) +{ + u_quad_t value, v1, v2; + char *q, tmp[20]; + int digit; + + if (p[0] == '0' && (p[1] == 'x' || p[1] == 'X')) { + base = 16; + p += 2; + } + + if (base == 16 && (q = strchr (p, '.')) != 0) { + if (q - p > sizeof(tmp) - 1) + return (0); + + strncpy (tmp, p, q - p); + tmp[q - p] = '\0'; + if (!_atob (&v1, tmp, 16)) + return (0); + + q++; + if (strchr (q, '.')) + return (0); + + if (!_atob (&v2, q, 16)) + return (0); + *vp = (v1 << 16) + v2; + return (1); + } + + value = *vp = 0; + for (; *p; p++) { + if (*p >= '0' && *p <= '9') + digit = *p - '0'; + else if (*p >= 'a' && *p <= 'f') + digit = *p - 'a' + 10; + else if (*p >= 'A' && *p <= 'F') + digit = *p - 'A' + 10; + else + return (0); + + if (digit >= base) + return (0); + value *= base; + value += digit; + } + *vp = value; + return (1); +} + +/* + * atob(vp,p,base) + * converts p to binary result in vp, rtn 1 on success + */ +int +atob(u_int32_t *vp, char *p, int base) +{ + u_quad_t v; + + if (base == 0) + p = _getbase (p, &base); + if (_atob (&v, p, base)) { + *vp = v; + return (1); + } + return (0); +} + + +/* + * llatob(vp,p,base) + * converts p to binary result in vp, rtn 1 on success + */ +int +llatob(u_quad_t *vp, char *p, int base) +{ + if (base == 0) + p = _getbase (p, &base); + return _atob(vp, p, base); +} + + +/* + * char *btoa(dst,value,base) + * converts value to ascii, result in dst + */ +char * +btoa(char *dst, u_int value, int base) +{ + char buf[34], digit; + int i, j, rem, neg; + + if (value == 0) { + dst[0] = '0'; + dst[1] = 0; + return (dst); + } + + neg = 0; + if (base == -10) { + base = 10; + if (value & (1L << 31)) { + value = (~value) + 1; + neg = 1; + } + } + + for (i = 0; value != 0; i++) { + rem = value % base; + value /= base; + if (rem >= 0 && rem <= 9) + digit = rem + '0'; + else if (rem >= 10 && rem <= 36) + digit = (rem - 10) + 'a'; + buf[i] = digit; + } + + buf[i] = 0; + if (neg) + strcat (buf, "-"); + + /* reverse the string */ + for (i = 0, j = strlen (buf) - 1; j >= 0; i++, j--) + dst[i] = buf[j]; + dst[i] = 0; + return (dst); +} + +/* + * char *btoa(dst,value,base) + * converts value to ascii, result in dst + */ +char * +llbtoa(char *dst, u_quad_t value, int base) +{ + char buf[66], digit; + int i, j, rem, neg; + + if (value == 0) { + dst[0] = '0'; + dst[1] = 0; + return (dst); + } + + neg = 0; + if (base == -10) { + base = 10; + if (value & (1LL << 63)) { + value = (~value) + 1; + neg = 1; + } + } + + for (i = 0; value != 0; i++) { + rem = value % base; + value /= base; + if (rem >= 0 && rem <= 9) + digit = rem + '0'; + else if (rem >= 10 && rem <= 36) + digit = (rem - 10) + 'a'; + buf[i] = digit; + } + + buf[i] = 0; + if (neg) + strcat (buf, "-"); + + /* reverse the string */ + for (i = 0, j = strlen (buf) - 1; j >= 0; i++, j--) + dst[i] = buf[j]; + dst[i] = 0; + return (dst); +} + +/* + * gethex(vp,p,n) + * convert n hex digits from p to binary, result in vp, + * rtn 1 on success + */ +int +gethex(int32_t *vp, char *p, int n) +{ + u_long v; + int digit; + + for (v = 0; n > 0; n--) { + if (*p == 0) + return (0); + if (*p >= '0' && *p <= '9') + digit = *p - '0'; + else if (*p >= 'a' && *p <= 'f') + digit = *p - 'a' + 10; + else if (*p >= 'A' && *p <= 'F') + digit = *p - 'A' + 10; + else + return (0); + + v <<= 4; + v |= digit; + p++; + } + *vp = v; + return (1); +} + +/* $Id: vsprintf.c,v 1.1.1.1 2006/08/23 17:03:06 pefo Exp $ */ + +/* + * Copyright (c) 2000-2002 Opsycon AB (www.opsycon.se) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Opsycon AB. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +//#include +//#include +//#include +//#include +//#include + +void dtoa (char *dbuf, rtype arg, int fmtch, int width, int prec); + +/* + * int vsprintf(d,s,ap) + */ +int +c_vsprintf (char *d, const char *s, va_list ap) +{ + const char *t; + char *p, *dst, tmp[40]; + unsigned int n; + int fmt, trunc, haddot, width, base, longlong; + double dbl; +#ifndef NEWFP + EP ex; +#endif + + dst = d; + for (; *s;) { + if (*s == '%') { + s++; + fmt = FMT_RJUST; + width = trunc = haddot = longlong = 0; + for (; *s; s++) { + if (strchr("bcdefgilopPrRsuxX%", *s)) + break; + else if (*s == '-') + fmt = FMT_LJUST; + else if (*s == '0') + fmt = FMT_RJUST0; + else if (*s == '~') + fmt = FMT_CENTER; + else if (*s == '*') { + if (haddot) + trunc = va_arg(ap, int); + else + width = va_arg(ap, int); + } else if (*s >= '1' && *s <= '9') { + for (t = s; isdigit(*s); s++); + strncpy(tmp, t, s - t); + tmp[s - t] = '\0'; + atob(&n, tmp, 10); + if (haddot) + trunc = n; + else + width = n; + s--; + } else if (*s == '.') + haddot = 1; + } + if (*s == '%') { + *d++ = '%'; + *d = 0; + } else if (*s == 's') { + p = va_arg(ap, char *); + + if (p) + strcpy(d, p); + else + strcpy(d, "(null)"); + } else if (*s == 'c') { + n = va_arg (ap, int); + *d = n; + d[1] = 0; + } else { + if (*s == 'l') { + if (*++s == 'l') { + longlong = 1; + ++s; + } + } + if (strchr("bdiopPrRxXu", *s)) { + if (*s == 'd' || *s == 'i') + base = -10; + else if (*s == 'u') + base = 10; + else if (*s == 'x' || *s == 'X') + base = 16; + else if(*s == 'p' || *s == 'P') { + base = 16; + if (*s == 'p') { + *d++ = '0'; + *d++ = 'x'; + } + fmt = FMT_RJUST0; + if (sizeof(long) > 4) { + width = 16; + longlong = 1; + } else { + width = 8; + } + } + else if(*s == 'r' || *s == 'R') { + base = 16; + if (*s == 'r') { + *d++ = '0'; + *d++ = 'x'; + } + fmt = FMT_RJUST0; + if (sizeof(register_t) > 4) { + width = 16; + longlong = 1; + } else { + width = 8; + } + } + else if (*s == 'o') + base = 8; + else if (*s == 'b') + base = 2; + if (longlong) + llbtoa(d, va_arg (ap, quad_t), + base); + else + btoa(d, va_arg (ap, int), base); + + if (*s == 'X') + strtoupper(d); + } + else if (strchr ("eEfgG", *s)) { + dbl = va_arg(ap, double); + dtoa(d, dbl, *s, width, trunc); + trunc = 0; + } + } + if (trunc) + d[trunc] = 0; + if (width) + str_fmt (d, width, fmt); + for (; *d; d++); + s++; + } else + *d++ = *s++; + } + *d = 0; + return (d - dst); +} + +/* + * Floating point output, cvt() onward lifted from BSD sources: + * + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#define MAX_FCONVERSION 512 /* largest possible real conversion */ +#define MAX_EXPT 5 /* largest possible exponent field */ +#define MAX_FRACT 39 /* largest possible fraction field */ + +#define TESTFLAG(x) 0 + + +typedef double rtype; + +extern double modf(double, double *); +#define to_char(n) ((n) + '0') +#define to_digit(c) ((c) - '0') +#define _isNan(arg) ((arg) != (arg)) + +static int cvt (rtype arg, int prec, char *signp, int fmtch, + char *startp, char *endp); +static char *c_round (double fract, int *exp, char *start, char *end, + char ch, char *signp); +static char *exponent(char *p, int exp, int fmtch); + + +/* + * _finite arg not Infinity or Nan + */ +static int _finite(rtype d) +{ +#if ENDIAN == ENDIAN_LITTLE + struct IEEEdp { + unsigned manl:32; + unsigned manh:20; + unsigned exp:11; + unsigned sign:1; + } *ip; +#else + struct IEEEdp { + unsigned sign:1; + unsigned exp:11; + unsigned manh:20; + unsigned manl:32; + } *ip; +#endif + + ip = (struct IEEEdp *)&d; + return (ip->exp != 0x7ff); +} + + +void dtoa (char *dbuf, rtype arg, int fmtch, int width, int prec) +{ + char buf[MAX_FCONVERSION+1], *cp; + char sign; + int size; + + if( !_finite(arg) ) { + if( _isNan(arg) ) + strcpy (dbuf, "NaN"); + else if( arg < 0) + strcpy (dbuf, "-Infinity"); + else + strcpy (dbuf, "Infinity"); + return; + } + + if (prec == 0) + prec = 6; + else if (prec > MAX_FRACT) + prec = MAX_FRACT; + + /* leave room for sign at start of buffer */ + cp = buf + 1; + + /* + * cvt may have to round up before the "start" of + * its buffer, i.e. ``intf("%.2f", (double)9.999);''; + * if the first character is still NUL, it did. + * softsign avoids negative 0 if _double < 0 but + * no significant digits will be shown. + */ + *cp = '\0'; + size = cvt (arg, prec, &sign, fmtch, cp, buf + sizeof(buf)); + if (*cp == '\0') + cp++; + + if (sign) + *--cp = sign, size++; + + cp[size] = 0; + memcpy (dbuf, cp, size + 1); +} + + +static int +cvt(rtype number, int prec, char *signp, int fmtch, char *startp, char *endp) +{ + register char *p, *t; + register double fract; + double integer, tmp; + int dotrim, expcnt, gformat; + + dotrim = expcnt = gformat = 0; + if (number < 0) { + number = -number; + *signp = '-'; + } else + *signp = 0; + + fract = modf(number, &integer); + + /* get an extra slot for rounding. */ + t = ++startp; + + /* + * get integer portion of number; put into the end of the buffer; the + * .01 is added for modf(356.0 / 10, &integer) returning .59999999... + */ + for (p = endp - 1; integer; ++expcnt) { + tmp = modf(integer / 10, &integer); + *p-- = to_char((int)((tmp + .01) * 10)); + } + switch (fmtch) { + case 'f': + /* reverse integer into beginning of buffer */ + if (expcnt) + for (; ++p < endp; *t++ = *p); + else + *t++ = '0'; + /* + * if precision required or alternate flag set, add in a + * decimal point. + */ + if (prec || TESTFLAG(ALTERNATE_FORM)) + *t++ = '.'; + /* if requires more precision and some fraction left */ + if (fract) { + if (prec) + do { + fract = modf(fract * 10, &tmp); + *t++ = to_char((int)tmp); + } while (--prec && fract); + if (fract) + startp = c_round(fract, (int *)NULL, startp, + t - 1, (char)0, signp); + } + for (; prec--; *t++ = '0'); + break; + case 'e': + case 'E': +eformat: if (expcnt) { + *t++ = *++p; + if (prec || TESTFLAG(ALTERNATE_FORM)) + *t++ = '.'; + /* if requires more precision and some integer left */ + for (; prec && ++p < endp; --prec) + *t++ = *p; + /* + * if done precision and more of the integer component, + * round using it; adjust fract so we don't re-round + * later. + */ + if (!prec && ++p < endp) { + fract = 0; + startp = c_round((double)0, &expcnt, startp, + t - 1, *p, signp); + } + /* adjust expcnt for digit in front of decimal */ + --expcnt; + } + /* until first fractional digit, decrement exponent */ + else if (fract) { + /* adjust expcnt for digit in front of decimal */ + for (expcnt = -1;; --expcnt) { + fract = modf(fract * 10, &tmp); + if (tmp) + break; + } + *t++ = to_char((int)tmp); + if (prec || TESTFLAG(ALTERNATE_FORM)) + *t++ = '.'; + } + else { + *t++ = '0'; + if (prec || TESTFLAG(ALTERNATE_FORM)) + *t++ = '.'; + } + /* if requires more precision and some fraction left */ + if (fract) { + if (prec) + do { + fract = modf(fract * 10, &tmp); + *t++ = to_char((int)tmp); + } while (--prec && fract); + if (fract) + startp = c_round(fract, &expcnt, startp, + t - 1, (char)0, signp); + } + /* if requires more precision */ + for (; prec--; *t++ = '0'); + + /* unless alternate flag, trim any g/G format trailing 0's */ + if (gformat && !TESTFLAG(ALTERNATE_FORM)) { + while (t > startp && *--t == '0'); + if (*t == '.') + --t; + ++t; + } + t = exponent(t, expcnt, fmtch); + break; + case 'g': + case 'G': + /* a precision of 0 is treated as a precision of 1. */ + if (!prec) + ++prec; + /* + * ``The style used depends on the value converted; style e + * will be used only if the exponent resulting from the + * conversion is less than -4 or greater than the precision.'' + * -- ANSI X3J11 + */ + if (expcnt > prec || (!expcnt && fract && fract < .0001)) { + /* + * g/G format counts "significant digits, not digits of + * precision; for the e/E format, this just causes an + * off-by-one problem, i.e. g/G considers the digit + * before the decimal point significant and e/E doesn't + * count it as precision. + */ + --prec; + fmtch -= 2; /* G->E, g->e */ + gformat = 1; + goto eformat; + } + /* + * reverse integer into beginning of buffer, + * note, decrement precision + */ + if (expcnt) + for (; ++p < endp; *t++ = *p, --prec); + else + *t++ = '0'; + /* + * if precision required or alternate flag set, add in a + * decimal point. If no digits yet, add in leading 0. + */ + if (prec || TESTFLAG(ALTERNATE_FORM)) { + dotrim = 1; + *t++ = '.'; + } + else + dotrim = 0; + /* if requires more precision and some fraction left */ + if (fract) { + if (prec) { + do { + fract = modf(fract * 10, &tmp); + *t++ = to_char((int)tmp); + } while(!tmp && !expcnt); + while (--prec && fract) { + fract = modf(fract * 10, &tmp); + *t++ = to_char((int)tmp); + } + } + if (fract) + startp = c_round(fract, (int *)NULL, startp, + t - 1, (char)0, signp); + } + /* alternate format, adds 0's for precision, else trim 0's */ + if (TESTFLAG(ALTERNATE_FORM)) + for (; prec--; *t++ = '0'); + else if (dotrim) { + while (t > startp && *--t == '0'); + if (*t != '.') + ++t; + } + } + return (t - startp); +} + + +static char * +c_round(double fract, int *exp, char *start, char *end, char ch, char *signp) +{ + double tmp; + + if (fract) + (void)modf(fract * 10, &tmp); + else + tmp = to_digit(ch); + if (tmp > 4) + for (;; --end) { + if (*end == '.') + --end; + if (++*end <= '9') + break; + *end = '0'; + if (end == start) { + if (exp) { /* e/E; increment exponent */ + *end = '1'; + ++*exp; + } + else { /* f; add extra digit */ + *--end = '1'; + --start; + } + break; + } + } + /* ``"%.3f", (double)-0.0004'' gives you a negative 0. */ + else if (*signp == '-') + for (;; --end) { + if (*end == '.') + --end; + if (*end != '0') + break; + if (end == start) + *signp = 0; + } + return (start); +} + +static char * +exponent(char *p, int exp, int fmtch) +{ + char *t; + char expbuf[MAX_FCONVERSION]; + + *p++ = fmtch; + if (exp < 0) { + exp = -exp; + *p++ = '-'; + } + else + *p++ = '+'; + t = expbuf + MAX_FCONVERSION; + if (exp > 9) { + do { + *--t = to_char(exp % 10); + } while ((exp /= 10) > 9); + *--t = to_char(exp); + for (; t < expbuf + MAX_FCONVERSION; *p++ = *t++); + } + else { + *p++ = '0'; + *p++ = to_char(exp); + } + return (p); +} + +int c_sprintf(char *str, const char *fmt, ...) +{ + va_list arg; + va_start(arg, fmt); + int ret = c_vsprintf(str, fmt, arg); + va_end(arg); + return ret; +} + +extern char AvaWds[]; +extern int ram_libgloss_write(int file, const char *ptr, int len); + +int c_printf(const char *fmt, ...) +{ + va_list arg; + va_start(arg, fmt); + int ret = c_vsprintf((char *)&AvaWds, fmt, arg); + va_end(arg); + return ram_libgloss_write(0, (char *)&AvaWds, ret); +} + +#endif // ENAC_FLOAT + +int puts (const char *s) +{ + while(*s) { + HalSerialPutcRtl8195a(*s++); + } +} + +void vTaskDelete(void *); + +void abort(void) +{ + + puts("Abort!\n"); + vTaskDelete(0); + while(1); +} + + + diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_libc.c b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_libc.c index 1b9132d..704a9d2 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_libc.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_libc.c @@ -10,30 +10,31 @@ //------------------------------------------------------------------------- // Function declarations - -//void rtl_libc_init(); -//int rtl_snprintf(char *str, size_t size, const char *fmt, ...); -//int rtl_sprintf(char *str, const char *fmt, ...); -//int rtl_printf(const char *fmt, ...); -//int rtl_vprintf(const char *fmt, void *param); -//int rtl_vsnprintf(char *str, size_t size, const char *fmt, void *param); -//int rtl_vfprintf(FILE *fp, const char *fmt0, va_list ap); -//int rtl_memchr(const void *src_void, int c, size_t length); -//int rtl_memcmp(const void *m1, const void *m2, size_t n); -//int rtl_memcpy(void *dst0, const void *src0, size_t len0); -//int rtl_memmove(void *dst_void, const void *src_void, size_t length); -//int rtl_memset(void *m, int c, size_t n); -//char * rtl_strcat(char *s1, const char *s2); -//char * rtl_strchr(const char *s1, int i); -//int rtl_strcmp(const char *s1, const char *s2); -//char * rtl_strcpy(char *dst0, const char *src0); -//int rtl_strlen(const char *str); -//char * rtl_strncat(char *s1, const char *s2, size_t n); -//int rtl_strncmp(const char *s1, const char *s2, size_t n); -//char * rtl_strncpy(char *dst0, const char *src0, size_t count); -//char * rtl_strstr(const char *searchee, const char *lookfor); -//char * rtl_strsep(char **source_ptr, const char *delim); -//char * rtl_strtok(char *s, const char *delim); +#if 0 +void rtl_libc_init(void); +int rtl_snprintf(char *str, size_t size, const char *fmt, ...); +int rtl_sprintf(char *str, const char *fmt, ...); +int rtl_printf(const char *fmt, ...); +int rtl_vprintf(const char *fmt, void *param); +int rtl_vsnprintf(char *str, size_t size, const char *fmt, void *param); +int rtl_vfprintf(FILE *fp, const char *fmt0, va_list ap); +void * rtl_memchr(const void * src_void , int c , size_t length); +int rtl_memcmp(const void *m1, const void *m2, size_t n); +void * rtl_memcpy(void *dst0, const void *src0, size_t len0); +void * rtl_memmove(void *dst_void, const void *src_void, size_t length); +void * rtl_memset(void *m, int c, size_t n); +char * rtl_strcat(char *s1, const char *s2); +char * rtl_strchr(const char *s1, int i); +int rtl_strcmp(const char *s1, const char *s2); +char * rtl_strcpy(char *dst0, const char *src0); +size_t rtl_strlen(const char *str); +char * rtl_strncat(char *s1, const char *s2, size_t n); +int rtl_strncmp(const char *s1, const char *s2, size_t n); +char * rtl_strncpy(char *dst0, const char *src0, size_t count); +char * rtl_strstr(const char *searchee, const char *lookfor); +char * rtl_strsep(char **source_ptr, const char *delim); +char * rtl_strtok(char *s, const char *delim); +#endif // Extern Calls: // extern int init_rom_libgloss_ram_map(_DWORD) // extern int _rom_mallocr_init_v1_00(void) @@ -149,20 +150,20 @@ int rtl_printf(const char *fmt, ...) { } //----- rtl_vprintf() -int rtl_vprintf(const char *fmt, void *param) { +int rtl_vprintf(const char *fmt, va_list param) { #if CHECK_LIBC_INIT if (!libc_has_init) { rtl_libc_init(); } #endif int result = __rtl_vfprintf_r_v1_00(_rtl_impure_ptr, - _rtl_impure_ptr->_stdout, fmt, *(va_list *)param); + _rtl_impure_ptr->_stdout, fmt, param); __rtl_fflush_r_v1_00(_rtl_impure_ptr, _rtl_impure_ptr->_stdout); return result; } //----- rtl_vsnprintf() -int rtl_vsnprintf(char *str, size_t size, const char *fmt, void *param) { +int rtl_vsnprintf(char *str, size_t size, const char *fmt, va_list param) { int result; int w; int v11; @@ -183,7 +184,7 @@ int rtl_vsnprintf(char *str, size_t size, const char *fmt, void *param) { f._w = w; f._bf._size = w; f._file = -1; - result = __rtl_vfprintf_r_v1_00(_rtl_impure_ptr, &f, fmt, *(va_list *)param); + result = __rtl_vfprintf_r_v1_00(_rtl_impure_ptr, &f, fmt, param); if (result + 1 < 0) _rtl_impure_ptr->_errno = 139; if (size) diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_pvvx_libc.c b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_pvvx_libc.c index d1ec84a..026201a 100644 --- a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_pvvx_libc.c +++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_pvvx_libc.c @@ -8,33 +8,38 @@ #include "va_list.h" #define CHECK_LIBC_INIT 0 - //------------------------------------------------------------------------- // Function declarations //void libc_init(); -//int snprintf(char *str, size_t size, const char *fmt, ...); -//int sprintf(char *str, const char *fmt, ...); -//int printf(const char *fmt, ...); -//int vprintf(const char *fmt, void *param); -//int vsnprintf(char *str, size_t size, const char *fmt, void *param); -//int vfprintf(FILE *fp, const char *fmt0, va_list ap); -//int memchr(const void *src_void, int c, size_t length); -//int memcmp(const void *m1, const void *m2, size_t n); -//int memcpy(void *dst0, const void *src0, size_t len0); -//int memmove(void *dst_void, const void *src_void, size_t length); -//int memset(void *m, int c, size_t n); -//char * strcat(char *s1, const char *s2); -//char * strchr(const char *s1, int i); -//int strcmp(const char *s1, const char *s2); -//char * strcpy(char *dst0, const char *src0); -//int strlen(const char *str); -//char * strncat(char *s1, const char *s2, size_t n); -//int strncmp(const char *s1, const char *s2, size_t n); -//char * strncpy(char *dst0, const char *src0, size_t count); -//char * strstr(const char *searchee, const char *lookfor); -//char * strsep(char **source_ptr, const char *delim); -//char * strtok(char *s, const char *delim); +#if 0 +int snprintf(char *str, size_t size, const char *fmt, ...); +int sprintf(char *str, const char *fmt, ...); +int printf(const char *fmt, ...); +int vprintf(const char * fmt, __VALIST param); +int vsnprintf(char *str, size_t size, const char *fmt, __VALIST param); +int vfprintf(FILE *fp, const char *fmt0, va_list ap); +void * memchr(const void * src_void , int c , size_t length); +int memcmp(const void *m1, const void *m2, size_t n); +void * memcpy(void *dst0, const void *src0, size_t len0); +void * memmove(void *dst_void, const void *src_void, size_t length); +void * memset(void *m, int c, size_t n); +char * strcat(char *s1, const char *s2); +char * strchr(const char *s1, int i); +int strcmp(const char *s1, const char *s2); +char * strcpy(char *dst0, const char *src0); +size_t strlen(const char *str); +char * strncat(char *s1, const char *s2, size_t n); +int strncmp(const char *s1, const char *s2, size_t n); +char * strncpy(char *dst0, const char *src0, size_t count); +char * strstr(const char *searchee, const char *lookfor); +char * strsep(char **source_ptr, const char *delim); +char * strtok(char *s, const char *delim); +int sscanf(const char *buf, const char *fmt, ...); +char toupper(char ch); +int _stricmp (const char *s1, const char *s2); +unsigned long long __aeabi_llsr(unsigned long long val, unsigned int shift); +#endif // Extern Calls: // extern int init_rom_libgloss_ram_map(_DWORD) // extern int _rom_mallocr_init_v1_00(void) @@ -68,7 +73,6 @@ extern int libc_has_init; //------------------------------------------------------------------------- // Function - //----- snprintf() int snprintf(char *str, size_t size, const char *fmt, ...) { va_list args; @@ -104,6 +108,7 @@ int snprintf(char *str, size_t size, const char *fmt, ...) { return result; } +#ifndef ENAC_FLOAT //----- sprintf() int sprintf(char *str, const char *fmt, ...) { FILE f; @@ -145,17 +150,17 @@ int printf(const char *fmt, ...) { //----- vprintf() int vprintf(const char * fmt, __VALIST param) { -//int vprintf(const char *fmt, void *param) { #if CHECK_LIBC_INIT if (!libc_has_init) { rtl_libc_init(); } -#endif +#endif int result = __rtl_vfprintf_r_v1_00(_rtl_impure_ptr, _rtl_impure_ptr->_stdout, fmt, param); __rtl_fflush_r_v1_00(_rtl_impure_ptr, _rtl_impure_ptr->_stdout); return result; } +#endif // ENAC_FLOAT //----- vsnprintf() int vsnprintf(char *str, size_t size, const char *fmt, __VALIST param) { @@ -310,3 +315,226 @@ unsigned long long __aeabi_llsr(unsigned long long val, unsigned int shift) return ((unsigned long long)hi << 32) | lo; } + +/* +#undef __VFP_FP__ + +#if defined(__VFP_FP__) +typedef long __jmp_buf[10 + 8 + 1]; // d8-d15 fpu + fpscr +#else +typedef long __jmp_buf[10]; +#endif + +int setjmp(__jmp_buf buf) __attribute__ ((noinline)); +int setjmp(__jmp_buf buf) +{ + register void * r0 __asm__("r0") = buf; + __asm__( + "mov %%ip, %%sp\n" + "stmia %[store]!, {%%r4-%%r9, %%sl, %%fp, %%ip, %%lr}\n" +#if defined(__VFP_FP__) + "vstmia %[store]!, {%%d8-%%d15}\n" + "vmrs %%r1, fpscr\n" + "str %%r1, [%[store]], #4\n" +#endif + "mov.w %r0, #0\n" + : : [store] "r" (r0) :); +} + +void longjmp(__jmp_buf buf, long value) __attribute__((noreturn)); +void longjmp(__jmp_buf buf, long value) +{ + __asm__( + "ldmia %[load]!, {%%r4-%%r9, %%sl, %%fp, %%ip, %%lr}\n" +#if defined(__VFP_FP__) + "vldmia %[load]!, {%%d8-%%d15}\n" + "ldr %%r0, [%[load]], #4\n" + "vmsr fpscr, %%r0\n" +#endif + "mov %%sp, %%ip\n" + "movs %%r0, %%r1\n" + "it eq\n" + "moveq %%r0, #1\n" + "bx lr\n" + : : [load] "r" (buf), [value] "r" (value):); + __builtin_unreachable(); +} +*/ + +extern __attribute__ ((long_call)) unsigned int Rand(void); + +unsigned int rand(void) +{ + return Rand(); +} + + + +//----- rtl_dtoi() +int __aeabi_dtoi(double d) +{ + return __rtl_dtoi_v1_00(d); +} + +//----- __aeabi_dtoui() +int __aeabi_dtoui(double d) +{ + return __rtl_dtoui_v1_00(d); +} + +//----- __aeabi_i2f() +float __aeabi_i2f(int val) +{ + return __rtl_itof_v1_00(val); +} + +//----- __aeabi_i2d() +int __aeabi_i2d(int val) +{ + return __rtl_itod_v1_00(val); +} + +//----- __aeabi_ui2f() +float __aeabi_ui2f(unsigned int val) +{ + return __rtl_uitof_v1_00(val); +} + +//----- __aeabi_ui2d() +int __aeabi_ui2d(unsigned int val) +{ + return __rtl_uitod_v1_00(val); +} + +//----- __aeabi_itoa() +char * __aeabi_itoa(int value, char *string, int radix) +{ + return (char *)__rtl_ltoa_v1_00(value, string, radix); +} + +//----- __aeabi_ltoa() +char * __aeabi_ltoa(int value, char *string, int radix) +{ + return (char *)__rtl_ltoa_v1_00(value, string, radix); +} + +//----- __aeabi_utoa() +char * __aeabi_utoa(unsigned int value, char *string, int radix) +{ + return (char *)__rtl_ultoa_v1_00(value, string, radix); +} + +//----- __aeabi_ultoa() +char * __aeabi_ultoa(unsigned int value, char *string, int radix) +{ + return (char *)__rtl_ultoa_v1_00(value, string, radix); +} + +//----- __aeabi_ftol() +int __aeabi_ftol(float f) +{ + return __rtl_ftol_v1_00(f); +} + +//----- __aeabi_ftod() +int __aeabi_ftod(float f) +{ + return __rtl_ftod_v1_00(f); +} + +//----- __aeabi_dtof() +float __aeabi_dtof(double d) +{ + return __rtl_dtof_v1_00(d); +} + +//----- __aeabi_fadd() +float __aeabi_fadd(float a, float b) +{ + return __rtl_fadd_v1_00(a, b); +} + +//----- __aeabi_fsub() +float __aeabi_fsub(float a, float b) +{ + return __rtl_fsub_v1_00(a, b); +} + +//----- __aeabi_fmul() +float __aeabi_fmul(float a, float b) +{ + return __rtl_fmul_v1_00(a, b); +} + +//----- __aeabi_fdiv() +float __aeabi_fdiv(float a, float b) +{ + return __rtl_fdiv_v1_00(a, b); +} + +//----- __aeabi_dadd() +int __aeabi_dadd(double a, double b) +{ + return __rtl_dadd_v1_00(a, b); +} + +//----- __aeabi_dsub() +int __aeabi_dsub(double a, double b) +{ + return __rtl_dsub_v1_00(a, b); +} + +//----- __aeabi_dmul() +int __aeabi_dmul(double a, double b) +{ + return __rtl_dmul_v1_00(a, b); +} + +//----- __aeabi_ddiv() +int __aeabi_ddiv(double a, double b) +{ + return __rtl_ddiv_v1_00(a, b); +} + +//----- __aeabi_dcmpeq() +int __aeabi_dcmpeq(double a, double b) +{ + return __rtl_dcmpeq_v1_00(a, b); +} + +//----- __aeabi_dcmplt() +int __aeabi_dcmplt(double a, double b) +{ + return __rtl_dcmplt_v1_00(a, b); +} + +//----- __aeabi_dcmple() +int __aeabi_dcmple(double a, double b) +{ + return __rtl_dcmple_v1_00(a, b); +} + +//----- __aeabi_dcmpgt() +int __aeabi_dcmpgt(double a, double b) +{ + return __rtl_dcmpgt_v1_00(a, b); +} + +//----- __aeabi_fcmplt() +int __aeabi_fcmplt(float a, float b) +{ + return __rtl_fcmplt_v1_00(a, b); +} + +//----- __aeabi_fcmpgt() +int __aeabi_fcmpgt(float a, float b) +{ + return __rtl_fcmpgt_v1_00(a, b); +} + + + + + + + diff --git a/build/bin/ota.bin b/build/bin/ota.bin index ba9de97..514ff01 100644 Binary files a/build/bin/ota.bin and b/build/bin/ota.bin differ diff --git a/build/bin/ram_2.bin b/build/bin/ram_2.bin index 3322889..cfabfa3 100644 Binary files a/build/bin/ram_2.bin and b/build/bin/ram_2.bin differ diff --git a/build/bin/ram_2.ns.bin b/build/bin/ram_2.ns.bin index 8dd1524..3490326 100644 Binary files a/build/bin/ram_2.ns.bin and b/build/bin/ram_2.ns.bin differ diff --git a/build/bin/ram_2.p.bin b/build/bin/ram_2.p.bin index bcf8cfc..db370c1 100644 Binary files a/build/bin/ram_2.p.bin and b/build/bin/ram_2.p.bin differ diff --git a/build/bin/ram_all.bin b/build/bin/ram_all.bin index 3ebfe04..665f37d 100644 Binary files a/build/bin/ram_all.bin and b/build/bin/ram_all.bin differ diff --git a/build/obj/build.nmap b/build/obj/build.nmap index 0f5b9a0..6628a2d 100644 --- a/build/obj/build.nmap +++ b/build/obj/build.nmap @@ -1,24 +1,6 @@ U __aeabi_d2iz - U __aeabi_dadd - U __aeabi_dcmpge - U __aeabi_dcmpgt - U __aeabi_dcmple - U __aeabi_dcmplt - U __aeabi_dmul - U __aeabi_dsub U __aeabi_f2d - U __aeabi_fdiv - U __aeabi_i2d - U __aeabi_i2f - U __aeabi_ui2f - U __ctype_ptr__ - U cmd_update - U floor - U free - U localtime - U malloc U mfl_code_to_length - U pow 00000000 A __vectors_table 00000000 D __rom_image_end__ 00000000 D __rom_image_start__ @@ -911,19 +893,19 @@ 10008758 T rtl_strncmp 10008760 T rtl_strncpy 10008768 T rtl_strsep -10008770 T memcpy -10008778 T memset -10008780 T sscanf -1000879a T __aeabi_llsr -100087b0 T ram_libgloss_close -100087c0 T ram_libgloss_fstat -100087e0 T ram_libgloss_isatty -100087ec T ram_libgloss_lseek -100087fc T ram_libgloss_read -1000880c T ram_libgloss_sbrk -10008828 T ram_libgloss_write -10008848 T ram_libgloss_open -10008884 T init_rom_libgloss_ram_map +10008770 T ram_libgloss_close +10008780 T ram_libgloss_fstat +100087a0 T ram_libgloss_isatty +100087ac T ram_libgloss_lseek +100087bc T ram_libgloss_read +100087cc T ram_libgloss_sbrk +100087e8 T ram_libgloss_write +10008808 T ram_libgloss_open +10008844 T init_rom_libgloss_ram_map +1000888c T memcpy +10008894 T memset +1000889c T sscanf +100088b6 T __aeabi_llsr 100088cc T wlan_init_done_callback 100088d0 T read_wifi_cfg 10008918 T write_wifi_cfg @@ -934,2267 +916,2267 @@ 100089c0 T StartStDHCPClient 10008a4c T _wifi_on 10008af8 T _LwIP_Init -10008ba4 T translate_rtw_security -10008bc8 T show_wifi_ap_ip -10008bfc T wifi_run_ap -10008d1c T show_wifi_st_ip -10008d50 T wifi_run_st -10008e0c T wifi_run -10008ef8 T wifi_init_thrd -10008f54 T fATWR -10008f70 T show_wifi_st_cfg -10008fc0 T fATPN -10009090 T show_wifi_ap_cfg -100090fc T fATPA -100091d8 T show_wifi_cfg -10009238 T fATWI -1000934c t mp3_cfg_read -100093ac T tskmad -100095c8 T render_sample_block -1000963c T set_dac_sample_rate -10009680 T getIpForHost -100096a4 T openConn -100097c8 T http_head_read -10009900 T tskreader -10009ac8 T connect_close -10009af0 T connect_start -10009b90 T fATWS -10009c70 T ShowMemInfo -10009c9c T main -10009cf4 T fATST -10009d64 T fATSD -10009d6c T fATSW -10009d74 T fATDS -10009d98 T print_hex_dump -10009dc8 T dump_bytes -10009e5c T fATSB -10009e94 T print_udp_pcb -10009f00 T print_tcp_pcb -10009fd8 T fATLW -10009fe8 T RamFifoClose -1000a044 T RamFifoInit -1000a198 T RamFifoRead -1000a254 T RamFifoWrite -1000a308 T RamFifoFill -1000a334 T RamFifoFree -1000a348 T RamFifoLen -1000a354 t decode_header -1000a4c4 T mad_header_init -1000a4f0 T mad_frame_finish -1000a508 T mad_header_decode -1000a7a4 T mad_frame_decode -1000a828 T mad_frame_mute -1000a872 T mad_frame_init -1000a890 t III_requantize -1000a90c t III_aliasreduce -1000a974 t fastsdct -1000aaac t III_imdct_l -1000aec4 t III_imdct_s -1000b018 t III_overlap -1000b042 t III_freqinver -1000b08c t III_decode -1000c0a8 T mad_layer_III -1000c50c T mad_bit_init -1000c518 T mad_bit_length -1000c530 T mad_bit_nextbyte -1000c53c T mad_bit_skip -1000c56c T mad_bit_read -1000c5d8 T mad_bit_crc -1000c6cc t scale -1000c6d8 t dct32 -1000cf6c t synth_half -1000d3b0 t synth_full -1000d804 T mad_synth_mute -1000d83c T mad_synth_init -1000d860 T mad_synth_frame -1000d8f4 t scale_rational -1000d968 T mad_timer_set -1000da50 T mad_stream_init -1000da82 T mad_stream_finish -1000da94 T mad_stream_buffer -1000daa8 T mad_stream_sync -1000daf0 T mad_stream_errorstr -1000dc4c t i2s_test_tx_complete -1000dc64 T i2sClose -1000dcf0 T i2sInit -1000de64 T i2sSetRate -1000deec T i2sPushPWMSamples -1000e054 T SystemCoreClockUpdate -1000e068 W console_help -1000e0a8 T GetArgvRam -1000e160 T get_eap_phase -1000e16c T get_eap_method -1000e178 T eap_autoreconnect_hdl -1000e17c t wifi_no_network_hdl -1000e194 t wifi_ap_sta_disassoc_hdl -1000e198 t wifi_handshake_done_hdl -1000e1b4 t wifi_disconn_hdl -1000e21c t wifi_connected_hdl -1000e250 t wifi_connect_local -1000e364 T wifi_autoreconnect_hdl -1000e3a0 t wifi_ap_sta_assoc_hdl -1000e3a2 T wifi_rx_beacon_hdl -1000e3a4 T wifi_connect -1000e628 t wifi_autoreconnect_thread -1000e690 T wifi_set_country -1000e69c T wifi_off -1000e708 T wifi_start_ap -1000e7e8 T wifi_get_setting -1000e898 T wifi_show_setting -1000e95c T wifi_config_autoreconnect -1000e980 T wifi_indication -1000e9bc T wifi_reg_event_handler -1000ea10 T wifi_unreg_event_handler -1000ea54 T init_event_callback_list -1000ea64 T promisc_deinit -1000ea68 T promisc_recv_func -1000ea6c T promisc_set -1000ea70 T is_promisc_enabled -1000ea7a T iw_ioctl -1000ea96 T wext_get_ssid -1000eae0 T wext_set_ssid -1000eb14 T is_broadcast_ether_addr -1000eb36 T wext_set_auth_param -1000eb64 T wext_set_key_ext -1000ec64 T wext_get_enc_ext -1000ecc6 T wext_set_passphrase -1000ecfa T wext_get_passphrase -1000ed2a T wext_set_mode -1000ed4e T wext_get_mode -1000ed78 T wext_set_ap_ssid -1000edac T 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rtw_joinbss_cmd -1001d04a T rtw_disassoc_cmd -1001d098 T rtw_setstakey_cmd -1001d188 T rtw_clearstakey_cmd -1001d228 T rtw_dynamic_chk_wk_cmd -1001d27a T rtw_set_chplan_cmd -1001d2fa T dynamic_chk_wk_hdl -1001d3c2 T lps_ctrl_wk_hdl -1001d426 T rtw_lps_ctrl_wk_cmd -1001d490 T rtw_sitesurvey_cmd -1001d558 T rpt_timer_setting_wk_hdl -1001d56c T rtw_ps_cmd -1001d5c8 T rtw_chk_hi_queue_cmd -1001d61c T rtw_drvextra_cmd_hdl -1001d6f8 t rtw_free_mlme_ie_data -1001d710 T rtw_init_mlme_timer -1001d76c T rtw_del_mlme_timer -1001d78c T reconnect_timer_hdl -1001d82c T _rtw_init_mlme_priv -1001d8ae T rtw_mfree_mlme_priv_lock -1001d8ca T rtw_free_mlme_priv_ie_data -1001d902 T _rtw_free_mlme_priv -1001d92a T _rtw_alloc_network -1001d97a T _rtw_free_network -1001d9da T _rtw_free_network_nolock -1001da00 T _rtw_find_network -1001da3c T _rtw_free_network_queue -1001da84 T rtw_if_up -1001daa4 T rtw_get_capability_from_ie -1001daa8 T rtw_get_capability -1001dac2 T rtw_get_beacon_interval_from_ie -1001dac6 T rtw_init_mlme_priv -1001dade T rtw_free_mlme_priv -1001dae2 T rtw_free_network_queue -1001dae6 T rtw_is_same_ibss -1001dafc T is_same_network -1001db60 T update_network -1001dbfa T rtw_update_scanned_network -1001dd0c T rtw_add_network -1001dd4a T rtw_survey_event_callback -1001ddf6 T rtw_dummy_event_callback -1001ddf8 T rtw_free_assoc_resources -1001dec2 T rtw_indicate_connect -1001ded2 T rtw_indicate_disconnect -1001def4 T rtw_indicate_scan_done -1001def8 T rtw_joinbss_event_callback -1001df16 T search_max_mac_id -1001df5e T rtw_stassoc_hw_rpt -1001df96 T rtw_stassoc_event_callback -1001dfc4 T rtw_stadel_event_callback -1001e06a T _rtw_join_timeout_handler -1001e0f4 T rtw_join_timeout_handler -1001e14c T rtw_scan_timeout_handler -1001e17c T _rtw_scan_timeout_handler -1001e180 T rtw_dynamic_check_timer_handlder -1001e1d8 T _dynamic_check_timer_handlder -1001e21c T rtw_select_and_join_from_scanned_queue -1001e2f0 T rtw_surveydone_event_callback -1001e408 T rtw_set_auth -1001e458 T rtw_set_key -1001e51a T rtw_restruct_wmm_ie -1001e580 T rtw_restruct_sec_ie -1001e5ec T rtw_joinbss_reset -1001e5fc T rtw_restructure_ht_ie -1001e6dc T rtw_update_ht_cap -1001e766 T rtw_joinbss_event_prehandle -1001e992 T rtw_linked_check -1001e9ae T rtw_buddy_adapter_up -1001e9e6 T check_buddy_fwstate -1001ea04 t get_da -1001ea24 t get_sa -1001ea4e T OnAction -1001ea60 T DoReserved -1001ea64 t _mgt_dispatcher.isra.2 -1001eab0 T rtw_is_channel_set_contains_channel -1001ead2 T init_hw_mlme_ext -1001eae8 T init_channel_set -1001eb80 T free_mlme_ext_priv -1001eba8 T mgt_dispatcher -1001ec30 T alloc_mgtxmitframe -1001ec68 T update_mgnt_tx_rate -1001ec6e T update_mgntframe_attrib -1001ecca T rtw_build_mgnt_frame -1001ed20 T dump_mgntframe -1001ed3a T rtw_send_mgnt -1001ed58 t issue_action_BSSCoexistPacket -1001ef64 T update_hidden_ssid -1001efb8 T issue_beacon -1001f1d0 T issue_probersp -1001f460 T OnProbeReq -1001f528 T issue_probereq -1001f6e0 T issue_auth -1001f948 T OnAuth -1001fbec T issue_asocrsp -1001fe60 T issue_assocreq -1002019c T issue_nulldata -10020286 T issue_qos_nulldata -100203b8 T issue_deauth -100204a0 T issue_action_BA -1002071c T OnAction_back -100207ea T collect_bss_info -10020a1c T start_clnt_auth -10020aac T start_clnt_assoc -10020ae0 T OnAuthClient -10020bc0 T report_scan_result_one -10020d80 T add_site_survey -10020f06 T report_survey_event -10021144 T OnProbeRsp -10021178 T report_surveydone_event -100211dc T report_join_res -1002124c T OnAssocRsp -10021398 T report_del_sta_event -1002142a T receive_disconnect -10021480 T OnBeacon -10021608 T OnDeAuth -10021760 T OnDisassoc -100218d0 T report_add_sta_event -10021944 T OnAssocReq -10021f34 T rtw_port_switch_chk -10021fb8 T update_sta_info -10022038 T mlmeext_sta_del_event_callback -100220b8 T _linked_info_dump -1002211a T _linked_rx_signal_strehgth_display -10022154 T linked_status_chk -100223c8 T survey_timer_hdl -100224a8 T _survey_timer_hdl -100224ac T link_timer_hdl -1002252a T _link_timer_hdl -1002252e T addba_timer_hdl -1002254e T NULL_hdl -10022552 T setopmode_hdl -10022598 T disconnect_hdl -10022644 T setauth_hdl -10022654 T setkey_hdl -100226ac T set_stakey_hdl -100227b0 T set_tx_beacon_cmd -10022824 T mlme_evt_hdl -10022870 T tx_beacon_hdl -1002292a T check_buddy_mlmeinfo_state -10022944 T site_survey -10022b14 T sitesurvey_cmd_hdl -10022c22 T concurrent_chk_start_clnt_join -10022cb8 T start_clnt_join -10022d8c T join_cmd_hdl -10022eb0 T concurrent_chk_joinbss_done -10023078 T mlmeext_joinbss_event_callback -100231b4 T set_chplan_hdl -100231d0 T init_mlme_ext_timer -1002322c T init_mlme_ext_priv -10023368 t get_hdr_bssid -10023390 t filter_packet -10023418 t promisc_get_encrypt -1002346a t promisc_info_get -1002350e t promisc_set_enable -100235aa T _promisc_deinit -100235fc T _promisc_recv_func -10023b48 T _promisc_set -10023bd8 T _is_promisc_enabled -10023bf0 t SetEAPOL_KEYIV -10023c8e t ToDrv_SetPTK -10023d36 t Message_ReplayCounter_OC2LI.isra.2 -10023d64 t Message_SmallerEqualReplayCounter.isra.4 -10023d96 t Message_setReplayCounter.isra.5 -10023db4 t INCLargeInteger -10023dd4 t INCOctet16_INTEGER -10023e1c t INCOctet32_INTEGER -10023e7c t ToDrv_DisconnectSTA -10023f40 t CheckMIC.constprop.14 -10023fc0 t CalcMIC.constprop.15 -10024020 T DecWPA2KeyData -100240d4 T DecGTK -10024190 T ToDrv_SetGTK -10024220 T init_wpa_sta_info -1002430c T SendEAPOL -100249c4 T ClientSendEAPOL -10024eac t ResendTimeout -10024f34 T EAPOLKeyRecvd -100250ac T ClientEAPOLKeyRecvd -1002546c T psk_derive -10025520 T psk_init -10025610 T psk_strip_rsn_pairwise -10025690 T psk_strip_wpa_pairwise -10025710 T tkip_send_mic_failure_report -10025884 T pwr_state_check_handler -10025888 T ips_enter -10025930 T ips_leave -10025a48 T rtw_pwr_unassociated_idle -10025a92 T rtw_ps_processor -10025aea T PS_RDY_CHECK -10025b52 T rtw_set_ps_mode -10025bc0 T LPS_RF_ON_check -10025c16 T LPS_Enter -10025c84 T LPS_Leave -10025cc0 T LeaveAllPowerSaveMode -10025cd0 T rtw_init_pwrctrl_priv -10025da4 T rtw_free_pwrctrl_priv -10025db8 T _rtw_pwr_wakeup -10025e94 T rtw_pm_set_lps -10025edc T rtw_pm_set_ips -10025f20 T rtw_pm_set_tdma_param -10025f3c T rtw_pm_set_lps_dtim -10025f48 T rtw_pm_get_lps_dtim -10025f54 t recvframe_pull -10025f76 t recvframe_pull_tail -10025f98 T rtw_signal_stat_timer_hdl -10026036 T _rtw_init_sta_recv_priv -10026054 T _rtw_init_recv_priv -100260fc T rtw_mfree_recv_priv_lock -10026130 T _rtw_alloc_recvframe -10026162 T rtw_alloc_recvframe -10026188 T rtw_free_recvframe -10026224 T _rtw_enqueue_recvframe -10026250 T rtw_enqueue_recvframe -1002627a T rtw_free_recvframe_queue -100262b2 T rtw_free_uc_swdec_pending_queue -100262da T _rtw_free_recv_priv -1002630a T rtw_free_buf_pending_queue -1002630e T recvframe_chkmic -1002640c T decryptor -100264a8 T portctrl -1002651e T recv_decache -1002654c T process_pwrbit_data -1002658c T process_wmmps_data -10026614 T count_rx_stats -10026688 T sta2sta_data_frame -100267c4 T ap2sta_data_frame -100268f0 T sta2ap_data_frame -10026978 T validate_recv_ctrl_frame -10026b12 T validate_recv_data_frame -10026d6c T wlanhdr_to_ethhdr -10026ea8 T recvframe_defrag -10026f52 T recvframe_chk_defrag -10027008 T validate_recv_mgnt_frame -10027044 T validate_recv_frame -1002710c T recv_indicatepkt_reorder -1002712e T process_recv_indicatepkts -10027186 T recv_func_prehandle -100271ae T recv_func_posthandle -10027212 T recv_func -1002729c T rtw_recv_entry -100272cc T rtw_recv_tasklet -10027324 T rtw_wep_encrypt -1002736a T rtw_wep_decrypt -100273b0 T rtw_tkip_encrypt -1002741c T rtw_tkip_decrypt -10027488 T rtw_aes_encrypt -100274f4 T rtw_aes_decrypt -10027558 T rtw_init_sec_priv -100275ca T rtw_free_sec_priv -100275ea t wifi_mac_hash -10027614 T _addba_timer_hdl -10027618 T _rtw_init_stainfo -10027692 T _rtw_init_sta_priv -1002777a T _rtw_free_sta_xmit_priv_lock -100277a6 T rtw_mfree_stainfo -100277d2 T rtw_mfree_sta_priv_lock -10027808 T _rtw_free_sta_priv -10027828 T init_addba_retry_timer -10027850 T rtw_alloc_stainfo -1002791a T rtw_free_stainfo -10027abc T rtw_get_stainfo -10027b38 T rtw_init_bcmc_stainfo -10027b68 T rtw_get_bcmc_stainfo -10027b8c T rtw_free_all_stainfo -10027be6 T cckrates_included -10027c0e T cckratesonly_included -10027c36 T networktype_to_raid_ex -10027c94 T judge_network_type -10027ce4 T ratetbl_val_2wifirate -10027cf8 T is_basicrate -10027d24 T ratetbl2rateset -10027d68 T get_rate_set -10027d92 T UpdateBrateTbl -10027dc4 T UpdateBrateTblForSoftAP -10027df8 T Save_DM_Func_Flag -10027e0e T Restore_DM_Func_Flag -10027e24 T Switch_DM_Func -10027e40 T Set_MSR -10027e64 T set_opmode -10027ea8 T SelectChannel -10027edc T SetBWMode -10027f18 T set_channel_bwmode -10027f6e T get_my_bssid -10027f72 T get_beacon_interval -10027f90 T is_client_associated_to_ap -10027fa8 T is_client_associated_to_ibss -10027fc4 T is_IBSS_empty -10027fe6 T decide_wait_for_beacon_timeout -10028002 T invalidate_cam_all -1002800a T write_cam -10028080 T clear_cam_entry -100280ae T flush_all_cam_entry -1002810c T WMM_param_handler -10028132 T WMMOnAssocRsp -10028200 T HT_caps_handler -100282a0 T HT_info_handler -100282c4 T HTOnAssocRsp -100282fc T ERP_IE_handler -10028318 T VCS_update -1002836a T rtw_check_bcn_info -1002857a T update_beacon_info -100285d0 T is_ap_in_tkip -10028648 T wifirate2_ratetbl_inx -100286b4 T update_basic_rate -100286e2 T update_supported_rate -1002870c T update_MCS_rate -10028718 T support_short_GI -10028746 T get_highest_rate_idx -10028760 T Update_RA_Entry -10028768 T set_sta_rate -10028770 T update_tx_basic_rate -100287c8 T check_assoc_AP -100288bc T update_IOT_info -1002891a T update_capinfo -10028998 T update_wireless_mode -10028a38 T update_bmc_sta_support_rate -10028a60 T update_TSF -10028a72 T correct_TSF -10028a7a t _init_txservq -10028a90 t set_qos -10028ae0 T _rtw_init_sta_xmit_priv -10028b26 T rtw_mfree_xmit_priv_lock -10028b72 T qos_acm -10028bac T xmitframe_addmic -10028d0a T xmitframe_swencrypt -10028d36 T rtw_make_wlanhdr -10028f16 T rtw_txframes_pending -10028f52 T rtw_txframes_sta_ac_pending -10028f88 T rtw_txframes_update_attrib_vcs_info -10029028 T rtw_put_snap -1002906c T rtw_update_protection -100290b2 T rtw_count_tx_stats -10029102 T rtw_free_xmitbuf_ext -10029144 T rtw_alloc_xmitframe -1002919c T rtw_free_xmitframe -100291ee T rtw_free_xmitframe_queue -1002922c T rtw_get_sta_pending -1002926c T rtw_xmit_classifier -100292d2 T rtw_xmitframe_enqueue -100292e0 T rtw_alloc_hwxmits -1002933a T rtw_free_hwxmits -10029350 T _rtw_free_xmit_priv -1002941c T rtw_init_hwxmits -10029434 T _rtw_init_xmit_priv -100295ec T rtw_get_ff_hwaddr -10029600 T xmitframe_enqueue_for_sleeping_sta -100297c0 t dequeue_xmitframes_to_sleeping_queue -10029816 T stop_sta_xmit -100298fe T wakeup_sta_to_xmit -10029b14 T xmit_delivery_enabled_frames -10029c30 T rtw_xmit_tasklet -10029c88 T rtw_xmit_mgnt -10029c8c T rtw_xmit -10029fb6 T rtw_sctx_done_err -10029fc2 T rtw_alloc_xmitbuf -1002a01c T rtw_free_xmitbuf -1002a08e T rtw_alloc_xmitbuf_ext -1002a114 T rtw_sctx_done -1002a11a t rtl8195a_free_rx_ring -1002a128 t bus_write32 -1002a184 t bus_write16 -1002a1e0 t bus_write8 -1002a23c t bus_read32 -1002a296 t bus_read16 -1002a2f2 t bus_read8 -1002a34e t rtl8195a_free_tx_ring -1002a3dc T rtl8195a_init_desc_ring -1002a51c T rtl8195a_free_desc_ring -1002a538 T rtl8195a_reset_desc_ring -1002a5ce T InitLxDmaRtl8195a -1002a730 T rtl8195a_check_txdesc_closed -1002a7a8 t rtl8195a_tx_isr -1002a88c T InterruptRecognized8195a -1002a91c T InitInterrupt8195a -1002a93c T EnableDMA8195a -1002a964 T EnableInterrupt8195a -1002a9a4 T DisableDMA8195a -1002a9b0 T DisableInterrupt8195a -1002a9c8 T UpdateInterruptMask8195a -1002aa2a T CheckRxTgRtl8195a -1002aa64 T rtl8192ee_check_rxdesc_remain -1002aa94 T rtl8195a_recv_tasklet -1002ada8 T rtl8195a_tx_int_handler -1002add4 T InterruptHandle8195a -1002b048 T rtl8195a_xmit_tasklet -1002b070 T lxbus_set_intf_ops -1002b0b0 t GetTxBufDesc -1002b0fa t UpdateFirstTxbdtoXmitBuf.isra.3 -1002b12c t check_nic_enough_desc.isra.4 -1002b17c T rtl8195ab_init_xmit_priv -1002b18a T rtl8195ab_free_xmit_priv -1002b192 T GetDmaTxbdIdx -1002b1ae T rtl8195a_enqueue_xmitbuf -1002b1d2 T rtl8195a_dequeue_xmitbuf -1002b1f6 T SetTxbdForLxDMARtl8195ab -1002b276 T UpdateTxbdHostIndex -1002b2b4 T rtw_dump_xframe -1002b486 T check_tx_desc_resource -1002b4c0 T rtw_dequeue_xframe -1002b554 T rtw_xmitframe_coalesce -1002b808 T rtl8195ab_xmitframe_resume -1002b8fe T rtl8195ab_mgnt_xmit -1002b93a T rtl8195ab_hal_xmit -1002ba48 t Hal_GetEfuseDefinition -1002ba78 t ResumeTxBeacon -1002babc T UpdateHalRAMask8195A -1002bc54 T HalLittleWifiMCUThreadRtl8195a -1002bca8 T HalCheckInReqStateThreadRtl8195a -1002bcf4 T HalTDMAChangeStateThreadRtl8195a -1002bd40 t rtl8195a_read_chip_version -1002bdb4 t Hal_EfuseWordEnableDataWrite -1002bff8 t Hal_EfusePowerSwitch -1002c00c t rtl8195a_free_hal_data -1002c026 t StopTxBeacon -1002c070 T SetHalODMVar8195A -1002c128 T rtl8195a_start_thread -1002c190 T rtl8195a_stop_thread -1002c1b4 t Hal_ReadEFuse -1002c324 T GetHalODMVar8195A -1002c338 t rtw_flash_map_update.part.12 -1002c3d8 t rtw_flash_map_erase -1002c41c t Hal_EfusePgPacketWrite -1002c698 t Hal_EfuseGetCurrentSize -1002c778 t rtw_flash_map_write -1002c946 T rtl8195a_InitBeaconParameters -1002c9b6 T _InitBurstPktLen_8195AB -1002c9c0 T rtl8195a_set_hal_ops -1002caa0 T rtl8195a_init_default_value -1002caa2 T rtl8195a_InitLLTTable -1002caec T Hal_GetChnlGroup8195A -1002cb28 T rtw_config_map_read -1002cc14 T rtw_config_map_write -1002ccc0 T Hal_InitPGData -1002cd1e T Hal_EfuseParseIDCode -1002cd36 T Hal_ReadPowerValueFromPROM_8195A -1002cdd4 T Hal_EfuseParseTxPowerInfo_8195A -1002ce6c T Hal_EfuseParseEEPROMVer_8195A -1002ce82 T Hal_EfuseParsePackageType_8195A -1002ceec T Hal_EfuseParseChnlPlan_8195A -1002cf1c T Hal_EfuseParseCustomerID_8195A -1002cf32 T Hal_EfuseParseXtal_8195A -1002cf4a T Hal_EfuseParseThermalMeter_8195A -1002cf72 T Hal_ReadRFGainOffset -1002cfc2 T BWMapping_8195A -1002cfe2 T SCMapping_8195A -1002d00a T rtl8195a_update_txdesc -1002d2da T rtl8195a_fill_fake_txdesc -1002d398 T SetHwReg8195A -1002e058 T GetHwReg8195A -1002e0ec T SetHalDefVar8195A -1002e1cc T GetHalDefVar8195A -1002e1f0 T PHY_QueryBBReg_8195A_Safe -1002e21c T PHY_SetBBReg_8195A_Safe -1002e248 t phy_RFSerialRead_8195A -1002e2fc T PHY_QueryRFReg_8195A -1002e314 T PHY_SetRFReg_8195A -1002e36c T PHY_MACConfig8195A -1002e386 T PHY_BBConfig8195A -1002e496 T PHY_RFConfig8195A -1002e49a T PHY_SetTxPowerIndex_8195A -1002e5a4 T phy_TxPwrAdjInPercentage -1002e5e4 T PHY_GetTxPowerIndex_8195A -1002e6d4 T PHY_SetTxPowerLevel8195A -1002e6da T phy_SpurCalibration_8195A -1002e992 T phy_SetRegBW_8195A -1002e9d0 T phy_PostSetBwMode8195A -1002eb2c T phy_SwChnl8195A -1002ebd4 T phy_SwChnlAndSetBwMode8195A -1002ec24 T PHY_HandleSwChnlAndSetBW8195A -1002ecd4 T PHY_SetBWMode8195A -1002ecf6 T PHY_SwChnl8195A -1002ed10 T PHY_SetSwChnlBWMode8195A -1002ed2e t HalTimerEnable -1002ed40 T InitTDMATimer -1002ed68 T ChangeStateByTDMA -1002ed78 T GetMinRateInRRSR -1002edac T CheckInReqState -1002edbc T InitCheckStateTimer -1002edec T InitGTimer1ms -1002ee38 T DeInitGTimer1ms -1002ee80 T ChangeTransmiteRate -1002eebc T PowerBitSetting -1002ef38 T ChkandChangePS -1002ef9c T IssueRsvdPagePacketSetting -1002f010 T IssuePSPoll -1002f03c T WaitTxStateMachineOk -1002f090 T IssueNullData -1002f120 T PsCloseRF -1002f154 T PsOpenRF -1002f184 T ChkTxQueueIsEmpty -1002f19c T InitPS -1002f20c T ConfigListenBeaconPeriod -1002f230 T PS_S2_Condition_Match -1002f264 T PS_S4_Condition_Match -1002f2e0 T PS_32K_Condition_Match -1002f31c T PS_S2ToS3ToS0State -1002f384 T PS_S2ToS0State -1002f3a0 T PS_S3ToS2orS0State -1002f3d0 T PS_S0ToS1ToS2State -1002f42c T PS_S1ToS0orS2State -1002f45c T PS_S2ToS4State -1002f4a8 T PS_S0ToS6State -1002f4c8 T PS_S6ToS0State -1002f4e0 T CheckTSFIsStable -1002f530 T WaitHWStateReady -1002f540 T SysClkDown -1002f5b0 T SysClkUp -1002f5fc T ResetPSParm -1002f670 T PS_S4ToS2State -1002f694 T SleepTo32K -1002f6f4 T Change_PS_State -1002f8a0 T Legacy_PS_Setting -1002f914 T PSModeSetting -1002f9b8 T ChangePSStateByRPWM -1002f9fc T ChangeTDMAState -1002fb1c T TDMAChangeStateTask -1002fb46 T EnterPS -1002fb68 T SetSmartPSTimer -1002fba4 T GTimer7Handle -1002fc00 T SmartPS2InitTimerAndToGetRxPkt -1002fc3c T PS_OnBeacon -1002fcec T PSBcnEarlyProcess -1002fda8 T PSMtiBcnEarlyProcess -1002fe54 T PSRxBcnProcess -1002ffa4 T TxPktInPSOn -1002ffe2 T PsBcnToProcess -1003009c T GTimer6Handle -100300e8 T RPWMProcess -10030124 T PSSetMode -1003019c T SpeRPT -100302bc T ISR_BcnEarly -10030328 T ISR_MtiBcnEarly -1003035c T ISR_RxBcn -10030378 T ISR_RxBCMD1 -100303a8 T ISR_RxBCMD0 -100303fc T ISR_RxUCMD1 -1003043a T ISR_RxUCMD0 -10030476 T ISR_TxPktIn -10030488 T ISR_TXCCX -1003048c T H2CHDL_SetPwrMode -100305b4 T CheckInReqStateTask -100305fa T HalGetNullTxRpt -10030618 T ISR_TBTT -10030690 T H2CHDL_BcnIgnoreEDCCA -100306a0 T PMUInitial -100306f0 T PMUTask -100307fc T PHY_RF6052SetBandwidth8195A -10030840 T PHY_RF6052_Config8195A -100308f8 t process_rssi -1003092e T rtl8195a_query_rx_desc_status -100309de T rtl8195a_query_rx_phy_status -10030b36 T hal_com_get_channel_plan -10030b6a T HAL_IsLegalChannel -10030b88 T MRateToHwRate -10030b9c T HwRateToMRate -10030bb0 T HalSetBrateCfg -10030c5c T Hal_MappingOutPipe -10030c78 T hal_init_macaddr -10030ca4 T hw_var_port_switch -10030f2c T SetHwReg -10030f36 T GetHwReg -10030f38 T switch_power_saving_mode -10030f7c T rtw_bb_rf_gain_offset -10030fc4 T PHY_GetRateValuesOfTxPowerByRate -1003115c T PHY_StoreTxPowerByRateNew -100311f8 T PHY_InitTxPowerByRate -10031210 T PHY_StoreTxPowerByRate -10031228 T PHY_GetTxPowerIndexBase -100312c8 T PHY_GetTxPowerTrackingOffset -100312f4 T PHY_GetRateIndexOfTxPowerByRate -10031308 T PHY_GetTxPowerByRate -10031368 T phy_StoreTxPowerByRateBase -100313b4 T PHY_SetTxPowerByRate -100313f0 T phy_ConvertTxPowerByRateInDbmToRelativeValues -100314f0 T PHY_TxPowerByRateConfiguration -10031502 T PHY_SetTxPowerIndexByRateArray -10031540 T PHY_SetTxPowerIndexByRateSection -100315a4 T PHY_SetTxPowerLevelByPath -100315da T phy_GetWorldWideLimit -10031606 T PHY_GetTxPowerLimit -10031730 T PHY_ConvertTxPowerLimitToPowerIndex -10031880 T PHY_InitTxPowerLimit -100318c8 T PHY_SetTxPowerLimit -10031944 T PHY_GetTxPowerIndex -10031954 T rtw_hal_chip_configure -1003196a T rtw_hal_read_chip_info -10031980 T rtw_hal_read_chip_version -10031996 T rtw_hal_def_value_init -100319ac T rtw_hal_free_data -100319c2 T rtw_hal_dm_init -100319d8 T rtw_hal_dm_deinit -100319ee T rtw_hal_init -10031a18 T rtw_hal_deinit -10031a32 T rtw_hal_set_hwreg -10031a40 T rtw_hal_get_hwreg -10031a4e T rtw_hal_set_def_var -10031a60 T rtw_hal_get_def_var -10031a72 T rtw_hal_set_odm_var -10031a80 T rtw_hal_get_odm_var -10031a8e T rtw_hal_enable_interrupt -10031ab0 T rtw_hal_disable_interrupt -10031ad2 T rtw_hal_inirp_init -10031ae4 T rtw_hal_inirp_deinit -10031af6 T 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skb_pull -100354fe T skb_copy -10035526 T rtw_remainder_len -10035532 T _rtw_open_pktfile -10035544 T _rtw_pktfile_read -10035572 T rtw_set_tx_chksum_offload -10035574 T rtw_os_xmit_resource_alloc -1003557e T rtw_os_xmit_resource_free -10035580 T rtw_os_pkt_complete -10035588 T rtw_os_xmit_complete -1003559a T rtw_os_xmit_schedule -100355d6 T rtw_xmit_entry -10035622 T rtw_alloc_etherdev_with_old_priv -10035638 T rtw_alloc_etherdev -10035664 T rtw_free_netdev -10035684 T timer_wrapper -100356d8 T alloc_etherdev -10035734 T free_netdev -1003574e T dev_alloc_name -10035758 T init_timer_wrapper -10035778 T deinit_timer_wrapper -100357c4 T init_timer -1003587c T mod_timer -1003595c T cancel_timer_ex -100359a4 T del_timer_sync -10035a08 T rtw_init_timer -10035a10 T rtw_set_timer -10035a14 T rtw_cancel_timer -10035a1e T rtw_del_timer -10035a24 T rltk_get_idx_bydev -10035a34 T rltk_wlan_init -10035abc T rltk_wlan_deinit -10035b80 T rltk_wlan_start -10035bb4 T rltk_wlan_check_isup -10035bc4 T rltk_wlan_tx_inc -10035bd8 T rltk_wlan_tx_dec -10035bec T rltk_wlan_get_recv_skb -10035bfc T rltk_wlan_alloc_skb -10035c3c T rltk_wlan_send_skb -10035c70 T rltk_netif_rx -10035d1c T rltk_set_sta_num -10035d20 T rltk_set_tx_power_percentage -10035d54 T rltk_wlan_control -10035de8 T rltk_wlan_running -10035e00 T rltk_wlan_handshake_done -10035e34 T rltk_wlan_is_connected_to_ap -10035e78 T Efuse_PowerSwitch -10035e84 T Efuse_GetCurrentSize -10035e90 T Efuse_CalculateWordCnts -10035eb4 T EFUSE_GetEfuseDefinition -10035ec8 T efuse_OneByteRead -10035efc T efuse_OneByteWrite -10035f30 T Efuse_PgPacketWrite -10035f44 T efuse_WordEnableDataRead -10035f76 T Efuse_WordEnableDataWrite -10035f8a T efuse_GetCurrentSize -10035fb2 T rtw_efuse_map_read -10036014 T rtw_efuse_map_write -10036194 T rtw_macaddr_cfg -10036258 T rtw_get_cipher_info -100362d2 T rtw_get_bcn_info -100363a2 T rtw_init_default_value -10036410 T rtw_cancel_all_timer -1003647a T rtw_free_drv_sw -100364f0 T rtw_reset_drv_sw -1003654c T rtw_init_drv_sw -100365d4 T rtw_start_drv_threads -10036690 T rtw_stop_drv_threads -100366c4 T rtw_read8 -100366d2 T rtw_read16 -100366e0 T rtw_read32 -100366ee T rtw_write8 -100366fc T rtw_write16 -1003670a T rtw_write32 -10036718 T rtw_do_join -100367bc T rtw_set_802_11_bssid -10036940 T rtw_set_802_11_ssid -10036a48 T rtw_set_802_11_infrastructure_mode -10036aea T rtw_set_802_11_bssid_list_scan -10036b3a T rtw_set_802_11_authentication_mode -10036b5c T rtw_set_802_11_add_wep -10036bbc T ODM_InitRAInfo -10036c5c T InitialRateUpdate -10036d5c T RateUp_search_RateMask -10036d8e T RateDown_search_RateMask -10036de0 T StartRateByRSSI -10036e0a T RateUpRAM8195A -10036e9e T RateDownTrying -10036edc T TryDone -10036f74 T RateDownStepRAM8195A -10037014 T RateDecisionRAM8195A -100370f8 T ArfrRefresh -10037300 T H2CHDL_Set_MACID_Config -100373c4 T PHY_DM_RA_SetRSSI_8195A -100373f2 t CheckPositive.isra.0 -100374d4 T ODM_ReadAndConfig_MP_8195A_AGC_TAB -1003754c T ODM_ReadAndConfig_MP_8195A_PHY_REG -100375c4 T ODM_GetVersion_MP_8195A_PHY_REG -100375c8 T ODM_ReadAndConfig_MP_8195A_PHY_REG_PG -100375fc T odm_ConfigRFReg_8195A -10037634 T odm_ConfigRF_RadioA_8195A -10037644 T odm_ConfigMAC_8195A -10037648 T odm_ConfigBB_AGC_8195A -10037658 T odm_ConfigBB_PHY_REG_PG_8195A -10037686 T odm_ConfigBB_PHY_8195A -100376ce T odm_ConfigBB_TXPWR_LMT_8195A -100376f4 T ODM_CmnInfoInit -100377e8 T ODM_CmnInfoHook -1003788c T ODM_CmnInfoPtrArrayHook -1003789c T ODM_CmnInfoUpdate -1003796c T odm_CommonInfoSelfInit -100379e0 T ODM_DMInit -10037a2e T odm_CommonInfoSelfUpdate -10037a80 T ODM_DMWatchdog -10037aec T PhyDM_Get_Structure -10037b10 T Phydm_CheckAdaptivity -10037b3e T Phydm_NHMCounterStatisticsInit -10037bb4 T Phydm_SetEDCCAThreshold -10037bec T Phydm_MACEDCCAState -10037c2a T Phydm_AdaptivityInit -10037d08 T Phydm_Adaptivity -10037e28 T ODM_CfoTrackingInit -10037e52 T ODM_CfoTracking -10037e72 T ODM_ParsingCFO -10037ea4 T ODM_InitDebugSetting -10037eb8 T ODM_Write_DIG -10037f58 T odm_ForbiddenIGICheck -10037fea T ODM_Write_CCK_CCA_Thres -10038024 T odm_DIGInit -100380be T odm_DigAbort -100380e0 T odm_DIGbyRSSI_LPS -1003818c T odm_FAThresholdCheck -100381b8 T odm_DIG -10038418 T odm_FalseAlarmCounterStatistics -10038444 T odm_CCKPacketDetectionThresh -1003849c T odm_RxPhyStatus8195A_Parsing -100385a0 T odm_Process_RSSIForDM_8195A -100386e2 T ODM_PhyStatusQuery_8195A -1003870e T ODM_PhyStatusQuery -10038712 T ODM_ConfigRFWithHeaderFile -10038730 T ODM_ConfigRFWithTxPwrTrackHeaderFile -10038762 T ODM_ConfigBBWithHeaderFile -1003878a T ODM_ConfigMACWithHeaderFile -1003879c T ODM_Read1Byte -100387a2 T ODM_Read4Byte -100387a8 T ODM_Write1Byte -100387ae T ODM_Write2Byte -100387b4 T ODM_Write4Byte -100387ba T ODM_SetMACReg -100387c0 T ODM_SetBBReg -100387c6 T ODM_GetBBReg -100387cc T ODM_SetRFReg -100387d2 T ODM_GetRFReg -100387d8 T ODM_MoveMemory -100387e2 T ODM_delay_ms -100387e6 T ODM_delay_us -100387ec T getSwingIndex -10038844 T odm_TXPowerTrackingThermalMeterInit -100388f6 T odm_TXPowerTrackingInit -100388fa T odm_TXPowerTrackingCheckIOT -1003892e T ODM_TXPowerTrackingCheck -1003893c T odm_RSSIMonitorInit -10038944 T ODM_RAPostActionOnAssoc -1003894c T odm_RSSIMonitorCheckIOT -10038a20 T odm_RSSIMonitorCheck -10038a34 T odm_RateAdaptiveMaskInit -10038a5c T ODM_RAStateCheck -10038a9e T odm_RefreshRateAdaptiveMaskIOT -10038aee T odm_RefreshRateAdaptiveMask -10038b04 T ODM_Get_Rate_Bitmap -10038bf4 t _ReadEfuseInfo8195a -10038cbc t rtl8195a_interface_configure -10038cf0 t rtl8195a_hal_deinit -10038d2c T _InitPowerOn -10038dac t ReadAdapterInfo8195a -10038ddc T _InitDriverInfoSize -10038de6 T _InitNetworkType -10038e08 T _InitWMACSetting -10038e78 T _InitAdaptiveCtrl -10038ebc T _InitEDCA -10038f38 T _InitRateFallback -10038f7c T _InitRetryFunction -10038fa8 T _InitOperationMode -10038ff0 T _InitInterrupt -10039030 t rtl8195a_hal_init -10039308 T rtl8195ab_set_hal_ops -100393e0 T FillH2CCmd8195A -10039400 T CheckFwRsvdPageContent -10039402 T rtl8195a_set_FwRsvdPage_cmd -1003940c T rtl8195a_set_FwMediaStatusRpt_cmd -10039438 T rtl8195a_set_FwMacIdConfig_cmd -100394f8 T rtl8195a_set_FwPwrMode_cmd -10039588 T rtl8195a_download_rsvd_page -10039890 T rtl8195a_set_FwJoinBssRpt_cmd -1003989a T rtl8195a_Add_RateATid -100398ec T rtw_rpt_h_addr -10039938 T rtw_txrpt_read8 -10039956 T rtw_txrpt_write8 -1003997a T rtw_ratemask_read8 -10039998 T rtw_ratemask_write8 -100399bc T ReadRateMask8 -100399c6 T WriteRateMask8 -100399ca T ReadTxrpt8 -100399d4 T WriteTxrpt8 -100399d8 T ResetTxrpt -10039a10 T PsuseTxrpt -10039a30 T CheckMaxMacidNum -10039a68 T GetMediaStatusCommon -10039a82 T GetTxrptStatistic -10039b38 T rtl8195a_InitHalDm -10039c5c T rtl8195a_HalDmWatchDog -10039d40 T rtl8195a_init_dm_priv -10039e18 T rtl8195a_deinit_dm_priv -10039e1a T MediaConnection -10039e38 T MediaDisconnection -10039e58 T RATaskEnable -10039e82 T SetMediaStatus -10039ec0 T H2CHDL_JoinInfo -10039ef8 T H2CHDL_SetRsvdPage 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V max_skb_buf_num +1004d4ac D rom_e_rtw_msgp_str_ +1004d688 D ARFB_table +1004d6c7 D TRYING_NECESSARY_idx +1004d6db D DROPING_NECESSARY +1004d6ef D PER_RATE_UP +1004d703 D PER_RATE_DOWN +1004d718 V Array_MP_8195A_PHY_REG_PG +1004d7a8 D Array_MP_8195A_AGC_TAB +1004d9b8 D Array_MP_8195A_PHY_REG +1004e030 D rtl8195A_card_disable_flow +1004e0d0 D rtl8195A_card_enable_flow +1004e170 D Array_MP_8195A_MAC_REG +1004e478 D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_TFBGA96_8195A +1004e498 D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_TFBGA96_8195A +1004e4b8 D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_QFN48_8195A +1004e4d6 D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_QFN56_8195A +1004e4f4 D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_QFN48_8195A +1004e512 D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN56_8195A +1004e530 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_TFBGA96_8195A +1004e550 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_QFN56_8195A +1004e56e D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_QFN48_8195A +1004e58c D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_QFN56_8195A +1004e5ac D Array_MP_8195A_RadioA +1004eb74 D gDeltaSwingTableXtal_MP_P_TxXtalTrack_8195A +1004eb92 D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_TFBGA96_8195A +1004ebb2 D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN48_8195A +1004ebd0 D .ram.bss$$Base +1004ebd0 D __bss_start__ +1004ebd0 D __data_end__ +1004ebd0 D __ram_image2_text_end__ +1004ebd0 d skbdata_list +1004ebd8 V skb_data_pool +10051fd8 d ucIdleTaskHeap +100520f0 D HalI2SOpSAL +1005212c D SYSAdapte +10052130 D PwrAdapter +100523bc D libc_has_init +100523c0 d rheap_end +100523c4 D wifi_run_mode +100523c8 D wlan_st_netifn +100523cc d event_init.21283 +100523d0 d sampCntAdd +100523d4 d sampCnt +100523d8 D mp3_serv +1005245a D tskreader_enable +1005245c D readBuf +10052460 D tskmad_enable +10052464 d bufUnderrunCt +10052468 d oldRate +1005246c d sampDelCnt +10052470 D pbuf_fifo +10052474 D pi2s +1005247c D I2sTxSema +10052480 D eap_method +10052481 D eap_phase +10052484 d param.21256 +1005249c D rtw_join_status +100524a0 D wifi_mode +100524a4 d join_user_data +100524a8 d event_callback_list +10052628 D paff_array +100526a0 D lwip_init_done +100526a4 D xnetif +10052724 d s_aliases.7444 +10052728 d s_hostent.7443 +1005273c d s_hostent_addr.7445 +10052740 D h_errno +10052744 d s_phostent_addr.7446 +1005274c d select_cb_list +10052750 d sockets +10052810 d select_cb_ctr +10052814 d mbox +10052818 d tcpip_init_done_arg +1005281c d tcpip_init_done +10052820 d allsystems +10052824 d allrouters +10052828 d igmp_group_list +1005282c D current_header +10052830 d ip_id +10052834 D current_iphdr_src +10052838 D current_iphdr_dest +1005283c D current_netif +10052840 d str.6809 +10052850 d reassdatagrams +10052854 d ip_reass_pbufcount +10052856 D dhcp_rx_options_given +10052860 d xid.7759 +10052864 D dhcp_rx_options_val +1005288c d dns_seqno +10052890 d dns_table +10052cf0 d dns_servers +10052cf8 d dns_payload_buffer +10052efc d dns_pcb +10052f00 d dns_payload +10052f04 d tcpip_tcp_timer_active +10052f08 d next_timeout +10052f0c D netif_list +10052f10 D netif_default +10052f14 d netif_num +10052f15 D pbuf_free_ooseq_pending +10052f18 d raw_pcbs +10052f1c D tcp_active_pcbs_changed +10052f20 D tcp_ticks +10052f24 d tcp_timer +10052f28 D tcp_listen_pcbs +10052f2c D tcp_active_pcbs +10052f30 d tcp_timer_ctr +10052f34 D tcp_tw_pcbs +10052f38 D tcp_tmp_pcb +10052f3c D tcp_bound_pcbs +10052f40 d seqno +10052f44 d tcplen +10052f48 d ackno +10052f4c d flags +10052f4d d recv_flags +10052f50 d tcphdr +10052f54 d recv_data +10052f58 d inseg +10052f6c D tcp_input_pcb +10052f70 D udp_pcbs +10052f74 d etharp_cached_entry +10052f78 d arp_table +10053040 D lwip_tickless_used +10053044 d s_timeoutlist +10053074 d s_nextthread +10053078 d dhcps_ip_table_semaphore +1005307c d dhcps_send_broadcast_address +10053080 D dhcps_ip4addr_pool_end +10053081 d dhcp_client_ethernet_address +10053094 d dhcps_subnet_broadcast +10053098 d bound_client_ethernet_address +100530a8 d ip_table +100530c8 d dhcps_pcb +100530cc d dhcp_message_total_options_lenth +100530d0 d dhcps_local_address +100530d4 d dhcps_netif +100530d8 d client_request_ip +100530dc d dhcps_allocated_client_address +100530e0 d dhcps_local_mask +100530e4 d dhcps_local_gateway +100530e8 d dhcps_network_id +100530ec D dhcps_ip4addr_pool_start +100530f0 d dhcp_message_repository +100530f4 D ext_upper +100530f8 d xFreeBytesRemaining +100530fc d ext_free +10053100 D ext_lower +10053104 d pxEnd +10053108 d xStart +10053110 d xMinimumEverFreeBytesRemaining +10053114 d ulTimerCountsForOneTick +10053118 d ulStoppedTimerCompensation +1005311c d xMaximumPossibleSuppressedTicks +10053120 d xPendingReadyList +10053134 d uxTopReadyPriority +10053138 d uxTasksDeleted +1005313c d xTickCount +10053140 d pxReadyTasksLists +1005321c d pxOverflowDelayedTaskList +10053220 d xTasksWaitingTermination +10053234 d pxDelayedTaskList +10053238 d xSchedulerRunning +1005323c d ulTaskSwitchedInTime +10053240 D pxCurrentTCB +10053244 d uxPendedTicks +10053248 d xSuspendedTaskList +1005325c d uxCurrentNumberOfTasks +10053260 d ulDeltaTotalRunTime +10053264 d xDelayedTaskList2 +10053278 d xDelayedTaskList1 +1005328c d uxTaskNumber +10053290 d xYieldPending +10053294 d uxSchedulerSuspended +10053298 d xNumOfOverflows +1005329c d pxCurrentTimerList +100532a0 d xActiveTimerList1 +100532b4 d xActiveTimerList2 +100532c8 d xLastTime.5284 +100532cc d xTimerQueue +100532d0 d pxOverflowTimerList +100532d4 d xTimerTaskHandle +100532d8 d device_mutex +100532e4 d mutex_init +100532e8 d uxSavedInterruptStatus +100532ec D min_free_heap_size +100532f0 d g_heap_inited +100532f4 d tcm_lock +100532f8 D g_tcm_heap +100532fc D flashobj +10053308 D fspic_isinit +1005330c D WDGAdapter +10053348 d last_acquire_wakelock_time +100533c8 D post_sleep_callback +10053448 D pre_sleep_callback +100534c8 D reserve_pll +100534cc d sys_sleep_time +100534d0 d hold_wakelock_time +10053550 D missing_tick +10053554 D Timer2To7HandlerData +1005356c D auto_reconnect_running +10053570 D p_wlan_autoreconnect_hdl +10053574 D mac_monitor_callback +10053578 D mf_list_head +1005357c d pscan_retry_cnt.21430 +10053580 D promisc_callback_all +10053584 D promisc_sema +10053588 D promisc_callback +1005358c D psk_essid +100535d4 D psk_passphrase +10053656 D psk_passphrase64 +10053697 D wpa_global_PSK +100536e7 d RFC1042_OUI +100536ec d rx_ring_pool +100557cc d stop_report_count.20629 +100557cd D bCheckStateTIMER +100557d0 d WifiMcuCmdBitMap.20974 +100557d4 D p_wlan_init_done_callback +100557d8 D rtw_power_percentage_idx +100557dc D p_wlan_uart_adapter_callback +100557e0 D rtw_adaptivity_en +100557e4 D p_wlan_mgmt_filter +100557e8 D rtw_initmac +100557ec D rtw_adaptivity_th_l2h_ini +100557f0 d drvpriv +10055804 D skbbuf_used_num +10055808 V skb_pool +100559c0 D skbdata_used_num +100559c4 d wrapper_skbbuf_list +100559cc D max_skbdata_used_num +100559d0 D max_skbbuf_used_num +100559d4 d skb_fail_count +100559d8 D timer_table +100559e0 D rltk_wlan_info +10055a10 d timer_used_num +10055a14 D max_timer_used_num +10055a18 D Noisy_State +10055a1c D pExportWlanIrqSemaphore +10055a20 D gDeltaSwingTableXtal_MP_N_TxXtalTrack_8195A +10055a3e D .ram.bss$$Limit +10055a3e D __bss_end__ +10055a40 B __ram_heap2_start__ 10070000 A __ram_heap2_end__ 1fff0000 D __ram_tcm_start__ 1fff0000 D __tcm_heap_start__ diff --git a/sdkset.mk b/sdkset.mk index 0b5bf49..8201901 100644 --- a/sdkset.mk +++ b/sdkset.mk @@ -1,6 +1,6 @@ # FLAGS # ------------------------------------------------------------------- -CFLAGS = -DM3 -DCONFIG_PLATFORM_8195A -DGCC_ARMCM3 -DARDUINO_SDK -DF_CPU=166666666L +CFLAGS = -DM3 -DCONFIG_PLATFORM_8195A -DGCC_ARMCM3 -DARDUINO_SDK -DF_CPU=166666666L -DNDEBUG CFLAGS += -mcpu=cortex-m3 -mthumb -g2 -Os -std=gnu99 CFLAGS += -fno-common -fmessage-length=0 -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-short-enums -fsigned-char CFLAGS += -w -Wno-pointer-sign @@ -97,8 +97,9 @@ SRC_C += sdk/component/soc/realtek/8195a/cmsis/device/system_8195a.c #DRAM_C += sdk/component/common/api/at_cmd/atcmd_wifi.c #SRC_C += sdk/component/common/api/at_cmd/log_service.c #SRC_C += sdk/component/soc/realtek/8195a/misc/driver/low_level_io.c -#SRC_C += sdk/component/soc/realtek/8195a/misc/driver/rtl_consol.c +#console new/old SRC_C += sdk/component/soc/realtek/8195a/misc/driver/rtl_console_new.c +#SRC_C += sdk/component/soc/realtek/8195a/misc/driver/rtl_consol.c #network - api SRC_C += sdk/component/common/api/wifi/rtw_wpa_supplicant/wpa_supplicant/wifi_eap_config.c @@ -114,13 +115,13 @@ SRC_C += sdk/component/common/api/lwip_netconf.c #network - app #SRC_C += sdk/component/common/utilities/ssl_client.c #SRC_C += sdk/component/common/utilities/ssl_client_ext.c -SRC_C += sdk/component/common/utilities/tcptest.c -SRC_C += sdk/component/common/utilities/uart_ymodem.c +#SRC_C += sdk/component/common/utilities/tcptest.c +#SRC_C += sdk/component/common/utilities/uart_ymodem.c #SRC_C += sdk/component/common/utilities/update.c #SRC_C += sdk/component/common/application/uart_adapter/uart_adapter.c SRC_C += sdk/component/common/api/network/src/wlan_network.c -SRC_C += sdk/component/common/api/wifi_interactive_mode.c -SRC_C += sdk/component/common/api/network/src/ping_test.c +#SRC_C += sdk/component/common/api/wifi_interactive_mode.c +#SRC_C += sdk/component/common/api/network/src/ping_test.c #network - lwip SRC_C += sdk/component/common/network/lwip/lwip_v1.4.1/src/api/api_lib.c @@ -160,7 +161,7 @@ SRC_C += sdk/component/common/network/lwip/lwip_v1.4.1/port/realtek/freertos/eth SRC_C += sdk/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c SRC_C += sdk/component/common/network/lwip/lwip_v1.4.1/port/realtek/freertos/sys_arch.c SRC_C += sdk/component/common/network/dhcp/dhcps.c -SRC_C += sdk/component/common/network/sntp/sntp.c +#SRC_C += sdk/component/common/network/sntp/sntp.c #network - mdns #SRC_C += sdk/component/common/network/mDNS/mDNSPlatform.c @@ -330,11 +331,11 @@ DRAM_C += sdk/component/common/network/ssl/ssl_ram_map/ssl_ram_map.c #DRAM_C += sdk/component/common/application/wigadget/wigadget.c #utilities -SRC_C += sdk/component/common/utilities/cJSON.c -SRC_C += sdk/component/common/utilities/http_client.c -SRC_C += sdk/component/common/utilities/uart_socket.c -SRC_C += sdk/component/common/utilities/webserver.c -SRC_C += sdk/component/common/utilities/xml.c +#SRC_C += sdk/component/common/utilities/cJSON.c +#SRC_C += sdk/component/common/utilities/http_client.c +#SRC_C += sdk/component/common/utilities/uart_socket.c +#SRC_C += sdk/component/common/utilities/webserver.c +#SRC_C += sdk/component/common/utilities/xml.c #utilities - FatFS SRC_C += sdk/component/common/file_system/fatfs/fatfs_ext/src/ff_driver.c @@ -344,10 +345,7 @@ SRC_C += sdk/component/common/file_system/fatfs/r0.10c/src/option/ccsbcs.c SRC_C += sdk/component/common/file_system/fatfs/disk_if/src/sdcard.c #utilities - xmodem update -SRC_C += sdk/component/common/application/xmodem/uart_fw_update.c -#user -#SRC_C += project/src/main.c - +#SRC_C += sdk/component/common/application/xmodem/uart_fw_update.c # ------------------------------------------------------------------- # My Source file list # ------------------------------------------------------------------- @@ -366,10 +364,13 @@ ADD_SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_misc.c ADD_SRC_C += sdk/component/soc/realtek/8195a/fwlib/ram_lib/startup.c ADD_SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/flash_eep.c ADD_SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_libc.c -ADD_SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_pvvx_libc.c ADD_SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_libgloss_retarget.c ADD_SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/rtl_eabi_cast_ram.c ADD_SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/rtl_math_ram.c +#if +- nostdlib.. +ADD_SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_pvvx_libc.c +#if c_printf() float +#ADD_SRC_C += sdk/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/c_stdio.c # ------------------------------------------------------------------- # SAMPLES # -------------------------------------------------------------------