stash

.build.yml

@@ -19,11 +19,12 @@ steps:
   - make firmware -j$(nproc)
 
 - name: pcb
-  image: setsoft/kicad_auto
+  image: setsoft/kicad_auto:ki6
   commands:
   - apt update
   - apt install -y make zip
-  - make pcb -j$(nproc)
+#  - make pcb -j$(nproc) BOARD=fiatlux
+  - make pcb -j$(nproc) BOARD=fiatlux_cc48
 
 - name: case
   image: debian:sid
@@ -58,10 +59,11 @@ steps:
     files: 
       - firmware/firmware/fiatlux.bin
       - firmware/otaflash.py
-      - pcb/pcb.zip
+#      - pcb/fiatlux_pcb.zip
+      - pcb/fiatlux_cc48_pcb.zip
     checksum:
       - sha512
       - md5
-    title: buildtest
+    title: fiatlux
   when:
     event: tag

Makefile

@@ -1,5 +1,5 @@
 
-.PHONY: firmware flash firmware_docker case pcb
+.PHONY: firmware flash firmware_docker flash_docker case pcb
 
 all: firmware case pcb
 
@@ -19,6 +19,10 @@ clean:
 	+@make -C firmware clean
 	+@make -C pcb clean
 
+flash_docker:
+	sh -c "docker build -t fiatlux_firmware_env docker/firmware"
+	sh -c "docker run --volume "$$(pwd)"/firmware:/app/firmware --device=/dev/ttyUSB0 fiatlux_firmware_env make -C firmware flash"
+
 firmware_docker:
 	sh -c "docker build -t fiatlux_firmware_env docker/firmware"
 	sh -c "docker run --volume "$$(pwd)"/firmware:/app/firmware fiatlux_firmware_env make -C firmware html all"

docker/firmware/Dockerfile

@@ -1,12 +1,33 @@
 # syntax=docker/dockerfile:1
-FROM debian:sid
-RUN apt update && apt install -y make bash gawk g++ gcc libc6-dev flex bison automake autoconf gperf texinfo wget git bzip2 help2man libtool libtool-bin unrar-free unzip ncurses-dev libexpat-dev python-dev python3; mkdir /app; chown 1000:1000 /app; cd /app; useradd user;
-USER 1000
-RUN cd app; git clone --recursive https://github.com/SuperHouse/esp-open-rtos.git modules/rtos; git clone --recursive https://github.com/pfalcon/esp-open-sdk.git modules/sdk
-RUN cd app; sed -i 's/GNU bash, version (3\\\.\[1-9\]|4)/GNU bash, version (3.[1-9]|4|5)/g' modules/sdk/crosstool-NG/configure.ac; mkdir -p modules/sdk/crosstool-NG/.build/tarballs; wget https://github.com/libexpat/libexpat/releases/download/R_2_1_0/expat-2.1.0.tar.gz -O modules/sdk/crosstool-NG/.build/tarballs/expat-2.1.0.tar.gz
-RUN cd app/modules/sdk; export CT_EXPERIMENTAL=y; export CT_ALLOW_BUILD_AS_ROOT=y; export CT_ALLOW_BUILD_AS_ROOT_SURE=y; make standalone=y -j$(nproc); wget -N https://raw.githubusercontent.com/espressif/esptool/master/esptool.py -O xtensa-lx106-elf/bin/esptool.py
+#FROM debian:sid
+#RUN apt update && apt install -y make bash gawk g++ gcc libc6-dev flex bison automake autoconf gperf texinfo wget git bzip2 help2man libtool libtool-bin unrar-free unzip ncurses-dev python2-dev python2 && mkdir /app && chown 1000:1000 /app && cd /app && useradd user && usermod -aG dialout user
+#USER 1000
+#RUN cd app && git clone --recursive https://github.com/SuperHouse/esp-open-rtos.git modules/rtos && git clone --recursive https://github.com/pfalcon/esp-open-sdk.git modules/sdk
+#RUN cd app  \
+#    && sed -i 's/GNU bash, version (3\\\.\[1-9\]|4)/GNU bash, version (3.[1-9]|4|5)/g' modules/sdk/crosstool-NG/configure.ac \
+#    && mkdir -p modules/sdk/crosstool-NG/.build/tarballs  \
+#    && wget https://github.com/libexpat/libexpat/releases/download/R_2_1_0/expat-2.1.0.tar.gz -O modules/sdk/crosstool-NG/.build/tarballs/expat-2.1.0.tar.gz  \
+#    && wget https://libisl.sourceforge.io/isl-0.14.tar.bz2 -O modules/sdk/crosstool-NG/.build/tarballs/isl-0.14.tar.bz2 \
+#    && wget https://ftp.gnu.org/gnu/gcc/gcc-4.8.5/gcc-4.8.5.tar.bz2 -O modules/sdk/crosstool-NG/.build/tarballs/gcc-4.8.5.tar.bz2
+#RUN cd app  \
+#    && bzip2 -d modules/sdk/crosstool-NG/.build/tarballs/gcc-4.8.5.tar.bz2\
+#    && tar -xf modules/sdk/crosstool-NG/.build/tarballs/gcc-4.8.5.tar gcc-4.8.5/gcc/reload1.c \
+#    && sed -i 's/spill_indirect_levels++;/spill_indirect_levels = 1;/g' gcc-4.8.5/gcc/reload1.c \
+#    && tar -uf modules/sdk/crosstool-NG/.build/tarballs/gcc-4.8.5.tar gcc-4.8.5/gcc/reload1.c \
+#    && bzip2 -z1 modules/sdk/crosstool-NG/.build/tarballs/gcc-4.8.5.tar \
+#    && rm -rf gcc-4.8.5 modules/sdk/crosstool-NG/.build/tarballs/gcc-4.8.5.tar
+#RUN cd app/modules/sdk && export CT_EXPERIMENTAL=y && export CT_ALLOW_BUILD_AS_ROOT=y && export CT_ALLOW_BUILD_AS_ROOT_SURE=y && make standalone=n -j$(nproc) || cat /app/modules/sdk/crosstool-NG/build.log #&& wget -N https://raw.githubusercontent.com/espressif/esptool/master/esptool.py -O xtensa-lx106-elf/bin/esptool.py
+#RUN cd app && tar -xf modules/sdk/crosstool-NG/.build/tarballs/gcc-4.8.5.tar.bz2 gcc-4.8.5/gcc/reload1.c && grep spill_indirect_levels gcc-4.8.5/gcc/reload1.c
+#USER 0
+#RUN apt remove --purge -y python2 && apt autoremove --purge -y && apt install -y python3 python3-serial esptool
+#RUN apt install -y --reinstall python-is-python3
+#USER 1000
+#WORKDIR /app
+#ENV PATH=/app/modules/sdk/xtensa-lx106-elf/bin:$PATH
+
+FROM docker-repo.service.intern.lab.or.it:5000/fiatlux-build-env
 USER 0
-RUN apt remove --purge -y python2 && apt autoremove --purge -y && apt install -y python3 python3-serial
+RUN apt remove --purge -y python2 && apt autoremove --purge -y && apt install -y python3 python3-serial esptool
 RUN apt install -y --reinstall python-is-python3
 USER 1000
 WORKDIR /app

docker/firmware/stm8/Dockerfile

@@ -0,0 +1,2 @@
+FROM debian:sid
+#steps taken from http://www.colecovision.eu/llvm+sdcc/

firmware/lux.cpp

@@ -4,6 +4,7 @@
 
 #include "lux.h"
 
+#include <stdio.h>
 #include <string.h>
 #include <FreeRTOS.h>
 #include <task.h>
@@ -13,20 +14,58 @@
 const int signal_led_pin = 2;
 
 const int cs0 = 15;
-const int gpio4 = 4;
-const int gpio5 = 5;
+const int nint_pin = 4;
+const int init_pin = 5;
+
 
 extern "C" void signal_led(bool state) {
     gpio_write(signal_led_pin, !state);
 }
 
+void int_to_hex(uint8_t i, char buf[2]) {
+    uint8_t hex_charset[] = "0123456789ABCDEF";
+    buf[0] = hex_charset[i >> 4];
+    buf[1] = hex_charset[i & 0x0F];
+}
+
+const gpio_inttype_t int_type = GPIO_INTTYPE_EDGE_NEG;
+
+void gpio_intr_handler(uint8_t gpio_num)
+{
+    uint8_t buf[2];
+    spi_read(1, 0x0000, buf, 2, SPI_8BIT);
+    char hex[5] = {0};
+    int_to_hex(buf[0], hex);
+    int_to_hex(buf[1], hex + 2);
+    hex[4] = '\0';
+    printf("lux_task output: %s\n", hex);
+}
+
 extern "C" void lux_task(void *pvParameters) {
 
     gpio_enable(signal_led_pin, GPIO_OUTPUT);
     gpio_enable(cs0, GPIO_OUTPUT);
-    gpio_enable(gpio4, GPIO_OUTPUT);
-    gpio_enable(gpio5, GPIO_OUTPUT);
+    gpio_enable(nint_pin, GPIO_INPUT);
+    gpio_enable(init_pin, GPIO_OUTPUT);
     spi_init(1, SPI_MODE0, SPI_FREQ_DIV_1M, 1, SPI_BIG_ENDIAN, 1);
 
+    gpio_set_interrupt(nint_pin, int_type, gpio_intr_handler);
+
+    uint8_t charset[] = "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
+
+    uint8_t cnt = 0;
+
+    while(1) {
+        uint8_t out[2];
+        out[1] = 0x0F;
+        out[0] = charset[cnt++];
+        spi_transfer_16(1, *(uint16_t*)out);
+
+
+        vTaskDelay(2000/portTICK_PERIOD_MS);
+        cnt %= sizeof(charset);
+    }
+
+
     vTaskDelete(nullptr);
 }

pcb/.gitignore

@@ -16,6 +16,7 @@ _autosave-*
 *-save.pro
 *-save.kicad_pcb
 fp-info-cache
+*-backups/
 
 # Netlist files (exported from Eeschema)
 *.net

pcb/Makefile

@@ -1,52 +1,54 @@
-.NOTPARALLEL:  gen/fab/fiatlux-F_Cu.gbr gen/fab/fiatlux-B_Cu.gbr gen/fab/fiatlux-F_Mask.gbr gen/fab/fiatlux-B_Mask.gbr  gen/fab/fiatlux-F_Paste.gbr gen/fab/fiatlux-B_Paste.gbr gen/fab/fiatlux-F_SilkS.gbr gen/fab/fiatlux-B_SilkS.gbr
+.NOTPARALLEL:  gen/fab/$(BOARD)-F_Cu.gbr gen/fab/$(BOARD)-B_Cu.gbr gen/fab/$(BOARD)-F_Mask.gbr gen/fab/$(BOARD)-B_Mask.gbr  gen/fab/$(BOARD)-F_Paste.gbr gen/fab/$(BOARD)-B_Paste.gbr gen/fab/$(BOARD)-F_SilkS.gbr gen/fab/$(BOARD)-B_SilkS.gbr
 
-all: test fab doc pcb.zip
+all: test fab doc pcb
 
-pcb.zip: fab doc
+test: gen/$(BOARD)-drc.txt gen/$(BOARD)-erc.txt
+
+pcb: $(BOARD)_pcb.zip
+
+doc: gen/$(BOARD).pdf gen/$(BOARD)-front.svg gen/$(BOARD)-back.svg
+
+fab: test gen/$(BOARD)_fab.zip gen/$(BOARD).csv gen/$(BOARD)-top-pos.csv
+
+$(BOARD)_pcb.zip: fab doc
 	@mkdir -p gen
-	@cd gen; zip -r ../pcb.zip fab.zip fiatlux.csv fiatlux-top-pos.csv fiatlux-front.svg fiatlux-back.svg fiatlux.pdf
-	@cd gen; zip -r ../debug.zip .
+	cd gen; zip -r ../$(BOARD)_pcb.zip $(BOARD)_fab.zip $(BOARD).csv $(BOARD)-top-pos.csv $(BOARD)-front.svg $(BOARD)-back.svg $(BOARD).pdf
+	cd gen; zip -r ../$(BOARD)_debug.zip .
 
-test: gen/fiatlux-drc.txt gen/fiatlux-erc.txt
-
-doc: gen/fiatlux.pdf gen/fiatlux-front.svg gen/fiatlux-back.svg
-
-fab: test gen/fab.zip gen/fiatlux.csv gen/fiatlux-top-pos.csv
-
-gen/fab.zip: gen/fab/fiatlux-F_Cu.gbr gen/fab/fiatlux-B_Cu.gbr gen/fab/fiatlux-F_Mask.gbr gen/fab/fiatlux-B_Mask.gbr
-gen/fab.zip: gen/fab/fiatlux-F_Paste.gbr gen/fab/fiatlux-B_Paste.gbr gen/fab/fiatlux-F_SilkS.gbr gen/fab/fiatlux-B_SilkS.gbr
+gen/$(BOARD)_fab.zip: gen/fab/$(BOARD)-F_Cu.gbr gen/fab/$(BOARD)-B_Cu.gbr gen/fab/$(BOARD)-F_Mask.gbr gen/fab/$(BOARD)-B_Mask.gbr
+gen/$(BOARD)_fab.zip: gen/fab/$(BOARD)-F_Paste.gbr gen/fab/$(BOARD)-B_Paste.gbr gen/fab/$(BOARD)-F_SilkS.gbr gen/fab/$(BOARD)-B_SilkS.gbr
 	@mkdir -p gen/fab
-	@cd gen/fab; zip -r ../fab.zip *.gbr
+	cd gen/fab; zip -r ../$(BOARD)_fab.zip *.gbr
 
-gen/fiatlux-erc.txt:  fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
+gen/$(BOARD)-erc.txt:  $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
 	@mkdir -p gen
-	kibot -d gen -c fiatlux.kiplot.yaml -s update_xml,run_drc -i
+	kibot -d gen -c $(BOARD).kiplot.yaml -s update_xml,run_drc -i
 
-gen/fiatlux-drc.txt:  fiatlux.kiplot.yaml fiatlux.pro fiatlux.sch
+gen/$(BOARD)-drc.txt:  $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_sch
 	@mkdir -p gen
-	kibot -d gen -c fiatlux.kiplot.yaml -s update_xml,run_erc -i
+	kibot -d gen -c $(BOARD).kiplot.yaml -s update_xml,run_erc -i
 
-gen/fab/%.gbr: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
+gen/fab/%.gbr: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
 	@mkdir -p gen
-	kibot -d gen -c fiatlux.kiplot.yaml -s all print_front gerbers
+	kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front gerbers
 
-gen/fiatlux-top-pos.csv: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
+gen/$(BOARD)-top-pos.csv: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
 	@mkdir -p gen
-	kibot -d gen -c fiatlux.kiplot.yaml -s all print_front position
+	kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front position
 
-gen/fiatlux.csv: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
+gen/$(BOARD).csv: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
 	@mkdir -p gen
-	kibot -d gen -c fiatlux.kiplot.yaml -s all print_front bom
+	kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front bom
 
-gen/fiatlux.pdf: fiatlux.kiplot.yaml fiatlux.pro fiatlux.sch
+gen/$(BOARD).pdf: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_sch
 	@mkdir -p gen
-	kibot -d gen -c fiatlux.kiplot.yaml -s run_drc,run_erc print_sch
+	kibot -d gen -c $(BOARD).kiplot.yaml -s run_drc,run_erc print_sch
 
-gen/fiatlux-front.svg: fiatlux.kicad_pcb
+gen/$(BOARD)-front.svg: $(BOARD).kicad_pcb
 	@mkdir -p gen
 	pcbdraw --libs default $< $@
 
-gen/fiatlux-back.svg: fiatlux.kicad_pcb
+gen/$(BOARD)-back.svg: $(BOARD).kicad_pcb
 	@mkdir -p gen
 	pcbdraw --libs default --back $< $@
 

pcb/bus_node.kicad_sch

@@ -0,0 +1,525 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+  (uuid 0a742bb2-0657-47bc-9dea-e70308e1113a)
+
+  (paper "A4")
+
+  (lib_symbols
+    (symbol "Device:C_Polarized" (pin_numbers hide) (pin_names (offset 0.254)) (in_bom yes) (on_board yes)
+      (property "Reference" "C" (id 0) (at 0.635 2.54 0)
+        (effects (font (size 1.27 1.27)) (justify left))
+      )
+      (property "Value" "C_Polarized" (id 1) (at 0.635 -2.54 0)
+        (effects (font (size 1.27 1.27)) (justify left))
+      )
+      (property "Footprint" "" (id 2) (at 0.9652 -3.81 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "Datasheet" "~" (id 3) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_keywords" "cap capacitor" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_description" "Polarized capacitor" (id 5) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_fp_filters" "CP_*" (id 6) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "C_Polarized_0_1"
+        (rectangle (start -2.286 0.508) (end 2.286 1.016)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (polyline
+          (pts
+            (xy -1.778 2.286)
+            (xy -0.762 2.286)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (polyline
+          (pts
+            (xy -1.27 2.794)
+            (xy -1.27 1.778)
+          )
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type none))
+        )
+        (rectangle (start 2.286 -0.508) (end -2.286 -1.016)
+          (stroke (width 0) (type default) (color 0 0 0 0))
+          (fill (type outline))
+        )
+      )
+      (symbol "C_Polarized_1_1"
+        (pin passive line (at 0 3.81 270) (length 2.794)
+          (name "~" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin passive line (at 0 -3.81 90) (length 2.794)
+          (name "~" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+      )
+    )
+    (symbol "MCU_ST_STM8:STM8S003F3U" (in_bom yes) (on_board yes)
+      (property "Reference" "U" (id 0) (at 1.27 25.4 0)
+        (effects (font (size 1.27 1.27)) (justify left))
+      )
+      (property "Value" "STM8S003F3U" (id 1) (at 1.27 22.86 0)
+        (effects (font (size 1.27 1.27)) (justify left))
+      )
+      (property "Footprint" "Package_DFN_QFN:ST_UFQFPN-20_3x3mm_P0.5mm" (id 2) (at 1.27 27.94 0)
+        (effects (font (size 1.27 1.27)) (justify left) hide)
+      )
+      (property "Datasheet" "http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00024550.pdf" (id 3) (at -1.27 -10.16 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_keywords" "STM8S Mainstream Value line 8-bit, 16MHz, 1k RAM, 128 EEPROM" (id 4) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_description" "16MHz, 8K Flash, 1K RAM, 128 EEPROM, USART, I²C, SPI, UFQFPN-20" (id 5) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (property "ki_fp_filters" "ST?UFQFPN*3x3mm*P0.5mm*" (id 6) (at 0 0 0)
+        (effects (font (size 1.27 1.27)) hide)
+      )
+      (symbol "STM8S003F3U_0_1"
+        (rectangle (start -11.43 21.59) (end 11.43 -21.59)
+          (stroke (width 0.254) (type default) (color 0 0 0 0))
+          (fill (type background))
+        )
+      )
+      (symbol "STM8S003F3U_1_1"
+        (pin input line (at -15.24 -15.24 0) (length 3.81)
+          (name "NRST" (effects (font (size 1.27 1.27))))
+          (number "1" (effects (font (size 1.27 1.27))))
+        )
+        (pin bidirectional line (at -15.24 0 0) (length 3.81)
+          (name "PC3" (effects (font (size 1.27 1.27))))
+          (number "10" (effects (font (size 1.27 1.27))))
+        )
+        (pin bidirectional line (at -15.24 -2.54 0) (length 3.81)
+          (name "PC4" (effects (font (size 1.27 1.27))))
+          (number "11" (effects (font (size 1.27 1.27))))
+        )
+        (pin bidirectional line (at -15.24 -5.08 0) (length 3.81)
+          (name "PC5" (effects (font (size 1.27 1.27))))
+          (number "12" (effects (font (size 1.27 1.27))))
+        )
+        (pin bidirectional line (at -15.24 -7.62 0) (length 3.81)
+          (name "PC6" (effects (font (size 1.27 1.27))))
+          (number "13" (effects (font (size 1.27 1.27))))
+        )
+        (pin bidirectional line (at -15.24 -10.16 0) (length 3.81)
+          (name "PC7" (effects (font (size 1.27 1.27))))
+          (number "14" (effects (font (size 1.27 1.27))))
+        )
+        (pin bidirectional line (at 15.24 7.62 180) (length 3.81)
+          (name "PD1" (effects (font (size 1.27 1.27))))
+          (number "15" (effects (font (size 1.27 1.27))))
+        )
+        (pin bidirectional line (at 15.24 5.08 180) (length 3.81)
+          (name "PD2" (effects (font (size 1.27 1.27))))
+          (number "16" (effects (font (size 1.27 1.27))))
+        )
+        (pin bidirectional line (at 15.24 2.54 180) (length 3.81)
+          (name "PD3" (effects (font (size 1.27 1.27))))
+          (number "17" (effects (font (size 1.27 1.27))))
+        )
+        (pin bidirectional line (at 15.24 0 180) (length 3.81)
+          (name "PD4" (effects (font (size 1.27 1.27))))
+          (number "18" (effects (font (size 1.27 1.27))))
+        )
+        (pin bidirectional line (at 15.24 -2.54 180) (length 3.81)
+          (name "PD5" (effects (font (size 1.27 1.27))))
+          (number "19" (effects (font (size 1.27 1.27))))
+        )
+        (pin bidirectional line (at -15.24 17.78 0) (length 3.81)
+          (name "PA1" (effects (font (size 1.27 1.27))))
+          (number "2" (effects (font (size 1.27 1.27))))
+        )
+        (pin bidirectional line (at 15.24 -5.08 180) (length 3.81)
+          (name "PD6" (effects (font (size 1.27 1.27))))
+          (number "20" (effects (font (size 1.27 1.27))))
+        )
+        (pin bidirectional line (at -15.24 15.24 0) (length 3.81)
+          (name "PA2" (effects (font (size 1.27 1.27))))
+          (number "3" (effects (font (size 1.27 1.27))))
+        )
+        (pin power_in line (at 0 -25.4 90) (length 3.81)
+          (name "VSS" (effects (font (size 1.27 1.27))))
+          (number "4" (effects (font (size 1.27 1.27))))
+        )
+        (pin passive line (at -15.24 -17.78 0) (length 3.81)
+          (name "VCAP" (effects (font (size 1.27 1.27))))
+          (number "5" (effects (font (size 1.27 1.27))))
+        )
+        (pin power_in line (at 0 25.4 270) (length 3.81)
+          (name "VDD" (effects (font (size 1.27 1.27))))
+          (number "6" (effects (font (size 1.27 1.27))))
+        )
+        (pin bidirectional line (at -15.24 12.7 0) (length 3.81)
+          (name "PA3" (effects (font (size 1.27 1.27))))
+          (number "7" (effects (font (size 1.27 1.27))))
+        )
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pcb/fiatlux.kicad_pro

@@ -0,0 +1,435 @@
+{
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+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.09999999999999999,
+        "copper_line_width": 0.19999999999999998,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.09999999999999999,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.65,
+          "height": 0.65,
+          "width": 0.65
+        },
+        "silk_line_width": 0.15,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.508
+        }
+      },
+      "diff_pair_dimensions": [],
+      "drc_exclusions": [],
+      "meta": {
+        "filename": "board_design_settings.json",
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "copper_edge_clearance": "error",
+        "courtyards_overlap": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zone_has_empty_net": "error",
+        "zones_intersect": "error"
+      },
+      "rule_severitieslegacy_courtyards_overlap": true,
+      "rule_severitieslegacy_no_courtyard_defined": false,
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.0,
+        "min_copper_edge_clearance": 0.049999999999999996,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_silk_clearance": 0.0,
+        "min_through_hole_diameter": 0.3,
+        "min_track_width": 0.19999999999999998,
+        "min_via_annular_width": 0.049999999999999996,
+        "min_via_diameter": 0.39999999999999997,
+        "use_height_for_length_calcs": true
+      },
+      "track_widths": [
+        0.0,
+        0.25,
+        0.5,
+        1.0,
+        2.0
+      ],
+      "via_dimensions": [],
+      "zones_allow_external_fillets": false,
+      "zones_use_no_outline": true
+    },
+    "layer_presets": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        1,
+        0,
+        1,
+        2
+      ],
+      [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        1,
+        1,
+        2,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        1,
+        1,
+        1,
+        1,
+        1,
+        0,
+        1,
+        1,
+        1,
+        1,
+        1,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        2,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        1,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        0,
+        0,
+        2
+      ],
+      [
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_label_syntax": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "fiatlux.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12.0,
+        "clearance": 0.127,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6.0
+      }
+    ],
+    "meta": {
+      "version": 2
+    },
+    "net_colors": null
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "fiatlux.net",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "drawing": {
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.25,
+      "pin_symbol_size": 0.0,
+      "text_offset_ratio": 0.08
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "net_format_name": "Pcbnew",
+    "ngspice": {
+      "fix_include_paths": true,
+      "fix_passive_vals": false,
+      "meta": {
+        "version": 0
+      },
+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "spice_adjust_passive_values": false,
+    "spice_external_command": "spice \"%I\"",
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
+  },
+  "sheets": [
+    [
+      "814763c2-92e5-4a2c-941c-9bbd073f6e87",
+      ""
+    ],
+    [
+      "00000000-0000-0000-0000-00006078273a",
+      "Power"
+    ],
+    [
+      "704d02d9-6cb6-48ad-b961-61eafd0de7c6",
+      "Ext-IO"
+    ]
+  ],
+  "text_variables": {}
+}

pcb/fiatlux.kiplot.yaml

@@ -8,6 +8,23 @@ preflight:
   run_drc: true
   check_zone_fills: false
   ignore_unconnected: false
+  filters:
+    - error: 'courtyards_overlap'
+      regex: '((?s)J4(.*)J13)|((?s)J13(.*)J21)|((?s)J2(.*)J15)|((?s)J2(.*)J4)'
+    - error: 'courtyards_overlap'
+      regex: '(?s)J3(.*)J12'
+    - error: 'clearance'
+      regex: '(.*)no net(.*) of J1'
+
+global:
+  filters:
+    - error: 'courtyards_overlap'
+      regex: '((?s)J4(.*)J13)|((?s)J13(.*)J21)|((?s)J2(.*)J15)|((?s)J2(.*)J4)'
+    - error: 'courtyards_overlap'
+      regex: '(?s)J3(.*)J12'
+    - error: 'clearance'
+      regex: '(.*)no net(.*) of J1'
+    - error: 'silk_overlap'
 
 # global:
 #   kiauto_wait_start: 60

pcb/fiatlux.pro

@@ -1,252 +0,0 @@
-update=Mo 12 Jul 2021 16:48:53 CEST
-version=1
-last_client=kicad
-[general]
-version=1
-RootSch=
-BoardNm=
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=Pcbnew
-SpiceAjustPassiveValues=0
-LabSize=50
-ERC_TestSimilarLabels=1
-[pcbnew]
-version=1
-PageLayoutDescrFile=
-LastNetListRead=fiatlux.net
-CopperLayerCount=2
-BoardThickness=1.6
-AllowMicroVias=0
-AllowBlindVias=0
-RequireCourtyardDefinitions=0
-ProhibitOverlappingCourtyards=1
-MinTrackWidth=0.2
-MinViaDiameter=0.4
-MinViaDrill=0.3
-MinMicroViaDiameter=0.2
-MinMicroViaDrill=0.09999999999999999
-MinHoleToHole=0.25
-TrackWidth1=0.25
-TrackWidth2=0.25
-TrackWidth3=0.5
-TrackWidth4=1
-TrackWidth5=2
-ViaDiameter1=0.8
-ViaDrill1=0.4
-dPairWidth1=0.2
-dPairGap1=0.25
-dPairViaGap1=0.25
-SilkLineWidth=0.15
-SilkTextSizeV=1
-SilkTextSizeH=1
-SilkTextSizeThickness=0.15
-SilkTextItalic=0
-SilkTextUpright=1
-CopperLineWidth=0.2
-CopperTextSizeV=1.5
-CopperTextSizeH=1.5
-CopperTextThickness=0.3
-CopperTextItalic=0
-CopperTextUpright=1
-EdgeCutLineWidth=0.09999999999999999
-CourtyardLineWidth=0.05
-OthersLineWidth=0.15
-OthersTextSizeV=1
-OthersTextSizeH=1
-OthersTextSizeThickness=0.15
-OthersTextItalic=0
-OthersTextUpright=1
-SolderMaskClearance=0
-SolderMaskMinWidth=0
-SolderPasteClearance=0
-SolderPasteRatio=-0
-[pcbnew/Layer.F.Cu]
-Name=F.Cu
-Type=0
-Enabled=1
-[pcbnew/Layer.In1.Cu]
-Name=In1.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In2.Cu]
-Name=In2.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In3.Cu]
-Name=In3.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In4.Cu]
-Name=In4.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In5.Cu]
-Name=In5.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In6.Cu]
-Name=In6.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In7.Cu]
-Name=In7.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In8.Cu]
-Name=In8.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In9.Cu]
-Name=In9.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In10.Cu]
-Name=In10.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In11.Cu]
-Name=In11.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In12.Cu]
-Name=In12.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In13.Cu]
-Name=In13.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In14.Cu]
-Name=In14.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In15.Cu]
-Name=In15.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In16.Cu]
-Name=In16.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In17.Cu]
-Name=In17.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In18.Cu]
-Name=In18.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In19.Cu]
-Name=In19.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In20.Cu]
-Name=In20.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In21.Cu]
-Name=In21.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In22.Cu]
-Name=In22.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In23.Cu]
-Name=In23.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In24.Cu]
-Name=In24.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In25.Cu]
-Name=In25.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In26.Cu]
-Name=In26.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In27.Cu]
-Name=In27.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In28.Cu]
-Name=In28.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In29.Cu]
-Name=In29.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In30.Cu]
-Name=In30.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.B.Cu]
-Name=B.Cu
-Type=0
-Enabled=1
-[pcbnew/Layer.B.Adhes]
-Enabled=1
-[pcbnew/Layer.F.Adhes]
-Enabled=1
-[pcbnew/Layer.B.Paste]
-Enabled=1
-[pcbnew/Layer.F.Paste]
-Enabled=1
-[pcbnew/Layer.B.SilkS]
-Enabled=1
-[pcbnew/Layer.F.SilkS]
-Enabled=1
-[pcbnew/Layer.B.Mask]
-Enabled=1
-[pcbnew/Layer.F.Mask]
-Enabled=1
-[pcbnew/Layer.Dwgs.User]
-Enabled=1
-[pcbnew/Layer.Cmts.User]
-Enabled=1
-[pcbnew/Layer.Eco1.User]
-Enabled=1
-[pcbnew/Layer.Eco2.User]
-Enabled=1
-[pcbnew/Layer.Edge.Cuts]
-Enabled=1
-[pcbnew/Layer.Margin]
-Enabled=1
-[pcbnew/Layer.B.CrtYd]
-Enabled=1
-[pcbnew/Layer.F.CrtYd]
-Enabled=1
-[pcbnew/Layer.B.Fab]
-Enabled=1
-[pcbnew/Layer.F.Fab]
-Enabled=1
-[pcbnew/Layer.Rescue]
-Enabled=0
-[pcbnew/Netclasses]
-[pcbnew/Netclasses/Default]
-Name=Default
-Clearance=0.127
-TrackWidth=0.25
-ViaDiameter=0.8
-ViaDrill=0.4
-uViaDiameter=0.3
-uViaDrill=0.1
-dPairWidth=0.2
-dPairGap=0.25
-dPairViaGap=0.25

pcb/fiatlux_cc48.kicad_pro

@@ -0,0 +1,460 @@
+{
+  "board": {
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.09999999999999999,
+        "copper_line_width": 0.19999999999999998,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.15,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 1.52,
+          "height": 3.0,
+          "width": 3.0
+        },
+        "silk_line_width": 0.15,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.508
+        }
+      },
+      "diff_pair_dimensions": [
+        {
+          "gap": 0.0,
+          "via_gap": 0.0,
+          "width": 0.0
+        }
+      ],
+      "drc_exclusions": [],
+      "meta": {
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "copper_edge_clearance": "error",
+        "courtyards_overlap": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zone_has_empty_net": "error",
+        "zones_intersect": "error"
+      },
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.0,
+        "min_copper_edge_clearance": 0.0,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_silk_clearance": 0.0,
+        "min_through_hole_diameter": 0.3,
+        "min_track_width": 0.19999999999999998,
+        "min_via_annular_width": 0.049999999999999996,
+        "min_via_diameter": 0.39999999999999997,
+        "solder_mask_clearance": 0.0,
+        "solder_mask_min_width": 0.0,
+        "use_height_for_length_calcs": true
+      },
+      "track_widths": [
+        0.0,
+        0.25,
+        1.0,
+        2.0
+      ],
+      "via_dimensions": [
+        {
+          "diameter": 0.0,
+          "drill": 0.0
+        }
+      ],
+      "zones_allow_external_fillets": false,
+      "zones_use_no_outline": true
+    },
+    "layer_presets": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        2
+      ],
+      [
+        0,
+        2,
+        0,
+        1,
+        0,
+        0,
+        1,
+        0,
+        2,
+        2,
+        2,
+        2
+      ],
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        1,
+        0,
+        1,
+        2
+      ],
+      [
+        0,
+        1,
+        0,
+        0,
+        0,
+        0,
+        1,
+        1,
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+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_label_syntax": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "fiatlux_cc48.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12.0,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6.0
+      }
+    ],
+    "meta": {
+      "version": 2
+    },
+    "net_colors": null
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "drawing": {
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.375,
+      "pin_symbol_size": 25.0,
+      "text_offset_ratio": 0.15
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "net_format_name": "",
+    "ngspice": {
+      "fix_include_paths": true,
+      "fix_passive_vals": false,
+      "meta": {
+        "version": 0
+      },
+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "spice_adjust_passive_values": false,
+    "spice_external_command": "spice \"%I\"",
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
+  },
+  "sheets": [
+    [
+      "9538e4ed-27e6-4c37-b989-9859dc0d49e8",
+      ""
+    ],
+    [
+      "d33c1df4-7e91-4c8a-86ff-6749f0933357",
+      "fiatlux_cc48_channel_driver2"
+    ],
+    [
+      "ec392c76-0785-4274-a56a-aeb995601b34",
+      "fiatlux_cc48_channel_driver1"
+    ],
+    [
+      "0f2c710f-e0cf-4531-985d-317b699b8a1b",
+      "fiatlux_cc48_channel_driver3"
+    ],
+    [
+      "a672b323-13f7-4347-a8ce-0a3f96c45d44",
+      "fiatlux_cc48_channel_driver5"
+    ],
+    [
+      "a5f417c9-09b7-4103-a9bc-767ebcf97650",
+      "fiatlux_cc48_channel_driver4"
+    ],
+    [
+      "41c6dc95-230a-4992-8ca4-7f36f4bdcf94",
+      "fiatlux_cc48_channel_driver6"
+    ]
+  ],
+  "text_variables": {}
+}

pcb/fiatlux_cc48.kiplot.yaml

@@ -0,0 +1,139 @@
+# Example KiPlot config file
+kiplot:
+  version: 1
+
+preflight:
+  run_erc: true
+  update_xml: true
+  run_drc: true
+  check_zone_fills: false
+  ignore_unconnected: false
+
+# global:
+#   kiauto_wait_start: 60
+#   kiauto_time_out_scale: 2
+
+filters:
+  - name: fix_rotation
+    comment: 'Adjust rotation for JLC'
+    type: rot_footprint
+
+  - name: only_jlc_parts
+    comment: 'Only parts with JLC code'
+    type: generic
+    include_only:
+      - column: 'LCSC#'
+        regex: '^C\d+'
+
+variants:
+  - name: rotated
+    comment: 'Just a place holder for the rotation filter'
+    type: kibom
+    variant: rotated
+    pre_transform: fix_rotation
+
+outputs:
+  - name: 'print_sch'
+    comment: "Print schematic (PDF)"
+    type: pdf_sch_print
+    dir: .
+    options:
+      output: fiatlux_cc48.pdf
+
+  - name: 'print_front'
+    comment: "Print F.Cu+Dwgs.User"
+    type: pdf_pcb_print
+    dir: .
+    options:
+      output_name: fiatlux_cc48-top.pdf
+    layers:
+      - layer: B.Cu
+      - layer: F.SilkS
+
+  - name: 'gerbers'
+    comment: "Gerbers for the board house"
+    type: gerber
+    dir: fab
+    options:
+      # generic layer options
+      exclude_edge_layer: true
+      exclude_pads_from_silkscreen: false
+      use_aux_axis_as_origin: false
+      plot_sheet_reference: false
+      plot_footprint_refs: true
+      plot_footprint_values: true
+      force_plot_invisible_refs_vals: false
+      tent_vias: true
+
+      # gerber options
+      line_width: 0.1
+      subtract_mask_from_silk: false
+      use_protel_extensions: false
+      gerber_precision: 4.6
+      create_gerber_job_file: true
+      use_gerber_x2_attributes: true
+      use_gerber_net_attributes: true
+
+    layers:
+      - layer: F.Cu
+        suffix: F_Cu
+      - layer: B.Cu
+        suffix: B_Cu
+      - layer: F.SilkS
+        suffix: F_SilkS
+      - layer: B.SilkS
+        suffix: B_SilkS
+      - layer: F.Paste
+        suffix: F_Paste
+      - layer: B.Paste
+        suffix: B_Paste
+      - layer: F.Mask
+        suffix: F_Mask
+      - layer: B.Mask
+        suffix: B_Mask
+      - layer: Edge.Cuts
+        suffix: Edge_Cuts
+
+  - name: 'position'
+    comment: "Pick and place file, JLC style"
+    type: position
+    options:
+      variant: rotated
+      output: '%f-top-pos.%x'
+      format: CSV
+      units: millimeters
+      separate_files_for_front_and_back: false
+      only_smd: true
+      columns:
+        - id: Ref
+          name: Designator
+        - Val
+        - Package
+        - id: PosX
+          name: "Mid X"
+        - id: PosY
+          name: "Mid Y"
+        - id: Rot
+          name: Rotation
+        - id: Side
+          name: Layer
+
+  - name: 'bom'
+    comment: "BoM for JLC"
+    type: bom
+    options:
+      output: '%f.%x'
+      exclude_filter: 'only_jlc_parts'
+      ref_separator: ','
+      columns:
+        - field: Value
+          name: Comment
+        - field: References
+          name: Designator
+        - Footprint
+        - field: 'LCSC#'
+          name: 'LCSC Part #'
+      csv:
+        hide_pcb_info: true
+        hide_stats_info: true
+        quote_all: true

pcb/fiatlux_cv24.kicad_pro

@@ -0,0 +1,488 @@
+{
+  "board": {
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.09999999999999999,
+        "copper_line_width": 0.19999999999999998,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.09999999999999999,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.0,
+          "height": 1.2,
+          "width": 2.2
+        },
+        "silk_line_width": 0.15,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.508
+        }
+      },
+      "diff_pair_dimensions": [
+        {
+          "gap": 0.0,
+          "via_gap": 0.0,
+          "width": 0.0
+        }
+      ],
+      "drc_exclusions": [],
+      "meta": {
+        "filename": "board_design_settings.json",
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "copper_edge_clearance": "error",
+        "courtyards_overlap": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zone_has_empty_net": "error",
+        "zones_intersect": "error"
+      },
+      "rule_severitieslegacy_courtyards_overlap": true,
+      "rule_severitieslegacy_no_courtyard_defined": false,
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.0,
+        "min_copper_edge_clearance": 0.049999999999999996,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_silk_clearance": 0.0,
+        "min_through_hole_diameter": 0.3,
+        "min_track_width": 0.19999999999999998,
+        "min_via_annular_width": 0.049999999999999996,
+        "min_via_diameter": 0.39999999999999997,
+        "use_height_for_length_calcs": true
+      },
+      "track_widths": [
+        0.0,
+        0.25,
+        0.5,
+        1.0,
+        2.0,
+        4.0
+      ],
+      "via_dimensions": [
+        {
+          "diameter": 0.0,
+          "drill": 0.0
+        }
+      ],
+      "zones_allow_external_fillets": false,
+      "zones_use_no_outline": true
+    },
+    "layer_presets": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
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+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_label_syntax": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "fiatlux_cv24.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12.0,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6.0
+      },
+      {
+        "bus_width": 12.0,
+        "clearance": 0.127,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Signal-Min",
+        "nets": [
+          "AIN3",
+          "AIN5",
+          "AIN6",
+          "BTN1",
+          "BTN2",
+          "BTN3",
+          "INIT_{IN}",
+          "INIT_{OUT}",
+          "MISO",
+          "MOSI",
+          "SCLK",
+          "SWIM",
+          "~{BUSRST}",
+          "~{INT}"
+        ],
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.2,
+        "via_diameter": 0.4,
+        "via_drill": 0.2,
+        "wire_width": 6.0
+      }
+    ],
+    "meta": {
+      "version": 2
+    },
+    "net_colors": null
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "fiatlux_cv24.net",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "drawing": {
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.25,
+      "pin_symbol_size": 0.0,
+      "text_offset_ratio": 0.08
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pcb/fiatlux_cv24_channel_driver.kicad_sch

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+    (pin "2" (uuid 81ed580a-8e27-406d-b7c9-133f47d2e76f))
+  )
+
+  (symbol (lib_id "Device:Q_NMOS_GDSD") (at 119.38 76.2 0)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid 6356fe97-06cd-4a4b-b2f2-2e98498da4a1)
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+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Value" "Q_NMOS_GDSD" (id 1) (at 125.095 78.0666 0)
+      (effects (font (size 1.27 1.27)) (justify left))
+    )
+    (property "Footprint" "Package_TO_SOT_SMD:TO-252-3_TabPin4" (id 2) (at 124.46 73.66 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "~" (id 3) (at 119.38 76.2 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
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+    (pin "4" (uuid 45580b2c-f853-4bae-b48d-8b2b7a8c9649))
+  )
+
+  (symbol (lib_id "power:GND") (at 121.92 91.44 0)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid 89d30dc5-826e-436b-acb9-f9172d6bf59d)
+    (property "Reference" "#PWR?" (id 0) (at 121.92 97.79 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (id 1) (at 121.92 96.0025 0))
+    (property "Footprint" "" (id 2) (at 121.92 91.44 0)
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+    )
+    (pin "1" (uuid a70a6a3f-2724-48b3-b488-859475275951))
+  )
+
+  (symbol (lib_id "Device:LED_Small") (at 111.76 81.28 90)
+    (in_bom yes) (on_board yes)
+    (uuid ce7cb119-1df8-42ef-b2f2-2dae443be651)
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+      (effects (font (size 1.27 1.27)) (justify right))
+    )
+    (property "Value" "RED" (id 1) (at 113.538 82.423 90)
+      (effects (font (size 1.27 1.27)) (justify right))
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+      (effects (font (size 1.27 1.27)) hide)
+    )
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+      (effects (font (size 1.27 1.27)) hide)
+    )
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+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 4fd135f0-38be-402a-9bc7-59f09498eddd))
+    (pin "2" (uuid 366b4e95-01fd-42ef-a705-8f901032e0c6))
+  )
+)

pcb/library.kicad_sym

@@ -0,0 +1,60 @@
+(kicad_symbol_lib (version 20211014) (generator kicad_symbol_editor)
+  (symbol "BL1551B" (in_bom yes) (on_board yes)
+    (property "Reference" "U" (id 0) (at 0 -1.27 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Value" "BL1551B" (id 1) (at 0 1.27 0)
+      (effects (font (size 1.27 1.27)))
+    )
+    (property "Footprint" "" (id 2) (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 0 0 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (symbol "BL1551B_0_1"
+      (rectangle (start 6.35 7.62) (end -6.35 -7.62)
+        (stroke (width 0.1524) (type default) (color 0 0 0 0))
+        (fill (type background))
+      )
+      (rectangle (start 10.16 -10.16) (end 10.16 -10.16)
+        (stroke (width 0.1524) (type default) (color 0 0 0 0))
+        (fill (type none))
+      )
+      (rectangle (start 10.16 -10.16) (end 10.16 -10.16)
+        (stroke (width 0.1524) (type default) (color 0 0 0 0))
+        (fill (type none))
+      )
+      (rectangle (start 10.16 -10.16) (end 10.16 -10.16)
+        (stroke (width 0.1524) (type default) (color 0 0 0 0))
+        (fill (type none))
+      )
+    )
+    (symbol "BL1551B_1_1"
+      (pin bidirectional line (at -8.89 3.81 0) (length 2.54)
+        (name "A1" (effects (font (size 1.27 1.27))))
+        (number "1" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 0 -10.16 90) (length 2.54)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "2" (effects (font (size 1.27 1.27))))
+      )
+      (pin bidirectional line (at -8.89 -3.81 0) (length 2.54)
+        (name "A2" (effects (font (size 1.27 1.27))))
+        (number "3" (effects (font (size 1.27 1.27))))
+      )
+      (pin bidirectional line (at 8.89 -3.81 180) (length 2.54)
+        (name "B" (effects (font (size 1.27 1.27))))
+        (number "4" (effects (font (size 1.27 1.27))))
+      )
+      (pin power_in line (at 0 10.16 270) (length 2.54)
+        (name "VCC" (effects (font (size 1.27 1.27))))
+        (number "5" (effects (font (size 1.27 1.27))))
+      )
+      (pin input line (at 8.89 3.81 180) (length 2.54)
+        (name "ENB" (effects (font (size 1.27 1.27))))
+        (number "6" (effects (font (size 1.27 1.27))))
+      )
+    )
+  )
+)

pcb/power.sch

@@ -1,643 +0,0 @@
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pcb/sym-lib-table

@@ -0,0 +1,3 @@
+(sym_lib_table
+  (lib (name "library")(type "KiCad")(uri "${KIPRJMOD}/library.kicad_sym")(options "")(descr ""))
+)