update to kicad6
This commit is contained in:
parent
b10103377d
commit
c85dc416ed
10 changed files with 25886 additions and 7382 deletions
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@ -19,11 +19,11 @@ steps:
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- make firmware -j$(nproc)
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- name: pcb
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image: setsoft/kicad_auto
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image: setsoft/kicad_auto:ki6
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commands:
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- apt update
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- apt install -y make zip
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- make pcb -j$(nproc)
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- make pcb -j$(nproc) BOARD=fiatlux
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- name: case
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image: debian:sid
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@ -58,10 +58,10 @@ steps:
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files:
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- firmware/firmware/fiatlux.bin
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- firmware/otaflash.py
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- pcb/pcb.zip
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- pcb/fiatlux_pcb.zip
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checksum:
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- sha512
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- md5
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title: buildtest
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title: fiatlux
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when:
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event: tag
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1
pcb/.gitignore
vendored
1
pcb/.gitignore
vendored
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@ -16,6 +16,7 @@ _autosave-*
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*-save.pro
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*-save.kicad_pcb
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fp-info-cache
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*-backups/
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# Netlist files (exported from Eeschema)
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*.net
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58
pcb/Makefile
58
pcb/Makefile
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@ -1,52 +1,54 @@
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.NOTPARALLEL: gen/fab/fiatlux-F_Cu.gbr gen/fab/fiatlux-B_Cu.gbr gen/fab/fiatlux-F_Mask.gbr gen/fab/fiatlux-B_Mask.gbr gen/fab/fiatlux-F_Paste.gbr gen/fab/fiatlux-B_Paste.gbr gen/fab/fiatlux-F_SilkS.gbr gen/fab/fiatlux-B_SilkS.gbr
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.NOTPARALLEL: gen/fab/$(BOARD)-F_Cu.gbr gen/fab/$(BOARD)-B_Cu.gbr gen/fab/$(BOARD)-F_Mask.gbr gen/fab/$(BOARD)-B_Mask.gbr gen/fab/$(BOARD)-F_Paste.gbr gen/fab/$(BOARD)-B_Paste.gbr gen/fab/$(BOARD)-F_SilkS.gbr gen/fab/$(BOARD)-B_SilkS.gbr
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all: test fab doc pcb.zip
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all: test fab doc pcb
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pcb.zip: fab doc
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test: gen/$(BOARD)-drc.txt gen/$(BOARD)-erc.txt
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pcb: $(BOARD)_pcb.zip
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doc: gen/$(BOARD).pdf gen/$(BOARD)-front.svg gen/$(BOARD)-back.svg
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fab: test gen/$(BOARD)_fab.zip gen/$(BOARD).csv gen/$(BOARD)-top-pos.csv
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$(BOARD)_pcb.zip: fab doc
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@mkdir -p gen
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@cd gen; zip -r ../pcb.zip fab.zip fiatlux.csv fiatlux-top-pos.csv fiatlux-front.svg fiatlux-back.svg fiatlux.pdf
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@cd gen; zip -r ../debug.zip .
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cd gen; zip -r ../$(BOARD)_pcb.zip $(BOARD)_fab.zip $(BOARD).csv $(BOARD)-top-pos.csv $(BOARD)-front.svg $(BOARD)-back.svg $(BOARD).pdf
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cd gen; zip -r ../$(BOARD)_debug.zip .
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test: gen/fiatlux-drc.txt gen/fiatlux-erc.txt
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doc: gen/fiatlux.pdf gen/fiatlux-front.svg gen/fiatlux-back.svg
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fab: test gen/fab.zip gen/fiatlux.csv gen/fiatlux-top-pos.csv
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gen/fab.zip: gen/fab/fiatlux-F_Cu.gbr gen/fab/fiatlux-B_Cu.gbr gen/fab/fiatlux-F_Mask.gbr gen/fab/fiatlux-B_Mask.gbr
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gen/fab.zip: gen/fab/fiatlux-F_Paste.gbr gen/fab/fiatlux-B_Paste.gbr gen/fab/fiatlux-F_SilkS.gbr gen/fab/fiatlux-B_SilkS.gbr
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gen/$(BOARD)_fab.zip: gen/fab/$(BOARD)-F_Cu.gbr gen/fab/$(BOARD)-B_Cu.gbr gen/fab/$(BOARD)-F_Mask.gbr gen/fab/$(BOARD)-B_Mask.gbr
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gen/$(BOARD)_fab.zip: gen/fab/$(BOARD)-F_Paste.gbr gen/fab/$(BOARD)-B_Paste.gbr gen/fab/$(BOARD)-F_SilkS.gbr gen/fab/$(BOARD)-B_SilkS.gbr
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@mkdir -p gen/fab
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@cd gen/fab; zip -r ../fab.zip *.gbr
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cd gen/fab; zip -r ../$(BOARD)_fab.zip *.gbr
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gen/fiatlux-erc.txt: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
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gen/$(BOARD)-erc.txt: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
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@mkdir -p gen
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kibot -d gen -c fiatlux.kiplot.yaml -s update_xml,run_drc -i
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kibot -d gen -c $(BOARD).kiplot.yaml -s update_xml,run_drc -i
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gen/fiatlux-drc.txt: fiatlux.kiplot.yaml fiatlux.pro fiatlux.sch
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gen/$(BOARD)-drc.txt: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_sch
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@mkdir -p gen
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kibot -d gen -c fiatlux.kiplot.yaml -s update_xml,run_erc -i
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kibot -d gen -c $(BOARD).kiplot.yaml -s update_xml,run_erc -i
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gen/fab/%.gbr: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
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gen/fab/%.gbr: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
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@mkdir -p gen
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kibot -d gen -c fiatlux.kiplot.yaml -s all print_front gerbers
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kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front gerbers
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gen/fiatlux-top-pos.csv: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
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gen/$(BOARD)-top-pos.csv: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
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@mkdir -p gen
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kibot -d gen -c fiatlux.kiplot.yaml -s all print_front position
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kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front position
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gen/fiatlux.csv: fiatlux.kiplot.yaml fiatlux.pro fiatlux.kicad_pcb
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gen/$(BOARD).csv: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_pcb
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@mkdir -p gen
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kibot -d gen -c fiatlux.kiplot.yaml -s all print_front bom
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kibot -d gen -c $(BOARD).kiplot.yaml -s all print_front bom
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gen/fiatlux.pdf: fiatlux.kiplot.yaml fiatlux.pro fiatlux.sch
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gen/$(BOARD).pdf: $(BOARD).kiplot.yaml $(BOARD).kicad_pro $(BOARD).kicad_sch
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@mkdir -p gen
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kibot -d gen -c fiatlux.kiplot.yaml -s run_drc,run_erc print_sch
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kibot -d gen -c $(BOARD).kiplot.yaml -s run_drc,run_erc print_sch
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gen/fiatlux-front.svg: fiatlux.kicad_pcb
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gen/$(BOARD)-front.svg: $(BOARD).kicad_pcb
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@mkdir -p gen
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pcbdraw --libs default $< $@
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gen/fiatlux-back.svg: fiatlux.kicad_pcb
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gen/$(BOARD)-back.svg: $(BOARD).kicad_pcb
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@mkdir -p gen
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pcbdraw --libs default --back $< $@
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24667
pcb/fiatlux.kicad_pcb
24667
pcb/fiatlux.kicad_pcb
File diff suppressed because it is too large
Load diff
431
pcb/fiatlux.kicad_pro
Normal file
431
pcb/fiatlux.kicad_pro
Normal file
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@ -0,0 +1,431 @@
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{
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"board": {
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.09999999999999999,
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"copper_line_width": 0.19999999999999998,
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"copper_text_italic": false,
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"copper_text_size_h": 1.5,
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"copper_text_size_v": 1.5,
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"copper_text_thickness": 0.3,
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"copper_text_upright": false,
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"courtyard_line_width": 0.049999999999999996,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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"arrow_length": 1270000,
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"extension_offset": 500000,
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"keep_text_aligned": true,
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"suppress_zeroes": false,
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"text_position": 0,
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"units_format": 1
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},
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"fab_line_width": 0.09999999999999999,
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"fab_text_italic": false,
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"fab_text_size_h": 1.0,
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"fab_text_size_v": 1.0,
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"fab_text_thickness": 0.15,
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"fab_text_upright": false,
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"other_line_width": 0.09999999999999999,
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"other_text_italic": false,
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"other_text_size_h": 1.0,
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"other_text_size_v": 1.0,
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"other_text_thickness": 0.15,
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"other_text_upright": false,
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"pads": {
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"drill": 0.65,
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"height": 0.65,
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"width": 0.65
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},
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"silk_line_width": 0.15,
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"silk_text_italic": false,
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"silk_text_size_h": 1.0,
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"silk_text_size_v": 1.0,
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"silk_text_thickness": 0.15,
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"silk_text_upright": false,
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"zones": {
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"45_degree_only": false,
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"min_clearance": 0.508
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}
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},
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"diff_pair_dimensions": [],
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"drc_exclusions": [],
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"meta": {
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"filename": "board_design_settings.json",
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"version": 2
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},
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"copper_edge_clearance": "error",
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"courtyards_overlap": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint_type_mismatch": "error",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "error",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_over_copper": "warning",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_width": "error",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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"zone_has_empty_net": "error",
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"zones_intersect": "error"
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},
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"rule_severitieslegacy_courtyards_overlap": true,
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"rule_severitieslegacy_no_courtyard_defined": false,
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"rules": {
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"allow_blind_buried_vias": false,
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"allow_microvias": false,
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"max_error": 0.005,
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"min_clearance": 0.0,
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"min_copper_edge_clearance": 0.049999999999999996,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.19999999999999998,
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"min_microvia_drill": 0.09999999999999999,
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"min_silk_clearance": 0.0,
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"min_through_hole_diameter": 0.3,
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"min_track_width": 0.19999999999999998,
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"min_via_annular_width": 0.049999999999999996,
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"min_via_diameter": 0.39999999999999997,
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"use_height_for_length_calcs": true
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},
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"track_widths": [
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0.0,
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0.25,
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0.5,
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1.0,
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2.0
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],
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"via_dimensions": [],
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"zones_allow_external_fillets": false,
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"zones_use_no_outline": true
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},
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"layer_presets": []
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},
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"boards": [],
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"cvpcb": {
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"equivalence_files": []
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},
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"erc": {
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"erc_exclusions": [],
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"meta": {
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"version": 0
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},
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"pin_map": [
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[
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0,
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0,
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0,
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0,
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0,
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0,
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1,
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0,
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0,
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0,
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0,
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2
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],
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[
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0,
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2,
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0,
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1,
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0,
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0,
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1,
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0,
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2,
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2,
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2,
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2
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],
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[
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0,
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0,
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0,
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0,
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0,
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0,
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1,
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0,
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1,
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0,
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1,
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2
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],
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[
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0,
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1,
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0,
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0,
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0,
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||||
0,
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1,
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1,
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2,
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1,
|
||||
1,
|
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2
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],
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[
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0,
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0,
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0,
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||||
0,
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0,
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||||
0,
|
||||
1,
|
||||
0,
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||||
0,
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||||
0,
|
||||
0,
|
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2
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],
|
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[
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0,
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0,
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||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
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0,
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0,
|
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0,
|
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0,
|
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2
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],
|
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[
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1,
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1,
|
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1,
|
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1,
|
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1,
|
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0,
|
||||
1,
|
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1,
|
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1,
|
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1,
|
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1,
|
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2
|
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],
|
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[
|
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0,
|
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0,
|
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0,
|
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1,
|
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0,
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0,
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1,
|
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0,
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0,
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0,
|
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0,
|
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2
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],
|
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[
|
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0,
|
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2,
|
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1,
|
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2,
|
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0,
|
||||
0,
|
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1,
|
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0,
|
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2,
|
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2,
|
||||
2,
|
||||
2
|
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],
|
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[
|
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0,
|
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2,
|
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0,
|
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1,
|
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0,
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0,
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1,
|
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0,
|
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2,
|
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0,
|
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0,
|
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2
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],
|
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[
|
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0,
|
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2,
|
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1,
|
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1,
|
||||
0,
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0,
|
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1,
|
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0,
|
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2,
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0,
|
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0,
|
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2
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],
|
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[
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2,
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2,
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2,
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2,
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2,
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2,
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2,
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2,
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2,
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2,
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2,
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2
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]
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],
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"rule_severities": {
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"bus_definition_conflict": "error",
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"bus_entry_needed": "error",
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"bus_label_syntax": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_net_conflict": "error",
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"different_unit_footprint": "error",
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"different_unit_net": "error",
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"duplicate_reference": "error",
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"duplicate_sheet_names": "error",
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"extra_units": "error",
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"global_label_dangling": "warning",
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"hier_label_mismatch": "error",
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"label_dangling": "error",
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"lib_symbol_issues": "warning",
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"multiple_net_names": "warning",
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"net_not_bus_member": "warning",
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"no_connect_connected": "warning",
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"no_connect_dangling": "warning",
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"pin_not_connected": "error",
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"pin_not_driven": "error",
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"pin_to_pin": "warning",
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"power_pin_not_driven": "error",
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"similar_labels": "warning",
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"unannotated": "error",
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"unit_value_mismatch": "error",
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"unresolved_variable": "error",
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"wire_dangling": "error"
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}
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},
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"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "fiatlux.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.127,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.25,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "fiatlux.net",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"drawing": {
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.25,
|
||||
"pin_symbol_size": 0.0,
|
||||
"text_offset_ratio": 0.08
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "Pcbnew",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"fix_passive_vals": false,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 0,
|
||||
"workbook_filename": ""
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_adjust_passive_values": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"ab06324e-b31e-4d03-a693-31b71a6eda60",
|
||||
""
|
||||
],
|
||||
[
|
||||
"00000000-0000-0000-0000-00006078273a",
|
||||
"Power"
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
||||
4169
pcb/fiatlux.kicad_sch
Normal file
4169
pcb/fiatlux.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
252
pcb/fiatlux.pro
252
pcb/fiatlux.pro
|
|
@ -1,252 +0,0 @@
|
|||
update=Mo 12 Jul 2021 16:48:53 CEST
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=fiatlux.net
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.2
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.25
|
||||
TrackWidth2=0.25
|
||||
TrackWidth3=0.5
|
||||
TrackWidth4=1
|
||||
TrackWidth5=2
|
||||
ViaDiameter1=0.8
|
||||
ViaDrill1=0.4
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.15
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.09999999999999999
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.127
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.4
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
1340
pcb/fiatlux.sch
1340
pcb/fiatlux.sch
File diff suppressed because it is too large
Load diff
1699
pcb/power.kicad_sch
Normal file
1699
pcb/power.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
643
pcb/power.sch
643
pcb/power.sch
|
|
@ -1,643 +0,0 @@
|
|||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 2 2
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L Regulator_Linear:AMS1117-3.3 U?
|
||||
U 1 1 6078C93E
|
||||
P 5650 2450
|
||||
AR Path="/6078C93E" Ref="U?" Part="1"
|
||||
AR Path="/6078273A/6078C93E" Ref="U3" Part="1"
|
||||
F 0 "U3" H 5650 2692 50 0000 C CNN
|
||||
F 1 "AMS1117-3.3" H 5650 2601 50 0000 C CNN
|
||||
F 2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" H 5650 2650 50 0001 C CNN
|
||||
F 3 "http://www.advanced-monolithic.com/pdf/ds1117.pdf" H 5750 2200 50 0001 C CNN
|
||||
F 4 "C6186" H 5650 2450 50 0001 C CNN "LCSC"
|
||||
1 5650 2450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR?
|
||||
U 1 1 6078C94A
|
||||
P 6250 3050
|
||||
AR Path="/6078C94A" Ref="#PWR?" Part="1"
|
||||
AR Path="/6078273A/6078C94A" Ref="#PWR0101" Part="1"
|
||||
F 0 "#PWR0101" H 6250 2800 50 0001 C CNN
|
||||
F 1 "GND" H 6255 2877 50 0000 C CNN
|
||||
F 2 "" H 6250 3050 50 0001 C CNN
|
||||
F 3 "" H 6250 3050 50 0001 C CNN
|
||||
1 6250 3050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR?
|
||||
U 1 1 6078C950
|
||||
P 5650 3050
|
||||
AR Path="/6078C950" Ref="#PWR?" Part="1"
|
||||
AR Path="/6078273A/6078C950" Ref="#PWR0102" Part="1"
|
||||
F 0 "#PWR0102" H 5650 2800 50 0001 C CNN
|
||||
F 1 "GND" H 5655 2877 50 0000 C CNN
|
||||
F 2 "" H 5650 3050 50 0001 C CNN
|
||||
F 3 "" H 5650 3050 50 0001 C CNN
|
||||
1 5650 3050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR?
|
||||
U 1 1 6078C956
|
||||
P 5050 3050
|
||||
AR Path="/6078C956" Ref="#PWR?" Part="1"
|
||||
AR Path="/6078273A/6078C956" Ref="#PWR0103" Part="1"
|
||||
F 0 "#PWR0103" H 5050 2800 50 0001 C CNN
|
||||
F 1 "GND" H 5055 2877 50 0000 C CNN
|
||||
F 2 "" H 5050 3050 50 0001 C CNN
|
||||
F 3 "" H 5050 3050 50 0001 C CNN
|
||||
1 5050 3050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3.3V #PWR?
|
||||
U 1 1 6078C95C
|
||||
P 6250 2400
|
||||
AR Path="/6078C95C" Ref="#PWR?" Part="1"
|
||||
AR Path="/6078273A/6078C95C" Ref="#PWR0104" Part="1"
|
||||
F 0 "#PWR0104" H 6250 2250 50 0001 C CNN
|
||||
F 1 "+3.3V" H 6265 2573 50 0000 C CNN
|
||||
F 2 "" H 6250 2400 50 0001 C CNN
|
||||
F 3 "" H 6250 2400 50 0001 C CNN
|
||||
1 6250 2400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5350 2450 5050 2450
|
||||
Wire Wire Line
|
||||
5050 2450 5050 2550
|
||||
Wire Wire Line
|
||||
6250 2400 6250 2450
|
||||
Wire Wire Line
|
||||
5950 2450 6250 2450
|
||||
Connection ~ 6250 2450
|
||||
Wire Wire Line
|
||||
6250 2450 6250 2550
|
||||
Wire Wire Line
|
||||
6250 2850 6250 3050
|
||||
$Comp
|
||||
L Device:D_Schottky D?
|
||||
U 1 1 6078C973
|
||||
P 5050 2150
|
||||
AR Path="/6078C973" Ref="D?" Part="1"
|
||||
AR Path="/6078273A/6078C973" Ref="D1" Part="1"
|
||||
F 0 "D1" H 5050 1933 50 0000 C CNN
|
||||
F 1 "SS14" H 5050 2024 50 0000 C CNN
|
||||
F 2 "Diode_SMD:D_SMA" H 5050 2025 50 0001 C CNN
|
||||
F 3 "~" H 5050 2150 50 0001 C CNN
|
||||
F 4 "C2480" H 5050 2150 50 0001 C CNN "LCSC"
|
||||
1 5050 2150
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 6078C989
|
||||
P 5050 2700
|
||||
AR Path="/6078C989" Ref="C?" Part="1"
|
||||
AR Path="/6078273A/6078C989" Ref="C1" Part="1"
|
||||
F 0 "C1" H 5165 2746 50 0000 L CNN
|
||||
F 1 "10uF" H 5165 2655 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0805_2012Metric" H 5088 2550 50 0001 C CNN
|
||||
F 3 "~" H 5050 2700 50 0001 C CNN
|
||||
F 4 "C15850" H 5050 2700 50 0001 C CNN "LCSC"
|
||||
1 5050 2700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3.3V #PWR0108
|
||||
U 1 1 60793A86
|
||||
P 7100 2400
|
||||
F 0 "#PWR0108" H 7100 2250 50 0001 C CNN
|
||||
F 1 "+3.3V" H 7115 2573 50 0000 C CNN
|
||||
F 2 "" H 7100 2400 50 0001 C CNN
|
||||
F 3 "" H 7100 2400 50 0001 C CNN
|
||||
1 7100 2400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0109
|
||||
U 1 1 6079401E
|
||||
P 7100 3050
|
||||
F 0 "#PWR0109" H 7100 2800 50 0001 C CNN
|
||||
F 1 "GND" H 7105 2877 50 0000 C CNN
|
||||
F 2 "" H 7100 3050 50 0001 C CNN
|
||||
F 3 "" H 7100 3050 50 0001 C CNN
|
||||
1 7100 3050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:CP C3
|
||||
U 1 1 60794539
|
||||
P 7100 2700
|
||||
F 0 "C3" H 7218 2746 50 0000 L CNN
|
||||
F 1 "TAJB107K006RNJ" H 7218 2655 50 0000 L CNN
|
||||
F 2 "Capacitor_Tantalum_SMD:CP_EIA-3528-21_Kemet-B" H 7138 2550 50 0001 C CNN
|
||||
F 3 "~" H 7100 2700 50 0001 C CNN
|
||||
F 4 "C16133" H 7100 2700 50 0001 C CNN "LCSC"
|
||||
1 7100 2700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
7100 2550 7100 2400
|
||||
Wire Wire Line
|
||||
7100 3050 7100 2850
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 607B779D
|
||||
P 5850 4100
|
||||
AR Path="/607B779D" Ref="C?" Part="1"
|
||||
AR Path="/6078273A/607B779D" Ref="C6" Part="1"
|
||||
F 0 "C6" H 5965 4146 50 0000 L CNN
|
||||
F 1 "100nF" H 5965 4055 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric" H 5888 3950 50 0001 C CNN
|
||||
F 3 "~" H 5850 4100 50 0001 C CNN
|
||||
F 4 "C14663" H 5850 4100 50 0001 C CNN "LCSC"
|
||||
1 5850 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3.3V #PWR?
|
||||
U 1 1 607B7FBF
|
||||
P 5050 3750
|
||||
AR Path="/607B7FBF" Ref="#PWR?" Part="1"
|
||||
AR Path="/6078273A/607B7FBF" Ref="#PWR0134" Part="1"
|
||||
F 0 "#PWR0134" H 5050 3600 50 0001 C CNN
|
||||
F 1 "+3.3V" H 5065 3923 50 0000 C CNN
|
||||
F 2 "" H 5050 3750 50 0001 C CNN
|
||||
F 3 "" H 5050 3750 50 0001 C CNN
|
||||
1 5050 3750
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0135
|
||||
U 1 1 607B9620
|
||||
P 5050 4450
|
||||
F 0 "#PWR0135" H 5050 4200 50 0001 C CNN
|
||||
F 1 "GND" H 5055 4277 50 0000 C CNN
|
||||
F 2 "" H 5050 4450 50 0001 C CNN
|
||||
F 3 "" H 5050 4450 50 0001 C CNN
|
||||
1 5050 4450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5050 4450 5050 4350
|
||||
Wire Wire Line
|
||||
5850 4250 5850 4350
|
||||
Wire Wire Line
|
||||
5850 4350 5050 4350
|
||||
Connection ~ 5050 4350
|
||||
Wire Wire Line
|
||||
5050 4350 5050 4250
|
||||
Wire Wire Line
|
||||
5850 3950 5850 3850
|
||||
Wire Wire Line
|
||||
5850 3850 5050 3850
|
||||
Wire Wire Line
|
||||
5050 3850 5050 3750
|
||||
Wire Wire Line
|
||||
5050 3950 5050 3850
|
||||
Connection ~ 5050 3850
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 607C2A6A
|
||||
P 7900 4100
|
||||
AR Path="/607C2A6A" Ref="C?" Part="1"
|
||||
AR Path="/6078273A/607C2A6A" Ref="C8" Part="1"
|
||||
F 0 "C8" H 8015 4146 50 0000 L CNN
|
||||
F 1 "100nF" H 8015 4055 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0603_1608Metric" H 7938 3950 50 0001 C CNN
|
||||
F 3 "~" H 7900 4100 50 0001 C CNN
|
||||
F 4 "C14663" H 7900 4100 50 0001 C CNN "LCSC"
|
||||
1 7900 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0136
|
||||
U 1 1 607C2A7C
|
||||
P 7100 4450
|
||||
F 0 "#PWR0136" H 7100 4200 50 0001 C CNN
|
||||
F 1 "GND" H 7105 4277 50 0000 C CNN
|
||||
F 2 "" H 7100 4450 50 0001 C CNN
|
||||
F 3 "" H 7100 4450 50 0001 C CNN
|
||||
1 7100 4450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
7100 4450 7100 4350
|
||||
Wire Wire Line
|
||||
7900 4250 7900 4350
|
||||
Wire Wire Line
|
||||
7900 4350 7100 4350
|
||||
Connection ~ 7100 4350
|
||||
Wire Wire Line
|
||||
7100 4350 7100 4250
|
||||
Wire Wire Line
|
||||
7900 3950 7900 3850
|
||||
Wire Wire Line
|
||||
7900 3850 7100 3850
|
||||
Wire Wire Line
|
||||
7100 3850 7100 3750
|
||||
Wire Wire Line
|
||||
7100 3950 7100 3850
|
||||
Connection ~ 7100 3850
|
||||
$Comp
|
||||
L Device:D_Schottky D?
|
||||
U 1 1 607C7255
|
||||
P 4450 2150
|
||||
AR Path="/607C7255" Ref="D?" Part="1"
|
||||
AR Path="/6078273A/607C7255" Ref="D6" Part="1"
|
||||
F 0 "D6" H 4450 1933 50 0000 C CNN
|
||||
F 1 "SS14" H 4450 2024 50 0000 C CNN
|
||||
F 2 "Diode_SMD:D_SMA" H 4450 2025 50 0001 C CNN
|
||||
F 3 "~" H 4450 2150 50 0001 C CNN
|
||||
F 4 "C2480" H 4450 2150 50 0001 C CNN "LCSC"
|
||||
1 4450 2150
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5650 2750 5650 3050
|
||||
Wire Wire Line
|
||||
5050 2850 5050 3050
|
||||
Wire Wire Line
|
||||
5050 2300 5050 2450
|
||||
Connection ~ 5050 2450
|
||||
Wire Wire Line
|
||||
4450 2300 4450 2450
|
||||
Wire Wire Line
|
||||
4450 2450 5050 2450
|
||||
$Comp
|
||||
L power:+12V #PWR0132
|
||||
U 1 1 608DD823
|
||||
P 4450 1850
|
||||
F 0 "#PWR0132" H 4450 1700 50 0001 C CNN
|
||||
F 1 "+12V" H 4465 2023 50 0000 C CNN
|
||||
F 2 "" H 4450 1850 50 0001 C CNN
|
||||
F 3 "" H 4450 1850 50 0001 C CNN
|
||||
1 4450 1850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+5V #PWR0133
|
||||
U 1 1 608DE102
|
||||
P 5050 1850
|
||||
F 0 "#PWR0133" H 5050 1700 50 0001 C CNN
|
||||
F 1 "+5V" H 5065 2023 50 0000 C CNN
|
||||
F 2 "" H 5050 1850 50 0001 C CNN
|
||||
F 3 "" H 5050 1850 50 0001 C CNN
|
||||
1 5050 1850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4450 1850 4450 2000
|
||||
Wire Wire Line
|
||||
5050 1850 5050 2000
|
||||
$Comp
|
||||
L power:+5V #PWR0137
|
||||
U 1 1 608E064A
|
||||
P 7100 3750
|
||||
F 0 "#PWR0137" H 7100 3600 50 0001 C CNN
|
||||
F 1 "+5V" H 7115 3923 50 0000 C CNN
|
||||
F 2 "" H 7100 3750 50 0001 C CNN
|
||||
F 3 "" H 7100 3750 50 0001 C CNN
|
||||
1 7100 3750
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:D_Zener D7
|
||||
U 1 1 608E2DA3
|
||||
P 8700 2700
|
||||
F 0 "D7" V 8654 2780 50 0000 L CNN
|
||||
F 1 "Z 5V" V 8745 2780 50 0000 L CNN
|
||||
F 2 "Diode_SMD:D_MiniMELF" H 8700 2700 50 0001 C CNN
|
||||
F 3 "~" H 8700 2700 50 0001 C CNN
|
||||
1 8700 2700
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:D_Zener D8
|
||||
U 1 1 608E7242
|
||||
P 9450 2700
|
||||
F 0 "D8" V 9404 2780 50 0000 L CNN
|
||||
F 1 "Z 12V" V 9495 2780 50 0000 L CNN
|
||||
F 2 "Diode_SMD:D_MiniMELF" H 9450 2700 50 0001 C CNN
|
||||
F 3 "~" H 9450 2700 50 0001 C CNN
|
||||
1 9450 2700
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+5V #PWR0138
|
||||
U 1 1 608EA16E
|
||||
P 8700 2400
|
||||
F 0 "#PWR0138" H 8700 2250 50 0001 C CNN
|
||||
F 1 "+5V" H 8715 2573 50 0000 C CNN
|
||||
F 2 "" H 8700 2400 50 0001 C CNN
|
||||
F 3 "" H 8700 2400 50 0001 C CNN
|
||||
1 8700 2400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+12V #PWR0139
|
||||
U 1 1 608EB6FB
|
||||
P 9450 2400
|
||||
F 0 "#PWR0139" H 9450 2250 50 0001 C CNN
|
||||
F 1 "+12V" H 9465 2573 50 0000 C CNN
|
||||
F 2 "" H 9450 2400 50 0001 C CNN
|
||||
F 3 "" H 9450 2400 50 0001 C CNN
|
||||
1 9450 2400
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0142
|
||||
U 1 1 608EC96E
|
||||
P 8700 3050
|
||||
F 0 "#PWR0142" H 8700 2800 50 0001 C CNN
|
||||
F 1 "GND" H 8705 2877 50 0000 C CNN
|
||||
F 2 "" H 8700 3050 50 0001 C CNN
|
||||
F 3 "" H 8700 3050 50 0001 C CNN
|
||||
1 8700 3050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR0143
|
||||
U 1 1 608ED499
|
||||
P 9450 3050
|
||||
F 0 "#PWR0143" H 9450 2800 50 0001 C CNN
|
||||
F 1 "GND" H 9455 2877 50 0000 C CNN
|
||||
F 2 "" H 9450 3050 50 0001 C CNN
|
||||
F 3 "" H 9450 3050 50 0001 C CNN
|
||||
1 9450 3050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
8700 2850 8700 3050
|
||||
Wire Wire Line
|
||||
9450 2850 9450 3050
|
||||
Wire Wire Line
|
||||
8700 2400 8700 2550
|
||||
Wire Wire Line
|
||||
9450 2400 9450 2550
|
||||
Text Label 4750 2450 0 50 ~ 0
|
||||
LDO_IN
|
||||
$Comp
|
||||
L Connector:Conn_01x01_Female J?
|
||||
U 1 1 6094781B
|
||||
P 2700 2200
|
||||
AR Path="/6094781B" Ref="J?" Part="1"
|
||||
AR Path="/6078273A/6094781B" Ref="J9" Part="1"
|
||||
F 0 "J9" H 2728 2226 50 0000 L CNN
|
||||
F 1 "Testpoint_3V3" H 2728 2135 50 0000 L CNN
|
||||
F 2 "TestPoint:TestPoint_Pad_D2.0mm" H 2700 2200 50 0001 C CNN
|
||||
F 3 "~" H 2700 2200 50 0001 C CNN
|
||||
1 2700 2200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+3.3V #PWR?
|
||||
U 1 1 60947821
|
||||
P 2500 2200
|
||||
AR Path="/60947821" Ref="#PWR?" Part="1"
|
||||
AR Path="/6078273A/60947821" Ref="#PWR0144" Part="1"
|
||||
F 0 "#PWR0144" H 2500 2050 50 0001 C CNN
|
||||
F 1 "+3.3V" H 2515 2373 50 0000 C CNN
|
||||
F 2 "" H 2500 2200 50 0001 C CNN
|
||||
F 3 "" H 2500 2200 50 0001 C CNN
|
||||
1 2500 2200
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Connector:Conn_01x01_Female J?
|
||||
U 1 1 60947827
|
||||
P 2700 2450
|
||||
AR Path="/60947827" Ref="J?" Part="1"
|
||||
AR Path="/6078273A/60947827" Ref="J10" Part="1"
|
||||
F 0 "J10" H 2728 2476 50 0000 L CNN
|
||||
F 1 "Testpoint_GND" H 2728 2385 50 0000 L CNN
|
||||
F 2 "TestPoint:TestPoint_Pad_D2.0mm" H 2700 2450 50 0001 C CNN
|
||||
F 3 "~" H 2700 2450 50 0001 C CNN
|
||||
1 2700 2450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:GND #PWR?
|
||||
U 1 1 6094782D
|
||||
P 2500 2450
|
||||
AR Path="/6094782D" Ref="#PWR?" Part="1"
|
||||
AR Path="/6078273A/6094782D" Ref="#PWR0145" Part="1"
|
||||
F 0 "#PWR0145" H 2500 2200 50 0001 C CNN
|
||||
F 1 "GND" H 2505 2277 50 0000 C CNN
|
||||
F 2 "" H 2500 2450 50 0001 C CNN
|
||||
F 3 "" H 2500 2450 50 0001 C CNN
|
||||
1 2500 2450
|
||||
0 1 1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L Connector:Conn_01x01_Female J?
|
||||
U 1 1 609480A1
|
||||
P 3900 2450
|
||||
AR Path="/609480A1" Ref="J?" Part="1"
|
||||
AR Path="/6078273A/609480A1" Ref="J11" Part="1"
|
||||
F 0 "J11" H 3792 2225 50 0000 C CNN
|
||||
F 1 "Testpoint_LDO_IN" H 3792 2316 50 0000 C CNN
|
||||
F 2 "TestPoint:TestPoint_Pad_D2.0mm" H 3900 2450 50 0001 C CNN
|
||||
F 3 "~" H 3900 2450 50 0001 C CNN
|
||||
1 3900 2450
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
4100 2450 4450 2450
|
||||
Connection ~ 4450 2450
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 609C4CDD
|
||||
P 6250 2700
|
||||
AR Path="/609C4CDD" Ref="C?" Part="1"
|
||||
AR Path="/6078273A/609C4CDD" Ref="C5" Part="1"
|
||||
F 0 "C5" H 6365 2746 50 0000 L CNN
|
||||
F 1 "10uF" H 6365 2655 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0805_2012Metric" H 6288 2550 50 0001 C CNN
|
||||
F 3 "~" H 6250 2700 50 0001 C CNN
|
||||
F 4 "C15850" H 6250 2700 50 0001 C CNN "LCSC"
|
||||
1 6250 2700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 609C54A2
|
||||
P 5050 4100
|
||||
AR Path="/609C54A2" Ref="C?" Part="1"
|
||||
AR Path="/6078273A/609C54A2" Ref="C2" Part="1"
|
||||
F 0 "C2" H 5165 4146 50 0000 L CNN
|
||||
F 1 "10uF" H 5165 4055 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0805_2012Metric" H 5088 3950 50 0001 C CNN
|
||||
F 3 "~" H 5050 4100 50 0001 C CNN
|
||||
F 4 "C15850" H 5050 4100 50 0001 C CNN "LCSC"
|
||||
1 5050 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Device:C C?
|
||||
U 1 1 609C5ABB
|
||||
P 7100 4100
|
||||
AR Path="/609C5ABB" Ref="C?" Part="1"
|
||||
AR Path="/6078273A/609C5ABB" Ref="C7" Part="1"
|
||||
F 0 "C7" H 7215 4146 50 0000 L CNN
|
||||
F 1 "10uF" H 7215 4055 50 0000 L CNN
|
||||
F 2 "Capacitor_SMD:C_0805_2012Metric" H 7138 3950 50 0001 C CNN
|
||||
F 3 "~" H 7100 4100 50 0001 C CNN
|
||||
F 4 "C15850" H 7100 4100 50 0001 C CNN "LCSC"
|
||||
1 7100 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2300 4100 2300 4200
|
||||
Wire Wire Line
|
||||
2400 4100 2300 4100
|
||||
$Comp
|
||||
L power:GND #PWR0105
|
||||
U 1 1 60929622
|
||||
P 2300 4200
|
||||
F 0 "#PWR0105" H 2300 3950 50 0001 C CNN
|
||||
F 1 "GND" H 2305 4027 50 0000 C CNN
|
||||
F 2 "" H 2300 4200 50 0001 C CNN
|
||||
F 3 "" H 2300 4200 50 0001 C CNN
|
||||
1 2300 4200
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Connector:Conn_01x03_Male J5
|
||||
U 1 1 60929628
|
||||
P 2600 3650
|
||||
F 0 "J5" H 2572 3582 50 0000 R CNN
|
||||
F 1 "Conn_01x03_Male" H 2572 3673 50 0000 R CNN
|
||||
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Horizontal" H 2600 3650 50 0001 C CNN
|
||||
F 3 "~" H 2600 3650 50 0001 C CNN
|
||||
1 2600 3650
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Connector:Conn_01x02_Male J12
|
||||
U 1 1 6092962E
|
||||
P 2600 4100
|
||||
F 0 "J12" H 2572 3982 50 0000 R CNN
|
||||
F 1 "Conn_01x02_Male" H 2572 4073 50 0000 R CNN
|
||||
F 2 "TerminalBlock:TerminalBlock_bornier-2_P5.08mm" H 2600 4100 50 0001 C CNN
|
||||
F 3 "~" H 2600 4100 50 0001 C CNN
|
||||
1 2600 4100
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
Text GLabel 2400 3650 0 50 Input ~ 0
|
||||
VOUT
|
||||
$Comp
|
||||
L power:+12V #PWR0123
|
||||
U 1 1 60929635
|
||||
P 2400 4000
|
||||
F 0 "#PWR0123" H 2400 3850 50 0001 C CNN
|
||||
F 1 "+12V" V 2415 4128 50 0000 L CNN
|
||||
F 2 "" H 2400 4000 50 0001 C CNN
|
||||
F 3 "" H 2400 4000 50 0001 C CNN
|
||||
1 2400 4000
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+12V #PWR0124
|
||||
U 1 1 6092963B
|
||||
P 2400 3550
|
||||
F 0 "#PWR0124" H 2400 3400 50 0001 C CNN
|
||||
F 1 "+12V" V 2415 3678 50 0000 L CNN
|
||||
F 2 "" H 2400 3550 50 0001 C CNN
|
||||
F 3 "" H 2400 3550 50 0001 C CNN
|
||||
1 2400 3550
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+5V #PWR?
|
||||
U 1 1 60929641
|
||||
P 2400 3750
|
||||
AR Path="/60929641" Ref="#PWR?" Part="1"
|
||||
AR Path="/6078273A/60929641" Ref="#PWR0125" Part="1"
|
||||
F 0 "#PWR0125" H 2400 3600 50 0001 C CNN
|
||||
F 1 "+5V" V 2415 3878 50 0000 L CNN
|
||||
F 2 "" H 2400 3750 50 0001 C CNN
|
||||
F 3 "" H 2400 3750 50 0001 C CNN
|
||||
1 2400 3750
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2250 4750 2250 4850
|
||||
Wire Wire Line
|
||||
2350 4750 2250 4750
|
||||
$Comp
|
||||
L power:GND #PWR0146
|
||||
U 1 1 60929649
|
||||
P 2250 4850
|
||||
F 0 "#PWR0146" H 2250 4600 50 0001 C CNN
|
||||
F 1 "GND" H 2255 4677 50 0000 C CNN
|
||||
F 2 "" H 2250 4850 50 0001 C CNN
|
||||
F 3 "" H 2250 4850 50 0001 C CNN
|
||||
1 2250 4850
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Connector:Conn_01x02_Male J3
|
||||
U 1 1 6092964F
|
||||
P 2550 4750
|
||||
F 0 "J3" H 2522 4632 50 0000 R CNN
|
||||
F 1 "Conn_01x02_Male" H 2522 4723 50 0000 R CNN
|
||||
F 2 "TerminalBlock:TerminalBlock_bornier-2_P5.08mm" H 2550 4750 50 0001 C CNN
|
||||
F 3 "~" H 2550 4750 50 0001 C CNN
|
||||
1 2550 4750
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+5V #PWR?
|
||||
U 1 1 60929655
|
||||
P 2350 4650
|
||||
AR Path="/60929655" Ref="#PWR?" Part="1"
|
||||
AR Path="/6078273A/60929655" Ref="#PWR0147" Part="1"
|
||||
F 0 "#PWR0147" H 2350 4500 50 0001 C CNN
|
||||
F 1 "+5V" V 2365 4778 50 0000 L CNN
|
||||
F 2 "" H 2350 4650 50 0001 C CNN
|
||||
F 3 "" H 2350 4650 50 0001 C CNN
|
||||
1 2350 4650
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:PWR_FLAG #FLG0101
|
||||
U 1 1 60A9BE5E
|
||||
P 1050 3800
|
||||
F 0 "#FLG0101" H 1050 3875 50 0001 C CNN
|
||||
F 1 "PWR_FLAG" H 1050 3973 50 0000 C CNN
|
||||
F 2 "" H 1050 3800 50 0001 C CNN
|
||||
F 3 "~" H 1050 3800 50 0001 C CNN
|
||||
1 1050 3800
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
$Comp
|
||||
L power:+12V #PWR0149
|
||||
U 1 1 60A9D3DB
|
||||
P 1050 3800
|
||||
F 0 "#PWR0149" H 1050 3650 50 0001 C CNN
|
||||
F 1 "+12V" V 1065 3928 50 0000 L CNN
|
||||
F 2 "" H 1050 3800 50 0001 C CNN
|
||||
F 3 "" H 1050 3800 50 0001 C CNN
|
||||
1 1050 3800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$EndSCHEMATC
|
||||
Loading…
Reference in a new issue