More LoadStoreErrorHandler performance improvements
This commit is contained in:
Alex Stewart
parent
f1bff97103
commit
b15d149b09
1 changed files with 102 additions and 105 deletions
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@ -58,9 +58,9 @@ KernelExceptionVector:
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.org 0x50
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.type UserExceptionVector, @function
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UserExceptionVector:
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wsr.excsave1 a0
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rsr.exccause a0
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beqi a0, CAUSE_LOADSTORE, LoadStoreErrorHandler
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wsr.excsave1 a1
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rsr.exccause a1
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beqi a1, CAUSE_LOADSTORE, LoadStoreErrorHandler
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j UserExceptionHandler
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.org 0x70
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@ -87,25 +87,15 @@ DoubleExceptionVector:
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.type LoadStoreErrorHandler, @function
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LoadStoreErrorHandler:
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# Note: we use a0 as our "stack pointer" here because it's already been
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# saved in UserExceptionVector, and we never call out to other routines
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# so we don't have to worry about it being clobbered. It would be
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# preferable to use a1 instead, but this would require changes to other
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# parts of UserExceptionHandler code which we haven't gotten around to
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# yet.
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# TODO: Eventually, switch everything over to saving a1 instead of a0
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# in UserExceptionVector so we can use the more mnemonic SP for this.
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# Note: registers are saved in the (regnum * 4) address so calculation
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# is easier later on. This means we don't use the first two entries
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# (since we don't save a0 or a1 here), so we just adjust the pointer in
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# a0 to pretend we have two extra slots at the beginning.
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movi a0, LoadStoreErrorHandlerStack - 8
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s32i a2, a0, 0x08
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s32i a3, a0, 0x0c
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s32i a4, a0, 0x10
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s32i a5, a0, 0x14
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rsr.sar a5 # Save SAR in a5 to restore later
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# Note: registers are saved in the address corresponding to their
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# register number times 4. This allows a quick and easy mapping later
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# on when needing to store the value to a particular register number.
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movi sp, LoadStoreErrorHandlerStack
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s32i a0, sp, 0
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s32i a2, sp, 0x08
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s32i a3, sp, 0x0c
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s32i a4, sp, 0x10
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rsr.sar a0 # Save SAR in a0 to restore later
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# Examine the opcode which generated the exception
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# Note: Instructions are in this order to avoid pipeline stalls.
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@ -143,11 +133,11 @@ LoadStoreErrorHandler:
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# At this point, a2 holds the faulting instruction and a4 holds the
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# correctly read value.
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# Restore original SAR value (saved in a5) and update EPC so we'll
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# Restore original SAR value (saved in a0) and update EPC so we'll
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# return back to the instruction following the one we just emulated
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# Note: Instructions are in this order to avoid pipeline stalls
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rsr.epc1 a3
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wsr.sar a5
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wsr.sar a0
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addi a3, a3, 0x3
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wsr.epc1 a3
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@ -162,34 +152,35 @@ LoadStoreErrorHandler:
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# needing any extra shift operations.
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extui a2, a2, 3, 5 /* a2 now destination register 0-15 times 2 */
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bgei a2, 12, .LSE_assign_reg # a6..a15 use jumptable
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blti a2, 4, .LSE_assign_reg # a0..a1 use jumptable
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bgei a2, 10, .LSE_assign_reg # a5..a15 use jumptable
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beqi a2, 2, .LSE_assign_a1 # a1 uses a special routine
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# We're storing into a2..a5, which are all saved in our "stack" area.
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# We're storing into a0 or a2..a4, which are all saved in our "stack" area.
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# Calculate the correct address and stick the value in there, then just
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# do our normal restore and RFE (no jumps required, which actually
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# makes a2..a5 substantially faster).
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addx2 a2, a2, a0
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# makes a0..a4 substantially faster).
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addx2 a2, a2, sp
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s32i a4, a2, 0
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# Restore all regs and return
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l32i a2, a0, 0x08
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l32i a3, a0, 0x0c
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l32i a4, a0, 0x10
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l32i a5, a0, 0x14
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rsr.excsave1 a0 # restore a0 saved by UserExceptionVector
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l32i a0, sp, 0
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l32i a2, sp, 0x08
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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rsr.excsave1 a1 # restore a1 saved by UserExceptionVector
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rfe
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.LSE_assign_reg:
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# At this point, a2 contains the register number times 2, a4 is the
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# read value.
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movi a3, .LSE_assign_jumptable
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addx8 a2, a2, a3 # a2 is now the address to jump to
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# Restore everything except a2 and a4
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l32i a3, a0, 0x0c
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l32i a5, a0, 0x14
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# Calculate the jumptable address, and restore regs except a2 and a4
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# so we have less to do after jumping.
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# Note: Instructions are in this order to avoid pipeline stalls.
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movi a3, .LSE_jumptable_base
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l32i a0, sp, 0
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addx8 a2, a2, a3 # a2 is now the address to jump to
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l32i a3, sp, 0x0c
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jx a2
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@ -226,105 +217,109 @@ LoadStoreErrorHandler:
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.LSE_wrong_opcode:
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# Restore registers so any dump the fatal exception routine produces
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# will have correct values
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wsr.sar a5 # Restore SAR saved in a5
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l32i a2, a0, 0x08
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l32i a3, a0, 0x0c
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l32i a4, a0, 0x10
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l32i a5, a0, 0x14
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wsr.sar a0 # Restore SAR saved in a0
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l32i a0, sp, 0
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l32i a2, sp, 0x08
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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rsr.excsave1 a1
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call0 sdk_user_fatal_exception_handler
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.balign 4
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.LSE_assign_jumptable:
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.org .LSE_assign_jumptable + (16 * 0)
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# a0 is saved in excsave1, so just update that with the value
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.LSE_assign_a1:
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# a1 is saved in excsave1, so just update that with the value
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wsr.excsave1 a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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# Restore all regs and return
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l32i a0, sp, 0
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l32i a2, sp, 0x08
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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rsr.excsave1 a1 # restore a1 saved by UserExceptionVector
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rfe
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.org .LSE_assign_jumptable + (16 * 1)
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mov a1, a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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.balign 4
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.LSE_jumptable:
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# The first 5 entries (80 bytes) of this table are unused (registers
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# a0..a4 are handled separately above). Rather than have a whole bunch
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# of wasted space, we just pretend that the table starts 80 bytes
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# earlier in memory.
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.set .LSE_jumptable_base, .LSE_jumptable - (16 * 5)
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.org .LSE_jumptable_base + (16 * 5)
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mov a5, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr.excsave1 a1
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rfe
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# NOTE: Opcodes a2 .. a5 are not handled by the jumptable routines
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# (they're taken care of directly in .LSE_post_fetch above)
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# This leaves 64 bytes of wasted space here. We could fill it with
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# other things, but that would just make it harder to understand what's
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# going on, and that's bad enough with this routine already. Even on
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# the ESP8266, 64 bytes of IRAM wasted aren't the end of the world..
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.org .LSE_assign_jumptable + (16 * 6)
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.org .LSE_jumptable_base + (16 * 6)
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mov a6, a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr.excsave1 a1
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rfe
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.org .LSE_assign_jumptable + (16 * 7)
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.org .LSE_jumptable_base + (16 * 7)
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mov a7, a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr.excsave1 a1
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rfe
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.org .LSE_assign_jumptable + (16 * 8)
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.org .LSE_jumptable_base + (16 * 8)
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mov a8, a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr.excsave1 a1
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rfe
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.org .LSE_assign_jumptable + (16 * 9)
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.org .LSE_jumptable_base + (16 * 9)
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mov a9, a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr.excsave1 a1
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rfe
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.org .LSE_assign_jumptable + (16 * 10)
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.org .LSE_jumptable_base + (16 * 10)
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mov a10, a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr.excsave1 a1
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rfe
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.org .LSE_assign_jumptable + (16 * 11)
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.org .LSE_jumptable_base + (16 * 11)
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mov a11, a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr.excsave1 a1
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rfe
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.org .LSE_assign_jumptable + (16 * 12)
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.org .LSE_jumptable_base + (16 * 12)
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mov a12, a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr.excsave1 a1
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rfe
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.org .LSE_assign_jumptable + (16 * 13)
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.org .LSE_jumptable_base + (16 * 13)
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mov a13, a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr.excsave1 a1
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rfe
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.org .LSE_assign_jumptable + (16 * 14)
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.org .LSE_jumptable_base + (16 * 14)
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mov a14, a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr.excsave1 a1
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rfe
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.org .LSE_assign_jumptable + (16 * 15)
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.org .LSE_jumptable_base + (16 * 15)
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mov a15, a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr.excsave1 a1
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rfe
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/* End of LoadStoreErrorHandler */
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@ -337,10 +332,11 @@ NMIRegisterSaved: /* register space for saving NMI registers */
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.skip 4*(16 + 6)
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LoadStoreErrorHandlerStack:
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.word 0 # a0
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.word 0 # (unused)
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.word 0 # a2
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.word 0 # a3
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.word 0 # a4
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.word 0 # a5
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/* Save register relative to a0 */
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.macro SAVE_REG register, regnum
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@ -439,7 +435,8 @@ CallNMIExceptionHandler:
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.type UserExceptionHandler, @function
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UserExceptionHandler:
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mov a0, sp /* a0 was saved by UserExceptionVector */
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xsr.excsave1 a0 # a0 now contains sp
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mov sp, a0
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addi sp, sp, -0x50
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s32i a0, sp, 0x10
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rsr.ps a0
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