Further optimizations for LoadStoreErrorHandler
This commit is contained in:
Alex Stewart
parent
a3d7732da8
commit
f1bff97103
2 changed files with 268 additions and 200 deletions
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@ -1,190 +0,0 @@
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/* Xtensa Exception unaligned load handler
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Completes l8/l16 load instructions from Instruction address space,
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that the architecture require to be 4 byte aligned word reads.
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Called from either UserExceptionVector or DoubleExceptionVector
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depending on where the exception happened.
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Fast path (no branches) is for l8ui.
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Part of esp-open-rtos
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Copyright (C) Angus Gratton
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BSD Licensed as described in the file LICENSE
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*/
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.text
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.section .vecbase.text, "x"
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.literal_position
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/* "Fix" LoadStoreException exceptions that are l8/l16 from an Instruction region,
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normal exception variant. */
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UserExceptionLoadStoreHandler:
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addi sp, sp, -0x18
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s32i a2, sp, 0x08
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rsr.epc1 a2
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/* Inner UserLoadStoreExceptionHandler handlers. Works for both level1 & level 2 interrupt level.
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*
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* Called from level-specific handler above which sets up stack and loads epcX into a2.
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*/
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InnerLoadStoreExceptionHandler:
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s32i a3, sp, 0x0c
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s32i a4, sp, 0x10
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s32i a5, sp, 0x14
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rsr.sar a0 // save sar in a0
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/* Examine the instruction we failed to execute (in a2) */
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ssa8l a2 // sar is now correct shift for aligned read
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movi a3, ~3
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and a2, a2, a3 // a2 now 4-byte aligned address of instruction
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l32i a3, a2, 0
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l32i a4, a2, 4
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src a2, a4, a3 // a2 now instruction that failed
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/* check for l8ui opcode 0x000002, or branch to check l16 */
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movi a3, 0x00700F /* opcode mask for l8ui/l16si/l16ui */
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and a3, a2, a3
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bnei a3, 0x000002, .Lcheck_fix_16bit
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movi a5, 0xFF
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.Lcan_fix:
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/* verified an 8- or 16-bit read
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a2 holds instruction, a5 holds mask to apply to read value
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*/
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rsr.excvaddr a3 // read faulting address
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ssa8l a3 /* sar is now shift to extract a3's byte */
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movi a4, ~3
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and a3, a3, a4 /* a3 now word aligned read address */
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l32i a3, a3, 0 /* perform the actual read */
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srl a3, a3 /* shift right correct distance */
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and a4, a3, a5 /* mask off bits we need for an l8/l16 */
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bbsi a5, 14, .Lmaybe_extend_sign
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.Lafter_extend_sign:
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/* a2 holds instruction, a4 holds the correctly read value */
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extui a2, a2, 4, 4 /* a2 now destination register 0-15 */
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/* test if a4 needs to be written directly to a register (ie not a working register) */
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bgei a2, 6, .Lwrite_value_direct_reg
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/* test if a4 needs to be written to a0 */
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beqz a2, .Lwrite_value_a0_reg
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/* otherwise, a4 can be written to a saved working register 'slot' on the stack */
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addx4 a5, a2, sp
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s32i a4, a5, 0
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.Lafter_write_value:
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/* test PS.INTLEVEL (1=User, 2=Double) to see which interrupt level we restore from
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*/
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rsr.ps a2
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bbsi a2, 1, .Lincrement_PC_intlevel2
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.Lincrement_PC_intlevel1:
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rsr.epc1 a2
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addi a3, a2, 0x3
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wsr.epc1 a3
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wsr.sar a0 // restore saved sar
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rsr.excsave1 a0 // restore a0 saved in exception vector
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.Lafter_increment_PC:
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// Restore registers
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l32i a2, sp, 0x08
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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l32i a5, sp, 0x14
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addi sp, sp, 0x18
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rfe
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/* Check the load instruction a2 for an l16si/16ui instruction
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First test for a signed vs unsigned load.
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a2 is the instruction, need to load a5 with the mask to use */
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.Lcheck_fix_16bit:
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movi a4, 0x001002 /* l16si or l16ui opcode after masking */
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bne a3, a4, .Lcant_fix
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bbsi a2, 15, .Lcan_fix_16bit_signed
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movi a5, 0xFFFF
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j .Lcan_fix
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.Lcan_fix_16bit_signed:
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movi a5, 0x7FFF
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j .Lcan_fix
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/* not an opcode we can try to fix, so bomb out
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TODO: the exception dump will have some wrong values in it */
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.Lcant_fix:
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call0 sdk_user_fatal_exception_handler
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/* increment PC for a DoubleException */
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.Lincrement_PC_intlevel2:
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rsr.epc2 a2
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addi a3, a2, 0x3
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wsr.epc2 a3
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wsr.sar a0 // restore saved sar
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rsr.excsave2 a0 // restore a0 saved in exception vector
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j .Lafter_increment_PC
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.Lmaybe_extend_sign: /* apply 16-bit sign extension if necessary
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a3 holds raw value, a4 holds masked */
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bbsi a5, 15, .Lafter_extend_sign /* 16-bit unsigned, no sign extension */
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bbci a3, 15, .Lafter_extend_sign /* sign bit not set, no sign extension */
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movi a3, 0xFFFF8000
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or a4, a3, a4 /* set 32-bit sign bits */
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j .Lafter_extend_sign
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.Lwrite_value_direct_reg:
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/* Directly update register index a2, in range 6-15, using value in a4 */
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addi a2, a2, -6
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slli a2, a2, 3 /* offset from a6, x8 */
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movi a3, .Ldirect_reg_jumptable
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add a2, a2, a3
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jx a2
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.align 8
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.Ldirect_reg_jumptable:
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mov a6, a4
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j .Lafter_write_value
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.align 8
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mov a7, a4
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j .Lafter_write_value
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.align 8
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mov a8, a4
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j .Lafter_write_value
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.align 8
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mov a9, a4
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j .Lafter_write_value
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.align 8
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mov a10, a4
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j .Lafter_write_value
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.align 8
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mov a11, a4
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j .Lafter_write_value
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.align 8
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mov a12, a4
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j .Lafter_write_value
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.align 8
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mov a13, a4
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j .Lafter_write_value
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.align 8
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mov a14, a4
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j .Lafter_write_value
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.align 8
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mov a15, a4
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j .Lafter_write_value
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.Lwrite_value_a0_reg:
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/* a0 is saved in excsave1,so just update this with value
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TODO: This won't work with interrupt level 2
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*/
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wsr.excsave1 a4
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j .Lafter_write_value
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.literal_position
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/* "Fix" LoadStoreException exceptions that are l8/l16 from an Instruction region,
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DoubleException exception variant (ie load happened in a level1 exception handler). */
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DoubleExceptionLoadStoreHandler:
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addi sp, sp, -0x18
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s32i a2, sp, 0x08
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rsr.epc2 a2
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j InnerLoadStoreExceptionHandler
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/* End of InnerUserLoadStoreExceptionHandler */
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@ -26,7 +26,6 @@
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.text
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.section .vecbase.text, "x"
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.global VecBase
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.type VecBase, @function /* it's not really a function, but treat it like one */
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.org 0
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VecBase:
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/* IMPORTANT: exception vector literals will go here, but we
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@ -36,35 +35,38 @@ VecBase:
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*/
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.literal_position
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.org 0x10
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.type DebugExceptionVector, @function
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DebugExceptionVector:
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wsr.excsave2 a0
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call0 sdk_user_fatal_exception_handler
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rfi 2
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.org 0x20
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.type NMIExceptionVector, @function
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NMIExceptionVector:
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wsr.excsave3 a0
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call0 CallNMIExceptionHandler
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rfi 3 /* CallNMIExceptionHandler should call rfi itself */
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.org 0x30
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.type KernelExceptionVector, @function
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KernelExceptionVector:
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break 1, 0
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call0 sdk_user_fatal_exception_handler
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rfe
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.org 0x50
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.type UserExceptionVector, @function
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UserExceptionVector:
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wsr.excsave1 a0
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rsr.exccause a0
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beqi a0, CAUSE_LOADSTORE, UserExceptionLoadStoreHandler
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beqi a0, CAUSE_LOADSTORE, LoadStoreErrorHandler
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j UserExceptionHandler
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.org 0x70
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.type DoubleExceptionVector, @function
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DoubleExceptionVector:
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break 1, 4
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rsr.exccause a0
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beqi a0, CAUSE_LOADSTORE, DoubleExceptionLoadStoreHandler
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call0 sdk_user_fatal_exception_handler
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/* Reset vector would go here at offset 0x80 but should be unused,
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@ -72,10 +74,260 @@ DoubleExceptionVector:
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/***** end of exception vectors *****/
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/* We include this here so UserExceptionLoadStoreHandler is within
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the range of a 'beq' instruction jump.
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/* Xtensa Exception unaligned load handler
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Completes l8/l16 load instructions from Instruction address space,
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for which the architecture only supports 32-bit reads.
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Called from UserExceptionVector if EXCCAUSE is LoadStoreErrorCause
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Fast path (no branches) is for l8ui.
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*/
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#include "exception_unaligned_load.S.inc"
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.literal_position
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.type LoadStoreErrorHandler, @function
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LoadStoreErrorHandler:
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# Note: we use a0 as our "stack pointer" here because it's already been
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# saved in UserExceptionVector, and we never call out to other routines
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# so we don't have to worry about it being clobbered. It would be
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# preferable to use a1 instead, but this would require changes to other
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# parts of UserExceptionHandler code which we haven't gotten around to
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# yet.
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# TODO: Eventually, switch everything over to saving a1 instead of a0
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# in UserExceptionVector so we can use the more mnemonic SP for this.
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# Note: registers are saved in the (regnum * 4) address so calculation
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# is easier later on. This means we don't use the first two entries
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# (since we don't save a0 or a1 here), so we just adjust the pointer in
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# a0 to pretend we have two extra slots at the beginning.
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movi a0, LoadStoreErrorHandlerStack - 8
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s32i a2, a0, 0x08
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s32i a3, a0, 0x0c
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s32i a4, a0, 0x10
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s32i a5, a0, 0x14
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rsr.sar a5 # Save SAR in a5 to restore later
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# Examine the opcode which generated the exception
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# Note: Instructions are in this order to avoid pipeline stalls.
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rsr.epc1 a2
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movi a3, ~3
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ssa8l a2 // sar is now correct shift for aligned read
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and a2, a2, a3 // a2 now 4-byte aligned address of instruction
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l32i a4, a2, 0
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l32i a2, a2, 4
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movi a3, 0x00700F // opcode mask for l8ui/l16si/l16ui
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src a2, a2, a4 // a2 now instruction that failed
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and a3, a2, a3
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bnei a3, 0x000002, .LSE_check_l16
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# Note: At this point, opcode could technically be one of two things:
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# xx0xx2 (L8UI)
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# xx8xx2 (Reserved (invalid) opcode)
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# It is assumed that we'll never get to this point from an illegal
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# opcode, so we don't bother to check for that case and presume this is
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# always an L8UI.
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/* a2 holds instruction */
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movi a4, ~3
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rsr.excvaddr a3 // read faulting address
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and a4, a3, a4 /* a4 now word aligned read address */
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l32i a4, a4, 0 /* perform the actual read */
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ssa8l a3 /* sar is now shift to extract a3's byte */
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srl a3, a4 /* shift right correct distance */
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extui a4, a3, 0, 8 /* mask off bits we need for an l8 */
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.LSE_post_fetch:
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# We jump back here after either the L8UI or the L16*I routines do the
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# necessary work to read the value from memory.
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# At this point, a2 holds the faulting instruction and a4 holds the
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# correctly read value.
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# Restore original SAR value (saved in a5) and update EPC so we'll
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# return back to the instruction following the one we just emulated
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# Note: Instructions are in this order to avoid pipeline stalls
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rsr.epc1 a3
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wsr.sar a5
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addi a3, a3, 0x3
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wsr.epc1 a3
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# Stupid opcode tricks: The jumptable we use later on needs 16 bytes
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# per entry (so we can avoid a second jump by just doing a RFE inside
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# each entry). Unfortunately, however, Xtensa doesn't have an addx16
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# operation to make that easy for us. Luckily, all of the faulting
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# opcodes we're processing are guaranteed to have bit 3 be zero, which
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# means if we just shift the register bits of the opcode down by 3
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# instead of 4, we will get the register number multiplied by 2. This
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# combined with an addx8 will give us an effective addx16 without
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# needing any extra shift operations.
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extui a2, a2, 3, 5 /* a2 now destination register 0-15 times 2 */
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bgei a2, 12, .LSE_assign_reg # a6..a15 use jumptable
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blti a2, 4, .LSE_assign_reg # a0..a1 use jumptable
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# We're storing into a2..a5, which are all saved in our "stack" area.
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# Calculate the correct address and stick the value in there, then just
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# do our normal restore and RFE (no jumps required, which actually
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# makes a2..a5 substantially faster).
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addx2 a2, a2, a0
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s32i a4, a2, 0
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# Restore all regs and return
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l32i a2, a0, 0x08
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l32i a3, a0, 0x0c
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l32i a4, a0, 0x10
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l32i a5, a0, 0x14
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rsr.excsave1 a0 # restore a0 saved by UserExceptionVector
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rfe
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.LSE_assign_reg:
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# At this point, a2 contains the register number times 2, a4 is the
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# read value.
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movi a3, .LSE_assign_jumptable
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addx8 a2, a2, a3 # a2 is now the address to jump to
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# Restore everything except a2 and a4
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l32i a3, a0, 0x0c
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l32i a5, a0, 0x14
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jx a2
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/* Check the load instruction a2 for an l16si/16ui instruction
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a2 is the instruction, a3 is masked instruction */
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.balign 4
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.LSE_check_l16:
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movi a4, 0x001002 /* l16si or l16ui opcode after masking */
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bne a3, a4, .LSE_wrong_opcode
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# Note: At this point, the opcode could be one of two things:
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# xx1xx2 (L16UI)
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# xx9xx2 (L16SI)
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# Both of these we can handle.
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movi a4, ~3
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rsr.excvaddr a3 // read faulting address
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and a4, a3, a4 /* a4 now word aligned read address */
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l32i a4, a4, 0 /* perform the actual read */
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ssa8l a3 /* sar is now shift to extract a3's byte */
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srl a3, a4 /* shift right correct distance */
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extui a4, a3, 0, 16 /* mask off bits we need for an l16 */
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bbci a2, 15, .LSE_post_fetch # Not a signed op
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bbci a4, 15, .LSE_post_fetch # Value does not require sign-extension
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movi a3, 0xFFFF0000
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or a4, a3, a4 /* set 32-bit sign bits */
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j .LSE_post_fetch
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/* If we got here it's not an opcode we can try to fix, so bomb out */
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.LSE_wrong_opcode:
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# Restore registers so any dump the fatal exception routine produces
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# will have correct values
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wsr.sar a5 # Restore SAR saved in a5
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l32i a2, a0, 0x08
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l32i a3, a0, 0x0c
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l32i a4, a0, 0x10
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l32i a5, a0, 0x14
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call0 sdk_user_fatal_exception_handler
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.balign 4
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.LSE_assign_jumptable:
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.org .LSE_assign_jumptable + (16 * 0)
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# a0 is saved in excsave1, so just update that with the value
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wsr.excsave1 a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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rfe
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.org .LSE_assign_jumptable + (16 * 1)
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mov a1, a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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rfe
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# NOTE: Opcodes a2 .. a5 are not handled by the jumptable routines
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# (they're taken care of directly in .LSE_post_fetch above)
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# This leaves 64 bytes of wasted space here. We could fill it with
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# other things, but that would just make it harder to understand what's
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# going on, and that's bad enough with this routine already. Even on
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# the ESP8266, 64 bytes of IRAM wasted aren't the end of the world..
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.org .LSE_assign_jumptable + (16 * 6)
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mov a6, a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
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rsr.excsave1 a0
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rfe
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.org .LSE_assign_jumptable + (16 * 7)
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mov a7, a4
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l32i a2, a0, 0x08
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l32i a4, a0, 0x10
|
||||
rsr.excsave1 a0
|
||||
rfe
|
||||
|
||||
.org .LSE_assign_jumptable + (16 * 8)
|
||||
mov a8, a4
|
||||
l32i a2, a0, 0x08
|
||||
l32i a4, a0, 0x10
|
||||
rsr.excsave1 a0
|
||||
rfe
|
||||
|
||||
.org .LSE_assign_jumptable + (16 * 9)
|
||||
mov a9, a4
|
||||
l32i a2, a0, 0x08
|
||||
l32i a4, a0, 0x10
|
||||
rsr.excsave1 a0
|
||||
rfe
|
||||
|
||||
.org .LSE_assign_jumptable + (16 * 10)
|
||||
mov a10, a4
|
||||
l32i a2, a0, 0x08
|
||||
l32i a4, a0, 0x10
|
||||
rsr.excsave1 a0
|
||||
rfe
|
||||
|
||||
.org .LSE_assign_jumptable + (16 * 11)
|
||||
mov a11, a4
|
||||
l32i a2, a0, 0x08
|
||||
l32i a4, a0, 0x10
|
||||
rsr.excsave1 a0
|
||||
rfe
|
||||
|
||||
.org .LSE_assign_jumptable + (16 * 12)
|
||||
mov a12, a4
|
||||
l32i a2, a0, 0x08
|
||||
l32i a4, a0, 0x10
|
||||
rsr.excsave1 a0
|
||||
rfe
|
||||
|
||||
.org .LSE_assign_jumptable + (16 * 13)
|
||||
mov a13, a4
|
||||
l32i a2, a0, 0x08
|
||||
l32i a4, a0, 0x10
|
||||
rsr.excsave1 a0
|
||||
rfe
|
||||
|
||||
.org .LSE_assign_jumptable + (16 * 14)
|
||||
mov a14, a4
|
||||
l32i a2, a0, 0x08
|
||||
l32i a4, a0, 0x10
|
||||
rsr.excsave1 a0
|
||||
rfe
|
||||
|
||||
.org .LSE_assign_jumptable + (16 * 15)
|
||||
mov a15, a4
|
||||
l32i a2, a0, 0x08
|
||||
l32i a4, a0, 0x10
|
||||
rsr.excsave1 a0
|
||||
rfe
|
||||
|
||||
/* End of LoadStoreErrorHandler */
|
||||
|
||||
.section .bss
|
||||
NMIHandlerStack: /* stack space for NMI handler */
|
||||
|
|
@ -84,6 +336,12 @@ NMIHandlerStack: /* stack space for NMI handler */
|
|||
NMIRegisterSaved: /* register space for saving NMI registers */
|
||||
.skip 4*(16 + 6)
|
||||
|
||||
LoadStoreErrorHandlerStack:
|
||||
.word 0 # a2
|
||||
.word 0 # a3
|
||||
.word 0 # a4
|
||||
.word 0 # a5
|
||||
|
||||
/* Save register relative to a0 */
|
||||
.macro SAVE_REG register, regnum
|
||||
s32i \register, a0, (0x20 + 4 * \regnum)
|
||||
|
|
@ -181,7 +439,7 @@ CallNMIExceptionHandler:
|
|||
|
||||
.type UserExceptionHandler, @function
|
||||
UserExceptionHandler:
|
||||
mov a0, sp /* a0 was saved in UserExceptionVector */
|
||||
mov a0, sp /* a0 was saved by UserExceptionVector */
|
||||
addi sp, sp, -0x50
|
||||
s32i a0, sp, 0x10
|
||||
rsr.ps a0
|
||||
|
|
@ -214,7 +472,7 @@ UserHandleTimer:
|
|||
and a3, a2, a3 /* a3 = a2 & 0xFFBF, ie remove 0x40 from a2 if set */
|
||||
bnez a3, UserTimerDone /* bits other than 0x40 are set */
|
||||
movi a3, 0x40
|
||||
sub a12, a2, a3 /* a12 - a2 - 0x40 - I think a12 _must_ be zero here? */
|
||||
sub a12, a2, a3 /* a12 = a2 - 0x40 -- Will be zero if bit 6 set */
|
||||
call0 sdk__xt_timer_int /* tick timer interrupt */
|
||||
mov a2, a12 /* restore a2 from a12, ie zero */
|
||||
beqz a2, UserIntDone
|
||||
|
|
@ -226,7 +484,7 @@ UserIntDone:
|
|||
break 1, 1 /* non-zero remnant in a2 means fail */
|
||||
call0 sdk_user_fatal_exception_handler
|
||||
UserIntExit:
|
||||
call0 sdk__xt_int_exit /* calls rfi */
|
||||
call0 sdk__xt_int_exit /* jumps to _xt_user_exit. Never returns here */
|
||||
|
||||
/* _xt_user_exit is used to exit interrupt context.
|
||||
TODO: Find a better place for this to live.
|
||||
|
|
|
|||
Loading…
Reference in a new issue