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First batch of opensdk additions

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Replacements for:
    libmain/misc.o
    libmain/os_cpu_a.o
    libmain/spi_flash.o
    libmain/timers.o
    libmain/uart.o
    libmain/xtensa_context.o
This commit is contained in:
Alex Stewart 2015-10-10 21:56:11 -07:00 • committed by Angus Gratton
parent 78c5b43a40
commit 2ecbf1d584
14 changed files with 642 additions and 44 deletions
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17
core/include/esp/rom.h
View file

@ -5,7 +5,9 @@
*/
#ifndef _ESP_ROM_H
#define _ESP_ROM_H
#include <stdint.h>
#include "esp/types.h"
#include "flashchip.h"
#ifdef __cplusplus
extern "C" {
@ -21,8 +23,19 @@ void Cache_Read_Disable(void);
*/
void Cache_Read_Enable(uint32_t odd_even, uint32_t mb_count, uint32_t no_idea);
/* Low-level SPI flash read/write routines */
int Enable_QMode(sdk_flashchip_t *chip);
int Disable_QMode(sdk_flashchip_t *chip);
int SPI_page_program(sdk_flashchip_t *chip, uint32_t dest_addr, uint32_t *src_addr, uint32_t size);
int SPI_read_data(sdk_flashchip_t *chip, uint32_t src_addr, uint32_t *dest_addr, uint32_t size);
int SPI_write_enable(sdk_flashchip_t *chip);
int SPI_sector_erase(sdk_flashchip_t *chip, uint32_t addr);
int SPI_read_status(sdk_flashchip_t *chip, uint32_t *status);
int SPI_write_status(sdk_flashchip_t *chip, uint32_t status);
int Wait_SPI_Idle(sdk_flashchip_t *chip);
#ifdef __cplusplus
}
#endif
#endif
#endif /* _ESP_ROM_H */

30
core/include/esp/spi_regs.h
View file

@ -46,22 +46,7 @@ struct SPI_REGS {
uint32_t volatile SLAVE1; // 0x34
uint32_t volatile SLAVE2; // 0x38
uint32_t volatile SLAVE3; // 0x3c
uint32_t volatile W0; // 0x40
uint32_t volatile W1; // 0x44
uint32_t volatile W2; // 0x48
uint32_t volatile W3; // 0x4c
uint32_t volatile W4; // 0x50
uint32_t volatile W5; // 0x54
uint32_t volatile W6; // 0x58
uint32_t volatile W7; // 0x5c
uint32_t volatile W8; // 0x60
uint32_t volatile W9; // 0x64
uint32_t volatile W10; // 0x68
uint32_t volatile W11; // 0x6c
uint32_t volatile W12; // 0x70
uint32_t volatile W13; // 0x74
uint32_t volatile W14; // 0x78
uint32_t volatile W15; // 0x7c
uint32_t volatile W[16]; // 0x40 - 0x7c
uint32_t volatile _unused[28]; // 0x80 - 0xec
uint32_t volatile EXT0; // 0xf0
uint32_t volatile EXT1; // 0xf4
@ -73,6 +58,19 @@ _Static_assert(sizeof(struct SPI_REGS) == 0x100, "SPI_REGS is the wrong size");
/* Details for CMD register */
#define SPI_CMD_READ BIT(31)
#define SPI_CMD_WRITE_ENABLE BIT(30)
#define SPI_CMD_WRITE_DISABLE BIT(29)
#define SPI_CMD_READ_ID BIT(28)
#define SPI_CMD_READ_SR BIT(27)
#define SPI_CMD_WRITE_SR BIT(26)
#define SPI_CMD_PP BIT(25)
#define SPI_CMD_SE BIT(24)
#define SPI_CMD_BE BIT(23)
#define SPI_CMD_CE BIT(22)
#define SPI_CMD_DP BIT(21)
#define SPI_CMD_RES BIT(20)
#define SPI_CMD_HPM BIT(19)
#define SPI_CMD_USR BIT(18)
/* Details for CTRL0 register */

39
core/include/flashchip.h Normal file
View file

@ -0,0 +1,39 @@
/* flashchip.h
*
* sdk_flashchip_t structure used by the SDK and some bootrom routines
*
* This is in a separate include file because it's referenced by several other
* headers which are otherwise independent of each other.
*
* Part of esp-open-rtos
* Copyright (C) 2015 Alex Stewart and Angus Gratton
* BSD Licensed as described in the file LICENSE
*/
#ifndef _FLASHCHIP_H
#define _FLASHCHIP_H
/* SDK/bootrom uses this structure internally to account for flash size.
chip_size field is initialised during startup from the flash size
saved in the image header (on the first 8 bytes of SPI flash).
Other field are initialised to hardcoded values by the SDK.
** NOTE: This structure is passed to some bootrom routines and is therefore
fixed. Be very careful if you want to change it that you do not break
things. **
Based on RE work by @foogod at
http://esp8266-re.foogod.com/wiki/Flashchip_%28IoT_RTOS_SDK_0.9.9%29
*/
typedef struct {
uint32_t device_id;
uint32_t chip_size; /* in bytes */
uint32_t block_size; /* in bytes */
uint32_t sector_size; /* in bytes */
uint32_t page_size; /* in bytes */
uint32_t status_mask;
} sdk_flashchip_t;
#endif /* _FLASHCHIP_H */

13
core/include/xtensa_ops.h
View file

@ -11,9 +11,6 @@
#ifndef _XTENSA_OPS_H
#define _XTENSA_OPS_H
// GCC macros for reading, writing, and exchanging Xtensa processor special
// registers:
/* Read stack pointer to variable.
*
* Note that the compiler will push a stack frame (minimum 16 bytes)
@ -28,8 +25,18 @@
*/
#define RETADDR(var) asm volatile ("mov %0, a0" : "=r" (var))
// GCC macros for reading, writing, and exchanging Xtensa processor special
// registers:
#define RSR(var, reg) asm volatile ("rsr %0, " #reg : "=r" (var));
#define WSR(var, reg) asm volatile ("wsr %0, " #reg : : "r" (var));
#define XSR(var, reg) asm volatile ("xsr %0, " #reg : "+r" (var));
// GCC macros for performing associated "*sync" opcodes
#define ISYNC() asm volatile ( "isync" )
#define RSYNC() asm volatile ( "rsync" )
#define ESYNC() asm volatile ( "esync" )
#define DSYNC() asm volatile ( "dsync" )
#endif /* _XTENSA_OPS_H */