diff --git a/core/include/esp/rom.h b/core/include/esp/rom.h index c2f8759..5c41e46 100644 --- a/core/include/esp/rom.h +++ b/core/include/esp/rom.h @@ -5,7 +5,9 @@ */ #ifndef _ESP_ROM_H #define _ESP_ROM_H -#include + +#include "esp/types.h" +#include "flashchip.h" #ifdef __cplusplus extern "C" { @@ -21,8 +23,19 @@ void Cache_Read_Disable(void); */ void Cache_Read_Enable(uint32_t odd_even, uint32_t mb_count, uint32_t no_idea); +/* Low-level SPI flash read/write routines */ +int Enable_QMode(sdk_flashchip_t *chip); +int Disable_QMode(sdk_flashchip_t *chip); +int SPI_page_program(sdk_flashchip_t *chip, uint32_t dest_addr, uint32_t *src_addr, uint32_t size); +int SPI_read_data(sdk_flashchip_t *chip, uint32_t src_addr, uint32_t *dest_addr, uint32_t size); +int SPI_write_enable(sdk_flashchip_t *chip); +int SPI_sector_erase(sdk_flashchip_t *chip, uint32_t addr); +int SPI_read_status(sdk_flashchip_t *chip, uint32_t *status); +int SPI_write_status(sdk_flashchip_t *chip, uint32_t status); +int Wait_SPI_Idle(sdk_flashchip_t *chip); + #ifdef __cplusplus } #endif -#endif +#endif /* _ESP_ROM_H */ diff --git a/core/include/esp/spi_regs.h b/core/include/esp/spi_regs.h index 37eb113..83b61af 100644 --- a/core/include/esp/spi_regs.h +++ b/core/include/esp/spi_regs.h @@ -46,22 +46,7 @@ struct SPI_REGS { uint32_t volatile SLAVE1; // 0x34 uint32_t volatile SLAVE2; // 0x38 uint32_t volatile SLAVE3; // 0x3c - uint32_t volatile W0; // 0x40 - uint32_t volatile W1; // 0x44 - uint32_t volatile W2; // 0x48 - uint32_t volatile W3; // 0x4c - uint32_t volatile W4; // 0x50 - uint32_t volatile W5; // 0x54 - uint32_t volatile W6; // 0x58 - uint32_t volatile W7; // 0x5c - uint32_t volatile W8; // 0x60 - uint32_t volatile W9; // 0x64 - uint32_t volatile W10; // 0x68 - uint32_t volatile W11; // 0x6c - uint32_t volatile W12; // 0x70 - uint32_t volatile W13; // 0x74 - uint32_t volatile W14; // 0x78 - uint32_t volatile W15; // 0x7c + uint32_t volatile W[16]; // 0x40 - 0x7c uint32_t volatile _unused[28]; // 0x80 - 0xec uint32_t volatile EXT0; // 0xf0 uint32_t volatile EXT1; // 0xf4 @@ -73,6 +58,19 @@ _Static_assert(sizeof(struct SPI_REGS) == 0x100, "SPI_REGS is the wrong size"); /* Details for CMD register */ +#define SPI_CMD_READ BIT(31) +#define SPI_CMD_WRITE_ENABLE BIT(30) +#define SPI_CMD_WRITE_DISABLE BIT(29) +#define SPI_CMD_READ_ID BIT(28) +#define SPI_CMD_READ_SR BIT(27) +#define SPI_CMD_WRITE_SR BIT(26) +#define SPI_CMD_PP BIT(25) +#define SPI_CMD_SE BIT(24) +#define SPI_CMD_BE BIT(23) +#define SPI_CMD_CE BIT(22) +#define SPI_CMD_DP BIT(21) +#define SPI_CMD_RES BIT(20) +#define SPI_CMD_HPM BIT(19) #define SPI_CMD_USR BIT(18) /* Details for CTRL0 register */ diff --git a/core/include/flashchip.h b/core/include/flashchip.h new file mode 100644 index 0000000..c14d4a3 --- /dev/null +++ b/core/include/flashchip.h @@ -0,0 +1,39 @@ +/* flashchip.h + * + * sdk_flashchip_t structure used by the SDK and some bootrom routines + * + * This is in a separate include file because it's referenced by several other + * headers which are otherwise independent of each other. + * + * Part of esp-open-rtos + * Copyright (C) 2015 Alex Stewart and Angus Gratton + * BSD Licensed as described in the file LICENSE + */ + +#ifndef _FLASHCHIP_H +#define _FLASHCHIP_H + +/* SDK/bootrom uses this structure internally to account for flash size. + + chip_size field is initialised during startup from the flash size + saved in the image header (on the first 8 bytes of SPI flash). + + Other field are initialised to hardcoded values by the SDK. + + ** NOTE: This structure is passed to some bootrom routines and is therefore + fixed. Be very careful if you want to change it that you do not break + things. ** + + Based on RE work by @foogod at + http://esp8266-re.foogod.com/wiki/Flashchip_%28IoT_RTOS_SDK_0.9.9%29 +*/ +typedef struct { + uint32_t device_id; + uint32_t chip_size; /* in bytes */ + uint32_t block_size; /* in bytes */ + uint32_t sector_size; /* in bytes */ + uint32_t page_size; /* in bytes */ + uint32_t status_mask; +} sdk_flashchip_t; + +#endif /* _FLASHCHIP_H */ diff --git a/core/include/xtensa_ops.h b/core/include/xtensa_ops.h index 52eba2a..6951869 100644 --- a/core/include/xtensa_ops.h +++ b/core/include/xtensa_ops.h @@ -11,9 +11,6 @@ #ifndef _XTENSA_OPS_H #define _XTENSA_OPS_H -// GCC macros for reading, writing, and exchanging Xtensa processor special -// registers: - /* Read stack pointer to variable. * * Note that the compiler will push a stack frame (minimum 16 bytes) @@ -28,8 +25,18 @@ */ #define RETADDR(var) asm volatile ("mov %0, a0" : "=r" (var)) +// GCC macros for reading, writing, and exchanging Xtensa processor special +// registers: + #define RSR(var, reg) asm volatile ("rsr %0, " #reg : "=r" (var)); #define WSR(var, reg) asm volatile ("wsr %0, " #reg : : "r" (var)); #define XSR(var, reg) asm volatile ("xsr %0, " #reg : "+r" (var)); +// GCC macros for performing associated "*sync" opcodes + +#define ISYNC() asm volatile ( "isync" ) +#define RSYNC() asm volatile ( "rsync" ) +#define ESYNC() asm volatile ( "esync" ) +#define DSYNC() asm volatile ( "dsync" ) + #endif /* _XTENSA_OPS_H */ diff --git a/include/espressif/spi_flash.h b/include/espressif/spi_flash.h index 44c8677..f08cda9 100644 --- a/include/espressif/spi_flash.h +++ b/include/espressif/spi_flash.h @@ -6,6 +6,8 @@ #ifndef __SPI_FLASH_H__ #define __SPI_FLASH_H__ +#include "flashchip.h" + #ifdef __cplusplus extern "C" { #endif @@ -44,29 +46,8 @@ sdk_SpiFlashOpResult sdk_spi_flash_write(uint32_t des_addr, const void *src, uin */ sdk_SpiFlashOpResult sdk_spi_flash_read(uint32_t src_addr, void *des, uint32_t size); - -/* SDK uses this structure internally to account for flash size. - - chip_size field is initialised during startup from the flash size - saved in the image header (on the first 8 bytes of SPI flash). - - Other field are initialised to hardcoded values by the SDK. - - Based on RE work by @foogod at - http://esp8266-re.foogod.com/wiki/Flashchip_%28IoT_RTOS_SDK_0.9.9%29 -*/ -typedef struct { - uint32_t device_id; - uint32_t chip_size; /* in bytes */ - uint32_t block_size; /* in bytes */ - uint32_t sector_size; /* in bytes */ - uint32_t page_size; /* in bytes */ - uint32_t status_mask; -} sdk_flashchip_t; - extern sdk_flashchip_t sdk_flashchip; - #ifdef __cplusplus } #endif diff --git a/include/etstimer.h b/include/etstimer.h new file mode 100644 index 0000000..bcc914a --- /dev/null +++ b/include/etstimer.h @@ -0,0 +1,39 @@ +/* Structures and constants used by some SDK routines + * + * Part of esp-open-rtos + * Copyright (C) 2015 Superhouse Automation Pty Ltd + * BSD Licensed as described in the file LICENSE + */ + +/* Note: The following definitions are normally found (in the non-RTOS SDK) in + * the ets_sys.h distributed by Espressif. Unfortunately, they are not found + * anywhere in the RTOS SDK headers, and differ substantially from the non-RTOS + * versions, so the structures defined here had to be obtained by careful + * examination of the code found in the Espressif RTOS SDK. + */ + +/* Note also: These cannot be included in esp8266/ets_sys.h, because it is + * included from FreeRTOS.h, creating an (unnecessary) circular dependency. + * They have therefore been put into their own header file instead. + */ + +#ifndef _ETSTIMER_H +#define _ETSTIMER_H + +#include "FreeRTOS.h" +#include "timers.h" +#include "esp/types.h" + +typedef void ETSTimerFunc(void *); + +typedef struct ETSTimer_st { + struct ETSTimer_st *timer_next; + xTimerHandle timer_handle; + uint32_t _unknown; + uint32_t timer_ms; + ETSTimerFunc *timer_func; + bool timer_repeat; + void *timer_arg; +} ETSTimer; + +#endif /* _ETSTIMER_H */ diff --git a/opensdk/component.mk b/opensdk/component.mk new file mode 100644 index 0000000..26fa5ad --- /dev/null +++ b/opensdk/component.mk @@ -0,0 +1,11 @@ +# Component makefile for "open sdk libs" + +# args for passing into compile rule generation +opensdk_libmain_ROOT = $(opensdk_libmain_DEFAULT_ROOT)libmain +opensdk_libmain_INC_DIR = +opensdk_libmain_SRC_DIR = $(opensdk_libmain_ROOT) +opensdk_libmain_EXTRA_SRC_FILES = + +opensdk_libmain_CFLAGS = $(CFLAGS) + +$(eval $(call component_compile_rules,opensdk_libmain)) diff --git a/opensdk/libmain/misc.c b/opensdk/libmain/misc.c new file mode 100644 index 0000000..25a059d --- /dev/null +++ b/opensdk/libmain/misc.c @@ -0,0 +1,59 @@ +#include "espressif/esp_misc.h" +#include "esp/gpio_regs.h" +#include "esp/rtc_regs.h" +#include "sdk_internal.h" +#include "xtensa/hal.h" + +static int cpu_freq = 80; + +void (*sdk__putc1)(char); + +int IRAM sdk_os_get_cpu_frequency(void) { + return cpu_freq; +} + +void sdk_os_update_cpu_frequency(int freq) { + cpu_freq = freq; +} + +void sdk_ets_update_cpu_frequency(int freq) __attribute__ (( alias ("sdk_os_update_cpu_frequency") )); + +void sdk_os_delay_us(uint16_t us) { + uint32_t start_ccount = xthal_get_ccount(); + uint32_t delay_ccount = cpu_freq * us; + while (xthal_get_ccount() - start_ccount < delay_ccount) {} +} + +void sdk_ets_delay_us(uint16_t us) __attribute__ (( alias ("sdk_os_delay_us") )); + +void sdk_os_install_putc1(void (*p)(char)) { + sdk__putc1 = p; +} + +void sdk_os_putc(char c) { + sdk__putc1(c); +} + +void sdk_gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask) { + GPIO.OUT_SET = set_mask; + GPIO.OUT_CLEAR = clear_mask; + GPIO.ENABLE_OUT_SET = enable_mask; + GPIO.ENABLE_OUT_CLEAR = disable_mask; +} + +uint8_t sdk_rtc_get_reset_reason(void) { + uint8_t reason; + + reason = FIELD2VAL(RTC_RESET_REASON1_CODE, RTC.RESET_REASON1); + if (reason == 5) { + if (FIELD2VAL(RTC_RESET_REASON2_CODE, RTC.RESET_REASON2) == 1) { + reason = 6; + } else { + if (FIELD2VAL(RTC_RESET_REASON2_CODE, RTC.RESET_REASON2) != 8) { + reason = 0; + } + } + } + RTC.RESET_REASON0 &= ~RTC_RESET_REASON0_SOMETHING; + return reason; +} diff --git a/opensdk/libmain/os_cpu_a.c b/opensdk/libmain/os_cpu_a.c new file mode 100644 index 0000000..4841ebe --- /dev/null +++ b/opensdk/libmain/os_cpu_a.c @@ -0,0 +1,121 @@ +#include "esp/types.h" +#include "FreeRTOS.h" +#include "task.h" +#include "xtensa_ops.h" +#include "common_macros.h" + +// xPortSysTickHandle is defined in FreeRTOS/Source/portable/esp8266/port.c but +// does not exist in any header files. +void xPortSysTickHandle(void); + +/* The following "functions" manipulate the stack at a low level and thus cannot be coded directly in C */ + +void IRAM vPortYield(void) { + asm(" wsr a0, excsave1 \n\ + addi sp, sp, -80 \n\ + s32i a0, sp, 4 \n\ + addi a0, sp, 80 \n\ + s32i a0, sp, 16 \n\ + rsr a0, ps \n\ + s32i a0, sp, 8 \n\ + rsr a0, excsave1 \n\ + s32i a0, sp, 12 \n\ + movi a0, _xt_user_exit \n\ + s32i a0, sp, 0 \n\ + call0 sdk__xt_int_enter \n\ + call0 vPortEnterCritical \n\ + call0 vTaskSwitchContext \n\ + call0 vPortExitCritical \n\ + call0 sdk__xt_int_exit \n\ + "); +} + +void IRAM sdk__xt_int_enter(void) { + asm(" s32i a12, sp, 60 \n\ + s32i a13, sp, 64 \n\ + mov a12, a0 \n\ + call0 sdk__xt_context_save \n\ + movi a0, pxCurrentTCB \n\ + l32i a0, a0, 0 \n\ + s32i sp, a0, 0 \n\ + mov a0, a12 \n\ + "); +} + +void IRAM sdk__xt_int_exit(void) { + asm(" s32i a14, sp, 68 \n\ + s32i a15, sp, 72 \n\ + movi sp, pxCurrentTCB \n\ + l32i sp, sp, 0 \n\ + l32i sp, sp, 0 \n\ + movi a14, pxCurrentTCB \n\ + l32i a14, a14, 0 \n\ + addi a15, sp, 80 \n\ + s32i a15, a14, 0 \n\ + call0 sdk__xt_context_restore \n\ + l32i a14, sp, 68 \n\ + l32i a15, sp, 72 \n\ + l32i a0, sp, 0 \n\ + "); +} + +void IRAM sdk__xt_timer_int(void) { + uint32_t trigger_ccount; + uint32_t current_ccount; + uint32_t ccount_interval = portTICK_RATE_MS * 80000; //FIXME + + do { + RSR(trigger_ccount, ccompare0); + WSR(trigger_ccount + ccount_interval, ccompare0); + ESYNC(); + xPortSysTickHandle(); + ESYNC(); + RSR(current_ccount, ccount); + } while (current_ccount - trigger_ccount > ccount_interval); +} + +void IRAM sdk__xt_timer_int1(void) { + vTaskSwitchContext(); +} + +#define INTENABLE_CCOMPARE BIT(6) + +void IRAM sdk__xt_tick_timer_init(void) { + uint32_t ints_enabled; + uint32_t current_ccount; + uint32_t ccount_interval = portTICK_RATE_MS * 80000; //FIXME + + RSR(current_ccount, ccount); + WSR(current_ccount + ccount_interval, ccompare0); + ints_enabled = 0; + XSR(ints_enabled, intenable); + WSR(ints_enabled | INTENABLE_CCOMPARE, intenable); +} + +void IRAM sdk__xt_isr_unmask(uint32_t mask) { + uint32_t ints_enabled; + + ints_enabled = 0; + XSR(ints_enabled, intenable); + WSR(ints_enabled | mask, intenable); +} + +void IRAM sdk__xt_isr_mask(uint32_t mask) { + uint32_t ints_enabled; + + ints_enabled = 0; + XSR(ints_enabled, intenable); + WSR(ints_enabled & mask, intenable); +} + +uint32_t IRAM sdk__xt_read_ints(void) { + uint32_t ints_enabled; + + RSR(ints_enabled, intenable); + return ints_enabled; +} + +void IRAM sdk__xt_clear_ints(uint32_t mask) { + WSR(mask, intclear); +} + diff --git a/opensdk/libmain/spi_flash.c b/opensdk/libmain/spi_flash.c new file mode 100644 index 0000000..2915c79 --- /dev/null +++ b/opensdk/libmain/spi_flash.c @@ -0,0 +1,183 @@ +#include "FreeRTOS.h" +#include "common_macros.h" +#include "esp/spi_regs.h" +#include "esp/rom.h" +#include "sdk_internal.h" +#include "espressif/spi_flash.h" + +sdk_flashchip_t sdk_flashchip = { + 0x001640ef, // device_id + 4 * 1024 * 1024, // chip_size + 65536, // block_size + 4096, // sector_size + 256, // page_size + 0x0000ffff, // status_mask +}; + +// NOTE: This routine appears to be completely unused in the SDK + +int IRAM sdk_SPIReadModeCnfig(uint32_t mode) { + uint32_t ctrl_bits; + + SPI(0).CTRL0 &= ~(SPI_CTRL0_FASTRD_MODE | SPI_CTRL0_DOUT_MODE | SPI_CTRL0_QOUT_MODE | SPI_CTRL0_DIO_MODE | SPI_CTRL0_QIO_MODE); + if (mode == 0) { + ctrl_bits = SPI_CTRL0_FASTRD_MODE | SPI_CTRL0_QIO_MODE; + } else if (mode == 1) { + ctrl_bits = SPI_CTRL0_FASTRD_MODE | SPI_CTRL0_QOUT_MODE; + } else if (mode == 2) { + ctrl_bits = SPI_CTRL0_FASTRD_MODE | SPI_CTRL0_DIO_MODE; + } else if (mode == 3) { + ctrl_bits = SPI_CTRL0_FASTRD_MODE | SPI_CTRL0_DOUT_MODE; + } else if (mode == 4) { + ctrl_bits = SPI_CTRL0_FASTRD_MODE; + } else { + ctrl_bits = 0; + } + if (mode == 0 || mode == 1) { + Enable_QMode(&sdk_flashchip); + } else { + Disable_QMode(&sdk_flashchip); + } + SPI(0).CTRL0 |= ctrl_bits; + return 0; +} + +sdk_SpiFlashOpResult IRAM sdk_SPIWrite(uint32_t des_addr, uint32_t *src_addr, uint32_t size) { + uint32_t first_page_portion; + uint32_t pos; + uint32_t full_pages; + uint32_t bytes_remaining; + + if (des_addr + size <= sdk_flashchip.chip_size) { + first_page_portion = sdk_flashchip.page_size - (des_addr % sdk_flashchip.page_size); + if (size < first_page_portion) { + if (SPI_page_program(&sdk_flashchip, des_addr, src_addr, size)) { + return SPI_FLASH_RESULT_ERR; + } else { + return SPI_FLASH_RESULT_OK; + } + } + } else { + return SPI_FLASH_RESULT_ERR; + } + if (SPI_page_program(&sdk_flashchip, des_addr, src_addr, first_page_portion)) { + return SPI_FLASH_RESULT_ERR; + } + pos = first_page_portion; + bytes_remaining = size - first_page_portion; + full_pages = bytes_remaining / sdk_flashchip.page_size; + if (full_pages) { + for (int i = 0; i != full_pages; i++) { + if (SPI_page_program(&sdk_flashchip, des_addr + pos, src_addr + (pos / 4), sdk_flashchip.page_size)) { + return SPI_FLASH_RESULT_ERR; + } + pos += sdk_flashchip.page_size; + } + bytes_remaining = size - pos; + } + if (SPI_page_program(&sdk_flashchip, des_addr + pos, src_addr + (pos / 4), bytes_remaining)) { + return SPI_FLASH_RESULT_ERR; + } + return SPI_FLASH_RESULT_OK; +} + +sdk_SpiFlashOpResult IRAM sdk_SPIRead(uint32_t src_addr, uint32_t *des_addr, uint32_t size) { + if (SPI_read_data(&sdk_flashchip, src_addr, des_addr, size)) { + return SPI_FLASH_RESULT_ERR; + } else { + return SPI_FLASH_RESULT_OK; + } +} + +sdk_SpiFlashOpResult IRAM sdk_SPIEraseSector(uint16_t sec) { + if (sec >= sdk_flashchip.chip_size / sdk_flashchip.sector_size) { + return SPI_FLASH_RESULT_ERR; + } + if (SPI_write_enable(&sdk_flashchip)) { + return SPI_FLASH_RESULT_ERR; + } + if (SPI_sector_erase(&sdk_flashchip, sdk_flashchip.sector_size * sec)) { + return SPI_FLASH_RESULT_ERR; + } + return SPI_FLASH_RESULT_OK; +} + +uint32_t IRAM sdk_spi_flash_get_id(void) { + uint32_t result; + + portENTER_CRITICAL(); + Cache_Read_Disable(); + Wait_SPI_Idle(&sdk_flashchip); + SPI(0).W[0] = 0; + SPI(0).CMD = SPI_CMD_READ_ID; + while (SPI(0).CMD != 0) {} + result = SPI(0).W[0] & 0x00ffffff; + Cache_Read_Enable(0, 0, 1); + portEXIT_CRITICAL(); + return result; +} + +sdk_SpiFlashOpResult IRAM sdk_spi_flash_read_status(uint32_t *status) { + sdk_SpiFlashOpResult result; + + portENTER_CRITICAL(); + Cache_Read_Disable(); + result = SPI_read_status(&sdk_flashchip, status); + Cache_Read_Enable(0, 0, 1); + portEXIT_CRITICAL(); + return result; +} + +sdk_SpiFlashOpResult IRAM sdk_spi_flash_write_status(uint32_t status) { + sdk_SpiFlashOpResult result; + + portENTER_CRITICAL(); + Cache_Read_Disable(); + result = SPI_write_status(&sdk_flashchip, status); + Cache_Read_Enable(0, 0, 1); + portEXIT_CRITICAL(); + return result; +} + +sdk_SpiFlashOpResult IRAM sdk_spi_flash_erase_sector(uint16_t sec) { + sdk_SpiFlashOpResult result; + + portENTER_CRITICAL(); + Cache_Read_Disable(); + result = sdk_SPIEraseSector(sec); + Cache_Read_Enable(0, 0, 1); + portEXIT_CRITICAL(); + return result; +} + +sdk_SpiFlashOpResult IRAM sdk_spi_flash_write(uint32_t des_addr, uint32_t *src_addr, uint32_t size) { + sdk_SpiFlashOpResult result; + + if (!src_addr) { + return SPI_FLASH_RESULT_ERR; + } + if (size & 3) { + size = (size & ~3) + 4; + } + portENTER_CRITICAL(); + Cache_Read_Disable(); + result = sdk_SPIWrite(des_addr, src_addr, size); + Cache_Read_Enable(0, 0, 1); + portEXIT_CRITICAL(); + return result; +} + +sdk_SpiFlashOpResult IRAM sdk_spi_flash_read(uint32_t src_addr, uint32_t *des_addr, uint32_t size) { + sdk_SpiFlashOpResult result; + + if (!des_addr) { + return SPI_FLASH_RESULT_ERR; + } + portENTER_CRITICAL(); + Cache_Read_Disable(); + result = sdk_SPIRead(src_addr, des_addr, size); + Cache_Read_Enable(0, 0, 1); + portEXIT_CRITICAL(); + return result; +} + diff --git a/opensdk/libmain/timers.c b/opensdk/libmain/timers.c new file mode 100644 index 0000000..1359fc1 --- /dev/null +++ b/opensdk/libmain/timers.c @@ -0,0 +1,89 @@ +#include "etstimer.h" + +struct timer_list_st { + struct timer_list_st *next; + ETSTimer *timer; +}; + +static struct timer_list_st *timer_list; +static uint8_t armed_timer_count; + +void sdk_os_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg) { + struct timer_list_st *entry = 0; + struct timer_list_st *new_entry; + struct timer_list_st **tailptr; + + if (timer_list) { + for (entry = timer_list; ; entry = entry->next) { + if (entry->timer == ptimer) { + if (ptimer->timer_arg == parg && ptimer->timer_func == pfunction) { + return; + } + if (ptimer->timer_handle) { + if (!xTimerDelete(ptimer->timer_handle, 50)) { + printf("Timer Delete Failed\n"); + } + armed_timer_count--; + } + ptimer->timer_func = pfunction; + ptimer->timer_arg = parg; + ptimer->timer_handle = 0; + ptimer->timer_ms = 0; + return; + } + if (!entry->next) { + break; + } + } + } + ptimer->timer_func = pfunction; + ptimer->timer_arg = parg; + ptimer->timer_handle = 0; + ptimer->timer_ms = 0; + new_entry = (struct timer_list_st *)pvPortMalloc(8); + new_entry->timer = ptimer; + new_entry->next = 0; + tailptr = &entry->next; + if (!timer_list) { + tailptr = &timer_list; + } + *tailptr = new_entry; +} + +void sdk_os_timer_arm(ETSTimer *ptimer, uint32_t milliseconds, bool repeat_flag) { + if (!ptimer->timer_handle) { + ptimer->timer_repeat = repeat_flag; + ptimer->timer_ms = milliseconds; + ptimer->timer_handle = xTimerCreate(0, milliseconds/10, repeat_flag, ptimer->timer_arg, ptimer->timer_func); + armed_timer_count++; + if (!ptimer->timer_handle) { + //FIXME: should print an error? (original code doesn't) + return; + } + } + if (ptimer->timer_repeat != repeat_flag) { + ptimer->timer_repeat = repeat_flag; + // FIXME: This is wrong. The original code is directly modifying + // internal FreeRTOS structures to try to change the uxAutoReload of an + // existing timer. The correct way to do this is probably to use + // xTimerDelete and then xTimerCreate to recreate the timer with a + // different uxAutoReload setting. + ((uint32_t *)ptimer->timer_handle)[7] = repeat_flag; + } + if (ptimer->timer_ms != milliseconds) { + ptimer->timer_ms = milliseconds; + xTimerChangePeriod(ptimer->timer_handle, milliseconds/10, 10); + } + if (!xTimerStart(ptimer->timer_handle, 50)) { + printf("Timer Start Failed\n"); + } +} + +void sdk_os_timer_disarm(ETSTimer *ptimer) { + if (ptimer->timer_handle) { + if (!xTimerStop(ptimer->timer_handle, 50)) { + printf("Timer Stop Failed\n"); + } + } +} + diff --git a/opensdk/libmain/uart.c b/opensdk/libmain/uart.c new file mode 100644 index 0000000..25ae961 --- /dev/null +++ b/opensdk/libmain/uart.c @@ -0,0 +1,17 @@ +#include "espressif/sdk_private.h" +#include "esp/uart_regs.h" + +void sdk_uart_buff_switch(void) { + /* No-Op */ +} + +void sdk_uart_div_modify(uint32_t uart_no, uint32_t new_divisor) { + UART(uart_no).CLOCK_DIVIDER = new_divisor; + UART(uart_no).CONF0 |= (UART_CONF0_TXFIFO_RESET | UART_CONF0_RXFIFO_RESET); + UART(uart_no).CONF0 &= ~(UART_CONF0_TXFIFO_RESET | UART_CONF0_RXFIFO_RESET); +} + +void sdk_Uart_Init(void) { + /* No-Op */ +} + diff --git a/opensdk/libmain/xtensa_context.S b/opensdk/libmain/xtensa_context.S new file mode 100644 index 0000000..511877e --- /dev/null +++ b/opensdk/libmain/xtensa_context.S @@ -0,0 +1,41 @@ + .section .iram1.text, "ax", @progbits + + .balign 4 + .global sdk__xt_context_save + .type sdk__xt_context_save, @function +sdk__xt_context_save: + + s32i a2, sp, 20 + s32i a3, sp, 24 + s32i a4, sp, 28 + s32i a5, sp, 32 + s32i a6, sp, 36 + s32i a7, sp, 40 + s32i a8, sp, 44 + s32i a9, sp, 48 + s32i a10, sp, 52 + s32i a11, sp, 56 + rsr a3, sar + s32i a3, sp, 76 + ret + + .balign 4 + .global sdk__xt_context_restore + .type sdk__xt_context_restore, @function +sdk__xt_context_restore: + l32i a3, sp, 76 + l32i a2, sp, 20 + wsr a3, sar + l32i a3, sp, 24 + l32i a4, sp, 28 + l32i a5, sp, 32 + l32i a6, sp, 36 + l32i a7, sp, 40 + l32i a8, sp, 44 + l32i a9, sp, 48 + l32i a10, sp, 52 + l32i a11, sp, 56 + l32i a12, sp, 60 + l32i a13, sp, 64 + ret + diff --git a/parameters.mk b/parameters.mk index e750e83..f14a26b 100644 --- a/parameters.mk +++ b/parameters.mk @@ -60,7 +60,7 @@ OBJDUMP = $(CROSS)objdump # Source components to compile and link. Each of these are subdirectories # of the root, with a 'component.mk' file. -COMPONENTS ?= $(EXTRA_COMPONENTS) FreeRTOS lwip core +COMPONENTS ?= $(EXTRA_COMPONENTS) FreeRTOS lwip core opensdk # binary esp-iot-rtos SDK libraries to link. These are pre-processed prior to linking. SDK_LIBS ?= main net80211 phy pp wpa @@ -114,7 +114,7 @@ else ifeq ($(FLAVOR),sdklike) # the output of the compiler used to build the SDK libs (for comparison of # disassemblies when coding replacement routines). It is not normally # intended to be used otherwise. - CFLAGS += -O2 -Os -fno-inline -fno-ipa-cp -fno-toplevel-reorder + CFLAGS += -O2 -Os -fno-inline -fno-ipa-cp -fno-toplevel-reorder -fno-caller-saves -fconserve-stack LDFLAGS += -O2 else C_CXX_FLAGS += -g -O2