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Working variant of esp_iot_rtos_sdk (files from commit ec75c85f9ef53)

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Angus Gratton 2015-04-30 14:00:03 +10:00
parent 101c8648ea
commit 1ffbc303ff
124 changed files with 19424 additions and 592 deletions
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366
FreeRTOS/Source/portable/esp8266/port.c Normal file
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/*
FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
* Implementation of functions defined in portable.h for the ARM CM3 port.
*----------------------------------------------------------*/
/* Scheduler includes. */
#include <xtensa/config/core.h>
//#include <xtensa/tie/xt_interrupt.h>
#include "FreeRTOS.h"
#include "task.h"
#include "xtensa_rtos.h"
extern char NMIIrqIsOn;
static char HdlMacSig = 0;
static char SWReq = 0;
static char PendSvIsPosted = 0;
unsigned cpu_sr;
/* Each task maintains its own interrupt status in the critical nesting
variable. */
static unsigned portBASE_TYPE uxCriticalNesting = 0;
void vPortEnterCritical( void );
void vPortExitCritical( void );
/*
* See header file for description.
*/
portSTACK_TYPE * ICACHE_FLASH_ATTR
pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
{
#define SET_STKREG(r,v) sp[(r) >> 2] = (portSTACK_TYPE)(v)
portSTACK_TYPE *sp, *tp;
/* Create interrupt stack frame aligned to 16 byte boundary */
sp = (portSTACK_TYPE*) (((INT32U)(pxTopOfStack+1) - XT_CP_SIZE - XT_STK_FRMSZ) & ~0xf);
/* Clear the entire frame (do not use memset() because we don't depend on C library) */
for (tp = sp; tp <= pxTopOfStack; ++tp)
*tp = 0;
/* Explicitly initialize certain saved registers */
SET_STKREG( XT_STK_PC, pxCode ); /* task entrypoint */
SET_STKREG( XT_STK_A0, 0 ); /* to terminate GDB backtrace */
SET_STKREG( XT_STK_A1, (INT32U)sp + XT_STK_FRMSZ ); /* physical top of stack frame */
SET_STKREG( XT_STK_A2, pvParameters ); /* parameters */
SET_STKREG( XT_STK_EXIT, _xt_user_exit ); /* user exception exit dispatcher */
/* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
#ifdef __XTENSA_CALL0_ABI__
SET_STKREG( XT_STK_PS, PS_UM | PS_EXCM );
#else
/* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
SET_STKREG( XT_STK_PS, PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1) );
#endif
return sp;
}
void PendSV( char req )
{
char tmp=0;
//ETS_INTR_LOCK();
if( NMIIrqIsOn == 0 )
{
vPortEnterCritical();
//PortDisableInt_NoNest();
tmp = 1;
}
if(req ==1)
{
SWReq = 1;
}
else if(req ==2)
HdlMacSig= 1;
#if 0
GPIO_REG_WRITE(GPIO_STATUS_W1TS_ADDRESS, 0x40);
#else
if(PendSvIsPosted == 0)
{
PendSvIsPosted = 1;
xthal_set_intset(1<<ETS_SOFT_INUM);
}
#endif
if(tmp == 1)
vPortExitCritical();
}
extern portBASE_TYPE MacIsrSigPostDefHdl(void);
#if 0
void IRAM_FUNC_ATTR
GPIOIntrHdl(void)
{
//if( (GPIO_REG_READ(GPIO_STATUS_ADDRESS) & (1<<6)) == 0 )
//printf("i");
//printf("g,%08x\n",GPIO_REG_READ(GPIO_STATUS_ADDRESS));
//SDIO_CLK GPIO interrupt
if( (GPIO_REG_READ(GPIO_STATUS_ADDRESS) & (1<<6)) != 0 )
{
//CloseNMI();
portBASE_TYPE xHigherPriorityTaskWoken=pdFALSE ;
if(HdlMacSig == 1)
{
HdlMacSig = 0;
xHigherPriorityTaskWoken = MacIsrSigPostDefHdl();
}
if( xHigherPriorityTaskWoken || (SWReq==1))
{
SWReq = 0;
_xt_timer_int1();
}
//OpenNMI();
GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, 0x40);
}
}
#else
void SoftIsrHdl(void)
{
//if(DbgVal5==1)
//printf("GP_%d,",SWReq);
PendSvIsPosted = 0;
portBASE_TYPE xHigherPriorityTaskWoken=pdFALSE ;
if(HdlMacSig == 1)
{
xHigherPriorityTaskWoken = MacIsrSigPostDefHdl();
HdlMacSig = 0;
}
if( xHigherPriorityTaskWoken || (SWReq==1))
{
//if( DbgVal5==1 || DbgVal10==1 )
//printf("_x_s,");
_xt_timer_int1();
SWReq = 0;
}
}
#endif
void xPortSysTickHandle (void)
{
//CloseNMI();
{
if(xTaskIncrementTick() !=pdFALSE )
{
//GPIO_REG_WRITE(GPIO_STATUS_W1TS_ADDRESS, 0x40);
vTaskSwitchContext();
}
}
//OpenNMI();
}
/*
* See header file for description.
*/
portBASE_TYPE ICACHE_FLASH_ATTR
xPortStartScheduler( void )
{
//set pendsv and systemtick as lowest priority ISR.
//pendsv setting
/*******GPIO sdio_clk isr*********/
#if 0
_xt_isr_attach(ETS_GPIO_INUM, GPIOIntrHdl);
_xt_isr_unmask(1<<ETS_GPIO_INUM);
#else
/*******software isr*********/
_xt_isr_attach(ETS_SOFT_INUM, SoftIsrHdl);
_xt_isr_unmask(1<<ETS_SOFT_INUM);
#endif
/* Initialize system tick timer interrupt and schedule the first tick. */
_xt_tick_timer_init();
printf("xPortStartScheduler\n");
vTaskSwitchContext();
// REG_SET_BIT(0x3ff2006c, BIT(4));
/* Restore the context of the first task that is going to run. */
XT_RTOS_INT_EXIT();
/* Should not get here as the tasks are now running! */
return pdTRUE;
}
void ICACHE_FLASH_ATTR
vPortEndScheduler( void )
{
/* It is unlikely that the CM3 port will require this function as there
is nothing to return to. */
}
/*-----------------------------------------------------------*/
/*-----------------------------------------------------------*/
static unsigned int tick_lock=0;
static char ClosedLv1Isr = 0;
void vPortEnterCritical( void )
{
if(NMIIrqIsOn == 0)
{
//if( uxCriticalNesting == 0 )
{
if( ClosedLv1Isr !=1 )
{
portDISABLE_INTERRUPTS();
ClosedLv1Isr = 1;
}
//tick_lock = WDEV_NOW();
}
uxCriticalNesting++;
}
}
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
if(NMIIrqIsOn == 0)
{
uxCriticalNesting--;
if( uxCriticalNesting == 0 )
{
//if( (WDEV_NOW() - tick_lock) > 2000000 )
//printf("INTR LOCK TOO LONG:%d\n",(WDEV_NOW() - tick_lock));
if( ClosedLv1Isr ==1 )
{
ClosedLv1Isr = 0;
portENABLE_INTERRUPTS();
}
}
}
}
void
PortDisableInt_NoNest( void )
{
//os_printf("ERRRRRRR\n");
if(NMIIrqIsOn == 0)
{
if( ClosedLv1Isr !=1 )
{
portDISABLE_INTERRUPTS();
ClosedLv1Isr = 1;
}
}
}
void
PortEnableInt_NoNest( void )
{
//os_printf("ERRRRR\n");
if(NMIIrqIsOn == 0)
{
if( ClosedLv1Isr ==1 )
{
ClosedLv1Isr = 0;
portENABLE_INTERRUPTS();
}
}
}
/*-----------------------------------------------------------*/
_xt_isr isr[16];
void _xt_isr_attach(uint8_t i, _xt_isr func)
{
isr[i] = func;
}
uint16_t _xt_isr_handler(uint16_t i)
{
uint8_t index;
if (i & (1 << ETS_WDT_INUM)) {
// printf("i %x %u\n", i, REG_READ(0x3ff20c00));
index = ETS_WDT_INUM;
}
else if (i & (1 << ETS_GPIO_INUM)) {
index = ETS_GPIO_INUM;
}else {
index = __builtin_ffs(i) - 1;
if (index == ETS_MAX_INUM) {
i &= ~(1 << ETS_MAX_INUM);
index = __builtin_ffs(i) - 1;
}
}
_xt_clear_ints(1<<index);
isr[index]();
return i & ~(1 << index);
}

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FreeRTOS/Source/portable/esp8266/portmacro.h Normal file
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/*
FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that has become a de facto standard. *
* *
* Help yourself get started quickly and support the FreeRTOS *
* project by purchasing a FreeRTOS tutorial book, reference *
* manual, or both from: http://www.FreeRTOS.org/Documentation *
* *
* Thank you! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
>>! NOTE: The modification to the GPL is included to allow you to distribute
>>! a combined work that includes FreeRTOS without being obliged to provide
>>! the source code for proprietary components outside of the FreeRTOS
>>! kernel.
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available from the following
link: http://www.freertos.org/a00114.html
1 tab == 4 spaces!
***************************************************************************
* *
* Having a problem? Start by reading the FAQ "My application does *
* not run, what could be wrong?" *
* *
* http://www.FreeRTOS.org/FAQHelp.html *
* *
***************************************************************************
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
license and Real Time Engineers Ltd. contact details.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
#ifndef PORTMACRO_H
#define PORTMACRO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "esp_common.h"
#include <xtruntime.h>
#include "xtensa_rtos.h"
/*-----------------------------------------------------------
* Port specific definitions.
*
* The settings in this file configure FreeRTOS correctly for the
* given hardware and compiler.
*
* These settings should not be altered.
*-----------------------------------------------------------
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE unsigned portLONG
#define portBASE_TYPE long
typedef unsigned portLONG portTickType;
typedef unsigned int INT32U;
#define portMAX_DELAY ( portTickType ) 0xffffffff
/*-----------------------------------------------------------*/
/* Architecture specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
#define ICACHE_FLASH_ATTR __attribute__((section(".irom0.text")))
/* Scheduler utilities. */
extern void PendSV(char req);
//#define portYIELD() vPortYield()
#define portYIELD() PendSV(1)
//#define portEND_SWITCHING_ISR( xSwitchRequired ) \
// if(xSwitchRequired) PendSV(1)
#define HDL_MAC_SIG_IN_LV1_ISR() PendSV(2)
/* Task utilities. */
#define portEND_SWITCHING_ISR( xSwitchRequired ) \
{ \
extern void vTaskSwitchContext( void ); \
\
if( xSwitchRequired ) \
{ \
vTaskSwitchContext(); \
} \
}
/*-----------------------------------------------------------*/
extern unsigned cpu_sr;
/* Critical section management. */
extern void vPortEnterCritical( void );
extern void vPortExitCritical( void );
//DYC_ISR_DBG
void PortDisableInt_NoNest( void );
void PortEnableInt_NoNest( void );
/* Disable interrupts, saving previous state in cpu_sr */
#define portDISABLE_INTERRUPTS() \
__asm__ volatile ("rsil %0, " XTSTR(XCHAL_EXCM_LEVEL) : "=a" (cpu_sr) :: "memory")
/* Restore interrupts to previous level saved in cpu_sr */
#define portENABLE_INTERRUPTS() __asm__ volatile ("wsr %0, ps" :: "a" (cpu_sr) : "memory")
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()
// no need to disable/enable lvl1 isr again in ISR
//#define portSET_INTERRUPT_MASK_FROM_ISR() PortDisableInt_NoNest()
//#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) PortEnableInt_NoNest()
/*-----------------------------------------------------------*/
/* Tickless idle/low power functionality. */
/*-----------------------------------------------------------*/
/* Port specific optimisations. */
/*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. These are
not necessary for to use this port. They are defined so the common demo files
(which build with all the ports) will build. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
void _xt_user_exit (void);
void _xt_tick_timer_init (void);
void _xt_isr_unmask (uint32_t unmask);
void _xt_isr_mask (uint32_t mask);
uint32_t _xt_read_ints (void);
void _xt_clear_ints(uint32_t mask);
/* interrupt related */
typedef void (* _xt_isr)(void);
void _xt_isr_attach (uint8_t i, _xt_isr func);
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */

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FreeRTOS/Source/portable/esp8266/xtensa_context.h Normal file
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/*******************************************************************************
Copyright (c) 2006-2008 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc.
--------------------------------------------------------------------------------
XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
This header contains definitions and macros for use primarily by Xtensa
RTOS assembly coded source files. It includes and uses the Xtensa hardware
abstraction layer (HAL) to deal with config specifics. It may also be
included in C source files.
!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
*******************************************************************************/
#ifndef XTENSA_CONTEXT_H
#define XTENSA_CONTEXT_H
#ifdef __ASSEMBLER__
#include <xtensa/coreasm.h>
#endif
#include <xtensa/config/tie.h>
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
/*
Align a value up to nearest n-byte boundary, where n is a power of 2.
*/
#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
/*******************************************************************************
INTERRUPT STACK FRAME FOR A THREAD OR NESTED INTERRUPT
A stack frame of this structure is allocated for any interrupt or exception.
It goes on the current stack. If the RTOS has a system stack for handling
interrupts, every thread stack must allow space for just one interrupt stack
frame, then nested interrupt stack frames go on the system stack.
The frame includes basic registers (explicit) and "extra" registers introduced
by user TIE or the use of the MAC16 option in the user's Xtensa config.
The frame size is minimized by omitting regs not applicable to user's config.
For Windowed ABI, this stack frame includes the interruptee's base save area,
another base save area to manage gcc nested functions, and a little temporary
space to help manage the spilling of the register windows.
*******************************************************************************/
#define XT_STK_EXIT 0x00 /* (offset 0) exit point for dispatch */
#define XT_STK_PC 0x04 /* return address */
#define XT_STK_PS 0x08 /* at level 1 PS.EXCM is set here */
#define XT_STK_A0 0x0C
#define XT_STK_A1 0x10 /* stack ptr before interrupt */
#define XT_STK_A2 0x14
#define XT_STK_A3 0x18
#define XT_STK_A4 0x1C
#define XT_STK_A5 0x20
#define XT_STK_A6 0x24
#define XT_STK_A7 0x28
#define XT_STK_A8 0x2C
#define XT_STK_A9 0x30
#define XT_STK_A10 0x34
#define XT_STK_A11 0x38
#define XT_STK_A12 0x3C /* Call0 callee-save */
#define XT_STK_A13 0x40 /* Call0 callee-save */
#define XT_STK_A14 0x44 /* Call0 callee-save */
#define XT_STK_A15 0x48 /* Call0 callee-save */
#define XT_STK_SAR 0x4C
#if XCHAL_HAVE_LOOPS
#define XT_STK_LBEG 0x50
#define XT_STK_LEND 0x54
#define XT_STK_LCOUNT 0x58
#define XT_STK_NEXT1 0x5C /* next unused offset */
#else
#define XT_STK_NEXT1 0x50 /* next unused offset */
#endif
/* there may be some unused space here */
#if XCHAL_EXTRA_SA_SIZE != 0
#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
#else
#define XT_STK_NEXT2 XT_STK_NEXT1
#endif
/* next unused offset */
/* there may be some unused space here */
#ifdef __XTENSA_CALL0_ABI__
/* Call0 - no more stack frame needed */
#define XT_STK_FRMSZ ALIGNUP(0x10, XT_STK_NEXT2)
#else
/*
Windowed -
Need some temp space for saving stuff during window spill.
Also add 16 bytes to skip over interruptee's base save area
and another 16 bytes in case of gcc nested functions: these
must be at physical top (logical base) of frame.
*/
#define XT_STK_N_TMP 3 /* # of 4-byte temp. slots */
#define XT_STK_TMP XT_STK_NEXT2
#define XT_STK_NEXT3 XT_STK_TMP + (4 * XT_STK_N_TMP)
#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT3) + 0x20)
#endif
/*******************************************************************************
SOLICTED STACK FRAME FOR A THREAD
A stack frame of this structure is allocated whenever a thread enters the
RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
It goes on the current thread's stack.
The solicted frame only includes registers that are required to be preserved
by the callee according to the compiler's ABI conventions, some space to save
the return address for returning to the caller, and the caller's PS register.
For Windowed ABI, this stack frame includes the caller's base save area.
Note on XT_SOL_EXIT field:
It is necessary to distinguish a solicited from an interrupt stack frame.
This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
always at the same offset (0). It can be written with a code (usually 0)
to distinguish a solicted frame from an interrupt frame. An RTOS port may
opt to ignore this field if it has another way of distinguishing frames.
*******************************************************************************/
#ifdef __XTENSA_CALL0_ABI__
/* Call0 ABI: room to save callee-save regs and return address. */
#define XT_SOL_EXIT XT_STK_EXIT /* code indicates solicited frame */
#define XT_SOL_PC 0x04 /* return address */
#define XT_SOL_PS 0x08
#define XT_SOL_NEXT 0x0c /* next unused offset */
/* there may be some unused space here */
#define XT_SOL_A12 ALIGNUP(0x10, XT_SOL_NEXT)
#define XT_SOL_A13 XT_SOL_A12 + 4
#define XT_SOL_A14 XT_SOL_A13 + 4
#define XT_SOL_A15 XT_SOL_A14 + 4
#define XT_SOL_FRMSZ ALIGNUP(0x10, XT_SOL_A15)
#else
/* Windowed ABI: room to spill base-save area and save return address. */
#define XT_SOL_EXIT XT_STK_EXIT /* code indicates solicited frame */
#define XT_SOL_PC 0x04 /* return address (b30-31=callinc) */
#define XT_SOL_PS 0x08
#define XT_SOL_NEXT 0x0c /* next unused offset */
/* there may be some unused space here */
#define XT_SOL_A0 ALIGNUP(0x10, XT_SOL_NEXT)
#define XT_SOL_A1 XT_SOL_A0 + 4
#define XT_SOL_A2 XT_SOL_A1 + 4
#define XT_SOL_A3 XT_SOL_A2 + 4
#define XT_SOL_FRMSZ ALIGNUP(0x10, XT_SOL_A3)
#endif
/*******************************************************************************
CO-PROCESSOR STATE SAVE AREA FOR A THREAD
The RTOS must provide an area per thread to save the state of co-processors
when that thread does not have control. Co-processors are context-switched
lazily (on demand) only when a new thread uses a co-processor instruction,
otherwise a thread retains ownership of the co-processor even when it loses
control of the processor. An Xtensa co-processor exception is triggered when
any co-processor instruction is executed by a thread that is not the owner,
and the context switch of that co-processor is then peformed by the handler.
Ownership represents which thread's state is currently in the co-processor.
Co-processors may not be used by interrupt or exception handlers. If an
co-processor instruction is executed by an interrupt or exception handler,
the co-processor exception handler will trigger a kernel panic and freeze.
This restriction is introduced to reduce the overhead of saving and restoring
co-processor state (which can be quite large) and in particular remove that
overhead from interrupt handlers.
The co-processor state save area may be in any convenient per-thread location
such as in the thread control block or above the thread stack area. It need
not be in the interrupt stack frame since interrupts don't use co-processors.
Along with the save area for each co-processor, two bitmasks with flags per
co-processor (laid out as in the CPENABLE reg) help manage context-switching
co-processors as efficiently as possible:
XT_CPENABLE
The contents of a non-running thread's CPENABLE register.
It represents the co-processors owned (and whose state is still needed)
by the thread. When a thread is preempted, its CPENABLE is saved here.
When a thread solicits a context-swtich, its CPENABLE is cleared - the
compiler has saved the (caller-saved) co-proc state if it needs to.
When a non-running thread loses ownership of a CP, its bit is cleared.
When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
Avoids co-processor exceptions when no change of ownership is needed.
XT_CPSTORED
A bitmask with the same layout as CPENABLE, a bit per co-processor.
Indicates whether the state of each co-processor is saved in the state
save area. When a thread enters the kernel, only the state of co-procs
still enabled in CPENABLE is saved. When the co-processor exception
handler assigns ownership of a co-processor to a thread, it restores
the saved state only if this bit is set, and clears this bit.
*******************************************************************************/
#if XCHAL_CP_NUM > 0
#define XT_CPENABLE 0
#define XT_CPSTORED (XT_CPENABLE + 1)
#define XT_CP0_SA ALIGNUP(XCHAL_CP0_SA_ALIGN, XT_CPSTORED + 1)
#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
#define XT_CP_SIZE ALIGNUP(4 , XT_CP7_SA + XCHAL_CP7_SA_SIZE)
#else
#define XT_CP_SIZE 0
#endif
/*******************************************************************************
MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
Convenient where the frame size requirements are the same for both ABIs.
ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
ENTRY0, RET0 are for frameless functions (no locals, no calls).
where size = size of stack frame in bytes (must be >0 and aligned to 16).
For framed functions the frame is created and the return address saved at
base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
For frameless functions, there is no frame and return address remains in a0.
Note: Because CPP macros expand to a single line, macros requiring multi-line
expansions are implemented as assembler macros.
*******************************************************************************/
#ifdef __ASSEMBLER__
#ifdef __XTENSA_CALL0_ABI__
/* Call0 */
#define ENTRY(sz) entry1 sz
.macro entry1 size=0x10
addi sp, sp, -\size
s32i a0, sp, 0
.endm
#define ENTRY0
#define RET(sz) ret1 sz
.macro ret1 size=0x10
l32i a0, sp, 0
addi sp, sp, \size
ret
.endm
#define RET0 ret
#else
/* Windowed */
#define ENTRY(sz) entry sp, sz
#define ENTRY0 entry sp, 0x10
#define RET(sz) retw
#define RET0 retw
#endif
#endif
#endif /* XTENSA_CONTEXT_H */

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/*******************************************************************************
Copyright (c) 2006-2009 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc.
--------------------------------------------------------------------------------
RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
This header is the primary glue between generic Xtensa RTOS support
sources and a specific RTOS port for Xtensa. It contains definitions
and macros for use primarily by Xtensa assembly coded source files.
Macros in this header map callouts from generic Xtensa files to specific
RTOS functions. It may also be included in C source files.
Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa
architecture, using the Xtensa hardware abstraction layer (HAL) to deal
with configuration specifics.
Should be included by all Xtensa generic and RTOS port-specific sources.
*******************************************************************************/
#ifndef XTENSA_RTOS_H
#define XTENSA_RTOS_H
#ifdef __ASSEMBLER__
#include <xtensa/coreasm.h>
#else
#include <xtensa/config/core.h>
#endif
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
/*
Include any RTOS specific definitions that are needed by this header.
*/
#ifdef XCHAL_EXCM_LEVEL
#undef XCHAL_EXCM_LEVEL
#define XCHAL_EXCM_LEVEL 3
#endif
/*
Name of RTOS (for messages).
*/
#define XT_RTOS_NAME FreeRTOS
/*
Check some Xtensa configuration requirements and report error if not met.
Error messages can be customize to the RTOS port.
*/
#if !XCHAL_HAVE_XEA2
#error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
#endif
/*******************************************************************************
RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
Define callout macros used in generic Xtensa code to interact with the RTOS.
The macros are simply the function names for use in calls from assembler code.
Some of these functions may call back to generic functions in xtensa_context.h .
*******************************************************************************/
/*
Inform RTOS of entry into an interrupt handler that will affect it.
Allows RTOS to manage switch to any system stack and count nesting level.
Called after minimal context has been saved, with interrupts disabled.
RTOS port can call0 _xt_context_save to save the rest of the context.
May only be called from assembly code by the 'call0' instruction.
*/
// void XT_RTOS_INT_ENTER(void)
#define XT_RTOS_INT_ENTER _xt_int_enter
/*
Inform RTOS of completion of an interrupt handler, and give control to
RTOS to perform thread/task scheduling, switch back from any system stack
and restore the context, and return to the exit dispatcher saved in the
stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
leaving only a minimal part of the context to be restored by the exit
dispatcher. This function does not return to the place it was called from.
May only be called from assembly code by the 'call0' instruction.
*/
// void XT_RTOS_INT_EXIT(void)
#define XT_RTOS_INT_EXIT _xt_int_exit
/*
Inform RTOS of the occurrence of a tick timer interrupt.
If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
May be coded in or called from C or assembly, per ABI conventions.
RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
*/
// void XT_RTOS_TIMER_INT(void)
#define XT_RTOS_TIMER_INT _xt_timer_int
/*
Return in a15 the base address of the co-processor state save area for the
thread that triggered a co-processor exception, or 0 if no thread was running.
The state save area is structured as defined in xtensa_context.h and has size
XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
in interrupt handlers or the RTOS kernel. May only be called from assembly code
and by the 'call0' instruction. A result of 0 indicates an unrecoverable error.
The implementation may use only a2-4, a15 (all other regs must be preserved).
*/
// void* XT_RTOS_CP_STATE(void)
/*******************************************************************************
HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
This Xtensa RTOS port provides hooks for dynamically installing exception
and interrupt handlers to facilitate automated testing where each test
case can install its own handler for user exceptions and each interrupt
priority (level). This consists of an array of function pointers indexed
by interrupt priority, with index 0 being the user exception handler hook.
Each entry in the array is initially 0, and may be replaced by a function
pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
The handler for low and medium priority obeys ABI conventions so may be coded
in C. For the exception handler, the cause is the contents of the EXCCAUSE
reg, and the result is -1 if handled, else the cause (still needs handling).
For interrupt handlers, the cause is a mask of pending enabled interrupts at
that level, and the result is the same mask with the bits for the handled
interrupts cleared (those not cleared still need handling). This allows a test
case to either pre-handle or override the default handling for the exception
or interrupt level (see xtensa_vectors.S).
High priority handlers (including NMI) must be coded in assembly, are always
called by 'call0' regardless of ABI, must preserve all registers except a0,
and must not use or modify the interrupted stack. The hook argument 'cause'
is not passed and the result is ignored, so as not to burden the caller with
saving and restoring a2 (it assumes only one interrupt per level - see the
discussion in high priority interrupts in xtensa_vectors.S). The handler
therefore should be coded to prototype 'void h(void)' even though it plugs
into an array of handlers of prototype 'unsigned h(unsigned)'.
To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
*******************************************************************************/
#define XT_INTEXC_HOOK_NUM (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
#ifndef __ASSEMBLER__
typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause);
extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
#endif
/*******************************************************************************
CONVENIENCE INCLUSIONS.
Ensures RTOS specific files need only include this one Xtensa-generic header.
These headers are included last so they can use the RTOS definitions above.
*******************************************************************************/
#include "xtensa_context.h"
#ifdef XT_RTOS_TIMER_INT
#include "xtensa_timer.h"
#endif
#endif /* XTENSA_RTOS_H */

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/*******************************************************************************
Copyright (c) 2006-2009 by Tensilica Inc. ALL RIGHTS RESERVED.
These coded instructions, statements, and computer programs are the
copyrighted works and confidential proprietary information of Tensilica Inc.
They may not be modified, copied, reproduced, distributed, or disclosed to
third parties in any manner, medium, or form, in whole or in part, without
the prior written consent of Tensilica Inc.
--------------------------------------------------------------------------------
XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
This header contains definitions and macros for use primarily by Xtensa
RTOS assembly coded source files. It includes and uses the Xtensa hardware
abstraction layer (HAL) to deal with config specifics. It may also be
included in C source files.
User may edit to modify timer selection and to specify clock frequency and
tick duration to match timer interrupt to the real-time tick duration.
If the RTOS has no timer interrupt, then there is no tick timer and the
clock frequency is irrelevant, so all of these macros are left undefined
and the Xtensa core configuration need not have a timer.
*******************************************************************************/
#ifndef XTENSA_TIMER_H
#define XTENSA_TIMER_H
#ifdef XT_RTOS_TIMER_INT /* skip all this stuff if no timer int */
#ifdef __ASSEMBLER__
#include <xtensa/coreasm.h>
#endif
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
#include "xtensa_rtos.h" /* in case this wasn't included directly */
/*
Select timer to use for periodic tick, and determine its interrupt number
and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
in which case its validity is checked (it must exist in this core and must
not be on a high priority interrupt - an error will be reported in invalid).
Otherwise select the first low or medium priority interrupt timer available.
*/
#ifndef XT_TIMER_INDEX
#if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
#if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
#undef XT_TIMER_INDEX
#define XT_TIMER_INDEX 3
#endif
#endif
#if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
#if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
#undef XT_TIMER_INDEX
#define XT_TIMER_INDEX 2
#endif
#endif
#if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
#if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
#undef XT_TIMER_INDEX
#define XT_TIMER_INDEX 1
#endif
#endif
#if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
#if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
#undef XT_TIMER_INDEX
#define XT_TIMER_INDEX 0
#endif
#endif
#endif
#ifndef XT_TIMER_INDEX
#error "There is no suitable timer in this Xtensa configuration."
#endif
#define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX)
#define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
#define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
#define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM)
#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
#error "The timer selected by XT_TIMER_INDEX does not exist in this core."
#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
#error "The timer interrupt cannot be high priority (use medium or low)."
#endif
/*
Set processor clock frequency, used to determine clock divisor for timer tick.
User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
If using a supported board via the board-independent API defined in xtbsp.h,
this may be left undefined and frequency and tick divisor will be computed
and cached during run-time initialization.
NOTE ON SIMULATOR:
Under the Xtensa instruction set simulator, the frequency can only be estimated
because it depends on the speed of the host and the version of the simulator.
Also because it runs much slower than hardware, it is not possible to achieve
real-time performance for most applications under the simulator. A frequency
too low does not allow enough time between timer interrupts, starving threads.
To obtain a more convenient but non-real-time tick duration on the simulator,
compile with xt-xcc option "-DXT_SIMULATOR".
Adjust this frequency to taste (it's not real-time anyway!).
*/
#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
#define XT_CLOCK_FREQ 2000000 /* 2 MHz */
#else
#ifdef XT_XT2000 /* deprecated */
#define XT_CLOCK_FREQ 16500000 /* 16.5 MHz (XT2000 default) */
#else
#define XT_CLOCK_FREQ 80000000
#endif
#endif /* XT_SIMULATOR */
#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
#error "XT_CLOCK_FREQ must be defined for the target platform."
#endif
/*
Default number of timer "ticks" per second (default 100 for 10ms tick).
RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
User may redefine this to an optimal value for the application, either by
editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
"-DXT_TICKS_PER_SEC <value>" where <value> is a suitable number.
*/
#ifndef XT_TICK_PER_SEC
#define XT_TICK_PER_SEC 100 /* 10 ms tick = 100 ticks per second */
#endif
/*
Derviation of clock divisor for timer tick and interrupt (one per tick).
*/
#ifdef XT_CLOCK_FREQ
#define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
#else
#ifndef __ASSEMBLER__
extern unsigned _xt_tick_divisor;
extern void _xt_tick_divisor_init(void);
#endif
#define XT_TICK_DIVISOR _xt_tick_divisor
#endif
#endif /* XT_RTOS_TIMER_INT */
#endif /* XTENSA_TIMER_H */

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/*
* xtruntime.h -- general C definitions for single-threaded run-time
*
* Copyright (c) 2002-2008 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTRUNTIME_H
#define XTRUNTIME_H
#include <xtensa/config/core.h>
#include <xtensa/config/specreg.h>
#ifndef XTSTR
#define _XTSTR(x) # x
#define XTSTR(x) _XTSTR(x)
#endif
#define _xtos_set_execption_handler _xtos_set_exception_handler /* backward compatibility */
#define _xtos_set_saved_intenable _xtos_ints_on /* backward compatibility */
#define _xtos_clear_saved_intenable _xtos_ints_off /* backward compatibility */
#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
#ifdef __cplusplus
extern "C" {
#endif
/*typedef void (_xtos_timerdelta_func)(int);*/
#ifdef __cplusplus
typedef void (_xtos_handler_func)(...);
#else
typedef void (_xtos_handler_func)();
#endif
typedef _xtos_handler_func *_xtos_handler;
/*
* unsigned XTOS_SET_INTLEVEL(int intlevel);
* This macro sets the current interrupt level.
* The 'intlevel' parameter must be a constant.
* This macro returns a 32-bit value that must be passed to
* XTOS_RESTORE_INTLEVEL() to restore the previous interrupt level.
* XTOS_RESTORE_JUST_INTLEVEL() also does this, but in XEA2 configs
* it restores only PS.INTLEVEL rather than the entire PS register
* and thus is slower.
*/
#if !XCHAL_HAVE_INTERRUPTS
# define XTOS_SET_INTLEVEL(intlevel) 0
# define XTOS_SET_MIN_INTLEVEL(intlevel) 0
# define XTOS_RESTORE_INTLEVEL(restoreval)
# define XTOS_RESTORE_JUST_INTLEVEL(restoreval)
#elif XCHAL_HAVE_XEA2
/* In XEA2, we can simply safely set PS.INTLEVEL directly: */
/* NOTE: these asm macros don't modify memory, but they are marked
* as such to act as memory access barriers to the compiler because
* these macros are sometimes used to delineate critical sections;
* function calls are natural barriers (the compiler does not know
* whether a function modifies memory) unless declared to be inlined. */
# define XTOS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \
__asm__ __volatile__( "rsil %0, " XTSTR(intlevel) "\n" \
: "=a" (__tmp) : : "memory" ); \
__tmp;})
# define XTOS_SET_MIN_INTLEVEL(intlevel) ({ unsigned __tmp, __tmp2, __tmp3; \
__asm__ __volatile__( "rsr %0, " XTSTR(PS) "\n" /* get old (current) PS.INTLEVEL */ \
"movi %2, " XTSTR(intlevel) "\n" \
"extui %1, %0, 0, 4\n" /* keep only INTLEVEL bits of parameter */ \
"blt %2, %1, 1f\n" \
"rsil %0, " XTSTR(intlevel) "\n" \
"1:\n" \
: "=a" (__tmp), "=&a" (__tmp2), "=&a" (__tmp3) : : "memory" ); \
__tmp;})
# define XTOS_RESTORE_INTLEVEL(restoreval) do{ unsigned __tmp = (restoreval); \
__asm__ __volatile__( "wsr %0, " XTSTR(PS) " ; rsync\n" \
: : "a" (__tmp) : "memory" ); \
}while(0)
# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_intlevel(restoreval)
#else
/* In XEA1, we have to rely on INTENABLE register virtualization: */
extern unsigned _xtos_set_vpri( unsigned vpri );
extern unsigned _xtos_vpri_enabled; /* current virtual priority */
# define XTOS_SET_INTLEVEL(intlevel) _xtos_set_vpri(~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
# define XTOS_SET_MIN_INTLEVEL(intlevel) _xtos_set_vpri(_xtos_vpri_enabled & ~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
# define XTOS_RESTORE_INTLEVEL(restoreval) _xtos_set_vpri(restoreval)
# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_vpri(restoreval)
#endif
/*
* The following macros build upon the above. They are generally used
* instead of invoking the SET_INTLEVEL and SET_MIN_INTLEVEL macros directly.
* They all return a value that can be used with XTOS_RESTORE_INTLEVEL()
* or _xtos_restore_intlevel() or _xtos_restore_just_intlevel() to restore
* the effective interrupt level to what it was before the macro was invoked.
* In XEA2, the DISABLE macros are much faster than the MASK macros
* (in all configs, DISABLE sets the effective interrupt level, whereas MASK
* makes ensures the effective interrupt level is at least the level given
* without lowering it; in XEA2 with INTENABLE virtualization, these macros
* affect PS.INTLEVEL only, not the virtual priority, so DISABLE has partial
* MASK semantics).
*
* A typical critical section sequence might be:
* unsigned rval = XTOS_DISABLE_EXCM_INTERRUPTS;
* ... critical section ...
* XTOS_RESTORE_INTLEVEL(rval);
*/
/* Enable all interrupts (those activated with _xtos_ints_on()): */
#define XTOS_ENABLE_INTERRUPTS XTOS_SET_INTLEVEL(0)
/* Disable low priority level interrupts (they can interact with the OS): */
#define XTOS_DISABLE_LOWPRI_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
#define XTOS_MASK_LOWPRI_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
/* Disable interrupts that can interact with the OS: */
#define XTOS_DISABLE_EXCM_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL)
#define XTOS_MASK_EXCM_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_EXCM_LEVEL)
#if 0 /* XTOS_LOCK_LEVEL is not exported to applications */
/* Disable interrupts that can interact with the OS, or manipulate virtual INTENABLE: */
#define XTOS_DISABLE_LOCK_INTERRUPTS XTOS_SET_INTLEVEL(XTOS_LOCK_LEVEL)
#define XTOS_MASK_LOCK_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XTOS_LOCK_LEVEL)
#endif
/* Disable ALL interrupts (not for common use, particularly if one's processor
* configuration has high-level interrupts and one cares about their latency): */
#define XTOS_DISABLE_ALL_INTERRUPTS XTOS_SET_INTLEVEL(15)
extern unsigned int _xtos_ints_off( unsigned int mask );
extern unsigned int _xtos_ints_on( unsigned int mask );
extern unsigned _xtos_set_intlevel( int intlevel );
extern unsigned _xtos_set_min_intlevel( int intlevel );
extern unsigned _xtos_restore_intlevel( unsigned restoreval );
extern unsigned _xtos_restore_just_intlevel( unsigned restoreval );
extern _xtos_handler _xtos_set_interrupt_handler( int n, _xtos_handler f );
extern _xtos_handler _xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg );
extern _xtos_handler _xtos_set_exception_handler( int n, _xtos_handler f );
extern void _xtos_memep_initrams( void );
extern void _xtos_memep_enable( int flags );
/* Deprecated (but kept because they were documented): */
extern unsigned int _xtos_read_ints( void ); /* use xthal_get_interrupt() instead */
extern void _xtos_clear_ints( unsigned int mask ); /* use xthal_set_intclear() instead */
#if XCHAL_NUM_CONTEXTS > 1
extern unsigned _xtos_init_context(int context_num, int stack_size,
_xtos_handler_func *start_func, int arg1);
#endif
/* Deprecated: */
#if XCHAL_NUM_TIMERS > 0
extern void _xtos_timer_0_delta( int cycles );
#endif
#if XCHAL_NUM_TIMERS > 1
extern void _xtos_timer_1_delta( int cycles );
#endif
#if XCHAL_NUM_TIMERS > 2
extern void _xtos_timer_2_delta( int cycles );
#endif
#if XCHAL_NUM_TIMERS > 3
extern void _xtos_timer_3_delta( int cycles );
#endif
#ifdef __cplusplus
}
#endif
#endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */
#endif /* XTRUNTIME_H */