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add sdk header file

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eggman 2016-06-26 15:38:00 +09:00
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158
sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_8195A_H_
#define _HAL_8195A_H_
#include "platform_autoconf.h"
#include "basic_types.h"
#include "section_config.h"
#include "rtl8195a_sys_on.h"
#include "rtl8195a_peri_on.h"
#include "hal_platform.h"
#include "hal_pinmux.h"
#include "hal_api.h"
#include "hal_peri_on.h"
#include "hal_misc.h"
#include "hal_irqn.h"
#include "hal_vector_table.h"
#include "hal_diag.h"
#include "hal_spi_flash.h"
#include "hal_timer.h"
#include "hal_util.h"
#include "hal_efuse.h"
#include "hal_soc_ps_monitor.h"
#include "diag.h"
#include "hal_common.h"
#include "hal_soc_ps_monitor.h"
/* ----------------------------------------------------------------------------
-- Cortex M3 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
* @{
*/
#define __CM3_REV 0x0200 /**< Core revision r0p0 */
#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 1 /**< Vendor specific implementation of SysTickConfig is defined */
#include "core_cm3.h"
#ifdef CONFIG_TIMER_EN
#include "hal_timer.h"
#endif
#ifdef CONFIG_GDMA_EN
#include "hal_gdma.h"
#include "rtl8195a_gdma.h"
#endif
#ifdef CONFIG_GPIO_EN
#include "hal_gpio.h"
#include "rtl8195a_gpio.h"
#endif
#ifdef CONFIG_SPI_COM_EN
#include "hal_ssi.h"
#include "rtl8195a_ssi.h"
#endif
#ifdef CONFIG_UART_EN
#include "hal_uart.h"
#include "rtl8195a_uart.h"
#endif
#ifdef CONFIG_I2C_EN
#include "hal_i2c.h"
#include "rtl8195a_i2c.h"
#endif
#ifdef CONFIG_PCM_EN
#include "hal_pcm.h"
#include "rtl8195a_pcm.h"
#endif
#ifdef CONFIG_PWM_EN
#include "hal_pwm.h"
#include "rtl8195a_pwm.h"
#endif
#ifdef CONFIG_I2S_EN
#include "hal_i2s.h"
#include "rtl8195a_i2s.h"
#endif
#ifdef CONFIG_DAC_EN
#include "hal_dac.h"
#include "rtl8195a_dac.h"
#endif
#ifdef CONFIG_ADC_EN
#include "hal_adc.h"
#include "rtl8195a_adc.h"
#endif
#ifdef CONFIG_SDR_EN
#endif
#ifdef CONFIG_SPIC_EN
#endif
#ifdef CONFIG_SDIO_DEVICE_EN
#include "hal_sdio.h"
#endif
#ifdef CONFIG_NFC_EN
#include "hal_nfc.h"
#include "rtl8195a_nfc.h"
#endif
#ifdef CONFIG_WDG
#include "rtl8195a_wdt.h"
#endif
#ifdef CONFIG_USB_EN
#include "hal_usb.h"
#include "rtl8195a_usb.h"
#endif
#include "hal_log_uart.h"
// firmware information, located at the header of Image2
#define FW_VERSION (0x0100)
#define FW_SUBVERSION (0x0001)
#define FW_CHIP_ID (0x8195)
#define FW_CHIP_VER (0x01)
#define FW_BUS_TYPE (0x01) // the iNIC firmware type: USB/SDIO
#define FW_INFO_RSV1 (0x00) // the firmware information reserved
#define FW_INFO_RSV2 (0x00) // the firmware information reserved
#define FW_INFO_RSV3 (0x00) // the firmware information reserved
#define FW_INFO_RSV4 (0x00) // the firmware information reserved
#define FLASH_RESERVED_DATA_BASE 0x8000 // reserve 32K for Image1
#define FLASH_SYSTEM_DATA_ADDR 0x9000 // reserve 32K+4K for Image1 + Reserved data
// Flash Map for Calibration data
#define FLASH_CAL_DATA_BASE 0xA000
#define FLASH_CAL_DATA_ADDR(_offset) (FLASH_CAL_DATA_BASE + _offset)
#define FLASH_CAL_DATA_SIZE 0x1000
#define FLASH_SECTOR_SIZE 0x1000
// SPIC Calibration Data
#define FLASH_SPIC_PARA_OFFSET 0x80
#define FLASH_SPIC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SPIC_PARA_OFFSET)
// SDRC Calibration Data
#define FLASH_SDRC_PARA_OFFSET 0x180
#define FLASH_SDRC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SDRC_PARA_OFFSET)
// ADC Calibration Data
#define FLASH_ADC_PARA_OFFSET 0x200
#define FLASH_ADC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_ADC_PARA_OFFSET)
#endif //_HAL_8195A_H_

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sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_adc.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_ADC_H_
#define _RTL8195A_ADC_H_
//================ Register Bit Field ==========================
//2 REG_ADC_FIFO_READ
#define BIT_SHIFT_ADC_FIFO_RO 0
#define BIT_MASK_ADC_FIFO_RO 0xffffffffL
#define BIT_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
#define BIT_CTRL_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
#define BIT_GET_ADC_FIFO_RO(x) (((x) >> BIT_SHIFT_ADC_FIFO_RO) & BIT_MASK_ADC_FIFO_RO)
//2 REG_ADC_CONTROL
#define BIT_SHIFT_ADC_DBG_SEL 24
#define BIT_MASK_ADC_DBG_SEL 0x7
#define BIT_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
#define BIT_CTRL_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
#define BIT_GET_ADC_DBG_SEL(x) (((x) >> BIT_SHIFT_ADC_DBG_SEL) & BIT_MASK_ADC_DBG_SEL)
#define BIT_SHIFT_ADC_THRESHOLD 16
#define BIT_MASK_ADC_THRESHOLD 0x3f
#define BIT_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
#define BIT_CTRL_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
#define BIT_GET_ADC_THRESHOLD(x) (((x) >> BIT_SHIFT_ADC_THRESHOLD) & BIT_MASK_ADC_THRESHOLD)
#define BIT_SHIFT_ADC_BURST_SIZE 8
#define BIT_MASK_ADC_BURST_SIZE 0x1f
#define BIT_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
#define BIT_CTRL_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
#define BIT_GET_ADC_BURST_SIZE(x) (((x) >> BIT_SHIFT_ADC_BURST_SIZE) & BIT_MASK_ADC_BURST_SIZE)
#define BIT_ADC_ENDIAN BIT(3)
#define BIT_SHIFT_ADC_ENDIAN 3
#define BIT_MASK_ADC_ENDIAN 0x1
#define BIT_CTRL_ADC_ENDIAN(x) (((x) & BIT_MASK_ADC_ENDIAN) << BIT_SHIFT_ADC_ENDIAN)
#define BIT_ADC_OVERWRITE BIT(2)
#define BIT_SHIFT_ADC_OVERWRITE 2
#define BIT_MASK_ADC_OVERWRITE 0x1
#define BIT_CTRL_ADC_OVERWRITE(x) (((x) & BIT_MASK_ADC_OVERWRITE) << BIT_SHIFT_ADC_OVERWRITE)
#define BIT_ADC_ONESHOT BIT(1)
#define BIT_SHIFT_ADC_ONESHOT 1
#define BIT_MASK_ADC_ONESHOT 0x1
#define BIT_CTRL_ADC_ONESHOT(x) (((x) & BIT_MASK_ADC_ONESHOT) << BIT_SHIFT_ADC_ONESHOT)
#define BIT_ADC_COMP_ONLY BIT(0)
#define BIT_SHIFT_ADC_COMP_ONLY 0
#define BIT_MASK_ADC_COMP_ONLY 0x1
#define BIT_CTRL_ADC_COMP_ONLY(x) (((x) & BIT_MASK_ADC_COMP_ONLY) << BIT_SHIFT_ADC_COMP_ONLY)
//2 REG_ADC_INTR_EN
#define BIT_ADC_AWAKE_CPU_EN BIT(7)
#define BIT_SHIFT_ADC_AWAKE_CPU_EN 7
#define BIT_MASK_ADC_AWAKE_CPU_EN 0x1
#define BIT_CTRL_ADC_AWAKE_CPU_EN(x) (((x) & BIT_MASK_ADC_AWAKE_CPU_EN) << BIT_SHIFT_ADC_AWAKE_CPU_EN)
#define BIT_ADC_FIFO_RD_ERROR_EN BIT(6)
#define BIT_SHIFT_ADC_FIFO_RD_ERROR_EN 6
#define BIT_MASK_ADC_FIFO_RD_ERROR_EN 0x1
#define BIT_CTRL_ADC_FIFO_RD_ERROR_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_EN) << BIT_SHIFT_ADC_FIFO_RD_ERROR_EN)
#define BIT_ADC_FIFO_RD_REQ_EN BIT(5)
#define BIT_SHIFT_ADC_FIFO_RD_REQ_EN 5
#define BIT_MASK_ADC_FIFO_RD_REQ_EN 0x1
#define BIT_CTRL_ADC_FIFO_RD_REQ_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_EN) << BIT_SHIFT_ADC_FIFO_RD_REQ_EN)
#define BIT_ADC_FIFO_FULL_EN BIT(4)
#define BIT_SHIFT_ADC_FIFO_FULL_EN 4
#define BIT_MASK_ADC_FIFO_FULL_EN 0x1
#define BIT_CTRL_ADC_FIFO_FULL_EN(x) (((x) & BIT_MASK_ADC_FIFO_FULL_EN) << BIT_SHIFT_ADC_FIFO_FULL_EN)
#define BIT_ADC_COMP_3_EN BIT(3)
#define BIT_SHIFT_ADC_COMP_3_EN 3
#define BIT_MASK_ADC_COMP_3_EN 0x1
#define BIT_CTRL_ADC_COMP_3_EN(x) (((x) & BIT_MASK_ADC_COMP_3_EN) << BIT_SHIFT_ADC_COMP_3_EN)
#define BIT_ADC_COMP_2_EN BIT(2)
#define BIT_SHIFT_ADC_COMP_2_EN 2
#define BIT_MASK_ADC_COMP_2_EN 0x1
#define BIT_CTRL_ADC_COMP_2_EN(x) (((x) & BIT_MASK_ADC_COMP_2_EN) << BIT_SHIFT_ADC_COMP_2_EN)
#define BIT_ADC_COMP_1_EN BIT(1)
#define BIT_SHIFT_ADC_COMP_1_EN 1
#define BIT_MASK_ADC_COMP_1_EN 0x1
#define BIT_CTRL_ADC_COMP_1_EN(x) (((x) & BIT_MASK_ADC_COMP_1_EN) << BIT_SHIFT_ADC_COMP_1_EN)
#define BIT_ADC_COMP_0_EN BIT(0)
#define BIT_SHIFT_ADC_COMP_0_EN 0
#define BIT_MASK_ADC_COMP_0_EN 0x1
#define BIT_CTRL_ADC_COMP_0_EN(x) (((x) & BIT_MASK_ADC_COMP_0_EN) << BIT_SHIFT_ADC_COMP_0_EN)
//2 REG_ADC_INTR_STS
#define BIT_ADC_FIFO_THRESHOLD BIT(7)
#define BIT_SHIFT_ADC_FIFO_THRESHOLD 7
#define BIT_MASK_ADC_FIFO_THRESHOLD 0x1
#define BIT_CTRL_ADC_FIFO_THRESHOLD(x) (((x) & BIT_MASK_ADC_FIFO_THRESHOLD) << BIT_SHIFT_ADC_FIFO_THRESHOLD)
#define BIT_ADC_FIFO_RD_ERROR_ST BIT(6)
#define BIT_SHIFT_ADC_FIFO_RD_ERROR_ST 6
#define BIT_MASK_ADC_FIFO_RD_ERROR_ST 0x1
#define BIT_CTRL_ADC_FIFO_RD_ERROR_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_ST) << BIT_SHIFT_ADC_FIFO_RD_ERROR_ST)
#define BIT_ADC_FIFO_RD_REQ_ST BIT(5)
#define BIT_SHIFT_ADC_FIFO_RD_REQ_ST 5
#define BIT_MASK_ADC_FIFO_RD_REQ_ST 0x1
#define BIT_CTRL_ADC_FIFO_RD_REQ_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_ST) << BIT_SHIFT_ADC_FIFO_RD_REQ_ST)
#define BIT_ADC_FIFO_FULL_ST BIT(4)
#define BIT_SHIFT_ADC_FIFO_FULL_ST 4
#define BIT_MASK_ADC_FIFO_FULL_ST 0x1
#define BIT_CTRL_ADC_FIFO_FULL_ST(x) (((x) & BIT_MASK_ADC_FIFO_FULL_ST) << BIT_SHIFT_ADC_FIFO_FULL_ST)
#define BIT_ADC_COMP_3_ST BIT(3)
#define BIT_SHIFT_ADC_COMP_3_ST 3
#define BIT_MASK_ADC_COMP_3_ST 0x1
#define BIT_CTRL_ADC_COMP_3_ST(x) (((x) & BIT_MASK_ADC_COMP_3_ST) << BIT_SHIFT_ADC_COMP_3_ST)
#define BIT_ADC_COMP_2_ST BIT(2)
#define BIT_SHIFT_ADC_COMP_2_ST 2
#define BIT_MASK_ADC_COMP_2_ST 0x1
#define BIT_CTRL_ADC_COMP_2_ST(x) (((x) & BIT_MASK_ADC_COMP_2_ST) << BIT_SHIFT_ADC_COMP_2_ST)
#define BIT_ADC_COMP_1_ST BIT(1)
#define BIT_SHIFT_ADC_COMP_1_ST 1
#define BIT_MASK_ADC_COMP_1_ST 0x1
#define BIT_CTRL_ADC_COMP_1_ST(x) (((x) & BIT_MASK_ADC_COMP_1_ST) << BIT_SHIFT_ADC_COMP_1_ST)
#define BIT_ADC_COMP_0_ST BIT(0)
#define BIT_SHIFT_ADC_COMP_0_ST 0
#define BIT_MASK_ADC_COMP_0_ST 0x1
#define BIT_CTRL_ADC_COMP_0_ST(x) (((x) & BIT_MASK_ADC_COMP_0_ST) << BIT_SHIFT_ADC_COMP_0_ST)
//2 REG_ADC_COMP_VALUE_L
#define BIT_SHIFT_ADC_COMP_TH_1 16
#define BIT_MASK_ADC_COMP_TH_1 0xffff
#define BIT_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
#define BIT_CTRL_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
#define BIT_GET_ADC_COMP_TH_1(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_1) & BIT_MASK_ADC_COMP_TH_1)
#define BIT_SHIFT_ADC_COMP_TH_0 0
#define BIT_MASK_ADC_COMP_TH_0 0xffff
#define BIT_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
#define BIT_CTRL_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
#define BIT_GET_ADC_COMP_TH_0(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_0) & BIT_MASK_ADC_COMP_TH_0)
//2 REG_ADC_COMP_VALUE_H
#define BIT_SHIFT_ADC_COMP_TH_3 16
#define BIT_MASK_ADC_COMP_TH_3 0xffff
#define BIT_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
#define BIT_CTRL_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
#define BIT_GET_ADC_COMP_TH_3(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_3) & BIT_MASK_ADC_COMP_TH_3)
#define BIT_SHIFT_ADC_COMP_TH_2 0
#define BIT_MASK_ADC_COMP_TH_2 0xffff
#define BIT_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
#define BIT_CTRL_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
#define BIT_GET_ADC_COMP_TH_2(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_2) & BIT_MASK_ADC_COMP_TH_2)
//2 REG_ADC_COMP_SET
#define BIT_SHIFT_ADC_GREATER_THAN 0
#define BIT_MASK_ADC_GREATER_THAN 0xf
#define BIT_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
#define BIT_CTRL_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
#define BIT_GET_ADC_GREATER_THAN(x) (((x) >> BIT_SHIFT_ADC_GREATER_THAN) & BIT_MASK_ADC_GREATER_THAN)
//2 REG_ADC_POWER
#define BIT_SHIFT_ADC_PWR_CUT_CNTR 16
#define BIT_MASK_ADC_PWR_CUT_CNTR 0xff
#define BIT_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
#define BIT_CTRL_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
#define BIT_GET_ADC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_ADC_PWR_CUT_CNTR) & BIT_MASK_ADC_PWR_CUT_CNTR)
#define BIT_ADC_FIFO_ON_ST BIT(11)
#define BIT_SHIFT_ADC_FIFO_ON_ST 11
#define BIT_MASK_ADC_FIFO_ON_ST 0x1
#define BIT_CTRL_ADC_FIFO_ON_ST(x) (((x) & BIT_MASK_ADC_FIFO_ON_ST) << BIT_SHIFT_ADC_FIFO_ON_ST)
#define BIT_ADC_ISO_ON_ST BIT(10)
#define BIT_SHIFT_ADC_ISO_ON_ST 10
#define BIT_MASK_ADC_ISO_ON_ST 0x1
#define BIT_CTRL_ADC_ISO_ON_ST(x) (((x) & BIT_MASK_ADC_ISO_ON_ST) << BIT_SHIFT_ADC_ISO_ON_ST)
#define BIT_ADC_PWR33_ON_ST BIT(9)
#define BIT_SHIFT_ADC_PWR33_ON_ST 9
#define BIT_MASK_ADC_PWR33_ON_ST 0x1
#define BIT_CTRL_ADC_PWR33_ON_ST(x) (((x) & BIT_MASK_ADC_PWR33_ON_ST) << BIT_SHIFT_ADC_PWR33_ON_ST)
#define BIT_ADC_PWR12_ON_ST BIT(8)
#define BIT_SHIFT_ADC_PWR12_ON_ST 8
#define BIT_MASK_ADC_PWR12_ON_ST 0x1
#define BIT_CTRL_ADC_PWR12_ON_ST(x) (((x) & BIT_MASK_ADC_PWR12_ON_ST) << BIT_SHIFT_ADC_PWR12_ON_ST)
#define BIT_ADC_ISO_MANUAL BIT(3)
#define BIT_SHIFT_ADC_ISO_MANUAL 3
#define BIT_MASK_ADC_ISO_MANUAL 0x1
#define BIT_CTRL_ADC_ISO_MANUAL(x) (((x) & BIT_MASK_ADC_ISO_MANUAL) << BIT_SHIFT_ADC_ISO_MANUAL)
#define BIT_ADC_PWR33_MANUAL BIT(2)
#define BIT_SHIFT_ADC_PWR33_MANUAL 2
#define BIT_MASK_ADC_PWR33_MANUAL 0x1
#define BIT_CTRL_ADC_PWR33_MANUAL(x) (((x) & BIT_MASK_ADC_PWR33_MANUAL) << BIT_SHIFT_ADC_PWR33_MANUAL)
#define BIT_ADC_PWR12_MANUAL BIT(1)
#define BIT_SHIFT_ADC_PWR12_MANUAL 1
#define BIT_MASK_ADC_PWR12_MANUAL 0x1
#define BIT_CTRL_ADC_PWR12_MANUAL(x) (((x) & BIT_MASK_ADC_PWR12_MANUAL) << BIT_SHIFT_ADC_PWR12_MANUAL)
#define BIT_ADC_PWR_AUTO BIT(0)
#define BIT_SHIFT_ADC_PWR_AUTO 0
#define BIT_MASK_ADC_PWR_AUTO 0x1
#define BIT_CTRL_ADC_PWR_AUTO(x) (((x) & BIT_MASK_ADC_PWR_AUTO) << BIT_SHIFT_ADC_PWR_AUTO)
//2 REG_ADC_ANAPAR_AD0
#define BIT_SHIFT_ADC_ANAPAR_AD0 2
#define BIT_MASK_ADC_ANAPAR_AD0 0x3fffffff
#define BIT_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
#define BIT_CTRL_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
#define BIT_GET_ADC_ANAPAR_AD0(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD0) & BIT_MASK_ADC_ANAPAR_AD0)
#define BIT_ADC_AUDIO_EN BIT(1)
#define BIT_SHIFT_ADC_AUDIO_EN 1
#define BIT_MASK_ADC_AUDIO_EN 0x1
#define BIT_CTRL_ADC_AUDIO_EN(x) (((x) & BIT_MASK_ADC_AUDIO_EN) << BIT_SHIFT_ADC_AUDIO_EN)
#define BIT_ADC_EN_MANUAL BIT(0)
#define BIT_SHIFT_ADC_EN_MANUAL 0
#define BIT_MASK_ADC_EN_MANUAL 0x1
#define BIT_CTRL_ADC_EN_MANUAL(x) (((x) & BIT_MASK_ADC_EN_MANUAL) << BIT_SHIFT_ADC_EN_MANUAL)
//2 REG_ADC_ANAPAR_AD1
#define BIT_SHIFT_ADC_ANAPAR_AD1 0
#define BIT_MASK_ADC_ANAPAR_AD1 0xffffffffL
#define BIT_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
#define BIT_CTRL_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
#define BIT_GET_ADC_ANAPAR_AD1(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD1) & BIT_MASK_ADC_ANAPAR_AD1)
//2 REG_ADC_ANAPAR_AD2
#define BIT_SHIFT_ADC_ANAPAR_AD2 0
#define BIT_MASK_ADC_ANAPAR_AD2 0xffffffffL
#define BIT_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
#define BIT_CTRL_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
#define BIT_GET_ADC_ANAPAR_AD2(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD2) & BIT_MASK_ADC_ANAPAR_AD2)
//2 REG_ADC_ANAPAR_AD3
#define BIT_SHIFT_ADC_ANAPAR_AD3 0
#define BIT_MASK_ADC_ANAPAR_AD3 0xffffffffL
#define BIT_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
#define BIT_CTRL_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
#define BIT_GET_ADC_ANAPAR_AD3(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD3) & BIT_MASK_ADC_ANAPAR_AD3)
//2 REG_ADC_ANAPAR_AD4
#define BIT_SHIFT_ADC_ANAPAR_AD4 0
#define BIT_MASK_ADC_ANAPAR_AD4 0xffffffffL
#define BIT_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
#define BIT_CTRL_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
#define BIT_GET_ADC_ANAPAR_AD4(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD4) & BIT_MASK_ADC_ANAPAR_AD4)
//2 REG_ADC_ANAPAR_AD5
#define BIT_SHIFT_ADC_ANAPAR_AD5 0
#define BIT_MASK_ADC_ANAPAR_AD5 0xffffffffL
#define BIT_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
#define BIT_CTRL_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
#define BIT_GET_ADC_ANAPAR_AD5(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD5) & BIT_MASK_ADC_ANAPAR_AD5)
//2 REG_ADC_CALI_DATA
#define BIT_SHIFT_ADC_CALI_DATA_6 16
#define BIT_MASK_ADC_CALI_DATA_6 0xffff
#define BIT_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
#define BIT_CTRL_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
#define BIT_GET_ADC_CALI_DATA_6(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_6) & BIT_MASK_ADC_CALI_DATA_6)
#define BIT_SHIFT_ADC_CALI_DATA_0 0
#define BIT_MASK_ADC_CALI_DATA_0 0xffff
#define BIT_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
#define BIT_CTRL_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
#define BIT_GET_ADC_CALI_DATA_0(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_0) & BIT_MASK_ADC_CALI_DATA_0)
//================ Register Reg Field =========================
#define REG_ADC_FIFO_READ 0x0000
#define REG_ADC_CONTROL 0x0004
#define REG_ADC_INTR_EN 0x0008
#define REG_ADC_INTR_STS 0x000C
#define REG_ADC_COMP_VALUE_L 0x0010
#define REG_ADC_COMP_VALUE_H 0x0014
#define REG_ADC_COMP_SET 0x0018
#define REG_ADC_POWER 0x001C
#define REG_ADC_ANAPAR_AD0 0x0020
#define REG_ADC_ANAPAR_AD1 0x0024
#define REG_ADC_ANAPAR_AD2 0x0028
#define REG_ADC_ANAPAR_AD3 0x002C
#define REG_ADC_ANAPAR_AD4 0x0030
#define REG_ADC_ANAPAR_AD5 0x0034
#define REG_ADC_CALI_DATA 0x0038
//================ ADC HAL related enumeration ==================
//================ ADC Function Prototypes =====================
#define HAL_ADC_WRITE32(addr, value) HAL_WRITE32(ADC_REG_BASE,addr,value)
#define HAL_ADC_READ32(addr) HAL_READ32(ADC_REG_BASE,addr)
RTK_STATUS HalADCInit8195a(IN VOID *Data);
RTK_STATUS HalADCDeInit8195a(IN VOID *Data);
RTK_STATUS HalADCEnableRtl8195a(IN VOID *Data);
RTK_STATUS HalADCIntrCtrl8195a(IN VOID *Data);
u32 HalADCReceiveRtl8195a(IN VOID *Data);
u32 HalADCReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg);
#endif

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#ifndef _RTL8195A_DAC_H_
#define _RTL8195A_DAC_H_
//================ Register Bit Field ==========================
//2 REG_DAC0_FIFO_WR
#define BIT_SHIFT_DAC0_FIFO_WO 0
#define BIT_MASK_DAC0_FIFO_WO 0xffffffffL
#define BIT_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
#define BIT_CTRL_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
#define BIT_GET_DAC0_FIFO_WO(x) (((x) >> BIT_SHIFT_DAC0_FIFO_WO) & BIT_MASK_DAC0_FIFO_WO)
//2 REG_DAC_CTRL
#define BIT_SHIFT_DAC_DELTA_SIGMA 25
#define BIT_MASK_DAC_DELTA_SIGMA 0x7
#define BIT_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
#define BIT_CTRL_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
#define BIT_GET_DAC_DELTA_SIGMA(x) (((x) >> BIT_SHIFT_DAC_DELTA_SIGMA) & BIT_MASK_DAC_DELTA_SIGMA)
#define BIT_DAC_BYPASS_DSC BIT(24)
#define BIT_SHIFT_DAC_BYPASS_DSC 24
#define BIT_MASK_DAC_BYPASS_DSC 0x1
#define BIT_CTRL_DAC_BYPASS_DSC(x) (((x) & BIT_MASK_DAC_BYPASS_DSC) << BIT_SHIFT_DAC_BYPASS_DSC)
#define BIT_SHIFT_DAC_DSC_DBG_SEL 19
#define BIT_MASK_DAC_DSC_DBG_SEL 0x3
#define BIT_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
#define BIT_CTRL_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
#define BIT_GET_DAC_DSC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DSC_DBG_SEL) & BIT_MASK_DAC_DSC_DBG_SEL)
#define BIT_SHIFT_DAC_DBG_SEL 16
#define BIT_MASK_DAC_DBG_SEL 0x7
#define BIT_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
#define BIT_CTRL_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
#define BIT_GET_DAC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DBG_SEL) & BIT_MASK_DAC_DBG_SEL)
#define BIT_SHIFT_DAC_BURST_SIZE 8
#define BIT_MASK_DAC_BURST_SIZE 0xf
#define BIT_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
#define BIT_CTRL_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
#define BIT_GET_DAC_BURST_SIZE(x) (((x) >> BIT_SHIFT_DAC_BURST_SIZE) & BIT_MASK_DAC_BURST_SIZE)
#define BIT_DAC_FILTER_SETTLE BIT(4)
#define BIT_SHIFT_DAC_FILTER_SETTLE 4
#define BIT_MASK_DAC_FILTER_SETTLE 0x1
#define BIT_CTRL_DAC_FILTER_SETTLE(x) (((x) & BIT_MASK_DAC_FILTER_SETTLE) << BIT_SHIFT_DAC_FILTER_SETTLE)
#define BIT_DAC_OV_OPTION BIT(3)
#define BIT_SHIFT_DAC_OV_OPTION 3
#define BIT_MASK_DAC_OV_OPTION 0x1
#define BIT_CTRL_DAC_OV_OPTION(x) (((x) & BIT_MASK_DAC_OV_OPTION) << BIT_SHIFT_DAC_OV_OPTION)
#define BIT_DAC_ENDIAN BIT(2)
#define BIT_SHIFT_DAC_ENDIAN 2
#define BIT_MASK_DAC_ENDIAN 0x1
#define BIT_CTRL_DAC_ENDIAN(x) (((x) & BIT_MASK_DAC_ENDIAN) << BIT_SHIFT_DAC_ENDIAN)
#define BIT_DAC_SPEED BIT(1)
#define BIT_SHIFT_DAC_SPEED 1
#define BIT_MASK_DAC_SPEED 0x1
#define BIT_CTRL_DAC_SPEED(x) (((x) & BIT_MASK_DAC_SPEED) << BIT_SHIFT_DAC_SPEED)
#define BIT_DAC_FIFO_EN BIT(0)
#define BIT_SHIFT_DAC_FIFO_EN 0
#define BIT_MASK_DAC_FIFO_EN 0x1
#define BIT_CTRL_DAC_FIFO_EN(x) (((x) & BIT_MASK_DAC_FIFO_EN) << BIT_SHIFT_DAC_FIFO_EN)
//2 REG_DAC_INTR_CTRL
#define BIT_DAC_DSC_OVERFLOW1_EN BIT(6)
#define BIT_SHIFT_DAC_DSC_OVERFLOW1_EN 6
#define BIT_MASK_DAC_DSC_OVERFLOW1_EN 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW1_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW1_EN)
#define BIT_DAC_DSC_OVERFLOW0_EN BIT(5)
#define BIT_SHIFT_DAC_DSC_OVERFLOW0_EN 5
#define BIT_MASK_DAC_DSC_OVERFLOW0_EN 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW0_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW0_EN)
#define BIT_DAC__WRITE_ERROR_EN BIT(4)
#define BIT_SHIFT_DAC__WRITE_ERROR_EN 4
#define BIT_MASK_DAC__WRITE_ERROR_EN 0x1
#define BIT_CTRL_DAC__WRITE_ERROR_EN(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_EN) << BIT_SHIFT_DAC__WRITE_ERROR_EN)
#define BIT_DAC_FIFO_STOP_EN BIT(3)
#define BIT_SHIFT_DAC_FIFO_STOP_EN 3
#define BIT_MASK_DAC_FIFO_STOP_EN 0x1
#define BIT_CTRL_DAC_FIFO_STOP_EN(x) (((x) & BIT_MASK_DAC_FIFO_STOP_EN) << BIT_SHIFT_DAC_FIFO_STOP_EN)
#define BIT_DAC_FIFO_OVERFLOW_EN BIT(2)
#define BIT_SHIFT_DAC_FIFO_OVERFLOW_EN 2
#define BIT_MASK_DAC_FIFO_OVERFLOW_EN 0x1
#define BIT_CTRL_DAC_FIFO_OVERFLOW_EN(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_EN) << BIT_SHIFT_DAC_FIFO_OVERFLOW_EN)
#define BIT_DAC_FIFO_WR_REQ_EN BIT(1)
#define BIT_SHIFT_DAC_FIFO_WR_REQ_EN 1
#define BIT_MASK_DAC_FIFO_WR_REQ_EN 0x1
#define BIT_CTRL_DAC_FIFO_WR_REQ_EN(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_EN) << BIT_SHIFT_DAC_FIFO_WR_REQ_EN)
#define BIT_DAC_FIFO_FULL_EN BIT(0)
#define BIT_SHIFT_DAC_FIFO_FULL_EN 0
#define BIT_MASK_DAC_FIFO_FULL_EN 0x1
#define BIT_CTRL_DAC_FIFO_FULL_EN(x) (((x) & BIT_MASK_DAC_FIFO_FULL_EN) << BIT_SHIFT_DAC_FIFO_FULL_EN)
//2 REG_DAC_INTR_STS
#define BIT_DAC_DSC_OVERFLOW1_ST BIT(6)
#define BIT_SHIFT_DAC_DSC_OVERFLOW1_ST 6
#define BIT_MASK_DAC_DSC_OVERFLOW1_ST 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW1_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW1_ST)
#define BIT_DAC_DSC_OVERFLOW0_ST BIT(5)
#define BIT_SHIFT_DAC_DSC_OVERFLOW0_ST 5
#define BIT_MASK_DAC_DSC_OVERFLOW0_ST 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW0_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW0_ST)
#define BIT_DAC__WRITE_ERROR_ST BIT(4)
#define BIT_SHIFT_DAC__WRITE_ERROR_ST 4
#define BIT_MASK_DAC__WRITE_ERROR_ST 0x1
#define BIT_CTRL_DAC__WRITE_ERROR_ST(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_ST) << BIT_SHIFT_DAC__WRITE_ERROR_ST)
#define BIT_DAC_FIFO_STOP_ST BIT(3)
#define BIT_SHIFT_DAC_FIFO_STOP_ST 3
#define BIT_MASK_DAC_FIFO_STOP_ST 0x1
#define BIT_CTRL_DAC_FIFO_STOP_ST(x) (((x) & BIT_MASK_DAC_FIFO_STOP_ST) << BIT_SHIFT_DAC_FIFO_STOP_ST)
#define BIT_DAC_FIFO_OVERFLOW_ST BIT(2)
#define BIT_SHIFT_DAC_FIFO_OVERFLOW_ST 2
#define BIT_MASK_DAC_FIFO_OVERFLOW_ST 0x1
#define BIT_CTRL_DAC_FIFO_OVERFLOW_ST(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_ST) << BIT_SHIFT_DAC_FIFO_OVERFLOW_ST)
#define BIT_DAC_FIFO_WR_REQ_ST BIT(1)
#define BIT_SHIFT_DAC_FIFO_WR_REQ_ST 1
#define BIT_MASK_DAC_FIFO_WR_REQ_ST 0x1
#define BIT_CTRL_DAC_FIFO_WR_REQ_ST(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_ST) << BIT_SHIFT_DAC_FIFO_WR_REQ_ST)
#define BIT_DAC_FIFO_FULL_ST BIT(0)
#define BIT_SHIFT_DAC_FIFO_FULL_ST 0
#define BIT_MASK_DAC_FIFO_FULL_ST 0x1
#define BIT_CTRL_DAC_FIFO_FULL_ST(x) (((x) & BIT_MASK_DAC_FIFO_FULL_ST) << BIT_SHIFT_DAC_FIFO_FULL_ST)
//2 REG_DAC_PWR_CTRL
#define BIT_SHIFT_DAC_PWR_CUT_CNTR 16
#define BIT_MASK_DAC_PWR_CUT_CNTR 0xff
#define BIT_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
#define BIT_CTRL_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
#define BIT_GET_DAC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_DAC_PWR_CUT_CNTR) & BIT_MASK_DAC_PWR_CUT_CNTR)
#define BIT_ST_DAC_FIFO_ON BIT(11)
#define BIT_SHIFT_ST_DAC_FIFO_ON 11
#define BIT_MASK_ST_DAC_FIFO_ON 0x1
#define BIT_CTRL_ST_DAC_FIFO_ON(x) (((x) & BIT_MASK_ST_DAC_FIFO_ON) << BIT_SHIFT_ST_DAC_FIFO_ON)
#define BIT_ST_DAC_ISO_ON BIT(10)
#define BIT_SHIFT_ST_DAC_ISO_ON 10
#define BIT_MASK_ST_DAC_ISO_ON 0x1
#define BIT_CTRL_ST_DAC_ISO_ON(x) (((x) & BIT_MASK_ST_DAC_ISO_ON) << BIT_SHIFT_ST_DAC_ISO_ON)
#define BIT_ST_DAC_PWR33_ON BIT(9)
#define BIT_SHIFT_ST_DAC_PWR33_ON 9
#define BIT_MASK_ST_DAC_PWR33_ON 0x1
#define BIT_CTRL_ST_DAC_PWR33_ON(x) (((x) & BIT_MASK_ST_DAC_PWR33_ON) << BIT_SHIFT_ST_DAC_PWR33_ON)
#define BIT_ST_DAC_PWR12_ON BIT(8)
#define BIT_SHIFT_ST_DAC_PWR12_ON 8
#define BIT_MASK_ST_DAC_PWR12_ON 0x1
#define BIT_CTRL_ST_DAC_PWR12_ON(x) (((x) & BIT_MASK_ST_DAC_PWR12_ON) << BIT_SHIFT_ST_DAC_PWR12_ON)
#define BIT_DAC_ISO_MANU BIT(3)
#define BIT_SHIFT_DAC_ISO_MANU 3
#define BIT_MASK_DAC_ISO_MANU 0x1
#define BIT_CTRL_DAC_ISO_MANU(x) (((x) & BIT_MASK_DAC_ISO_MANU) << BIT_SHIFT_DAC_ISO_MANU)
#define BIT_DAC_PWR33_MANU BIT(2)
#define BIT_SHIFT_DAC_PWR33_MANU 2
#define BIT_MASK_DAC_PWR33_MANU 0x1
#define BIT_CTRL_DAC_PWR33_MANU(x) (((x) & BIT_MASK_DAC_PWR33_MANU) << BIT_SHIFT_DAC_PWR33_MANU)
#define BIT_DAC_PWR12_MANU BIT(1)
#define BIT_SHIFT_DAC_PWR12_MANU 1
#define BIT_MASK_DAC_PWR12_MANU 0x1
#define BIT_CTRL_DAC_PWR12_MANU(x) (((x) & BIT_MASK_DAC_PWR12_MANU) << BIT_SHIFT_DAC_PWR12_MANU)
#define BIT_DAC_PWR_AUTO BIT(0)
#define BIT_SHIFT_DAC_PWR_AUTO 0
#define BIT_MASK_DAC_PWR_AUTO 0x1
#define BIT_CTRL_DAC_PWR_AUTO(x) (((x) & BIT_MASK_DAC_PWR_AUTO) << BIT_SHIFT_DAC_PWR_AUTO)
//2 REG_DAC_ANAPAR_DA0
#define BIT_SHIFT_PWR_ALL_CNTR 12
#define BIT_MASK_PWR_ALL_CNTR 0xfffff
#define BIT_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
#define BIT_CTRL_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
#define BIT_GET_PWR_ALL_CNTR(x) (((x) >> BIT_SHIFT_PWR_ALL_CNTR) & BIT_MASK_PWR_ALL_CNTR)
#define BIT_SHIFT_PWR_FUP_CNTR 0
#define BIT_MASK_PWR_FUP_CNTR 0xfff
#define BIT_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
#define BIT_CTRL_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
#define BIT_GET_PWR_FUP_CNTR(x) (((x) >> BIT_SHIFT_PWR_FUP_CNTR) & BIT_MASK_PWR_FUP_CNTR)
//2 REG_DAC_ANAPAR_DA1
#define BIT_FUP_EN BIT(31)
#define BIT_SHIFT_FUP_EN 31
#define BIT_MASK_FUP_EN 0x1
#define BIT_CTRL_FUP_EN(x) (((x) & BIT_MASK_FUP_EN) << BIT_SHIFT_FUP_EN)
#define BIT_SHIFT_ANAPAR_DA 8
#define BIT_MASK_ANAPAR_DA 0x7fffff
#define BIT_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
#define BIT_CTRL_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
#define BIT_GET_ANAPAR_DA(x) (((x) >> BIT_SHIFT_ANAPAR_DA) & BIT_MASK_ANAPAR_DA)
#define BIT_D_POW_DACVREF BIT(7)
#define BIT_SHIFT_D_POW_DACVREF 7
#define BIT_MASK_D_POW_DACVREF 0x1
#define BIT_CTRL_D_POW_DACVREF(x) (((x) & BIT_MASK_D_POW_DACVREF) << BIT_SHIFT_D_POW_DACVREF)
#define BIT_D_POW_VREF2 BIT(6)
#define BIT_SHIFT_D_POW_VREF2 6
#define BIT_MASK_D_POW_VREF2 0x1
#define BIT_CTRL_D_POW_VREF2(x) (((x) & BIT_MASK_D_POW_VREF2) << BIT_SHIFT_D_POW_VREF2)
#define BIT_D_POW_MBIAS BIT(5)
#define BIT_SHIFT_D_POW_MBIAS 5
#define BIT_MASK_D_POW_MBIAS 0x1
#define BIT_CTRL_D_POW_MBIAS(x) (((x) & BIT_MASK_D_POW_MBIAS) << BIT_SHIFT_D_POW_MBIAS)
#define BIT_D_POW_DIV4 BIT(4)
#define BIT_SHIFT_D_POW_DIV4 4
#define BIT_MASK_D_POW_DIV4 0x1
#define BIT_CTRL_D_POW_DIV4(x) (((x) & BIT_MASK_D_POW_DIV4) << BIT_SHIFT_D_POW_DIV4)
#define BIT_D_POW_DF1SE_R BIT(3)
#define BIT_SHIFT_D_POW_DF1SE_R 3
#define BIT_MASK_D_POW_DF1SE_R 0x1
#define BIT_CTRL_D_POW_DF1SE_R(x) (((x) & BIT_MASK_D_POW_DF1SE_R) << BIT_SHIFT_D_POW_DF1SE_R)
#define BIT_D_POW_DF2SE_L BIT(2)
#define BIT_SHIFT_D_POW_DF2SE_L 2
#define BIT_MASK_D_POW_DF2SE_L 0x1
#define BIT_CTRL_D_POW_DF2SE_L(x) (((x) & BIT_MASK_D_POW_DF2SE_L) << BIT_SHIFT_D_POW_DF2SE_L)
#define BIT_D_POW_DAC_R BIT(1)
#define BIT_SHIFT_D_POW_DAC_R 1
#define BIT_MASK_D_POW_DAC_R 0x1
#define BIT_CTRL_D_POW_DAC_R(x) (((x) & BIT_MASK_D_POW_DAC_R) << BIT_SHIFT_D_POW_DAC_R)
#define BIT_D_POW_DAC_L BIT(0)
#define BIT_SHIFT_D_POW_DAC_L 0
#define BIT_MASK_D_POW_DAC_L 0x1
#define BIT_CTRL_D_POW_DAC_L(x) (((x) & BIT_MASK_D_POW_DAC_L) << BIT_SHIFT_D_POW_DAC_L)
//================ Register Reg Field =========================
#define REG_DAC0_FIFO_WR 0x0000
#define REG_DAC_CTRL 0x0004
#define REG_DAC_INTR_CTRL 0x0008
#define REG_DAC_INTR_STS 0x000C
#define REG_DAC_PWR_CTRL 0x0010
#define REG_DAC_ANAPAR_DA0 0x0014
#define REG_DAC_ANAPAR_DA1 0x0018
//================ DAC HAL related enumeration ==================
//================ DAC HAL Macro ===========================
#define HAL_DAC_WRITE32(dacidx, addr, value) HAL_WRITE32(DAC_REG_BASE+dacidx*0x800 \
,addr,value)
#define HAL_DAC_READ32(dacidx, addr) HAL_READ32(DAC_REG_BASE+dacidx*0x800,addr)
//================ DAC Function Prototypes =====================
RTK_STATUS HalDACInit8195a(IN VOID *Data);
RTK_STATUS HalDACDeInit8195a(IN VOID *Data);
RTK_STATUS HalDACEnableRtl8195a(IN VOID *Data);
RTK_STATUS HalDACIntrCtrl8195a(IN VOID *Data);
u8 HalDACSendRtl8195a(IN VOID *Data);
u32 HalDACReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_GDMA_H_
#define _RTL8195A_GDMA_H_
// Define GDMA Handshake interface with peripheral, 0 -> GDMA0, 1-> GDMA1
// Set this Hnadshake interface map to register REG_PESOC_SOC_CTRL
#define GDMA_HANDSHAKE_UART0_TX 0
#define GDMA_HANDSHAKE_UART0_RX 1
#define GDMA_HANDSHAKE_UART1_TX 2
#define GDMA_HANDSHAKE_UART1_RX 3
#define GDMA_HANDSHAKE_UART2_TX 14 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_UART2_RX 14 // Only on GDMA 1, hardware fixed
#define GDMA_HANDSHAKE_SSI0_TX 4
#define GDMA_HANDSHAKE_SSI0_RX 5
#define GDMA_HANDSHAKE_SSI1_TX 6
#define GDMA_HANDSHAKE_SSI1_RX 7
#define GDMA_HANDSHAKE_SSI2_TX 15 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_SSI2_RX 15 // Only on GDMA 1, hardware fixed
#define GDMA_HANDSHAKE_I2C0_TX 8
#define GDMA_HANDSHAKE_I2C0_RX 9
#define GDMA_HANDSHAKE_I2C1_TX 10
#define GDMA_HANDSHAKE_I2C1_RX 11
#define GDMA_HANDSHAKE_ADC 12
#define GDMA_HANDSHAKE_DAC0 13 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_DAC1 13 // Only on GDMA 1, hardware fixed
#define HAL_GDMAX_READ32(GdmaIndex, addr) \
HAL_READ32(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE32(GdmaIndex, addr, value) \
HAL_WRITE32((GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF)), addr, value)
#define HAL_GDMAX_READ16(GdmaIndex, addr) \
HAL_READ16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE16(GdmaIndex, addr, value) \
HAL_WRITE16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
#define HAL_GDMAX_READ8(GdmaIndex, addr) \
HAL_READ8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE8(GdmaIndex, addr, value) \
HAL_WRITE8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
#define GDMA_CH_MAX 0x06
#define REG_GDMA_CH_OFF 0x058
#define REG_GDMA_CH_SAR 0x000
#define REG_GDMA_CH_DAR 0x008
#define REG_GDMA_CH_LLP 0x010
#define REG_GDMA_CH_CTL 0x018
#define REG_GDMA_CH_SSTAT 0x020
#define REG_GDMA_CH_DSTAT 0x028
#define REG_GDMA_CH_SSTATAR 0x030
#define REG_GDMA_CH_DSTATAR 0x038
#define REG_GDMA_CH_CFG 0x040
#define REG_GDMA_CH_SGR 0x048
#define REG_GDMA_CH_DSR 0x050
//3 Interrupt Registers
#define REG_GDMA_RAW_INT_BASE 0x2C0
#define REG_GDMA_RAW_INT_TFR 0x2C0
#define REG_GDMA_RAW_INT_BLOCK 0x2c8
#define REG_GDMA_RAW_INT_SRC_TRAN 0x2D0
#define REG_GDMA_RAW_INT_DST_TRAN 0x2D8
#define REG_GDMA_RAW_INT_ERR 0x2E0
#define REG_GDMA_STATUS_INT_BASE 0x2E8
#define REG_GDMA_STATUS_INT_TFR 0x2E8
#define REG_GDMA_STATUS_INT_BLOCK 0x2F0
#define REG_GDMA_STATUS_INT_SRC_TRAN 0x2F8
#define REG_GDMA_STATUS_INT_DST_TRAN 0x300
#define REG_GDMA_STATUS_INT_ERR 0x308
#define REG_GDMA_MASK_INT_BASE 0x310
#define REG_GDMA_MASK_INT_TFR 0x310
#define REG_GDMA_MASK_INT_BLOCK 0x318
#define REG_GDMA_MASK_INT_SRC_TRAN 0x320
#define REG_GDMA_MASK_INT_DST_TRAN 0x328
#define REG_GDMA_MASK_INT_INT_ERR 0x330
#define REG_GDMA_CLEAR_INT_BASE 0x338
#define REG_GDMA_CLEAR_INT_TFR 0x338
#define REG_GDMA_CLEAR_INT_BLOCK 0x340
#define REG_GDMA_CLEAR_INT_SRC_TRAN 0x348
#define REG_GDMA_CLEAR_INT_DST_TRAN 0x350
#define REG_GDMA_CLEAR_INT_ERR 0x358
#define REG_GDMA_STATUS_INT 0x360
//3 Software handshaking Registers
#define REG_GDMA_REQ_SRC 0x368
#define REG_GDMA_REQ_DST 0x370
#define REG_GDMA_REQ_SGL_REQ 0x378
#define REG_GDMA_REQ_DST_REQ 0x380
#define REG_GDMA_REQ_LST_SRC 0x388
#define REG_GDMA_REQ_LST_DST 0x390
//3 Miscellaneous Registers
#define REG_GDMA_DMAC_CFG 0x398
#define REG_GDMA_CH_EN 0x3A0
#define REG_GDMA_DMA_ID 0x3A8
#define REG_GDMA_DMA_TEST 0x3B0
#define REG_GDMA_DMA_COM_PARAMS6 0x3C8
#define REG_GDMA_DMA_COM_PARAMS5 0x3D0
#define REG_GDMA_DMA_COM_PARAMS4 0x3D8
#define REG_GDMA_DMA_COM_PARAMS3 0x3E0
#define REG_GDMA_DMA_COM_PARAMS2 0x3E8
#define REG_GDMA_DMA_COM_PARAMS1 0x3F0
#define REG_GDMA_DMA_COM_PARAMS0 0x3F8
//3 CTL Register Bit Control
#define BIT_SHIFT_CTLX_LO_INT_EN 0
#define BIT_MASK_CTLX_LO_INT_EN 0x1
#define BIT_CTLX_LO_INT_EN(x)(((x) & BIT_MASK_CTLX_LO_INT_EN) << BIT_SHIFT_CTLX_LO_INT_EN)
#define BIT_INVC_CTLX_LO_INT_EN (~(BIT_MASK_CTLX_LO_INT_EN << BIT_SHIFT_CTLX_LO_INT_EN))
#define BIT_SHIFT_CTLX_LO_DST_TR_WIDTH 1
#define BIT_MASK_CTLX_LO_DST_TR_WIDTH 0x7
#define BIT_CTLX_LO_DST_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_DST_TR_WIDTH) << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH)
#define BIT_INVC_CTLX_LO_DST_TR_WIDTH (~(BIT_MASK_CTLX_LO_DST_TR_WIDTH << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH))
#define BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH 4
#define BIT_MASK_CTLX_LO_SRC_TR_WIDTH 0x7
#define BIT_CTLX_LO_SRC_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_SRC_TR_WIDTH) << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH)
#define BIT_INVC_CTLX_LO_SRC_TR_WIDTH (~(BIT_MASK_CTLX_LO_SRC_TR_WIDTH << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH))
#define BIT_SHIFT_CTLX_LO_DINC 7
#define BIT_MASK_CTLX_LO_DINC 0x3
#define BIT_CTLX_LO_DINC(x)(((x) & BIT_MASK_CTLX_LO_DINC) << BIT_SHIFT_CTLX_LO_DINC)
#define BIT_INVC_CTLX_LO_DINC (~(BIT_MASK_CTLX_LO_DINC << BIT_SHIFT_CTLX_LO_DINC))
#define BIT_SHIFT_CTLX_LO_SINC 9
#define BIT_MASK_CTLX_LO_SINC 0x3
#define BIT_CTLX_LO_SINC(x)(((x) & BIT_MASK_CTLX_LO_SINC) << BIT_SHIFT_CTLX_LO_SINC)
#define BIT_INVC_CTLX_LO_SINC (~(BIT_MASK_CTLX_LO_SINC << BIT_SHIFT_CTLX_LO_SINC))
#define BIT_SHIFT_CTLX_LO_DEST_MSIZE 11
#define BIT_MASK_CTLX_LO_DEST_MSIZE 0x7
#define BIT_CTLX_LO_DEST_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_DEST_MSIZE) << BIT_SHIFT_CTLX_LO_DEST_MSIZE)
#define BIT_INVC_CTLX_LO_DEST_MSIZE (~(BIT_MASK_CTLX_LO_DEST_MSIZE << BIT_SHIFT_CTLX_LO_DEST_MSIZE))
#define BIT_SHIFT_CTLX_LO_SRC_MSIZE 14
#define BIT_MASK_CTLX_LO_SRC_MSIZE 0x7
#define BIT_CTLX_LO_SRC_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_SRC_MSIZE) << BIT_SHIFT_CTLX_LO_SRC_MSIZE)
#define BIT_INVC_CTLX_LO_SRC_MSIZE (~(BIT_MASK_CTLX_LO_SRC_MSIZE << BIT_SHIFT_CTLX_LO_SRC_MSIZE))
#define BIT_SHIFT_CTLX_LO_SRC_GATHER_EN 17
#define BIT_MASK_CTLX_LO_SRC_GATHER_EN 0x1
#define BIT_CTLX_LO_SRC_GATHER_EN(x)(((x) & BIT_MASK_CTLX_LO_SRC_GATHER_EN) << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN)
#define BIT_INVC_CTLX_LO_SRC_GATHER_EN (~(BIT_MASK_CTLX_LO_SRC_GATHER_EN << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN))
#define BIT_SHIFT_CTLX_LO_DST_SCATTER_EN 18
#define BIT_MASK_CTLX_LO_DST_SCATTER_EN 0x1
#define BIT_CTLX_LO_DST_SCATTER_EN(x)(((x) & BIT_MASK_CTLX_LO_DST_SCATTER_EN) << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN)
#define BIT_INVC_CTLX_LO_DST_SCATTER_EN (~(BIT_MASK_CTLX_LO_DST_SCATTER_EN << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN))
#define BIT_SHIFT_CTLX_LO_TT_FC 20
#define BIT_MASK_CTLX_LO_TT_FC 0x7
#define BIT_CTLX_LO_TT_FC(x)(((x) & BIT_MASK_CTLX_LO_TT_FC) << BIT_SHIFT_CTLX_LO_TT_FC)
#define BIT_INVC_CTLX_LO_TT_FC (~(BIT_MASK_CTLX_LO_TT_FC << BIT_SHIFT_CTLX_LO_TT_FC))
#define BIT_SHIFT_CTLX_LO_DMS 23
#define BIT_MASK_CTLX_LO_DMS 0x3
#define BIT_CTLX_LO_DMS(x)(((x) & BIT_MASK_CTLX_LO_DMS) << BIT_MASK_CTLX_LO_DMS)
#define BIT_INVC_CTLX_LO_DMS (~(BIT_MASK_CTLX_LO_DMS << BIT_SHIFT_CTLX_LO_DMS))
#define BIT_SHIFT_CTLX_LO_SMS 25
#define BIT_MASK_CTLX_LO_SMS 0x3
#define BIT_CTLX_LO_SMS(x)(((x) & BIT_MASK_CTLX_LO_SMS) << BIT_SHIFT_CTLX_LO_SMS)
#define BIT_INVC_CTLX_LO_SMS (~(BIT_MASK_CTLX_LO_SMS << BIT_SHIFT_CTLX_LO_SMS))
#define BIT_SHIFT_CTLX_LO_LLP_DST_EN 27
#define BIT_MASK_CTLX_LO_LLP_DST_EN 0x1
#define BIT_CTLX_LO_LLP_DST_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_DST_EN) << BIT_SHIFT_CTLX_LO_LLP_DST_EN)
#define BIT_INVC_CTLX_LO_LLP_DST_EN (~(BIT_MASK_CTLX_LO_LLP_DST_EN << BIT_SHIFT_CTLX_LO_LLP_DST_EN))
#define BIT_SHIFT_CTLX_LO_LLP_SRC_EN 28
#define BIT_MASK_CTLX_LO_LLP_SRC_EN 0x1
#define BIT_CTLX_LO_LLP_SRC_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_SRC_EN) << BIT_SHIFT_CTLX_LO_LLP_SRC_EN)
#define BIT_INVC_CTLX_LO_LLP_SRC_EN (~(BIT_MASK_CTLX_LO_LLP_SRC_EN << BIT_SHIFT_CTLX_LO_LLP_SRC_EN))
#define BIT_SHIFT_CTLX_UP_BLOCK_BS 0
#define BIT_MASK_CTLX_UP_BLOCK_BS 0xFFF
#define BIT_CTLX_UP_BLOCK_BS(x)(((x) & BIT_MASK_CTLX_UP_BLOCK_BS) << BIT_SHIFT_CTLX_UP_BLOCK_BS)
#define BIT_INVC_CTLX_UP_BLOCK_BS (~(BIT_MASK_CTLX_UP_BLOCK_BS << BIT_SHIFT_CTLX_UP_BLOCK_BS))
#define BIT_SHIFT_CTLX_UP_DONE 12
#define BIT_MASK_CTLX_UP_DONE 0x1
#define BIT_CTLX_UP_DONE(x)(((x) & BIT_MASK_CTLX_UP_DONE) << BIT_SHIFT_CTLX_UP_DONE)
#define BIT_INVC_CTLX_UP_DONE (~(BIT_MASK_CTLX_UP_DONE << BIT_SHIFT_CTLX_UP_DONE))
//3 CFG Register Bit Control
#define BIT_SHIFT_CFGX_LO_CH_PRIOR 5
#define BIT_MASK_CFGX_LO_CH_PRIOR 0x7
#define BIT_CFGX_LO_CH_PRIOR(x)(((x) & BIT_MASK_CFGX_LO_CH_PRIOR) << BIT_SHIFT_CFGX_LO_CH_PRIOR)
#define BIT_INVC_CFGX_LO_CH_PRIOR (~(BIT_MASK_CFGX_LO_CH_PRIOR << BIT_SHIFT_CFGX_LO_CH_PRIOR))
#define BIT_SHIFT_CFGX_LO_CH_SUSP 8
#define BIT_MASK_CFGX_LO_CH_SUSP 0x1
#define BIT_CFGX_LO_CH_SUSP(x)(((x) & BIT_MASK_CFGX_LO_CH_SUSP) << BIT_SHIFT_CFGX_LO_CH_SUSP)
#define BIT_INVC_CFGX_LO_CH_SUSP (~(BIT_MASK_CFGX_LO_CH_SUSP << BIT_SHIFT_CFGX_LO_CH_SUSP))
#define BIT_SHIFT_CFGX_LO_FIFO_EMPTY 9
#define BIT_MASK_CFGX_LO_FIFO_EMPTY 0x1
#define BIT_CFGX_LO_FIFO_EMPTY(x)(((x) & BIT_MASK_CFGX_LO_FIFO_EMPTY) << BIT_SHIFT_CFGX_LO_FIFO_EMPTY)
#define BIT_INVC_CFGX_LO_FIFO_EMPTY (~(BIT_MASK_CFGX_LO_FIFO_EMPTY << BIT_SHIFT_CFGX_LO_FIFO_EMPTY))
#define BIT_SHIFT_CFGX_LO_HS_SEL_DST 10
#define BIT_MASK_CFGX_LO_HS_SEL_DST 0x1
#define BIT_CFGX_LO_HS_SEL_DST(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_DST) << BIT_SHIFT_CFGX_LO_HS_SEL_DST)
#define BIT_INVC_CFGX_LO_HS_SEL_DST (~(BIT_MASK_CFGX_LO_HS_SEL_DST << BIT_SHIFT_CFGX_LO_HS_SEL_DST))
#define BIT_SHIFT_CFGX_LO_HS_SEL_SRC 11
#define BIT_MASK_CFGX_LO_HS_SEL_SRC 0x1
#define BIT_CFGX_LO_HS_SEL_SRC(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_SRC) << BIT_SHIFT_CFGX_LO_HS_SEL_SRC)
#define BIT_INVC_CFGX_LO_HS_SEL_SRC (~(BIT_MASK_CFGX_LO_HS_SEL_SRC << BIT_SHIFT_CFGX_LO_HS_SEL_SRC))
#define BIT_SHIFT_CFGX_LO_LOCK_CH_L 12
#define BIT_MASK_CFGX_LO_LOCK_CH_L 0x3
#define BIT_CFGX_LO_LOCK_CH_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH_L) << BIT_SHIFT_CFGX_LO_LOCK_CH_L)
#define BIT_INVC_CFGX_LO_LOCK_CH_L (~(BIT_MASK_CFGX_LO_LOCK_CH_L << BIT_SHIFT_CFGX_LO_LOCK_CH_L))
#define BIT_SHIFT_CFGX_LO_LOCK_B_L 14
#define BIT_MASK_CFGX_LO_LOCK_B_L 0x3
#define BIT_CFGX_LO_LOCK_B_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B_L) << BIT_SHIFT_CFGX_LO_LOCK_B_L)
#define BIT_INVC_CFGX_LO_LOCK_B_L (~(BIT_MASK_CFGX_LO_LOCK_B_L << BIT_SHIFT_CFGX_LO_LOCK_B_L))
#define BIT_SHIFT_CFGX_LO_LOCK_CH 16
#define BIT_MASK_CFGX_LO_LOCK_CH 0x1
#define BIT_CFGX_LO_LOCK_CH(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH) << BIT_SHIFT_CFGX_LO_LOCK_CH)
#define BIT_INVC_CFGX_LO_LOCK_CH (~(BIT_MASK_CFGX_LO_LOCK_CH << BIT_SHIFT_CFGX_LO_LOCK_CH))
#define BIT_SHIFT_CFGX_LO_LOCK_B 17
#define BIT_MASK_CFGX_LO_LOCK_B 0x1
#define BIT_CFGX_LO_LOCK_B(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B) << BIT_SHIFT_CFGX_LO_LOCK_B)
#define BIT_INVC_CFGX_LO_LOCK_B (~(BIT_MASK_CFGX_LO_LOCK_B << BIT_SHIFT_CFGX_LO_LOCK_B))
#define BIT_SHIFT_CFGX_LO_DST_HS_POL 18
#define BIT_MASK_CFGX_LO_DST_HS_POL 0x1
#define BIT_CFGX_LO_DST_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_DST_HS_POL) << BIT_SHIFT_CFGX_LO_DST_HS_POL)
#define BIT_INVC_CFGX_LO_DST_HS_POL (~(BIT_MASK_CFGX_LO_DST_HS_POL << BIT_SHIFT_CFGX_LO_DST_HS_POL))
#define BIT_SHIFT_CFGX_LO_SRC_HS_POL 19
#define BIT_MASK_CFGX_LO_SRC_HS_POL 0x1
#define BIT_CFGX_LO_SRC_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_SRC_HS_POL) << BIT_SHIFT_CFGX_LO_SRC_HS_POL)
#define BIT_INVC_CFGX_LO_SRC_HS_POL (~(BIT_MASK_CFGX_LO_SRC_HS_POL << BIT_SHIFT_CFGX_LO_SRC_HS_POL))
#define BIT_SHIFT_CFGX_LO_MAX_ABRST 20
#define BIT_MASK_CFGX_LO_MAX_ABRST 0x3FF
#define BIT_CFGX_LO_MAX_ABRST(x)(((x) & BIT_MASK_CFGX_LO_MAX_ABRST) << BIT_SHIFT_CFGX_LO_MAX_ABRST)
#define BIT_INVC_CFGX_LO_MAX_ABRST (~(BIT_MASK_CFGX_LO_MAX_ABRST << BIT_SHIFT_CFGX_LO_MAX_ABRST))
#define BIT_SHIFT_CFGX_LO_RELOAD_SRC 30
#define BIT_MASK_CFGX_LO_RELOAD_SRC 0x1
#define BIT_CFGX_LO_RELOAD_SRC(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_SRC) << BIT_SHIFT_CFGX_LO_RELOAD_SRC)
#define BIT_INVC_CFGX_LO_RELOAD_SRC (~(BIT_MASK_CFGX_LO_RELOAD_SRC << BIT_SHIFT_CFGX_LO_RELOAD_SRC))
#define BIT_SHIFT_CFGX_LO_RELOAD_DST 31
#define BIT_MASK_CFGX_LO_RELOAD_DST 0x1
#define BIT_CFGX_LO_RELOAD_DST(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_DST) << BIT_SHIFT_CFGX_LO_RELOAD_DST)
#define BIT_INVC_CFGX_LO_RELOAD_DST (~(BIT_MASK_CFGX_LO_RELOAD_DST << BIT_SHIFT_CFGX_LO_RELOAD_DST))
#define BIT_SHIFT_CFGX_UP_FCMODE 0
#define BIT_MASK_CFGX_UP_FCMODE 0x1
#define BIT_CFGX_UP_FCMODE(x)(((x) & BIT_MASK_CFGX_UP_FCMODE) << BIT_SHIFT_CFGX_UP_FCMODE)
#define BIT_INVC_CFGX_UP_FCMODE (~(BIT_MASK_CFGX_UP_FCMODE << BIT_SHIFT_CFGX_UP_FCMODE))
#define BIT_SHIFT_CFGX_UP_FIFO_MODE 1
#define BIT_MASK_CFGX_UP_FIFO_MODE 0x1
#define BIT_CFGX_UP_FIFO_MODE(x)(((x) & BIT_MASK_CFGX_UP_FIFO_MODE) << BIT_SHIFT_CFGX_UP_FIFO_MODE)
#define BIT_INVC_CFGX_UP_FIFO_MODE (~(BIT_MASK_CFGX_UP_FIFO_MODE << BIT_SHIFT_CFGX_UP_FIFO_MODE))
#define BIT_SHIFT_CFGX_UP_PROTCTL 2
#define BIT_MASK_CFGX_UP_PROTCTL 0x7
#define BIT_CFGX_UP_PROTCTL(x)(((x) & BIT_MASK_CFGX_UP_PROTCTL) << BIT_SHIFT_CFGX_UP_PROTCTL)
#define BIT_INVC_CFGX_UP_PROTCTL (~(BIT_MASK_CFGX_UP_PROTCTL << BIT_SHIFT_CFGX_UP_PROTCTL))
#define BIT_SHIFT_CFGX_UP_DS_UPD_EN 5
#define BIT_MASK_CFGX_UP_DS_UPD_EN 0x1
#define BIT_CFGX_UP_DS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_DS_UPD_EN) << BIT_SHIFT_CFGX_UP_DS_UPD_EN)
#define BIT_INVC_CFGX_UP_DS_UPD_EN (~(BIT_MASK_CFGX_UP_DS_UPD_EN << BIT_SHIFT_CFGX_UP_DS_UPD_EN))
#define BIT_SHIFT_CFGX_UP_SS_UPD_EN 6
#define BIT_MASK_CFGX_UP_SS_UPD_EN 0x1
#define BIT_CFGX_UP_SS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_SS_UPD_EN) << BIT_SHIFT_CFGX_UP_SS_UPD_EN)
#define BIT_INVC_CFGX_UP_SS_UPD_EN (~(BIT_MASK_CFGX_UP_SS_UPD_EN << BIT_SHIFT_CFGX_UP_SS_UPD_EN))
#define BIT_SHIFT_CFGX_UP_SRC_PER 7
#define BIT_MASK_CFGX_UP_SRC_PER 0xF
#define BIT_CFGX_UP_SRC_PER(x)(((x) & BIT_MASK_CFGX_UP_SRC_PER) << BIT_SHIFT_CFGX_UP_SRC_PER)
#define BIT_INVC_CFGX_UP_SRC_PER (~(BIT_MASK_CFGX_UP_SRC_PER << BIT_SHIFT_CFGX_UP_SRC_PER))
#define BIT_SHIFT_CFGX_UP_DEST_PER 11
#define BIT_MASK_CFGX_UP_DEST_PER 0xF
#define BIT_CFGX_UP_DEST_PER(x)(((x) & BIT_MASK_CFGX_UP_DEST_PER) << BIT_SHIFT_CFGX_UP_DEST_PER)
#define BIT_INVC_CFGX_UP_DEST_PER (~(BIT_MASK_CFGX_UP_DEST_PER << BIT_SHIFT_CFGX_UP_DEST_PER))
typedef enum _GDMA_CHANNEL_NUM_ {
GdmaNoCh = 0x0000,
GdmaCh0 = 0x0101,
GdmaCh1 = 0x0202,
GdmaCh2 = 0x0404,
GdmaCh3 = 0x0808,
GdmaCh4 = 0x1010,
GdmaCh5 = 0x2020,
GdmaCh6 = 0x4040,
GdmaCh7 = 0x8080,
GdmaAllCh = 0xffff
}GDMA_CHANNEL_NUM, *PGDMA_CHANNEL_NUM;
//3 CTL register struct
typedef enum _GDMA_CTL_TT_FC_TYPE_ {
TTFCMemToMem = 0x00,
TTFCMemToPeri = 0x01,
TTFCPeriToMem = 0x02
}GDMA_CTL_TT_FC_TYPE, *PGDMA_CTL_TT_FC_TYPE;
//Max type = Bus Width
typedef enum _GDMA_CTL_TR_WIDTH_ {
TrWidthOneByte = 0x00,
TrWidthTwoBytes = 0x01,
TrWidthFourBytes = 0x02
}GDMA_CTL_TR_WIDTH, *PGDMA_CTL_TR_WIDTH;
typedef enum _GDMA_CTL_MSIZE_ {
MsizeOne = 0x00,
MsizeFour = 0x01,
MsizeEight = 0x02
}GDMA_CTL_MSIZE, *PGDMA_CTL_MSIZE;
typedef enum _GDMA_INC_TYPE_ {
IncType = 0x00,
DecType = 0x01,
NoChange = 0x02
}GDMA_INC_TYPE, *PGDMA_INC_TYPE;
typedef struct _GDMA_CTL_REG_ {
GDMA_CTL_TT_FC_TYPE TtFc;
GDMA_CTL_TR_WIDTH DstTrWidth;
GDMA_CTL_TR_WIDTH SrcTrWidth;
GDMA_INC_TYPE Dinc;
GDMA_INC_TYPE Sinc;
GDMA_CTL_MSIZE DestMsize;
GDMA_CTL_MSIZE SrcMsize;
u8 IntEn :1; // Bit 0
u8 SrcGatherEn :1; // Bit 1
u8 DstScatterEn :1; // Bit 2
u8 LlpDstEn :1; // Bit 3
u8 LlpSrcEn :1; // Bit 4
u8 Done :1; // Bit 5
u8 Rsvd6To7 :2; //Bit 6 -7
u16 BlockSize;
}GDMA_CTL_REG, *PGDMA_CTL_REG;
//3 CFG Register Structure
typedef enum _GDMA_CH_PRIORITY_ {
Prior0 = 0,
Prior1 = 1,
Prior2 = 2,
Prior3 = 3,
Prior4 = 4,
Prior5 = 5,
Prior6 = 6,
Prior7 = 7
}GDMA_CH_PRIORITY, *PGDMA_CH_PRIORITY;
typedef enum _GDMA_LOCK_LEVEL_ {
OverComplDmaTransfer = 0x00,
OverComplDmaBlockTransfer = 0x01,
OverComplDmaTransation = 0x02
}GDMA_LOCK_LEVEL, *PGDMA_LOCK_LEVEL;
typedef struct _GDMA_CFG_REG_ {
GDMA_CH_PRIORITY ChPrior;
GDMA_LOCK_LEVEL LockBL;
GDMA_LOCK_LEVEL LockChL;
u16 MaxAbrst;
u8 SrcPer;
u8 DestPer;
u16 ChSusp :1; //Bit 0
u16 FifoEmpty :1; //Bit 1
u16 HsSelDst :1; //Bit 2
u16 HsSelSrc :1; //Bit 3
u16 LockCh :1; //Bit 4
u16 LockB :1; //Bit 5
u16 DstHsPol :1; //Bit 6
u16 SrcHsPol :1; //Bit 7
u16 ReloadSrc :1; //Bit 8
u16 ReloadDst :1; //Bit 9
u16 FifoMode :1; //Bit 10
u16 DsUpdEn :1; //Bit 11
u16 SsUpdEn :1; //Bit 12
u16 Rsvd13To15 :3;
}GDMA_CFG_REG, *PGDMA_CFG_REG;
typedef enum _GDMA_ISR_TYPE_ {
TransferType = 0x1,
BlockType = 0x2,
SrcTransferType = 0x4,
DstTransferType = 0x8,
ErrType = 0x10
}GDMA_ISR_TYPE, *PGDMA_ISR_TYPE;
VOID
HalGdmaOnOffRtl8195a (
IN VOID *Data
);
BOOL
HalGdamChInitRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaChSetingRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaChBlockSetingRtl8195a(
IN VOID *Data
);
VOID
HalGdmaChDisRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChEnRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChIsrEnAndDisRtl8195a (
IN VOID *Data
);
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChCleanAutoSrcRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChCleanAutoDstRtl8195a (
IN VOID *Data
);
u32
HalGdmaQueryDArRtl8195a(
IN VOID *Data
);
u32
HalGdmaQuerySArRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaQueryChEnRtl8195a (
IN VOID *Data
);
#ifdef CONFIG_CHIP_E_CUT
_LONG_CALL_ BOOL
HalGdmaChBlockSetingRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ u32
HalGdmaQueryDArRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ u32
HalGdmaQuerySArRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ BOOL
HalGdmaQueryChEnRtl8195a_V04 (
IN VOID *Data
);
#endif // #ifdef CONFIG_CHIP_E_CUT
#endif

352
sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gpio.h Normal file
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@ -0,0 +1,352 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_GPIO_H_
#define _RTL8195A_GPIO_H_
#include "hal_api.h"
#include "hal_gpio.h"
#define GPIO_PORTA_DR 0x00 // data register
#define GPIO_PORTA_DDR 0x04 // data direction
#define GPIO_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software
#define GPIO_PORTB_DR 0x0c // data register
#define GPIO_PORTB_DDR 0x10 // data direction
#define GPIO_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software
#define GPIO_PORTC_DR 0x18 // data register
#define GPIO_PORTC_DDR 0x1c // data direction
#define GPIO_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software
//1 Only the PORTA can be configured to generate interrupts
#define GPIO_INT_EN 0x30 // Interrupt enable register
#define GPIO_INT_MASK 0x34 // Interrupt mask
#define GPIO_INT_TYPE 0x38 // Interrupt type(level/edge) register
#define GPIO_INT_POLARITY 0x3C // Interrupt polarity(Active low/high) register
#define GPIO_INT_STATUS 0x40 // Interrupt status
#define GPIO_INT_RAWSTATUS 0x44 // Interrupt status without mask
#define GPIO_DEBOUNCE 0x48 // Interrupt signal debounce
#define GPIO_PORTA_EOI 0x4c // Clear interrupt
#define GPIO_EXT_PORTA 0x50 // GPIO IN read or OUT read back
#define GPIO_EXT_PORTB 0x54 // GPIO IN read or OUT read back
#define GPIO_EXT_PORTC 0x58 // GPIO IN read or OUT read back
#define GPIO_INT_SYNC 0x60 // Is level-sensitive interrupt being sync sith PCLK
enum {
HAL_GPIO_HIGHZ = 0,
HAL_GPIO_PULL_LOW = 1,
HAL_GPIO_PULL_HIGH = 2
};
//======================================================
// ROM Function prototype
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
static __inline HAL_Status
GPIO_Lock (
VOID
)
{
HAL_Status Status;
if (_pHAL_Gpio_Adapter->EnterCritical) {
_pHAL_Gpio_Adapter->EnterCritical();
}
if(_pHAL_Gpio_Adapter->Locked) {
Status = HAL_BUSY;
}
else {
_pHAL_Gpio_Adapter->Locked = 1;
Status = HAL_OK;
}
if (_pHAL_Gpio_Adapter->ExitCritical) {
_pHAL_Gpio_Adapter->ExitCritical();
}
return Status;
}
static __inline VOID
GPIO_UnLock (
VOID
)
{
if (_pHAL_Gpio_Adapter->EnterCritical) {
_pHAL_Gpio_Adapter->EnterCritical();
}
_pHAL_Gpio_Adapter->Locked = 0;
if (_pHAL_Gpio_Adapter->ExitCritical) {
_pHAL_Gpio_Adapter->ExitCritical();
}
}
_LONG_CALL_ extern u32
HAL_GPIO_IrqHandler_8195a(
IN VOID *pData
);
_LONG_CALL_ extern u32
HAL_GPIO_MbedIrqHandler_8195a(
IN VOID *pData
);
_LONG_CALL_ HAL_Status
HAL_GPIO_IntCtrl_8195a(
HAL_GPIO_PIN *GPIO_Pin,
u32 En
);
_LONG_CALL_ HAL_Status
HAL_GPIO_Init_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_DeInit_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_GPIO_PIN_STATE
HAL_GPIO_ReadPin_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_WritePin_8195a(
HAL_GPIO_PIN *GPIO_Pin,
HAL_GPIO_PIN_STATE Pin_State
);
_LONG_CALL_ HAL_Status
HAL_GPIO_RegIrq_8195a(
IN PIRQ_HANDLE pIrqHandle
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UnRegIrq_8195a(
IN PIRQ_HANDLE pIrqHandle
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UserRegIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin,
VOID *IrqHandler,
VOID *IrqData
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UserUnRegIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_MaskIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UnMaskIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_IntDebounce_8195a(
HAL_GPIO_PIN *GPIO_Pin,
u8 Enable
);
_LONG_CALL_ u32
HAL_GPIO_GetIPPinName_8195a(
u32 chip_pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_PullCtrl_8195a(
u32 chip_pin,
u8 pull_type
);
_LONG_CALL_ u32
GPIO_GetChipPinName_8195a(
u32 port,
u32 pin
);
_LONG_CALL_ VOID
GPIO_PullCtrl_8195a(
u32 chip_pin,
u8 pull_type
);
_LONG_CALL_ VOID
GPIO_Int_SetType_8195a(
u8 pin_num,
u8 int_mode
);
_LONG_CALL_ HAL_Status HAL_GPIO_IntCtrl_8195aV02(HAL_GPIO_PIN *GPIO_Pin, u32 En);
_LONG_CALL_ u32 GPIO_Int_Clear_8195aV02(u32 irq_clr);
HAL_Status
HAL_GPIO_ClearISR_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
/********** HAL In-Line Functions **********/
/**
* @brief De-Initializes a GPIO Pin, reset it as default setting.
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval HAL_Status
*/
static __inline VOID
HAL_GPIO_DeInit(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_DeInit_8195a(GPIO_Pin);
}
/**
* @brief Reads the specified input port pin.
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval The input port pin current status(High or Low).
*/
static __inline s32
HAL_GPIO_ReadPin(
HAL_GPIO_PIN *GPIO_Pin
)
{
return (s32)HAL_GPIO_ReadPin_8195a(GPIO_Pin);
}
/**
* @brief Write the specified output port pin.
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @param Pin_State: The state going to be set to the assigned GPIO pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_WritePin(
HAL_GPIO_PIN *GPIO_Pin,
u32 Value
)
{
HAL_GPIO_WritePin_8195a(GPIO_Pin, (HAL_GPIO_PIN_STATE)Value);
}
/**
* @brief To register a user interrupt handler for a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @param IrqHandler: The IRQ handler to be assigned to the specified pin
*
* @param IrqData: The pointer will be pass the the IRQ handler
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UserRegIrq(
HAL_GPIO_PIN *GPIO_Pin,
VOID *IrqHandler,
VOID *IrqData
)
{
HAL_GPIO_UserRegIrq_8195a(GPIO_Pin, IrqHandler, IrqData);
}
/**
* @brief To un-register a user interrupt handler for a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UserUnRegIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_UserUnRegIrq_8195a(GPIO_Pin);
}
/**
* @brief Enable/Disable GPIO interrupt
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
*
* @param En: Enable (1) or Disable (0)
*
* @retval HAL_Status
*/
static __inline VOID
HAL_GPIO_IntCtrl(
HAL_GPIO_PIN *GPIO_Pin,
u32 En
)
{
HAL_GPIO_IntCtrl_8195a(GPIO_Pin, En);
}
/**
* @brief Mask the interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_MaskIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_MaskIrq_8195a(GPIO_Pin);
}
/**
* @brief UnMask the interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UnMaskIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_ClearISR_8195a(GPIO_Pin);
HAL_GPIO_UnMaskIrq_8195a(GPIO_Pin);
}
#endif // end of "#define _RTL8195A_GPIO_H_"

851
sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h Normal file
View file

@ -0,0 +1,851 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_I2C_H_
#define _RTL8195A_I2C_H_
#include "hal_api.h"
//================ Register Bit Field ==================
//2 REG_DW_I2C_IC_CON
#define BIT_IC_CON_IC_SLAVE_DISABLE BIT(6)
#define BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE 6
#define BIT_MASK_IC_CON_IC_SLAVE_DISABLE 0x1
#define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(x) (((x) & BIT_MASK_IC_CON_IC_SLAVE_DISABLE) << BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE)
#define BIT_IC_CON_IC_RESTART_EN BIT(5)
#define BIT_SHIFT_IC_CON_IC_RESTART_EN 5
#define BIT_MASK_IC_CON_IC_RESTART_EN 0x1
#define BIT_CTRL_IC_CON_IC_RESTART_EN(x) (((x) & BIT_MASK_IC_CON_IC_RESTART_EN) << BIT_SHIFT_IC_CON_IC_RESTART_EN)
#define BIT_IC_CON_IC_10BITADDR_MASTER BIT(4)
#define BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER 4
#define BIT_MASK_IC_CON_IC_10BITADDR_MASTER 0x1
#define BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER)
#define BIT_IC_CON_IC_10BITADDR_SLAVE BIT(3)
#define BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE 3
#define BIT_MASK_IC_CON_IC_10BITADDR_SLAVE 0x1
#define BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_SLAVE) << BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE)
#define BIT_SHIFT_IC_CON_SPEED 1
#define BIT_MASK_IC_CON_SPEED 0x3
#define BIT_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
#define BIT_CTRL_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
#define BIT_GET_IC_CON_SPEED(x) (((x) >> BIT_SHIFT_IC_CON_SPEED) & BIT_MASK_IC_CON_SPEED)
#define BIT_IC_CON_MASTER_MODE BIT(0)
#define BIT_SHIFT_IC_CON_MASTER_MODE 0
#define BIT_MASK_IC_CON_MASTER_MODE 0x1
#define BIT_CTRL_IC_CON_MASTER_MODE(x) (((x) & BIT_MASK_IC_CON_MASTER_MODE) << BIT_SHIFT_IC_CON_MASTER_MODE)
//2 REG_DW_I2C_IC_TAR
#define BIT_IC_TAR_IC_10BITADDR_MASTER BIT(12)
#define BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER 12
#define BIT_MASK_IC_TAR_IC_10BITADDR_MASTER 0x1
#define BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_TAR_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER)
#define BIT_IC_TAR_SPECIAL BIT(11)
#define BIT_SHIFT_IC_TAR_SPECIAL 11
#define BIT_MASK_IC_TAR_SPECIAL 0x1
#define BIT_CTRL_IC_TAR_SPECIAL(x) (((x) & BIT_MASK_IC_TAR_SPECIAL) << BIT_SHIFT_IC_TAR_SPECIAL)
#define BIT_IC_TAR_GC_OR_START BIT(10)
#define BIT_SHIFT_IC_TAR_GC_OR_START 10
#define BIT_MASK_IC_TAR_GC_OR_START 0x1
#define BIT_CTRL_IC_TAR_GC_OR_START(x) (((x) & BIT_MASK_IC_TAR_GC_OR_START) << BIT_SHIFT_IC_TAR_GC_OR_START)
#define BIT_SHIFT_IC_TAR 0
#define BIT_MASK_IC_TAR 0x3ff
#define BIT_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
#define BIT_CTRL_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
#define BIT_GET_IC_TAR(x) (((x) >> BIT_SHIFT_IC_TAR) & BIT_MASK_IC_TAR)
//2 REG_DW_I2C_IC_SAR
#define BIT_SHIFT_IC_SAR 0
#define BIT_MASK_IC_SAR 0x3ff
#define BIT_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
#define BIT_CTRL_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
#define BIT_GET_IC_SAR(x) (((x) >> BIT_SHIFT_IC_SAR) & BIT_MASK_IC_SAR)
//2 REG_DW_I2C_IC_HS_MADDR
#define BIT_SHIFT_IC_HS_MADDR 0
#define BIT_MASK_IC_HS_MADDR 0x7
#define BIT_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
#define BIT_CTRL_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
#define BIT_GET_IC_HS_MADDR(x) (((x) >> BIT_SHIFT_IC_HS_MADDR) & BIT_MASK_IC_HS_MADDR)
//2 REG_DW_I2C_IC_DATA_CMD
#define BIT_IC_DATA_CMD_RESTART BIT(10)
#define BIT_SHIFT_IC_DATA_CMD_RESTART 10
#define BIT_MASK_IC_DATA_CMD_RESTART 0x1
#define BIT_CTRL_IC_DATA_CMD_RESTART(x) (((x) & BIT_MASK_IC_DATA_CMD_RESTART) << BIT_SHIFT_IC_DATA_CMD_RESTART)
#define BIT_IC_DATA_CMD_STOP BIT(9)
#define BIT_SHIFT_IC_DATA_CMD_STOP 9
#define BIT_MASK_IC_DATA_CMD_STOP 0x1
#define BIT_CTRL_IC_DATA_CMD_STOP(x) (((x) & BIT_MASK_IC_DATA_CMD_STOP) << BIT_SHIFT_IC_DATA_CMD_STOP)
#define BIT_IC_DATA_CMD_CMD BIT(8)
#define BIT_SHIFT_IC_DATA_CMD_CMD 8
#define BIT_MASK_IC_DATA_CMD_CMD 0x1
#define BIT_CTRL_IC_DATA_CMD_CMD(x) (((x) & BIT_MASK_IC_DATA_CMD_CMD) << BIT_SHIFT_IC_DATA_CMD_CMD)
#define BIT_SHIFT_IC_DATA_CMD_DAT 0
#define BIT_MASK_IC_DATA_CMD_DAT 0xff
#define BIT_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
#define BIT_CTRL_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
#define BIT_GET_IC_DATA_CMD_DAT(x) (((x) >> BIT_SHIFT_IC_DATA_CMD_DAT) & BIT_MASK_IC_DATA_CMD_DAT)
//2 REG_DW_I2C_IC_SS_SCL_HCNT
#define BIT_SHIFT_IC_SS_SCL_HCNT 0
#define BIT_MASK_IC_SS_SCL_HCNT 0xffff
#define BIT_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
#define BIT_CTRL_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
#define BIT_GET_IC_SS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_HCNT) & BIT_MASK_IC_SS_SCL_HCNT)
//2 REG_DW_I2C_IC_SS_SCL_LCNT
#define BIT_SHIFT_IC_SS_SCL_LCNT 0
#define BIT_MASK_IC_SS_SCL_LCNT 0xffff
#define BIT_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
#define BIT_CTRL_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
#define BIT_GET_IC_SS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_LCNT) & BIT_MASK_IC_SS_SCL_LCNT)
//2 REG_DW_I2C_IC_FS_SCL_HCNT
#define BIT_SHIFT_IC_FS_SCL_HCNT 0
#define BIT_MASK_IC_FS_SCL_HCNT 0xffff
#define BIT_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
#define BIT_CTRL_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
#define BIT_GET_IC_FS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_HCNT) & BIT_MASK_IC_FS_SCL_HCNT)
//2 REG_DW_I2C_IC_FS_SCL_LCNT
#define BIT_SHIFT_IC_FS_SCL_LCNT 0
#define BIT_MASK_IC_FS_SCL_LCNT 0xffff
#define BIT_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
#define BIT_CTRL_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
#define BIT_GET_IC_FS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_LCNT) & BIT_MASK_IC_FS_SCL_LCNT)
//2 REG_DW_I2C_IC_HS_SCL_HCNT
#define BIT_SHIFT_IC_HS_SCL_HCNT 0
#define BIT_MASK_IC_HS_SCL_HCNT 0xffff
#define BIT_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
#define BIT_CTRL_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
#define BIT_GET_IC_HS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_HCNT) & BIT_MASK_IC_HS_SCL_HCNT)
//2 REG_DW_I2C_IC_HS_SCL_LCNT
#define BIT_SHIFT_IC_HS_SCL_LCNT 0
#define BIT_MASK_IC_HS_SCL_LCNT 0xffff
#define BIT_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
#define BIT_CTRL_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
#define BIT_GET_IC_HS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_LCNT) & BIT_MASK_IC_HS_SCL_LCNT)
//2 REG_DW_I2C_IC_INTR_STAT
#define BIT_IC_INTR_STAT_R_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL 11
#define BIT_MASK_IC_INTR_STAT_R_GEN_CALL 0x1
#define BIT_CTRL_IC_INTR_STAT_R_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_GEN_CALL) << BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL)
#define BIT_IC_INTR_STAT_R_START_DET BIT(10)
#define BIT_SHIFT_IC_INTR_STAT_R_START_DET 10
#define BIT_MASK_IC_INTR_STAT_R_START_DET 0x1
#define BIT_CTRL_IC_INTR_STAT_R_START_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_START_DET) << BIT_SHIFT_IC_INTR_STAT_R_START_DET)
#define BIT_IC_INTR_STAT_R_STOP_DET BIT(9)
#define BIT_SHIFT_IC_INTR_STAT_R_STOP_DET 9
#define BIT_MASK_IC_INTR_STAT_R_STOP_DET 0x1
#define BIT_CTRL_IC_INTR_STAT_R_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_STOP_DET) << BIT_SHIFT_IC_INTR_STAT_R_STOP_DET)
#define BIT_IC_INTR_STAT_R_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY 8
#define BIT_MASK_IC_INTR_STAT_R_ACTIVITY 0x1
#define BIT_CTRL_IC_INTR_STAT_R_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_ACTIVITY) << BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY)
#define BIT_IC_INTR_STAT_R_RX_DONE BIT(7)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_DONE 7
#define BIT_MASK_IC_INTR_STAT_R_RX_DONE 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_DONE) << BIT_SHIFT_IC_INTR_STAT_R_RX_DONE)
#define BIT_IC_INTR_STAT_R_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT 6
#define BIT_MASK_IC_INTR_STAT_R_TX_ABRT 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_ABRT) << BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT)
#define BIT_IC_INTR_STAT_R_RD_REQ BIT(5)
#define BIT_SHIFT_IC_INTR_STAT_R_RD_REQ 5
#define BIT_MASK_IC_INTR_STAT_R_RD_REQ 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RD_REQ) << BIT_SHIFT_IC_INTR_STAT_R_RD_REQ)
#define BIT_IC_INTR_STAT_R_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY 4
#define BIT_MASK_IC_INTR_STAT_R_TX_EMPTY 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_EMPTY) << BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY)
#define BIT_IC_INTR_STAT_R_TX_OVER BIT(3)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_OVER 3
#define BIT_MASK_IC_INTR_STAT_R_TX_OVER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_TX_OVER)
#define BIT_IC_INTR_STAT_R_RX_FULL BIT(2)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_FULL 2
#define BIT_MASK_IC_INTR_STAT_R_RX_FULL 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_FULL) << BIT_SHIFT_IC_INTR_STAT_R_RX_FULL)
#define BIT_IC_INTR_STAT_R_RX_OVER BIT(1)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_OVER 1
#define BIT_MASK_IC_INTR_STAT_R_RX_OVER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_RX_OVER)
#define BIT_IC_INTR_STAT_R_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER 0
#define BIT_MASK_IC_INTR_STAT_R_RX_UNDER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_UNDER) << BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER)
//2 REG_DW_I2C_IC_INTR_MASK
#define BIT_IC_INTR_MASK_M_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL 11
#define BIT_MASK_IC_INTR_MASK_M_GEN_CALL 0x1
#define BIT_CTRL_IC_INTR_MASK_M_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_GEN_CALL) << BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL)
#define BIT_IC_INTR_MASK_M_START_DET BIT(10)
#define BIT_SHIFT_IC_INTR_MASK_M_START_DET 10
#define BIT_MASK_IC_INTR_MASK_M_START_DET 0x1
#define BIT_CTRL_IC_INTR_MASK_M_START_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_START_DET) << BIT_SHIFT_IC_INTR_MASK_M_START_DET)
#define BIT_IC_INTR_MASK_M_STOP_DET BIT(9)
#define BIT_SHIFT_IC_INTR_MASK_M_STOP_DET 9
#define BIT_MASK_IC_INTR_MASK_M_STOP_DET 0x1
#define BIT_CTRL_IC_INTR_MASK_M_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_STOP_DET) << BIT_SHIFT_IC_INTR_MASK_M_STOP_DET)
#define BIT_IC_INTR_MASK_M_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY 8
#define BIT_MASK_IC_INTR_MASK_M_ACTIVITY 0x1
#define BIT_CTRL_IC_INTR_MASK_M_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_ACTIVITY) << BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY)
#define BIT_IC_INTR_MASK_M_RX_DONE BIT(7)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_DONE 7
#define BIT_MASK_IC_INTR_MASK_M_RX_DONE 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_DONE) << BIT_SHIFT_IC_INTR_MASK_M_RX_DONE)
#define BIT_IC_INTR_MASK_M_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT 6
#define BIT_MASK_IC_INTR_MASK_M_TX_ABRT 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_ABRT) << BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT)
#define BIT_IC_INTR_MASK_M_RD_REQ BIT(5)
#define BIT_SHIFT_IC_INTR_MASK_M_RD_REQ 5
#define BIT_MASK_IC_INTR_MASK_M_RD_REQ 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RD_REQ) << BIT_SHIFT_IC_INTR_MASK_M_RD_REQ)
#define BIT_IC_INTR_MASK_M_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY 4
#define BIT_MASK_IC_INTR_MASK_M_TX_EMPTY 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_EMPTY) << BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY)
#define BIT_IC_INTR_MASK_M_TX_OVER BIT(3)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_OVER 3
#define BIT_MASK_IC_INTR_MASK_M_TX_OVER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_TX_OVER)
#define BIT_IC_INTR_MASK_M_RX_FULL BIT(2)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_FULL 2
#define BIT_MASK_IC_INTR_MASK_M_RX_FULL 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_FULL) << BIT_SHIFT_IC_INTR_MASK_M_RX_FULL)
#define BIT_IC_INTR_MASK_M_RX_OVER BIT(1)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_OVER 1
#define BIT_MASK_IC_INTR_MASK_M_RX_OVER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_RX_OVER)
#define BIT_IC_INTR_MASK_M_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER 0
#define BIT_MASK_IC_INTR_MASK_M_RX_UNDER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_UNDER) << BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER)
//2 REG_DW_I2C_IC_RAW_INTR_STAT
#define BIT_IC_RAW_INTR_STAT_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL 11
#define BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_GEN_CALL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL) << BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL)
#define BIT_IC_RAW_INTR_STAT_START_DET BIT(10)
#define BIT_SHIFT_IC_RAW_INTR_STAT_START_DET 10
#define BIT_MASK_IC_RAW_INTR_STAT_START_DET 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_START_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_START_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_START_DET)
#define BIT_IC_RAW_INTR_STAT_STOP_DET BIT(9)
#define BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET 9
#define BIT_MASK_IC_RAW_INTR_STAT_STOP_DET 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_STOP_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_STOP_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET)
#define BIT_IC_RAW_INTR_STAT_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY 8
#define BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_ACTIVITY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY) << BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY)
#define BIT_IC_RAW_INTR_STAT_RX_DONE BIT(7)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE 7
#define BIT_MASK_IC_RAW_INTR_STAT_RX_DONE 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_DONE(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_DONE) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE)
#define BIT_IC_RAW_INTR_STAT_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT 6
#define BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_ABRT(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT)
#define BIT_IC_RAW_INTR_STAT_RD_REQ BIT(5)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ 5
#define BIT_MASK_IC_RAW_INTR_STAT_RD_REQ 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RD_REQ(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RD_REQ) << BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ)
#define BIT_IC_RAW_INTR_STAT_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY 4
#define BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_EMPTY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY)
#define BIT_IC_RAW_INTR_STAT_TX_OVER BIT(3)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER 3
#define BIT_MASK_IC_RAW_INTR_STAT_TX_OVER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER)
#define BIT_IC_RAW_INTR_STAT_RX_FULL BIT(2)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL 2
#define BIT_MASK_IC_RAW_INTR_STAT_RX_FULL 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_FULL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_FULL) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL)
#define BIT_IC_RAW_INTR_STAT_RX_OVER BIT(1)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER 1
#define BIT_MASK_IC_RAW_INTR_STAT_RX_OVER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER)
#define BIT_IC_RAW_INTR_STAT_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER 0
#define BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_UNDER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER)
//2 REG_DW_I2C_IC_RX_TL
#define BIT_SHIFT_IC_RX_TL 0
#define BIT_MASK_IC_RX_TL 0xff
#define BIT_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
#define BIT_CTRL_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
#define BIT_GET_IC_RX_TL(x) (((x) >> BIT_SHIFT_IC_RX_TL) & BIT_MASK_IC_RX_TL)
//2 REG_DW_I2C_IC_TX_TL
#define BIT_SHIFT_IC_TX_TL 0
#define BIT_MASK_IC_TX_TL 0xff
#define BIT_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
#define BIT_CTRL_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
#define BIT_GET_IC_TX_TL(x) (((x) >> BIT_SHIFT_IC_TX_TL) & BIT_MASK_IC_TX_TL)
//2 REG_DW_I2C_IC_CLR_INTR
#define BIT_IC_CLR_INTR BIT(0)
#define BIT_SHIFT_IC_CLR_INTR 0
#define BIT_MASK_IC_CLR_INTR 0x1
#define BIT_CTRL_IC_CLR_INTR(x) (((x) & BIT_MASK_IC_CLR_INTR) << BIT_SHIFT_IC_CLR_INTR)
//2 REG_DW_I2C_IC_CLR_RX_UNDER
#define BIT_IC_CLR_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_CLR_RX_UNDER 0
#define BIT_MASK_IC_CLR_RX_UNDER 0x1
#define BIT_CTRL_IC_CLR_RX_UNDER(x) (((x) & BIT_MASK_IC_CLR_RX_UNDER) << BIT_SHIFT_IC_CLR_RX_UNDER)
//2 REG_DW_I2C_IC_CLR_RX_OVER
#define BIT_IC_CLR_RX_OVER BIT(0)
#define BIT_SHIFT_IC_CLR_RX_OVER 0
#define BIT_MASK_IC_CLR_RX_OVER 0x1
#define BIT_CTRL_IC_CLR_RX_OVER(x) (((x) & BIT_MASK_IC_CLR_RX_OVER) << BIT_SHIFT_IC_CLR_RX_OVER)
//2 REG_DW_I2C_IC_CLR_TX_OVER
#define BIT_IC_CLR_TX_OVER BIT(0)
#define BIT_SHIFT_IC_CLR_TX_OVER 0
#define BIT_MASK_IC_CLR_TX_OVER 0x1
#define BIT_CTRL_IC_CLR_TX_OVER(x) (((x) & BIT_MASK_IC_CLR_TX_OVER) << BIT_SHIFT_IC_CLR_TX_OVER)
//2 REG_DW_I2C_IC_CLR_RD_REQ
#define BIT_IC_CLR_RD_REQ BIT(0)
#define BIT_SHIFT_IC_CLR_RD_REQ 0
#define BIT_MASK_IC_CLR_RD_REQ 0x1
#define BIT_CTRL_IC_CLR_RD_REQ(x) (((x) & BIT_MASK_IC_CLR_RD_REQ) << BIT_SHIFT_IC_CLR_RD_REQ)
//2 REG_DW_I2C_IC_CLR_TX_ABRT
#define BIT_CLR_RD_REQ BIT(0)
#define BIT_SHIFT_CLR_RD_REQ 0
#define BIT_MASK_CLR_RD_REQ 0x1
#define BIT_CTRL_CLR_RD_REQ(x) (((x) & BIT_MASK_CLR_RD_REQ) << BIT_SHIFT_CLR_RD_REQ)
//2 REG_DW_I2C_IC_CLR_RX_DONE
#define BIT_IC_CLR_RX_DONE BIT(0)
#define BIT_SHIFT_IC_CLR_RX_DONE 0
#define BIT_MASK_IC_CLR_RX_DONE 0x1
#define BIT_CTRL_IC_CLR_RX_DONE(x) (((x) & BIT_MASK_IC_CLR_RX_DONE) << BIT_SHIFT_IC_CLR_RX_DONE)
//2 REG_DW_I2C_IC_CLR_ACTIVITY
#define BIT_IC_CLR_ACTIVITY BIT(0)
#define BIT_SHIFT_IC_CLR_ACTIVITY 0
#define BIT_MASK_IC_CLR_ACTIVITY 0x1
#define BIT_CTRL_IC_CLR_ACTIVITY(x) (((x) & BIT_MASK_IC_CLR_ACTIVITY) << BIT_SHIFT_IC_CLR_ACTIVITY)
//2 REG_DW_I2C_IC_CLR_STOP_DET
#define BIT_IC_CLR_STOP_DET BIT(0)
#define BIT_SHIFT_IC_CLR_STOP_DET 0
#define BIT_MASK_IC_CLR_STOP_DET 0x1
#define BIT_CTRL_IC_CLR_STOP_DET(x) (((x) & BIT_MASK_IC_CLR_STOP_DET) << BIT_SHIFT_IC_CLR_STOP_DET)
//2 REG_DW_I2C_IC_CLR_START_DET
#define BIT_IC_CLR_START_DET BIT(0)
#define BIT_SHIFT_IC_CLR_START_DET 0
#define BIT_MASK_IC_CLR_START_DET 0x1
#define BIT_CTRL_IC_CLR_START_DET(x) (((x) & BIT_MASK_IC_CLR_START_DET) << BIT_SHIFT_IC_CLR_START_DET)
//2 REG_DW_I2C_IC_CLR_GEN_CALL
#define BIT_IC_CLR_GEN_CALL BIT(0)
#define BIT_SHIFT_IC_CLR_GEN_CALL 0
#define BIT_MASK_IC_CLR_GEN_CALL 0x1
#define BIT_CTRL_IC_CLR_GEN_CALL(x) (((x) & BIT_MASK_IC_CLR_GEN_CALL) << BIT_SHIFT_IC_CLR_GEN_CALL)
//2 REG_DW_I2C_IC_ENABLE
#define BIT_IC_ENABLE BIT(0)
#define BIT_SHIFT_IC_ENABLE 0
#define BIT_MASK_IC_ENABLE 0x1
#define BIT_CTRL_IC_ENABLE(x) (((x) & BIT_MASK_IC_ENABLE) << BIT_SHIFT_IC_ENABLE)
//2 REG_DW_I2C_IC_STATUS
#define BIT_IC_STATUS_SLV_ACTIVITY BIT(6)
#define BIT_SHIFT_IC_STATUS_SLV_ACTIVITY 6
#define BIT_MASK_IC_STATUS_SLV_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_SLV_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_SLV_ACTIVITY) << BIT_SHIFT_IC_STATUS_SLV_ACTIVITY)
#define BIT_IC_STATUS_MST_ACTIVITY BIT(5)
#define BIT_SHIFT_IC_STATUS_MST_ACTIVITY 5
#define BIT_MASK_IC_STATUS_MST_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_MST_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_MST_ACTIVITY) << BIT_SHIFT_IC_STATUS_MST_ACTIVITY)
#define BIT_IC_STATUS_RFF BIT(4)
#define BIT_SHIFT_IC_STATUS_RFF 4
#define BIT_MASK_IC_STATUS_RFF 0x1
#define BIT_CTRL_IC_STATUS_RFF(x) (((x) & BIT_MASK_IC_STATUS_RFF) << BIT_SHIFT_IC_STATUS_RFF)
#define BIT_IC_STATUS_RFNE BIT(3)
#define BIT_SHIFT_IC_STATUS_RFNE 3
#define BIT_MASK_IC_STATUS_RFNE 0x1
#define BIT_CTRL_IC_STATUS_RFNE(x) (((x) & BIT_MASK_IC_STATUS_RFNE) << BIT_SHIFT_IC_STATUS_RFNE)
#define BIT_IC_STATUS_TFE BIT(2)
#define BIT_SHIFT_IC_STATUS_TFE 2
#define BIT_MASK_IC_STATUS_TFE 0x1
#define BIT_CTRL_IC_STATUS_TFE(x) (((x) & BIT_MASK_IC_STATUS_TFE) << BIT_SHIFT_IC_STATUS_TFE)
#define BIT_IC_STATUS_TFNF BIT(1)
#define BIT_SHIFT_IC_STATUS_TFNF 1
#define BIT_MASK_IC_STATUS_TFNF 0x1
#define BIT_CTRL_IC_STATUS_TFNF(x) (((x) & BIT_MASK_IC_STATUS_TFNF) << BIT_SHIFT_IC_STATUS_TFNF)
#define BIT_IC_STATUS_ACTIVITY BIT(0)
#define BIT_SHIFT_IC_STATUS_ACTIVITY 0
#define BIT_MASK_IC_STATUS_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_ACTIVITY) << BIT_SHIFT_IC_STATUS_ACTIVITY)
//2 REG_DW_I2C_IC_TXFLR
#define BIT_SHIFT_IC_TXFLR 0
#define BIT_MASK_IC_TXFLR 0x3f
#define BIT_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
#define BIT_CTRL_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
#define BIT_GET_IC_TXFLR(x) (((x) >> BIT_SHIFT_IC_TXFLR) & BIT_MASK_IC_TXFLR)
//2 REG_DW_I2C_IC_RXFLR
#define BIT_SHIFT_IC_RXFLR 0
#define BIT_MASK_IC_RXFLR 0x1f
#define BIT_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
#define BIT_CTRL_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
#define BIT_GET_IC_RXFLR(x) (((x) >> BIT_SHIFT_IC_RXFLR) & BIT_MASK_IC_RXFLR)
//2 REG_DW_I2C_IC_SDA_HOLD
#define BIT_SHIFT_IC_SDA_HOLD 0
#define BIT_MASK_IC_SDA_HOLD 0xffff
#define BIT_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
#define BIT_CTRL_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
#define BIT_GET_IC_SDA_HOLD(x) (((x) >> BIT_SHIFT_IC_SDA_HOLD) & BIT_MASK_IC_SDA_HOLD)
//2 REG_DW_I2C_IC_TX_ABRT_SOURCE
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX BIT(15)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 15
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST BIT(14)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 14
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO BIT(13)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 13
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO)
#define BIT_IC_TX_ABRT_SOURCE_ARB_LOST BIT(12)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST 12
#define BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ARB_LOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS BIT(11)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 11
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT BIT(10)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 10
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT BIT(9)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 9
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT BIT(8)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 8
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET BIT(7)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 7
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET BIT(6)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 6
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ BIT(5)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 5
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK BIT(4)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 4
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK BIT(3)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 3
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK BIT(2)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 2
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK BIT(1)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 1
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK BIT(0)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK)
//2 REG_DW_I2C_IC_SLV_DATA_NACK_ONLY
#define BIT_IC_SLV_DATA_NACK_ONLY BIT(0)
#define BIT_SHIFT_IC_SLV_DATA_NACK_ONLY 0
#define BIT_MASK_IC_SLV_DATA_NACK_ONLY 0x1
#define BIT_CTRL_IC_SLV_DATA_NACK_ONLY(x) (((x) & BIT_MASK_IC_SLV_DATA_NACK_ONLY) << BIT_SHIFT_IC_SLV_DATA_NACK_ONLY)
//2 REG_DW_I2C_IC_DMA_CR
#define BIT_IC_DMA_CR_TDMAE BIT(1)
#define BIT_SHIFT_IC_DMA_CR_TDMAE 1
#define BIT_MASK_IC_DMA_CR_TDMAE 0x1
#define BIT_CTRL_IC_DMA_CR_TDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_TDMAE) << BIT_SHIFT_IC_DMA_CR_TDMAE)
#define BIT_IC_DMA_CR_RDMAE BIT(0)
#define BIT_SHIFT_IC_DMA_CR_RDMAE 0
#define BIT_MASK_IC_DMA_CR_RDMAE 0x1
#define BIT_CTRL_IC_DMA_CR_RDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_RDMAE) << BIT_SHIFT_IC_DMA_CR_RDMAE)
//2 REG_DW_I2C_IC_DMA_TDLR
#define BIT_SHIFT_IC_DMA_TDLR_DMATDL 0
#define BIT_MASK_IC_DMA_TDLR_DMATDL 0x1f
#define BIT_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
#define BIT_CTRL_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
#define BIT_GET_IC_DMA_TDLR_DMATDL(x) (((x) >> BIT_SHIFT_IC_DMA_TDLR_DMATDL) & BIT_MASK_IC_DMA_TDLR_DMATDL)
//2 REG_DW_I2C_IC_DMA_RDLR
#define BIT_SHIFT_IC_DMA_RDLR_DMARDL 0
#define BIT_MASK_IC_DMA_RDLR_DMARDL 0xf
#define BIT_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
#define BIT_CTRL_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
#define BIT_GET_IC_DMA_RDLR_DMARDL(x) (((x) >> BIT_SHIFT_IC_DMA_RDLR_DMARDL) & BIT_MASK_IC_DMA_RDLR_DMARDL)
//2 REG_DW_I2C_IC_SDA_SETUP
#define BIT_SHIFT_IC_SDA_SETUP 0
#define BIT_MASK_IC_SDA_SETUP 0xff
#define BIT_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
#define BIT_CTRL_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
#define BIT_GET_IC_SDA_SETUP(x) (((x) >> BIT_SHIFT_IC_SDA_SETUP) & BIT_MASK_IC_SDA_SETUP)
//2 REG_DW_I2C_IC_ACK_GENERAL_CALL
#define BIT_IC_ACK_GENERAL_CALL BIT(0)
#define BIT_SHIFT_IC_ACK_GENERAL_CALL 0
#define BIT_MASK_IC_ACK_GENERAL_CALL 0x1
#define BIT_CTRL_IC_ACK_GENERAL_CALL(x) (((x) & BIT_MASK_IC_ACK_GENERAL_CALL) << BIT_SHIFT_IC_ACK_GENERAL_CALL)
//2 REG_DW_I2C_IC_ENABLE_STATUS
#define BIT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST BIT(2)
#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 2
#define BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_SLV_RX_DATA_LOST(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST)
#define BIT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY BIT(1)
#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 1
#define BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY)
#define BIT_IC_ENABLE_STATUS_IC_EN BIT(0)
#define BIT_SHIFT_IC_ENABLE_STATUS_IC_EN 0
#define BIT_MASK_IC_ENABLE_STATUS_IC_EN 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_IC_EN(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_IC_EN) << BIT_SHIFT_IC_ENABLE_STATUS_IC_EN)
//2 REG_DW_I2C_IC_COMP_PARAM_1
#define BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 16
#define BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 0xff
#define BIT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_CTRL_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_GET_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 8
#define BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 0xff
#define BIT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_CTRL_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_GET_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS BIT(7)
#define BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 7
#define BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS) << BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS)
#define BIT_IC_COMP_PARAM_1_HAS_DMA BIT(6)
#define BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA 6
#define BIT_MASK_IC_COMP_PARAM_1_HAS_DMA 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_HAS_DMA(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HAS_DMA) << BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA)
#define BIT_IC_COMP_PARAM_1_INTR_IO BIT(5)
#define BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO 5
#define BIT_MASK_IC_COMP_PARAM_1_INTR_IO 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_INTR_IO(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_INTR_IO) << BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO)
#define BIT_IC_COMP_PARAM_1_HC_COUNT_VALUES BIT(4)
#define BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES 4
#define BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_HC_COUNT_VALUES(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES) << BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES)
#define BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE 2
#define BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE 0x3
#define BIT_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_CTRL_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_GET_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH 0
#define BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH 0x3
#define BIT_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
#define BIT_CTRL_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
#define BIT_GET_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH)
//2 REG_DW_I2C_IC_COMP_VERSION
#define BIT_SHIFT_IC_COMP_VERSION 0
#define BIT_MASK_IC_COMP_VERSION 0xffffffffL
#define BIT_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
#define BIT_CTRL_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
#define BIT_GET_IC_COMP_VERSION(x) (((x) >> BIT_SHIFT_IC_COMP_VERSION) & BIT_MASK_IC_COMP_VERSION)
//2 REG_DW_I2C_IC_COMP_TYPE
#define BIT_SHIFT_IC_COMP_TYPE 0
#define BIT_MASK_IC_COMP_TYPE 0xffffffffL
#define BIT_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
#define BIT_CTRL_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
#define BIT_GET_IC_COMP_TYPE(x) (((x) >> BIT_SHIFT_IC_COMP_TYPE) & BIT_MASK_IC_COMP_TYPE)
//======================== Register Address Definition ========================
#define REG_DW_I2C_IC_CON 0x0000
#define REG_DW_I2C_IC_TAR 0x0004
#define REG_DW_I2C_IC_SAR 0x0008
#define REG_DW_I2C_IC_HS_MADDR 0x000C
#define REG_DW_I2C_IC_DATA_CMD 0x0010
#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014
#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018
#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C
#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020
#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024
#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028
#define REG_DW_I2C_IC_INTR_STAT 0x002C
#define REG_DW_I2C_IC_INTR_MASK 0x0030
#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034
#define REG_DW_I2C_IC_RX_TL 0x0038
#define REG_DW_I2C_IC_TX_TL 0x003C
#define REG_DW_I2C_IC_CLR_INTR 0x0040
#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044
#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048
#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C
#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050
#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054
#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058
#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C
#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060
#define REG_DW_I2C_IC_CLR_START_DET 0x0064
#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068
#define REG_DW_I2C_IC_ENABLE 0x006C
#define REG_DW_I2C_IC_STATUS 0x0070
#define REG_DW_I2C_IC_TXFLR 0x0074
#define REG_DW_I2C_IC_RXFLR 0x0078
#define REG_DW_I2C_IC_SDA_HOLD 0x007C
#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080
#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084
#define REG_DW_I2C_IC_DMA_CR 0x0088
#define REG_DW_I2C_IC_DMA_TDLR 0x008C
#define REG_DW_I2C_IC_DMA_RDLR 0x0090
#define REG_DW_I2C_IC_SDA_SETUP 0x0094
#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098
#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C
#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4
#define REG_DW_I2C_IC_COMP_VERSION 0x00F8
#define REG_DW_I2C_IC_COMP_TYPE 0x00FC
//======================================================
// I2C related enumeration
// I2C Address Mode
typedef enum _I2C_ADDR_MODE_ {
I2C_ADDR_7BIT = 0,
I2C_ADDR_10BIT = 1,
}I2C_ADDR_MODE,*PI2C_ADDR_MODE;
// I2C Speed Mode
typedef enum _I2C_SPD_MODE_ {
I2C_SS_MODE = 1,
I2C_FS_MODE = 2,
I2C_HS_MODE = 3,
}I2C_SPD_MODE,*PI2C_SPD_MODE;
//I2C Timing Parameters
#define I2C_SS_MIN_SCL_HTIME 4000 //the unit is ns.
#define I2C_SS_MIN_SCL_LTIME 4700 //the unit is ns.
#define I2C_FS_MIN_SCL_HTIME 600 //the unit is ns.
#define I2C_FS_MIN_SCL_LTIME 1300 //the unit is ns.
#define I2C_HS_MIN_SCL_HTIME_100 60 //the unit is ns, with bus loading = 100pf
#define I2C_HS_MIN_SCL_LTIME_100 120 //the unit is ns., with bus loading = 100pf
#define I2C_HS_MIN_SCL_HTIME_400 160 //the unit is ns, with bus loading = 400pf
#define I2C_HS_MIN_SCL_LTIME_400 320 //the unit is ns., with bus loading = 400pf
//======================================================
//I2C Essential functions and macros
_LONG_CALL_ROM_ VOID HalI2CWrite32(IN u8 I2CIdx, IN u8 I2CReg, IN u32 I2CVal);
_LONG_CALL_ROM_ u32 HalI2CRead32(IN u8 I2CIdx, IN u8 I2CReg);
#define HAL_I2C_WRITE32(I2CIdx, addr, value) HalI2CWrite32(I2CIdx,addr,value)
#define HAL_I2C_READ32(I2CIdx, addr) HalI2CRead32(I2CIdx,addr)
// Rtl8195a I2C function prototypes
_LONG_CALL_ HAL_Status HalI2CEnableRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CInit8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CDeInit8195a(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CSendRtl8195a(IN VOID *Data);
_LONG_CALL_ u8 HalI2CReceiveRtl8195a(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status HalI2CIntrCtrl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CClrIntrRtl8195a(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status HalI2CClrAllIntrRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CDMACtrl8195a(IN VOID *Data);
_LONG_CALL_ u32 HalI2CReadRegRtl8195a(IN VOID *Data, IN u8 I2CReg);
_LONG_CALL_ HAL_Status HalI2CWriteRegRtl8195a(IN VOID *Data, IN u8 I2CReg, IN u32 RegVal);
//Rtl8195a I2C V02 function prototype
_LONG_CALL_ HAL_Status HalI2CSendRtl8195aV02(IN VOID *Data);
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data);
#elif defined(CONFIG_CHIP_E_CUT)
_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data);
#endif
//Rtl8195a I2C V02 function prototype END
HAL_Status HalI2CInit8195a_Patch(IN VOID *Data);
HAL_Status HalI2CSendRtl8195a_Patch(IN VOID *Data);
HAL_Status HalI2CSetCLKRtl8195a_Patch(IN VOID *Data);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_I2S_H_
#define _RTL8195A_I2S_H_
//=============== Register Bit Field Definition ====================
// REG_I2S_CONTROL
#define BIT_CTLX_I2S_EN BIT(0)
#define BIT_SHIFT_CTLX_I2S_EN 0
#define BIT_MASK_CTLX_I2S_EN 0x1
#define BIT_CTRL_CTLX_I2S_EN(x) (((x) & BIT_MASK_CTLX_I2S_EN) << BIT_SHIFT_CTLX_I2S_EN)
#define BIT_SHIFT_CTLX_I2S_TRX_ACT 1
#define BIT_MASK_CTLX_I2S_TRX_ACT 0x3
#define BIT_CTRL_CTLX_I2S_TRX_ACT(x) (((x) & BIT_MASK_CTLX_I2S_TRX_ACT) << BIT_SHIFT_CTLX_I2S_TRX_ACT)
#define BIT_GET_CTLX_I2S_TRX_ACT(x) (((x) >> BIT_SHIFT_CTLX_I2S_TRX_ACT) & BIT_MASK_CTLX_I2S_TRX_ACT)
#define BIT_SHIFT_CTLX_I2S_CH_NUM 3
#define BIT_MASK_CTLX_I2S_CH_NUM 0x3
#define BIT_CTRL_CTLX_I2S_CH_NUM(x) (((x) & BIT_MASK_CTLX_I2S_CH_NUM) << BIT_SHIFT_CTLX_I2S_CH_NUM)
#define BIT_GET_CTLX_I2S_CH_NUM(x) (((x) >> BIT_SHIFT_CTLX_I2S_CH_NUM) & BIT_MASK_CTLX_I2S_CH_NUM)
#define BIT_CTLX_I2S_WL BIT(6)
#define BIT_SHIFT_CTLX_I2S_WL 6
#define BIT_MASK_CTLX_I2S_WL 0x1
#define BIT_CTRL_CTLX_I2S_WL(x) (((x) & BIT_MASK_CTLX_I2S_WL) << BIT_SHIFT_CTLX_I2S_WL)
#define BIT_CTLX_I2S_LRSWAP BIT(10)
#define BIT_SHIFT_CTLX_I2S_LRSWAP 10
#define BIT_MASK_CTLX_I2S_LRSWAP 0x1
#define BIT_CTRL_CTLX_I2S_LRSWAP(x) (((x) & BIT_MASK_CTLX_I2S_LRSWAP) << BIT_SHIFT_CTLX_I2S_LRSWAP)
#define BIT_CTLX_I2S_SCK_INV BIT(11)
#define BIT_SHIFT_CTLX_I2S_SCK_INV 11
#define BIT_MASK_CTLX_I2S_SCK_INV 0x1
#define BIT_CTRL_CTLX_I2S_SCK_INV(x) (((x) & BIT_MASK_CTLX_I2S_SCK_INV) << BIT_SHIFT_CTLX_I2S_SCK_INV)
#define BIT_CTLX_I2S_ENDIAN_SWAP BIT(12)
#define BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP 12
#define BIT_MASK_CTLX_I2S_ENDIAN_SWAP 0x1
#define BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_I2S_ENDIAN_SWAP) << BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP)
#define BIT_CTLX_I2S_SLAVE_MODE BIT(29)
#define BIT_SHIFT_CTLX_I2S_SLAVE_MODE 29
#define BIT_MASK_CTLX_I2S_SLAVE_MODE 0x1
#define BIT_CTRL_CTLX_I2S_SLAVE_MODE(x) (((x) & BIT_MASK_CTLX_I2S_SLAVE_MODE) << BIT_SHIFT_CTLX_I2S_SLAVE_MODE)
#define BIT_CTLX_I2S_CLK_SRC BIT(30)
#define BIT_SHIFT_CTLX_I2S_CLK_SRC 30
#define BIT_MASK_CTLX_I2S_CLK_SRC 0x1
#define BIT_CTRL_CTLX_I2S_CLK_SRC(x) (((x) & BIT_MASK_CTLX_I2S_CLK_SRC) << BIT_SHIFT_CTLX_I2S_CLK_SRC)
#define BIT_CTLX_I2S_SW_RSTN BIT(31)
#define BIT_SHIFT_CTLX_I2S_SW_RSTN 31
#define BIT_MASK_CTLX_I2S_SW_RSTN 0x1
#define BIT_CTRL_CTLX_I2S_SW_RSTN(x) (((x) & BIT_MASK_CTLX_I2S_SW_RSTN) << BIT_SHIFT_CTLX_I2S_SW_RSTN)
// REG_I2S_SETTING
#define BIT_SHIFT_SETTING_I2S_PAGE_SZ 0
#define BIT_MASK_SETTING_I2S_PAGE_SZ 0xFFF
#define BIT_CTRL_SETTING_I2S_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_SZ) << BIT_SHIFT_SETTING_I2S_PAGE_SZ)
#define BIT_GET_SETTING_I2S_PAGE_SZ(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_SZ) & BIT_MASK_SETTING_I2S_PAGE_SZ)
#define BIT_SHIFT_SETTING_I2S_PAGE_NUM 12
#define BIT_MASK_SETTING_I2S_PAGE_NUM 0x3
#define BIT_CTRL_SETTING_I2S_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_NUM) << BIT_SHIFT_SETTING_I2S_PAGE_NUM)
#define BIT_GET_SETTING_I2S_PAGE_NUM(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_NUM) & BIT_MASK_SETTING_I2S_PAGE_NUM)
#define BIT_SHIFT_SETTING_I2S_SAMPLE_RATE 14
#define BIT_MASK_SETTING_I2S_SAMPLE_RATE 0x7
#define BIT_CTRL_SETTING_I2S_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_I2S_SAMPLE_RATE) << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE)
#define BIT_GET_SETTING_I2S_SAMPLE_RATE(x) (((x) >> BIT_SHIFT_SETTING_I2S_SAMPLE_RATE) & BIT_MASK_SETTING_I2S_SAMPLE_RATE)
// i2s trx page own bit
#define BIT_PAGE_I2S_OWN_BIT BIT(31)
#define BIT_SHIFT_PAGE_I2S_OWN_BIT 31
#define BIT_MASK_PAGE_I2S_OWN_BIT 0x1
#define BIT_CTRL_PAGE_I2S_OWN_BIT(x) (((x) & BIT_MASK_PAGE_I2S_OWN_BIT) << BIT_SHIFT_PAGE_I2S_OWN_BIT)
//=============== Register Address Definition ====================
#define REG_I2S_PAGE_OWN_OFF 0x004
#define REG_I2S_CTL 0x000
#define REG_I2S_TX_PAGE_PTR 0x004
#define REG_I2S_RX_PAGE_PTR 0x008
#define REG_I2S_SETTING 0x00C
#define REG_I2S_TX_MASK_INT 0x010
#define REG_I2S_TX_STATUS_INT 0x014
#define REG_I2S_RX_MASK_INT 0x018
#define REG_I2S_RX_STATUS_INT 0x01c
#define REG_I2S_TX_PAGE0_OWN 0x020
#define REG_I2S_TX_PAGE1_OWN 0x024
#define REG_I2S_TX_PAGE2_OWN 0x028
#define REG_I2S_TX_PAGE3_OWN 0x02C
#define REG_I2S_RX_PAGE0_OWN 0x030
#define REG_I2S_RX_PAGE1_OWN 0x034
#define REG_I2S_RX_PAGE2_OWN 0x038
#define REG_I2S_RX_PAGE3_OWN 0x03C
/*I2S Essential Functions and Macros*/
VOID
HalI2SWrite32(
IN u8 I2SIdx,
IN u8 I2SReg,
IN u32 I2SVal
);
u32
HalI2SRead32(
IN u8 I2SIdx,
IN u8 I2SReg
);
/*
#define HAL_I2SX_READ32(I2sIndex, addr) \
HAL_READ32(I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF), addr)
#define HAL_I2SX_WRITE32(I2sIndex, addr, value) \
HAL_WRITE32((I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF)), addr, value)
*/
#define HAL_I2S_WRITE32(I2SIdx, addr, value) HalI2SWrite32(I2SIdx,addr,value)
#define HAL_I2S_READ32(I2SIdx, addr) HalI2SRead32(I2SIdx,addr)
/* I2S debug output*/
#define I2S_PREFIX "RTL8195A[i2s]: "
#define I2S_PREFIX_LVL " [i2s_DBG]: "
typedef enum _I2S_DBG_LVL_ {
HAL_I2S_LVL = 0x01,
SAL_I2S_LVL = 0x02,
VERI_I2S_LVL = 0x03,
}I2S_DBG_LVL,*PI2S_DBG_LVL;
#ifdef CONFIG_DEBUG_LOG
#ifdef CONFIG_DEBUG_LOG_I2S_HAL
#define DBG_8195A_I2S(...) do{ \
_DbgDump("\r"I2S_PREFIX __VA_ARGS__);\
}while(0)
#define I2SDBGLVL 0xFF
#define DBG_8195A_I2S_LVL(LVL,...) do{\
if (LVL&I2SDBGLVL){\
_DbgDump("\r"I2S_PREFIX_LVL __VA_ARGS__);\
}\
}while(0)
#else
#define DBG_I2S_LOG_PERD 100
#define DBG_8195A_I2S(...)
#define DBG_8195A_I2S_LVL(...)
#endif
#else
#define DBG_I2S_LOG_PERD 100
#define DBG_8195A_I2S(...)
#define DBG_8195A_I2S_LVL(...)
#endif
/*
#define REG_I2S_PAGE_OWN_OFF 0x004
#define REG_I2S_CTL 0x000
#define REG_I2S_TX_PAGE_PTR 0x004
#define REG_I2S_RX_PAGE_PTR 0x008
#define REG_I2S_SETTING 0x00C
#define REG_I2S_TX_MASK_INT 0x010
#define REG_I2S_TX_STATUS_INT 0x014
#define REG_I2S_RX_MASK_INT 0x018
#define REG_I2S_RX_STATUS_INT 0x01c
#define REG_I2S_TX_PAGE0_OWN 0x020
#define REG_I2S_TX_PAGE1_OWN 0x024
#define REG_I2S_TX_PAGE2_OWN 0x028
#define REG_I2S_TX_PAGE3_OWN 0x02C
#define REG_I2S_RX_PAGE0_OWN 0x030
#define REG_I2S_RX_PAGE1_OWN 0x034
#define REG_I2S_RX_PAGE2_OWN 0x038
#define REG_I2S_RX_PAGE3_OWN 0x03C
*/
/* template
#define BIT_SHIFT_CTLX_ 7
#define BIT_MASK_CTLX_ 0x1
#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_)
#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_))
*//*
#define BIT_SHIFT_CTLX_IIS_EN 0
#define BIT_MASK_CTLX_IIS_EN 0x1
#define BIT_CTLX_IIS_EN(x) (((x) & BIT_MASK_CTLX_IIS_EN) << BIT_SHIFT_CTLX_IIS_EN)
#define BIT_INV_CTLX_IIS_EN (~(BIT_MASK_CTLX_IIS_EN << BIT_SHIFT_CTLX_IIS_EN))
#define BIT_SHIFT_CTLX_TRX 1
#define BIT_MASK_CTLX_TRX 0x3
#define BIT_CTLX_TRX(x) (((x) & BIT_MASK_CTLX_TRX) << BIT_SHIFT_CTLX_TRX)
#define BIT_INV_CTLX_TRX (~(BIT_MASK_CTLX_TRX << BIT_SHIFT_CTLX_TRX))
#define BIT_SHIFT_CTLX_CH_NUM 3
#define BIT_MASK_CTLX_CH_NUM 0x3
#define BIT_CTLX_CH_NUM(x) (((x) & BIT_MASK_CTLX_CH_NUM) << BIT_SHIFT_CTLX_CH_NUM)
#define BIT_INV_CTLX_CH_NUM (~(BIT_MASK_CTLX_CH_NUM << BIT_SHIFT_CTLX_CH_NUM))
#define BIT_SHIFT_CTLX_EDGE_SW 5
#define BIT_MASK_CTLX_EDGE_SW 0x1
#define BIT_CTLX_EDGE_SW(x) (((x) & BIT_MASK_CTLX_EDGE_SW) << BIT_SHIFT_CTLX_EDGE_SW)
#define BIT_INV_CTLX_EDGE_SW (~(BIT_MASK_CTLX_EDGE_SW << BIT_SHIFT_CTLX_EDGE_SW))
#define BIT_SHIFT_CTLX_WL 6
#define BIT_MASK_CTLX_WL 0x1
#define BIT_CTLX_WL(x) (((x) & BIT_MASK_CTLX_WL) << BIT_SHIFT_CTLX_WL)
#define BIT_INV_CTLX_WL (~(BIT_MASK_CTLX_WL << BIT_SHIFT_CTLX_WL))
#define BIT_SHIFT_CTLX_LOOP_BACK 7
#define BIT_MASK_CTLX_LOOP_BACK 0x1
#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK)
#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK))
#define BIT_SHIFT_CTLX_FORMAT 8
#define BIT_MASK_CTLX_FORMAT 0x3
#define BIT_CTLX_FORMAT(x) (((x) & BIT_MASK_CTLX_FORMAT) << BIT_SHIFT_CTLX_FORMAT)
#define BIT_INV_CTLX_FORMAT (~(BIT_MASK_CTLX_FORMAT << BIT_SHIFT_CTLX_FORMAT))
#define BIT_SHIFT_CTLX_LRSWAP 10
#define BIT_MASK_CTLX_LRSWAP 0x1
#define BIT_CTLX_LRSWAP(x) (((x) & BIT_MASK_CTLX_LRSWAP) << BIT_SHIFT_CTLX_LRSWAP)
#define BIT_INV_CTLX_LRSWAP (~(BIT_MASK_CTLX_LRSWAP << BIT_SHIFT_CTLX_LRSWAP))
#define BIT_SHIFT_CTLX_SCK_INV 11
#define BIT_MASK_CTLX_SCK_INV 0x1
#define BIT_CTLX_SCK_INV(x) (((x) & BIT_MASK_CTLX_SCK_INV) << BIT_SHIFT_CTLX_SCK_INV)
#define BIT_INV_CTLX_SCK_INV (~(BIT_MASK_CTLX_SCK_INV << BIT_SHIFT_CTLX_SCK_INV))
#define BIT_SHIFT_CTLX_ENDIAN_SWAP 12
#define BIT_MASK_CTLX_ENDIAN_SWAP 0x1
#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP)
#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP))
#define BIT_SHIFT_CTLX_DEBUG_SWITCH 15
#define BIT_MASK_CTLX_DEBUG_SWITCH 0x3
#define BIT_CTLX_DEBUG_SWITCH(x) (((x) & BIT_MASK_CTLX_DEBUG_SWITCH) << BIT_SHIFT_CTLX_DEBUG_SWITCH)
#define BIT_INV_CTLX_DEBUG_SWITCH (~(BIT_MASK_CTLX_DEBUG_SWITCH << BIT_SHIFT_CTLX_DEBUG_SWITCH))
#define BIT_SHIFT_CTLX_SLAVE_SEL 29
#define BIT_MASK_CTLX_SLAVE_SEL 0x1
#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL)
#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL))
#define BIT_SHIFT_CTLX_CLK_SRC 30
#define BIT_MASK_CTLX_CLK_SRC 0x1
#define BIT_CTLX_CLK_SRC(x) (((x) & BIT_MASK_CTLX_CLK_SRC) << BIT_SHIFT_CTLX_CLK_SRC)
#define BIT_INV_CTLX_CLK_SRC (~(BIT_MASK_CTLX_CLK_SRC << BIT_SHIFT_CTLX_CLK_SRC))
#define BIT_SHIFT_CTLX_SW_RSTN 31
#define BIT_MASK_CTLX_SW_RSTN 0x1
#define BIT_CTLX_SW_RSTN(x) (((x) & BIT_MASK_CTLX_SW_RSTN) << BIT_SHIFT_CTLX_SW_RSTN)
#define BIT_INV_CTLX_SW_RSTN (~(BIT_MASK_CTLX_SW_RSTN << BIT_SHIFT_CTLX_SW_RSTN))
#define BIT_SHIFT_SETTING_PAGE_SZ 0
#define BIT_MASK_SETTING_PAGE_SZ 0xFFF
#define BIT_SETTING_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_PAGE_SZ) << BIT_SHIFT_SETTING_PAGE_SZ)
#define BIT_INV_SETTING_PAGE_SZ (~(BIT_MASK_SETTING_PAGE_SZ << BIT_SHIFT_SETTING_PAGE_SZ))
#define BIT_SHIFT_SETTING_PAGE_NUM 12
#define BIT_MASK_SETTING_PAGE_NUM 0x3
#define BIT_SETTING_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_PAGE_NUM) << BIT_SHIFT_SETTING_PAGE_NUM)
#define BIT_INV_SETTING_PAGE_NUM (~(BIT_MASK_SETTING_PAGE_NUM << BIT_SHIFT_SETTING_PAGE_NUM))
#define BIT_SHIFT_SETTING_SAMPLE_RATE 14
#define BIT_MASK_SETTING_SAMPLE_RATE 0x7
#define BIT_SETTING_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_SAMPLE_RATE) << BIT_SHIFT_SETTING_SAMPLE_RATE)
#define BIT_INV_SETTING_SAMPLE_RATE (~(BIT_MASK_SETTING_SAMPLE_RATE << BIT_SHIFT_SETTING_SAMPLE_RATE))
*/
typedef enum _I2S_CTL_FORMAT {
FormatI2s = 0x00,
FormatLeftJustified = 0x01,
FormatRightJustified = 0x02
}I2S_CTL_FORMAT, *PI2S_CTL_FORMAT;
typedef enum _I2S_CTL_CHNUM {
ChannelStereo = 0x00,
Channel5p1 = 0x01,
ChannelMono = 0x02
}I2S_CTL_CHNUM, *PI2S_CTL_CHNUM;
typedef enum _I2S_CTL_TRX_ACT {
RxOnly = 0x00,
TxOnly = 0x01,
TXRX = 0x02
}I2S_CTL_TRX_ACT, *PI2S_CTL_TRX_ACT;
/*
typedef struct _I2S_CTL_REG_ {
I2S_CTL_FORMAT Format;
I2S_CTL_CHNUM ChNum;
I2S_CTL_TRX_ACT TrxAct;
u32 I2s_En :1; // Bit 0
u32 Rsvd1to4 :4; // Bit 1-4 is TrxAct, ChNum
u32 EdgeSw :1; // Bit 5 Edge switch
u32 WordLength :1; // Bit 6
u32 LoopBack :1; // Bit 7
u32 Rsvd8to9 :2; // Bit 8-9 is Format
u32 DacLrSwap :1; // Bit 10
u32 SckInv :1; // Bit 11
u32 EndianSwap :1; // Bit 12
u32 Rsvd13to14 :2; // Bit 11-14
u32 DebugSwitch :2; // Bit 15-16
u32 Rsvd17to28 :12; // Bit 17-28
u32 SlaveMode :1; // Bit 29
u32 SR44p1KHz :1; // Bit 30
u32 SwRstn :1; // Bit 31
} I2S_CTL_REG, *PI2S_CTL_REG;
*/
typedef enum _I2S_SETTING_PAGE_NUM {
I2s1Page = 0x00,
I2s2Page = 0x01,
I2s3Page = 0x02,
I2s4Page = 0x03
}I2S_SETTING_PAGE_NUM, *PI2S_SETTING_PAGE_NUM;
//sampling rate
typedef enum _I2S_SETTING_SR {
I2sSR8K = 0x00,
I2sSR16K = 0x01,
I2sSR24K = 0x02,
I2sSR32K = 0x03,
I2sSR48K = 0x05,
I2sSR44p1K = 0x15,
I2sSR96K = 0x06,
I2sSR88p2K = 0x16
}I2S_SETTING_SR, *PI2S_SETTING_SR;
/*
typedef struct _I2S_SETTING_REG_ {
I2S_SETTING_PAGE_NUM PageNum;
I2S_SETTING_SR SampleRate;
u32 PageSize:12; // Bit 0-11
}I2S_SETTING_REG, *PI2S_SETTING_REG;
typedef enum _I2S_TX_ISR {
I2sTxP0OK = 0x01,
I2sTxP1OK = 0x02,
I2sTxP2OK = 0x04,
I2sTxP3OK = 0x08,
I2sTxPageUn = 0x10,
I2sTxFifoEmpty = 0x20
}I2S_TX_ISR, *PI2S_TX_ISR;
typedef enum _I2S_RX_ISR {
I2sRxP0OK = 0x01,
I2sRxP1OK = 0x02,
I2sRxP2OK = 0x04,
I2sRxP3OK = 0x08,
I2sRxPageUn = 0x10,
I2sRxFifoFull = 0x20
}I2S_RX_ISR, *PI2S_RX_ISR;
*/
/* Hal I2S function prototype*/
RTK_STATUS
HalI2SInitRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SInitRtl8195a_Patch(
IN VOID *Data
);
RTK_STATUS
HalI2SDeInitRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2STxRtl8195a(
IN VOID *Data,
IN u8 *pBuff
);
RTK_STATUS
HalI2SRxRtl8195a(
IN VOID *Data,
OUT u8 *pBuff
);
RTK_STATUS
HalI2SEnableRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SIntrCtrlRtl8195a(
IN VOID *Data
);
u32
HalI2SReadRegRtl8195a(
IN VOID *Data,
IN u8 I2SReg
);
RTK_STATUS
HalI2SSetRateRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetWordLenRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetChNumRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetPageNumRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetPageSizeRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetDirectionRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetDMABufRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SClrIntrRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SClrAllIntrRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SDMACtrlRtl8195a(
IN VOID *Data
);
u8
HalI2SGetTxPageRtl8195a(
IN VOID *Data
);
u8
HalI2SGetRxPageRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SPageSendRtl8195a(
IN VOID *Data,
IN u8 PageIdx
);
#if 0
RTK_STATUS
HalI2SPageRecvRtl8195a(
IN VOID *Data,
IN u8 PageIdx
);
#else
RTK_STATUS
HalI2SPageRecvRtl8195a(
IN VOID *Data
);
#endif
RTK_STATUS
HalI2SClearAllOwnBitRtl8195a(
IN VOID *Data
);
// HAL functions Wrapper
static __inline VOID
HalI2SSetRate(
IN VOID *Data
)
{
HalI2SSetRateRtl8195a(Data);
}
static __inline VOID
HalI2SSetWordLen(
IN VOID *Data
)
{
HalI2SSetWordLenRtl8195a(Data);
}
static __inline VOID
HalI2SSetChNum(
IN VOID *Data
)
{
HalI2SSetChNumRtl8195a(Data);
}
static __inline VOID
HalI2SSetPageNum(
IN VOID *Data
)
{
HalI2SSetPageNumRtl8195a(Data);
}
static __inline VOID
HalI2SSetPageSize(
IN VOID *Data
)
{
HalI2SSetPageSizeRtl8195a(Data);
}
static __inline VOID
HalI2SSetDirection(
IN VOID *Data
)
{
HalI2SSetDirectionRtl8195a(Data);
}
static __inline VOID
HalI2SSetDMABuf(
IN VOID *Data
)
{
HalI2SSetDMABufRtl8195a(Data);
}
static __inline u8
HalI2SGetTxPage(
IN VOID *Data
)
{
return HalI2SGetTxPageRtl8195a(Data);
}
static __inline u8
HalI2SGetRxPage(
IN VOID *Data
)
{
return HalI2SGetRxPageRtl8195a(Data);
}
static __inline VOID
HalI2SPageSend(
IN VOID *Data,
IN u8 PageIdx
)
{
HalI2SPageSendRtl8195a(Data, PageIdx);
}
#if 0
static __inline VOID
HalI2SPageRecv(
IN VOID *Data,
IN u8 PageIdx
)
{
HalI2SPageRecvRtl8195a(Data, PageIdx);
}
#else
static __inline VOID
HalI2SPageRecv(
IN VOID *Data
)
{
HalI2SPageRecvRtl8195a(Data);
}
#endif
static __inline VOID
HalI2SClearAllOwnBit(
IN VOID *Data
)
{
HalI2SClearAllOwnBitRtl8195a(Data);
}
#endif /* _RTL8195A_I2S_H_ */

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sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_nfc.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_NFC_H_
#define _RTL8195A_NFC_H_
#include "hal_api.h"
//#include "osdep_api.h"
#ifdef CONFIG_NFC_VERIFY
#include "../test/nfc/rtl8195a_nfc_test.h"
#endif
#if CONFIG_NFC_NORMAL
//===================== Register Bit Field Definition =====================
// TODO:
//===================== Register Address Definition =====================
//TODO:
//#include "osdep_api.h"
#define N2A_Q_LENGTH 10
#define N2ARLENGTH 4
//#define NFCTAGLENGTH 36 // maximum 36*4=144 bytes
#define NFCTAG_BASE 0x7F000
#define NFCTAG_PAGESIZE 256
#define NFCTAG_MAXPAGEIDX 16//(4*(1024/NFCTAG_PAGESIZE))
#define A2NWCLENGTH 4
#define FLASHAPPLENGTH 31
#define FLASHAPP_BASE 0x7E000
#define FLASH_PAGESIZE 128
#define FLASH_MAXPAGEIDX 32//(4*(1024/FLASH_PAGESIZE))
typedef struct _A2N_CATCH_W_ {
//u8 Vaild;
u8 A2NCatchRPage;
u32 A2NCatchWData[A2NWCLENGTH];
}A2N_CATCH_W_QUEUE, *PA2N_CATCH_W_QUEUE;
typedef struct _A2N_MAILBOX_Q_ {
u8 Length;
u8 Response;
u32 Content[A2NWCLENGTH+1];
}A2N_MAILBOX_Q,*PA2N_MAILBOX_Q;
typedef struct _N2A_CATCH_R_ {
u8 Vaild;
u8 N2ACatchRPage;
u32 N2ACatchRData[N2ARLENGTH];
}N2A_CATCH_R_QUEUE, *PN2A_CATCH_R_QUEUE;
typedef struct _N2A_R_ {
u8 Vaild;
u8 N2ARPage;
}N2A_R_QUEUE, *PN2A_R_QUEUE;
typedef struct _N2A_W_ {
u8 Vaild;
u8 N2AWPage;
u32 N2AWData;
}N2A_W_QUEUE, *PN2A_W_QUEUE;
typedef struct _NFC_ADAPTER_ {
u8 Function;
u32 NFCIsr;
u8 N2ABoxOpen;
u8 A2NSeq;
//u8 NFCTagFlashWIdx;
//u8 NFCTagFlashRIdx;
// u32 NFCTag[NFCTAGLENGTH];
#if !TASK_SCHEDULER_DISABLED
void * VeriSema;
#else
u32 VeriSema;
#endif
#ifdef PLATFORM_FREERTOS
void * NFCTask;
#else
u32 NFCTask;
#endif
#ifdef CONFIG_NFC_VERIFY
//N2A Write Tag
u8 N2AWQRIdx;
u8 N2AWQWIdx;
N2A_W_QUEUE N2AWQ[N2A_Q_LENGTH];
//N2A Read Tag
u8 N2ARQRIdx;
u8 N2ARQWIdx;
N2A_R_QUEUE N2ARQ[N2A_Q_LENGTH];
//N2A Read Catch
u8 N2ARCRIdx;
u8 N2ARCWIdx;
N2A_CATCH_R_QUEUE N2ACatchR[N2A_Q_LENGTH];
#endif
//A2N Write Catch
//u8 A2NWCRIdx;
//u8 A2NWCWIdx;
//A2N_CATCH_W_QUEUE A2NCatchW[N2A_Q_LENGTH];
//A2N Write mailbox queue
u8 A2NWMailBox;
u8 A2NWQRIdx;
u8 A2NWQWIdx;
A2N_MAILBOX_Q A2NMAILQ[N2A_Q_LENGTH];
u8 TaskStop;
void *nfc_obj;
}NFC_ADAPTER, *PNFC_ADAPTER;
typedef enum _N2A_CMD_ {
TAG_READ = 0,
TAG_WRITE = 1,
CATCH_READ_DATA = 2,
NFC_R_PRESENT = 4,
N2A_MAILBOX_STATE = 5,
EXT_CLK_REQ = 6,
MAX_N2ACMD
} N2A_CMD, *PN2A_CMD;
typedef enum _A2N_CMD_ {
TAG_READ_DATA = 0,
CATCH_READ = 2,
CATCH_WRITE = 3,
A2N_MAILBOX_STATE = 4,
CONFIRM_N2A_BOX_STATE = 5,
EXT_CLK_RSP = 6,
MAX_A2NCMD
} A2N_CMD, *PA2N_CMD;
// Callback event defination
typedef enum _NFC_HAL_EVENT_ {
NFC_HAL_READER_PRESENT = (1<<0),
NFC_HAL_READ = (1<<1),
NFC_HAL_WRITE = (1<<2),
NFC_HAL_ERR = (1<<3),
NFC_HAL_CACHE_RD = (1<<4)
}NFC_CB_EVENT, *PNFC_CB_EVENT;
VOID A2NWriteCatch(IN VOID *pNFCAdapte, IN u8 N2AWPage,
IN u8 Length, IN u32 *WData);
VOID A2NReadCatch(IN VOID *pNFCAdapte, IN u8 A2NRPage);
VOID HalNFCDmemInit(IN u32 *pTagData, IN u32 TagLen);
VOID HalNFCInit(PNFC_ADAPTER pNFCAdp);
VOID HalNFCDeinit(PNFC_ADAPTER pNFCAdp);
VOID HalNFCFwDownload(VOID);
u32 HalNFCDbgRead32(IN u32 Addr);
VOID HalNFCDbgWrite32(IN u32 Addr, IN u32 Data);
#endif //CONFIG_NFC_NORMAL
#endif // #ifndef _RTL8195A_NFC_H_

1251
sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h Normal file
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37
sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pwm.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_PWM_H_
#define _RTL8195A_PWM_H_
extern void
HAL_Pwm_SetDuty_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern HAL_Status
HAL_Pwm_Init_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Enable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Disable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
#endif

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sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_ssi.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_SSI_H_
#define _RTL8195A_SSI_H_
#define SSI_DUMMY_DATA 0x00 // for master mode, we need to push a Dummy data to TX FIFO for read
#define SSI_CLK_SPI1 (PLATFORM_CLOCK/2)
#define SSI_CLK_SPI0_2 (PLATFORM_CLOCK/4)
/* Parameters of DW_apb_ssi for RTL8195A */
#define SSI_TX_FIFO_DEPTH 64
#define TX_ABW 6 // 1-8, log2(SSI_TX_FIFO_DEPTH)
#define SSI_RX_FIFO_DEPTH 64
#define RX_ABW 6 // 1-8, log2(SSI_RX_FIFO_DEPTH)
#define SSI0_REG_BASE 0x40042000
#define SSI1_REG_BASE 0x40042400
#define SSI2_REG_BASE 0x40042800
/* Memory Map of DW_apb_ssi */
#define REG_DW_SSI_CTRLR0 0x00 // 16 bits
#define REG_DW_SSI_CTRLR1 0x04 // 16 bits
#define REG_DW_SSI_SSIENR 0x08 // 1 bit
#define REG_DW_SSI_MWCR 0x0C // 3 bits
#define REG_DW_SSI_SER 0x10 //
#define REG_DW_SSI_BAUDR 0x14 // 16 bits
#define REG_DW_SSI_TXFTLR 0x18 // TX_ABW
#define REG_DW_SSI_RXFTLR 0x1C // RX_ABW
#define REG_DW_SSI_TXFLR 0x20 //
#define REG_DW_SSI_RXFLR 0x24 //
#define REG_DW_SSI_SR 0x28 // 7 bits
#define REG_DW_SSI_IMR 0x2C //
#define REG_DW_SSI_ISR 0x30 // 6 bits
#define REG_DW_SSI_RISR 0x34 // 6 bits
#define REG_DW_SSI_TXOICR 0x38 // 1 bits
#define REG_DW_SSI_RXOICR 0x3C // 1 bits
#define REG_DW_SSI_RXUICR 0x40 // 1 bits
#define REG_DW_SSI_MSTICR 0x44 // 1 bits
#define REG_DW_SSI_ICR 0x48 // 1 bits
#define REG_DW_SSI_DMACR 0x4C // 2 bits
#define REG_DW_SSI_DMATDLR 0x50 // TX_ABW
#define REG_DW_SSI_DMARDLR 0x54 // RX_ABW
#define REG_DW_SSI_IDR 0x58 // 32 bits
#define REG_DW_SSI_COMP_VERSION 0x5C // 32 bits
#define REG_DW_SSI_DR 0x60 // 16 bits 0x60-0xEC
#define REG_DW_SSI_RX_SAMPLE_DLY 0xF0 // 8 bits
#define REG_DW_SSI_RSVD_0 0xF4 // 32 bits
#define REG_DW_SSI_RSVD_1 0xF8 // 32 bits
#define REG_DW_SSI_RSVD_2 0xFC // 32 bits
// CTRLR0 0x00 // 16 bits, 6.2.1
// DFS Reset Value: 0x7
#define BIT_SHIFT_CTRLR0_DFS 0
#define BIT_MASK_CTRLR0_DFS 0xF
#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS)
#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS))
#define BIT_SHIFT_CTRLR0_FRF 4
#define BIT_MASK_CTRLR0_FRF 0x3
#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF)
#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF))
#define BIT_SHIFT_CTRLR0_SCPH 6
#define BIT_MASK_CTRLR0_SCPH 0x1
#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH)
#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH))
#define BIT_SHIFT_CTRLR0_SCPOL 7
#define BIT_MASK_CTRLR0_SCPOL 0x1
#define BIT_CTRLR0_SCPOL(x)(((x) & BIT_MASK_CTRLR0_SCPOL) << BIT_SHIFT_CTRLR0_SCPOL)
#define BIT_INVC_CTRLR0_SCPOL (~(BIT_MASK_CTRLR0_SCPOL << BIT_SHIFT_CTRLR0_SCPOL))
#define BIT_SHIFT_CTRLR0_TMOD 8
#define BIT_MASK_CTRLR0_TMOD 0x3
#define BIT_CTRLR0_TMOD(x)(((x) & BIT_MASK_CTRLR0_TMOD) << BIT_SHIFT_CTRLR0_TMOD)
#define BIT_INVC_CTRLR0_TMOD (~(BIT_MASK_CTRLR0_TMOD << BIT_SHIFT_CTRLR0_TMOD))
#define BIT_SHIFT_CTRLR0_SLV_OE 10
#define BIT_MASK_CTRLR0_SLV_OE 0x1
#define BIT_CTRLR0_SLV_OE(x)(((x) & BIT_MASK_CTRLR0_SLV_OE) << BIT_SHIFT_CTRLR0_SLV_OE)
#define BIT_INVC_CTRLR0_SLV_OE (~(BIT_MASK_CTRLR0_SLV_OE << BIT_SHIFT_CTRLR0_SLV_OE))
#define BIT_SHIFT_CTRLR0_SRL 11
#define BIT_MASK_CTRLR0_SRL 0x1
#define BIT_CTRLR0_SRL(x)(((x) & BIT_MASK_CTRLR0_SRL) << BIT_SHIFT_CTRLR0_SRL)
#define BIT_INVC_CTRLR0_SRL (~(BIT_MASK_CTRLR0_SRL << BIT_SHIFT_CTRLR0_SRL))
#define BIT_SHIFT_CTRLR0_CFS 12
#define BIT_MASK_CTRLR0_CFS 0xF
#define BIT_CTRLR0_CFS(x)(((x) & BIT_MASK_CTRLR0_CFS) << BIT_SHIFT_CTRLR0_CFS)
#define BIT_INVC_CTRLR0_CFS (~(BIT_MASK_CTRLR0_CFS << BIT_SHIFT_CTRLR0_CFS))
// CTRLR1 0x04 // 16 bits
#define BIT_SHIFT_CTRLR1_NDF 0
#define BIT_MASK_CTRLR1_NDF 0xFFFF
#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF)
#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF))
// SSIENR 0x08 // 1 bit
#define BIT_SHIFT_SSIENR_SSI_EN 0
#define BIT_MASK_SSIENR_SSI_EN 0x1
#define BIT_SSIENR_SSI_EN(x)(((x) & BIT_MASK_SSIENR_SSI_EN) << BIT_SHIFT_SSIENR_SSI_EN)
#define BIT_INVC_SSIENR_SSI_EN (~(BIT_MASK_SSIENR_SSI_EN << BIT_SHIFT_SSIENR_SSI_EN))
// MWCR 0x0c // 3 bits
#define BIT_SHIFT_MWCR_MWMOD 0
#define BIT_MASK_MWCR_MWMOD 0x1
#define BIT_MWCR_MWMOD(x)(((x) & BIT_MASK_MWCR_MWMOD) << BIT_SHIFT_MWCR_MWMOD)
#define BIT_INVC_MWCR_MWMOD (~(BIT_MASK_MWCR_MWMOD << BIT_SHIFT_MWCR_MWMOD))
#define BIT_SHIFT_MWCR_MDD 1
#define BIT_MASK_MWCR_MDD 0x1
#define BIT_MWCR_MDD(x)(((x) & BIT_MASK_MWCR_MDD) << BIT_SHIFT_MWCR_MDD)
#define BIT_INVC_MWCR_MDD (~(BIT_MASK_MWCR_MDD << BIT_SHIFT_MWCR_MDD))
#define BIT_SHIFT_MWCR_MHS 2
#define BIT_MASK_MWCR_MHS 0x1
#define BIT_MWCR_MHS(x)(((x) & BIT_MASK_MWCR_MHS) << BIT_SHIFT_MWCR_MHS)
#define BIT_INVC_MWCR_MHS (~(BIT_MASK_MWCR_MHS << BIT_SHIFT_MWCR_MHS))
// SER 0x10 // Variable Length
#define BIT_SHIFT_SER_SER 0
#define BIT_MASK_SER_SER 0xFF
#define BIT_SER_SER(x)(((x) & BIT_MASK_SER_SER) << BIT_SHIFT_SER_SER)
#define BIT_INVC_SER_SER (~(BIT_MASK_SER_SER << BIT_SHIFT_SER_SER))
// BAUDR 0x14 // 16 bits
#define BIT_SHIFT_BAUDR_SCKDV 0
#define BIT_MASK_BAUDR_SCKDV 0xFFFF
#define BIT_BAUDR_SCKDV(x)(((x) & BIT_MASK_BAUDR_SCKDV) << BIT_SHIFT_BAUDR_SCKDV)
#define BIT_INVC_BAUDR_SCKDV (~(BIT_MASK_BAUDR_SCKDV << BIT_SHIFT_BAUDR_SCKDV))
// TXFLTR 0x18 // Variable Length
#define BIT_SHIFT_TXFTLR_TFT 0
#define BIT_MASK_TXFTLR_TFT 0x3F // (TX_ABW-1):0
#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT)
#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT))
// RXFLTR 0x1c // Variable Length
#define BIT_SHIFT_RXFTLR_RFT 0
#define BIT_MASK_RXFTLR_RFT 0x3F // (RX_ABW-1):0
#define BIT_RXFTLR_RFT(x)(((x) & BIT_MASK_RXFTLR_RFT) << BIT_SHIFT_RXFTLR_RFT)
#define BIT_INVC_RXFTLR_RFT (~(BIT_MASK_RXFTLR_RFT << BIT_SHIFT_RXFTLR_RFT))
// TXFLR 0x20 // see [READ ONLY]
#define BIT_MASK_TXFLR_TXTFL 0x7F // (TX_ABW):0
// RXFLR 0x24 // see [READ ONLY]
#define BIT_MASK_RXFLR_RXTFL 0x7F // (RX_ABW):0
// SR 0x28 // 7 bits [READ ONLY]
#define BIT_SR_BUSY BIT0
#define BIT_SR_TFNF BIT1
#define BIT_SR_TFE BIT2
#define BIT_SR_RFNE BIT3
#define BIT_SR_RFF BIT4
#define BIT_SR_TXE BIT5
#define BIT_SR_DCOL BIT6
// IMR 0x2c // see
#define BIT_SHIFT_IMR_TXEIM 0
#define BIT_MASK_IMR_TXEIM 0x1
// #define BIT_IMR_TXEIM(x)(((x) & BIT_MASK_IMR_TXEIM) << BIT_SHIFT_IMR_TXEIM)
#define BIT_INVC_IMR_TXEIM (~(BIT_MASK_IMR_TXEIM << BIT_SHIFT_IMR_TXEIM))
#define BIT_SHIFT_IMR_TXOIM 1
#define BIT_MASK_IMR_TXOIM 0x1
// #define BIT_IMR_TXOIM(x)(((x) & BIT_MASK_IMR_TXOIM) << BIT_SHIFT_IMR_TXOIM)
#define BIT_INVC_IMR_TXOIM (~(BIT_MASK_IMR_TXOIM << BIT_SHIFT_IMR_TXOIM))
#define BIT_SHIFT_IMR_RXUIM 2
#define BIT_MASK_IMR_RXUIM 0x1
// #define BIT_IMR_RXUIM(x)(((x) & BIT_MASK_IMR_RXUIM) << BIT_SHIFT_IMR_RXUIM)
#define BIT_INVC_IMR_RXUIM (~(BIT_MASK_IMR_RXUIM << BIT_SHIFT_IMR_RXUIM))
#define BIT_SHIFT_IMR_RXOIM 3
#define BIT_MASK_IMR_RXOIM 0x1
// #define BIT_IMR_RXOIM(x)(((x) & BIT_MASK_IMR_RXOIM) << BIT_SHIFT_IMR_RXOIM)
#define BIT_INVC_IMR_RXOIM (~(BIT_MASK_IMR_RXOIM << BIT_SHIFT_IMR_RXOIM))
#define BIT_SHIFT_IMR_RXFIM 4
#define BIT_MASK_IMR_RXFIM 0x1
// #define BIT_IMR_RXFIM(x)(((x) & BIT_MASK_IMR_RXFIM) << BIT_SHIFT_IMR_RXFIM)
#define BIT_INVC_IMR_RXFIM (~(BIT_MASK_IMR_RXFIM << BIT_SHIFT_IMR_RXFIM))
#define BIT_SHIFT_IMR_MSTIM 5
#define BIT_MASK_IMR_MSTIM 0x1
// #define BIT_IMR_MSTIM(x)(((x) & BIT_MASK_IMR_MSTIM) << BIT_SHIFT_IMR_MSTIM)
#define BIT_INVC_IMR_MSTIM (~(BIT_MASK_IMR_MSTIM << BIT_SHIFT_IMR_MSTIM))
#define BIT_IMR_TXEIM BIT0
#define BIT_IMR_TXOIM BIT1
#define BIT_IMR_RXUIM BIT2
#define BIT_IMR_RXOIM BIT3
#define BIT_IMR_RXFIM BIT4
#define BIT_IMR_MSTIM BIT5
// ISR 0x30 // 6 bits [READ ONLY]
#define BIT_ISR_TXEIS BIT0
#define BIT_ISR_TXOIS BIT1
#define BIT_ISR_RXUIS BIT2
#define BIT_ISR_RXOIS BIT3
#define BIT_ISR_RXFIS BIT4
#define BIT_ISR_MSTIS BIT5
// RISR 0x34 // 6 bits [READ ONLY]
#define BIT_RISR_TXEIR BIT0
#define BIT_RISR_TXOIR BIT1
#define BIT_RISR_RXUIR BIT2
#define BIT_RISR_RXOIR BIT3
#define BIT_RISR_RXFIR BIT4
#define BIT_RISR_MSTIR BIT5
// TXOICR 0x38 // 1 bits [READ ONLY]
// RXOICR 0x3c // 1 bits [READ ONLY]
// RXUICR 0x40 // 1 bits [READ ONLY]
// MSTICR 0x44 // 1 bits [READ ONLY]
// ICR 0x48 // 1 bits [READ ONLY]
// DMACR 0x4c // 2 bits
#define BIT_SHIFT_DMACR_RDMAE 0
#define BIT_MASK_DMACR_RDMAE 0x1
#define BIT_DMACR_RDMAE(x)(((x) & BIT_MASK_DMACR_RDMAE) << BIT_SHIFT_DMACR_RDMAE)
#define BIT_INVC_DMACR_RDMAE (~(BIT_MASK_DMACR_RDMAE << BIT_SHIFT_DMACR_RDMAE))
#define BIT_SHIFT_DMACR_TDMAE 1
#define BIT_MASK_DMACR_TDMAE 0x1
#define BIT_DMACR_TDMAE(x)(((x) & BIT_MASK_DMACR_TDMAE) << BIT_SHIFT_DMACR_TDMAE)
#define BIT_INVC_DMACR_TDMAE (~(BIT_MASK_DMACR_TDMAE << BIT_SHIFT_DMACR_TDMAE))
// DMATDLR 0x50
#define BIT_SHIFT_DMATDLR_DMATDL 0
#define BIT_MASK_DMATDLR_DMATDL 0x3F // (TX_ABW-1):0
#define BIT_DMATDLR_DMATDL(x)(((x) & BIT_MASK_DMATDLR_DMATDL) << BIT_SHIFT_DMATDLR_DMATDL)
#define BIT_INVC_DMATDLR_DMATDL (~(BIT_MASK_DMATDLR_DMATDL << BIT_SHIFT_DMATDLR_DMATDL))
// DMARDLR 0x54
#define BIT_SHIFT_DMARDLR_DMARDL 0
#define BIT_MASK_DMARDLR_DMARDL 0x3F // (RX_ABW-1):0
#define BIT_DMARDLR_DMARDL(x)(((x) & BIT_MASK_DMARDLR_DMARDL) << BIT_SHIFT_DMARDLR_DMARDL)
#define BIT_INVC_DMARDLR_DMARDL (~(BIT_MASK_DMARDLR_DMARDL << BIT_SHIFT_DMARDLR_DMARDL))
// IDR 0x58 // 32 bits [READ ONLY]
// COMP_VERSION 0x5c // 32 bits [READ ONLY]
// DR 0x60 // 16 bits 0x60-0xEC
#define BIT_SHIFT_DR_DR 0
#define BIT_MASK_DR_DR 0xFFFF
#define BIT_DR_DR(x)(((x) & BIT_MASK_DR_DR) << BIT_SHIFT_DR_DR)
#define BIT_INVC_DR_DR (~(BIT_MASK_DR_DR << BIT_SHIFT_DR_DR))
// RX_SAMPLE_DLY 0xF0 // 8 bits
#define BIT_SHIFT_RX_SAMPLE_DLY_RSD 0
#define BIT_MASK_RX_SAMPLE_DLY_RSD 0xFFFF
#define BIT_RX_SAMPLE_DLY_RSD(x)(((x) & BIT_MASK_RX_SAMPLE_DLY_RSD) << BIT_SHIFT_RX_SAMPLE_DLY_RSD)
#define BIT_INVC_RX_SAMPLE_DLY_RSD (~(BIT_MASK_RX_SAMPLE_DLY_RSD << BIT_SHIFT_RX_SAMPLE_DLY_RSD))
// RSVD_0 0xF4 // 32 bits
// RSVD_1 0xF8 // 32 bits
// RSVD_2 0xFC // 32 bits
// SSI0 Pinmux
#define BIT_SHIFT_SSI0_PIN_EN 0
#define BIT_MASK_SSI0_PIN_EN 0x1
#define BIT_SSI0_PIN_EN(x)(((x) & BIT_MASK_SSI0_PIN_EN) << BIT_SHIFT_SSI0_PIN_EN)
#define BIT_INVC_SSI0_PIN_EN (~(BIT_MASK_SSI0_PIN_EN << BIT_SHIFT_SSI0_PIN_EN))
#define BIT_SHIFT_SSI0_PIN_SEL 1
#define BIT_MASK_SSI0_PIN_SEL 0x7
#define BIT_SSI0_PIN_SEL(x)(((x) & BIT_MASK_SSI0_PIN_SEL) << BIT_SHIFT_SSI0_PIN_SEL)
#define BIT_INVC_SSI0_PIN_SEL (~(BIT_MASK_SSI0_PIN_SEL << BIT_SHIFT_SSI0_PIN_SEL))
// SSI1 Pinmux
#define BIT_SHIFT_SSI1_PIN_EN 4
#define BIT_MASK_SSI1_PIN_EN 0x1
#define BIT_SSI1_PIN_EN(x)(((x) & BIT_MASK_SSI1_PIN_EN) << BIT_SHIFT_SSI1_PIN_EN)
#define BIT_INVC_SSI1_PIN_EN (~(BIT_MASK_SSI1_PIN_EN << BIT_SHIFT_SSI1_PIN_EN))
#define BIT_SHIFT_SSI1_PIN_SEL 5
#define BIT_MASK_SSI1_PIN_SEL 0x7
#define BIT_SSI1_PIN_SEL(x)(((x) & BIT_MASK_SSI1_PIN_SEL) << BIT_SHIFT_SSI1_PIN_SEL)
#define BIT_INVC_SSI1_PIN_SEL (~(BIT_MASK_SSI1_PIN_SEL << BIT_SHIFT_SSI1_PIN_SEL))
// SSI2 Pinmux
#define BIT_SHIFT_SSI2_PIN_EN 8
#define BIT_MASK_SSI2_PIN_EN 0x1
#define BIT_SSI2_PIN_EN(x)(((x) & BIT_MASK_SSI2_PIN_EN) << BIT_SHIFT_SSI2_PIN_EN)
#define BIT_INVC_SSI2_PIN_EN (~(BIT_MASK_SSI2_PIN_EN << BIT_SHIFT_SSI2_PIN_EN))
#define BIT_SHIFT_SSI2_PIN_SEL 9
#define BIT_MASK_SSI2_PIN_SEL 0x7
#define BIT_SSI2_PIN_SEL(x)(((x) & BIT_MASK_SSI2_PIN_SEL) << BIT_SHIFT_SSI2_PIN_SEL)
#define BIT_INVC_SSI2_PIN_SEL (~(BIT_MASK_SSI2_PIN_SEL << BIT_SHIFT_SSI2_PIN_SEL))
// SSI0 Multiple Chip Selection (Pinmux Select is controlled by BIT_SSI0_PIN_SEL)
#define BIT_SHIFT_SSI0_MULTI_CS_EN 28
#define BIT_MASK_SSI0_MULTI_CS_EN 0x1
#define BIT_SSI0_MULTI_CS_EN(x)(((x) & BIT_MASK_SSI0_MULTI_CS_EN) << BIT_SHIFT_SSI0_MULTI_CS_EN)
#define BIT_INVC_SSI0_MULTI_CS_EN (~(BIT_MASK_SSI0_MULTI_CS_EN << BIT_SHIFT_SSI0_MULTI_CS_EN))
#define HAL_SSI_READ32(SsiIndex, addr) \
HAL_READ32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE32(SsiIndex, addr, value) \
HAL_WRITE32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
#define HAL_SSI_READ16(SsiIndex, addr) \
HAL_READ16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE16(SsiIndex, addr, value) \
HAL_WRITE16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
#define HAL_SSI_READ8(SsiIndex, addr) \
HAL_READ8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE8(SsiIndex, addr, value) \
HAL_WRITE8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
// SSI Pinmux Select
typedef enum _SSI0_PINMUX_SELECT_ {
SSI0_MUX_TO_GPIOE = S0,
SSI0_MUX_TO_GPIOC = S1
}SSI0_PINMUX_SELECT, *PSSI0_PINMUX_SELECT;
typedef enum _SSI1_PINMUX_SELECT_ {
SSI1_MUX_TO_GPIOA = S0,
SSI1_MUX_TO_GPIOB = S1,
SSI1_MUX_TO_GPIOD = S2
}SSI1_PINMUX_SELECT, *PSSI1_PINMUX_SELECT;
typedef enum _SSI2_PINMUX_SELECT_ {
SSI2_MUX_TO_GPIOG = S0,
SSI2_MUX_TO_GPIOE = S1,
SSI2_MUX_TO_GPIOD = S2
}SSI2_PINMUX_SELECT, *PSSI2_PINMUX_SELECT;
typedef enum _SSI0_MULTI_CS_PINMUX_SELECT_ {
SSI0_CS_MUX_TO_GPIOE = S0,
SSI0_CS_MUX_TO_GPIOC = S1
}SSI0_MULTI_CS_PINMUX_SELECT, *PSSI0_MULTI_CS_PINMUX_SELECT;
typedef enum _SSI_CTRLR0_TMOD_ {
TMOD_TR = 0,
TMOD_TO = 1,
TMOD_RO = 2,
TMOD_EEPROM_R = 3
}SSI_CTRLR0_TMOD, *PSSI_CTRLR0_TMOD;
typedef enum _SSI_CTRLR0_SCPOL_ {
SCPOL_INACTIVE_IS_LOW = 0,
SCPOL_INACTIVE_IS_HIGH = 1
}SSI_CTRLR0_SCPOL, *PSSI_CTRLR0_SCPOL;
typedef enum _SSI_CTRLR0_SCPH_ {
SCPH_TOGGLES_IN_MIDDLE = 0,
SCPH_TOGGLES_AT_START = 1
}SSI_CTRLR0_SCPH, *PSSI_CTRLR0_SCPH;
typedef enum _SSI_CTRLR0_DFS_ {
DFS_4_BITS = 3,
DFS_5_BITS = 4,
DFS_6_BITS = 5,
DFS_7_BITS = 6,
DFS_8_BITS = 7,
DFS_9_BITS = 8,
DFS_10_BITS = 9,
DFS_11_BITS = 10,
DFS_12_BITS = 11,
DFS_13_BITS = 12,
DFS_14_BITS = 13,
DFS_15_BITS = 14,
DFS_16_BITS = 15,
}SSI_CTRLR0_DFS, *PSSI_CTRLR0_DFS;
typedef enum _SSI_CTRLR0_CFS_ {
CFS_1_BIT = 0,
CFS_2_BITS = 1,
CFS_3_BITS = 2,
CFS_4_BITS = 3,
CFS_5_BITS = 4,
CFS_6_BITS = 5,
CFS_7_BITS = 6,
CFS_8_BITS = 7,
CFS_9_BITS = 8,
CFS_10_BITS = 9,
CFS_11_BITS = 10,
CFS_12_BITS = 11,
CFS_13_BITS = 12,
CFS_14_BITS = 13,
CFS_15_BITS = 14,
CFS_16_BITS = 15
}SSI_CTRLR0_CFS, *PSSI_CTRLR0_CFS;
typedef enum _SSI_CTRLR0_SLV_OE_ {
SLV_TXD_ENABLE = 0,
SLV_TXD_DISABLE = 1
}SSI_CTRLR0_SLV_OE, *PSSI_CTRLR0_SLV_OE;
typedef enum _SSI_ROLE_SELECT_ {
SSI_SLAVE = 0,
SSI_MASTER = 1
}SSI_ROLE_SELECT, *PSSI_ROLE_SELECT;
typedef enum _SSI_FRAME_FORMAT_ {
FRF_MOTOROLA_SPI = 0,
FRF_TI_SSP = 1,
FRF_NS_MICROWIRE = 2,
FRF_RSVD = 3
}SSI_FRAME_FORMAT, *PSSI_FRAME_FORMAT;
typedef enum _SSI_DMACR_ENABLE_ {
SSI_NODMA = 0,
SSI_RXDMA_ENABLE = 1,
SSI_TXDMA_ENABLE = 2,
SSI_TRDMA_ENABLE = 3
}SSI_DMACR_ENABLE, *PSSI_DMACR_ENABLE;
typedef enum _SSI_MWCR_HANDSHAKE_ {
MW_HANDSHAKE_DISABLE = 0,
MW_HANDSHAKE_ENABLE = 1
}SSI_MWCR_HANDSHAKE, *PSSI_MWCR_HANDSHAKE;
typedef enum _SSI_MWCR_DIRECTION_ {
MW_DIRECTION_SLAVE_TO_MASTER = 0,
MW_DIRECTION_MASTER_TO_SLAVE = 1
}SSI_MWCR_DIRECTION, *PSSI_MWCR_DIRECTION;
typedef enum _SSI_MWCR_TMOD_ {
MW_TMOD_NONSEQUENTIAL = 0,
MW_TMOD_SEQUENTIAL = 1
}SSI_MWCR_TMOD, *PSSI_MWCR_TMOD;
typedef enum _SSI_DATA_TRANSFER_MECHANISM_ {
SSI_DTM_BASIC,
SSI_DTM_INTERRUPT,
SSI_DTM_DMA
}SSI_DATA_TRANSFER_MECHANISM, *PSSI_DATA_TRANSFER_MECHANISM;
_LONG_CALL_ HAL_Status HalSsiPinmuxEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiDisableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiInitRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetSclkPolarityRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetSclkPhaseRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiWriteRtl8195a(VOID *Adaptor, u32 value);
_LONG_CALL_ HAL_Status HalSsiLoadSettingRtl8195a(VOID *Adaptor, VOID *Setting);
_LONG_CALL_ HAL_Status HalSsiSetInterruptMaskRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetDeviceRoleRtl8195a(VOID *Adaptor, u32 Role);
_LONG_CALL_ HAL_Status HalSsiInterruptEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiInterruptDisableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiReadInterruptRtl8195a(VOID *Adaptor, VOID *RxData, u32 Length);
_LONG_CALL_ HAL_Status HalSsiSetRxFifoThresholdLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetTxFifoThresholdLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiWriteInterruptRtl8195a(VOID *Adaptor, VOID *TxData, u32 Length);
_LONG_CALL_ HAL_Status HalSsiSetSlaveEnableRegisterRtl8195a(VOID *Adaptor, u32 SlaveIndex);
_LONG_CALL_ u32 HalSsiBusyRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiWriteableRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiReadableRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetInterruptMaskRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetRxFifoLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetTxFifoLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetInterruptStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiReadRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetRawInterruptStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetSlaveEnableRegisterRtl8195a(VOID *Adaptor);
_LONG_CALL_ VOID _SsiReadInterrupt(VOID *Adaptor);
_LONG_CALL_ VOID _SsiWriteInterrupt(VOID *Adaptor);
_LONG_CALL_ u32 _SsiIrqHandle(VOID *Adaptor);
// ROM code patch
VOID _SsiReadInterruptRtl8195a(VOID *Adapter);
VOID _SsiWriteInterruptRtl8195a(VOID *Adapter);
HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor);
HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor);
HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor);
HAL_Status HalSsiDeInitRtl8195a(VOID * Adapter);
HAL_Status HalSsiClockOffRtl8195a(VOID * Adapter);
HAL_Status HalSsiClockOnRtl8195a(VOID * Adapter);
VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate);
HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length);
HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
#ifdef CONFIG_GDMA_EN
VOID HalSsiTxGdmaLoadDefRtl8195a(VOID *Adapter);
VOID HalSsiRxGdmaLoadDefRtl8195a(VOID *Adapter);
VOID HalSsiDmaInitRtl8195a(VOID *Adapter);
HAL_Status HalSsiDmaSendRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
HAL_Status HalSsiDmaRecvRtl8195a(VOID *Adapter, u8 *pRxData, u32 Length);
#endif // end of "#ifdef CONFIG_GDMA_EN"
#endif

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sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h Normal file
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sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_timer.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_TIMER_H_
#define _RTL8195A_TIMER_H_
#define TIMER_TICK_US 31
#define TIMER_LOAD_COUNT_OFF 0x00
#define TIMER_CURRENT_VAL_OFF 0x04
#define TIMER_CTL_REG_OFF 0x08
#define TIMER_EOI_OFF 0x0c
#define TIMER_INT_STATUS_OFF 0x10
#define TIMER_INTERVAL 0x14
#define TIMERS_INT_STATUS_OFF 0xa0
#define TIMERS_EOI_OFF 0xa4
#define TIMERS_RAW_INT_STATUS_OFF 0xa8
#define TIMERS_COMP_VER_OFF 0xac
#define MAX_TIMER_VECTOR_TABLE_NUM 6
#define HAL_TIMER_READ32(addr) (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE32(addr, value) ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ16(addr) (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE16(addr, value) ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ8(addr) (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE8(addr, value) ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value)
_LONG_CALL_ u32
HalGetTimerIdRtl8195a(
IN u32 *TimerID
);
_LONG_CALL_ BOOL
HalTimerInitRtl8195a(
IN VOID *Data
);
_LONG_CALL_ u32
HalTimerReadCountRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerIrqClearRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDisRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerEnRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDumpRegRtl8195a(
IN u32 TimerId
);
// ROM Code patch
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
);
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
);
VOID
HalTimerClearIsrRtl8195a(
IN u32 TimerId
);
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
);
#ifdef CONFIG_CHIP_C_CUT
__weak _LONG_CALL_
VOID
HalTimerIrq2To7HandleV02(
IN VOID *Data
);
__weak _LONG_CALL_
HAL_Status
HalTimerIrqRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
HAL_Status
HalTimerInitRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
u32
HalTimerReadCountRtl8195aV02(
IN u32 TimerId
);
__weak _LONG_CALL_
VOID
HalTimerReLoadRtl8195aV02(
IN u32 TimerId,
IN u32 LoadUs
);
__weak _LONG_CALL_
HAL_Status
HalTimerIrqUnRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
VOID
HalTimerDeInitRtl8195aV02(
IN VOID *Data
);
#endif // end of "#ifdef CONFIG_CHIP_C_CUT"
// HAL functions wrapper
static __inline HAL_Status
HalTimerInit(
IN VOID *Data
)
{
return (HalTimerInitRtl8195a_Patch(Data));
}
static __inline VOID
HalTimerEnable(
IN u32 TimerId
)
{
HalTimerIrqEnRtl8195a(TimerId);
HalTimerEnRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerDisable(
IN u32 TimerId
)
{
HalTimerDisRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerClearIsr(
IN u32 TimerId
)
{
HalTimerClearIsrRtl8195a(TimerId);
}
static __inline VOID
HalTimerReLoad(
IN u32 TimerId,
IN u32 LoadUs
)
{
HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs);
}
#ifndef CONFIG_CHIP_C_CUT
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195a_Patch(Data);
}
#else
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195aV02(Data);
}
#endif // end of "#ifndef CONFIG_CHIP_C_CUT"
#endif //_RTL8195A_TIMER_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_UART_H_
#define _RTL8195A_UART_H_
#define MAX_UART_INDEX 2
#define RUART_DLL_OFF 0x00
#define RUART_DLM_OFF 0x04 //RW, DLAB = 1
#define RUART_INTERRUPT_EN_REG_OFF 0x04
#define RUART_IER_ERBI 0x01 //BIT0, Enable Received Data Available Interrupt (rx trigger)
#define RUART_IER_ETBEI (1<<1) //BIT1, Enable Transmitter FIFO Empty Interrupt (tx fifo empty)
#define RUART_IER_ELSI (1<<2) //BIT2, Enable Receiver Line Status Interrupt (receiver line status)
#define RUART_IER_EDSSI (1<<3) //BIT3, Enable Modem Status Interrupt (modem status transition)
#define RUART_INT_ID_REG_OFF 0x08 //[R]
#define RUART_IIR_INT_PEND 0x01
#define RUART_IIR_INT_ID (0x07<<1) //011(3), 010(2), 110(6), 001(1), 000(0)
#define RUART_FIFO_CTL_REG_OFF 0x08 //[W]
#define RUART_FIFO_CTL_REG_CLEAR_RXFIFO (1<<1) //BIT1, 0x02, Write 1 clear
#define RUART_FIFO_CTL_REG_CLEAR_TXFIFO (1<<2) //BIT2, 0x04, Write 1 clear
#define RUART_FIFO_CTL_REG_DMA_ENABLE 0x08 //BIT3
#define FIFO_CTL_DEFAULT_WITH_FIFO_DMA 0xC9
#define FIFO_CTL_DEFAULT_WITH_FIFO 0xC1
#define RUART_MODEM_CTL_REG_OFF 0x10
#define RUART_MCR_RTS BIT1
#define RUART_MCL_AUTOFLOW_ENABLE (1<<5) //BIT5, 0x20
#define RUART_LINE_CTL_REG_OFF 0x0C
#define RUART_LINE_CTL_REG_DLAB_ENABLE (1<<7) //BIT7, 0x80
#define RUART_LINE_STATUS_REG_OFF 0x14
#define RUART_LINE_STATUS_REG_DR 0x01 //BIT0, Data Ready indicator
#define RUART_LINE_STATUS_ERR_OVERRUN (1<<1) //BIT1, Over Run
#define RUART_LINE_STATUS_ERR_PARITY (1<<2) //BIT2, Parity error
#define RUART_LINE_STATUS_ERR_FRAMING (1<<3) //BIT3, Framing error
#define RUART_LINE_STATUS_ERR_BREAK (1<<4) //BIT4, Break interrupt error
#define RUART_LINE_STATUS_REG_THRE (1<<5) //BIT5, 0x20, Transmit Holding Register Empty Interrupt enable
#define RUART_LINE_STATUS_REG_TEMT (1<<6) //BIT6, 0x40, Transmitter Empty indicator(bit)
#define RUART_LINE_STATUS_ERR_RXFIFO (1<<7) //BIT7, RX FIFO error
#define RUART_LINE_STATUS_ERR (RUART_LINE_STATUS_ERR_OVERRUN|RUART_LINE_STATUS_ERR_PARITY| \
RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \
RUART_LINE_STATUS_ERR_RXFIFO) //Line status error
#define RUART_MODEM_STATUS_REG_OFF 0x18 //Modem Status Register
#define RUART_SCRATCH_PAD_REG_OFF 0x1C //Scratch Pad Register
#define RUART_SP_REG_RXBREAK_INT_STATUS (1<<7) //BIT7, 0x80, Write 1 clear
#define RUART_SP_REG_DBG_SEL (0x0F<<8) //[11:8], Debug port selection
#define RUART_SP_REG_XFACTOR_ADJ (0x7FF<<16) //[26:16]
#define RUART_STS_REG_OFF 0x20
#define RUART_STS_REG_RESET_RCV (1<<3) //BIT3, 0x08, Reset Uart Receiver
#define RUART_STS_REG_XFACTOR 0xF<<4
#define RUART_REV_BUF_REG_OFF 0x24 //Receiver Buffer Register
#define RUART_TRAN_HOLD_REG_OFF 0x24 //Transmitter Holding Register
#define RUART_MISC_CTL_REG_OFF 0x28
#define RUART_TXDMA_BURSTSIZE_MASK 0xF8 //7:3
#define RUART_RXDMA_BURSTSIZE_MASK 0x1F00 //12:8
#define RUART_DEBUG_REG_OFF 0x3C
// RUART_LINE_CTL_REG_OFF (0x0C)
#define BIT_SHIFT_LCR_WLS 0 // word length select: 0: 7 bits, 1: 8bits
#define BIT_MASK_LCR_WLS_8BITS 0x1
#define BIT_LCR_WLS(x)(((x) & BIT_MASK_LCR_WLS_8BITS) << BIT_SHIFT_LCR_WLS)
#define BIT_CLR_LCR_WLS (~(BIT_MASK_LCR_WLS_8BITS << BIT_SHIFT_LCR_WLS))
#define BIT_SHIFT_LCR_STB 2 // Stop bit select: 0: no stop bit, 1: 1 stop bit
#define BIT_MASK_LCR_STB_EN 0x1
#define BIT_LCR_STB_EN(x)(((x) & BIT_MASK_LCR_STB_EN) << BIT_SHIFT_LCR_STB)
#define BIT_INVC_LCR_STB_EN (~(BIT_MASK_LCR_STB_EN << BIT_SHIFT_LCR_STB))
#define BIT_SHIFT_LCR_PARITY_EN 3
#define BIT_MASK_LCR_PARITY_EN 0x1
#define BIT_LCR_PARITY_EN(x)(((x) & BIT_MASK_LCR_PARITY_EN) << BIT_SHIFT_LCR_PARITY_EN)
#define BIT_INVC_LCR_PARITY_EN (~(BIT_MASK_LCR_PARITY_EN << BIT_SHIFT_LCR_PARITY_EN))
#define BIT_SHIFT_LCR_PARITY_TYPE 4
#define BIT_MASK_LCR_PARITY_TYPE 0x1
#define BIT_LCR_PARITY_TYPE(x)(((x) & BIT_MASK_LCR_PARITY_TYPE) << BIT_SHIFT_LCR_PARITY_TYPE)
#define BIT_INVC_LCR_PARITY_TYPE (~(BIT_MASK_LCR_PARITY_TYPE << BIT_SHIFT_LCR_PARITY_TYPE))
#define BIT_SHIFT_LCR_STICK_PARITY_EN 5
#define BIT_MASK_LCR_STICK_PARITY_EN 0x1
#define BIT_LCR_STICK_PARITY_EN(x)(((x) & BIT_MASK_LCR_STICK_PARITY_EN) << BIT_SHIFT_LCR_STICK_PARITY_EN)
#define BIT_INVC_LCR_STICK_PARITY_EN (~(BIT_MASK_LCR_STICK_PARITY_EN << BIT_SHIFT_LCR_STICK_PARITY_EN))
#define BIT_SHIFT_LCR_BREAK_CTRL 6
#define BIT_MASK_LCR_BREAK_CTRL 0x1
#define BIT_UART_LCR_BREAK_CTRL ((BIT_MASK_LCR_BREAK_CTRL) << BIT_SHIFT_LCR_BREAK_CTRL)
#define RUART_BAUD_RATE_2400 2400
#define RUART_BAUD_RATE_4800 4800
#define RUART_BAUD_RATE_9600 9600
#define RUART_BAUD_RATE_19200 19200
#define RUART_BAUD_RATE_38400 38400
#define RUART_BAUD_RATE_57600 57600
#define RUART_BAUD_RATE_115200 115200
#define RUART_BAUD_RATE_921600 921600
#define RUART_BAUD_RATE_1152000 1152000
#define HAL_RUART_READ32(UartIndex, addr) \
HAL_READ32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE32(UartIndex, addr, value) \
HAL_WRITE32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
#define HAL_RUART_READ16(UartIndex, addr) \
HAL_READ16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE16(UartIndex, addr, value) \
HAL_WRITE16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
#define HAL_RUART_READ8(UartIndex, addr) \
HAL_READ8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE8(UartIndex, addr, value) \
HAL_WRITE8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
#define UART_OVSR_POOL_MIN 1000
#define UART_OVSR_POOL_MAX 2090
#define DIVISOR_RESOLUTION 10
#define JITTER_LIMIT 100
#define UART_SCLK (200000000*5/12)
typedef struct _RUART_SPEED_SETTING_ {
u32 BaudRate;
u32 Ovsr;
u32 Div;
u16 Ovsr_adj;
u8 Ovsr_adj_max_bits; // 9: No parity, 10: with Parity
u8 Ovsr_adj_bits;
u16 *Ovsr_adj_map;
u32 max_err; // 10 ~ 100: 30
u32 Ovsr_min; // 10 ~ 20: 1000
u32 Ovsr_max; // 10 ~ 20: 2000
u32 divisor_resolution; // 1 ~ 20: 10
u32 jitter_lim; // 50 ~ 100: 100
u32 sclk; // 83.33333 MHz
}RUART_SPEED_SETTING, *PRUART_SPEED_SETTING;
typedef enum _UART_RXFIFO_TRIGGER_LEVEL_ {
OneByte = 0x00,
FourBytes = 0x01,
EightBytes = 0x10,
FourteenBytes = 0x11
}UART_RXFIFO_TRIGGER_LEVEL, *PUART_RXFIFO_TRIGGER_LEVEL;
typedef enum _RUART0_PINMUX_SELECT_ {
RUART0_MUX_TO_GPIOC = S0,
RUART0_MUX_TO_GPIOE = S1,
RUART0_MUX_TO_GPIOA = S2
}RUART0_PINMUX_SELECT, *PRUART0_PINMUX_SELECT;
typedef enum _RUART1_PINMUX_SELECT_ {
RUART1_MUX_TO_GPIOD = S0,
RUART1_MUX_TO_GPIOE = S1,
RUART1_MUX_TO_GPIOB = S2
}RUART1_PINMUX_SELECT, *PRUART1_PINMUX_SELECT;
typedef enum _RUART2_PINMUX_SELECT_ {
RUART2_MUX_TO_GPIOA = S0,
RUART2_MUX_TO_GPIOC = S1,
RUART2_MUX_TO_GPIOD = S2
}RUART2_PINMUX_SELECT, *PRUART2_PINMUX_SELECT;
typedef enum _RUART_FLOW_CONTROL_ {
AUTOFLOW_DISABLE = 0,
AUTOFLOW_ENABLE = 1
}RUART_FLOW_CONTROL, *PRUART_FLOW_CONTROL;
typedef enum _RUART_WORD_LEN_SEL_ {
RUART_WLS_7BITS = 0,
RUART_WLS_8BITS = 1
}RUART_WORD_LEN_SEL, *PRUART_WORD_LEN_SEL;
typedef enum _RUART_STOP_BITS_ {
RUART_STOP_BIT_1 = 0,
RUART_STOP_BIT_2 = 1
}RUART_STOP_BITS, *PRUART_STOP_BITS;
typedef enum _RUART_PARITY_CONTROL_ {
RUART_PARITY_DISABLE = 0,
RUART_PARITY_ENABLE = 1
}RUART_PARITY_CONTROL, *PRUART_PARITY_CONTROL;
typedef enum _RUART_PARITY_TYPE_ {
RUART_ODD_PARITY = 0,
RUART_EVEN_PARITY = 1
}RUART_PARITY_TYPE, *PRUART_PARITY_TYPE;
typedef enum _RUART_STICK_PARITY_CONTROL_ {
RUART_STICK_PARITY_DISABLE = 0,
RUART_STICK_PARITY_ENABLE = 1
}RUART_STICK_PARITY_CONTROL, *PRUART_STICK_PARITY_CONTROL;
typedef enum _UART_INT_ID_ {
ModemStatus = 0,
TxFifoEmpty = 1,
ReceiverDataAvailable = 2,
ReceivLineStatus = 3,
TimeoutIndication = 6
}UART_INT_ID, *PUART_INT_ID;
typedef enum _HAL_UART_State_
{
HAL_UART_STATE_NULL = 0x00, // UART hardware not been initial yet
HAL_UART_STATE_READY = 0x10, // UART is initialed, ready to use
HAL_UART_STATE_BUSY = 0x20, // UART hardware is busy on configuration
HAL_UART_STATE_BUSY_TX = 0x21, // UART is buzy on TX
HAL_UART_STATE_BUSY_RX = 0x22, // UART is busy on RX
HAL_UART_STATE_BUSY_TX_RX = 0x23, // UART is busy on TX an RX
HAL_UART_STATE_TIMEOUT = 0x30, // Transfer timeout
HAL_UART_STATE_ERROR = 0x40 // UART Error
}HAL_UART_State, *PHAL_UART_State;
typedef enum _HAL_UART_Status_
{
HAL_UART_STATUS_OK = 0x00, // Transfer OK
HAL_UART_STATUS_TIMEOUT = 0x01, // Transfer Timeout
HAL_UART_STATUS_ERR_OVERRUN = 0x02, // RX Over run
HAL_UART_STATUS_ERR_PARITY = 0x04, // Parity error
HAL_UART_STATUS_ERR_FRAM = 0x08, // Framing Error
HAL_UART_STATUS_ERR_BREAK = 0x10, // Break Interrupt
HAL_UART_STATUS_ERR_PARA = 0x20, // Parameter error
HAL_UART_STATUS_ERR_RXFIFO = 0x80, // RX FIFO error
}HAL_UART_Status, *PHAL_UART_Status;
u32
HalRuartGetDebugValueRtl8195a(
IN VOID* Data,
IN u32 DbgSel
);
#if 0
u32
FindElementIndex(
u32 Element,
u32* Array
);
#endif
VOID
RuartResetRxFifoRtl8195a(
IN u8 UartIndex
);
#if 0
VOID
RuartBusDomainEnableRtl8195a(
IN u8 UartIndex
);
#endif
HAL_Status
HalRuartResetRxFifoRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartInitRtl8195a(
IN VOID *Data
);
VOID
HalRuartDeInitRtl8195a(
IN VOID *Data ///< RUART Adapter
);
HAL_Status
HalRuartPutCRtl8195a(
IN VOID *Data,
IN u8 TxData
);
u32
HalRuartSendRtl8195a(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length,
IN u32 Timeout
);
HAL_Status
HalRuartIntSendRtl8195a(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
HAL_Status
HalRuartDmaSendRtl8195a(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
HAL_Status
HalRuartStopSendRtl8195a(
IN VOID *Data // PHAL_RUART_ADAPTER
);
HAL_Status
HalRuartGetCRtl8195a(
IN VOID *Data,
OUT u8 *pRxByte
);
u32
HalRuartRecvRtl8195a(
IN VOID *Data,
IN u8 *pRxData,
IN u32 Length,
IN u32 Timeout
);
HAL_Status
HalRuartIntRecvRtl8195a(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
HAL_Status
HalRuartDmaRecvRtl8195a(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
HAL_Status
HalRuartStopRecvRtl8195a(
IN VOID *Data // PHAL_RUART_ADAPTER
);
u8
HalRuartGetIMRRtl8195a(
IN VOID *Data
);
_LONG_CALL_ VOID
HalRuartSetIMRRtl8195a(
IN VOID *Data
);
VOID
HalRuartDmaInitRtl8195a(
IN VOID *Data
);
VOID
HalRuartRTSCtrlRtl8195a(
IN VOID *Data,
IN BOOLEAN RtsCtrl
);
VOID
HalRuartRegIrqRtl8195a(
IN VOID *Data
);
VOID
HalRuartIntEnableRtl8195a(
IN VOID *Data
);
VOID
HalRuartIntDisableRtl8195a(
IN VOID *Data
);
VOID
HalRuartAdapterLoadDefRtl8195a(
IN VOID *pAdp,
IN u8 UartIdx
);
VOID
HalRuartTxGdmaLoadDefRtl8195a(
IN VOID *pAdp,
IN VOID *pCfg
);
VOID
HalRuartRxGdmaLoadDefRtl8195a(
IN VOID *pAdp,
IN VOID *pCfg
);
_LONG_CALL_ HAL_Status HalRuartIntSendRtl8195aV02(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
_LONG_CALL_ HAL_Status
HalRuartIntRecvRtl8195aV02(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
_LONG_CALL_ s32
FindElementIndex_v02(
u32 Element, ///< RUART Baudrate
u32* Array, ///< Pre-defined Baudrate Array
u32 ElementNo
);
_LONG_CALL_ HAL_Status HalRuartInitRtl8195a_v02(IN VOID *Data);
// New added function 2015/04/20
HAL_Status
HalRuartResetTxFifoRtl8195a(
IN VOID *Data ///< RUART Adapter
);
HAL_Status
HalRuartSetBaudRateRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartEnableRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartDisableRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartFlowCtrlRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartDmaSendRtl8195a_Patch(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length
);
HAL_Status
RuartIsTimeout (
u32 StartCount,
u32 TimeoutCnt
);
HAL_Status
HalRuartStopRecvRtl8195a_Patch(
IN VOID *Data
);
HAL_Status
HalRuartStopSendRtl8195a_Patch(
IN VOID *Data
);
VOID
HalRuartEnterCriticalRtl8195a(
IN VOID *Data
);
VOID
HalRuartExitCriticalRtl8195a(
IN VOID *Data
);
#if CONFIG_CHIP_E_CUT
_LONG_CALL_ HAL_Status
HalRuartSetBaudRateRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartInitRtl8195a_V04(
IN VOID *Data ///< RUART Adapter
);
_LONG_CALL_ HAL_Status
HalRuartEnableRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartDisableRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartFlowCtrlRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartDmaSendRtl8195a_V04(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length
);
_LONG_CALL_ HAL_Status
HalRuartStopRecvRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartStopSendRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ VOID
HalRuartEnterCriticalRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ VOID
HalRuartExitCriticalRtl8195a_V04(
IN VOID *Data
);
#endif // #if CONFIG_CHIP_E_CUT
#endif

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sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_usb.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_USB_H_
#define _RTL8195A_USB_H_
// common command for USB
#define USB_CMD_TX_ETH 0x83 // request to TX a 802.3 packet
#define USB_CMD_TX_WLN 0x81 // request to TX a 802.11 packet
#define USB_CMD_H2C 0x11 // H2C(host to device) command packet
#define USB_CMD_MEMRD 0x51 // request to read a block of memory data
#define USB_CMD_MEMWR 0x53 // request to write a block of memory
#define USB_CMD_MEMST 0x55 // request to set a block of memory with a value
#define USB_CMD_STARTUP 0x61 // request to jump to the start up function
#define USB_CMD_RX_ETH 0x82 // indicate a RX 802.3 packet
#define USB_CMD_RX_WLN 0x80 // indicate a RX 802.11 packet
#define USB_CMD_C2H 0x10 // C2H(device to host) command packet
#define USB_CMD_MEMRD_RSP 0x50 // response to memory block read command
#define USB_CMD_MEMWR_RSP 0x52 // response to memory write command
#define USB_CMD_MEMST_RSP 0x54 // response to memory set command
#define USB_CMD_STARTED 0x60 // indicate the program has jumped to the given function
// TODO: This data structer just for test, we should modify it for the normal driver
typedef struct _USB_TX_DESC{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 rsvd0:24;
#else
u32 rsvd0:24;
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 rsvd1;
// u4Byte 3
u32 rsvd2;
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} USB_TX_DESC, *PUSB_TX_DESC;
#define SIZE_USB_TX_DESC sizeof(USB_TX_DESC)
// TODO: This data structer just for test, we should modify it for the normal driver
typedef struct _USB_RX_DESC{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:6; // bit[29:24]
u32 icv:1; // bit[30], ICV error
u32 crc:1; // bit[31], CRC error
#else
u32 crc:1; // bit[31], CRC error
u32 icv:1; // bit[30], ICV error
u32 rsvd0:6; // bit[29:24]
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 pkt_len:16; // bit[15:0], the packet size
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
#else
u32 rsvd1:24; // bit[31:8]
u32 type:8; // bit[7:0], the type of this packet
#endif
// u4Byte 2
u32 rsvd2;
// u4Byte 3
u32 rsvd3;
// u4Byte 4
u32 rsvd4;
// u4Byte 5
u32 rsvd5;
} USB_RX_DESC, *PUSB_RX_DESC;
#define SIZE_USB_RX_DESC sizeof(USB_RX_DESC)
#endif // #ifndef _RTL8195A_USB_H_

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sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_wdt.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2014 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_WDT_H_
#define _RTL8195A_WDT_H_
#define WDGTIMERELY (10*1024) //us
typedef struct _WDG_REG_ {
u16 WdgScalar;
u8 WdgEnByte;
u8 WdgClear:1;
u8 WdgCunLimit:4;
u8 Rsvd:1;
u8 WdgMode:1;
u8 WdgToISR:1;
}WDG_REG, *PWDG_REG;
typedef struct _WDG_ADAPTER_ {
WDG_REG Ctrl;
IRQ_HANDLE IrqHandle;
TIMER_ADAPTER WdgGTimer;
VOID (*UserCallback)(u32 callback_id); // User callback function
u32 callback_id;
}WDG_ADAPTER, *PWDG_ADAPTER;
typedef enum _WDG_CNTLMT_ {
CNT1H = 0,
CNT3H = 1,
CNT7H = 2,
CNTFH = 3,
CNT1FH = 4,
CNT3FH = 5,
CNT7FH = 6,
CNTFFH = 7,
CNT1FFH = 8,
CNT3FFH = 9,
CNT7FFH = 10,
CNTFFFH = 11
}WDG_CNTLMT, *PWDG_CNTLMT;
typedef enum _WDG_MODE_ {
INT_MODE = 0,
RESET_MODE = 1
}WDG_MODE, *PWDG_MODE;
extern VOID
WDGInitial(
IN u32 Period
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGStop(
VOID
);
extern VOID
WDGRefresh(
VOID
);
extern VOID
WDGIrqCallBackReg(
IN VOID *CallBack,
IN u32 Id
);
#endif //_RTL8195A_WDT_H_