mirror of
https://github.com/eggman/ameba-gcc-sample-rtos.git
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498 lines
19 KiB
C
498 lines
19 KiB
C
/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _RTL8195A_SSI_H_
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#define _RTL8195A_SSI_H_
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#define SSI_DUMMY_DATA 0x00 // for master mode, we need to push a Dummy data to TX FIFO for read
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#define SSI_CLK_SPI1 (PLATFORM_CLOCK/2)
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#define SSI_CLK_SPI0_2 (PLATFORM_CLOCK/4)
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/* Parameters of DW_apb_ssi for RTL8195A */
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#define SSI_TX_FIFO_DEPTH 64
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#define TX_ABW 6 // 1-8, log2(SSI_TX_FIFO_DEPTH)
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#define SSI_RX_FIFO_DEPTH 64
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#define RX_ABW 6 // 1-8, log2(SSI_RX_FIFO_DEPTH)
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#define SSI0_REG_BASE 0x40042000
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#define SSI1_REG_BASE 0x40042400
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#define SSI2_REG_BASE 0x40042800
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/* Memory Map of DW_apb_ssi */
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#define REG_DW_SSI_CTRLR0 0x00 // 16 bits
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#define REG_DW_SSI_CTRLR1 0x04 // 16 bits
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#define REG_DW_SSI_SSIENR 0x08 // 1 bit
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#define REG_DW_SSI_MWCR 0x0C // 3 bits
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#define REG_DW_SSI_SER 0x10 //
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#define REG_DW_SSI_BAUDR 0x14 // 16 bits
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#define REG_DW_SSI_TXFTLR 0x18 // TX_ABW
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#define REG_DW_SSI_RXFTLR 0x1C // RX_ABW
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#define REG_DW_SSI_TXFLR 0x20 //
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#define REG_DW_SSI_RXFLR 0x24 //
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#define REG_DW_SSI_SR 0x28 // 7 bits
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#define REG_DW_SSI_IMR 0x2C //
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#define REG_DW_SSI_ISR 0x30 // 6 bits
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#define REG_DW_SSI_RISR 0x34 // 6 bits
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#define REG_DW_SSI_TXOICR 0x38 // 1 bits
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#define REG_DW_SSI_RXOICR 0x3C // 1 bits
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#define REG_DW_SSI_RXUICR 0x40 // 1 bits
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#define REG_DW_SSI_MSTICR 0x44 // 1 bits
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#define REG_DW_SSI_ICR 0x48 // 1 bits
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#define REG_DW_SSI_DMACR 0x4C // 2 bits
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#define REG_DW_SSI_DMATDLR 0x50 // TX_ABW
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#define REG_DW_SSI_DMARDLR 0x54 // RX_ABW
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#define REG_DW_SSI_IDR 0x58 // 32 bits
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#define REG_DW_SSI_COMP_VERSION 0x5C // 32 bits
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#define REG_DW_SSI_DR 0x60 // 16 bits 0x60-0xEC
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#define REG_DW_SSI_RX_SAMPLE_DLY 0xF0 // 8 bits
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#define REG_DW_SSI_RSVD_0 0xF4 // 32 bits
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#define REG_DW_SSI_RSVD_1 0xF8 // 32 bits
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#define REG_DW_SSI_RSVD_2 0xFC // 32 bits
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// CTRLR0 0x00 // 16 bits, 6.2.1
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// DFS Reset Value: 0x7
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#define BIT_SHIFT_CTRLR0_DFS 0
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#define BIT_MASK_CTRLR0_DFS 0xF
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#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS)
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#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS))
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#define BIT_SHIFT_CTRLR0_FRF 4
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#define BIT_MASK_CTRLR0_FRF 0x3
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#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF)
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#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF))
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#define BIT_SHIFT_CTRLR0_SCPH 6
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#define BIT_MASK_CTRLR0_SCPH 0x1
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#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH)
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#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH))
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#define BIT_SHIFT_CTRLR0_SCPOL 7
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#define BIT_MASK_CTRLR0_SCPOL 0x1
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#define BIT_CTRLR0_SCPOL(x)(((x) & BIT_MASK_CTRLR0_SCPOL) << BIT_SHIFT_CTRLR0_SCPOL)
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#define BIT_INVC_CTRLR0_SCPOL (~(BIT_MASK_CTRLR0_SCPOL << BIT_SHIFT_CTRLR0_SCPOL))
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#define BIT_SHIFT_CTRLR0_TMOD 8
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#define BIT_MASK_CTRLR0_TMOD 0x3
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#define BIT_CTRLR0_TMOD(x)(((x) & BIT_MASK_CTRLR0_TMOD) << BIT_SHIFT_CTRLR0_TMOD)
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#define BIT_INVC_CTRLR0_TMOD (~(BIT_MASK_CTRLR0_TMOD << BIT_SHIFT_CTRLR0_TMOD))
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#define BIT_SHIFT_CTRLR0_SLV_OE 10
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#define BIT_MASK_CTRLR0_SLV_OE 0x1
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#define BIT_CTRLR0_SLV_OE(x)(((x) & BIT_MASK_CTRLR0_SLV_OE) << BIT_SHIFT_CTRLR0_SLV_OE)
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#define BIT_INVC_CTRLR0_SLV_OE (~(BIT_MASK_CTRLR0_SLV_OE << BIT_SHIFT_CTRLR0_SLV_OE))
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#define BIT_SHIFT_CTRLR0_SRL 11
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#define BIT_MASK_CTRLR0_SRL 0x1
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#define BIT_CTRLR0_SRL(x)(((x) & BIT_MASK_CTRLR0_SRL) << BIT_SHIFT_CTRLR0_SRL)
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#define BIT_INVC_CTRLR0_SRL (~(BIT_MASK_CTRLR0_SRL << BIT_SHIFT_CTRLR0_SRL))
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#define BIT_SHIFT_CTRLR0_CFS 12
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#define BIT_MASK_CTRLR0_CFS 0xF
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#define BIT_CTRLR0_CFS(x)(((x) & BIT_MASK_CTRLR0_CFS) << BIT_SHIFT_CTRLR0_CFS)
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#define BIT_INVC_CTRLR0_CFS (~(BIT_MASK_CTRLR0_CFS << BIT_SHIFT_CTRLR0_CFS))
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// CTRLR1 0x04 // 16 bits
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#define BIT_SHIFT_CTRLR1_NDF 0
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#define BIT_MASK_CTRLR1_NDF 0xFFFF
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#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF)
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#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF))
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// SSIENR 0x08 // 1 bit
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#define BIT_SHIFT_SSIENR_SSI_EN 0
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#define BIT_MASK_SSIENR_SSI_EN 0x1
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#define BIT_SSIENR_SSI_EN(x)(((x) & BIT_MASK_SSIENR_SSI_EN) << BIT_SHIFT_SSIENR_SSI_EN)
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#define BIT_INVC_SSIENR_SSI_EN (~(BIT_MASK_SSIENR_SSI_EN << BIT_SHIFT_SSIENR_SSI_EN))
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// MWCR 0x0c // 3 bits
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#define BIT_SHIFT_MWCR_MWMOD 0
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#define BIT_MASK_MWCR_MWMOD 0x1
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#define BIT_MWCR_MWMOD(x)(((x) & BIT_MASK_MWCR_MWMOD) << BIT_SHIFT_MWCR_MWMOD)
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#define BIT_INVC_MWCR_MWMOD (~(BIT_MASK_MWCR_MWMOD << BIT_SHIFT_MWCR_MWMOD))
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#define BIT_SHIFT_MWCR_MDD 1
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#define BIT_MASK_MWCR_MDD 0x1
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#define BIT_MWCR_MDD(x)(((x) & BIT_MASK_MWCR_MDD) << BIT_SHIFT_MWCR_MDD)
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#define BIT_INVC_MWCR_MDD (~(BIT_MASK_MWCR_MDD << BIT_SHIFT_MWCR_MDD))
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#define BIT_SHIFT_MWCR_MHS 2
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#define BIT_MASK_MWCR_MHS 0x1
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#define BIT_MWCR_MHS(x)(((x) & BIT_MASK_MWCR_MHS) << BIT_SHIFT_MWCR_MHS)
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#define BIT_INVC_MWCR_MHS (~(BIT_MASK_MWCR_MHS << BIT_SHIFT_MWCR_MHS))
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// SER 0x10 // Variable Length
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#define BIT_SHIFT_SER_SER 0
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#define BIT_MASK_SER_SER 0xFF
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#define BIT_SER_SER(x)(((x) & BIT_MASK_SER_SER) << BIT_SHIFT_SER_SER)
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#define BIT_INVC_SER_SER (~(BIT_MASK_SER_SER << BIT_SHIFT_SER_SER))
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// BAUDR 0x14 // 16 bits
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#define BIT_SHIFT_BAUDR_SCKDV 0
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#define BIT_MASK_BAUDR_SCKDV 0xFFFF
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#define BIT_BAUDR_SCKDV(x)(((x) & BIT_MASK_BAUDR_SCKDV) << BIT_SHIFT_BAUDR_SCKDV)
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#define BIT_INVC_BAUDR_SCKDV (~(BIT_MASK_BAUDR_SCKDV << BIT_SHIFT_BAUDR_SCKDV))
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// TXFLTR 0x18 // Variable Length
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#define BIT_SHIFT_TXFTLR_TFT 0
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#define BIT_MASK_TXFTLR_TFT 0x3F // (TX_ABW-1):0
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#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT)
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#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT))
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// RXFLTR 0x1c // Variable Length
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#define BIT_SHIFT_RXFTLR_RFT 0
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#define BIT_MASK_RXFTLR_RFT 0x3F // (RX_ABW-1):0
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#define BIT_RXFTLR_RFT(x)(((x) & BIT_MASK_RXFTLR_RFT) << BIT_SHIFT_RXFTLR_RFT)
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#define BIT_INVC_RXFTLR_RFT (~(BIT_MASK_RXFTLR_RFT << BIT_SHIFT_RXFTLR_RFT))
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// TXFLR 0x20 // see [READ ONLY]
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#define BIT_MASK_TXFLR_TXTFL 0x7F // (TX_ABW):0
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// RXFLR 0x24 // see [READ ONLY]
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#define BIT_MASK_RXFLR_RXTFL 0x7F // (RX_ABW):0
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// SR 0x28 // 7 bits [READ ONLY]
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#define BIT_SR_BUSY BIT0
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#define BIT_SR_TFNF BIT1
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#define BIT_SR_TFE BIT2
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#define BIT_SR_RFNE BIT3
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#define BIT_SR_RFF BIT4
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#define BIT_SR_TXE BIT5
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#define BIT_SR_DCOL BIT6
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// IMR 0x2c // see
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#define BIT_SHIFT_IMR_TXEIM 0
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#define BIT_MASK_IMR_TXEIM 0x1
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// #define BIT_IMR_TXEIM(x)(((x) & BIT_MASK_IMR_TXEIM) << BIT_SHIFT_IMR_TXEIM)
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#define BIT_INVC_IMR_TXEIM (~(BIT_MASK_IMR_TXEIM << BIT_SHIFT_IMR_TXEIM))
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#define BIT_SHIFT_IMR_TXOIM 1
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#define BIT_MASK_IMR_TXOIM 0x1
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// #define BIT_IMR_TXOIM(x)(((x) & BIT_MASK_IMR_TXOIM) << BIT_SHIFT_IMR_TXOIM)
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#define BIT_INVC_IMR_TXOIM (~(BIT_MASK_IMR_TXOIM << BIT_SHIFT_IMR_TXOIM))
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#define BIT_SHIFT_IMR_RXUIM 2
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#define BIT_MASK_IMR_RXUIM 0x1
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// #define BIT_IMR_RXUIM(x)(((x) & BIT_MASK_IMR_RXUIM) << BIT_SHIFT_IMR_RXUIM)
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#define BIT_INVC_IMR_RXUIM (~(BIT_MASK_IMR_RXUIM << BIT_SHIFT_IMR_RXUIM))
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#define BIT_SHIFT_IMR_RXOIM 3
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#define BIT_MASK_IMR_RXOIM 0x1
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// #define BIT_IMR_RXOIM(x)(((x) & BIT_MASK_IMR_RXOIM) << BIT_SHIFT_IMR_RXOIM)
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#define BIT_INVC_IMR_RXOIM (~(BIT_MASK_IMR_RXOIM << BIT_SHIFT_IMR_RXOIM))
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#define BIT_SHIFT_IMR_RXFIM 4
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#define BIT_MASK_IMR_RXFIM 0x1
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// #define BIT_IMR_RXFIM(x)(((x) & BIT_MASK_IMR_RXFIM) << BIT_SHIFT_IMR_RXFIM)
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#define BIT_INVC_IMR_RXFIM (~(BIT_MASK_IMR_RXFIM << BIT_SHIFT_IMR_RXFIM))
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#define BIT_SHIFT_IMR_MSTIM 5
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#define BIT_MASK_IMR_MSTIM 0x1
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// #define BIT_IMR_MSTIM(x)(((x) & BIT_MASK_IMR_MSTIM) << BIT_SHIFT_IMR_MSTIM)
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#define BIT_INVC_IMR_MSTIM (~(BIT_MASK_IMR_MSTIM << BIT_SHIFT_IMR_MSTIM))
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#define BIT_IMR_TXEIM BIT0
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#define BIT_IMR_TXOIM BIT1
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#define BIT_IMR_RXUIM BIT2
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#define BIT_IMR_RXOIM BIT3
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#define BIT_IMR_RXFIM BIT4
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#define BIT_IMR_MSTIM BIT5
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// ISR 0x30 // 6 bits [READ ONLY]
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#define BIT_ISR_TXEIS BIT0
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#define BIT_ISR_TXOIS BIT1
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#define BIT_ISR_RXUIS BIT2
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#define BIT_ISR_RXOIS BIT3
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#define BIT_ISR_RXFIS BIT4
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#define BIT_ISR_MSTIS BIT5
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// RISR 0x34 // 6 bits [READ ONLY]
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#define BIT_RISR_TXEIR BIT0
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#define BIT_RISR_TXOIR BIT1
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#define BIT_RISR_RXUIR BIT2
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#define BIT_RISR_RXOIR BIT3
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#define BIT_RISR_RXFIR BIT4
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#define BIT_RISR_MSTIR BIT5
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// TXOICR 0x38 // 1 bits [READ ONLY]
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// RXOICR 0x3c // 1 bits [READ ONLY]
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// RXUICR 0x40 // 1 bits [READ ONLY]
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// MSTICR 0x44 // 1 bits [READ ONLY]
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// ICR 0x48 // 1 bits [READ ONLY]
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// DMACR 0x4c // 2 bits
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#define BIT_SHIFT_DMACR_RDMAE 0
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#define BIT_MASK_DMACR_RDMAE 0x1
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#define BIT_DMACR_RDMAE(x)(((x) & BIT_MASK_DMACR_RDMAE) << BIT_SHIFT_DMACR_RDMAE)
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#define BIT_INVC_DMACR_RDMAE (~(BIT_MASK_DMACR_RDMAE << BIT_SHIFT_DMACR_RDMAE))
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#define BIT_SHIFT_DMACR_TDMAE 1
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#define BIT_MASK_DMACR_TDMAE 0x1
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#define BIT_DMACR_TDMAE(x)(((x) & BIT_MASK_DMACR_TDMAE) << BIT_SHIFT_DMACR_TDMAE)
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#define BIT_INVC_DMACR_TDMAE (~(BIT_MASK_DMACR_TDMAE << BIT_SHIFT_DMACR_TDMAE))
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// DMATDLR 0x50
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#define BIT_SHIFT_DMATDLR_DMATDL 0
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#define BIT_MASK_DMATDLR_DMATDL 0x3F // (TX_ABW-1):0
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#define BIT_DMATDLR_DMATDL(x)(((x) & BIT_MASK_DMATDLR_DMATDL) << BIT_SHIFT_DMATDLR_DMATDL)
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#define BIT_INVC_DMATDLR_DMATDL (~(BIT_MASK_DMATDLR_DMATDL << BIT_SHIFT_DMATDLR_DMATDL))
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// DMARDLR 0x54
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#define BIT_SHIFT_DMARDLR_DMARDL 0
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#define BIT_MASK_DMARDLR_DMARDL 0x3F // (RX_ABW-1):0
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#define BIT_DMARDLR_DMARDL(x)(((x) & BIT_MASK_DMARDLR_DMARDL) << BIT_SHIFT_DMARDLR_DMARDL)
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#define BIT_INVC_DMARDLR_DMARDL (~(BIT_MASK_DMARDLR_DMARDL << BIT_SHIFT_DMARDLR_DMARDL))
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// IDR 0x58 // 32 bits [READ ONLY]
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// COMP_VERSION 0x5c // 32 bits [READ ONLY]
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// DR 0x60 // 16 bits 0x60-0xEC
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#define BIT_SHIFT_DR_DR 0
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#define BIT_MASK_DR_DR 0xFFFF
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#define BIT_DR_DR(x)(((x) & BIT_MASK_DR_DR) << BIT_SHIFT_DR_DR)
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#define BIT_INVC_DR_DR (~(BIT_MASK_DR_DR << BIT_SHIFT_DR_DR))
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// RX_SAMPLE_DLY 0xF0 // 8 bits
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#define BIT_SHIFT_RX_SAMPLE_DLY_RSD 0
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#define BIT_MASK_RX_SAMPLE_DLY_RSD 0xFFFF
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#define BIT_RX_SAMPLE_DLY_RSD(x)(((x) & BIT_MASK_RX_SAMPLE_DLY_RSD) << BIT_SHIFT_RX_SAMPLE_DLY_RSD)
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#define BIT_INVC_RX_SAMPLE_DLY_RSD (~(BIT_MASK_RX_SAMPLE_DLY_RSD << BIT_SHIFT_RX_SAMPLE_DLY_RSD))
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// RSVD_0 0xF4 // 32 bits
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// RSVD_1 0xF8 // 32 bits
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// RSVD_2 0xFC // 32 bits
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// SSI0 Pinmux
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#define BIT_SHIFT_SSI0_PIN_EN 0
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#define BIT_MASK_SSI0_PIN_EN 0x1
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#define BIT_SSI0_PIN_EN(x)(((x) & BIT_MASK_SSI0_PIN_EN) << BIT_SHIFT_SSI0_PIN_EN)
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#define BIT_INVC_SSI0_PIN_EN (~(BIT_MASK_SSI0_PIN_EN << BIT_SHIFT_SSI0_PIN_EN))
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#define BIT_SHIFT_SSI0_PIN_SEL 1
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#define BIT_MASK_SSI0_PIN_SEL 0x7
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#define BIT_SSI0_PIN_SEL(x)(((x) & BIT_MASK_SSI0_PIN_SEL) << BIT_SHIFT_SSI0_PIN_SEL)
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#define BIT_INVC_SSI0_PIN_SEL (~(BIT_MASK_SSI0_PIN_SEL << BIT_SHIFT_SSI0_PIN_SEL))
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// SSI1 Pinmux
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#define BIT_SHIFT_SSI1_PIN_EN 4
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#define BIT_MASK_SSI1_PIN_EN 0x1
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#define BIT_SSI1_PIN_EN(x)(((x) & BIT_MASK_SSI1_PIN_EN) << BIT_SHIFT_SSI1_PIN_EN)
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#define BIT_INVC_SSI1_PIN_EN (~(BIT_MASK_SSI1_PIN_EN << BIT_SHIFT_SSI1_PIN_EN))
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#define BIT_SHIFT_SSI1_PIN_SEL 5
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#define BIT_MASK_SSI1_PIN_SEL 0x7
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#define BIT_SSI1_PIN_SEL(x)(((x) & BIT_MASK_SSI1_PIN_SEL) << BIT_SHIFT_SSI1_PIN_SEL)
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#define BIT_INVC_SSI1_PIN_SEL (~(BIT_MASK_SSI1_PIN_SEL << BIT_SHIFT_SSI1_PIN_SEL))
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// SSI2 Pinmux
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#define BIT_SHIFT_SSI2_PIN_EN 8
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#define BIT_MASK_SSI2_PIN_EN 0x1
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#define BIT_SSI2_PIN_EN(x)(((x) & BIT_MASK_SSI2_PIN_EN) << BIT_SHIFT_SSI2_PIN_EN)
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#define BIT_INVC_SSI2_PIN_EN (~(BIT_MASK_SSI2_PIN_EN << BIT_SHIFT_SSI2_PIN_EN))
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#define BIT_SHIFT_SSI2_PIN_SEL 9
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#define BIT_MASK_SSI2_PIN_SEL 0x7
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#define BIT_SSI2_PIN_SEL(x)(((x) & BIT_MASK_SSI2_PIN_SEL) << BIT_SHIFT_SSI2_PIN_SEL)
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#define BIT_INVC_SSI2_PIN_SEL (~(BIT_MASK_SSI2_PIN_SEL << BIT_SHIFT_SSI2_PIN_SEL))
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// SSI0 Multiple Chip Selection (Pinmux Select is controlled by BIT_SSI0_PIN_SEL)
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#define BIT_SHIFT_SSI0_MULTI_CS_EN 28
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#define BIT_MASK_SSI0_MULTI_CS_EN 0x1
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#define BIT_SSI0_MULTI_CS_EN(x)(((x) & BIT_MASK_SSI0_MULTI_CS_EN) << BIT_SHIFT_SSI0_MULTI_CS_EN)
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#define BIT_INVC_SSI0_MULTI_CS_EN (~(BIT_MASK_SSI0_MULTI_CS_EN << BIT_SHIFT_SSI0_MULTI_CS_EN))
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#define HAL_SSI_READ32(SsiIndex, addr) \
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HAL_READ32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
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#define HAL_SSI_WRITE32(SsiIndex, addr, value) \
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HAL_WRITE32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
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#define HAL_SSI_READ16(SsiIndex, addr) \
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HAL_READ16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
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#define HAL_SSI_WRITE16(SsiIndex, addr, value) \
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HAL_WRITE16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
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#define HAL_SSI_READ8(SsiIndex, addr) \
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HAL_READ8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
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#define HAL_SSI_WRITE8(SsiIndex, addr, value) \
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HAL_WRITE8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
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// SSI Pinmux Select
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typedef enum _SSI0_PINMUX_SELECT_ {
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SSI0_MUX_TO_GPIOE = S0,
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SSI0_MUX_TO_GPIOC = S1
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}SSI0_PINMUX_SELECT, *PSSI0_PINMUX_SELECT;
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typedef enum _SSI1_PINMUX_SELECT_ {
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SSI1_MUX_TO_GPIOA = S0,
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SSI1_MUX_TO_GPIOB = S1,
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SSI1_MUX_TO_GPIOD = S2
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}SSI1_PINMUX_SELECT, *PSSI1_PINMUX_SELECT;
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typedef enum _SSI2_PINMUX_SELECT_ {
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SSI2_MUX_TO_GPIOG = S0,
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SSI2_MUX_TO_GPIOE = S1,
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SSI2_MUX_TO_GPIOD = S2
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}SSI2_PINMUX_SELECT, *PSSI2_PINMUX_SELECT;
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typedef enum _SSI0_MULTI_CS_PINMUX_SELECT_ {
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SSI0_CS_MUX_TO_GPIOE = S0,
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SSI0_CS_MUX_TO_GPIOC = S1
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}SSI0_MULTI_CS_PINMUX_SELECT, *PSSI0_MULTI_CS_PINMUX_SELECT;
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typedef enum _SSI_CTRLR0_TMOD_ {
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TMOD_TR = 0,
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TMOD_TO = 1,
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TMOD_RO = 2,
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TMOD_EEPROM_R = 3
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}SSI_CTRLR0_TMOD, *PSSI_CTRLR0_TMOD;
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typedef enum _SSI_CTRLR0_SCPOL_ {
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SCPOL_INACTIVE_IS_LOW = 0,
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SCPOL_INACTIVE_IS_HIGH = 1
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}SSI_CTRLR0_SCPOL, *PSSI_CTRLR0_SCPOL;
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typedef enum _SSI_CTRLR0_SCPH_ {
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SCPH_TOGGLES_IN_MIDDLE = 0,
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SCPH_TOGGLES_AT_START = 1
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}SSI_CTRLR0_SCPH, *PSSI_CTRLR0_SCPH;
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typedef enum _SSI_CTRLR0_DFS_ {
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DFS_4_BITS = 3,
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DFS_5_BITS = 4,
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DFS_6_BITS = 5,
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DFS_7_BITS = 6,
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DFS_8_BITS = 7,
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DFS_9_BITS = 8,
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DFS_10_BITS = 9,
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DFS_11_BITS = 10,
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DFS_12_BITS = 11,
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DFS_13_BITS = 12,
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DFS_14_BITS = 13,
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DFS_15_BITS = 14,
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DFS_16_BITS = 15,
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}SSI_CTRLR0_DFS, *PSSI_CTRLR0_DFS;
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typedef enum _SSI_CTRLR0_CFS_ {
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CFS_1_BIT = 0,
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CFS_2_BITS = 1,
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CFS_3_BITS = 2,
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CFS_4_BITS = 3,
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CFS_5_BITS = 4,
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CFS_6_BITS = 5,
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CFS_7_BITS = 6,
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CFS_8_BITS = 7,
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CFS_9_BITS = 8,
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CFS_10_BITS = 9,
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CFS_11_BITS = 10,
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CFS_12_BITS = 11,
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CFS_13_BITS = 12,
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CFS_14_BITS = 13,
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CFS_15_BITS = 14,
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CFS_16_BITS = 15
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}SSI_CTRLR0_CFS, *PSSI_CTRLR0_CFS;
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typedef enum _SSI_CTRLR0_SLV_OE_ {
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SLV_TXD_ENABLE = 0,
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SLV_TXD_DISABLE = 1
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}SSI_CTRLR0_SLV_OE, *PSSI_CTRLR0_SLV_OE;
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typedef enum _SSI_ROLE_SELECT_ {
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SSI_SLAVE = 0,
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SSI_MASTER = 1
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}SSI_ROLE_SELECT, *PSSI_ROLE_SELECT;
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typedef enum _SSI_FRAME_FORMAT_ {
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FRF_MOTOROLA_SPI = 0,
|
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FRF_TI_SSP = 1,
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FRF_NS_MICROWIRE = 2,
|
|
FRF_RSVD = 3
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}SSI_FRAME_FORMAT, *PSSI_FRAME_FORMAT;
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|
|
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typedef enum _SSI_DMACR_ENABLE_ {
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SSI_NODMA = 0,
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SSI_RXDMA_ENABLE = 1,
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SSI_TXDMA_ENABLE = 2,
|
|
SSI_TRDMA_ENABLE = 3
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}SSI_DMACR_ENABLE, *PSSI_DMACR_ENABLE;
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|
|
|
typedef enum _SSI_MWCR_HANDSHAKE_ {
|
|
MW_HANDSHAKE_DISABLE = 0,
|
|
MW_HANDSHAKE_ENABLE = 1
|
|
}SSI_MWCR_HANDSHAKE, *PSSI_MWCR_HANDSHAKE;
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|
|
|
typedef enum _SSI_MWCR_DIRECTION_ {
|
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MW_DIRECTION_SLAVE_TO_MASTER = 0,
|
|
MW_DIRECTION_MASTER_TO_SLAVE = 1
|
|
}SSI_MWCR_DIRECTION, *PSSI_MWCR_DIRECTION;
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|
|
|
typedef enum _SSI_MWCR_TMOD_ {
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|
MW_TMOD_NONSEQUENTIAL = 0,
|
|
MW_TMOD_SEQUENTIAL = 1
|
|
}SSI_MWCR_TMOD, *PSSI_MWCR_TMOD;
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|
|
|
typedef enum _SSI_DATA_TRANSFER_MECHANISM_ {
|
|
SSI_DTM_BASIC,
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|
SSI_DTM_INTERRUPT,
|
|
SSI_DTM_DMA
|
|
}SSI_DATA_TRANSFER_MECHANISM, *PSSI_DATA_TRANSFER_MECHANISM;
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|
|
|
|
|
_LONG_CALL_ HAL_Status HalSsiPinmuxEnableRtl8195a(VOID *Adaptor);
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_LONG_CALL_ HAL_Status HalSsiEnableRtl8195a(VOID *Adaptor);
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_LONG_CALL_ HAL_Status HalSsiDisableRtl8195a(VOID *Adaptor);
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_LONG_CALL_ HAL_Status HalSsiInitRtl8195a(VOID *Adaptor);
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_LONG_CALL_ HAL_Status HalSsiSetSclkPolarityRtl8195a(VOID *Adaptor);
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_LONG_CALL_ HAL_Status HalSsiSetSclkPhaseRtl8195a(VOID *Adaptor);
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_LONG_CALL_ HAL_Status HalSsiWriteRtl8195a(VOID *Adaptor, u32 value);
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_LONG_CALL_ HAL_Status HalSsiLoadSettingRtl8195a(VOID *Adaptor, VOID *Setting);
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_LONG_CALL_ HAL_Status HalSsiSetInterruptMaskRtl8195a(VOID *Adaptor);
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|
_LONG_CALL_ HAL_Status HalSsiSetDeviceRoleRtl8195a(VOID *Adaptor, u32 Role);
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_LONG_CALL_ HAL_Status HalSsiInterruptEnableRtl8195a(VOID *Adaptor);
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|
_LONG_CALL_ HAL_Status HalSsiInterruptDisableRtl8195a(VOID *Adaptor);
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|
_LONG_CALL_ HAL_Status HalSsiReadInterruptRtl8195a(VOID *Adaptor, VOID *RxData, u32 Length);
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_LONG_CALL_ HAL_Status HalSsiSetRxFifoThresholdLevelRtl8195a(VOID *Adaptor);
|
|
_LONG_CALL_ HAL_Status HalSsiSetTxFifoThresholdLevelRtl8195a(VOID *Adaptor);
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|
_LONG_CALL_ HAL_Status HalSsiWriteInterruptRtl8195a(VOID *Adaptor, VOID *TxData, u32 Length);
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|
_LONG_CALL_ HAL_Status HalSsiSetSlaveEnableRegisterRtl8195a(VOID *Adaptor, u32 SlaveIndex);
|
|
_LONG_CALL_ u32 HalSsiBusyRtl8195a(VOID *Adaptor);
|
|
_LONG_CALL_ u32 HalSsiWriteableRtl8195a(VOID *Adaptor);
|
|
_LONG_CALL_ u32 HalSsiReadableRtl8195a(VOID *Adaptor);
|
|
_LONG_CALL_ u32 HalSsiGetInterruptMaskRtl8195a(VOID *Adaptor);
|
|
_LONG_CALL_ u32 HalSsiGetRxFifoLevelRtl8195a(VOID *Adaptor);
|
|
_LONG_CALL_ u32 HalSsiGetTxFifoLevelRtl8195a(VOID *Adaptor);
|
|
_LONG_CALL_ u32 HalSsiGetStatusRtl8195a(VOID *Adaptor);
|
|
_LONG_CALL_ u32 HalSsiGetInterruptStatusRtl8195a(VOID *Adaptor);
|
|
_LONG_CALL_ u32 HalSsiReadRtl8195a(VOID *Adaptor);
|
|
_LONG_CALL_ u32 HalSsiGetRawInterruptStatusRtl8195a(VOID *Adaptor);
|
|
_LONG_CALL_ u32 HalSsiGetSlaveEnableRegisterRtl8195a(VOID *Adaptor);
|
|
|
|
_LONG_CALL_ VOID _SsiReadInterrupt(VOID *Adaptor);
|
|
_LONG_CALL_ VOID _SsiWriteInterrupt(VOID *Adaptor);
|
|
_LONG_CALL_ u32 _SsiIrqHandle(VOID *Adaptor);
|
|
|
|
// ROM code patch
|
|
VOID _SsiReadInterruptRtl8195a(VOID *Adapter);
|
|
VOID _SsiWriteInterruptRtl8195a(VOID *Adapter);
|
|
HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor);
|
|
HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor);
|
|
HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor);
|
|
HAL_Status HalSsiDeInitRtl8195a(VOID * Adapter);
|
|
HAL_Status HalSsiClockOffRtl8195a(VOID * Adapter);
|
|
HAL_Status HalSsiClockOnRtl8195a(VOID * Adapter);
|
|
VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate);
|
|
HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length);
|
|
HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
|
|
#ifdef CONFIG_GDMA_EN
|
|
VOID HalSsiTxGdmaLoadDefRtl8195a(VOID *Adapter);
|
|
VOID HalSsiRxGdmaLoadDefRtl8195a(VOID *Adapter);
|
|
VOID HalSsiDmaInitRtl8195a(VOID *Adapter);
|
|
HAL_Status HalSsiDmaSendRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
|
|
HAL_Status HalSsiDmaRecvRtl8195a(VOID *Adapter, u8 *pRxData, u32 Length);
|
|
#endif // end of "#ifdef CONFIG_GDMA_EN"
|
|
|
|
#endif
|