add sdk header file

sdk/component/soc/realtek/8195a/cmsis/core_cmFunc.h

@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */

sdk/component/soc/realtek/8195a/cmsis/core_cmInstr.h

@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

sdk/component/soc/realtek/8195a/cmsis/device/diag.h

@@ -0,0 +1,843 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _DIAG_H_
+#define _DIAG_H_
+
+#include "platform_autoconf.h"
+#include "basic_types.h"
+
+#include <stddef.h> /* for size_t */
+
+extern u32 ConfigDebugErr;
+extern u32 ConfigDebugInfo;
+extern u32 ConfigDebugWarn;
+
+extern u32 CfgSysDebugErr;
+extern u32 CfgSysDebugInfo;
+extern u32 CfgSysDebugWarn;
+
+#define DBG_ERR_MSG_ON(x)       (ConfigDebugErr |= (x))
+#define DBG_WARN_MSG_ON(x)      (ConfigDebugWarn |= (x))
+#define DBG_INFO_MSG_ON(x)      (ConfigDebugInfo |= (x))
+
+#define DBG_ERR_MSG_OFF(x)      (ConfigDebugErr &= ~(x))
+#define DBG_WARN_MSG_OFF(x)     (ConfigDebugWarn &= ~(x))
+#define DBG_INFO_MSG_OFF(x)     (ConfigDebugInfo &= ~(x))
+
+// Define debug group
+#define	_DBG_BOOT_          	0x00000001
+#define	_DBG_GDMA_          	0x00000002
+#define	_DBG_GPIO_			    0x00000004
+#define	_DBG_TIMER_         	0x00000008
+#define	_DBG_I2C_           	0x00000010
+#define	_DBG_I2S_           	0x00000020
+#define	_DBG_MII_           	0x00000040
+#define	_DBG_NFC_           	0x00000080
+#define	_DBG_PCM_           	0x00000100
+#define	_DBG_PWM_           	0x00000200
+#define	_DBG_SDIO_          	0x00000400
+#define	_DBG_SSI_           	0x00000800
+#define	_DBG_SPI_FLASH_         0x00001000
+#define	_DBG_SDR_           	0x00002000
+#define	_DBG_UART_          	0x00004000
+#define	_DBG_USB_OTG_           0x00008000
+#define	_DBG_USB_CORE_          0x00010000
+#define	_DBG_CRYPTO_        	0x00020000
+#define	_DBG_ADC_           	0x00040000
+#define	_DBG_DAC_               0x00080000
+
+#define _DBG_MISC_              0x40000000
+#define	_DBG_FAULT_        	    0x80000000
+
+typedef enum _SYSTEM_DBG_DEFINE_ {
+    _SYSDBG_MISC_       = 1<<0,
+    _SYSDBG_MAILBOX_    = 1<<1,
+    _SYSDBG_TIMER_      = 1<<2
+
+} SYSTEM_DBG;
+
+extern
+_LONG_CALL_ROM_ u32
+DiagPrintf(
+    IN  const char *fmt, ...
+);
+
+u32
+DiagSPrintf(
+    IN  u8 *buf,
+    IN  const char *fmt, ...
+);
+
+int
+prvDiagPrintf(
+    IN  const char *fmt, ...
+);
+
+int
+prvDiagSPrintf(
+    IN char *buf,
+    IN  const char *fmt, ...
+);
+
+
+#define _DbgDump  DiagPrintf
+
+#define DRIVER_PREFIX	"RTL8195A[Driver]: "
+#define HAL_PREFIX      "RTL8195A[HAL]: "
+#define DMA_PREFIX      "RTL8195A[DMA]: "
+#define SDIO_PREFIX     "RTL8195A[SDIO]"
+#define MBOX_PREFIX		"[OS-MBOX]"
+#define TIMER_PREFIX	"[OS-TMR]"
+
+#define BOOT_ERR_PREFIX         "[BOOT Err]"
+#define BOOT_WARN_PREFIX        "[BOOT Wrn]"
+#define BOOT_INFO_PREFIX        "[BOOT Inf]"
+
+#define GDMA_ERR_PREFIX         "[GDMA Err]"
+#define GDMA_WARN_PREFIX        "[GDMA Wrn]"
+#define GDMA_INFO_PREFIX        "[GDMA Inf]"
+
+#define GPIO_ERR_PREFIX         "[GPIO Err]"
+#define GPIO_WARN_PREFIX        "[GPIO Wrn]"
+#define GPIO_INFO_PREFIX        "[GPIO Inf]"
+
+#define TIMER_ERR_PREFIX        "[TIMR Err]"
+#define TIMER_WARN_PREFIX       "[TIMR Wrn]"
+#define TIMER_INFO_PREFIX       "[TIMR Inf]"
+
+#define I2C_ERR_PREFIX          "[I2C  Err]"
+#define I2C_WARN_PREFIX         "[I2C  Wrn]"
+#define I2C_INFO_PREFIX         "[I2C  Inf]"
+
+#define I2S_ERR_PREFIX          "[I2S  Err]"
+#define I2S_WARN_PREFIX         "[I2S  Wrn]"
+#define I2S_INFO_PREFIX         "[I2S  Inf]"
+
+#define MII_ERR_PREFIX          "[MII  Err]"
+#define MII_WARN_PREFIX         "[MII  Wrn]"
+#define MII_INFO_PREFIX         "[MII  Inf]"
+
+#define NFC_ERR_PREFIX          "[NFC  Err]"
+#define NFC_WARN_PREFIX         "[NFC  Wrn]"
+#define NFC_INFO_PREFIX         "[NFC  Inf]"
+
+#define PCM_ERR_PREFIX          "[PCM  Err]"
+#define PCM_WARN_PREFIX         "[PCM  Wrn]"
+#define PCM_INFO_PREFIX         "[PCM  Inf]"
+
+#define PWM_ERR_PREFIX          "[PWM  Err]"
+#define PWM_WARN_PREFIX         "[PWM  Wrn]"
+#define PWM_INFO_PREFIX         "[PWM  Inf]"
+
+#define SSI_ERR_PREFIX          "[SSI  Err]"
+#define SSI_WARN_PREFIX         "[SSI  Wrn]"
+#define SSI_INFO_PREFIX         "[SSI  Inf]"
+
+#define SDIO_ERR_PREFIX         "[SDIO Err]"
+#define SDIO_WARN_PREFIX        "[SDIO Wrn]"
+#define SDIO_INFO_PREFIX        "[SDIO Inf]"
+
+#define SPIF_ERR_PREFIX         "[SPIF Err]"
+#define SPIF_WARN_PREFIX        "[SPIF Wrn]"
+#define SPIF_INFO_PREFIX        "[SPIF Inf]"
+
+#define SDR_ERR_PREFIX          "[SDR  Err]"
+#define SDR_WARN_PREFIX         "[SDR  Wrn]"
+#define SDR_INFO_PREFIX         "[SDR  Inf]"
+
+#define UART_ERR_PREFIX         "[UART Err]"
+#define UART_WARN_PREFIX        "[UART Wrn]"
+#define UART_INFO_PREFIX        "[UART Inf]"
+
+#define USB_ERR_PREFIX          "[USB  Err]"
+#define USB_WARN_PREFIX         "[USB  Wrn]"
+#define USB_INFO_PREFIX         "[USB  Inf]"
+
+#define IPSEC_ERR_PREFIX        "[CRYP Err]"
+#define IPSEC_WARN_PREFIX       "[CRYP Wrn]"
+#define IPSEC_INFO_PREFIX       "[CRYP Inf]"
+
+#define ADC_ERR_PREFIX          "[ADC  Err]"
+#define ADC_WARN_PREFIX         "[ADC  Wrn]"
+#define ADC_INFO_PREFIX         "[ADC  Inf]"
+
+#define DAC_ERR_PREFIX          "[DAC  Err]"
+#define DAC_WARN_PREFIX         "[DAC  Wrn]"
+#define DAC_INFO_PREFIX         "[DAC  Inf]"
+
+#define MISC_ERR_PREFIX         "[MISC Err]"
+#define MISC_WARN_PREFIX        "[MISC Wrn]"
+#define MISC_INFO_PREFIX        "[MISC Inf]"
+
+#define OTG_ERR_PREFIX         "[OTG Err]"
+#define OTG_WARN_PREFIX        "[OTG Wrn]"
+#define OTG_INFO_PREFIX        "[OTG Inf]"
+
+#define OTG_PREFIX      "RTL8195A[OTG]: "
+#define OTG_PREFIX_LVL  "RTL8195A[OTG_LVL_%2x]: "
+
+//#ifdef
+#define CONFIG_DEBUG_ERROR      1
+#define CONFIG_DEBUG_WARN       1
+#define CONFIG_DEBUG_INFO       1
+
+#ifndef likely
+#define likely(x)               (x)
+#define unlikely(x)             (x)
+#endif
+
+#ifdef CONFIG_DEBUG_LOG
+
+#if CONFIG_DEBUG_ERROR      // if Build-In Debug Error Message
+
+#define DBG_BOOT_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_BOOT_)) \
+        _DbgDump("\r"BOOT_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GDMA_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_GDMA_)) \
+        _DbgDump("\r"GDMA_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GPIO_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_GPIO_)) \
+        _DbgDump("\r"GPIO_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_TIMER_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_TIMER_)) \
+        _DbgDump("\r"TIMER_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2C_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_I2C_)) \
+        _DbgDump("\r"I2C_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2S_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_I2S_)) \
+        _DbgDump("\r"I2S_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_MII_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_MII_)) \
+        _DbgDump("\r"MII_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_NFC_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_NFC_)) \
+        _DbgDump("\r"NFC_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PCM_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_PCM_)) \
+        _DbgDump("\r"PCM_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PWM_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_PWM_)) \
+        _DbgDump("\r"PWM_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SSI_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_SSI_)) \
+        _DbgDump("\r"SSI_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDIO_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_SDIO_)) \
+        _DbgDump("\r"SDIO_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SPIF_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_SPI_FLASH_)) \
+        _DbgDump("\r"SPIF_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDR_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_SDR_)) \
+        _DbgDump("\r"SDR_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_UART_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_UART_)) \
+        _DbgDump("\r"UART_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBOTG_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_USB_OTG_)) \
+        _DbgDump("\r" __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBCOR_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_USB_CORE_)) \
+        _DbgDump("\r"USB_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_CRYPTO_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_CRYPTO_)) \
+        _DbgDump("\r"IPSEC_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_ADC_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_ADC_)) \
+        _DbgDump("\r"ADC_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_DAC_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_DAC_)) \
+        _DbgDump("\r"DAC_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_MBOX_ERR(...)     do {\
+    if (likely(CfgSysDebugErr & _SYSDBG_MAILBOX_)) \
+        _DbgDump("\r"MBOX_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_TIMER_ERR(...)     do {\
+    if (likely(CfgSysDebugErr & _SYSDBG_TIMER_)) \
+        _DbgDump("\r"TIMER_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A_OTG(...)  do{\
+                if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \
+                    _DbgDump("\r"OTG_PREFIX __VA_ARGS__);\
+            }while(0)
+
+#define DBG_8195A_OTG_INFO(...)  do{\
+                if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \
+                    _DbgDump("\r"OTG_PREFIX __VA_ARGS__);\
+            }while(0)
+
+#define DBG_8195A_OTG_WARN(...)  do{\
+                if (unlikely(ConfigDebugWarn & _DBG_USB_OTG_)) \
+                    _DbgDump("\r"OTG_PREFIX __VA_ARGS__);\
+            }while(0)
+
+#define DBG_8195A_OTG_ERR(...)  do{\
+                if (unlikely(ConfigDebugErr & _DBG_USB_OTG_)) \
+                    _DbgDump("\r"OTG_PREFIX __VA_ARGS__);\
+            }while(0)
+            
+#define DBG_8195A_OTG_LVL(LVL,...)  do{\
+    if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)){ \
+        _DbgDump("\r"OTG_PREFIX_LVL,LVL);\
+        _DbgDump(__VA_ARGS__);\
+    }\
+}while(0)
+
+#define DBG_MISC_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_MISC_)) \
+        _DbgDump("\r"MISC_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#else   // else of "#if CONFIG_DEBUG_ERROR"
+
+#define DBG_BOOT_ERR(...)
+#define DBG_GDMA_ERR(...)
+#define DBG_GPIO_ERR(...)
+#define DBG_TIMER_ERR(...)
+#define DBG_I2C_ERR(...)
+#define DBG_I2S_ERR(...)
+#define DBG_MII_ERR(...)
+#define DBG_NFC_ERR(...)
+#define DBG_PCM_ERR(...)
+#define DBG_PWM_ERR(...)
+#define DBG_SSI_ERR(...)
+#define DBG_SDIO_ERR(...)
+#define DBG_SPIF_ERR(...)
+#define DBG_SDR_ERR(...)
+#define DBG_UART_ERR(...)
+#define DBG_USBOTG_ERR(...)
+#define DBG_USBCOR_ERR(...)
+#define DBG_CRYPTO_ERR(...)
+#define DBG_ADC_ERR(...)
+#define DBG_DAC_ERR(...)
+
+#define MSG_MBOX_ERR(...)
+#define MSG_TIMER_ERR(...)
+#define DBG_8195A_OTG(...)
+#define DBG_8195A_OTG_LVL(LVL,...)
+#define DBG_8195A_OTG_INFO(...)
+#define DBG_8195A_OTG_WARN(...)
+#define DBG_8195A_OTG_ERR(...)
+
+
+#endif  // end of else of "#if CONFIG_DEBUG_ERROR"
+
+// =============================================================
+
+#if CONFIG_DEBUG_WARN     // if Build-In Debug Warring Message
+
+#define DBG_BOOT_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn& _DBG_BOOT_)) \
+        _DbgDump("\r"BOOT_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GDMA_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_GDMA_)) \
+        _DbgDump("\r"GDMA_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GPIO_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_GPIO_)) \
+        _DbgDump("\r"GPIO_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_TIMER_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_TIMER_)) \
+        _DbgDump("\r"TIMER_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2C_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_I2C_)) \
+        _DbgDump("\r"I2C_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2S_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_I2S_)) \
+        _DbgDump("\r"I2S_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_MII_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_MII_)) \
+        _DbgDump("\r"MII_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_NFC_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_NFC_)) \
+        _DbgDump("\r"NFC_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PCM_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_PCM_)) \
+        _DbgDump("\r"PCM_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PWM_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_PWM_)) \
+        _DbgDump("\r"PWM_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SSI_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_SSI_)) \
+        _DbgDump("\r"SSI_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDIO_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_SDIO_)) \
+        _DbgDump("\r"SDIO_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SPIF_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_SPI_FLASH_)) \
+        _DbgDump("\r"SPIF_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDR_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_SDR_)) \
+        _DbgDump("\r"SDR_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_UART_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_UART_)) \
+        _DbgDump("\r"UART_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBOTG_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_USB_OTG_)) \
+        _DbgDump("\r" __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBCOR_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_USB_CORE_)) \
+        _DbgDump("\r"USB_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_CRYPTO_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_CRYPTO_)) \
+        _DbgDump("\r"IPSEC_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_ADC_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_ADC_)) \
+        _DbgDump("\r"ADC_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_DAC_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_DAC_)) \
+        _DbgDump("\r"DAC_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_MBOX_WARN(...)     do {\
+    if (unlikely(CfgSysDebugWarn& _SYSDBG_MAILBOX_)) \
+        _DbgDump("\r"MBOX_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_TIMER_WARN(...)     do {\
+    if (unlikely(CfgSysDebugWarn & _SYSDBG_TIMER_)) \
+        _DbgDump("\r"TIMER_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_MISC_WARN(...)     do {\
+    if (likely(ConfigDebugWarn & _DBG_MISC_)) \
+        _DbgDump("\r"MISC_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#else   // else of "#if CONFIG_DEBUG_WARN"
+
+#define DBG_BOOT_WARN(...)
+#define DBG_GDMA_WARN(...)
+#define DBG_GPIO_WARN(...)
+#define DBG_TIMER_WARN(...)
+#define DBG_I2C_WARN(...)
+#define DBG_I2S_WARN(...)
+#define DBG_MII_WARN(...)
+#define DBG_NFC_WARN(...)
+#define DBG_PCM_WARN(...)
+#define DBG_PWM_WARN(...)
+#define DBG_SSI_WARN(...)
+#define DBG_SDIO_WARN(...)
+#define DBG_SPIF_WARN(...)
+#define DBG_SDR_WARN(...)
+#define DBG_UART_WARN(...)
+#define DBG_USBOTG_WARN(...)
+#define DBG_USBCOR_WARN(...)
+#define DBG_CRYPTO_WARN(...)
+#define DBG_ADC_WARN(...)
+#define DBG_DAC_WARN(...)
+#define DBG_MISC_WARN(...)
+
+#define MSG_MBOX_WARN(...)
+#define MSG_TIMER_WARN(...)
+
+#endif  // end of else of "#if CONFIG_DEBUG_WARN"
+
+// =============================================================
+
+#if CONFIG_DEBUG_INFO     // if Build-In Debug Information Message
+
+#define DBG_BOOT_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_BOOT_)) \
+        _DbgDump("\r"BOOT_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GDMA_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_GDMA_)) \
+        _DbgDump("\r"GDMA_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GPIO_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_GPIO_)) \
+        _DbgDump("\r"GPIO_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_TIMER_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_TIMER_)) \
+        _DbgDump("\r"TIMER_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2C_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_I2C_)) \
+        _DbgDump("\r"I2C_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2S_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_I2S_)) \
+        _DbgDump("\r"I2S_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_MII_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_MII_)) \
+        _DbgDump("\r"MII_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_NFC_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_NFC_)) \
+        _DbgDump("\r"NFC_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PCM_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_PCM_)) \
+        _DbgDump("\r"PCM_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PWM_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_PWM_)) \
+        _DbgDump("\r"PWM_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SSI_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_SSI_)) \
+        _DbgDump("\r"SSI_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDIO_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_SDIO_)) \
+        _DbgDump("\r"SDIO_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SPIF_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_SPI_FLASH_)) \
+        _DbgDump("\r"SPIF_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDR_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_SDR_)) \
+        _DbgDump("\r"SDR_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_UART_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_UART_)) \
+        _DbgDump("\r"UART_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBOTG_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \
+        _DbgDump("\r" __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBCOR_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_USB_CORE_)) \
+        _DbgDump("\r"USB_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_CRYPTO_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_CRYPTO_)) \
+        _DbgDump("\r"IPSEC_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_ADC_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_ADC_)) \
+        _DbgDump("\r"ADC_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_DAC_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_DAC_)) \
+        _DbgDump("\r"DAC_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_MBOX_INFO(...)     do {\
+    if (unlikely(CfgSysDebugInfo & _SYSDBG_MAILBOX_)) \
+        _DbgDump("\r"MBOX_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_TIMER_INFO(...)     do {\
+    if (unlikely(CfgSysDebugInfo & _SYSDBG_TIMER_)) \
+        _DbgDump("\r"TIMER_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_MISC_INFO(...)     do {\
+    if (likely(ConfigDebugInfo & _DBG_MISC_)) \
+        _DbgDump("\r"MISC_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#else   // else of "#if CONFIG_DEBUG_INFO"
+
+#define DBG_BOOT_INFO(...)
+#define DBG_GDMA_INFO(...)
+#define DBG_GPIO_INFO(...)
+#define DBG_TIMER_INFO(...)
+#define DBG_I2C_INFO(...)
+#define DBG_I2S_INFO(...)
+#define DBG_MII_INFO(...)
+#define DBG_NFC_INFO(...)
+#define DBG_PCM_INFO(...)
+#define DBG_PWM_INFO(...)
+#define DBG_SSI_INFO(...)
+#define DBG_SDIO_INFO(...)
+#define DBG_SPIF_INFO(...)
+#define DBG_SDR_INFO(...)
+#define DBG_UART_INFO(...)
+#define DBG_USBOTG_INFO(...)
+#define DBG_USBCOR_INFO(...)
+#define DBG_CRYPTO_INFO(...)
+#define DBG_ADC_INFO(...)
+#define DBG_DAC_INFO(...)
+#define DBG_MISC_INFO(...)
+
+#define MSG_MBOX_INFO(...)
+#define MSG_TIMER_INFO(...)
+
+#endif  // end of else of "#if CONFIG_DEBUG_INFO"
+
+#define DBG_8195A_DRIVER(...)     do {\
+    if (unlikely(ConfigDebugErr & (_DBG_I2S_|_DBG_PCM_|_DBG_TIMER_))) \
+        _DbgDump("\r"DRIVER_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A_HAL(...)     do {\
+    if (unlikely(ConfigDebugErr & (_DBG_SDR_|_DBG_MISC_))) \
+        _DbgDump("\r"HAL_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A_DMA(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_GDMA_)) \
+        _DbgDump("\r"DMA_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A_SDIO(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_SDIO_)) \
+        _DbgDump("\r"SDIO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_MISC_)) \
+        _DbgDump("\r" __VA_ARGS__);\
+}while(0)
+
+#define MONITOR_LOG(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_MISC_)) \
+        _DbgDump( __VA_ARGS__);\
+}while(0)
+
+#define DBG_ERROR_LOG(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_FAULT_)) \
+        _DbgDump( __VA_ARGS__);\
+}while(0)
+
+#ifdef __GNUC__
+#define DBG_ASSERT(x)     do {\
+        if (unlikely(!(x))) \
+            _DbgDump("Assertion: %s:%s, %d\n", __FILE__, __func__, __LINE__);\
+    }while(0)
+#endif
+
+#ifdef __ICCARM__
+#define DBG_ASSERT(x)     do {\
+        if (unlikely(!(x))) \
+            _DbgDump("Assertion: %s:%s, %d\n", __FILE__, __func__, __LINE__);\
+    }while(0)
+#endif
+
+#else   // else of "#if CONFIG_DEBUG_LOG"
+#define DBG_8195A_DRIVER(...)
+
+#define DBG_8195A_HAL(...)
+
+#define DBG_8195A(...)
+
+#define DBG_8195A_DMA(...)
+
+#define MONITOR_LOG(...)
+
+#define DBG_ERROR_LOG(...)
+
+#define DBG_8195A_SDIO(...)
+
+#define DBG_BOOT_ERR(...)
+#define DBG_GDMA_ERR(...)
+#define DBG_GPIO_ERR(...)
+#define DBG_TIMER_ERR(...)
+#define DBG_I2C_ERR(...)
+#define DBG_I2S_ERR(...)
+#define DBG_MII_ERR(...)
+#define DBG_NFC_ERR(...)
+#define DBG_PCM_ERR(...)
+#define DBG_PWM_ERR(...)
+#define DBG_SSI_ERR(...)
+#define DBG_SDIO_ERR(...)
+#define DBG_SPIF_ERR(...)
+#define DBG_SDR_ERR(...)
+#define DBG_UART_ERR(...)
+#define DBG_USBOTG_ERR(...)
+#define DBG_USBCOR_ERR(...)
+#define DBG_CRYPTO_ERR(...)
+#define DBG_ADC_ERR(...)
+#define DBG_DAC_ERR(...)
+#define MSG_MBOX_ERR(...)
+#define MSG_TIMER_ERR(...)
+
+#define DBG_BOOT_WARN(...)
+#define DBG_GDMA_WARN(...)
+#define DBG_GPIO_WARN(...)
+#define DBG_TIMER_WARN(...)
+#define DBG_I2C_WARN(...)
+#define DBG_I2S_WARN(...)
+#define DBG_MII_WARN(...)
+#define DBG_NFC_WARN(...)
+#define DBG_PCM_WARN(...)
+#define DBG_PWM_WARN(...)
+#define DBG_SSI_WARN(...)
+#define DBG_SDIO_WARN(...)
+#define DBG_SPIF_WARN(...)
+#define DBG_SDR_WARN(...)
+#define DBG_UART_WARN(...)
+#define DBG_USBOTG_WARN(...)
+#define DBG_USBCOR_WARN(...)
+#define DBG_CRYPTO_WARN(...)
+#define DBG_ADC_WARN(...)
+#define DBG_DAC_WARN(...)
+#define MSG_MBOX_WARN(...)
+#define MSG_TIMER_WARN(...)
+
+#define DBG_BOOT_INFO(...)
+#define DBG_GDMA_INFO(...)
+#define DBG_GPIO_INFO(...)
+#define DBG_TIMER_INFO(...)
+#define DBG_I2C_INFO(...)
+#define DBG_I2S_INFO(...)
+#define DBG_MII_INFO(...)
+#define DBG_NFC_INFO(...)
+#define DBG_PCM_INFO(...)
+#define DBG_PWM_INFO(...)
+#define DBG_SSI_INFO(...)
+#define DBG_SDIO_INFO(...)
+#define DBG_SPIF_INFO(...)
+#define DBG_SDR_INFO(...)
+#define DBG_UART_INFO(...)
+#define DBG_USBOTG_INFO(...)
+#define DBG_USBCOR_INFO(...)
+#define DBG_CRYPTO_INFO(...)
+#define DBG_ADC_INFO(...)
+#define DBG_DAC_INFO(...)
+
+#define MSG_MBOX_INFO(...)
+#define MSG_TIMER_INFO(...)
+
+#define DBG_ASSERT(x)
+
+#endif
+
+#define ANSI_COLOR_GREEN   "\x1b[32m"
+#define ANSI_COLOR_CYAN    "\x1b[36m"
+#define ANSI_COLOR_YELLOW  "\x1b[33m"
+#define ANSI_COLOR_MAGENTA "\x1b[35m"
+#define ANSI_COLOR_RED     "\x1b[31m"
+#define ANSI_COLOR_BLUE    "\x1b[34m"
+#define ANSI_COLOR_RESET   "\x1b[0m"
+
+#define IDENT_ONE_SPACE    " "
+#define IDENT_TWO_SPACE    "  "
+#define IDENT_FOUR_SPACE   "    "
+#define IDENT_SIX_SPACE    "      "
+#define IDENT_EIGHT_SPACE  "        "
+
+#ifdef CONFIG_DEBUG_LOG
+typedef enum _DBG_CFG_TYPE_ {
+	DBG_CFG_ERR=0,
+	DBG_CFG_WARN=1,
+	DBG_CFG_INFO=2
+} DBG_CFG_TYPE;
+
+typedef struct _DBG_CFG_CMD_ {
+	u8 cmd_name[16];
+	u32	cmd_type;
+} DBG_CFG_CMD, *PDBG_CFG_CMD;
+
+#endif
+
+typedef enum _CONSOLE_OP_STAGE_ {
+    ROM_STAGE = 0,
+    RAM_STAGE = 1
+}CONSOLE_OP_STAGE;
+
+#endif //_DIAG_H_

sdk/component/soc/realtek/8195a/fwlib/hal_adc.h

@@ -0,0 +1,319 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_ADC_H_
+#define _HAL_ADC_H_
+
+#include "rtl8195a.h"
+#include "rtl8195a_adc.h"
+#include "hal_gdma.h"
+
+//================ ADC Configuration  =========================
+#define ADC_INTR_OP_TYPE    1
+#define ADC_DMA_OP_TYPE     1
+
+// ADC SAL management macros
+#define SAL_ADC_USER_CB_NUM     (sizeof(SAL_ADC_USER_CB) / sizeof(PSAL_ADC_USERCB_ADPT))
+
+// ADC used module. 
+// Please set the ADC module flag to 1 to enable the related 
+#define ADC0_USED                   1
+#define ADC1_USED                   1
+#define ADC2_USED                   1
+#define ADC3_USED                   1
+
+
+//================ Debug MSG Definition =======================
+#define ADC_PREFIX      "RTL8195A[adc]: "
+#define ADC_PREFIX_LVL  "    [ADC_DBG]: "
+
+typedef enum _ADC_DBG_LVL_ {
+    HAL_ADC_LVL         =   0x01,
+    SAL_ADC_LVL         =   0x02,
+    VERI_ADC_LVL        =   0x04,
+}ADC_DBG_LVL,*PADC_DBG_LVL;
+
+#ifdef CONFIG_DEBUG_LOG
+#ifdef CONFIG_DEBUG_LOG_ADC_HAL
+
+    #define DBG_8195A_ADC(...)  do{ \
+        _DbgDump("\r"ADC_PREFIX __VA_ARGS__);\
+    }while(0)
+
+
+    #define ADCDBGLVL   0xFF   
+    #define DBG_8195A_ADC_LVL(LVL,...)  do{\
+            if (LVL&ADCDBGLVL){\
+                _DbgDump("\r"ADC_PREFIX_LVL __VA_ARGS__);\
+            }\
+    }while(0)
+#else
+    #define DBG_ADC_LOG_PERD    100
+    #define DBG_8195A_ADC(...)
+    #define DBG_8195A_ADC_LVL(...)
+#endif
+#endif
+
+
+//================ ADC HAL Related Enumeration ==================
+// ADC Module Selection 
+typedef enum _ADC_MODULE_SEL_ {
+        ADC0_SEL    =   0x0,
+        ADC1_SEL    =   0x1,
+        ADC2_SEL    =   0x2,
+        ADC3_SEL    =   0x3,
+}ADC_MODULE_SEL,*PADC_MODULE_SEL;
+
+// ADC module status 
+typedef enum _ADC_MODULE_STATUS_ {
+    ADC_DISABLE     =   0x0,
+    ADC_ENABLE      =   0x1,
+}ADC_MODULE_STATUS, *PADC_MODULE_STATUS;
+
+// ADC Data Endian
+typedef enum _ADC_DATA_ENDIAN_ {
+    ADC_DATA_ENDIAN_LITTLE      =   0x0,
+    ADC_DATA_ENDIAN_BIG         =   0x1,
+}ADC_DATA_ENDIAN,*PADC_DATA_ENDIAN;
+
+// ADC Debug Select
+typedef enum _ADC_DEBUG_SEL_ {
+    ADC_DBG_SEL_DISABLE         =   0x0,
+    ADC_DBG_SEL_ENABLE          =   0x1,
+}ADC_DEBUG_SEL,*PADC_DEBUG_SEL;
+
+typedef enum _ADC_COMPARE_SET_ {
+    ADC_COMP_SMALLER_THAN       =   0x0,
+    ADC_COMP_GREATER_THAN       =   0x1,
+}ADC_COMPARE_SET, *PADC_COMPARE_SET;
+
+// ADC feature status 
+typedef enum _ADC_FEATURE_STATUS_{
+    ADC_FEATURE_DISABLED    =   0,
+    ADC_FEATURE_ENABLED     =   1,
+}ADC_FEATURE_STATUS,*PADC_FEATURE_STATUS;
+
+// ADC operation type
+typedef enum _ADC_OP_TYPE_ {
+    ADC_RDREG_TYPE  =   0x0,
+    ADC_DMA_TYPE    =   0x1,
+    ADC_INTR_TYPE   =   0x2,
+}ADC_OP_TYPE, *PADC_OP_TYPE;
+
+// ADC device status 
+typedef enum _ADC_DEVICE_STATUS_ {
+    ADC_STS_UNINITIAL   =   0x00,
+    ADC_STS_INITIALIZED =   0x01,
+    ADC_STS_IDLE        =   0x02,
+    
+    ADC_STS_TX_READY    =   0x03,    
+    ADC_STS_TX_ING      =   0x04,
+    
+    ADC_STS_RX_READY    =   0x05,
+    ADC_STS_RX_ING      =   0x06,
+
+    ADC_STS_ERROR       =   0x07,
+    ADC_STS_FULL        =   0x08,
+}ADC_DEVICE_STATUS, *PADC_DEVICE_STATUS;
+
+// ADC error type
+typedef enum _ADC_ERR_TYPE_ {
+    ADC_ERR_FIFO_RD_ERROR           =   0x40,       //ADC FIFO read error
+}ADC_ERR_TYPE, *PADC_ERR_TYPE;
+
+// ADC initial status
+typedef enum _ADC_INITAIL_STATUS_ {
+    ADC0_INITED     =   0x1,
+    ADC1_INITED     =   0x2,
+    ADC2_INITED     =   0x4,
+    ADC3_INITED     =   0x8,
+}ADC_INITAIL_STATUS, *PADC_INITAIL_STATUS;
+
+
+//================ ADC HAL Data Structure ======================
+// ADC HAL initial data structure
+typedef struct _HAL_ADC_INIT_DAT_ {
+    u8                  ADCIdx;         //ADC index used
+    u8                  ADCEn;          //ADC module enable
+    u8                  ADCEndian;      //ADC endian selection, 
+                                        //but actually it's for 32-bit ADC data swap control
+                                        //1'b0: no swap, 
+                                        //1'b1: swap the upper 16-bit and the lower 16-bit
+    u8                  ADCBurstSz;     //ADC DMA operation threshold
+
+    u8                  ADCCompOnly;    //ADC compare mode only enable (without FIFO enable)
+    u8                  ADCOneShotEn;   //ADC one-shot mode enable
+    u8                  ADCOverWREn;    //ADC overwrite mode enable
+    u8                  ADCOneShotTD;   //ADC one shot mode threshold
+
+    u16                 ADCCompCtrl;    //ADC compare mode control,
+                                        //1'b0:less than the compare threshold
+                                        //1'b1:greater than the compare threshod
+    u16                 ADCCompTD;      //ADC compare mode threshold
+    
+    u8                  ADCDataRate;    //ADC down sample data rate, 
+    u8                  ADCAudioEn;     //ADC audio mode enable
+    u8                  ADCEnManul;     //ADC enable manually
+    u8                  ADCDbgSel;
+    
+    u32                  RSVD0;
+    
+    u32                 *ADCData;       //ADC data pointer
+    u32                 ADCPWCtrl;      //ADC0 power control
+    u32                 ADCIntrMSK;     //ADC Interrupt Mask
+    u32                 ADCAnaParAd3;   //ADC analog parameter 3
+    u32                 ADCInInput;     //ADC Input is internal?
+}HAL_ADC_INIT_DAT,*PHAL_ADC_INIT_DAT;
+
+// ADC HAL Operations
+typedef struct _HAL_ADC_OP_ {
+    RTK_STATUS  (*HalADCInit)       (VOID *Data);   //HAL ADC initialization
+    RTK_STATUS  (*HalADCDeInit)     (VOID *Data);   //HAL ADC de-initialization
+    RTK_STATUS  (*HalADCEnable)     (VOID *Data);   //HAL ADC de-initialization
+    u32         (*HalADCReceive)    (VOID *Data);   //HAL ADC receive
+    RTK_STATUS  (*HalADCIntrCtrl)   (VOID *Data);   //HAL ADC interrupt control
+    u32         (*HalADCReadReg)    (VOID *Data, u8 ADCReg);//HAL ADC read register
+}HAL_ADC_OP, *PHAL_ADC_OP;
+
+// ADC user callback adapter
+typedef struct _SAL_ADC_USERCB_ADPT_ {
+    VOID (*USERCB)      (VOID *Data);
+    u32  USERData;
+}SAL_ADC_USERCB_ADPT, *PSAL_ADC_USERCB_ADPT;
+
+// ADC user callback structure
+typedef struct _SAL_ADC_USER_CB_ {
+    PSAL_ADC_USERCB_ADPT    pTXCB;          //ADC Transmit Callback
+    PSAL_ADC_USERCB_ADPT    pTXCCB;         //ADC Transmit Complete Callback
+    PSAL_ADC_USERCB_ADPT    pRXCB;          //ADC Receive Callback
+    PSAL_ADC_USERCB_ADPT    pRXCCB;         //ADC Receive Complete Callback
+    PSAL_ADC_USERCB_ADPT    pRDREQCB;       //ADC Read Request Callback
+    PSAL_ADC_USERCB_ADPT    pERRCB;         //ADC Error Callback
+    PSAL_ADC_USERCB_ADPT    pDMATXCB;       //ADC DMA Transmit Callback
+    PSAL_ADC_USERCB_ADPT    pDMATXCCB;      //ADC DMA Transmit Complete Callback
+    PSAL_ADC_USERCB_ADPT    pDMARXCB;       //ADC DMA Receive Callback
+    PSAL_ADC_USERCB_ADPT    pDMARXCCB;      //ADC DMA Receive Complete Callback
+}SAL_ADC_USER_CB, *PSAL_ADC_USER_CB;
+
+// ADC Transmit Buffer
+typedef struct _SAL_ADC_TRANSFER_BUF_ {
+    u32     DataLen;                        //ADC Transmfer Length
+    u32     *pDataBuf;                      //ADC Transfer Buffer Pointer
+    u32     RSVD;                           //
+}SAL_ADC_TRANSFER_BUF,*PSAL_ADC_TRANSFER_BUF;
+
+typedef struct _SAL_ADC_DMA_USER_DEF_ {
+    
+    u8      TxDatSrcWdth;
+    u8      TxDatDstWdth;
+    u8      TxDatSrcBstSz;
+    u8      TxDatDstBstSz;
+
+    u8      TxChNo;
+    u8      LlpCtrl;
+    u16     RSVD0;
+
+    u32     MaxMultiBlk;    
+    u32     pLlix;
+    u32     pBlockSizeList;
+}SAL_ADC_DMA_USER_DEF, *PSAL_ADC_DMA_USER_DEF;
+
+// Software API Level ADC Handler 
+typedef struct _SAL_ADC_HND_ {
+    u8                      DevNum;             //ADC device number
+    u8                      PinMux;             //ADC pin mux seletion
+    u8                      OpType;             //ADC operation type selection
+    volatile u8             DevSts;             //ADC device status
+    
+    u32                     ADCExd;             //ADC extended options:
+                                                //bit 0: example
+                                                //bit 31~bit 1: Reserved
+    u32                     ErrType;            //
+    u32                     TimeOut;            //ADC IO Timeout count
+                                                                            
+    PHAL_ADC_INIT_DAT       pInitDat;           //Pointer to ADC initial data struct
+    PSAL_ADC_TRANSFER_BUF   pRXBuf;             //Pointer to ADC TX buffer
+    PSAL_ADC_USER_CB        pUserCB;            //Pointer to ADC User Callback
+}SAL_ADC_HND, *PSAL_ADC_HND;
+
+// ADC SAL handle private 
+typedef struct _SAL_ADC_HND_PRIV_ {
+    VOID            **ppSalADCHnd;              //Pointer to SAL_ADC_HND pointer
+    SAL_ADC_HND     SalADCHndPriv;              //Private SAL_ADC_HND
+}SAL_ADC_HND_PRIV, *PSAL_ADC_HND_PRIV;
+
+//ADC SAL management adapter
+typedef struct _SAL_ADC_MNGT_ADPT_ {
+    PSAL_ADC_HND_PRIV       pSalHndPriv;        //Pointer to SAL_ADC_HND
+    PHAL_ADC_INIT_DAT       pHalInitDat;        //Pointer to HAL ADC initial data( HAL_ADC_INIT_DAT )
+    PHAL_ADC_OP             pHalOp;             //Pointer to HAL ADC operation( HAL_ADC_OP )
+    VOID                    (*pHalOpInit)(VOID*);//Pointer to HAL ADC initialize function
+
+    PIRQ_HANDLE             pIrqHnd;            //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
+    VOID                    (*pSalIrqFunc)(VOID*);      //Used for SAL ADC interrupt function
+
+    PSAL_ADC_DMA_USER_DEF   pDMAConf;                   //Pointer to DAC User Define DMA config
+    PHAL_GDMA_ADAPTER       pHalGdmaAdp;
+    PHAL_GDMA_OP            pHalGdmaOp;
+    PIRQ_HANDLE             pIrqGdmaHnd;
+    VOID                    (*pHalGdmaOpInit)(VOID*);   //Pointer to HAL DAC initialize function    
+    PSAL_ADC_USER_CB        pUserCB;                    //Pointer to SAL user callbacks (SAL_ADC_USER_CB )
+    VOID                    (*pSalDMAIrqFunc)(VOID*);   //Used for SAL DAC interrupt function
+}SAL_ADC_MNGT_ADPT, *PSAL_ADC_MNGT_ADPT;
+
+
+//================ ADC HAL Function Prototype ===================
+// ADC HAL inline function
+// For checking I2C input index valid or not
+static inline RTK_STATUS
+RtkADCIdxChk(
+    IN  u8  ADCIdx
+)
+{
+#if !ADC0_USED
+    if (ADCIdx == ADC0_SEL)
+        return _EXIT_FAILURE;
+#endif
+
+#if !ADC1_USED
+    if (ADCIdx == ADC1_SEL)
+        return _EXIT_FAILURE;
+#endif
+
+#if !ADC2_USED
+    if (ADCIdx == ADC2_SEL)
+        return _EXIT_FAILURE;
+#endif
+
+#if !ADC3_USED
+        if (ADCIdx == ADC3_SEL)
+            return _EXIT_FAILURE;
+#endif
+
+    return _EXIT_SUCCESS;
+}
+
+VOID HalADCOpInit(IN VOID *Data);
+PSAL_ADC_HND RtkADCGetSalHnd(IN  u8  DACIdx);
+RTK_STATUS RtkADCFreeSalHnd(IN  PSAL_ADC_HND    pSalADCHND);
+RTK_STATUS RtkADCLoadDefault(IN  VOID *Data);
+RTK_STATUS RtkADCInit(IN  VOID *Data);
+RTK_STATUS RtkADCDeInit(IN  VOID *Data);
+//RTK_STATUS RtkADCReceive(IN  VOID *Data);
+u32 RtkADCReceive(IN  VOID *Data);
+u32 RtkADCReceiveBuf(IN  VOID *Data,IN  u32  *pBuf);
+
+PSAL_ADC_MNGT_ADPT RtkADCGetMngtAdpt(IN  u8  ADCIdx);
+RTK_STATUS RtkADCFreeMngtAdpt(IN  PSAL_ADC_MNGT_ADPT  pSalADCMngtAdpt);
+VOID ADCISRHandle(IN  VOID *Data);
+VOID ADCGDMAISRHandle(IN  VOID *Data);
+HAL_Status RtkADCDisablePS(IN  VOID *Data);
+HAL_Status RtkADCEnablePS(IN  VOID *Data);
+
+#endif

sdk/component/soc/realtek/8195a/fwlib/hal_api.h

@@ -0,0 +1,126 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+#ifndef _HAL_API_H_
+#define _HAL_API_H_
+
+#include "basic_types.h"
+#include "hal_irqn.h"
+
+#define HAL_READ32(base, addr)            \
+        rtk_le32_to_cpu(*((volatile u32*)(base + addr)))
+    
+#define HAL_WRITE32(base, addr, value32)  \
+        ((*((volatile u32*)(base + addr))) = rtk_cpu_to_le32(value32))
+
+
+#define HAL_READ16(base, addr)            \
+        rtk_le16_to_cpu(*((volatile u16*)(base + addr)))
+        
+#define HAL_WRITE16(base, addr, value)  \
+        ((*((volatile u16*)(base + addr))) = rtk_cpu_to_le16(value))
+    
+
+#define HAL_READ8(base, addr)            \
+        (*((volatile u8*)(base + addr)))
+            
+#define HAL_WRITE8(base, addr, value)  \
+        ((*((volatile u8*)(base + addr))) = value)
+
+#if 0
+// These "extern _LONG_CALL_" function declaration are for RAM code building only
+// For ROM code building, thses code should be marked off
+extern _LONG_CALL_ u8 
+HalPinCtrlRtl8195A(
+    IN u32  Function, 
+    IN u32  PinLocation, 
+    IN BOOL   Operation
+    );
+
+extern _LONG_CALL_ VOID 
+HalSerialPutcRtl8195a(
+    IN  u8 c
+    );
+
+extern _LONG_CALL_ u8 
+HalSerialGetcRtl8195a(
+    IN  BOOL    PullMode
+    );
+
+extern _LONG_CALL_ u32
+HalSerialGetIsrEnRegRtl8195a(VOID);
+
+extern _LONG_CALL_ VOID
+HalSerialSetIrqEnRegRtl8195a (
+    IN  u32 SetValue
+    );
+
+extern _LONG_CALL_  VOID
+VectorTableInitForOSRtl8195A(
+    IN  VOID *PortSVC,
+    IN  VOID *PortPendSVH,
+    IN  VOID *PortSysTick    
+    );
+
+extern _LONG_CALL_ BOOL
+VectorIrqRegisterRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+    );
+
+extern _LONG_CALL_ BOOL
+VectorIrqUnRegisterRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+    );
+
+extern _LONG_CALL_ VOID
+VectorIrqEnRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+    );
+
+extern _LONG_CALL_  VOID
+VectorIrqDisRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+    );
+#endif
+
+extern BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);
+extern VOID InitWDGIRQ(VOID);
+
+#define PinCtrl HalPinCtrlRtl8195A
+
+#define DiagPutChar	HalSerialPutcRtl8195a
+#define DiagGetChar HalSerialGetcRtl8195a
+#define DiagGetIsrEnReg HalSerialGetIsrEnRegRtl8195a
+#define DiagSetIsrEnReg HalSerialSetIrqEnRegRtl8195a
+
+#define InterruptForOSInit VectorTableInitForOSRtl8195A
+#define InterruptRegister VectorIrqRegisterRtl8195A
+#define InterruptUnRegister  VectorIrqUnRegisterRtl8195A
+
+#define InterruptEn VectorIrqEnRtl8195A
+#define InterruptDis VectorIrqDisRtl8195A
+
+#define SpicFlashInit SpicFlashInitRtl8195A
+#define Calibration32k En32KCalibration
+#define WDGInit InitWDGIRQ
+
+typedef enum  _HAL_Status
+{
+  HAL_OK            = 0x00,
+  HAL_BUSY          = 0x01,
+  HAL_TIMEOUT       = 0x02,
+  HAL_ERR_PARA      = 0x03,     // error with invaild parameters 
+  HAL_ERR_MEM       = 0x04,     // error with memory allocation failed
+  HAL_ERR_HW        = 0x05,     // error with hardware error
+
+  HAL_ERR_UNKNOWN   = 0xee      // unknown error
+  
+} HAL_Status;
+
+
+#endif //_HAL_API_H_

sdk/component/soc/realtek/8195a/fwlib/hal_common.h

@@ -0,0 +1,17 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_COMMON_H_
+#define _HAL_COMMON_H_
+
+//================= Function Prototype START  ===================
+HAL_Status HalCommonInit(void);
+//================= Function Prototype END     ===================
+
+#endif

sdk/component/soc/realtek/8195a/fwlib/hal_dac.h

@@ -0,0 +1,313 @@
+//======================================================
+//  Routines to access hardware
+//
+//  Copyright (c) 2013 Realtek Semiconductor Corp.
+//
+//  This module is a confidential and proprietary property of RealTek and
+//  possession or use of this module requires written permission of RealTek.
+//======================================================
+#ifndef _HAL_DAC_H_
+#define _HAL_DAC_H_
+
+#include "rtl8195a.h"
+#include "rtl8195a_dac.h"
+#include "hal_api.h"
+#include "hal_gdma.h"
+
+//================ DAC Configuration  =========================
+#define DAC_INTR_OP_TYPE    1
+#define DAC_DMA_OP_TYPE     1
+
+// DAC SAL management macros
+#define SAL_DAC_USER_CB_NUM     (sizeof(SAL_DAC_USER_CB) / sizeof(PSAL_DAC_USERCB_ADPT))
+
+// DAC SAL used module. 
+// Please set the DAC module flag to 1 to enable the related DAC module functions.
+#define DAC0_USED                   1
+#define DAC1_USED                   1
+
+
+//================ Debug MSG Definition =======================
+#define DAC_PREFIX      "RTL8195A[dac]: "
+#define DAC_PREFIX_LVL  "    [DAC_DBG]: "
+
+typedef enum _DAC_DBG_LVL_ {
+    HAL_DAC_LVL         =   0x00,
+    SAL_DAC_LVL         =   0x02,
+    VERI_DAC_LVL        =   0x04,
+}DAC_DBG_LVL,*PDAC_DBG_LVL;
+
+#ifdef CONFIG_DEBUG_LOG
+#ifdef CONFIG_DEBUG_LOG_DAC_HAL
+
+    #define DBG_8195A_DAC(...)  do{ \
+        _DbgDump("\r"DAC_PREFIX __VA_ARGS__);\
+    }while(0)
+
+
+    #define DACDBGLVL   0xFF   
+    #define DBG_8195A_DAC_LVL(LVL,...)  do{\
+            if (LVL&DACDBGLVL){\
+                _DbgDump("\r"DAC_PREFIX_LVL __VA_ARGS__);\
+            }\
+    }while(0)
+#else
+    #define DBG_DAC_LOG_PERD    100
+    #define DBG_8195A_DAC(...)
+    #define DBG_8195A_DAC_LVL(...)
+#endif
+#endif
+
+
+//================ DAC HAL Related Enumeration ==================
+// DAC Module Selection 
+typedef enum _DAC_MODULE_SEL_ {
+        DAC0_SEL    =   0x0,
+        DAC1_SEL    =   0x1,
+}DAC_MODULE_SEL,*PDAC_MODULE_SEL;
+
+// DAC module status 
+typedef enum _DAC_MODULE_STATUS_ {
+    DAC_DISABLE     =   0x0,
+    DAC_ENABLE      =   0x1,
+}DAC_MODULE_STATUS, *PDAC_MODULE_STATUS;
+
+// DAC Data Rate
+typedef enum _DAC_DATA_RATE_ {
+    DAC_DATA_RATE_10K   =   0x0,
+    DAC_DATA_RATE_250K  =   0x1,
+}DAC_DATA_RATE,*PDAC_DATA_RATE;
+
+// DAC Data Endian
+typedef enum _DAC_DATA_ENDIAN_ {
+    DAC_DATA_ENDIAN_LITTLE      =   0x0,
+    DAC_DATA_ENDIAN_BIG         =   0x1,
+}DAC_DATA_ENDIAN,*PDAC_DATA_ENDIAN;
+
+// DAC Debug Select
+typedef enum _DAC_DEBUG_SEL_ {
+    DAC_DBG_SEL_DISABLE         =   0x0,
+    DAC_DBG_SEL_ENABLE          =   0x1,
+}DAC_DEBUG_SEL,*PDAC_DEBUG_SEL;
+
+// DAC Dsc Debug Select
+typedef enum _DAC_DSC_DEBUG_SEL_ {
+    DAC_DSC_DBG_SEL_DISABLE         =   0x0,
+    DAC_DSC_DBG_SEL_ENABLE          =   0x1,
+}DAC_DSC_DEBUG_SEL,*PDAC_DSC_DEBUG_SEL;
+
+
+// DAC Bypass Dsc Debug Select
+typedef enum _DAC_BYPASS_DSC_SEL_ {
+    DAC_BYPASS_DSC_SEL_DISABLE          =   0x0,
+    DAC_BYPASS_DSC_SEL_ENABLE           =   0x1,
+}DAC_BYPASS_DSC_SEL,*PDAC_BYPASS_DSC_SEL;
+
+// DAC feature status 
+typedef enum _DAC_FEATURE_STATUS_{
+    DAC_FEATURE_DISABLED    =   0,
+    DAC_FEATURE_ENABLED     =   1,
+}DAC_FEATURE_STATUS,*PDAC_FEATURE_STATUS;
+
+// DAC operation type
+typedef enum _DAC_OP_TYPE_ {
+    DAC_POLL_TYPE   =   0x0,
+    DAC_DMA_TYPE    =   0x1,
+    DAC_INTR_TYPE   =   0x2,
+}DAC_OP_TYPE, *PDAC_OP_TYPE;
+
+// DAC device status 
+typedef enum _DAC_Device_STATUS_ {
+    DAC_STS_UNINITIAL   =   0x00,
+    DAC_STS_INITIALIZED =   0x01,
+    DAC_STS_IDLE        =   0x02,
+    
+    DAC_STS_TX_READY    =   0x03,    
+    DAC_STS_TX_ING      =   0x04,
+    
+    DAC_STS_RX_READY    =   0x05,
+    DAC_STS_RX_ING      =   0x06,
+
+    DAC_STS_ERROR       =   0x07,
+}DAC_Device_STATUS, *PDAC_Device_STATUS;
+
+//DAC device error type
+typedef enum _DAC_ERR_TYPE_ {
+    DAC_ERR_FIFO_OVER       =   0x04,       //DAC FIFO overflow.
+    DAC_ERR_FIFO_STOP       =   0x08,       //DAC FIFO is completely empty, and it will be stopped automatically.
+    DAC_ERR_FIFO_WRFAIL     =   0x10,       //When DAC is NOT enabled, a write operation attempts to access DAC register.
+    DAC_ERR_FIFO_DSC_OVER0  =   0x20,
+    DAC_ERR_FIFO_DSC_OVER1  =   0x40,
+}DAC_ERR_TYPE, *PDAC_ERR_TYPE;
+
+// DAC data input method
+typedef enum _DAC_INPUT_TYPE_{
+    DAC_INPUT_SINGLE_WR     =   0x1,        //DAC input by using single register write
+    DAC_INPUT_DMA_ONEBLK    =   0x2,        //DAC input by using single DMA block
+    DAC_INPUT_DMA_LLP       =   0x3,        //DAC input by using DMA linked list mode
+}DAC_INPUT_TYPE,*PDAC_INPUT_TYPE;
+
+
+
+
+//======================================================
+// DAC HAL initial data structure 
+typedef struct _HAL_DAC_INIT_DAT_ {
+    u8                  DACIdx;         //DAC index used
+    u8                  DACEn;          //DAC module enable
+    u8                  DACDataRate;    //DAC data rate, 1'b0:10KHz, 1'b1:250KHz
+    u8                  DACEndian;      //DAC endian selection, 
+                                        //but actually it's for 32-bit DAC data swap control
+                                        //1'b0: no swap, 
+                                        //1'b1: swap the upper 16-bit and the lower 16-bit
+    u8                  DACFilterSet;   //DAC filter settle
+    u8                  DACBurstSz;     //DAC burst size
+    u8                  DACDbgSel;      //DAC debug sel
+    u8                  DACDscDbgSel;   //DAC debug dsc sel
+    
+    u8                  DACBPDsc;       //DAC bypass delta sigma for loopback
+    u8                  DACDeltaSig;    //DAC bypass value of delta sigma
+    u16                 RSVD1;          
+
+
+    
+    u32                 *DACData;       //DAC data pointer
+    u32                 DACPWCtrl;      //DAC0 and DAC1 power control
+    u32                 DACAnaCtrl0;    //DAC anapar_da control 0
+    u32                 DACAnaCtrl1;    //DAC anapar_da control 1
+    u32                 DACIntrMSK;     //DAC Interrupt Mask
+}HAL_DAC_INIT_DAT,*PHAL_DAC_INIT_DAT;
+
+// DAC HAL Operations
+typedef struct _HAL_DAC_OP_ {
+    RTK_STATUS  (*HalDACInit)       (VOID *Data);   //HAL DAC initialization
+    RTK_STATUS  (*HalDACDeInit)     (VOID *Data);   //HAL DAC de-initialization
+    RTK_STATUS  (*HalDACEnable)     (VOID *Data);   //HAL DAC de-initialization
+    u8          (*HalDACSend)       (VOID *Data);   //HAL DAC receive
+    RTK_STATUS  (*HalDACIntrCtrl)   (VOID *Data);   //HAL DAC interrupt control
+    u32         (*HalDACReadReg)    (VOID *Data, u8 DACReg);//HAL DAC read register
+}HAL_DAC_OP, *PHAL_DAC_OP;
+
+// DAC user callback adapter
+typedef struct _SAL_DAC_USERCB_ADPT_ {
+    VOID (*USERCB)      (VOID *Data);
+    u32  USERData;
+}SAL_DAC_USERCB_ADPT, *PSAL_DAC_USERCB_ADPT;
+
+// DAC user callback structure
+typedef struct _SAL_DAC_USER_CB_ {
+    PSAL_DAC_USERCB_ADPT    pTXCB;          //DAC Transmit Callback
+    PSAL_DAC_USERCB_ADPT    pTXCCB;         //DAC Transmit Complete Callback
+    PSAL_DAC_USERCB_ADPT    pRXCB;          //DAC Receive Callback
+    PSAL_DAC_USERCB_ADPT    pRXCCB;         //DAC Receive Complete Callback
+    PSAL_DAC_USERCB_ADPT    pRDREQCB;       //DAC Read Request Callback
+    PSAL_DAC_USERCB_ADPT    pERRCB;         //DAC Error Callback
+    PSAL_DAC_USERCB_ADPT    pDMATXCB;       //DAC DMA Transmit Callback
+    PSAL_DAC_USERCB_ADPT    pDMATXCCB;      //DAC DMA Transmit Complete Callback
+    PSAL_DAC_USERCB_ADPT    pDMARXCB;       //DAC DMA Receive Callback
+    PSAL_DAC_USERCB_ADPT    pDMARXCCB;      //DAC DMA Receive Complete Callback
+}SAL_DAC_USER_CB, *PSAL_DAC_USER_CB;
+
+// DAC Transmit Buffer
+typedef struct _SAL_DAC_TRANSFER_BUF_ {
+    u32     DataLen;                        //DAC Transmfer Length
+    u32     *pDataBuf;                      //DAC Transfer Buffer Pointer
+    u32     RSVD;                           //
+}SAL_DAC_TRANSFER_BUF,*PSAL_DAC_TRANSFER_BUF;
+
+typedef struct _SAL_DAC_DMA_USER_DEF_ {
+    
+    u8      TxDatSrcWdth;
+    u8      TxDatDstWdth;
+    u8      TxDatSrcBstSz;
+    u8      TxDatDstBstSz;
+
+    u8      TxChNo;
+    u8      LlpCtrl;
+    u16     RSVD0;
+
+    u32     MaxMultiBlk;    
+    u32     pLlix;
+    u32     pBlockSizeList;
+}SAL_DAC_DMA_USER_DEF, *PSAL_DAC_DMA_USER_DEF;
+
+// Software API Level DAC Handler 
+typedef struct _SAL_DAC_HND_ {
+    u8                      DevNum;             //DAC device number
+    u8                      PinMux;             //DAC pin mux seletion
+    u8                      OpType;             //DAC operation type selection
+    volatile u8             DevSts;             //DAC device status
+
+    u8                      DACInType;          //DAC input type
+    u8                      RSVD0;
+    u16                     RSVD1;
+    
+    u32                     DACExd;             //DAC extended options:
+                                                //bit 0: example
+                                                //bit 31~bit 1: Reserved
+    u32                     ErrType;            //
+    u32                     TimeOut;            //DAC IO Timeout count
+                                                                            
+    PHAL_DAC_INIT_DAT       pInitDat;           //Pointer to DAC initial data struct
+    PSAL_DAC_TRANSFER_BUF   pTXBuf;             //Pointer to DAC TX buffer
+    PSAL_DAC_USER_CB        pUserCB;            //Pointer to DAC User Callback
+    PSAL_DAC_DMA_USER_DEF   pDMAConf;           //Pointer to DAC User Define DMA Config
+}SAL_DAC_HND, *PSAL_DAC_HND;
+
+// DAC SAL handle private 
+typedef struct _SAL_DAC_HND_PRIV_ {
+    VOID            **ppSalDACHnd;              //Pointer to SAL_DAC_HND pointer
+    SAL_DAC_HND     SalDACHndPriv;              //Private SAL_DAC_HND
+}SAL_DAC_HND_PRIV, *PSAL_DAC_HND_PRIV;
+
+//DAC SAL management adapter
+typedef struct _SAL_DAC_MNGT_ADPT_ {
+    PSAL_DAC_HND_PRIV       pSalHndPriv;                //Pointer to SAL_DAC_HND
+    PHAL_DAC_INIT_DAT       pHalInitDat;                //Pointer to HAL DAC initial data( HAL_I2C_INIT_DAT )
+    PHAL_DAC_OP             pHalOp;                     //Pointer to HAL DAC operation( HAL_DAC_OP )
+    VOID                    (*pHalOpInit)(VOID*);       //Pointer to HAL DAC initialize function
+    PIRQ_HANDLE             pIrqHnd;                    //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
+    PSAL_DAC_USER_CB        pUserCB;                    //Pointer to SAL user callbacks (SAL_DAC_USER_CB )
+    VOID                    (*pSalIrqFunc)(VOID*);      //Used for SAL DAC interrupt function
+
+    PSAL_DAC_DMA_USER_DEF   pDMAConf;                   //Pointer to DAC User Define DMA config
+    PHAL_GDMA_ADAPTER       pHalGdmaAdp;
+    PHAL_GDMA_OP            pHalGdmaOp;
+    VOID                    (*pHalGdmaOpInit)(VOID*);   //Pointer to HAL DAC initialize function    
+    PIRQ_HANDLE             pIrqGdmaHnd;
+    VOID                    (*pSalDMAIrqFunc)(VOID*);   //Used for SAL DAC interrupt function
+}SAL_DAC_MNGT_ADPT, *PSAL_DAC_MNGT_ADPT;
+
+
+//================ DAC HAL Function Prototype ===================
+// DAC HAL inline function
+// For checking DAC input index valid or not
+static inline RTK_STATUS
+RtkDACIdxChk(
+    IN  u8  DACIdx
+)
+{
+#if !DAC0_USED
+    if (DACIdx == DAC0_SEL)
+        return _EXIT_FAILURE;
+#endif
+
+#if !DAC1_USED
+    if (DACIdx == DAC1_SEL)
+        return _EXIT_FAILURE;
+#endif
+        
+    return _EXIT_SUCCESS;
+}
+
+VOID HalDACOpInit(IN VOID *Data);
+RTK_STATUS RtkDACLoadDefault(IN  VOID *Data);
+RTK_STATUS RtkDACInit(IN  VOID *Data);
+RTK_STATUS RtkDACDeInit(IN  VOID *Data);
+RTK_STATUS RtkDACSend(IN  VOID *Data);
+PSAL_DAC_HND RtkDACGetSalHnd(IN  u8  DACIdx);
+RTK_STATUS RtkDACFreeSalHnd(IN  PSAL_DAC_HND    pSalDACHND);
+PSAL_DAC_MNGT_ADPT RtkDACGetMngtAdpt(IN  u8  DACIdx);
+RTK_STATUS RtkDACFreeMngtAdpt(IN  PSAL_DAC_MNGT_ADPT  pSalDACMngtAdpt);
+
+#endif

sdk/component/soc/realtek/8195a/fwlib/hal_diag.h

@@ -0,0 +1,107 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_DIAG_H_
+#define _HAL_DIAG_H_
+
+
+//Register offset
+#define UART_REV_BUF_OFF            0x00
+#define UART_TRAN_HOLD_OFF          0x00
+#define UART_DLH_OFF                0x04
+#define UART_DLL_OFF                0x00
+#define UART_INTERRUPT_EN_REG_OFF   0x04
+#define UART_INTERRUPT_IDEN_REG_OFF 0x08
+#define UART_FIFO_CTL_REG_OFF       0x08
+#define UART_LINE_CTL_REG_OFF       0x0c
+#define UART_MODEM_CTL_REG_OFF      0x10
+#define UART_LINE_STATUS_REG_OFF    0x14
+#define UART_MODEM_STATUS_REG_OFF   0x18
+#define UART_FIFO_ACCESS_REG_OFF    0x70
+#define UART_STATUS_REG_OFF         0x7c
+#define UART_TFL_OFF                0x80
+#define UART_RFL_OFF                0x84
+
+
+//Buad rate
+#define UART_BAUD_RATE_2400         2400
+#define UART_BAUD_RATE_4800         4800
+#define UART_BAUD_RATE_9600         9600
+#define UART_BAUD_RATE_19200        19200
+#define UART_BAUD_RATE_38400        38400
+#define UART_BAUD_RATE_57600        57600
+#define UART_BAUD_RATE_115200       115200
+#define UART_BAUD_RATE_921600       921600
+#define UART_BAUD_RATE_1152000      1152000
+
+#define UART_PARITY_ENABLE          0x08
+#define UART_PARITY_DISABLE         0
+
+#define UART_DATA_LEN_5BIT          0x0
+#define UART_DATA_LEN_6BIT          0x1
+#define UART_DATA_LEN_7BIT          0x2
+#define UART_DATA_LEN_8BIT          0x3
+
+#define UART_STOP_1BIT              0x0
+#define UART_STOP_2BIT              0x4
+
+
+#define HAL_UART_READ32(addr)            HAL_READ32(LOG_UART_REG_BASE, addr)
+#define HAL_UART_WRITE32(addr, value)    HAL_WRITE32(LOG_UART_REG_BASE, addr, value)
+#define HAL_UART_READ16(addr)            HAL_READ16(LOG_UART_REG_BASE, addr)
+#define HAL_UART_WRITE16(addr, value)    HAL_WRITE16(LOG_UART_REG_BASE, addr, value)
+#define HAL_UART_READ8(addr)             HAL_READ8(LOG_UART_REG_BASE, addr)
+#define HAL_UART_WRITE8(addr, value)     HAL_WRITE8(LOG_UART_REG_BASE, addr, value)
+
+typedef struct _LOG_UART_ADAPTER_ {
+    u32     BaudRate;
+    u32     FIFOControl; 
+    u32     IntEnReg;
+    u8      Parity;
+    u8      Stop;
+    u8      DataLength;
+}LOG_UART_ADAPTER, *PLOG_UART_ADAPTER;
+
+typedef struct _COMMAND_TABLE_ {
+    const   u8* cmd;
+    u16     ArgvCnt;
+    u32     (*func)(u16 argc, u8* argv[]);
+    const   u8* msg;
+}COMMAND_TABLE, *PCOMMAND_TABLE;
+
+//VOID
+//HalLogUartHandle(void);
+
+
+extern _LONG_CALL_ROM_ u32 
+HalLogUartInit(
+    IN  LOG_UART_ADAPTER    UartAdapter
+    );
+
+
+extern _LONG_CALL_ROM_ VOID 
+HalSerialPutcRtl8195a(
+    IN  u8 c
+    );
+
+extern _LONG_CALL_ROM_ u8 
+HalSerialGetcRtl8195a(
+    IN  BOOL    PullMode
+    );
+
+extern _LONG_CALL_ROM_ u32
+HalSerialGetIsrEnRegRtl8195a(VOID);
+
+extern _LONG_CALL_ROM_ VOID
+HalSerialSetIrqEnRegRtl8195a (
+    IN  u32 SetValue
+);
+
+
+#endif//_HAL_DIAG_H_

sdk/component/soc/realtek/8195a/fwlib/hal_efuse.h

@@ -0,0 +1,22 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_EFUSE_H_
+#define _HAL_EFUSE_H_
+
+_LONG_CALL_ROM_ extern VOID HalEFUSEPowerSwitch8195AROM(IN u8 bWrite, IN u8 PwrState, IN u8 L25OutVoltage);
+_LONG_CALL_ extern u32 HALEFUSEOneByteReadROM(IN	u32 CtrlSetting, IN	u16 Addr, OUT u8 *Data, IN u8 L25OutVoltage);
+_LONG_CALL_ extern u32 HALEFUSEOneByteWriteROM(IN	u32 CtrlSetting, IN	u16 Addr, IN u8 Data, IN u8 L25OutVoltage);
+
+#define EFUSERead8     HALEFUSEOneByteReadROM
+#define EFUSEWrite8    HALEFUSEOneByteWriteROM
+
+#define L25EOUTVOLTAGE	7
+#endif
+

sdk/component/soc/realtek/8195a/fwlib/hal_gdma.h

@@ -0,0 +1,141 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_GDMA_H_
+#define _HAL_GDMA_H_
+
+#include "rtl8195a_gdma.h"
+
+typedef struct _GDMA_CH_LLI_ELE_ {
+    u32                   Sarx;
+    u32                   Darx;
+    u32                   Llpx;
+    u32                   CtlxLow;
+    u32                   CtlxUp;
+    u32                   Temp;
+}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
+#if 1
+#if 0
+typedef struct _GDMA_CH_LLI_ {
+    PGDMA_CH_LLI_ELE      pLliEle;
+    PGDMA_CH_LLI          pNextLli;
+}GDMA_CH_LLI, *PGDMA_CH_LLI;
+
+typedef struct _BLOCK_SIZE_LIST_ {
+    u32                  BlockSize;
+    PBLOCK_SIZE_LIST     pNextBlockSiz;
+}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST;
+#else
+struct GDMA_CH_LLI {
+    PGDMA_CH_LLI_ELE                pLliEle;
+    struct GDMA_CH_LLI             *pNextLli;
+};
+
+struct BLOCK_SIZE_LIST {
+    u32                             BlockSize;
+    struct BLOCK_SIZE_LIST          *pNextBlockSiz;
+};
+
+#endif
+
+#endif
+typedef struct _HAL_GDMA_ADAPTER_ {
+    u32                   ChSar;
+    u32                   ChDar;
+    GDMA_CHANNEL_NUM      ChEn;
+    GDMA_CTL_REG          GdmaCtl;
+    GDMA_CFG_REG          GdmaCfg;
+    u32                   PacketLen;
+    u32                   BlockLen;
+    u32                   MuliBlockCunt;
+    u32                   MaxMuliBlock;
+    struct GDMA_CH_LLI          *pLlix;
+    struct BLOCK_SIZE_LIST      *pBlockSizeList;
+
+    PGDMA_CH_LLI_ELE            pLli;
+    u32                         NextPlli;
+    u8                    TestItem;
+    u8                          ChNum;
+    u8                          GdmaIndex;
+    u8                          IsrCtrl:1;
+    u8                          GdmaOnOff:1;
+    u8                          Llpctrl:1;
+    u8                          Lli0:1;
+    u8                          Rsvd4to7:4;
+    u8                          GdmaIsrType;
+}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER;
+
+typedef struct _HAL_GDMA_CHNL_ {
+    u8 GdmaIndx;
+    u8 GdmaChnl;
+    u8 IrqNum;
+    u8 Reserved;
+}HAL_GDMA_CHNL, *PHAL_GDMA_CHNL;
+
+typedef struct _HAL_GDMA_BLOCK_ {
+    u32 SrcAddr;
+    u32 DstAddr;
+    u32 BlockLength;
+    u32 SrcOffset;
+    u32 DstOffset;
+}HAL_GDMA_BLOCK, *PHAL_GDMA_BLOCK;
+
+typedef struct _HAL_GDMA_OP_ {
+    VOID (*HalGdmaOnOff)(VOID *Data);
+    BOOL (*HalGdamChInit)(VOID *Data);
+    BOOL (*HalGdmaChSeting)(VOID *Data);
+    BOOL (*HalGdmaChBlockSeting)(VOID *Data);
+    VOID (*HalGdmaChDis)(VOID *Data);
+    VOID (*HalGdmaChEn)(VOID *Data);
+    VOID (*HalGdmaChIsrEnAndDis) (VOID *Data);
+    u8   (*HalGdmaChIsrClean)(VOID *Data);
+    VOID (*HalGdmaChCleanAutoSrc)(VOID *Data);
+    VOID (*HalGdmaChCleanAutoDst)(VOID *Data);
+}HAL_GDMA_OP, *PHAL_GDMA_OP;
+
+typedef struct _HAL_GDMA_OBJ_ {
+    HAL_GDMA_ADAPTER HalGdmaAdapter;
+    IRQ_HANDLE GdmaIrqHandle;
+    volatile GDMA_CH_LLI_ELE GdmaChLli[16];
+    struct GDMA_CH_LLI Lli[16];
+    struct BLOCK_SIZE_LIST BlockSizeList[16];
+    u8 Busy;      // is transfering
+    u8 BlockNum;
+} HAL_GDMA_OBJ, *PHAL_GDMA_OBJ;
+
+VOID HalGdmaOpInit(IN  VOID *Data);
+VOID HalGdmaOn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+VOID HalGdmaOff(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+BOOL HalGdmaChInit(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+VOID HalGdmaChDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+VOID HalGdmaChEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+BOOL HalGdmaChSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+BOOL HalGdmaChBlockSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+VOID HalGdmaChIsrEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+VOID HalGdmaChIsrDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+u8 HalGdmaChIsrClean(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+VOID HalGdmaChCleanAutoSrc(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+VOID HalGdmaChCleanAutoDst(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
+
+extern HAL_Status HalGdmaChnlRegister (u8 GdmaIdx, u8 ChnlNum);
+extern VOID HalGdmaChnlUnRegister (u8 GdmaIdx, u8 ChnlNum);
+extern PHAL_GDMA_CHNL HalGdmaChnlAlloc (HAL_GDMA_CHNL *pChnlOption);
+extern VOID HalGdmaChnlFree (HAL_GDMA_CHNL *pChnl);
+extern BOOL HalGdmaMemCpyInit(PHAL_GDMA_OBJ pHalGdmaObj);
+extern VOID HalGdmaMemCpyDeInit(PHAL_GDMA_OBJ pHalGdmaObj);
+extern VOID* HalGdmaMemCpy(PHAL_GDMA_OBJ pHalGdmaObj, void* pDest, void* pSrc, u32 len);
+extern VOID HalGdmaMemAggr(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock);
+extern BOOL HalGdmaMemCpyAggrInit(PHAL_GDMA_OBJ pHalGdmaObj);
+
+extern const HAL_GDMA_OP _HalGdmaOp;
+extern const HAL_GDMA_CHNL GDMA_Chnl_Option[];
+extern const HAL_GDMA_CHNL GDMA_Multi_Block_Chnl_Option[];
+extern const u16 HalGdmaChnlEn[6];
+
+#endif

sdk/component/soc/realtek/8195a/fwlib/hal_gpio.h

@@ -0,0 +1,236 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_GPIO_H_
+#define _HAL_GPIO_H_
+
+#define HAL_GPIO_PIN_INT_MODE       0x80
+
+typedef enum {
+    _PORT_A = 0,
+    _PORT_B = 1,
+    _PORT_C = 2,
+    _PORT_D = 3,
+    _PORT_E = 4,
+    _PORT_F = 5,
+    _PORT_G = 6,
+    _PORT_H = 7,
+    _PORT_I = 8,
+    _PORT_J = 9,
+    _PORT_K = 10,
+
+    _PORT_MAX
+} HAL_GPIO_PORT_NAME;
+
+typedef enum {
+    _PA_0  = (_PORT_A<<4|0),
+    _PA_1  = (_PORT_A<<4|1),
+    _PA_2  = (_PORT_A<<4|2),
+    _PA_3  = (_PORT_A<<4|3),
+    _PA_4  = (_PORT_A<<4|4),
+    _PA_5  = (_PORT_A<<4|5),
+    _PA_6  = (_PORT_A<<4|6),
+    _PA_7  = (_PORT_A<<4|7),
+
+    _PB_0  = (_PORT_B<<4|0),
+    _PB_1  = (_PORT_B<<4|1),
+    _PB_2  = (_PORT_B<<4|2),
+    _PB_3  = (_PORT_B<<4|3),
+    _PB_4  = (_PORT_B<<4|4),
+    _PB_5  = (_PORT_B<<4|5),
+    _PB_6  = (_PORT_B<<4|6),
+    _PB_7  = (_PORT_B<<4|7),
+
+    _PC_0  = (_PORT_C<<4|0),
+    _PC_1  = (_PORT_C<<4|1),
+    _PC_2  = (_PORT_C<<4|2),
+    _PC_3  = (_PORT_C<<4|3),
+    _PC_4  = (_PORT_C<<4|4),
+    _PC_5  = (_PORT_C<<4|5),
+    _PC_6  = (_PORT_C<<4|6),
+    _PC_7  = (_PORT_C<<4|7),
+    _PC_8  = (_PORT_C<<4|8),
+    _PC_9  = (_PORT_C<<4|9),
+
+    _PD_0  = (_PORT_D<<4|0),
+    _PD_1  = (_PORT_D<<4|1),
+    _PD_2  = (_PORT_D<<4|2),
+    _PD_3  = (_PORT_D<<4|3),
+    _PD_4  = (_PORT_D<<4|4),
+    _PD_5  = (_PORT_D<<4|5),
+    _PD_6  = (_PORT_D<<4|6),
+    _PD_7  = (_PORT_D<<4|7),
+    _PD_8  = (_PORT_D<<4|8),
+    _PD_9  = (_PORT_D<<4|9),
+  
+    _PE_0  = (_PORT_E<<4|0),
+    _PE_1  = (_PORT_E<<4|1),
+    _PE_2  = (_PORT_E<<4|2),
+    _PE_3  = (_PORT_E<<4|3),
+    _PE_4  = (_PORT_E<<4|4),
+    _PE_5  = (_PORT_E<<4|5),
+    _PE_6  = (_PORT_E<<4|6),
+    _PE_7  = (_PORT_E<<4|7),
+    _PE_8  = (_PORT_E<<4|8),
+    _PE_9  = (_PORT_E<<4|9),
+    _PE_A  = (_PORT_E<<4|10),
+  
+    _PF_0  = (_PORT_F<<4|0),
+    _PF_1  = (_PORT_F<<4|1),
+    _PF_2  = (_PORT_F<<4|2),
+    _PF_3  = (_PORT_F<<4|3),
+    _PF_4  = (_PORT_F<<4|4),
+    _PF_5  = (_PORT_F<<4|5),
+//    _PF_6  = (_PORT_F<<4|6),
+//    _PF_7  = (_PORT_F<<4|7),
+
+    _PG_0  = (_PORT_G<<4|0),
+    _PG_1  = (_PORT_G<<4|1),
+    _PG_2  = (_PORT_G<<4|2),
+    _PG_3  = (_PORT_G<<4|3),
+    _PG_4  = (_PORT_G<<4|4),
+    _PG_5  = (_PORT_G<<4|5),
+    _PG_6  = (_PORT_G<<4|6),
+    _PG_7  = (_PORT_G<<4|7),
+
+    _PH_0  = (_PORT_H<<4|0),
+    _PH_1  = (_PORT_H<<4|1),
+    _PH_2  = (_PORT_H<<4|2),
+    _PH_3  = (_PORT_H<<4|3),
+    _PH_4  = (_PORT_H<<4|4),
+    _PH_5  = (_PORT_H<<4|5),
+    _PH_6  = (_PORT_H<<4|6),
+    _PH_7  = (_PORT_H<<4|7),
+
+    _PI_0  = (_PORT_I<<4|0),
+    _PI_1  = (_PORT_I<<4|1),
+    _PI_2  = (_PORT_I<<4|2),
+    _PI_3  = (_PORT_I<<4|3),
+    _PI_4  = (_PORT_I<<4|4),
+    _PI_5  = (_PORT_I<<4|5),
+    _PI_6  = (_PORT_I<<4|6),
+    _PI_7  = (_PORT_I<<4|7),
+
+    _PJ_0  = (_PORT_J<<4|0),
+    _PJ_1  = (_PORT_J<<4|1),
+    _PJ_2  = (_PORT_J<<4|2),
+    _PJ_3  = (_PORT_J<<4|3),
+    _PJ_4  = (_PORT_J<<4|4),
+    _PJ_5  = (_PORT_J<<4|5),
+    _PJ_6  = (_PORT_J<<4|6),
+//    _PJ_7  = (_PORT_J<<4|7),
+
+    _PK_0  = (_PORT_K<<4|0),
+    _PK_1  = (_PORT_K<<4|1),
+    _PK_2  = (_PORT_K<<4|2),
+    _PK_3  = (_PORT_K<<4|3),
+    _PK_4  = (_PORT_K<<4|4),
+    _PK_5  = (_PORT_K<<4|5),
+    _PK_6  = (_PORT_K<<4|6),
+//    _PK_7  = (_PORT_K<<4|7),
+
+    // Not connected
+    _PIN_NC = (int)0xFFFFFFFF
+} HAL_PIN_NAME;
+
+typedef enum
+{
+  GPIO_PIN_LOW  = 0,
+  GPIO_PIN_HIGH = 1,
+  GPIO_PIN_ERR  = 2     // read Pin error
+} HAL_GPIO_PIN_STATE;
+
+typedef enum {
+    DIN_PULL_NONE   = 0,    //floating or high impedance ?
+    DIN_PULL_LOW    = 1,
+    DIN_PULL_HIGH   = 2,
+
+    DOUT_PUSH_PULL  = 3,
+    DOUT_OPEN_DRAIN = 4,
+
+    INT_LOW         = (5|HAL_GPIO_PIN_INT_MODE),    // Interrupt Low level trigger
+    INT_HIGH        = (6|HAL_GPIO_PIN_INT_MODE),    // Interrupt High level trigger
+    INT_FALLING     = (7|HAL_GPIO_PIN_INT_MODE),    // Interrupt Falling edge trigger
+    INT_RISING      = (8|HAL_GPIO_PIN_INT_MODE)     // Interrupt Rising edge trigger        
+} HAL_GPIO_PIN_MODE;
+
+enum {
+    GPIO_PORT_A = 0,
+    GPIO_PORT_B = 1,
+    GPIO_PORT_C = 2,
+    GPIO_PORT_D = 3
+};
+
+typedef enum {
+    hal_PullNone  = 0,
+    hal_PullUp    = 1,
+    hal_PullDown  = 2,
+    hal_OpenDrain = 3,
+    hal_PullDefault = hal_PullNone
+} HAL_PinMode;
+
+typedef struct _HAL_GPIO_PORT_ {
+    u32 out_data;       // to write the GPIO port
+    u32 in_data;        // to read the GPIO port
+    u32 dir;            // config each pin direction    
+}HAL_GPIO_PORT, *PHAL_GPIO_PORT;
+
+#define HAL_GPIO_PIN_NAME(port,pin)         (((port)<<5)|(pin))
+#define HAL_GPIO_GET_PORT_BY_NAME(x)        ((x>>5) & 0x03)
+#define HAL_GPIO_GET_PIN_BY_NAME(x)         (x & 0x1f)
+
+typedef struct _HAL_GPIO_PIN_ {
+    HAL_GPIO_PIN_MODE pin_mode;
+    u32 pin_name;    // Pin: [7:5]: port number, [4:0]: pin number
+}HAL_GPIO_PIN, *PHAL_GPIO_PIN;
+
+typedef struct _HAL_GPIO_OP_ {
+#if defined(__ICCARM__)
+    void* dummy;
+#endif
+}HAL_GPIO_OP, *PHAL_GPIO_OP;
+
+typedef void (*GPIO_IRQ_FUN)(VOID *Data, u32 Id);
+typedef void (*GPIO_USER_IRQ_FUN)(u32 Id);
+
+typedef struct _HAL_GPIO_ADAPTER_ {
+    IRQ_HANDLE IrqHandle;   // GPIO HAL IRQ Handle
+    GPIO_USER_IRQ_FUN UserIrqHandler;   // GPIO IRQ Handler
+    GPIO_IRQ_FUN PortA_IrqHandler[32]; // The interrupt handler triggered by Port A[x]
+    VOID *PortA_IrqData[32];
+    VOID (*EnterCritical)(void);
+    VOID (*ExitCritical)(void);
+    u32 Local_Gpio_Dir[3];  // to record direction setting: 0- IN, 1- Out
+    u8 Gpio_Func_En;    // Is GPIO HW function enabled ?
+    u8 Locked;
+}HAL_GPIO_ADAPTER, *PHAL_GPIO_ADAPTER;
+
+u32 
+HAL_GPIO_GetPinName(
+    u32 chip_pin
+);
+
+VOID 
+HAL_GPIO_PullCtrl(
+    u32 pin,
+    u32 mode    
+);
+
+VOID 
+HAL_GPIO_Init(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+VOID 
+HAL_GPIO_Irq_Init(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+#endif  // end of "#define _HAL_GPIO_H_"
+

sdk/component/soc/realtek/8195a/fwlib/hal_i2c.h

@@ -0,0 +1,585 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_I2C_H_     //#ifndef _HAL_I2C_H_
+#define _HAL_I2C_H_
+
+#include "rtl8195a_i2c.h"
+#include "hal_gdma.h"
+
+//================= I2C CONFIGURATION START ==================
+// I2C SAL User Configuration Flags
+
+// I2C SAL operation types
+#define I2C_POLL_OP_TYPE            1
+#define I2C_INTR_OP_TYPE            1
+#define I2C_DMA_OP_TYPE             1
+
+// I2C supports user register address
+#define I2C_USER_REG_ADDR           1       //I2C User specific register address by using 
+                                            //the first I2C data as the register 
+                                            //address
+                                            
+// I2C SAL used module. Please set the I2C module flag to 1 to enable the related 
+// I2C module functions.
+#define I2C0_USED                   1
+#define I2C1_USED                   1
+#define I2C2_USED                   1
+#define I2C3_USED                   1
+//================= I2C CONFIGURATION END  ===================
+
+
+//================= I2C HAL START  ==========================
+// I2C debug output
+#define I2C_PREFIX      "RTL8195A[i2c]: "
+#define I2C_PREFIX_LVL  "    [i2c_DBG]: "
+
+typedef enum _I2C_DBG_LVL_ {
+    HAL_I2C_LVL         =   0x01,
+    SAL_I2C_LVL         =   0x02,
+    VERI_I2C_LVL        =   0x03,
+}I2C_DBG_LVL,*PI2C_DBG_LVL;
+
+#ifdef CONFIG_DEBUG_LOG
+#ifdef CONFIG_DEBUG_LOG_I2C_HAL
+#define DBG_I2C_LOG_PERD    100
+
+    #define I2CDBGLVL   0xFF
+    #define DBG_8195A_I2C(...)  do{ \
+                                    _DbgDump("\r"I2C_PREFIX __VA_ARGS__);\
+                                }while(0)
+   
+    #define DBG_8195A_I2C_LVL(LVL,...)  do{\
+                                            if (LVL&I2CDBGLVL){\
+                                                _DbgDump("\r"I2C_PREFIX_LVL __VA_ARGS__);\
+                                            }\
+                                        }while(0)
+#else
+    #define DBG_I2C_LOG_PERD    100
+    #define DBG_8195A_I2C(...)
+    #define DBG_8195A_I2C_LVL(...)
+#endif
+#else
+    #define DBG_I2C_LOG_PERD    100
+    #define DBG_8195A_I2C(...)
+    #define DBG_8195A_I2C_LVL(...)
+#endif
+
+//======================================================
+// I2C HAL related enumeration
+// I2C Module Selection 
+typedef enum _I2C_MODULE_SEL_ {
+        I2C0_SEL    =   0x0,
+        I2C1_SEL    =   0x1,
+        I2C2_SEL    =   0x2,
+        I2C3_SEL    =   0x3,
+}I2C_MODULE_SEL,*PI2C_MODULE_SEL;
+
+// I2C HAL initial data structure 
+typedef struct _HAL_I2C_INIT_DAT_ {
+    u8                  I2CIdx;         //I2C index used
+    u8                  I2CEn;          //I2C module enable
+    u8                  I2CMaster;      //Master or Slave mode
+    u8                  I2CAddrMod;     //I2C addressing mode(7-bit, 10-bit)
+
+    u8                  I2CSpdMod;      //I2C  speed mode(Standard, Fast, High)
+    u8                  I2CSetup;       //I2C SDA setup time
+    u8                  I2CRXTL;        //I2C RX FIFO Threshold
+    u8                  I2CTXTL;        //I2C TX FIFO Threshold
+
+    u8                  I2CBusLd;       //I2C bus load (pf) for high speed mode
+    u8                  I2CReSTR;       //I2C restart support
+    u8                  I2CGC;          //I2C general support
+    u8                  I2CStartB;      //I2C start byte support
+
+    u8                  I2CSlvNoAck;    //I2C slave no ack support
+    u8                  I2CDMACtrl;     //I2C DMA feature support
+    u8                  I2CCmd;         //I2C Command
+    u8                  I2CDataLen;     //I2C Data Length
+
+    u8                  I2CSlvAckGC;    //I2C slave acks to General Call
+    u8                  I2CStop;        //I2C issues STOP bit or not
+    u16                 RSVD0;
+    
+    u8                  *I2CRWData;     //I2C Read/Write data pointer
+
+    u16                 I2CIntrMSK;     //I2C Interrupt Mask
+    u16                 I2CIntrClr;     //I2C Interrupt register to clear 
+
+    u16                 I2CAckAddr;     //I2C target address in I2C Master mode,
+                                        //ack address in I2C Slave mode    
+    u16                 I2CSdaHd;       //I2C SDA hold time
+
+    u32                 I2CClk;         //I2C bus clock (in kHz)
+
+    u8                  I2CTxDMARqLv;   //I2C TX DMA Empty Level
+    u8                  I2CRxDMARqLv;   //I2C RX DMA Full Level
+    u16                 RSVD1;          //Reserved
+}HAL_I2C_INIT_DAT,*PHAL_I2C_INIT_DAT;
+
+// I2C HAL Operations
+typedef struct _HAL_I2C_OP_ {
+    HAL_Status  (*HalI2CInit)       (VOID *Data);   //HAL I2C initialization
+    HAL_Status  (*HalI2CDeInit)     (VOID *Data);   //HAL I2C de-initialization
+    HAL_Status  (*HalI2CSend)       (VOID *Data);   //HAL I2C send
+    u8          (*HalI2CReceive)    (VOID *Data);   //HAL I2C receive
+    HAL_Status  (*HalI2CEnable)     (VOID *Data);   //HAL I2C enable module
+    HAL_Status  (*HalI2CIntrCtrl)   (VOID *Data);   //HAL I2C interrupt control
+    u32         (*HalI2CReadReg)    (VOID *Data, u8 I2CReg);//HAL I2C read register
+    HAL_Status  (*HalI2CWriteReg)   (VOID *Data, u8 I2CReg, u32 RegVal);//HAL I2C write register
+    HAL_Status  (*HalI2CSetCLK)     (VOID *Data);   //HAL I2C set bus clock
+    HAL_Status  (*HalI2CMassSend)   (VOID *Data);   //HAL I2C mass send
+    HAL_Status  (*HalI2CClrIntr)    (VOID *Data);   //HAL I2C clear interrupts
+    HAL_Status  (*HalI2CClrAllIntr) (VOID *Data);   //HAL I2C clear all interrupts
+    HAL_Status  (*HalI2CDMACtrl)    (VOID *Data);   //HAL I2C DMA control
+}HAL_I2C_OP, *PHAL_I2C_OP;
+//================= I2C HAL END   ===========================
+
+
+//================= I2C SAL START  ==========================
+//I2C SAL Macros
+
+//======================================================
+// I2C SAL related enumerations
+// I2C Extend Features
+typedef enum _I2C_EXD_SUPPORT_{
+    I2C_EXD_RESTART     =   0x1,            //BIT_0, RESTART bit
+    I2C_EXD_GENCALL     =   0x2,            //BIT_1, Master generates General Call. All "send" operations generate General Call addresss
+    I2C_EXD_STARTB      =   0x4,            //BIT_2, Using START BYTE, instead of START Bit
+    I2C_EXD_SLVNOACK    =   0x8,            //BIT_3, Slave no ack to master
+    I2C_EXD_BUS400PF    =   0x10,           //BIT_4, I2C bus loading is 400pf
+    I2C_EXD_SLVACKGC    =   0x20,           //BIT_5, Slave acks to a General Call
+    I2C_EXD_USER_REG    =   0x40,           //BIT_6, Using User Register Address
+    I2C_EXD_USER_TWOB   =   0x80,           //BIT_7, User Register Address is 2-byte
+    I2C_EXD_MTR_ADDR_RTY=   0x100,          //BIT_8, Master retries to send start condition and Slave address when the slave doesn't ack 
+                                            //         the address.
+    I2C_EXD_MTR_ADDR_UPD=   0x200,         //BIT_9, Master dynamically updates slave address
+    I2C_EXD_MTR_HOLD_BUS=   0x400,         //BIT_10, Master doesn't generate STOP when the FIFO is empty. This would make Master hold
+                                            //         the bus.
+}I2C_EXD_SUPPORT,*PI2C_EXD_SUPPORT;
+
+// I2C operation type
+typedef enum _I2C_OP_TYPE_ {
+    I2C_POLL_TYPE   =   0x0,
+    I2C_DMA_TYPE    =   0x1,
+    I2C_INTR_TYPE   =   0x2,
+}I2C_OP_TYPE, *PI2C_OP_TYPE;
+
+// I2C pinmux selection 
+typedef enum _I2C_PINMUX_ {
+    I2C_PIN_S0      =   0x0,
+    I2C_PIN_S1      =   0x1,
+    I2C_PIN_S2      =   0x2,
+    I2C_PIN_S3      =   0x3,    //Only valid for I2C0 and I2C3
+}I2C_PINMUX, *PI2C_PINMUX;
+
+// I2C module status 
+typedef enum _I2C_MODULE_STATUS_ {
+    I2C_DISABLE     =   0x0,
+    I2C_ENABLE      =   0x1,
+}I2C_MODULE_STATUS, *PI2C_MODULE_STATUS;
+
+// I2C device status 
+typedef enum _I2C_Device_STATUS_ {
+    I2C_STS_UNINITIAL   =   0x00,
+    I2C_STS_INITIALIZED =   0x01,
+    I2C_STS_IDLE        =   0x02,
+    
+    I2C_STS_TX_READY    =   0x03,    
+    I2C_STS_TX_ING      =   0x04,
+    
+    I2C_STS_RX_READY    =   0x05,
+    I2C_STS_RX_ING      =   0x06,
+
+    I2C_STS_ERROR       =   0x10,
+    I2C_STS_TIMEOUT     =   0x11, 
+}I2C_Device_STATUS, *PI2C_Device_STATUS;
+
+// I2C feature status 
+typedef enum _I2C_FEATURE_STATUS_{
+    I2C_FEATURE_DISABLED    =   0,
+    I2C_FEATURE_ENABLED     =   1,
+}I2C_FEATURE_STATUS,*PI2C_FEATURE_STATUS;
+
+// I2C device mode
+typedef enum _I2C_DEV_MODE_ {
+    I2C_SLAVE_MODE  =   0x0,
+    I2C_MASTER_MODE =   0x1,
+}I2C_DEV_MODE, *PI2C_DEV_MODE;
+
+// I2C Bus Transmit/Receive
+typedef enum _I2C_DIRECTION_ {
+    I2C_ONLY_TX     =   0x1,
+    I2C_ONLY_RX     =   0x2,
+    I2C_TXRX        =   0x3,
+}I2C_DIRECTION, *PI2C_DIRECTION;
+
+//I2C DMA module number
+typedef enum _I2C_DMA_MODULE_SEL_ {
+    I2C_DMA_MODULE_0    =   0x0,
+    I2C_DMA_MODULE_1    =   0x1
+}I2C_DMA_MODULE_SEL, *PI2C_DMA_MODULE_SEL;
+
+// I2C0 DMA peripheral number
+typedef enum _I2C0_DMA_PERI_NUM_ {
+    I2C0_DMA_TX_NUM =   0x8,
+    I2C0_DMA_RX_NUM =   0x9,
+}I2C0_DMA_PERI_NUM,*PI2C0_DMA_PERI_NUM;
+
+// I2C1 DMA peripheral number
+typedef enum _I2C1_DMA_PERI_NUM_ {
+    I2C1_DMA_TX_NUM =   0xA,
+    I2C1_DMA_RX_NUM =   0xB,
+}I2C1_DMA_PERI_NUM,*PI2C1_DMA_PERI_NUM;
+
+// I2C0 DMA module used
+typedef enum _I2C0_DMA_MODULE_ {
+    I2C0_DMA0   =   0x0,
+    I2C0_DMA1   =   0x1,
+}I2C0_DMA_MODULE,*PI2C0_DMA_MODULE;
+
+// I2C0 DMA module used
+typedef enum _I2C1_DMA_MODULE_ {
+    I2C1_DMA0   =   0x0,
+    I2C1_DMA1   =   0x1,
+}I2C1_DMA_MODULE,*PI2C1_DMA_MODULE;
+
+// I2C command type 
+typedef enum _I2C_COMMAND_TYPE_ {
+    I2C_WRITE_CMD   =   0x0,
+    I2C_READ_CMD    =   0x1,
+}I2C_COMMAND_TYPE,*PI2C_COMMAND_TYPE;
+
+// I2C STOP BIT 
+typedef enum _I2C_STOP_TYPE_ {
+    I2C_STOP_DIS    =   0x0,
+    I2C_STOP_EN     =   0x1,
+}I2C_STOP_TYPE, *PI2C_STOP_TYPE;
+
+// I2C error type 
+typedef enum _I2C_ERR_TYPE_ {
+    I2C_ERR_RX_UNDER    =   0x01,           //I2C RX FIFO Underflow
+    I2C_ERR_RX_OVER     =   0x02,           //I2C RX FIFO Overflow
+    I2C_ERR_TX_OVER     =   0x04,           //I2C TX FIFO Overflow
+    I2C_ERR_TX_ABRT     =   0x08,           //I2C TX terminated
+    I2C_ERR_SLV_TX_NACK =   0x10,           //I2C slave transmission terminated by master NACK, 
+                                            //but there are data in slave TX FIFO
+    I2C_ERR_USER_REG_TO =   0x20,
+
+    I2C_ERR_RX_CMD_TO   =   0x21,
+    I2C_ERR_RX_FF_TO    =   0x22,
+    I2C_ERR_TX_CMD_TO   =   0x23,
+    I2C_ERR_TX_FF_TO    =   0x24,
+
+    I2C_ERR_TX_ADD_TO   =   0x25,
+    I2C_ERR_RX_ADD_TO   =   0x26,
+}I2C_ERR_TYPE, *PI2C_ERR_TYPE;
+
+// I2C Time Out type
+typedef enum _I2C_TIMEOUT_TYPE_ {
+    I2C_TIMEOOUT_DISABLE    =   0x00,           
+    I2C_TIMEOOUT_ENDLESS    =   0xFFFFFFFF,
+}I2C_TIMEOUT_TYPE, *PI2C_TIMEOUT_TYPE;
+
+//======================================================
+// SAL I2C related data structures
+// I2C user callback adapter
+typedef struct _SAL_I2C_USERCB_ADPT_ {
+    VOID (*USERCB)      (VOID *Data);
+    u32  USERData;
+}SAL_I2C_USERCB_ADPT, *PSAL_I2C_USERCB_ADPT;
+
+// I2C user callback structure
+typedef struct _SAL_I2C_USER_CB_ {
+    PSAL_I2C_USERCB_ADPT    pTXCB;          //I2C Transmit Callback
+    PSAL_I2C_USERCB_ADPT    pTXCCB;         //I2C Transmit Complete Callback
+    PSAL_I2C_USERCB_ADPT    pRXCB;          //I2C Receive Callback
+    PSAL_I2C_USERCB_ADPT    pRXCCB;         //I2C Receive Complete Callback
+    PSAL_I2C_USERCB_ADPT    pRDREQCB;       //I2C Read Request Callback
+    PSAL_I2C_USERCB_ADPT    pERRCB;         //I2C Error Callback
+    PSAL_I2C_USERCB_ADPT    pDMATXCB;       //I2C DMA Transmit Callback
+    PSAL_I2C_USERCB_ADPT    pDMATXCCB;      //I2C DMA Transmit Complete Callback
+    PSAL_I2C_USERCB_ADPT    pDMARXCB;       //I2C DMA Receive Callback
+    PSAL_I2C_USERCB_ADPT    pDMARXCCB;      //I2C DMA Receive Complete Callback
+    PSAL_I2C_USERCB_ADPT    pGENCALLCB;     //I2C General Call Callback
+}SAL_I2C_USER_CB, *PSAL_I2C_USER_CB;
+
+// I2C Transmit Buffer
+typedef struct _SAL_I2C_TRANSFER_BUF_ {
+    u16     DataLen;                        //I2C Transmfer Length
+    u16     TargetAddr;                     //I2C Target Address. It's only valid in Master Mode.
+    u32     RegAddr;                        //I2C Register Address. It's only valid in Master Mode.
+    u32     RSVD;                           //
+    u8      *pDataBuf;                      //I2C Transfer Buffer Pointer
+}SAL_I2C_TRANSFER_BUF,*PSAL_I2C_TRANSFER_BUF;
+
+typedef struct _SAL_I2C_DMA_USER_DEF_ {
+    u8      TxDatSrcWdth;
+    u8      TxDatDstWdth;
+    u8      TxDatSrcBstSz;
+    u8      TxDatDstBstSz;
+    u8      TxChNo;
+    u8      RSVD0;
+    u16     RSVD1;
+    u8      RxDatSrcWdth;
+    u8      RxDatDstWdth;
+    u8      RxDatSrcBstSz;
+    u8      RxDatDstBstSz;
+    u8      RxChNo;
+    u8      RSVD2;
+    u16     RSVD3;
+}SAL_I2C_DMA_USER_DEF, *PSAL_I2C_DMA_USER_DEF;
+
+// RTK I2C OP
+typedef struct _RTK_I2C_OP_ {
+    HAL_Status (*Init)      (VOID *Data);
+    HAL_Status (*DeInit)    (VOID *Data);
+    HAL_Status (*Send)      (VOID *Data);
+    HAL_Status (*Receive)   (VOID *Data);
+    HAL_Status (*IoCtrl)    (VOID *Data);
+    HAL_Status (*PowerCtrl) (VOID *Data);    
+}RTK_I2C_OP, *PRTK_I2C_OP;
+
+// Software API Level I2C Handler 
+typedef struct _SAL_I2C_HND_ {
+    u8                      DevNum;             //I2C device number
+    u8                      PinMux;             //I2C pin mux seletion
+    u8                      OpType;             //I2C operation type selection
+    volatile u8             DevSts;             //I2C device status
+    
+    u8                      I2CMaster;          //I2C Master or Slave mode
+    u8                      I2CAddrMod;         //I2C 7-bit or 10-bit mode
+    u8                      I2CSpdMod;          //I2C SS/ FS/ HS speed mode
+    u8                      I2CAckAddr;         //I2C target address in Master 
+                                                //mode or ack address in Slave
+                                                //mode
+                                                
+    u16                     I2CClk;             //I2C bus clock
+    u8                      MasterRead;         //I2C Master Read Supported,
+                                                //An Address will be sent before
+                                                //read data back.
+                                                
+    u8                      I2CDmaSel;          //I2C DMA module select
+                                                //         0 for DMA0,
+                                                //         1 for DMA1
+    u8                      I2CTxDMARqLv;       //I2C TX DMA Empty Level
+    u8                      I2CRxDMARqLv;       //I2C RX DMA Full Level
+    u16                     RSVD0;              //Reserved
+
+    u32                     AddRtyTimeOut;      //I2C TimeOut Value for master send address retry
+                                                //(Originally Reserved.)
+    
+    u32                     I2CExd;             //I2C extended options:
+                                                //bit 0: I2C RESTART supported,
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 1: I2C General Call supported
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 2: I2C START Byte supported
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 3: I2C Slave-No-Ack
+                                                //         supported
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 4: I2C bus loading,
+                                                //          0 for 100pf, 
+                                                //          1  for 400pf
+                                                //bit 5: I2C slave ack to General
+                                                //         Call
+                                                //bit 6: I2C User register address
+                                                //bit 7: I2C 2-Byte User register
+                                                //         address
+                                                //bit 8: I2C slave address no ack retry,
+                                                //        It's only for Master mode,
+                                                //        when slave doesn't ack the
+                                                //        address
+                                                //bit 31~bit 8: Reserved
+    u32                     ErrType;            //
+    u32                     TimeOut;            //I2C IO Timeout count,  in ms
+                                                                            
+    PHAL_I2C_INIT_DAT       pInitDat;           //Pointer to I2C initial data struct
+    PSAL_I2C_TRANSFER_BUF   pTXBuf;             //Pointer to I2C TX buffer
+    PSAL_I2C_TRANSFER_BUF   pRXBuf;             //Pointer to I2C RX buffer
+    PSAL_I2C_USER_CB        pUserCB;            //Pointer to I2C User Callback
+    PSAL_I2C_DMA_USER_DEF   pDMAConf;           //Pointer to I2C User Define DMA config
+}SAL_I2C_HND, *PSAL_I2C_HND;
+
+
+
+//======================================================
+// I2C SAL Function Prototypes
+
+// For checking I2C input index valid or not
+static inline HAL_Status
+RtkI2CIdxChk(
+    IN  u8  I2CIdx
+)
+{
+    if (I2CIdx > I2C3_SEL)
+        return HAL_ERR_UNKNOWN;
+        
+    return HAL_OK;
+}
+#if 0
+//For checking I2C operation type valid or not
+static inline HAL_Status
+RtkI2COpTypeChk(
+    IN  VOID *Data
+)
+{
+    PSAL_I2C_HND    pSalI2CHND = (PSAL_I2C_HND) Data;
+
+    if (pSalI2CHND->OpType == I2C_POLL_TYPE)
+        return HAL_ERR_UNKNOWN;
+
+    if (pSalI2CHND->OpType == I2C_DMA_TYPE)
+        return HAL_ERR_UNKNOWN;
+
+    if (pSalI2CHND->OpType == I2C_INTR_TYPE)
+        return HAL_ERR_UNKNOWN;
+
+    pSalI2CHND = pSalI2CHND;
+    
+    return HAL_OK;
+}
+#endif
+//For checking I2C DMA available or not
+static inline HAL_Status
+RtkI2CDMAChk(
+    IN  VOID *Data
+)
+{
+    PSAL_I2C_HND    pSalI2CHND = (PSAL_I2C_HND) Data;
+
+    if (pSalI2CHND->OpType == I2C_DMA_TYPE) {
+        if (pSalI2CHND->DevNum >= I2C2_SEL)
+            return HAL_ERR_UNKNOWN;
+    }
+    else {
+        return HAL_ERR_UNKNOWN;
+    }
+
+    return HAL_OK;
+}
+
+//For checking I2C DMA available or not
+static inline HAL_Status
+RtkI2CDMAInitChk(
+    IN  VOID *Data
+)
+{
+    PSAL_I2C_HND    pSalI2CHND = (PSAL_I2C_HND) Data;
+
+    if (pSalI2CHND->OpType != I2C_DMA_TYPE) {
+        return HAL_ERR_UNKNOWN;
+    }
+    else {
+        return HAL_OK;
+    }
+    
+}
+
+//======================================================
+//SAL I2C management function prototype
+_LONG_CALL_ROM_ HAL_Status RtkI2CLoadDefault(IN VOID *Data);
+_LONG_CALL_ROM_ HAL_Status RtkI2CInit(IN  VOID *Data);
+_LONG_CALL_ROM_ HAL_Status RtkI2CDeInit(IN  VOID *Data);
+_LONG_CALL_ROM_ HAL_Status RtkI2CSend(IN  VOID *Data);
+_LONG_CALL_ROM_ HAL_Status RtkI2CReceive(IN  VOID *Data);
+_LONG_CALL_ROM_ VOID RtkSalI2COpInit(IN  VOID *Data);
+_LONG_CALL_ROM_ HAL_Status RtkI2CSendUserAddr(IN  VOID *Data,IN  u8  MtrWr);
+_LONG_CALL_ROM_ HAL_Status RtkI2CIoCtrl(IN  VOID *Data);
+_LONG_CALL_ROM_ HAL_Status RtkI2CPowerCtrl(IN  VOID *Data);
+_LONG_CALL_ HAL_Status RtkI2CInitForPS(IN  VOID *Data);
+_LONG_CALL_ HAL_Status RtkI2CDeInitForPS(IN  VOID *Data);
+_LONG_CALL_ HAL_Status RtkI2CDisablePS(IN  VOID *Data);
+_LONG_CALL_ HAL_Status RtkI2CEnablePS(IN  VOID *Data);
+//================= I2C SAL END   ===========================
+
+
+//================= I2C SAL MANAGEMENT START  =================
+// I2C SAL management macros
+#define SAL_USER_CB_NUM     (sizeof(SAL_I2C_USER_CB) / sizeof(PSAL_I2C_USERCB_ADPT))
+
+//======================================================
+// I2C SAL management data structures
+// I2C SAL handle private 
+typedef struct _SAL_I2C_HND_PRIV_ {
+    VOID            **ppSalI2CHnd;              //Pointer to SAL_I2C_HND pointer
+    SAL_I2C_HND     SalI2CHndPriv;              //Private SAL_I2C_HND
+}SAL_I2C_HND_PRIV, *PSAL_I2C_HND_PRIV;
+
+//I2C SAL management adapter
+typedef struct _SAL_I2C_MNGT_ADPT_ {
+    PSAL_I2C_HND_PRIV       pSalHndPriv;                //Pointer to SAL_I2C_HND
+    PHAL_I2C_INIT_DAT       pHalInitDat;                //Pointer to HAL I2C initial data( HAL_I2C_INIT_DAT )
+    PHAL_I2C_OP             pHalOp;                     //Pointer to HAL I2C operation( HAL_I2C_OP )
+    VOID                    (*pHalOpInit)(VOID*);       //Pointer to HAL I2C initialize function
+    PIRQ_HANDLE             pIrqHnd;                    //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
+    PSAL_I2C_USER_CB        pUserCB;                    //Pointer to SAL user callbacks (SAL_I2C_USER_CB )
+    volatile u32            MstRDCmdCnt;                //Used for Master Read command count
+    volatile u32            InnerTimeOut;               //Used for SAL internal timeout count
+    VOID                    (*pSalIrqFunc)(VOID*);      //Used for SAL I2C interrupt function
+    
+    PSAL_I2C_DMA_USER_DEF   pDMAConf;                   //Pointer to I2C User Define DMA config
+    PHAL_GDMA_ADAPTER       pHalTxGdmaAdp;              //Pointer to HAL_GDMA_ADAPTER
+    PHAL_GDMA_ADAPTER       pHalRxGdmaAdp;              //Pointer to HAL_GDMA_ADAPTER
+    PHAL_GDMA_OP            pHalGdmaOp;                 //Pointer to HAL_GDMA_OP
+    VOID                    (*pHalGdmaOpInit)(VOID*);   //Pointer to HAL I2C initialize function
+    PIRQ_HANDLE             pIrqTxGdmaHnd;              //Pointer to IRQ handler for Tx GDMA
+    PIRQ_HANDLE             pIrqRxGdmaHnd;              //Pointer to IRQ handler for Rx GDMA
+    VOID                    (*pSalDMATxIrqFunc)(VOID*); //Used for SAL I2C interrupt function
+    VOID                    (*pSalDMARxIrqFunc)(VOID*); //Used for SAL I2C interrupt function
+    u32                     RSVD;                       //Reserved
+}SAL_I2C_MNGT_ADPT, *PSAL_I2C_MNGT_ADPT;
+
+//======================================================
+//SAL I2C management function prototype
+PSAL_I2C_MNGT_ADPT RtkI2CGetMngtAdpt(IN u8 I2CIdx);
+HAL_Status RtkI2CFreeMngtAdpt(IN  PSAL_I2C_MNGT_ADPT  pSalI2CMngtAdpt);
+PSAL_I2C_HND RtkI2CGetSalHnd(IN  u8  I2CIdx);
+HAL_Status RtkI2CFreeSalHnd(IN  PSAL_I2C_HND    pSalI2CHND);
+u32 RtkSalI2CSts(IN  VOID *Data);
+
+extern _LONG_CALL_ VOID I2CISRHandle(IN  VOID *Data);
+extern _LONG_CALL_ VOID I2CTXGDMAISRHandle(IN  VOID *Data);
+extern _LONG_CALL_ VOID I2CRXGDMAISRHandle(IN  VOID *Data);
+extern HAL_Status I2CIsTimeout (IN  u32 StartCount, IN  u32 TimeoutCnt);
+extern HAL_TIMER_OP        HalTimerOp;
+//======================================================
+// Function Prototypes
+_LONG_CALL_ VOID HalI2COpInit(IN VOID *Data);
+//================= I2C SAL MANAGEMENT END   ==================
+
+//================= Rtl8195a I2C V02 function prototype  ============
+_LONG_CALL_ VOID HalI2COpInitV02(IN  VOID *Data);
+_LONG_CALL_ VOID I2CISRHandleV02(IN  VOID *Data);
+_LONG_CALL_ HAL_Status RtkI2CSendV02(IN  VOID *Data);
+_LONG_CALL_ HAL_Status RtkI2CReceiveV02(IN  VOID *Data);
+_LONG_CALL_ VOID RtkSalI2COpInitV02(IN  VOID *Data);
+//================= Rtl8195a I2C V02 function prototype  END==========
+
+//======================================================
+//SAL I2C patch function prototype
+HAL_Status RtkI2CSend_Patch(IN  VOID *Data);
+HAL_Status RtkI2CReceive_Patch(IN  VOID *Data);
+VOID HalI2COpInit_Patch(IN VOID *Data);
+VOID I2CISRHandle_Patch(IN  VOID *Data);
+
+#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
+#define RtkI2CSend RtkI2CSend_Patch
+#define RtkI2CReceive RtkI2CReceive_Patch
+#endif
+HAL_Status RtkI2CSend_Patch(IN  VOID *Data);
+HAL_Status RtkI2CReceive_Patch(IN  VOID *Data);
+//================= I2C SAL END   ===========================
+
+#endif                  //#ifndef _HAL_I2C_H_

sdk/component/soc/realtek/8195a/fwlib/hal_i2s.h

@@ -0,0 +1,347 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_I2S_H_
+#define _HAL_I2S_H_
+
+#include "rtl8195a_i2s.h"
+
+/* User Define Flags */
+
+#define I2S_MAX_ID                  1   // valid I2S index 0 ~ I2S_MAX_ID
+
+/**********************************************************************/
+/* I2S HAL initial data structure */
+typedef struct _HAL_I2S_INIT_DAT_ {
+    u8                  I2SIdx;         /*I2S index used*/
+    u8                  I2SEn;          /*I2S module enable tx/rx/tx+rx*/
+    u8                  I2SMaster;      /*I2S Master or Slave mode*/
+    u8                  I2SWordLen;     /*I2S Word length 16 or 24bits*/
+
+    u8                  I2SChNum;       /*I2S Channel number mono or stereo*/
+    u8                  I2SPageNum;     /*I2S Page Number 2~4*/
+    u16                 I2SPageSize;    /*I2S page Size 1~4096 word*/
+
+    u8                  *I2STxData;     /*I2S Tx data pointer*/
+
+    u8                  *I2SRxData;     /*I2S Rx data pointer*/
+
+    u32                 I2STxIntrMSK;   /*I2S Tx Interrupt Mask*/
+    u32                 I2STxIntrClr;   /*I2S Tx Interrupt register to clear */
+
+    u32                 I2SRxIntrMSK;   /*I2S Rx Interrupt Mask*/
+    u32                 I2SRxIntrClr;   /*I2S Rx Interrupt register to clear*/
+
+	u16                 I2STxIdx;       /*I2S TX page index */
+	u16                 I2SRxIdx;       /*I2S RX page index */
+
+	u16                 I2SHWTxIdx;       /*I2S HW TX page index */
+	u16                 I2SHWRxIdx;       /*I2S HW RX page index */
+
+	
+    u16                 I2SRate;        /*I2S sample rate*/
+    u8                  I2STRxAct;      /*I2S tx rx act*/	
+}HAL_I2S_INIT_DAT, *PHAL_I2S_INIT_DAT;
+
+/**********************************************************************/
+/* I2S Data Structures */
+/* I2S Module Selection */
+typedef enum _I2S_MODULE_SEL_ {
+        I2S0_SEL    =   0x0,
+        I2S1_SEL    =   0x1,
+}I2S_MODULE_SEL,*PI2S_MODULE_SEL;
+/*
+typedef struct _HAL_I2S_ADAPTER_ {
+    u32                       Enable:1;
+    I2S_CTL_REG               I2sCtl;
+    I2S_SETTING_REG           I2sSetting;
+    u32                       abc;
+    u8                        I2sIndex;
+}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER;
+*/
+/* I2S HAL Operations */
+typedef struct _HAL_I2S_OP_ {
+    RTK_STATUS  (*HalI2SInit)       (VOID *Data);
+    RTK_STATUS  (*HalI2SDeInit)     (VOID *Data);
+    RTK_STATUS  (*HalI2STx)       (VOID *Data, u8 *pBuff);
+    RTK_STATUS  (*HalI2SRx)       (VOID *Data, u8 *pBuff);
+    RTK_STATUS  (*HalI2SEnable)     (VOID *Data);
+    RTK_STATUS  (*HalI2SIntrCtrl)   (VOID *Data);
+    u32         (*HalI2SReadReg)    (VOID *Data, u8 I2SReg);
+    RTK_STATUS  (*HalI2SSetRate)    (VOID *Data);
+    RTK_STATUS  (*HalI2SSetWordLen) (VOID *Data);
+    RTK_STATUS  (*HalI2SSetChNum)   (VOID *Data);
+    RTK_STATUS  (*HalI2SSetPageNum) (VOID *Data);
+    RTK_STATUS  (*HalI2SSetPageSize) (VOID *Data);
+
+    RTK_STATUS  (*HalI2SClrIntr)    (VOID *Data);
+    RTK_STATUS  (*HalI2SClrAllIntr) (VOID *Data);
+    RTK_STATUS  (*HalI2SDMACtrl)    (VOID *Data); 
+/*
+    VOID (*HalI2sOnOff)(VOID *Data);
+    BOOL (*HalI2sInit)(VOID *Data);
+    BOOL (*HalI2sSetting)(VOID *Data);
+    BOOL (*HalI2sEn)(VOID *Data);
+    BOOL (*HalI2sIsrEnAndDis) (VOID *Data);
+    BOOL (*HalI2sDumpReg)(VOID *Data);
+    BOOL (*HalI2s)(VOID *Data);
+*/
+}HAL_I2S_OP, *PHAL_I2S_OP;
+
+
+/**********************************************************************/
+
+/* I2S Pinmux Selection */
+#if 0
+typedef enum _I2S0_PINMUX_ {
+    I2S0_TO_S0      =   0x0,
+    I2S0_TO_S1      =   0x1,
+    I2S0_TO_S2      =   0x2,
+}I2S0_PINMUX, *PI2S0_PINMUX;
+
+typedef enum _I2S1_PINMUX_ {
+    I2S1_TO_S0      =   0x0,
+    I2S1_TO_S1      =   0x1,
+}I2S1_PINMUX, *PI2S1_PINMUX;
+#endif
+
+typedef enum _I2S_PINMUX_ {
+    I2S_S0      =   0,
+    I2S_S1      =   1,
+    I2S_S2      =   2,
+    I2S_S3      =   3
+}I2S_PINMUX, *PI2S_PINMUX;
+
+
+/* I2S Module Status */
+typedef enum _I2S_MODULE_STATUS_ {
+    I2S_DISABLE     =   0x0,
+    I2S_ENABLE      =   0x1,
+}I2S_MODULE_STATUS, *PI2S_MODULE_STATUS;
+
+
+/* I2S Device Status */
+typedef enum _I2S_Device_STATUS_ {
+    I2S_STS_UNINITIAL   =   0x00,
+    I2S_STS_INITIALIZED =   0x01,
+    I2S_STS_IDLE        =   0x02,
+    
+    I2S_STS_TX_READY    =   0x03,    
+    I2S_STS_TX_ING      =   0x04,
+    
+    I2S_STS_RX_READY    =   0x05,
+    I2S_STS_RX_ING      =   0x06,
+
+    I2S_STS_TRX_READY   =   0x07,    
+    I2S_STS_TRX_ING     =   0x08,
+    
+    I2S_STS_ERROR       =   0x09,
+}I2S_Device_STATUS, *PI2S_Device_STATUS;
+
+
+/* I2S Feature Status */
+typedef enum _I2S_FEATURE_STATUS_{
+    I2S_FEATURE_DISABLED    =   0,
+    I2S_FEATURE_ENABLED     =   1,
+}I2S_FEATURE_STATUS,*PI2S_FEATURE_STATUS;
+
+/* I2S Device Mode */
+typedef enum _I2S_DEV_MODE_ {
+	I2S_MASTER_MODE =   0x0,
+    I2S_SLAVE_MODE  =   0x1
+}I2S_DEV_MODE, *PI2S_DEV_MODE;
+
+/* I2S Word Length */
+typedef enum _I2S_WORD_LEN_ {
+	I2S_WL_16 = 0x0,
+    I2S_WL_24 = 0x1,    
+}I2S_WORD_LEN, *PI2S_WORD_LEN;
+
+/* I2S Bus Transmit/Receive */
+typedef enum _I2S_DIRECTION_ {
+    I2S_ONLY_RX     =   0x0,
+    I2S_ONLY_TX     =   0x1,
+    I2S_TXRX        =   0x2
+}I2S_DIRECTION, *PI2S_DIRECTION;
+
+/* I2S Channel number */
+typedef enum _I2S_CH_NUM_ {
+    I2S_CH_STEREO   =   0x0,
+    I2S_CH_RSVD     =   0x1,
+    I2S_CH_MONO     =   0x2
+}I2S_CH_NUM, *PI2S_CH_NUM;
+
+/* I2S Page number */
+typedef enum _I2S_PAGE_NUM_ {
+    I2S_1PAGE       =   0x0,
+    I2S_2PAGE       =   0x1,
+    I2S_3PAGE       =   0x2,
+    I2S_4PAGE       =   0x3
+}I2S_PAGE_NUM, *PI2S_PAGE_NUM;
+
+/* I2S Sample rate*/
+typedef enum _I2S_SAMPLE_RATE_ {
+    I2S_SR_8KHZ     =   0x00,	// /12
+    I2S_SR_16KHZ    =   0x01,	// /6
+    I2S_SR_24KHZ    =   0x02,	// /4
+	I2S_SR_32KHZ	= 	0x03,	// /3
+    I2S_SR_48KHZ    =   0x05,	// /2
+	I2S_SR_96KHZ	=	0x06,	// x1, base 96kHz
+	I2S_SR_7p35KHZ	= 	0x10,
+	I2S_SR_11p02KHZ	= 	0x11,
+	I2S_SR_22p05KHZ	= 	0x12,
+	I2S_SR_29p4KHZ	= 	0x13,
+	I2S_SR_44p1KHZ	= 	0x15,	
+	I2S_SR_88p2KHZ	= 	0x16	// x1, base 88200Hz
+}I2S_SAMPLE_RATE, *PI2S_SAMPLE_RATE;
+
+/* I2S TX interrupt mask/status */
+typedef enum _I2S_TX_IMR_ {
+    I2S_TX_INT_PAGE0_OK = (1<<0),
+    I2S_TX_INT_PAGE1_OK = (1<<1),
+    I2S_TX_INT_PAGE2_OK = (1<<2),
+    I2S_TX_INT_PAGE3_OK = (1<<3),
+    I2S_TX_INT_FULL     = (1<<4),
+    I2S_TX_INT_EMPTY    = (1<<5)    
+} I2S_TX_IMR, *PI2S_TX_IMR;
+
+/* I2S RX interrupt mask/status */
+typedef enum _I2S_RX_IMR_ {
+    I2S_RX_INT_PAGE0_OK = (1<<0),
+    I2S_RX_INT_PAGE1_OK = (1<<1),
+    I2S_RX_INT_PAGE2_OK = (1<<2),
+    I2S_RX_INT_PAGE3_OK = (1<<3),
+    I2S_RX_INT_EMPTY    = (1<<4),
+    I2S_RX_INT_FULL     = (1<<5)    
+} I2S_RX_IMR, *PI2S_RX_IMR;
+
+/* I2S User Callbacks */
+typedef struct _SAL_I2S_USER_CB_{
+    VOID (*TXCB)        (VOID *Data);
+    VOID (*TXCCB)       (VOID *Data);
+    VOID (*RXCB)        (VOID *Data);
+    VOID (*RXCCB)       (VOID *Data);
+    VOID (*RDREQCB)     (VOID *Data);
+    VOID (*ERRCB)       (VOID *Data);
+    VOID (*GENCALLCB)   (VOID *Data);
+}SAL_I2S_USER_CB,*PSAL_I2S_USER_CB;
+
+typedef struct _I2S_USER_CB_{
+    VOID (*TxCCB)(uint32_t id, char *pbuf);
+    u32 TxCBId;
+    VOID (*RxCCB)(uint32_t id, char *pbuf);
+    u32 RxCBId;
+}I2S_USER_CB,*PI2S_USER_CB;
+
+/* Software API Level I2S Handler */
+typedef struct _HAL_I2S_ADAPTER_{
+    u8                      DevNum;             //I2S device number
+    u8                      PinMux;             //I2S pin mux seletion
+    u8                      RSVD0;              //Reserved
+    volatile u8             DevSts;             //I2S device status
+    
+    u32                     RSVD2;              //Reserved
+    u32                     I2SExd;             //I2S extended options:
+                                                //bit 0: I2C RESTART supported,
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 1: I2C General Call supported
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 2: I2C START Byte supported
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 3: I2C Slave-No-Ack
+                                                //         supported
+                                                //          0 for NOT supported,
+                                                //          1 for supported
+                                                //bit 4: I2C bus loading,
+                                                //          0 for 100pf, 
+                                                //          1  for 400pf
+                                                //bit 5: I2C slave ack to General
+                                                //         Call
+                                                //bit 6: I2C User register address
+                                                //bit 7: I2C 2-Byte User register
+                                                //         address
+                                                //bit 31~bit 8: Reserved
+    u32                     ErrType;         //
+    u32                     TimeOut;            //I2S IO Timeout count
+                                                                            
+    PHAL_I2S_INIT_DAT       pInitDat;           //Pointer to I2S initial data struct
+    I2S_USER_CB             UserCB;            //Pointer to I2S User Callback
+    IRQ_HANDLE              IrqHandle;          // Irq Handler
+
+    u32* TxPageList[4];       // The Tx DAM buffer: pointer of each page
+    u32* RxPageList[4];       // The Tx DAM buffer: pointer of each page
+}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER;
+
+typedef struct _HAL_I2S_DEF_SETTING_{
+    u8 I2SMaster;           // Master or Slave mode
+    u8 DevSts;             //I2S device status
+    u8 I2SChNum;           //I2S Channel number mono or stereo
+    u8 I2SPageNum;         //I2S Page number 2~4
+    u8  I2STRxAct;          //I2S tx rx act, tx only or rx only or tx+rx
+    u8  I2SWordLen;         //I2S Word length 16bit or 24bit
+    u16 I2SPageSize;        //I2S Page size 1~4096 word
+                                                
+    u16 I2SRate;            //I2S sample rate 8k ~ 96khz
+    
+    u32 I2STxIntrMSK;   /*I2S Tx Interrupt Mask*/
+    u32 I2SRxIntrMSK;   /*I2S Rx Interrupt Mask*/
+}HAL_I2S_DEF_SETTING, *PHAL_I2S_DEF_SETTING;
+
+
+
+/**********************************************************************/
+HAL_Status
+RtkI2SLoadDefault(IN  VOID *Adapter, IN  VOID *Setting);
+
+HAL_Status
+RtkI2SInit(IN  VOID *Data);
+
+HAL_Status
+RtkI2SDeInit(IN  VOID *Data);
+
+HAL_Status
+RtkI2SEnable(IN  VOID *Data);
+
+HAL_Status
+RtkI2SDisable(IN  VOID *Data);
+
+extern HAL_Status 
+HalI2SInit( IN VOID *Data);
+
+extern VOID 
+HalI2SDeInit( IN VOID *Data);
+
+extern HAL_Status 
+HalI2SDisable( IN VOID *Data);
+
+extern HAL_Status 
+HalI2SEnable( IN VOID *Data);
+
+
+
+
+/**********************************************************************/
+
+
+VOID I2S0ISRHandle(VOID *Data);
+VOID I2S1ISRHandle(VOID *Data);
+
+
+/**********************************************************************/
+
+VOID HalI2SOpInit(
+    IN  VOID *Data
+);
+
+
+#endif
+

sdk/component/soc/realtek/8195a/fwlib/hal_irqn.h

@@ -0,0 +1,112 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_IRQN_H_
+#define _HAL_IRQN_H_
+
+#define PERIPHERAL_IRQ_BASE_NUM     64
+
+typedef enum _IRQn_Type_ {
+#if 0
+/******  Cortex-M3 Processor Exceptions Numbers ********/  
+    NON_MASKABLE_INT_IRQ            = -14,
+    HARD_FAULT_IRQ                  = -13,
+    MEM_MANAGE_FAULT_IRQ            = -12,
+    BUS_FAULT_IRQ                   = -11,
+    USAGE_FAULT_IRQ                 = -10,
+    SVCALL_IRQ                      = -5,
+    DEBUG_MONITOR_IRQ               = -4,
+    PENDSVC_IRQ                     = -2,
+    SYSTICK_IRQ                     = -1,
+#else    
+/******  Cortex-M3 Processor Exceptions Numbers ********/  
+    NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt                         */
+    HardFault_IRQn                  = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
+    MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
+    BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
+    UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
+    SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
+    DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
+    PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
+    SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
+#endif
+/******  RTL8195A Specific Interrupt Numbers ************/
+    SYSTEM_ON_IRQ                   =  0,
+    WDG_IRQ                         =  1,
+    TIMER0_IRQ                      =  2,
+    TIMER1_IRQ                      =  3,
+    I2C3_IRQ                        =  4,
+    TIMER2_7_IRQ                    =  5,
+    SPI0_IRQ                        =  6,
+    GPIO_IRQ                        =  7,
+    UART0_IRQ                       =  8,
+    SPI_FLASH_IRQ                   =  9,
+    USB_OTG_IRQ                     =  10,
+    SDIO_HOST_IRQ                   =  11,
+    SDIO_DEVICE_IRQ                 =  12,
+    I2S0_PCM0_IRQ                   =  13,
+    I2S1_PCM1_IRQ                   =  14,
+    WL_DMA_IRQ                      =  15,
+    WL_PROTOCOL_IRQ                 =  16,
+    CRYPTO_IRQ                      =  17,
+    GMAC_IRQ						=  18,
+    PERIPHERAL_IRQ                  =  19,
+    GDMA0_CHANNEL0_IRQ              =  20,
+    GDMA0_CHANNEL1_IRQ              =  21,
+    GDMA0_CHANNEL2_IRQ              =  22,
+    GDMA0_CHANNEL3_IRQ              =  23,
+    GDMA0_CHANNEL4_IRQ              =  24,
+    GDMA0_CHANNEL5_IRQ              =  25,
+    GDMA1_CHANNEL0_IRQ              =  26,
+    GDMA1_CHANNEL1_IRQ              =  27,
+    GDMA1_CHANNEL2_IRQ              =  28,
+    GDMA1_CHANNEL3_IRQ              =  29,
+    GDMA1_CHANNEL4_IRQ              =  30,
+    GDMA1_CHANNEL5_IRQ              =  31,
+
+/******  RTL8195A Peripheral Interrupt Numbers ************/
+    I2C0_IRQ                        =  64,// 0 + 64,
+    I2C1_IRQ                        =  65,// 1 + 64,
+    I2C2_IRQ                        =  66,// 2 + 64,
+    SPI1_IRQ                        =  72,// 8 + 64,
+    SPI2_IRQ                        =  73,// 9 + 64,
+    UART1_IRQ                       =  80,// 16 + 64,
+    UART2_IRQ                       =  81,// 17 + 64,
+    UART_LOG_IRQ                    =  88,// 24 + 64,
+    ADC_IRQ                         =  89,// 25 + 64,
+    DAC0_IRQ                        =  91,// 27 + 64,
+    DAC1_IRQ                        =  92,// 28 + 64,
+    //RXI300_IRQ                      =  93// 29 + 64
+    LP_EXTENSION_IRQ                =  93,// 29+64
+    
+    PTA_TRX_IRQ                     =  95,// 31+64
+    RXI300_IRQ                      =  96,// 0+32 + 64
+    NFC_IRQ                         =  97// 1+32+64
+} IRQn_Type, *PIRQn_Type;
+
+
+typedef VOID (*HAL_VECTOR_FUN) (VOID);
+
+typedef enum _VECTOR_TABLE_TYPE_{
+    DEDECATED_VECTRO_TABLE,
+    PERIPHERAL_VECTOR_TABLE
+}VECTOR_TABLE_TYPE, *PVECTOR_TABLE_TYPE;
+
+
+typedef u32 (*IRQ_FUN)(VOID *Data);
+
+typedef struct _IRQ_HANDLE_ {
+    IRQ_FUN     IrqFun;
+    IRQn_Type   IrqNum;
+    u32         Data;
+    u32         Priority;
+}IRQ_HANDLE, *PIRQ_HANDLE;
+
+
+#endif //_HAL_IRQN_H_

sdk/component/soc/realtek/8195a/fwlib/hal_log_uart.h

@@ -0,0 +1,150 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_LOG_UART_H_
+#define _HAL_LOG_UART_H_
+
+#include "hal_diag.h"
+
+#define LOG_UART_WAIT_FOREVER       0xffffffff
+
+// Define Line Control Register Bits
+typedef enum {
+    LCR_DLS_5B = 0,      // Data Length: 5 bits
+    LCR_DLS_6B = BIT(0),      // Data Length: 6 bits
+    LCR_DLS_7B = BIT(1),      // Data Length: 7 bits
+    LCR_DLS_8B = (BIT(1)|BIT(0)),      // Data Length: 7 bits
+
+    LCR_STOP_1B = 0,      // Number of stop bits: 1
+    LCR_STOP_2B = BIT(2), // Number of stop bits: 1.5(data len=5) or 2
+
+    LCR_PARITY_NONE = 0,      // Parity Enable: 0
+    LCR_PARITY_ODD = BIT(3),      // Parity Enable: 1, Even Parity: 0
+    LCR_PARITY_EVEN = (BIT(4)|BIT(3)), // Parity Enable: 1, Even Parity: 1
+
+    LCR_BC = BIT(6),      // Break Control Bit
+    LCR_DLAB = BIT(7)      // Divisor Latch Access Bit
+} LOG_UART_LINE_CTRL;
+
+// define Log UART Interrupt Indication ID
+/*
+IIR[3:0]:
+0000 = modem status
+0001 = no interrupt pending
+0010 = THR empty
+0100 = received data available
+0110 = receiver line status
+0111 = busy detect
+1100 = character timeout
+*/
+typedef enum {
+    IIR_MODEM_STATUS = 0,   //Clear to send or data set ready or ring indicator or data carrier detect.
+    IIR_NO_PENDING = 1,
+    IIR_THR_EMPTY = 2,   // TX FIFO level lower than threshold or FIFO empty
+    IIR_RX_RDY = 4,     // RX data ready
+    IIR_RX_LINE_STATUS = 6, // Overrun/parity/framing errors or break interrupt
+    IIR_BUSY = 7,
+    IIR_CHAR_TIMEOUT = 12   // timeout: Rx dara ready but no read 
+} LOG_UART_INT_ID;
+
+// Define Interrupt Enable Bit
+typedef enum {
+    IER_ERBFI = BIT(0),   // Enable Received Data Available Interrupt
+    IER_ETBEI = BIT(1),   // Enable Transmit Holding Register Empty Interrupt
+    IER_ELSI =  BIT(2),   // Enable Receiver Line Status Interrupt
+    IER_EDSSI = BIT(3),   // Enable Modem Status Interrupt
+    IER_PTIME = BIT(7)    // Programmable THRE Interrupt Mode Enable
+} LOG_UART_INT_EN;
+
+// Define Line Status Bit
+typedef enum {
+    LSR_DR =   BIT(0),   // Data Ready bit
+    LSR_OE =   BIT(1),   // Overrun error bit
+    LSR_PE =   BIT(2),   // Parity Error bit
+    LSR_FE =   BIT(3),   // Framing Error bit
+    LSR_BI =   BIT(4),   // Break Interrupt bit
+    LSR_THRE = BIT(5),   // Transmit Holding Register Empty bit(IER_PTIME=0)
+    LSR_FIFOF = BIT(5),  // Transmit FIFO Full bit(IER_PTIME=1)
+    LSR_TEMT = BIT(6),   // Transmitter Empty bit 
+    LSR_RFE =  BIT(7)    // Receiver FIFO Error bit    
+} LOG_UART_LINE_STATUS;
+
+enum {
+    LOG_UART_RST_TX_FIFO = 0x01,
+    LOG_UART_RST_RX_FIFO = 0x02
+};
+
+#define LOG_UART_TX_FIFO_DEPTH      16
+#define LOG_UART_RX_FIFO_DEPTH      16
+
+// Define FIFO Control Register Bits
+typedef enum {
+    FCR_FIFO_EN      = BIT(0),   // FIFO Enable.
+    FCR_RST_RX       = BIT(1),   // RCVR FIFO Reset, self clear
+    FCR_RST_TX       = BIT(2),   // XMIT FIFO Reset, self clear
+    FCR_TX_TRIG_EMP  = 0,        // TX Empty Trigger: FIFO empty
+    FCR_TX_TRIG_2CH  = BIT(4),   // TX Empty Trigger: 2 characters in the FIFO
+    FCR_TX_TRIG_QF   = BIT(5),   // TX Empty Trigger: FIFO 1/4 full
+    FCR_TX_TRIG_HF   = (BIT(5)|BIT(4)),   // TX Empty Trigger: FIFO 1/2 full
+    FCR_TX_TRIG_MASK = (BIT(5)|BIT(4)),   // TX Empty Trigger Bit Mask
+    FCR_RX_TRIG_1CH  = 0,        // RCVR Trigger: 1 character in the FIFO
+    FCR_RX_TRIG_QF   = BIT(6),   // RCVR Trigger: FIFO 1/4 full
+    FCR_RX_TRIG_HF   = BIT(7),   // RCVR Trigger: FIFO 1/2 full
+    FCR_RX_TRIG_AF   = (BIT(7)|BIT(6)),  // RCVR Trigger: FIFO 2 less than full
+    FCR_RX_TRIG_MASK = (BIT(7)|BIT(6))   // RCVR Trigger bits Mask
+} LOG_UART_FIFO_CTRL;
+
+typedef struct _HAL_LOG_UART_ADAPTER_ {
+    u32 BaudRate;
+    u32 FIFOControl; 
+    u32 IntEnReg;
+    u8 Parity;
+    u8 Stop;
+    u8 DataLength;
+
+    u8 LineStatus;
+    volatile u32 TxCount;     // how many byte to TX
+    volatile u32 RxCount;     // how many bytes to RX
+    volatile u8 *pTxBuf;
+    volatile u8 *pRxBuf;
+    u8 *pTxStartAddr;
+    u8 *pRxStartAddr;
+
+    IRQ_HANDLE IrqHandle;
+    VOID (*LineStatusCallback)(VOID *para, u8 status);    // User Line Status interrupt callback
+    VOID (*TxCompCallback)(VOID *para);    // User Tx complete callback
+    VOID (*RxCompCallback)(VOID *para);    // User Rx complete callback
+    VOID *LineStatusCbPara; // the argument for LineStatusCallback
+    VOID *TxCompCbPara; // the argument for TxCompCallback
+    VOID *RxCompCbPara; // the argument for RxCompCallback
+
+    void (*api_irq_handler)(u32 id, LOG_UART_INT_ID event);
+    u32 api_irq_id;
+}HAL_LOG_UART_ADAPTER, *PHAL_LOG_UART_ADAPTER;
+
+VOID HalLogUartIrqHandle(VOID * Data);
+VOID HalLogUartSetBaudRate(HAL_LOG_UART_ADAPTER *pUartAdapter);
+VOID HalLogUartSetLineCtrl(HAL_LOG_UART_ADAPTER *pUartAdapter);
+VOID HalLogUartSetIntEn(HAL_LOG_UART_ADAPTER *pUartAdapter);
+u32 HalLogUartInitSetting(HAL_LOG_UART_ADAPTER *pUartAdapter);
+u32 HalLogUartRecv(HAL_LOG_UART_ADAPTER *pUartAdapter,
+                    u8  *pRxData, u32 Length, u32 TimeoutMS);
+u32 HalLogUartSend(HAL_LOG_UART_ADAPTER *pUartAdapter,
+        u8 *pTxData, u32 Length, u32 TimeoutMS);
+HAL_Status HalLogUartIntSend(HAL_LOG_UART_ADAPTER *pUartAdapter,
+        u8 *pTxData, u32 Length);
+HAL_Status HalLogUartIntRecv(HAL_LOG_UART_ADAPTER *pUartAdapter,
+        u8  *pRxData, u32 Length);
+VOID HalLogUartAbortIntSend(HAL_LOG_UART_ADAPTER *pUartAdapter);
+VOID HalLogUartAbortIntRecv(HAL_LOG_UART_ADAPTER *pUartAdapter);
+HAL_Status HalLogUartRstFIFO(HAL_LOG_UART_ADAPTER *pUartAdapter, u8 RstCtrl);
+VOID HalLogUartEnable(HAL_LOG_UART_ADAPTER *pUartAdapter);
+VOID HalLogUartDisable(HAL_LOG_UART_ADAPTER *pUartAdapter);
+
+#endif

sdk/component/soc/realtek/8195a/fwlib/hal_misc.h

@@ -0,0 +1,30 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _MISC_H_
+#define _MISC_H_
+
+#include <basic_types.h>
+
+#ifdef CONFIG_TIMER_MODULE
+extern _LONG_CALL_ u32 HalDelayUs(u32 us);
+#endif
+
+extern _LONG_CALL_ u32 HalGetCpuClk(VOID);
+extern _LONG_CALL_ u8 HalGetRomInfo(VOID);
+
+extern _LONG_CALL_ void *_memset( void *s, int c, SIZE_T n );
+extern _LONG_CALL_ void *_memcpy( void *s1, const void *s2, SIZE_T n );
+extern _LONG_CALL_ int _memcmp( const void *av, const void *bv, SIZE_T len );
+
+extern _LONG_CALL_ SIZE_T _strlen(const char *s);
+extern _LONG_CALL_ int _strcmp(const char *cs, const char *ct);
+
+
+#endif  //_MISC_H_

sdk/component/soc/realtek/8195a/fwlib/hal_nfc.h

@@ -0,0 +1,22 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_NFC_H_
+#define _HAL_NFC_H_
+
+#include "rtl8195a_nfc.h"
+
+
+VOID HalNFCOpInit(
+    IN  VOID *Data
+);
+
+
+#endif
+

sdk/component/soc/realtek/8195a/fwlib/hal_peri_on.h

@@ -0,0 +1,451 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_PERI_ON_H_
+#define _HAL_PERI_ON_H_
+
+#define MASK_ALLON                          0xFFFFFFFF
+
+#define HAL_PERI_ON_READ32(addr)            HAL_READ32(PERI_ON_BASE, addr)
+#define HAL_PERI_ON_WRITE32(addr, value)    HAL_WRITE32(PERI_ON_BASE, addr, value)
+#define HAL_PERI_ON_READ16(addr)            HAL_READ16(PERI_ON_BASE, addr)
+#define HAL_PERI_ON_WRITE16(addr, value)    HAL_WRITE16(PERI_ON_BASE, addr, value)
+#define HAL_PERI_ON_READ8(addr)             HAL_READ8(PERI_ON_BASE, addr)
+#define HAL_PERI_ON_WRITE8(addr, value)     HAL_WRITE8(PERI_ON_BASE, addr, value)
+#define HAL_PERL_ON_FUNC_CTRL(addr,value,ctrl)  \
+        HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~value))|((MASK_ALLON - ctrl + 1) & value)))
+#define HAL_PERL_ON_PIN_SEL(addr,mask,value)  \
+        HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~mask)) | value))
+
+//40 REG_SYS_REGU_CTRL0
+#define LDO25M_CTRL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_SYS_REGU_CTRL0, BIT_SYS_REGU_LDO25M_EN, ctrl)
+
+//A0 SYS_DEBUG_CTRL
+#define DEBUG_PIN_CTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_SYS_DEBUG_CTRL, BIT_SYS_DBG_PIN_EN, ctrl)
+
+//A4 SYS_PINMUX_CTRL
+#define SIC_PIN_CTRL(ctrl)      HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_SIC_PIN_EN, ctrl)
+#define EEPROM_PIN_CTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_EEPROM_PIN_EN, ctrl)
+
+
+//210 SOV_FUNC_EN
+#define LXBUS_FCTRL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LXBUS_EN, ctrl)
+#define FLASH_FCTRL(ctrl)       { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SPI_FLASH_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_FLASH_EN, ctrl);}
+
+#define MEM_CTRL_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SDR_SDRAM_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_MEM_CTRL_EN, ctrl);}
+
+#define LOC_UART_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(LOG_UART_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LOG_UART_EN, ctrl);}
+
+#define GDMA0_FCTRL(ctrl)       { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(GDMA0_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA0_EN, ctrl);}
+
+#define GDMA1_FCTRL(ctrl)       { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(GDMA1_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA1_EN, ctrl);}
+
+#define GTIMER_FCTRL(ctrl)      { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(TIMER_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GTIMER_EN, ctrl);}
+
+#define SECURITY_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(CRYPTO_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_SECURITY_ENGINE_EN, ctrl);}
+
+//214 SOC_HCI_COM_FUNC_EN
+#define SDIOD_ON_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SDIO_DEVICE_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN, ctrl);}
+
+#define SDIOD_OFF_FCTRL(ctrl)   { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SDIO_DEVICE_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN, ctrl);}
+
+#define SDIOH_FCTRL(ctrl)       { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SDIO_HOST_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN, ctrl);}
+
+#define SDIO_ON_RST_MASK(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_RST_MUX, ctrl)
+#define OTG_FCTRL(ctrl)         { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(USB_OTG_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_EN, ctrl);}
+
+#define OTG_RST_MASK(ctrl)      HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_RST_MUX, ctrl)
+#define MII_FCTRL(ctrl)         { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(MII_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_MII_EN, ctrl);}
+
+#define MII_MUX_SEL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SM_SEL, ctrl)
+#define WL_MACON_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(WIFI_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_WL_MACON_EN, ctrl);}
+
+//218 SOC_PERI_FUNC0_EN
+#define UART0_FCTRL(ctrl)       { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(UART0_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART0_EN, ctrl);}
+
+#define UART1_FCTRL(ctrl)       { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(UART1_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART1_EN, ctrl);}
+
+#define UART2_FCTRL(ctrl)       { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(UART2_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART2_EN, ctrl);}
+
+#define SPI0_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SPI0_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI0_EN, ctrl);}
+
+#define SPI1_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SPI1_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI1_EN, ctrl);}
+
+#define SPI2_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(SPI2_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI2_EN, ctrl);}
+
+#define I2C0_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(I2C0_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C0_EN, ctrl);}
+
+#define I2C1_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(I2C1_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C1_EN, ctrl);}
+
+#define I2C2_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(I2C2_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C2_EN, ctrl);}
+
+#define I2C3_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(I2C3_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C3_EN, ctrl);}
+
+#define I2S0_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(I2S0_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S0_EN, ctrl);}
+
+#define I2S1_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(I2S1_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S1_EN, ctrl);}
+
+#define PCM0_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(PCM0_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM0_EN, ctrl);}
+
+#define PCM1_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(PCM1_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM1_EN, ctrl);}
+
+//21C SOC_PERI_FUNC1_EN
+#define ADC0_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(ADC_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_ADC0_EN, ctrl);}
+
+#define DAC0_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(DAC_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC0_EN, ctrl);}
+
+#define DAC1_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(DAC_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC1_EN, ctrl);}
+
+#define GPIO_FCTRL(ctrl)        { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(GPIO_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_GPIO_EN, ctrl);}
+
+//220 SOC_PERI_BD_FUNC0_EN
+#define UART0_BD_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(UART0_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART0_BD_EN, ctrl);}
+
+#define UART1_BD_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(UART1_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART1_BD_EN, ctrl);}
+
+#define UART2_BD_FCTRL(ctrl)    { \
+                                    if (!ctrl) { \
+                                        HAL_READ32(UART2_REG_BASE,0);\
+                                    }\
+                                    HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART2_BD_EN, ctrl);}
+
+//230 PESOC_CLK_CTRL
+#define ACTCK_CPU_CCTRL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_CKE_PLFM, ctrl)
+#define ACTCK_TRACE_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TRACE_EN, ctrl)
+#define SLPCK_TRACE_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TRACE_EN, ctrl)
+#define ACTCK_VENDOR_CCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_VENDOR_REG_EN, ctrl)
+#define SLPCK_VENDOR_CCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_VENDOR_REG_EN, ctrl)
+#define ACTCK_FLASH_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_FLASH_EN, ctrl)
+#define SLPCK_FLASH_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_FLASH_EN, ctrl)
+#define ACTCK_SDR_CCTRL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_SDR_EN, ctrl)
+#define SLPCK_SDR_CCTRL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_SDR_EN, ctrl)
+#define ACTCK_LOG_UART_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_LOG_UART_EN, ctrl)
+#define SLPCK_LOG_UART_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_LOG_UART_EN, ctrl)
+#define ACTCK_TIMER_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TIMER_EN, ctrl)
+#define SLPCK_TIMER_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TIMER_EN, ctrl)
+#define ACTCK_GDMA0_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA0_EN, ctrl)
+#define SLPCK_GDMA0_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA0_EN, ctrl)
+#define ACTCK_GDMA1_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA1_EN, ctrl)
+#define SLPCK_GDMA1_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA1_EN, ctrl)
+#define ACTCK_GPIO_CCTRL(ctrl)      HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GPIO_EN, ctrl)
+#define SLPCK_GPIO_CCTRL(ctrl)      HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GPIO_EN, ctrl)
+#define ACTCK_BTCMD_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_BTCMD_EN, ctrl)
+#define SLPCK_BTCMD_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_BTCMD_EN, ctrl)
+
+//234 PESOC_PERI_CLK_CTRL0
+#define ACTCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART0_EN, ctrl)
+#define SLPCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART0_EN, ctrl)
+#define ACTCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART1_EN, ctrl)
+#define SLPCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART1_EN, ctrl)
+#define ACTCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART2_EN, ctrl)
+#define SLPCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART2_EN, ctrl)
+#define ACTCK_SPI0_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI0_EN, ctrl)
+#define SLPCK_SPI0_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI0_EN, ctrl)
+#define ACTCK_SPI1_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI1_EN, ctrl)
+#define SLPCK_SPI1_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI1_EN, ctrl)
+#define ACTCK_SPI2_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI2_EN, ctrl)
+#define SLPCK_SPI2_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI2_EN, ctrl)
+
+//238 PESOC_PERI_CLK_CTRL1
+#define ACTCK_I2C0_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C0_EN, ctrl)
+#define SLPCK_I2C0_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C0_EN, ctrl)
+#define ACTCK_I2C1_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C1_EN, ctrl)
+#define SLPCK_I2C1_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C1_EN, ctrl)
+#define ACTCK_I2C2_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C2_EN, ctrl)
+#define SLPCK_I2C2_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C2_EN, ctrl)
+#define ACTCK_I2C3_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C3_EN, ctrl)
+#define SLPCK_I2C3_CCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C3_EN, ctrl)
+#define ACTCK_I2S_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2S_EN, ctrl)
+#define SLPCK_I2S_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2S_EN, ctrl)
+#define ACTCK_PCM_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_PCM_EN, ctrl)
+#define SLPCK_PCM_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_PCM_EN, ctrl)
+#define ACTCK_ADC_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_ADC_EN, ctrl)
+#define SLPCK_ADC_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_ADC_EN, ctrl)
+#define ACTCK_DAC_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_DAC_EN, ctrl)
+#define SLPCK_DAC_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_DAC_EN, ctrl)
+
+//240 PESOC_HCI_CLK_CTRL0
+#define ACTCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_DEV_EN, ctrl)
+#define SLPCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_DEV_EN, ctrl)
+#define ACTCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_HST_EN, ctrl)
+#define SLPCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_HST_EN, ctrl)
+#define ACTCK_OTG_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_OTG_EN, ctrl)
+#define SLPCK_OTG_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_OTG_EN, ctrl)
+#define ACTCK_MII_MPHY_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_MII_MPHY_EN, ctrl)
+#define SLPCK_MII_MPHY_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_MII_MPHY_EN, ctrl)
+
+//244 PESOC_COM_CLK_CTRL1
+#define ACTCK_WL_CCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_WL_EN, ctrl)
+#define SLPCK_WL_CCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_WL_EN, ctrl)
+#define ACTCK_SEC_ENG_CCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_SECURITY_ENG_EN, ctrl)
+#define SLPCK_SEC_ENG_CCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_SECURITY_ENG_EN, ctrl)
+#define ACTCK_NFC_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_NFC_EN, ctrl)
+#define SLPCK_NFC_CCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_NFC_EN, ctrl)
+#define NFC_CAL_CCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_NFC_CAL_EN, ctrl)
+
+//250 REG_PERI_CLK_SEL
+#define TRACE_CLK_SEL(num)      HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_TRACE_CK_SEL << BIT_SHIFT_PESOC_TRACE_CK_SEL), BIT_PESOC_TRACE_CK_SEL(num))
+#define FLASH_CLK_SEL(num)      HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_FLASH_CK_SEL << BIT_SHIFT_PESOC_FLASH_CK_SEL), BIT_PESOC_FLASH_CK_SEL(num))
+#define SDR_CLK_SEL(num)        HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_SDR_CK_SEL << BIT_SHIFT_PESOC_SDR_CK_SEL), BIT_PESOC_SDR_CK_SEL(num))
+#define I2C_SCLK_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_PERI_SCLK_SEL << BIT_SHIFT_PESOC_PERI_SCLK_SEL), BIT_PESOC_PERI_SCLK_SEL(num))
+
+//270 REG_OSC32K_CTRL
+#define OSC32K_CKGEN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_OSC32K_CTRL, BIT_32K_POW_CKGEN_EN, ctrl)
+
+//280 REG_UART_MUX_CTRL
+#define UART0_PIN_CTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART0_PIN_EN, ctrl)
+#define UART0_PIN_SEL(num)      HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART0_PIN_SEL << BIT_SHIFT_UART0_PIN_SEL), BIT_UART0_PIN_SEL(num))
+#define UART1_PIN_CTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART1_PIN_EN, ctrl)
+#define UART1_PIN_SEL(num)      HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART1_PIN_SEL << BIT_SHIFT_UART1_PIN_SEL), BIT_UART1_PIN_SEL(num))
+#define UART2_PIN_CTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART2_PIN_EN, ctrl)
+#define UART2_PIN_SEL(num)      HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART2_PIN_SEL << BIT_SHIFT_UART2_PIN_SEL), BIT_UART2_PIN_SEL(num))
+
+//284 REG_SPI_MUX_CTRL
+#define SPI0_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_PIN_EN, ctrl)
+#define SPI0_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI0_PIN_SEL << BIT_SHIFT_SPI0_PIN_SEL), BIT_SPI0_PIN_SEL(num))
+#define SPI1_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI1_PIN_EN, ctrl)
+#define SPI1_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI1_PIN_SEL << BIT_SHIFT_SPI1_PIN_SEL), BIT_SPI1_PIN_SEL(num))
+#define SPI2_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI2_PIN_EN, ctrl)
+#define SPI2_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI2_PIN_SEL << BIT_SHIFT_SPI2_PIN_SEL), BIT_SPI2_PIN_SEL(num))
+#define SPI0_MULTI_CS_CTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_MULTI_CS_EN, ctrl)
+
+//288 REG_I2C_MUX_CTRL
+#define I2C0_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C0_PIN_EN, ctrl)
+#define I2C0_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C0_PIN_SEL << BIT_SHIFT_I2C0_PIN_SEL), BIT_I2C0_PIN_SEL(num))
+#define I2C1_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C1_PIN_EN, ctrl)
+#define I2C1_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C1_PIN_SEL << BIT_SHIFT_I2C1_PIN_SEL), BIT_I2C1_PIN_SEL(num))
+#define I2C2_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C2_PIN_EN, ctrl)
+#define I2C2_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C2_PIN_SEL << BIT_SHIFT_I2C2_PIN_SEL), BIT_I2C2_PIN_SEL(num))
+#define I2C3_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C3_PIN_EN, ctrl)
+#define I2C3_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C3_PIN_SEL << BIT_SHIFT_I2C3_PIN_SEL), BIT_I2C3_PIN_SEL(num))
+
+//28C REG_I2S_MUX_CTRL
+#define I2S0_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_PIN_EN, ctrl)
+#define I2S0_MCK_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_MCK_EN, ctrl)
+#define I2S0_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S0_PIN_SEL << BIT_SHIFT_I2S0_PIN_SEL), BIT_I2S0_PIN_SEL(num))
+#define I2S1_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_PIN_EN, ctrl)
+#define I2S1_MCK_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_MCK_EN, ctrl)
+#define I2S1_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S1_PIN_SEL << BIT_SHIFT_I2S1_PIN_SEL), BIT_I2S1_PIN_SEL(num))
+#define PCM0_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM0_PIN_EN, ctrl)
+#define PCM0_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM0_PIN_SEL << BIT_SHIFT_PCM0_PIN_SEL), BIT_PCM0_PIN_SEL(num))
+#define PCM1_PIN_CTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM1_PIN_EN, ctrl)
+#define PCM1_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM1_PIN_SEL << BIT_SHIFT_PCM1_PIN_SEL), BIT_PCM1_PIN_SEL(num))
+
+//2A0 HCI_PINMUX_CTRL
+#define SDIOD_PIN_FCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN, ctrl)
+#define SDIOH_PIN_FCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN, ctrl)
+#define MII_PIN_FCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN, ctrl)
+
+//2A4 WL_PINMUX_CTRL
+#define LED_PIN_FCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_LED_PIN_EN, ctrl)
+#define LED_PIN_SEL(num)        HAL_PERL_ON_PIN_SEL(REG_WL_PINMUX_CTRL, (BIT_MASK_WL_LED_PIN_SEL << BIT_SHIFT_WL_LED_PIN_SEL), BIT_WL_LED_PIN_SEL(num))
+#define ANT0_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT0_PIN_EN, ctrl)
+#define ANT1_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT1_PIN_EN, ctrl)
+#define BTCOEX_PIN_FCTRL(ctrl)  HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCOEX_PIN_EN, ctrl)
+#define BTCMD_PIN_FCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCMD_PIN_EN, ctrl)
+#define NFC_PIN_FCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_NFC_PIN_EN, ctrl)
+
+//2AC PWM_PINMUX_CTRL
+#define PWM0_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM0_PIN_EN, ctrl)
+#define PWM0_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM0_PIN_SEL << BIT_SHIFT_PWM0_PIN_SEL), BIT_PWM0_PIN_SEL(num))
+#define PWM1_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM1_PIN_EN, ctrl)
+#define PWM1_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM1_PIN_SEL << BIT_SHIFT_PWM1_PIN_SEL), BIT_PWM1_PIN_SEL(num))
+#define PWM2_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM2_PIN_EN, ctrl)
+#define PWM2_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM2_PIN_SEL << BIT_SHIFT_PWM2_PIN_SEL), BIT_PWM2_PIN_SEL(num))
+#define PWM3_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM3_PIN_EN, ctrl)
+#define PWM3_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM3_PIN_SEL << BIT_SHIFT_PWM3_PIN_SEL), BIT_PWM3_PIN_SEL(num))
+#define ETE0_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE0_PIN_EN, ctrl)
+#define ETE0_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE0_PIN_SEL << BIT_SHIFT_ETE0_PIN_SEL), BIT_ETE0_PIN_SEL(num))
+#define ETE1_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE1_PIN_EN, ctrl)
+#define ETE1_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE1_PIN_SEL << BIT_SHIFT_ETE1_PIN_SEL), BIT_ETE1_PIN_SEL(num))
+#define ETE2_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE2_PIN_EN, ctrl)
+#define ETE2_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE2_PIN_SEL << BIT_SHIFT_ETE2_PIN_SEL), BIT_ETE2_PIN_SEL(num))
+#define ETE3_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE3_PIN_EN, ctrl)
+#define ETE3_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE3_PIN_SEL << BIT_SHIFT_ETE3_PIN_SEL), BIT_ETE3_PIN_SEL(num))
+
+//2C0 CPU_PERIPHERAL_CTRL
+#define SPI_FLASH_PIN_FCTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SPI_FLSH_PIN_EN, ctrl)
+#define SPI_FLASH_PIN_SEL(num)       HAL_PERL_ON_PIN_SEL(REG_CPU_PERIPHERAL_CTRL, (BIT_MASK_SPI_FLSH_PIN_SEL << BIT_SHIFT_SPI_FLSH_PIN_SEL), BIT_SPI_FLSH_PIN_SEL(num))
+#define SDR_PIN_FCTRL(ctrl)          HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SDR_PIN_EN, ctrl)
+#define TRACE_PIN_FCTRL(ctrl)        HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_TRACE_PIN_EN, ctrl)
+#define LOG_UART_PIN_FCTRL(ctrl)     HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_PIN_EN, ctrl)
+#define LOG_UART_IR_FCTRL(ctrl)      HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_IR_EN, ctrl)
+
+//300 REG_PESOC_MEM_CTRL
+#define SDR_DDL_FCTRL(ctrl)      HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_SDR_DDL_CTRL << BIT_SHIFT_PESOC_SDR_DDL_CTRL), BIT_PESOC_SDR_DDL_CTRL(ctrl))
+#define FLASH_DDL_FCTRL(ctrl)    HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_FLASH_DDL_CTRL << BIT_SHIFT_PESOC_FLASH_DDL_CTRL), BIT_PESOC_FLASH_DDL_CTRL(ctrl))
+
+//304 REG_PESOC_SOC_CTRL
+#define SRAM_MUX_CFG(num)        HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_SRAM_MUX_CFG << BIT_SHIFT_PESOC_SRAM_MUX_CFG), BIT_PESOC_SRAM_MUX_CFG(num))
+#define LX_WL_SWAP_CTRL(ctrl)    HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_WL_SWAP_SEL, ctrl)
+#define LX_MST_SWAP_CTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_MST_SWAP_SEL, ctrl)
+#define LX_SLV_SWAP_CTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_SLV_SWAP_SEL, ctrl)
+#define MII_LX_WRAPPER_FCTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_WRAPPER_EN, ctrl)
+#define MII_LX_MST_SWAP_CTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_MST_SWAP_SEL, ctrl)
+#define MII_LX_SLV_SWAP_CTRL(ctrl)   HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_SLV_SWAP_SEL, ctrl)
+#define GDMA_CFG(num)            HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_GDMA_CFG << BIT_SHIFT_PESOC_GDMA_CFG), BIT_PESOC_GDMA_CFG(num))
+
+//308 PESOC_PERI_CTRL
+#define SPI_RN_FCTRL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CTRL, BIT_SOC_FUNC_SPI_RN, ctrl)
+
+//320 GPIO_SHTDN_CTRL
+#define GPIO_GPA_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPA_SHTDN_N, ctrl)
+#define GPIO_GPB_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPB_SHTDN_N, ctrl)
+#define GPIO_GPC_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPC_SHTDN_N, ctrl)
+#define GPIO_GPD_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPD_SHTDN_N, ctrl)
+#define GPIO_GPE_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPE_SHTDN_N, ctrl)
+#define GPIO_GPF_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPF_SHTDN_N, ctrl)
+#define GPIO_GPG_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPG_SHTDN_N, ctrl)
+#define GPIO_GPH_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPH_SHTDN_N, ctrl)
+#define GPIO_GPI_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPI_SHTDN_N, ctrl)
+#define GPIO_GPJ_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPJ_SHTDN_N, ctrl)
+#define GPIO_GPK_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPK_SHTDN_N, ctrl)
+
+//374
+#define EGTIM_FCTRL(ctrl)       HAL_PERL_ON_FUNC_CTRL(REG_PERI_EGTIM_CTRL, BIT_PERI_EGTIM_EN, ctrl)
+#define EGTIM_RSIG_SEL(num)     HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_REF_SIG_SEL << BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL), BIT_PERI_EGTIM_REF_SIG_SEL(num))
+#define EGTIME_PIN_G0_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP0_OPT_SEL(num))
+#define EGTIME_PIN_G1_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP1_OPT_SEL(num))
+#define EGTIME_PIN_G2_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP2_OPT_SEL(num))
+
+
+#endif //_HAL_PERI_ON_H_
+

sdk/component/soc/realtek/8195a/fwlib/hal_pinmux.h

@@ -0,0 +1,64 @@
+#ifndef _HAL_PINMUX_
+#define _HAL_PINMUX_
+
+
+//Function Index
+#define UART0       0
+#define UART1       1
+#define UART2       2
+#define SPI0        8
+#define SPI1        9
+#define SPI2        10
+#define SPI0_MCS    15
+#define I2C0        16
+#define I2C1        17
+#define I2C2        18
+#define I2C3        19
+#define I2S0        24
+#define I2S1        25
+#define PCM0        28
+#define PCM1        29
+#define ADC0        32
+#define DAC0        36
+#define DAC1        37
+#define SDIOD       64
+#define SDIOH       65
+#define USBOTG      66
+#define MII         88
+#define WL_LED      96
+#define WL_ANT0     104
+#define WL_ANT1     105
+#define WL_BTCOEX   108
+#define WL_BTCMD    109
+#define NFC         112
+#define PWM0        160
+#define PWM1        161
+#define PWM2        162
+#define PWM3        163
+#define ETE0        164
+#define ETE1        165
+#define ETE2        166
+#define ETE3        167
+#define EGTIM       168
+#define SPI_FLASH   196
+#define SDR         200
+#define JTAG        216
+#define TRACE       217
+#define LOG_UART    220
+#define LOG_UART_IR 221
+#define SIC         224
+#define EEPROM      225
+#define DEBUG       226
+
+//Location Index(Pin Mux Selection)
+#define S0          0
+#define S1          1
+#define S2          2
+#define S3          3
+
+_LONG_CALL_ u8 
+HalPinCtrlRtl8195A(
+    IN u32  Function, 
+    IN u32  PinLocation, 
+    IN BOOL   Operation);
+#endif   //_HAL_PINMUX_

sdk/component/soc/realtek/8195a/fwlib/hal_platform.h

@@ -0,0 +1,102 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _HAL_PLATFORM_
+#define _HAL_PLATFORM_
+
+#define ROMVERSION 0x03
+#define ROMINFORMATION (ROMVERSION)
+
+#define SYSTEM_CLK                  PLATFORM_CLOCK
+
+#define SDR_SDRAM_BASE              0x30000000
+#define SYSTEM_CTRL_BASE            0x40000000
+#define PERI_ON_BASE                0x40000000
+#define VENDOR_REG_BASE             0x40002800
+#define SPI_FLASH_BASE              0x98000000
+#define SDR_CTRL_BASE               0x40005000
+
+#define PERIPHERAL_IRQ_STATUS       0x04
+#define PERIPHERAL_IRQ_MODE         0x08
+#define PERIPHERAL_IRQ_EN           0x0C
+#define LP_PERI_EXT_IRQ_STATUS      0x24
+#define LP_PERI_EXT_IRQ_MODE        0x28
+#define LP_PERI_EXT_IRQ_EN          0x2C
+
+#define PERIPHERAL_IRQ_ALL_LEVEL    0
+
+#define TIMER_CLK                   32*1000
+
+//3 Peripheral IP Base Address
+#define GPIO_REG_BASE               0x40001000
+#define TIMER_REG_BASE              0x40002000
+#define NFC_INTERFACE_BASE          0x40002400
+#define LOG_UART_REG_BASE           0x40003000
+#define I2C2_REG_BASE               0x40003400
+#define I2C3_REG_BASE               0x40003800
+#define SPI_FLASH_CTRL_BASE         0x40006000
+#define ADC_REG_BASE                0x40010000
+#define DAC_REG_BASE                0x40011000
+#define UART0_REG_BASE              0x40040000
+#define UART1_REG_BASE              0x40040400
+#define UART2_REG_BASE              0x40040800
+#define SPI0_REG_BASE               0x40042000
+#define SPI1_REG_BASE               0x40042400
+#define SPI2_REG_BASE               0x40042800
+#define I2C0_REG_BASE               0x40044000
+#define I2C1_REG_BASE               0x40044400
+#define SDIO_DEVICE_REG_BASE        0x40050000
+#define MII_REG_BASE                0x40050000
+#define SDIO_HOST_REG_BASE          0x40058000
+#define GDMA0_REG_BASE              0x40060000
+#define GDMA1_REG_BASE              0x40061000
+#define I2S0_REG_BASE               0x40062000
+#define I2S1_REG_BASE               0x40063000
+#define PCM0_REG_BASE               0x40064000
+#define PCM1_REG_BASE               0x40065000
+#define CRYPTO_REG_BASE             0x40070000
+#define WIFI_REG_BASE               0x40080000
+#define USB_OTG_REG_BASE            0x400C0000
+
+#define GDMA1_REG_OFF               0x1000
+#define I2S1_REG_OFF                0x1000
+#define PCM1_REG_OFF                0x1000
+#define SSI_REG_OFF                 0x400
+#define RUART_REG_OFF               0x400
+
+#define CPU_CLK_TYPE_NO             6
+
+enum _BOOT_TYPE_ {
+    BOOT_FROM_FLASH = 0,
+    BOOT_FROM_SDIO  = 1,        
+    BOOT_FROM_USB   = 2,
+    BOOT_FROM_RSVD  = 3,    
+};
+
+enum _EFUSE_CPU_CLK_ {
+    #if 1
+    CLK_200M   = 0,
+    CLK_100M   = 1,
+    CLK_50M    = 2,
+    CLK_25M    = 3,
+    CLK_12_5M  = 4,    
+    CLK_4M     = 5,
+    #else
+    CLK_25M    = 0,
+    CLK_200M   = 1,
+    CLK_100M   = 2,        
+    CLK_50M    = 3,
+    CLK_12_5M  = 4,    
+    CLK_4M     = 5,    
+    #endif
+};
+
+
+#endif //_HAL_PLATFORM_

sdk/component/soc/realtek/8195a/fwlib/hal_pwm.h

@@ -0,0 +1,57 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_PWM_H_
+#define _HAL_PWM_H_
+
+#define MAX_PWM_CTRL_PIN        4
+// the minimum tick time for G-timer is 61 us (clock source = 32768Hz, reload value=1 and reload takes extra 1T)
+//#define GTIMER_TICK_US            31   // micro-second, 1000000/32768 ~= 30.5
+#define MIN_GTIMER_TIMEOUT    61  // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
+#define PWM_GTIMER_TICK_TIME    61  // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
+
+typedef struct _HAL_PWM_ADAPTER_ {
+    u8 pwm_id;      // the PWM ID, 0~3
+    u8 sel;         // PWM Pin selection, 0~3
+    u8 gtimer_id;   // using G-Timer ID, there are 7 G-timer, but we prefer to use timer 3~6
+    u8 enable;      // is enabled
+//    u32 timer_value;    // the G-Timer auto-reload value, source clock is 32768Hz, reload will takes extra 1 tick. To set the time of a tick of PWM
+    u32 tick_time;  // the tick time for the G-timer
+    u32 period;    // the period of a PWM control cycle, in PWM tick
+    u32 pulsewidth;    // the pulse width in a period of a PWM control cycle, in PWM tick. To control the ratio
+//    float duty_ratio;   // the dyty ratio = pulswidth/period
+}HAL_PWM_ADAPTER, *PHAL_PWM_ADAPTER;
+
+
+extern HAL_Status 
+HAL_Pwm_Init(
+    u32 pwm_id,
+    u32 sel
+);
+
+extern void 
+HAL_Pwm_Enable(
+    u32 pwm_id
+);
+
+extern void 
+HAL_Pwm_Disable(
+    u32 pwm_id
+);
+
+extern void
+HAL_Pwm_SetDuty(
+    u32 pwm_id,
+    u32 period,
+    u32 pulse_width
+);
+
+
+#endif
+

sdk/component/soc/realtek/8195a/fwlib/hal_soc_ps_monitor.h

@@ -0,0 +1,278 @@
+#ifndef _HAL_SOCPWR_
+#define _HAL_SOCPWR_
+
+
+
+#define MAX_BACKUP_SIZE 129
+#define MAXFUNC     10
+#define FSTREG      0xFF
+
+#define REG_VDR_ANACK_CAL_CTRL 0xA0
+
+#define PS_MASK 0xFFFFFFFF
+
+//pwr state
+#define HWACT    0
+#define HWCG     1
+#define HWINACT  2
+#define UNDEF    3
+#define ALLMET   0xff
+
+//SLP
+#define     SLP_STIMER    BIT0
+#define     SLP_GTIMER    BIT1
+#define     SLP_GPIO      BIT2
+#define     SLP_WL        BIT3
+#define     SLP_NFC       BIT4
+#define     SLP_SDIO      BIT5
+#define     SLP_USB       BIT6
+#define     SLP_TIMER33   BIT7
+
+//DSTBY
+#define     DSTBY_STIMER  BIT0
+#define     DSTBY_NFC     BIT1
+#define     DSTBY_TIMER33 BIT2
+#define     DSTBY_GPIO    BIT3
+
+//DS wake event
+#define DS_TIMER33 BIT0
+#define DS_GPIO    BIT1
+
+enum power_state_idx{
+    ACT    = 0,
+    WFE    = 1,
+    WFI    = 2,
+    SNOOZE = 3,
+    SLPCG  = 4,
+    SLPPG  = 5,
+    DSTBY  = 6,
+    DSLP   = 7,
+    INACT  = 8,
+    MAXSTATE = 9
+};
+
+enum clk_idx{
+    ANACK = 0,
+    A33CK = 1,
+};
+
+
+typedef struct _power_state_{
+    u8  FuncIdx;
+    u8  PowerState;
+}POWER_STATE, *pPOWER_STATE;
+
+typedef struct _reg_power_state_{
+    u8  FuncIdx;
+    u8  PwrState;
+}REG_POWER_STATE, *pPREG_POWER_STATE;
+
+#if 0
+typedef struct _power_state_{
+    u8  FuncIdx;
+    u8  PowerState;
+    u32 ReqDuration;
+    u32 RegCount;
+    u32 RemainDuration;
+}POWER_STATE, *pPOWER_STATE;
+
+typedef struct _reg_power_state_{
+    u8  FuncIdx;
+    u8  PwrState;
+    u32 ReqDuration;
+    //u8 StateIdx;
+}REG_POWER_STATE, *pPREG_POWER_STATE;
+#endif
+
+typedef struct _power_mgn_{
+    u8          ActFuncCount;
+    POWER_STATE PwrState[MAXFUNC];
+    u8          CurrentState;
+    u8          SDREn;
+    u32         MSPbackup[MAX_BACKUP_SIZE];
+    u32         CPURegbackup[25];
+    u32         CPUPSP;
+    u32         WakeEventFlag;
+    BOOL        SleepFlag;
+    //u32         CPUReg[13];
+    //u32         MSBackUp[128];
+}Power_Mgn, *pPower_Mgn;
+
+typedef struct _SYS_ADAPTER_ {
+    u8      function;
+}SYS_ADAPTER, *PSYS_ADAPTER;
+
+extern Power_Mgn PwrAdapter;
+
+u8 ChangeSoCPwrState(
+    IN  u8  RequestState,
+    IN  u32 ReqCount
+);
+
+VOID PrintCPU(VOID);
+void WakeFromSLPPG(void);
+VOID SOCPSTestApp(VOID *Data);
+
+
+__inline static VOID 
+CPURegBackUp(
+    VOID
+)
+{
+#if defined (__ICCARM__)
+    // TODO: IAR has different way using assembly
+#elif defined (__GNUC__)
+	//backup cpu reg
+    #if 0
+    asm volatile
+    (
+        "PUSH {PSR, PC, LR, R12,R3,R2,R1,R0}\n"
+    );
+    #endif
+    #if 0
+    asm volatile
+    (
+        "PUSH {r0,r1,r2,r3,r4}\n"
+    );
+    #endif
+    
+    asm volatile
+    (
+
+        "MOV %0, r0\n"
+        :"=r"(PwrAdapter.CPURegbackup[0])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r1\n"
+        :"=r"(PwrAdapter.CPURegbackup[1])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r2\n"
+        :"=r"(PwrAdapter.CPURegbackup[2])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r3\n"
+        :"=r"(PwrAdapter.CPURegbackup[3])
+        ::"memory"
+    );
+    
+    asm volatile
+    (
+        "MOV %0, r4\n"
+        :"=r"(PwrAdapter.CPURegbackup[4])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r5\n"
+        :"=r"(PwrAdapter.CPURegbackup[5])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r6\n"
+        :"=r"(PwrAdapter.CPURegbackup[6])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r7\n"
+        :"=r"(PwrAdapter.CPURegbackup[7])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r8\n"
+        :"=r"(PwrAdapter.CPURegbackup[8])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r9\n"
+        :"=r"(PwrAdapter.CPURegbackup[9])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r10\n"
+        :"=r"(PwrAdapter.CPURegbackup[10])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r11\n"
+        :"=r"(PwrAdapter.CPURegbackup[11])
+        ::"memory"
+    );
+    asm volatile
+    (
+        "MOV %0, r12\n"
+        :"=r"(PwrAdapter.CPURegbackup[12])
+        ::"memory"
+    );
+
+    asm volatile
+    (
+        "MOV %0, r13\n"
+        :"=r"(PwrAdapter.CPURegbackup[13])
+        ::"memory"
+    );
+    asm volatile
+    (
+        //"MOV %0, r14\n"
+        "LDR %0, =SLPPG_WAKEUP_POINT\n"
+        "ADD %0, #1\n"
+        :"=r"(PwrAdapter.CPURegbackup[14])
+        ::"memory"
+    );
+    asm volatile
+    (
+        "LDR %0, =SLPPG_WAKEUP_POINT\n"
+        "ADD %0, #1\n"
+        :"=r"(PwrAdapter.CPURegbackup[15])
+        ::"memory"
+    );
+    asm volatile
+    (
+        "MRS %0, PSR\n"
+        :"=r"(PwrAdapter.CPURegbackup[16])
+        ::"memory"
+    );
+
+#if 1
+    asm volatile
+    (
+        "mov %0, r13\n"
+        "MOV %1, PC\n" 
+        "MRS %2, CONTROL\n"
+        "MRS %3, PSP\n" 
+        "MRS %4, MSP\n" 
+        :"=r"(PwrAdapter.CPURegbackup[24]),"=r"(PwrAdapter.CPURegbackup[23]),"=r"(PwrAdapter.CPURegbackup[22]),"=r"(PwrAdapter.CPURegbackup[21]),"=r"(PwrAdapter.CPURegbackup[20])
+        ::"memory"
+    );
+#endif
+    #ifdef CONFIG_SOC_PS_VERIFY
+    PrintCPU();
+    #endif  //#ifdef CONFIG_SOC_PS_VERIFY
+#endif //#elif defined (__GNUC__)
+}
+
+VOID RegPowerState(REG_POWER_STATE RegPwrState);
+
+#endif  //_HAL_SOCPWR_

sdk/component/soc/realtek/8195a/fwlib/hal_spi_flash.h

@@ -0,0 +1,254 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _HAL_SPIFLASH__
+#define _HAL_SPIFLASH__
+//======================================================
+// Header files
+
+#define SPIC_CALIBRATION_IN_NVM         1   // if store the SPIC calibration data in the NVM
+#ifndef CONFIG_IMAGE_SEPARATE       // Store SPIC Calibration only for seprated image
+#undef SPIC_CALIBRATION_IN_NVM
+#define SPIC_CALIBRATION_IN_NVM         0
+#endif
+
+//======================================================
+// Definition
+#define HAL_SPI_WRITE32(addr, value32)  HAL_WRITE32(SPI_FLASH_CTRL_BASE, addr, value32)
+#define HAL_SPI_WRITE16(addr, value16)  HAL_WRITE16(SPI_FLASH_CTRL_BASE, addr, value16)
+#define HAL_SPI_WRITE8(addr, value8)    HAL_WRITE8(SPI_FLASH_CTRL_BASE, addr, value8)
+#define HAL_SPI_READ32(addr)            HAL_READ32(SPI_FLASH_CTRL_BASE, addr)
+#define HAL_SPI_READ16(addr)            HAL_READ16(SPI_FLASH_CTRL_BASE, addr)
+#define HAL_SPI_READ8(addr)             HAL_READ8(SPI_FLASH_CTRL_BASE, addr)
+
+typedef struct _SPIC_PARA_MODE_ {
+    u8 Valid:1;         // valid
+    u8 CpuClk:3;        // CPU clock
+    u8 BitMode:2;       // Bit mode
+	u8 Reserved:2;		// reserved
+} SPIC_PARA_MODE, *PSPIC_PARA_MODE;
+
+typedef struct _SPIC_INIT_PARA_ {
+    u8  BaudRate;
+    u8  RdDummyCyle;
+    u8  DelayLine;
+    union {
+        u8  Rsvd;
+        u8  Valid;
+        SPIC_PARA_MODE Mode;
+    };
+#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
+    u8 id[3];
+    u8 flashtype;
+#endif
+}SPIC_INIT_PARA, *PSPIC_INIT_PARA;
+
+
+enum _SPIC_BIT_MODE_ {
+    SpicOneBitMode = 0,
+    SpicDualBitMode = 1,
+    SpicQuadBitMode = 2,
+};
+
+//======================================================
+// Flash type used 
+#define FLASH_OTHERS 0
+#define FLASH_MXIC 1
+#define FLASH_WINBOND 2
+#define FLASH_MICRON 3
+
+#define FLASH_MXIC_MX25L4006E   1
+#define FLASH_MXIC_MX25L8073E   0
+
+// The below parts are based on the flash characteristics
+//====== Flash Command Definition  ======
+#if FLASH_MXIC_MX25L4006E
+    #define FLASH_CMD_WREN      0x06            //write enable
+    #define FLASH_CMD_WRDI      0x04            //write disable
+    #define FLASH_CMD_WRSR      0x01            //write status register
+    #define FLASH_CMD_RDID      0x9F            //read idenfication
+    #define FLASH_CMD_RDSR      0x05            //read status register
+    #define FLASH_CMD_READ      0x03            //read data
+    #define FLASH_CMD_FREAD     0x0B            //fast read data
+    #define FLASH_CMD_RDSFDP    0x5A            //Read SFDP
+    #define FLASH_CMD_RES       0xAB            //Read Electronic ID
+    #define FLASH_CMD_REMS      0x90            //Read Electronic Manufacturer & Device ID
+    #define FLASH_CMD_DREAD     0x3B            //Double Output Mode command
+    #define FLASH_CMD_SE        0x20            //Sector Erase
+    #define FLASH_CMD_BE        0xD8            //Block Erase(or 0x52)
+    #define FLASH_CMD_CE        0x60            //Chip Erase(or 0xC7)
+    #define FLASH_CMD_PP        0x02            //Page Program
+    #define FLASH_CMD_DP        0xB9            //Deep Power Down
+    #define FLASH_CMD_RDP       0xAB            //Release from Deep Power-Down
+#elif  FLASH_MXIC_MX25L8073E
+    #define FLASH_CMD_WREN      0x06            //write enable
+    #define FLASH_CMD_WRDI      0x04            //write disable
+    #define FLASH_CMD_WRSR      0x01            //write status register
+    #define FLASH_CMD_RDID      0x9F            //read idenfication
+    #define FLASH_CMD_RDSR      0x05            //read status register
+    #define FLASH_CMD_READ      0x03            //read data
+    #define FLASH_CMD_FREAD     0x0B            //fast read data
+    #define FLASH_CMD_RDSFDP    0x5A            //Read SFDP
+    #define FLASH_CMD_RES       0xAB            //Read Electronic ID
+    #define FLASH_CMD_REMS      0x90            //Read Electronic Manufacturer & Device ID
+    #define FLASH_CMD_DREAD     0x3B            //Double Output Mode command
+    #define FLASH_CMD_SE        0x20            //Sector Erase
+    #define FLASH_CMD_BE        0x52            //Block Erase
+    #define FLASH_CMD_CE        0x60            //Chip Erase(or 0xC7)
+    #define FLASH_CMD_PP        0x02            //Page Program
+    #define FLASH_CMD_DP        0xB9            //Deep Power Down
+    #define FLASH_CMD_RDP       0xAB            //Release from Deep Power-Down
+    #define FLASH_CMD_2READ     0xBB            // 2 x I/O read  command
+    #define FLASH_CMD_4READ     0xEB            // 4 x I/O read  command
+    #define FLASH_CMD_QREAD     0x6B            // 1I / 4O read command
+    #define FLASH_CMD_4PP       0x38            //quad page program
+    #define FLASH_CMD_FF        0xFF            //Release Read Enhanced
+    #define FLASH_CMD_REMS2     0xEF            // read ID for 2x I/O mode
+    #define FLASH_CMD_REMS4     0xDF            // read ID for 4x I/O mode
+    #define FLASH_CMD_ENSO      0xB1            // enter secured OTP
+    #define FLASH_CMD_EXSO      0xC1            // exit secured OTP
+    #define FLASH_CMD_RDSCUR    0x2B            // read security register
+    #define FLASH_CMD_WRSCUR    0x2F            // write security register
+#else
+    #define FLASH_CMD_WREN      0x06            //write enable
+    #define FLASH_CMD_WRDI      0x04            //write disable
+    #define FLASH_CMD_WRSR      0x01            //write status register
+    #define FLASH_CMD_RDID      0x9F            //read idenfication
+    #define FLASH_CMD_RDSR      0x05            //read status register
+    #define FLASH_CMD_READ      0x03            //read data
+    #define FLASH_CMD_FREAD     0x0B            //fast read data
+    #define FLASH_CMD_RDSFDP    0x5A            //Read SFDP
+    #define FLASH_CMD_RES       0xAB            //Read Electronic ID
+    #define FLASH_CMD_REMS      0x90            //Read Electronic Manufacturer & Device ID
+    #define FLASH_CMD_DREAD     0x3B            //Double Output Mode command
+    #define FLASH_CMD_SE        0x20            //Sector Erase
+    #define FLASH_CMD_BE        0x52            //Block Erase
+    #define FLASH_CMD_CE        0x60            //Chip Erase(or 0xC7)
+    #define FLASH_CMD_PP        0x02            //Page Program
+    #define FLASH_CMD_DP        0xB9            //Deep Power Down
+    #define FLASH_CMD_RDP       0xAB            //Release from Deep Power-Down
+    #define FLASH_CMD_2READ     0xBB            // 2 x I/O read  command
+    #define FLASH_CMD_4READ     0xEB            // 4 x I/O read  command
+    #define FLASH_CMD_QREAD     0x6B            // 1I / 4O read command
+    #define FLASH_CMD_4PP       0x38            //quad page program
+    #define FLASH_CMD_FF        0xFF            //Release Read Enhanced
+    #define FLASH_CMD_REMS2     0xEF            // read ID for 2x I/O mode
+    #define FLASH_CMD_REMS4     0xDF            // read ID for 4x I/O mode
+    #define FLASH_CMD_ENSO      0xB1            // enter secured OTP
+    #define FLASH_CMD_EXSO      0xC1            // exit secured OTP
+    #define FLASH_CMD_RDSCUR    0x2B            // read security register
+    #define FLASH_CMD_WRSCUR    0x2F            // write security register
+#endif //#if FLASH_MXIC_MX25L4006E
+// ============================
+
+// =====  Flash Parameter Definition  =====
+#if FLASH_MXIC_MX25L4006E
+    #define FLASH_RD_2IO_EN         0
+    #define FLASH_RD_2O_EN          1
+    #define FLASH_RD_4IO_EN         0
+    #define FLASH_RD_4O_EN          0
+    #define FLASH_WR_2IO_EN         0
+    #define FLASH_WR_2O_EN          0
+    #define FLASH_WR_4IO_EN         0
+    #define FLASH_WR_4O_EN          0    
+    
+    #define FLASH_DM_CYCLE_2O   0x08
+    #define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_I)
+    #define FLASH_VLD_QUAD_CMDS (0)
+    
+#elif  FLASH_MXIC_MX25L8073E //This flash model is just for prototype, if you want to use it, 
+                             //the code MUST be rechecked according to the flash spec.
+    #define FLASH_RD_2IO_EN         1
+    #define FLASH_RD_2O_EN          0
+    #define FLASH_RD_4IO_EN         1
+    #define FLASH_RD_4O_EN          0
+    #define FLASH_WR_2IO_EN         1
+    #define FLASH_WR_2O_EN          0
+    #define FLASH_WR_4IO_EN         1
+    #define FLASH_WR_4O_EN          0                             
+    
+    #define FLASH_DM_CYCLE_2O  0x08
+    #define FLASH_DM_CYCLE_2IO 0x04
+    #define FLASH_DM_CYCLE_4O  0x08
+    #define FLASH_DM_CYCLE_4IO 0x04
+    
+    #define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)
+    #define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
+#else
+    #define FLASH_RD_2IO_EN         1
+    #define FLASH_RD_2O_EN          0
+    #define FLASH_RD_4IO_EN         1
+    #define FLASH_RD_4O_EN          0
+    #define FLASH_WR_2IO_EN         1
+    #define FLASH_WR_2O_EN          0
+    #define FLASH_WR_4IO_EN         1
+    #define FLASH_WR_4O_EN          0
+    
+    #define FLASH_DM_CYCLE_2O  0x08
+    #define FLASH_DM_CYCLE_2IO 0x04
+    #define FLASH_DM_CYCLE_4O  0x08
+    #define FLASH_DM_CYCLE_4IO 0x04
+    
+    #define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)  
+    #define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
+#endif
+#if 0
+//======================================================
+// Function prototype
+BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);
+
+_LONG_CALL_
+extern VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara); 
+
+// spi-flash controller initialization
+_LONG_CALL_
+extern VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode);
+
+// wait sr[0] = 0, wait transmission done
+_LONG_CALL_
+extern VOID SpicWaitBusyDoneRtl8195A(VOID);
+
+// wait spi-flash status register[0] = 0
+//_LONG_CALL_
+//extern VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara);
+#endif
+
+//======================================================
+// ROM Function prototype
+_LONG_CALL_ VOID SpiFlashAppV02(IN  VOID *Data);
+_LONG_CALL_ROM_ VOID SpicInitRtl8195AV02(IN  u8 InitBaudRate,IN  u8 SpicBitMode);
+
+_LONG_CALL_ROM_ VOID SpicEraseFlashRtl8195AV02(VOID);
+
+_LONG_CALL_ROM_ VOID SpicLoadInitParaFromClockRtl8195AV02(IN  u8 CpuClkMode,IN  u8 BaudRate,IN  PSPIC_INIT_PARA pSpicInitPara);
+
+
+VOID SpicBlockEraseFlashRtl8195A(IN u32 Address);
+VOID SpicSectorEraseFlashRtl8195A(IN u32 Address);
+VOID SpicDieEraseFlashRtl8195A(IN u32 Address);
+VOID SpicWriteProtectFlashRtl8195A(IN u32 Protect);
+VOID SpicWaitWipDoneRefinedRtl8195A(IN  SPIC_INIT_PARA SpicInitPara);
+VOID SpicWaitOperationDoneRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
+VOID SpicRxCmdRefinedRtl8195A(IN  u8 cmd,IN  SPIC_INIT_PARA SpicInitPara);
+u8 SpicGetFlashStatusRefinedRtl8195A(IN  SPIC_INIT_PARA SpicInitPara);
+VOID SpicInitRefinedRtl8195A(IN  u8 InitBaudRate,IN  u8 SpicBitMode);
+u32 SpicWaitWipRtl8195A(VOID);
+u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk);
+VOID SpicDisableRtl8195A(VOID);
+VOID SpicDeepPowerDownFlashRtl8195A(VOID);
+VOID SpicUserProgramRtl8195A(IN u8 * data, IN SPIC_INIT_PARA SpicInitPara, IN u32 addr, IN u32 * LengthInfo);
+
+#if SPIC_CALIBRATION_IN_NVM
+VOID SpicNVMCalLoad(u8 BitMode, u8 CpuClk);
+VOID SpicNVMCalLoadAll(void);
+VOID SpicNVMCalStore(u8 BitMode, u8 CpuClk);
+#endif  // #if SPIC_CALIBRATION_IN_NVM
+
+#endif //_HAL_SPIFLASH__

sdk/component/soc/realtek/8195a/fwlib/hal_ssi.h

@@ -0,0 +1,309 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_SSI_H_
+#define _HAL_SSI_H_
+
+#include "rtl8195a_ssi.h"
+
+/**
+ * LOG Configurations
+ */
+
+extern u32 SSI_DBG_CONFIG;
+extern uint8_t SPI0_IS_AS_SLAVE;
+
+
+#define SSI_DBG_ENTRANCE(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENTRANCE)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE ANSI_COLOR_GREEN __VA_ARGS__ ANSI_COLOR_RESET); \
+}while(0)
+
+#define SSI_DBG_INIT(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_INIT_V(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_V)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_INIT_VV(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_VV)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_PINMUX(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_PINMUX)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_ENDIS(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENDIS)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_INT(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_INT_V(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_V)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_INT_HNDLR(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_HNDLR)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_INT_READ(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_READ)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_INT_WRITE(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_WRITE)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_STATUS(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_STATUS)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_FIFO(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_FIFO)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_READ(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_READ)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_WRITE(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_WRITE)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+#define SSI_DBG_SLV_CTRL(...)  do {\
+    if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_SLV_CTRL)) \
+        DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
+}while(0)
+
+typedef enum _SSI_DBG_TYPE_LIST_ {
+    DBG_TYPE_ENTRANCE  = 1 << 0,
+    DBG_TYPE_INIT      = 1 << 1,
+    DBG_TYPE_INIT_V    = 1 << 2,
+    DBG_TYPE_INIT_VV   = 1 << 3,
+    DBG_TYPE_PINMUX    = 1 << 4,
+    DBG_TYPE_ENDIS     = 1 << 5,
+    DBG_TYPE_INT       = 1 << 6,
+    DBG_TYPE_INT_V     = 1 << 7,
+    DBG_TYPE_INT_HNDLR = 1 << 8,
+    DBG_TYPE_INT_READ  = 1 << 9,
+    DBG_TYPE_INT_WRITE = 1 << 10,
+    DBG_TYPE_STATUS    = 1 << 11,
+    DBG_TYPE_FIFO      = 1 << 12,
+    DBG_TYPE_READ      = 1 << 13,
+    DBG_TYPE_WRITE     = 1 << 14,
+    DBG_TYPE_SLV_CTRL  = 1 << 15
+} SSI_DBG_TYPE_LIST, *PSSI_DBG_TYPE_LIST;
+
+ typedef struct _SSI_DMA_CONFIG_ {
+    VOID *pHalGdmaOp;
+    VOID *pTxHalGdmaAdapter;
+    VOID *pRxHalGdmaAdapter;
+    u8    RxDmaBurstSize;
+    u8    TxDmaBurstSize;
+    u8    RxDmaEnable;
+    u8    TxDmaEnable;
+    IRQ_HANDLE RxGdmaIrqHandle;
+    IRQ_HANDLE TxGdmaIrqHandle;
+}SSI_DMA_CONFIG, *PSSI_DMA_CONFIG;
+
+/**
+ * DesignWare SSI Configurations
+ */
+typedef struct _HAL_SSI_ADAPTOR_ {
+    SSI_DMA_CONFIG DmaConfig;
+    IRQ_HANDLE IrqHandle;
+    //
+    VOID (*RxCompCallback)(VOID *Para);
+    VOID *RxCompCbPara;
+    VOID *RxData;
+    VOID (*TxCompCallback)(VOID *Para);
+    VOID *TxCompCbPara;
+    VOID *TxData;
+    u32  DmaRxDataLevel;
+    u32  DmaTxDataLevel;
+    u32  InterruptPriority;
+    u32  RxLength;
+    u32  RxLengthRemainder;
+    u32  RxThresholdLevel;
+    u32  TxLength;
+    u32  TxThresholdLevel;
+    u32  SlaveSelectEnable;
+    //
+    u16  ClockDivider;
+    u16  DataFrameNumber;
+    //
+    u8   ControlFrameSize;
+    u8   DataFrameFormat;
+    u8   DataFrameSize;
+    u8   DmaControl;
+    u8   Index;
+    u8   InterruptMask;
+    u8   MicrowireDirection;
+    u8   MicrowireHandshaking;
+    u8   MicrowireTransferMode;
+    u8   PinmuxSelect;
+    u8   Role;
+    u8   SclkPhase;
+    u8   SclkPolarity;
+    u8   SlaveOutputEnable;
+    u8   TransferMode;
+    u8   TransferMechanism;
+
+    // Extend
+    u32 Reserved1;
+    u8 DefaultRxThresholdLevel;
+}HAL_SSI_ADAPTOR, *PHAL_SSI_ADAPTOR;
+
+typedef struct _HAL_SSI_OP_{
+    HAL_Status (*HalSsiPinmuxEnable)(VOID *Adaptor);
+    HAL_Status (*HalSsiPinmuxDisable)(VOID *Adaptor);
+    HAL_Status (*HalSsiEnable)(VOID *Adaptor);
+    HAL_Status (*HalSsiDisable)(VOID *Adaptor);
+    HAL_Status (*HalSsiInit)(VOID *Adaptor);
+    HAL_Status (*HalSsiSetSclkPolarity)(VOID *Adaptor);
+    HAL_Status (*HalSsiSetSclkPhase)(VOID *Adaptor);
+    HAL_Status (*HalSsiWrite)(VOID *Adaptor, u32 value);
+    HAL_Status (*HalSsiLoadSetting)(VOID *Adaptor, VOID *Setting);
+    HAL_Status (*HalSsiSetInterruptMask)(VOID *Adaptor);
+    HAL_Status (*HalSsiSetDeviceRole)(VOID *Adaptor, u32 Role);
+    HAL_Status (*HalSsiInterruptEnable)(VOID *Adaptor);
+    HAL_Status (*HalSsiInterruptDisable)(VOID *Adaptor);
+    HAL_Status (*HalSsiReadInterrupt)(VOID *Adaptor, VOID *RxData, u32 Length);
+    HAL_Status (*HalSsiSetRxFifoThresholdLevel)(VOID *Adaptor);
+    HAL_Status (*HalSsiSetTxFifoThresholdLevel)(VOID *Adaptor);
+    HAL_Status (*HalSsiWriteInterrupt)(VOID *Adaptor, u8 *TxData, u32 Length);
+    HAL_Status (*HalSsiSetSlaveEnableRegister)(VOID *Adaptor, u32 SlaveIndex);
+    u32  (*HalSsiBusy)(VOID *Adaptor);
+    u32  (*HalSsiReadable)(VOID *Adaptor);
+    u32  (*HalSsiWriteable)(VOID *Adaptor);
+    u32  (*HalSsiGetInterruptMask)(VOID *Adaptor);
+    u32  (*HalSsiGetRxFifoLevel)(VOID *Adaptor);
+    u32  (*HalSsiGetTxFifoLevel)(VOID *Adaptor);
+    u32  (*HalSsiGetStatus)(VOID *Adaptor);
+    u32  (*HalSsiGetInterruptStatus)(VOID *Adaptor);
+    u32  (*HalSsiRead)(VOID *Adaptor);
+    u32  (*HalSsiGetRawInterruptStatus)(VOID *Adaptor);
+    u32  (*HalSsiGetSlaveEnableRegister)(VOID *Adaptor);
+}HAL_SSI_OP, *PHAL_SSI_OP;
+
+typedef struct _DW_SSI_DEFAULT_SETTING_ {
+    VOID (*RxCompCallback)(VOID *Para);
+    VOID *RxCompCbPara;
+    VOID *RxData;
+    VOID (*TxCompCallback)(VOID *Para);
+    VOID *TxCompCbPara;
+    VOID *TxData;
+    u32  DmaRxDataLevel;
+    u32  DmaTxDataLevel;
+    u32  InterruptPriority;
+    u32  RxLength;
+    u32  RxLengthRemainder;
+    u32  RxThresholdLevel;
+    u32  TxLength;
+    u32  TxThresholdLevel;
+    u32  SlaveSelectEnable;
+    //
+    u16  ClockDivider;
+    u16  DataFrameNumber;
+    //
+    u8   ControlFrameSize;
+    u8   DataFrameFormat;
+    u8   DataFrameSize;
+    u8   DmaControl;
+    //u8   Index;
+    u8   InterruptMask;
+    u8   MicrowireDirection;
+    u8   MicrowireHandshaking;
+    u8   MicrowireTransferMode;
+    //u8   PinmuxSelect;
+    //u8   Role;
+    u8   SclkPhase;
+    u8   SclkPolarity;
+    u8   SlaveOutputEnable;
+    u8   TransferMode;
+    u8   TransferMechanism;
+} DW_SSI_DEFAULT_SETTING, *PDW_SSI_DEFAULT_SETTING;
+
+
+struct spi_s {
+    HAL_SSI_ADAPTOR spi_adp;
+    HAL_SSI_OP      spi_op;
+    u32 irq_handler;
+    u32 irq_id;
+    u32 dma_en;
+    u32 state;
+    u8 sclk;
+#ifdef CONFIG_GDMA_EN    
+    HAL_GDMA_ADAPTER spi_gdma_adp_tx;
+    HAL_GDMA_ADAPTER spi_gdma_adp_rx;
+#endif    
+};
+
+VOID HalSsiOpInit(VOID *Adaptor);
+static __inline__ VOID HalSsiSetSclk(
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter,
+    IN u32 ClkRate)
+{
+    HalSsiSetSclkRtl8195a((VOID*)pHalSsiAdapter, ClkRate);
+}
+
+HAL_Status HalSsiInit(VOID * Data);
+HAL_Status HalSsiDeInit(VOID * Data);
+HAL_Status HalSsiEnable(VOID * Data);
+HAL_Status HalSsiDisable(VOID * Data);
+
+
+#ifdef CONFIG_GDMA_EN    
+HAL_Status HalSsiTxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
+VOID HalSsiTxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
+HAL_Status HalSsiRxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
+VOID HalSsiRxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
+
+static __inline__ VOID
+HalSsiDmaInit(
+    IN PHAL_SSI_ADAPTOR pHalSsiAdapter
+)
+{
+    HalSsiDmaInitRtl8195a((void *)pHalSsiAdapter);
+}
+
+static __inline__ HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length)
+{
+    return (HalSsiDmaSendRtl8195a(Adapter, pTxData, Length));
+}
+
+static __inline__ HAL_Status HalSsiDmaRecv(VOID *Adapter, u8  *pRxData, u32 Length)
+{
+    return (HalSsiDmaRecvRtl8195a(Adapter, pRxData, Length));
+}
+    
+
+#endif  // end of "#ifdef CONFIG_GDMA_EN"
+
+#endif
+

sdk/component/soc/realtek/8195a/fwlib/hal_timer.h

@@ -0,0 +1,58 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_TIMER_H_
+#define _HAL_TIMER_H_
+#include "basic_types.h"
+#include "hal_platform.h"
+#include "rtl8195a_timer.h"
+
+#define GTIMER_CLK_HZ           (32768)
+#define GTIMER_TICK_US          (1000000/GTIMER_CLK_HZ)
+
+typedef enum _TIMER_MODE_ {
+    FREE_RUN_MODE = 0,
+    USER_DEFINED = 1
+}TIMER_MODE, *PTIMER_MODE;
+
+
+typedef struct _TIMER_ADAPTER_ {
+
+    u32         TimerLoadValueUs;
+    u32         TimerIrqPriority;
+    TIMER_MODE  TimerMode;
+    IRQ_HANDLE  IrqHandle;
+    u8          TimerId;    
+    u8          IrqDis;
+
+}TIMER_ADAPTER, *PTIMER_ADAPTER;
+
+
+typedef struct _HAL_TIMER_OP_ {
+    u32  (*HalGetTimerId)(u32 *TimerId);
+    BOOL (*HalTimerInit)(VOID *Data);
+    u32  (*HalTimerReadCount)(u32 TimerId);
+    VOID (*HalTimerIrqClear)(u32 TimerId);
+    VOID (*HalTimerDis)(u32 TimerId);
+    VOID (*HalTimerEn)(u32 TimerId);
+    VOID (*HalTimerDumpReg)(u32 TimerId);
+}HAL_TIMER_OP, *PHAL_TIMER_OP;
+
+VOID HalTimerOpInit_Patch(
+    IN  VOID *Data
+);
+
+
+//======================================================
+// ROM Function prototype
+_LONG_CALL_ VOID HalTimerOpInitV02(IN  VOID *Data);
+
+#define HalTimerOpInit      HalTimerOpInit_Patch
+
+#endif

sdk/component/soc/realtek/8195a/fwlib/hal_uart.h

@@ -0,0 +1,204 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_UART_H_
+#define _HAL_UART_H_
+
+#include "rtl8195a_uart.h"
+
+/**
+ * RUART Configurations
+ */
+#define UART_WAIT_FOREVER       0xffffffff
+
+typedef struct _UART_DMA_CONFIG_ {
+    u8 TxDmaEnable;
+    u8 RxDmaEnable;
+    u8 TxDmaBurstSize;
+    u8 RxDmaBurstSize;
+    VOID *pHalGdmaOp;
+    VOID *pTxHalGdmaAdapter;
+    VOID *pRxHalGdmaAdapter;
+    IRQ_HANDLE TxGdmaIrqHandle;
+    IRQ_HANDLE RxGdmaIrqHandle;
+}UART_DMA_CONFIG, *PUART_DMA_CONFIG;
+
+typedef struct _HAL_RUART_ADAPTER_ {
+    u32 BaudRate;
+    u32 FlowControl;
+    u32 FifoControl;
+    u32 Interrupts;
+    u32 TxCount;     // how many byte to TX
+    u32 RxCount;     // how many bytes to RX
+    u8 *pTxBuf;
+    u8 *pRxBuf;
+    HAL_UART_State State;       // UART state
+    u8 Status;      // Transfer Status
+    u8 Locked;      // is UART locked for operation
+    u8 UartIndex;
+    u8 WordLen;     // word length select: 0 -> 7 bits, 1 -> 8 bits
+    u8 StopBit;     // word length select: 0 -> 1 stop bit, 1 -> 2 stop bit
+    u8 Parity;      // parity check enable
+    u8 ParityType;  // parity check type
+    u8 StickParity;
+    u8 ModemStatus; // the modem status
+    u8 DmaEnable;
+    u8 TestCaseNumber;
+    u8 PinmuxSelect;
+    BOOL PullMode;
+    IRQ_HANDLE IrqHandle;
+    PUART_DMA_CONFIG DmaConfig;
+    VOID (*ModemStatusInd)(VOID *pAdapter);    // modem status indication interrupt handler
+    VOID (*TxTDCallback)(VOID *pAdapter);      // User Tx Done callback function
+    VOID (*RxDRCallback)(VOID *pAdapter);      // User Rx Data ready callback function
+    VOID (*TxCompCallback)(VOID *para);    // User Tx complete callback function
+    VOID (*RxCompCallback)(VOID *para);    // User Rx complete callback function
+    VOID *TxTDCbPara;   // the pointer agrument for TxTDCallback
+    VOID *RxDRCbPara;   // the pointer agrument for RxDRCallback
+    VOID *TxCompCbPara; // the pointer argument for TxCompCbPara
+    VOID *RxCompCbPara; // the pointer argument for RxCompCallback
+    VOID (*EnterCritical)(void);
+    VOID (*ExitCritical)(void);
+
+    //1 New member only can be added below: members above must be fixed for ROM code
+    u32 *pDefaultBaudRateTbl;      // point to the table of pre-defined baud rate
+    u8 *pDefaultOvsrRTbl;         // point to the table of OVSR for pre-defined baud rate
+    u16 *pDefaultDivTbl;           // point to the table of DIV for pre-defined baud rate
+    u8  *pDefOvsrAdjBitTbl_10;     // point to the table of OVSR-Adj bits for 10 bits
+    u8  *pDefOvsrAdjBitTbl_9;     // point to the table of OVSR-Adj bits for 9 bits
+    u8  *pDefOvsrAdjBitTbl_8;     // point to the table of OVSR-Adj bits for 8 bits
+    u16 *pDefOvsrAdjTbl_10;       // point to the table of OVSR-Adj for pre-defined baud rate
+    u16 *pDefOvsrAdjTbl_9;       // point to the table of OVSR-Adj for pre-defined baud rate
+    u16 *pDefOvsrAdjTbl_8;       // point to the table of OVSR-Adj for pre-defined baud rate
+    u32 BaudRateUsing;             // Current using Baud-Rate    
+
+#if CONFIG_CHIP_E_CUT
+    u8  TxState;
+    u8  RxState;
+    u32 TxInitSize;     // how many byte to TX at atart
+    u32 RxInitSize;     // how many bytes to RX at start
+
+    VOID (*RuartEnterCritical)(VOID *para);   // enter critical: disable UART interrupt
+    VOID (*RuartExitCritical)(VOID *para);    // exit critical: re-enable UART interrupt
+    VOID (*TaskYield)(VOID *para);    // User Task Yield: do a context switch while waitting
+    VOID *TaskYieldPara;   // the agrument (pointer) for TaskYield
+#endif    // #if CONFIG_CHIP_E_CUT
+}HAL_RUART_ADAPTER, *PHAL_RUART_ADAPTER;
+
+typedef struct _HAL_RUART_OP_ {
+    VOID (*HalRuartAdapterLoadDef)(VOID *pAdp, u8 UartIdx);    // Load UART adapter default setting
+    VOID (*HalRuartTxGdmaLoadDef)(VOID *pAdp, VOID *pCfg);     // Load TX GDMA default setting
+    VOID (*HalRuartRxGdmaLoadDef)(VOID *pAdp, VOID *pCfg);     // Load RX GDMA default setting
+    HAL_Status (*HalRuartResetRxFifo)(VOID *Data);
+    HAL_Status (*HalRuartInit)(VOID *Data);
+    VOID (*HalRuartDeInit)(VOID *Data);
+    HAL_Status (*HalRuartPutC)(VOID *Data, u8 TxData);
+    u32  (*HalRuartSend)(VOID *Data, u8 *pTxData, u32 Length, u32 Timeout);
+    HAL_Status  (*HalRuartIntSend)(VOID *Data, u8 *pTxData, u32 Length);
+    HAL_Status  (*HalRuartDmaSend)(VOID *Data, u8 *pTxData, u32 Length);
+    HAL_Status  (*HalRuartStopSend)(VOID *Data);
+    HAL_Status (*HalRuartGetC)(VOID *Data, u8 *pRxByte);
+    u32  (*HalRuartRecv)(VOID *Data, u8  *pRxData, u32 Length, u32 Timeout);
+    HAL_Status  (*HalRuartIntRecv)(VOID *Data, u8  *pRxData, u32 Length);
+    HAL_Status  (*HalRuartDmaRecv)(VOID *Data, u8  *pRxData, u32 Length);
+    HAL_Status  (*HalRuartStopRecv)(VOID *Data);
+    u8   (*HalRuartGetIMR)(VOID *Data);
+    VOID (*HalRuartSetIMR)(VOID *Data);
+    u32  (*HalRuartGetDebugValue)(VOID *Data, u32 DbgSel);
+    VOID (*HalRuartDmaInit)(VOID *Data);
+    VOID (*HalRuartRTSCtrl)(VOID *Data, BOOLEAN RtsCtrl);
+    VOID (*HalRuartRegIrq)(VOID *Data);
+    VOID (*HalRuartIntEnable)(VOID *Data);
+    VOID (*HalRuartIntDisable)(VOID *Data);
+}HAL_RUART_OP, *PHAL_RUART_OP;
+
+typedef struct _RUART_DATA_ {
+    PHAL_RUART_ADAPTER pHalRuartAdapter;
+    BOOL PullMode;
+    u8   BinaryData;
+    u8   SendBuffer;
+    u8   RecvBuffer;
+}RUART_DATA, *PRUART_DATA;
+
+typedef struct _RUART_ADAPTER_ {
+    PHAL_RUART_OP      pHalRuartOp;
+    PHAL_RUART_ADAPTER pHalRuartAdapter;
+    PUART_DMA_CONFIG   pHalRuartDmaCfg;
+}RUART_ADAPTER, *PRUART_ADAPTER;
+
+extern VOID
+HalRuartOpInit(
+        IN VOID *Data
+);
+
+extern HAL_Status
+HalRuartTxGdmaInit(
+    PHAL_RUART_OP pHalRuartOp,
+    PHAL_RUART_ADAPTER pHalRuartAdapter,
+    PUART_DMA_CONFIG pUartGdmaConfig
+);
+
+extern VOID
+HalRuartTxGdmaDeInit(
+    PUART_DMA_CONFIG pUartGdmaConfig
+);
+
+extern HAL_Status
+HalRuartRxGdmaInit(
+    PHAL_RUART_OP pHalRuartOp,
+    PHAL_RUART_ADAPTER pHalRuartAdapter,
+    PUART_DMA_CONFIG pUartGdmaConfig
+);
+
+extern VOID
+HalRuartRxGdmaDeInit(
+    PUART_DMA_CONFIG pUartGdmaConfig
+);
+
+extern HAL_Status
+HalRuartResetTxFifo(
+    VOID *Data
+);
+
+extern HAL_Status 
+HalRuartSetBaudRate(
+        IN VOID *Data
+);
+
+extern HAL_Status 
+HalRuartInit(
+    IN VOID *Data
+);
+
+extern VOID
+HalRuartDeInit(
+    IN VOID *Data
+);
+
+extern HAL_Status 
+HalRuartDisable(
+    IN VOID *Data
+);
+
+extern HAL_Status 
+HalRuartEnable(
+    IN VOID *Data
+);
+
+HAL_Status 
+HalRuartFlowCtrl(
+    IN VOID *Data
+);
+
+extern const HAL_RUART_OP _HalRuartOp;
+extern HAL_Status RuartLock (PHAL_RUART_ADAPTER pHalRuartAdapter);
+extern VOID RuartUnLock (PHAL_RUART_ADAPTER pHalRuartAdapter);
+
+#endif
+

sdk/component/soc/realtek/8195a/fwlib/hal_usb.h

@@ -0,0 +1,15 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _HAL_USB_H_
+#define _HAL_USB_H_
+
+#include "rtl8195a_usb.h"
+
+#endif //_HAL_USB_H_

sdk/component/soc/realtek/8195a/fwlib/hal_util.h

@@ -0,0 +1,252 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+#ifndef _HAL_UTIL_H_
+#define _HAL_UTIL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Simple doubly linked list implementation.
+ *
+ * Some of the internal functions ("__xxx") are useful when
+ * manipulating whole lists rather than single entries, as
+ * sometimes we already know the next/prev entries and we can
+ * generate better code by using them directly rather than
+ * using the generic single-entry routines.
+ */
+struct LIST_HEADER {
+	struct LIST_HEADER *Next, *Prev;
+};
+
+typedef struct  LIST_HEADER     _LIST;
+
+//#define RTL_LIST_HEAD_INIT(name) { &(name), &(name) }
+
+#define RTL_INIT_LIST_HEAD(ptr) do { \
+	(ptr)->Next = (ptr); (ptr)->Prev = (ptr); \
+} while (0)
+
+
+/*
+ * Insert a new entry between two known consecutive entries. 
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+ static __inline__ VOID 
+ __List_Add(
+    IN  struct LIST_HEADER * New,
+    IN  struct LIST_HEADER * Prev,
+    IN  struct LIST_HEADER * Next
+)
+{
+	Next->Prev = New;
+	New->Next = Next;
+	New->Prev = Prev;
+	Prev->Next = New;
+}
+
+/*
+ * Delete a list entry by making the prev/next entries
+ * point to each other.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+ static __inline__ VOID
+ __List_Del(
+    IN  struct LIST_HEADER * Prev,
+    IN  struct LIST_HEADER * Next
+ )
+{
+	Next->Prev = Prev;
+	Prev->Next = Next;
+}
+
+/**
+ * ListDel - deletes entry from list.
+ * @entry: the element to delete from the list.
+ * Note: list_empty on entry does not return true after this, the entry is in an undefined state.
+ */
+static __inline__ VOID 
+ListDel(
+    IN  struct LIST_HEADER *Entry
+)
+{
+	__List_Del(Entry->Prev, Entry->Next);
+}
+
+/**
+ * ListDelInit - deletes entry from list and reinitialize it.
+ * @entry: the element to delete from the list.
+ */
+static  __inline__ VOID
+ListDelInit(
+    IN  struct LIST_HEADER *Entry
+)
+{
+	__List_Del(Entry->Prev, Entry->Next);
+	RTL_INIT_LIST_HEAD(Entry);
+
+}
+
+/**
+ * ListEmpty - tests whether a list is empty
+ * @head: the list to test.
+ */
+static __inline__ u32 
+ListEmpty(
+    IN  struct LIST_HEADER *Head
+)
+{
+	return Head->Next == Head;
+}
+
+/**
+ * ListSplice - join two lists
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ */
+static __inline__ VOID 
+ListSplice(
+    IN  struct LIST_HEADER *List,
+    IN  struct LIST_HEADER *Head
+)
+{
+	struct LIST_HEADER *First = List->Next;
+
+	if (First != List) {
+		struct LIST_HEADER *Last = List->Prev;
+		struct LIST_HEADER *At = Head->Next;
+
+		First->Prev = Head;
+		Head->Next = First;
+
+		Last->Next = At;
+		At->Prev = Last;
+	}
+}
+
+static __inline__ VOID 
+ListAdd(
+    IN  struct LIST_HEADER *New, 
+    IN  struct LIST_HEADER *head
+)
+{
+	__List_Add(New, head, head->Next);
+}
+
+
+static __inline__ VOID 
+ListAddTail(
+    IN  struct LIST_HEADER *New, 
+    IN  struct LIST_HEADER *head
+)
+{
+	__List_Add(New, head->Prev, head);
+}
+
+static __inline VOID 
+RtlInitListhead(
+    IN  _LIST *list
+)
+{
+    RTL_INIT_LIST_HEAD(list);
+}
+
+
+/*
+For the following list_xxx operations, 
+caller must guarantee the atomic context.
+Otherwise, there will be racing condition.
+*/
+static __inline u32	
+RtlIsListEmpty(
+    IN  _LIST *phead
+)
+{
+
+	if (ListEmpty(phead))
+		return _TRUE;
+	else
+		return _FALSE;
+	
+}
+
+static __inline VOID 
+RtlListInsertHead(
+    IN  _LIST *plist,
+    IN  _LIST *phead
+)
+{
+	ListAdd(plist, phead);
+}
+
+static __inline VOID 
+RtlListInsertTail(
+    IN  _LIST *plist,
+    IN  _LIST *phead
+)
+{
+	ListAddTail(plist, phead);	
+}
+
+
+static __inline _LIST
+*RtlListGetNext(
+    IN  _LIST *plist
+)
+{
+	return plist->Next;
+}
+
+static __inline VOID 
+RtlListDelete(
+    IN _LIST *plist
+)
+{
+	ListDelInit(plist);
+}
+
+#define RTL_LIST_CONTAINOR(ptr, type, member) \
+        ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
+        
+#ifndef CONTAINER_OF
+#define CONTAINER_OF(ptr, type, member) \
+        ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
+#endif
+/*
+#define list_entry(ptr, type, member) \
+ 		CONTAINER_OF(ptr, type, member)
+
+#define list_first_entry(ptr, type, member) \
+        list_entry((ptr)->Next, type, member) 		
+
+#define list_next_entry(pos, member, type) \
+        list_entry((pos)->member.Next, type, member)
+
+#define list_for_each_entry(pos, head, member, type) \
+        for (pos = list_first_entry(head, type, member); \
+             &pos->member != (head); \
+             pos = list_next_entry(pos, member, type))
+#define list_for_each(pos, head) \
+        for (pos = (head)->Next; pos != (head); pos = pos->Next)
+*/
+
+#ifndef BIT
+	#define BIT(x)	( 1 << (x))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //_HAL_UTIL_H_

sdk/component/soc/realtek/8195a/fwlib/hal_vector_table.h

@@ -0,0 +1,53 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _HAL_VECTOR_TABLE_H_
+#define _HAL_VECTOR_TABLE_H_
+
+
+
+
+extern _LONG_CALL_ROM_ VOID
+VectorTableInitRtl8195A(
+    IN  u32 StackP
+);
+
+extern _LONG_CALL_ROM_ VOID
+VectorTableInitForOSRtl8195A(
+    IN  VOID *PortSVC,
+    IN  VOID *PortPendSVH,
+    IN  VOID *PortSysTick    
+);
+
+extern _LONG_CALL_ROM_ BOOL
+VectorIrqRegisterRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+);
+
+extern _LONG_CALL_ROM_ BOOL
+VectorIrqUnRegisterRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+);
+
+
+extern _LONG_CALL_ROM_ VOID
+VectorIrqEnRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+);
+
+extern _LONG_CALL_ROM_ VOID
+VectorIrqDisRtl8195A(
+    IN  PIRQ_HANDLE pIrqHandle
+);
+
+ 
+extern _LONG_CALL_ROM_ VOID
+HalPeripheralIntrHandle(VOID);
+#endif //_HAL_VECTOR_TABLE_H_

sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h

@@ -0,0 +1,158 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+#ifndef _HAL_8195A_H_
+#define _HAL_8195A_H_
+
+#include "platform_autoconf.h"
+#include "basic_types.h"
+#include "section_config.h"
+#include "rtl8195a_sys_on.h"
+#include "rtl8195a_peri_on.h"
+#include "hal_platform.h"
+#include "hal_pinmux.h"
+#include "hal_api.h"
+#include "hal_peri_on.h"
+#include "hal_misc.h"
+#include "hal_irqn.h"
+#include "hal_vector_table.h"
+#include "hal_diag.h"
+#include "hal_spi_flash.h"
+#include "hal_timer.h"
+#include "hal_util.h"
+#include "hal_efuse.h"
+#include "hal_soc_ps_monitor.h"
+#include "diag.h"
+#include "hal_common.h"
+#include "hal_soc_ps_monitor.h"
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M3 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM3_REV                      0x0200    /**< Core revision r0p0 */
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         1         /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm3.h"
+
+#ifdef CONFIG_TIMER_EN
+#include "hal_timer.h"
+#endif
+
+#ifdef CONFIG_GDMA_EN
+#include "hal_gdma.h"
+#include "rtl8195a_gdma.h"
+#endif
+
+#ifdef CONFIG_GPIO_EN
+#include "hal_gpio.h"
+#include "rtl8195a_gpio.h"
+#endif
+
+#ifdef CONFIG_SPI_COM_EN
+#include "hal_ssi.h"
+#include "rtl8195a_ssi.h"
+#endif
+
+#ifdef CONFIG_UART_EN
+#include "hal_uart.h"
+#include "rtl8195a_uart.h"
+#endif
+
+#ifdef CONFIG_I2C_EN
+#include "hal_i2c.h"
+#include "rtl8195a_i2c.h"
+#endif
+
+#ifdef CONFIG_PCM_EN
+#include "hal_pcm.h"
+#include "rtl8195a_pcm.h"
+#endif
+
+#ifdef CONFIG_PWM_EN
+#include "hal_pwm.h"
+#include "rtl8195a_pwm.h"
+#endif
+
+#ifdef CONFIG_I2S_EN
+#include "hal_i2s.h"
+#include "rtl8195a_i2s.h"
+#endif
+
+#ifdef CONFIG_DAC_EN
+#include "hal_dac.h"
+#include "rtl8195a_dac.h"
+#endif
+
+#ifdef CONFIG_ADC_EN
+#include "hal_adc.h"
+#include "rtl8195a_adc.h"
+#endif
+
+#ifdef CONFIG_SDR_EN
+#endif
+
+#ifdef CONFIG_SPIC_EN
+#endif
+
+#ifdef CONFIG_SDIO_DEVICE_EN
+#include "hal_sdio.h"
+#endif
+
+#ifdef CONFIG_NFC_EN
+#include "hal_nfc.h"
+#include "rtl8195a_nfc.h"
+#endif
+
+#ifdef CONFIG_WDG
+#include "rtl8195a_wdt.h"
+#endif
+
+#ifdef CONFIG_USB_EN
+#include "hal_usb.h"
+#include "rtl8195a_usb.h"
+#endif
+
+#include "hal_log_uart.h"
+
+// firmware information, located at the header of Image2
+#define FW_VERSION          (0x0100)
+#define FW_SUBVERSION       (0x0001)
+#define FW_CHIP_ID          (0x8195)
+#define FW_CHIP_VER         (0x01)
+#define FW_BUS_TYPE         (0x01)          // the iNIC firmware type: USB/SDIO
+#define FW_INFO_RSV1        (0x00)          // the firmware information reserved
+#define FW_INFO_RSV2        (0x00)          // the firmware information reserved
+#define FW_INFO_RSV3        (0x00)          // the firmware information reserved
+#define FW_INFO_RSV4        (0x00)          // the firmware information reserved
+
+#define FLASH_RESERVED_DATA_BASE		0x8000  // reserve 32K for Image1
+#define FLASH_SYSTEM_DATA_ADDR			0x9000  // reserve 32K+4K for Image1 + Reserved data
+// Flash Map for Calibration data
+#define FLASH_CAL_DATA_BASE				0xA000
+#define FLASH_CAL_DATA_ADDR(_offset)	(FLASH_CAL_DATA_BASE + _offset)
+#define FLASH_CAL_DATA_SIZE				0x1000
+#define FLASH_SECTOR_SIZE				0x1000
+// SPIC Calibration Data
+#define FLASH_SPIC_PARA_OFFSET          0x80
+#define FLASH_SPIC_PARA_BASE            (FLASH_SYSTEM_DATA_ADDR+FLASH_SPIC_PARA_OFFSET)
+// SDRC Calibration Data
+#define FLASH_SDRC_PARA_OFFSET          0x180
+#define FLASH_SDRC_PARA_BASE            (FLASH_SYSTEM_DATA_ADDR+FLASH_SDRC_PARA_OFFSET)
+// ADC Calibration Data
+#define FLASH_ADC_PARA_OFFSET           0x200
+#define FLASH_ADC_PARA_BASE             (FLASH_SYSTEM_DATA_ADDR+FLASH_ADC_PARA_OFFSET)
+
+#endif //_HAL_8195A_H_

sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_adc.h

@@ -0,0 +1,350 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _RTL8195A_ADC_H_
+#define _RTL8195A_ADC_H_
+
+
+//================ Register Bit Field ==========================
+//2 REG_ADC_FIFO_READ
+
+#define BIT_SHIFT_ADC_FIFO_RO 0
+#define BIT_MASK_ADC_FIFO_RO 0xffffffffL
+#define BIT_ADC_FIFO_RO(x)                    	(((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
+#define BIT_CTRL_ADC_FIFO_RO(x)               	(((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
+#define BIT_GET_ADC_FIFO_RO(x)                	(((x) >> BIT_SHIFT_ADC_FIFO_RO) & BIT_MASK_ADC_FIFO_RO)
+
+
+//2 REG_ADC_CONTROL
+
+#define BIT_SHIFT_ADC_DBG_SEL 24
+#define BIT_MASK_ADC_DBG_SEL 0x7
+#define BIT_ADC_DBG_SEL(x)                    	(((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
+#define BIT_CTRL_ADC_DBG_SEL(x)               	(((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
+#define BIT_GET_ADC_DBG_SEL(x)                	(((x) >> BIT_SHIFT_ADC_DBG_SEL) & BIT_MASK_ADC_DBG_SEL)
+
+
+#define BIT_SHIFT_ADC_THRESHOLD 16
+#define BIT_MASK_ADC_THRESHOLD 0x3f
+#define BIT_ADC_THRESHOLD(x)                  	(((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
+#define BIT_CTRL_ADC_THRESHOLD(x)             	(((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
+#define BIT_GET_ADC_THRESHOLD(x)              	(((x) >> BIT_SHIFT_ADC_THRESHOLD) & BIT_MASK_ADC_THRESHOLD)
+
+
+#define BIT_SHIFT_ADC_BURST_SIZE 8
+#define BIT_MASK_ADC_BURST_SIZE 0x1f
+#define BIT_ADC_BURST_SIZE(x)                 	(((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
+#define BIT_CTRL_ADC_BURST_SIZE(x)            	(((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
+#define BIT_GET_ADC_BURST_SIZE(x)             	(((x) >> BIT_SHIFT_ADC_BURST_SIZE) & BIT_MASK_ADC_BURST_SIZE)
+
+#define BIT_ADC_ENDIAN                        	BIT(3)
+#define BIT_SHIFT_ADC_ENDIAN                  	3
+#define BIT_MASK_ADC_ENDIAN                   	0x1
+#define BIT_CTRL_ADC_ENDIAN(x)                	(((x) & BIT_MASK_ADC_ENDIAN) << BIT_SHIFT_ADC_ENDIAN)
+
+#define BIT_ADC_OVERWRITE                     	BIT(2)
+#define BIT_SHIFT_ADC_OVERWRITE               	2
+#define BIT_MASK_ADC_OVERWRITE                	0x1
+#define BIT_CTRL_ADC_OVERWRITE(x)             	(((x) & BIT_MASK_ADC_OVERWRITE) << BIT_SHIFT_ADC_OVERWRITE)
+
+#define BIT_ADC_ONESHOT                       	BIT(1)
+#define BIT_SHIFT_ADC_ONESHOT                 	1
+#define BIT_MASK_ADC_ONESHOT                  	0x1
+#define BIT_CTRL_ADC_ONESHOT(x)               	(((x) & BIT_MASK_ADC_ONESHOT) << BIT_SHIFT_ADC_ONESHOT)
+
+#define BIT_ADC_COMP_ONLY                     	BIT(0)
+#define BIT_SHIFT_ADC_COMP_ONLY               	0
+#define BIT_MASK_ADC_COMP_ONLY                	0x1
+#define BIT_CTRL_ADC_COMP_ONLY(x)             	(((x) & BIT_MASK_ADC_COMP_ONLY) << BIT_SHIFT_ADC_COMP_ONLY)
+
+
+//2 REG_ADC_INTR_EN
+#define BIT_ADC_AWAKE_CPU_EN                  	BIT(7)
+#define BIT_SHIFT_ADC_AWAKE_CPU_EN            	7
+#define BIT_MASK_ADC_AWAKE_CPU_EN             	0x1
+#define BIT_CTRL_ADC_AWAKE_CPU_EN(x)          	(((x) & BIT_MASK_ADC_AWAKE_CPU_EN) << BIT_SHIFT_ADC_AWAKE_CPU_EN)
+
+#define BIT_ADC_FIFO_RD_ERROR_EN              	BIT(6)
+#define BIT_SHIFT_ADC_FIFO_RD_ERROR_EN        	6
+#define BIT_MASK_ADC_FIFO_RD_ERROR_EN         	0x1
+#define BIT_CTRL_ADC_FIFO_RD_ERROR_EN(x)      	(((x) & BIT_MASK_ADC_FIFO_RD_ERROR_EN) << BIT_SHIFT_ADC_FIFO_RD_ERROR_EN)
+
+#define BIT_ADC_FIFO_RD_REQ_EN                	BIT(5)
+#define BIT_SHIFT_ADC_FIFO_RD_REQ_EN          	5
+#define BIT_MASK_ADC_FIFO_RD_REQ_EN           	0x1
+#define BIT_CTRL_ADC_FIFO_RD_REQ_EN(x)        	(((x) & BIT_MASK_ADC_FIFO_RD_REQ_EN) << BIT_SHIFT_ADC_FIFO_RD_REQ_EN)
+
+#define BIT_ADC_FIFO_FULL_EN                  	BIT(4)
+#define BIT_SHIFT_ADC_FIFO_FULL_EN            	4
+#define BIT_MASK_ADC_FIFO_FULL_EN             	0x1
+#define BIT_CTRL_ADC_FIFO_FULL_EN(x)          	(((x) & BIT_MASK_ADC_FIFO_FULL_EN) << BIT_SHIFT_ADC_FIFO_FULL_EN)
+
+#define BIT_ADC_COMP_3_EN                     	BIT(3)
+#define BIT_SHIFT_ADC_COMP_3_EN               	3
+#define BIT_MASK_ADC_COMP_3_EN                	0x1
+#define BIT_CTRL_ADC_COMP_3_EN(x)             	(((x) & BIT_MASK_ADC_COMP_3_EN) << BIT_SHIFT_ADC_COMP_3_EN)
+
+#define BIT_ADC_COMP_2_EN                     	BIT(2)
+#define BIT_SHIFT_ADC_COMP_2_EN               	2
+#define BIT_MASK_ADC_COMP_2_EN                	0x1
+#define BIT_CTRL_ADC_COMP_2_EN(x)             	(((x) & BIT_MASK_ADC_COMP_2_EN) << BIT_SHIFT_ADC_COMP_2_EN)
+
+#define BIT_ADC_COMP_1_EN                     	BIT(1)
+#define BIT_SHIFT_ADC_COMP_1_EN               	1
+#define BIT_MASK_ADC_COMP_1_EN                	0x1
+#define BIT_CTRL_ADC_COMP_1_EN(x)             	(((x) & BIT_MASK_ADC_COMP_1_EN) << BIT_SHIFT_ADC_COMP_1_EN)
+
+#define BIT_ADC_COMP_0_EN                     	BIT(0)
+#define BIT_SHIFT_ADC_COMP_0_EN               	0
+#define BIT_MASK_ADC_COMP_0_EN                	0x1
+#define BIT_CTRL_ADC_COMP_0_EN(x)             	(((x) & BIT_MASK_ADC_COMP_0_EN) << BIT_SHIFT_ADC_COMP_0_EN)
+
+
+//2 REG_ADC_INTR_STS
+#define BIT_ADC_FIFO_THRESHOLD                	BIT(7)
+#define BIT_SHIFT_ADC_FIFO_THRESHOLD          	7
+#define BIT_MASK_ADC_FIFO_THRESHOLD           	0x1
+#define BIT_CTRL_ADC_FIFO_THRESHOLD(x)        	(((x) & BIT_MASK_ADC_FIFO_THRESHOLD) << BIT_SHIFT_ADC_FIFO_THRESHOLD)
+
+#define BIT_ADC_FIFO_RD_ERROR_ST              	BIT(6)
+#define BIT_SHIFT_ADC_FIFO_RD_ERROR_ST        	6
+#define BIT_MASK_ADC_FIFO_RD_ERROR_ST         	0x1
+#define BIT_CTRL_ADC_FIFO_RD_ERROR_ST(x)      	(((x) & BIT_MASK_ADC_FIFO_RD_ERROR_ST) << BIT_SHIFT_ADC_FIFO_RD_ERROR_ST)
+
+#define BIT_ADC_FIFO_RD_REQ_ST                	BIT(5)
+#define BIT_SHIFT_ADC_FIFO_RD_REQ_ST          	5
+#define BIT_MASK_ADC_FIFO_RD_REQ_ST           	0x1
+#define BIT_CTRL_ADC_FIFO_RD_REQ_ST(x)        	(((x) & BIT_MASK_ADC_FIFO_RD_REQ_ST) << BIT_SHIFT_ADC_FIFO_RD_REQ_ST)
+
+#define BIT_ADC_FIFO_FULL_ST                  	BIT(4)
+#define BIT_SHIFT_ADC_FIFO_FULL_ST            	4
+#define BIT_MASK_ADC_FIFO_FULL_ST             	0x1
+#define BIT_CTRL_ADC_FIFO_FULL_ST(x)          	(((x) & BIT_MASK_ADC_FIFO_FULL_ST) << BIT_SHIFT_ADC_FIFO_FULL_ST)
+
+#define BIT_ADC_COMP_3_ST                     	BIT(3)
+#define BIT_SHIFT_ADC_COMP_3_ST               	3
+#define BIT_MASK_ADC_COMP_3_ST                	0x1
+#define BIT_CTRL_ADC_COMP_3_ST(x)             	(((x) & BIT_MASK_ADC_COMP_3_ST) << BIT_SHIFT_ADC_COMP_3_ST)
+
+#define BIT_ADC_COMP_2_ST                     	BIT(2)
+#define BIT_SHIFT_ADC_COMP_2_ST               	2
+#define BIT_MASK_ADC_COMP_2_ST                	0x1
+#define BIT_CTRL_ADC_COMP_2_ST(x)             	(((x) & BIT_MASK_ADC_COMP_2_ST) << BIT_SHIFT_ADC_COMP_2_ST)
+
+#define BIT_ADC_COMP_1_ST                     	BIT(1)
+#define BIT_SHIFT_ADC_COMP_1_ST               	1
+#define BIT_MASK_ADC_COMP_1_ST                	0x1
+#define BIT_CTRL_ADC_COMP_1_ST(x)             	(((x) & BIT_MASK_ADC_COMP_1_ST) << BIT_SHIFT_ADC_COMP_1_ST)
+
+#define BIT_ADC_COMP_0_ST                     	BIT(0)
+#define BIT_SHIFT_ADC_COMP_0_ST               	0
+#define BIT_MASK_ADC_COMP_0_ST                	0x1
+#define BIT_CTRL_ADC_COMP_0_ST(x)             	(((x) & BIT_MASK_ADC_COMP_0_ST) << BIT_SHIFT_ADC_COMP_0_ST)
+
+
+//2 REG_ADC_COMP_VALUE_L
+
+#define BIT_SHIFT_ADC_COMP_TH_1 16
+#define BIT_MASK_ADC_COMP_TH_1 0xffff
+#define BIT_ADC_COMP_TH_1(x)                  	(((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
+#define BIT_CTRL_ADC_COMP_TH_1(x)             	(((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
+#define BIT_GET_ADC_COMP_TH_1(x)              	(((x) >> BIT_SHIFT_ADC_COMP_TH_1) & BIT_MASK_ADC_COMP_TH_1)
+
+
+#define BIT_SHIFT_ADC_COMP_TH_0 0
+#define BIT_MASK_ADC_COMP_TH_0 0xffff
+#define BIT_ADC_COMP_TH_0(x)                  	(((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
+#define BIT_CTRL_ADC_COMP_TH_0(x)             	(((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
+#define BIT_GET_ADC_COMP_TH_0(x)              	(((x) >> BIT_SHIFT_ADC_COMP_TH_0) & BIT_MASK_ADC_COMP_TH_0)
+
+
+//2 REG_ADC_COMP_VALUE_H
+
+#define BIT_SHIFT_ADC_COMP_TH_3 16
+#define BIT_MASK_ADC_COMP_TH_3 0xffff
+#define BIT_ADC_COMP_TH_3(x)                  	(((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
+#define BIT_CTRL_ADC_COMP_TH_3(x)             	(((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
+#define BIT_GET_ADC_COMP_TH_3(x)              	(((x) >> BIT_SHIFT_ADC_COMP_TH_3) & BIT_MASK_ADC_COMP_TH_3)
+
+
+#define BIT_SHIFT_ADC_COMP_TH_2 0
+#define BIT_MASK_ADC_COMP_TH_2 0xffff
+#define BIT_ADC_COMP_TH_2(x)                  	(((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
+#define BIT_CTRL_ADC_COMP_TH_2(x)             	(((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
+#define BIT_GET_ADC_COMP_TH_2(x)              	(((x) >> BIT_SHIFT_ADC_COMP_TH_2) & BIT_MASK_ADC_COMP_TH_2)
+
+
+//2 REG_ADC_COMP_SET
+
+#define BIT_SHIFT_ADC_GREATER_THAN 0
+#define BIT_MASK_ADC_GREATER_THAN 0xf
+#define BIT_ADC_GREATER_THAN(x)               	(((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
+#define BIT_CTRL_ADC_GREATER_THAN(x)          	(((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
+#define BIT_GET_ADC_GREATER_THAN(x)           	(((x) >> BIT_SHIFT_ADC_GREATER_THAN) & BIT_MASK_ADC_GREATER_THAN)
+
+
+//2 REG_ADC_POWER
+
+#define BIT_SHIFT_ADC_PWR_CUT_CNTR 16
+#define BIT_MASK_ADC_PWR_CUT_CNTR 0xff
+#define BIT_ADC_PWR_CUT_CNTR(x)               	(((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
+#define BIT_CTRL_ADC_PWR_CUT_CNTR(x)          	(((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
+#define BIT_GET_ADC_PWR_CUT_CNTR(x)           	(((x) >> BIT_SHIFT_ADC_PWR_CUT_CNTR) & BIT_MASK_ADC_PWR_CUT_CNTR)
+
+#define BIT_ADC_FIFO_ON_ST                    	BIT(11)
+#define BIT_SHIFT_ADC_FIFO_ON_ST              	11
+#define BIT_MASK_ADC_FIFO_ON_ST               	0x1
+#define BIT_CTRL_ADC_FIFO_ON_ST(x)            	(((x) & BIT_MASK_ADC_FIFO_ON_ST) << BIT_SHIFT_ADC_FIFO_ON_ST)
+
+#define BIT_ADC_ISO_ON_ST                     	BIT(10)
+#define BIT_SHIFT_ADC_ISO_ON_ST               	10
+#define BIT_MASK_ADC_ISO_ON_ST                	0x1
+#define BIT_CTRL_ADC_ISO_ON_ST(x)             	(((x) & BIT_MASK_ADC_ISO_ON_ST) << BIT_SHIFT_ADC_ISO_ON_ST)
+
+#define BIT_ADC_PWR33_ON_ST                   	BIT(9)
+#define BIT_SHIFT_ADC_PWR33_ON_ST             	9
+#define BIT_MASK_ADC_PWR33_ON_ST              	0x1
+#define BIT_CTRL_ADC_PWR33_ON_ST(x)           	(((x) & BIT_MASK_ADC_PWR33_ON_ST) << BIT_SHIFT_ADC_PWR33_ON_ST)
+
+#define BIT_ADC_PWR12_ON_ST                   	BIT(8)
+#define BIT_SHIFT_ADC_PWR12_ON_ST             	8
+#define BIT_MASK_ADC_PWR12_ON_ST              	0x1
+#define BIT_CTRL_ADC_PWR12_ON_ST(x)           	(((x) & BIT_MASK_ADC_PWR12_ON_ST) << BIT_SHIFT_ADC_PWR12_ON_ST)
+
+#define BIT_ADC_ISO_MANUAL                    	BIT(3)
+#define BIT_SHIFT_ADC_ISO_MANUAL              	3
+#define BIT_MASK_ADC_ISO_MANUAL               	0x1
+#define BIT_CTRL_ADC_ISO_MANUAL(x)            	(((x) & BIT_MASK_ADC_ISO_MANUAL) << BIT_SHIFT_ADC_ISO_MANUAL)
+
+#define BIT_ADC_PWR33_MANUAL                  	BIT(2)
+#define BIT_SHIFT_ADC_PWR33_MANUAL            	2
+#define BIT_MASK_ADC_PWR33_MANUAL             	0x1
+#define BIT_CTRL_ADC_PWR33_MANUAL(x)          	(((x) & BIT_MASK_ADC_PWR33_MANUAL) << BIT_SHIFT_ADC_PWR33_MANUAL)
+
+#define BIT_ADC_PWR12_MANUAL                  	BIT(1)
+#define BIT_SHIFT_ADC_PWR12_MANUAL            	1
+#define BIT_MASK_ADC_PWR12_MANUAL             	0x1
+#define BIT_CTRL_ADC_PWR12_MANUAL(x)          	(((x) & BIT_MASK_ADC_PWR12_MANUAL) << BIT_SHIFT_ADC_PWR12_MANUAL)
+
+#define BIT_ADC_PWR_AUTO                      	BIT(0)
+#define BIT_SHIFT_ADC_PWR_AUTO                	0
+#define BIT_MASK_ADC_PWR_AUTO                 	0x1
+#define BIT_CTRL_ADC_PWR_AUTO(x)              	(((x) & BIT_MASK_ADC_PWR_AUTO) << BIT_SHIFT_ADC_PWR_AUTO)
+
+
+//2 REG_ADC_ANAPAR_AD0
+
+#define BIT_SHIFT_ADC_ANAPAR_AD0 2
+#define BIT_MASK_ADC_ANAPAR_AD0 0x3fffffff
+#define BIT_ADC_ANAPAR_AD0(x)                 	(((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
+#define BIT_CTRL_ADC_ANAPAR_AD0(x)            	(((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
+#define BIT_GET_ADC_ANAPAR_AD0(x)             	(((x) >> BIT_SHIFT_ADC_ANAPAR_AD0) & BIT_MASK_ADC_ANAPAR_AD0)
+
+#define BIT_ADC_AUDIO_EN                      	BIT(1)
+#define BIT_SHIFT_ADC_AUDIO_EN                	1
+#define BIT_MASK_ADC_AUDIO_EN                 	0x1
+#define BIT_CTRL_ADC_AUDIO_EN(x)              	(((x) & BIT_MASK_ADC_AUDIO_EN) << BIT_SHIFT_ADC_AUDIO_EN)
+
+#define BIT_ADC_EN_MANUAL                     	BIT(0)
+#define BIT_SHIFT_ADC_EN_MANUAL               	0
+#define BIT_MASK_ADC_EN_MANUAL                	0x1
+#define BIT_CTRL_ADC_EN_MANUAL(x)             	(((x) & BIT_MASK_ADC_EN_MANUAL) << BIT_SHIFT_ADC_EN_MANUAL)
+
+
+//2 REG_ADC_ANAPAR_AD1
+
+#define BIT_SHIFT_ADC_ANAPAR_AD1 0
+#define BIT_MASK_ADC_ANAPAR_AD1 0xffffffffL
+#define BIT_ADC_ANAPAR_AD1(x)                 	(((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
+#define BIT_CTRL_ADC_ANAPAR_AD1(x)            	(((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
+#define BIT_GET_ADC_ANAPAR_AD1(x)             	(((x) >> BIT_SHIFT_ADC_ANAPAR_AD1) & BIT_MASK_ADC_ANAPAR_AD1)
+
+
+//2 REG_ADC_ANAPAR_AD2
+
+#define BIT_SHIFT_ADC_ANAPAR_AD2 0
+#define BIT_MASK_ADC_ANAPAR_AD2 0xffffffffL
+#define BIT_ADC_ANAPAR_AD2(x)                 	(((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
+#define BIT_CTRL_ADC_ANAPAR_AD2(x)            	(((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
+#define BIT_GET_ADC_ANAPAR_AD2(x)             	(((x) >> BIT_SHIFT_ADC_ANAPAR_AD2) & BIT_MASK_ADC_ANAPAR_AD2)
+
+
+//2 REG_ADC_ANAPAR_AD3
+
+#define BIT_SHIFT_ADC_ANAPAR_AD3 0
+#define BIT_MASK_ADC_ANAPAR_AD3 0xffffffffL
+#define BIT_ADC_ANAPAR_AD3(x)                 	(((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
+#define BIT_CTRL_ADC_ANAPAR_AD3(x)            	(((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
+#define BIT_GET_ADC_ANAPAR_AD3(x)             	(((x) >> BIT_SHIFT_ADC_ANAPAR_AD3) & BIT_MASK_ADC_ANAPAR_AD3)
+
+
+//2 REG_ADC_ANAPAR_AD4
+
+#define BIT_SHIFT_ADC_ANAPAR_AD4 0
+#define BIT_MASK_ADC_ANAPAR_AD4 0xffffffffL
+#define BIT_ADC_ANAPAR_AD4(x)                 	(((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
+#define BIT_CTRL_ADC_ANAPAR_AD4(x)            	(((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
+#define BIT_GET_ADC_ANAPAR_AD4(x)             	(((x) >> BIT_SHIFT_ADC_ANAPAR_AD4) & BIT_MASK_ADC_ANAPAR_AD4)
+
+
+//2 REG_ADC_ANAPAR_AD5
+
+#define BIT_SHIFT_ADC_ANAPAR_AD5 0
+#define BIT_MASK_ADC_ANAPAR_AD5 0xffffffffL
+#define BIT_ADC_ANAPAR_AD5(x)                 	(((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
+#define BIT_CTRL_ADC_ANAPAR_AD5(x)            	(((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
+#define BIT_GET_ADC_ANAPAR_AD5(x)             	(((x) >> BIT_SHIFT_ADC_ANAPAR_AD5) & BIT_MASK_ADC_ANAPAR_AD5)
+
+
+//2 REG_ADC_CALI_DATA
+
+#define BIT_SHIFT_ADC_CALI_DATA_6 16
+#define BIT_MASK_ADC_CALI_DATA_6 0xffff
+#define BIT_ADC_CALI_DATA_6(x)                	(((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
+#define BIT_CTRL_ADC_CALI_DATA_6(x)           	(((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
+#define BIT_GET_ADC_CALI_DATA_6(x)            	(((x) >> BIT_SHIFT_ADC_CALI_DATA_6) & BIT_MASK_ADC_CALI_DATA_6)
+
+
+#define BIT_SHIFT_ADC_CALI_DATA_0 0
+#define BIT_MASK_ADC_CALI_DATA_0 0xffff
+#define BIT_ADC_CALI_DATA_0(x)                	(((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
+#define BIT_CTRL_ADC_CALI_DATA_0(x)           	(((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
+#define BIT_GET_ADC_CALI_DATA_0(x)            	(((x) >> BIT_SHIFT_ADC_CALI_DATA_0) & BIT_MASK_ADC_CALI_DATA_0)
+
+//================ Register Reg Field  =========================
+#define REG_ADC_FIFO_READ 0x0000
+#define REG_ADC_CONTROL 0x0004
+#define REG_ADC_INTR_EN 0x0008
+#define REG_ADC_INTR_STS 0x000C
+#define REG_ADC_COMP_VALUE_L 0x0010
+#define REG_ADC_COMP_VALUE_H 0x0014
+#define REG_ADC_COMP_SET 0x0018
+#define REG_ADC_POWER 0x001C
+#define REG_ADC_ANAPAR_AD0 0x0020
+#define REG_ADC_ANAPAR_AD1 0x0024
+#define REG_ADC_ANAPAR_AD2 0x0028
+#define REG_ADC_ANAPAR_AD3 0x002C
+#define REG_ADC_ANAPAR_AD4 0x0030
+#define REG_ADC_ANAPAR_AD5 0x0034
+#define REG_ADC_CALI_DATA 0x0038
+
+//================ ADC HAL related enumeration ==================
+
+//================ ADC Function Prototypes  =====================
+#define HAL_ADC_WRITE32(addr, value)    HAL_WRITE32(ADC_REG_BASE,addr,value)
+#define HAL_ADC_READ32(addr)            HAL_READ32(ADC_REG_BASE,addr)
+
+RTK_STATUS HalADCInit8195a(IN VOID *Data);
+RTK_STATUS HalADCDeInit8195a(IN VOID *Data);
+RTK_STATUS HalADCEnableRtl8195a(IN VOID *Data);
+RTK_STATUS HalADCIntrCtrl8195a(IN VOID *Data);
+u32 HalADCReceiveRtl8195a(IN VOID *Data);
+u32 HalADCReadRegRtl8195a(IN VOID *Data,IN  u8 I2CReg);
+
+#endif

sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_dac.h

@@ -0,0 +1,294 @@
+#ifndef _RTL8195A_DAC_H_
+#define _RTL8195A_DAC_H_
+
+//================ Register Bit Field ==========================
+//2 REG_DAC0_FIFO_WR
+
+#define BIT_SHIFT_DAC0_FIFO_WO 0
+#define BIT_MASK_DAC0_FIFO_WO 0xffffffffL
+#define BIT_DAC0_FIFO_WO(x)                   	(((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
+#define BIT_CTRL_DAC0_FIFO_WO(x)              	(((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
+#define BIT_GET_DAC0_FIFO_WO(x)               	(((x) >> BIT_SHIFT_DAC0_FIFO_WO) & BIT_MASK_DAC0_FIFO_WO)
+
+
+//2 REG_DAC_CTRL
+
+#define BIT_SHIFT_DAC_DELTA_SIGMA 25
+#define BIT_MASK_DAC_DELTA_SIGMA 0x7
+#define BIT_DAC_DELTA_SIGMA(x)                	(((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
+#define BIT_CTRL_DAC_DELTA_SIGMA(x)           	(((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
+#define BIT_GET_DAC_DELTA_SIGMA(x)            	(((x) >> BIT_SHIFT_DAC_DELTA_SIGMA) & BIT_MASK_DAC_DELTA_SIGMA)
+
+#define BIT_DAC_BYPASS_DSC                    	BIT(24)
+#define BIT_SHIFT_DAC_BYPASS_DSC              	24
+#define BIT_MASK_DAC_BYPASS_DSC               	0x1
+#define BIT_CTRL_DAC_BYPASS_DSC(x)            	(((x) & BIT_MASK_DAC_BYPASS_DSC) << BIT_SHIFT_DAC_BYPASS_DSC)
+
+
+#define BIT_SHIFT_DAC_DSC_DBG_SEL 19
+#define BIT_MASK_DAC_DSC_DBG_SEL 0x3
+#define BIT_DAC_DSC_DBG_SEL(x)                	(((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
+#define BIT_CTRL_DAC_DSC_DBG_SEL(x)           	(((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
+#define BIT_GET_DAC_DSC_DBG_SEL(x)            	(((x) >> BIT_SHIFT_DAC_DSC_DBG_SEL) & BIT_MASK_DAC_DSC_DBG_SEL)
+
+
+#define BIT_SHIFT_DAC_DBG_SEL 16
+#define BIT_MASK_DAC_DBG_SEL 0x7
+#define BIT_DAC_DBG_SEL(x)                    	(((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
+#define BIT_CTRL_DAC_DBG_SEL(x)               	(((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
+#define BIT_GET_DAC_DBG_SEL(x)                	(((x) >> BIT_SHIFT_DAC_DBG_SEL) & BIT_MASK_DAC_DBG_SEL)
+
+
+#define BIT_SHIFT_DAC_BURST_SIZE 8
+#define BIT_MASK_DAC_BURST_SIZE 0xf
+#define BIT_DAC_BURST_SIZE(x)                 	(((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
+#define BIT_CTRL_DAC_BURST_SIZE(x)            	(((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
+#define BIT_GET_DAC_BURST_SIZE(x)             	(((x) >> BIT_SHIFT_DAC_BURST_SIZE) & BIT_MASK_DAC_BURST_SIZE)
+
+#define BIT_DAC_FILTER_SETTLE                 	BIT(4)
+#define BIT_SHIFT_DAC_FILTER_SETTLE           	4
+#define BIT_MASK_DAC_FILTER_SETTLE            	0x1
+#define BIT_CTRL_DAC_FILTER_SETTLE(x)         	(((x) & BIT_MASK_DAC_FILTER_SETTLE) << BIT_SHIFT_DAC_FILTER_SETTLE)
+
+#define BIT_DAC_OV_OPTION                     	BIT(3)
+#define BIT_SHIFT_DAC_OV_OPTION               	3
+#define BIT_MASK_DAC_OV_OPTION                	0x1
+#define BIT_CTRL_DAC_OV_OPTION(x)             	(((x) & BIT_MASK_DAC_OV_OPTION) << BIT_SHIFT_DAC_OV_OPTION)
+
+#define BIT_DAC_ENDIAN                        	BIT(2)
+#define BIT_SHIFT_DAC_ENDIAN                  	2
+#define BIT_MASK_DAC_ENDIAN                   	0x1
+#define BIT_CTRL_DAC_ENDIAN(x)                	(((x) & BIT_MASK_DAC_ENDIAN) << BIT_SHIFT_DAC_ENDIAN)
+
+#define BIT_DAC_SPEED                         	BIT(1)
+#define BIT_SHIFT_DAC_SPEED                   	1
+#define BIT_MASK_DAC_SPEED                    	0x1
+#define BIT_CTRL_DAC_SPEED(x)                 	(((x) & BIT_MASK_DAC_SPEED) << BIT_SHIFT_DAC_SPEED)
+
+#define BIT_DAC_FIFO_EN                       	BIT(0)
+#define BIT_SHIFT_DAC_FIFO_EN                 	0
+#define BIT_MASK_DAC_FIFO_EN                  	0x1
+#define BIT_CTRL_DAC_FIFO_EN(x)               	(((x) & BIT_MASK_DAC_FIFO_EN) << BIT_SHIFT_DAC_FIFO_EN)
+
+
+//2 REG_DAC_INTR_CTRL
+#define BIT_DAC_DSC_OVERFLOW1_EN              	BIT(6)
+#define BIT_SHIFT_DAC_DSC_OVERFLOW1_EN        	6
+#define BIT_MASK_DAC_DSC_OVERFLOW1_EN         	0x1
+#define BIT_CTRL_DAC_DSC_OVERFLOW1_EN(x)      	(((x) & BIT_MASK_DAC_DSC_OVERFLOW1_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW1_EN)
+
+#define BIT_DAC_DSC_OVERFLOW0_EN              	BIT(5)
+#define BIT_SHIFT_DAC_DSC_OVERFLOW0_EN        	5
+#define BIT_MASK_DAC_DSC_OVERFLOW0_EN         	0x1
+#define BIT_CTRL_DAC_DSC_OVERFLOW0_EN(x)      	(((x) & BIT_MASK_DAC_DSC_OVERFLOW0_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW0_EN)
+
+#define BIT_DAC__WRITE_ERROR_EN               	BIT(4)
+#define BIT_SHIFT_DAC__WRITE_ERROR_EN         	4
+#define BIT_MASK_DAC__WRITE_ERROR_EN          	0x1
+#define BIT_CTRL_DAC__WRITE_ERROR_EN(x)       	(((x) & BIT_MASK_DAC__WRITE_ERROR_EN) << BIT_SHIFT_DAC__WRITE_ERROR_EN)
+
+#define BIT_DAC_FIFO_STOP_EN                  	BIT(3)
+#define BIT_SHIFT_DAC_FIFO_STOP_EN            	3
+#define BIT_MASK_DAC_FIFO_STOP_EN             	0x1
+#define BIT_CTRL_DAC_FIFO_STOP_EN(x)          	(((x) & BIT_MASK_DAC_FIFO_STOP_EN) << BIT_SHIFT_DAC_FIFO_STOP_EN)
+
+#define BIT_DAC_FIFO_OVERFLOW_EN              	BIT(2)
+#define BIT_SHIFT_DAC_FIFO_OVERFLOW_EN        	2
+#define BIT_MASK_DAC_FIFO_OVERFLOW_EN         	0x1
+#define BIT_CTRL_DAC_FIFO_OVERFLOW_EN(x)      	(((x) & BIT_MASK_DAC_FIFO_OVERFLOW_EN) << BIT_SHIFT_DAC_FIFO_OVERFLOW_EN)
+
+#define BIT_DAC_FIFO_WR_REQ_EN                	BIT(1)
+#define BIT_SHIFT_DAC_FIFO_WR_REQ_EN          	1
+#define BIT_MASK_DAC_FIFO_WR_REQ_EN           	0x1
+#define BIT_CTRL_DAC_FIFO_WR_REQ_EN(x)        	(((x) & BIT_MASK_DAC_FIFO_WR_REQ_EN) << BIT_SHIFT_DAC_FIFO_WR_REQ_EN)
+
+#define BIT_DAC_FIFO_FULL_EN                  	BIT(0)
+#define BIT_SHIFT_DAC_FIFO_FULL_EN            	0
+#define BIT_MASK_DAC_FIFO_FULL_EN             	0x1
+#define BIT_CTRL_DAC_FIFO_FULL_EN(x)          	(((x) & BIT_MASK_DAC_FIFO_FULL_EN) << BIT_SHIFT_DAC_FIFO_FULL_EN)
+
+
+//2 REG_DAC_INTR_STS
+#define BIT_DAC_DSC_OVERFLOW1_ST              	BIT(6)
+#define BIT_SHIFT_DAC_DSC_OVERFLOW1_ST        	6
+#define BIT_MASK_DAC_DSC_OVERFLOW1_ST         	0x1
+#define BIT_CTRL_DAC_DSC_OVERFLOW1_ST(x)      	(((x) & BIT_MASK_DAC_DSC_OVERFLOW1_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW1_ST)
+
+#define BIT_DAC_DSC_OVERFLOW0_ST              	BIT(5)
+#define BIT_SHIFT_DAC_DSC_OVERFLOW0_ST        	5
+#define BIT_MASK_DAC_DSC_OVERFLOW0_ST         	0x1
+#define BIT_CTRL_DAC_DSC_OVERFLOW0_ST(x)      	(((x) & BIT_MASK_DAC_DSC_OVERFLOW0_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW0_ST)
+
+#define BIT_DAC__WRITE_ERROR_ST               	BIT(4)
+#define BIT_SHIFT_DAC__WRITE_ERROR_ST         	4
+#define BIT_MASK_DAC__WRITE_ERROR_ST          	0x1
+#define BIT_CTRL_DAC__WRITE_ERROR_ST(x)       	(((x) & BIT_MASK_DAC__WRITE_ERROR_ST) << BIT_SHIFT_DAC__WRITE_ERROR_ST)
+
+#define BIT_DAC_FIFO_STOP_ST                  	BIT(3)
+#define BIT_SHIFT_DAC_FIFO_STOP_ST            	3
+#define BIT_MASK_DAC_FIFO_STOP_ST             	0x1
+#define BIT_CTRL_DAC_FIFO_STOP_ST(x)          	(((x) & BIT_MASK_DAC_FIFO_STOP_ST) << BIT_SHIFT_DAC_FIFO_STOP_ST)
+
+#define BIT_DAC_FIFO_OVERFLOW_ST              	BIT(2)
+#define BIT_SHIFT_DAC_FIFO_OVERFLOW_ST        	2
+#define BIT_MASK_DAC_FIFO_OVERFLOW_ST         	0x1
+#define BIT_CTRL_DAC_FIFO_OVERFLOW_ST(x)      	(((x) & BIT_MASK_DAC_FIFO_OVERFLOW_ST) << BIT_SHIFT_DAC_FIFO_OVERFLOW_ST)
+
+#define BIT_DAC_FIFO_WR_REQ_ST                	BIT(1)
+#define BIT_SHIFT_DAC_FIFO_WR_REQ_ST          	1
+#define BIT_MASK_DAC_FIFO_WR_REQ_ST           	0x1
+#define BIT_CTRL_DAC_FIFO_WR_REQ_ST(x)        	(((x) & BIT_MASK_DAC_FIFO_WR_REQ_ST) << BIT_SHIFT_DAC_FIFO_WR_REQ_ST)
+
+#define BIT_DAC_FIFO_FULL_ST                  	BIT(0)
+#define BIT_SHIFT_DAC_FIFO_FULL_ST            	0
+#define BIT_MASK_DAC_FIFO_FULL_ST             	0x1
+#define BIT_CTRL_DAC_FIFO_FULL_ST(x)          	(((x) & BIT_MASK_DAC_FIFO_FULL_ST) << BIT_SHIFT_DAC_FIFO_FULL_ST)
+
+
+//2 REG_DAC_PWR_CTRL
+
+#define BIT_SHIFT_DAC_PWR_CUT_CNTR 16
+#define BIT_MASK_DAC_PWR_CUT_CNTR 0xff
+#define BIT_DAC_PWR_CUT_CNTR(x)               	(((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
+#define BIT_CTRL_DAC_PWR_CUT_CNTR(x)          	(((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
+#define BIT_GET_DAC_PWR_CUT_CNTR(x)           	(((x) >> BIT_SHIFT_DAC_PWR_CUT_CNTR) & BIT_MASK_DAC_PWR_CUT_CNTR)
+
+#define BIT_ST_DAC_FIFO_ON                    	BIT(11)
+#define BIT_SHIFT_ST_DAC_FIFO_ON              	11
+#define BIT_MASK_ST_DAC_FIFO_ON               	0x1
+#define BIT_CTRL_ST_DAC_FIFO_ON(x)            	(((x) & BIT_MASK_ST_DAC_FIFO_ON) << BIT_SHIFT_ST_DAC_FIFO_ON)
+
+#define BIT_ST_DAC_ISO_ON                     	BIT(10)
+#define BIT_SHIFT_ST_DAC_ISO_ON               	10
+#define BIT_MASK_ST_DAC_ISO_ON                	0x1
+#define BIT_CTRL_ST_DAC_ISO_ON(x)             	(((x) & BIT_MASK_ST_DAC_ISO_ON) << BIT_SHIFT_ST_DAC_ISO_ON)
+
+#define BIT_ST_DAC_PWR33_ON                   	BIT(9)
+#define BIT_SHIFT_ST_DAC_PWR33_ON             	9
+#define BIT_MASK_ST_DAC_PWR33_ON              	0x1
+#define BIT_CTRL_ST_DAC_PWR33_ON(x)           	(((x) & BIT_MASK_ST_DAC_PWR33_ON) << BIT_SHIFT_ST_DAC_PWR33_ON)
+
+#define BIT_ST_DAC_PWR12_ON                   	BIT(8)
+#define BIT_SHIFT_ST_DAC_PWR12_ON             	8
+#define BIT_MASK_ST_DAC_PWR12_ON              	0x1
+#define BIT_CTRL_ST_DAC_PWR12_ON(x)           	(((x) & BIT_MASK_ST_DAC_PWR12_ON) << BIT_SHIFT_ST_DAC_PWR12_ON)
+
+#define BIT_DAC_ISO_MANU                      	BIT(3)
+#define BIT_SHIFT_DAC_ISO_MANU                	3
+#define BIT_MASK_DAC_ISO_MANU                 	0x1
+#define BIT_CTRL_DAC_ISO_MANU(x)              	(((x) & BIT_MASK_DAC_ISO_MANU) << BIT_SHIFT_DAC_ISO_MANU)
+
+#define BIT_DAC_PWR33_MANU                    	BIT(2)
+#define BIT_SHIFT_DAC_PWR33_MANU              	2
+#define BIT_MASK_DAC_PWR33_MANU               	0x1
+#define BIT_CTRL_DAC_PWR33_MANU(x)            	(((x) & BIT_MASK_DAC_PWR33_MANU) << BIT_SHIFT_DAC_PWR33_MANU)
+
+#define BIT_DAC_PWR12_MANU                    	BIT(1)
+#define BIT_SHIFT_DAC_PWR12_MANU              	1
+#define BIT_MASK_DAC_PWR12_MANU               	0x1
+#define BIT_CTRL_DAC_PWR12_MANU(x)            	(((x) & BIT_MASK_DAC_PWR12_MANU) << BIT_SHIFT_DAC_PWR12_MANU)
+
+#define BIT_DAC_PWR_AUTO                      	BIT(0)
+#define BIT_SHIFT_DAC_PWR_AUTO                	0
+#define BIT_MASK_DAC_PWR_AUTO                 	0x1
+#define BIT_CTRL_DAC_PWR_AUTO(x)              	(((x) & BIT_MASK_DAC_PWR_AUTO) << BIT_SHIFT_DAC_PWR_AUTO)
+
+
+//2 REG_DAC_ANAPAR_DA0
+
+#define BIT_SHIFT_PWR_ALL_CNTR 12
+#define BIT_MASK_PWR_ALL_CNTR 0xfffff
+#define BIT_PWR_ALL_CNTR(x)                   	(((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
+#define BIT_CTRL_PWR_ALL_CNTR(x)              	(((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
+#define BIT_GET_PWR_ALL_CNTR(x)               	(((x) >> BIT_SHIFT_PWR_ALL_CNTR) & BIT_MASK_PWR_ALL_CNTR)
+
+
+#define BIT_SHIFT_PWR_FUP_CNTR 0
+#define BIT_MASK_PWR_FUP_CNTR 0xfff
+#define BIT_PWR_FUP_CNTR(x)                   	(((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
+#define BIT_CTRL_PWR_FUP_CNTR(x)              	(((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
+#define BIT_GET_PWR_FUP_CNTR(x)               	(((x) >> BIT_SHIFT_PWR_FUP_CNTR) & BIT_MASK_PWR_FUP_CNTR)
+
+
+//2 REG_DAC_ANAPAR_DA1
+#define BIT_FUP_EN                            	BIT(31)
+#define BIT_SHIFT_FUP_EN                      	31
+#define BIT_MASK_FUP_EN                       	0x1
+#define BIT_CTRL_FUP_EN(x)                    	(((x) & BIT_MASK_FUP_EN) << BIT_SHIFT_FUP_EN)
+
+
+#define BIT_SHIFT_ANAPAR_DA 8
+#define BIT_MASK_ANAPAR_DA 0x7fffff
+#define BIT_ANAPAR_DA(x)                      	(((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
+#define BIT_CTRL_ANAPAR_DA(x)                 	(((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
+#define BIT_GET_ANAPAR_DA(x)                  	(((x) >> BIT_SHIFT_ANAPAR_DA) & BIT_MASK_ANAPAR_DA)
+
+#define BIT_D_POW_DACVREF                     	BIT(7)
+#define BIT_SHIFT_D_POW_DACVREF               	7
+#define BIT_MASK_D_POW_DACVREF                	0x1
+#define BIT_CTRL_D_POW_DACVREF(x)             	(((x) & BIT_MASK_D_POW_DACVREF) << BIT_SHIFT_D_POW_DACVREF)
+
+#define BIT_D_POW_VREF2                       	BIT(6)
+#define BIT_SHIFT_D_POW_VREF2                 	6
+#define BIT_MASK_D_POW_VREF2                  	0x1
+#define BIT_CTRL_D_POW_VREF2(x)               	(((x) & BIT_MASK_D_POW_VREF2) << BIT_SHIFT_D_POW_VREF2)
+
+#define BIT_D_POW_MBIAS                       	BIT(5)
+#define BIT_SHIFT_D_POW_MBIAS                 	5
+#define BIT_MASK_D_POW_MBIAS                  	0x1
+#define BIT_CTRL_D_POW_MBIAS(x)               	(((x) & BIT_MASK_D_POW_MBIAS) << BIT_SHIFT_D_POW_MBIAS)
+
+#define BIT_D_POW_DIV4                        	BIT(4)
+#define BIT_SHIFT_D_POW_DIV4                  	4
+#define BIT_MASK_D_POW_DIV4                   	0x1
+#define BIT_CTRL_D_POW_DIV4(x)                	(((x) & BIT_MASK_D_POW_DIV4) << BIT_SHIFT_D_POW_DIV4)
+
+#define BIT_D_POW_DF1SE_R                     	BIT(3)
+#define BIT_SHIFT_D_POW_DF1SE_R               	3
+#define BIT_MASK_D_POW_DF1SE_R                	0x1
+#define BIT_CTRL_D_POW_DF1SE_R(x)             	(((x) & BIT_MASK_D_POW_DF1SE_R) << BIT_SHIFT_D_POW_DF1SE_R)
+
+#define BIT_D_POW_DF2SE_L                     	BIT(2)
+#define BIT_SHIFT_D_POW_DF2SE_L               	2
+#define BIT_MASK_D_POW_DF2SE_L                	0x1
+#define BIT_CTRL_D_POW_DF2SE_L(x)             	(((x) & BIT_MASK_D_POW_DF2SE_L) << BIT_SHIFT_D_POW_DF2SE_L)
+
+#define BIT_D_POW_DAC_R                       	BIT(1)
+#define BIT_SHIFT_D_POW_DAC_R                 	1
+#define BIT_MASK_D_POW_DAC_R                  	0x1
+#define BIT_CTRL_D_POW_DAC_R(x)               	(((x) & BIT_MASK_D_POW_DAC_R) << BIT_SHIFT_D_POW_DAC_R)
+
+#define BIT_D_POW_DAC_L                       	BIT(0)
+#define BIT_SHIFT_D_POW_DAC_L                 	0
+#define BIT_MASK_D_POW_DAC_L                  	0x1
+#define BIT_CTRL_D_POW_DAC_L(x)               	(((x) & BIT_MASK_D_POW_DAC_L) << BIT_SHIFT_D_POW_DAC_L)
+
+
+//================ Register Reg Field  =========================
+#define REG_DAC0_FIFO_WR 0x0000
+#define REG_DAC_CTRL 0x0004
+#define REG_DAC_INTR_CTRL 0x0008
+#define REG_DAC_INTR_STS 0x000C
+#define REG_DAC_PWR_CTRL 0x0010
+#define REG_DAC_ANAPAR_DA0 0x0014
+#define REG_DAC_ANAPAR_DA1 0x0018
+
+
+//================ DAC HAL related enumeration ==================
+
+
+//================ DAC HAL Macro  ===========================
+#define HAL_DAC_WRITE32(dacidx, addr, value)    HAL_WRITE32(DAC_REG_BASE+dacidx*0x800 \
+                                                        ,addr,value)
+#define HAL_DAC_READ32(dacidx, addr)            HAL_READ32(DAC_REG_BASE+dacidx*0x800,addr)
+
+
+//================ DAC Function Prototypes  =====================
+RTK_STATUS HalDACInit8195a(IN  VOID *Data);
+RTK_STATUS HalDACDeInit8195a(IN  VOID *Data);
+RTK_STATUS HalDACEnableRtl8195a(IN  VOID *Data);
+RTK_STATUS HalDACIntrCtrl8195a(IN  VOID    *Data);
+u8 HalDACSendRtl8195a(IN  VOID    *Data);
+u32 HalDACReadRegRtl8195a(IN  VOID    *Data,IN  u8      I2CReg);
+
+#endif

sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gdma.h

@@ -0,0 +1,522 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_GDMA_H_
+#define _RTL8195A_GDMA_H_
+
+// Define GDMA Handshake interface with peripheral, 0 -> GDMA0, 1-> GDMA1
+// Set this Hnadshake interface map to register REG_PESOC_SOC_CTRL
+#define GDMA_HANDSHAKE_UART0_TX             0
+#define GDMA_HANDSHAKE_UART0_RX             1
+#define GDMA_HANDSHAKE_UART1_TX             2
+#define GDMA_HANDSHAKE_UART1_RX             3
+#define GDMA_HANDSHAKE_UART2_TX             14      // Only on GDMA 0, hardware fixed
+#define GDMA_HANDSHAKE_UART2_RX             14      // Only on GDMA 1, hardware fixed
+
+#define GDMA_HANDSHAKE_SSI0_TX              4
+#define GDMA_HANDSHAKE_SSI0_RX              5
+#define GDMA_HANDSHAKE_SSI1_TX              6
+#define GDMA_HANDSHAKE_SSI1_RX              7
+#define GDMA_HANDSHAKE_SSI2_TX              15      // Only on GDMA 0, hardware fixed
+#define GDMA_HANDSHAKE_SSI2_RX              15      // Only on GDMA 1, hardware fixed
+
+#define GDMA_HANDSHAKE_I2C0_TX              8
+#define GDMA_HANDSHAKE_I2C0_RX              9
+#define GDMA_HANDSHAKE_I2C1_TX              10
+#define GDMA_HANDSHAKE_I2C1_RX              11
+
+#define GDMA_HANDSHAKE_ADC                  12
+#define GDMA_HANDSHAKE_DAC0                 13      // Only on GDMA 0, hardware fixed
+#define GDMA_HANDSHAKE_DAC1                 13      // Only on GDMA 1, hardware fixed
+
+#define HAL_GDMAX_READ32(GdmaIndex, addr)     \
+                HAL_READ32(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
+#define HAL_GDMAX_WRITE32(GdmaIndex, addr, value)     \
+                HAL_WRITE32((GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF)), addr, value)
+#define HAL_GDMAX_READ16(GdmaIndex, addr)     \
+                HAL_READ16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
+#define HAL_GDMAX_WRITE16(GdmaIndex, addr, value)     \
+                HAL_WRITE16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
+#define HAL_GDMAX_READ8(GdmaIndex, addr)     \
+                HAL_READ8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
+#define HAL_GDMAX_WRITE8(GdmaIndex, addr, value)     \
+                HAL_WRITE8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
+
+
+#define GDMA_CH_MAX                 0x06
+
+#define REG_GDMA_CH_OFF                 0x058
+#define REG_GDMA_CH_SAR                 0x000
+#define REG_GDMA_CH_DAR                 0x008
+#define REG_GDMA_CH_LLP                 0x010
+#define REG_GDMA_CH_CTL                 0x018
+#define REG_GDMA_CH_SSTAT               0x020
+#define REG_GDMA_CH_DSTAT               0x028
+#define REG_GDMA_CH_SSTATAR             0x030
+#define REG_GDMA_CH_DSTATAR             0x038
+#define REG_GDMA_CH_CFG                 0x040
+#define REG_GDMA_CH_SGR                 0x048
+#define REG_GDMA_CH_DSR                 0x050
+
+//3 Interrupt Registers
+#define REG_GDMA_RAW_INT_BASE           0x2C0
+#define REG_GDMA_RAW_INT_TFR            0x2C0
+#define REG_GDMA_RAW_INT_BLOCK          0x2c8
+#define REG_GDMA_RAW_INT_SRC_TRAN       0x2D0
+#define REG_GDMA_RAW_INT_DST_TRAN       0x2D8
+#define REG_GDMA_RAW_INT_ERR            0x2E0
+
+#define REG_GDMA_STATUS_INT_BASE        0x2E8
+#define REG_GDMA_STATUS_INT_TFR         0x2E8
+#define REG_GDMA_STATUS_INT_BLOCK       0x2F0
+#define REG_GDMA_STATUS_INT_SRC_TRAN    0x2F8
+#define REG_GDMA_STATUS_INT_DST_TRAN    0x300
+#define REG_GDMA_STATUS_INT_ERR         0x308
+
+#define REG_GDMA_MASK_INT_BASE          0x310
+#define REG_GDMA_MASK_INT_TFR           0x310
+#define REG_GDMA_MASK_INT_BLOCK         0x318
+#define REG_GDMA_MASK_INT_SRC_TRAN      0x320
+#define REG_GDMA_MASK_INT_DST_TRAN      0x328
+#define REG_GDMA_MASK_INT_INT_ERR       0x330
+
+#define REG_GDMA_CLEAR_INT_BASE         0x338
+#define REG_GDMA_CLEAR_INT_TFR          0x338
+#define REG_GDMA_CLEAR_INT_BLOCK        0x340
+#define REG_GDMA_CLEAR_INT_SRC_TRAN     0x348
+#define REG_GDMA_CLEAR_INT_DST_TRAN     0x350
+#define REG_GDMA_CLEAR_INT_ERR          0x358
+#define REG_GDMA_STATUS_INT             0x360
+
+//3 Software handshaking Registers
+#define REG_GDMA_REQ_SRC                0x368
+#define REG_GDMA_REQ_DST                0x370
+#define REG_GDMA_REQ_SGL_REQ            0x378
+#define REG_GDMA_REQ_DST_REQ            0x380
+#define REG_GDMA_REQ_LST_SRC            0x388
+#define REG_GDMA_REQ_LST_DST            0x390
+
+//3 Miscellaneous Registers
+#define REG_GDMA_DMAC_CFG               0x398
+#define REG_GDMA_CH_EN                  0x3A0
+#define REG_GDMA_DMA_ID                 0x3A8
+#define REG_GDMA_DMA_TEST               0x3B0
+#define REG_GDMA_DMA_COM_PARAMS6        0x3C8
+#define REG_GDMA_DMA_COM_PARAMS5        0x3D0
+#define REG_GDMA_DMA_COM_PARAMS4        0x3D8
+#define REG_GDMA_DMA_COM_PARAMS3        0x3E0
+#define REG_GDMA_DMA_COM_PARAMS2        0x3E8
+#define REG_GDMA_DMA_COM_PARAMS1        0x3F0
+#define REG_GDMA_DMA_COM_PARAMS0        0x3F8
+
+//3 CTL Register Bit Control
+#define BIT_SHIFT_CTLX_LO_INT_EN 0
+#define BIT_MASK_CTLX_LO_INT_EN 0x1
+#define BIT_CTLX_LO_INT_EN(x)(((x) & BIT_MASK_CTLX_LO_INT_EN) << BIT_SHIFT_CTLX_LO_INT_EN)
+#define BIT_INVC_CTLX_LO_INT_EN (~(BIT_MASK_CTLX_LO_INT_EN << BIT_SHIFT_CTLX_LO_INT_EN))
+
+#define BIT_SHIFT_CTLX_LO_DST_TR_WIDTH 1
+#define BIT_MASK_CTLX_LO_DST_TR_WIDTH 0x7
+#define BIT_CTLX_LO_DST_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_DST_TR_WIDTH) << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH)
+#define BIT_INVC_CTLX_LO_DST_TR_WIDTH (~(BIT_MASK_CTLX_LO_DST_TR_WIDTH << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH))
+
+#define BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH 4
+#define BIT_MASK_CTLX_LO_SRC_TR_WIDTH 0x7
+#define BIT_CTLX_LO_SRC_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_SRC_TR_WIDTH) << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH)
+#define BIT_INVC_CTLX_LO_SRC_TR_WIDTH (~(BIT_MASK_CTLX_LO_SRC_TR_WIDTH << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH))
+
+#define BIT_SHIFT_CTLX_LO_DINC 7
+#define BIT_MASK_CTLX_LO_DINC 0x3
+#define BIT_CTLX_LO_DINC(x)(((x) & BIT_MASK_CTLX_LO_DINC) << BIT_SHIFT_CTLX_LO_DINC)
+#define BIT_INVC_CTLX_LO_DINC (~(BIT_MASK_CTLX_LO_DINC << BIT_SHIFT_CTLX_LO_DINC))
+
+#define BIT_SHIFT_CTLX_LO_SINC 9
+#define BIT_MASK_CTLX_LO_SINC 0x3
+#define BIT_CTLX_LO_SINC(x)(((x) & BIT_MASK_CTLX_LO_SINC) << BIT_SHIFT_CTLX_LO_SINC)
+#define BIT_INVC_CTLX_LO_SINC (~(BIT_MASK_CTLX_LO_SINC << BIT_SHIFT_CTLX_LO_SINC))
+
+#define BIT_SHIFT_CTLX_LO_DEST_MSIZE 11
+#define BIT_MASK_CTLX_LO_DEST_MSIZE 0x7
+#define BIT_CTLX_LO_DEST_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_DEST_MSIZE) << BIT_SHIFT_CTLX_LO_DEST_MSIZE)
+#define BIT_INVC_CTLX_LO_DEST_MSIZE (~(BIT_MASK_CTLX_LO_DEST_MSIZE << BIT_SHIFT_CTLX_LO_DEST_MSIZE))
+
+#define BIT_SHIFT_CTLX_LO_SRC_MSIZE 14
+#define BIT_MASK_CTLX_LO_SRC_MSIZE 0x7
+#define BIT_CTLX_LO_SRC_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_SRC_MSIZE) << BIT_SHIFT_CTLX_LO_SRC_MSIZE)
+#define BIT_INVC_CTLX_LO_SRC_MSIZE (~(BIT_MASK_CTLX_LO_SRC_MSIZE << BIT_SHIFT_CTLX_LO_SRC_MSIZE))
+
+
+#define BIT_SHIFT_CTLX_LO_SRC_GATHER_EN 17
+#define BIT_MASK_CTLX_LO_SRC_GATHER_EN 0x1
+#define BIT_CTLX_LO_SRC_GATHER_EN(x)(((x) & BIT_MASK_CTLX_LO_SRC_GATHER_EN) << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN)
+#define BIT_INVC_CTLX_LO_SRC_GATHER_EN (~(BIT_MASK_CTLX_LO_SRC_GATHER_EN << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN))
+
+
+#define BIT_SHIFT_CTLX_LO_DST_SCATTER_EN 18
+#define BIT_MASK_CTLX_LO_DST_SCATTER_EN 0x1
+#define BIT_CTLX_LO_DST_SCATTER_EN(x)(((x) & BIT_MASK_CTLX_LO_DST_SCATTER_EN) << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN)
+#define BIT_INVC_CTLX_LO_DST_SCATTER_EN (~(BIT_MASK_CTLX_LO_DST_SCATTER_EN << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN))
+
+
+#define BIT_SHIFT_CTLX_LO_TT_FC 20
+#define BIT_MASK_CTLX_LO_TT_FC 0x7
+#define BIT_CTLX_LO_TT_FC(x)(((x) & BIT_MASK_CTLX_LO_TT_FC) << BIT_SHIFT_CTLX_LO_TT_FC)
+#define BIT_INVC_CTLX_LO_TT_FC (~(BIT_MASK_CTLX_LO_TT_FC << BIT_SHIFT_CTLX_LO_TT_FC))
+
+
+#define BIT_SHIFT_CTLX_LO_DMS 23
+#define BIT_MASK_CTLX_LO_DMS 0x3
+#define BIT_CTLX_LO_DMS(x)(((x) & BIT_MASK_CTLX_LO_DMS) << BIT_MASK_CTLX_LO_DMS)
+#define BIT_INVC_CTLX_LO_DMS (~(BIT_MASK_CTLX_LO_DMS << BIT_SHIFT_CTLX_LO_DMS))
+
+
+#define BIT_SHIFT_CTLX_LO_SMS 25
+#define BIT_MASK_CTLX_LO_SMS 0x3
+#define BIT_CTLX_LO_SMS(x)(((x) & BIT_MASK_CTLX_LO_SMS) << BIT_SHIFT_CTLX_LO_SMS)
+#define BIT_INVC_CTLX_LO_SMS (~(BIT_MASK_CTLX_LO_SMS << BIT_SHIFT_CTLX_LO_SMS))
+
+
+#define BIT_SHIFT_CTLX_LO_LLP_DST_EN 27
+#define BIT_MASK_CTLX_LO_LLP_DST_EN 0x1
+#define BIT_CTLX_LO_LLP_DST_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_DST_EN) << BIT_SHIFT_CTLX_LO_LLP_DST_EN)
+#define BIT_INVC_CTLX_LO_LLP_DST_EN (~(BIT_MASK_CTLX_LO_LLP_DST_EN << BIT_SHIFT_CTLX_LO_LLP_DST_EN))
+
+#define BIT_SHIFT_CTLX_LO_LLP_SRC_EN 28
+#define BIT_MASK_CTLX_LO_LLP_SRC_EN 0x1
+#define BIT_CTLX_LO_LLP_SRC_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_SRC_EN) << BIT_SHIFT_CTLX_LO_LLP_SRC_EN)
+#define BIT_INVC_CTLX_LO_LLP_SRC_EN (~(BIT_MASK_CTLX_LO_LLP_SRC_EN << BIT_SHIFT_CTLX_LO_LLP_SRC_EN))
+
+
+#define BIT_SHIFT_CTLX_UP_BLOCK_BS 0
+#define BIT_MASK_CTLX_UP_BLOCK_BS 0xFFF
+#define BIT_CTLX_UP_BLOCK_BS(x)(((x) & BIT_MASK_CTLX_UP_BLOCK_BS) << BIT_SHIFT_CTLX_UP_BLOCK_BS)
+#define BIT_INVC_CTLX_UP_BLOCK_BS (~(BIT_MASK_CTLX_UP_BLOCK_BS << BIT_SHIFT_CTLX_UP_BLOCK_BS))
+
+
+#define BIT_SHIFT_CTLX_UP_DONE 12
+#define BIT_MASK_CTLX_UP_DONE 0x1
+#define BIT_CTLX_UP_DONE(x)(((x) & BIT_MASK_CTLX_UP_DONE) << BIT_SHIFT_CTLX_UP_DONE)
+#define BIT_INVC_CTLX_UP_DONE (~(BIT_MASK_CTLX_UP_DONE << BIT_SHIFT_CTLX_UP_DONE))
+
+
+//3 CFG Register Bit Control
+#define BIT_SHIFT_CFGX_LO_CH_PRIOR 5
+#define BIT_MASK_CFGX_LO_CH_PRIOR 0x7
+#define BIT_CFGX_LO_CH_PRIOR(x)(((x) & BIT_MASK_CFGX_LO_CH_PRIOR) << BIT_SHIFT_CFGX_LO_CH_PRIOR)
+#define BIT_INVC_CFGX_LO_CH_PRIOR (~(BIT_MASK_CFGX_LO_CH_PRIOR << BIT_SHIFT_CFGX_LO_CH_PRIOR))
+
+
+#define BIT_SHIFT_CFGX_LO_CH_SUSP 8
+#define BIT_MASK_CFGX_LO_CH_SUSP 0x1
+#define BIT_CFGX_LO_CH_SUSP(x)(((x) & BIT_MASK_CFGX_LO_CH_SUSP) << BIT_SHIFT_CFGX_LO_CH_SUSP)
+#define BIT_INVC_CFGX_LO_CH_SUSP (~(BIT_MASK_CFGX_LO_CH_SUSP << BIT_SHIFT_CFGX_LO_CH_SUSP))
+
+
+#define BIT_SHIFT_CFGX_LO_FIFO_EMPTY 9
+#define BIT_MASK_CFGX_LO_FIFO_EMPTY 0x1
+#define BIT_CFGX_LO_FIFO_EMPTY(x)(((x) & BIT_MASK_CFGX_LO_FIFO_EMPTY) << BIT_SHIFT_CFGX_LO_FIFO_EMPTY)
+#define BIT_INVC_CFGX_LO_FIFO_EMPTY (~(BIT_MASK_CFGX_LO_FIFO_EMPTY << BIT_SHIFT_CFGX_LO_FIFO_EMPTY))
+
+
+#define BIT_SHIFT_CFGX_LO_HS_SEL_DST 10
+#define BIT_MASK_CFGX_LO_HS_SEL_DST 0x1
+#define BIT_CFGX_LO_HS_SEL_DST(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_DST) << BIT_SHIFT_CFGX_LO_HS_SEL_DST)
+#define BIT_INVC_CFGX_LO_HS_SEL_DST (~(BIT_MASK_CFGX_LO_HS_SEL_DST << BIT_SHIFT_CFGX_LO_HS_SEL_DST))
+
+#define BIT_SHIFT_CFGX_LO_HS_SEL_SRC 11
+#define BIT_MASK_CFGX_LO_HS_SEL_SRC 0x1
+#define BIT_CFGX_LO_HS_SEL_SRC(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_SRC) << BIT_SHIFT_CFGX_LO_HS_SEL_SRC)
+#define BIT_INVC_CFGX_LO_HS_SEL_SRC (~(BIT_MASK_CFGX_LO_HS_SEL_SRC << BIT_SHIFT_CFGX_LO_HS_SEL_SRC))
+
+#define BIT_SHIFT_CFGX_LO_LOCK_CH_L 12
+#define BIT_MASK_CFGX_LO_LOCK_CH_L 0x3
+#define BIT_CFGX_LO_LOCK_CH_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH_L) << BIT_SHIFT_CFGX_LO_LOCK_CH_L)
+#define BIT_INVC_CFGX_LO_LOCK_CH_L (~(BIT_MASK_CFGX_LO_LOCK_CH_L << BIT_SHIFT_CFGX_LO_LOCK_CH_L))
+
+#define BIT_SHIFT_CFGX_LO_LOCK_B_L 14
+#define BIT_MASK_CFGX_LO_LOCK_B_L 0x3
+#define BIT_CFGX_LO_LOCK_B_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B_L) << BIT_SHIFT_CFGX_LO_LOCK_B_L)
+#define BIT_INVC_CFGX_LO_LOCK_B_L (~(BIT_MASK_CFGX_LO_LOCK_B_L << BIT_SHIFT_CFGX_LO_LOCK_B_L))
+
+#define BIT_SHIFT_CFGX_LO_LOCK_CH 16
+#define BIT_MASK_CFGX_LO_LOCK_CH 0x1
+#define BIT_CFGX_LO_LOCK_CH(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH) << BIT_SHIFT_CFGX_LO_LOCK_CH)
+#define BIT_INVC_CFGX_LO_LOCK_CH (~(BIT_MASK_CFGX_LO_LOCK_CH << BIT_SHIFT_CFGX_LO_LOCK_CH))
+
+#define BIT_SHIFT_CFGX_LO_LOCK_B 17
+#define BIT_MASK_CFGX_LO_LOCK_B 0x1
+#define BIT_CFGX_LO_LOCK_B(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B) << BIT_SHIFT_CFGX_LO_LOCK_B)
+#define BIT_INVC_CFGX_LO_LOCK_B (~(BIT_MASK_CFGX_LO_LOCK_B << BIT_SHIFT_CFGX_LO_LOCK_B))
+
+#define BIT_SHIFT_CFGX_LO_DST_HS_POL 18
+#define BIT_MASK_CFGX_LO_DST_HS_POL 0x1
+#define BIT_CFGX_LO_DST_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_DST_HS_POL) << BIT_SHIFT_CFGX_LO_DST_HS_POL)
+#define BIT_INVC_CFGX_LO_DST_HS_POL (~(BIT_MASK_CFGX_LO_DST_HS_POL << BIT_SHIFT_CFGX_LO_DST_HS_POL))
+
+#define BIT_SHIFT_CFGX_LO_SRC_HS_POL 19
+#define BIT_MASK_CFGX_LO_SRC_HS_POL 0x1
+#define BIT_CFGX_LO_SRC_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_SRC_HS_POL) << BIT_SHIFT_CFGX_LO_SRC_HS_POL)
+#define BIT_INVC_CFGX_LO_SRC_HS_POL (~(BIT_MASK_CFGX_LO_SRC_HS_POL << BIT_SHIFT_CFGX_LO_SRC_HS_POL))
+
+#define BIT_SHIFT_CFGX_LO_MAX_ABRST 20
+#define BIT_MASK_CFGX_LO_MAX_ABRST 0x3FF
+#define BIT_CFGX_LO_MAX_ABRST(x)(((x) & BIT_MASK_CFGX_LO_MAX_ABRST) << BIT_SHIFT_CFGX_LO_MAX_ABRST)
+#define BIT_INVC_CFGX_LO_MAX_ABRST (~(BIT_MASK_CFGX_LO_MAX_ABRST << BIT_SHIFT_CFGX_LO_MAX_ABRST))
+
+#define BIT_SHIFT_CFGX_LO_RELOAD_SRC 30
+#define BIT_MASK_CFGX_LO_RELOAD_SRC 0x1
+#define BIT_CFGX_LO_RELOAD_SRC(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_SRC) << BIT_SHIFT_CFGX_LO_RELOAD_SRC)
+#define BIT_INVC_CFGX_LO_RELOAD_SRC (~(BIT_MASK_CFGX_LO_RELOAD_SRC << BIT_SHIFT_CFGX_LO_RELOAD_SRC))
+
+#define BIT_SHIFT_CFGX_LO_RELOAD_DST 31
+#define BIT_MASK_CFGX_LO_RELOAD_DST 0x1
+#define BIT_CFGX_LO_RELOAD_DST(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_DST) << BIT_SHIFT_CFGX_LO_RELOAD_DST)
+#define BIT_INVC_CFGX_LO_RELOAD_DST (~(BIT_MASK_CFGX_LO_RELOAD_DST << BIT_SHIFT_CFGX_LO_RELOAD_DST))
+
+#define BIT_SHIFT_CFGX_UP_FCMODE 0
+#define BIT_MASK_CFGX_UP_FCMODE 0x1
+#define BIT_CFGX_UP_FCMODE(x)(((x) & BIT_MASK_CFGX_UP_FCMODE) << BIT_SHIFT_CFGX_UP_FCMODE)
+#define BIT_INVC_CFGX_UP_FCMODE (~(BIT_MASK_CFGX_UP_FCMODE << BIT_SHIFT_CFGX_UP_FCMODE))
+
+#define BIT_SHIFT_CFGX_UP_FIFO_MODE 1
+#define BIT_MASK_CFGX_UP_FIFO_MODE 0x1
+#define BIT_CFGX_UP_FIFO_MODE(x)(((x) & BIT_MASK_CFGX_UP_FIFO_MODE) << BIT_SHIFT_CFGX_UP_FIFO_MODE)
+#define BIT_INVC_CFGX_UP_FIFO_MODE (~(BIT_MASK_CFGX_UP_FIFO_MODE << BIT_SHIFT_CFGX_UP_FIFO_MODE))
+
+#define BIT_SHIFT_CFGX_UP_PROTCTL 2
+#define BIT_MASK_CFGX_UP_PROTCTL 0x7
+#define BIT_CFGX_UP_PROTCTL(x)(((x) & BIT_MASK_CFGX_UP_PROTCTL) << BIT_SHIFT_CFGX_UP_PROTCTL)
+#define BIT_INVC_CFGX_UP_PROTCTL (~(BIT_MASK_CFGX_UP_PROTCTL << BIT_SHIFT_CFGX_UP_PROTCTL))
+
+#define BIT_SHIFT_CFGX_UP_DS_UPD_EN 5
+#define BIT_MASK_CFGX_UP_DS_UPD_EN 0x1
+#define BIT_CFGX_UP_DS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_DS_UPD_EN) << BIT_SHIFT_CFGX_UP_DS_UPD_EN)
+#define BIT_INVC_CFGX_UP_DS_UPD_EN (~(BIT_MASK_CFGX_UP_DS_UPD_EN << BIT_SHIFT_CFGX_UP_DS_UPD_EN))
+
+#define BIT_SHIFT_CFGX_UP_SS_UPD_EN 6
+#define BIT_MASK_CFGX_UP_SS_UPD_EN 0x1
+#define BIT_CFGX_UP_SS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_SS_UPD_EN) << BIT_SHIFT_CFGX_UP_SS_UPD_EN)
+#define BIT_INVC_CFGX_UP_SS_UPD_EN (~(BIT_MASK_CFGX_UP_SS_UPD_EN << BIT_SHIFT_CFGX_UP_SS_UPD_EN))
+
+#define BIT_SHIFT_CFGX_UP_SRC_PER 7
+#define BIT_MASK_CFGX_UP_SRC_PER 0xF
+#define BIT_CFGX_UP_SRC_PER(x)(((x) & BIT_MASK_CFGX_UP_SRC_PER) << BIT_SHIFT_CFGX_UP_SRC_PER)
+#define BIT_INVC_CFGX_UP_SRC_PER (~(BIT_MASK_CFGX_UP_SRC_PER << BIT_SHIFT_CFGX_UP_SRC_PER))
+
+#define BIT_SHIFT_CFGX_UP_DEST_PER 11
+#define BIT_MASK_CFGX_UP_DEST_PER 0xF
+#define BIT_CFGX_UP_DEST_PER(x)(((x) & BIT_MASK_CFGX_UP_DEST_PER) << BIT_SHIFT_CFGX_UP_DEST_PER)
+#define BIT_INVC_CFGX_UP_DEST_PER (~(BIT_MASK_CFGX_UP_DEST_PER << BIT_SHIFT_CFGX_UP_DEST_PER))
+
+typedef enum _GDMA_CHANNEL_NUM_ {
+        GdmaNoCh    = 0x0000,
+        GdmaCh0     = 0x0101,
+        GdmaCh1     = 0x0202,
+        GdmaCh2     = 0x0404,
+        GdmaCh3     = 0x0808,
+        GdmaCh4     = 0x1010,
+        GdmaCh5     = 0x2020,
+        GdmaCh6     = 0x4040,
+        GdmaCh7     = 0x8080,
+        GdmaAllCh   = 0xffff
+}GDMA_CHANNEL_NUM, *PGDMA_CHANNEL_NUM;
+
+
+//3 CTL register struct
+
+typedef enum _GDMA_CTL_TT_FC_TYPE_ {
+        TTFCMemToMem    = 0x00,
+        TTFCMemToPeri   = 0x01,
+        TTFCPeriToMem   = 0x02
+}GDMA_CTL_TT_FC_TYPE, *PGDMA_CTL_TT_FC_TYPE;
+
+//Max type = Bus Width
+typedef enum _GDMA_CTL_TR_WIDTH_ {
+        TrWidthOneByte    = 0x00,
+        TrWidthTwoBytes   = 0x01,
+        TrWidthFourBytes  = 0x02
+}GDMA_CTL_TR_WIDTH, *PGDMA_CTL_TR_WIDTH;
+
+typedef enum _GDMA_CTL_MSIZE_ {
+        MsizeOne        = 0x00,
+        MsizeFour       = 0x01,
+        MsizeEight      = 0x02
+}GDMA_CTL_MSIZE, *PGDMA_CTL_MSIZE;
+
+typedef enum _GDMA_INC_TYPE_ {
+        IncType         = 0x00,
+        DecType         = 0x01,
+        NoChange        = 0x02
+}GDMA_INC_TYPE, *PGDMA_INC_TYPE;
+
+
+typedef struct _GDMA_CTL_REG_ {
+        GDMA_CTL_TT_FC_TYPE     TtFc;
+        GDMA_CTL_TR_WIDTH       DstTrWidth;
+        GDMA_CTL_TR_WIDTH       SrcTrWidth;
+        GDMA_INC_TYPE           Dinc;
+        GDMA_INC_TYPE           Sinc;
+        GDMA_CTL_MSIZE          DestMsize;
+        GDMA_CTL_MSIZE          SrcMsize;
+
+        u8                      IntEn           :1; // Bit 0
+        u8                      SrcGatherEn     :1; // Bit 1
+        u8                      DstScatterEn    :1; // Bit 2
+        u8                      LlpDstEn        :1; // Bit 3
+        u8                      LlpSrcEn        :1; // Bit 4
+        u8                      Done            :1; // Bit 5
+        u8                      Rsvd6To7        :2; //Bit 6 -7
+        u16                     BlockSize;
+        
+}GDMA_CTL_REG, *PGDMA_CTL_REG;
+
+
+//3 CFG Register Structure
+
+typedef enum _GDMA_CH_PRIORITY_ {
+    Prior0          = 0,
+    Prior1          = 1,
+    Prior2          = 2,
+    Prior3          = 3,
+    Prior4          = 4,
+    Prior5          = 5,
+    Prior6          = 6,
+    Prior7          = 7
+}GDMA_CH_PRIORITY, *PGDMA_CH_PRIORITY;
+
+typedef enum _GDMA_LOCK_LEVEL_ {
+    OverComplDmaTransfer        = 0x00,
+    OverComplDmaBlockTransfer   = 0x01,
+    OverComplDmaTransation      = 0x02
+}GDMA_LOCK_LEVEL, *PGDMA_LOCK_LEVEL;
+
+
+typedef struct _GDMA_CFG_REG_ {
+    GDMA_CH_PRIORITY        ChPrior;
+    GDMA_LOCK_LEVEL         LockBL;     
+    GDMA_LOCK_LEVEL         LockChL;     
+    u16                     MaxAbrst;
+    u8                      SrcPer;
+    u8                      DestPer;
+    u16                     ChSusp      :1; //Bit 0
+    u16                     FifoEmpty   :1; //Bit 1
+    u16                     HsSelDst    :1; //Bit 2
+    u16                     HsSelSrc    :1; //Bit 3
+    u16                     LockCh      :1; //Bit 4
+    u16                     LockB       :1; //Bit 5
+    u16                     DstHsPol    :1; //Bit 6
+    u16                     SrcHsPol    :1; //Bit 7
+    u16                     ReloadSrc   :1; //Bit 8
+    u16                     ReloadDst   :1; //Bit 9
+    u16                     FifoMode    :1; //Bit 10
+    u16                     DsUpdEn     :1; //Bit 11
+    u16                     SsUpdEn     :1; //Bit 12
+    u16                     Rsvd13To15  :3;
+}GDMA_CFG_REG, *PGDMA_CFG_REG;
+
+typedef enum _GDMA_ISR_TYPE_ {
+    TransferType        = 0x1,
+    BlockType           = 0x2,
+    SrcTransferType     = 0x4,
+    DstTransferType     = 0x8,
+    ErrType             = 0x10
+}GDMA_ISR_TYPE, *PGDMA_ISR_TYPE;
+
+
+VOID
+HalGdmaOnOffRtl8195a (
+    IN  VOID              *Data
+);
+
+BOOL
+HalGdamChInitRtl8195a(
+    IN  VOID     *Data
+);
+
+BOOL
+HalGdmaChSetingRtl8195a(
+    IN  VOID     *Data
+);
+
+BOOL
+HalGdmaChBlockSetingRtl8195a(
+    IN  VOID     *Data
+);
+
+
+VOID
+HalGdmaChDisRtl8195a (
+    IN  VOID              *Data
+);
+
+VOID
+HalGdmaChEnRtl8195a (
+    IN  VOID              *Data
+);
+
+VOID
+HalGdmaChIsrEnAndDisRtl8195a (
+    IN  VOID              *Data
+);
+
+u8
+HalGdmaChIsrCleanRtl8195a (
+    IN  VOID              *Data
+);
+
+VOID
+HalGdmaChCleanAutoSrcRtl8195a (
+    IN  VOID              *Data
+);
+
+VOID
+HalGdmaChCleanAutoDstRtl8195a (
+    IN  VOID              *Data
+); 
+
+u32
+HalGdmaQueryDArRtl8195a(
+    IN  VOID     *Data
+);
+
+u32
+HalGdmaQuerySArRtl8195a(
+    IN  VOID     *Data
+);
+
+BOOL
+HalGdmaQueryChEnRtl8195a (
+    IN  VOID              *Data
+);
+
+#ifdef CONFIG_CHIP_E_CUT
+_LONG_CALL_ BOOL
+HalGdmaChBlockSetingRtl8195a_V04(
+    IN  VOID     *Data
+);
+
+_LONG_CALL_ u32
+HalGdmaQueryDArRtl8195a_V04(
+    IN  VOID     *Data
+);
+
+_LONG_CALL_ u32
+HalGdmaQuerySArRtl8195a_V04(
+    IN  VOID     *Data
+);
+
+_LONG_CALL_ BOOL
+HalGdmaQueryChEnRtl8195a_V04 (
+    IN  VOID      *Data
+);
+
+#endif  // #ifdef CONFIG_CHIP_E_CUT
+
+#endif

sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gpio.h

@@ -0,0 +1,352 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_GPIO_H_
+#define _RTL8195A_GPIO_H_
+
+#include "hal_api.h"
+#include "hal_gpio.h"
+
+#define GPIO_PORTA_DR           0x00        // data register
+#define GPIO_PORTA_DDR          0x04        // data direction
+#define GPIO_PORTA_CTRL         0x08        // data source control, we should keep it as default: data source from software
+
+#define GPIO_PORTB_DR           0x0c        // data register
+#define GPIO_PORTB_DDR          0x10        // data direction
+#define GPIO_PORTB_CTRL         0x14        // data source control, we should keep it as default: data source from software
+
+#define GPIO_PORTC_DR           0x18        // data register
+#define GPIO_PORTC_DDR          0x1c        // data direction
+#define GPIO_PORTC_CTRL         0x20        // data source control, we should keep it as default: data source from software
+
+//1 Only the PORTA can be configured to generate interrupts
+#define GPIO_INT_EN             0x30        // Interrupt enable register
+#define GPIO_INT_MASK           0x34        // Interrupt mask
+#define GPIO_INT_TYPE           0x38        // Interrupt type(level/edge) register
+#define GPIO_INT_POLARITY       0x3C        // Interrupt polarity(Active low/high) register
+#define GPIO_INT_STATUS         0x40        // Interrupt status
+#define GPIO_INT_RAWSTATUS      0x44        // Interrupt status without mask
+#define GPIO_DEBOUNCE           0x48        // Interrupt signal debounce
+#define GPIO_PORTA_EOI          0x4c        // Clear interrupt
+
+#define GPIO_EXT_PORTA          0x50        // GPIO IN read or OUT read back
+#define GPIO_EXT_PORTB          0x54        // GPIO IN read or OUT read back
+#define GPIO_EXT_PORTC          0x58        // GPIO IN read or OUT read back
+
+#define GPIO_INT_SYNC           0x60        // Is level-sensitive interrupt being sync sith PCLK
+
+enum {
+    HAL_GPIO_HIGHZ      = 0,
+    HAL_GPIO_PULL_LOW   = 1,
+    HAL_GPIO_PULL_HIGH  = 2
+};
+
+//======================================================
+// ROM Function prototype
+extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
+
+static __inline HAL_Status
+GPIO_Lock (
+    VOID
+)
+{
+    HAL_Status Status;
+
+    if (_pHAL_Gpio_Adapter->EnterCritical) {
+        _pHAL_Gpio_Adapter->EnterCritical();
+    }
+
+    if(_pHAL_Gpio_Adapter->Locked) {
+       Status = HAL_BUSY;
+    }
+    else {
+       _pHAL_Gpio_Adapter->Locked = 1;
+       Status = HAL_OK;
+    }
+
+    if (_pHAL_Gpio_Adapter->ExitCritical) {
+        _pHAL_Gpio_Adapter->ExitCritical();
+    }
+
+    return Status;
+}
+
+
+static __inline VOID
+GPIO_UnLock (
+    VOID
+)
+{
+    if (_pHAL_Gpio_Adapter->EnterCritical) {
+        _pHAL_Gpio_Adapter->EnterCritical();
+    }
+
+    _pHAL_Gpio_Adapter->Locked = 0;
+
+    if (_pHAL_Gpio_Adapter->ExitCritical) {
+        _pHAL_Gpio_Adapter->ExitCritical();
+    }
+}
+
+
+_LONG_CALL_ extern u32
+HAL_GPIO_IrqHandler_8195a(
+    IN VOID *pData
+);
+
+_LONG_CALL_ extern u32
+HAL_GPIO_MbedIrqHandler_8195a(
+    IN VOID *pData
+);
+
+_LONG_CALL_ HAL_Status 
+HAL_GPIO_IntCtrl_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin, 
+    u32 En
+);
+
+_LONG_CALL_ HAL_Status 
+HAL_GPIO_Init_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+_LONG_CALL_ HAL_Status 
+HAL_GPIO_DeInit_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+_LONG_CALL_ HAL_GPIO_PIN_STATE 
+HAL_GPIO_ReadPin_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+_LONG_CALL_ HAL_Status 
+HAL_GPIO_WritePin_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin,
+    HAL_GPIO_PIN_STATE Pin_State
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_RegIrq_8195a(
+    IN PIRQ_HANDLE pIrqHandle
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_UnRegIrq_8195a(
+    IN PIRQ_HANDLE pIrqHandle
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_UserRegIrq_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin,
+    VOID *IrqHandler,
+    VOID *IrqData
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_UserUnRegIrq_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_MaskIrq_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_UnMaskIrq_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_IntDebounce_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin,
+    u8 Enable
+);
+
+_LONG_CALL_ u32
+HAL_GPIO_GetIPPinName_8195a(
+    u32 chip_pin
+);
+
+_LONG_CALL_ HAL_Status
+HAL_GPIO_PullCtrl_8195a(
+    u32 chip_pin,
+    u8 pull_type
+);
+
+_LONG_CALL_ u32 
+GPIO_GetChipPinName_8195a(
+    u32 port,
+    u32 pin
+);
+
+_LONG_CALL_ VOID 
+GPIO_PullCtrl_8195a(
+    u32 chip_pin,
+    u8 pull_type
+);
+
+_LONG_CALL_ VOID 
+GPIO_Int_SetType_8195a(
+    u8 pin_num,
+    u8 int_mode
+);
+
+
+_LONG_CALL_  HAL_Status HAL_GPIO_IntCtrl_8195aV02(HAL_GPIO_PIN  *GPIO_Pin, u32 En);
+_LONG_CALL_ u32 GPIO_Int_Clear_8195aV02(u32 irq_clr);
+
+HAL_Status
+HAL_GPIO_ClearISR_8195a(
+    HAL_GPIO_PIN  *GPIO_Pin
+);
+
+
+/********** HAL In-Line Functions **********/
+
+/**
+  * @brief  De-Initializes a GPIO Pin, reset it as default setting.
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @retval HAL_Status
+  */
+static __inline VOID 
+HAL_GPIO_DeInit(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    HAL_GPIO_DeInit_8195a(GPIO_Pin);
+}
+
+/**
+  * @brief  Reads the specified input port pin.
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @retval The input port pin current status(High or Low).
+  */
+static __inline s32 
+HAL_GPIO_ReadPin(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    return (s32)HAL_GPIO_ReadPin_8195a(GPIO_Pin);    
+}
+
+/**
+  * @brief  Write the specified output port pin.
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @param  Pin_State: The state going to be set to the assigned GPIO pin.
+  *
+  * @retval None
+  */
+static __inline VOID 
+HAL_GPIO_WritePin(
+    HAL_GPIO_PIN  *GPIO_Pin,
+    u32 Value
+)
+{
+    HAL_GPIO_WritePin_8195a(GPIO_Pin, (HAL_GPIO_PIN_STATE)Value);
+}
+
+/**
+  * @brief  To register a user interrupt handler for a specified pin
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @param  IrqHandler: The IRQ handler to be assigned to the specified pin
+  *
+  * @param  IrqData: The pointer will be pass the the IRQ handler
+  *
+  * @retval None
+  */
+static __inline VOID
+HAL_GPIO_UserRegIrq(
+    HAL_GPIO_PIN  *GPIO_Pin,
+    VOID *IrqHandler,
+    VOID *IrqData
+)
+{
+    HAL_GPIO_UserRegIrq_8195a(GPIO_Pin, IrqHandler, IrqData);
+}
+
+/**
+  * @brief  To un-register a user interrupt handler for a specified pin
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @retval None
+  */
+static __inline VOID
+HAL_GPIO_UserUnRegIrq(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    HAL_GPIO_UserUnRegIrq_8195a(GPIO_Pin);
+}
+
+
+/**
+  * @brief  Enable/Disable GPIO interrupt
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
+  *
+  * @param  En: Enable (1) or Disable (0)
+  *
+  * @retval HAL_Status
+  */
+static __inline VOID
+HAL_GPIO_IntCtrl(
+    HAL_GPIO_PIN  *GPIO_Pin, 
+    u32 En
+)
+{
+    HAL_GPIO_IntCtrl_8195a(GPIO_Pin, En);
+}
+
+/**
+  * @brief  Mask the interrupt of a specified pin
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @retval None
+  */
+static __inline VOID
+HAL_GPIO_MaskIrq(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    HAL_GPIO_MaskIrq_8195a(GPIO_Pin);
+}
+
+
+/**
+  * @brief  UnMask the interrupt of a specified pin
+  *
+  * @param  GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
+  *
+  * @retval None
+  */
+static __inline VOID
+HAL_GPIO_UnMaskIrq(
+    HAL_GPIO_PIN  *GPIO_Pin
+)
+{
+    HAL_GPIO_ClearISR_8195a(GPIO_Pin);
+    HAL_GPIO_UnMaskIrq_8195a(GPIO_Pin);
+}
+
+
+#endif  // end of "#define _RTL8195A_GPIO_H_"
+

sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h

@@ -0,0 +1,851 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _RTL8195A_I2C_H_
+#define _RTL8195A_I2C_H_
+
+#include "hal_api.h"
+
+//================ Register Bit Field ==================
+//2 REG_DW_I2C_IC_CON
+#define BIT_IC_CON_IC_SLAVE_DISABLE           	BIT(6)
+#define BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE     	6
+#define BIT_MASK_IC_CON_IC_SLAVE_DISABLE      	0x1
+#define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(x)   	(((x) & BIT_MASK_IC_CON_IC_SLAVE_DISABLE) << BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE)
+
+#define BIT_IC_CON_IC_RESTART_EN              	BIT(5)
+#define BIT_SHIFT_IC_CON_IC_RESTART_EN        	5
+#define BIT_MASK_IC_CON_IC_RESTART_EN         	0x1
+#define BIT_CTRL_IC_CON_IC_RESTART_EN(x)      	(((x) & BIT_MASK_IC_CON_IC_RESTART_EN) << BIT_SHIFT_IC_CON_IC_RESTART_EN)
+
+#define BIT_IC_CON_IC_10BITADDR_MASTER        	BIT(4)
+#define BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER  	4
+#define BIT_MASK_IC_CON_IC_10BITADDR_MASTER   	0x1
+#define BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(x)	(((x) & BIT_MASK_IC_CON_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER)
+
+#define BIT_IC_CON_IC_10BITADDR_SLAVE         	BIT(3)
+#define BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE   	3
+#define BIT_MASK_IC_CON_IC_10BITADDR_SLAVE    	0x1
+#define BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(x) 	(((x) & BIT_MASK_IC_CON_IC_10BITADDR_SLAVE) << BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE)
+
+
+#define BIT_SHIFT_IC_CON_SPEED 1
+#define BIT_MASK_IC_CON_SPEED 0x3
+#define BIT_IC_CON_SPEED(x)                   	(((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
+#define BIT_CTRL_IC_CON_SPEED(x)              	(((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
+#define BIT_GET_IC_CON_SPEED(x)               	(((x) >> BIT_SHIFT_IC_CON_SPEED) & BIT_MASK_IC_CON_SPEED)
+
+#define BIT_IC_CON_MASTER_MODE                	BIT(0)
+#define BIT_SHIFT_IC_CON_MASTER_MODE          	0
+#define BIT_MASK_IC_CON_MASTER_MODE           	0x1
+#define BIT_CTRL_IC_CON_MASTER_MODE(x)        	(((x) & BIT_MASK_IC_CON_MASTER_MODE) << BIT_SHIFT_IC_CON_MASTER_MODE)
+
+
+//2 REG_DW_I2C_IC_TAR
+#define BIT_IC_TAR_IC_10BITADDR_MASTER        	BIT(12)
+#define BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER  	12
+#define BIT_MASK_IC_TAR_IC_10BITADDR_MASTER   	0x1
+#define BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(x)	(((x) & BIT_MASK_IC_TAR_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER)
+
+#define BIT_IC_TAR_SPECIAL                    	BIT(11)
+#define BIT_SHIFT_IC_TAR_SPECIAL              	11
+#define BIT_MASK_IC_TAR_SPECIAL               	0x1
+#define BIT_CTRL_IC_TAR_SPECIAL(x)            	(((x) & BIT_MASK_IC_TAR_SPECIAL) << BIT_SHIFT_IC_TAR_SPECIAL)
+
+#define BIT_IC_TAR_GC_OR_START                	BIT(10)
+#define BIT_SHIFT_IC_TAR_GC_OR_START          	10
+#define BIT_MASK_IC_TAR_GC_OR_START           	0x1
+#define BIT_CTRL_IC_TAR_GC_OR_START(x)        	(((x) & BIT_MASK_IC_TAR_GC_OR_START) << BIT_SHIFT_IC_TAR_GC_OR_START)
+
+
+#define BIT_SHIFT_IC_TAR 0
+#define BIT_MASK_IC_TAR 0x3ff
+#define BIT_IC_TAR(x)                         	(((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
+#define BIT_CTRL_IC_TAR(x)                    	(((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
+#define BIT_GET_IC_TAR(x)                     	(((x) >> BIT_SHIFT_IC_TAR) & BIT_MASK_IC_TAR)
+
+
+//2 REG_DW_I2C_IC_SAR
+
+#define BIT_SHIFT_IC_SAR 0
+#define BIT_MASK_IC_SAR 0x3ff
+#define BIT_IC_SAR(x)                         	(((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
+#define BIT_CTRL_IC_SAR(x)                    	(((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
+#define BIT_GET_IC_SAR(x)                     	(((x) >> BIT_SHIFT_IC_SAR) & BIT_MASK_IC_SAR)
+
+
+//2 REG_DW_I2C_IC_HS_MADDR
+
+#define BIT_SHIFT_IC_HS_MADDR 0
+#define BIT_MASK_IC_HS_MADDR 0x7
+#define BIT_IC_HS_MADDR(x)                    	(((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
+#define BIT_CTRL_IC_HS_MADDR(x)               	(((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
+#define BIT_GET_IC_HS_MADDR(x)                	(((x) >> BIT_SHIFT_IC_HS_MADDR) & BIT_MASK_IC_HS_MADDR)
+
+
+//2 REG_DW_I2C_IC_DATA_CMD
+#define BIT_IC_DATA_CMD_RESTART               	BIT(10)
+#define BIT_SHIFT_IC_DATA_CMD_RESTART         	10
+#define BIT_MASK_IC_DATA_CMD_RESTART          	0x1
+#define BIT_CTRL_IC_DATA_CMD_RESTART(x)       	(((x) & BIT_MASK_IC_DATA_CMD_RESTART) << BIT_SHIFT_IC_DATA_CMD_RESTART)
+
+#define BIT_IC_DATA_CMD_STOP                  	BIT(9)
+#define BIT_SHIFT_IC_DATA_CMD_STOP            	9
+#define BIT_MASK_IC_DATA_CMD_STOP             	0x1
+#define BIT_CTRL_IC_DATA_CMD_STOP(x)          	(((x) & BIT_MASK_IC_DATA_CMD_STOP) << BIT_SHIFT_IC_DATA_CMD_STOP)
+
+#define BIT_IC_DATA_CMD_CMD                   	BIT(8)
+#define BIT_SHIFT_IC_DATA_CMD_CMD             	8
+#define BIT_MASK_IC_DATA_CMD_CMD              	0x1
+#define BIT_CTRL_IC_DATA_CMD_CMD(x)           	(((x) & BIT_MASK_IC_DATA_CMD_CMD) << BIT_SHIFT_IC_DATA_CMD_CMD)
+
+
+#define BIT_SHIFT_IC_DATA_CMD_DAT 0
+#define BIT_MASK_IC_DATA_CMD_DAT 0xff
+#define BIT_IC_DATA_CMD_DAT(x)                	(((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
+#define BIT_CTRL_IC_DATA_CMD_DAT(x)           	(((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
+#define BIT_GET_IC_DATA_CMD_DAT(x)            	(((x) >> BIT_SHIFT_IC_DATA_CMD_DAT) & BIT_MASK_IC_DATA_CMD_DAT)
+
+
+//2 REG_DW_I2C_IC_SS_SCL_HCNT
+
+#define BIT_SHIFT_IC_SS_SCL_HCNT 0
+#define BIT_MASK_IC_SS_SCL_HCNT 0xffff
+#define BIT_IC_SS_SCL_HCNT(x)                 	(((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
+#define BIT_CTRL_IC_SS_SCL_HCNT(x)            	(((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
+#define BIT_GET_IC_SS_SCL_HCNT(x)             	(((x) >> BIT_SHIFT_IC_SS_SCL_HCNT) & BIT_MASK_IC_SS_SCL_HCNT)
+
+
+//2 REG_DW_I2C_IC_SS_SCL_LCNT
+
+#define BIT_SHIFT_IC_SS_SCL_LCNT 0
+#define BIT_MASK_IC_SS_SCL_LCNT 0xffff
+#define BIT_IC_SS_SCL_LCNT(x)                 	(((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
+#define BIT_CTRL_IC_SS_SCL_LCNT(x)            	(((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
+#define BIT_GET_IC_SS_SCL_LCNT(x)             	(((x) >> BIT_SHIFT_IC_SS_SCL_LCNT) & BIT_MASK_IC_SS_SCL_LCNT)
+
+
+//2 REG_DW_I2C_IC_FS_SCL_HCNT
+
+#define BIT_SHIFT_IC_FS_SCL_HCNT 0
+#define BIT_MASK_IC_FS_SCL_HCNT 0xffff
+#define BIT_IC_FS_SCL_HCNT(x)                 	(((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
+#define BIT_CTRL_IC_FS_SCL_HCNT(x)            	(((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
+#define BIT_GET_IC_FS_SCL_HCNT(x)             	(((x) >> BIT_SHIFT_IC_FS_SCL_HCNT) & BIT_MASK_IC_FS_SCL_HCNT)
+
+
+//2 REG_DW_I2C_IC_FS_SCL_LCNT
+
+#define BIT_SHIFT_IC_FS_SCL_LCNT 0
+#define BIT_MASK_IC_FS_SCL_LCNT 0xffff
+#define BIT_IC_FS_SCL_LCNT(x)                 	(((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
+#define BIT_CTRL_IC_FS_SCL_LCNT(x)            	(((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
+#define BIT_GET_IC_FS_SCL_LCNT(x)             	(((x) >> BIT_SHIFT_IC_FS_SCL_LCNT) & BIT_MASK_IC_FS_SCL_LCNT)
+
+
+//2 REG_DW_I2C_IC_HS_SCL_HCNT
+
+#define BIT_SHIFT_IC_HS_SCL_HCNT 0
+#define BIT_MASK_IC_HS_SCL_HCNT 0xffff
+#define BIT_IC_HS_SCL_HCNT(x)                 	(((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
+#define BIT_CTRL_IC_HS_SCL_HCNT(x)            	(((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
+#define BIT_GET_IC_HS_SCL_HCNT(x)             	(((x) >> BIT_SHIFT_IC_HS_SCL_HCNT) & BIT_MASK_IC_HS_SCL_HCNT)
+
+
+//2 REG_DW_I2C_IC_HS_SCL_LCNT
+
+#define BIT_SHIFT_IC_HS_SCL_LCNT 0
+#define BIT_MASK_IC_HS_SCL_LCNT 0xffff
+#define BIT_IC_HS_SCL_LCNT(x)                 	(((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
+#define BIT_CTRL_IC_HS_SCL_LCNT(x)            	(((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
+#define BIT_GET_IC_HS_SCL_LCNT(x)             	(((x) >> BIT_SHIFT_IC_HS_SCL_LCNT) & BIT_MASK_IC_HS_SCL_LCNT)
+
+
+//2 REG_DW_I2C_IC_INTR_STAT
+#define BIT_IC_INTR_STAT_R_GEN_CALL           	BIT(11)
+#define BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL     	11
+#define BIT_MASK_IC_INTR_STAT_R_GEN_CALL      	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_GEN_CALL(x)   	(((x) & BIT_MASK_IC_INTR_STAT_R_GEN_CALL) << BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL)
+
+#define BIT_IC_INTR_STAT_R_START_DET          	BIT(10)
+#define BIT_SHIFT_IC_INTR_STAT_R_START_DET    	10
+#define BIT_MASK_IC_INTR_STAT_R_START_DET     	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_START_DET(x)  	(((x) & BIT_MASK_IC_INTR_STAT_R_START_DET) << BIT_SHIFT_IC_INTR_STAT_R_START_DET)
+
+#define BIT_IC_INTR_STAT_R_STOP_DET           	BIT(9)
+#define BIT_SHIFT_IC_INTR_STAT_R_STOP_DET     	9
+#define BIT_MASK_IC_INTR_STAT_R_STOP_DET      	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_STOP_DET(x)   	(((x) & BIT_MASK_IC_INTR_STAT_R_STOP_DET) << BIT_SHIFT_IC_INTR_STAT_R_STOP_DET)
+
+#define BIT_IC_INTR_STAT_R_ACTIVITY           	BIT(8)
+#define BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY     	8
+#define BIT_MASK_IC_INTR_STAT_R_ACTIVITY      	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_ACTIVITY(x)   	(((x) & BIT_MASK_IC_INTR_STAT_R_ACTIVITY) << BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY)
+
+#define BIT_IC_INTR_STAT_R_RX_DONE            	BIT(7)
+#define BIT_SHIFT_IC_INTR_STAT_R_RX_DONE      	7
+#define BIT_MASK_IC_INTR_STAT_R_RX_DONE       	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_RX_DONE(x)    	(((x) & BIT_MASK_IC_INTR_STAT_R_RX_DONE) << BIT_SHIFT_IC_INTR_STAT_R_RX_DONE)
+
+#define BIT_IC_INTR_STAT_R_TX_ABRT            	BIT(6)
+#define BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT      	6
+#define BIT_MASK_IC_INTR_STAT_R_TX_ABRT       	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_TX_ABRT(x)    	(((x) & BIT_MASK_IC_INTR_STAT_R_TX_ABRT) << BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT)
+
+#define BIT_IC_INTR_STAT_R_RD_REQ             	BIT(5)
+#define BIT_SHIFT_IC_INTR_STAT_R_RD_REQ       	5
+#define BIT_MASK_IC_INTR_STAT_R_RD_REQ        	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_RD_REQ(x)     	(((x) & BIT_MASK_IC_INTR_STAT_R_RD_REQ) << BIT_SHIFT_IC_INTR_STAT_R_RD_REQ)
+
+#define BIT_IC_INTR_STAT_R_TX_EMPTY           	BIT(4)
+#define BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY     	4
+#define BIT_MASK_IC_INTR_STAT_R_TX_EMPTY      	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_TX_EMPTY(x)   	(((x) & BIT_MASK_IC_INTR_STAT_R_TX_EMPTY) << BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY)
+
+#define BIT_IC_INTR_STAT_R_TX_OVER            	BIT(3)
+#define BIT_SHIFT_IC_INTR_STAT_R_TX_OVER      	3
+#define BIT_MASK_IC_INTR_STAT_R_TX_OVER       	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_TX_OVER(x)    	(((x) & BIT_MASK_IC_INTR_STAT_R_TX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_TX_OVER)
+
+#define BIT_IC_INTR_STAT_R_RX_FULL            	BIT(2)
+#define BIT_SHIFT_IC_INTR_STAT_R_RX_FULL      	2
+#define BIT_MASK_IC_INTR_STAT_R_RX_FULL       	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_RX_FULL(x)    	(((x) & BIT_MASK_IC_INTR_STAT_R_RX_FULL) << BIT_SHIFT_IC_INTR_STAT_R_RX_FULL)
+
+#define BIT_IC_INTR_STAT_R_RX_OVER            	BIT(1)
+#define BIT_SHIFT_IC_INTR_STAT_R_RX_OVER      	1
+#define BIT_MASK_IC_INTR_STAT_R_RX_OVER       	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_RX_OVER(x)    	(((x) & BIT_MASK_IC_INTR_STAT_R_RX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_RX_OVER)
+
+#define BIT_IC_INTR_STAT_R_RX_UNDER           	BIT(0)
+#define BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER     	0
+#define BIT_MASK_IC_INTR_STAT_R_RX_UNDER      	0x1
+#define BIT_CTRL_IC_INTR_STAT_R_RX_UNDER(x)   	(((x) & BIT_MASK_IC_INTR_STAT_R_RX_UNDER) << BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER)
+
+
+//2 REG_DW_I2C_IC_INTR_MASK
+#define BIT_IC_INTR_MASK_M_GEN_CALL           	BIT(11)
+#define BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL     	11
+#define BIT_MASK_IC_INTR_MASK_M_GEN_CALL      	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_GEN_CALL(x)   	(((x) & BIT_MASK_IC_INTR_MASK_M_GEN_CALL) << BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL)
+
+#define BIT_IC_INTR_MASK_M_START_DET          	BIT(10)
+#define BIT_SHIFT_IC_INTR_MASK_M_START_DET    	10
+#define BIT_MASK_IC_INTR_MASK_M_START_DET     	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_START_DET(x)  	(((x) & BIT_MASK_IC_INTR_MASK_M_START_DET) << BIT_SHIFT_IC_INTR_MASK_M_START_DET)
+
+#define BIT_IC_INTR_MASK_M_STOP_DET           	BIT(9)
+#define BIT_SHIFT_IC_INTR_MASK_M_STOP_DET     	9
+#define BIT_MASK_IC_INTR_MASK_M_STOP_DET      	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_STOP_DET(x)   	(((x) & BIT_MASK_IC_INTR_MASK_M_STOP_DET) << BIT_SHIFT_IC_INTR_MASK_M_STOP_DET)
+
+#define BIT_IC_INTR_MASK_M_ACTIVITY           	BIT(8)
+#define BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY     	8
+#define BIT_MASK_IC_INTR_MASK_M_ACTIVITY      	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_ACTIVITY(x)   	(((x) & BIT_MASK_IC_INTR_MASK_M_ACTIVITY) << BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY)
+
+#define BIT_IC_INTR_MASK_M_RX_DONE            	BIT(7)
+#define BIT_SHIFT_IC_INTR_MASK_M_RX_DONE      	7
+#define BIT_MASK_IC_INTR_MASK_M_RX_DONE       	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_RX_DONE(x)    	(((x) & BIT_MASK_IC_INTR_MASK_M_RX_DONE) << BIT_SHIFT_IC_INTR_MASK_M_RX_DONE)
+
+#define BIT_IC_INTR_MASK_M_TX_ABRT            	BIT(6)
+#define BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT      	6
+#define BIT_MASK_IC_INTR_MASK_M_TX_ABRT       	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_TX_ABRT(x)    	(((x) & BIT_MASK_IC_INTR_MASK_M_TX_ABRT) << BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT)
+
+#define BIT_IC_INTR_MASK_M_RD_REQ             	BIT(5)
+#define BIT_SHIFT_IC_INTR_MASK_M_RD_REQ       	5
+#define BIT_MASK_IC_INTR_MASK_M_RD_REQ        	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_RD_REQ(x)     	(((x) & BIT_MASK_IC_INTR_MASK_M_RD_REQ) << BIT_SHIFT_IC_INTR_MASK_M_RD_REQ)
+
+#define BIT_IC_INTR_MASK_M_TX_EMPTY           	BIT(4)
+#define BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY     	4
+#define BIT_MASK_IC_INTR_MASK_M_TX_EMPTY      	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_TX_EMPTY(x)   	(((x) & BIT_MASK_IC_INTR_MASK_M_TX_EMPTY) << BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY)
+
+#define BIT_IC_INTR_MASK_M_TX_OVER            	BIT(3)
+#define BIT_SHIFT_IC_INTR_MASK_M_TX_OVER      	3
+#define BIT_MASK_IC_INTR_MASK_M_TX_OVER       	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_TX_OVER(x)    	(((x) & BIT_MASK_IC_INTR_MASK_M_TX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_TX_OVER)
+
+#define BIT_IC_INTR_MASK_M_RX_FULL            	BIT(2)
+#define BIT_SHIFT_IC_INTR_MASK_M_RX_FULL      	2
+#define BIT_MASK_IC_INTR_MASK_M_RX_FULL       	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_RX_FULL(x)    	(((x) & BIT_MASK_IC_INTR_MASK_M_RX_FULL) << BIT_SHIFT_IC_INTR_MASK_M_RX_FULL)
+
+#define BIT_IC_INTR_MASK_M_RX_OVER            	BIT(1)
+#define BIT_SHIFT_IC_INTR_MASK_M_RX_OVER      	1
+#define BIT_MASK_IC_INTR_MASK_M_RX_OVER       	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_RX_OVER(x)    	(((x) & BIT_MASK_IC_INTR_MASK_M_RX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_RX_OVER)
+
+#define BIT_IC_INTR_MASK_M_RX_UNDER           	BIT(0)
+#define BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER     	0
+#define BIT_MASK_IC_INTR_MASK_M_RX_UNDER      	0x1
+#define BIT_CTRL_IC_INTR_MASK_M_RX_UNDER(x)   	(((x) & BIT_MASK_IC_INTR_MASK_M_RX_UNDER) << BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER)
+
+
+//2 REG_DW_I2C_IC_RAW_INTR_STAT
+#define BIT_IC_RAW_INTR_STAT_GEN_CALL         	BIT(11)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL   	11
+#define BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL    	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_GEN_CALL(x) 	(((x) & BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL) << BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL)
+
+#define BIT_IC_RAW_INTR_STAT_START_DET        	BIT(10)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_START_DET  	10
+#define BIT_MASK_IC_RAW_INTR_STAT_START_DET   	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_START_DET(x)	(((x) & BIT_MASK_IC_RAW_INTR_STAT_START_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_START_DET)
+
+#define BIT_IC_RAW_INTR_STAT_STOP_DET         	BIT(9)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET   	9
+#define BIT_MASK_IC_RAW_INTR_STAT_STOP_DET    	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_STOP_DET(x) 	(((x) & BIT_MASK_IC_RAW_INTR_STAT_STOP_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET)
+
+#define BIT_IC_RAW_INTR_STAT_ACTIVITY         	BIT(8)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY   	8
+#define BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY    	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_ACTIVITY(x) 	(((x) & BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY) << BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY)
+
+#define BIT_IC_RAW_INTR_STAT_RX_DONE          	BIT(7)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE    	7
+#define BIT_MASK_IC_RAW_INTR_STAT_RX_DONE     	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_RX_DONE(x)  	(((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_DONE) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE)
+
+#define BIT_IC_RAW_INTR_STAT_TX_ABRT          	BIT(6)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT    	6
+#define BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT     	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_TX_ABRT(x)  	(((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT)
+
+#define BIT_IC_RAW_INTR_STAT_RD_REQ           	BIT(5)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ     	5
+#define BIT_MASK_IC_RAW_INTR_STAT_RD_REQ      	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_RD_REQ(x)   	(((x) & BIT_MASK_IC_RAW_INTR_STAT_RD_REQ) << BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ)
+
+#define BIT_IC_RAW_INTR_STAT_TX_EMPTY         	BIT(4)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY   	4
+#define BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY    	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_TX_EMPTY(x) 	(((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY)
+
+#define BIT_IC_RAW_INTR_STAT_TX_OVER          	BIT(3)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER    	3
+#define BIT_MASK_IC_RAW_INTR_STAT_TX_OVER     	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_TX_OVER(x)  	(((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER)
+
+#define BIT_IC_RAW_INTR_STAT_RX_FULL          	BIT(2)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL    	2
+#define BIT_MASK_IC_RAW_INTR_STAT_RX_FULL     	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_RX_FULL(x)  	(((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_FULL) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL)
+
+#define BIT_IC_RAW_INTR_STAT_RX_OVER          	BIT(1)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER    	1
+#define BIT_MASK_IC_RAW_INTR_STAT_RX_OVER     	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_RX_OVER(x)  	(((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER)
+
+#define BIT_IC_RAW_INTR_STAT_RX_UNDER         	BIT(0)
+#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER   	0
+#define BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER    	0x1
+#define BIT_CTRL_IC_RAW_INTR_STAT_RX_UNDER(x) 	(((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER)
+
+
+//2 REG_DW_I2C_IC_RX_TL
+
+#define BIT_SHIFT_IC_RX_TL 0
+#define BIT_MASK_IC_RX_TL 0xff
+#define BIT_IC_RX_TL(x)                       	(((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
+#define BIT_CTRL_IC_RX_TL(x)                  	(((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
+#define BIT_GET_IC_RX_TL(x)                   	(((x) >> BIT_SHIFT_IC_RX_TL) & BIT_MASK_IC_RX_TL)
+
+
+//2 REG_DW_I2C_IC_TX_TL
+
+#define BIT_SHIFT_IC_TX_TL 0
+#define BIT_MASK_IC_TX_TL 0xff
+#define BIT_IC_TX_TL(x)                       	(((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
+#define BIT_CTRL_IC_TX_TL(x)                  	(((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
+#define BIT_GET_IC_TX_TL(x)                   	(((x) >> BIT_SHIFT_IC_TX_TL) & BIT_MASK_IC_TX_TL)
+
+
+//2 REG_DW_I2C_IC_CLR_INTR
+#define BIT_IC_CLR_INTR                       	BIT(0)
+#define BIT_SHIFT_IC_CLR_INTR                 	0
+#define BIT_MASK_IC_CLR_INTR                  	0x1
+#define BIT_CTRL_IC_CLR_INTR(x)               	(((x) & BIT_MASK_IC_CLR_INTR) << BIT_SHIFT_IC_CLR_INTR)
+
+
+//2 REG_DW_I2C_IC_CLR_RX_UNDER
+#define BIT_IC_CLR_RX_UNDER                   	BIT(0)
+#define BIT_SHIFT_IC_CLR_RX_UNDER             	0
+#define BIT_MASK_IC_CLR_RX_UNDER              	0x1
+#define BIT_CTRL_IC_CLR_RX_UNDER(x)           	(((x) & BIT_MASK_IC_CLR_RX_UNDER) << BIT_SHIFT_IC_CLR_RX_UNDER)
+
+
+//2 REG_DW_I2C_IC_CLR_RX_OVER
+#define BIT_IC_CLR_RX_OVER                    	BIT(0)
+#define BIT_SHIFT_IC_CLR_RX_OVER              	0
+#define BIT_MASK_IC_CLR_RX_OVER               	0x1
+#define BIT_CTRL_IC_CLR_RX_OVER(x)            	(((x) & BIT_MASK_IC_CLR_RX_OVER) << BIT_SHIFT_IC_CLR_RX_OVER)
+
+
+//2 REG_DW_I2C_IC_CLR_TX_OVER
+#define BIT_IC_CLR_TX_OVER                    	BIT(0)
+#define BIT_SHIFT_IC_CLR_TX_OVER              	0
+#define BIT_MASK_IC_CLR_TX_OVER               	0x1
+#define BIT_CTRL_IC_CLR_TX_OVER(x)            	(((x) & BIT_MASK_IC_CLR_TX_OVER) << BIT_SHIFT_IC_CLR_TX_OVER)
+
+
+//2 REG_DW_I2C_IC_CLR_RD_REQ
+#define BIT_IC_CLR_RD_REQ                     	BIT(0)
+#define BIT_SHIFT_IC_CLR_RD_REQ               	0
+#define BIT_MASK_IC_CLR_RD_REQ                	0x1
+#define BIT_CTRL_IC_CLR_RD_REQ(x)             	(((x) & BIT_MASK_IC_CLR_RD_REQ) << BIT_SHIFT_IC_CLR_RD_REQ)
+
+
+//2 REG_DW_I2C_IC_CLR_TX_ABRT
+#define BIT_CLR_RD_REQ                        	BIT(0)
+#define BIT_SHIFT_CLR_RD_REQ                  	0
+#define BIT_MASK_CLR_RD_REQ                   	0x1
+#define BIT_CTRL_CLR_RD_REQ(x)                	(((x) & BIT_MASK_CLR_RD_REQ) << BIT_SHIFT_CLR_RD_REQ)
+
+
+//2 REG_DW_I2C_IC_CLR_RX_DONE
+#define BIT_IC_CLR_RX_DONE                    	BIT(0)
+#define BIT_SHIFT_IC_CLR_RX_DONE              	0
+#define BIT_MASK_IC_CLR_RX_DONE               	0x1
+#define BIT_CTRL_IC_CLR_RX_DONE(x)            	(((x) & BIT_MASK_IC_CLR_RX_DONE) << BIT_SHIFT_IC_CLR_RX_DONE)
+
+
+//2 REG_DW_I2C_IC_CLR_ACTIVITY
+#define BIT_IC_CLR_ACTIVITY                   	BIT(0)
+#define BIT_SHIFT_IC_CLR_ACTIVITY             	0
+#define BIT_MASK_IC_CLR_ACTIVITY              	0x1
+#define BIT_CTRL_IC_CLR_ACTIVITY(x)           	(((x) & BIT_MASK_IC_CLR_ACTIVITY) << BIT_SHIFT_IC_CLR_ACTIVITY)
+
+
+//2 REG_DW_I2C_IC_CLR_STOP_DET
+#define BIT_IC_CLR_STOP_DET                   	BIT(0)
+#define BIT_SHIFT_IC_CLR_STOP_DET             	0
+#define BIT_MASK_IC_CLR_STOP_DET              	0x1
+#define BIT_CTRL_IC_CLR_STOP_DET(x)           	(((x) & BIT_MASK_IC_CLR_STOP_DET) << BIT_SHIFT_IC_CLR_STOP_DET)
+
+
+//2 REG_DW_I2C_IC_CLR_START_DET
+#define BIT_IC_CLR_START_DET                  	BIT(0)
+#define BIT_SHIFT_IC_CLR_START_DET            	0
+#define BIT_MASK_IC_CLR_START_DET             	0x1
+#define BIT_CTRL_IC_CLR_START_DET(x)          	(((x) & BIT_MASK_IC_CLR_START_DET) << BIT_SHIFT_IC_CLR_START_DET)
+
+
+//2 REG_DW_I2C_IC_CLR_GEN_CALL
+#define BIT_IC_CLR_GEN_CALL                   	BIT(0)
+#define BIT_SHIFT_IC_CLR_GEN_CALL             	0
+#define BIT_MASK_IC_CLR_GEN_CALL              	0x1
+#define BIT_CTRL_IC_CLR_GEN_CALL(x)           	(((x) & BIT_MASK_IC_CLR_GEN_CALL) << BIT_SHIFT_IC_CLR_GEN_CALL)
+
+
+//2 REG_DW_I2C_IC_ENABLE
+#define BIT_IC_ENABLE                         	BIT(0)
+#define BIT_SHIFT_IC_ENABLE                   	0
+#define BIT_MASK_IC_ENABLE                    	0x1
+#define BIT_CTRL_IC_ENABLE(x)                 	(((x) & BIT_MASK_IC_ENABLE) << BIT_SHIFT_IC_ENABLE)
+
+
+//2 REG_DW_I2C_IC_STATUS
+#define BIT_IC_STATUS_SLV_ACTIVITY            	BIT(6)
+#define BIT_SHIFT_IC_STATUS_SLV_ACTIVITY      	6
+#define BIT_MASK_IC_STATUS_SLV_ACTIVITY       	0x1
+#define BIT_CTRL_IC_STATUS_SLV_ACTIVITY(x)    	(((x) & BIT_MASK_IC_STATUS_SLV_ACTIVITY) << BIT_SHIFT_IC_STATUS_SLV_ACTIVITY)
+
+#define BIT_IC_STATUS_MST_ACTIVITY            	BIT(5)
+#define BIT_SHIFT_IC_STATUS_MST_ACTIVITY      	5
+#define BIT_MASK_IC_STATUS_MST_ACTIVITY       	0x1
+#define BIT_CTRL_IC_STATUS_MST_ACTIVITY(x)    	(((x) & BIT_MASK_IC_STATUS_MST_ACTIVITY) << BIT_SHIFT_IC_STATUS_MST_ACTIVITY)
+
+#define BIT_IC_STATUS_RFF                     	BIT(4)
+#define BIT_SHIFT_IC_STATUS_RFF               	4
+#define BIT_MASK_IC_STATUS_RFF                	0x1
+#define BIT_CTRL_IC_STATUS_RFF(x)             	(((x) & BIT_MASK_IC_STATUS_RFF) << BIT_SHIFT_IC_STATUS_RFF)
+
+#define BIT_IC_STATUS_RFNE                    	BIT(3)
+#define BIT_SHIFT_IC_STATUS_RFNE              	3
+#define BIT_MASK_IC_STATUS_RFNE               	0x1
+#define BIT_CTRL_IC_STATUS_RFNE(x)            	(((x) & BIT_MASK_IC_STATUS_RFNE) << BIT_SHIFT_IC_STATUS_RFNE)
+
+#define BIT_IC_STATUS_TFE                     	BIT(2)
+#define BIT_SHIFT_IC_STATUS_TFE               	2
+#define BIT_MASK_IC_STATUS_TFE                	0x1
+#define BIT_CTRL_IC_STATUS_TFE(x)             	(((x) & BIT_MASK_IC_STATUS_TFE) << BIT_SHIFT_IC_STATUS_TFE)
+
+#define BIT_IC_STATUS_TFNF                    	BIT(1)
+#define BIT_SHIFT_IC_STATUS_TFNF              	1
+#define BIT_MASK_IC_STATUS_TFNF               	0x1
+#define BIT_CTRL_IC_STATUS_TFNF(x)            	(((x) & BIT_MASK_IC_STATUS_TFNF) << BIT_SHIFT_IC_STATUS_TFNF)
+
+#define BIT_IC_STATUS_ACTIVITY                	BIT(0)
+#define BIT_SHIFT_IC_STATUS_ACTIVITY          	0
+#define BIT_MASK_IC_STATUS_ACTIVITY           	0x1
+#define BIT_CTRL_IC_STATUS_ACTIVITY(x)        	(((x) & BIT_MASK_IC_STATUS_ACTIVITY) << BIT_SHIFT_IC_STATUS_ACTIVITY)
+
+
+//2 REG_DW_I2C_IC_TXFLR
+
+#define BIT_SHIFT_IC_TXFLR 0
+#define BIT_MASK_IC_TXFLR 0x3f
+#define BIT_IC_TXFLR(x)                       	(((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
+#define BIT_CTRL_IC_TXFLR(x)                  	(((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
+#define BIT_GET_IC_TXFLR(x)                   	(((x) >> BIT_SHIFT_IC_TXFLR) & BIT_MASK_IC_TXFLR)
+
+
+//2 REG_DW_I2C_IC_RXFLR
+
+#define BIT_SHIFT_IC_RXFLR 0
+#define BIT_MASK_IC_RXFLR 0x1f
+#define BIT_IC_RXFLR(x)                       	(((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
+#define BIT_CTRL_IC_RXFLR(x)                  	(((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
+#define BIT_GET_IC_RXFLR(x)                   	(((x) >> BIT_SHIFT_IC_RXFLR) & BIT_MASK_IC_RXFLR)
+
+
+//2 REG_DW_I2C_IC_SDA_HOLD
+
+#define BIT_SHIFT_IC_SDA_HOLD 0
+#define BIT_MASK_IC_SDA_HOLD 0xffff
+#define BIT_IC_SDA_HOLD(x)                    	(((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
+#define BIT_CTRL_IC_SDA_HOLD(x)               	(((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
+#define BIT_GET_IC_SDA_HOLD(x)                	(((x) >> BIT_SHIFT_IC_SDA_HOLD) & BIT_MASK_IC_SDA_HOLD)
+
+
+//2 REG_DW_I2C_IC_TX_ABRT_SOURCE
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 	BIT(15)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX	15
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST	BIT(14)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST	14
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO	BIT(13)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO	13
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO)
+
+#define BIT_IC_TX_ABRT_SOURCE_ARB_LOST        	BIT(12)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST  	12
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST   	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ARB_LOST(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 	BIT(11)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS	11
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT	BIT(10)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT	10
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT	BIT(9)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT	9
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 	BIT(8)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT	8
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET	BIT(7)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET	7
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET  	BIT(6)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET	6
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 	BIT(5)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ	5
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK	BIT(4)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK	4
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK	BIT(3)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK	3
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK	BIT(2)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK	2
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK	BIT(1)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK	1
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK)
+
+#define BIT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK	BIT(0)
+#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK	0
+#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK	0x1
+#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK(x)	(((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK)
+
+
+//2 REG_DW_I2C_IC_SLV_DATA_NACK_ONLY
+#define BIT_IC_SLV_DATA_NACK_ONLY             	BIT(0)
+#define BIT_SHIFT_IC_SLV_DATA_NACK_ONLY       	0
+#define BIT_MASK_IC_SLV_DATA_NACK_ONLY        	0x1
+#define BIT_CTRL_IC_SLV_DATA_NACK_ONLY(x)     	(((x) & BIT_MASK_IC_SLV_DATA_NACK_ONLY) << BIT_SHIFT_IC_SLV_DATA_NACK_ONLY)
+
+
+//2 REG_DW_I2C_IC_DMA_CR
+#define BIT_IC_DMA_CR_TDMAE                   	BIT(1)
+#define BIT_SHIFT_IC_DMA_CR_TDMAE             	1
+#define BIT_MASK_IC_DMA_CR_TDMAE              	0x1
+#define BIT_CTRL_IC_DMA_CR_TDMAE(x)           	(((x) & BIT_MASK_IC_DMA_CR_TDMAE) << BIT_SHIFT_IC_DMA_CR_TDMAE)
+
+#define BIT_IC_DMA_CR_RDMAE                   	BIT(0)
+#define BIT_SHIFT_IC_DMA_CR_RDMAE             	0
+#define BIT_MASK_IC_DMA_CR_RDMAE              	0x1
+#define BIT_CTRL_IC_DMA_CR_RDMAE(x)           	(((x) & BIT_MASK_IC_DMA_CR_RDMAE) << BIT_SHIFT_IC_DMA_CR_RDMAE)
+
+
+//2 REG_DW_I2C_IC_DMA_TDLR
+
+#define BIT_SHIFT_IC_DMA_TDLR_DMATDL 0
+#define BIT_MASK_IC_DMA_TDLR_DMATDL 0x1f
+#define BIT_IC_DMA_TDLR_DMATDL(x)             	(((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
+#define BIT_CTRL_IC_DMA_TDLR_DMATDL(x)        	(((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
+#define BIT_GET_IC_DMA_TDLR_DMATDL(x)         	(((x) >> BIT_SHIFT_IC_DMA_TDLR_DMATDL) & BIT_MASK_IC_DMA_TDLR_DMATDL)
+
+
+//2 REG_DW_I2C_IC_DMA_RDLR
+
+#define BIT_SHIFT_IC_DMA_RDLR_DMARDL 0
+#define BIT_MASK_IC_DMA_RDLR_DMARDL 0xf
+#define BIT_IC_DMA_RDLR_DMARDL(x)             	(((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
+#define BIT_CTRL_IC_DMA_RDLR_DMARDL(x)        	(((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
+#define BIT_GET_IC_DMA_RDLR_DMARDL(x)         	(((x) >> BIT_SHIFT_IC_DMA_RDLR_DMARDL) & BIT_MASK_IC_DMA_RDLR_DMARDL)
+
+
+//2 REG_DW_I2C_IC_SDA_SETUP
+
+#define BIT_SHIFT_IC_SDA_SETUP 0
+#define BIT_MASK_IC_SDA_SETUP 0xff
+#define BIT_IC_SDA_SETUP(x)                   	(((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
+#define BIT_CTRL_IC_SDA_SETUP(x)              	(((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
+#define BIT_GET_IC_SDA_SETUP(x)               	(((x) >> BIT_SHIFT_IC_SDA_SETUP) & BIT_MASK_IC_SDA_SETUP)
+
+
+//2 REG_DW_I2C_IC_ACK_GENERAL_CALL
+#define BIT_IC_ACK_GENERAL_CALL               	BIT(0)
+#define BIT_SHIFT_IC_ACK_GENERAL_CALL         	0
+#define BIT_MASK_IC_ACK_GENERAL_CALL          	0x1
+#define BIT_CTRL_IC_ACK_GENERAL_CALL(x)       	(((x) & BIT_MASK_IC_ACK_GENERAL_CALL) << BIT_SHIFT_IC_ACK_GENERAL_CALL)
+
+
+//2 REG_DW_I2C_IC_ENABLE_STATUS
+#define BIT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 	BIT(2)
+#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST	2
+#define BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST	0x1
+#define BIT_CTRL_IC_ENABLE_STATUS_SLV_RX_DATA_LOST(x)	(((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST)
+
+#define BIT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY	BIT(1)
+#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY	1
+#define BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY	0x1
+#define BIT_CTRL_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY(x)	(((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY)
+
+#define BIT_IC_ENABLE_STATUS_IC_EN            	BIT(0)
+#define BIT_SHIFT_IC_ENABLE_STATUS_IC_EN      	0
+#define BIT_MASK_IC_ENABLE_STATUS_IC_EN       	0x1
+#define BIT_CTRL_IC_ENABLE_STATUS_IC_EN(x)    	(((x) & BIT_MASK_IC_ENABLE_STATUS_IC_EN) << BIT_SHIFT_IC_ENABLE_STATUS_IC_EN)
+
+
+//2 REG_DW_I2C_IC_COMP_PARAM_1
+
+#define BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 16
+#define BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 0xff
+#define BIT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
+#define BIT_CTRL_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
+#define BIT_GET_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x)	(((x) >> BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
+
+
+#define BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 8
+#define BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 0xff
+#define BIT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
+#define BIT_CTRL_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
+#define BIT_GET_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x)	(((x) >> BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
+
+#define BIT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS	BIT(7)
+#define BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS	7
+#define BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS	0x1
+#define BIT_CTRL_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS) << BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS)
+
+#define BIT_IC_COMP_PARAM_1_HAS_DMA           	BIT(6)
+#define BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA     	6
+#define BIT_MASK_IC_COMP_PARAM_1_HAS_DMA      	0x1
+#define BIT_CTRL_IC_COMP_PARAM_1_HAS_DMA(x)   	(((x) & BIT_MASK_IC_COMP_PARAM_1_HAS_DMA) << BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA)
+
+#define BIT_IC_COMP_PARAM_1_INTR_IO           	BIT(5)
+#define BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO     	5
+#define BIT_MASK_IC_COMP_PARAM_1_INTR_IO      	0x1
+#define BIT_CTRL_IC_COMP_PARAM_1_INTR_IO(x)   	(((x) & BIT_MASK_IC_COMP_PARAM_1_INTR_IO) << BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO)
+
+#define BIT_IC_COMP_PARAM_1_HC_COUNT_VALUES   	BIT(4)
+#define BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES	4
+#define BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES	0x1
+#define BIT_CTRL_IC_COMP_PARAM_1_HC_COUNT_VALUES(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES) << BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES)
+
+
+#define BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE 2
+#define BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE 0x3
+#define BIT_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) 	(((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
+#define BIT_CTRL_IC_COMP_PARAM_1_MAX_SPEED_MODE(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
+#define BIT_GET_IC_COMP_PARAM_1_MAX_SPEED_MODE(x)	(((x) >> BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE)
+
+
+#define BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH 0
+#define BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH 0x3
+#define BIT_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) 	(((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
+#define BIT_CTRL_IC_COMP_PARAM_1_APB_DATA_WIDTH(x)	(((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
+#define BIT_GET_IC_COMP_PARAM_1_APB_DATA_WIDTH(x)	(((x) >> BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH)
+
+
+//2 REG_DW_I2C_IC_COMP_VERSION
+
+#define BIT_SHIFT_IC_COMP_VERSION 0
+#define BIT_MASK_IC_COMP_VERSION 0xffffffffL
+#define BIT_IC_COMP_VERSION(x)                	(((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
+#define BIT_CTRL_IC_COMP_VERSION(x)           	(((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
+#define BIT_GET_IC_COMP_VERSION(x)            	(((x) >> BIT_SHIFT_IC_COMP_VERSION) & BIT_MASK_IC_COMP_VERSION)
+
+
+//2 REG_DW_I2C_IC_COMP_TYPE
+
+#define BIT_SHIFT_IC_COMP_TYPE 0
+#define BIT_MASK_IC_COMP_TYPE 0xffffffffL
+#define BIT_IC_COMP_TYPE(x)                   	(((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
+#define BIT_CTRL_IC_COMP_TYPE(x)              	(((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
+#define BIT_GET_IC_COMP_TYPE(x)               	(((x) >> BIT_SHIFT_IC_COMP_TYPE) & BIT_MASK_IC_COMP_TYPE)
+
+//======================== Register Address Definition ========================
+#define REG_DW_I2C_IC_CON 0x0000
+#define REG_DW_I2C_IC_TAR 0x0004
+#define REG_DW_I2C_IC_SAR 0x0008
+#define REG_DW_I2C_IC_HS_MADDR 0x000C
+#define REG_DW_I2C_IC_DATA_CMD 0x0010
+#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014
+#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018
+#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C
+#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020
+#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024
+#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028
+#define REG_DW_I2C_IC_INTR_STAT 0x002C
+#define REG_DW_I2C_IC_INTR_MASK 0x0030
+#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034
+#define REG_DW_I2C_IC_RX_TL 0x0038
+#define REG_DW_I2C_IC_TX_TL 0x003C
+#define REG_DW_I2C_IC_CLR_INTR 0x0040
+#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044
+#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048
+#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C
+#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050
+#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054
+#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058
+#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C
+#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060
+#define REG_DW_I2C_IC_CLR_START_DET 0x0064
+#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068
+#define REG_DW_I2C_IC_ENABLE 0x006C
+#define REG_DW_I2C_IC_STATUS 0x0070
+#define REG_DW_I2C_IC_TXFLR 0x0074
+#define REG_DW_I2C_IC_RXFLR 0x0078
+#define REG_DW_I2C_IC_SDA_HOLD 0x007C
+#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080
+#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084
+#define REG_DW_I2C_IC_DMA_CR 0x0088
+#define REG_DW_I2C_IC_DMA_TDLR 0x008C
+#define REG_DW_I2C_IC_DMA_RDLR 0x0090
+#define REG_DW_I2C_IC_SDA_SETUP 0x0094
+#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098
+#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C
+#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4
+#define REG_DW_I2C_IC_COMP_VERSION 0x00F8
+#define REG_DW_I2C_IC_COMP_TYPE 0x00FC
+
+//======================================================
+// I2C related enumeration
+// I2C Address Mode
+typedef enum _I2C_ADDR_MODE_   {
+    I2C_ADDR_7BIT   =   0,
+    I2C_ADDR_10BIT  =   1,  
+}I2C_ADDR_MODE,*PI2C_ADDR_MODE;
+
+// I2C Speed Mode
+typedef enum _I2C_SPD_MODE_   {
+    I2C_SS_MODE     =   1,
+    I2C_FS_MODE     =   2,
+    I2C_HS_MODE     =   3,
+}I2C_SPD_MODE,*PI2C_SPD_MODE;
+
+//I2C Timing Parameters
+#define I2C_SS_MIN_SCL_HTIME    4000    //the unit is ns.
+#define I2C_SS_MIN_SCL_LTIME    4700    //the unit is ns.
+
+#define I2C_FS_MIN_SCL_HTIME    600     //the unit is ns.
+#define I2C_FS_MIN_SCL_LTIME    1300    //the unit is ns.
+
+#define I2C_HS_MIN_SCL_HTIME_100    60      //the unit is ns, with bus loading = 100pf
+#define I2C_HS_MIN_SCL_LTIME_100    120     //the unit is ns., with bus loading = 100pf
+
+#define I2C_HS_MIN_SCL_HTIME_400    160     //the unit is ns, with bus loading = 400pf
+#define I2C_HS_MIN_SCL_LTIME_400    320     //the unit is ns., with bus loading = 400pf
+
+
+//======================================================
+//I2C Essential functions and macros
+_LONG_CALL_ROM_ VOID HalI2CWrite32(IN u8 I2CIdx, IN u8 I2CReg, IN u32 I2CVal);
+_LONG_CALL_ROM_ u32 HalI2CRead32(IN u8 I2CIdx, IN u8 I2CReg);
+
+#define HAL_I2C_WRITE32(I2CIdx, addr, value)    HalI2CWrite32(I2CIdx,addr,value)
+#define HAL_I2C_READ32(I2CIdx, addr)            HalI2CRead32(I2CIdx,addr)
+
+// Rtl8195a I2C function prototypes
+_LONG_CALL_ HAL_Status HalI2CEnableRtl8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CInit8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CDeInit8195a(IN VOID *Data);
+_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CSendRtl8195a(IN VOID *Data);
+_LONG_CALL_ u8 HalI2CReceiveRtl8195a(IN VOID *Data);
+_LONG_CALL_ROM_ HAL_Status HalI2CIntrCtrl8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CClrIntrRtl8195a(IN VOID *Data);
+_LONG_CALL_ROM_ HAL_Status HalI2CClrAllIntrRtl8195a(IN VOID *Data);
+_LONG_CALL_ HAL_Status HalI2CDMACtrl8195a(IN VOID *Data);
+_LONG_CALL_ u32 HalI2CReadRegRtl8195a(IN VOID *Data, IN u8 I2CReg);
+_LONG_CALL_ HAL_Status HalI2CWriteRegRtl8195a(IN VOID *Data, IN u8 I2CReg, IN u32 RegVal);
+
+//Rtl8195a I2C V02 function prototype
+_LONG_CALL_ HAL_Status HalI2CSendRtl8195aV02(IN  VOID *Data);
+#if  defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
+_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195aV02(IN  VOID *Data);
+#elif defined(CONFIG_CHIP_E_CUT)
+_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195aV02(IN  VOID *Data);
+#endif
+//Rtl8195a I2C V02 function prototype  END
+
+HAL_Status HalI2CInit8195a_Patch(IN VOID *Data);
+HAL_Status HalI2CSendRtl8195a_Patch(IN VOID *Data);
+HAL_Status HalI2CSetCLKRtl8195a_Patch(IN VOID *Data);
+
+#endif

sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2s.h

@@ -0,0 +1,617 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_I2S_H_
+#define _RTL8195A_I2S_H_
+
+
+//=============== Register Bit Field Definition ====================
+// REG_I2S_CONTROL
+#define BIT_CTLX_I2S_EN                         BIT(0)
+#define BIT_SHIFT_CTLX_I2S_EN                   0
+#define BIT_MASK_CTLX_I2S_EN                    0x1
+#define BIT_CTRL_CTLX_I2S_EN(x)                 (((x) & BIT_MASK_CTLX_I2S_EN) << BIT_SHIFT_CTLX_I2S_EN)
+
+#define BIT_SHIFT_CTLX_I2S_TRX_ACT              1
+#define BIT_MASK_CTLX_I2S_TRX_ACT               0x3
+#define BIT_CTRL_CTLX_I2S_TRX_ACT(x)            (((x) & BIT_MASK_CTLX_I2S_TRX_ACT) << BIT_SHIFT_CTLX_I2S_TRX_ACT)
+#define BIT_GET_CTLX_I2S_TRX_ACT(x)             (((x) >> BIT_SHIFT_CTLX_I2S_TRX_ACT) & BIT_MASK_CTLX_I2S_TRX_ACT)
+
+#define BIT_SHIFT_CTLX_I2S_CH_NUM               3
+#define BIT_MASK_CTLX_I2S_CH_NUM                0x3
+#define BIT_CTRL_CTLX_I2S_CH_NUM(x)             (((x) & BIT_MASK_CTLX_I2S_CH_NUM) << BIT_SHIFT_CTLX_I2S_CH_NUM)
+#define BIT_GET_CTLX_I2S_CH_NUM(x)              (((x) >> BIT_SHIFT_CTLX_I2S_CH_NUM) & BIT_MASK_CTLX_I2S_CH_NUM)
+
+#define BIT_CTLX_I2S_WL                         BIT(6)
+#define BIT_SHIFT_CTLX_I2S_WL                   6
+#define BIT_MASK_CTLX_I2S_WL                    0x1
+#define BIT_CTRL_CTLX_I2S_WL(x)                 (((x) & BIT_MASK_CTLX_I2S_WL) << BIT_SHIFT_CTLX_I2S_WL)
+
+#define BIT_CTLX_I2S_LRSWAP                     BIT(10)
+#define BIT_SHIFT_CTLX_I2S_LRSWAP               10
+#define BIT_MASK_CTLX_I2S_LRSWAP                0x1
+#define BIT_CTRL_CTLX_I2S_LRSWAP(x)             (((x) & BIT_MASK_CTLX_I2S_LRSWAP) << BIT_SHIFT_CTLX_I2S_LRSWAP)
+
+#define BIT_CTLX_I2S_SCK_INV                    BIT(11)
+#define BIT_SHIFT_CTLX_I2S_SCK_INV              11
+#define BIT_MASK_CTLX_I2S_SCK_INV               0x1
+#define BIT_CTRL_CTLX_I2S_SCK_INV(x)            (((x) & BIT_MASK_CTLX_I2S_SCK_INV) << BIT_SHIFT_CTLX_I2S_SCK_INV)
+
+#define BIT_CTLX_I2S_ENDIAN_SWAP                BIT(12)
+#define BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP          12
+#define BIT_MASK_CTLX_I2S_ENDIAN_SWAP           0x1
+#define BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(x)        (((x) & BIT_MASK_CTLX_I2S_ENDIAN_SWAP) << BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP)
+
+#define BIT_CTLX_I2S_SLAVE_MODE                 BIT(29)
+#define BIT_SHIFT_CTLX_I2S_SLAVE_MODE           29
+#define BIT_MASK_CTLX_I2S_SLAVE_MODE            0x1
+#define BIT_CTRL_CTLX_I2S_SLAVE_MODE(x)         (((x) & BIT_MASK_CTLX_I2S_SLAVE_MODE) << BIT_SHIFT_CTLX_I2S_SLAVE_MODE)
+
+#define BIT_CTLX_I2S_CLK_SRC                    BIT(30)
+#define BIT_SHIFT_CTLX_I2S_CLK_SRC              30
+#define BIT_MASK_CTLX_I2S_CLK_SRC               0x1
+#define BIT_CTRL_CTLX_I2S_CLK_SRC(x)            (((x) & BIT_MASK_CTLX_I2S_CLK_SRC) << BIT_SHIFT_CTLX_I2S_CLK_SRC)
+
+#define BIT_CTLX_I2S_SW_RSTN                    BIT(31)
+#define BIT_SHIFT_CTLX_I2S_SW_RSTN              31
+#define BIT_MASK_CTLX_I2S_SW_RSTN               0x1
+#define BIT_CTRL_CTLX_I2S_SW_RSTN(x)            (((x) & BIT_MASK_CTLX_I2S_SW_RSTN) << BIT_SHIFT_CTLX_I2S_SW_RSTN)
+
+// REG_I2S_SETTING
+#define BIT_SHIFT_SETTING_I2S_PAGE_SZ           0
+#define BIT_MASK_SETTING_I2S_PAGE_SZ            0xFFF
+#define BIT_CTRL_SETTING_I2S_PAGE_SZ(x)         (((x) & BIT_MASK_SETTING_I2S_PAGE_SZ) << BIT_SHIFT_SETTING_I2S_PAGE_SZ)
+#define BIT_GET_SETTING_I2S_PAGE_SZ(x)          (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_SZ) & BIT_MASK_SETTING_I2S_PAGE_SZ)
+
+#define BIT_SHIFT_SETTING_I2S_PAGE_NUM          12
+#define BIT_MASK_SETTING_I2S_PAGE_NUM           0x3
+#define BIT_CTRL_SETTING_I2S_PAGE_NUM(x)        (((x) & BIT_MASK_SETTING_I2S_PAGE_NUM) << BIT_SHIFT_SETTING_I2S_PAGE_NUM)
+#define BIT_GET_SETTING_I2S_PAGE_NUM(x)         (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_NUM) & BIT_MASK_SETTING_I2S_PAGE_NUM)
+
+#define BIT_SHIFT_SETTING_I2S_SAMPLE_RATE       14
+#define BIT_MASK_SETTING_I2S_SAMPLE_RATE        0x7
+#define BIT_CTRL_SETTING_I2S_SAMPLE_RATE(x)     (((x) & BIT_MASK_SETTING_I2S_SAMPLE_RATE) << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE)
+#define BIT_GET_SETTING_I2S_SAMPLE_RATE(x)      (((x) >> BIT_SHIFT_SETTING_I2S_SAMPLE_RATE) & BIT_MASK_SETTING_I2S_SAMPLE_RATE)
+
+// i2s trx page own bit
+#define BIT_PAGE_I2S_OWN_BIT                    BIT(31)
+#define BIT_SHIFT_PAGE_I2S_OWN_BIT              31
+#define BIT_MASK_PAGE_I2S_OWN_BIT               0x1
+#define BIT_CTRL_PAGE_I2S_OWN_BIT(x)            (((x) & BIT_MASK_PAGE_I2S_OWN_BIT) << BIT_SHIFT_PAGE_I2S_OWN_BIT)
+
+//=============== Register Address Definition ====================
+#define REG_I2S_PAGE_OWN_OFF   0x004
+
+#define REG_I2S_CTL            0x000
+#define REG_I2S_TX_PAGE_PTR    0x004
+#define REG_I2S_RX_PAGE_PTR    0x008
+#define REG_I2S_SETTING        0x00C
+
+#define REG_I2S_TX_MASK_INT    0x010
+#define REG_I2S_TX_STATUS_INT  0x014
+#define REG_I2S_RX_MASK_INT    0x018
+#define REG_I2S_RX_STATUS_INT  0x01c
+
+
+#define REG_I2S_TX_PAGE0_OWN   0x020
+#define REG_I2S_TX_PAGE1_OWN   0x024
+#define REG_I2S_TX_PAGE2_OWN   0x028
+#define REG_I2S_TX_PAGE3_OWN   0x02C
+#define REG_I2S_RX_PAGE0_OWN   0x030
+#define REG_I2S_RX_PAGE1_OWN   0x034
+#define REG_I2S_RX_PAGE2_OWN   0x038
+#define REG_I2S_RX_PAGE3_OWN   0x03C
+
+/*I2S Essential Functions and Macros*/
+VOID
+HalI2SWrite32(
+    IN  u8      I2SIdx,
+    IN  u8      I2SReg,
+    IN  u32     I2SVal
+);
+
+u32
+HalI2SRead32(
+    IN  u8      I2SIdx,
+    IN  u8      I2SReg
+);
+
+/*
+#define HAL_I2SX_READ32(I2sIndex, addr)     \
+                HAL_READ32(I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF), addr)
+#define HAL_I2SX_WRITE32(I2sIndex, addr, value)     \
+                HAL_WRITE32((I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF)), addr, value)
+*/
+
+#define HAL_I2S_WRITE32(I2SIdx, addr, value)    HalI2SWrite32(I2SIdx,addr,value)
+#define HAL_I2S_READ32(I2SIdx, addr)            HalI2SRead32(I2SIdx,addr)
+
+/* I2S debug output*/
+#define I2S_PREFIX      "RTL8195A[i2s]: "
+#define I2S_PREFIX_LVL  "    [i2s_DBG]: "
+
+typedef enum _I2S_DBG_LVL_ {
+    HAL_I2S_LVL         =   0x01,
+    SAL_I2S_LVL         =   0x02,
+    VERI_I2S_LVL        =   0x03,
+}I2S_DBG_LVL,*PI2S_DBG_LVL;
+
+#ifdef CONFIG_DEBUG_LOG
+#ifdef CONFIG_DEBUG_LOG_I2S_HAL
+
+    #define DBG_8195A_I2S(...)  do{ \
+        _DbgDump("\r"I2S_PREFIX __VA_ARGS__);\
+    }while(0)
+
+
+    #define I2SDBGLVL   0xFF   
+    #define DBG_8195A_I2S_LVL(LVL,...)  do{\
+            if (LVL&I2SDBGLVL){\
+                _DbgDump("\r"I2S_PREFIX_LVL __VA_ARGS__);\
+            }\
+    }while(0)
+#else
+    #define DBG_I2S_LOG_PERD    100
+    #define DBG_8195A_I2S(...)
+    #define DBG_8195A_I2S_LVL(...)
+#endif
+#else
+    #define DBG_I2S_LOG_PERD    100
+    #define DBG_8195A_I2S(...)
+    #define DBG_8195A_I2S_LVL(...)
+#endif
+
+/*
+#define REG_I2S_PAGE_OWN_OFF   0x004
+#define REG_I2S_CTL            0x000
+#define REG_I2S_TX_PAGE_PTR    0x004
+#define REG_I2S_RX_PAGE_PTR    0x008
+#define REG_I2S_SETTING        0x00C
+
+#define REG_I2S_TX_MASK_INT    0x010
+#define REG_I2S_TX_STATUS_INT  0x014
+#define REG_I2S_RX_MASK_INT    0x018
+#define REG_I2S_RX_STATUS_INT  0x01c
+
+
+
+#define REG_I2S_TX_PAGE0_OWN   0x020
+#define REG_I2S_TX_PAGE1_OWN   0x024
+#define REG_I2S_TX_PAGE2_OWN   0x028
+#define REG_I2S_TX_PAGE3_OWN   0x02C
+#define REG_I2S_RX_PAGE0_OWN   0x030
+#define REG_I2S_RX_PAGE1_OWN   0x034
+#define REG_I2S_RX_PAGE2_OWN   0x038
+#define REG_I2S_RX_PAGE3_OWN   0x03C
+*/
+/* template 
+#define BIT_SHIFT_CTLX_ 7
+#define BIT_MASK_CTLX_  0x1
+#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_)
+#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_))
+*//*
+#define BIT_SHIFT_CTLX_IIS_EN 0
+#define BIT_MASK_CTLX_IIS_EN  0x1
+#define BIT_CTLX_IIS_EN(x) (((x) & BIT_MASK_CTLX_IIS_EN) << BIT_SHIFT_CTLX_IIS_EN)
+#define BIT_INV_CTLX_IIS_EN (~(BIT_MASK_CTLX_IIS_EN << BIT_SHIFT_CTLX_IIS_EN))
+
+#define BIT_SHIFT_CTLX_TRX 1
+#define BIT_MASK_CTLX_TRX 0x3
+#define BIT_CTLX_TRX(x) (((x) & BIT_MASK_CTLX_TRX) << BIT_SHIFT_CTLX_TRX)
+#define BIT_INV_CTLX_TRX (~(BIT_MASK_CTLX_TRX << BIT_SHIFT_CTLX_TRX))
+
+#define BIT_SHIFT_CTLX_CH_NUM 3
+#define BIT_MASK_CTLX_CH_NUM  0x3
+#define BIT_CTLX_CH_NUM(x) (((x) & BIT_MASK_CTLX_CH_NUM) << BIT_SHIFT_CTLX_CH_NUM)
+#define BIT_INV_CTLX_CH_NUM (~(BIT_MASK_CTLX_CH_NUM << BIT_SHIFT_CTLX_CH_NUM))
+
+#define BIT_SHIFT_CTLX_EDGE_SW 5
+#define BIT_MASK_CTLX_EDGE_SW  0x1
+#define BIT_CTLX_EDGE_SW(x) (((x) & BIT_MASK_CTLX_EDGE_SW) << BIT_SHIFT_CTLX_EDGE_SW)
+#define BIT_INV_CTLX_EDGE_SW (~(BIT_MASK_CTLX_EDGE_SW << BIT_SHIFT_CTLX_EDGE_SW))
+
+#define BIT_SHIFT_CTLX_WL 6
+#define BIT_MASK_CTLX_WL  0x1
+#define BIT_CTLX_WL(x) (((x) & BIT_MASK_CTLX_WL) << BIT_SHIFT_CTLX_WL)
+#define BIT_INV_CTLX_WL (~(BIT_MASK_CTLX_WL << BIT_SHIFT_CTLX_WL))
+
+#define BIT_SHIFT_CTLX_LOOP_BACK 7
+#define BIT_MASK_CTLX_LOOP_BACK  0x1
+#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK)
+#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK))
+
+
+#define BIT_SHIFT_CTLX_FORMAT 8
+#define BIT_MASK_CTLX_FORMAT  0x3
+#define BIT_CTLX_FORMAT(x) (((x) & BIT_MASK_CTLX_FORMAT) << BIT_SHIFT_CTLX_FORMAT)
+#define BIT_INV_CTLX_FORMAT (~(BIT_MASK_CTLX_FORMAT << BIT_SHIFT_CTLX_FORMAT))
+
+#define BIT_SHIFT_CTLX_LRSWAP 10
+#define BIT_MASK_CTLX_LRSWAP  0x1
+#define BIT_CTLX_LRSWAP(x) (((x) & BIT_MASK_CTLX_LRSWAP) << BIT_SHIFT_CTLX_LRSWAP)
+#define BIT_INV_CTLX_LRSWAP (~(BIT_MASK_CTLX_LRSWAP << BIT_SHIFT_CTLX_LRSWAP))
+
+#define BIT_SHIFT_CTLX_SCK_INV 11
+#define BIT_MASK_CTLX_SCK_INV  0x1
+#define BIT_CTLX_SCK_INV(x) (((x) & BIT_MASK_CTLX_SCK_INV) << BIT_SHIFT_CTLX_SCK_INV)
+#define BIT_INV_CTLX_SCK_INV (~(BIT_MASK_CTLX_SCK_INV << BIT_SHIFT_CTLX_SCK_INV))
+
+#define BIT_SHIFT_CTLX_ENDIAN_SWAP 12
+#define BIT_MASK_CTLX_ENDIAN_SWAP  0x1
+#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP)
+#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP))
+
+
+#define BIT_SHIFT_CTLX_DEBUG_SWITCH 15
+#define BIT_MASK_CTLX_DEBUG_SWITCH  0x3
+#define BIT_CTLX_DEBUG_SWITCH(x) (((x) & BIT_MASK_CTLX_DEBUG_SWITCH) << BIT_SHIFT_CTLX_DEBUG_SWITCH)
+#define BIT_INV_CTLX_DEBUG_SWITCH (~(BIT_MASK_CTLX_DEBUG_SWITCH << BIT_SHIFT_CTLX_DEBUG_SWITCH))
+
+#define BIT_SHIFT_CTLX_SLAVE_SEL 29
+#define BIT_MASK_CTLX_SLAVE_SEL  0x1
+#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL)
+#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL))
+
+
+#define BIT_SHIFT_CTLX_CLK_SRC 30
+#define BIT_MASK_CTLX_CLK_SRC  0x1
+#define BIT_CTLX_CLK_SRC(x) (((x) & BIT_MASK_CTLX_CLK_SRC) << BIT_SHIFT_CTLX_CLK_SRC)
+#define BIT_INV_CTLX_CLK_SRC (~(BIT_MASK_CTLX_CLK_SRC << BIT_SHIFT_CTLX_CLK_SRC))
+
+
+
+#define BIT_SHIFT_CTLX_SW_RSTN 31
+#define BIT_MASK_CTLX_SW_RSTN  0x1
+#define BIT_CTLX_SW_RSTN(x) (((x) & BIT_MASK_CTLX_SW_RSTN) << BIT_SHIFT_CTLX_SW_RSTN)
+#define BIT_INV_CTLX_SW_RSTN (~(BIT_MASK_CTLX_SW_RSTN << BIT_SHIFT_CTLX_SW_RSTN))
+
+
+#define BIT_SHIFT_SETTING_PAGE_SZ 0
+#define BIT_MASK_SETTING_PAGE_SZ  0xFFF
+#define BIT_SETTING_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_PAGE_SZ) << BIT_SHIFT_SETTING_PAGE_SZ)
+#define BIT_INV_SETTING_PAGE_SZ (~(BIT_MASK_SETTING_PAGE_SZ << BIT_SHIFT_SETTING_PAGE_SZ))
+
+#define BIT_SHIFT_SETTING_PAGE_NUM 12
+#define BIT_MASK_SETTING_PAGE_NUM  0x3
+#define BIT_SETTING_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_PAGE_NUM) << BIT_SHIFT_SETTING_PAGE_NUM)
+#define BIT_INV_SETTING_PAGE_NUM (~(BIT_MASK_SETTING_PAGE_NUM << BIT_SHIFT_SETTING_PAGE_NUM))
+
+#define BIT_SHIFT_SETTING_SAMPLE_RATE 14
+#define BIT_MASK_SETTING_SAMPLE_RATE  0x7
+#define BIT_SETTING_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_SAMPLE_RATE) << BIT_SHIFT_SETTING_SAMPLE_RATE)
+#define BIT_INV_SETTING_SAMPLE_RATE (~(BIT_MASK_SETTING_SAMPLE_RATE << BIT_SHIFT_SETTING_SAMPLE_RATE))
+*/
+
+typedef enum _I2S_CTL_FORMAT {
+    FormatI2s             = 0x00,
+    FormatLeftJustified   = 0x01,
+    FormatRightJustified  = 0x02
+}I2S_CTL_FORMAT, *PI2S_CTL_FORMAT;
+
+typedef enum _I2S_CTL_CHNUM {
+    ChannelStereo      = 0x00,
+    Channel5p1         = 0x01,
+    ChannelMono        = 0x02
+}I2S_CTL_CHNUM, *PI2S_CTL_CHNUM;
+
+typedef enum _I2S_CTL_TRX_ACT {
+    RxOnly             = 0x00,
+    TxOnly             = 0x01,
+    TXRX               = 0x02
+}I2S_CTL_TRX_ACT, *PI2S_CTL_TRX_ACT;
+/*
+typedef struct _I2S_CTL_REG_ {
+    I2S_CTL_FORMAT         Format;
+    I2S_CTL_CHNUM          ChNum;
+    I2S_CTL_TRX_ACT        TrxAct;
+
+    u32                    I2s_En         :1; // Bit 0
+    u32                    Rsvd1to4       :4; // Bit 1-4 is TrxAct, ChNum
+    u32                    EdgeSw         :1; // Bit 5 Edge switch
+    u32                    WordLength     :1; // Bit 6
+    u32                    LoopBack       :1; // Bit 7
+    u32                    Rsvd8to9       :2; // Bit 8-9 is Format
+    u32                    DacLrSwap      :1; // Bit 10
+    u32                    SckInv         :1; // Bit 11
+    u32                    EndianSwap     :1; // Bit 12
+    u32                    Rsvd13to14     :2; // Bit 11-14
+    u32                    DebugSwitch    :2; // Bit 15-16
+    u32                    Rsvd17to28    :12; // Bit 17-28
+    u32                    SlaveMode      :1; // Bit 29
+    u32                    SR44p1KHz      :1; // Bit 30
+    u32                    SwRstn         :1; // Bit 31
+} I2S_CTL_REG, *PI2S_CTL_REG;
+*/
+typedef enum _I2S_SETTING_PAGE_NUM {
+    I2s1Page           = 0x00,
+    I2s2Page           = 0x01,
+    I2s3Page           = 0x02,
+    I2s4Page           = 0x03
+}I2S_SETTING_PAGE_NUM, *PI2S_SETTING_PAGE_NUM;
+
+//sampling rate
+typedef enum _I2S_SETTING_SR {
+    I2sSR8K            = 0x00,
+    I2sSR16K           = 0x01,
+    I2sSR24K           = 0x02,
+    I2sSR32K           = 0x03,
+    I2sSR48K           = 0x05,
+    I2sSR44p1K         = 0x15,
+    I2sSR96K           = 0x06,
+    I2sSR88p2K         = 0x16
+}I2S_SETTING_SR, *PI2S_SETTING_SR;
+/*
+typedef struct _I2S_SETTING_REG_ {
+    I2S_SETTING_PAGE_NUM     PageNum;
+    I2S_SETTING_SR           SampleRate;
+
+    u32                      PageSize:12; // Bit 0-11
+}I2S_SETTING_REG, *PI2S_SETTING_REG;
+
+typedef enum _I2S_TX_ISR {
+    I2sTxP0OK          = 0x01,
+    I2sTxP1OK          = 0x02,
+    I2sTxP2OK          = 0x04,
+    I2sTxP3OK          = 0x08,
+    I2sTxPageUn        = 0x10,
+    I2sTxFifoEmpty     = 0x20
+}I2S_TX_ISR, *PI2S_TX_ISR;
+
+typedef enum _I2S_RX_ISR {
+    I2sRxP0OK          = 0x01,
+    I2sRxP1OK          = 0x02,
+    I2sRxP2OK          = 0x04,
+    I2sRxP3OK          = 0x08,
+    I2sRxPageUn        = 0x10,
+    I2sRxFifoFull      = 0x20
+}I2S_RX_ISR, *PI2S_RX_ISR;
+*/
+
+/* Hal I2S function prototype*/
+RTK_STATUS
+HalI2SInitRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SInitRtl8195a_Patch(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SDeInitRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2STxRtl8195a(
+    IN  VOID    *Data,
+	IN  u8      *pBuff
+);
+
+RTK_STATUS
+HalI2SRxRtl8195a(
+    IN  VOID    *Data,
+	OUT u8      *pBuff
+);
+
+RTK_STATUS
+HalI2SEnableRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SIntrCtrlRtl8195a(
+    IN  VOID    *Data
+);
+
+u32
+HalI2SReadRegRtl8195a(
+    IN  VOID    *Data,
+    IN  u8      I2SReg
+);
+
+RTK_STATUS
+HalI2SSetRateRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SSetWordLenRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SSetChNumRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SSetPageNumRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SSetPageSizeRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SSetDirectionRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SSetDMABufRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SClrIntrRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SClrAllIntrRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SDMACtrlRtl8195a(
+    IN  VOID    *Data
+);
+
+u8
+HalI2SGetTxPageRtl8195a(
+    IN  VOID    *Data
+);
+
+u8
+HalI2SGetRxPageRtl8195a(
+    IN  VOID    *Data
+);
+
+RTK_STATUS
+HalI2SPageSendRtl8195a(
+    IN  VOID    *Data,
+	IN  u8      PageIdx
+);
+
+#if 0
+RTK_STATUS
+HalI2SPageRecvRtl8195a(
+    IN  VOID    *Data,
+	IN u8      PageIdx
+);
+#else
+RTK_STATUS
+HalI2SPageRecvRtl8195a(
+    IN  VOID    *Data
+);
+#endif
+
+RTK_STATUS
+HalI2SClearAllOwnBitRtl8195a(
+    IN  VOID    *Data
+);
+
+
+// HAL functions Wrapper
+static __inline VOID
+HalI2SSetRate(
+    IN  VOID    *Data
+)
+{
+    HalI2SSetRateRtl8195a(Data);
+}
+
+static __inline VOID
+HalI2SSetWordLen(
+    IN  VOID    *Data
+)
+{
+    HalI2SSetWordLenRtl8195a(Data);
+}
+
+static __inline VOID
+HalI2SSetChNum(
+    IN  VOID    *Data
+)
+{
+    HalI2SSetChNumRtl8195a(Data);
+}
+
+static __inline VOID
+HalI2SSetPageNum(
+    IN  VOID    *Data
+)
+{
+    HalI2SSetPageNumRtl8195a(Data);
+}
+
+static __inline VOID
+HalI2SSetPageSize(
+    IN  VOID    *Data
+)
+{
+    HalI2SSetPageSizeRtl8195a(Data);
+}
+
+static __inline VOID
+HalI2SSetDirection(
+    IN  VOID    *Data
+)
+{
+    HalI2SSetDirectionRtl8195a(Data);
+}
+
+static __inline VOID
+HalI2SSetDMABuf(
+    IN  VOID    *Data
+)
+{
+    HalI2SSetDMABufRtl8195a(Data);
+}
+
+static __inline u8
+HalI2SGetTxPage(
+    IN  VOID    *Data
+)
+{
+    return HalI2SGetTxPageRtl8195a(Data);
+}
+
+static __inline u8
+HalI2SGetRxPage(
+    IN  VOID    *Data
+)
+{
+    return HalI2SGetRxPageRtl8195a(Data);
+}
+
+static __inline VOID
+HalI2SPageSend(
+    IN  VOID    *Data,
+	IN  u8      PageIdx
+)
+{
+    HalI2SPageSendRtl8195a(Data, PageIdx);
+}
+
+#if 0
+static __inline VOID
+HalI2SPageRecv(
+    IN  VOID    *Data,
+	IN u8      PageIdx
+)
+{
+    HalI2SPageRecvRtl8195a(Data, PageIdx);
+}
+#else
+static __inline VOID
+HalI2SPageRecv(
+    IN  VOID    *Data
+)
+{
+    HalI2SPageRecvRtl8195a(Data);
+}
+#endif
+
+static __inline VOID
+HalI2SClearAllOwnBit(
+    IN  VOID    *Data
+)
+{
+    HalI2SClearAllOwnBitRtl8195a(Data);
+}
+
+#endif /* _RTL8195A_I2S_H_ */
+
+

sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_nfc.h

@@ -0,0 +1,155 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_NFC_H_
+#define _RTL8195A_NFC_H_
+
+#include "hal_api.h"
+//#include "osdep_api.h"
+#ifdef CONFIG_NFC_VERIFY
+#include "../test/nfc/rtl8195a_nfc_test.h"
+#endif
+
+#if CONFIG_NFC_NORMAL
+//===================== Register Bit Field Definition =====================
+// TODO:
+//===================== Register Address Definition =====================
+//TODO:
+//#include "osdep_api.h"
+#define N2A_Q_LENGTH 10
+#define N2ARLENGTH    4
+//#define NFCTAGLENGTH 36 // maximum 36*4=144 bytes
+#define NFCTAG_BASE  0x7F000
+#define NFCTAG_PAGESIZE 256
+#define NFCTAG_MAXPAGEIDX 16//(4*(1024/NFCTAG_PAGESIZE))
+#define A2NWCLENGTH    4
+
+#define FLASHAPPLENGTH 31
+#define FLASHAPP_BASE  0x7E000
+#define FLASH_PAGESIZE 128
+#define FLASH_MAXPAGEIDX 32//(4*(1024/FLASH_PAGESIZE))
+
+typedef struct _A2N_CATCH_W_ {
+    //u8          Vaild;
+    u8          A2NCatchRPage;
+    u32         A2NCatchWData[A2NWCLENGTH];
+}A2N_CATCH_W_QUEUE, *PA2N_CATCH_W_QUEUE;
+
+typedef struct _A2N_MAILBOX_Q_ {
+    u8          Length;
+    u8          Response;
+    u32         Content[A2NWCLENGTH+1];
+}A2N_MAILBOX_Q,*PA2N_MAILBOX_Q;
+
+typedef struct _N2A_CATCH_R_ {
+    u8          Vaild;
+    u8          N2ACatchRPage;
+    u32         N2ACatchRData[N2ARLENGTH];
+}N2A_CATCH_R_QUEUE, *PN2A_CATCH_R_QUEUE;
+
+
+typedef struct _N2A_R_ {
+    u8          Vaild;
+    u8          N2ARPage;
+}N2A_R_QUEUE, *PN2A_R_QUEUE;
+
+typedef struct _N2A_W_ {
+    u8          Vaild;
+    u8          N2AWPage;
+    u32         N2AWData;
+}N2A_W_QUEUE, *PN2A_W_QUEUE;
+
+typedef struct _NFC_ADAPTER_ {
+    u8          Function;
+    u32         NFCIsr;
+    u8          N2ABoxOpen;
+    u8          A2NSeq;
+    //u8          NFCTagFlashWIdx;
+    //u8          NFCTagFlashRIdx;
+//    u32         NFCTag[NFCTAGLENGTH];
+#if !TASK_SCHEDULER_DISABLED
+    void *      VeriSema;
+#else
+    u32         VeriSema;
+#endif  
+#ifdef PLATFORM_FREERTOS
+    void *      NFCTask;
+#else
+    u32         NFCTask;
+#endif
+#ifdef CONFIG_NFC_VERIFY
+    //N2A Write Tag
+    u8          N2AWQRIdx;
+    u8          N2AWQWIdx;
+    N2A_W_QUEUE N2AWQ[N2A_Q_LENGTH];
+    //N2A Read Tag
+    u8          N2ARQRIdx;
+    u8          N2ARQWIdx;
+    N2A_R_QUEUE N2ARQ[N2A_Q_LENGTH];
+    //N2A Read Catch
+    u8          N2ARCRIdx;
+    u8          N2ARCWIdx;
+    N2A_CATCH_R_QUEUE N2ACatchR[N2A_Q_LENGTH];
+#endif
+    //A2N Write Catch
+    //u8          A2NWCRIdx;
+    //u8          A2NWCWIdx;
+    //A2N_CATCH_W_QUEUE A2NCatchW[N2A_Q_LENGTH];
+
+    //A2N Write mailbox queue
+    u8          A2NWMailBox;
+    u8          A2NWQRIdx;
+    u8          A2NWQWIdx;          
+    A2N_MAILBOX_Q A2NMAILQ[N2A_Q_LENGTH];
+
+    u8          TaskStop;
+    void        *nfc_obj;
+}NFC_ADAPTER, *PNFC_ADAPTER;
+
+typedef enum _N2A_CMD_ {
+    TAG_READ            = 0,
+    TAG_WRITE           = 1,
+    CATCH_READ_DATA     = 2,
+    NFC_R_PRESENT       = 4,
+    N2A_MAILBOX_STATE   = 5,
+    EXT_CLK_REQ         = 6,
+    MAX_N2ACMD
+} N2A_CMD, *PN2A_CMD;
+
+typedef enum _A2N_CMD_ {
+    TAG_READ_DATA       = 0,
+    CATCH_READ          = 2,
+    CATCH_WRITE         = 3,
+    A2N_MAILBOX_STATE   = 4,
+    CONFIRM_N2A_BOX_STATE = 5,
+    EXT_CLK_RSP         = 6,
+    MAX_A2NCMD
+} A2N_CMD, *PA2N_CMD;
+
+// Callback event defination
+typedef enum _NFC_HAL_EVENT_ {
+    NFC_HAL_READER_PRESENT = (1<<0),
+    NFC_HAL_READ = (1<<1),
+    NFC_HAL_WRITE = (1<<2),
+    NFC_HAL_ERR = (1<<3),
+    NFC_HAL_CACHE_RD = (1<<4)    
+}NFC_CB_EVENT, *PNFC_CB_EVENT;
+
+VOID A2NWriteCatch(IN VOID *pNFCAdapte, IN u8 N2AWPage,
+    IN u8 Length, IN u32 *WData);
+VOID A2NReadCatch(IN VOID *pNFCAdapte, IN u8   A2NRPage);
+VOID HalNFCDmemInit(IN u32 *pTagData, IN u32 TagLen);
+VOID HalNFCInit(PNFC_ADAPTER pNFCAdp);
+VOID HalNFCDeinit(PNFC_ADAPTER pNFCAdp);
+VOID HalNFCFwDownload(VOID);
+u32 HalNFCDbgRead32(IN  u32 Addr);
+VOID HalNFCDbgWrite32(IN  u32 Addr, IN  u32 Data);
+#endif  //CONFIG_NFC_NORMAL
+#endif  // #ifndef _RTL8195A_NFC_H_

sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_pwm.h

@@ -0,0 +1,37 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_PWM_H_
+#define _RTL8195A_PWM_H_
+
+extern void
+HAL_Pwm_SetDuty_8195a(
+    HAL_PWM_ADAPTER *pPwmAdapt,
+    u32 period,
+    u32 pulse_width
+);
+
+extern HAL_Status 
+HAL_Pwm_Init_8195a(
+    HAL_PWM_ADAPTER *pPwmAdapt
+);
+
+extern void 
+HAL_Pwm_Enable_8195a(
+    HAL_PWM_ADAPTER *pPwmAdapt
+);
+
+extern void 
+HAL_Pwm_Disable_8195a(
+    HAL_PWM_ADAPTER *pPwmAdapt
+);
+
+
+#endif

sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_ssi.h

@@ -0,0 +1,498 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _RTL8195A_SSI_H_
+#define _RTL8195A_SSI_H_
+
+#define SSI_DUMMY_DATA      0x00        // for master mode, we need to push a Dummy data to TX FIFO for read
+
+#define SSI_CLK_SPI1        (PLATFORM_CLOCK/2)
+#define SSI_CLK_SPI0_2      (PLATFORM_CLOCK/4)
+
+/* Parameters of DW_apb_ssi for RTL8195A */
+#define SSI_TX_FIFO_DEPTH  64
+#define TX_ABW              6  // 1-8, log2(SSI_TX_FIFO_DEPTH)
+#define SSI_RX_FIFO_DEPTH  64
+#define RX_ABW              6  // 1-8, log2(SSI_RX_FIFO_DEPTH)
+
+#define SSI0_REG_BASE  0x40042000
+#define SSI1_REG_BASE  0x40042400
+#define SSI2_REG_BASE  0x40042800
+
+/* Memory Map of DW_apb_ssi */
+#define REG_DW_SSI_CTRLR0          0x00  // 16 bits
+#define REG_DW_SSI_CTRLR1          0x04  // 16 bits
+#define REG_DW_SSI_SSIENR          0x08  //  1 bit
+#define REG_DW_SSI_MWCR            0x0C  //  3 bits
+#define REG_DW_SSI_SER             0x10  //
+#define REG_DW_SSI_BAUDR           0x14  // 16 bits
+#define REG_DW_SSI_TXFTLR          0x18  //  TX_ABW
+#define REG_DW_SSI_RXFTLR          0x1C  //  RX_ABW
+#define REG_DW_SSI_TXFLR           0x20  //
+#define REG_DW_SSI_RXFLR           0x24  //
+#define REG_DW_SSI_SR              0x28  //  7 bits
+#define REG_DW_SSI_IMR             0x2C  //
+#define REG_DW_SSI_ISR             0x30  //  6 bits
+#define REG_DW_SSI_RISR            0x34  //  6 bits
+#define REG_DW_SSI_TXOICR          0x38  //  1 bits
+#define REG_DW_SSI_RXOICR          0x3C  //  1 bits
+#define REG_DW_SSI_RXUICR          0x40  //  1 bits
+#define REG_DW_SSI_MSTICR          0x44  //  1 bits
+#define REG_DW_SSI_ICR             0x48  //  1 bits
+#define REG_DW_SSI_DMACR           0x4C  //  2 bits
+#define REG_DW_SSI_DMATDLR         0x50  //  TX_ABW
+#define REG_DW_SSI_DMARDLR         0x54  //  RX_ABW
+#define REG_DW_SSI_IDR             0x58  // 32 bits
+#define REG_DW_SSI_COMP_VERSION    0x5C  // 32 bits
+#define REG_DW_SSI_DR              0x60  // 16 bits 0x60-0xEC
+#define REG_DW_SSI_RX_SAMPLE_DLY   0xF0  //  8 bits
+#define REG_DW_SSI_RSVD_0          0xF4  // 32 bits
+#define REG_DW_SSI_RSVD_1          0xF8  // 32 bits
+#define REG_DW_SSI_RSVD_2          0xFC  // 32 bits
+
+// CTRLR0          0x00  // 16 bits, 6.2.1
+// DFS Reset Value: 0x7
+#define BIT_SHIFT_CTRLR0_DFS       0
+#define BIT_MASK_CTRLR0_DFS        0xF
+#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS)
+#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS))
+
+#define BIT_SHIFT_CTRLR0_FRF       4
+#define BIT_MASK_CTRLR0_FRF        0x3
+#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF)
+#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF))
+
+#define BIT_SHIFT_CTRLR0_SCPH      6
+#define BIT_MASK_CTRLR0_SCPH       0x1
+#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH)
+#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH))
+
+#define BIT_SHIFT_CTRLR0_SCPOL     7
+#define BIT_MASK_CTRLR0_SCPOL      0x1
+#define BIT_CTRLR0_SCPOL(x)(((x) & BIT_MASK_CTRLR0_SCPOL) << BIT_SHIFT_CTRLR0_SCPOL)
+#define BIT_INVC_CTRLR0_SCPOL (~(BIT_MASK_CTRLR0_SCPOL << BIT_SHIFT_CTRLR0_SCPOL))
+
+#define BIT_SHIFT_CTRLR0_TMOD      8
+#define BIT_MASK_CTRLR0_TMOD       0x3
+#define BIT_CTRLR0_TMOD(x)(((x) & BIT_MASK_CTRLR0_TMOD) << BIT_SHIFT_CTRLR0_TMOD)
+#define BIT_INVC_CTRLR0_TMOD (~(BIT_MASK_CTRLR0_TMOD << BIT_SHIFT_CTRLR0_TMOD))
+
+#define BIT_SHIFT_CTRLR0_SLV_OE    10
+#define BIT_MASK_CTRLR0_SLV_OE     0x1
+#define BIT_CTRLR0_SLV_OE(x)(((x) & BIT_MASK_CTRLR0_SLV_OE) << BIT_SHIFT_CTRLR0_SLV_OE)
+#define BIT_INVC_CTRLR0_SLV_OE (~(BIT_MASK_CTRLR0_SLV_OE << BIT_SHIFT_CTRLR0_SLV_OE))
+
+#define BIT_SHIFT_CTRLR0_SRL       11
+#define BIT_MASK_CTRLR0_SRL        0x1
+#define BIT_CTRLR0_SRL(x)(((x) & BIT_MASK_CTRLR0_SRL) << BIT_SHIFT_CTRLR0_SRL)
+#define BIT_INVC_CTRLR0_SRL (~(BIT_MASK_CTRLR0_SRL << BIT_SHIFT_CTRLR0_SRL))
+
+#define BIT_SHIFT_CTRLR0_CFS       12
+#define BIT_MASK_CTRLR0_CFS        0xF
+#define BIT_CTRLR0_CFS(x)(((x) & BIT_MASK_CTRLR0_CFS) << BIT_SHIFT_CTRLR0_CFS)
+#define BIT_INVC_CTRLR0_CFS (~(BIT_MASK_CTRLR0_CFS << BIT_SHIFT_CTRLR0_CFS))
+
+// CTRLR1          0x04  // 16 bits
+#define BIT_SHIFT_CTRLR1_NDF    0
+#define BIT_MASK_CTRLR1_NDF     0xFFFF
+#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF)
+#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF))
+
+// SSIENR          0x08  //  1 bit
+#define BIT_SHIFT_SSIENR_SSI_EN    0
+#define BIT_MASK_SSIENR_SSI_EN     0x1
+#define BIT_SSIENR_SSI_EN(x)(((x) & BIT_MASK_SSIENR_SSI_EN) << BIT_SHIFT_SSIENR_SSI_EN)
+#define BIT_INVC_SSIENR_SSI_EN (~(BIT_MASK_SSIENR_SSI_EN << BIT_SHIFT_SSIENR_SSI_EN))
+
+// MWCR            0x0c  //  3 bits
+#define BIT_SHIFT_MWCR_MWMOD    0
+#define BIT_MASK_MWCR_MWMOD     0x1
+#define BIT_MWCR_MWMOD(x)(((x) & BIT_MASK_MWCR_MWMOD) << BIT_SHIFT_MWCR_MWMOD)
+#define BIT_INVC_MWCR_MWMOD (~(BIT_MASK_MWCR_MWMOD << BIT_SHIFT_MWCR_MWMOD))
+
+#define BIT_SHIFT_MWCR_MDD      1
+#define BIT_MASK_MWCR_MDD       0x1
+#define BIT_MWCR_MDD(x)(((x) & BIT_MASK_MWCR_MDD) << BIT_SHIFT_MWCR_MDD)
+#define BIT_INVC_MWCR_MDD (~(BIT_MASK_MWCR_MDD << BIT_SHIFT_MWCR_MDD))
+
+#define BIT_SHIFT_MWCR_MHS      2
+#define BIT_MASK_MWCR_MHS       0x1
+#define BIT_MWCR_MHS(x)(((x) & BIT_MASK_MWCR_MHS) << BIT_SHIFT_MWCR_MHS)
+#define BIT_INVC_MWCR_MHS (~(BIT_MASK_MWCR_MHS << BIT_SHIFT_MWCR_MHS))
+
+// SER             0x10   // Variable Length
+#define BIT_SHIFT_SER_SER    0
+#define BIT_MASK_SER_SER     0xFF
+#define BIT_SER_SER(x)(((x) & BIT_MASK_SER_SER) << BIT_SHIFT_SER_SER)
+#define BIT_INVC_SER_SER (~(BIT_MASK_SER_SER << BIT_SHIFT_SER_SER))
+
+// BAUDR           0x14  // 16 bits
+#define BIT_SHIFT_BAUDR_SCKDV    0
+#define BIT_MASK_BAUDR_SCKDV     0xFFFF
+#define BIT_BAUDR_SCKDV(x)(((x) & BIT_MASK_BAUDR_SCKDV) << BIT_SHIFT_BAUDR_SCKDV)
+#define BIT_INVC_BAUDR_SCKDV (~(BIT_MASK_BAUDR_SCKDV << BIT_SHIFT_BAUDR_SCKDV))
+
+// TXFLTR          0x18        // Variable Length
+#define BIT_SHIFT_TXFTLR_TFT    0
+#define BIT_MASK_TXFTLR_TFT     0x3F  // (TX_ABW-1):0
+#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT)
+#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT))
+
+// RXFLTR          0x1c        // Variable Length
+#define BIT_SHIFT_RXFTLR_RFT    0
+#define BIT_MASK_RXFTLR_RFT     0x3F  // (RX_ABW-1):0
+#define BIT_RXFTLR_RFT(x)(((x) & BIT_MASK_RXFTLR_RFT) << BIT_SHIFT_RXFTLR_RFT)
+#define BIT_INVC_RXFTLR_RFT (~(BIT_MASK_RXFTLR_RFT << BIT_SHIFT_RXFTLR_RFT))
+
+// TXFLR           0x20  // see     [READ ONLY]
+#define BIT_MASK_TXFLR_TXTFL    0x7F  // (TX_ABW):0
+
+// RXFLR           0x24  // see     [READ ONLY]
+#define BIT_MASK_RXFLR_RXTFL    0x7F  // (RX_ABW):0
+
+// SR              0x28  //  7 bits [READ ONLY]
+#define BIT_SR_BUSY  BIT0
+#define BIT_SR_TFNF  BIT1
+#define BIT_SR_TFE   BIT2
+#define BIT_SR_RFNE  BIT3
+#define BIT_SR_RFF   BIT4
+#define BIT_SR_TXE   BIT5
+#define BIT_SR_DCOL  BIT6
+
+// IMR             0x2c  // see
+#define BIT_SHIFT_IMR_TXEIM    0
+#define BIT_MASK_IMR_TXEIM     0x1
+// #define BIT_IMR_TXEIM(x)(((x) & BIT_MASK_IMR_TXEIM) << BIT_SHIFT_IMR_TXEIM)
+#define BIT_INVC_IMR_TXEIM (~(BIT_MASK_IMR_TXEIM << BIT_SHIFT_IMR_TXEIM))
+
+#define BIT_SHIFT_IMR_TXOIM    1
+#define BIT_MASK_IMR_TXOIM     0x1
+// #define BIT_IMR_TXOIM(x)(((x) & BIT_MASK_IMR_TXOIM) << BIT_SHIFT_IMR_TXOIM)
+#define BIT_INVC_IMR_TXOIM (~(BIT_MASK_IMR_TXOIM << BIT_SHIFT_IMR_TXOIM))
+
+#define BIT_SHIFT_IMR_RXUIM    2
+#define BIT_MASK_IMR_RXUIM     0x1
+// #define BIT_IMR_RXUIM(x)(((x) & BIT_MASK_IMR_RXUIM) << BIT_SHIFT_IMR_RXUIM)
+#define BIT_INVC_IMR_RXUIM (~(BIT_MASK_IMR_RXUIM << BIT_SHIFT_IMR_RXUIM))
+
+#define BIT_SHIFT_IMR_RXOIM    3
+#define BIT_MASK_IMR_RXOIM     0x1
+// #define BIT_IMR_RXOIM(x)(((x) & BIT_MASK_IMR_RXOIM) << BIT_SHIFT_IMR_RXOIM)
+#define BIT_INVC_IMR_RXOIM (~(BIT_MASK_IMR_RXOIM << BIT_SHIFT_IMR_RXOIM))
+
+#define BIT_SHIFT_IMR_RXFIM    4
+#define BIT_MASK_IMR_RXFIM     0x1
+// #define BIT_IMR_RXFIM(x)(((x) & BIT_MASK_IMR_RXFIM) << BIT_SHIFT_IMR_RXFIM)
+#define BIT_INVC_IMR_RXFIM (~(BIT_MASK_IMR_RXFIM << BIT_SHIFT_IMR_RXFIM))
+
+#define BIT_SHIFT_IMR_MSTIM    5
+#define BIT_MASK_IMR_MSTIM     0x1
+// #define BIT_IMR_MSTIM(x)(((x) & BIT_MASK_IMR_MSTIM) << BIT_SHIFT_IMR_MSTIM)
+#define BIT_INVC_IMR_MSTIM (~(BIT_MASK_IMR_MSTIM << BIT_SHIFT_IMR_MSTIM))
+
+#define BIT_IMR_TXEIM  BIT0
+#define BIT_IMR_TXOIM  BIT1
+#define BIT_IMR_RXUIM  BIT2
+#define BIT_IMR_RXOIM  BIT3
+#define BIT_IMR_RXFIM  BIT4
+#define BIT_IMR_MSTIM  BIT5
+
+// ISR             0x30  //  6 bits [READ ONLY]
+#define BIT_ISR_TXEIS  BIT0
+#define BIT_ISR_TXOIS  BIT1
+#define BIT_ISR_RXUIS  BIT2
+#define BIT_ISR_RXOIS  BIT3
+#define BIT_ISR_RXFIS  BIT4
+#define BIT_ISR_MSTIS  BIT5
+
+// RISR            0x34  //  6 bits [READ ONLY]
+#define BIT_RISR_TXEIR  BIT0
+#define BIT_RISR_TXOIR  BIT1
+#define BIT_RISR_RXUIR  BIT2
+#define BIT_RISR_RXOIR  BIT3
+#define BIT_RISR_RXFIR  BIT4
+#define BIT_RISR_MSTIR  BIT5
+
+// TXOICR          0x38  //  1 bits [READ ONLY]
+// RXOICR          0x3c  //  1 bits [READ ONLY]
+// RXUICR          0x40  //  1 bits [READ ONLY]
+// MSTICR          0x44  //  1 bits [READ ONLY]
+// ICR             0x48  //  1 bits [READ ONLY]
+
+// DMACR           0x4c  //  2 bits
+#define BIT_SHIFT_DMACR_RDMAE    0
+#define BIT_MASK_DMACR_RDMAE     0x1
+#define BIT_DMACR_RDMAE(x)(((x) & BIT_MASK_DMACR_RDMAE) << BIT_SHIFT_DMACR_RDMAE)
+#define BIT_INVC_DMACR_RDMAE (~(BIT_MASK_DMACR_RDMAE << BIT_SHIFT_DMACR_RDMAE))
+
+#define BIT_SHIFT_DMACR_TDMAE    1
+#define BIT_MASK_DMACR_TDMAE     0x1
+#define BIT_DMACR_TDMAE(x)(((x) & BIT_MASK_DMACR_TDMAE) << BIT_SHIFT_DMACR_TDMAE)
+#define BIT_INVC_DMACR_TDMAE (~(BIT_MASK_DMACR_TDMAE << BIT_SHIFT_DMACR_TDMAE))
+
+// DMATDLR         0x50
+#define BIT_SHIFT_DMATDLR_DMATDL    0
+#define BIT_MASK_DMATDLR_DMATDL     0x3F  // (TX_ABW-1):0
+#define BIT_DMATDLR_DMATDL(x)(((x) & BIT_MASK_DMATDLR_DMATDL) << BIT_SHIFT_DMATDLR_DMATDL)
+#define BIT_INVC_DMATDLR_DMATDL (~(BIT_MASK_DMATDLR_DMATDL << BIT_SHIFT_DMATDLR_DMATDL))
+
+// DMARDLR         0x54
+#define BIT_SHIFT_DMARDLR_DMARDL    0
+#define BIT_MASK_DMARDLR_DMARDL     0x3F  // (RX_ABW-1):0
+#define BIT_DMARDLR_DMARDL(x)(((x) & BIT_MASK_DMARDLR_DMARDL) << BIT_SHIFT_DMARDLR_DMARDL)
+#define BIT_INVC_DMARDLR_DMARDL (~(BIT_MASK_DMARDLR_DMARDL << BIT_SHIFT_DMARDLR_DMARDL))
+
+// IDR             0x58  // 32 bits [READ ONLY]
+// COMP_VERSION    0x5c  // 32 bits [READ ONLY]
+
+// DR              0x60  // 16 bits 0x60-0xEC
+#define BIT_SHIFT_DR_DR    0
+#define BIT_MASK_DR_DR     0xFFFF
+#define BIT_DR_DR(x)(((x) & BIT_MASK_DR_DR) << BIT_SHIFT_DR_DR)
+#define BIT_INVC_DR_DR (~(BIT_MASK_DR_DR << BIT_SHIFT_DR_DR))
+
+// RX_SAMPLE_DLY   0xF0  //  8 bits
+#define BIT_SHIFT_RX_SAMPLE_DLY_RSD    0
+#define BIT_MASK_RX_SAMPLE_DLY_RSD     0xFFFF
+#define BIT_RX_SAMPLE_DLY_RSD(x)(((x) & BIT_MASK_RX_SAMPLE_DLY_RSD) << BIT_SHIFT_RX_SAMPLE_DLY_RSD)
+#define BIT_INVC_RX_SAMPLE_DLY_RSD (~(BIT_MASK_RX_SAMPLE_DLY_RSD << BIT_SHIFT_RX_SAMPLE_DLY_RSD))
+
+// RSVD_0          0xF4  // 32 bits
+// RSVD_1          0xF8  // 32 bits
+// RSVD_2          0xFC  // 32 bits
+
+// SSI0 Pinmux
+#define BIT_SHIFT_SSI0_PIN_EN    0
+#define BIT_MASK_SSI0_PIN_EN     0x1
+#define BIT_SSI0_PIN_EN(x)(((x) & BIT_MASK_SSI0_PIN_EN) << BIT_SHIFT_SSI0_PIN_EN)
+#define BIT_INVC_SSI0_PIN_EN (~(BIT_MASK_SSI0_PIN_EN << BIT_SHIFT_SSI0_PIN_EN))
+
+#define BIT_SHIFT_SSI0_PIN_SEL    1
+#define BIT_MASK_SSI0_PIN_SEL     0x7
+#define BIT_SSI0_PIN_SEL(x)(((x) & BIT_MASK_SSI0_PIN_SEL) << BIT_SHIFT_SSI0_PIN_SEL)
+#define BIT_INVC_SSI0_PIN_SEL (~(BIT_MASK_SSI0_PIN_SEL << BIT_SHIFT_SSI0_PIN_SEL))
+
+// SSI1 Pinmux
+#define BIT_SHIFT_SSI1_PIN_EN    4
+#define BIT_MASK_SSI1_PIN_EN     0x1
+#define BIT_SSI1_PIN_EN(x)(((x) & BIT_MASK_SSI1_PIN_EN) << BIT_SHIFT_SSI1_PIN_EN)
+#define BIT_INVC_SSI1_PIN_EN (~(BIT_MASK_SSI1_PIN_EN << BIT_SHIFT_SSI1_PIN_EN))
+
+#define BIT_SHIFT_SSI1_PIN_SEL    5
+#define BIT_MASK_SSI1_PIN_SEL     0x7
+#define BIT_SSI1_PIN_SEL(x)(((x) & BIT_MASK_SSI1_PIN_SEL) << BIT_SHIFT_SSI1_PIN_SEL)
+#define BIT_INVC_SSI1_PIN_SEL (~(BIT_MASK_SSI1_PIN_SEL << BIT_SHIFT_SSI1_PIN_SEL))
+
+// SSI2 Pinmux
+#define BIT_SHIFT_SSI2_PIN_EN    8
+#define BIT_MASK_SSI2_PIN_EN     0x1
+#define BIT_SSI2_PIN_EN(x)(((x) & BIT_MASK_SSI2_PIN_EN) << BIT_SHIFT_SSI2_PIN_EN)
+#define BIT_INVC_SSI2_PIN_EN (~(BIT_MASK_SSI2_PIN_EN << BIT_SHIFT_SSI2_PIN_EN))
+
+#define BIT_SHIFT_SSI2_PIN_SEL    9
+#define BIT_MASK_SSI2_PIN_SEL     0x7
+#define BIT_SSI2_PIN_SEL(x)(((x) & BIT_MASK_SSI2_PIN_SEL) << BIT_SHIFT_SSI2_PIN_SEL)
+#define BIT_INVC_SSI2_PIN_SEL (~(BIT_MASK_SSI2_PIN_SEL << BIT_SHIFT_SSI2_PIN_SEL))
+
+// SSI0 Multiple Chip Selection (Pinmux Select is controlled by BIT_SSI0_PIN_SEL)
+#define BIT_SHIFT_SSI0_MULTI_CS_EN    28
+#define BIT_MASK_SSI0_MULTI_CS_EN     0x1
+#define BIT_SSI0_MULTI_CS_EN(x)(((x) & BIT_MASK_SSI0_MULTI_CS_EN) << BIT_SHIFT_SSI0_MULTI_CS_EN)
+#define BIT_INVC_SSI0_MULTI_CS_EN (~(BIT_MASK_SSI0_MULTI_CS_EN << BIT_SHIFT_SSI0_MULTI_CS_EN))
+
+
+#define HAL_SSI_READ32(SsiIndex, addr)         \
+    HAL_READ32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
+#define HAL_SSI_WRITE32(SsiIndex, addr, value) \
+    HAL_WRITE32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
+#define HAL_SSI_READ16(SsiIndex, addr)         \
+    HAL_READ16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
+#define HAL_SSI_WRITE16(SsiIndex, addr, value) \
+    HAL_WRITE16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
+#define HAL_SSI_READ8(SsiIndex, addr)          \
+    HAL_READ8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
+#define HAL_SSI_WRITE8(SsiIndex, addr, value)  \
+    HAL_WRITE8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
+
+
+// SSI Pinmux Select
+typedef enum _SSI0_PINMUX_SELECT_ {
+    SSI0_MUX_TO_GPIOE = S0,
+    SSI0_MUX_TO_GPIOC = S1
+}SSI0_PINMUX_SELECT, *PSSI0_PINMUX_SELECT;
+
+typedef enum _SSI1_PINMUX_SELECT_ {
+    SSI1_MUX_TO_GPIOA = S0,
+    SSI1_MUX_TO_GPIOB = S1,
+    SSI1_MUX_TO_GPIOD = S2
+}SSI1_PINMUX_SELECT, *PSSI1_PINMUX_SELECT;
+
+typedef enum _SSI2_PINMUX_SELECT_ {
+    SSI2_MUX_TO_GPIOG = S0,
+    SSI2_MUX_TO_GPIOE = S1,
+    SSI2_MUX_TO_GPIOD = S2
+}SSI2_PINMUX_SELECT, *PSSI2_PINMUX_SELECT;
+
+typedef enum _SSI0_MULTI_CS_PINMUX_SELECT_ {
+    SSI0_CS_MUX_TO_GPIOE    = S0,
+    SSI0_CS_MUX_TO_GPIOC    = S1
+}SSI0_MULTI_CS_PINMUX_SELECT, *PSSI0_MULTI_CS_PINMUX_SELECT;
+
+typedef enum _SSI_CTRLR0_TMOD_ {
+    TMOD_TR       = 0,
+    TMOD_TO       = 1,
+    TMOD_RO       = 2,
+    TMOD_EEPROM_R = 3
+}SSI_CTRLR0_TMOD, *PSSI_CTRLR0_TMOD;
+
+typedef enum _SSI_CTRLR0_SCPOL_ {
+    SCPOL_INACTIVE_IS_LOW  = 0,
+    SCPOL_INACTIVE_IS_HIGH = 1
+}SSI_CTRLR0_SCPOL, *PSSI_CTRLR0_SCPOL;
+
+typedef enum _SSI_CTRLR0_SCPH_ {
+    SCPH_TOGGLES_IN_MIDDLE = 0,
+    SCPH_TOGGLES_AT_START  = 1
+}SSI_CTRLR0_SCPH, *PSSI_CTRLR0_SCPH;
+
+typedef enum _SSI_CTRLR0_DFS_ {
+    DFS_4_BITS   = 3,
+    DFS_5_BITS   = 4,
+    DFS_6_BITS   = 5,
+    DFS_7_BITS   = 6,
+    DFS_8_BITS   = 7,
+    DFS_9_BITS   = 8,
+    DFS_10_BITS  = 9,
+    DFS_11_BITS  = 10,
+    DFS_12_BITS  = 11,
+    DFS_13_BITS  = 12,
+    DFS_14_BITS  = 13,
+    DFS_15_BITS  = 14,
+    DFS_16_BITS  = 15,
+}SSI_CTRLR0_DFS, *PSSI_CTRLR0_DFS;
+
+typedef enum _SSI_CTRLR0_CFS_ {
+    CFS_1_BIT    = 0,
+    CFS_2_BITS   = 1,
+    CFS_3_BITS   = 2,
+    CFS_4_BITS   = 3,
+    CFS_5_BITS   = 4,
+    CFS_6_BITS   = 5,
+    CFS_7_BITS   = 6,
+    CFS_8_BITS   = 7,
+    CFS_9_BITS   = 8,
+    CFS_10_BITS  = 9,
+    CFS_11_BITS  = 10,
+    CFS_12_BITS  = 11,
+    CFS_13_BITS  = 12,
+    CFS_14_BITS  = 13,
+    CFS_15_BITS  = 14,
+    CFS_16_BITS  = 15
+}SSI_CTRLR0_CFS, *PSSI_CTRLR0_CFS;
+
+typedef enum _SSI_CTRLR0_SLV_OE_ {
+    SLV_TXD_ENABLE  = 0,
+    SLV_TXD_DISABLE = 1
+}SSI_CTRLR0_SLV_OE, *PSSI_CTRLR0_SLV_OE;
+
+typedef enum _SSI_ROLE_SELECT_ {
+    SSI_SLAVE  = 0,
+    SSI_MASTER = 1
+}SSI_ROLE_SELECT, *PSSI_ROLE_SELECT;
+
+typedef enum _SSI_FRAME_FORMAT_ {
+    FRF_MOTOROLA_SPI = 0,
+    FRF_TI_SSP       = 1,
+    FRF_NS_MICROWIRE = 2,
+    FRF_RSVD         = 3
+}SSI_FRAME_FORMAT, *PSSI_FRAME_FORMAT;
+
+typedef enum _SSI_DMACR_ENABLE_ {
+    SSI_NODMA        = 0,
+    SSI_RXDMA_ENABLE = 1,
+    SSI_TXDMA_ENABLE = 2,
+    SSI_TRDMA_ENABLE = 3
+}SSI_DMACR_ENABLE, *PSSI_DMACR_ENABLE;
+
+typedef enum _SSI_MWCR_HANDSHAKE_ {
+    MW_HANDSHAKE_DISABLE = 0,
+    MW_HANDSHAKE_ENABLE  = 1
+}SSI_MWCR_HANDSHAKE, *PSSI_MWCR_HANDSHAKE;
+
+typedef enum _SSI_MWCR_DIRECTION_ {
+    MW_DIRECTION_SLAVE_TO_MASTER = 0,
+    MW_DIRECTION_MASTER_TO_SLAVE = 1
+}SSI_MWCR_DIRECTION, *PSSI_MWCR_DIRECTION;
+
+typedef enum _SSI_MWCR_TMOD_ {
+    MW_TMOD_NONSEQUENTIAL = 0,
+    MW_TMOD_SEQUENTIAL    = 1
+}SSI_MWCR_TMOD, *PSSI_MWCR_TMOD;
+
+typedef enum _SSI_DATA_TRANSFER_MECHANISM_ {
+    SSI_DTM_BASIC,
+    SSI_DTM_INTERRUPT,
+    SSI_DTM_DMA
+}SSI_DATA_TRANSFER_MECHANISM, *PSSI_DATA_TRANSFER_MECHANISM;
+
+
+_LONG_CALL_ HAL_Status HalSsiPinmuxEnableRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiEnableRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiDisableRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiInitRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiSetSclkPolarityRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiSetSclkPhaseRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiWriteRtl8195a(VOID *Adaptor, u32 value);
+_LONG_CALL_ HAL_Status HalSsiLoadSettingRtl8195a(VOID *Adaptor, VOID *Setting);
+_LONG_CALL_ HAL_Status HalSsiSetInterruptMaskRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiSetDeviceRoleRtl8195a(VOID *Adaptor, u32 Role);
+_LONG_CALL_ HAL_Status HalSsiInterruptEnableRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiInterruptDisableRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiReadInterruptRtl8195a(VOID *Adaptor, VOID *RxData, u32 Length);
+_LONG_CALL_ HAL_Status HalSsiSetRxFifoThresholdLevelRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiSetTxFifoThresholdLevelRtl8195a(VOID *Adaptor);
+_LONG_CALL_ HAL_Status HalSsiWriteInterruptRtl8195a(VOID *Adaptor, VOID *TxData, u32 Length);
+_LONG_CALL_ HAL_Status HalSsiSetSlaveEnableRegisterRtl8195a(VOID *Adaptor, u32 SlaveIndex);
+_LONG_CALL_ u32 HalSsiBusyRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiWriteableRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiReadableRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiGetInterruptMaskRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiGetRxFifoLevelRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiGetTxFifoLevelRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiGetStatusRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiGetInterruptStatusRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiReadRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiGetRawInterruptStatusRtl8195a(VOID *Adaptor);
+_LONG_CALL_ u32 HalSsiGetSlaveEnableRegisterRtl8195a(VOID *Adaptor);
+
+_LONG_CALL_ VOID _SsiReadInterrupt(VOID *Adaptor);
+_LONG_CALL_ VOID _SsiWriteInterrupt(VOID *Adaptor);
+_LONG_CALL_ u32  _SsiIrqHandle(VOID *Adaptor);
+
+// ROM code patch
+VOID _SsiReadInterruptRtl8195a(VOID *Adapter);
+VOID _SsiWriteInterruptRtl8195a(VOID *Adapter);
+HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor);
+HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor);
+HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor);
+HAL_Status HalSsiDeInitRtl8195a(VOID * Adapter);
+HAL_Status HalSsiClockOffRtl8195a(VOID * Adapter);
+HAL_Status HalSsiClockOnRtl8195a(VOID * Adapter);
+VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate);
+HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length);
+HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
+#ifdef CONFIG_GDMA_EN
+VOID HalSsiTxGdmaLoadDefRtl8195a(VOID *Adapter);
+VOID HalSsiRxGdmaLoadDefRtl8195a(VOID *Adapter);
+VOID HalSsiDmaInitRtl8195a(VOID *Adapter);
+HAL_Status HalSsiDmaSendRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
+HAL_Status HalSsiDmaRecvRtl8195a(VOID *Adapter, u8 *pRxData, u32 Length);
+#endif  // end of "#ifdef CONFIG_GDMA_EN"
+
+#endif

sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_timer.h

@@ -0,0 +1,235 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _RTL8195A_TIMER_H_
+#define _RTL8195A_TIMER_H_
+
+
+#define TIMER_TICK_US               31
+
+#define TIMER_LOAD_COUNT_OFF        0x00
+#define TIMER_CURRENT_VAL_OFF       0x04
+#define TIMER_CTL_REG_OFF           0x08
+#define TIMER_EOI_OFF               0x0c
+#define TIMER_INT_STATUS_OFF        0x10
+#define TIMER_INTERVAL              0x14
+#define TIMERS_INT_STATUS_OFF       0xa0
+#define TIMERS_EOI_OFF              0xa4
+#define TIMERS_RAW_INT_STATUS_OFF   0xa8
+#define TIMERS_COMP_VER_OFF         0xac
+
+#define MAX_TIMER_VECTOR_TABLE_NUM                  6
+
+#define HAL_TIMER_READ32(addr)            (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr)
+#define HAL_TIMER_WRITE32(addr, value)    ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value)
+#define HAL_TIMER_READ16(addr)            (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr)
+#define HAL_TIMER_WRITE16(addr, value)    ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value)
+#define HAL_TIMER_READ8(addr)             (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr)
+#define HAL_TIMER_WRITE8(addr, value)     ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value)
+
+_LONG_CALL_ u32
+HalGetTimerIdRtl8195a(
+    IN  u32     *TimerID
+);
+
+_LONG_CALL_ BOOL
+HalTimerInitRtl8195a(
+    IN  VOID    *Data
+);
+
+_LONG_CALL_ u32
+HalTimerReadCountRtl8195a(
+    IN  u32     TimerId
+);
+
+_LONG_CALL_ VOID
+HalTimerIrqClearRtl8195a(
+    IN  u32 TimerId
+);
+
+_LONG_CALL_ VOID
+HalTimerDisRtl8195a(
+    IN  u32 TimerId
+);
+
+_LONG_CALL_ VOID
+HalTimerEnRtl8195a(
+    IN  u32 TimerId
+);
+
+_LONG_CALL_ VOID
+HalTimerDumpRegRtl8195a(
+    IN  u32 TimerId
+);
+
+// ROM Code patch
+HAL_Status
+HalTimerInitRtl8195a_Patch(
+    IN  VOID    *Data
+);
+
+u32
+HalTimerReadCountRtl8195a_Patch(
+    IN  u32 TimerId
+);
+
+VOID
+HalTimerReLoadRtl8195a_Patch(
+    IN  u32 TimerId,
+    IN  u32 LoadUs
+);
+
+u32
+HalTimerReadCountRtl8195a_Patch(
+    IN  u32 TimerId
+);
+
+VOID
+HalTimerIrqEnRtl8195a(
+    IN  u32 TimerId
+);
+
+VOID
+HalTimerIrqDisRtl8195a(
+    IN  u32 TimerId
+);
+
+VOID
+HalTimerClearIsrRtl8195a(
+    IN  u32 TimerId
+);
+
+VOID
+HalTimerEnRtl8195a_Patch(
+    IN  u32 TimerId
+);
+
+VOID
+HalTimerDisRtl8195a_Patch(
+    IN  u32 TimerId
+);
+
+VOID
+HalTimerDeInitRtl8195a_Patch(
+    IN  VOID    *Data
+);
+
+#ifdef CONFIG_CHIP_C_CUT
+
+__weak _LONG_CALL_
+VOID
+HalTimerIrq2To7HandleV02(
+    IN  VOID    *Data
+);
+
+__weak _LONG_CALL_
+HAL_Status
+HalTimerIrqRegisterRtl8195aV02(
+    IN  VOID    *Data
+);
+
+__weak _LONG_CALL_
+HAL_Status
+HalTimerInitRtl8195aV02(
+    IN  VOID    *Data
+);
+
+__weak _LONG_CALL_
+u32
+HalTimerReadCountRtl8195aV02(
+    IN  u32 TimerId
+);
+
+__weak _LONG_CALL_
+VOID
+HalTimerReLoadRtl8195aV02(
+    IN  u32 TimerId,
+    IN  u32 LoadUs
+);
+
+__weak _LONG_CALL_
+HAL_Status
+HalTimerIrqUnRegisterRtl8195aV02(
+    IN  VOID    *Data
+);
+
+__weak _LONG_CALL_
+VOID
+HalTimerDeInitRtl8195aV02(
+    IN  VOID    *Data
+);
+
+#endif  // end of "#ifdef CONFIG_CHIP_C_CUT"
+
+// HAL functions wrapper
+static __inline HAL_Status
+HalTimerInit(
+    IN  VOID    *Data
+)
+{
+    return (HalTimerInitRtl8195a_Patch(Data));
+}
+
+static __inline VOID
+HalTimerEnable(
+    IN  u32 TimerId
+)
+{
+    HalTimerIrqEnRtl8195a(TimerId);
+    HalTimerEnRtl8195a_Patch(TimerId);
+}
+
+static __inline VOID
+HalTimerDisable(
+    IN  u32 TimerId
+)
+{
+    HalTimerDisRtl8195a_Patch(TimerId);
+}
+
+static __inline VOID
+HalTimerClearIsr(
+    IN  u32 TimerId
+)
+{
+    HalTimerClearIsrRtl8195a(TimerId);
+}
+
+static __inline VOID
+HalTimerReLoad(
+    IN  u32 TimerId,
+    IN  u32 LoadUs
+)
+{
+    HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs);
+}
+
+#ifndef CONFIG_CHIP_C_CUT
+
+static __inline VOID
+HalTimerDeInit(
+    IN  VOID    *Data
+)
+{
+    HalTimerDeInitRtl8195a_Patch(Data);
+}
+
+#else
+
+static __inline VOID
+HalTimerDeInit(
+    IN  VOID    *Data
+)
+{
+    HalTimerDeInitRtl8195aV02(Data);
+}
+
+#endif      // end of "#ifndef CONFIG_CHIP_C_CUT"
+
+#endif //_RTL8195A_TIMER_H_

sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h

@@ -0,0 +1,532 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+
+#ifndef _RTL8195A_UART_H_
+#define _RTL8195A_UART_H_
+
+#define MAX_UART_INDEX      2
+
+#define RUART_DLL_OFF                   0x00
+#define RUART_DLM_OFF                   0x04    //RW, DLAB = 1
+#define RUART_INTERRUPT_EN_REG_OFF      0x04
+#define RUART_IER_ERBI                  0x01    //BIT0, Enable Received Data Available Interrupt (rx trigger)
+#define RUART_IER_ETBEI                 (1<<1)  //BIT1, Enable Transmitter FIFO Empty Interrupt (tx fifo empty)
+#define RUART_IER_ELSI                  (1<<2)  //BIT2, Enable Receiver Line Status Interrupt (receiver line status)
+#define RUART_IER_EDSSI                 (1<<3)  //BIT3, Enable Modem Status Interrupt (modem status transition)
+
+#define RUART_INT_ID_REG_OFF            0x08    //[R]
+#define RUART_IIR_INT_PEND              0x01
+#define RUART_IIR_INT_ID                (0x07<<1) //011(3), 010(2), 110(6), 001(1), 000(0)
+#define RUART_FIFO_CTL_REG_OFF          0x08    //[W]
+#define RUART_FIFO_CTL_REG_CLEAR_RXFIFO (1<<1)  //BIT1, 0x02, Write 1 clear
+#define RUART_FIFO_CTL_REG_CLEAR_TXFIFO (1<<2)  //BIT2, 0x04, Write 1 clear
+#define RUART_FIFO_CTL_REG_DMA_ENABLE   0x08    //BIT3
+
+#define FIFO_CTL_DEFAULT_WITH_FIFO_DMA  0xC9
+#define FIFO_CTL_DEFAULT_WITH_FIFO      0xC1
+
+#define RUART_MODEM_CTL_REG_OFF         0x10
+#define RUART_MCR_RTS                   BIT1
+#define RUART_MCL_AUTOFLOW_ENABLE       (1<<5)  //BIT5, 0x20
+
+#define RUART_LINE_CTL_REG_OFF          0x0C
+#define RUART_LINE_CTL_REG_DLAB_ENABLE  (1<<7)  //BIT7, 0x80
+
+#define RUART_LINE_STATUS_REG_OFF       0x14
+#define RUART_LINE_STATUS_REG_DR        0x01    //BIT0, Data Ready indicator
+#define RUART_LINE_STATUS_ERR_OVERRUN   (1<<1)  //BIT1, Over Run
+#define RUART_LINE_STATUS_ERR_PARITY    (1<<2)  //BIT2, Parity error
+#define RUART_LINE_STATUS_ERR_FRAMING   (1<<3)  //BIT3, Framing error
+#define RUART_LINE_STATUS_ERR_BREAK     (1<<4)  //BIT4, Break interrupt error
+#define RUART_LINE_STATUS_REG_THRE      (1<<5)  //BIT5, 0x20, Transmit Holding Register Empty Interrupt enable
+#define RUART_LINE_STATUS_REG_TEMT      (1<<6)  //BIT6, 0x40, Transmitter Empty indicator(bit)
+#define RUART_LINE_STATUS_ERR_RXFIFO    (1<<7)  //BIT7, RX FIFO error
+#define RUART_LINE_STATUS_ERR           (RUART_LINE_STATUS_ERR_OVERRUN|RUART_LINE_STATUS_ERR_PARITY| \
+                                        RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \
+                                        RUART_LINE_STATUS_ERR_RXFIFO)      //Line status error
+
+#define RUART_MODEM_STATUS_REG_OFF      0x18    //Modem Status Register
+#define RUART_SCRATCH_PAD_REG_OFF       0x1C    //Scratch Pad Register
+#define RUART_SP_REG_RXBREAK_INT_STATUS (1<<7)  //BIT7, 0x80, Write 1 clear
+#define RUART_SP_REG_DBG_SEL            (0x0F<<8) //[11:8], Debug port selection
+#define RUART_SP_REG_XFACTOR_ADJ        (0x7FF<<16)  //[26:16]
+
+#define RUART_STS_REG_OFF               0x20
+#define RUART_STS_REG_RESET_RCV         (1<<3)  //BIT3, 0x08, Reset Uart Receiver
+#define RUART_STS_REG_XFACTOR           0xF<<4
+
+#define RUART_REV_BUF_REG_OFF           0x24  //Receiver Buffer Register
+#define RUART_TRAN_HOLD_REG_OFF         0x24  //Transmitter Holding Register
+
+#define RUART_MISC_CTL_REG_OFF          0x28
+#define RUART_TXDMA_BURSTSIZE_MASK      0xF8    //7:3
+#define RUART_RXDMA_BURSTSIZE_MASK      0x1F00  //12:8
+
+#define RUART_DEBUG_REG_OFF             0x3C
+
+// RUART_LINE_CTL_REG_OFF (0x0C)
+#define BIT_SHIFT_LCR_WLS             0     // word length select: 0: 7 bits, 1: 8bits
+#define BIT_MASK_LCR_WLS_8BITS        0x1
+#define BIT_LCR_WLS(x)(((x) & BIT_MASK_LCR_WLS_8BITS) << BIT_SHIFT_LCR_WLS)
+#define BIT_CLR_LCR_WLS (~(BIT_MASK_LCR_WLS_8BITS << BIT_SHIFT_LCR_WLS))
+
+#define BIT_SHIFT_LCR_STB             2     // Stop bit select: 0: no stop bit, 1: 1 stop bit
+#define BIT_MASK_LCR_STB_EN           0x1
+#define BIT_LCR_STB_EN(x)(((x) & BIT_MASK_LCR_STB_EN) << BIT_SHIFT_LCR_STB)
+#define BIT_INVC_LCR_STB_EN (~(BIT_MASK_LCR_STB_EN << BIT_SHIFT_LCR_STB))
+
+#define BIT_SHIFT_LCR_PARITY_EN       3
+#define BIT_MASK_LCR_PARITY_EN        0x1
+#define BIT_LCR_PARITY_EN(x)(((x) & BIT_MASK_LCR_PARITY_EN) << BIT_SHIFT_LCR_PARITY_EN)
+#define BIT_INVC_LCR_PARITY_EN (~(BIT_MASK_LCR_PARITY_EN << BIT_SHIFT_LCR_PARITY_EN))
+
+#define BIT_SHIFT_LCR_PARITY_TYPE       4
+#define BIT_MASK_LCR_PARITY_TYPE        0x1
+#define BIT_LCR_PARITY_TYPE(x)(((x) & BIT_MASK_LCR_PARITY_TYPE) << BIT_SHIFT_LCR_PARITY_TYPE)
+#define BIT_INVC_LCR_PARITY_TYPE (~(BIT_MASK_LCR_PARITY_TYPE << BIT_SHIFT_LCR_PARITY_TYPE))
+
+#define BIT_SHIFT_LCR_STICK_PARITY_EN       5
+#define BIT_MASK_LCR_STICK_PARITY_EN        0x1
+#define BIT_LCR_STICK_PARITY_EN(x)(((x) & BIT_MASK_LCR_STICK_PARITY_EN) << BIT_SHIFT_LCR_STICK_PARITY_EN)
+#define BIT_INVC_LCR_STICK_PARITY_EN (~(BIT_MASK_LCR_STICK_PARITY_EN << BIT_SHIFT_LCR_STICK_PARITY_EN))
+
+#define BIT_SHIFT_LCR_BREAK_CTRL       6
+#define BIT_MASK_LCR_BREAK_CTRL        0x1
+#define BIT_UART_LCR_BREAK_CTRL        ((BIT_MASK_LCR_BREAK_CTRL) << BIT_SHIFT_LCR_BREAK_CTRL)
+
+#define RUART_BAUD_RATE_2400     2400
+#define RUART_BAUD_RATE_4800     4800
+#define RUART_BAUD_RATE_9600     9600
+#define RUART_BAUD_RATE_19200    19200
+#define RUART_BAUD_RATE_38400    38400
+#define RUART_BAUD_RATE_57600    57600
+#define RUART_BAUD_RATE_115200   115200
+#define RUART_BAUD_RATE_921600   921600
+#define RUART_BAUD_RATE_1152000  1152000
+
+#define HAL_RUART_READ32(UartIndex, addr)    \
+    HAL_READ32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
+#define HAL_RUART_WRITE32(UartIndex, addr, value)    \
+    HAL_WRITE32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
+#define HAL_RUART_READ16(UartIndex, addr)    \
+    HAL_READ16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
+#define HAL_RUART_WRITE16(UartIndex, addr, value)    \
+    HAL_WRITE16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
+#define HAL_RUART_READ8(UartIndex, addr)    \
+    HAL_READ8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
+#define HAL_RUART_WRITE8(UartIndex, addr, value)    \
+    HAL_WRITE8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
+
+#define UART_OVSR_POOL_MIN      1000
+#define UART_OVSR_POOL_MAX      2090
+#define DIVISOR_RESOLUTION      10
+#define JITTER_LIMIT            100
+#define UART_SCLK               (200000000*5/12)
+
+typedef struct _RUART_SPEED_SETTING_ {
+    u32 BaudRate;
+    u32 Ovsr;
+    u32 Div;
+    u16 Ovsr_adj;
+    u8 Ovsr_adj_max_bits;  // 9: No parity, 10: with Parity
+    u8 Ovsr_adj_bits;
+    u16 *Ovsr_adj_map;
+    u32 max_err;        // 10 ~ 100: 30
+    u32 Ovsr_min;       // 10 ~ 20: 1000
+    u32 Ovsr_max;       // 10 ~ 20: 2000
+    u32 divisor_resolution; // 1 ~ 20: 10
+    u32 jitter_lim;     // 50 ~ 100: 100
+    u32 sclk;           // 83.33333 MHz
+}RUART_SPEED_SETTING, *PRUART_SPEED_SETTING;
+
+typedef enum _UART_RXFIFO_TRIGGER_LEVEL_ {
+    OneByte       = 0x00,
+    FourBytes     = 0x01,
+    EightBytes    = 0x10,
+    FourteenBytes = 0x11
+}UART_RXFIFO_TRIGGER_LEVEL, *PUART_RXFIFO_TRIGGER_LEVEL;
+
+typedef enum _RUART0_PINMUX_SELECT_ {
+    RUART0_MUX_TO_GPIOC = S0,
+    RUART0_MUX_TO_GPIOE = S1,
+    RUART0_MUX_TO_GPIOA = S2
+}RUART0_PINMUX_SELECT, *PRUART0_PINMUX_SELECT;
+
+typedef enum _RUART1_PINMUX_SELECT_ {
+    RUART1_MUX_TO_GPIOD = S0,
+    RUART1_MUX_TO_GPIOE = S1,
+    RUART1_MUX_TO_GPIOB = S2
+}RUART1_PINMUX_SELECT, *PRUART1_PINMUX_SELECT;
+
+typedef enum _RUART2_PINMUX_SELECT_ {
+    RUART2_MUX_TO_GPIOA = S0,
+    RUART2_MUX_TO_GPIOC = S1,
+    RUART2_MUX_TO_GPIOD = S2
+}RUART2_PINMUX_SELECT, *PRUART2_PINMUX_SELECT;
+
+typedef enum _RUART_FLOW_CONTROL_ {
+    AUTOFLOW_DISABLE = 0,
+    AUTOFLOW_ENABLE  = 1
+}RUART_FLOW_CONTROL, *PRUART_FLOW_CONTROL;
+
+typedef enum _RUART_WORD_LEN_SEL_ {
+	RUART_WLS_7BITS = 0,
+    RUART_WLS_8BITS = 1
+}RUART_WORD_LEN_SEL, *PRUART_WORD_LEN_SEL;
+
+typedef enum _RUART_STOP_BITS_ {
+    RUART_STOP_BIT_1 = 0,
+    RUART_STOP_BIT_2 = 1
+}RUART_STOP_BITS, *PRUART_STOP_BITS;
+
+typedef enum _RUART_PARITY_CONTROL_ {
+	RUART_PARITY_DISABLE = 0,
+	RUART_PARITY_ENABLE  = 1
+}RUART_PARITY_CONTROL, *PRUART_PARITY_CONTROL;
+
+typedef enum _RUART_PARITY_TYPE_ {
+	RUART_ODD_PARITY  = 0,
+	RUART_EVEN_PARITY = 1
+}RUART_PARITY_TYPE, *PRUART_PARITY_TYPE;
+
+typedef enum _RUART_STICK_PARITY_CONTROL_ {
+    RUART_STICK_PARITY_DISABLE = 0,
+    RUART_STICK_PARITY_ENABLE  = 1
+}RUART_STICK_PARITY_CONTROL, *PRUART_STICK_PARITY_CONTROL;
+
+typedef enum _UART_INT_ID_ {
+    ModemStatus           = 0,
+    TxFifoEmpty           = 1,
+    ReceiverDataAvailable = 2,
+    ReceivLineStatus      = 3,
+    TimeoutIndication     = 6
+}UART_INT_ID, *PUART_INT_ID;
+
+typedef enum _HAL_UART_State_
+{
+  HAL_UART_STATE_NULL              = 0x00,    // UART hardware not been initial yet
+  HAL_UART_STATE_READY             = 0x10,    // UART is initialed, ready to use
+  HAL_UART_STATE_BUSY              = 0x20,    // UART hardware is busy on configuration
+  HAL_UART_STATE_BUSY_TX           = 0x21,    // UART is buzy on TX
+  HAL_UART_STATE_BUSY_RX           = 0x22,    // UART is busy on RX
+  HAL_UART_STATE_BUSY_TX_RX        = 0x23,    // UART is busy on TX an RX
+  HAL_UART_STATE_TIMEOUT           = 0x30,    // Transfer timeout
+  HAL_UART_STATE_ERROR             = 0x40     // UART Error
+}HAL_UART_State, *PHAL_UART_State;
+
+typedef enum _HAL_UART_Status_
+{
+  HAL_UART_STATUS_OK               = 0x00,    // Transfer OK
+  HAL_UART_STATUS_TIMEOUT          = 0x01,    // Transfer Timeout
+  HAL_UART_STATUS_ERR_OVERRUN      = 0x02,    // RX Over run
+  HAL_UART_STATUS_ERR_PARITY       = 0x04,    // Parity error
+  HAL_UART_STATUS_ERR_FRAM         = 0x08,    // Framing Error
+  HAL_UART_STATUS_ERR_BREAK        = 0x10,    // Break Interrupt
+  HAL_UART_STATUS_ERR_PARA         = 0x20,    // Parameter error
+  HAL_UART_STATUS_ERR_RXFIFO       = 0x80,    // RX FIFO error
+}HAL_UART_Status, *PHAL_UART_Status;
+
+u32
+HalRuartGetDebugValueRtl8195a(
+        IN VOID* Data,
+        IN u32    DbgSel
+        );
+
+#if 0
+u32
+FindElementIndex(
+        u32 Element,
+        u32* Array
+        );
+#endif
+
+VOID
+RuartResetRxFifoRtl8195a(
+        IN u8 UartIndex
+        );
+#if 0
+VOID
+RuartBusDomainEnableRtl8195a(
+        IN u8 UartIndex
+        );
+#endif
+
+HAL_Status
+HalRuartResetRxFifoRtl8195a(
+        IN VOID *Data
+        );
+
+HAL_Status
+HalRuartInitRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalRuartDeInitRtl8195a(
+        IN VOID *Data  ///< RUART Adapter
+        );
+
+HAL_Status
+HalRuartPutCRtl8195a(
+        IN VOID *Data,
+        IN u8 TxData
+        );
+
+u32
+HalRuartSendRtl8195a(
+        IN VOID *Data,
+        IN u8 *pTxData,
+        IN u32 Length,
+        IN u32 Timeout
+        );
+
+HAL_Status
+HalRuartIntSendRtl8195a(
+        IN VOID *Data,      // PHAL_RUART_ADAPTER
+        IN u8 *pTxData,     // the Buffer to be send
+        IN u32 Length       // the length of data to be send
+        );
+
+HAL_Status
+HalRuartDmaSendRtl8195a(
+        IN VOID *Data,      // PHAL_RUART_ADAPTER
+        IN u8 *pTxData,     // the Buffer to be send
+        IN u32 Length      // the length of data to be send
+);
+
+HAL_Status
+HalRuartStopSendRtl8195a(
+        IN VOID *Data      // PHAL_RUART_ADAPTER
+);
+
+HAL_Status
+HalRuartGetCRtl8195a(
+        IN VOID *Data,
+        OUT u8  *pRxByte        
+        );
+
+u32
+HalRuartRecvRtl8195a(
+        IN VOID *Data,
+        IN u8  *pRxData,
+        IN u32 Length,
+        IN u32 Timeout
+        );
+
+HAL_Status
+HalRuartIntRecvRtl8195a(
+        IN VOID *Data,  ///< RUART Adapter
+        IN u8  *pRxData,  ///< Rx buffer
+        IN u32 Length      // buffer length
+        );
+
+HAL_Status
+HalRuartDmaRecvRtl8195a(
+        IN VOID *Data,  ///< RUART Adapter
+        IN u8  *pRxData,  ///< Rx buffer
+        IN u32 Length      // buffer length
+        );
+
+HAL_Status
+HalRuartStopRecvRtl8195a(
+        IN VOID *Data      // PHAL_RUART_ADAPTER
+);
+
+u8
+HalRuartGetIMRRtl8195a(
+        IN VOID *Data
+        );
+
+_LONG_CALL_ VOID
+HalRuartSetIMRRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalRuartDmaInitRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalRuartRTSCtrlRtl8195a(
+        IN VOID *Data,
+        IN BOOLEAN RtsCtrl
+        );
+
+VOID
+HalRuartRegIrqRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalRuartIntEnableRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalRuartIntDisableRtl8195a(
+        IN VOID *Data
+        );
+
+VOID
+HalRuartAdapterLoadDefRtl8195a(
+        IN VOID *pAdp,
+        IN u8 UartIdx
+);
+
+VOID
+HalRuartTxGdmaLoadDefRtl8195a(
+        IN VOID *pAdp,
+        IN VOID *pCfg
+);
+
+VOID
+HalRuartRxGdmaLoadDefRtl8195a(
+        IN VOID *pAdp,
+        IN VOID *pCfg
+);
+
+_LONG_CALL_  HAL_Status HalRuartIntSendRtl8195aV02(
+    IN VOID *Data,      // PHAL_RUART_ADAPTER
+    IN u8 *pTxData,     // the Buffer to be send
+    IN u32 Length      // the length of data to be send
+);
+
+_LONG_CALL_  HAL_Status
+HalRuartIntRecvRtl8195aV02(
+    IN VOID *Data,  ///< RUART Adapter
+    IN u8  *pRxData,  ///< Rx buffer
+    IN u32 Length      // buffer length
+);
+
+_LONG_CALL_ s32
+FindElementIndex_v02(
+        u32 Element,  ///< RUART Baudrate
+        u32* Array,    ///< Pre-defined Baudrate Array
+        u32 ElementNo
+);
+
+_LONG_CALL_ HAL_Status HalRuartInitRtl8195a_v02(IN VOID *Data);
+
+// New added function 2015/04/20
+HAL_Status
+HalRuartResetTxFifoRtl8195a(
+        IN VOID *Data  ///< RUART Adapter
+        );
+
+HAL_Status 
+HalRuartSetBaudRateRtl8195a(
+        IN VOID *Data
+        );
+
+HAL_Status 
+HalRuartEnableRtl8195a(
+    IN VOID *Data
+);
+
+HAL_Status 
+HalRuartDisableRtl8195a(
+    IN VOID *Data
+);
+
+HAL_Status 
+HalRuartFlowCtrlRtl8195a(
+    IN VOID *Data
+);
+
+HAL_Status
+HalRuartDmaSendRtl8195a_Patch(
+    IN VOID *Data,
+    IN u8 *pTxData,
+    IN u32 Length
+);
+
+HAL_Status
+RuartIsTimeout (
+    u32 StartCount,
+    u32 TimeoutCnt
+);
+
+HAL_Status
+HalRuartStopRecvRtl8195a_Patch(
+        IN VOID *Data
+);
+
+HAL_Status
+HalRuartStopSendRtl8195a_Patch(
+        IN VOID *Data
+);
+
+VOID
+HalRuartEnterCriticalRtl8195a(
+        IN VOID *Data
+);
+
+VOID
+HalRuartExitCriticalRtl8195a(
+        IN VOID *Data
+);
+
+#if CONFIG_CHIP_E_CUT
+_LONG_CALL_ HAL_Status 
+HalRuartSetBaudRateRtl8195a_V04(
+    IN VOID *Data
+);
+
+_LONG_CALL_ HAL_Status 
+HalRuartInitRtl8195a_V04(
+    IN VOID *Data  ///< RUART Adapter
+);
+
+_LONG_CALL_ HAL_Status 
+HalRuartEnableRtl8195a_V04(
+    IN VOID *Data
+);
+
+_LONG_CALL_ HAL_Status 
+HalRuartDisableRtl8195a_V04(
+    IN VOID *Data
+);
+
+_LONG_CALL_ HAL_Status 
+HalRuartFlowCtrlRtl8195a_V04(
+    IN VOID *Data
+);
+
+_LONG_CALL_ HAL_Status
+HalRuartDmaSendRtl8195a_V04(
+    IN VOID *Data,
+    IN u8 *pTxData,
+    IN u32 Length
+);
+
+_LONG_CALL_ HAL_Status
+HalRuartStopRecvRtl8195a_V04(
+    IN VOID *Data
+);
+
+_LONG_CALL_ HAL_Status
+HalRuartStopSendRtl8195a_V04(
+    IN VOID *Data
+);
+
+_LONG_CALL_ VOID
+HalRuartEnterCriticalRtl8195a_V04(
+    IN VOID *Data
+);
+
+_LONG_CALL_ VOID
+HalRuartExitCriticalRtl8195a_V04(
+    IN VOID *Data
+);
+
+#endif  // #if CONFIG_CHIP_E_CUT
+
+#endif

sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_usb.h

@@ -0,0 +1,111 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _RTL8195A_USB_H_
+#define _RTL8195A_USB_H_
+
+
+// common command for USB
+#define USB_CMD_TX_ETH         0x83    // request to TX a 802.3 packet
+#define USB_CMD_TX_WLN         0x81    // request to TX a 802.11 packet
+#define USB_CMD_H2C            0x11    // H2C(host to device) command packet
+#define USB_CMD_MEMRD          0x51    // request to read a block of memory data
+#define USB_CMD_MEMWR          0x53    // request to write a block of memory
+#define USB_CMD_MEMST          0x55    // request to set a block of memory with a value
+#define USB_CMD_STARTUP        0x61    // request to jump to the start up function
+
+#define USB_CMD_RX_ETH         0x82    // indicate a RX 802.3 packet
+#define USB_CMD_RX_WLN         0x80    // indicate a RX 802.11 packet
+#define USB_CMD_C2H            0x10    // C2H(device to host) command packet
+#define USB_CMD_MEMRD_RSP      0x50    // response to memory block read command
+#define USB_CMD_MEMWR_RSP      0x52    // response to memory write command
+#define USB_CMD_MEMST_RSP      0x54    // response to memory set command
+#define USB_CMD_STARTED        0x60    // indicate the program has jumped to the given function
+
+
+// TODO: This data structer just for test, we should modify it for the normal driver
+typedef struct _USB_TX_DESC{
+	// u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	txpktsize:16;       // bit[15:0]
+	u32	offset:8;    		// bit[23:16], store the sizeof(SDIO_TX_DESC)
+	u32	bus_agg_num:8;		// bit[31:24], the bus aggregation number
+#else
+    u32 bus_agg_num:8;      // bit[31:24], the bus aggregation number
+    u32 offset:8;           // bit[23:16], store the sizeof(SDIO_TX_DESC)
+    u32 txpktsize:16;       // bit[15:0]
+#endif
+
+	// u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+    u32 type:8;             // bit[7:0], the packet type
+    u32 rsvd0:24;
+#else
+    u32 rsvd0:24;
+    u32 type:8;             // bit[7:0], the packet type
+#endif
+
+	// u4Byte 2
+	u32	rsvd1;
+	
+	// u4Byte 3
+	u32	rsvd2;
+	
+	// u4Byte 4
+	u32	rsvd3;
+
+	// u4Byte 5
+	u32	rsvd4;
+} USB_TX_DESC, *PUSB_TX_DESC;
+
+#define SIZE_USB_TX_DESC	sizeof(USB_TX_DESC)
+
+// TODO: This data structer just for test, we should modify it for the normal driver
+typedef struct _USB_RX_DESC{
+	// u4Byte 0
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	pkt_len:16;     // bit[15:0], the packet size
+	u32	offset:8;    	// bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+	u32	rsvd0:6;        // bit[29:24]
+	u32	icv:1;          // bit[30], ICV error
+	u32	crc:1;          // bit[31], CRC error
+#else
+	u32	crc:1;          // bit[31], CRC error
+	u32	icv:1;          // bit[30], ICV error
+	u32	rsvd0:6;        // bit[29:24]
+	u32	offset:8;    	// bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
+	u32	pkt_len:16;     // bit[15:0], the packet size
+#endif
+
+	// u4Byte 1
+#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
+	u32	type:8;         // bit[7:0], the type of this packet
+	u32	rsvd1:24;       // bit[31:8]
+#else
+    u32 rsvd1:24;       // bit[31:8]
+    u32 type:8;         // bit[7:0], the type of this packet
+#endif
+
+	// u4Byte 2
+	u32	rsvd2;
+	
+	// u4Byte 3
+	u32	rsvd3;
+	
+	// u4Byte 4
+	u32	rsvd4;
+
+	// u4Byte 5
+	u32	rsvd5;
+} USB_RX_DESC, *PUSB_RX_DESC;
+
+#define SIZE_USB_RX_DESC	sizeof(USB_RX_DESC)
+
+#endif	// #ifndef _RTL8195A_USB_H_
+

sdk/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_wdt.h

@@ -0,0 +1,86 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2014 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _RTL8195A_WDT_H_
+#define _RTL8195A_WDT_H_
+
+#define WDGTIMERELY  (10*1024)  //us
+
+typedef struct _WDG_REG_ {
+    u16     WdgScalar;
+    u8      WdgEnByte;
+    u8      WdgClear:1;
+    u8      WdgCunLimit:4;
+    u8      Rsvd:1;
+    u8      WdgMode:1;
+    u8      WdgToISR:1;
+}WDG_REG, *PWDG_REG;
+
+typedef struct _WDG_ADAPTER_ {
+
+    WDG_REG             Ctrl;
+    IRQ_HANDLE          IrqHandle;
+    TIMER_ADAPTER       WdgGTimer;
+    VOID (*UserCallback)(u32 callback_id);    // User callback function
+    u32                 callback_id;
+}WDG_ADAPTER, *PWDG_ADAPTER;
+
+typedef enum _WDG_CNTLMT_ {
+    CNT1H    = 0,
+    CNT3H    = 1,
+    CNT7H    = 2,
+    CNTFH    = 3,
+    CNT1FH   = 4,
+    CNT3FH   = 5,
+    CNT7FH   = 6,
+    CNTFFH   = 7,
+    CNT1FFH  = 8,
+    CNT3FFH  = 9,
+    CNT7FFH  = 10,
+    CNTFFFH  = 11
+}WDG_CNTLMT, *PWDG_CNTLMT;
+
+
+typedef enum _WDG_MODE_ {
+    INT_MODE    = 0,
+    RESET_MODE  = 1
+}WDG_MODE, *PWDG_MODE;
+
+extern VOID
+WDGInitial(
+    IN  u32 Period
+);
+
+extern VOID
+WDGIrqInitial(
+    VOID
+);
+
+extern VOID
+WDGIrqInitial(
+    VOID
+);
+
+extern VOID
+WDGStop(
+    VOID
+);
+
+extern VOID
+WDGRefresh(
+    VOID
+);
+
+extern VOID
+WDGIrqCallBackReg(
+    IN VOID *CallBack,
+    IN u32   Id
+);
+
+#endif //_RTL8195A_WDT_H_