j3d1/RTL00_WEB
1
0
Fork 0
mirror of https://github.com/pvvx/RTL00_WEB.git synced 2024-11-25 07:24:18 +00:00
Code Issues Projects Releases Packages Wiki Activity

update

Browse source
This commit is contained in:
pvvx 2017-07-30 09:01:39 +03:00
parent 09a4286889
commit fb8cc58058
15 changed files with 60 additions and 38 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
.cproject
View file

@ -668,10 +668,10 @@
</target> </target>
<target name="reset" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder"> <target name="reset" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>mingw32-make.exe</buildCommand> <buildCommand>mingw32-make.exe</buildCommand>
<buildArguments/> <buildArguments>-s</buildArguments>
<buildTarget>reset</buildTarget> <buildTarget>reset</buildTarget>
<stopOnError>true</stopOnError> <stopOnError>true</stopOnError>
<useDefaultCommand>false</useDefaultCommand> <useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>false</runAllBuilders> <runAllBuilders>false</runAllBuilders>
</target> </target>
<target name="test" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder"> <target name="test" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">

6
USDK/component/common/mbed/targets/hal/rtl8195a/sys_api.c
View file

@ -38,12 +38,13 @@ extern VOID HalJtagPinOff(VOID);
extern void HalInitLogUart(void); extern void HalInitLogUart(void);
extern void HalDeinitLogUart(void); extern void HalDeinitLogUart(void);
/*
#ifdef CONFIG_SDR_EN #ifdef CONFIG_SDR_EN
//#if defined ( __ICCARM__ ) //#if defined ( __ICCARM__ )
extern u8 IsSdrPowerOn(); extern u8 IsSdrPowerOn();
//#endif //#endif
#endif #endif
*/
/** /**
* @brief Turn off the JTAG function * @brief Turn off the JTAG function
* *
@ -203,12 +204,12 @@ void sys_reset(void)
(1 << 2)); // SYSRESETREQ (1 << 2)); // SYSRESETREQ
} }
/*
#ifdef CONFIG_SDR_EN #ifdef CONFIG_SDR_EN
u8 sys_is_sdram_power_on(void) u8 sys_is_sdram_power_on(void)
{ {
return IsSdrPowerOn(); return IsSdrPowerOn();
} }
void sys_sdram_off(void) void sys_sdram_off(void)
{ {
if (IsSdrPowerOn()) { if (IsSdrPowerOn()) {
@ -216,3 +217,4 @@ void sys_sdram_off(void)
} }
} }
#endif #endif
*/

6
USDK/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c
View file

@ -568,7 +568,7 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
//----- SDRAM Off //----- SDRAM Off
SDR_PIN_FCTRL(OFF); SDR_PIN_FCTRL(OFF);
LDO25M_CTRL(OFF); LDO25M_CTRL(OFF);
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init
} else { } else {
//----- SDRAM On //----- SDRAM On
LDO25M_CTRL(ON); LDO25M_CTRL(ON);
@ -580,7 +580,7 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
DBG_8195A("Spic Init Error!\n"); DBG_8195A("Spic Init Error!\n");
RtlConsolRam(); RtlConsolRam();
}; };
if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена? if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // Flag SDRAM Init?
// extern DRAM_DEVICE_INFO SdrDramInfo_rom; // 50 MHz // extern DRAM_DEVICE_INFO SdrDramInfo_rom; // 50 MHz
if (!SdrControllerInit_rom(&SdrDramInfo)) { // 100 MHz if (!SdrControllerInit_rom(&SdrDramInfo)) { // 100 MHz
DBG_8195A("SDR Controller Init fail!\n"); DBG_8195A("SDR Controller Init fail!\n");
@ -604,7 +604,7 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
DBG_8195A("SDR tst end\n"); DBG_8195A("SDR tst end\n");
}; };
#endif // test #endif // test
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init
}; };
if (!flg) if (!flg)

2
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h
View file

@ -24,7 +24,7 @@
//2 REG_NOT_VALID //2 REG_NOT_VALID
//2 REG_SOC_FUNC_EN //2 REG_SOC_FUNC_EN
// BIT(21) SDRAM // BIT(21) = 1 -> SDRAM Init
#define BIT_SOC_SECURITY_ENGINE_EN BIT(20) #define BIT_SOC_SECURITY_ENGINE_EN BIT(20)
#define BIT_SOC_GTIMER_EN BIT(16) #define BIT_SOC_GTIMER_EN BIT(16)
#define BIT_SOC_GDMA1_EN BIT(14) #define BIT_SOC_GDMA1_EN BIT(14)

2
USDK/component/soc/realtek/8195a/fwlib/src/bitband_io.c
View file

@ -41,7 +41,9 @@ volatile uint8_t * HardSetPin(PinName pin, HAL_GPIO_PIN_MODE pmode, uint8_t val)
if(_pHAL_Gpio_Adapter->Gpio_Func_En == 0) GPIO_FuncOn_8195a(); if(_pHAL_Gpio_Adapter->Gpio_Func_En == 0) GPIO_FuncOn_8195a();
delayMicroseconds(100); delayMicroseconds(100);
// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4); // paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
#if CONFIG_DEBUG_LOG > 3
GpioFunctionChk(ippin, ENABLE); GpioFunctionChk(ippin, ENABLE);
#endif
GPIO_PullCtrl_8195a(ippin, HAL_GPIO_HIGHZ); // Make the pin pull control default as High-Z GPIO_PullCtrl_8195a(ippin, HAL_GPIO_HIGHZ); // Make the pin pull control default as High-Z
paddr = BitBandPeriAddr((void *)(GPIO_REG_BASE + GPIO_PORTB_DR * (ippin >> 5)), ippin & 0x1f); paddr = BitBandPeriAddr((void *)(GPIO_REG_BASE + GPIO_PORTB_DR * (ippin >> 5)), ippin & 0x1f);
*paddr = val; // data register *paddr = val; // data register

14
USDK/component/soc/realtek/8195a/fwlib/src/hal_gpio.c
View file

@ -95,6 +95,7 @@ HAL_GPIO_Init(
port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name); port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name); pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num); chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num);
#if CONFIG_DEBUG_LOG > 3
if (GpioFunctionChk(chip_pin, ENABLE) == _FALSE) { if (GpioFunctionChk(chip_pin, ENABLE) == _FALSE) {
// if((chip_pin > 0x03) && (chip_pin != 0x25)) { // if((chip_pin > 0x03) && (chip_pin != 0x25)) {
DBG_GPIO_ERR("HAL_GPIO_Init: GPIO Pin(%x) Unavailable\n ", chip_pin); DBG_GPIO_ERR("HAL_GPIO_Init: GPIO Pin(%x) Unavailable\n ", chip_pin);
@ -102,15 +103,16 @@ HAL_GPIO_Init(
// } // }
// else DBG_GPIO_WARN("HAL_GPIO_Init: GPIO Pin(%x) Warning for RTL8710AF!\n ", chip_pin); // else DBG_GPIO_WARN("HAL_GPIO_Init: GPIO Pin(%x) Warning for RTL8710AF!\n ", chip_pin);
} }
#endif
// Make the pin pull control default as High-Z // Make the pin pull control default as High-Z
GPIO_PullCtrl_8195a(chip_pin, HAL_GPIO_HIGHZ); GPIO_PullCtrl_8195a(chip_pin, HAL_GPIO_HIGHZ);
ret = HAL_GPIO_Init_8195a(GPIO_Pin); ret = HAL_GPIO_Init_8195a(GPIO_Pin);
#if CONFIG_DEBUG_LOG > 3
if (ret != HAL_OK) { if (ret != HAL_OK) {
GpioFunctionChk(chip_pin, DISABLE); GpioFunctionChk(chip_pin, DISABLE);
} }
#endif
} }
/** /**
@ -146,18 +148,21 @@ HAL_GPIO_Irq_Init(
port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name); port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name); pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num); chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num);
#if CONFIG_DEBUG_LOG > 3
if (GpioFunctionChk(chip_pin, ENABLE) == _FALSE) { if (GpioFunctionChk(chip_pin, ENABLE) == _FALSE) {
DBG_GPIO_ERR("HAL_GPIO_Irq_Init: GPIO Pin(%x) Unavailable\n ", chip_pin); DBG_GPIO_ERR("HAL_GPIO_Irq_Init: GPIO Pin(%x) Unavailable\n ", chip_pin);
return; return;
} }
#endif
DBG_GPIO_INFO("HAL_GPIO_Irq_Init: GPIO(name=0x%x)(mode=%d)\n ", GPIO_Pin->pin_name, DBG_GPIO_INFO("HAL_GPIO_Irq_Init: GPIO(name=0x%x)(mode=%d)\n ", GPIO_Pin->pin_name,
GPIO_Pin->pin_mode); GPIO_Pin->pin_mode);
HAL_GPIO_MaskIrq_8195a(GPIO_Pin); HAL_GPIO_MaskIrq_8195a(GPIO_Pin);
ret = HAL_GPIO_Init_8195a(GPIO_Pin); ret = HAL_GPIO_Init_8195a(GPIO_Pin);
#if CONFIG_DEBUG_LOG > 3
if (ret != HAL_OK) { if (ret != HAL_OK) {
GpioFunctionChk(chip_pin, DISABLE); GpioFunctionChk(chip_pin, DISABLE);
} }
#endif
} }
/** /**
@ -199,8 +204,9 @@ HAL_GPIO_DeInit(
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name); pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num); chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num);
HAL_GPIO_DeInit_8195a(GPIO_Pin); HAL_GPIO_DeInit_8195a(GPIO_Pin);
#if CONFIG_DEBUG_LOG > 3
GpioFunctionChk(chip_pin, DISABLE); GpioFunctionChk(chip_pin, DISABLE);
#endif
} }

5
USDK/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c
View file

@ -207,6 +207,10 @@ SDRSleep(
HAL_WRITE32(0x40005000, 0X10, HAL_READ32(0x40005000, 0x10)|BIT28); HAL_WRITE32(0x40005000, 0X10, HAL_READ32(0x40005000, 0x10)|BIT28);
ACTCK_SDR_CCTRL(OFF); ACTCK_SDR_CCTRL(OFF);
GPIOState[PORT_G] = 0;
GPIOState[PORT_J] = 0;
gpio_init(&gpio_obj, PG_1); gpio_init(&gpio_obj, PG_1);
gpio_mode(&gpio_obj, PullUp); gpio_mode(&gpio_obj, PullUp);
gpio_dir(&gpio_obj, PIN_OUTPUT); gpio_dir(&gpio_obj, PIN_OUTPUT);
@ -243,6 +247,7 @@ SDRSleep(
gpio_mode(&gpio_obj, PullUp); gpio_mode(&gpio_obj, PullUp);
gpio_dir(&gpio_obj, PIN_OUTPUT); gpio_dir(&gpio_obj, PIN_OUTPUT);
gpio_write(&gpio_obj, GPIO_PIN_LOW); gpio_write(&gpio_obj, GPIO_PIN_LOW);
} }
#endif #endif

22
USDK/component/soc/realtek/8195a/misc/os/freertos_pmu_8195a.c
View file

@ -74,8 +74,7 @@ void freertos_pre_sleep_processing(unsigned int *expected_idle_time) {
uint32_t tick_after_sleep; uint32_t tick_after_sleep;
uint32_t tick_passed; uint32_t tick_passed;
uint32_t backup_systick_reg; uint32_t backup_systick_reg;
unsigned char IsDramOn = 1; unsigned char suspend_sdram;
unsigned char suspend_sdram = 1;
/* To disable freertos sleep function and use our sleep function, /* To disable freertos sleep function and use our sleep function,
* we can set original expected idle time to 0. */ * we can set original expected idle time to 0. */
@ -91,21 +90,18 @@ void freertos_pre_sleep_processing(unsigned int *expected_idle_time) {
// Store gtimer timestamp before sleep // Store gtimer timestamp before sleep
tick_before_sleep = us_ticker_read(); tick_before_sleep = us_ticker_read();
if ( sys_is_sdram_power_on() == 0 ) { backup_systick_reg = portNVIC_SYSTICK_CURRENT_VALUE_REG;
IsDramOn = 0;
}
if (IsDramOn) {
#if defined(FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM) && (FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM==0) #if defined(FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM) && (FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM==0)
// sdram is turned on, and we don't want suspend sdram suspend_sdram = 0;
#else
#ifdef CONFIG_SDR_EN
extern u8 IsSdrPowerOn();
suspend_sdram = IsSdrPowerOn(); // = 0 if SDRAM уже init
#else
suspend_sdram = 0; suspend_sdram = 0;
#endif #endif
} else { #endif
// sdram didn't turned on, we should not suspend it
suspend_sdram = 0;
}
backup_systick_reg = portNVIC_SYSTICK_CURRENT_VALUE_REG;
// sleep // sleep
sleep_ex_selective(wakeup_event, stime, reserve_pll, suspend_sdram); sleep_ex_selective(wakeup_event, stime, reserve_pll, suspend_sdram);

2
project/inc/platform_autoconf.h
View file

@ -156,7 +156,7 @@
#undef CONFIG_SPIC_TEST #undef CONFIG_SPIC_TEST
#define CONFIG_SPIC_MODULE 1 #define CONFIG_SPIC_MODULE 1
#define CONFIG_ADC_EN 1 #define CONFIG_ADC_EN 1
//#define CONFIG_DAC_EN 1 #define CONFIG_DAC_EN 1
#define CONFIG_NOR_FLASH 1 #define CONFIG_NOR_FLASH 1
#undef CONFIG_SPI_FLASH #undef CONFIG_SPI_FLASH
#undef CONFIG_NAND_FLASH #undef CONFIG_NAND_FLASH

2
project/inc/platform_opts.h
View file

@ -39,7 +39,7 @@
* For FreeRTOS tickless configurations * For FreeRTOS tickless configurations
*/ */
#define FREERTOS_PMU_TICKLESS_PLL_RESERVED 0 // In sleep mode, 0: close PLL clock, 1: reserve PLL clock #define FREERTOS_PMU_TICKLESS_PLL_RESERVED 0 // In sleep mode, 0: close PLL clock, 1: reserve PLL clock
#define FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM 1 // In sleep mode, 1: suspend SDRAM, 0: no act #define FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM 0 // In sleep mode, 1: suspend SDRAM, 0: no act
/******************************************************************************/ /******************************************************************************/

11
project/src/console/atcmd_user.c
View file

@ -283,6 +283,16 @@ LOCAL void fATLW(int argc, char *argv[]) // Info Lwip
print_udp_pcb(); print_udp_pcb();
print_tcp_pcb(); print_tcp_pcb();
} }
//------------------------------------------------------------------------------
// GPIO Info
//------------------------------------------------------------------------------
LOCAL void fATGI(int argc, char *argv[])
{
int i;
for (i = 0; i < _PORT_MAX; i++)
printf("Port %c state: 0x%04x\n", i + 'A', GPIOState[i]);
}
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
// Deep sleep // Deep sleep
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
@ -350,6 +360,7 @@ LOCAL void fATSP(int argc, char *argv[])
MON_RAM_TAB_SECTION COMMAND_TABLE console_commands_at[] = { MON_RAM_TAB_SECTION COMMAND_TABLE console_commands_at[] = {
{"ATST", 0, fATST, ": Memory info"}, {"ATST", 0, fATST, ": Memory info"},
{"ATLW", 0, fATLW, ": LwIP Info"}, {"ATLW", 0, fATLW, ": LwIP Info"},
{"ATGI", 0, fATGI, ": GPIO Info"},
{"ATSB", 1, fATSB, "=<ADDRES(hex)>[,COUNT(dec)]: Dump byte register"}, {"ATSB", 1, fATSB, "=<ADDRES(hex)>[,COUNT(dec)]: Dump byte register"},
{"ATSD", 1, fATSD, "=<ADDRES(hex)>[,COUNT(dec)]: Dump dword register"}, {"ATSD", 1, fATSD, "=<ADDRES(hex)>[,COUNT(dec)]: Dump dword register"},
{"ATSW", 2, fATSW, "=<ADDRES(hex)>,<DATA(hex)>: Set register"}, {"ATSW", 2, fATSW, "=<ADDRES(hex)>,<DATA(hex)>: Set register"},

2
project/src/console/flash_tst.c
View file

@ -30,7 +30,7 @@ LOCAL void FlashDump(int argc, char *argv[]) {
} }
MON_RAM_TAB_SECTION COMMAND_TABLE console_flash_tst[] = { MON_RAM_TAB_SECTION COMMAND_TABLE console_flash_tst[] = {
{"FLASHDB", 1, FlashDump, ": <faddr(HEX)>[,size]: Flash Dump"} {"FLASHDB", 1, FlashDump, "=<faddr(HEX)>[,size]: Flash Dump"}
}; };

4
project/src/console/sd_fat.c
View file

@ -377,8 +377,8 @@ LOCAL void fATHS(int argc, char *argv[]) {
MON_RAM_TAB_SECTION COMMAND_TABLE console_commands_dscard[] = { MON_RAM_TAB_SECTION COMMAND_TABLE console_commands_dscard[] = {
{"ATHS", 0, fATHS, ": SD test"}, {"ATHS", 0, fATHS, "=[dir]: SD test"},
{"ATHF", 0, fATHF, ": SD file read"} {"ATHF", 0, fATHF, "=[dir]: SD file read"}
}; };
#endif // CONFIG_SDIO_HOST_EN #endif // CONFIG_SDIO_HOST_EN

2
project/src/console/spi_tst.c
View file

@ -79,5 +79,5 @@ LOCAL void fATSSI(int argc, char *argv[])
} }
MON_RAM_TAB_SECTION COMMAND_TABLE console_commands_spitst[] = { MON_RAM_TAB_SECTION COMMAND_TABLE console_commands_spitst[] = {
{"ATSSI", 0, fATSSI, "[len[,count[,clk[,ssn]]]]: Spi test"} {"ATSSI", 0, fATSSI, "=[len[,count[,clk[,ssn]]]]: Spi test"}
}; };

4
userset.mk
View file

@ -6,8 +6,8 @@ SDK_PATH = USDK/
#GCC_PATH = d:/MCU/GNU_Tools_ARM_Embedded/6.2017-q1-update/bin/# + or set in PATH #GCC_PATH = d:/MCU/GNU_Tools_ARM_Embedded/6.2017-q1-update/bin/# + or set in PATH
OPENOCD_PATH = D:/MCU/OpenOCD/bin/ OPENOCD_PATH = D:/MCU/OpenOCD/bin/
TOOLS_PATH ?= $(SDK_PATH)component/soc/realtek/8195a/misc/iar_utility/common/tools/ TOOLS_PATH ?= $(SDK_PATH)component/soc/realtek/8195a/misc/iar_utility/common/tools/
#FLASHER_TYPE = Jlink FLASHER_TYPE = Jlink
FLASHER_TYPE = cmsis-dap #FLASHER_TYPE = cmsis-dap
FLASHER_SPEED = 3500 FLASHER_SPEED = 3500
FLASHER_PATH = flasher/ FLASHER_PATH = flasher/
JLINK_PATH ?= D:/MCU/SEGGER/JLink_V612i/ JLINK_PATH ?= D:/MCU/SEGGER/JLink_V612i/