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pvvx 2017-07-30 09:01:39 +03:00
parent 09a4286889
commit fb8cc58058
15 changed files with 60 additions and 38 deletions
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6
USDK/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c
View file

@ -568,7 +568,7 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
//----- SDRAM Off
SDR_PIN_FCTRL(OFF);
LDO25M_CTRL(OFF);
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init
} else {
//----- SDRAM On
LDO25M_CTRL(ON);
@ -580,7 +580,7 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
DBG_8195A("Spic Init Error!\n");
RtlConsolRam();
};
if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена?
if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // Flag SDRAM Init?
// extern DRAM_DEVICE_INFO SdrDramInfo_rom; // 50 MHz
if (!SdrControllerInit_rom(&SdrDramInfo)) { // 100 MHz
DBG_8195A("SDR Controller Init fail!\n");
@ -604,7 +604,7 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
DBG_8195A("SDR tst end\n");
};
#endif // test
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21));
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init
};
if (!flg)

2
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h
View file

@ -24,7 +24,7 @@
//2 REG_NOT_VALID
//2 REG_SOC_FUNC_EN
// BIT(21) SDRAM
// BIT(21) = 1 -> SDRAM Init
#define BIT_SOC_SECURITY_ENGINE_EN BIT(20)
#define BIT_SOC_GTIMER_EN BIT(16)
#define BIT_SOC_GDMA1_EN BIT(14)

2
USDK/component/soc/realtek/8195a/fwlib/src/bitband_io.c
View file

@ -41,7 +41,9 @@ volatile uint8_t * HardSetPin(PinName pin, HAL_GPIO_PIN_MODE pmode, uint8_t val)
if(_pHAL_Gpio_Adapter->Gpio_Func_En == 0) GPIO_FuncOn_8195a();
delayMicroseconds(100);
// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
#if CONFIG_DEBUG_LOG > 3
GpioFunctionChk(ippin, ENABLE);
#endif
GPIO_PullCtrl_8195a(ippin, HAL_GPIO_HIGHZ); // Make the pin pull control default as High-Z
paddr = BitBandPeriAddr((void *)(GPIO_REG_BASE + GPIO_PORTB_DR * (ippin >> 5)), ippin & 0x1f);
*paddr = val; // data register

16
USDK/component/soc/realtek/8195a/fwlib/src/hal_gpio.c
View file

@ -95,6 +95,7 @@ HAL_GPIO_Init(
port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num);
#if CONFIG_DEBUG_LOG > 3
if (GpioFunctionChk(chip_pin, ENABLE) == _FALSE) {
// if((chip_pin > 0x03) && (chip_pin != 0x25)) {
DBG_GPIO_ERR("HAL_GPIO_Init: GPIO Pin(%x) Unavailable\n ", chip_pin);
@ -102,15 +103,16 @@ HAL_GPIO_Init(
// }
// else DBG_GPIO_WARN("HAL_GPIO_Init: GPIO Pin(%x) Warning for RTL8710AF!\n ", chip_pin);
}
#endif
// Make the pin pull control default as High-Z
GPIO_PullCtrl_8195a(chip_pin, HAL_GPIO_HIGHZ);
ret = HAL_GPIO_Init_8195a(GPIO_Pin);
#if CONFIG_DEBUG_LOG > 3
if (ret != HAL_OK) {
GpioFunctionChk(chip_pin, DISABLE);
}
#endif
}
/**
@ -146,18 +148,21 @@ HAL_GPIO_Irq_Init(
port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num);
#if CONFIG_DEBUG_LOG > 3
if (GpioFunctionChk(chip_pin, ENABLE) == _FALSE) {
DBG_GPIO_ERR("HAL_GPIO_Irq_Init: GPIO Pin(%x) Unavailable\n ", chip_pin);
return;
}
#endif
DBG_GPIO_INFO("HAL_GPIO_Irq_Init: GPIO(name=0x%x)(mode=%d)\n ", GPIO_Pin->pin_name,
GPIO_Pin->pin_mode);
HAL_GPIO_MaskIrq_8195a(GPIO_Pin);
ret = HAL_GPIO_Init_8195a(GPIO_Pin);
#if CONFIG_DEBUG_LOG > 3
if (ret != HAL_OK) {
GpioFunctionChk(chip_pin, DISABLE);
}
}
#endif
}
/**
@ -199,8 +204,9 @@ HAL_GPIO_DeInit(
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num);
HAL_GPIO_DeInit_8195a(GPIO_Pin);
#if CONFIG_DEBUG_LOG > 3
GpioFunctionChk(chip_pin, DISABLE);
#endif
}

5
USDK/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c
View file

@ -207,6 +207,10 @@ SDRSleep(
HAL_WRITE32(0x40005000, 0X10, HAL_READ32(0x40005000, 0x10)|BIT28);
ACTCK_SDR_CCTRL(OFF);
GPIOState[PORT_G] = 0;
GPIOState[PORT_J] = 0;
gpio_init(&gpio_obj, PG_1);
gpio_mode(&gpio_obj, PullUp);
gpio_dir(&gpio_obj, PIN_OUTPUT);
@ -243,6 +247,7 @@ SDRSleep(
gpio_mode(&gpio_obj, PullUp);
gpio_dir(&gpio_obj, PIN_OUTPUT);
gpio_write(&gpio_obj, GPIO_PIN_LOW);
}
#endif