mirror of
https://github.com/pvvx/RTL00_WEB.git
synced 2024-11-22 05:54:19 +00:00
update
This commit is contained in:
pvvx
parent
20d954e09e
commit
de758bfdb3
10 changed files with 175 additions and 84 deletions
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@ -738,6 +738,14 @@
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<useDefaultCommand>true</useDefaultCommand>
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<runAllBuilders>false</runAllBuilders>
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</target>
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<target name="flashboot" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
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<buildCommand>mingw32-make.exe</buildCommand>
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<buildArguments>-s</buildArguments>
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<buildTarget>flashboot</buildTarget>
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<stopOnError>true</stopOnError>
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<useDefaultCommand>true</useDefaultCommand>
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<runAllBuilders>true</runAllBuilders>
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</target>
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</buildTargets>
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</storageModule>
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</cproject>
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@ -18,7 +18,7 @@ var gu = new Dygraph(
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{
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labels: ['X', 'I', 'U'],
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// drawPoints: true,
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rollPeriod: 100,
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// rollPeriod: 10,
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// errorBars: true,
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// showRoller: true,
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ylabel: 'I(mA)',
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5
Makefile
5
Makefile
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@ -20,7 +20,10 @@ clean:
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clean_all:
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@$(MAKE) -f $(SDK_PATH)sdkbuild.mk clean_all
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.PHONY: flashburn runram reset test readfullflash flashwebfs
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.PHONY: flashburn runram reset test readfullflash flashwebfs flashboot
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flashboot:
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@$(MAKE) -f $(SDK_PATH)flasher.mk flashboot
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flashburn:
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#JLinkGDB-WrFlash.bat
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@$(MAKE) -f $(SDK_PATH)flasher.mk flashburn
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@ -20,20 +20,42 @@ clean:
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clean_all:
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@$(MAKE) -f $(SDK_PATH)sdkbuild.mk clean_all
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.PHONY: flashburn runram reset test readfullflash flashwebfs
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.PHONY: flashburn runram reset test readfullflash flashwebfs flashboot
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flashboot:
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@$(MAKE) -f $(SDK_PATH)flasher.mk flashboot
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flashburn:
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#JLinkGDB-WrFlash.bat
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@$(MAKE) -f $(SDK_PATH)flasher.mk flashburn
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flash_OTA:
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@$(MAKE) -f $(SDK_PATH)flasher.mk flash_OTA
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webfs:
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@$(MAKE) -f webfs.mk
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flashwebfs:
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@$(MAKE) -f webfs.mk
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@$(MAKE) -f $(SDK_PATH)flasher.mk flashwebfs
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#JLinkGDB-WrWebFs.bat
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runram:
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#JLink-RunRAM.bat
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@$(MAKE) --f $(SDK_PATH)flasher.mk runram
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runsdram:
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#JLink-RunRAM.bat
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@$(MAKE) --f $(SDK_PATH)flasher.mk runsdram
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reset:
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#JLink-Reset.bat
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@$(MAKE) -f $(SDK_PATH)flasher.mk reset
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test:
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JLink-RTL00ConsoleROM.bat
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#@make -f flasher.mk test
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readfullflash:
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#JLink-RdFullFlash.bat
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@$(MAKE) -f $(SDK_PATH)flasher.mk readfullflash
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@ -1,5 +1,5 @@
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/*
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* BootLoader Ver 0.2
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* BootLoader Ver 0.3 (18/10/2017)
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* Created on: 12/02/2017
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* Author: pvvx
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*/
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@ -31,7 +31,7 @@
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#define DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE (DEFAULT_BOOT_CLK_CPU-6)
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#endif
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#endif // DEFAULT_BOOT_CLK_CPU
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#define FIX_SDR_CALIBRATION // for speed
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#define FIX_SDR_CALIBRATION // for speed and low used SRAM
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#define BOOT_RAM_TEXT_SECTION // __attribute__((section(".boot.text")))
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//-------------------------------------------------------------------------
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@ -100,14 +100,14 @@ LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() {
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CfgSysDebugErr = -1;
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ConfigDebugWarn = -1;
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// ConfigDebugInfo = 0;
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ConfigDebugErr = ~_DBG_SDR_;
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ConfigDebugErr = -1; // ~_DBG_SDR_;
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#elif CONFIG_DEBUG_LOG > 0
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// CfgSysDebugWarn = 0;
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// CfgSysDebugInfo = 0;
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CfgSysDebugErr = -1;
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// ConfigDebugWarn = 0;
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// ConfigDebugInfo = 0;
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ConfigDebugErr = ~_DBG_SDR_;
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ConfigDebugErr = -1; // ~_DBG_SDR_;
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#else
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// CfgSysDebugWarn = 0;
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// CfgSysDebugInfo = 0;
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@ -125,15 +125,6 @@ LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) {
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HalPinCtrlRtl8195A(JTAG, 0, 1);
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}
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/* GetChipId() */
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LOCAL uint8 INFRA_START_SECTION _Get_ChipId() {
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uint8 ChipId = CHIP_ID_8710AF;
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if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
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&ChipId, L25EOUTVOLTAGE) != 1)
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DBG_8195A("Get Chip ID Failed\r");
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return ChipId;
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}
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/*
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* 16 bytes FIFO ... 16*11/38400 = 0.004583 sec
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* (0.005/5)*166666666 = 166666.666 Tcpu
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@ -286,32 +277,32 @@ LOCAL int BOOT_RAM_TEXT_SECTION InitSpic(uint8 SpicBitMode) {
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return SetSpicBitMode(SpicBitMode);
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}
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LOCAL void INFRA_START_SECTION sdr_preinit(void) {
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#ifdef CONFIG_SDR_EN
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LDO25M_CTRL(ON);
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HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
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((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); // ROM: BIT_SYS_REGU_LDO25M_ADJ(0x0e)?
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SRAM_MUX_CFG(0x2);
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SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE); // REG_PESOC_CLK_SEL
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HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4, 0);
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ACTCK_SDR_CCTRL(ON);
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SLPCK_SDR_CCTRL(ON);
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HalPinCtrlRtl8195A(SDR, 0, ON); // SDR_PIN_FCTRL(ON);
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HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4, 0);
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MEM_CTRL_FCTRL(ON);
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// HalDelayUs(3000);
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/* GetChipId() */
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LOCAL uint8 INFRA_START_SECTION _Get_ChipId() {
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uint8 ChipId = CHIP_ID_8710AF;
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if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
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&ChipId, L25EOUTVOLTAGE) != 1)
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DBG_8195A("Get Chip ID Failed\r");
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return ChipId;
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}
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LOCAL void INFRA_START_SECTION sdr_preinit(void) {
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HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
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((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); // ROM: BIT_SYS_REGU_LDO25M_ADJ(0x0e)? HAL RAM BIT_SYS_REGU_LDO25M_ADJ(0x03)
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LDO25M_CTRL(ON);
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SRAM_MUX_CFG(0x2);
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SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE); // REG_PESOC_CLK_SEL
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HalPinCtrlRtl8195A(SDR, 0, ON); // SDR_PIN_FCTRL(ON);
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ACTCK_SDR_CCTRL(ON);
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SLPCK_SDR_CCTRL(ON);
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HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4, 0);
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MEM_CTRL_FCTRL(ON);
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// HalDelayUs(1000);
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}
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#ifdef CONFIG_SDR_EN
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#ifndef FIX_SDR_CALIBRATION
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extern _LONG_CALL_ int SdrCalibration_rom(void);
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extern _LONG_CALL_ unsigned int Rand(void);
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@ -334,11 +325,21 @@ LOCAL int INFRA_START_SECTION sdr_test(u32 LoopCnt) {
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#endif
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LOCAL int INFRA_START_SECTION sdr_init_from_flash(void) {
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#define RdPipe 0
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#if DEFAULT_BOOT_CLK_CPU < 6
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#define TapCnt 0x11
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#elif DEFAULT_BOOT_CLK_CPU == 7
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#define TapCnt 0x23
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#else
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#define TapCnt 0x19
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#endif
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// set all_mode _idle
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HAL_SDR_WRITE32(REG_SDR_CSR, 0x700);
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// WRAP_MISC setting
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HAL_SDR_WRITE32(REG_SDR_MISC, 0x00000001);
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// PCTL setting
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HAL_SDR_WRITE32(REG_SDR_DCR, 0x00000008);
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HAL_SDR_WRITE32(REG_SDR_IOCR, 0x00000000);
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HAL_SDR_WRITE32(REG_SDR_IOCR, RdPipe << PCTL_IOCR_RD_PIPE_BFO);
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HAL_SDR_WRITE32(REG_SDR_EMR2, 0x00000000);
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HAL_SDR_WRITE32(REG_SDR_EMR1, 0x00000006);
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HAL_SDR_WRITE32(REG_SDR_MR, 0x00000022);
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@ -346,31 +347,14 @@ LOCAL int INFRA_START_SECTION sdr_init_from_flash(void) {
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HAL_SDR_WRITE32(REG_SDR_TPR0, 0x00002652);
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HAL_SDR_WRITE32(REG_SDR_TPR1, 0x00068873);
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HAL_SDR_WRITE32(REG_SDR_TPR2, 0x00000042);
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// set all_mode _idle
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HAL_SDR_WRITE32(REG_SDR_CSR, 0x700);
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// start to init
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HAL_SDR_WRITE32(REG_SDR_CCR, 0x01);
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DBG_8195A("SDR calibration: %02x-%02x\n", RdPipe, TapCnt);
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while ((HAL_SDR_READ32(REG_SDR_CCR) & 0x1) == 0x0);
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// enter mem_mode
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HAL_SDR_WRITE32(REG_SDR_CSR, 0x600);
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#ifdef FIX_SDR_CALIBRATION // for speed :)
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#if 0
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// read calibration data from system data FLASH_SDRC_PARA_BASE
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u32 reg = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1);
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u32 value = 0x00190031;
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if(reg & BIT17) value = 0x00060031;
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else if((reg & 0x70) == 0) value = 0x00230031;
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HAL_PERI_ON_WRITE32(REG_PESOC_MEM_CTRL, value);
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#else
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#if DEFAULT_BOOT_CLK_CPU < 6
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HAL_PERI_ON_WRITE32(REG_PESOC_MEM_CTRL, 0x00060031);
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#elif DEFAULT_BOOT_CLK_CPU == 7
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HAL_PERI_ON_WRITE32(REG_PESOC_MEM_CTRL, 0x00230031);
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#else
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HAL_PERI_ON_WRITE32(REG_PESOC_MEM_CTRL, 0x00190031);
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#endif
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#endif
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#ifdef FIX_SDR_CALIBRATION
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SDR_DDL_FCTRL(TapCnt); // SDR_DDL_FCTRL(0x11);
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return 1;
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#else
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union { u8 b[8]; u16 s[4]; u32 l[2]; u64 d;} value;
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@ -388,7 +372,7 @@ LOCAL int INFRA_START_SECTION sdr_init_from_flash(void) {
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DBG_8195A("Not valid SDR calibration in flash!\n");
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} else
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DBG_8195A("Error SDR calibration in flash!\n");
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if(SdrCalibration_rom()) {
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if(SdrCalibration_rom()) { // Внимание: дает завышенный TapCnt !
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// DBG_8195A("SDR calibration: %02x-%02x-%02x\n", value.b[0], value.b[4], value.b[6]);
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value.s[0] = 0xFE01;
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value.b[4] = HAL_SDR_READ32(REG_SDR_IOCR) >> PCTL_IOCR_RD_PIPE_BFO;
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@ -691,27 +675,31 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
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DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\n", HalGetCpuClk(),
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HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
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#endif
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#ifdef CONFIG_SDR_EN
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uint8 ChipId = _Get_ChipId();
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if (ChipId < CHIP_ID_8195AM) {
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#endif
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//----- SDRAM Off
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SDR_PIN_FCTRL(OFF);
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LDO25M_CTRL(OFF);
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#ifdef CONFIG_SDR_EN
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init or None
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} else {
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//----- SDRAM On
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sdr_preinit();
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};
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#endif
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if (!InitSpic(SpicDualBitMode)) {
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DBG_8195A("Spic Init fail!\n");
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RtlConsolRam();
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};
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#ifdef CONFIG_SDR_EN
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if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // Flag SDRAM No ReInit?
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if(!sdr_init_from_flash()) {
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DBG_8195A("SDR Init fail!\n");
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RtlConsolRam();
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}
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#if 0 // Test SDRAM
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#ifdef USE_SDRAM_TEST // Test SDRAM
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else {
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uint32 *ptr = (uint32 *)SDR_SDRAM_BASE;
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uint32 tt = 0x55AA55AA;
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@ -724,25 +712,26 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
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DBG_8195A("SDR err %p %p != %p!\n", &ptr[i], ptr[i], tt);
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RtlConsolRam();
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}
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// ptr[i] = 0;
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tt++;
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};
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DBG_8195A("SDR test end\n");
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DBG_8195A("SDR test ok\n");
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};
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#endif // Test SDRAM
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#ifdef CONFIG_SDR_EN
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// Тест и ожидание загрузки Jlink-ом sdram.bin (~7 sec)
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if(flg && *((uint32 *)0x1FFF0000) == 0x12345678) {
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*((volatile uint32 *)0x1FFF0000) = 0x87654321;
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uint32 tt = 0x03ffffff; // ~7 sec
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DBG_8195A("Waiting for SDRAM to load...\n");
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// __asm__ __volatile__ ("cpsid f\n");
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while(*((volatile uint32 *)0x1FFF0000) == 0x87654321 && tt--);
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// __asm__ __volatile__ ("cpsie f\n");
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if(*((volatile uint32 *)0x1FFF0000) == 1)
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DBG_8195A("SDRAM load ok\n");
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}
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#endif // CONFIG_SDR_EN
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM No ReInit
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};
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#endif // CONFIG_SDR_EN
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if (!flg)
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loadUserImges(IsForceLoadDefaultImg2() + 1);
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@ -1,5 +1,5 @@
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/*
|
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* StartUp SDK
|
||||
* StartUp USDK v0.2 (18/10/2017)
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||||
* Created on: 02/03/2017
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* Author: pvvx
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*/
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@ -41,6 +41,7 @@ void SDIO_Device_Off(void);
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//void VectorTableOverrideRtl8195A(u32 StackP);
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void SYSPlatformInit(void);
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|
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#define FIX_SDR_CALIBRATION // for speed :)
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//-------------------------------------------------------------------------
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// Data declarations
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extern u8 __bss_start__, __bss_end__;
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@ -50,6 +51,61 @@ extern const unsigned char cus_sig[32]; // images name
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IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 =
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{ InfraStart + 1 };
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|
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#ifdef FIX_SDR_CALIBRATION // for speed :)
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#include "rtl8195a/rtl8195a_sdr.h"
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LOCAL void sdr_init(void) {
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HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
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((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); // ROM: BIT_SYS_REGU_LDO25M_ADJ(0x0e)? HAL RAM BIT_SYS_REGU_LDO25M_ADJ(0x03)
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LDO25M_CTRL(ON);
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SRAM_MUX_CFG(0x2);
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SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE); // REG_PESOC_CLK_SEL
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HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4, 0);
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ACTCK_SDR_CCTRL(ON);
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SLPCK_SDR_CCTRL(ON);
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HalPinCtrlRtl8195A(SDR, 0, ON); // SDR_PIN_FCTRL(ON);
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MEM_CTRL_FCTRL(ON);
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// HalDelayUs(1000);
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// read calibration data from system data FLASH_SDRC_PARA_BASE
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union { u8 b[8]; u16 s[4]; u32 l[2]; u64 d;} value;
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u32 faddr = SPI_FLASH_BASE + FLASH_SDRC_PARA_BASE + CPU_CLOCK_SEL_VALUE*8 + CPU_CLOCK_SEL_DIV5_3*8*8; // step 8 in FLASH_SDRC_PARA_BASE[64 + 64 bytes]
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value.d = *((volatile u64 *)faddr);
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if(value.s[0] == 0xFE01 && (value.b[4]^value.b[5]) == 0xFF && (value.b[6]^value.b[7]) == 0xFF) {
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DBG_8195A("SDR flash calibration [%08x]: %02x-%02x ", faddr, value.b[4], value.b[6]);
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} else {
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value.b[4] = 0; // TapCnt
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#if CONFIG_CPU_CLK < 6
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value.b[6] = 0x11; // RdPipe
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#elif CONFIG_CPU_CLK == 7
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value.b[6] = 0x23; // RdPipe
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#else
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value.b[6] = 0x19; // RdPipe
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#endif
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DBG_8195A("Use fix SDR calibration: %02x-%02x ", value.b[4], value.b[6]);
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}
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// set all_mode _idle
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HAL_SDR_WRITE32(REG_SDR_CSR, 0x700);
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// WRAP_MISC setting
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HAL_SDR_WRITE32(REG_SDR_MISC, 0x00000001);
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// PCTL setting
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HAL_SDR_WRITE32(REG_SDR_DCR, 0x00000008);
|
||||
HAL_SDR_WRITE32(REG_SDR_IOCR, (u32)value.b[4] << PCTL_IOCR_RD_PIPE_BFO);
|
||||
HAL_SDR_WRITE32(REG_SDR_EMR2, 0x00000000);
|
||||
HAL_SDR_WRITE32(REG_SDR_EMR1, 0x00000006);
|
||||
HAL_SDR_WRITE32(REG_SDR_MR, 0x00000022);
|
||||
HAL_SDR_WRITE32(REG_SDR_DRR, 0x09030e07);
|
||||
HAL_SDR_WRITE32(REG_SDR_TPR0, 0x00002652);
|
||||
HAL_SDR_WRITE32(REG_SDR_TPR1, 0x00068873);
|
||||
HAL_SDR_WRITE32(REG_SDR_TPR2, 0x00000042);
|
||||
// start to init
|
||||
HAL_SDR_WRITE32(REG_SDR_CCR, 0x01);
|
||||
while ((HAL_SDR_READ32(REG_SDR_CCR) & 0x1) == 0x0)
|
||||
DBG_8195A(".");
|
||||
// enter mem_mode
|
||||
HAL_SDR_WRITE32(REG_SDR_CSR, 0x600);
|
||||
SDR_DDL_FCTRL((u32)value.b[6]);
|
||||
DBG_8195A(" ok\n");
|
||||
}
|
||||
#endif // FIX_SDR_CALIBRATION
|
||||
/*
|
||||
//----- HalNMIHandler_Patch
|
||||
void HalNMIHandler_Patch(void) {
|
||||
|
|
@ -167,34 +223,36 @@ extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
|
|||
};
|
||||
*/
|
||||
// SpicFlashInitRtl8195A(SpicDualBitMode); // SpicReadIDRtl8195A(); SpicDualBitMode
|
||||
#ifdef CONFIG_SDR_EN
|
||||
//---- SDRAM
|
||||
uint8 ChipId = HalGetChipId();
|
||||
if (ChipId >= CHIP_ID_8195AM) {
|
||||
#ifdef CONFIG_SDR_EN
|
||||
if((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // ещё не инициализирована?
|
||||
if((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // SDR not init?
|
||||
#ifdef FIX_SDR_CALIBRATION // for speed :)
|
||||
sdr_init();
|
||||
#else // not FIX_SDR_CALIBRATION
|
||||
SdrCtrlInit();
|
||||
if(!SdrControllerInit()) {
|
||||
DBG_8195A("SDR Controller Init fail!\n");
|
||||
};
|
||||
} else if (CPU_CLOCK_SEL_DIV5_3) { // clk 5/6
|
||||
if(((HAL_PERI_ON_READ32(REG_PESOC_MEM_CTRL) >> BIT_SHIFT_PESOC_SDR_DDL_CTRL) & 0xFF) < 0x15) {
|
||||
SDR_DDL_FCTRL(0x23);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif // FIX_SDR_CALIBRATION
|
||||
};
|
||||
// clear SDRAM bss
|
||||
extern uint8 __sdram_bss_start__[];
|
||||
extern uint8 __sdram_bss_end__[];
|
||||
if((uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__ > 0)
|
||||
memset(__sdram_bss_start__, 0, (uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__);
|
||||
}
|
||||
else
|
||||
else // if (ChipId < CHIP_ID_8195AM)
|
||||
{
|
||||
//----- SDRAM Off
|
||||
SDR_PIN_FCTRL(OFF);
|
||||
LDO25M_CTRL(OFF);
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off
|
||||
};
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init or None
|
||||
#else
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (~BIT(21))); // Flag SDRAM Not Init
|
||||
#endif // CONFIG_SDR_EN
|
||||
//----- Close Flash
|
||||
SPI_FLASH_PIN_FCTRL(OFF);
|
||||
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@ mp: OTA_IMAGE = $(BIN_DIR)/ota_mp.bin
|
|||
|
||||
TST_IMAGE = $(BIN_DIR)/ram_2.bin
|
||||
|
||||
.PHONY: genbin1 genbin23 flashburn reset test readfullflash flashwebfs flash_OTA runram runsdram
|
||||
.PHONY: genbin1 genbin23 flashburn reset test readfullflash flashboot flashwebfs flash_OTA runram runsdram
|
||||
.NOTPARALLEL: all mp genbin1 genbin23 flashburn reset test readfullflash _endgenbin flashwebfs flash_OTA
|
||||
|
||||
all: $(ELFFILE) $(OTA_IMAGE) $(FLASH_IMAGE) _endgenbin
|
||||
|
|
@ -137,6 +137,17 @@ flashburn:
|
|||
@$(GDB) -x $(FLASHER_PATH)gdb_wrflash.jlink
|
||||
#@taskkill /F /IM $(JLINK_GDBSRV)
|
||||
|
||||
flashboot:
|
||||
@echo define call1>$(FLASHER_PATH)file_info.jlink
|
||||
@echo set '$$'ImageSize = $(shell printf '0x%X\n' $$(stat --printf="%s" $(BIN_DIR)/ram_1.p.bin))>>$(FLASHER_PATH)file_info.jlink
|
||||
@echo set '$$'ImageAddr = 0x000000>>$(FLASHER_PATH)file_info.jlink
|
||||
@echo end>>$(FLASHER_PATH)file_info.jlink
|
||||
@echo define call2>>$(FLASHER_PATH)file_info.jlink
|
||||
@echo FlasherWrite $(BIN_DIR)/ram_1.p.bin '$$'ImageAddr '$$'ImageSize>>$(FLASHER_PATH)file_info.jlink
|
||||
@echo end>>$(FLASHER_PATH)file_info.jlink
|
||||
@cmd /K start $(JLINK_PATH)$(JLINK_GDBSRV) -device Cortex-M3 -if SWD -ir -endian little -speed 1000
|
||||
@$(GDB) -x $(FLASHER_PATH)gdb_wrfile.jlink
|
||||
|
||||
flashwebfs:
|
||||
@echo define call1>$(FLASHER_PATH)file_info.jlink
|
||||
@echo set '$$'ImageSize = $(shell printf '0x%X\n' $$(stat --printf="%s" $(BIN_DIR)/WEBFiles.bin))>>$(FLASHER_PATH)file_info.jlink
|
||||
|
|
|
|||
|
|
@ -7,6 +7,6 @@ r
|
|||
loadbin build/bin/ram_1.r.bin 0x10000bc8
|
||||
loadbin build/bin/ram_2.bin 0x10006000
|
||||
r
|
||||
w4 0x40000210,0x20111113
|
||||
w4 0x40000210,0x20011113
|
||||
g
|
||||
q
|
||||
|
|
@ -2,15 +2,15 @@ r0
|
|||
trst0
|
||||
r1
|
||||
trst1
|
||||
h
|
||||
r
|
||||
h
|
||||
loadbin build/bin/ram_1.r.bin 0x10000bc8
|
||||
loadbin build/bin/ram_2.bin 0x10006000
|
||||
r
|
||||
w4 0x40000210,0x20011113
|
||||
w4 0x1FFF0000,0x12345678
|
||||
g
|
||||
sleep 3000
|
||||
sleep 1000
|
||||
h
|
||||
loadbin build/bin/sdram.bin 0x30000000
|
||||
w4 0x1FFF0000,1
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
#define RTL8195A 1
|
||||
/* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz,
|
||||
6 - 200000000 Hz, 7 - 100000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */
|
||||
#define CONFIG_CPU_CLK 0
|
||||
#define CONFIG_CPU_CLK 1
|
||||
//166.6MHZ - RUN/IDLE/SLP ~63/21/6.4 mA
|
||||
//83.3MHZ - RUN/IDLE/SLP ~55/15/6.4 mA
|
||||
//41.6MHZ - RUN/IDLE ~51/11 mA
|
||||
|
|
|
|||
Loading…
Reference in a new issue