diff --git a/.cproject b/.cproject
index e7b0321..c56dbf4 100644
--- a/.cproject
+++ b/.cproject
@@ -738,6 +738,14 @@
true
false
+
+ mingw32-make.exe
+ -s
+ flashboot
+ true
+ true
+ true
+
diff --git a/ExampleHTM/dygraph/ws_test_ina219.html b/ExampleHTM/dygraph/ws_test_ina219.html
index d3ed900..69ecdd3 100644
--- a/ExampleHTM/dygraph/ws_test_ina219.html
+++ b/ExampleHTM/dygraph/ws_test_ina219.html
@@ -18,7 +18,7 @@ var gu = new Dygraph(
{
labels: ['X', 'I', 'U'],
// drawPoints: true,
- rollPeriod: 100,
+// rollPeriod: 10,
// errorBars: true,
// showRoller: true,
ylabel: 'I(mA)',
diff --git a/Makefile b/Makefile
index c53a064..5158de2 100644
--- a/Makefile
+++ b/Makefile
@@ -20,7 +20,10 @@ clean:
clean_all:
@$(MAKE) -f $(SDK_PATH)sdkbuild.mk clean_all
-.PHONY: flashburn runram reset test readfullflash flashwebfs
+.PHONY: flashburn runram reset test readfullflash flashwebfs flashboot
+flashboot:
+ @$(MAKE) -f $(SDK_PATH)flasher.mk flashboot
+
flashburn:
#JLinkGDB-WrFlash.bat
@$(MAKE) -f $(SDK_PATH)flasher.mk flashburn
diff --git a/USDK/Makefile b/USDK/Makefile
index ac92758..5158de2 100644
--- a/USDK/Makefile
+++ b/USDK/Makefile
@@ -5,7 +5,7 @@ mp: ram_all_mp
.PHONY: ram_all
ram_all:
- @$(MAKE) -f $(SDK_PATH)sdkbuild.mk
+ @$(MAKE) -f $(SDK_PATH)sdkbuild.mk
@$(MAKE) -f $(SDK_PATH)flasher.mk genbin1 genbin23
.PHONY: ram_all_mp
@@ -20,20 +20,42 @@ clean:
clean_all:
@$(MAKE) -f $(SDK_PATH)sdkbuild.mk clean_all
-.PHONY: flashburn runram reset test readfullflash flashwebfs
+.PHONY: flashburn runram reset test readfullflash flashwebfs flashboot
+flashboot:
+ @$(MAKE) -f $(SDK_PATH)flasher.mk flashboot
+
flashburn:
+ #JLinkGDB-WrFlash.bat
@$(MAKE) -f $(SDK_PATH)flasher.mk flashburn
flash_OTA:
@$(MAKE) -f $(SDK_PATH)flasher.mk flash_OTA
+
+webfs:
+ @$(MAKE) -f webfs.mk
+flashwebfs:
+ @$(MAKE) -f webfs.mk
+ @$(MAKE) -f $(SDK_PATH)flasher.mk flashwebfs
+ #JLinkGDB-WrWebFs.bat
runram:
+ #JLink-RunRAM.bat
@$(MAKE) --f $(SDK_PATH)flasher.mk runram
+runsdram:
+ #JLink-RunRAM.bat
+ @$(MAKE) --f $(SDK_PATH)flasher.mk runsdram
+
reset:
+ #JLink-Reset.bat
@$(MAKE) -f $(SDK_PATH)flasher.mk reset
+test:
+ JLink-RTL00ConsoleROM.bat
+ #@make -f flasher.mk test
+
readfullflash:
+ #JLink-RdFullFlash.bat
@$(MAKE) -f $(SDK_PATH)flasher.mk readfullflash
diff --git a/USDK/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c b/USDK/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c
index 914e5b6..5200357 100644
--- a/USDK/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c
+++ b/USDK/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c
@@ -1,5 +1,5 @@
/*
- * BootLoader Ver 0.2
+ * BootLoader Ver 0.3 (18/10/2017)
* Created on: 12/02/2017
* Author: pvvx
*/
@@ -31,7 +31,7 @@
#define DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE (DEFAULT_BOOT_CLK_CPU-6)
#endif
#endif // DEFAULT_BOOT_CLK_CPU
-#define FIX_SDR_CALIBRATION // for speed
+#define FIX_SDR_CALIBRATION // for speed and low used SRAM
#define BOOT_RAM_TEXT_SECTION // __attribute__((section(".boot.text")))
//-------------------------------------------------------------------------
@@ -100,14 +100,14 @@ LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() {
CfgSysDebugErr = -1;
ConfigDebugWarn = -1;
// ConfigDebugInfo = 0;
- ConfigDebugErr = ~_DBG_SDR_;
+ ConfigDebugErr = -1; // ~_DBG_SDR_;
#elif CONFIG_DEBUG_LOG > 0
// CfgSysDebugWarn = 0;
// CfgSysDebugInfo = 0;
CfgSysDebugErr = -1;
// ConfigDebugWarn = 0;
// ConfigDebugInfo = 0;
- ConfigDebugErr = ~_DBG_SDR_;
+ ConfigDebugErr = -1; // ~_DBG_SDR_;
#else
// CfgSysDebugWarn = 0;
// CfgSysDebugInfo = 0;
@@ -125,15 +125,6 @@ LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) {
HalPinCtrlRtl8195A(JTAG, 0, 1);
}
-/* GetChipId() */
-LOCAL uint8 INFRA_START_SECTION _Get_ChipId() {
- uint8 ChipId = CHIP_ID_8710AF;
- if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
- &ChipId, L25EOUTVOLTAGE) != 1)
- DBG_8195A("Get Chip ID Failed\r");
- return ChipId;
-}
-
/*
* 16 bytes FIFO ... 16*11/38400 = 0.004583 sec
* (0.005/5)*166666666 = 166666.666 Tcpu
@@ -286,32 +277,32 @@ LOCAL int BOOT_RAM_TEXT_SECTION InitSpic(uint8 SpicBitMode) {
return SetSpicBitMode(SpicBitMode);
}
-LOCAL void INFRA_START_SECTION sdr_preinit(void) {
+#ifdef CONFIG_SDR_EN
- LDO25M_CTRL(ON);
-
- HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
- ((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); // ROM: BIT_SYS_REGU_LDO25M_ADJ(0x0e)?
-
- SRAM_MUX_CFG(0x2);
-
- SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE); // REG_PESOC_CLK_SEL
-
- HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4, 0);
-
- ACTCK_SDR_CCTRL(ON);
- SLPCK_SDR_CCTRL(ON);
-
- HalPinCtrlRtl8195A(SDR, 0, ON); // SDR_PIN_FCTRL(ON);
-
- HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4, 0);
-
- MEM_CTRL_FCTRL(ON);
-
- // HalDelayUs(3000);
+/* GetChipId() */
+LOCAL uint8 INFRA_START_SECTION _Get_ChipId() {
+ uint8 ChipId = CHIP_ID_8710AF;
+ if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
+ &ChipId, L25EOUTVOLTAGE) != 1)
+ DBG_8195A("Get Chip ID Failed\r");
+ return ChipId;
+}
+
+LOCAL void INFRA_START_SECTION sdr_preinit(void) {
+
+ HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
+ ((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); // ROM: BIT_SYS_REGU_LDO25M_ADJ(0x0e)? HAL RAM BIT_SYS_REGU_LDO25M_ADJ(0x03)
+ LDO25M_CTRL(ON);
+ SRAM_MUX_CFG(0x2);
+ SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE); // REG_PESOC_CLK_SEL
+ HalPinCtrlRtl8195A(SDR, 0, ON); // SDR_PIN_FCTRL(ON);
+ ACTCK_SDR_CCTRL(ON);
+ SLPCK_SDR_CCTRL(ON);
+ HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4, 0);
+ MEM_CTRL_FCTRL(ON);
+// HalDelayUs(1000);
}
-#ifdef CONFIG_SDR_EN
#ifndef FIX_SDR_CALIBRATION
extern _LONG_CALL_ int SdrCalibration_rom(void);
extern _LONG_CALL_ unsigned int Rand(void);
@@ -334,11 +325,21 @@ LOCAL int INFRA_START_SECTION sdr_test(u32 LoopCnt) {
#endif
LOCAL int INFRA_START_SECTION sdr_init_from_flash(void) {
+#define RdPipe 0
+#if DEFAULT_BOOT_CLK_CPU < 6
+#define TapCnt 0x11
+ #elif DEFAULT_BOOT_CLK_CPU == 7
+#define TapCnt 0x23
+ #else
+#define TapCnt 0x19
+ #endif
+ // set all_mode _idle
+ HAL_SDR_WRITE32(REG_SDR_CSR, 0x700);
// WRAP_MISC setting
HAL_SDR_WRITE32(REG_SDR_MISC, 0x00000001);
// PCTL setting
HAL_SDR_WRITE32(REG_SDR_DCR, 0x00000008);
- HAL_SDR_WRITE32(REG_SDR_IOCR, 0x00000000);
+ HAL_SDR_WRITE32(REG_SDR_IOCR, RdPipe << PCTL_IOCR_RD_PIPE_BFO);
HAL_SDR_WRITE32(REG_SDR_EMR2, 0x00000000);
HAL_SDR_WRITE32(REG_SDR_EMR1, 0x00000006);
HAL_SDR_WRITE32(REG_SDR_MR, 0x00000022);
@@ -346,31 +347,14 @@ LOCAL int INFRA_START_SECTION sdr_init_from_flash(void) {
HAL_SDR_WRITE32(REG_SDR_TPR0, 0x00002652);
HAL_SDR_WRITE32(REG_SDR_TPR1, 0x00068873);
HAL_SDR_WRITE32(REG_SDR_TPR2, 0x00000042);
- // set all_mode _idle
- HAL_SDR_WRITE32(REG_SDR_CSR, 0x700);
// start to init
HAL_SDR_WRITE32(REG_SDR_CCR, 0x01);
+ DBG_8195A("SDR calibration: %02x-%02x\n", RdPipe, TapCnt);
while ((HAL_SDR_READ32(REG_SDR_CCR) & 0x1) == 0x0);
// enter mem_mode
HAL_SDR_WRITE32(REG_SDR_CSR, 0x600);
-
-#ifdef FIX_SDR_CALIBRATION // for speed :)
-#if 0
- // read calibration data from system data FLASH_SDRC_PARA_BASE
- u32 reg = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1);
- u32 value = 0x00190031;
- if(reg & BIT17) value = 0x00060031;
- else if((reg & 0x70) == 0) value = 0x00230031;
- HAL_PERI_ON_WRITE32(REG_PESOC_MEM_CTRL, value);
-#else
- #if DEFAULT_BOOT_CLK_CPU < 6
- HAL_PERI_ON_WRITE32(REG_PESOC_MEM_CTRL, 0x00060031);
- #elif DEFAULT_BOOT_CLK_CPU == 7
- HAL_PERI_ON_WRITE32(REG_PESOC_MEM_CTRL, 0x00230031);
- #else
- HAL_PERI_ON_WRITE32(REG_PESOC_MEM_CTRL, 0x00190031);
- #endif
-#endif
+#ifdef FIX_SDR_CALIBRATION
+ SDR_DDL_FCTRL(TapCnt); // SDR_DDL_FCTRL(0x11);
return 1;
#else
union { u8 b[8]; u16 s[4]; u32 l[2]; u64 d;} value;
@@ -388,7 +372,7 @@ LOCAL int INFRA_START_SECTION sdr_init_from_flash(void) {
DBG_8195A("Not valid SDR calibration in flash!\n");
} else
DBG_8195A("Error SDR calibration in flash!\n");
- if(SdrCalibration_rom()) {
+ if(SdrCalibration_rom()) { // Внимание: дает завышенный TapCnt !
// DBG_8195A("SDR calibration: %02x-%02x-%02x\n", value.b[0], value.b[4], value.b[6]);
value.s[0] = 0xFE01;
value.b[4] = HAL_SDR_READ32(REG_SDR_IOCR) >> PCTL_IOCR_RD_PIPE_BFO;
@@ -691,27 +675,31 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\n", HalGetCpuClk(),
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
#endif
+#ifdef CONFIG_SDR_EN
uint8 ChipId = _Get_ChipId();
if (ChipId < CHIP_ID_8195AM) {
+#endif
//----- SDRAM Off
SDR_PIN_FCTRL(OFF);
LDO25M_CTRL(OFF);
+#ifdef CONFIG_SDR_EN
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init or None
} else {
//----- SDRAM On
sdr_preinit();
-
};
+#endif
if (!InitSpic(SpicDualBitMode)) {
DBG_8195A("Spic Init fail!\n");
RtlConsolRam();
};
+#ifdef CONFIG_SDR_EN
if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // Flag SDRAM No ReInit?
if(!sdr_init_from_flash()) {
DBG_8195A("SDR Init fail!\n");
RtlConsolRam();
}
-#if 0 // Test SDRAM
+#ifdef USE_SDRAM_TEST // Test SDRAM
else {
uint32 *ptr = (uint32 *)SDR_SDRAM_BASE;
uint32 tt = 0x55AA55AA;
@@ -724,25 +712,26 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
DBG_8195A("SDR err %p %p != %p!\n", &ptr[i], ptr[i], tt);
RtlConsolRam();
}
+// ptr[i] = 0;
tt++;
};
- DBG_8195A("SDR test end\n");
+ DBG_8195A("SDR test ok\n");
};
#endif // Test SDRAM
-#ifdef CONFIG_SDR_EN
// Тест и ожидание загрузки Jlink-ом sdram.bin (~7 sec)
if(flg && *((uint32 *)0x1FFF0000) == 0x12345678) {
*((volatile uint32 *)0x1FFF0000) = 0x87654321;
uint32 tt = 0x03ffffff; // ~7 sec
DBG_8195A("Waiting for SDRAM to load...\n");
+// __asm__ __volatile__ ("cpsid f\n");
while(*((volatile uint32 *)0x1FFF0000) == 0x87654321 && tt--);
+// __asm__ __volatile__ ("cpsie f\n");
if(*((volatile uint32 *)0x1FFF0000) == 1)
DBG_8195A("SDRAM load ok\n");
}
-#endif // CONFIG_SDR_EN
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM No ReInit
};
-
+#endif // CONFIG_SDR_EN
if (!flg)
loadUserImges(IsForceLoadDefaultImg2() + 1);
diff --git a/USDK/component/soc/realtek/8195a/fwlib/ram_lib/startup.c b/USDK/component/soc/realtek/8195a/fwlib/ram_lib/startup.c
index b308f1a..288a670 100644
--- a/USDK/component/soc/realtek/8195a/fwlib/ram_lib/startup.c
+++ b/USDK/component/soc/realtek/8195a/fwlib/ram_lib/startup.c
@@ -1,5 +1,5 @@
/*
- * StartUp SDK
+ * StartUp USDK v0.2 (18/10/2017)
* Created on: 02/03/2017
* Author: pvvx
*/
@@ -41,6 +41,7 @@ void SDIO_Device_Off(void);
//void VectorTableOverrideRtl8195A(u32 StackP);
void SYSPlatformInit(void);
+#define FIX_SDR_CALIBRATION // for speed :)
//-------------------------------------------------------------------------
// Data declarations
extern u8 __bss_start__, __bss_end__;
@@ -50,6 +51,61 @@ extern const unsigned char cus_sig[32]; // images name
IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 =
{ InfraStart + 1 };
+#ifdef FIX_SDR_CALIBRATION // for speed :)
+#include "rtl8195a/rtl8195a_sdr.h"
+LOCAL void sdr_init(void) {
+ HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
+ ((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); // ROM: BIT_SYS_REGU_LDO25M_ADJ(0x0e)? HAL RAM BIT_SYS_REGU_LDO25M_ADJ(0x03)
+ LDO25M_CTRL(ON);
+ SRAM_MUX_CFG(0x2);
+ SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE); // REG_PESOC_CLK_SEL
+ HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4, 0);
+ ACTCK_SDR_CCTRL(ON);
+ SLPCK_SDR_CCTRL(ON);
+ HalPinCtrlRtl8195A(SDR, 0, ON); // SDR_PIN_FCTRL(ON);
+ MEM_CTRL_FCTRL(ON);
+// HalDelayUs(1000);
+ // read calibration data from system data FLASH_SDRC_PARA_BASE
+ union { u8 b[8]; u16 s[4]; u32 l[2]; u64 d;} value;
+ u32 faddr = SPI_FLASH_BASE + FLASH_SDRC_PARA_BASE + CPU_CLOCK_SEL_VALUE*8 + CPU_CLOCK_SEL_DIV5_3*8*8; // step 8 in FLASH_SDRC_PARA_BASE[64 + 64 bytes]
+ value.d = *((volatile u64 *)faddr);
+ if(value.s[0] == 0xFE01 && (value.b[4]^value.b[5]) == 0xFF && (value.b[6]^value.b[7]) == 0xFF) {
+ DBG_8195A("SDR flash calibration [%08x]: %02x-%02x ", faddr, value.b[4], value.b[6]);
+ } else {
+ value.b[4] = 0; // TapCnt
+#if CONFIG_CPU_CLK < 6
+ value.b[6] = 0x11; // RdPipe
+#elif CONFIG_CPU_CLK == 7
+ value.b[6] = 0x23; // RdPipe
+#else
+ value.b[6] = 0x19; // RdPipe
+#endif
+ DBG_8195A("Use fix SDR calibration: %02x-%02x ", value.b[4], value.b[6]);
+ }
+ // set all_mode _idle
+ HAL_SDR_WRITE32(REG_SDR_CSR, 0x700);
+ // WRAP_MISC setting
+ HAL_SDR_WRITE32(REG_SDR_MISC, 0x00000001);
+ // PCTL setting
+ HAL_SDR_WRITE32(REG_SDR_DCR, 0x00000008);
+ HAL_SDR_WRITE32(REG_SDR_IOCR, (u32)value.b[4] << PCTL_IOCR_RD_PIPE_BFO);
+ HAL_SDR_WRITE32(REG_SDR_EMR2, 0x00000000);
+ HAL_SDR_WRITE32(REG_SDR_EMR1, 0x00000006);
+ HAL_SDR_WRITE32(REG_SDR_MR, 0x00000022);
+ HAL_SDR_WRITE32(REG_SDR_DRR, 0x09030e07);
+ HAL_SDR_WRITE32(REG_SDR_TPR0, 0x00002652);
+ HAL_SDR_WRITE32(REG_SDR_TPR1, 0x00068873);
+ HAL_SDR_WRITE32(REG_SDR_TPR2, 0x00000042);
+ // start to init
+ HAL_SDR_WRITE32(REG_SDR_CCR, 0x01);
+ while ((HAL_SDR_READ32(REG_SDR_CCR) & 0x1) == 0x0)
+ DBG_8195A(".");
+ // enter mem_mode
+ HAL_SDR_WRITE32(REG_SDR_CSR, 0x600);
+ SDR_DDL_FCTRL((u32)value.b[6]);
+ DBG_8195A(" ok\n");
+}
+#endif // FIX_SDR_CALIBRATION
/*
//----- HalNMIHandler_Patch
void HalNMIHandler_Patch(void) {
@@ -167,34 +223,36 @@ extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
};
*/
// SpicFlashInitRtl8195A(SpicDualBitMode); // SpicReadIDRtl8195A(); SpicDualBitMode
+#ifdef CONFIG_SDR_EN
//---- SDRAM
uint8 ChipId = HalGetChipId();
if (ChipId >= CHIP_ID_8195AM) {
-#ifdef CONFIG_SDR_EN
- if((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // ещё не инициализирована?
+ if((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // SDR not init?
+ #ifdef FIX_SDR_CALIBRATION // for speed :)
+ sdr_init();
+ #else // not FIX_SDR_CALIBRATION
SdrCtrlInit();
if(!SdrControllerInit()) {
DBG_8195A("SDR Controller Init fail!\n");
};
- } else if (CPU_CLOCK_SEL_DIV5_3) { // clk 5/6
- if(((HAL_PERI_ON_READ32(REG_PESOC_MEM_CTRL) >> BIT_SHIFT_PESOC_SDR_DDL_CTRL) & 0xFF) < 0x15) {
- SDR_DDL_FCTRL(0x23);
- }
- }
-#endif
+ #endif // FIX_SDR_CALIBRATION
+ };
// clear SDRAM bss
extern uint8 __sdram_bss_start__[];
extern uint8 __sdram_bss_end__[];
if((uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__ > 0)
memset(__sdram_bss_start__, 0, (uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__);
}
- else
+ else // if (ChipId < CHIP_ID_8195AM)
{
//----- SDRAM Off
SDR_PIN_FCTRL(OFF);
LDO25M_CTRL(OFF);
- HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off
};
+ HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init or None
+#else
+ HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (~BIT(21))); // Flag SDRAM Not Init
+#endif // CONFIG_SDR_EN
//----- Close Flash
SPI_FLASH_PIN_FCTRL(OFF);
diff --git a/USDK/flasher.mk b/USDK/flasher.mk
index ebd00c7..9d1c78f 100644
--- a/USDK/flasher.mk
+++ b/USDK/flasher.mk
@@ -91,7 +91,7 @@ mp: OTA_IMAGE = $(BIN_DIR)/ota_mp.bin
TST_IMAGE = $(BIN_DIR)/ram_2.bin
-.PHONY: genbin1 genbin23 flashburn reset test readfullflash flashwebfs flash_OTA runram runsdram
+.PHONY: genbin1 genbin23 flashburn reset test readfullflash flashboot flashwebfs flash_OTA runram runsdram
.NOTPARALLEL: all mp genbin1 genbin23 flashburn reset test readfullflash _endgenbin flashwebfs flash_OTA
all: $(ELFFILE) $(OTA_IMAGE) $(FLASH_IMAGE) _endgenbin
@@ -137,6 +137,17 @@ flashburn:
@$(GDB) -x $(FLASHER_PATH)gdb_wrflash.jlink
#@taskkill /F /IM $(JLINK_GDBSRV)
+flashboot:
+ @echo define call1>$(FLASHER_PATH)file_info.jlink
+ @echo set '$$'ImageSize = $(shell printf '0x%X\n' $$(stat --printf="%s" $(BIN_DIR)/ram_1.p.bin))>>$(FLASHER_PATH)file_info.jlink
+ @echo set '$$'ImageAddr = 0x000000>>$(FLASHER_PATH)file_info.jlink
+ @echo end>>$(FLASHER_PATH)file_info.jlink
+ @echo define call2>>$(FLASHER_PATH)file_info.jlink
+ @echo FlasherWrite $(BIN_DIR)/ram_1.p.bin '$$'ImageAddr '$$'ImageSize>>$(FLASHER_PATH)file_info.jlink
+ @echo end>>$(FLASHER_PATH)file_info.jlink
+ @cmd /K start $(JLINK_PATH)$(JLINK_GDBSRV) -device Cortex-M3 -if SWD -ir -endian little -speed 1000
+ @$(GDB) -x $(FLASHER_PATH)gdb_wrfile.jlink
+
flashwebfs:
@echo define call1>$(FLASHER_PATH)file_info.jlink
@echo set '$$'ImageSize = $(shell printf '0x%X\n' $$(stat --printf="%s" $(BIN_DIR)/WEBFiles.bin))>>$(FLASHER_PATH)file_info.jlink
diff --git a/USDK/flasher/RTL_RunRAM.JLinkScript b/USDK/flasher/RTL_RunRAM.JLinkScript
index 7632f1e..f8b665b 100644
--- a/USDK/flasher/RTL_RunRAM.JLinkScript
+++ b/USDK/flasher/RTL_RunRAM.JLinkScript
@@ -7,6 +7,6 @@ r
loadbin build/bin/ram_1.r.bin 0x10000bc8
loadbin build/bin/ram_2.bin 0x10006000
r
-w4 0x40000210,0x20111113
+w4 0x40000210,0x20011113
g
q
\ No newline at end of file
diff --git a/flasher/RTL_RunRAM_SDR.JLinkScript b/flasher/RTL_RunRAM_SDR.JLinkScript
index 3319606..0e48894 100644
--- a/flasher/RTL_RunRAM_SDR.JLinkScript
+++ b/flasher/RTL_RunRAM_SDR.JLinkScript
@@ -2,15 +2,15 @@ r0
trst0
r1
trst1
-h
r
+h
loadbin build/bin/ram_1.r.bin 0x10000bc8
loadbin build/bin/ram_2.bin 0x10006000
r
w4 0x40000210,0x20011113
w4 0x1FFF0000,0x12345678
g
-sleep 3000
+sleep 1000
h
loadbin build/bin/sdram.bin 0x30000000
w4 0x1FFF0000,1
diff --git a/project/inc/platform_autoconf.h b/project/inc/platform_autoconf.h
index 10f114d..e6b819e 100644
--- a/project/inc/platform_autoconf.h
+++ b/project/inc/platform_autoconf.h
@@ -31,7 +31,7 @@
#define RTL8195A 1
/* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz,
6 - 200000000 Hz, 7 - 100000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */
-#define CONFIG_CPU_CLK 0
+#define CONFIG_CPU_CLK 1
//166.6MHZ - RUN/IDLE/SLP ~63/21/6.4 mA
//83.3MHZ - RUN/IDLE/SLP ~55/15/6.4 mA
//41.6MHZ - RUN/IDLE ~51/11 mA