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update

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pvvx 2017-09-06 20:20:53 +03:00
parent c98cbe6e00
commit 9ffd9dac1a
27 changed files with 113 additions and 119 deletions
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8
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c
View file

@ -245,7 +245,6 @@ HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor)
u32 IRQ_UNKNOWN = 999;
u32 Ctrlr0Value = 0;
u32 Ctrlr1Value = 0;
u32 SerValue;
u32 BaudrValue = 0;
u32 TxftlrValue = 0;
u32 RxftlrValue = 0;
@ -318,8 +317,7 @@ HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor)
HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR1));
}
SerValue = BIT_SER_SER(1 << (pHalSsiAdaptor->SlaveSelectEnable));
SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_SER Value: %X\n", Index, SerValue);
SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_SER Value: %X\n", Index, BIT_SER_SER(1 << (pHalSsiAdaptor->SlaveSelectEnable)));
//HAL_SSI_WRITE32(Index, REG_DW_SSI_SER, SerValue);
HalSsiSetSlaveEnableRegisterRtl8195a(Adaptor, pHalSsiAdaptor->SlaveSelectEnable);
@ -617,7 +615,6 @@ HAL_Status HalSsiSetFormatRtl8195a(VOID *Adaptor)
u32 RxftlrValue = 0;
u8 Index = pHalSsiAdaptor->Index;
u8 Role = pHalSsiAdaptor->Role;
u32 Spi_mode;
if (Index > 2) {
DBG_SSI_ERR("HalSsiSetFormatRtl8195a: Invalid SSI Idx %d\r\n", Index);
@ -639,10 +636,9 @@ HAL_Status HalSsiSetFormatRtl8195a(VOID *Adaptor)
HAL_SSI_WRITE32(Index, REG_DW_SSI_CTRLR0, Ctrlr0Value);
Spi_mode = (HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0) >>6) & 0x3;
SSI_DBG_INIT("[2] SSI%d REG_DW_SSI_CTRLR0(%X) = %X, SPI Mode = %X\n", Index,
SSI0_REG_BASE + (SSI_REG_OFF * Index) + REG_DW_SSI_CTRLR0,
HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0), Spi_mode);
HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0), (HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0) >>6) & 0x3);
//The tx threshold and rx threshold value will be reset after the spi changes its role
/* REG_DW_SSI_TXFTLR */
TxftlrValue = BIT_TXFTLR_TFT(pHalSsiAdaptor->TxThresholdLevel);

17
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c
View file

@ -152,9 +152,8 @@ HalRuartGenBaudRateRtl8195a(
u32 min_divisor=0;
u32 min_err=0xffffffff;
u32 uart_ovsr;
u32 uart_ovsr_mod;
u32 min_uart_ovsr; // ovsr with mini err
u32 min_uart_ovsr_mod;
u32 min_uart_ovsr = 0; // ovsr with mini err
u32 min_uart_ovsr_mod = 0;
u64 uart_clock;
u32 divisor_temp;
u32 max_jitter_temp;
@ -201,7 +200,7 @@ HalRuartGenBaudRateRtl8195a(
min_uart_ovsr = uart_ovsr/100;
min_uart_ovsr_mod = uart_ovsr%100;
} else if (err_temp == min_err) {
uart_ovsr_mod = uart_ovsr%100;
u32 uart_ovsr_mod = uart_ovsr%100;
// we perfer OVSR bigger and adj bits smaller
if (((uart_ovsr/100) >= min_uart_ovsr) && (uart_ovsr_mod < min_uart_ovsr_mod)) {
min_err = err_temp;
@ -1284,7 +1283,7 @@ HalRuartStopRecvRtl8195a_Patch(
if (NULL != pUartGdmaConfig) {
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
PHAL_GDMA_OP pHalGdmaOp;
u8 IsrTypeMap;
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pRxHalGdmaAdapter;
pHalGdmaOp = (PHAL_GDMA_OP)pUartGdmaConfig->pHalGdmaOp;
@ -1294,7 +1293,8 @@ HalRuartStopRecvRtl8195a_Patch(
// Clean Auto Reload Bit
pHalGdmaOp->HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter);
// Clear Pending ISR
IsrTypeMap = pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
// u8 IsrTypeMap =
pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
pHalGdmaOp->HalGdmaChDis((VOID*)(pHalGdmaAdapter));
DMA_Dar = HalGdmaQueryDArRtl8195a((VOID*)pHalGdmaAdapter);
@ -1359,7 +1359,7 @@ HalRuartStopSendRtl8195a_Patch(
if (NULL != pUartGdmaConfig) {
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
PHAL_GDMA_OP pHalGdmaOp;
u8 IsrTypeMap;
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter;
pHalGdmaOp = (PHAL_GDMA_OP)pUartGdmaConfig->pHalGdmaOp;
@ -1369,7 +1369,8 @@ HalRuartStopSendRtl8195a_Patch(
// Clean Auto Reload Bit
pHalGdmaOp->HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter);
// Clear Pending ISR
IsrTypeMap = pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
// u8 IsrTypeMap =
pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
pHalGdmaOp->HalGdmaChDis((VOID*)(pHalGdmaAdapter));
DMA_Sar = HalGdmaQuerySArRtl8195a((VOID*)pHalGdmaAdapter);