From 9ffd9dac1aa66c690f15e37e68c5f880e6dab542 Mon Sep 17 00:00:00 2001 From: pvvx Date: Wed, 6 Sep 2017 20:20:53 +0300 Subject: [PATCH] update --- .../wlan/realtek/src/osdep/lwip_intf.c | 6 ++-- USDK/component/common/mbed/hal/gpio_irq_api.h | 4 ++- .../common/mbed/hal_ext/gpio_irq_ex_api.h | 5 +-- .../mbed/targets/hal/rtl8195a/analogin_api.c | 2 +- .../mbed/targets/hal/rtl8195a/flash_eep.c | 2 +- .../mbed/targets/hal/rtl8195a/i2c_api.c | 14 ++++---- .../mbed/targets/hal/rtl8195a/log_uart_api.c | 12 +++---- .../mbed/targets/hal/rtl8195a/serial_api.c | 8 ++--- .../mbed/targets/hal/rtl8195a/spi_api.c | 8 ++--- .../lwip/lwip_v1.4.1/src/api/sockets.c | 19 ++++++----- .../network/lwip/lwip_v1.4.1/src/core/dhcp.c | 2 +- .../lwip/lwip_v1.4.1/src/core/ipv4/icmp.c | 7 ++-- .../lwip/lwip_v1.4.1/src/core/ipv4/ip.c | 2 +- USDK/component/os/freertos/cmsis_os.c | 12 +++---- USDK/component/os/os_dep/device_lock.c | 3 +- USDK/component/os/os_dep/tcm_heap.c | 4 +-- .../8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c | 8 ++--- .../8195a/fwlib/rtl8195a/src/rtl8195a_uart.c | 17 +++++----- .../soc/realtek/8195a/fwlib/src/hal_adc.c | 8 ++--- .../soc/realtek/8195a/fwlib/src/hal_gpio.c | 32 ++++++++----------- .../8195a/fwlib/src/hal_sdr_controller.c | 19 ++++++----- .../8195a/fwlib/src/hal_soc_ps_monitor.c | 9 ++---- .../soc/realtek/8195a/fwlib/src/hal_ssi.c | 2 +- .../soc/realtek/8195a/fwlib/src/hal_uart.c | 4 +-- .../8195a/misc/os/freertos_pmu_8195a.c | 8 ++--- .../misc/rtl_std_lib/lib_rtlstd/c_stdio.c | 7 ++-- USDK/sdkset.mk | 8 ++--- 27 files changed, 113 insertions(+), 119 deletions(-) diff --git a/USDK/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c b/USDK/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c index 40f750a..57958d1 100644 --- a/USDK/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c +++ b/USDK/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c @@ -133,13 +133,13 @@ void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len) DBG_TRACE("%s is called", __FUNCTION__); - if (rltk_wlan_check_isup(idx) == 0) - return; - if(idx == -1){ DBG_ERR("skb is NULL"); return; } + if (rltk_wlan_check_isup(idx) == 0) + return; + skb = rltk_wlan_get_recv_skb(idx); DBG_ASSERT(skb, "No pending rx skb"); diff --git a/USDK/component/common/mbed/hal/gpio_irq_api.h b/USDK/component/common/mbed/hal/gpio_irq_api.h index ccdb30c..10f5775 100644 --- a/USDK/component/common/mbed/hal/gpio_irq_api.h +++ b/USDK/component/common/mbed/hal/gpio_irq_api.h @@ -27,7 +27,9 @@ extern "C" { typedef enum { IRQ_NONE, IRQ_RISE, - IRQ_FALL + IRQ_FALL, + IRQ_LOW, + IRQ_HIGH } gpio_irq_event; typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event); diff --git a/USDK/component/common/mbed/hal_ext/gpio_irq_ex_api.h b/USDK/component/common/mbed/hal_ext/gpio_irq_ex_api.h index 2fcee20..6e083b5 100644 --- a/USDK/component/common/mbed/hal_ext/gpio_irq_ex_api.h +++ b/USDK/component/common/mbed/hal_ext/gpio_irq_ex_api.h @@ -23,11 +23,12 @@ #ifdef __cplusplus extern "C" { #endif - +/* typedef enum { IRQ_LOW = 3, IRQ_HIGH =4 } gpio_irq_event_ex; +*/ void gpio_irq_deinit(gpio_irq_t *obj); void gpio_irq_pull_ctrl(gpio_irq_t *obj, PinMode pull_type); @@ -37,4 +38,4 @@ void gpio_irq_pull_ctrl(gpio_irq_t *obj, PinMode pull_type); #endif // end of "#if DEVICE_INTERRUPTIN" -#endif // end of #ifndef MBED_GPIO_IRQ_EX_API_H \ No newline at end of file +#endif // end of #ifndef MBED_GPIO_IRQ_EX_API_H diff --git a/USDK/component/common/mbed/targets/hal/rtl8195a/analogin_api.c b/USDK/component/common/mbed/targets/hal/rtl8195a/analogin_api.c index 5534443..18c5d14 100644 --- a/USDK/component/common/mbed/targets/hal/rtl8195a/analogin_api.c +++ b/USDK/component/common/mbed/targets/hal/rtl8195a/analogin_api.c @@ -118,7 +118,7 @@ void analogin_init (analogin_t *obj, PinName pin){ } float analogin_read(analogin_t *obj){ - float value; +// float value; union { unsigned int ui[2]; unsigned short us[4]; diff --git a/USDK/component/common/mbed/targets/hal/rtl8195a/flash_eep.c b/USDK/component/common/mbed/targets/hal/rtl8195a/flash_eep.c index f44426e..82ce6c9 100644 --- a/USDK/component/common/mbed/targets/hal/rtl8195a/flash_eep.c +++ b/USDK/component/common/mbed/targets/hal/rtl8195a/flash_eep.c @@ -376,7 +376,7 @@ LOCAL signed short FLASH_EEP_ATTR _flash_write_cfg(void *ptr, unsigned short id, fobj_head fobj; fobj.n.id = id; fobj.n.size = size; - bool retb = false; +// bool retb = false; unsigned int faddr = get_addr_bscfg(false); if(faddr >= FMEM_ERROR_MAX) { diff --git a/USDK/component/common/mbed/targets/hal/rtl8195a/i2c_api.c b/USDK/component/common/mbed/targets/hal/rtl8195a/i2c_api.c index 6d1ed3e..cc7f095 100644 --- a/USDK/component/common/mbed/targets/hal/rtl8195a/i2c_api.c +++ b/USDK/component/common/mbed/targets/hal/rtl8195a/i2c_api.c @@ -440,7 +440,7 @@ int i2c_byte_write(i2c_t *obj, int data) { pSalI2CHND->pTXBuf->pDataBuf = (unsigned char*)&data; if (RtkI2CSend(pSalI2CHND) != HAL_OK) { - return 0; + return 0; // error } return 1; @@ -573,6 +573,7 @@ int i2c_enable_control(i2c_t *obj, int enable) { pSalI2CHND->pInitDat->I2CEn = enable; pSalI2CMngtAdpt->pHalOp->HalI2CEnable(pSalI2CHND->pInitDat); + return 1; } #if DEVICE_I2CSLAVE @@ -719,14 +720,14 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length) { * \return result */ int i2c_slave_set_for_rd_req(i2c_t *obj, int set) { - PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; - PSAL_I2C_HND pSalI2CHND = NULL; - PHAL_I2C_INIT_DAT pHalI2CInitDat = NULL; - PHAL_I2C_OP pHalI2COP = NULL; + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt; +// PSAL_I2C_HND pSalI2CHND; + PHAL_I2C_INIT_DAT pHalI2CInitDat; + PHAL_I2C_OP pHalI2COP; u32 I2CLocalTemp; pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt); - pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); +// pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); pHalI2CInitDat = pSalI2CMngtAdpt->pHalInitDat; pHalI2COP = pSalI2CMngtAdpt->pHalOp; @@ -772,6 +773,7 @@ int i2c_slave_set_for_data_nak(i2c_t *obj, int set_nak) { //} HAL_I2C_WRITE32(pSalI2CHND->DevNum, REG_DW_I2C_IC_SLV_DATA_NACK_ONLY, set_nak); + return 1; } #endif // CONFIG_I2C_SLAVE_EN diff --git a/USDK/component/common/mbed/targets/hal/rtl8195a/log_uart_api.c b/USDK/component/common/mbed/targets/hal/rtl8195a/log_uart_api.c index fc284a7..cb0f60c 100644 --- a/USDK/component/common/mbed/targets/hal/rtl8195a/log_uart_api.c +++ b/USDK/component/common/mbed/targets/hal/rtl8195a/log_uart_api.c @@ -253,7 +253,7 @@ void log_uart_irq_set(log_uart_t *obj, LOG_UART_INT_ID irq, uint32_t enable) char log_uart_getc(log_uart_t *obj) { - HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); +// HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); while (!log_uart_readable(obj)); return (char)(HAL_UART_READ32(UART_REV_BUF_OFF) & 0xFF); @@ -261,7 +261,7 @@ char log_uart_getc(log_uart_t *obj) void log_uart_putc(log_uart_t *obj, char c) { - HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); +// HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); while (!log_uart_writable(obj)); HAL_UART_WRITE8(UART_TRAN_HOLD_OFF, c); @@ -269,7 +269,7 @@ void log_uart_putc(log_uart_t *obj, char c) int log_uart_readable(log_uart_t *obj) { - HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); +// HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); volatile u8 line_status; line_status = HAL_UART_READ8(UART_LINE_STATUS_REG_OFF); @@ -283,7 +283,7 @@ int log_uart_readable(log_uart_t *obj) int log_uart_writable(log_uart_t *obj) { - HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); +// HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); volatile u8 line_status; line_status = HAL_UART_READ8(UART_LINE_STATUS_REG_OFF); @@ -321,7 +321,7 @@ void log_uart_clear_rx(log_uart_t *obj) void log_uart_break_set(log_uart_t *obj) { - HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); +// HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); u32 RegValue; RegValue = HAL_UART_READ32(UART_LINE_CTL_REG_OFF); @@ -331,7 +331,7 @@ void log_uart_break_set(log_uart_t *obj) void log_uart_break_clear(log_uart_t *obj) { - HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); +// HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart); u32 RegValue; RegValue = HAL_UART_READ32(UART_LINE_CTL_REG_OFF); diff --git a/USDK/component/common/mbed/targets/hal/rtl8195a/serial_api.c b/USDK/component/common/mbed/targets/hal/rtl8195a/serial_api.c index af21347..0f495b6 100644 --- a/USDK/component/common/mbed/targets/hal/rtl8195a/serial_api.c +++ b/USDK/component/common/mbed/targets/hal/rtl8195a/serial_api.c @@ -536,12 +536,12 @@ int32_t serial_send_stream (serial_t *obj, char *ptxbuf, uint32_t len) int32_t serial_recv_stream_dma (serial_t *obj, char *prxbuf, uint32_t len) { - PHAL_RUART_OP pHalRuartOp; +// PHAL_RUART_OP pHalRuartOp; PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp); u8 uart_idx = pHalRuartAdapter->UartIndex; int32_t ret; - pHalRuartOp = &(obj->hal_uart_op); +// pHalRuartOp = &(obj->hal_uart_op); if ((serial_dma_en[uart_idx] & SERIAL_RX_DMA_EN)==0) { PUART_DMA_CONFIG pHalRuartDmaCfg; @@ -563,12 +563,12 @@ int32_t serial_recv_stream_dma (serial_t *obj, char *prxbuf, uint32_t len) int32_t serial_send_stream_dma (serial_t *obj, char *ptxbuf, uint32_t len) { - PHAL_RUART_OP pHalRuartOp; +// PHAL_RUART_OP pHalRuartOp; PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp); u8 uart_idx = pHalRuartAdapter->UartIndex; int32_t ret; - pHalRuartOp = &(obj->hal_uart_op); +// pHalRuartOp = &(obj->hal_uart_op); if ((serial_dma_en[uart_idx] & SERIAL_TX_DMA_EN)==0) { PUART_DMA_CONFIG pHalRuartDmaCfg; diff --git a/USDK/component/common/mbed/targets/hal/rtl8195a/spi_api.c b/USDK/component/common/mbed/targets/hal/rtl8195a/spi_api.c index 85471cd..1a3fe69 100644 --- a/USDK/component/common/mbed/targets/hal/rtl8195a/spi_api.c +++ b/USDK/component/common/mbed/targets/hal/rtl8195a/spi_api.c @@ -58,13 +58,13 @@ void spi_init (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName sse _memset((void*)obj, 0, sizeof(spi_t)); obj->state = 0; - uint32_t SystemClock = SystemGetCpuClk(); - uint32_t MaxSsiFreq = (SystemClock >> 2) >> 1; +// uint32_t SystemClock = SystemGetCpuClk(); +// uint32_t MaxSsiFreq = (SystemClock >> 2) >> 1; /* SsiClockDivider doesn't support odd number */ - DBG_SSI_INFO("SystemClock: %d\n", SystemClock); - DBG_SSI_INFO("MaxSsiFreq : %d\n", MaxSsiFreq); + DBG_SSI_INFO("SystemClock: %d\n", SystemGetCpuClk()); + DBG_SSI_INFO("MaxSsiFreq : %d\n", (SystemClock >> 2) >> 1); ssi_mosi = pinmap_peripheral(mosi, PinMap_SSI_MOSI); ssi_miso = pinmap_peripheral(miso, PinMap_SSI_MISO); diff --git a/USDK/component/common/network/lwip/lwip_v1.4.1/src/api/sockets.c b/USDK/component/common/network/lwip/lwip_v1.4.1/src/api/sockets.c index 5669497..083695b 100644 --- a/USDK/component/common/network/lwip/lwip_v1.4.1/src/api/sockets.c +++ b/USDK/component/common/network/lwip/lwip_v1.4.1/src/api/sockets.c @@ -105,7 +105,7 @@ struct lwip_select_cb { struct lwip_setgetsockopt_data { /** socket struct for which to change options */ struct lwip_sock *sock; -#ifdef LWIP_DEBUG +#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0) /** socket index for which to change options */ int s; #endif /* LWIP_DEBUG */ @@ -1641,7 +1641,7 @@ lwip_getsockopt(int s, int level, int optname, void *optval, socklen_t *optlen) /* Now do the actual option processing */ data.sock = sock; -#ifdef LWIP_DEBUG +#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0) data.s = s; #endif /* LWIP_DEBUG */ data.level = level; @@ -1662,9 +1662,6 @@ static void lwip_getsockopt_internal(void *arg) { struct lwip_sock *sock; -#ifdef LWIP_DEBUG - int s; -#endif /* LWIP_DEBUG */ int level, optname; void *optval; struct lwip_setgetsockopt_data *data; @@ -1673,8 +1670,8 @@ lwip_getsockopt_internal(void *arg) data = (struct lwip_setgetsockopt_data*)arg; sock = data->sock; -#ifdef LWIP_DEBUG - s = data->s; +#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0) + int s = data->s; #endif /* LWIP_DEBUG */ level = data->level; optname = data->optname; @@ -1699,8 +1696,10 @@ lwip_getsockopt_internal(void *arg) #endif /* SO_REUSE */ /*case SO_USELOOPBACK: UNIMPL */ *(int*)optval = ip_get_option(sock->conn->pcb.ip, optname); +#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0) LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", s, optname, (*(int*)optval?"on":"off"))); +#endif /* LWIP_DEBUG */ break; case SO_TYPE: @@ -2059,7 +2058,7 @@ lwip_setsockopt(int s, int level, int optname, const void *optval, socklen_t opt /* Now do the actual option processing */ data.sock = sock; -#ifdef LWIP_DEBUG +#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0) data.s = s; #endif /* LWIP_DEBUG */ data.level = level; @@ -2080,7 +2079,7 @@ static void lwip_setsockopt_internal(void *arg) { struct lwip_sock *sock; -#ifdef LWIP_DEBUG +#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0) int s; #endif /* LWIP_DEBUG */ int level, optname; @@ -2091,7 +2090,7 @@ lwip_setsockopt_internal(void *arg) data = (struct lwip_setgetsockopt_data*)arg; sock = data->sock; -#ifdef LWIP_DEBUG +#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0) s = data->s; #endif /* LWIP_DEBUG */ level = data->level; diff --git a/USDK/component/common/network/lwip/lwip_v1.4.1/src/core/dhcp.c b/USDK/component/common/network/lwip/lwip_v1.4.1/src/core/dhcp.c index fcecff1..8b62123 100644 --- a/USDK/component/common/network/lwip/lwip_v1.4.1/src/core/dhcp.c +++ b/USDK/component/common/network/lwip/lwip_v1.4.1/src/core/dhcp.c @@ -1008,7 +1008,7 @@ dhcp_bind(struct netif *netif) ip_addr_copy(gw_addr, dhcp->offered_gw_addr); /* gateway address not given? */ - if (ip_addr_isany(&gw_addr)) { + if (gw_addr.addr == IPADDR_ANY) { /* copy network address */ ip_addr_get_network(&gw_addr, &dhcp->offered_ip_addr, &sn_mask); /* use first host address on network as gateway */ diff --git a/USDK/component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/icmp.c b/USDK/component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/icmp.c index 47ba857..cfc41b6 100644 --- a/USDK/component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/icmp.c +++ b/USDK/component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/icmp.c @@ -77,9 +77,6 @@ void icmp_input(struct pbuf *p, struct netif *inp) { u8_t type; -#ifdef LWIP_DEBUG - u8_t code; -#endif /* LWIP_DEBUG */ struct icmp_echo_hdr *iecho; struct ip_hdr *iphdr; s16_t hlen; @@ -96,8 +93,8 @@ icmp_input(struct pbuf *p, struct netif *inp) } type = *((u8_t *)p->payload); -#ifdef LWIP_DEBUG - code = *(((u8_t *)p->payload)+1); +#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0) + u8_t code = *(((u8_t *)p->payload)+1); #endif /* LWIP_DEBUG */ switch (type) { case ICMP_ER: diff --git a/USDK/component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/ip.c b/USDK/component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/ip.c index c3537f7..16319ba 100644 --- a/USDK/component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/ip.c +++ b/USDK/component/common/network/lwip/lwip_v1.4.1/src/core/ipv4/ip.c @@ -500,7 +500,7 @@ ip_input(struct pbuf *p, struct netif *inp) /* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */ #if IP_ACCEPT_LINK_LAYER_ADDRESSING /* DHCP servers need 0.0.0.0 to be allowed as source address (RFC 1.1.2.2: 3.2.1.3/a) */ - if (check_ip_src && !ip_addr_isany(¤t_iphdr_src)) + if (check_ip_src && current_iphdr_src.addr != IPADDR_ANY) // !ip_addr_isany(¤t_iphdr_src)) #endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */ { if ((ip_addr_isbroadcast(¤t_iphdr_src, inp)) || (ip_addr_ismulticast(¤t_iphdr_src))) { diff --git a/USDK/component/os/freertos/cmsis_os.c b/USDK/component/os/freertos/cmsis_os.c index f89830a..7eedf9a 100644 --- a/USDK/component/os/freertos/cmsis_os.c +++ b/USDK/component/os/freertos/cmsis_os.c @@ -74,7 +74,7 @@ static int inHandlerMode (void) #if configSignalManagementSupport // the older FreeRTOS version didn't support Signal Management functions static void add_thread_signal_map (osThreadId thread_id, EventGroupHandle_t signals) { - int dummy; + int dummy = 0; // uint32_t i; ThreadSignalRec *prec_entity; @@ -134,8 +134,7 @@ static void add_thread_signal_map (osThreadId thread_id, EventGroupHandle_t sign static EventGroupHandle_t find_signal_by_thread (osThreadId thread_id) { EventGroupHandle_t signals_hdl=NULL; -// uint32_t i; - int dummy; + int dummy = 0; ThreadSignalRec *prec_entity; if (inHandlerMode()) { @@ -157,6 +156,7 @@ static EventGroupHandle_t find_signal_by_thread (osThreadId thread_id) } #if 0 + // uint32_t i; for (i=0;i 1 if(!g_heap_inited) tcm_heap_init(); - MemChunk *chunk, *prev; + MemChunk *chunk; struct Heap* h = &g_tcm_heap; int count = 0; - int free_mem; DBG_8195A("TCM Free Heap Memory List:\n"); for (chunk = h->FreeList; chunk; chunk = chunk->next) { @@ -68,6 +67,7 @@ void tcm_heap_dump(void) } /* + MemChunk *prev; for (prev = (MemChunk *)&h->FreeList, chunk = h->FreeList; chunk; prev = chunk, chunk = chunk->next) diff --git a/USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c b/USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c index 4d9ec6c..c1c77aa 100644 --- a/USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c +++ b/USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c @@ -245,7 +245,6 @@ HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor) u32 IRQ_UNKNOWN = 999; u32 Ctrlr0Value = 0; u32 Ctrlr1Value = 0; - u32 SerValue; u32 BaudrValue = 0; u32 TxftlrValue = 0; u32 RxftlrValue = 0; @@ -318,8 +317,7 @@ HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor) HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR1)); } - SerValue = BIT_SER_SER(1 << (pHalSsiAdaptor->SlaveSelectEnable)); - SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_SER Value: %X\n", Index, SerValue); + SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_SER Value: %X\n", Index, BIT_SER_SER(1 << (pHalSsiAdaptor->SlaveSelectEnable))); //HAL_SSI_WRITE32(Index, REG_DW_SSI_SER, SerValue); HalSsiSetSlaveEnableRegisterRtl8195a(Adaptor, pHalSsiAdaptor->SlaveSelectEnable); @@ -617,7 +615,6 @@ HAL_Status HalSsiSetFormatRtl8195a(VOID *Adaptor) u32 RxftlrValue = 0; u8 Index = pHalSsiAdaptor->Index; u8 Role = pHalSsiAdaptor->Role; - u32 Spi_mode; if (Index > 2) { DBG_SSI_ERR("HalSsiSetFormatRtl8195a: Invalid SSI Idx %d\r\n", Index); @@ -639,10 +636,9 @@ HAL_Status HalSsiSetFormatRtl8195a(VOID *Adaptor) HAL_SSI_WRITE32(Index, REG_DW_SSI_CTRLR0, Ctrlr0Value); - Spi_mode = (HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0) >>6) & 0x3; SSI_DBG_INIT("[2] SSI%d REG_DW_SSI_CTRLR0(%X) = %X, SPI Mode = %X\n", Index, SSI0_REG_BASE + (SSI_REG_OFF * Index) + REG_DW_SSI_CTRLR0, - HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0), Spi_mode); + HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0), (HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0) >>6) & 0x3); //The tx threshold and rx threshold value will be reset after the spi changes its role /* REG_DW_SSI_TXFTLR */ TxftlrValue = BIT_TXFTLR_TFT(pHalSsiAdaptor->TxThresholdLevel); diff --git a/USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c b/USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c index d5670c4..9eb2a3d 100644 --- a/USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c +++ b/USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c @@ -152,9 +152,8 @@ HalRuartGenBaudRateRtl8195a( u32 min_divisor=0; u32 min_err=0xffffffff; u32 uart_ovsr; - u32 uart_ovsr_mod; - u32 min_uart_ovsr; // ovsr with mini err - u32 min_uart_ovsr_mod; + u32 min_uart_ovsr = 0; // ovsr with mini err + u32 min_uart_ovsr_mod = 0; u64 uart_clock; u32 divisor_temp; u32 max_jitter_temp; @@ -201,7 +200,7 @@ HalRuartGenBaudRateRtl8195a( min_uart_ovsr = uart_ovsr/100; min_uart_ovsr_mod = uart_ovsr%100; } else if (err_temp == min_err) { - uart_ovsr_mod = uart_ovsr%100; + u32 uart_ovsr_mod = uart_ovsr%100; // we perfer OVSR bigger and adj bits smaller if (((uart_ovsr/100) >= min_uart_ovsr) && (uart_ovsr_mod < min_uart_ovsr_mod)) { min_err = err_temp; @@ -1284,7 +1283,7 @@ HalRuartStopRecvRtl8195a_Patch( if (NULL != pUartGdmaConfig) { PHAL_GDMA_ADAPTER pHalGdmaAdapter; PHAL_GDMA_OP pHalGdmaOp; - u8 IsrTypeMap; + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pRxHalGdmaAdapter; pHalGdmaOp = (PHAL_GDMA_OP)pUartGdmaConfig->pHalGdmaOp; @@ -1294,7 +1293,8 @@ HalRuartStopRecvRtl8195a_Patch( // Clean Auto Reload Bit pHalGdmaOp->HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter); // Clear Pending ISR - IsrTypeMap = pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter); +// u8 IsrTypeMap = + pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter); pHalGdmaOp->HalGdmaChDis((VOID*)(pHalGdmaAdapter)); DMA_Dar = HalGdmaQueryDArRtl8195a((VOID*)pHalGdmaAdapter); @@ -1359,7 +1359,7 @@ HalRuartStopSendRtl8195a_Patch( if (NULL != pUartGdmaConfig) { PHAL_GDMA_ADAPTER pHalGdmaAdapter; PHAL_GDMA_OP pHalGdmaOp; - u8 IsrTypeMap; + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter; pHalGdmaOp = (PHAL_GDMA_OP)pUartGdmaConfig->pHalGdmaOp; @@ -1369,7 +1369,8 @@ HalRuartStopSendRtl8195a_Patch( // Clean Auto Reload Bit pHalGdmaOp->HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter); // Clear Pending ISR - IsrTypeMap = pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter); +// u8 IsrTypeMap = + pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter); pHalGdmaOp->HalGdmaChDis((VOID*)(pHalGdmaAdapter)); DMA_Sar = HalGdmaQuerySArRtl8195a((VOID*)pHalGdmaAdapter); diff --git a/USDK/component/soc/realtek/8195a/fwlib/src/hal_adc.c b/USDK/component/soc/realtek/8195a/fwlib/src/hal_adc.c index fee78fe..a5c6abb 100644 --- a/USDK/component/soc/realtek/8195a/fwlib/src/hal_adc.c +++ b/USDK/component/soc/realtek/8195a/fwlib/src/hal_adc.c @@ -533,16 +533,16 @@ ADCISRHandle( PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; PHAL_ADC_INIT_DAT pHalADCInitDat = NULL; PHAL_ADC_OP pHalADCOP = NULL; - PSAL_ADC_USER_CB pSalADCUserCB = NULL; - u8 ADCIrqIdx; +// PSAL_ADC_USER_CB pSalADCUserCB = NULL; +// u8 ADCIrqIdx; /* To get the SAL_I2C_MNGT_ADPT pointer, and parse the rest pointers */ pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv); pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv); pHalADCInitDat = pSalADCMngtAdpt->pHalInitDat; pHalADCOP = pSalADCMngtAdpt->pHalOp; - ADCIrqIdx = pHalADCInitDat->ADCIdx; - pSalADCUserCB = pSalADCHND->pUserCB; +// ADCIrqIdx = pHalADCInitDat->ADCIdx; +// pSalADCUserCB = pSalADCHND->pUserCB; DBG_8195A_ADC_LVL(HAL_ADC_LVL,"ADC INTR STS:%x\n",pHalADCOP->HalADCReadReg(pHalADCInitDat, REG_ADC_INTR_STS)); #else diff --git a/USDK/component/soc/realtek/8195a/fwlib/src/hal_gpio.c b/USDK/component/soc/realtek/8195a/fwlib/src/hal_gpio.c index 3b3c8dd..2887654 100644 --- a/USDK/component/soc/realtek/8195a/fwlib/src/hal_gpio.c +++ b/USDK/component/soc/realtek/8195a/fwlib/src/hal_gpio.c @@ -85,7 +85,7 @@ HAL_GPIO_Init( u8 port_num; u8 pin_num; u32 chip_pin; - HAL_Status ret; + if (_pHAL_Gpio_Adapter == NULL) { _pHAL_Gpio_Adapter = &gHAL_Gpio_Adapter; @@ -107,7 +107,8 @@ HAL_GPIO_Init( // Make the pin pull control default as High-Z GPIO_PullCtrl_8195a(chip_pin, HAL_GPIO_HIGHZ); - ret = HAL_GPIO_Init_8195a(GPIO_Pin); + // HAL_Status ret = + HAL_GPIO_Init_8195a(GPIO_Pin); #if CONFIG_DEBUG_LOG > 3 if (ret != HAL_OK) { GpioFunctionChk(chip_pin, DISABLE); @@ -127,11 +128,6 @@ HAL_GPIO_Irq_Init( HAL_GPIO_PIN *GPIO_Pin ) { - u8 port_num; - u8 pin_num; - u32 chip_pin; - HAL_Status ret; - if (_pHAL_Gpio_Adapter == NULL) { _pHAL_Gpio_Adapter = &gHAL_Gpio_Adapter; // DBG_GPIO_INFO("%s: Initial GPIO Adapter\n ", __FUNCTION__); @@ -145,10 +141,10 @@ HAL_GPIO_Irq_Init( // DBG_GPIO_INFO("%s: Initial GPIO IRQ Adapter\n ", __FUNCTION__); } - port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name); - pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name); - chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num); #if CONFIG_DEBUG_LOG > 3 + u8 port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name); + u8 pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name); + u32 chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num); if (GpioFunctionChk(chip_pin, ENABLE) == _FALSE) { DBG_GPIO_ERR("HAL_GPIO_Irq_Init: GPIO Pin(%x) Unavailable\n ", chip_pin); return; @@ -157,7 +153,8 @@ HAL_GPIO_Irq_Init( DBG_GPIO_INFO("HAL_GPIO_Irq_Init: GPIO(name=0x%x)(mode=%d)\n ", GPIO_Pin->pin_name, GPIO_Pin->pin_mode); HAL_GPIO_MaskIrq_8195a(GPIO_Pin); - ret = HAL_GPIO_Init_8195a(GPIO_Pin); +// HAL_Status ret = + HAL_GPIO_Init_8195a(GPIO_Pin); #if CONFIG_DEBUG_LOG > 3 if (ret != HAL_OK) { GpioFunctionChk(chip_pin, DISABLE); @@ -196,16 +193,13 @@ HAL_GPIO_DeInit( HAL_GPIO_PIN *GPIO_Pin ) { - u8 port_num; - u8 pin_num; - u32 chip_pin; - - port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name); - pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name); - chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num); +#if CONFIG_DEBUG_LOG > 3 + u8 port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name); + u8 pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name); +#endif HAL_GPIO_DeInit_8195a(GPIO_Pin); #if CONFIG_DEBUG_LOG > 3 - GpioFunctionChk(chip_pin, DISABLE); + GpioFunctionChk(GPIO_GetChipPinName_8195a(port_num, pin_num), DISABLE); #endif } diff --git a/USDK/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c b/USDK/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c index 65b2ad2..1051f1d 100644 --- a/USDK/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c +++ b/USDK/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c @@ -150,11 +150,13 @@ unsigned int rand_x = 123456789; */ #ifdef CONFIG_SDR_EN +#ifndef __GNUC__ //#pragma arm section code = ".hal.sdrc.text" #pragma arm section rodata = ".rodata.hal.sdrc" //, rwdata = ".hal.sdrc.data" //, zidata = ".hal.sdrc.bss" //#pragma arm section bss = ".hal.sdrc.bss" +#endif #ifdef CONFIG_SDR_VERIFY enum{ @@ -448,13 +450,10 @@ DramInit ( u32 CrTwr, DramMaxWr, DramWr; u32 CrTrtw = 0, CrTrtwT = 0; u32 DrmaPeriod; - DRAM_TYPE DdrType; + DRAM_TYPE DdrType = DRAM_SDR; DRAM_DQ_WIDTH DqWidth; DRAM_COLADDR_WTH Page; u32 DfiRate; - volatile struct ms_rxi310_portmap *ms_ctrl_0_map; - ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE; -// ms_ctrl_0_map = ms_ctrl_0_map; DfiRate = 1 << (u32) (DramInfo->DfiRate); DrmaPeriod = (DramInfo->DdrPeriodPs)*(DfiRate); // according DFI_RATE to setting @@ -658,6 +657,9 @@ DramInit ( // enter mem_mode HAL_SDR_WRITE32(REG_SDR_CSR,0x600); #else + volatile struct ms_rxi310_portmap *ms_ctrl_0_map; + ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE; +// ms_ctrl_0_map = ms_ctrl_0_map; // WRAP_MISC setting ms_ctrl_0_map->misc = //0x12; ( @@ -753,7 +755,8 @@ SdrCalibration( DBG_8195A("%s()\n", __func__); u32 RdPipe = 0, TapCnt = 0, Pass = 0, AvaWdsCnt = 0; u32 RdPipeCounter, RecNum[2], RecRdPipe[2];//, AvaWds[2][REC_NUM]; - BOOL RdPipeFlag, PassFlag = 0, Result; + BOOL RdPipeFlag, Result; +// BOOL PassFlag = 0; u8 flashtype = 0; flashtype = SpicInitParaAllClk[0][0].flashtype; @@ -829,7 +832,7 @@ SdrCalibration( #endif RdPipeFlag = _FALSE; - PassFlag = _FALSE; +// PassFlag = _FALSE; AvaWdsCnt = 0; for(TapCnt=0; TapCnt < (MAX_TAP_DLY+1); TapCnt++) { @@ -853,7 +856,7 @@ SdrCalibration( #endif Pass = MemTest(10000); - PassFlag = _FALSE; +// PassFlag = _FALSE; if(Pass==_TRUE) { // PASS @@ -876,7 +879,7 @@ SdrCalibration( break; } - PassFlag = _TRUE; +// PassFlag = _TRUE; DBG_SDR_INFO("Verify Pass => RdPipe:%d; TapCnt: %d\n", RdPipe, TapCnt); diff --git a/USDK/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c b/USDK/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c index 6e556b3..09f0806 100644 --- a/USDK/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c +++ b/USDK/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c @@ -553,7 +553,7 @@ VOID SleepPwrGatted( //3 1.1 Set TU timer timescale //0x4000_0090[21:16] = 6'h1F //0x4000_0090[15] = 1'b0 => Disable timer - u32 CalTemp = (CLKCal(ANACK) << 16); +// u32 CalTemp = (CLKCal(ANACK) << 16); Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL) & (~((BIT_MASK_SYS_DSTDY_TIM_SCAL << BIT_SHIFT_SYS_DSTDY_TIM_SCAL) | (BIT_MASK_SYS_ANACK_TU_TIME << BIT_SHIFT_SYS_ANACK_TU_TIME)))) | ScaleTemp; @@ -620,7 +620,7 @@ DStandby( //3 1.1 Set TU timer timescale //0x4000_0090[21:16] = 6'h1F //0x4000_0090[15] = 1'b0 => Disable timer - u32 CalTemp = (CLKCal(ANACK) << 16); +// u32 CalTemp = (CLKCal(ANACK) << 16); Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL) & (~((BIT_MASK_SYS_DSTDY_TIM_SCAL << BIT_SHIFT_SYS_DSTDY_TIM_SCAL) | (BIT_MASK_SYS_ANACK_TU_TIME << BIT_SHIFT_SYS_ANACK_TU_TIME)))) | ScaleTemp; @@ -678,8 +678,6 @@ DSleep( u32 UTemp = 0; u32 MaxTemp = 0; - u32 Reada335; - //2 Deep Sleep mode: //3 2.1 Set TU timer timescale @@ -729,9 +727,8 @@ DSleep( HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); HalDelayUs(1000); - Reada335 = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CAL_CTRL); #if CONFIG_DEBUG_LOG > 3 - DiagPrintf("a33 timer : 0x%x\n", Reada335); + DiagPrintf("a33 timer : 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CAL_CTRL)); #endif HalDelayUs(8000); diff --git a/USDK/component/soc/realtek/8195a/fwlib/src/hal_ssi.c b/USDK/component/soc/realtek/8195a/fwlib/src/hal_ssi.c index 96c92f9..d7bb997 100644 --- a/USDK/component/soc/realtek/8195a/fwlib/src/hal_ssi.c +++ b/USDK/component/soc/realtek/8195a/fwlib/src/hal_ssi.c @@ -527,7 +527,7 @@ HalSsiInit(VOID *Data) { HAL_Status ret; PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data; - u32 Function; + u32 Function = SPI0; u8 PinmuxSelect; u8 Index; diff --git a/USDK/component/soc/realtek/8195a/fwlib/src/hal_uart.c b/USDK/component/soc/realtek/8195a/fwlib/src/hal_uart.c index 2b3fe3c..8448b1c 100644 --- a/USDK/component/soc/realtek/8195a/fwlib/src/hal_uart.c +++ b/USDK/component/soc/realtek/8195a/fwlib/src/hal_uart.c @@ -1021,7 +1021,7 @@ HalRuartDmaSend( u32 BlockSize; HAL_Status ret; PUART_DMA_CONFIG pUartGdmaConfig; - PHAL_GDMA_ADAPTER pHalGdmaAdapter; +// PHAL_GDMA_ADAPTER pHalGdmaAdapter; if (((Length & 0x03)==0) && (((u32)(pTxBuf) & 0x03)==0)) { @@ -1078,7 +1078,7 @@ HalRuartDmaRecv( // u32 BlockSize; HAL_Status ret; PUART_DMA_CONFIG pUartGdmaConfig; - PHAL_GDMA_ADAPTER pHalGdmaAdapter; +// PHAL_GDMA_ADAPTER pHalGdmaAdapter; if (Length < 4096) { #if CONFIG_CHIP_E_CUT diff --git a/USDK/component/soc/realtek/8195a/misc/os/freertos_pmu_8195a.c b/USDK/component/soc/realtek/8195a/misc/os/freertos_pmu_8195a.c index 06d64ff..52b49b8 100644 --- a/USDK/component/soc/realtek/8195a/misc/os/freertos_pmu_8195a.c +++ b/USDK/component/soc/realtek/8195a/misc/os/freertos_pmu_8195a.c @@ -253,7 +253,7 @@ extern int sprintf(char* str, const char* fmt, ...); extern size_t strlen(const char *str); //#define sprintf rtl_sprintf void pmu_get_wakelock_hold_stats( char *pcWriteBuffer ) { - uint32_t i; + int i; uint32_t current_timestamp = osKernelSysTick(); *pcWriteBuffer = 0x00; @@ -265,15 +265,15 @@ void pmu_get_wakelock_hold_stats( char *pcWriteBuffer ) { for (i=0; i<32; i++) { if (last_wakelock_state[i] == 1) { - sprintf(pcWriteBuffer, "%x\t\t%d\r\n", i, hold_wakelock_time[i] + (current_timestamp - last_acquire_wakelock_time[i])); + sprintf(pcWriteBuffer, "%x\t\t%u\r\n", i, (unsigned int)( hold_wakelock_time[i] + (current_timestamp - last_acquire_wakelock_time[i]))); } else { if (hold_wakelock_time[i] > 0) { - sprintf(pcWriteBuffer, "%x\t\t%d\r\n", i, hold_wakelock_time[i]); + sprintf(pcWriteBuffer, "%x\t\t%u\r\n", i, (unsigned int)hold_wakelock_time[i]); } } pcWriteBuffer += strlen( pcWriteBuffer ); } - sprintf(pcWriteBuffer, "time passed: %d ms, system sleep %d ms\r\n", current_timestamp - base_sys_time, sys_sleep_time); + sprintf(pcWriteBuffer, "time passed: %u ms, system sleep %u ms\r\n", (unsigned int)(current_timestamp - base_sys_time), (unsigned int)sys_sleep_time); } } diff --git a/USDK/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/c_stdio.c b/USDK/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/c_stdio.c index b238bdf..de6857e 100644 --- a/USDK/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/c_stdio.c +++ b/USDK/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/c_stdio.c @@ -373,7 +373,7 @@ llatob(u_quad_t *vp, char *p, int base) char * btoa(char *dst, u_int value, int base) { - char buf[34], digit; + char buf[34], digit = 0; int i, j, rem, neg; if (value == 0) { @@ -419,7 +419,7 @@ btoa(char *dst, u_int value, int base) char * llbtoa(char *dst, u_quad_t value, int base) { - char buf[66], digit; + char buf[66], digit = 0; int i, j, rem, neg; if (value == 0) { @@ -538,7 +538,7 @@ c_vsprintf (char *d, const char *s, va_list ap) const char *t; char *p, *dst, tmp[40]; unsigned int n; - int fmt, trunc, haddot, width, base, longlong; + int fmt, trunc, haddot, width, base = 0, longlong; double dbl; #ifndef NEWFP EP ex; @@ -1081,6 +1081,7 @@ int puts (const char *s) while(*s) { HalSerialPutcRtl8195a(*s++); } + return 0; // -1 -> EOF } void vTaskDelete(void *); diff --git a/USDK/sdkset.mk b/USDK/sdkset.mk index 4592c0e..766ab6f 100644 --- a/USDK/sdkset.mk +++ b/USDK/sdkset.mk @@ -21,10 +21,10 @@ CFLAGS = -DM3 -DCONFIG_PLATFORM_8195A -DGCC_ARMCM3 -DARDUINO_SDK -DF_CPU=166666666L -DNDEBUG CFLAGS += -mcpu=cortex-m3 -mthumb -g2 -Os -std=gnu99 CFLAGS += -fno-common -fmessage-length=0 -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-short-enums -fsigned-char -CFLAGS += -Wall -CFLAGS += -Wno-old-style-declaration -Wno-pointer-sign -Wno-strict-aliasing -CFLAGS += -Wno-variadic-macros -Wno-empty-body -#CFLAGS += -Werror -Wpedantic -Wno-char-subscripts -Wno-unused-parameter +CFLAGS += -Wall -Werror +CFLAGS += -Wno-old-style-declaration -Wno-pointer-sign -Wno-strict-aliasing +CFLAGS += -Wno-variadic-macros -Wno-empty-body +#CFLAGS += -Wno-char-subscripts -Wno-unused-parameter ifdef USE_GCC_LIB LFLAGS = -mcpu=cortex-m3 -mthumb -g -Os -nostartfiles --specs=nano.specs