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pvvx 2017-09-06 20:20:53 +03:00
parent c98cbe6e00
commit 9ffd9dac1a
27 changed files with 113 additions and 119 deletions
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8
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c
View file

@ -245,7 +245,6 @@ HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor)
u32 IRQ_UNKNOWN = 999;
u32 Ctrlr0Value = 0;
u32 Ctrlr1Value = 0;
u32 SerValue;
u32 BaudrValue = 0;
u32 TxftlrValue = 0;
u32 RxftlrValue = 0;
@ -318,8 +317,7 @@ HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor)
HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR1));
}
SerValue = BIT_SER_SER(1 << (pHalSsiAdaptor->SlaveSelectEnable));
SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_SER Value: %X\n", Index, SerValue);
SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_SER Value: %X\n", Index, BIT_SER_SER(1 << (pHalSsiAdaptor->SlaveSelectEnable)));
//HAL_SSI_WRITE32(Index, REG_DW_SSI_SER, SerValue);
HalSsiSetSlaveEnableRegisterRtl8195a(Adaptor, pHalSsiAdaptor->SlaveSelectEnable);
@ -617,7 +615,6 @@ HAL_Status HalSsiSetFormatRtl8195a(VOID *Adaptor)
u32 RxftlrValue = 0;
u8 Index = pHalSsiAdaptor->Index;
u8 Role = pHalSsiAdaptor->Role;
u32 Spi_mode;
if (Index > 2) {
DBG_SSI_ERR("HalSsiSetFormatRtl8195a: Invalid SSI Idx %d\r\n", Index);
@ -639,10 +636,9 @@ HAL_Status HalSsiSetFormatRtl8195a(VOID *Adaptor)
HAL_SSI_WRITE32(Index, REG_DW_SSI_CTRLR0, Ctrlr0Value);
Spi_mode = (HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0) >>6) & 0x3;
SSI_DBG_INIT("[2] SSI%d REG_DW_SSI_CTRLR0(%X) = %X, SPI Mode = %X\n", Index,
SSI0_REG_BASE + (SSI_REG_OFF * Index) + REG_DW_SSI_CTRLR0,
HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0), Spi_mode);
HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0), (HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0) >>6) & 0x3);
//The tx threshold and rx threshold value will be reset after the spi changes its role
/* REG_DW_SSI_TXFTLR */
TxftlrValue = BIT_TXFTLR_TFT(pHalSsiAdaptor->TxThresholdLevel);

17
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c
View file

@ -152,9 +152,8 @@ HalRuartGenBaudRateRtl8195a(
u32 min_divisor=0;
u32 min_err=0xffffffff;
u32 uart_ovsr;
u32 uart_ovsr_mod;
u32 min_uart_ovsr; // ovsr with mini err
u32 min_uart_ovsr_mod;
u32 min_uart_ovsr = 0; // ovsr with mini err
u32 min_uart_ovsr_mod = 0;
u64 uart_clock;
u32 divisor_temp;
u32 max_jitter_temp;
@ -201,7 +200,7 @@ HalRuartGenBaudRateRtl8195a(
min_uart_ovsr = uart_ovsr/100;
min_uart_ovsr_mod = uart_ovsr%100;
} else if (err_temp == min_err) {
uart_ovsr_mod = uart_ovsr%100;
u32 uart_ovsr_mod = uart_ovsr%100;
// we perfer OVSR bigger and adj bits smaller
if (((uart_ovsr/100) >= min_uart_ovsr) && (uart_ovsr_mod < min_uart_ovsr_mod)) {
min_err = err_temp;
@ -1284,7 +1283,7 @@ HalRuartStopRecvRtl8195a_Patch(
if (NULL != pUartGdmaConfig) {
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
PHAL_GDMA_OP pHalGdmaOp;
u8 IsrTypeMap;
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pRxHalGdmaAdapter;
pHalGdmaOp = (PHAL_GDMA_OP)pUartGdmaConfig->pHalGdmaOp;
@ -1294,7 +1293,8 @@ HalRuartStopRecvRtl8195a_Patch(
// Clean Auto Reload Bit
pHalGdmaOp->HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter);
// Clear Pending ISR
IsrTypeMap = pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
// u8 IsrTypeMap =
pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
pHalGdmaOp->HalGdmaChDis((VOID*)(pHalGdmaAdapter));
DMA_Dar = HalGdmaQueryDArRtl8195a((VOID*)pHalGdmaAdapter);
@ -1359,7 +1359,7 @@ HalRuartStopSendRtl8195a_Patch(
if (NULL != pUartGdmaConfig) {
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
PHAL_GDMA_OP pHalGdmaOp;
u8 IsrTypeMap;
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter;
pHalGdmaOp = (PHAL_GDMA_OP)pUartGdmaConfig->pHalGdmaOp;
@ -1369,7 +1369,8 @@ HalRuartStopSendRtl8195a_Patch(
// Clean Auto Reload Bit
pHalGdmaOp->HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter);
// Clear Pending ISR
IsrTypeMap = pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
// u8 IsrTypeMap =
pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
pHalGdmaOp->HalGdmaChDis((VOID*)(pHalGdmaAdapter));
DMA_Sar = HalGdmaQuerySArRtl8195a((VOID*)pHalGdmaAdapter);

8
USDK/component/soc/realtek/8195a/fwlib/src/hal_adc.c
View file

@ -533,16 +533,16 @@ ADCISRHandle(
PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL;
PHAL_ADC_INIT_DAT pHalADCInitDat = NULL;
PHAL_ADC_OP pHalADCOP = NULL;
PSAL_ADC_USER_CB pSalADCUserCB = NULL;
u8 ADCIrqIdx;
// PSAL_ADC_USER_CB pSalADCUserCB = NULL;
// u8 ADCIrqIdx;
/* To get the SAL_I2C_MNGT_ADPT pointer, and parse the rest pointers */
pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv);
pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv);
pHalADCInitDat = pSalADCMngtAdpt->pHalInitDat;
pHalADCOP = pSalADCMngtAdpt->pHalOp;
ADCIrqIdx = pHalADCInitDat->ADCIdx;
pSalADCUserCB = pSalADCHND->pUserCB;
// ADCIrqIdx = pHalADCInitDat->ADCIdx;
// pSalADCUserCB = pSalADCHND->pUserCB;
DBG_8195A_ADC_LVL(HAL_ADC_LVL,"ADC INTR STS:%x\n",pHalADCOP->HalADCReadReg(pHalADCInitDat, REG_ADC_INTR_STS));
#else

32
USDK/component/soc/realtek/8195a/fwlib/src/hal_gpio.c
View file

@ -85,7 +85,7 @@ HAL_GPIO_Init(
u8 port_num;
u8 pin_num;
u32 chip_pin;
HAL_Status ret;
if (_pHAL_Gpio_Adapter == NULL) {
_pHAL_Gpio_Adapter = &gHAL_Gpio_Adapter;
@ -107,7 +107,8 @@ HAL_GPIO_Init(
// Make the pin pull control default as High-Z
GPIO_PullCtrl_8195a(chip_pin, HAL_GPIO_HIGHZ);
ret = HAL_GPIO_Init_8195a(GPIO_Pin);
// HAL_Status ret =
HAL_GPIO_Init_8195a(GPIO_Pin);
#if CONFIG_DEBUG_LOG > 3
if (ret != HAL_OK) {
GpioFunctionChk(chip_pin, DISABLE);
@ -127,11 +128,6 @@ HAL_GPIO_Irq_Init(
HAL_GPIO_PIN *GPIO_Pin
)
{
u8 port_num;
u8 pin_num;
u32 chip_pin;
HAL_Status ret;
if (_pHAL_Gpio_Adapter == NULL) {
_pHAL_Gpio_Adapter = &gHAL_Gpio_Adapter;
// DBG_GPIO_INFO("%s: Initial GPIO Adapter\n ", __FUNCTION__);
@ -145,10 +141,10 @@ HAL_GPIO_Irq_Init(
// DBG_GPIO_INFO("%s: Initial GPIO IRQ Adapter\n ", __FUNCTION__);
}
port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num);
#if CONFIG_DEBUG_LOG > 3
u8 port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
u8 pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
u32 chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num);
if (GpioFunctionChk(chip_pin, ENABLE) == _FALSE) {
DBG_GPIO_ERR("HAL_GPIO_Irq_Init: GPIO Pin(%x) Unavailable\n ", chip_pin);
return;
@ -157,7 +153,8 @@ HAL_GPIO_Irq_Init(
DBG_GPIO_INFO("HAL_GPIO_Irq_Init: GPIO(name=0x%x)(mode=%d)\n ", GPIO_Pin->pin_name,
GPIO_Pin->pin_mode);
HAL_GPIO_MaskIrq_8195a(GPIO_Pin);
ret = HAL_GPIO_Init_8195a(GPIO_Pin);
// HAL_Status ret =
HAL_GPIO_Init_8195a(GPIO_Pin);
#if CONFIG_DEBUG_LOG > 3
if (ret != HAL_OK) {
GpioFunctionChk(chip_pin, DISABLE);
@ -196,16 +193,13 @@ HAL_GPIO_DeInit(
HAL_GPIO_PIN *GPIO_Pin
)
{
u8 port_num;
u8 pin_num;
u32 chip_pin;
port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
chip_pin = GPIO_GetChipPinName_8195a(port_num, pin_num);
#if CONFIG_DEBUG_LOG > 3
u8 port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
u8 pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
#endif
HAL_GPIO_DeInit_8195a(GPIO_Pin);
#if CONFIG_DEBUG_LOG > 3
GpioFunctionChk(chip_pin, DISABLE);
GpioFunctionChk(GPIO_GetChipPinName_8195a(port_num, pin_num), DISABLE);
#endif
}

19
USDK/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c
View file

@ -150,11 +150,13 @@ unsigned int rand_x = 123456789;
*/
#ifdef CONFIG_SDR_EN
#ifndef __GNUC__
//#pragma arm section code = ".hal.sdrc.text"
#pragma arm section rodata = ".rodata.hal.sdrc"
//, rwdata = ".hal.sdrc.data"
//, zidata = ".hal.sdrc.bss"
//#pragma arm section bss = ".hal.sdrc.bss"
#endif
#ifdef CONFIG_SDR_VERIFY
enum{
@ -448,13 +450,10 @@ DramInit (
u32 CrTwr, DramMaxWr, DramWr;
u32 CrTrtw = 0, CrTrtwT = 0;
u32 DrmaPeriod;
DRAM_TYPE DdrType;
DRAM_TYPE DdrType = DRAM_SDR;
DRAM_DQ_WIDTH DqWidth;
DRAM_COLADDR_WTH Page;
u32 DfiRate;
volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
// ms_ctrl_0_map = ms_ctrl_0_map;
DfiRate = 1 << (u32) (DramInfo->DfiRate);
DrmaPeriod = (DramInfo->DdrPeriodPs)*(DfiRate); // according DFI_RATE to setting
@ -658,6 +657,9 @@ DramInit (
// enter mem_mode
HAL_SDR_WRITE32(REG_SDR_CSR,0x600);
#else
volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
// ms_ctrl_0_map = ms_ctrl_0_map;
// WRAP_MISC setting
ms_ctrl_0_map->misc = //0x12;
(
@ -753,7 +755,8 @@ SdrCalibration(
DBG_8195A("%s()\n", __func__);
u32 RdPipe = 0, TapCnt = 0, Pass = 0, AvaWdsCnt = 0;
u32 RdPipeCounter, RecNum[2], RecRdPipe[2];//, AvaWds[2][REC_NUM];
BOOL RdPipeFlag, PassFlag = 0, Result;
BOOL RdPipeFlag, Result;
// BOOL PassFlag = 0;
u8 flashtype = 0;
flashtype = SpicInitParaAllClk[0][0].flashtype;
@ -829,7 +832,7 @@ SdrCalibration(
#endif
RdPipeFlag = _FALSE;
PassFlag = _FALSE;
// PassFlag = _FALSE;
AvaWdsCnt = 0;
for(TapCnt=0; TapCnt < (MAX_TAP_DLY+1); TapCnt++) {
@ -853,7 +856,7 @@ SdrCalibration(
#endif
Pass = MemTest(10000);
PassFlag = _FALSE;
// PassFlag = _FALSE;
if(Pass==_TRUE) { // PASS
@ -876,7 +879,7 @@ SdrCalibration(
break;
}
PassFlag = _TRUE;
// PassFlag = _TRUE;
DBG_SDR_INFO("Verify Pass => RdPipe:%d; TapCnt: %d\n", RdPipe, TapCnt);

9
USDK/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c
View file

@ -553,7 +553,7 @@ VOID SleepPwrGatted(
//3 1.1 Set TU timer timescale
//0x4000_0090[21:16] = 6'h1F
//0x4000_0090[15] = 1'b0 => Disable timer
u32 CalTemp = (CLKCal(ANACK) << 16);
// u32 CalTemp = (CLKCal(ANACK) << 16);
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL)
& (~((BIT_MASK_SYS_DSTDY_TIM_SCAL << BIT_SHIFT_SYS_DSTDY_TIM_SCAL) | (BIT_MASK_SYS_ANACK_TU_TIME << BIT_SHIFT_SYS_ANACK_TU_TIME))))
| ScaleTemp;
@ -620,7 +620,7 @@ DStandby(
//3 1.1 Set TU timer timescale
//0x4000_0090[21:16] = 6'h1F
//0x4000_0090[15] = 1'b0 => Disable timer
u32 CalTemp = (CLKCal(ANACK) << 16);
// u32 CalTemp = (CLKCal(ANACK) << 16);
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL)
& (~((BIT_MASK_SYS_DSTDY_TIM_SCAL << BIT_SHIFT_SYS_DSTDY_TIM_SCAL) | (BIT_MASK_SYS_ANACK_TU_TIME << BIT_SHIFT_SYS_ANACK_TU_TIME))))
| ScaleTemp;
@ -678,8 +678,6 @@ DSleep(
u32 UTemp = 0;
u32 MaxTemp = 0;
u32 Reada335;
//2 Deep Sleep mode:
//3 2.1 Set TU timer timescale
@ -729,9 +727,8 @@ DSleep(
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp);
HalDelayUs(1000);
Reada335 = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CAL_CTRL);
#if CONFIG_DEBUG_LOG > 3
DiagPrintf("a33 timer : 0x%x\n", Reada335);
DiagPrintf("a33 timer : 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CAL_CTRL));
#endif
HalDelayUs(8000);

2
USDK/component/soc/realtek/8195a/fwlib/src/hal_ssi.c
View file

@ -527,7 +527,7 @@ HalSsiInit(VOID *Data)
{
HAL_Status ret;
PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
u32 Function;
u32 Function = SPI0;
u8 PinmuxSelect;
u8 Index;

4
USDK/component/soc/realtek/8195a/fwlib/src/hal_uart.c
View file

@ -1021,7 +1021,7 @@ HalRuartDmaSend(
u32 BlockSize;
HAL_Status ret;
PUART_DMA_CONFIG pUartGdmaConfig;
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
// PHAL_GDMA_ADAPTER pHalGdmaAdapter;
if (((Length & 0x03)==0) &&
(((u32)(pTxBuf) & 0x03)==0)) {
@ -1078,7 +1078,7 @@ HalRuartDmaRecv(
// u32 BlockSize;
HAL_Status ret;
PUART_DMA_CONFIG pUartGdmaConfig;
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
// PHAL_GDMA_ADAPTER pHalGdmaAdapter;
if (Length < 4096) {
#if CONFIG_CHIP_E_CUT

8
USDK/component/soc/realtek/8195a/misc/os/freertos_pmu_8195a.c
View file

@ -253,7 +253,7 @@ extern int sprintf(char* str, const char* fmt, ...);
extern size_t strlen(const char *str);
//#define sprintf rtl_sprintf
void pmu_get_wakelock_hold_stats( char *pcWriteBuffer ) {
uint32_t i;
int i;
uint32_t current_timestamp = osKernelSysTick();
*pcWriteBuffer = 0x00;
@ -265,15 +265,15 @@ void pmu_get_wakelock_hold_stats( char *pcWriteBuffer ) {
for (i=0; i<32; i++) {
if (last_wakelock_state[i] == 1) {
sprintf(pcWriteBuffer, "%x\t\t%d\r\n", i, hold_wakelock_time[i] + (current_timestamp - last_acquire_wakelock_time[i]));
sprintf(pcWriteBuffer, "%x\t\t%u\r\n", i, (unsigned int)( hold_wakelock_time[i] + (current_timestamp - last_acquire_wakelock_time[i])));
} else {
if (hold_wakelock_time[i] > 0) {
sprintf(pcWriteBuffer, "%x\t\t%d\r\n", i, hold_wakelock_time[i]);
sprintf(pcWriteBuffer, "%x\t\t%u\r\n", i, (unsigned int)hold_wakelock_time[i]);
}
}
pcWriteBuffer += strlen( pcWriteBuffer );
}
sprintf(pcWriteBuffer, "time passed: %d ms, system sleep %d ms\r\n", current_timestamp - base_sys_time, sys_sleep_time);
sprintf(pcWriteBuffer, "time passed: %u ms, system sleep %u ms\r\n", (unsigned int)(current_timestamp - base_sys_time), (unsigned int)sys_sleep_time);
}
}

7
USDK/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/c_stdio.c
View file

@ -373,7 +373,7 @@ llatob(u_quad_t *vp, char *p, int base)
char *
btoa(char *dst, u_int value, int base)
{
char buf[34], digit;
char buf[34], digit = 0;
int i, j, rem, neg;
if (value == 0) {
@ -419,7 +419,7 @@ btoa(char *dst, u_int value, int base)
char *
llbtoa(char *dst, u_quad_t value, int base)
{
char buf[66], digit;
char buf[66], digit = 0;
int i, j, rem, neg;
if (value == 0) {
@ -538,7 +538,7 @@ c_vsprintf (char *d, const char *s, va_list ap)
const char *t;
char *p, *dst, tmp[40];
unsigned int n;
int fmt, trunc, haddot, width, base, longlong;
int fmt, trunc, haddot, width, base = 0, longlong;
double dbl;
#ifndef NEWFP
EP ex;
@ -1081,6 +1081,7 @@ int puts (const char *s)
while(*s) {
HalSerialPutcRtl8195a(*s++);
}
return 0; // -1 -> EOF
}
void vTaskDelete(void *);