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https://github.com/pvvx/RTL00_HelloWorld.git
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pvvx
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125 changed files with 45637 additions and 1 deletions
377
lib/fwlib/src/hal_ssi.c
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377
lib/fwlib/src/hal_ssi.c
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#include "rtl8195a.h"
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#include "hal_ssi.h"
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const HAL_GDMA_CHNL Ssi2_TX_GDMA_Chnl_Option[] = {
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{0,4,GDMA0_CHANNEL4_IRQ,0},
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{0,5,GDMA0_CHANNEL5_IRQ,0},
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{0,3,GDMA0_CHANNEL3_IRQ,0},
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{0,0,GDMA0_CHANNEL0_IRQ,0},
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{0,1,GDMA0_CHANNEL1_IRQ,0},
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{0,2,GDMA0_CHANNEL2_IRQ,0},
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{0xff,0,0,0} // end
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};
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const HAL_GDMA_CHNL Ssi2_RX_GDMA_Chnl_Option[] = {
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{1,4,GDMA1_CHANNEL4_IRQ,0},
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{1,5,GDMA1_CHANNEL5_IRQ,0},
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{1,3,GDMA1_CHANNEL3_IRQ,0},
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{1,0,GDMA1_CHANNEL0_IRQ,0},
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{1,1,GDMA1_CHANNEL1_IRQ,0},
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{1,2,GDMA1_CHANNEL2_IRQ,0},
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{0xff,0,0,0} // end
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};
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//TODO: Load default Setting: It should be loaded from external setting file.
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const DW_SSI_DEFAULT_SETTING SpiDefaultSetting =
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{
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.RxCompCallback = NULL,
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.RxCompCbPara = NULL,
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.RxData = NULL,
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.TxCompCallback = NULL,
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.TxCompCbPara = NULL,
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.TxData = NULL,
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.DmaRxDataLevel = 7, // RX FIFO stored bytes > (DMARDLR(7) + 1) then trigger DMA transfer
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.DmaTxDataLevel = 48, // TX FIFO free space > (FIFO_SPACE(64)-DMATDLR(48)) then trigger DMA transfer
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.InterruptPriority = 0x20,
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.RxLength = 0,
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.RxLengthRemainder = 0,
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.RxThresholdLevel = 7, // if number of entries in th RX FIFO >= (RxThresholdLevel+1), RX interrupt asserted
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.TxLength = 0,
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.TxThresholdLevel = 8, // if number of entries in th TX FIFO <= TxThresholdLevel, TX interrupt asserted
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.SlaveSelectEnable = 0,
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.ClockDivider = SSI_CLK_SPI0_2/1000000, // SCLK=1M
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.DataFrameNumber = 0,
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.ControlFrameSize = CFS_1_BIT,
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.DataFrameFormat = FRF_MOTOROLA_SPI,
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.DataFrameSize = DFS_8_BITS,
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.DmaControl = 0, // default DMA is disable
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.InterruptMask = 0x0,
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.MicrowireDirection = MW_DIRECTION_MASTER_TO_SLAVE,
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.MicrowireHandshaking = MW_HANDSHAKE_DISABLE,
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.MicrowireTransferMode = MW_TMOD_NONSEQUENTIAL,
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.SclkPhase = SCPH_TOGGLES_AT_START,
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.SclkPolarity = SCPOL_INACTIVE_IS_HIGH,
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.SlaveOutputEnable = SLV_TXD_ENABLE, // Slave
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.TransferMode = TMOD_TR,
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.TransferMechanism = SSI_DTM_INTERRUPT
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};
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extern HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor);
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extern HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor);
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extern HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor);
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extern HAL_Status HalSsiDeInitRtl8195a(VOID * Adapter);
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extern HAL_Status HalSsiClockOffRtl8195a(VOID * Adapter);
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extern HAL_Status HalSsiClockOnRtl8195a(VOID * Adapter);
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extern HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length);
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extern HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
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extern VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate);
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#ifdef CONFIG_GDMA_EN
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extern VOID HalSsiDmaInitRtl8195a(VOID *Adapter);
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#endif
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VOID HalSsiOpInit(VOID *Adaptor)
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{
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PHAL_SSI_OP pHalSsiOp = (PHAL_SSI_OP) Adaptor;
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// pHalSsiOp->HalSsiPinmuxEnable = HalSsiPinmuxEnableRtl8195a;
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pHalSsiOp->HalSsiPinmuxEnable = HalSsiPinmuxEnableRtl8195a_Patch;
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pHalSsiOp->HalSsiPinmuxDisable = HalSsiPinmuxDisableRtl8195a;
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pHalSsiOp->HalSsiEnable = HalSsiEnableRtl8195a;
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pHalSsiOp->HalSsiDisable = HalSsiDisableRtl8195a;
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// pHalSsiOp->HalSsiInit = HalSsiInitRtl8195a;
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pHalSsiOp->HalSsiInit = HalSsiInitRtl8195a_Patch;
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pHalSsiOp->HalSsiSetSclkPolarity = HalSsiSetSclkPolarityRtl8195a;
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pHalSsiOp->HalSsiSetSclkPhase = HalSsiSetSclkPhaseRtl8195a;
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pHalSsiOp->HalSsiWrite = HalSsiWriteRtl8195a;
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pHalSsiOp->HalSsiRead = HalSsiReadRtl8195a;
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pHalSsiOp->HalSsiGetRxFifoLevel = HalSsiGetRxFifoLevelRtl8195a;
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pHalSsiOp->HalSsiGetTxFifoLevel = HalSsiGetTxFifoLevelRtl8195a;
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pHalSsiOp->HalSsiGetStatus = HalSsiGetStatusRtl8195a;
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pHalSsiOp->HalSsiGetInterruptStatus = HalSsiGetInterruptStatusRtl8195a;
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pHalSsiOp->HalSsiLoadSetting = HalSsiLoadSettingRtl8195a;
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pHalSsiOp->HalSsiSetInterruptMask = HalSsiSetInterruptMaskRtl8195a;
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pHalSsiOp->HalSsiGetInterruptMask = HalSsiGetInterruptMaskRtl8195a;
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pHalSsiOp->HalSsiSetDeviceRole = HalSsiSetDeviceRoleRtl8195a;
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pHalSsiOp->HalSsiWriteable = HalSsiWriteableRtl8195a;
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pHalSsiOp->HalSsiReadable = HalSsiReadableRtl8195a;
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pHalSsiOp->HalSsiBusy = HalSsiBusyRtl8195a;
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pHalSsiOp->HalSsiInterruptEnable = HalSsiInterruptEnableRtl8195a;
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pHalSsiOp->HalSsiInterruptDisable = HalSsiInterruptDisableRtl8195a;
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// pHalSsiOp->HalSsiReadInterrupt = HalSsiReadInterruptRtl8195a;
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pHalSsiOp->HalSsiReadInterrupt = HalSsiIntReadRtl8195a;
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pHalSsiOp->HalSsiSetRxFifoThresholdLevel = HalSsiSetRxFifoThresholdLevelRtl8195a;
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pHalSsiOp->HalSsiSetTxFifoThresholdLevel = HalSsiSetTxFifoThresholdLevelRtl8195a;
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// pHalSsiOp->HalSsiWriteInterrupt = HalSsiWriteInterruptRtl8195a;
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pHalSsiOp->HalSsiWriteInterrupt = HalSsiIntWriteRtl8195a;
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pHalSsiOp->HalSsiGetRawInterruptStatus = HalSsiGetRawInterruptStatusRtl8195a;
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pHalSsiOp->HalSsiGetSlaveEnableRegister = HalSsiGetSlaveEnableRegisterRtl8195a;
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pHalSsiOp->HalSsiSetSlaveEnableRegister = HalSsiSetSlaveEnableRegisterRtl8195a;
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}
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#ifdef CONFIG_GDMA_EN
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HAL_Status
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HalSsiTxGdmaInit(
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IN PHAL_SSI_OP pHalSsiOp,
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IN PHAL_SSI_ADAPTOR pHalSsiAdapter
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)
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{
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PHAL_GDMA_ADAPTER pHalGdmaAdapter;
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PSSI_DMA_CONFIG pDmaConfig;
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HAL_GDMA_CHNL *pgdma_chnl;
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PHAL_GDMA_OP pHalGdmaOp;
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if ((NULL == pHalSsiOp) || (NULL == pHalSsiAdapter)) {
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return HAL_ERR_PARA;
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}
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pDmaConfig = &pHalSsiAdapter->DmaConfig;
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// Load default setting
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HalSsiTxGdmaLoadDefRtl8195a((void*)pHalSsiAdapter);
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// Start to patch the default setting
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pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter;
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if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) {
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// The default GDMA Channel is not available, try others
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if (pHalSsiAdapter->Index == 2) {
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// SSI2 TX Only can use GDMA 0
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pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Ssi2_TX_GDMA_Chnl_Option);
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}
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else {
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pgdma_chnl = HalGdmaChnlAlloc(NULL);
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}
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if (pgdma_chnl == NULL) {
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// No Available DMA channel
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return HAL_BUSY;
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}
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else {
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pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx;
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pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl;
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pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl;
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pDmaConfig->TxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum;
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}
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}
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DBG_SSI_INFO("HalSsiTxGdmaInit: GdmaIndex=%d ChNum=%d \r\n", pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum);
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pHalGdmaOp = (PHAL_GDMA_OP)pDmaConfig->pHalGdmaOp;
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pHalGdmaOp->HalGdmaOnOff((VOID*)(pHalGdmaAdapter));
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pHalGdmaOp->HalGdmaChIsrEnAndDis((VOID*)(pHalGdmaAdapter));
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HalSsiDmaInit(pHalSsiAdapter);
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InterruptRegister(&pDmaConfig->TxGdmaIrqHandle);
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InterruptEn(&pDmaConfig->TxGdmaIrqHandle);
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return HAL_OK;
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}
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VOID
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HalSsiTxGdmaDeInit(
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IN PHAL_SSI_ADAPTOR pHalSsiAdapter
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)
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{
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PSSI_DMA_CONFIG pDmaConfig;
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PHAL_GDMA_ADAPTER pHalGdmaAdapter;
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HAL_GDMA_CHNL GdmaChnl;
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if (NULL == pHalSsiAdapter) {
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return;
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}
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pDmaConfig = &pHalSsiAdapter->DmaConfig;
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pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter;
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GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
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GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
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GdmaChnl.IrqNum = pDmaConfig->TxGdmaIrqHandle.IrqNum;
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HalGdmaChnlFree(&GdmaChnl);
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}
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HAL_Status
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HalSsiRxGdmaInit(
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IN PHAL_SSI_OP pHalSsiOp,
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IN PHAL_SSI_ADAPTOR pHalSsiAdapter
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)
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{
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PHAL_GDMA_ADAPTER pHalGdmaAdapter;
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PSSI_DMA_CONFIG pDmaConfig;
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HAL_GDMA_CHNL *pgdma_chnl;
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PHAL_GDMA_OP pHalGdmaOp;
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if ((NULL == pHalSsiOp) || (NULL == pHalSsiAdapter)) {
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return HAL_ERR_PARA;
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}
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pDmaConfig = &pHalSsiAdapter->DmaConfig;
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// Load default setting
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HalSsiRxGdmaLoadDefRtl8195a((void*)pHalSsiAdapter);
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// Start to patch the default setting
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pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter;
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if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) {
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// The default GDMA Channel is not available, try others
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if (pHalSsiAdapter->Index == 2) {
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// SSI2 RX Only can use GDMA 1
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pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Ssi2_RX_GDMA_Chnl_Option);
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}
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else {
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pgdma_chnl = HalGdmaChnlAlloc(NULL);
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}
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if (pgdma_chnl == NULL) {
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// No Available DMA channel
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return HAL_BUSY;
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}
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else {
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pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx;
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pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl;
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pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl;
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pDmaConfig->RxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum;
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}
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}
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DBG_SSI_INFO("HalSsiRxGdmaInit: GdmaIndex=%d ChNum=%d \r\n", pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum);
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pHalGdmaOp = (PHAL_GDMA_OP)pDmaConfig->pHalGdmaOp;
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pHalGdmaOp->HalGdmaOnOff((VOID*)(pHalGdmaAdapter));
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pHalGdmaOp->HalGdmaChIsrEnAndDis((VOID*)(pHalGdmaAdapter));
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HalSsiDmaInit(pHalSsiAdapter);
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InterruptRegister(&pDmaConfig->RxGdmaIrqHandle);
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InterruptEn(&pDmaConfig->RxGdmaIrqHandle);
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return HAL_OK;
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}
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VOID
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HalSsiRxGdmaDeInit(
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IN PHAL_SSI_ADAPTOR pHalSsiAdapter
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)
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{
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PSSI_DMA_CONFIG pDmaConfig;
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PHAL_GDMA_ADAPTER pHalGdmaAdapter;
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HAL_GDMA_CHNL GdmaChnl;
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if (NULL == pHalSsiAdapter) {
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return;
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}
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pDmaConfig = &pHalSsiAdapter->DmaConfig;
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pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter;
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GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
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GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
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GdmaChnl.IrqNum = pDmaConfig->RxGdmaIrqHandle.IrqNum;
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HalGdmaChnlFree(&GdmaChnl);
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}
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#endif // end of "#ifdef CONFIG_GDMA_EN"
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HAL_Status
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HalSsiInit(VOID *Data)
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{
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HAL_Status ret;
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PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
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#ifdef CONFIG_SOC_PS_MODULE
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REG_POWER_STATE SsiPwrState;
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#endif
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ret = HalSsiInitRtl8195a_Patch(pHalSsiAdapter);
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#ifdef CONFIG_SOC_PS_MODULE
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if(ret == HAL_OK) {
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// To register a new peripheral device power state
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SsiPwrState.FuncIdx = SPI0+ pHalSsiAdapter->Index;
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SsiPwrState.PwrState = ACT;
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RegPowerState(SsiPwrState);
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}
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#endif
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return ret;
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}
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HAL_Status
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HalSsiDeInit(VOID *Data)
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{
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HAL_Status ret;
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PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
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#ifdef CONFIG_SOC_PS_MODULE
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REG_POWER_STATE SsiPwrState;
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u8 HardwareState;
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SsiPwrState.FuncIdx= SPI0+ pHalSsiAdapter->Index;
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QueryRegPwrState(SsiPwrState.FuncIdx, &(SsiPwrState.PwrState), &HardwareState);
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if(SsiPwrState.PwrState != HardwareState){
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DBG_SSI_ERR("Registered State is not the Hardware State");
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return HAL_ERR_UNKNOWN;
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}
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else{
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if((SsiPwrState.PwrState != INACT) && (SsiPwrState.PwrState !=ACT)){
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DBG_SSI_INFO("Return to ACT state before DeInit");
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HalSsiEnable(pHalSsiAdapter);
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QueryRegPwrState(SsiPwrState.FuncIdx, &(SsiPwrState.PwrState), &HardwareState);
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}
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if(SsiPwrState.PwrState == ACT){
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SsiPwrState.PwrState = INACT;
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RegPowerState(SsiPwrState);
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}
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}
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#endif
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ret = HalSsiDeInitRtl8195a(pHalSsiAdapter);
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return ret;
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}
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HAL_Status
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HalSsiEnable(VOID *Data)
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{
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HAL_Status ret;
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PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
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#ifdef CONFIG_SOC_PS_MODULE
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REG_POWER_STATE SsiPwrState;
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#endif
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ret = HalSsiClockOnRtl8195a(pHalSsiAdapter);
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#ifdef CONFIG_SOC_PS_MODULE
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if(ret == HAL_OK) {
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// To register a new peripheral device power state
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SsiPwrState.FuncIdx = SPI0+ pHalSsiAdapter->Index;
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SsiPwrState.PwrState = ACT;
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RegPowerState(SsiPwrState);
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}
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#endif
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return ret;
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}
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HAL_Status
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HalSsiDisable(VOID *Data)
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{
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HAL_Status ret;
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PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
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#ifdef CONFIG_SOC_PS_MODULE
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REG_POWER_STATE SsiPwrState;
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#endif
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ret = HalSsiClockOffRtl8195a(pHalSsiAdapter);
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#ifdef CONFIG_SOC_PS_MODULE
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if(ret == HAL_OK) {
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// To register a new peripheral device power state
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SsiPwrState.FuncIdx = SPI0+ pHalSsiAdapter->Index;
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SsiPwrState.PwrState = SLPCG;
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RegPowerState(SsiPwrState);
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}
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#endif
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return ret;
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}
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