From 56693eef0de6ce552ef9abf14e2a4d2108a645ac Mon Sep 17 00:00:00 2001 From: pvvx Date: Tue, 13 Sep 2016 12:31:00 +0300 Subject: [PATCH] initial --- .cproject | 164 + .gitignore | 5 + .project | 26 + .settings/org.eclipse.cdt.codan.core.prefs | 67 + .settings/org.eclipse.cdt.core.prefs | 29 + LICENSE | 36 + Makefile | 62 + README.md | 25 +- lib/basic_types.h | 501 +++ lib/cpu/cortex/cortex.c | 1069 +++++ lib/cpu/cortex/cortex.h | 79 + lib/cpu/cortex/cortex.ocd | 14 + lib/cpu/rtl8710/export-rom_v03.txt | 737 ++++ lib/cpu/rtl8710/rtl8710.h | 13 + lib/cpu/rtl8710/rtl8710.ld | 48 + lib/cpu/rtl8710/rtl8710.ocd | 332 ++ lib/cpu/rtl8710/rtl8710_gpio.h | 37 + lib/cpu/rtl8710/rtl8710_int.h | 53 + lib/cpu/rtl8710/rtl8710_log_uart.h | 76 + lib/cpu/rtl8710/rtl8710_peri_on.h | 128 + lib/cpu/rtl8710/rtl8710_spi.h | 100 + lib/cpu/rtl8710/rtl8710_sys.h | 106 + lib/cpu/rtl8710/rtl8710_timer.h | 35 + lib/fwlib/hal_adc.h | 319 ++ lib/fwlib/hal_api.h | 126 + lib/fwlib/hal_common.h | 17 + lib/fwlib/hal_crypto.h | 213 + lib/fwlib/hal_dac.h | 313 ++ lib/fwlib/hal_diag.h | 107 + lib/fwlib/hal_efuse.h | 22 + lib/fwlib/hal_gdma.h | 141 + lib/fwlib/hal_gpio.h | 236 ++ lib/fwlib/hal_i2c.h | 585 +++ lib/fwlib/hal_i2s.h | 347 ++ lib/fwlib/hal_irqn.h | 112 + lib/fwlib/hal_mii.h | 118 + lib/fwlib/hal_misc.h | 30 + lib/fwlib/hal_nfc.h | 22 + lib/fwlib/hal_pcm.h | 104 + lib/fwlib/hal_peri_on.h | 451 +++ lib/fwlib/hal_pinmux.h | 64 + lib/fwlib/hal_platform.h | 102 + lib/fwlib/hal_pwm.h | 57 + lib/fwlib/hal_sdio.h | 252 ++ lib/fwlib/hal_sdr_controller.h | 188 + lib/fwlib/hal_soc_ps_monitor.h | 278 ++ lib/fwlib/hal_spi_flash.h | 254 ++ lib/fwlib/hal_ssi.h | 309 ++ lib/fwlib/hal_timer.h | 59 + lib/fwlib/hal_uart.h | 204 + lib/fwlib/hal_usb.h | 15 + lib/fwlib/hal_util.h | 252 ++ lib/fwlib/hal_vector_table.h | 53 + lib/fwlib/rtl8195a/rtl8195a.h | 157 + lib/fwlib/rtl8195a/rtl8195a_adc.h | 350 ++ lib/fwlib/rtl8195a/rtl8195a_dac.h | 294 ++ lib/fwlib/rtl8195a/rtl8195a_gdma.h | 522 +++ lib/fwlib/rtl8195a/rtl8195a_gpio.h | 352 ++ lib/fwlib/rtl8195a/rtl8195a_i2c.h | 851 ++++ lib/fwlib/rtl8195a/rtl8195a_i2s.h | 617 +++ lib/fwlib/rtl8195a/rtl8195a_mii.h | 674 ++++ lib/fwlib/rtl8195a/rtl8195a_nfc.h | 153 + lib/fwlib/rtl8195a/rtl8195a_pcm.h | 449 +++ lib/fwlib/rtl8195a/rtl8195a_peri_on.h | 1251 ++++++ lib/fwlib/rtl8195a/rtl8195a_pwm.h | 37 + lib/fwlib/rtl8195a/rtl8195a_sdio.h | 1019 +++++ lib/fwlib/rtl8195a/rtl8195a_sdio_host.h | 295 ++ lib/fwlib/rtl8195a/rtl8195a_sdr.h | 379 ++ lib/fwlib/rtl8195a/rtl8195a_spi_flash.h | 990 +++++ lib/fwlib/rtl8195a/rtl8195a_ssi.h | 498 +++ lib/fwlib/rtl8195a/rtl8195a_sys_on.h | 1093 ++++++ lib/fwlib/rtl8195a/rtl8195a_timer.h | 222 ++ lib/fwlib/rtl8195a/rtl8195a_uart.h | 532 +++ lib/fwlib/rtl8195a/rtl8195a_wdt.h | 86 + lib/fwlib/rtl8195a/src/rtl8195a_adc.c | 387 ++ lib/fwlib/rtl8195a/src/rtl8195a_dac.c | 269 ++ lib/fwlib/rtl8195a/src/rtl8195a_gdma.c | 291 ++ lib/fwlib/rtl8195a/src/rtl8195a_gpio.c | 53 + lib/fwlib/rtl8195a/src/rtl8195a_i2c.c | 408 ++ lib/fwlib/rtl8195a/src/rtl8195a_i2s.c | 395 ++ lib/fwlib/rtl8195a/src/rtl8195a_mii.c | 325 ++ lib/fwlib/rtl8195a/src/rtl8195a_nfc.c | 1921 +++++++++ lib/fwlib/rtl8195a/src/rtl8195a_pcm.c | 360 ++ lib/fwlib/rtl8195a/src/rtl8195a_pwm.c | 219 ++ lib/fwlib/rtl8195a/src/rtl8195a_sdio_device.c | 3177 +++++++++++++++ lib/fwlib/rtl8195a/src/rtl8195a_ssi.c | 1271 ++++++ lib/fwlib/rtl8195a/src/rtl8195a_timer.c | 323 ++ lib/fwlib/rtl8195a/src/rtl8195a_uart.c | 1013 +++++ lib/fwlib/rtl8195a_usb.h | 111 + lib/fwlib/src/hal_32k.c | 293 ++ lib/fwlib/src/hal_adc.c | 1603 ++++++++ lib/fwlib/src/hal_common.c | 23 + lib/fwlib/src/hal_dac.c | 1450 +++++++ lib/fwlib/src/hal_gdma.c | 574 +++ lib/fwlib/src/hal_gpio.c | 145 + lib/fwlib/src/hal_i2c.c | 2694 +++++++++++++ lib/fwlib/src/hal_i2s.c | 535 +++ lib/fwlib/src/hal_mii.c | 42 + lib/fwlib/src/hal_nfc.c | 20 + lib/fwlib/src/hal_pcm.c | 28 + lib/fwlib/src/hal_pwm.c | 131 + lib/fwlib/src/hal_sdr_controller.c | 971 +++++ lib/fwlib/src/hal_soc_ps_monitor.c | 3449 +++++++++++++++++ lib/fwlib/src/hal_ssi.c | 377 ++ lib/fwlib/src/hal_timer.c | 32 + lib/fwlib/src/hal_uart.c | 871 +++++ lib/libc/assert.h | 7 + lib/libc/ctype.h | 7 + lib/libc/libc.c | 863 +++++ lib/libc/stddef.h | 7 + lib/libc/stdio.h | 111 + lib/libc/stdlib.h | 7 + lib/libc/string.h | 7 + lib/libc/time.h | 7 + lib/mask.h | 19 + lib/rom_lib.h | 94 + lib/rtl_consol.h | 133 + lib/rtl_std_lib/include/rt_lib_rom.h | 254 ++ lib/rtl_std_lib/include/rtl_lib.h | 141 + .../libc/rom/string/rom_libc_string.h | 45 + .../rtl8195a/rom/rom_libgloss_retarget.h | 37 + lib/strproc.h | 106 + lib/va_list.h | 37 + main.c | 36 + rtl8710_flash_boot.s | 46 + 125 files changed, 45637 insertions(+), 1 deletion(-) create mode 100644 .cproject create mode 100644 .gitignore create mode 100644 .project create mode 100644 .settings/org.eclipse.cdt.codan.core.prefs create mode 100644 .settings/org.eclipse.cdt.core.prefs create mode 100644 LICENSE create mode 100644 Makefile create mode 100644 lib/basic_types.h create mode 100644 lib/cpu/cortex/cortex.c create mode 100644 lib/cpu/cortex/cortex.h create mode 100644 lib/cpu/cortex/cortex.ocd create mode 100644 lib/cpu/rtl8710/export-rom_v03.txt create mode 100644 lib/cpu/rtl8710/rtl8710.h create mode 100644 lib/cpu/rtl8710/rtl8710.ld create mode 100644 lib/cpu/rtl8710/rtl8710.ocd create mode 100644 lib/cpu/rtl8710/rtl8710_gpio.h create mode 100644 lib/cpu/rtl8710/rtl8710_int.h create mode 100644 lib/cpu/rtl8710/rtl8710_log_uart.h create mode 100644 lib/cpu/rtl8710/rtl8710_peri_on.h create mode 100644 lib/cpu/rtl8710/rtl8710_spi.h create mode 100644 lib/cpu/rtl8710/rtl8710_sys.h create mode 100644 lib/cpu/rtl8710/rtl8710_timer.h create mode 100644 lib/fwlib/hal_adc.h create mode 100644 lib/fwlib/hal_api.h create mode 100644 lib/fwlib/hal_common.h create mode 100644 lib/fwlib/hal_crypto.h create mode 100644 lib/fwlib/hal_dac.h create mode 100644 lib/fwlib/hal_diag.h create mode 100644 lib/fwlib/hal_efuse.h create mode 100644 lib/fwlib/hal_gdma.h create mode 100644 lib/fwlib/hal_gpio.h create mode 100644 lib/fwlib/hal_i2c.h create mode 100644 lib/fwlib/hal_i2s.h create mode 100644 lib/fwlib/hal_irqn.h create mode 100644 lib/fwlib/hal_mii.h create mode 100644 lib/fwlib/hal_misc.h create mode 100644 lib/fwlib/hal_nfc.h create mode 100644 lib/fwlib/hal_pcm.h create mode 100644 lib/fwlib/hal_peri_on.h create mode 100644 lib/fwlib/hal_pinmux.h create mode 100644 lib/fwlib/hal_platform.h create mode 100644 lib/fwlib/hal_pwm.h create mode 100644 lib/fwlib/hal_sdio.h create mode 100644 lib/fwlib/hal_sdr_controller.h create mode 100644 lib/fwlib/hal_soc_ps_monitor.h create mode 100644 lib/fwlib/hal_spi_flash.h create mode 100644 lib/fwlib/hal_ssi.h create mode 100644 lib/fwlib/hal_timer.h create mode 100644 lib/fwlib/hal_uart.h create mode 100644 lib/fwlib/hal_usb.h create mode 100644 lib/fwlib/hal_util.h create mode 100644 lib/fwlib/hal_vector_table.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_adc.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_dac.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_gdma.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_gpio.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_i2c.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_i2s.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_mii.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_nfc.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_pcm.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_peri_on.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_pwm.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_sdio.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_sdio_host.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_sdr.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_spi_flash.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_ssi.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_sys_on.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_timer.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_uart.h create mode 100644 lib/fwlib/rtl8195a/rtl8195a_wdt.h create mode 100644 lib/fwlib/rtl8195a/src/rtl8195a_adc.c create mode 100644 lib/fwlib/rtl8195a/src/rtl8195a_dac.c create mode 100644 lib/fwlib/rtl8195a/src/rtl8195a_gdma.c create mode 100644 lib/fwlib/rtl8195a/src/rtl8195a_gpio.c create mode 100644 lib/fwlib/rtl8195a/src/rtl8195a_i2c.c create mode 100644 lib/fwlib/rtl8195a/src/rtl8195a_i2s.c create mode 100644 lib/fwlib/rtl8195a/src/rtl8195a_mii.c create mode 100644 lib/fwlib/rtl8195a/src/rtl8195a_nfc.c create mode 100644 lib/fwlib/rtl8195a/src/rtl8195a_pcm.c create mode 100644 lib/fwlib/rtl8195a/src/rtl8195a_pwm.c create mode 100644 lib/fwlib/rtl8195a/src/rtl8195a_sdio_device.c create mode 100644 lib/fwlib/rtl8195a/src/rtl8195a_ssi.c create mode 100644 lib/fwlib/rtl8195a/src/rtl8195a_timer.c create mode 100644 lib/fwlib/rtl8195a/src/rtl8195a_uart.c create mode 100644 lib/fwlib/rtl8195a_usb.h create mode 100644 lib/fwlib/src/hal_32k.c create mode 100644 lib/fwlib/src/hal_adc.c create mode 100644 lib/fwlib/src/hal_common.c create mode 100644 lib/fwlib/src/hal_dac.c create mode 100644 lib/fwlib/src/hal_gdma.c create mode 100644 lib/fwlib/src/hal_gpio.c create mode 100644 lib/fwlib/src/hal_i2c.c create mode 100644 lib/fwlib/src/hal_i2s.c create mode 100644 lib/fwlib/src/hal_mii.c create mode 100644 lib/fwlib/src/hal_nfc.c create mode 100644 lib/fwlib/src/hal_pcm.c create mode 100644 lib/fwlib/src/hal_pwm.c create mode 100644 lib/fwlib/src/hal_sdr_controller.c create mode 100644 lib/fwlib/src/hal_soc_ps_monitor.c create mode 100644 lib/fwlib/src/hal_ssi.c create mode 100644 lib/fwlib/src/hal_timer.c create mode 100644 lib/fwlib/src/hal_uart.c create mode 100644 lib/libc/assert.h create mode 100644 lib/libc/ctype.h create mode 100644 lib/libc/libc.c create mode 100644 lib/libc/stddef.h create mode 100644 lib/libc/stdio.h create mode 100644 lib/libc/stdlib.h create mode 100644 lib/libc/string.h create mode 100644 lib/libc/time.h create mode 100644 lib/mask.h create mode 100644 lib/rom_lib.h create mode 100644 lib/rtl_consol.h create mode 100644 lib/rtl_std_lib/include/rt_lib_rom.h create mode 100644 lib/rtl_std_lib/include/rtl_lib.h create mode 100644 lib/rtl_std_lib/libc/rom/string/rom_libc_string.h create mode 100644 lib/rtl_std_lib/libgloss/rtl8195a/rom/rom_libgloss_retarget.h create mode 100644 lib/strproc.h create mode 100644 lib/va_list.h create mode 100644 main.c create mode 100644 rtl8710_flash_boot.s diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..76919c9 --- /dev/null +++ b/.cproject @@ -0,0 +1,164 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + make + + test + true + true + true + + + make + + flash + true + true + true + + + make + + all + true + true + true + + + make + + clean + true + true + true + + + make + + reset + true + true + true + + + + diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..a7947fe --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +test.elf +test.bin +flash.elf +flash.bin + diff --git a/.project b/.project new file mode 100644 index 0000000..e5c607e --- /dev/null +++ b/.project @@ -0,0 +1,26 @@ + + + RTL00_HelloWorld + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/.settings/org.eclipse.cdt.codan.core.prefs b/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..77386c2 --- /dev/null +++ b/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,67 @@ 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+org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},paramNot\=>false} +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},else\=>false,afterelse\=>false} +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>("@(\#)","$Id")} +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} diff --git a/.settings/org.eclipse.cdt.core.prefs b/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 0000000..eb5db47 --- /dev/null +++ b/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,29 @@ +eclipse.preferences.version=1 +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/MINGW_HOME/delimiter=; +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/MINGW_HOME/operation=replace +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/MINGW_HOME/value=C\:\\MinGW +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/OOCD_HOME/delimiter=; +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/OOCD_HOME/operation=append +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/OOCD_HOME/value=D\:\\MCU\\OpenOCD\\bin +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/PATH/delimiter=; +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/PATH/operation=replace +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/PATH/value=${MINGW_HOME}\\mingw64\\bin;${MSYS_HOME}\\bin;${OOCD_HOME};${TL_PATH};C\:\\Eclipse;D\:\\MentorGraphics\\Sourcery_CodeBench_Lite_for_MIPS_ELF\\bin;D\:\\MCU\\STMicroelectronics\\st_toolset\\asm;C\:\\Windows;C\:\\Windows\\system32 +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/SYSTEMROOT/delimiter=; +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/SYSTEMROOT/operation=append +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/SYSTEMROOT/value=C\:\\Windows +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/TL_PATH/delimiter=; +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/TL_PATH/operation=append +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/TL_PATH/value=D\:\\MCU\\GNU Tools ARM Embedded\\5.2 2015q4\\bin +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/append=true +environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/appendContributed=false +environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/OOCD_HOME/delimiter=; +environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/OOCD_HOME/operation=append +environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/OOCD_HOME/value=D\:\\MCU\\OpenOCD\\bin +environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/PATH/delimiter=; +environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/PATH/operation=replace +environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/PATH/value=${MINGW_HOME}\\bin;${MSYS_HOME}\\bin;${OOCD_HOME}C\:/Program Files (x86)/Java/jre1.8.0_101/bin/client;C\:/Program Files (x86)/Java/jre1.8.0_101/bin;C\:/Program Files (x86)/Java/jre1.8.0_101/lib/i386;C\:\\MinGW\\mingw64\\bin;C\:\\MinGW\\msys\\1.0\\bin;C\:\\MinGW\\bin;D\:\\MCU\\STMicroelectronics\\st_toolset\\asm;C\:\\Python27;C\:\\Utils\\FarUtils;C\:\\Utils\\FarUtils\\HIEW810;C\:\\Windows;C\:\\Windows\\system32;C\:\\Windows\\System32\\Wbem;C\:\\Windows\\System32\\WindowsPowerShell\\v1.0;D\:\\MCU\\Microchip\\xc32\\v1.42\\bin;D\:\\MCU\\Microchip\\mplabc30\\v3.31\\bin;D\:\\MCU\\Microchip\\MPLAB C32 Suite\\bin;D\:\\MCU\\Microchip\\mplabc32\\v1.12\\bin;D\:\\MCU\\Microchip\\mcc18\\mpasm;D\:\\MCU\\Microchip\\mcc18\\bin;D\:\\WRK\\TortoiseGit\\bin;C\:\\Utils\\TortoiseSVN\\binC\:\\Program Files (x86)\\Git\\cmd;C\:\\Program Files (x86)\\Borland\\Delphi7\\Bin;C\:\\Program Files (x86)\\Borland\\Delphi7\\Projects\\Bpl\\;C\:\\Program Files (x86)\\Common Files\\Microsoft Shared\\Windows Live;C\:\\Program Files (x86)\\ATI Technologies\\ATI.ACE\\Core-Static;C\:\\Program Files (x86)\\Common Files\\Acronis\\SnapAPI;C\:\\Program Files (x86)\\Windows Live\\Shared;C\:\\Program Files (x86)\\IVI Foundation\\VISA\\WinNT\\Bin;C\:\\Program Files (x86)\\Windows Kits\\8.1\\Windows Performance Toolkit;C\:\\Program Files (x86)\\Microsoft SDKs\\TypeScript\\1.0;C\:\\Program Files (x86)\\IVI Foundation\\VISA\\WinNT\\Bin;C\:\\Program Files\\Microsoft SQL Server\\110\\Tools\\Binn;C\:\\Program Files\\Common Files\\Microsoft Shared\\Windows Live;C\:\\Program Files\\Microsoft SQL Server\\120\\Tools\\Binn;C\:\\Program Files\\Microsoft DNX\\Dnvm;C\:\\Program Files\\IVI Foundation\\VISA\\Win64\\Bin;D\:\\Automation\\Samcoon\\SKWorkshop\\Marco\\HMI\\bin;D\:\\Automation\\Samcoon\\SKWorkshop\\Marco\\X86\\bin;D\:\\Automation\\Samcoon\\SK035AE\\SKWorkshop\\Marco\\HMI\\bin;D\:\\Automation\\Samcoon\\SK035AE\\SKWorkshop\\Marco\\X86\\bin;C\:\\Users\\PVV\\.dnx\\bin;C\:\\ProgramData\\chocolatey\\bin;C\:\\ProgramData\\Oracle\\Java\\javapath;C\:\\Program Files (x86)\\QuickTime\\QTSystem;C\:\\Program Files\\nodejs;D\:\\MCU\\GNU Tools ARM Embedded\\5.2 2015q4\\bin;D\:\\MentorGraphics\\Sourcery_CodeBench_Lite_for_MIPS_ELF\\bin;D\:\\MCU\\OpenOCD\\bin;C\:\\Eclipse +environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/TL_PATH/delimiter=; +environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/TL_PATH/operation=append +environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/TL_PATH/value=D\:\\MCU\\GNU Tools ARM Embedded\\5.2 2015q4\\bin +environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/append=true +environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/appendContributed=true diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..de902b6 --- /dev/null +++ b/LICENSE @@ -0,0 +1,36 @@ +THE BEER-WARE LICENSE + +As long as you retain this notice you can do whatever you want +with this stuff. If we meet some day, and you think this stuff +is worth it, you can buy me a beer in return. + + Rebane, rebane@alkohol.ee + +----------------------------------------------------------------------- + + This is free and unencumbered software released into the public domain. + +Anyone is free to copy, modify, publish, use, compile, sell, or +distribute this software, either in source code form or as a compiled +binary, for any purpose, commercial or non-commercial, and by any +means. + +In jurisdictions that recognize copyright laws, the author or authors +of this software dedicate any and all copyright interest in the +software to the public domain. We make this dedication for the benefit +of the public at large and to the detriment of our heirs and +successors. We intend this dedication to be an overt act of +relinquishment in perpetuity of all present and future rights to this +software under copyright law. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +For more information, please refer to + + diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..7219766 --- /dev/null +++ b/Makefile @@ -0,0 +1,62 @@ +LIBDIR = lib +FILENAME_PREFIX = test +ADDRESS = 0x10001000 + +#FLASHER = stlink-v2-1 +#FLASHER = stlink-v2 +FLASHER = Jlink +# stlink-v2-1 +ifeq ($(FLASHER), Jlink) +# Jlink FLASHER_SPEED ..4000 kHz +FLASHER_SPEED = 3500 +else +ifeq ($(FLASHER),stlink-v2) +# stlink-v2 FLASHER_SPEED ..1800 kHz +FLASHER_SPEED = 1800 +else +# ? FLASHER_SPEED ..500 kHz ? +FLASHER_SPEED = 500 +endif +endif + +CC_PARAMS = -Wall -g -Os -mlittle-endian -mlong-calls -mthumb -mcpu=cortex-m3 -mfloat-abi=soft -mthumb-interwork -ffunction-sections -ffreestanding -fsingle-precision-constant -fshort-wchar -fno-short-enums -Ddouble=float -Wstrict-aliasing=0 -Wl,-T,$(LIBDIR)/cpu/rtl8710/rtl8710.ld -L$(LIBDIR)/cpu/rtl8710 -nostartfiles -nostdlib -u cortex_vectors -Wl,--gc-sections + +BASE_PARAMS = -DCORTEX_INTERRUPT_MAX=32 -I$(LIBDIR) -I$(LIBDIR)/cpu/rtl8710 -I$(LIBDIR)/cpu/cortex -I$(LIBDIR)/fwlib -Wl,--section-start=.text=$(ADDRESS) + +#$(LIBDIR)/cpu/cortex/cortex.c + +LIBC_PARAMS = -I$(LIBDIR)/libc $(LIBDIR)/libc/libc.c -DLIBC_PRINTF + + +FIRMWARE_PARAMS = main.c + +CC = arm-none-eabi-gcc + +all: firmware + +firmware: + $(CC) $(CC_PARAMS) $(BASE_PARAMS) $(LIBC_PARAMS) $(FIRMWARE_PARAMS) -lgcc -o $(FILENAME_PREFIX).elf + arm-none-eabi-objdump -S $(FILENAME_PREFIX).elf >$(FILENAME_PREFIX).asm + arm-none-eabi-strip $(FILENAME_PREFIX).elf + arm-none-eabi-objcopy -O binary $(FILENAME_PREFIX).elf $(FILENAME_PREFIX).bin + chmod 755 $(FILENAME_PREFIX).bin + $(CC) $(CC_PARAMS) -DSeg1StartAddr=$(ADDRESS) -DBinFileName="\"$(FILENAME_PREFIX).bin\"" rtl8710_flash_boot.S -o flash.elf + arm-none-eabi-objcopy -O binary flash.elf flash.bin + chmod 755 flash.bin + +size: + arm-none-eabi-size -A -x $(FILENAME_PREFIX).elf + +clean: + rm -rf $(FILENAME_PREFIX).bin $(FILENAME_PREFIX).elf $(FILENAME_PREFIX).asm flash.bin flash.elf + +test: + openocd -f interface/$(FLASHER).cfg -c "adapter_khz $(FLASHER_SPEED)" -f $(LIBDIR)/cpu/rtl8710/rtl8710.ocd -f $(LIBDIR)/cpu/cortex/cortex.ocd -c "init" -c "reset halt" -c "load_image $(FILENAME_PREFIX).bin $(ADDRESS) bin" -c "cortex_bootstrap $(ADDRESS)" -c "shutdown" + +flash: + openocd -f interface/$(FLASHER).cfg -c "adapter_khz $(FLASHER_SPEED)" -f $(LIBDIR)/cpu/rtl8710/rtl8710.ocd -c "init" -c "reset halt" -c "rtl8710_flash_auto_erase 1" -c "rtl8710_flash_auto_verify 1" -c "rtl8710_flash_write flash.bin 0" -c "rtl8710_reboot" -c "reset run" -c shutdown + +reset: + openocd -f interface/$(FLASHER).cfg -c "adapter_khz $(FLASHER_SPEED)" -f $(LIBDIR)/cpu/rtl8710/rtl8710.ocd -c "init" -c "reset halt" -c "rtl8710_reboot" -c shutdown + + \ No newline at end of file diff --git a/README.md b/README.md index df7783c..430e13d 100644 --- a/README.md +++ b/README.md @@ -1 +1,24 @@ -# RTL00_HelloWorld \ No newline at end of file +# RTL-00 Test Hello World +RTL8710 OpenOCD J-Link/STlink +## pins: +* UART RX: GB0 +* UART TX: GB1 +* LED: GC4 +* SWDIO: GE3 +* SWCLK: GE4 +## building: +``` +make +``` +## testing in ram: +``` +make test +``` +## flashing: +``` +make flash +``` +## reset: +``` +make reset +``` diff --git a/lib/basic_types.h b/lib/basic_types.h new file mode 100644 index 0000000..754c3e4 --- /dev/null +++ b/lib/basic_types.h @@ -0,0 +1,501 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __BASIC_TYPES_H__ +#define __BASIC_TYPES_H__ + +//#define PLATFORM_FREERTOS +#include + +#define PLATFORM_LITTLE_ENDIAN 0 +#define PLATFORM_BIG_ENDIAN 1 + +#define SYSTEM_ENDIAN PLATFORM_LITTLE_ENDIAN + +#define SUCCESS 0 +#define FAIL (-1) + +#undef _SUCCESS +#define _SUCCESS 1 + +#undef _FAIL +#define _FAIL 0 + +#ifndef FALSE + #define FALSE 0 +#endif + +#ifndef TRUE + #define TRUE (!FALSE) +#endif + +#define _TRUE TRUE +#define _FALSE FALSE + +#ifndef NULL +#define NULL 0 +#endif + +#ifdef __GNUC__ +#define __weak __attribute__((weak)) +#define likely(x) __builtin_expect ((x), 1) +#define unlikely(x) __builtin_expect ((x), 0) +#endif + +typedef unsigned int uint; +typedef signed int sint; + +#ifdef __ICCARM__ +typedef signed long long __int64_t; +typedef unsigned long long __uint64_t; +#endif + +#define s8 int8_t +#define u8 uint8_t +#define s16 int16_t +#define u16 uint16_t +#define s32 int32_t +#define u32 uint32_t +#define s64 int64_t +#define u64 uint64_t + +#ifdef CONFIG_MBED_ENABLED +typedef unsigned int BOOL; +#else +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef bool +#ifndef __cplusplus +typedef unsigned char bool; +#endif +#endif +#endif + +#define UCHAR uint8_t +#define USHORT uint16_t +#define UINT uint32_t +#define ULONG uint32_t + +typedef struct { volatile int counter; } atomic_t; + +typedef enum _RTK_STATUS_ { + _EXIT_SUCCESS = 0, + _EXIT_FAILURE = 1 +}RTK_STATUS, *PRTK_STATUS; + +#define IN +#define OUT +#define VOID void +#define INOUT +#define NDIS_OID uint +#define NDIS_STATUS uint + +#ifndef PVOID +typedef void * PVOID; +#endif + +typedef u32 dma_addr_t; + +typedef void (*proc_t)(void*); + +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; + +typedef __kernel_size_t SIZE_T; +typedef __kernel_ssize_t SSIZE_T; +#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field) + +#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T)) +#define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1) + +#define SIZE_PTR SIZE_T +#define SSIZE_PTR SSIZE_T + +#ifndef ON +#define ON 1 +#endif + +#ifndef OFF +#define OFF 0 +#endif + +#ifndef ENABLE +#define ENABLE 1 +#endif + +#ifndef DISABLE +#define DISABLE 0 +#endif + + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#define BIT_(__n) (1<<(__n)) + +#ifndef BIT +#define BIT(__n) (1<<(__n)) +#endif + +#if defined (__ICCARM__) +#define STRINGIFY(s) #s +#define SECTION(_name) _Pragma( STRINGIFY(location=_name)) +#define ALIGNMTO(_bound) _Pragma( STRINGIFY(data_alignment=##_bound##)) +#define _PACKED_ __packed +#define _LONG_CALL_ +#define _LONG_CALL_ROM_ +#define _WEAK __weak +#else +#define SECTION(_name) __attribute__ ((__section__(_name))) +#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound))) +#define _PACKED_ __attribute__ ((packed)) +#define _LONG_CALL_ __attribute__ ((long_call)) +#define _LONG_CALL_ROM_ _LONG_CALL_ +#define _WEAK __attribute__ ((weak)) +#endif + + + +//port from fw by thomas +// TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness + +#define SWAP32(x) ((u32)( \ + (((u32)(x) & (u32)0x000000ff) << 24) | \ + (((u32)(x) & (u32)0x0000ff00) << 8) | \ + (((u32)(x) & (u32)0x00ff0000) >> 8) | \ + (((u32)(x) & (u32)0xff000000) >> 24))) + +#define WAP16(x) ((u16)( \ + (((u16)(x) & (u16)0x00ff) << 8) | \ + (((u16)(x) & (u16)0xff00) >> 8))) + +#if SYSTEM_ENDIAN == PLATFORM_LITTLE_ENDIAN +#ifndef rtk_le16_to_cpu +#define rtk_cpu_to_le32(x) ((u32)(x)) +#define rtk_le32_to_cpu(x) ((u32)(x)) +#define rtk_cpu_to_le16(x) ((u16)(x)) +#define rtk_le16_to_cpu(x) ((u16)(x)) +#define rtk_cpu_to_be32(x) SWAP32((x)) +#define rtk_be32_to_cpu(x) SWAP32((x)) +#define rtk_cpu_to_be16(x) WAP16((x)) +#define rtk_be16_to_cpu(x) WAP16((x)) +#endif + +#elif SYSTEM_ENDIAN == PLATFORM_BIG_ENDIAN +#ifndef rtk_le16_to_cpu +#define rtk_cpu_to_le32(x) SWAP32((x)) +#define rtk_le32_to_cpu(x) SWAP32((x)) +#define rtk_cpu_to_le16(x) WAP16((x)) +#define rtk_le16_to_cpu(x) WAP16((x)) +#define rtk_cpu_to_be32(x) ((__u32)(x)) +#define rtk_be32_to_cpu(x) ((__u32)(x)) +#define rtk_cpu_to_be16(x) ((__u16)(x)) +#define rtk_be16_to_cpu(x) ((__u16)(x)) +#endif +#endif + + +/* + * Call endian free function when + * 1. Read/write packet content. + * 2. Before write integer to IO. + * 3. After read integer from IO. +*/ + +// +// Byte Swapping routine. +// +#define EF1Byte (u8) +#define EF2Byte le16_to_cpu +#define EF4Byte le32_to_cpu + +// +// Read LE format data from memory +// +#define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr))) +#define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr))) +#define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr))) + +// +// Write LE data to memory +// +#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val) +#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val) +#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val) + +// +// Example: +// BIT_LEN_MASK_32(0) => 0x00000000 +// BIT_LEN_MASK_32(1) => 0x00000001 +// BIT_LEN_MASK_32(2) => 0x00000003 +// BIT_LEN_MASK_32(32) => 0xFFFFFFFF +// +#define BIT_LEN_MASK_32(__BitLen) \ + (0xFFFFFFFF >> (32 - (__BitLen))) +// +// Example: +// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 +// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 +// +#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \ + (BIT_LEN_MASK_32(__BitLen) << (__BitOffset)) + +// +// Description: +// Return 4-byte value in host byte ordering from +// 4-byte pointer in litten-endian system. +// +#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ + (EF4Byte(*((u32 *)(__pStart)))) + +// +// Description: +// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to +// 4-byte value in host byte ordering. +// +#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + ( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \ + & \ + BIT_LEN_MASK_32(__BitLen) \ + ) + +// +// Description: +// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering +// and return the result in 4-byte value in host byte ordering. +// +#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ + & \ + ( ~ BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \ + ) + +// +// Description: +// Set subfield of little-endian 4-byte value to specified value. +// +#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + *((u32 *)(__pStart)) = \ + EF4Byte( \ + LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \ + ); + + +#define BIT_LEN_MASK_16(__BitLen) \ + (0xFFFF >> (16 - (__BitLen))) + +#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \ + (BIT_LEN_MASK_16(__BitLen) << (__BitOffset)) + +#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ + (EF2Byte(*((u16 *)(__pStart)))) + +#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + ( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \ + & \ + BIT_LEN_MASK_16(__BitLen) \ + ) + +#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ + & \ + ( ~ BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \ + ) + +#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + *((u16 *)(__pStart)) = \ + EF2Byte( \ + LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \ + ); + +#define BIT_LEN_MASK_8(__BitLen) \ + (0xFF >> (8 - (__BitLen))) + +#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \ + (BIT_LEN_MASK_8(__BitLen) << (__BitOffset)) + +#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ + (EF1Byte(*((u8 *)(__pStart)))) + +#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + ( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \ + & \ + BIT_LEN_MASK_8(__BitLen) \ + ) + +#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ + & \ + ( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \ + ) + +#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + *((u8 *)(__pStart)) = \ + EF1Byte( \ + LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \ + ); + +//pclint +#define LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ + ) + +//pclint +#define SET_BITS_TO_LE_1BYTE_8BIT(__pStart, __BitOffset, __BitLen, __Value) \ +{ \ + *((pu1Byte)(__pStart)) = \ + EF1Byte( \ + LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \ + | \ + ((u1Byte)__Value) \ + ); \ +} + +// Get the N-bytes aligment offset from the current length +#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment)) + +typedef unsigned char BOOLEAN,*PBOOLEAN; + +#define TEST_FLAG(__Flag,__testFlag) (((__Flag) & (__testFlag)) != 0) +#define SET_FLAG(__Flag, __setFlag) ((__Flag) |= __setFlag) +#define CLEAR_FLAG(__Flag, __clearFlag) ((__Flag) &= ~(__clearFlag)) +#define CLEAR_FLAGS(__Flag) ((__Flag) = 0) +#define TEST_FLAGS(__Flag, __testFlags) (((__Flag) & (__testFlags)) == (__testFlags)) + +/* Define compilor specific symbol */ +// +// inline function +// + +#if defined ( __ICCARM__ ) +#define __inline__ inline +#define __inline inline +#define __inline_definition //In dialect C99, inline means that a function's definition is provided + //only for inlining, and that there is another definition + //(without inline) somewhere else in the program. + //That means that this program is incomplete, because if + //add isn't inlined (for example, when compiling without optimization), + //then main will have an unresolved reference to that other definition. + + // Do not inline function is the function body is defined .c file and this + // function will be called somewhere else, otherwise there is compile error +#elif defined ( __CC_ARM ) +#define __inline__ __inline //__linine__ is not supported in keil compilor, use __inline instead +#define inline __inline +#define __inline_definition // for dialect C99 +#elif defined ( __GNUC__ ) +#define __inline__ inline +#define __inline inline +#define __inline_definition inline +#endif + +// +// pack +// + +#if defined (__ICCARM__) + +#define RTW_PACK_STRUCT_BEGIN _Pragma( STRINGIFY(pack(1))) +#define RTW_PACK_STRUCT_STRUCT +#define RTW_PACK_STRUCT_END _Pragma( STRINGIFY(pack())) +//#define RTW_PACK_STRUCT_USE_INCLUDES + +#elif defined (__CC_ARM) + +#define RTW_PACK_STRUCT_BEGIN __packed +#define RTW_PACK_STRUCT_STRUCT +#define RTW_PACK_STRUCT_END + +#elif defined (__GNUC__) + +#define RTW_PACK_STRUCT_BEGIN +#define RTW_PACK_STRUCT_STRUCT __attribute__ ((__packed__)) +#define RTW_PACK_STRUCT_END + +#elif defined(PLATFORM_WINDOWS) + +#define RTW_PACK_STRUCT_BEGIN +#define RTW_PACK_STRUCT_STRUCT +#define RTW_PACK_STRUCT_END +#define RTW_PACK_STRUCT_USE_INCLUDES +#endif + +// for standard library +#ifdef __ICCARM__ +#define __extension__ /* Ignore */ +#define __restrict /* Ignore */ +#endif + +typedef struct _RAM_START_FUNCTION_ { + VOID (*RamStartFun) (VOID); +}RAM_START_FUNCTION, *PRAM_START_FUNCTION; + +typedef struct _RAM_FUNCTION_START_TABLE_ { + VOID (*RamStartFun) (VOID); + VOID (*RamWakeupFun) (VOID); + VOID (*RamPatchFun0) (VOID); + VOID (*RamPatchFun1) (VOID); + VOID (*RamPatchFun2) (VOID); +}RAM_FUNCTION_START_TABLE, *PRAM_FUNCTION_START_TABLE; + +#endif// __BASIC_TYPES_H__ diff --git a/lib/cpu/cortex/cortex.c b/lib/cpu/cortex/cortex.c new file mode 100644 index 0000000..8c4fd13 --- /dev/null +++ b/lib/cpu/cortex/cortex.c @@ -0,0 +1,1069 @@ +#include +#include "cortex.h" + +#ifndef CORTEX_INTERRUPT_MAX +#define CORTEX_INTERRUPT_MAX 256 +#endif + +extern uint8_t __text_end__, __data_beg__, __data_end__, __bss_beg__, __bss_end__, STACK_TOP; + +extern int main(int argc, char *argv[]); + +static void crt0(void); + +static void __attribute__((interrupt)) CORTEX_Default_Handler(void){ +} + +static void crt_empty(void){ +} + +void __attribute__((weak, alias("crt_empty"))) crt1(void); +void __attribute__((weak, alias("crt_empty"))) crt2(void); +void __attribute__((weak, alias("crt_empty"))) crt3(void); +void __attribute__((weak, alias("crt_empty"))) crt4(void); +void __attribute__((weak, alias("crt_empty"))) crt5(void); + +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_NMI_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_HardFault_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_MemManage_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_BusFault_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_UsageFault_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_SVC_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_DebugMon_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_PendSV_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_SysTick_Handler(void); + +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_0_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_1_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_2_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_3_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_4_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_5_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_6_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_7_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_8_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_9_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_10_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_11_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_12_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_13_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_14_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_15_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_16_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_17_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_18_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_19_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_20_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_21_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_22_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_23_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_24_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_25_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_26_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_27_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_28_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_29_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_30_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_31_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_32_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_33_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_34_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_35_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_36_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_37_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_38_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_39_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_40_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_41_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_42_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_43_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_44_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_45_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_46_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_47_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_48_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_49_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_50_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_51_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_52_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_53_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_54_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_55_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_56_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_57_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_58_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_59_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_60_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_61_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_62_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_63_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_64_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_65_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_66_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_67_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_68_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_69_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_70_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_71_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_72_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_73_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_74_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_75_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_76_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_77_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_78_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_79_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_80_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_81_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_82_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_83_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_84_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_85_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_86_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_87_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_88_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_89_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_90_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_91_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_92_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_93_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_94_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_95_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_96_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_97_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_98_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_99_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_100_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_101_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_102_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_103_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_104_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_105_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_106_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_107_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_108_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_109_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_110_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_111_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_112_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_113_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_114_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_115_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_116_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_117_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_118_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_119_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_120_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_121_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_122_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_123_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_124_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_125_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_126_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_127_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_128_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_129_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_130_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_131_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_132_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_133_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_134_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_135_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_136_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_137_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_138_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_139_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_140_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_141_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_142_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_143_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_144_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_145_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_146_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_147_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_148_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_149_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_150_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_151_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_152_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_153_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_154_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_155_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_156_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_157_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_158_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_159_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_160_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_161_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_162_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_163_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_164_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_165_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_166_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_167_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_168_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_169_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_170_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_171_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_172_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_173_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_174_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_175_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_176_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_177_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_178_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_179_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_180_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_181_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_182_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_183_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_184_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_185_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_186_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_187_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_188_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_189_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_190_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_191_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_192_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_193_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_194_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_195_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_196_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_197_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_198_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_199_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_200_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_201_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_202_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_203_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_204_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_205_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_206_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_207_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_208_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_209_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_210_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_211_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_212_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_213_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_214_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_215_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_216_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_217_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_218_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_219_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_220_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_221_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_222_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_223_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_224_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_225_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_226_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_227_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_228_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_229_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_230_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_231_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_232_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_233_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_234_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_235_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_236_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_237_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_238_Handler(void); +void __attribute__((weak, alias("CORTEX_Default_Handler"))) CORTEX_INTERRUPT_239_Handler(void); + +uint32_t *cortex_vectors[] __attribute__((section(".vectors"))) = { + (uint32_t *)&STACK_TOP, + (uint32_t *)crt0, + (uint32_t *)CORTEX_NMI_Handler, + (uint32_t *)CORTEX_HardFault_Handler, + (uint32_t *)CORTEX_MemManage_Handler, + (uint32_t *)CORTEX_BusFault_Handler, + (uint32_t *)CORTEX_UsageFault_Handler, + (uint32_t *)0, + (uint32_t *)0, + (uint32_t *)0, + (uint32_t *)0, + (uint32_t *)CORTEX_SVC_Handler, + (uint32_t *)CORTEX_DebugMon_Handler, + (uint32_t *)0, + (uint32_t *)CORTEX_PendSV_Handler, + (uint32_t *)CORTEX_SysTick_Handler, +#if (CORTEX_INTERRUPT_MAX > 0) + (uint32_t *)CORTEX_INTERRUPT_0_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 1) + (uint32_t *)CORTEX_INTERRUPT_1_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 2) + (uint32_t *)CORTEX_INTERRUPT_2_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 3) + (uint32_t *)CORTEX_INTERRUPT_3_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 4) + (uint32_t *)CORTEX_INTERRUPT_4_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 5) + (uint32_t *)CORTEX_INTERRUPT_5_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 6) + (uint32_t *)CORTEX_INTERRUPT_6_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 7) + (uint32_t *)CORTEX_INTERRUPT_7_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 8) + (uint32_t *)CORTEX_INTERRUPT_8_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 9) + (uint32_t *)CORTEX_INTERRUPT_9_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 10) + (uint32_t *)CORTEX_INTERRUPT_10_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 11) + (uint32_t *)CORTEX_INTERRUPT_11_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 12) + (uint32_t *)CORTEX_INTERRUPT_12_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 13) + (uint32_t *)CORTEX_INTERRUPT_13_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 14) + (uint32_t *)CORTEX_INTERRUPT_14_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 15) + (uint32_t *)CORTEX_INTERRUPT_15_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 16) + (uint32_t *)CORTEX_INTERRUPT_16_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 17) + (uint32_t *)CORTEX_INTERRUPT_17_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 18) + (uint32_t *)CORTEX_INTERRUPT_18_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 19) + (uint32_t *)CORTEX_INTERRUPT_19_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 20) + (uint32_t *)CORTEX_INTERRUPT_20_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 21) + (uint32_t *)CORTEX_INTERRUPT_21_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 22) + (uint32_t *)CORTEX_INTERRUPT_22_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 23) + (uint32_t *)CORTEX_INTERRUPT_23_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 24) + (uint32_t *)CORTEX_INTERRUPT_24_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 25) + (uint32_t *)CORTEX_INTERRUPT_25_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 26) + (uint32_t *)CORTEX_INTERRUPT_26_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 27) + (uint32_t *)CORTEX_INTERRUPT_27_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 28) + (uint32_t *)CORTEX_INTERRUPT_28_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 29) + (uint32_t *)CORTEX_INTERRUPT_29_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 30) + (uint32_t *)CORTEX_INTERRUPT_30_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 31) + (uint32_t *)CORTEX_INTERRUPT_31_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 32) + (uint32_t *)CORTEX_INTERRUPT_32_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 33) + (uint32_t *)CORTEX_INTERRUPT_33_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 34) + (uint32_t *)CORTEX_INTERRUPT_34_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 35) + (uint32_t *)CORTEX_INTERRUPT_35_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 36) + (uint32_t *)CORTEX_INTERRUPT_36_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 37) + (uint32_t *)CORTEX_INTERRUPT_37_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 38) + (uint32_t *)CORTEX_INTERRUPT_38_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 39) + (uint32_t *)CORTEX_INTERRUPT_39_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 40) + (uint32_t *)CORTEX_INTERRUPT_40_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 41) + (uint32_t *)CORTEX_INTERRUPT_41_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 42) + (uint32_t *)CORTEX_INTERRUPT_42_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 43) + (uint32_t *)CORTEX_INTERRUPT_43_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 44) + (uint32_t *)CORTEX_INTERRUPT_44_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 45) + (uint32_t *)CORTEX_INTERRUPT_45_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 46) + (uint32_t *)CORTEX_INTERRUPT_46_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 47) + (uint32_t *)CORTEX_INTERRUPT_47_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 48) + (uint32_t *)CORTEX_INTERRUPT_48_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 49) + (uint32_t *)CORTEX_INTERRUPT_49_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 50) + (uint32_t *)CORTEX_INTERRUPT_50_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 51) + (uint32_t *)CORTEX_INTERRUPT_51_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 52) + (uint32_t *)CORTEX_INTERRUPT_52_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 53) + (uint32_t *)CORTEX_INTERRUPT_53_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 54) + (uint32_t *)CORTEX_INTERRUPT_54_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 55) + (uint32_t *)CORTEX_INTERRUPT_55_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 56) + (uint32_t *)CORTEX_INTERRUPT_56_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 57) + (uint32_t *)CORTEX_INTERRUPT_57_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 58) + (uint32_t *)CORTEX_INTERRUPT_58_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 59) + (uint32_t *)CORTEX_INTERRUPT_59_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 60) + (uint32_t *)CORTEX_INTERRUPT_60_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 61) + (uint32_t *)CORTEX_INTERRUPT_61_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 62) + (uint32_t *)CORTEX_INTERRUPT_62_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 63) + (uint32_t *)CORTEX_INTERRUPT_63_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 64) + (uint32_t *)CORTEX_INTERRUPT_64_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 65) + (uint32_t *)CORTEX_INTERRUPT_65_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 66) + (uint32_t *)CORTEX_INTERRUPT_66_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 67) + (uint32_t *)CORTEX_INTERRUPT_67_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 68) + (uint32_t *)CORTEX_INTERRUPT_68_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 69) + (uint32_t *)CORTEX_INTERRUPT_69_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 70) + (uint32_t *)CORTEX_INTERRUPT_70_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 71) + (uint32_t *)CORTEX_INTERRUPT_71_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 72) + (uint32_t *)CORTEX_INTERRUPT_72_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 73) + (uint32_t *)CORTEX_INTERRUPT_73_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 74) + (uint32_t *)CORTEX_INTERRUPT_74_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 75) + (uint32_t *)CORTEX_INTERRUPT_75_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 76) + (uint32_t *)CORTEX_INTERRUPT_76_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 77) + (uint32_t *)CORTEX_INTERRUPT_77_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 78) + (uint32_t *)CORTEX_INTERRUPT_78_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 79) + (uint32_t *)CORTEX_INTERRUPT_79_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 80) + (uint32_t *)CORTEX_INTERRUPT_80_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 81) + (uint32_t *)CORTEX_INTERRUPT_81_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 82) + (uint32_t *)CORTEX_INTERRUPT_82_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 83) + (uint32_t *)CORTEX_INTERRUPT_83_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 84) + (uint32_t *)CORTEX_INTERRUPT_84_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 85) + (uint32_t *)CORTEX_INTERRUPT_85_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 86) + (uint32_t *)CORTEX_INTERRUPT_86_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 87) + (uint32_t *)CORTEX_INTERRUPT_87_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 88) + (uint32_t *)CORTEX_INTERRUPT_88_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 89) + (uint32_t *)CORTEX_INTERRUPT_89_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 90) + (uint32_t *)CORTEX_INTERRUPT_90_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 91) + (uint32_t *)CORTEX_INTERRUPT_91_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 92) + (uint32_t *)CORTEX_INTERRUPT_92_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 93) + (uint32_t *)CORTEX_INTERRUPT_93_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 94) + (uint32_t *)CORTEX_INTERRUPT_94_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 95) + (uint32_t *)CORTEX_INTERRUPT_95_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 96) + (uint32_t *)CORTEX_INTERRUPT_96_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 97) + (uint32_t *)CORTEX_INTERRUPT_97_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 98) + (uint32_t *)CORTEX_INTERRUPT_98_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 99) + (uint32_t *)CORTEX_INTERRUPT_99_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 100) + (uint32_t *)CORTEX_INTERRUPT_100_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 101) + (uint32_t *)CORTEX_INTERRUPT_101_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 102) + (uint32_t *)CORTEX_INTERRUPT_102_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 103) + (uint32_t *)CORTEX_INTERRUPT_103_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 104) + (uint32_t *)CORTEX_INTERRUPT_104_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 105) + (uint32_t *)CORTEX_INTERRUPT_105_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 106) + (uint32_t *)CORTEX_INTERRUPT_106_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 107) + (uint32_t *)CORTEX_INTERRUPT_107_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 108) + (uint32_t *)CORTEX_INTERRUPT_108_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 109) + (uint32_t *)CORTEX_INTERRUPT_109_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 110) + (uint32_t *)CORTEX_INTERRUPT_110_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 111) + (uint32_t *)CORTEX_INTERRUPT_111_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 112) + (uint32_t *)CORTEX_INTERRUPT_112_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 113) + (uint32_t *)CORTEX_INTERRUPT_113_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 114) + (uint32_t *)CORTEX_INTERRUPT_114_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 115) + (uint32_t *)CORTEX_INTERRUPT_115_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 116) + (uint32_t *)CORTEX_INTERRUPT_116_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 117) + (uint32_t *)CORTEX_INTERRUPT_117_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 118) + (uint32_t *)CORTEX_INTERRUPT_118_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 119) + (uint32_t *)CORTEX_INTERRUPT_119_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 120) + (uint32_t *)CORTEX_INTERRUPT_120_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 121) + (uint32_t *)CORTEX_INTERRUPT_121_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 122) + (uint32_t *)CORTEX_INTERRUPT_122_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 123) + (uint32_t *)CORTEX_INTERRUPT_123_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 124) + (uint32_t *)CORTEX_INTERRUPT_124_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 125) + (uint32_t *)CORTEX_INTERRUPT_125_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 126) + (uint32_t *)CORTEX_INTERRUPT_126_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 127) + (uint32_t *)CORTEX_INTERRUPT_127_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 128) + (uint32_t *)CORTEX_INTERRUPT_128_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 129) + (uint32_t *)CORTEX_INTERRUPT_129_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 130) + (uint32_t *)CORTEX_INTERRUPT_130_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 131) + (uint32_t *)CORTEX_INTERRUPT_131_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 132) + (uint32_t *)CORTEX_INTERRUPT_132_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 133) + (uint32_t *)CORTEX_INTERRUPT_133_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 134) + (uint32_t *)CORTEX_INTERRUPT_134_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 135) + (uint32_t *)CORTEX_INTERRUPT_135_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 136) + (uint32_t *)CORTEX_INTERRUPT_136_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 137) + (uint32_t *)CORTEX_INTERRUPT_137_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 138) + (uint32_t *)CORTEX_INTERRUPT_138_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 139) + (uint32_t *)CORTEX_INTERRUPT_139_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 140) + (uint32_t *)CORTEX_INTERRUPT_140_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 141) + (uint32_t *)CORTEX_INTERRUPT_141_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 142) + (uint32_t *)CORTEX_INTERRUPT_142_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 143) + (uint32_t *)CORTEX_INTERRUPT_143_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 144) + (uint32_t *)CORTEX_INTERRUPT_144_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 145) + (uint32_t *)CORTEX_INTERRUPT_145_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 146) + (uint32_t *)CORTEX_INTERRUPT_146_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 147) + (uint32_t *)CORTEX_INTERRUPT_147_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 148) + (uint32_t *)CORTEX_INTERRUPT_148_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 149) + (uint32_t *)CORTEX_INTERRUPT_149_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 150) + (uint32_t *)CORTEX_INTERRUPT_150_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 151) + (uint32_t *)CORTEX_INTERRUPT_151_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 152) + (uint32_t *)CORTEX_INTERRUPT_152_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 153) + (uint32_t *)CORTEX_INTERRUPT_153_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 154) + (uint32_t *)CORTEX_INTERRUPT_154_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 155) + (uint32_t *)CORTEX_INTERRUPT_155_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 156) + (uint32_t *)CORTEX_INTERRUPT_156_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 157) + (uint32_t *)CORTEX_INTERRUPT_157_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 158) + (uint32_t *)CORTEX_INTERRUPT_158_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 159) + (uint32_t *)CORTEX_INTERRUPT_159_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 160) + (uint32_t *)CORTEX_INTERRUPT_160_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 161) + (uint32_t *)CORTEX_INTERRUPT_161_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 162) + (uint32_t *)CORTEX_INTERRUPT_162_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 163) + (uint32_t *)CORTEX_INTERRUPT_163_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 164) + (uint32_t *)CORTEX_INTERRUPT_164_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 165) + (uint32_t *)CORTEX_INTERRUPT_165_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 166) + (uint32_t *)CORTEX_INTERRUPT_166_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 167) + (uint32_t *)CORTEX_INTERRUPT_167_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 168) + (uint32_t *)CORTEX_INTERRUPT_168_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 169) + (uint32_t *)CORTEX_INTERRUPT_169_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 170) + (uint32_t *)CORTEX_INTERRUPT_170_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 171) + (uint32_t *)CORTEX_INTERRUPT_171_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 172) + (uint32_t *)CORTEX_INTERRUPT_172_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 173) + (uint32_t *)CORTEX_INTERRUPT_173_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 174) + (uint32_t *)CORTEX_INTERRUPT_174_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 175) + (uint32_t *)CORTEX_INTERRUPT_175_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 176) + (uint32_t *)CORTEX_INTERRUPT_176_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 177) + (uint32_t *)CORTEX_INTERRUPT_177_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 178) + (uint32_t *)CORTEX_INTERRUPT_178_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 179) + (uint32_t *)CORTEX_INTERRUPT_179_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 180) + (uint32_t *)CORTEX_INTERRUPT_180_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 181) + (uint32_t *)CORTEX_INTERRUPT_181_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 182) + (uint32_t *)CORTEX_INTERRUPT_182_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 183) + (uint32_t *)CORTEX_INTERRUPT_183_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 184) + (uint32_t *)CORTEX_INTERRUPT_184_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 185) + (uint32_t *)CORTEX_INTERRUPT_185_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 186) + (uint32_t *)CORTEX_INTERRUPT_186_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 187) + (uint32_t *)CORTEX_INTERRUPT_187_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 188) + (uint32_t *)CORTEX_INTERRUPT_188_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 189) + (uint32_t *)CORTEX_INTERRUPT_189_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 190) + (uint32_t *)CORTEX_INTERRUPT_190_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 191) + (uint32_t *)CORTEX_INTERRUPT_191_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 192) + (uint32_t *)CORTEX_INTERRUPT_192_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 193) + (uint32_t *)CORTEX_INTERRUPT_193_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 194) + (uint32_t *)CORTEX_INTERRUPT_194_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 195) + (uint32_t *)CORTEX_INTERRUPT_195_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 196) + (uint32_t *)CORTEX_INTERRUPT_196_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 197) + (uint32_t *)CORTEX_INTERRUPT_197_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 198) + (uint32_t *)CORTEX_INTERRUPT_198_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 199) + (uint32_t *)CORTEX_INTERRUPT_199_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 200) + (uint32_t *)CORTEX_INTERRUPT_200_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 201) + (uint32_t *)CORTEX_INTERRUPT_201_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 202) + (uint32_t *)CORTEX_INTERRUPT_202_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 203) + (uint32_t *)CORTEX_INTERRUPT_203_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 204) + (uint32_t *)CORTEX_INTERRUPT_204_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 205) + (uint32_t *)CORTEX_INTERRUPT_205_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 206) + (uint32_t *)CORTEX_INTERRUPT_206_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 207) + (uint32_t *)CORTEX_INTERRUPT_207_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 208) + (uint32_t *)CORTEX_INTERRUPT_208_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 209) + (uint32_t *)CORTEX_INTERRUPT_209_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 210) + (uint32_t *)CORTEX_INTERRUPT_210_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 211) + (uint32_t *)CORTEX_INTERRUPT_211_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 212) + (uint32_t *)CORTEX_INTERRUPT_212_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 213) + (uint32_t *)CORTEX_INTERRUPT_213_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 214) + (uint32_t *)CORTEX_INTERRUPT_214_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 215) + (uint32_t *)CORTEX_INTERRUPT_215_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 216) + (uint32_t *)CORTEX_INTERRUPT_216_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 217) + (uint32_t *)CORTEX_INTERRUPT_217_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 218) + (uint32_t *)CORTEX_INTERRUPT_218_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 219) + (uint32_t *)CORTEX_INTERRUPT_219_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 220) + (uint32_t *)CORTEX_INTERRUPT_220_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 221) + (uint32_t *)CORTEX_INTERRUPT_221_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 222) + (uint32_t *)CORTEX_INTERRUPT_222_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 223) + (uint32_t *)CORTEX_INTERRUPT_223_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 224) + (uint32_t *)CORTEX_INTERRUPT_224_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 225) + (uint32_t *)CORTEX_INTERRUPT_225_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 226) + (uint32_t *)CORTEX_INTERRUPT_226_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 227) + (uint32_t *)CORTEX_INTERRUPT_227_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 228) + (uint32_t *)CORTEX_INTERRUPT_228_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 229) + (uint32_t *)CORTEX_INTERRUPT_229_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 230) + (uint32_t *)CORTEX_INTERRUPT_230_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 231) + (uint32_t *)CORTEX_INTERRUPT_231_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 232) + (uint32_t *)CORTEX_INTERRUPT_232_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 233) + (uint32_t *)CORTEX_INTERRUPT_233_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 234) + (uint32_t *)CORTEX_INTERRUPT_234_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 235) + (uint32_t *)CORTEX_INTERRUPT_235_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 236) + (uint32_t *)CORTEX_INTERRUPT_236_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 237) + (uint32_t *)CORTEX_INTERRUPT_237_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 238) + (uint32_t *)CORTEX_INTERRUPT_238_Handler, +#endif +#if (CORTEX_INTERRUPT_MAX > 239) + (uint32_t *)CORTEX_INTERRUPT_239_Handler, +#endif +}; + +static void crt0(void){ + uint8_t *m, *n; + uint32_t i; + crt1(); + // disable all interrupts + cortex_interrupts_disable(); + for(i = 0; i < CORTEX_INTERRUPT_MAX; i++)cortex_interrupt_disable(i); + crt2(); +//#ifndef __ARM_ARCH_6M__ // if not cortex m0 + // locate interrupt vectors + SCB->VTOR = (uint32_t)&cortex_vectors[0]; +//#endif + // http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/ch01s01s04.html + // kuidagi oleks vaja detektida, et mitte-FPU puhul seda ei teeks: http://stackoverflow.com/questions/2224334/gcc-dump-preprocessor-defines + SCB->CPACR |= ((((uint32_t)0x03) << 20) | (((uint32_t)0x03) << 22)); /* set CP10 and CP11 Full Access */ + __asm__("dsb"); // wait for store to complete + __asm__("isb"); // reset pipeline + crt3(); + for(m = &__data_beg__, n = &__text_end__; m < &__data_end__; m++, n++){ + *m = *n; + } + crt4(); + for(m = &__bss_beg__; m < &__bss_end__; m++){ + *m = 0; + } + crt5(); + // set stack pointer back to cortex_vectors[0] + __asm__("mov r2, %0": : "r" (cortex_vectors)); + __asm__("ldr r3, [r2, #0]"); + __asm__("mov sp, r3"); + // jump to main + __asm__("mov r3, %0": : "r" (main)); + __asm__("bx r3"); +} + +void cortex_bootstrap(void *start){ + uint32_t i; + cortex_interrupts_disable(); + for(i = 0; i < CORTEX_INTERRUPT_MAX; i++)cortex_interrupt_disable(i); + // set stack pointer to ((uint32_t *)start)[0] + __asm__("mov r2, %0": : "r" (start)); + __asm__("ldr r3, [r2, #0]"); + __asm__("mov sp, r3"); + // jump to ((uint32_t *)start)[1] + __asm__("ldr r3, [r2, #4]"); + __asm__("bx r3"); + while(1); +} + +void cortex_reboot(){ + SCB->AIRCR = (SCB->AIRCR & (((uint32_t)0x07) << 8)) | (((uint32_t)0x05FA) << 16) | SCB_AIRCR_SYSRESETREQ; + while(1); +} + diff --git a/lib/cpu/cortex/cortex.h b/lib/cpu/cortex/cortex.h new file mode 100644 index 0000000..d4c12a0 --- /dev/null +++ b/lib/cpu/cortex/cortex.h @@ -0,0 +1,79 @@ +#ifndef _CORTEX_H_ +#define _CORTEX_H_ + +#include + +typedef struct{ + volatile uint32_t ISER[8]; + uint32_t RESERVED1[24]; + volatile uint32_t ICER[8]; + uint32_t RESERVED2[24]; + volatile uint32_t ISPR[8]; + uint32_t RESERVED3[24]; + volatile uint32_t ICPR[8]; + uint32_t RESERVED4[24]; + volatile uint32_t IABR[8]; + uint32_t RESERVED5[56]; + volatile uint32_t IPR[32]; +}NVIC_TypeDef; + +typedef struct{ + uint32_t RESERVED1[2]; + volatile uint32_t ACTLR; + uint32_t RESERVED2[829]; + volatile const uint32_t CPUID; + volatile uint32_t ICSR; + volatile uint32_t VTOR; + volatile uint32_t AIRCR; + volatile uint32_t SCR; + volatile uint32_t CCR; + volatile uint32_t SHPR[3]; + volatile uint32_t SHCSR; + volatile uint32_t CFSR; + volatile uint32_t HFSR; + volatile uint32_t DFSR; + volatile uint32_t MMFAR; + volatile uint32_t BFAR; + volatile uint32_t AFSR; + volatile const uint32_t PFR[2]; + volatile const uint32_t DFR; + volatile const uint32_t AFR; + volatile const uint32_t MMFR[4]; + volatile const uint32_t ISAR[5]; + uint32_t RESERVED3[5]; + volatile uint32_t CPACR; +}SCB_TypeDef; + +#define NVIC ((NVIC_TypeDef *)0xE000E100) +#define SCB ((SCB_TypeDef *)0xE000E000) + +// SCB_AIRCR +#define SCB_AIRCR_VECTRESET (((uint32_t)0x0001) << 0) +#define SCB_AIRCR_VECTCLRACTIVE (((uint32_t)0x0001) << 1) +#define SCB_AIRCR_SYSRESETREQ (((uint32_t)0x0001) << 2) +#define SCB_AIRCR_PRIGROUP (((uint32_t)0x0007) << 8) +#define SCB_AIRCR_VECTKEY (((uint32_t)0xFFFF) << 16) +#define SCB_AIRCR_VECTKEYSTAT (((uint32_t)0xFFFF) << 16) + +// SCB_CPACR +#define SCB_CPACR_CP10 (((uint32_t)0x03) << 20) +#define SCB_CPACR_CP11 (((uint32_t)0x03) << 22) + +#define cortex_interrupt_set_priority(i, p) (NVIC->IPR[(i) >> 2] = ((NVIC->IPR[(i) >> 2] & ~(((uint32_t)0xFF) << (((i) & 0x03) << 3))) | (((uint32_t)p) << (((i) & 0x03) << 3)))) +#define cortex_interrupt_enable(i) (NVIC->ISER[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F))) +#define cortex_interrupt_disable(i) (NVIC->ICER[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F))) +#define cortex_interrupt_clear(i) (NVIC->ICPR[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F))) +#define cortex_interrupts_disable() __asm__("cpsid f") +#define cortex_interrupts_enable() __asm__("cpsie f") + +#define interrupts_disable() __asm__("cpsid f") +#define interrupts_enable() __asm__("cpsie f") + +#define CORTEX_ISR(n) _CORTEX_ISR(n) +#define _CORTEX_ISR(n) void __attribute__((interrupt)) CORTEX_INTERRUPT_##n##_Handler() + +void cortex_bootstrap(void *start) __attribute__ ((noreturn)); +void cortex_reboot() __attribute__ ((noreturn)); + +#endif + diff --git a/lib/cpu/cortex/cortex.ocd b/lib/cpu/cortex/cortex.ocd new file mode 100644 index 0000000..2e631af --- /dev/null +++ b/lib/cpu/cortex/cortex.ocd @@ -0,0 +1,14 @@ +proc cortex_bootstrap {start} { + # disable interrupts + reg faultmask 0x01 + set vectors "" + mem2array vectors 32 $start 2 + reg sp $vectors(0) + reg pc $vectors(1) + resume +} + +proc cortex_reboot {} { + mww 0xE000ED0C 0x05FA0007 +} + diff --git a/lib/cpu/rtl8710/export-rom_v03.txt b/lib/cpu/rtl8710/export-rom_v03.txt new file mode 100644 index 0000000..2c94191 --- /dev/null +++ b/lib/cpu/rtl8710/export-rom_v03.txt @@ -0,0 +1,737 @@ +SECTIONS +{ + __vectors_table = 0x0; + Reset_Handler = 0x101; + NMI_Handler = 0x109; + HardFault_Handler = 0x10d; + MemManage_Handler = 0x121; + BusFault_Handler = 0x125; + UsageFault_Handler = 0x129; + HalLogUartInit = 0x201; + HalSerialPutcRtl8195a = 0x2d9; + HalSerialGetcRtl8195a = 0x309; + HalSerialGetIsrEnRegRtl8195a = 0x329; + HalSerialSetIrqEnRegRtl8195a = 0x335; + HalCpuClkConfig = 0x341; + HalGetCpuClk = 0x355; + HalRomInfo = 0x39d; + HalGetRomInfo = 0x3b5; + HalResetVsr = 0x3c5; + HalDelayUs = 0x899; + HalNMIHandler = 0x8e1; + HalHardFaultHandler = 0x911; + HalMemManageHandler = 0xc09; + HalBusFaultHandler = 0xc39; + HalUsageFaultHandler = 0xc69; + HalUart0PinCtrlRtl8195A = 0xcfd; + HalUart1PinCtrlRtl8195A = 0xdc9; + HalUart2PinCtrlRtl8195A = 0xe9d; + HalSPI0PinCtrlRtl8195A = 0xf75; + HalSPI1PinCtrlRtl8195A = 0x1015; + HalSPI2PinCtrlRtl8195A = 0x10e5; + HalSPI0MCSPinCtrlRtl8195A = 0x11b5; + HalI2C0PinCtrlRtl8195A = 0x1275; + HalI2C1PinCtrlRtl8195A = 0x1381; + HalI2C2PinCtrlRtl8195A = 0x1459; + HalI2C3PinCtrlRtl8195A = 0x1529; + HalI2S0PinCtrlRtl8195A = 0x1639; + HalI2S1PinCtrlRtl8195A = 0x176d; + HalPCM0PinCtrlRtl8195A = 0x1845; + HalPCM1PinCtrlRtl8195A = 0x1949; + HalSDIODPinCtrlRtl8195A = 0x1a1d; + HalSDIOHPinCtrlRtl8195A = 0x1a6d; + HalMIIPinCtrlRtl8195A = 0x1ab9; + HalWLLEDPinCtrlRtl8195A = 0x1b51; + HalWLANT0PinCtrlRtl8195A = 0x1c0d; + HalWLANT1PinCtrlRtl8195A = 0x1c61; + HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5; + HalWLBTCMDPinCtrlRtl8195A = 0x1d05; + HalNFCPinCtrlRtl8195A = 0x1d59; + HalPWM0PinCtrlRtl8195A = 0x1da9; + HalPWM1PinCtrlRtl8195A = 0x1ead; + HalPWM2PinCtrlRtl8195A = 0x1fb5; + HalPWM3PinCtrlRtl8195A = 0x20b1; + HalETE0PinCtrlRtl8195A = 0x21b9; + HalETE1PinCtrlRtl8195A = 0x22c1; + HalETE2PinCtrlRtl8195A = 0x23c9; + HalETE3PinCtrlRtl8195A = 0x24d1; + HalEGTIMPinCtrlRtl8195A = 0x25d9; + HalSPIFlashPinCtrlRtl8195A = 0x2679; + HalSDRPinCtrlRtl8195A = 0x2725; + HalJTAGPinCtrlRtl8195A = 0x280d; + HalTRACEPinCtrlRtl8195A = 0x2861; + HalLOGUartPinCtrlRtl8195A = 0x28b9; + HalLOGUartIRPinCtrlRtl8195A = 0x291d; + HalSICPinCtrlRtl8195A = 0x2981; + HalEEPROMPinCtrlRtl8195A = 0x29d9; + HalDEBUGPinCtrlRtl8195A = 0x2a31; + HalPinCtrlRtl8195A = 0x2b39; + SpicRxCmdRtl8195A = 0x2e5d; + SpicWaitBusyDoneRtl8195A = 0x2ea5; + SpicGetFlashStatusRtl8195A = 0x2eb5; + SpicWaitWipDoneRtl8195A = 0x2f55; + SpicTxCmdRtl8195A = 0x2f6d; + SpicSetFlashStatusRtl8195A = 0x2fc1; + SpicCmpDataForCalibrationRtl8195A = 0x3049; + SpicLoadInitParaFromClockRtl8195A = 0x3081; + SpicInitRtl8195A = 0x30e5; + SpicEraseFlashRtl8195A = 0x31bd; + SpiFlashApp = 0x3279; + HalPeripheralIntrHandle = 0x33b5; + HalSysOnIntrHandle = 0x3439; + HalWdgIntrHandle = 0x3485; + HalTimer0IntrHandle = 0x34d5; + HalTimer1IntrHandle = 0x3525; + HalI2C3IntrHandle = 0x3575; + HalTimer2To7IntrHandle = 0x35c5; + HalSpi0IntrHandle = 0x3615; + HalGpioIntrHandle = 0x3665; + HalUart0IntrHandle = 0x36b5; + HalSpiFlashIntrHandle = 0x3705; + HalUsbOtgIntrHandle = 0x3755; + HalSdioHostIntrHandle = 0x37a5; + HalI2s0OrPcm0IntrHandle = 0x37f5; + HalI2s1OrPcm1IntrHandle = 0x3845; + HalWlDmaIntrHandle = 0x3895; + HalWlProtocolIntrHandle = 0x38e5; + HalCryptoIntrHandle = 0x3935; + HalGmacIntrHandle = 0x3985; + HalGdma0Ch0IntrHandle = 0x39d5; + HalGdma0Ch1IntrHandle = 0x3a25; + HalGdma0Ch2IntrHandle = 0x3a75; + HalGdma0Ch3IntrHandle = 0x3ac5; + HalGdma0Ch4IntrHandle = 0x3b15; + HalGdma0Ch5IntrHandle = 0x3b65; + HalGdma1Ch0IntrHandle = 0x3bb5; + HalGdma1Ch1IntrHandle = 0x3c05; + HalGdma1Ch2IntrHandle = 0x3c55; + HalGdma1Ch3IntrHandle = 0x3ca5; + HalGdma1Ch4IntrHandle = 0x3cf5; + HalGdma1Ch5IntrHandle = 0x3d45; + HalSdioDeviceIntrHandle = 0x3d95; + VectorTableInitRtl8195A = 0x3de5; + VectorTableInitForOSRtl8195A = 0x4019; + VectorIrqRegisterRtl8195A = 0x4029; + VectorIrqUnRegisterRtl8195A = 0x4091; + VectorIrqEnRtl8195A = 0x40f1; + VectorIrqDisRtl8195A = 0x418d; + _UartRxDmaIrqHandle = 0x422d; + HalRuartPutCRtl8195a = 0x4281; + HalRuartGetCRtl8195a = 0x429d; + HalRuartRTSCtrlRtl8195a = 0x42bd; + HalRuartGetDebugValueRtl8195a = 0x42e1; + HalRuartGetIMRRtl8195a = 0x43e1; + HalRuartSetIMRRtl8195a = 0x442d; + _UartIrqHandle = 0x4465; + HalRuartDmaInitRtl8195a = 0x4681; + HalRuartIntDisableRtl8195a = 0x4845; + HalRuartDeInitRtl8195a = 0x4855; + HalRuartIntEnableRtl8195a = 0x4985; + _UartTxDmaIrqHandle = 0x4995; + HalRuartRegIrqRtl8195a = 0x49d1; + HalRuartAdapterLoadDefRtl8195a = 0x4a4d; + HalRuartTxGdmaLoadDefRtl8195a = 0x4add; + HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9; + RuartLock = 0x4cc9; + RuartUnLock = 0x4ced; + HalRuartIntSendRtl8195a = 0x4d09; + HalRuartDmaSendRtl8195a = 0x4e35; + HalRuartStopSendRtl8195a = 0x4f89; + HalRuartIntRecvRtl8195a = 0x504d; + HalRuartDmaRecvRtl8195a = 0x51ad; + HalRuartStopRecvRtl8195a = 0x52cd; + RuartIsTimeout = 0x5385; + HalRuartSendRtl8195a = 0x53b1; + HalRuartRecvRtl8195a = 0x5599; + RuartResetRxFifoRtl8195a = 0x5751; + HalRuartResetRxFifoRtl8195a = 0x5775; + HalRuartInitRtl8195a = 0x5829; + HalGdmaOnOffRtl8195a = 0x5df1; + HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d; + HalGdmaChEnRtl8195a = 0x5e51; + HalGdmaChDisRtl8195a = 0x5e6d; + HalGdamChInitRtl8195a = 0x5e91; + HalGdmaChSetingRtl8195a = 0x5ebd; + HalGdmaChIsrCleanRtl8195a = 0x6419; + HalGdmaChCleanAutoSrcRtl8195a = 0x64a1; + HalGdmaChCleanAutoDstRtl8195a = 0x6501; + HalEFUSEPowerSwitch8195AROM = 0x6561; + HALEFUSEOneByteReadROM = 0x65f9; + HALEFUSEOneByteWriteROM = 0x6699; + rtl_memcmpb_v1_00 = 0x681d; + rtl_random_v1_00 = 0x6861; + rtl_align_to_be32_v1_00 = 0x6881; + rtl_memsetw_v1_00 = 0x6899; + rtl_memsetb_v1_00 = 0x68ad; + rtl_memcpyw_v1_00 = 0x68bd; + rtl_memcpyb_v1_00 = 0x68dd; + rtl_memDump_v1_00 = 0x68f5; + rtl_AES_set_encrypt_key = 0x6901; + rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11; + rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95; + rtl_cryptoEngine_init_v1_00 = 0x6ea9; + rtl_cryptoEngine_exit_v1_00 = 0x7055; + rtl_cryptoEngine_reset_v1_00 = 0x70b1; + rtl_cryptoEngine_v1_00 = 0x70ed; + rtl_crypto_cipher_init_v1_00 = 0x7c69; + rtl_crypto_cipher_encrypt_v1_00 = 0x7c89; + rtl_crypto_cipher_decrypt_v1_00 = 0x7cad; + HalSsiPinmuxEnableRtl8195a = 0x7cd5; + HalSsiEnableRtl8195a = 0x7e45; + HalSsiDisableRtl8195a = 0x7ef9; + HalSsiLoadSettingRtl8195a = 0x7fad; + HalSsiSetInterruptMaskRtl8195a = 0x8521; + HalSsiGetInterruptMaskRtl8195a = 0x85c9; + HalSsiSetSclkPolarityRtl8195a = 0x863d; + HalSsiSetSclkPhaseRtl8195a = 0x8715; + HalSsiWriteRtl8195a = 0x87e9; + HalSsiSetDeviceRoleRtl8195a = 0x8861; + HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9; + HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941; + HalSsiReadRtl8195a = 0x89b9; + HalSsiGetRxFifoLevelRtl8195a = 0x8a2d; + HalSsiGetTxFifoLevelRtl8195a = 0x8aa5; + HalSsiGetStatusRtl8195a = 0x8b1d; + HalSsiWriteableRtl8195a = 0x8b91; + HalSsiReadableRtl8195a = 0x8c09; + HalSsiBusyRtl8195a = 0x8c81; + HalSsiReadInterruptRtl8195a = 0x8cf9; + HalSsiWriteInterruptRtl8195a = 0x8efd; + HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009; + HalSsiGetInterruptStatusRtl8195a = 0x90d9; + HalSsiInterruptEnableRtl8195a = 0x914d; + HalSsiInterruptDisableRtl8195a = 0x9299; + HalSsiGetRawInterruptStatusRtl8195a = 0x93e9; + HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d; + HalSsiInitRtl8195a = 0x94d1; + _SsiReadInterrupt = 0x9ba5; + _SsiWriteInterrupt = 0x9db1; + _SsiIrqHandle = 0x9eb1; + HalI2CWrite32 = 0xa061; + HalI2CRead32 = 0xa09d; + HalI2CDeInit8195a = 0xa0dd; + HalI2CSendRtl8195a = 0xa1f1; + HalI2CReceiveRtl8195a = 0xa25d; + HalI2CEnableRtl8195a = 0xa271; + HalI2CIntrCtrl8195a = 0xa389; + HalI2CReadRegRtl8195a = 0xa3a1; + HalI2CWriteRegRtl8195a = 0xa3b1; + HalI2CSetCLKRtl8195a = 0xa3c5; + HalI2CMassSendRtl8195a = 0xa6e9; + HalI2CClrIntrRtl8195a = 0xa749; + HalI2CClrAllIntrRtl8195a = 0xa761; + HalI2CInit8195a = 0xa775; + HalI2CDMACtrl8195a = 0xaa31; + RtkI2CIoCtrl = 0xaa61; + RtkI2CPowerCtrl = 0xaa65; + HalI2COpInit = 0xaa69; + I2CIsTimeout = 0xac65; + I2CTXGDMAISRHandle = 0xb435; + I2CRXGDMAISRHandle = 0xb4c1; + RtkI2CIrqInit = 0xb54d; + RtkI2CIrqDeInit = 0xb611; + RtkI2CPinMuxInit = 0xb675; + RtkI2CPinMuxDeInit = 0xb7c9; + RtkI2CDMAInit = 0xb955; + RtkI2CInit = 0xbc95; + RtkI2CDMADeInit = 0xbdad; + RtkI2CDeInit = 0xbe4d; + RtkI2CSendUserAddr = 0xbee5; + RtkI2CSend = 0xc07d; + RtkI2CLoadDefault = 0xce51; + RtkSalI2COpInit = 0xcf21; + HalI2SWrite32 = 0xcf65; + HalI2SRead32 = 0xcf85; + HalI2SDeInitRtl8195a = 0xcfa9; + HalI2STxRtl8195a = 0xcfc9; + HalI2SRxRtl8195a = 0xd011; + HalI2SEnableRtl8195a = 0xd05d; + HalI2SIntrCtrlRtl8195a = 0xd0b1; + HalI2SReadRegRtl8195a = 0xd0d1; + HalI2SClrIntrRtl8195a = 0xd0dd; + HalI2SClrAllIntrRtl8195a = 0xd0fd; + HalI2SInitRtl8195a = 0xd11d; + GPIO_GetIPPinName_8195a = 0xd2e5; + GPIO_GetChipPinName_8195a = 0xd331; + GPIO_PullCtrl_8195a = 0xd39d; + GPIO_FuncOn_8195a = 0xd421; + GPIO_FuncOff_8195a = 0xd481; + GPIO_Int_Mask_8195a = 0xd4e9; + GPIO_Int_SetType_8195a = 0xd511; + HAL_GPIO_IrqHandler_8195a = 0xd5fd; + HAL_GPIO_MbedIrqHandler_8195a = 0xd645; + HAL_GPIO_UserIrqHandler_8195a = 0xd6a1; + HAL_GPIO_IntCtrl_8195a = 0xd6cd; + HAL_GPIO_Init_8195a = 0xd805; + HAL_GPIO_DeInit_8195a = 0xdac1; + HAL_GPIO_ReadPin_8195a = 0xdbd1; + HAL_GPIO_WritePin_8195a = 0xdc91; + HAL_GPIO_RegIrq_8195a = 0xddad; + HAL_GPIO_UnRegIrq_8195a = 0xddf5; + HAL_GPIO_UserRegIrq_8195a = 0xde15; + HAL_GPIO_UserUnRegIrq_8195a = 0xdef9; + HAL_GPIO_MaskIrq_8195a = 0xdfc1; + HAL_GPIO_UnMaskIrq_8195a = 0xe061; + HAL_GPIO_IntDebounce_8195a = 0xe101; + HAL_GPIO_GetIPPinName_8195a = 0xe1c1; + HAL_GPIO_PullCtrl_8195a = 0xe1c9; + DumpForOneBytes = 0xe259; + CmdRomHelp = 0xe419; + CmdWriteWord = 0xe491; + CmdDumpHelfWord = 0xe505; + CmdDumpWord = 0xe5f1; + CmdDumpByte = 0xe6f5; + CmdSpiFlashTool = 0xe751; + GetRomCmdNum = 0xe7a9; + CmdWriteByte = 0xe7ad; + Isspace = 0xe7ed; + Strtoul = 0xe801; + ArrayInitialize = 0xe8b1; + GetArgc = 0xe8c9; + GetArgv = 0xe8f9; + UartLogCmdExecute = 0xe95d; + UartLogShowBackSpace = 0xe9fd; + UartLogRecallOldCmd = 0xea39; + UartLogHistoryCmd = 0xea71; + UartLogCmdChk = 0xeadd; + UartLogIrqHandle = 0xebf5; + RtlConsolInit = 0xecc5; + RtlConsolTaskRom = 0xed49; + RtlExitConsol = 0xed79; + RtlConsolRom = 0xedcd; + HalTimerOpInit = 0xee0d; + HalTimerIrq2To7Handle = 0xee59; + HalGetTimerIdRtl8195a = 0xef09; + HalTimerInitRtl8195a = 0xef3d; + HalTimerDisRtl8195a = 0xf069; + HalTimerEnRtl8195a = 0xf089; + HalTimerReadCountRtl8195a = 0xf0a9; + HalTimerIrqClearRtl8195a = 0xf0bd; + HalTimerDumpRegRtl8195a = 0xf0d1; + VSprintf = 0xf129; + DiagPrintf = 0xf39d; + DiagSPrintf = 0xf3b9; + DiagSnPrintf = 0xf3d1; + prvDiagPrintf = 0xf3ed; + prvDiagSPrintf = 0xf40d; + _memcmp = 0xf429; + _memcpy = 0xf465; + _memset = 0xf511; + Rand = 0xf585; + _strncpy = 0xf60d; + _strcpy = 0xf629; + prvStrCpy = 0xf639; + _strlen = 0xf651; + _strnlen = 0xf669; + prvStrLen = 0xf699; + _strcmp = 0xf6b1; + _strncmp = 0xf6d1; + prvStrCmp = 0xf719; + StrUpr = 0xf749; + prvAtoi = 0xf769; + prvStrStr = 0xf7bd; + _strsep = 0xf7d5; + skip_spaces = 0xf815; + skip_atoi = 0xf831; + _parse_integer_fixup_radix = 0xf869; + _parse_integer = 0xf8bd; + simple_strtoull = 0xf915; + simple_strtoll = 0xf945; + simple_strtoul = 0xf965; + simple_strtol = 0xf96d; + _vsscanf = 0xf985; + _sscanf = 0xff71; + div_u64 = 0xff91; + div_s64 = 0xff99; + div_u64_rem = 0xffa1; + div_s64_rem = 0xffb1; + _strpbrk = 0xffc1; + _strchr = 0xffed; + aes_set_key = 0x10005; + aes_encrypt = 0x103d1; + aes_decrypt = 0x114a5; + AES_WRAP = 0x125c9; + AES_UnWRAP = 0x12701; + crc32_get = 0x12861; + arc4_byte = 0x12895; + rt_arc4_init = 0x128bd; + rt_arc4_crypt = 0x12901; + rt_md5_init = 0x131c1; + rt_md5_append = 0x131f5; + rt_md5_final = 0x1327d; + rt_md5_hmac = 0x132d5; + rtw_get_bit_value_from_ieee_value = 0x13449; + rtw_is_cckrates_included = 0x13475; + rtw_is_cckratesonly_included = 0x134b5; + rtw_check_network_type = 0x134dd; + rtw_set_fixed_ie = 0x1350d; + rtw_set_ie = 0x1352d; + rtw_get_ie = 0x1355d; + rtw_set_supported_rate = 0x13591; + rtw_get_rateset_len = 0x13611; + rtw_get_wpa_ie = 0x1362d; + rtw_get_wpa2_ie = 0x136c9; + rtw_get_wpa_cipher_suite = 0x13701; + rtw_get_wpa2_cipher_suite = 0x13769; + rtw_parse_wpa_ie = 0x137d1; + rtw_parse_wpa2_ie = 0x138ad; + rtw_get_sec_ie = 0x13965; + rtw_get_wps_ie = 0x13a15; + rtw_get_wps_attr = 0x13a99; + rtw_get_wps_attr_content = 0x13b49; + rtw_ieee802_11_parse_elems = 0x13b91; + str_2char2num = 0x13d9d; + key_2char2num = 0x13db9; + convert_ip_addr = 0x13dd1; + rom_psk_PasswordHash = 0x13e9d; + rom_psk_CalcGTK = 0x13ed5; + rom_psk_CalcPTK = 0x13f69; + wep_80211_encrypt = 0x14295; + wep_80211_decrypt = 0x142f5; + tkip_micappendbyte = 0x14389; + rtw_secmicsetkey = 0x143d9; + rtw_secmicappend = 0x14419; + rtw_secgetmic = 0x14435; + rtw_seccalctkipmic = 0x1449d; + tkip_phase1 = 0x145a5; + tkip_phase2 = 0x14725; + tkip_80211_encrypt = 0x14941; + tkip_80211_decrypt = 0x149d5; + aes1_encrypt = 0x14a8d; + aesccmp_construct_mic_iv = 0x14c65; + aesccmp_construct_mic_header1 = 0x14ccd; + aesccmp_construct_mic_header2 = 0x14d21; + aesccmp_construct_ctr_preload = 0x14db5; + aes_80211_encrypt = 0x14e29; + aes_80211_decrypt = 0x151ad; + _sha1_process_message_block = 0x155b9; + _sha1_pad_message = 0x15749; + rt_sha1_init = 0x157e5; + rt_sha1_update = 0x15831; + rt_sha1_finish = 0x158a9; + rt_hmac_sha1 = 0x15909; + rom_aes_128_cbc_encrypt = 0x15a65; + rom_aes_128_cbc_decrypt = 0x15ae1; + rom_rijndaelKeySetupEnc = 0x15b5d; + rom_aes_decrypt_init = 0x15c39; + rom_aes_internal_decrypt = 0x15d15; + rom_aes_decrypt_deinit = 0x16071; + rom_aes_encrypt_init = 0x16085; + rom_aes_internal_encrypt = 0x1609d; + rom_aes_encrypt_deinit = 0x16451; + bignum_init = 0x17b35; + bignum_deinit = 0x17b61; + bignum_get_unsigned_bin_len = 0x17b81; + bignum_get_unsigned_bin = 0x17b85; + bignum_set_unsigned_bin = 0x17c21; + bignum_cmp = 0x17cd1; + bignum_cmp_d = 0x17cd5; + bignum_add = 0x17cfd; + bignum_sub = 0x17d0d; + bignum_mul = 0x17d1d; + bignum_exptmod = 0x17d2d; + WPS_realloc = 0x17d51; + os_zalloc = 0x17d99; + rom_hmac_sha256_vector = 0x17dc1; + rom_hmac_sha256 = 0x17ebd; + rom_sha256_vector = 0x18009; + phy_CalculateBitShift = 0x18221; + PHY_SetBBReg_8195A = 0x18239; + PHY_QueryBBReg_8195A = 0x18279; + ROM_odm_QueryRxPwrPercentage = 0x1829d; + ROM_odm_EVMdbToPercentage = 0x182bd; + ROM_odm_SignalScaleMapping_8195A = 0x182e5; + ROM_odm_FalseAlarmCounterStatistics = 0x183cd; + ROM_odm_SetEDCCAThreshold = 0x18721; + ROM_odm_SetTRxMux = 0x18749; + ROM_odm_SetCrystalCap = 0x18771; + ROM_odm_GetDefaultCrytaltalCap = 0x187d5; + ROM_ODM_CfoTrackingReset = 0x187e9; + ROM_odm_CfoTrackingFlow = 0x18811; + curve25519_donna = 0x1965d; + aes_test_alignment_detection = 0x1a391; + aes_mode_reset = 0x1a3ed; + aes_ecb_encrypt = 0x1a3f9; + aes_ecb_decrypt = 0x1a431; + aes_cbc_encrypt = 0x1a469; + aes_cbc_decrypt = 0x1a579; + aes_cfb_encrypt = 0x1a701; + aes_cfb_decrypt = 0x1a9e5; + aes_ofb_crypt = 0x1acc9; + aes_ctr_crypt = 0x1af7d; + aes_encrypt_key128 = 0x1b289; + aes_encrypt_key192 = 0x1b2a5; + aes_encrypt_key256 = 0x1b2c1; + aes_encrypt_key = 0x1b2e1; + aes_decrypt_key128 = 0x1b351; + aes_decrypt_key192 = 0x1b36d; + aes_decrypt_key256 = 0x1b389; + aes_decrypt_key = 0x1b3a9; + aes_init = 0x1b419; + CRYPTO_chacha_20 = 0x1b41d; + CRYPTO_poly1305_init = 0x1bc25; + CRYPTO_poly1305_update = 0x1bd09; + CRYPTO_poly1305_finish = 0x1bd8d; + rom_sha512_starts = 0x1ceb5; + rom_sha512_update = 0x1d009; + rom_sha512_finish = 0x1d011; + rom_sha512 = 0x1d261; + rom_sha512_hmac_starts = 0x1d299; + rom_sha512_hmac_update = 0x1d35d; + rom_sha512_hmac_finish = 0x1d365; + rom_sha512_hmac_reset = 0x1d3b5; + rom_sha512_hmac = 0x1d3d1; + rom_sha512_hkdf = 0x1d40d; + rom_ed25519_gen_keypair = 0x1d501; + rom_ed25519_gen_signature = 0x1d505; + rom_ed25519_verify_signature = 0x1d51d; + rom_ed25519_crypto_sign_seed_keypair = 0x1d521; + rom_ed25519_crypto_sign_detached = 0x1d579; + rom_ed25519_crypto_sign_verify_detached = 0x1d655; + rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d; + rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35; + rom_ed25519_ge_p3_tobytes = 0x207d5; + rom_ed25519_ge_scalarmult_base = 0x20821; + rom_ed25519_ge_tobytes = 0x209e1; + rom_ed25519_sc_muladd = 0x20a2d; + rom_ed25519_sc_reduce = 0x2603d; + rtl_memchr_v1_00 = 0x28a4d; + rtl_memcmp_v1_00 = 0x28ae1; + rtl_memcpy_v1_00 = 0x28b49; + __aeabi_memcpy = 0x28b49; + __aeabi_memcpy4 = 0x28b49; + rtl_memmove_v1_00 = 0x28bed; + rtl_memset_v1_00 = 0x28cb5; + __aeabi_memset = 0x28cb5; + rtl_strcat_v1_00 = 0x28d49; + rtl_strchr_v1_00 = 0x28d91; + rtl_strcmp_v1_00 = 0x28e55; + rtl_strcpy_v1_00 = 0x28ec9; + rtl_strlen_v1_00 = 0x28f15; + rtl_strncat_v1_00 = 0x28f69; + rtl_strncmp_v1_00 = 0x28fc5; + rtl_strncpy_v1_00 = 0x2907d; + rtl_strstr_v1_00 = 0x293cd; + rtl_strsep_v1_00 = 0x2960d; + rtl_strtok_v1_00 = 0x29619; + rtl__strtok_r_v1_00 = 0x2962d; + rtl_strtok_r_v1_00 = 0x29691; + rtl_close_v1_00 = 0x29699; + rtl_fstat_v1_00 = 0x296ad; + rtl_isatty_v1_00 = 0x296c1; + rtl_lseek_v1_00 = 0x296d5; + rtl_open_v1_00 = 0x296e9; + rtl_read_v1_00 = 0x296fd; + rtl_write_v1_00 = 0x29711; + rtl_sbrk_v1_00 = 0x29725; + rtl_ltoa_v1_00 = 0x297bd; + rtl_ultoa_v1_00 = 0x29855; + rtl_dtoi_v1_00 = 0x298c5; + rtl_dtoi64_v1_00 = 0x29945; + rtl_dtoui_v1_00 = 0x299dd; + rtl_ftol_v1_00 = 0x299e5; + rtl_itof_v1_00 = 0x29a51; + rtl_itod_v1_00 = 0x29ae9; + rtl_i64tod_v1_00 = 0x29b79; + rtl_uitod_v1_00 = 0x29c55; + rtl_ftod_v1_00 = 0x29d2d; + rtl_dtof_v1_00 = 0x29de9; + rtl_uitof_v1_00 = 0x29e89; + rtl_fadd_v1_00 = 0x29f65; + rtl_fsub_v1_00 = 0x2a261; + rtl_fmul_v1_00 = 0x2a559; + rtl_fdiv_v1_00 = 0x2a695; + rtl_dadd_v1_00 = 0x2a825; + rtl_dsub_v1_00 = 0x2aed9; + rtl_dmul_v1_00 = 0x2b555; + rtl_ddiv_v1_00 = 0x2b8ad; + rtl_dcmpeq_v1_00 = 0x2be4d; + rtl_dcmplt_v1_00 = 0x2bebd; + rtl_dcmpgt_v1_00 = 0x2bf51; + rtl_dcmple_v1_00 = 0x2c049; + rtl_fcmplt_v1_00 = 0x2c139; + rtl_fcmpgt_v1_00 = 0x2c195; + rtl_cos_f32_v1_00 = 0x2c229; + rtl_sin_f32_v1_00 = 0x2c435; + rtl_fabs_v1_00 = 0x2c639; + rtl_fabsf_v1_00 = 0x2c641; + rtl_dtoa_r_v1_00 = 0x2c77d; + __rom_mallocr_init_v1_00 = 0x2d7d1; + rtl_free_r_v1_00 = 0x2d841; + rtl_malloc_r_v1_00 = 0x2da31; + rtl_realloc_r_v1_00 = 0x2df55; + rtl_memalign_r_v1_00 = 0x2e331; + rtl_valloc_r_v1_00 = 0x2e421; + rtl_pvalloc_r_v1_00 = 0x2e42d; + rtl_calloc_r_v1_00 = 0x2e441; + rtl_cfree_r_v1_00 = 0x2e4a9; + rtl_Balloc_v1_00 = 0x2e515; + rtl_Bfree_v1_00 = 0x2e571; + rtl_i2b_v1_00 = 0x2e585; + rtl_multadd_v1_00 = 0x2e599; + rtl_mult_v1_00 = 0x2e629; + rtl_pow5mult_v1_00 = 0x2e769; + rtl_hi0bits_v1_00 = 0x2e809; + rtl_d2b_v1_00 = 0x2e845; + rtl_lshift_v1_00 = 0x2e901; + rtl_cmp_v1_00 = 0x2e9bd; + rtl_diff_v1_00 = 0x2ea01; + rtl_sread_v1_00 = 0x2eae9; + rtl_seofread_v1_00 = 0x2eb39; + rtl_swrite_v1_00 = 0x2eb3d; + rtl_sseek_v1_00 = 0x2ebc1; + rtl_sclose_v1_00 = 0x2ec11; + rtl_sbrk_r_v1_00 = 0x2ec41; + rtl_fflush_r_v1_00 = 0x2ef8d; + rtl_vfprintf_r_v1_00 = 0x2f661; + rtl_fpclassifyd = 0x30c15; + CpkClkTbl = 0x30c68; + ROM_IMG1_VALID_PATTEN = 0x30c80; + SpicCalibrationPattern = 0x30c88; + SpicInitCPUCLK = 0x30c98; + BAUDRATE = 0x30ca8; + OVSR = 0x30d1c; + DIV = 0x30d90; + OVSR_ADJ = 0x30e04; + __AES_rcon = 0x30e78; + __AES_Te4 = 0x30ea0; + I2CDmaChNo = 0x312a0; + _GPIO_PinMap_Chip2IP_8195a = 0x312b4; + _GPIO_PinMap_PullCtrl_8195a = 0x3136c; + _GPIO_SWPORT_DDR_TBL = 0x31594; + _GPIO_EXT_PORT_TBL = 0x31598; + _GPIO_SWPORT_DR_TBL = 0x3159c; + UartLogRomCmdTable = 0x316a0; + _HalRuartOp = 0x31700; + _HalGdmaOp = 0x31760; + RTW_WPA_OUI_TYPE = 0x3540c; + WPA_CIPHER_SUITE_NONE = 0x35410; + WPA_CIPHER_SUITE_WEP40 = 0x35414; + WPA_CIPHER_SUITE_TKIP = 0x35418; + WPA_CIPHER_SUITE_CCMP = 0x3541c; + WPA_CIPHER_SUITE_WEP104 = 0x35420; + RSN_CIPHER_SUITE_NONE = 0x35424; + RSN_CIPHER_SUITE_WEP40 = 0x35428; + RSN_CIPHER_SUITE_TKIP = 0x3542c; + RSN_CIPHER_SUITE_CCMP = 0x35430; + RSN_CIPHER_SUITE_WEP104 = 0x35434; + RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444; + RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448; + RSN_VERSION_BSD = 0x3544c; + rom_wps_Te0 = 0x35988; + rom_wps_rcons = 0x35d88; + rom_wps_Td4s = 0x35d94; + rom_wps_Td0 = 0x35e94; + __rom_b_cut_end__ = 0x4467c; + __rom_c_cut_text_start__ = 0x4467c; + HalInitPlatformLogUartV02 = 0x4467d; + HalReInitPlatformLogUartV02 = 0x4471d; + HalInitPlatformTimerV02 = 0x44755; + HalShowBuildInfoV02 = 0x447cd; + SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831; + HalSpiInitV02 = 0x4488d; + HalBootFlowV02 = 0x44a29; + HalInitialROMCodeGlobalVarV02 = 0x44ae5; + HalResetVsrV02 = 0x44b41; + HalI2CSendRtl8195aV02 = 0x44ce1; + HalI2CSetCLKRtl8195aV02 = 0x44d59; + RtkI2CSendV02 = 0x4508d; + RtkI2CReceiveV02 = 0x459a1; + HalI2COpInitV02 = 0x461ed; + I2CISRHandleV02 = 0x463e9; + RtkSalI2COpInitV02 = 0x46be1; + SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25; + SpiFlashAppV02 = 0x46c85; + SpicInitRtl8195AV02 = 0x46dc5; + SpicEraseFlashRtl8195AV02 = 0x46ea1; + HalTimerIrq2To7HandleV02 = 0x46f5d; + HalTimerIrqRegisterRtl8195aV02 = 0x46fe1; + HalTimerInitRtl8195aV02 = 0x4706d; + HalTimerReadCountRtl8195aV02 = 0x471b5; + HalTimerReLoadRtl8195aV02 = 0x471d1; + HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d; + HalTimerDeInitRtl8195aV02 = 0x472c1; + HalTimerOpInitV02 = 0x472f9; + GPIO_LockV02 = 0x47345; + GPIO_UnLockV02 = 0x47379; + GPIO_Int_Clear_8195aV02 = 0x473a5; + HAL_GPIO_IntCtrl_8195aV02 = 0x473b5; + FindElementIndexV02 = 0x47541; + HalRuartInitRtl8195aV02 = 0x4756d; + DramInit_rom = 0x47619; + ChangeRandSeed_rom = 0x47979; + Sdr_Rand2_rom = 0x47985; + MemTest_rom = 0x479dd; + SdrCalibration_rom = 0x47a45; + SdrControllerInit_rom = 0x47d99; + SDIO_EnterCritical = 0x47e39; + SDIO_ExitCritical = 0x47e85; + SDIO_IRQ_Handler_Rom = 0x47ec5; + SDIO_Interrupt_Init_Rom = 0x47f31; + SDIO_Device_Init_Rom = 0x47f81; + SDIO_Interrupt_DeInit_Rom = 0x48215; + SDIO_Device_DeInit_Rom = 0x48255; + SDIO_Enable_Interrupt_Rom = 0x48281; + SDIO_Disable_Interrupt_Rom = 0x482a1; + SDIO_Clear_ISR_Rom = 0x482c1; + SDIO_Alloc_Rx_Pkt_Rom = 0x482d9; + SDIO_Free_Rx_Pkt_Rom = 0x48331; + SDIO_Recycle_Rx_BD_Rom = 0x48355; + SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1; + SDIO_RxTask_Rom = 0x4851d; + SDIO_Process_H2C_IOMsg_Rom = 0x4856d; + SDIO_Send_C2H_IOMsg_Rom = 0x4859d; + SDIO_Process_RPWM_Rom = 0x485b5; + SDIO_Reset_Cmd_Rom = 0x485e9; + SDIO_Rx_Data_Transaction_Rom = 0x48611; + SDIO_Send_C2H_PktMsg_Rom = 0x48829; + SDIO_Register_Tx_Callback_Rom = 0x488f5; + SDIO_ReadMem_Rom = 0x488fd; + SDIO_WriteMem_Rom = 0x489a9; + SDIO_SetMem_Rom = 0x48a69; + SDIO_TX_Pkt_Handle_Rom = 0x48b29; + SDIO_TX_FIFO_DataReady_Rom = 0x48c69; + SDIO_IRQ_Handler_BH_Rom = 0x48d95; + SDIO_TxTask_Rom = 0x48e9d; + SDIO_TaskUp_Rom = 0x48eed; + SDIO_Boot_Up = 0x48f55; + __rom_c_cut_text_end__ = 0x49070; + __rom_c_cut_rodata_start__ = 0x49070; + BAUDRATE_v02 = 0x49070; + OVSR_v02 = 0x490fc; + DIV_v02 = 0x49188; + OVSR_ADJ_v02 = 0x49214; + SdrDramInfo_rom = 0x492a0; + SdrDramTiming_rom = 0x492b4; + SdrDramModeReg_rom = 0x492e8; + SdrDramDev_rom = 0x49304; + __rom_c_cut_rodata_end__ = 0x49314; + NewVectorTable = 0x10000000; + UserIrqFunTable = 0x10000100; + UserIrqDataTable = 0x10000200; + __rom_bss_start__ = 0x10000300; + CfgSysDebugWarn = 0x10000300; + CfgSysDebugInfo = 0x10000304; + CfgSysDebugErr = 0x10000308; + ConfigDebugWarn = 0x1000030c; + ConfigDebugInfo = 0x10000310; + ConfigDebugErr = 0x10000314; + HalTimerOp = 0x10000318; + GPIOState = 0x10000334; + gTimerRecord = 0x1000034c; + SSI_DBG_CONFIG = 0x10000350; + _pHAL_Gpio_Adapter = 0x10000354; + Timer2To7VectorTable = 0x10000358; + pUartLogCtl = 0x10000384; + UartLogBuf = 0x10000388; + UartLogCtl = 0x10000408; + UartLogHistoryBuf = 0x10000430; + ArgvArray = 0x100006ac; + rom_wlan_ram_map = 0x100006d4; + FalseAlmCnt = 0x100006e0; + ROMInfo = 0x10000720; + DM_CfoTrack = 0x10000738; + rom_libgloss_ram_map = 0x10000760; + rtl_errno = 0x10000bc4; + _rtl_impure_ptr = 0x10001c60; +} diff --git a/lib/cpu/rtl8710/rtl8710.h b/lib/cpu/rtl8710/rtl8710.h new file mode 100644 index 0000000..8eb9ec9 --- /dev/null +++ b/lib/cpu/rtl8710/rtl8710.h @@ -0,0 +1,13 @@ +#ifndef _RTL8710_H_ +#define _RTL8710_H_ + +#include "rtl8710_sys.h" +#include "rtl8710_int.h" +#include "rtl8710_peri_on.h" +#include "rtl8710_timer.h" +#include "rtl8710_gpio.h" +//#include "rtl8710_log_uart.h" +//#include "rtl8710_spi.h" + +#endif + diff --git a/lib/cpu/rtl8710/rtl8710.ld b/lib/cpu/rtl8710/rtl8710.ld new file mode 100644 index 0000000..5f6a35b --- /dev/null +++ b/lib/cpu/rtl8710/rtl8710.ld @@ -0,0 +1,48 @@ +MEMORY{ + tcm (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64k + ram (rwx) : ORIGIN = 0x10000000, LENGTH = 448k +} + +PROVIDE(STACK_TOP = 0x1FFF0000 + 64k); + +SECTIONS{ + __rom_bss_start__ = 0x10000300; + __rom_bss_end__ = 0x10000bc8; + + + .text : { + __text_beg__ = . ; + *(.vectors*) *(.header) *(.text) *(.text*) *(.rodata) *(.rodata*) *(.glue_7) *(.glue_7t) *(.eh_frame) *(.ARM.extab*) . = ALIGN(4); __text_end__ = . ; + } >ram + + .data : { + . = ALIGN(4); + __data_beg__ = . ; + *(.ram_vectors) *(.data) *(.data*) *(.ram_func) . = ALIGN(4); + __data_end__ = . ; + } >ram + + .bss : { + . = ALIGN(4); + __bss_beg__ = . ; + *(.bss) *(COMMON) . = ALIGN(4); __bss_end__ = . ; + } >ram + __exidx_start = .; + + .ARM.exidx : { + ___exidx_start = . ; + *(.ARM.exidx*) ; + ___exidx_end = . ; } >ram + __exidx_end = .; + + .ARM.extab : { + *(.ARM.extab*) + } >ram + + . = ALIGN(4); + + end = .; + PROVIDE (end = .); +} + +INCLUDE "export-rom_v03.txt" diff --git a/lib/cpu/rtl8710/rtl8710.ocd b/lib/cpu/rtl8710/rtl8710.ocd new file mode 100644 index 0000000..adfb0f5 --- /dev/null +++ b/lib/cpu/rtl8710/rtl8710.ocd @@ -0,0 +1,332 @@ +# +# OpenOCD script for RTL8710 +# Copyright (C) 2016 Rebane, rebane@alkohol.ee +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME rtl8710 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x800 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x2ba01477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x10001000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# adapter_khz 500 +adapter_nsrst_delay 100 + +if {![using_hla]} { + cortex_m reset_config sysresetreq +} + +set rtl8710_flasher_firmware_ptr 0x10001000 +set rtl8710_flasher_buffer 0x10008000 +set rtl8710_flasher_buffer_size 262144 +set rtl8710_flasher_sector_size 4096 + +array set rtl8710_flasher_code { + 0 0xB671B57F 1 0x25FF4B58 2 0x6B196B1A 3 0x7040F042 4 0x69D96318 5 0xF4414E55 + 6 0x69D97480 7 0xF8D361DC 8 0xF8C32120 9 0xF8D35120 10 0xF8C31124 11 0x47B05124 + 12 0x47B04E4F 13 0x47984B4F 14 0x60104A4F 15 0x484F47B0 16 0x60012100 17 0x2C006804 + 18 0x4D4DD0FC 19 0xB93E682E 20 0x60264C49 21 0x47B04E46 22 0x47984B46 23 0xE7ED6020 + 24 0x2B01682B 25 0x4E42D109 26 0x4C4647B0 27 0x47A02006 28 0x47904A45 29 0x47A020C7 + 30 0x682AE00D 31 0xD10E2A02 32 0x47B04E3B 33 0x20064C3F 34 0x483F47A0 35 0x493F4780 + 36 0x68084D3F 37 0x47B047A8 38 0x47A02004 39 0x6828E7CE 40 0xD1132803 41 0x47A04C32 + 42 0x24004838 43 0x4E396805 44 0x68311960 45 0xD206428C 46 0x4B384A37 47 0x221018A1 + 48 0x34104798 49 0x4D2AE7F3 50 0xE7B847A8 51 0x29046829 52 0x2400D11B 53 0x6806482F + 54 0xD2B042B4 55 0x47A84D24 56 0x20064E28 57 0x4B2847B0 58 0x49284798 59 0x680A4B2A + 60 0x18A018E1 61 0xF44F4B2A 62 0x47987280 63 0x200447A8 64 0xF50447B0 65 0x47A87480 + 66 0x682CE7E4 67 0xD1232C05 68 0x47984B17 69 0x4D1F2400 70 0x4294682A 71 0x481BD28F + 72 0x68012210 73 0x18604E1D 74 0x47B04669 75 0x1B19682B 76 0xBF282910 77 0x23002110 + 78 0xD011428B 79 0xF81D4A16 80 0x18A05003 81 0x42B55CC6 82 0x3301D101 83 0x4A15E7F4 + 84 0x60112101 85 0xE7726054 86 0x25014E12 87 0xE76E6035 88 0x47A84D03 89 0xE7D63410 + 90 0x40000200 91 0x100011BD 92 0x100013DD 93 0x10001289 94 0x1000800C 95 0x10008000 + 96 0x10008004 97 0x1000130D 98 0x100013ED 99 0x10008010 100 0x10001335 101 0x10008014 + 102 0x10008020 103 0x10001221 104 0x10001375 105 0x10008008 106 0x6A5A4B03 107 0xD0FB0512 + 108 0x0060F893 109 0xBF004770 110 0x40006000 111 0x6B194B17 112 0xF4416B1A 113 0x63187040 + 114 0x69186919 115 0x0110F041 116 0xF8D36119 117 0x220000C0 118 0x0106F020 119 0x00C0F8D3 + 120 0x10C0F8C3 121 0x00C0F8D3 122 0x0101F040 123 0x00C0F8D3 124 0x10C0F8C3 125 0x43BCF503 + 126 0x609A6899 127 0x20016AD9 128 0x691962DA 129 0x69596118 130 0x61592102 131 0x619A6999 + 132 0x61DA69D9 133 0x64DA6CD9 134 0xBF004770 135 0x40000200 136 0x460EB570 137 0xB34A4614 + 138 0xF3C04B15 139 0x681A4507 140 0x7240F44F 141 0x685A601A 142 0xF3C02103 143 0x2C102207 + 144 0x2410BF28 145 0x605CB2C0 146 0x1060F883 147 0x5060F883 148 0xF8832101 149 0xF8832060 + 150 0x689A0060 151 0x60992500 152 0x47984B08 153 0x35015570 154 0x42A2B2AA 155 0x4804D3F8 + 156 0xF0116A81 157 0xD1FA0301 158 0x60836881 159 0xBD704620 160 0x40006000 161 0x100011A9 + 162 0x4C10B5F8 163 0x68232003 164 0x7340F44F 165 0x68636023 166 0x60602101 167 0x68A3229F + 168 0x60A14D0B 169 0x2060F884 170 0x460647A8 171 0x460747A8 172 0x040347A8 173 0x2707EA43 + 174 0x0006EA47 175 0x4B036AA1 176 0x0201F011 177 0x6899D1FA 178 0xBDF8609A 179 0x40006000 + 180 0x100011A9 181 0x4C0BB510 182 0x68232001 183 0x7340F44F 184 0x68636023 185 0x60602105 + 186 0x60A068A2 187 0xF8844A06 188 0x47901060 189 0x4B036AA1 190 0x0201F011 191 0x6899D1FA + 192 0xBD10609A 193 0x40006000 194 0x100011A9 195 0x21014B08 196 0xF44F681A 197 0x601A7280 + 198 0x6099689A 199 0x0060F883 200 0x48036A9A 201 0x0101F012 202 0x6883D1FA 203 0x47706081 + 204 0x40006000 205 0x21014B0E 206 0xF44F681A 207 0x601A7280 208 0x2220689A 209 0xF8836099 + 210 0xF3C02060 211 0xF3C04107 212 0xB2C02207 213 0x1060F883 214 0x2060F883 215 0x0060F883 + 216 0x4A036A99 217 0x0001F011 218 0x6893D1FA 219 0x47706090 220 0x40006000 221 0xB36AB530 + 222 0x25014B17 223 0xF44F681C 224 0x601C7480 225 0x2402689C 226 0xF883609D 227 0xF3C04060 + 228 0xF3C04507 229 0xB2C02407 230 0x5060F883 231 0x7F80F5B2 232 0xF44FBF28 233 0xF8837280 + 234 0xF8834060 235 0x20000060 236 0x4C095C0D 237 0xF8843001 238 0xB2855060 239 0xD3F74295 + 240 0x07496A99 241 0x6AA0D5FC 242 0xF0104B03 243 0xD1FA0101 244 0x60996898 245 0xBD304610 + 246 0x40006000 247 0x4B02B508 248 0x07C04798 249 0xBD08D4FB 250 0x100012D5 251 0x4B04B508 + 252 0xF0004798 253 0xB2C10002 254 0xD0F82900 255 0xBF00BD08 256 0x100012D5 +} + +set rtl8710_flasher_command_read_id 0 +set rtl8710_flasher_command_mass_erase 1 +set rtl8710_flasher_command_sector_erase 2 +set rtl8710_flasher_command_read 3 +set rtl8710_flasher_command_write 4 +set rtl8710_flasher_command_verify 5 + +set rtl8710_flasher_ready 0 +set rtl8710_flasher_capacity 0 +set rtl8710_flasher_auto_erase 0 +set rtl8710_flasher_auto_verify 0 +set rtl8710_flasher_auto_erase_sector 0xFFFFFFFF + +proc rtl8710_flasher_init {} { + global rtl8710_flasher_firmware_ptr + global rtl8710_flasher_buffer + global rtl8710_flasher_capacity + global rtl8710_flasher_ready + global rtl8710_flasher_code + + if {[expr {$rtl8710_flasher_ready == 0}]} { + echo "initializing RTL8710 flasher" + halt + mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000 + mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001 + array2mem rtl8710_flasher_code 32 $rtl8710_flasher_firmware_ptr [array size rtl8710_flasher_code] + reg faultmask 0x01 + reg sp 0x20000000 + reg pc $rtl8710_flasher_firmware_ptr + resume + rtl8710_flasher_wait + set id [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]] + set rtl8710_flasher_capacity [expr {2 ** [expr {($id >> 16) & 0xFF}]}] + set rtl8710_flasher_ready 1 + echo "RTL8710 flasher initialized" + } + return "" +} + +proc rtl8710_flasher_mrw {reg} { + set value "" + mem2array value 32 $reg 1 + return $value(0) +} + +proc rtl8710_flasher_wait {} { + global rtl8710_flasher_buffer + while {[rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x00}]]} { } +} + +proc rtl8710_flasher_load_block {local_filename offset len} { + global rtl8710_flasher_buffer + load_image $local_filename [expr {$rtl8710_flasher_buffer + 0x20 - $offset}] bin [expr {$rtl8710_flasher_buffer + 0x20}] $len +} + +proc rtl8710_flasher_read_block {offset len} { + global rtl8710_flasher_buffer + global rtl8710_flasher_command_read + mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_read + mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000 + mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset + mww [expr {$rtl8710_flasher_buffer + 0x14}] $len + mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001 + rtl8710_flasher_wait + set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]] + if {[expr {$status > 0}]} { + error "read error, offset $offset" + } +} + +proc rtl8710_flasher_write_block {offset len} { + global rtl8710_flasher_buffer + global rtl8710_flasher_command_write + mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_write + mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000 + mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset + mww [expr {$rtl8710_flasher_buffer + 0x14}] $len + mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001 + rtl8710_flasher_wait + set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]] + if {[expr {$status > 0}]} { + error "write error, offset $offset" + } +} + +proc rtl8710_flasher_verify_block {offset len} { + global rtl8710_flasher_buffer + global rtl8710_flasher_command_verify + mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_verify + mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000 + mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset + mww [expr {$rtl8710_flasher_buffer + 0x14}] $len + mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001 + rtl8710_flasher_wait + set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]] + if {[expr {$status > 0}]} { + set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]] + set status [expr {$status + $offset}] + error "verify error, offset $status" + } +} + +proc rtl8710_flash_read_id {} { + global rtl8710_flasher_buffer + global rtl8710_flasher_capacity + global rtl8710_flasher_command_read_id + rtl8710_flasher_init + mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_read_id + mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000 + mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001 + rtl8710_flasher_wait + set id [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]] + set manufacturer_id [format "0x%02X" [expr {$id & 0xFF}]] + set memory_type [format "0x%02X" [expr {($id >> 8) & 0xFF}]] + set memory_capacity [expr {2 ** [expr {($id >> 16) & 0xFF}]}] + echo "manufacturer ID: $manufacturer_id, memory type: $memory_type, memory capacity: $memory_capacity bytes" +} + +proc rtl8710_flash_mass_erase {} { + global rtl8710_flasher_buffer + global rtl8710_flasher_command_mass_erase + rtl8710_flasher_init + mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_mass_erase + mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000 + mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001 + rtl8710_flasher_wait +} + +proc rtl8710_flash_sector_erase {offset} { + global rtl8710_flasher_buffer + global rtl8710_flasher_command_sector_erase + rtl8710_flasher_init + mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_sector_erase + mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000 + mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset + mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001 + rtl8710_flasher_wait +} + +proc rtl8710_flash_read {local_filename loc size} { + global rtl8710_flasher_buffer + global rtl8710_flasher_buffer_size + rtl8710_flasher_init + for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} { + set len [expr {$size - $offset}] + if {[expr {$len > $rtl8710_flasher_buffer_size}]} { + set len $rtl8710_flasher_buffer_size + } + set flash_offset [expr {$loc + $offset}] + echo "read offset $flash_offset" + rtl8710_flasher_read_block $flash_offset $len + dump_image /tmp/_rtl8710_flasher.bin [expr {$rtl8710_flasher_buffer + 0x20}] $len + exec dd conv=notrunc if=/tmp/_rtl8710_flasher.bin "of=$local_filename" bs=1 "seek=$offset" + echo "read $len bytes" + } +} + +proc rtl8710_flash_write {local_filename loc} { + global rtl8710_flasher_buffer_size + global rtl8710_flasher_sector_size + global rtl8710_flasher_auto_erase + global rtl8710_flasher_auto_verify + global rtl8710_flasher_auto_erase_sector + rtl8710_flasher_init + set sector 0 + set size [file size $local_filename] + for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} { + set len [expr {$size - $offset}] + if {[expr {$len > $rtl8710_flasher_buffer_size}]} { + set len $rtl8710_flasher_buffer_size + } + set flash_offset [expr {$loc + $offset}] + echo "write offset $flash_offset" + rtl8710_flasher_load_block $local_filename $offset $len + if {[expr {$rtl8710_flasher_auto_erase != 0}]} { + for {set i $flash_offset} {$i < [expr {$flash_offset + $len}]} {incr i} { + set sector [expr {$i / $rtl8710_flasher_sector_size}] + if {[expr {$rtl8710_flasher_auto_erase_sector != $sector}]} { + echo "erase sector $sector" + rtl8710_flash_sector_erase [expr {$sector * $rtl8710_flasher_sector_size}] + set rtl8710_flasher_auto_erase_sector $sector + } + } + } + rtl8710_flasher_write_block $flash_offset $len + echo "wrote $len bytes" + if {[expr {$rtl8710_flasher_auto_verify != 0}]} { + echo "verify offset $flash_offset" + rtl8710_flasher_verify_block $flash_offset $len + } + } +} + +proc rtl8710_flash_verify {local_filename loc} { + global rtl8710_flasher_buffer_size + rtl8710_flasher_init + set size [file size $local_filename] + for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} { + set len [expr {$size - $offset}] + if {[expr {$len > $rtl8710_flasher_buffer_size}]} { + set len $rtl8710_flasher_buffer_size + } + set flash_offset [expr {$loc + $offset}] + echo "read offset $flash_offset" + rtl8710_flasher_load_block $local_filename $offset $len + echo "verify offset $flash_offset" + rtl8710_flasher_verify_block $flash_offset $len + } +} + +proc rtl8710_flash_auto_erase {on} { + global rtl8710_flasher_auto_erase + if {[expr {$on != 0}]} { + set rtl8710_flasher_auto_erase 1 + echo "auto erase on" + } else { + set rtl8710_flasher_auto_erase 0 + echo "auto erase off" + } +} + +proc rtl8710_flash_auto_verify {on} { + global rtl8710_flasher_auto_verify + if {[expr {$on != 0}]} { + set rtl8710_flasher_auto_verify 1 + echo "auto verify on" + } else { + set rtl8710_flasher_auto_verify 0 + echo "auto verify off" + } +} + +proc rtl8710_reboot {} { + mww 0xE000ED0C 0x05FA0007 +} + diff --git a/lib/cpu/rtl8710/rtl8710_gpio.h b/lib/cpu/rtl8710/rtl8710_gpio.h new file mode 100644 index 0000000..8f92fd1 --- /dev/null +++ b/lib/cpu/rtl8710/rtl8710_gpio.h @@ -0,0 +1,37 @@ +#ifndef _RTL8710_GPIO_H_ +#define _RTL8710_GPIO_H_ + +#include + +typedef struct{ + volatile uint32_t SWPORTA_DR; + volatile uint32_t SWPORTA_DDR; + volatile uint32_t SWPORTA_CTRL; + volatile uint32_t SWPORTB_DR; + volatile uint32_t SWPORTB_DDR; + volatile uint32_t SWPORTB_CTRL; + volatile uint32_t SWPORTC_DR; + volatile uint32_t SWPORTC_DDR; + volatile uint32_t SWPORTC_CTRL; + uint32_t RESERVED1[3]; + volatile uint32_t INTEN; + volatile uint32_t INTMASK; + volatile uint32_t INTTYPE_LEVEL; + volatile uint32_t INT_POLARITY; + volatile uint32_t INTSTATUS; + volatile uint32_t RAW_INTSTATUS; + volatile uint32_t DEBOUNCE; + volatile uint32_t PORTA_EOI; + volatile uint32_t EXT_PORTA; + volatile uint32_t EXT_PORTB; + volatile uint32_t EXT_PORTC; + uint32_t RESERVED2[1]; + volatile uint32_t LS_SYNC; +}__attribute__((packed)) GPIO_TypeDef; + +#define GPIO ((GPIO_TypeDef *)0x40001000) + +#define GPIO_PORTA_GC4 (((uint32_t)1) << 8) + +#endif + diff --git a/lib/cpu/rtl8710/rtl8710_int.h b/lib/cpu/rtl8710/rtl8710_int.h new file mode 100644 index 0000000..8ec2b8e --- /dev/null +++ b/lib/cpu/rtl8710/rtl8710_int.h @@ -0,0 +1,53 @@ +#ifndef _RTL8710_INT_H_ +#define _RTL8710_INT_H_ + +#define SYSTEM_ON_INT 0 +#define WDG_INT 1 +#define TIMER0_INT 2 +#define TIMER1_INT 3 +#define I2C3_INT 4 +#define TIMER2_7_INT 5 +#define SPI0_INT 6 +#define GPIO_INT 7 +#define UART0_INT 8 +#define SPI_FLASH_INT 9 +#define USB_OTG_INT 10 +#define SDIO_HOST_INT 11 +#define SDIO_DEVICE_INT 12 +#define I2S0_PCM0_INT 13 +#define I2S1_PCM1_INT 14 +#define WL_DMA_INT 15 +#define WL_PROTOCOL_INT 16 +#define CRYPTO_INT 17 +#define GMAC_INT 18 +#define PERIPHERAL_INT 19 +#define GDMA0_CHANNEL0_INT 20 +#define GDMA0_CHANNEL1_INT 21 +#define GDMA0_CHANNEL2_INT 22 +#define GDMA0_CHANNEL3_INT 23 +#define GDMA0_CHANNEL4_INT 24 +#define GDMA0_CHANNEL5_INT 25 +#define GDMA1_CHANNEL0_INT 26 +#define GDMA1_CHANNEL1_INT 27 +#define GDMA1_CHANNEL2_INT 28 +#define GDMA1_CHANNEL3_INT 29 +#define GDMA1_CHANNEL4_INT 30 +#define GDMA1_CHANNEL5_INT 31 +#define I2C0_INT 64 +#define I2C1_INT 65 +#define I2C2_INT 66 +#define SPI1_INT 72 +#define SPI2_INT 73 +#define UART1_INT 80 +#define UART2_INT 81 +#define LOG_UART_INT 88 +#define ADC_INT 89 +#define DAC0_INT 91 +#define DAC1_INT 92 +#define LP_EXTENSION_INT 93 +#define PTA_TRX_INT 95 +#define RXI300_INT 96 +#define NFC_INT 97 + +#endif + diff --git a/lib/cpu/rtl8710/rtl8710_log_uart.h b/lib/cpu/rtl8710/rtl8710_log_uart.h new file mode 100644 index 0000000..8147d9b --- /dev/null +++ b/lib/cpu/rtl8710/rtl8710_log_uart.h @@ -0,0 +1,76 @@ +#ifndef _RTL8710_LOG_UART_H_ +#define _RTL8710_LOG_UART_H_ + +#include + +typedef struct{ + union{ + volatile uint32_t RBR; + volatile uint32_t THR; + volatile uint32_t DLL; + volatile uint32_t RBR_THR_DLL; + }; + union{ + volatile uint32_t IER; + volatile uint32_t DLH; + volatile uint32_t IER_DLH; + }; + union{ + volatile uint32_t IIR; + volatile uint32_t FCR; + volatile uint32_t IIR_FCR; + }; + volatile uint32_t LCR; + volatile uint32_t MCR; + volatile uint32_t LSR; + volatile uint32_t MSR; + uint32_t RESERVED1[24]; + volatile uint32_t USR; +}__attribute__((packed)) LOG_UART_TypeDef; + +#define LOG_UART ((LOG_UART_TypeDef *)0x40003000) + +// LOG_UART_IER +#define LOG_UART_IER_ERBFI (((uint32_t)0x01) << 0) +#define LOG_UART_IER_ETBEI (((uint32_t)0x01) << 1) +#define LOG_UART_IER_ELSI (((uint32_t)0x01) << 2) +#define LOG_UART_IER_EDSSI (((uint32_t)0x01) << 3) + +// LOG_UART_FCR +#define LOG_UART_FCR_FIFOE (((uint32_t)0x01) << 0) +#define LOG_UART_FCR_RFIFOR (((uint32_t)0x01) << 1) +#define LOG_UART_FCR_XFIFOR (((uint32_t)0x01) << 2) +#define LOG_UART_FCR_DMAM (((uint32_t)0x01) << 3) +#define LOG_UART_FCR_TET (((uint32_t)0x03) << 4) +#define LOG_UART_FCR_RT (((uint32_t)0x03) << 6) + +// LOG_UART_LCR +#define LOG_UART_LCR_DLS (((uint32_t)0x03) << 0) +#define LOG_UART_LCR_STOP (((uint32_t)0x01) << 2) +#define LOG_UART_LCR_PEN (((uint32_t)0x01) << 3) +#define LOG_UART_LCR_EPS (((uint32_t)0x01) << 4) +#define LOG_UART_LCR_STICK_PAR (((uint32_t)0x01) << 5) +#define LOG_UART_LCR_BC (((uint32_t)0x01) << 6) +#define LOG_UART_LCR_DLAB (((uint32_t)0x01) << 7) + +// LOG_UART_MCR +#define LOG_UART_MCR_DTR (((uint32_t)0x01) << 0) +#define LOG_UART_MCR_RTS (((uint32_t)0x01) << 1) +#define LOG_UART_MCR_OUT1 (((uint32_t)0x01) << 2) +#define LOG_UART_MCR_OUT2 (((uint32_t)0x01) << 3) +#define LOG_UART_MCR_LOOPBACK (((uint32_t)0x01) << 4) +#define LOG_UART_MCR_AFCE (((uint32_t)0x01) << 5) + +// LOG_UART_LSR +#define LOG_UART_LSR_DR (((uint32_t)0x01) << 0) +#define LOG_UART_LSR_OE (((uint32_t)0x01) << 1) +#define LOG_UART_LSR_PE (((uint32_t)0x01) << 2) +#define LOG_UART_LSR_FE (((uint32_t)0x01) << 3) +#define LOG_UART_LSR_BI (((uint32_t)0x01) << 4) +#define LOG_UART_LSR_THRE (((uint32_t)0x01) << 5) +#define LOG_UART_LSR_TEMT (((uint32_t)0x01) << 6) +#define LOG_UART_LSR_RFE (((uint32_t)0x01) << 7) +#define LOG_UART_LSR_ADDR_RCVD (((uint32_t)0x01) << 8) + +#endif + diff --git a/lib/cpu/rtl8710/rtl8710_peri_on.h b/lib/cpu/rtl8710/rtl8710_peri_on.h new file mode 100644 index 0000000..3152e4b --- /dev/null +++ b/lib/cpu/rtl8710/rtl8710_peri_on.h @@ -0,0 +1,128 @@ +#ifndef _RTL8710_PERI_ON_H_ +#define _RTL8710_PERI_ON_H_ + +#include + +typedef struct{ + volatile uint32_t PEON_PWR_CTRL; // 0x0200 + volatile uint32_t PON_ISO_CTRL; // 0x0204 + uint32_t RESERVED1[2]; + volatile uint32_t SOC_FUNC_EN; // 0x0210 + volatile uint32_t SOC_HCI_COM_FUNC_EN; // 0x0214 + volatile uint32_t SOC_PERI_FUNC0_EN; // 0x0218 + volatile uint32_t SOC_PERI_FUNC1_EN; // 0x021C + volatile uint32_t SOC_PERI_DB_FUNC0_EN; // 0x0220 + uint32_t RESERVED2[3]; + volatile uint32_t PESOC_CLK_CTRL; // 0x0230 + volatile uint32_t PESOC_PERI_CLK_CTRL0; // 0x0234 + volatile uint32_t PESOC_PERI_CLK_CTRL1; // 0x0238 + volatile uint32_t PESOC_CLK_CTRL3; // 0x023C + volatile uint32_t PESOC_HCI_CLK_CTRL0; // 0x0240 + volatile uint32_t PESOC_COM_CLK_CTRL1; // 0x0244 + volatile uint32_t PESOC_HW_ENG_CLK_CTRL; // 0x0248 + uint32_t RESERVED3[1]; + volatile uint32_t PESOC_CLK_SEL; // 0x0250 + uint32_t RESERVED4[6]; + volatile uint32_t SYS_ANACK_CAL_CTRL; // 0x026C + volatile uint32_t OSC32K_CTRL; // 0x0270 + volatile uint32_t OSC32K_REG_CTRL0; // 0x0274 + volatile uint32_t OSC32K_REG_CTRL1; // 0x0278 + volatile uint32_t THERMAL_METER_CTRL; // 0x027C + volatile uint32_t UART_MUX_CTRL; // 0x0280 + volatile uint32_t SPI_MUX_CTRL; // 0x0284 + volatile uint32_t I2C_MUX_CTRL; // 0x0288 + volatile uint32_t I2S_MUX_CTRL; // 0x028C + uint32_t RESERVED5[4]; + volatile uint32_t HCI_PINMUX_CTRL; // 0x02A0 + volatile uint32_t WL_PINMUX_CTRL; // 0x02A4 + volatile uint32_t BT_PINMUX_CTRL; // 0x02A8 + volatile uint32_t PWM_PINMUX_CTRL; // 0x02AC + uint32_t RESERVED6[4]; + volatile uint32_t CPU_PERIPHERAL_CTRL; // 0x02C0 + uint32_t RESERVED7[7]; + volatile uint32_t HCI_CTRL_STATUS_0; // 0x02E0 + volatile uint32_t HCI_CTRL_STATUS_1; // 0x02E4 + uint32_t RESERVED8[6]; + volatile uint32_t PESOC_MEM_CTRL; // 0x0300 + volatile uint32_t PESOC_SOC_CTRL; // 0x0304 + volatile uint32_t PESOC_PERI_CTRL; // 0x0308 + uint32_t RESERVED9[5]; + volatile uint32_t GPIO_SHTDN_CTRL; // 0x0320 + volatile uint32_t GPIO_DRIVING_CTRL; // 0x0324 + uint32_t RESERVED10[2]; + volatile uint32_t GPIO_PULL_CTRL0; // 0x0330 + volatile uint32_t GPIO_PULL_CTRL1; // 0x0334 + volatile uint32_t GPIO_PULL_CTRL2; // 0x0338 + volatile uint32_t GPIO_PULL_CTRL3; // 0x033C + volatile uint32_t GPIO_PULL_CTRL4; // 0x0340 + volatile uint32_t GPIO_PULL_CTRL5; // 0x0344 + volatile uint32_t GPIO_PULL_CTRL6; // 0x0348 + uint32_t RESERVED11[5]; + volatile uint32_t PERI_PWM0_CTRL; // 0x0360 + volatile uint32_t PERI_PWM1_CTRL; // 0x0364 + volatile uint32_t PERI_PWM2_CTRL; // 0x0368 + volatile uint32_t PERI_PWM3_CTRL; // 0x036C + volatile uint32_t PERI_TIM_EVT_CTRL; // 0x0370 + volatile uint32_t PERI_EGTIM_CTRL; // 0x0374 + uint32_t RESERVED12[30]; + volatile uint32_t PEON_CFG; // 0x03F0 + volatile uint32_t PEON_STATUS; // 0x03F4 +}__attribute__((packed)) PERI_ON_TypeDef; + +#define PERI_ON ((PERI_ON_TypeDef *)0x40000200) + +// PERI_ON_SOC_FUNC_EN +#define PERI_ON_SOC_FUNC_EN_FUN (((uint32_t)0x01) << 0) +#define PERI_ON_SOC_FUNC_EN_OCP (((uint32_t)0x01) << 1) +#define PERI_ON_SOC_FUNC_EN_LXBUS (((uint32_t)0x01) << 2) +#define PERI_ON_SOC_FUNC_EN_FLASH (((uint32_t)0x01) << 4) +#define PERI_ON_SOC_FUNC_EN_MEM_CTRL (((uint32_t)0x01) << 6) +#define PERI_ON_SOC_FUNC_EN_CPU (((uint32_t)0x01) << 8) +#define PERI_ON_SOC_FUNC_EN_LOG_UART (((uint32_t)0x01) << 12) +#define PERI_ON_SOC_FUNC_EN_GDMA0 (((uint32_t)0x01) << 13) +#define PERI_ON_SOC_FUNC_EN_GDMA1 (((uint32_t)0x01) << 14) +#define PERI_ON_SOC_FUNC_EN_GTIMER (((uint32_t)0x01) << 16) +#define PERI_ON_SOC_FUNC_EN_SECURITY_ENGINE (((uint32_t)0x01) << 20) + +// PERI_ON_SOC_PERI_FUNC1_EN +#define PERI_ON_SOC_PERI_FUNC1_EN_ADC0 (((uint32_t)0x01) << 0) +#define PERI_ON_SOC_PERI_FUNC1_EN_DAC0 (((uint32_t)0x01) << 4) +#define PERI_ON_SOC_PERI_FUNC1_EN_DAC1 (((uint32_t)0x01) << 5) +#define PERI_ON_SOC_PERI_FUNC1_EN_GPIO (((uint32_t)0x01) << 8) + +// PERI_ON_PESOC_CLK_CTRL +#define PERI_ON_CLK_CTRL_CKE_OCP (((uint32_t)0x01) << 0) +#define PERI_ON_CLK_CTRL_CKE_PLFM (((uint32_t)0x01) << 2) +#define PERI_ON_CLK_CTRL_ACTCK_TRACE_EN (((uint32_t)0x01) << 4) +#define PERI_ON_CLK_CTRL_SLPCK_TRACE_EN (((uint32_t)0x01) << 5) +#define PERI_ON_CLK_CTRL_ACTCK_VENDOR_REG_EN (((uint32_t)0x01) << 6) +#define PERI_ON_CLK_CTRL_SLPCK_VENDOR_REG_EN (((uint32_t)0x01) << 7) +#define PERI_ON_CLK_CTRL_ACTCK_FLASH_EN (((uint32_t)0x01) << 8) +#define PERI_ON_CLK_CTRL_SLPCK_FLASH_EN (((uint32_t)0x01) << 9) +#define PERI_ON_CLK_CTRL_ACTCK_SDR_EN (((uint32_t)0x01) << 10) +#define PERI_ON_CLK_CTRL_SLPCK_SDR_EN (((uint32_t)0x01) << 11) +#define PERI_ON_CLK_CTRL_ACTCK_LOG_UART_EN (((uint32_t)0x01) << 12) +#define PERI_ON_CLK_CTRL_SLPCK_LOG_UART_EN (((uint32_t)0x01) << 13) +#define PERI_ON_CLK_CTRL_ACTCK_TIMER_EN (((uint32_t)0x01) << 14) +#define PERI_ON_CLK_CTRL_SLPCK_TIMER_EN (((uint32_t)0x01) << 15) +#define PERI_ON_CLK_CTRL_ACTCK_GDMA0_EN (((uint32_t)0x01) << 16) +#define PERI_ON_CLK_CTRL_SLPCK_GDMA0_EN (((uint32_t)0x01) << 17) +#define PERI_ON_CLK_CTRL_ACTCK_GDMA1_EN (((uint32_t)0x01) << 18) +#define PERI_ON_CLK_CTRL_SLPCK_GDMA1_EN (((uint32_t)0x01) << 19) +#define PERI_ON_CLK_CTRL_ACTCK_GPIO_EN (((uint32_t)0x01) << 24) +#define PERI_ON_CLK_CTRL_SLPCK_GPIO_EN (((uint32_t)0x01) << 25) +#define PERI_ON_CLK_CTRL_ACTCK_BTCMD_EN (((uint32_t)0x01) << 28) +#define PERI_ON_CLK_CTRL_SLPCK_BTCMD_EN (((uint32_t)0x01) << 29) + +// PERI_ON_CPU_PERIPHERAL_CTRL +#define PERI_ON_CPU_PERIPHERAL_CTRL_SPI_FLASH_PIN_EN (((uint32_t)0x01) << 0) +#define PERI_ON_CPU_PERIPHERAL_CTRL_SPI_FLASH_PIN_SEL (((uint32_t)0x03) << 1) +#define PERI_ON_CPU_PERIPHERAL_CTRL_SDR_PIN_EN (((uint32_t)0x01) << 4) +#define PERI_ON_CPU_PERIPHERAL_CTRL_SWD_PIN_EN (((uint32_t)0x01) << 16) +#define PERI_ON_CPU_PERIPHERAL_CTRL_TRACE_PIN_EN (((uint32_t)0x01) << 17) +#define PERI_ON_CPU_PERIPHERAL_CTRL_LOG_UART_PIN_EN (((uint32_t)0x01) << 20) +#define PERI_ON_CPU_PERIPHERAL_CTRL_LOG_UART_IR_EN (((uint32_t)0x01) << 21) +#define PERI_ON_CPU_PERIPHERAL_CTRL_LOG_UART_PIN_SEL (((uint32_t)0x03) << 22) + +#endif + diff --git a/lib/cpu/rtl8710/rtl8710_spi.h b/lib/cpu/rtl8710/rtl8710_spi.h new file mode 100644 index 0000000..9ba24b5 --- /dev/null +++ b/lib/cpu/rtl8710/rtl8710_spi.h @@ -0,0 +1,100 @@ +#ifndef _RTL8710_SPI_H_ +#define _RTL8710_SPI_H_ + +#include + +typedef struct{ + volatile uint32_t CTRLR0; + volatile uint32_t CTRLR1; + volatile uint32_t SSIENR; + volatile uint32_t MWCR; + volatile uint32_t SER; + volatile uint32_t BAUDR; + volatile uint32_t TXFTLR; + volatile uint32_t RXFTLR; + volatile uint32_t TXFLR; + volatile uint32_t RXFLR; + volatile uint32_t SR; + volatile uint32_t IMR; + volatile uint32_t ISR; + volatile uint32_t RISR; + volatile uint32_t TXOICR; + volatile uint32_t RXOICR; + volatile uint32_t RXUICR; + volatile uint32_t MSTICR; + volatile uint32_t ICR; + volatile uint32_t DMACR; + volatile uint32_t DMATDLR; + volatile uint32_t DMARDLR; + volatile uint32_t IDR; + volatile uint32_t SSI_COMP_VERSION; + union{ + struct{ + union{ + volatile uint8_t DR; + volatile uint8_t DR8; + }; + uint8_t RESERVED1[3]; + }__attribute__((packed)); + struct{ + volatile uint16_t DR16; + uint16_t RESERVED2[1]; + }__attribute__((packed)); + volatile uint32_t DR32; + }; + uint32_t RESERVED3[31]; + volatile uint32_t READ_FAST_SINGLE; + volatile uint32_t READ_DUAL_DATA; + volatile uint32_t READ_DUAL_ADDR_DATA; + volatile uint32_t READ_QUAD_DATA; + union{ + volatile uint32_t READ_QUAD_ADDR_DATA; + volatile uint32_t RX_SAMPLE_DLY; + }; + volatile uint32_t WRITE_SIGNLE; + volatile uint32_t WRITE_DUAL_DATA; + volatile uint32_t WRITE_DUAL_ADDR_DATA; + volatile uint32_t WRITE_QUAD_DATA; + volatile uint32_t WRITE_QUAD_ADDR_DATA; + volatile uint32_t WRITE_ENABLE; + volatile uint32_t READ_STATUS; + volatile uint32_t CTRLR2; + volatile uint32_t FBAUDR; + volatile uint32_t ADDR_LENGTH; + volatile uint32_t AUTO_LENGTH; + volatile uint32_t VALID_CMD; + volatile uint32_t FLASE_SIZE; + volatile uint32_t FLUSH_FIFO; +}__attribute__((packed)) SPI_TypeDef; + +#define SPI_FLASH ((SPI_TypeDef *)0x40006000) + +// SPI_CTRLR0 +#define SPI_CTRLR0_FRF (((uint32_t)0x03) << 4) +#define SPI_CTRLR0_SCPH (((uint32_t)0x01) << 6) +#define SPI_CTRLR0_SCPOL (((uint32_t)0x01) << 7) +#define SPI_CTRLR0_TMOD (((uint32_t)0x03) << 8) +#define SPI_CTRLR0_SLV_OE (((uint32_t)0x01) << 10) +#define SPI_CTRLR0_SRL (((uint32_t)0x01) << 11) +#define SPI_CTRLR0_CFS (((uint32_t)0x0F) << 12) +#define SPI_CTRLR0_ADDR_CH (((uint32_t)0x03) << 16) +#define SPI_CTRLR0_DATA_CH (((uint32_t)0x03) << 18) +#define SPI_CTRLR0_CMD_CH (((uint32_t)0x03) << 20) +#define SPI_CTRLR0_FAST_RD (((uint32_t)0x01) << 22) +#define SPI_CTRLR0_SHIFT_CK_MTIMES (((uint32_t)0x1F) << 23) + +// SPI_SER +#define SPI_SER_SS0 (((uint32_t)0x01) << 0) +#define SPI_SER_SS1 (((uint32_t)0x01) << 1) +#define SPI_SER_SS2 (((uint32_t)0x01) << 2) + +// SPI_SR +#define SPI_SR_SSI (((uint32_t)0x01) << 0) +#define SPI_SR_TFNF (((uint32_t)0x01) << 1) +#define SPI_SR_TFE (((uint32_t)0x01) << 2) +#define SPI_SR_RFNE (((uint32_t)0x01) << 3) +#define SPI_SR_RFF (((uint32_t)0x01) << 4) +#define SPI_SR_TXE (((uint32_t)0x01) << 5) + +#endif + diff --git a/lib/cpu/rtl8710/rtl8710_sys.h b/lib/cpu/rtl8710/rtl8710_sys.h new file mode 100644 index 0000000..83eb229 --- /dev/null +++ b/lib/cpu/rtl8710/rtl8710_sys.h @@ -0,0 +1,106 @@ +#ifndef _RTL8710_SYS_H_ +#define _RTL8710_SYS_H_ + +#include + +// ~/programming/rtl8710/doc/registers/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h + +typedef struct{ + volatile uint16_t PWR_CTRL; // 0x0000 + volatile uint16_t ISO_CTRL; // 0x0002 + uint32_t RESERVED1[1]; + volatile uint32_t FUNC_EN; // 0x0008 + uint32_t RESERVED2[1]; + volatile uint32_t CLK_CTRL0; // 0x0010 + volatile uint32_t CLK_CTRL1; // 0x0014 + uint32_t RESERVED3[2]; + volatile uint32_t EFUSE_SYSCFG0; // 0x0020 + volatile uint32_t EFUSE_SYSCFG1; // 0x0024 + volatile uint32_t EFUSE_SYSCFG2; // 0x0028 + volatile uint32_t EFUSE_SYSCFG3; // 0x002C + volatile uint32_t EFUSE_SYSCFG4; // 0x0030 + volatile uint32_t EFUSE_SYSCFG5; // 0x0034 + volatile uint32_t EFUSE_SYSCFG6; // 0x0038 + volatile uint32_t EFUSE_SYSCFG7; // 0x003C + volatile uint32_t REGU_CTRL0; // 0x0040 + uint32_t RESERVED4[1]; + volatile uint32_t SWR_CTRL0; // 0x0048 + volatile uint32_t SWR_CTRL1; // 0x004C + uint32_t RESERVED5[4]; + volatile uint32_t XTAL_CTRL0; // 0x0060 + volatile uint32_t XTAL_CTRL1; // 0x0064 + uint32_t RESERVED6[2]; + volatile uint32_t SYSPLL_CTRL0; // 0x0070 + volatile uint32_t SYSPLL_CTRL1; // 0x0074 + volatile uint32_t SYSPLL_CTRL2; // 0x0078 + uint32_t RESERVED7[5]; + volatile uint32_t ANA_TIM_CTRL; // 0x0090 + volatile uint32_t DSLP_TIM_CTRL; // 0x0094 + volatile uint32_t DSLP_TIM_CAL_CTRL; // 0x0098 + uint32_t RESERVED8[1]; + volatile uint32_t DEBUG_CTRL; // 0x00A0 + volatile uint32_t PINMUX_CTRL; // 0x00A4 + volatile uint32_t GPIO_DSTBY_WAKE_CTRL0; // 0x00A8 + volatile uint32_t GPIO_DSTBY_WAKE_CTRL1; // 0x00AC + uint32_t RESERVED9[3]; + volatile uint32_t DEBUG_REG; // 0x00BC + uint32_t RESERVED10[8]; + volatile uint32_t EEPROM_CTRL0; // 0x00E0 + volatile uint32_t EEPROM_CTRL1; // 0x00E4 + volatile uint32_t EFUSE_CTRL; // 0x00E8 + volatile uint32_t EFUSE_TEST; // 0x00EC + volatile uint32_t DSTBY_INFO0; // 0x00F0 + volatile uint32_t DSTBY_INFO1; // 0x00F4 + volatile uint32_t DSTBY_INFO2; // 0x00F8 + volatile uint32_t DSTBY_INFO3; // 0x00FC + volatile uint32_t SLP_WAKE_EVENT_MSK0; // 0x0100 + volatile uint32_t SLP_WAKE_EVENT_MSK1; // 0x0104 + volatile uint32_t SLP_WAKE_EVENT_STATUS0; // 0x0108 + volatile uint32_t SLP_WAKE_EVENT_STATUS1; // 0x010C + volatile uint32_t SNF_WAKE_EVENT_MSK0; // 0x0110 + volatile uint32_t SNF_WAKE_EVENT_STATUS; // 0x0114 + volatile uint32_t PWRMGT_CTRL; // 0x0118 + uint32_t RESERVED11[1]; + volatile uint32_t PWRMGT_OPTION; // 0x0120 + volatile uint32_t PWRMGT_OPTION_EXT; // 0x0124 + uint32_t RESERVED12[2]; + volatile uint32_t DSLP_WEVENT; // 0x0130 + volatile uint32_t PERI_MONITOR; // 0x0134 + uint32_t RESERVED13[46]; + volatile uint32_t SYSTEM_CFG0; // 0x01F0 + volatile uint32_t SYSTEM_CFG1; // 0x01F4 + volatile uint32_t SYSTEM_CFG2; // 0x01F8 +}__attribute__((packed)) SYS_TypeDef; + +#define SYS ((SYS_TypeDef *)0x40000000) + +// SYS_PWR_CTRL +#define SYS_PWR_CTRL_PEON_EN (((uint16_t)0x01) << 0) +#define SYS_PWR_CTRL_RET_MEM_EN (((uint16_t)0x01) << 1) +#define SYS_PWR_CTRL_SOC_EN (((uint16_t)0x01) << 2) + +// SYS_ISO_CTRL +#define SYS_ISO_CTRL_PEON (((uint16_t)0x01) << 0) +#define SYS_ISO_CTRL_RET_MEM (((uint16_t)0x01) << 1) +#define SYS_ISO_CTRL_SOC (((uint16_t)0x01) << 2) +#define SYS_ISO_CTRL_SYSPLL (((uint16_t)0x01) << 7) + +// SYS_FUNC_EN +#define SYS_FUNC_EN_FEN_EELDR (((uint32_t)0x01) << 0) +#define SYS_FUNC_EN_SOC_SYSPEON_EN (((uint32_t)0x01) << 4) +#define SYS_FUNC_EN_FEN_SIC (((uint32_t)0x01) << 24) +#define SYS_FUNC_EN_FEN_SIC_MST (((uint32_t)0x01) << 25) +#define SYS_FUNC_EN_PWRON_TRAP_SHTDN_N (((uint32_t)0x01) << 30) +#define SYS_FUNC_EN_AMACRO_EN (((uint32_t)0x01) << 31) + +// SYS_CLK_CTRL0 +#define SYS_CLK_CTRL0_CK_SYSREG_EN (((uint32_t)0x01) << 0) +#define SYS_CLK_CTRL0_CK_EELDR_EN (((uint32_t)0x01) << 1) +#define SYS_CLK_CTRL0_SOC_OCP_IOBUS_CK_EN (((uint32_t)0x01) << 2) + +// SYS_CLK_CTRL1 +#define SYS_CLK_CTRL1_PESOC_EELDR_CK_SEL (((uint32_t)0x01) << 0) +#define SYS_CLK_CTRL1_PESOC_OCP_CPU_CK_SEL (((uint32_t)0x07) << 4) + +#endif + diff --git a/lib/cpu/rtl8710/rtl8710_timer.h b/lib/cpu/rtl8710/rtl8710_timer.h new file mode 100644 index 0000000..a4f7ef9 --- /dev/null +++ b/lib/cpu/rtl8710/rtl8710_timer.h @@ -0,0 +1,35 @@ +#ifndef _RTL8710_TIMER_H_ +#define _RTL8710_TIMER_H_ + +#include + +typedef struct{ + volatile uint32_t TIM0_LOAD_COUNT; + volatile uint32_t TIM0_CURRENT_VALUE; + volatile uint32_t TIM0_CONTROL; + volatile uint32_t TIM0_EOI; + volatile uint32_t TIM0_IS; + volatile uint32_t TIM1_LOAD_COUNT; + volatile uint32_t TIM1_CURRENT_VALUE; + volatile uint32_t TIM1_CONTROL; + volatile uint32_t TIM1_EOI; + volatile uint32_t TIM1_IS; + uint32_t RESERVED1[30]; + volatile uint32_t TIMS_IS; + volatile uint32_t TIMS_EOI; + volatile uint32_t TIMS_RAW_IS; + volatile uint32_t TIMS_COMP_VERSION; + volatile uint32_t TIM0_LOAD_COUNT2; + volatile uint32_t TIM1_LOAD_COUNT2; +}__attribute__((packed)) TIMER_TypeDef; + +#define TIMER ((TIMER_TypeDef *)0x40002000) + +// TIMER_CONTROL +#define TIMER_CONTROL_ENABLE (((uint32_t)0x01) << 0) +#define TIMER_CONTROL_MODE (((uint32_t)0x01) << 1) +#define TIMER_CONTROL_IM (((uint32_t)0x01) << 2) +#define TIMER_CONTROL_PWM (((uint32_t)0x01) << 3) + +#endif + diff --git a/lib/fwlib/hal_adc.h b/lib/fwlib/hal_adc.h new file mode 100644 index 0000000..a509dc3 --- /dev/null +++ b/lib/fwlib/hal_adc.h @@ -0,0 +1,319 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_ADC_H_ +#define _HAL_ADC_H_ + +#include "rtl8195a.h" +#include "rtl8195a_adc.h" +#include "hal_gdma.h" + +//================ ADC Configuration ========================= +#define ADC_INTR_OP_TYPE 1 +#define ADC_DMA_OP_TYPE 1 + +// ADC SAL management macros +#define SAL_ADC_USER_CB_NUM (sizeof(SAL_ADC_USER_CB) / sizeof(PSAL_ADC_USERCB_ADPT)) + +// ADC used module. +// Please set the ADC module flag to 1 to enable the related +#define ADC0_USED 1 +#define ADC1_USED 1 +#define ADC2_USED 1 +#define ADC3_USED 1 + + +//================ Debug MSG Definition ======================= +#define ADC_PREFIX "RTL8195A[adc]: " +#define ADC_PREFIX_LVL " [ADC_DBG]: " + +typedef enum _ADC_DBG_LVL_ { + HAL_ADC_LVL = 0x01, + SAL_ADC_LVL = 0x02, + VERI_ADC_LVL = 0x04, +}ADC_DBG_LVL,*PADC_DBG_LVL; + +#ifdef CONFIG_DEBUG_LOG +#ifdef CONFIG_DEBUG_LOG_ADC_HAL + + #define DBG_8195A_ADC(...) do{ \ + _DbgDump("\r"ADC_PREFIX __VA_ARGS__);\ + }while(0) + + + #define ADCDBGLVL 0xFF + #define DBG_8195A_ADC_LVL(LVL,...) do{\ + if (LVL&ADCDBGLVL){\ + _DbgDump("\r"ADC_PREFIX_LVL __VA_ARGS__);\ + }\ + }while(0) +#else + #define DBG_ADC_LOG_PERD 100 + #define DBG_8195A_ADC(...) + #define DBG_8195A_ADC_LVL(...) +#endif +#endif + + +//================ ADC HAL Related Enumeration ================== +// ADC Module Selection +typedef enum _ADC_MODULE_SEL_ { + ADC0_SEL = 0x0, + ADC1_SEL = 0x1, + ADC2_SEL = 0x2, + ADC3_SEL = 0x3, +}ADC_MODULE_SEL,*PADC_MODULE_SEL; + +// ADC module status +typedef enum _ADC_MODULE_STATUS_ { + ADC_DISABLE = 0x0, + ADC_ENABLE = 0x1, +}ADC_MODULE_STATUS, *PADC_MODULE_STATUS; + +// ADC Data Endian +typedef enum _ADC_DATA_ENDIAN_ { + ADC_DATA_ENDIAN_LITTLE = 0x0, + ADC_DATA_ENDIAN_BIG = 0x1, +}ADC_DATA_ENDIAN,*PADC_DATA_ENDIAN; + +// ADC Debug Select +typedef enum _ADC_DEBUG_SEL_ { + ADC_DBG_SEL_DISABLE = 0x0, + ADC_DBG_SEL_ENABLE = 0x1, +}ADC_DEBUG_SEL,*PADC_DEBUG_SEL; + +typedef enum _ADC_COMPARE_SET_ { + ADC_COMP_SMALLER_THAN = 0x0, + ADC_COMP_GREATER_THAN = 0x1, +}ADC_COMPARE_SET, *PADC_COMPARE_SET; + +// ADC feature status +typedef enum _ADC_FEATURE_STATUS_{ + ADC_FEATURE_DISABLED = 0, + ADC_FEATURE_ENABLED = 1, +}ADC_FEATURE_STATUS,*PADC_FEATURE_STATUS; + +// ADC operation type +typedef enum _ADC_OP_TYPE_ { + ADC_RDREG_TYPE = 0x0, + ADC_DMA_TYPE = 0x1, + ADC_INTR_TYPE = 0x2, +}ADC_OP_TYPE, *PADC_OP_TYPE; + +// ADC device status +typedef enum _ADC_DEVICE_STATUS_ { + ADC_STS_UNINITIAL = 0x00, + ADC_STS_INITIALIZED = 0x01, + ADC_STS_IDLE = 0x02, + + ADC_STS_TX_READY = 0x03, + ADC_STS_TX_ING = 0x04, + + ADC_STS_RX_READY = 0x05, + ADC_STS_RX_ING = 0x06, + + ADC_STS_ERROR = 0x07, + ADC_STS_FULL = 0x08, +}ADC_DEVICE_STATUS, *PADC_DEVICE_STATUS; + +// ADC error type +typedef enum _ADC_ERR_TYPE_ { + ADC_ERR_FIFO_RD_ERROR = 0x40, //ADC FIFO read error +}ADC_ERR_TYPE, *PADC_ERR_TYPE; + +// ADC initial status +typedef enum _ADC_INITAIL_STATUS_ { + ADC0_INITED = 0x1, + ADC1_INITED = 0x2, + ADC2_INITED = 0x4, + ADC3_INITED = 0x8, +}ADC_INITAIL_STATUS, *PADC_INITAIL_STATUS; + + +//================ ADC HAL Data Structure ====================== +// ADC HAL initial data structure +typedef struct _HAL_ADC_INIT_DAT_ { + u8 ADCIdx; //ADC index used + u8 ADCEn; //ADC module enable + u8 ADCEndian; //ADC endian selection, + //but actually it's for 32-bit ADC data swap control + //1'b0: no swap, + //1'b1: swap the upper 16-bit and the lower 16-bit + u8 ADCBurstSz; //ADC DMA operation threshold + + u8 ADCCompOnly; //ADC compare mode only enable (without FIFO enable) + u8 ADCOneShotEn; //ADC one-shot mode enable + u8 ADCOverWREn; //ADC overwrite mode enable + u8 ADCOneShotTD; //ADC one shot mode threshold + + u16 ADCCompCtrl; //ADC compare mode control, + //1'b0:less than the compare threshold + //1'b1:greater than the compare threshod + u16 ADCCompTD; //ADC compare mode threshold + + u8 ADCDataRate; //ADC down sample data rate, + u8 ADCAudioEn; //ADC audio mode enable + u8 ADCEnManul; //ADC enable manually + u8 ADCDbgSel; + + u32 RSVD0; + + u32 *ADCData; //ADC data pointer + u32 ADCPWCtrl; //ADC0 power control + u32 ADCIntrMSK; //ADC Interrupt Mask + u32 ADCAnaParAd3; //ADC analog parameter 3 + u32 ADCInInput; //ADC Input is internal? +}HAL_ADC_INIT_DAT,*PHAL_ADC_INIT_DAT; + +// ADC HAL Operations +typedef struct _HAL_ADC_OP_ { + RTK_STATUS (*HalADCInit) (VOID *Data); //HAL ADC initialization + RTK_STATUS (*HalADCDeInit) (VOID *Data); //HAL ADC de-initialization + RTK_STATUS (*HalADCEnable) (VOID *Data); //HAL ADC de-initialization + u32 (*HalADCReceive) (VOID *Data); //HAL ADC receive + RTK_STATUS (*HalADCIntrCtrl) (VOID *Data); //HAL ADC interrupt control + u32 (*HalADCReadReg) (VOID *Data, u8 ADCReg);//HAL ADC read register +}HAL_ADC_OP, *PHAL_ADC_OP; + +// ADC user callback adapter +typedef struct _SAL_ADC_USERCB_ADPT_ { + VOID (*USERCB) (VOID *Data); + u32 USERData; +}SAL_ADC_USERCB_ADPT, *PSAL_ADC_USERCB_ADPT; + +// ADC user callback structure +typedef struct _SAL_ADC_USER_CB_ { + PSAL_ADC_USERCB_ADPT pTXCB; //ADC Transmit Callback + PSAL_ADC_USERCB_ADPT pTXCCB; //ADC Transmit Complete Callback + PSAL_ADC_USERCB_ADPT pRXCB; //ADC Receive Callback + PSAL_ADC_USERCB_ADPT pRXCCB; //ADC Receive Complete Callback + PSAL_ADC_USERCB_ADPT pRDREQCB; //ADC Read Request Callback + PSAL_ADC_USERCB_ADPT pERRCB; //ADC Error Callback + PSAL_ADC_USERCB_ADPT pDMATXCB; //ADC DMA Transmit Callback + PSAL_ADC_USERCB_ADPT pDMATXCCB; //ADC DMA Transmit Complete Callback + PSAL_ADC_USERCB_ADPT pDMARXCB; //ADC DMA Receive Callback + PSAL_ADC_USERCB_ADPT pDMARXCCB; //ADC DMA Receive Complete Callback +}SAL_ADC_USER_CB, *PSAL_ADC_USER_CB; + +// ADC Transmit Buffer +typedef struct _SAL_ADC_TRANSFER_BUF_ { + u32 DataLen; //ADC Transmfer Length + u32 *pDataBuf; //ADC Transfer Buffer Pointer + u32 RSVD; // +}SAL_ADC_TRANSFER_BUF,*PSAL_ADC_TRANSFER_BUF; + +typedef struct _SAL_ADC_DMA_USER_DEF_ { + + u8 TxDatSrcWdth; + u8 TxDatDstWdth; + u8 TxDatSrcBstSz; + u8 TxDatDstBstSz; + + u8 TxChNo; + u8 LlpCtrl; + u16 RSVD0; + + u32 MaxMultiBlk; + u32 pLlix; + u32 pBlockSizeList; +}SAL_ADC_DMA_USER_DEF, *PSAL_ADC_DMA_USER_DEF; + +// Software API Level ADC Handler +typedef struct _SAL_ADC_HND_ { + u8 DevNum; //ADC device number + u8 PinMux; //ADC pin mux seletion + u8 OpType; //ADC operation type selection + volatile u8 DevSts; //ADC device status + + u32 ADCExd; //ADC extended options: + //bit 0: example + //bit 31~bit 1: Reserved + u32 ErrType; // + u32 TimeOut; //ADC IO Timeout count + + PHAL_ADC_INIT_DAT pInitDat; //Pointer to ADC initial data struct + PSAL_ADC_TRANSFER_BUF pRXBuf; //Pointer to ADC TX buffer + PSAL_ADC_USER_CB pUserCB; //Pointer to ADC User Callback +}SAL_ADC_HND, *PSAL_ADC_HND; + +// ADC SAL handle private +typedef struct _SAL_ADC_HND_PRIV_ { + VOID **ppSalADCHnd; //Pointer to SAL_ADC_HND pointer + SAL_ADC_HND SalADCHndPriv; //Private SAL_ADC_HND +}SAL_ADC_HND_PRIV, *PSAL_ADC_HND_PRIV; + +//ADC SAL management adapter +typedef struct _SAL_ADC_MNGT_ADPT_ { + PSAL_ADC_HND_PRIV pSalHndPriv; //Pointer to SAL_ADC_HND + PHAL_ADC_INIT_DAT pHalInitDat; //Pointer to HAL ADC initial data( HAL_ADC_INIT_DAT ) + PHAL_ADC_OP pHalOp; //Pointer to HAL ADC operation( HAL_ADC_OP ) + VOID (*pHalOpInit)(VOID*);//Pointer to HAL ADC initialize function + + PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE ) + VOID (*pSalIrqFunc)(VOID*); //Used for SAL ADC interrupt function + + PSAL_ADC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA config + PHAL_GDMA_ADAPTER pHalGdmaAdp; + PHAL_GDMA_OP pHalGdmaOp; + PIRQ_HANDLE pIrqGdmaHnd; + VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL DAC initialize function + PSAL_ADC_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_ADC_USER_CB ) + VOID (*pSalDMAIrqFunc)(VOID*); //Used for SAL DAC interrupt function +}SAL_ADC_MNGT_ADPT, *PSAL_ADC_MNGT_ADPT; + + +//================ ADC HAL Function Prototype =================== +// ADC HAL inline function +// For checking I2C input index valid or not +static inline RTK_STATUS +RtkADCIdxChk( + IN u8 ADCIdx +) +{ +#if !ADC0_USED + if (ADCIdx == ADC0_SEL) + return _EXIT_FAILURE; +#endif + +#if !ADC1_USED + if (ADCIdx == ADC1_SEL) + return _EXIT_FAILURE; +#endif + +#if !ADC2_USED + if (ADCIdx == ADC2_SEL) + return _EXIT_FAILURE; +#endif + +#if !ADC3_USED + if (ADCIdx == ADC3_SEL) + return _EXIT_FAILURE; +#endif + + return _EXIT_SUCCESS; +} + +VOID HalADCOpInit(IN VOID *Data); +PSAL_ADC_HND RtkADCGetSalHnd(IN u8 DACIdx); +RTK_STATUS RtkADCFreeSalHnd(IN PSAL_ADC_HND pSalADCHND); +RTK_STATUS RtkADCLoadDefault(IN VOID *Data); +RTK_STATUS RtkADCInit(IN VOID *Data); +RTK_STATUS RtkADCDeInit(IN VOID *Data); +//RTK_STATUS RtkADCReceive(IN VOID *Data); +u32 RtkADCReceive(IN VOID *Data); +u32 RtkADCReceiveBuf(IN VOID *Data,IN u32 *pBuf); + +PSAL_ADC_MNGT_ADPT RtkADCGetMngtAdpt(IN u8 ADCIdx); +RTK_STATUS RtkADCFreeMngtAdpt(IN PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt); +VOID ADCISRHandle(IN VOID *Data); +VOID ADCGDMAISRHandle(IN VOID *Data); +HAL_Status RtkADCDisablePS(IN VOID *Data); +HAL_Status RtkADCEnablePS(IN VOID *Data); + +#endif diff --git a/lib/fwlib/hal_api.h b/lib/fwlib/hal_api.h new file mode 100644 index 0000000..c50b6e7 --- /dev/null +++ b/lib/fwlib/hal_api.h @@ -0,0 +1,126 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ +#ifndef _HAL_API_H_ +#define _HAL_API_H_ + +#include "basic_types.h" +#include "hal_irqn.h" + +#define HAL_READ32(base, addr) \ + rtk_le32_to_cpu(*((volatile u32*)(base + addr))) + +#define HAL_WRITE32(base, addr, value32) \ + ((*((volatile u32*)(base + addr))) = rtk_cpu_to_le32(value32)) + + +#define HAL_READ16(base, addr) \ + rtk_le16_to_cpu(*((volatile u16*)(base + addr))) + +#define HAL_WRITE16(base, addr, value) \ + ((*((volatile u16*)(base + addr))) = rtk_cpu_to_le16(value)) + + +#define HAL_READ8(base, addr) \ + (*((volatile u8*)(base + addr))) + +#define HAL_WRITE8(base, addr, value) \ + ((*((volatile u8*)(base + addr))) = value) + +#if 0 +// These "extern _LONG_CALL_" function declaration are for RAM code building only +// For ROM code building, thses code should be marked off +extern _LONG_CALL_ u8 +HalPinCtrlRtl8195A( + IN u32 Function, + IN u32 PinLocation, + IN BOOL Operation + ); + +extern _LONG_CALL_ VOID +HalSerialPutcRtl8195a( + IN u8 c + ); + +extern _LONG_CALL_ u8 +HalSerialGetcRtl8195a( + IN BOOL PullMode + ); + +extern _LONG_CALL_ u32 +HalSerialGetIsrEnRegRtl8195a(VOID); + +extern _LONG_CALL_ VOID +HalSerialSetIrqEnRegRtl8195a ( + IN u32 SetValue + ); + +extern _LONG_CALL_ VOID +VectorTableInitForOSRtl8195A( + IN VOID *PortSVC, + IN VOID *PortPendSVH, + IN VOID *PortSysTick + ); + +extern _LONG_CALL_ BOOL +VectorIrqRegisterRtl8195A( + IN PIRQ_HANDLE pIrqHandle + ); + +extern _LONG_CALL_ BOOL +VectorIrqUnRegisterRtl8195A( + IN PIRQ_HANDLE pIrqHandle + ); + +extern _LONG_CALL_ VOID +VectorIrqEnRtl8195A( + IN PIRQ_HANDLE pIrqHandle + ); + +extern _LONG_CALL_ VOID +VectorIrqDisRtl8195A( + IN PIRQ_HANDLE pIrqHandle + ); +#endif + +extern BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode); +extern VOID InitWDGIRQ(VOID); + +#define PinCtrl HalPinCtrlRtl8195A + +#define DiagPutChar HalSerialPutcRtl8195a +#define DiagGetChar HalSerialGetcRtl8195a +#define DiagGetIsrEnReg HalSerialGetIsrEnRegRtl8195a +#define DiagSetIsrEnReg HalSerialSetIrqEnRegRtl8195a + +#define InterruptForOSInit VectorTableInitForOSRtl8195A +#define InterruptRegister VectorIrqRegisterRtl8195A +#define InterruptUnRegister VectorIrqUnRegisterRtl8195A + +#define InterruptEn VectorIrqEnRtl8195A +#define InterruptDis VectorIrqDisRtl8195A + +#define SpicFlashInit SpicFlashInitRtl8195A +#define Calibration32k En32KCalibration +#define WDGInit InitWDGIRQ + +typedef enum _HAL_Status +{ + HAL_OK = 0x00, + HAL_BUSY = 0x01, + HAL_TIMEOUT = 0x02, + HAL_ERR_PARA = 0x03, // error with invaild parameters + HAL_ERR_MEM = 0x04, // error with memory allocation failed + HAL_ERR_HW = 0x05, // error with hardware error + + HAL_ERR_UNKNOWN = 0xee // unknown error + +} HAL_Status; + + +#endif //_HAL_API_H_ diff --git a/lib/fwlib/hal_common.h b/lib/fwlib/hal_common.h new file mode 100644 index 0000000..113c1a1 --- /dev/null +++ b/lib/fwlib/hal_common.h @@ -0,0 +1,17 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_COMMON_H_ +#define _HAL_COMMON_H_ + +//================= Function Prototype START =================== +HAL_Status HalCommonInit(void); +//================= Function Prototype END =================== + +#endif diff --git a/lib/fwlib/hal_crypto.h b/lib/fwlib/hal_crypto.h new file mode 100644 index 0000000..0224448 --- /dev/null +++ b/lib/fwlib/hal_crypto.h @@ -0,0 +1,213 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef __HAL_CRYPTO_H__ +#define __HAL_CRYPTO_H__ + + +#include "hal_api.h" +#include "basic_types.h" + + +#define CRYPTO_MAX_MSG_LENGTH 16000 +#define CRYPTO_MD5_DIGEST_LENGTH 16 +#define CRYPTO_SHA1_DIGEST_LENGTH 20 +#define CRYPTO_SHA2_DIGEST_LENGTH 32 + + +typedef enum _SHA2_TYPE_ { + SHA2_NONE = 0, + SHA2_224 = 224/8, + SHA2_256 = 256/8, + SHA2_384 = 384/8, + SHA2_512 = 512/8 +} SHA2_TYPE; + + +#define _ERRNO_CRYPTO_DESC_NUM_SET_OutRange -2 +#define _ERRNO_CRYPTO_BURST_NUM_SET_OutRange -3 +#define _ERRNO_CRYPTO_NULL_POINTER -4 +#define _ERRNO_CRYPTO_ENGINE_NOT_INIT -5 +#define _ERRNO_CRYPTO_ADDR_NOT_4Byte_Aligned -6 +#define _ERRNO_CRYPTO_KEY_OutRange -7 +#define _ERRNO_CRYPTO_MSG_OutRange -8 +#define _ERRNO_CRYPTO_IV_OutRange -9 +#define _ERRNO_CRYPTO_AUTH_TYPE_NOT_MATCH -10 +#define _ERRNO_CRYPTO_CIPHER_TYPE_NOT_MATCH -11 +#define _ERRNO_CRYPTO_KEY_IV_LEN_DIFF -12 + + + +// +// External API Functions +// + + +// Crypto Engine +extern int rtl_cryptoEngine_init(void); +extern void rtl_cryptoEngine_info(void); + + + +// +// Authentication +// + +// md5 + +extern int rtl_crypto_md5(IN const u8* message, IN const u32 msglen, OUT u8* pDigest); + +extern int rtl_crypto_md5_init(void); +extern int rtl_crypto_md5_process(IN const u8* message, const IN u32 msglen, OUT u8* pDigest); + + +// sha1 +extern int rtl_crypto_sha1(IN const u8* message, IN const u32 msglen, OUT u8* pDigest); + +extern int rtl_crypto_sha1_init(void); +extern int rtl_crypto_sha1_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest); + +// sha2 + +extern int rtl_crypto_sha2(IN const SHA2_TYPE sha2type, + IN const u8* message, IN const u32 msglen, OUT u8* pDigest); + +extern int rtl_crypto_sha2_init(IN const SHA2_TYPE sha2type); +extern int rtl_crypto_sha2_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest); + + +// HMAC-md5 +extern int rtl_crypto_hmac_md5(IN const u8* message, IN const u32 msglen, + IN const u8* key, IN const u32 keylen, OUT u8* pDigest); + +extern int rtl_crypto_hmac_md5_init(IN const u8* key, IN const u32 keylen); +extern int rtl_crypto_hmac_md5_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest); + + +// HMAC-sha1 +extern int rtl_crypto_hmac_sha1(IN const u8* message, IN const u32 msglen, + IN const u8* key, IN const u32 keylen, OUT u8* pDigest); + +extern int rtl_crypto_hmac_sha1_init(IN const u8* key, IN const u32 keylen); +extern int rtl_crypto_hmac_sha1_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest); + + +// HMAC-sha2 +extern int rtl_crypto_hmac_sha2(IN const SHA2_TYPE sha2type, IN const u8* message, IN const u32 msglen, + IN const u8* key, IN const u32 keylen, OUT u8* pDigest); + +extern int rtl_crypto_hmac_sha2_init(IN const SHA2_TYPE sha2type, IN const u8* key, IN const u32 keylen); +extern int rtl_crypto_hmac_sha2_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest); + + +// +// Cipher Functions +// + +// AES - CBC + +extern int rtl_crypto_aes_cbc_init(IN const u8* key, IN const u32 keylen); + +extern int rtl_crypto_aes_cbc_encrypt( + IN const u8* message, IN const u32 msglen, + IN const u8* iv, IN const u32 ivlen, OUT u8* pResult); + +extern int rtl_crypto_aes_cbc_decrypt( + IN const u8* message, IN const u32 msglen, + IN const u8* iv, IN const u32 ivlen, OUT u8* pResult); + + +// AES - ECB + +extern int rtl_crypto_aes_ecb_init(IN const u8* key, IN const u32 keylen); + +extern int rtl_crypto_aes_ecb_encrypt( + IN const u8* message, IN const u32 msglen, + IN const u8* iv, IN const u32 ivlen, OUT u8* pResult); + +extern int rtl_crypto_aes_ecb_decrypt( + IN const u8* message, IN const u32 msglen, + IN const u8* iv, IN const u32 ivlen, OUT u8* pResult); + + +// AES - CTR + +extern int rtl_crypto_aes_ctr_init(IN const u8* key, IN const u32 keylen); + +extern int rtl_crypto_aes_ctr_encrypt( + IN const u8* message, IN const u32 msglen, + IN const u8* iv, IN const u32 ivlen, OUT u8* pResult); + +extern int rtl_crypto_aes_ctr_decrypt( + IN const u8* message, IN const u32 msglen, + IN const u8* iv, IN const u32 ivlen, OUT u8* pResult); + + +// 3DES - CBC + +extern int rtl_crypto_3des_cbc_init(IN const u8* key, IN const u32 keylen); + +extern int rtl_crypto_3des_cbc_encrypt( + IN const u8* message, IN const u32 msglen, + IN const u8* iv, IN const u32 ivlen, OUT u8* pResult); + +extern int rtl_crypto_3des_cbc_decrypt( + IN const u8* message, IN const u32 msglen, + IN const u8* iv, IN const u32 ivlen, OUT u8* pResult); + + +// 3DES - ECB + +extern int rtl_crypto_3des_ecb_init(IN const u8* key, IN const u32 keylen); + +extern int rtl_crypto_3des_ecb_encrypt( + IN const u8* message, IN const u32 msglen, + IN const u8* iv, IN const u32 ivlen, OUT u8* pResult); + +extern int rtl_crypto_3des_ecb_decrypt( + IN const u8* message, IN const u32 msglen, + IN const u8* iv, IN const u32 ivlen, OUT u8* pResult); + + +// DES - CBC + +extern int rtl_crypto_des_cbc_init(IN const u8* key, IN const u32 keylen); + +extern int rtl_crypto_des_cbc_encrypt( + IN const u8* message, IN const u32 msglen, + IN const u8* iv, IN const u32 ivlen, OUT u8* pResult); + +extern int rtl_crypto_des_cbc_decrypt( + IN const u8* message, IN const u32 msglen, + IN const u8* iv, IN const u32 ivlen, OUT u8* pResult); + + +// DES - ECB + +extern int rtl_crypto_des_ecb_init(IN const u8* key, IN const u32 keylen); + +extern int rtl_crypto_des_ecb_encrypt( + IN const u8* message, IN const u32 msglen, + IN const u8* iv, IN const u32 ivlen, OUT u8* pResult); + +extern int rtl_crypto_des_ecb_decrypt( + IN const u8* message, IN const u32 msglen, + IN const u8* iv, IN const u32 ivlen, OUT u8* pResult); + + +// +// C functions in ROM +// + +extern int rtl_memcmpb(const u8 *dst, const u8 *src, int bytes); +extern int rtl_memcpyb(u8 *dst, const u8 *src, int bytes); + +#endif /* __HAL_CRYPTO_H__ */ + diff --git a/lib/fwlib/hal_dac.h b/lib/fwlib/hal_dac.h new file mode 100644 index 0000000..f8b3c8f --- /dev/null +++ b/lib/fwlib/hal_dac.h @@ -0,0 +1,313 @@ +//====================================================== +// Routines to access hardware +// +// Copyright (c) 2013 Realtek Semiconductor Corp. +// +// This module is a confidential and proprietary property of RealTek and +// possession or use of this module requires written permission of RealTek. +//====================================================== +#ifndef _HAL_DAC_H_ +#define _HAL_DAC_H_ + +#include "rtl8195a.h" +#include "rtl8195a_dac.h" +#include "hal_api.h" +#include "hal_gdma.h" + +//================ DAC Configuration ========================= +#define DAC_INTR_OP_TYPE 1 +#define DAC_DMA_OP_TYPE 1 + +// DAC SAL management macros +#define SAL_DAC_USER_CB_NUM (sizeof(SAL_DAC_USER_CB) / sizeof(PSAL_DAC_USERCB_ADPT)) + +// DAC SAL used module. +// Please set the DAC module flag to 1 to enable the related DAC module functions. +#define DAC0_USED 1 +#define DAC1_USED 1 + + +//================ Debug MSG Definition ======================= +#define DAC_PREFIX "RTL8195A[dac]: " +#define DAC_PREFIX_LVL " [DAC_DBG]: " + +typedef enum _DAC_DBG_LVL_ { + HAL_DAC_LVL = 0x00, + SAL_DAC_LVL = 0x02, + VERI_DAC_LVL = 0x04, +}DAC_DBG_LVL,*PDAC_DBG_LVL; + +#ifdef CONFIG_DEBUG_LOG +#ifdef CONFIG_DEBUG_LOG_DAC_HAL + + #define DBG_8195A_DAC(...) do{ \ + _DbgDump("\r"DAC_PREFIX __VA_ARGS__);\ + }while(0) + + + #define DACDBGLVL 0xFF + #define DBG_8195A_DAC_LVL(LVL,...) do{\ + if (LVL&DACDBGLVL){\ + _DbgDump("\r"DAC_PREFIX_LVL __VA_ARGS__);\ + }\ + }while(0) +#else + #define DBG_DAC_LOG_PERD 100 + #define DBG_8195A_DAC(...) + #define DBG_8195A_DAC_LVL(...) +#endif +#endif + + +//================ DAC HAL Related Enumeration ================== +// DAC Module Selection +typedef enum _DAC_MODULE_SEL_ { + DAC0_SEL = 0x0, + DAC1_SEL = 0x1, +}DAC_MODULE_SEL,*PDAC_MODULE_SEL; + +// DAC module status +typedef enum _DAC_MODULE_STATUS_ { + DAC_DISABLE = 0x0, + DAC_ENABLE = 0x1, +}DAC_MODULE_STATUS, *PDAC_MODULE_STATUS; + +// DAC Data Rate +typedef enum _DAC_DATA_RATE_ { + DAC_DATA_RATE_10K = 0x0, + DAC_DATA_RATE_250K = 0x1, +}DAC_DATA_RATE,*PDAC_DATA_RATE; + +// DAC Data Endian +typedef enum _DAC_DATA_ENDIAN_ { + DAC_DATA_ENDIAN_LITTLE = 0x0, + DAC_DATA_ENDIAN_BIG = 0x1, +}DAC_DATA_ENDIAN,*PDAC_DATA_ENDIAN; + +// DAC Debug Select +typedef enum _DAC_DEBUG_SEL_ { + DAC_DBG_SEL_DISABLE = 0x0, + DAC_DBG_SEL_ENABLE = 0x1, +}DAC_DEBUG_SEL,*PDAC_DEBUG_SEL; + +// DAC Dsc Debug Select +typedef enum _DAC_DSC_DEBUG_SEL_ { + DAC_DSC_DBG_SEL_DISABLE = 0x0, + DAC_DSC_DBG_SEL_ENABLE = 0x1, +}DAC_DSC_DEBUG_SEL,*PDAC_DSC_DEBUG_SEL; + + +// DAC Bypass Dsc Debug Select +typedef enum _DAC_BYPASS_DSC_SEL_ { + DAC_BYPASS_DSC_SEL_DISABLE = 0x0, + DAC_BYPASS_DSC_SEL_ENABLE = 0x1, +}DAC_BYPASS_DSC_SEL,*PDAC_BYPASS_DSC_SEL; + +// DAC feature status +typedef enum _DAC_FEATURE_STATUS_{ + DAC_FEATURE_DISABLED = 0, + DAC_FEATURE_ENABLED = 1, +}DAC_FEATURE_STATUS,*PDAC_FEATURE_STATUS; + +// DAC operation type +typedef enum _DAC_OP_TYPE_ { + DAC_POLL_TYPE = 0x0, + DAC_DMA_TYPE = 0x1, + DAC_INTR_TYPE = 0x2, +}DAC_OP_TYPE, *PDAC_OP_TYPE; + +// DAC device status +typedef enum _DAC_Device_STATUS_ { + DAC_STS_UNINITIAL = 0x00, + DAC_STS_INITIALIZED = 0x01, + DAC_STS_IDLE = 0x02, + + DAC_STS_TX_READY = 0x03, + DAC_STS_TX_ING = 0x04, + + DAC_STS_RX_READY = 0x05, + DAC_STS_RX_ING = 0x06, + + DAC_STS_ERROR = 0x07, +}DAC_Device_STATUS, *PDAC_Device_STATUS; + +//DAC device error type +typedef enum _DAC_ERR_TYPE_ { + DAC_ERR_FIFO_OVER = 0x04, //DAC FIFO overflow. + DAC_ERR_FIFO_STOP = 0x08, //DAC FIFO is completely empty, and it will be stopped automatically. + DAC_ERR_FIFO_WRFAIL = 0x10, //When DAC is NOT enabled, a write operation attempts to access DAC register. + DAC_ERR_FIFO_DSC_OVER0 = 0x20, + DAC_ERR_FIFO_DSC_OVER1 = 0x40, +}DAC_ERR_TYPE, *PDAC_ERR_TYPE; + +// DAC data input method +typedef enum _DAC_INPUT_TYPE_{ + DAC_INPUT_SINGLE_WR = 0x1, //DAC input by using single register write + DAC_INPUT_DMA_ONEBLK = 0x2, //DAC input by using single DMA block + DAC_INPUT_DMA_LLP = 0x3, //DAC input by using DMA linked list mode +}DAC_INPUT_TYPE,*PDAC_INPUT_TYPE; + + + + +//====================================================== +// DAC HAL initial data structure +typedef struct _HAL_DAC_INIT_DAT_ { + u8 DACIdx; //DAC index used + u8 DACEn; //DAC module enable + u8 DACDataRate; //DAC data rate, 1'b0:10KHz, 1'b1:250KHz + u8 DACEndian; //DAC endian selection, + //but actually it's for 32-bit DAC data swap control + //1'b0: no swap, + //1'b1: swap the upper 16-bit and the lower 16-bit + u8 DACFilterSet; //DAC filter settle + u8 DACBurstSz; //DAC burst size + u8 DACDbgSel; //DAC debug sel + u8 DACDscDbgSel; //DAC debug dsc sel + + u8 DACBPDsc; //DAC bypass delta sigma for loopback + u8 DACDeltaSig; //DAC bypass value of delta sigma + u16 RSVD1; + + + + u32 *DACData; //DAC data pointer + u32 DACPWCtrl; //DAC0 and DAC1 power control + u32 DACAnaCtrl0; //DAC anapar_da control 0 + u32 DACAnaCtrl1; //DAC anapar_da control 1 + u32 DACIntrMSK; //DAC Interrupt Mask +}HAL_DAC_INIT_DAT,*PHAL_DAC_INIT_DAT; + +// DAC HAL Operations +typedef struct _HAL_DAC_OP_ { + RTK_STATUS (*HalDACInit) (VOID *Data); //HAL DAC initialization + RTK_STATUS (*HalDACDeInit) (VOID *Data); //HAL DAC de-initialization + RTK_STATUS (*HalDACEnable) (VOID *Data); //HAL DAC de-initialization + u8 (*HalDACSend) (VOID *Data); //HAL DAC receive + RTK_STATUS (*HalDACIntrCtrl) (VOID *Data); //HAL DAC interrupt control + u32 (*HalDACReadReg) (VOID *Data, u8 DACReg);//HAL DAC read register +}HAL_DAC_OP, *PHAL_DAC_OP; + +// DAC user callback adapter +typedef struct _SAL_DAC_USERCB_ADPT_ { + VOID (*USERCB) (VOID *Data); + u32 USERData; +}SAL_DAC_USERCB_ADPT, *PSAL_DAC_USERCB_ADPT; + +// DAC user callback structure +typedef struct _SAL_DAC_USER_CB_ { + PSAL_DAC_USERCB_ADPT pTXCB; //DAC Transmit Callback + PSAL_DAC_USERCB_ADPT pTXCCB; //DAC Transmit Complete Callback + PSAL_DAC_USERCB_ADPT pRXCB; //DAC Receive Callback + PSAL_DAC_USERCB_ADPT pRXCCB; //DAC Receive Complete Callback + PSAL_DAC_USERCB_ADPT pRDREQCB; //DAC Read Request Callback + PSAL_DAC_USERCB_ADPT pERRCB; //DAC Error Callback + PSAL_DAC_USERCB_ADPT pDMATXCB; //DAC DMA Transmit Callback + PSAL_DAC_USERCB_ADPT pDMATXCCB; //DAC DMA Transmit Complete Callback + PSAL_DAC_USERCB_ADPT pDMARXCB; //DAC DMA Receive Callback + PSAL_DAC_USERCB_ADPT pDMARXCCB; //DAC DMA Receive Complete Callback +}SAL_DAC_USER_CB, *PSAL_DAC_USER_CB; + +// DAC Transmit Buffer +typedef struct _SAL_DAC_TRANSFER_BUF_ { + u32 DataLen; //DAC Transmfer Length + u32 *pDataBuf; //DAC Transfer Buffer Pointer + u32 RSVD; // +}SAL_DAC_TRANSFER_BUF,*PSAL_DAC_TRANSFER_BUF; + +typedef struct _SAL_DAC_DMA_USER_DEF_ { + + u8 TxDatSrcWdth; + u8 TxDatDstWdth; + u8 TxDatSrcBstSz; + u8 TxDatDstBstSz; + + u8 TxChNo; + u8 LlpCtrl; + u16 RSVD0; + + u32 MaxMultiBlk; + u32 pLlix; + u32 pBlockSizeList; +}SAL_DAC_DMA_USER_DEF, *PSAL_DAC_DMA_USER_DEF; + +// Software API Level DAC Handler +typedef struct _SAL_DAC_HND_ { + u8 DevNum; //DAC device number + u8 PinMux; //DAC pin mux seletion + u8 OpType; //DAC operation type selection + volatile u8 DevSts; //DAC device status + + u8 DACInType; //DAC input type + u8 RSVD0; + u16 RSVD1; + + u32 DACExd; //DAC extended options: + //bit 0: example + //bit 31~bit 1: Reserved + u32 ErrType; // + u32 TimeOut; //DAC IO Timeout count + + PHAL_DAC_INIT_DAT pInitDat; //Pointer to DAC initial data struct + PSAL_DAC_TRANSFER_BUF pTXBuf; //Pointer to DAC TX buffer + PSAL_DAC_USER_CB pUserCB; //Pointer to DAC User Callback + PSAL_DAC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA Config +}SAL_DAC_HND, *PSAL_DAC_HND; + +// DAC SAL handle private +typedef struct _SAL_DAC_HND_PRIV_ { + VOID **ppSalDACHnd; //Pointer to SAL_DAC_HND pointer + SAL_DAC_HND SalDACHndPriv; //Private SAL_DAC_HND +}SAL_DAC_HND_PRIV, *PSAL_DAC_HND_PRIV; + +//DAC SAL management adapter +typedef struct _SAL_DAC_MNGT_ADPT_ { + PSAL_DAC_HND_PRIV pSalHndPriv; //Pointer to SAL_DAC_HND + PHAL_DAC_INIT_DAT pHalInitDat; //Pointer to HAL DAC initial data( HAL_I2C_INIT_DAT ) + PHAL_DAC_OP pHalOp; //Pointer to HAL DAC operation( HAL_DAC_OP ) + VOID (*pHalOpInit)(VOID*); //Pointer to HAL DAC initialize function + PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE ) + PSAL_DAC_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_DAC_USER_CB ) + VOID (*pSalIrqFunc)(VOID*); //Used for SAL DAC interrupt function + + PSAL_DAC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA config + PHAL_GDMA_ADAPTER pHalGdmaAdp; + PHAL_GDMA_OP pHalGdmaOp; + VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL DAC initialize function + PIRQ_HANDLE pIrqGdmaHnd; + VOID (*pSalDMAIrqFunc)(VOID*); //Used for SAL DAC interrupt function +}SAL_DAC_MNGT_ADPT, *PSAL_DAC_MNGT_ADPT; + + +//================ DAC HAL Function Prototype =================== +// DAC HAL inline function +// For checking DAC input index valid or not +static inline RTK_STATUS +RtkDACIdxChk( + IN u8 DACIdx +) +{ +#if !DAC0_USED + if (DACIdx == DAC0_SEL) + return _EXIT_FAILURE; +#endif + +#if !DAC1_USED + if (DACIdx == DAC1_SEL) + return _EXIT_FAILURE; +#endif + + return _EXIT_SUCCESS; +} + +VOID HalDACOpInit(IN VOID *Data); +RTK_STATUS RtkDACLoadDefault(IN VOID *Data); +RTK_STATUS RtkDACInit(IN VOID *Data); +RTK_STATUS RtkDACDeInit(IN VOID *Data); +RTK_STATUS RtkDACSend(IN VOID *Data); +PSAL_DAC_HND RtkDACGetSalHnd(IN u8 DACIdx); +RTK_STATUS RtkDACFreeSalHnd(IN PSAL_DAC_HND pSalDACHND); +PSAL_DAC_MNGT_ADPT RtkDACGetMngtAdpt(IN u8 DACIdx); +RTK_STATUS RtkDACFreeMngtAdpt(IN PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt); + +#endif diff --git a/lib/fwlib/hal_diag.h b/lib/fwlib/hal_diag.h new file mode 100644 index 0000000..8bacf16 --- /dev/null +++ b/lib/fwlib/hal_diag.h @@ -0,0 +1,107 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_DIAG_H_ +#define _HAL_DIAG_H_ + + +//Register offset +#define UART_REV_BUF_OFF 0x00 +#define UART_TRAN_HOLD_OFF 0x00 +#define UART_DLH_OFF 0x04 +#define UART_DLL_OFF 0x00 +#define UART_INTERRUPT_EN_REG_OFF 0x04 +#define UART_INTERRUPT_IDEN_REG_OFF 0x08 +#define UART_FIFO_CTL_REG_OFF 0x08 +#define UART_LINE_CTL_REG_OFF 0x0c +#define UART_MODEM_CTL_REG_OFF 0x10 +#define UART_LINE_STATUS_REG_OFF 0x14 +#define UART_MODEM_STATUS_REG_OFF 0x18 +#define UART_FIFO_ACCESS_REG_OFF 0x70 +#define UART_STATUS_REG_OFF 0x7c +#define UART_TFL_OFF 0x80 +#define UART_RFL_OFF 0x84 + + +//Buad rate +#define UART_BAUD_RATE_2400 2400 +#define UART_BAUD_RATE_4800 4800 +#define UART_BAUD_RATE_9600 9600 +#define UART_BAUD_RATE_19200 19200 +#define UART_BAUD_RATE_38400 38400 +#define UART_BAUD_RATE_57600 57600 +#define UART_BAUD_RATE_115200 115200 +#define UART_BAUD_RATE_921600 921600 +#define UART_BAUD_RATE_1152000 1152000 + +#define UART_PARITY_ENABLE 0x08 +#define UART_PARITY_DISABLE 0 + +#define UART_DATA_LEN_5BIT 0x0 +#define UART_DATA_LEN_6BIT 0x1 +#define UART_DATA_LEN_7BIT 0x2 +#define UART_DATA_LEN_8BIT 0x3 + +#define UART_STOP_1BIT 0x0 +#define UART_STOP_2BIT 0x4 + + +#define HAL_UART_READ32(addr) HAL_READ32(LOG_UART_REG_BASE, addr) +#define HAL_UART_WRITE32(addr, value) HAL_WRITE32(LOG_UART_REG_BASE, addr, value) +#define HAL_UART_READ16(addr) HAL_READ16(LOG_UART_REG_BASE, addr) +#define HAL_UART_WRITE16(addr, value) HAL_WRITE16(LOG_UART_REG_BASE, addr, value) +#define HAL_UART_READ8(addr) HAL_READ8(LOG_UART_REG_BASE, addr) +#define HAL_UART_WRITE8(addr, value) HAL_WRITE8(LOG_UART_REG_BASE, addr, value) + +typedef struct _LOG_UART_ADAPTER_ { + u32 BaudRate; + u32 FIFOControl; + u32 IntEnReg; + u8 Parity; + u8 Stop; + u8 DataLength; +}LOG_UART_ADAPTER, *PLOG_UART_ADAPTER; + +typedef struct _COMMAND_TABLE_ { + const u8* cmd; + u16 ArgvCnt; + u32 (*func)(u16 argc, u8* argv[]); + const u8* msg; +}COMMAND_TABLE, *PCOMMAND_TABLE; + +//VOID +//HalLogUartHandle(void); + + +extern _LONG_CALL_ROM_ u32 +HalLogUartInit( + IN LOG_UART_ADAPTER UartAdapter + ); + + +extern _LONG_CALL_ROM_ VOID +HalSerialPutcRtl8195a( + IN u8 c + ); + +extern _LONG_CALL_ROM_ u8 +HalSerialGetcRtl8195a( + IN BOOL PullMode + ); + +extern _LONG_CALL_ROM_ u32 +HalSerialGetIsrEnRegRtl8195a(VOID); + +extern _LONG_CALL_ROM_ VOID +HalSerialSetIrqEnRegRtl8195a ( + IN u32 SetValue +); + + +#endif//_HAL_DIAG_H_ diff --git a/lib/fwlib/hal_efuse.h b/lib/fwlib/hal_efuse.h new file mode 100644 index 0000000..aca819d --- /dev/null +++ b/lib/fwlib/hal_efuse.h @@ -0,0 +1,22 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_EFUSE_H_ +#define _HAL_EFUSE_H_ + +_LONG_CALL_ROM_ extern VOID HalEFUSEPowerSwitch8195AROM(IN u8 bWrite, IN u8 PwrState, IN u8 L25OutVoltage); +_LONG_CALL_ extern u32 HALEFUSEOneByteReadROM(IN u32 CtrlSetting, IN u16 Addr, OUT u8 *Data, IN u8 L25OutVoltage); +_LONG_CALL_ extern u32 HALEFUSEOneByteWriteROM(IN u32 CtrlSetting, IN u16 Addr, IN u8 Data, IN u8 L25OutVoltage); + +#define EFUSERead8 HALEFUSEOneByteReadROM +#define EFUSEWrite8 HALEFUSEOneByteWriteROM + +#define L25EOUTVOLTAGE 7 +#endif + diff --git a/lib/fwlib/hal_gdma.h b/lib/fwlib/hal_gdma.h new file mode 100644 index 0000000..d7294e6 --- /dev/null +++ b/lib/fwlib/hal_gdma.h @@ -0,0 +1,141 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_GDMA_H_ +#define _HAL_GDMA_H_ + +#include "rtl8195a_gdma.h" + +typedef struct _GDMA_CH_LLI_ELE_ { + u32 Sarx; + u32 Darx; + u32 Llpx; + u32 CtlxLow; + u32 CtlxUp; + u32 Temp; +}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE; +#if 1 +#if 0 +typedef struct _GDMA_CH_LLI_ { + PGDMA_CH_LLI_ELE pLliEle; + PGDMA_CH_LLI pNextLli; +}GDMA_CH_LLI, *PGDMA_CH_LLI; + +typedef struct _BLOCK_SIZE_LIST_ { + u32 BlockSize; + PBLOCK_SIZE_LIST pNextBlockSiz; +}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST; +#else +struct GDMA_CH_LLI { + PGDMA_CH_LLI_ELE pLliEle; + struct GDMA_CH_LLI *pNextLli; +}; + +struct BLOCK_SIZE_LIST { + u32 BlockSize; + struct BLOCK_SIZE_LIST *pNextBlockSiz; +}; + +#endif + +#endif +typedef struct _HAL_GDMA_ADAPTER_ { + u32 ChSar; + u32 ChDar; + GDMA_CHANNEL_NUM ChEn; + GDMA_CTL_REG GdmaCtl; + GDMA_CFG_REG GdmaCfg; + u32 PacketLen; + u32 BlockLen; + u32 MuliBlockCunt; + u32 MaxMuliBlock; + struct GDMA_CH_LLI *pLlix; + struct BLOCK_SIZE_LIST *pBlockSizeList; + + PGDMA_CH_LLI_ELE pLli; + u32 NextPlli; + u8 TestItem; + u8 ChNum; + u8 GdmaIndex; + u8 IsrCtrl:1; + u8 GdmaOnOff:1; + u8 Llpctrl:1; + u8 Lli0:1; + u8 Rsvd4to7:4; + u8 GdmaIsrType; +}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER; + +typedef struct _HAL_GDMA_CHNL_ { + u8 GdmaIndx; + u8 GdmaChnl; + u8 IrqNum; + u8 Reserved; +}HAL_GDMA_CHNL, *PHAL_GDMA_CHNL; + +typedef struct _HAL_GDMA_BLOCK_ { + u32 SrcAddr; + u32 DstAddr; + u32 BlockLength; + u32 SrcOffset; + u32 DstOffset; +}HAL_GDMA_BLOCK, *PHAL_GDMA_BLOCK; + +typedef struct _HAL_GDMA_OP_ { + VOID (*HalGdmaOnOff)(VOID *Data); + BOOL (*HalGdamChInit)(VOID *Data); + BOOL (*HalGdmaChSeting)(VOID *Data); + BOOL (*HalGdmaChBlockSeting)(VOID *Data); + VOID (*HalGdmaChDis)(VOID *Data); + VOID (*HalGdmaChEn)(VOID *Data); + VOID (*HalGdmaChIsrEnAndDis) (VOID *Data); + u8 (*HalGdmaChIsrClean)(VOID *Data); + VOID (*HalGdmaChCleanAutoSrc)(VOID *Data); + VOID (*HalGdmaChCleanAutoDst)(VOID *Data); +}HAL_GDMA_OP, *PHAL_GDMA_OP; + +typedef struct _HAL_GDMA_OBJ_ { + HAL_GDMA_ADAPTER HalGdmaAdapter; + IRQ_HANDLE GdmaIrqHandle; + volatile GDMA_CH_LLI_ELE GdmaChLli[16]; + struct GDMA_CH_LLI Lli[16]; + struct BLOCK_SIZE_LIST BlockSizeList[16]; + u8 Busy; // is transfering + u8 BlockNum; +} HAL_GDMA_OBJ, *PHAL_GDMA_OBJ; + +VOID HalGdmaOpInit(IN VOID *Data); +VOID HalGdmaOn(PHAL_GDMA_ADAPTER pHalGdmaAdapter); +VOID HalGdmaOff(PHAL_GDMA_ADAPTER pHalGdmaAdapter); +BOOL HalGdmaChInit(PHAL_GDMA_ADAPTER pHalGdmaAdapter); +VOID HalGdmaChDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter); +VOID HalGdmaChEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter); +BOOL HalGdmaChSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter); +BOOL HalGdmaChBlockSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter); +VOID HalGdmaChIsrEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter); +VOID HalGdmaChIsrDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter); +u8 HalGdmaChIsrClean(PHAL_GDMA_ADAPTER pHalGdmaAdapter); +VOID HalGdmaChCleanAutoSrc(PHAL_GDMA_ADAPTER pHalGdmaAdapter); +VOID HalGdmaChCleanAutoDst(PHAL_GDMA_ADAPTER pHalGdmaAdapter); + +extern HAL_Status HalGdmaChnlRegister (u8 GdmaIdx, u8 ChnlNum); +extern VOID HalGdmaChnlUnRegister (u8 GdmaIdx, u8 ChnlNum); +extern PHAL_GDMA_CHNL HalGdmaChnlAlloc (HAL_GDMA_CHNL *pChnlOption); +extern VOID HalGdmaChnlFree (HAL_GDMA_CHNL *pChnl); +extern BOOL HalGdmaMemCpyInit(PHAL_GDMA_OBJ pHalGdmaObj); +extern VOID HalGdmaMemCpyDeInit(PHAL_GDMA_OBJ pHalGdmaObj); +extern VOID* HalGdmaMemCpy(PHAL_GDMA_OBJ pHalGdmaObj, void* pDest, void* pSrc, u32 len); +extern VOID HalGdmaMemAggr(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock); +extern BOOL HalGdmaMemCpyAggrInit(PHAL_GDMA_OBJ pHalGdmaObj); + +extern const HAL_GDMA_OP _HalGdmaOp; +extern const HAL_GDMA_CHNL GDMA_Chnl_Option[]; +extern const HAL_GDMA_CHNL GDMA_Multi_Block_Chnl_Option[]; +extern const u16 HalGdmaChnlEn[6]; + +#endif diff --git a/lib/fwlib/hal_gpio.h b/lib/fwlib/hal_gpio.h new file mode 100644 index 0000000..3046336 --- /dev/null +++ b/lib/fwlib/hal_gpio.h @@ -0,0 +1,236 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_GPIO_H_ +#define _HAL_GPIO_H_ + +#define HAL_GPIO_PIN_INT_MODE 0x80 + +typedef enum { + _PORT_A = 0, + _PORT_B = 1, + _PORT_C = 2, + _PORT_D = 3, + _PORT_E = 4, + _PORT_F = 5, + _PORT_G = 6, + _PORT_H = 7, + _PORT_I = 8, + _PORT_J = 9, + _PORT_K = 10, + + _PORT_MAX +} HAL_GPIO_PORT_NAME; + +typedef enum { + _PA_0 = (_PORT_A<<4|0), + _PA_1 = (_PORT_A<<4|1), + _PA_2 = (_PORT_A<<4|2), + _PA_3 = (_PORT_A<<4|3), + _PA_4 = (_PORT_A<<4|4), + _PA_5 = (_PORT_A<<4|5), + _PA_6 = (_PORT_A<<4|6), + _PA_7 = (_PORT_A<<4|7), + + _PB_0 = (_PORT_B<<4|0), + _PB_1 = (_PORT_B<<4|1), + _PB_2 = (_PORT_B<<4|2), + _PB_3 = (_PORT_B<<4|3), + _PB_4 = (_PORT_B<<4|4), + _PB_5 = (_PORT_B<<4|5), + _PB_6 = (_PORT_B<<4|6), + _PB_7 = (_PORT_B<<4|7), + + _PC_0 = (_PORT_C<<4|0), + _PC_1 = (_PORT_C<<4|1), + _PC_2 = (_PORT_C<<4|2), + _PC_3 = (_PORT_C<<4|3), + _PC_4 = (_PORT_C<<4|4), + _PC_5 = (_PORT_C<<4|5), + _PC_6 = (_PORT_C<<4|6), + _PC_7 = (_PORT_C<<4|7), + _PC_8 = (_PORT_C<<4|8), + _PC_9 = (_PORT_C<<4|9), + + _PD_0 = (_PORT_D<<4|0), + _PD_1 = (_PORT_D<<4|1), + _PD_2 = (_PORT_D<<4|2), + _PD_3 = (_PORT_D<<4|3), + _PD_4 = (_PORT_D<<4|4), + _PD_5 = (_PORT_D<<4|5), + _PD_6 = (_PORT_D<<4|6), + _PD_7 = (_PORT_D<<4|7), + _PD_8 = (_PORT_D<<4|8), + _PD_9 = (_PORT_D<<4|9), + + _PE_0 = (_PORT_E<<4|0), + _PE_1 = (_PORT_E<<4|1), + _PE_2 = (_PORT_E<<4|2), + _PE_3 = (_PORT_E<<4|3), + _PE_4 = (_PORT_E<<4|4), + _PE_5 = (_PORT_E<<4|5), + _PE_6 = (_PORT_E<<4|6), + _PE_7 = (_PORT_E<<4|7), + _PE_8 = (_PORT_E<<4|8), + _PE_9 = (_PORT_E<<4|9), + _PE_A = (_PORT_E<<4|10), + + _PF_0 = (_PORT_F<<4|0), + _PF_1 = (_PORT_F<<4|1), + _PF_2 = (_PORT_F<<4|2), + _PF_3 = (_PORT_F<<4|3), + _PF_4 = (_PORT_F<<4|4), + _PF_5 = (_PORT_F<<4|5), +// _PF_6 = (_PORT_F<<4|6), +// _PF_7 = (_PORT_F<<4|7), + + _PG_0 = (_PORT_G<<4|0), + _PG_1 = (_PORT_G<<4|1), + _PG_2 = (_PORT_G<<4|2), + _PG_3 = (_PORT_G<<4|3), + _PG_4 = (_PORT_G<<4|4), + _PG_5 = (_PORT_G<<4|5), + _PG_6 = (_PORT_G<<4|6), + _PG_7 = (_PORT_G<<4|7), + + _PH_0 = (_PORT_H<<4|0), + _PH_1 = (_PORT_H<<4|1), + _PH_2 = (_PORT_H<<4|2), + _PH_3 = (_PORT_H<<4|3), + _PH_4 = (_PORT_H<<4|4), + _PH_5 = (_PORT_H<<4|5), + _PH_6 = (_PORT_H<<4|6), + _PH_7 = (_PORT_H<<4|7), + + _PI_0 = (_PORT_I<<4|0), + _PI_1 = (_PORT_I<<4|1), + _PI_2 = (_PORT_I<<4|2), + _PI_3 = (_PORT_I<<4|3), + _PI_4 = (_PORT_I<<4|4), + _PI_5 = (_PORT_I<<4|5), + _PI_6 = (_PORT_I<<4|6), + _PI_7 = (_PORT_I<<4|7), + + _PJ_0 = (_PORT_J<<4|0), + _PJ_1 = (_PORT_J<<4|1), + _PJ_2 = (_PORT_J<<4|2), + _PJ_3 = (_PORT_J<<4|3), + _PJ_4 = (_PORT_J<<4|4), + _PJ_5 = (_PORT_J<<4|5), + _PJ_6 = (_PORT_J<<4|6), +// _PJ_7 = (_PORT_J<<4|7), + + _PK_0 = (_PORT_K<<4|0), + _PK_1 = (_PORT_K<<4|1), + _PK_2 = (_PORT_K<<4|2), + _PK_3 = (_PORT_K<<4|3), + _PK_4 = (_PORT_K<<4|4), + _PK_5 = (_PORT_K<<4|5), + _PK_6 = (_PORT_K<<4|6), +// _PK_7 = (_PORT_K<<4|7), + + // Not connected + _PIN_NC = (int)0xFFFFFFFF +} HAL_PIN_NAME; + +typedef enum +{ + GPIO_PIN_LOW = 0, + GPIO_PIN_HIGH = 1, + GPIO_PIN_ERR = 2 // read Pin error +} HAL_GPIO_PIN_STATE; + +typedef enum { + DIN_PULL_NONE = 0, //floating or high impedance ? + DIN_PULL_LOW = 1, + DIN_PULL_HIGH = 2, + + DOUT_PUSH_PULL = 3, + DOUT_OPEN_DRAIN = 4, + + INT_LOW = (5|HAL_GPIO_PIN_INT_MODE), // Interrupt Low level trigger + INT_HIGH = (6|HAL_GPIO_PIN_INT_MODE), // Interrupt High level trigger + INT_FALLING = (7|HAL_GPIO_PIN_INT_MODE), // Interrupt Falling edge trigger + INT_RISING = (8|HAL_GPIO_PIN_INT_MODE) // Interrupt Rising edge trigger +} HAL_GPIO_PIN_MODE; + +enum { + GPIO_PORT_A = 0, + GPIO_PORT_B = 1, + GPIO_PORT_C = 2, + GPIO_PORT_D = 3 +}; + +typedef enum { + hal_PullNone = 0, + hal_PullUp = 1, + hal_PullDown = 2, + hal_OpenDrain = 3, + hal_PullDefault = hal_PullNone +} HAL_PinMode; + +typedef struct _HAL_GPIO_PORT_ { + u32 out_data; // to write the GPIO port + u32 in_data; // to read the GPIO port + u32 dir; // config each pin direction +}HAL_GPIO_PORT, *PHAL_GPIO_PORT; + +#define HAL_GPIO_PIN_NAME(port,pin) (((port)<<5)|(pin)) +#define HAL_GPIO_GET_PORT_BY_NAME(x) ((x>>5) & 0x03) +#define HAL_GPIO_GET_PIN_BY_NAME(x) (x & 0x1f) + +typedef struct _HAL_GPIO_PIN_ { + HAL_GPIO_PIN_MODE pin_mode; + u32 pin_name; // Pin: [7:5]: port number, [4:0]: pin number +}HAL_GPIO_PIN, *PHAL_GPIO_PIN; + +typedef struct _HAL_GPIO_OP_ { +#if defined(__ICCARM__) + void* dummy; +#endif +}HAL_GPIO_OP, *PHAL_GPIO_OP; + +typedef void (*GPIO_IRQ_FUN)(VOID *Data, u32 Id); +typedef void (*GPIO_USER_IRQ_FUN)(u32 Id); + +typedef struct _HAL_GPIO_ADAPTER_ { + IRQ_HANDLE IrqHandle; // GPIO HAL IRQ Handle + GPIO_USER_IRQ_FUN UserIrqHandler; // GPIO IRQ Handler + GPIO_IRQ_FUN PortA_IrqHandler[32]; // The interrupt handler triggered by Port A[x] + VOID *PortA_IrqData[32]; + VOID (*EnterCritical)(void); + VOID (*ExitCritical)(void); + u32 Local_Gpio_Dir[3]; // to record direction setting: 0- IN, 1- Out + u8 Gpio_Func_En; // Is GPIO HW function enabled ? + u8 Locked; +}HAL_GPIO_ADAPTER, *PHAL_GPIO_ADAPTER; + +u32 +HAL_GPIO_GetPinName( + u32 chip_pin +); + +VOID +HAL_GPIO_PullCtrl( + u32 pin, + u32 mode +); + +VOID +HAL_GPIO_Init( + HAL_GPIO_PIN *GPIO_Pin +); + +VOID +HAL_GPIO_Irq_Init( + HAL_GPIO_PIN *GPIO_Pin +); + +#endif // end of "#define _HAL_GPIO_H_" + diff --git a/lib/fwlib/hal_i2c.h b/lib/fwlib/hal_i2c.h new file mode 100644 index 0000000..5fadbe3 --- /dev/null +++ b/lib/fwlib/hal_i2c.h @@ -0,0 +1,585 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_I2C_H_ //#ifndef _HAL_I2C_H_ +#define _HAL_I2C_H_ + +#include "rtl8195a_i2c.h" +#include "hal_gdma.h" + +//================= I2C CONFIGURATION START ================== +// I2C SAL User Configuration Flags + +// I2C SAL operation types +#define I2C_POLL_OP_TYPE 1 +#define I2C_INTR_OP_TYPE 1 +#define I2C_DMA_OP_TYPE 1 + +// I2C supports user register address +#define I2C_USER_REG_ADDR 1 //I2C User specific register address by using + //the first I2C data as the register + //address + +// I2C SAL used module. Please set the I2C module flag to 1 to enable the related +// I2C module functions. +#define I2C0_USED 1 +#define I2C1_USED 1 +#define I2C2_USED 1 +#define I2C3_USED 1 +//================= I2C CONFIGURATION END =================== + + +//================= I2C HAL START ========================== +// I2C debug output +#define I2C_PREFIX "RTL8195A[i2c]: " +#define I2C_PREFIX_LVL " [i2c_DBG]: " + +typedef enum _I2C_DBG_LVL_ { + HAL_I2C_LVL = 0x01, + SAL_I2C_LVL = 0x02, + VERI_I2C_LVL = 0x03, +}I2C_DBG_LVL,*PI2C_DBG_LVL; + +#ifdef CONFIG_DEBUG_LOG +#ifdef CONFIG_DEBUG_LOG_I2C_HAL +#define DBG_I2C_LOG_PERD 100 + + #define I2CDBGLVL 0xFF + #define DBG_8195A_I2C(...) do{ \ + _DbgDump("\r"I2C_PREFIX __VA_ARGS__);\ + }while(0) + + #define DBG_8195A_I2C_LVL(LVL,...) do{\ + if (LVL&I2CDBGLVL){\ + _DbgDump("\r"I2C_PREFIX_LVL __VA_ARGS__);\ + }\ + }while(0) +#else + #define DBG_I2C_LOG_PERD 100 + #define DBG_8195A_I2C(...) + #define DBG_8195A_I2C_LVL(...) +#endif +#else + #define DBG_I2C_LOG_PERD 100 + #define DBG_8195A_I2C(...) + #define DBG_8195A_I2C_LVL(...) +#endif + +//====================================================== +// I2C HAL related enumeration +// I2C Module Selection +typedef enum _I2C_MODULE_SEL_ { + I2C0_SEL = 0x0, + I2C1_SEL = 0x1, + I2C2_SEL = 0x2, + I2C3_SEL = 0x3, +}I2C_MODULE_SEL,*PI2C_MODULE_SEL; + +// I2C HAL initial data structure +typedef struct _HAL_I2C_INIT_DAT_ { + u8 I2CIdx; //I2C index used + u8 I2CEn; //I2C module enable + u8 I2CMaster; //Master or Slave mode + u8 I2CAddrMod; //I2C addressing mode(7-bit, 10-bit) + + u8 I2CSpdMod; //I2C speed mode(Standard, Fast, High) + u8 I2CSetup; //I2C SDA setup time + u8 I2CRXTL; //I2C RX FIFO Threshold + u8 I2CTXTL; //I2C TX FIFO Threshold + + u8 I2CBusLd; //I2C bus load (pf) for high speed mode + u8 I2CReSTR; //I2C restart support + u8 I2CGC; //I2C general support + u8 I2CStartB; //I2C start byte support + + u8 I2CSlvNoAck; //I2C slave no ack support + u8 I2CDMACtrl; //I2C DMA feature support + u8 I2CCmd; //I2C Command + u8 I2CDataLen; //I2C Data Length + + u8 I2CSlvAckGC; //I2C slave acks to General Call + u8 I2CStop; //I2C issues STOP bit or not + u16 RSVD0; + + u8 *I2CRWData; //I2C Read/Write data pointer + + u16 I2CIntrMSK; //I2C Interrupt Mask + u16 I2CIntrClr; //I2C Interrupt register to clear + + u16 I2CAckAddr; //I2C target address in I2C Master mode, + //ack address in I2C Slave mode + u16 I2CSdaHd; //I2C SDA hold time + + u32 I2CClk; //I2C bus clock (in kHz) + + u8 I2CTxDMARqLv; //I2C TX DMA Empty Level + u8 I2CRxDMARqLv; //I2C RX DMA Full Level + u16 RSVD1; //Reserved +}HAL_I2C_INIT_DAT,*PHAL_I2C_INIT_DAT; + +// I2C HAL Operations +typedef struct _HAL_I2C_OP_ { + HAL_Status (*HalI2CInit) (VOID *Data); //HAL I2C initialization + HAL_Status (*HalI2CDeInit) (VOID *Data); //HAL I2C de-initialization + HAL_Status (*HalI2CSend) (VOID *Data); //HAL I2C send + u8 (*HalI2CReceive) (VOID *Data); //HAL I2C receive + HAL_Status (*HalI2CEnable) (VOID *Data); //HAL I2C enable module + HAL_Status (*HalI2CIntrCtrl) (VOID *Data); //HAL I2C interrupt control + u32 (*HalI2CReadReg) (VOID *Data, u8 I2CReg);//HAL I2C read register + HAL_Status (*HalI2CWriteReg) (VOID *Data, u8 I2CReg, u32 RegVal);//HAL I2C write register + HAL_Status (*HalI2CSetCLK) (VOID *Data); //HAL I2C set bus clock + HAL_Status (*HalI2CMassSend) (VOID *Data); //HAL I2C mass send + HAL_Status (*HalI2CClrIntr) (VOID *Data); //HAL I2C clear interrupts + HAL_Status (*HalI2CClrAllIntr) (VOID *Data); //HAL I2C clear all interrupts + HAL_Status (*HalI2CDMACtrl) (VOID *Data); //HAL I2C DMA control +}HAL_I2C_OP, *PHAL_I2C_OP; +//================= I2C HAL END =========================== + + +//================= I2C SAL START ========================== +//I2C SAL Macros + +//====================================================== +// I2C SAL related enumerations +// I2C Extend Features +typedef enum _I2C_EXD_SUPPORT_{ + I2C_EXD_RESTART = 0x1, //BIT_0, RESTART bit + I2C_EXD_GENCALL = 0x2, //BIT_1, Master generates General Call. All "send" operations generate General Call addresss + I2C_EXD_STARTB = 0x4, //BIT_2, Using START BYTE, instead of START Bit + I2C_EXD_SLVNOACK = 0x8, //BIT_3, Slave no ack to master + I2C_EXD_BUS400PF = 0x10, //BIT_4, I2C bus loading is 400pf + I2C_EXD_SLVACKGC = 0x20, //BIT_5, Slave acks to a General Call + I2C_EXD_USER_REG = 0x40, //BIT_6, Using User Register Address + I2C_EXD_USER_TWOB = 0x80, //BIT_7, User Register Address is 2-byte + I2C_EXD_MTR_ADDR_RTY= 0x100, //BIT_8, Master retries to send start condition and Slave address when the slave doesn't ack + // the address. + I2C_EXD_MTR_ADDR_UPD= 0x200, //BIT_9, Master dynamically updates slave address + I2C_EXD_MTR_HOLD_BUS= 0x400, //BIT_10, Master doesn't generate STOP when the FIFO is empty. This would make Master hold + // the bus. +}I2C_EXD_SUPPORT,*PI2C_EXD_SUPPORT; + +// I2C operation type +typedef enum _I2C_OP_TYPE_ { + I2C_POLL_TYPE = 0x0, + I2C_DMA_TYPE = 0x1, + I2C_INTR_TYPE = 0x2, +}I2C_OP_TYPE, *PI2C_OP_TYPE; + +// I2C pinmux selection +typedef enum _I2C_PINMUX_ { + I2C_PIN_S0 = 0x0, + I2C_PIN_S1 = 0x1, + I2C_PIN_S2 = 0x2, + I2C_PIN_S3 = 0x3, //Only valid for I2C0 and I2C3 +}I2C_PINMUX, *PI2C_PINMUX; + +// I2C module status +typedef enum _I2C_MODULE_STATUS_ { + I2C_DISABLE = 0x0, + I2C_ENABLE = 0x1, +}I2C_MODULE_STATUS, *PI2C_MODULE_STATUS; + +// I2C device status +typedef enum _I2C_Device_STATUS_ { + I2C_STS_UNINITIAL = 0x00, + I2C_STS_INITIALIZED = 0x01, + I2C_STS_IDLE = 0x02, + + I2C_STS_TX_READY = 0x03, + I2C_STS_TX_ING = 0x04, + + I2C_STS_RX_READY = 0x05, + I2C_STS_RX_ING = 0x06, + + I2C_STS_ERROR = 0x10, + I2C_STS_TIMEOUT = 0x11, +}I2C_Device_STATUS, *PI2C_Device_STATUS; + +// I2C feature status +typedef enum _I2C_FEATURE_STATUS_{ + I2C_FEATURE_DISABLED = 0, + I2C_FEATURE_ENABLED = 1, +}I2C_FEATURE_STATUS,*PI2C_FEATURE_STATUS; + +// I2C device mode +typedef enum _I2C_DEV_MODE_ { + I2C_SLAVE_MODE = 0x0, + I2C_MASTER_MODE = 0x1, +}I2C_DEV_MODE, *PI2C_DEV_MODE; + +// I2C Bus Transmit/Receive +typedef enum _I2C_DIRECTION_ { + I2C_ONLY_TX = 0x1, + I2C_ONLY_RX = 0x2, + I2C_TXRX = 0x3, +}I2C_DIRECTION, *PI2C_DIRECTION; + +//I2C DMA module number +typedef enum _I2C_DMA_MODULE_SEL_ { + I2C_DMA_MODULE_0 = 0x0, + I2C_DMA_MODULE_1 = 0x1 +}I2C_DMA_MODULE_SEL, *PI2C_DMA_MODULE_SEL; + +// I2C0 DMA peripheral number +typedef enum _I2C0_DMA_PERI_NUM_ { + I2C0_DMA_TX_NUM = 0x8, + I2C0_DMA_RX_NUM = 0x9, +}I2C0_DMA_PERI_NUM,*PI2C0_DMA_PERI_NUM; + +// I2C1 DMA peripheral number +typedef enum _I2C1_DMA_PERI_NUM_ { + I2C1_DMA_TX_NUM = 0xA, + I2C1_DMA_RX_NUM = 0xB, +}I2C1_DMA_PERI_NUM,*PI2C1_DMA_PERI_NUM; + +// I2C0 DMA module used +typedef enum _I2C0_DMA_MODULE_ { + I2C0_DMA0 = 0x0, + I2C0_DMA1 = 0x1, +}I2C0_DMA_MODULE,*PI2C0_DMA_MODULE; + +// I2C0 DMA module used +typedef enum _I2C1_DMA_MODULE_ { + I2C1_DMA0 = 0x0, + I2C1_DMA1 = 0x1, +}I2C1_DMA_MODULE,*PI2C1_DMA_MODULE; + +// I2C command type +typedef enum _I2C_COMMAND_TYPE_ { + I2C_WRITE_CMD = 0x0, + I2C_READ_CMD = 0x1, +}I2C_COMMAND_TYPE,*PI2C_COMMAND_TYPE; + +// I2C STOP BIT +typedef enum _I2C_STOP_TYPE_ { + I2C_STOP_DIS = 0x0, + I2C_STOP_EN = 0x1, +}I2C_STOP_TYPE, *PI2C_STOP_TYPE; + +// I2C error type +typedef enum _I2C_ERR_TYPE_ { + I2C_ERR_RX_UNDER = 0x01, //I2C RX FIFO Underflow + I2C_ERR_RX_OVER = 0x02, //I2C RX FIFO Overflow + I2C_ERR_TX_OVER = 0x04, //I2C TX FIFO Overflow + I2C_ERR_TX_ABRT = 0x08, //I2C TX terminated + I2C_ERR_SLV_TX_NACK = 0x10, //I2C slave transmission terminated by master NACK, + //but there are data in slave TX FIFO + I2C_ERR_USER_REG_TO = 0x20, + + I2C_ERR_RX_CMD_TO = 0x21, + I2C_ERR_RX_FF_TO = 0x22, + I2C_ERR_TX_CMD_TO = 0x23, + I2C_ERR_TX_FF_TO = 0x24, + + I2C_ERR_TX_ADD_TO = 0x25, + I2C_ERR_RX_ADD_TO = 0x26, +}I2C_ERR_TYPE, *PI2C_ERR_TYPE; + +// I2C Time Out type +typedef enum _I2C_TIMEOUT_TYPE_ { + I2C_TIMEOOUT_DISABLE = 0x00, + I2C_TIMEOOUT_ENDLESS = 0xFFFFFFFF, +}I2C_TIMEOUT_TYPE, *PI2C_TIMEOUT_TYPE; + +//====================================================== +// SAL I2C related data structures +// I2C user callback adapter +typedef struct _SAL_I2C_USERCB_ADPT_ { + VOID (*USERCB) (VOID *Data); + u32 USERData; +}SAL_I2C_USERCB_ADPT, *PSAL_I2C_USERCB_ADPT; + +// I2C user callback structure +typedef struct _SAL_I2C_USER_CB_ { + PSAL_I2C_USERCB_ADPT pTXCB; //I2C Transmit Callback + PSAL_I2C_USERCB_ADPT pTXCCB; //I2C Transmit Complete Callback + PSAL_I2C_USERCB_ADPT pRXCB; //I2C Receive Callback + PSAL_I2C_USERCB_ADPT pRXCCB; //I2C Receive Complete Callback + PSAL_I2C_USERCB_ADPT pRDREQCB; //I2C Read Request Callback + PSAL_I2C_USERCB_ADPT pERRCB; //I2C Error Callback + PSAL_I2C_USERCB_ADPT pDMATXCB; //I2C DMA Transmit Callback + PSAL_I2C_USERCB_ADPT pDMATXCCB; //I2C DMA Transmit Complete Callback + PSAL_I2C_USERCB_ADPT pDMARXCB; //I2C DMA Receive Callback + PSAL_I2C_USERCB_ADPT pDMARXCCB; //I2C DMA Receive Complete Callback + PSAL_I2C_USERCB_ADPT pGENCALLCB; //I2C General Call Callback +}SAL_I2C_USER_CB, *PSAL_I2C_USER_CB; + +// I2C Transmit Buffer +typedef struct _SAL_I2C_TRANSFER_BUF_ { + u16 DataLen; //I2C Transmfer Length + u16 TargetAddr; //I2C Target Address. It's only valid in Master Mode. + u32 RegAddr; //I2C Register Address. It's only valid in Master Mode. + u32 RSVD; // + u8 *pDataBuf; //I2C Transfer Buffer Pointer +}SAL_I2C_TRANSFER_BUF,*PSAL_I2C_TRANSFER_BUF; + +typedef struct _SAL_I2C_DMA_USER_DEF_ { + u8 TxDatSrcWdth; + u8 TxDatDstWdth; + u8 TxDatSrcBstSz; + u8 TxDatDstBstSz; + u8 TxChNo; + u8 RSVD0; + u16 RSVD1; + u8 RxDatSrcWdth; + u8 RxDatDstWdth; + u8 RxDatSrcBstSz; + u8 RxDatDstBstSz; + u8 RxChNo; + u8 RSVD2; + u16 RSVD3; +}SAL_I2C_DMA_USER_DEF, *PSAL_I2C_DMA_USER_DEF; + +// RTK I2C OP +typedef struct _RTK_I2C_OP_ { + HAL_Status (*Init) (VOID *Data); + HAL_Status (*DeInit) (VOID *Data); + HAL_Status (*Send) (VOID *Data); + HAL_Status (*Receive) (VOID *Data); + HAL_Status (*IoCtrl) (VOID *Data); + HAL_Status (*PowerCtrl) (VOID *Data); +}RTK_I2C_OP, *PRTK_I2C_OP; + +// Software API Level I2C Handler +typedef struct _SAL_I2C_HND_ { + u8 DevNum; //I2C device number + u8 PinMux; //I2C pin mux seletion + u8 OpType; //I2C operation type selection + volatile u8 DevSts; //I2C device status + + u8 I2CMaster; //I2C Master or Slave mode + u8 I2CAddrMod; //I2C 7-bit or 10-bit mode + u8 I2CSpdMod; //I2C SS/ FS/ HS speed mode + u8 I2CAckAddr; //I2C target address in Master + //mode or ack address in Slave + //mode + + u16 I2CClk; //I2C bus clock + u8 MasterRead; //I2C Master Read Supported, + //An Address will be sent before + //read data back. + + u8 I2CDmaSel; //I2C DMA module select + // 0 for DMA0, + // 1 for DMA1 + u8 I2CTxDMARqLv; //I2C TX DMA Empty Level + u8 I2CRxDMARqLv; //I2C RX DMA Full Level + u16 RSVD0; //Reserved + + u32 AddRtyTimeOut; //I2C TimeOut Value for master send address retry + //(Originally Reserved.) + + u32 I2CExd; //I2C extended options: + //bit 0: I2C RESTART supported, + // 0 for NOT supported, + // 1 for supported + //bit 1: I2C General Call supported + // 0 for NOT supported, + // 1 for supported + //bit 2: I2C START Byte supported + // 0 for NOT supported, + // 1 for supported + //bit 3: I2C Slave-No-Ack + // supported + // 0 for NOT supported, + // 1 for supported + //bit 4: I2C bus loading, + // 0 for 100pf, + // 1 for 400pf + //bit 5: I2C slave ack to General + // Call + //bit 6: I2C User register address + //bit 7: I2C 2-Byte User register + // address + //bit 8: I2C slave address no ack retry, + // It's only for Master mode, + // when slave doesn't ack the + // address + //bit 31~bit 8: Reserved + u32 ErrType; // + u32 TimeOut; //I2C IO Timeout count, in ms + + PHAL_I2C_INIT_DAT pInitDat; //Pointer to I2C initial data struct + PSAL_I2C_TRANSFER_BUF pTXBuf; //Pointer to I2C TX buffer + PSAL_I2C_TRANSFER_BUF pRXBuf; //Pointer to I2C RX buffer + PSAL_I2C_USER_CB pUserCB; //Pointer to I2C User Callback + PSAL_I2C_DMA_USER_DEF pDMAConf; //Pointer to I2C User Define DMA config +}SAL_I2C_HND, *PSAL_I2C_HND; + + + +//====================================================== +// I2C SAL Function Prototypes + +// For checking I2C input index valid or not +static inline HAL_Status +RtkI2CIdxChk( + IN u8 I2CIdx +) +{ + if (I2CIdx > I2C3_SEL) + return HAL_ERR_UNKNOWN; + + return HAL_OK; +} +#if 0 +//For checking I2C operation type valid or not +static inline HAL_Status +RtkI2COpTypeChk( + IN VOID *Data +) +{ + PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data; + + if (pSalI2CHND->OpType == I2C_POLL_TYPE) + return HAL_ERR_UNKNOWN; + + if (pSalI2CHND->OpType == I2C_DMA_TYPE) + return HAL_ERR_UNKNOWN; + + if (pSalI2CHND->OpType == I2C_INTR_TYPE) + return HAL_ERR_UNKNOWN; + + pSalI2CHND = pSalI2CHND; + + return HAL_OK; +} +#endif +//For checking I2C DMA available or not +static inline HAL_Status +RtkI2CDMAChk( + IN VOID *Data +) +{ + PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data; + + if (pSalI2CHND->OpType == I2C_DMA_TYPE) { + if (pSalI2CHND->DevNum >= I2C2_SEL) + return HAL_ERR_UNKNOWN; + } + else { + return HAL_ERR_UNKNOWN; + } + + return HAL_OK; +} + +//For checking I2C DMA available or not +static inline HAL_Status +RtkI2CDMAInitChk( + IN VOID *Data +) +{ + PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data; + + if (pSalI2CHND->OpType != I2C_DMA_TYPE) { + return HAL_ERR_UNKNOWN; + } + else { + return HAL_OK; + } + +} + +//====================================================== +//SAL I2C management function prototype +_LONG_CALL_ROM_ HAL_Status RtkI2CLoadDefault(IN VOID *Data); +_LONG_CALL_ROM_ HAL_Status RtkI2CInit(IN VOID *Data); +_LONG_CALL_ROM_ HAL_Status RtkI2CDeInit(IN VOID *Data); +_LONG_CALL_ROM_ HAL_Status RtkI2CSend(IN VOID *Data); +_LONG_CALL_ROM_ HAL_Status RtkI2CReceive(IN VOID *Data); +_LONG_CALL_ROM_ VOID RtkSalI2COpInit(IN VOID *Data); +_LONG_CALL_ROM_ HAL_Status RtkI2CSendUserAddr(IN VOID *Data,IN u8 MtrWr); +_LONG_CALL_ROM_ HAL_Status RtkI2CIoCtrl(IN VOID *Data); +_LONG_CALL_ROM_ HAL_Status RtkI2CPowerCtrl(IN VOID *Data); +_LONG_CALL_ HAL_Status RtkI2CInitForPS(IN VOID *Data); +_LONG_CALL_ HAL_Status RtkI2CDeInitForPS(IN VOID *Data); +_LONG_CALL_ HAL_Status RtkI2CDisablePS(IN VOID *Data); +_LONG_CALL_ HAL_Status RtkI2CEnablePS(IN VOID *Data); +//================= I2C SAL END =========================== + + +//================= I2C SAL MANAGEMENT START ================= +// I2C SAL management macros +#define SAL_USER_CB_NUM (sizeof(SAL_I2C_USER_CB) / sizeof(PSAL_I2C_USERCB_ADPT)) + +//====================================================== +// I2C SAL management data structures +// I2C SAL handle private +typedef struct _SAL_I2C_HND_PRIV_ { + VOID **ppSalI2CHnd; //Pointer to SAL_I2C_HND pointer + SAL_I2C_HND SalI2CHndPriv; //Private SAL_I2C_HND +}SAL_I2C_HND_PRIV, *PSAL_I2C_HND_PRIV; + +//I2C SAL management adapter +typedef struct _SAL_I2C_MNGT_ADPT_ { + PSAL_I2C_HND_PRIV pSalHndPriv; //Pointer to SAL_I2C_HND + PHAL_I2C_INIT_DAT pHalInitDat; //Pointer to HAL I2C initial data( HAL_I2C_INIT_DAT ) + PHAL_I2C_OP pHalOp; //Pointer to HAL I2C operation( HAL_I2C_OP ) + VOID (*pHalOpInit)(VOID*); //Pointer to HAL I2C initialize function + PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE ) + PSAL_I2C_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_I2C_USER_CB ) + volatile u32 MstRDCmdCnt; //Used for Master Read command count + volatile u32 InnerTimeOut; //Used for SAL internal timeout count + VOID (*pSalIrqFunc)(VOID*); //Used for SAL I2C interrupt function + + PSAL_I2C_DMA_USER_DEF pDMAConf; //Pointer to I2C User Define DMA config + PHAL_GDMA_ADAPTER pHalTxGdmaAdp; //Pointer to HAL_GDMA_ADAPTER + PHAL_GDMA_ADAPTER pHalRxGdmaAdp; //Pointer to HAL_GDMA_ADAPTER + PHAL_GDMA_OP pHalGdmaOp; //Pointer to HAL_GDMA_OP + VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL I2C initialize function + PIRQ_HANDLE pIrqTxGdmaHnd; //Pointer to IRQ handler for Tx GDMA + PIRQ_HANDLE pIrqRxGdmaHnd; //Pointer to IRQ handler for Rx GDMA + VOID (*pSalDMATxIrqFunc)(VOID*); //Used for SAL I2C interrupt function + VOID (*pSalDMARxIrqFunc)(VOID*); //Used for SAL I2C interrupt function + u32 RSVD; //Reserved +}SAL_I2C_MNGT_ADPT, *PSAL_I2C_MNGT_ADPT; + +//====================================================== +//SAL I2C management function prototype +PSAL_I2C_MNGT_ADPT RtkI2CGetMngtAdpt(IN u8 I2CIdx); +HAL_Status RtkI2CFreeMngtAdpt(IN PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt); +PSAL_I2C_HND RtkI2CGetSalHnd(IN u8 I2CIdx); +HAL_Status RtkI2CFreeSalHnd(IN PSAL_I2C_HND pSalI2CHND); +u32 RtkSalI2CSts(IN VOID *Data); + +extern _LONG_CALL_ VOID I2CISRHandle(IN VOID *Data); +extern _LONG_CALL_ VOID I2CTXGDMAISRHandle(IN VOID *Data); +extern _LONG_CALL_ VOID I2CRXGDMAISRHandle(IN VOID *Data); +extern HAL_Status I2CIsTimeout (IN u32 StartCount, IN u32 TimeoutCnt); +extern HAL_TIMER_OP HalTimerOp; +//====================================================== +// Function Prototypes +_LONG_CALL_ VOID HalI2COpInit(IN VOID *Data); +//================= I2C SAL MANAGEMENT END ================== + +//================= Rtl8195a I2C V02 function prototype ============ +_LONG_CALL_ VOID HalI2COpInitV02(IN VOID *Data); +_LONG_CALL_ VOID I2CISRHandleV02(IN VOID *Data); +_LONG_CALL_ HAL_Status RtkI2CSendV02(IN VOID *Data); +_LONG_CALL_ HAL_Status RtkI2CReceiveV02(IN VOID *Data); +_LONG_CALL_ VOID RtkSalI2COpInitV02(IN VOID *Data); +//================= Rtl8195a I2C V02 function prototype END========== + +//====================================================== +//SAL I2C patch function prototype +HAL_Status RtkI2CSend_Patch(IN VOID *Data); +HAL_Status RtkI2CReceive_Patch(IN VOID *Data); +VOID HalI2COpInit_Patch(IN VOID *Data); +VOID I2CISRHandle_Patch(IN VOID *Data); + +#ifndef CONFIG_RELEASE_BUILD_LIBRARIES +#define RtkI2CSend RtkI2CSend_Patch +#define RtkI2CReceive RtkI2CReceive_Patch +#endif +HAL_Status RtkI2CSend_Patch(IN VOID *Data); +HAL_Status RtkI2CReceive_Patch(IN VOID *Data); +//================= I2C SAL END =========================== + +#endif //#ifndef _HAL_I2C_H_ diff --git a/lib/fwlib/hal_i2s.h b/lib/fwlib/hal_i2s.h new file mode 100644 index 0000000..92eef0e --- /dev/null +++ b/lib/fwlib/hal_i2s.h @@ -0,0 +1,347 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_I2S_H_ +#define _HAL_I2S_H_ + +#include "rtl8195a_i2s.h" + +/* User Define Flags */ + +#define I2S_MAX_ID 1 // valid I2S index 0 ~ I2S_MAX_ID + +/**********************************************************************/ +/* I2S HAL initial data structure */ +typedef struct _HAL_I2S_INIT_DAT_ { + u8 I2SIdx; /*I2S index used*/ + u8 I2SEn; /*I2S module enable tx/rx/tx+rx*/ + u8 I2SMaster; /*I2S Master or Slave mode*/ + u8 I2SWordLen; /*I2S Word length 16 or 24bits*/ + + u8 I2SChNum; /*I2S Channel number mono or stereo*/ + u8 I2SPageNum; /*I2S Page Number 2~4*/ + u16 I2SPageSize; /*I2S page Size 1~4096 word*/ + + u8 *I2STxData; /*I2S Tx data pointer*/ + + u8 *I2SRxData; /*I2S Rx data pointer*/ + + u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/ + u32 I2STxIntrClr; /*I2S Tx Interrupt register to clear */ + + u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/ + u32 I2SRxIntrClr; /*I2S Rx Interrupt register to clear*/ + + u16 I2STxIdx; /*I2S TX page index */ + u16 I2SRxIdx; /*I2S RX page index */ + + u16 I2SHWTxIdx; /*I2S HW TX page index */ + u16 I2SHWRxIdx; /*I2S HW RX page index */ + + + u16 I2SRate; /*I2S sample rate*/ + u8 I2STRxAct; /*I2S tx rx act*/ +}HAL_I2S_INIT_DAT, *PHAL_I2S_INIT_DAT; + +/**********************************************************************/ +/* I2S Data Structures */ +/* I2S Module Selection */ +typedef enum _I2S_MODULE_SEL_ { + I2S0_SEL = 0x0, + I2S1_SEL = 0x1, +}I2S_MODULE_SEL,*PI2S_MODULE_SEL; +/* +typedef struct _HAL_I2S_ADAPTER_ { + u32 Enable:1; + I2S_CTL_REG I2sCtl; + I2S_SETTING_REG I2sSetting; + u32 abc; + u8 I2sIndex; +}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER; +*/ +/* I2S HAL Operations */ +typedef struct _HAL_I2S_OP_ { + RTK_STATUS (*HalI2SInit) (VOID *Data); + RTK_STATUS (*HalI2SDeInit) (VOID *Data); + RTK_STATUS (*HalI2STx) (VOID *Data, u8 *pBuff); + RTK_STATUS (*HalI2SRx) (VOID *Data, u8 *pBuff); + RTK_STATUS (*HalI2SEnable) (VOID *Data); + RTK_STATUS (*HalI2SIntrCtrl) (VOID *Data); + u32 (*HalI2SReadReg) (VOID *Data, u8 I2SReg); + RTK_STATUS (*HalI2SSetRate) (VOID *Data); + RTK_STATUS (*HalI2SSetWordLen) (VOID *Data); + RTK_STATUS (*HalI2SSetChNum) (VOID *Data); + RTK_STATUS (*HalI2SSetPageNum) (VOID *Data); + RTK_STATUS (*HalI2SSetPageSize) (VOID *Data); + + RTK_STATUS (*HalI2SClrIntr) (VOID *Data); + RTK_STATUS (*HalI2SClrAllIntr) (VOID *Data); + RTK_STATUS (*HalI2SDMACtrl) (VOID *Data); +/* + VOID (*HalI2sOnOff)(VOID *Data); + BOOL (*HalI2sInit)(VOID *Data); + BOOL (*HalI2sSetting)(VOID *Data); + BOOL (*HalI2sEn)(VOID *Data); + BOOL (*HalI2sIsrEnAndDis) (VOID *Data); + BOOL (*HalI2sDumpReg)(VOID *Data); + BOOL (*HalI2s)(VOID *Data); +*/ +}HAL_I2S_OP, *PHAL_I2S_OP; + + +/**********************************************************************/ + +/* I2S Pinmux Selection */ +#if 0 +typedef enum _I2S0_PINMUX_ { + I2S0_TO_S0 = 0x0, + I2S0_TO_S1 = 0x1, + I2S0_TO_S2 = 0x2, +}I2S0_PINMUX, *PI2S0_PINMUX; + +typedef enum _I2S1_PINMUX_ { + I2S1_TO_S0 = 0x0, + I2S1_TO_S1 = 0x1, +}I2S1_PINMUX, *PI2S1_PINMUX; +#endif + +typedef enum _I2S_PINMUX_ { + I2S_S0 = 0, + I2S_S1 = 1, + I2S_S2 = 2, + I2S_S3 = 3 +}I2S_PINMUX, *PI2S_PINMUX; + + +/* I2S Module Status */ +typedef enum _I2S_MODULE_STATUS_ { + I2S_DISABLE = 0x0, + I2S_ENABLE = 0x1, +}I2S_MODULE_STATUS, *PI2S_MODULE_STATUS; + + +/* I2S Device Status */ +typedef enum _I2S_Device_STATUS_ { + I2S_STS_UNINITIAL = 0x00, + I2S_STS_INITIALIZED = 0x01, + I2S_STS_IDLE = 0x02, + + I2S_STS_TX_READY = 0x03, + I2S_STS_TX_ING = 0x04, + + I2S_STS_RX_READY = 0x05, + I2S_STS_RX_ING = 0x06, + + I2S_STS_TRX_READY = 0x07, + I2S_STS_TRX_ING = 0x08, + + I2S_STS_ERROR = 0x09, +}I2S_Device_STATUS, *PI2S_Device_STATUS; + + +/* I2S Feature Status */ +typedef enum _I2S_FEATURE_STATUS_{ + I2S_FEATURE_DISABLED = 0, + I2S_FEATURE_ENABLED = 1, +}I2S_FEATURE_STATUS,*PI2S_FEATURE_STATUS; + +/* I2S Device Mode */ +typedef enum _I2S_DEV_MODE_ { + I2S_MASTER_MODE = 0x0, + I2S_SLAVE_MODE = 0x1 +}I2S_DEV_MODE, *PI2S_DEV_MODE; + +/* I2S Word Length */ +typedef enum _I2S_WORD_LEN_ { + I2S_WL_16 = 0x0, + I2S_WL_24 = 0x1, +}I2S_WORD_LEN, *PI2S_WORD_LEN; + +/* I2S Bus Transmit/Receive */ +typedef enum _I2S_DIRECTION_ { + I2S_ONLY_RX = 0x0, + I2S_ONLY_TX = 0x1, + I2S_TXRX = 0x2 +}I2S_DIRECTION, *PI2S_DIRECTION; + +/* I2S Channel number */ +typedef enum _I2S_CH_NUM_ { + I2S_CH_STEREO = 0x0, + I2S_CH_RSVD = 0x1, + I2S_CH_MONO = 0x2 +}I2S_CH_NUM, *PI2S_CH_NUM; + +/* I2S Page number */ +typedef enum _I2S_PAGE_NUM_ { + I2S_1PAGE = 0x0, + I2S_2PAGE = 0x1, + I2S_3PAGE = 0x2, + I2S_4PAGE = 0x3 +}I2S_PAGE_NUM, *PI2S_PAGE_NUM; + +/* I2S Sample rate*/ +typedef enum _I2S_SAMPLE_RATE_ { + I2S_SR_8KHZ = 0x00, // /12 + I2S_SR_16KHZ = 0x01, // /6 + I2S_SR_24KHZ = 0x02, // /4 + I2S_SR_32KHZ = 0x03, // /3 + I2S_SR_48KHZ = 0x05, // /2 + I2S_SR_96KHZ = 0x06, // x1, base 96kHz + I2S_SR_7p35KHZ = 0x10, + I2S_SR_11p02KHZ = 0x11, + I2S_SR_22p05KHZ = 0x12, + I2S_SR_29p4KHZ = 0x13, + I2S_SR_44p1KHZ = 0x15, + I2S_SR_88p2KHZ = 0x16 // x1, base 88200Hz +}I2S_SAMPLE_RATE, *PI2S_SAMPLE_RATE; + +/* I2S TX interrupt mask/status */ +typedef enum _I2S_TX_IMR_ { + I2S_TX_INT_PAGE0_OK = (1<<0), + I2S_TX_INT_PAGE1_OK = (1<<1), + I2S_TX_INT_PAGE2_OK = (1<<2), + I2S_TX_INT_PAGE3_OK = (1<<3), + I2S_TX_INT_FULL = (1<<4), + I2S_TX_INT_EMPTY = (1<<5) +} I2S_TX_IMR, *PI2S_TX_IMR; + +/* I2S RX interrupt mask/status */ +typedef enum _I2S_RX_IMR_ { + I2S_RX_INT_PAGE0_OK = (1<<0), + I2S_RX_INT_PAGE1_OK = (1<<1), + I2S_RX_INT_PAGE2_OK = (1<<2), + I2S_RX_INT_PAGE3_OK = (1<<3), + I2S_RX_INT_EMPTY = (1<<4), + I2S_RX_INT_FULL = (1<<5) +} I2S_RX_IMR, *PI2S_RX_IMR; + +/* I2S User Callbacks */ +typedef struct _SAL_I2S_USER_CB_{ + VOID (*TXCB) (VOID *Data); + VOID (*TXCCB) (VOID *Data); + VOID (*RXCB) (VOID *Data); + VOID (*RXCCB) (VOID *Data); + VOID (*RDREQCB) (VOID *Data); + VOID (*ERRCB) (VOID *Data); + VOID (*GENCALLCB) (VOID *Data); +}SAL_I2S_USER_CB,*PSAL_I2S_USER_CB; + +typedef struct _I2S_USER_CB_{ + VOID (*TxCCB)(uint32_t id, char *pbuf); + u32 TxCBId; + VOID (*RxCCB)(uint32_t id, char *pbuf); + u32 RxCBId; +}I2S_USER_CB,*PI2S_USER_CB; + +/* Software API Level I2S Handler */ +typedef struct _HAL_I2S_ADAPTER_{ + u8 DevNum; //I2S device number + u8 PinMux; //I2S pin mux seletion + u8 RSVD0; //Reserved + volatile u8 DevSts; //I2S device status + + u32 RSVD2; //Reserved + u32 I2SExd; //I2S extended options: + //bit 0: I2C RESTART supported, + // 0 for NOT supported, + // 1 for supported + //bit 1: I2C General Call supported + // 0 for NOT supported, + // 1 for supported + //bit 2: I2C START Byte supported + // 0 for NOT supported, + // 1 for supported + //bit 3: I2C Slave-No-Ack + // supported + // 0 for NOT supported, + // 1 for supported + //bit 4: I2C bus loading, + // 0 for 100pf, + // 1 for 400pf + //bit 5: I2C slave ack to General + // Call + //bit 6: I2C User register address + //bit 7: I2C 2-Byte User register + // address + //bit 31~bit 8: Reserved + u32 ErrType; // + u32 TimeOut; //I2S IO Timeout count + + PHAL_I2S_INIT_DAT pInitDat; //Pointer to I2S initial data struct + I2S_USER_CB UserCB; //Pointer to I2S User Callback + IRQ_HANDLE IrqHandle; // Irq Handler + + u32* TxPageList[4]; // The Tx DAM buffer: pointer of each page + u32* RxPageList[4]; // The Tx DAM buffer: pointer of each page +}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER; + +typedef struct _HAL_I2S_DEF_SETTING_{ + u8 I2SMaster; // Master or Slave mode + u8 DevSts; //I2S device status + u8 I2SChNum; //I2S Channel number mono or stereo + u8 I2SPageNum; //I2S Page number 2~4 + u8 I2STRxAct; //I2S tx rx act, tx only or rx only or tx+rx + u8 I2SWordLen; //I2S Word length 16bit or 24bit + u16 I2SPageSize; //I2S Page size 1~4096 word + + u16 I2SRate; //I2S sample rate 8k ~ 96khz + + u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/ + u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/ +}HAL_I2S_DEF_SETTING, *PHAL_I2S_DEF_SETTING; + + + +/**********************************************************************/ +HAL_Status +RtkI2SLoadDefault(IN VOID *Adapter, IN VOID *Setting); + +HAL_Status +RtkI2SInit(IN VOID *Data); + +HAL_Status +RtkI2SDeInit(IN VOID *Data); + +HAL_Status +RtkI2SEnable(IN VOID *Data); + +HAL_Status +RtkI2SDisable(IN VOID *Data); + +extern HAL_Status +HalI2SInit( IN VOID *Data); + +extern VOID +HalI2SDeInit( IN VOID *Data); + +extern HAL_Status +HalI2SDisable( IN VOID *Data); + +extern HAL_Status +HalI2SEnable( IN VOID *Data); + + + + +/**********************************************************************/ + + +VOID I2S0ISRHandle(VOID *Data); +VOID I2S1ISRHandle(VOID *Data); + + +/**********************************************************************/ + +VOID HalI2SOpInit( + IN VOID *Data +); + + +#endif + diff --git a/lib/fwlib/hal_irqn.h b/lib/fwlib/hal_irqn.h new file mode 100644 index 0000000..0741358 --- /dev/null +++ b/lib/fwlib/hal_irqn.h @@ -0,0 +1,112 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_IRQN_H_ +#define _HAL_IRQN_H_ + +#define PERIPHERAL_IRQ_BASE_NUM 64 + +typedef enum _IRQn_Type_ { +#if 0 +/****** Cortex-M3 Processor Exceptions Numbers ********/ + NON_MASKABLE_INT_IRQ = -14, + HARD_FAULT_IRQ = -13, + MEM_MANAGE_FAULT_IRQ = -12, + BUS_FAULT_IRQ = -11, + USAGE_FAULT_IRQ = -10, + SVCALL_IRQ = -5, + DEBUG_MONITOR_IRQ = -4, + PENDSVC_IRQ = -2, + SYSTICK_IRQ = -1, +#else +/****** Cortex-M3 Processor Exceptions Numbers ********/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ +#endif +/****** RTL8195A Specific Interrupt Numbers ************/ + SYSTEM_ON_IRQ = 0, + WDG_IRQ = 1, + TIMER0_IRQ = 2, + TIMER1_IRQ = 3, + I2C3_IRQ = 4, + TIMER2_7_IRQ = 5, + SPI0_IRQ = 6, + GPIO_IRQ = 7, + UART0_IRQ = 8, + SPI_FLASH_IRQ = 9, + USB_OTG_IRQ = 10, + SDIO_HOST_IRQ = 11, + SDIO_DEVICE_IRQ = 12, + I2S0_PCM0_IRQ = 13, + I2S1_PCM1_IRQ = 14, + WL_DMA_IRQ = 15, + WL_PROTOCOL_IRQ = 16, + CRYPTO_IRQ = 17, + GMAC_IRQ = 18, + PERIPHERAL_IRQ = 19, + GDMA0_CHANNEL0_IRQ = 20, + GDMA0_CHANNEL1_IRQ = 21, + GDMA0_CHANNEL2_IRQ = 22, + GDMA0_CHANNEL3_IRQ = 23, + GDMA0_CHANNEL4_IRQ = 24, + GDMA0_CHANNEL5_IRQ = 25, + GDMA1_CHANNEL0_IRQ = 26, + GDMA1_CHANNEL1_IRQ = 27, + GDMA1_CHANNEL2_IRQ = 28, + GDMA1_CHANNEL3_IRQ = 29, + GDMA1_CHANNEL4_IRQ = 30, + GDMA1_CHANNEL5_IRQ = 31, + +/****** RTL8195A Peripheral Interrupt Numbers ************/ + I2C0_IRQ = 64,// 0 + 64, + I2C1_IRQ = 65,// 1 + 64, + I2C2_IRQ = 66,// 2 + 64, + SPI1_IRQ = 72,// 8 + 64, + SPI2_IRQ = 73,// 9 + 64, + UART1_IRQ = 80,// 16 + 64, + UART2_IRQ = 81,// 17 + 64, + UART_LOG_IRQ = 88,// 24 + 64, + ADC_IRQ = 89,// 25 + 64, + DAC0_IRQ = 91,// 27 + 64, + DAC1_IRQ = 92,// 28 + 64, + //RXI300_IRQ = 93// 29 + 64 + LP_EXTENSION_IRQ = 93,// 29+64 + + PTA_TRX_IRQ = 95,// 31+64 + RXI300_IRQ = 96,// 0+32 + 64 + NFC_IRQ = 97// 1+32+64 +} IRQn_Type, *PIRQn_Type; + + +typedef VOID (*HAL_VECTOR_FUN) (VOID); + +typedef enum _VECTOR_TABLE_TYPE_{ + DEDECATED_VECTRO_TABLE, + PERIPHERAL_VECTOR_TABLE +}VECTOR_TABLE_TYPE, *PVECTOR_TABLE_TYPE; + + +typedef u32 (*IRQ_FUN)(VOID *Data); + +typedef struct _IRQ_HANDLE_ { + IRQ_FUN IrqFun; + IRQn_Type IrqNum; + u32 Data; + u32 Priority; +}IRQ_HANDLE, *PIRQ_HANDLE; + + +#endif //_HAL_IRQN_H_ diff --git a/lib/fwlib/hal_mii.h b/lib/fwlib/hal_mii.h new file mode 100644 index 0000000..ede51e0 --- /dev/null +++ b/lib/fwlib/hal_mii.h @@ -0,0 +1,118 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_MII_H_ +#define _HAL_MII_H_ + +#include "rtl8195a_mii.h" + + +/** + * LOG Configurations + */ + +#define NOLOG + +#define LOG_TAG "NoTag" +#define LOG_INFO_HEADER "I" +#define LOG_DEBUG_HEADER "D" +#define LOG_ERROR_HEADER "E" +#define LOG_TEST_HEADER "T" + +#define IDENT_TWO_SPACE " " +#define IDENT_FOUR_SPACE " " + +#define LOG_INFO(...) do {\ + DiagPrintf("\r"LOG_INFO_HEADER"/"LOG_TAG": " __VA_ARGS__);\ +}while(0) + +#define LOG_DEBUG(...) do {\ + DiagPrintf("\r"LOG_DEBUG_HEADER"/"LOG_TAG": " __VA_ARGS__);\ +}while(0) + +#define LOG_ERROR(...) do {\ + DiagPrintf("\r"LOG_ERROR_HEADER"/"LOG_TAG": " __VA_ARGS__);\ +}while(0) + +#ifdef NOLOG + #define LOGI + #define LOGD + #define LOGE + #define LOGI2 + #define LOGD2 + #define LOGE2 + #define LOGI4 + #define LOGD4 + #define LOGE4 +#else + #define LOGI LOG_INFO + #define LOGD LOG_DEBUG + #define LOGE LOG_ERROR + #define LOGI2(...) LOG_INFO(IDENT_TWO_SPACE __VA_ARGS__) + #define LOGD2(...) LOG_DEBUG(IDENT_TWO_SPACE __VA_ARGS__) + #define LOGE2(...) LOG_ERROR(IDENT_TWO_SPACE __VA_ARGS__) + #define LOGI4(...) LOG_INFO(IDENT_FOUR_SPACE __VA_ARGS__) + #define LOGD4(...) LOG_DEBUG(IDENT_FOUR_SPACE __VA_ARGS__) + #define LOGE4(...) LOG_ERROR(IDENT_FOUR_SPACE __VA_ARGS__) +#endif + +#define ANSI_COLOR_GREEN "\x1b[32m" +#define ANSI_COLOR_CYAN "\x1b[36m" +#define ANSI_COLOR_YELLOW "\x1b[33m" +#define ANSI_COLOR_MAGENTA "\x1b[35m" +#define ANSI_COLOR_RED "\x1b[31m" +#define ANSI_COLOR_BLUE "\x1b[34m" +#define ANSI_COLOR_RESET "\x1b[0m" + +#define DBG_ENTRANCE LOGI(ANSI_COLOR_GREEN "=> %s() <%s>\n" ANSI_COLOR_RESET, \ + __func__, __FILE__) + + +// GMAC MII Configurations +#ifdef LOG_TAG +#undef LOG_TAG +#define LOG_TAG "MII" +#endif + + +typedef struct _HAL_MII_ADAPTER_ { + u32 InterruptMask; + PPHY_MODE_INFO pPhyModeInfo; +}HAL_MII_ADAPTER, *PHAL_MII_ADAPTER; + +typedef struct _HAL_MII_OP_ { + BOOL (*HalMiiGmacInit)(VOID *Data); + BOOL (*HalMiiInit)(VOID *Data); + BOOL (*HalMiiGmacReset)(VOID *Data); + BOOL (*HalMiiGmacEnablePhyMode)(VOID *Data); + u32 (*HalMiiGmacXmit)(VOID *Data); + VOID (*HalMiiGmacCleanTxRing)(VOID *Data); + VOID (*HalMiiGmacFillTxInfo)(VOID *Data); + VOID (*HalMiiGmacFillRxInfo)(VOID *Data); + VOID (*HalMiiGmacTx)(VOID *Data); + VOID (*HalMiiGmacRx)(VOID *Data); + VOID (*HalMiiGmacSetDefaultEthIoCmd)(VOID *Data); + VOID (*HalMiiGmacInitIrq)(VOID *Data); + u32 (*HalMiiGmacGetInterruptStatus)(VOID); + VOID (*HalMiiGmacClearInterruptStatus)(u32 IsrStatus); +}HAL_MII_OP, *PHAL_MII_OP; + +VOID HalMiiOpInit(IN VOID *Data); + +typedef struct _MII_ADAPTER_ { + PHAL_MII_OP pHalMiiOp; + PHAL_MII_ADAPTER pHalMiiAdapter; + PTX_INFO pTx_Info; + PRX_INFO pRx_Info; + VOID* TxBuffer; + VOID* RxBuffer; +}MII_ADAPTER, *PMII_ADAPTER; + +#endif + diff --git a/lib/fwlib/hal_misc.h b/lib/fwlib/hal_misc.h new file mode 100644 index 0000000..a910fa6 --- /dev/null +++ b/lib/fwlib/hal_misc.h @@ -0,0 +1,30 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _MISC_H_ +#define _MISC_H_ + +#include + +#ifdef CONFIG_TIMER_MODULE +extern _LONG_CALL_ u32 HalDelayUs(u32 us); +#endif + +extern _LONG_CALL_ u32 HalGetCpuClk(VOID); +extern _LONG_CALL_ u8 HalGetRomInfo(VOID); + +extern _LONG_CALL_ void *_memset( void *s, int c, SIZE_T n ); +extern _LONG_CALL_ void *_memcpy( void *s1, const void *s2, SIZE_T n ); +extern _LONG_CALL_ int _memcmp( const void *av, const void *bv, SIZE_T len ); + +//extern _LONG_CALL_ SIZE_T _strlen(const char *s); +extern _LONG_CALL_ int _strcmp(const char *cs, const char *ct); + + +#endif //_MISC_H_ diff --git a/lib/fwlib/hal_nfc.h b/lib/fwlib/hal_nfc.h new file mode 100644 index 0000000..b73dada --- /dev/null +++ b/lib/fwlib/hal_nfc.h @@ -0,0 +1,22 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_NFC_H_ +#define _HAL_NFC_H_ + +#include "rtl8195a_nfc.h" + + +VOID HalNFCOpInit( + IN VOID *Data +); + + +#endif + diff --git a/lib/fwlib/hal_pcm.h b/lib/fwlib/hal_pcm.h new file mode 100644 index 0000000..fa34432 --- /dev/null +++ b/lib/fwlib/hal_pcm.h @@ -0,0 +1,104 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_PCM_H_ +#define _HAL_PCM_H_ + +#include "rtl8195a_pcm.h" +/* +typedef struct _GDMA_CH_LLI_ELE_ { + u32 Sarx; + u32 Darx; + u32 Llpx; + u32 CtlxLow; + u32 CtlxUp; + u32 Temp; +}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE; +#if 1 +#if 0 +typedef struct _GDMA_CH_LLI_ { + PGDMA_CH_LLI_ELE pLliEle; + PGDMA_CH_LLI pNextLli; +}GDMA_CH_LLI, *PGDMA_CH_LLI; + +typedef struct _BLOCK_SIZE_LIST_ { + u32 BlockSize; + PBLOCK_SIZE_LIST pNextBlockSiz; +}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST; +#else +struct GDMA_CH_LLI { + PGDMA_CH_LLI_ELE pLliEle; + struct GDMA_CH_LLI *pNextLli; +}; + +struct BLOCK_SIZE_LIST { + u32 BlockSize; + struct BLOCK_SIZE_LIST *pNextBlockSiz; +}; + +#endif + +#endif +typedef struct _HAL_GDMA_ADAPTER_ { + u32 ChSar; + u32 ChDar; + GDMA_CHANNEL_NUM ChEn; + GDMA_CTL_REG GdmaCtl; + GDMA_CFG_REG GdmaCfg; + u32 PacketLen; + u32 BlockLen; + u32 MuliBlockCunt; + u32 MaxMuliBlock; + struct GDMA_CH_LLI *pLlix; + struct BLOCK_SIZE_LIST *pBlockSizeList; + + PGDMA_CH_LLI_ELE pLli; + u32 NextPlli; + u8 TestItem; + u8 ChNum; + u8 GdmaIndex; + u8 IsrCtrl:1; + u8 GdmaOnOff:1; + u8 Llpctrl:1; + u8 Lli0:1; + u8 Rsvd4to7:4; + u8 GdmaIsrType; +}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER; + +*/ + +typedef struct _HAL_PCM_ADAPTER_ { + u32 Enable:1; + PCM_CTL_REG PcmCtl; + PCM_CHCNR03_REG PcmChCNR03; + PCM_TSR03_REG PcmTSR03; + PCM_BSIZE03_REG PcmBSize03; + u32 abc; + u8 PcmIndex; + u8 PcmCh; +}HAL_PCM_ADAPTER, *PHAL_PCM_ADAPTER; + + +typedef struct _HAL_PCM_OP_ { + VOID (*HalPcmOnOff)(VOID *Data); + BOOL (*HalPcmInit)(VOID *Data); + BOOL (*HalPcmSetting)(VOID *Data); + BOOL (*HalPcmEn)(VOID *Data); + BOOL (*HalPcmIsrEnAndDis) (VOID *Data); + BOOL (*HalPcmDumpReg)(VOID *Data); + BOOL (*HalPcm)(VOID *Data); +}HAL_PCM_OP, *PHAL_PCM_OP; + + +VOID HalPcmOpInit( + IN VOID *Data +); + + +#endif diff --git a/lib/fwlib/hal_peri_on.h b/lib/fwlib/hal_peri_on.h new file mode 100644 index 0000000..abcbdd0 --- /dev/null +++ b/lib/fwlib/hal_peri_on.h @@ -0,0 +1,451 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_PERI_ON_H_ +#define _HAL_PERI_ON_H_ + +#define MASK_ALLON 0xFFFFFFFF + +#define HAL_PERI_ON_READ32(addr) HAL_READ32(PERI_ON_BASE, addr) +#define HAL_PERI_ON_WRITE32(addr, value) HAL_WRITE32(PERI_ON_BASE, addr, value) +#define HAL_PERI_ON_READ16(addr) HAL_READ16(PERI_ON_BASE, addr) +#define HAL_PERI_ON_WRITE16(addr, value) HAL_WRITE16(PERI_ON_BASE, addr, value) +#define HAL_PERI_ON_READ8(addr) HAL_READ8(PERI_ON_BASE, addr) +#define HAL_PERI_ON_WRITE8(addr, value) HAL_WRITE8(PERI_ON_BASE, addr, value) +#define HAL_PERL_ON_FUNC_CTRL(addr,value,ctrl) \ + HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~value))|((MASK_ALLON - ctrl + 1) & value))) +#define HAL_PERL_ON_PIN_SEL(addr,mask,value) \ + HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~mask)) | value)) + +//40 REG_SYS_REGU_CTRL0 +#define LDO25M_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_REGU_CTRL0, BIT_SYS_REGU_LDO25M_EN, ctrl) + +//A0 SYS_DEBUG_CTRL +#define DEBUG_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_DEBUG_CTRL, BIT_SYS_DBG_PIN_EN, ctrl) + +//A4 SYS_PINMUX_CTRL +#define SIC_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_SIC_PIN_EN, ctrl) +#define EEPROM_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_EEPROM_PIN_EN, ctrl) + + +//210 SOV_FUNC_EN +#define LXBUS_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LXBUS_EN, ctrl) +#define FLASH_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(SPI_FLASH_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_FLASH_EN, ctrl);} + +#define MEM_CTRL_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(SDR_SDRAM_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_MEM_CTRL_EN, ctrl);} + +#define LOC_UART_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(LOG_UART_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LOG_UART_EN, ctrl);} + +#define GDMA0_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(GDMA0_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA0_EN, ctrl);} + +#define GDMA1_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(GDMA1_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA1_EN, ctrl);} + +#define GTIMER_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(TIMER_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GTIMER_EN, ctrl);} + +#define SECURITY_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(CRYPTO_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_SECURITY_ENGINE_EN, ctrl);} + +//214 SOC_HCI_COM_FUNC_EN +#define SDIOD_ON_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(SDIO_DEVICE_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN, ctrl);} + +#define SDIOD_OFF_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(SDIO_DEVICE_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN, ctrl);} + +#define SDIOH_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(SDIO_HOST_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN, ctrl);} + +#define SDIO_ON_RST_MASK(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_RST_MUX, ctrl) +#define OTG_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(USB_OTG_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_EN, ctrl);} + +#define OTG_RST_MASK(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_RST_MUX, ctrl) +#define MII_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(MII_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_MII_EN, ctrl);} + +#define MII_MUX_SEL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SM_SEL, ctrl) +#define WL_MACON_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(WIFI_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_WL_MACON_EN, ctrl);} + +//218 SOC_PERI_FUNC0_EN +#define UART0_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(UART0_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART0_EN, ctrl);} + +#define UART1_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(UART1_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART1_EN, ctrl);} + +#define UART2_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(UART2_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART2_EN, ctrl);} + +#define SPI0_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(SPI0_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI0_EN, ctrl);} + +#define SPI1_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(SPI1_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI1_EN, ctrl);} + +#define SPI2_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(SPI2_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI2_EN, ctrl);} + +#define I2C0_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(I2C0_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C0_EN, ctrl);} + +#define I2C1_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(I2C1_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C1_EN, ctrl);} + +#define I2C2_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(I2C2_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C2_EN, ctrl);} + +#define I2C3_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(I2C3_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C3_EN, ctrl);} + +#define I2S0_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(I2S0_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S0_EN, ctrl);} + +#define I2S1_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(I2S1_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S1_EN, ctrl);} + +#define PCM0_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(PCM0_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM0_EN, ctrl);} + +#define PCM1_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(PCM1_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM1_EN, ctrl);} + +//21C SOC_PERI_FUNC1_EN +#define ADC0_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(ADC_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_ADC0_EN, ctrl);} + +#define DAC0_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(DAC_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC0_EN, ctrl);} + +#define DAC1_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(DAC_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC1_EN, ctrl);} + +#define GPIO_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(GPIO_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_GPIO_EN, ctrl);} + +//220 SOC_PERI_BD_FUNC0_EN +#define UART0_BD_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(UART0_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART0_BD_EN, ctrl);} + +#define UART1_BD_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(UART1_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART1_BD_EN, ctrl);} + +#define UART2_BD_FCTRL(ctrl) { \ + if (!ctrl) { \ + HAL_READ32(UART2_REG_BASE,0);\ + }\ + HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART2_BD_EN, ctrl);} + +//230 PESOC_CLK_CTRL +#define ACTCK_CPU_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_CKE_PLFM, ctrl) +#define ACTCK_TRACE_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TRACE_EN, ctrl) +#define SLPCK_TRACE_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TRACE_EN, ctrl) +#define ACTCK_VENDOR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_VENDOR_REG_EN, ctrl) +#define SLPCK_VENDOR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_VENDOR_REG_EN, ctrl) +#define ACTCK_FLASH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_FLASH_EN, ctrl) +#define SLPCK_FLASH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_FLASH_EN, ctrl) +#define ACTCK_SDR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_SDR_EN, ctrl) +#define SLPCK_SDR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_SDR_EN, ctrl) +#define ACTCK_LOG_UART_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_LOG_UART_EN, ctrl) +#define SLPCK_LOG_UART_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_LOG_UART_EN, ctrl) +#define ACTCK_TIMER_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TIMER_EN, ctrl) +#define SLPCK_TIMER_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TIMER_EN, ctrl) +#define ACTCK_GDMA0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA0_EN, ctrl) +#define SLPCK_GDMA0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA0_EN, ctrl) +#define ACTCK_GDMA1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA1_EN, ctrl) +#define SLPCK_GDMA1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA1_EN, ctrl) +#define ACTCK_GPIO_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GPIO_EN, ctrl) +#define SLPCK_GPIO_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GPIO_EN, ctrl) +#define ACTCK_BTCMD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_BTCMD_EN, ctrl) +#define SLPCK_BTCMD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_BTCMD_EN, ctrl) + +//234 PESOC_PERI_CLK_CTRL0 +#define ACTCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART0_EN, ctrl) +#define SLPCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART0_EN, ctrl) +#define ACTCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART1_EN, ctrl) +#define SLPCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART1_EN, ctrl) +#define ACTCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART2_EN, ctrl) +#define SLPCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART2_EN, ctrl) +#define ACTCK_SPI0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI0_EN, ctrl) +#define SLPCK_SPI0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI0_EN, ctrl) +#define ACTCK_SPI1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI1_EN, ctrl) +#define SLPCK_SPI1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI1_EN, ctrl) +#define ACTCK_SPI2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI2_EN, ctrl) +#define SLPCK_SPI2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI2_EN, ctrl) + +//238 PESOC_PERI_CLK_CTRL1 +#define ACTCK_I2C0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C0_EN, ctrl) +#define SLPCK_I2C0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C0_EN, ctrl) +#define ACTCK_I2C1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C1_EN, ctrl) +#define SLPCK_I2C1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C1_EN, ctrl) +#define ACTCK_I2C2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C2_EN, ctrl) +#define SLPCK_I2C2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C2_EN, ctrl) +#define ACTCK_I2C3_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C3_EN, ctrl) +#define SLPCK_I2C3_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C3_EN, ctrl) +#define ACTCK_I2S_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2S_EN, ctrl) +#define SLPCK_I2S_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2S_EN, ctrl) +#define ACTCK_PCM_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_PCM_EN, ctrl) +#define SLPCK_PCM_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_PCM_EN, ctrl) +#define ACTCK_ADC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_ADC_EN, ctrl) +#define SLPCK_ADC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_ADC_EN, ctrl) +#define ACTCK_DAC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_DAC_EN, ctrl) +#define SLPCK_DAC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_DAC_EN, ctrl) + +//240 PESOC_HCI_CLK_CTRL0 +#define ACTCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_DEV_EN, ctrl) +#define SLPCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_DEV_EN, ctrl) +#define ACTCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_HST_EN, ctrl) +#define SLPCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_HST_EN, ctrl) +#define ACTCK_OTG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_OTG_EN, ctrl) +#define SLPCK_OTG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_OTG_EN, ctrl) +#define ACTCK_MII_MPHY_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_MII_MPHY_EN, ctrl) +#define SLPCK_MII_MPHY_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_MII_MPHY_EN, ctrl) + +//244 PESOC_COM_CLK_CTRL1 +#define ACTCK_WL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_WL_EN, ctrl) +#define SLPCK_WL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_WL_EN, ctrl) +#define ACTCK_SEC_ENG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_SECURITY_ENG_EN, ctrl) +#define SLPCK_SEC_ENG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_SECURITY_ENG_EN, ctrl) +#define ACTCK_NFC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_NFC_EN, ctrl) +#define SLPCK_NFC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_NFC_EN, ctrl) +#define NFC_CAL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_NFC_CAL_EN, ctrl) + +//250 REG_PERI_CLK_SEL +#define TRACE_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_TRACE_CK_SEL << BIT_SHIFT_PESOC_TRACE_CK_SEL), BIT_PESOC_TRACE_CK_SEL(num)) +#define FLASH_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_FLASH_CK_SEL << BIT_SHIFT_PESOC_FLASH_CK_SEL), BIT_PESOC_FLASH_CK_SEL(num)) +#define SDR_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_SDR_CK_SEL << BIT_SHIFT_PESOC_SDR_CK_SEL), BIT_PESOC_SDR_CK_SEL(num)) +#define I2C_SCLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_PERI_SCLK_SEL << BIT_SHIFT_PESOC_PERI_SCLK_SEL), BIT_PESOC_PERI_SCLK_SEL(num)) + +//270 REG_OSC32K_CTRL +#define OSC32K_CKGEN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_OSC32K_CTRL, BIT_32K_POW_CKGEN_EN, ctrl) + +//280 REG_UART_MUX_CTRL +#define UART0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART0_PIN_EN, ctrl) +#define UART0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART0_PIN_SEL << BIT_SHIFT_UART0_PIN_SEL), BIT_UART0_PIN_SEL(num)) +#define UART1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART1_PIN_EN, ctrl) +#define UART1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART1_PIN_SEL << BIT_SHIFT_UART1_PIN_SEL), BIT_UART1_PIN_SEL(num)) +#define UART2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART2_PIN_EN, ctrl) +#define UART2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART2_PIN_SEL << BIT_SHIFT_UART2_PIN_SEL), BIT_UART2_PIN_SEL(num)) + +//284 REG_SPI_MUX_CTRL +#define SPI0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_PIN_EN, ctrl) +#define SPI0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI0_PIN_SEL << BIT_SHIFT_SPI0_PIN_SEL), BIT_SPI0_PIN_SEL(num)) +#define SPI1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI1_PIN_EN, ctrl) +#define SPI1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI1_PIN_SEL << BIT_SHIFT_SPI1_PIN_SEL), BIT_SPI1_PIN_SEL(num)) +#define SPI2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI2_PIN_EN, ctrl) +#define SPI2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI2_PIN_SEL << BIT_SHIFT_SPI2_PIN_SEL), BIT_SPI2_PIN_SEL(num)) +#define SPI0_MULTI_CS_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_MULTI_CS_EN, ctrl) + +//288 REG_I2C_MUX_CTRL +#define I2C0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C0_PIN_EN, ctrl) +#define I2C0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C0_PIN_SEL << BIT_SHIFT_I2C0_PIN_SEL), BIT_I2C0_PIN_SEL(num)) +#define I2C1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C1_PIN_EN, ctrl) +#define I2C1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C1_PIN_SEL << BIT_SHIFT_I2C1_PIN_SEL), BIT_I2C1_PIN_SEL(num)) +#define I2C2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C2_PIN_EN, ctrl) +#define I2C2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C2_PIN_SEL << BIT_SHIFT_I2C2_PIN_SEL), BIT_I2C2_PIN_SEL(num)) +#define I2C3_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C3_PIN_EN, ctrl) +#define I2C3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C3_PIN_SEL << BIT_SHIFT_I2C3_PIN_SEL), BIT_I2C3_PIN_SEL(num)) + +//28C REG_I2S_MUX_CTRL +#define I2S0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_PIN_EN, ctrl) +#define I2S0_MCK_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_MCK_EN, ctrl) +#define I2S0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S0_PIN_SEL << BIT_SHIFT_I2S0_PIN_SEL), BIT_I2S0_PIN_SEL(num)) +#define I2S1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_PIN_EN, ctrl) +#define I2S1_MCK_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_MCK_EN, ctrl) +#define I2S1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S1_PIN_SEL << BIT_SHIFT_I2S1_PIN_SEL), BIT_I2S1_PIN_SEL(num)) +#define PCM0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM0_PIN_EN, ctrl) +#define PCM0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM0_PIN_SEL << BIT_SHIFT_PCM0_PIN_SEL), BIT_PCM0_PIN_SEL(num)) +#define PCM1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM1_PIN_EN, ctrl) +#define PCM1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM1_PIN_SEL << BIT_SHIFT_PCM1_PIN_SEL), BIT_PCM1_PIN_SEL(num)) + +//2A0 HCI_PINMUX_CTRL +#define SDIOD_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN, ctrl) +#define SDIOH_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN, ctrl) +#define MII_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN, ctrl) + +//2A4 WL_PINMUX_CTRL +#define LED_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_LED_PIN_EN, ctrl) +#define LED_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_WL_PINMUX_CTRL, (BIT_MASK_WL_LED_PIN_SEL << BIT_SHIFT_WL_LED_PIN_SEL), BIT_WL_LED_PIN_SEL(num)) +#define ANT0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT0_PIN_EN, ctrl) +#define ANT1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT1_PIN_EN, ctrl) +#define BTCOEX_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCOEX_PIN_EN, ctrl) +#define BTCMD_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCMD_PIN_EN, ctrl) +#define NFC_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_NFC_PIN_EN, ctrl) + +//2AC PWM_PINMUX_CTRL +#define PWM0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM0_PIN_EN, ctrl) +#define PWM0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM0_PIN_SEL << BIT_SHIFT_PWM0_PIN_SEL), BIT_PWM0_PIN_SEL(num)) +#define PWM1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM1_PIN_EN, ctrl) +#define PWM1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM1_PIN_SEL << BIT_SHIFT_PWM1_PIN_SEL), BIT_PWM1_PIN_SEL(num)) +#define PWM2_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM2_PIN_EN, ctrl) +#define PWM2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM2_PIN_SEL << BIT_SHIFT_PWM2_PIN_SEL), BIT_PWM2_PIN_SEL(num)) +#define PWM3_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM3_PIN_EN, ctrl) +#define PWM3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM3_PIN_SEL << BIT_SHIFT_PWM3_PIN_SEL), BIT_PWM3_PIN_SEL(num)) +#define ETE0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE0_PIN_EN, ctrl) +#define ETE0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE0_PIN_SEL << BIT_SHIFT_ETE0_PIN_SEL), BIT_ETE0_PIN_SEL(num)) +#define ETE1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE1_PIN_EN, ctrl) +#define ETE1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE1_PIN_SEL << BIT_SHIFT_ETE1_PIN_SEL), BIT_ETE1_PIN_SEL(num)) +#define ETE2_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE2_PIN_EN, ctrl) +#define ETE2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE2_PIN_SEL << BIT_SHIFT_ETE2_PIN_SEL), BIT_ETE2_PIN_SEL(num)) +#define ETE3_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE3_PIN_EN, ctrl) +#define ETE3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE3_PIN_SEL << BIT_SHIFT_ETE3_PIN_SEL), BIT_ETE3_PIN_SEL(num)) + +//2C0 CPU_PERIPHERAL_CTRL +#define SPI_FLASH_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SPI_FLSH_PIN_EN, ctrl) +#define SPI_FLASH_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_CPU_PERIPHERAL_CTRL, (BIT_MASK_SPI_FLSH_PIN_SEL << BIT_SHIFT_SPI_FLSH_PIN_SEL), BIT_SPI_FLSH_PIN_SEL(num)) +#define SDR_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SDR_PIN_EN, ctrl) +#define TRACE_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_TRACE_PIN_EN, ctrl) +#define LOG_UART_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_PIN_EN, ctrl) +#define LOG_UART_IR_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_IR_EN, ctrl) + +//300 REG_PESOC_MEM_CTRL +#define SDR_DDL_FCTRL(ctrl) HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_SDR_DDL_CTRL << BIT_SHIFT_PESOC_SDR_DDL_CTRL), BIT_PESOC_SDR_DDL_CTRL(ctrl)) +#define FLASH_DDL_FCTRL(ctrl) HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_FLASH_DDL_CTRL << BIT_SHIFT_PESOC_FLASH_DDL_CTRL), BIT_PESOC_FLASH_DDL_CTRL(ctrl)) + +//304 REG_PESOC_SOC_CTRL +#define SRAM_MUX_CFG(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_SRAM_MUX_CFG << BIT_SHIFT_PESOC_SRAM_MUX_CFG), BIT_PESOC_SRAM_MUX_CFG(num)) +#define LX_WL_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_WL_SWAP_SEL, ctrl) +#define LX_MST_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_MST_SWAP_SEL, ctrl) +#define LX_SLV_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_SLV_SWAP_SEL, ctrl) +#define MII_LX_WRAPPER_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_WRAPPER_EN, ctrl) +#define MII_LX_MST_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_MST_SWAP_SEL, ctrl) +#define MII_LX_SLV_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_SLV_SWAP_SEL, ctrl) +#define GDMA_CFG(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_GDMA_CFG << BIT_SHIFT_PESOC_GDMA_CFG), BIT_PESOC_GDMA_CFG(num)) + +//308 PESOC_PERI_CTRL +#define SPI_RN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CTRL, BIT_SOC_FUNC_SPI_RN, ctrl) + +//320 GPIO_SHTDN_CTRL +#define GPIO_GPA_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPA_SHTDN_N, ctrl) +#define GPIO_GPB_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPB_SHTDN_N, ctrl) +#define GPIO_GPC_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPC_SHTDN_N, ctrl) +#define GPIO_GPD_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPD_SHTDN_N, ctrl) +#define GPIO_GPE_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPE_SHTDN_N, ctrl) +#define GPIO_GPF_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPF_SHTDN_N, ctrl) +#define GPIO_GPG_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPG_SHTDN_N, ctrl) +#define GPIO_GPH_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPH_SHTDN_N, ctrl) +#define GPIO_GPI_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPI_SHTDN_N, ctrl) +#define GPIO_GPJ_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPJ_SHTDN_N, ctrl) +#define GPIO_GPK_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPK_SHTDN_N, ctrl) + +//374 +#define EGTIM_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PERI_EGTIM_CTRL, BIT_PERI_EGTIM_EN, ctrl) +#define EGTIM_RSIG_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_REF_SIG_SEL << BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL), BIT_PERI_EGTIM_REF_SIG_SEL(num)) +#define EGTIME_PIN_G0_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP0_OPT_SEL(num)) +#define EGTIME_PIN_G1_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP1_OPT_SEL(num)) +#define EGTIME_PIN_G2_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP2_OPT_SEL(num)) + + +#endif //_HAL_PERI_ON_H_ + diff --git a/lib/fwlib/hal_pinmux.h b/lib/fwlib/hal_pinmux.h new file mode 100644 index 0000000..68b2c80 --- /dev/null +++ b/lib/fwlib/hal_pinmux.h @@ -0,0 +1,64 @@ +#ifndef _HAL_PINMUX_ +#define _HAL_PINMUX_ + + +//Function Index +#define UART0 0 +#define UART1 1 +#define UART2 2 +#define SPI0 8 +#define SPI1 9 +#define SPI2 10 +#define SPI0_MCS 15 +#define I2C0 16 +#define I2C1 17 +#define I2C2 18 +#define I2C3 19 +#define I2S0 24 +#define I2S1 25 +#define PCM0 28 +#define PCM1 29 +#define ADC0 32 +#define DAC0 36 +#define DAC1 37 +#define SDIOD 64 +#define SDIOH 65 +#define USBOTG 66 +#define MII 88 +#define WL_LED 96 +#define WL_ANT0 104 +#define WL_ANT1 105 +#define WL_BTCOEX 108 +#define WL_BTCMD 109 +#define NFC 112 +#define PWM0 160 +#define PWM1 161 +#define PWM2 162 +#define PWM3 163 +#define ETE0 164 +#define ETE1 165 +#define ETE2 166 +#define ETE3 167 +#define EGTIM 168 +#define SPI_FLASH 196 +#define SDR 200 +#define JTAG 216 +#define TRACE 217 +#define LOG_UART 220 +#define LOG_UART_IR 221 +#define SIC 224 +#define EEPROM 225 +#define DEBUG 226 + +//Location Index(Pin Mux Selection) +#define S0 0 +#define S1 1 +#define S2 2 +#define S3 3 + +_LONG_CALL_ u8 +HalPinCtrlRtl8195A( + IN u32 Function, + IN u32 PinLocation, + IN BOOL Operation); +#endif //_HAL_PINMUX_ \ No newline at end of file diff --git a/lib/fwlib/hal_platform.h b/lib/fwlib/hal_platform.h new file mode 100644 index 0000000..d0979d7 --- /dev/null +++ b/lib/fwlib/hal_platform.h @@ -0,0 +1,102 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _HAL_PLATFORM_ +#define _HAL_PLATFORM_ + +#define ROMVERSION 0x03 +#define ROMINFORMATION (ROMVERSION) + +#define SYSTEM_CLK PLATFORM_CLOCK + +#define SDR_SDRAM_BASE 0x30000000 +#define SYSTEM_CTRL_BASE 0x40000000 +#define PERI_ON_BASE 0x40000000 +#define VENDOR_REG_BASE 0x40002800 +#define SPI_FLASH_BASE 0x98000000 +#define SDR_CTRL_BASE 0x40005000 + +#define PERIPHERAL_IRQ_STATUS 0x04 +#define PERIPHERAL_IRQ_MODE 0x08 +#define PERIPHERAL_IRQ_EN 0x0C +#define LP_PERI_EXT_IRQ_STATUS 0x24 +#define LP_PERI_EXT_IRQ_MODE 0x28 +#define LP_PERI_EXT_IRQ_EN 0x2C + +#define PERIPHERAL_IRQ_ALL_LEVEL 0 + +#define TIMER_CLK 32*1000 + +//3 Peripheral IP Base Address +#define GPIO_REG_BASE 0x40001000 +#define TIMER_REG_BASE 0x40002000 +#define NFC_INTERFACE_BASE 0x40002400 +#define LOG_UART_REG_BASE 0x40003000 +#define I2C2_REG_BASE 0x40003400 +#define I2C3_REG_BASE 0x40003800 +#define SPI_FLASH_CTRL_BASE 0x40006000 +#define ADC_REG_BASE 0x40010000 +#define DAC_REG_BASE 0x40011000 +#define UART0_REG_BASE 0x40040000 +#define UART1_REG_BASE 0x40040400 +#define UART2_REG_BASE 0x40040800 +#define SPI0_REG_BASE 0x40042000 +#define SPI1_REG_BASE 0x40042400 +#define SPI2_REG_BASE 0x40042800 +#define I2C0_REG_BASE 0x40044000 +#define I2C1_REG_BASE 0x40044400 +#define SDIO_DEVICE_REG_BASE 0x40050000 +#define MII_REG_BASE 0x40050000 +#define SDIO_HOST_REG_BASE 0x40058000 +#define GDMA0_REG_BASE 0x40060000 +#define GDMA1_REG_BASE 0x40061000 +#define I2S0_REG_BASE 0x40062000 +#define I2S1_REG_BASE 0x40063000 +#define PCM0_REG_BASE 0x40064000 +#define PCM1_REG_BASE 0x40065000 +#define CRYPTO_REG_BASE 0x40070000 +#define WIFI_REG_BASE 0x40080000 +#define USB_OTG_REG_BASE 0x400C0000 + +#define GDMA1_REG_OFF 0x1000 +#define I2S1_REG_OFF 0x1000 +#define PCM1_REG_OFF 0x1000 +#define SSI_REG_OFF 0x400 +#define RUART_REG_OFF 0x400 + +#define CPU_CLK_TYPE_NO 6 + +enum _BOOT_TYPE_ { + BOOT_FROM_FLASH = 0, + BOOT_FROM_SDIO = 1, + BOOT_FROM_USB = 2, + BOOT_FROM_RSVD = 3, +}; + +enum _EFUSE_CPU_CLK_ { + #if 1 + CLK_200M = 0, + CLK_100M = 1, + CLK_50M = 2, + CLK_25M = 3, + CLK_12_5M = 4, + CLK_4M = 5, + #else + CLK_25M = 0, + CLK_200M = 1, + CLK_100M = 2, + CLK_50M = 3, + CLK_12_5M = 4, + CLK_4M = 5, + #endif +}; + + +#endif //_HAL_PLATFORM_ diff --git a/lib/fwlib/hal_pwm.h b/lib/fwlib/hal_pwm.h new file mode 100644 index 0000000..ff74413 --- /dev/null +++ b/lib/fwlib/hal_pwm.h @@ -0,0 +1,57 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_PWM_H_ +#define _HAL_PWM_H_ + +#define MAX_PWM_CTRL_PIN 4 +// the minimum tick time for G-timer is 61 us (clock source = 32768Hz, reload value=1 and reload takes extra 1T) +//#define GTIMER_TICK_US 31 // micro-second, 1000000/32768 ~= 30.5 +#define MIN_GTIMER_TIMEOUT 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2 +#define PWM_GTIMER_TICK_TIME 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2 + +typedef struct _HAL_PWM_ADAPTER_ { + u8 pwm_id; // the PWM ID, 0~3 + u8 sel; // PWM Pin selection, 0~3 + u8 gtimer_id; // using G-Timer ID, there are 7 G-timer, but we prefer to use timer 3~6 + u8 enable; // is enabled +// u32 timer_value; // the G-Timer auto-reload value, source clock is 32768Hz, reload will takes extra 1 tick. To set the time of a tick of PWM + u32 tick_time; // the tick time for the G-timer + u32 period; // the period of a PWM control cycle, in PWM tick + u32 pulsewidth; // the pulse width in a period of a PWM control cycle, in PWM tick. To control the ratio +// float duty_ratio; // the dyty ratio = pulswidth/period +}HAL_PWM_ADAPTER, *PHAL_PWM_ADAPTER; + + +extern HAL_Status +HAL_Pwm_Init( + u32 pwm_id, + u32 sel +); + +extern void +HAL_Pwm_Enable( + u32 pwm_id +); + +extern void +HAL_Pwm_Disable( + u32 pwm_id +); + +extern void +HAL_Pwm_SetDuty( + u32 pwm_id, + u32 period, + u32 pulse_width +); + + +#endif + diff --git a/lib/fwlib/hal_sdio.h b/lib/fwlib/hal_sdio.h new file mode 100644 index 0000000..7fa7980 --- /dev/null +++ b/lib/fwlib/hal_sdio.h @@ -0,0 +1,252 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_SDIO_H_ +#define _HAL_SDIO_H_ + +#include "rtl8195a_sdio.h" + +#if !SDIO_BOOT_DRIVER +#include "mailbox.h" +#endif +#define PURE_SDIO_INIC 0 // is a pure SDIO iNIC device or a SDIO iNIC + peripheral device + +#if SDIO_BOOT_DRIVER +typedef struct _HAL_SDIO_ADAPTER_ { + u8 *pTXBDAddr; /* The TX_BD start address */ + PSDIO_TX_BD pTXBDAddrAligned; /* The TX_BD start address, it must be 4-bytes aligned */ + PSDIO_TX_BD_HANDLE pTXBDHdl; /* point to the allocated memory for TX_BD Handle array */ + u16 TXBDWPtr; /* The SDIO TX(Host->Device) BD local write index, different with HW maintained write Index. */ + u16 TXBDRPtr; /* The SDIO TX(Host->Device) BD read index */ + u16 TXBDRPtrReg; /* The SDIO TX(Host->Device) BD read index has been write to HW register */ + u16 reserve1; + + u8 *pRXBDAddr; /* The RX_BD start address */ + PSDIO_RX_BD pRXBDAddrAligned; /* The RX_BD start address, it must be 8-bytes aligned */ + PSDIO_RX_BD_HANDLE pRXBDHdl; /* point to the allocated memory for RX_BD Handle array */ + u16 RXBDWPtr; /* The SDIO RX(Device->Host) BD write index */ + u16 RXBDRPtr; /* The SDIO RX(Device->Host) BD local read index, different with HW maintained Read Index. */ + u16 IntMask; /* The Interrupt Mask */ + u16 IntStatus; /* The Interrupt Status */ + u32 Events; /* The Event to the SDIO Task */ + + u32 EventSema; /* Semaphore for SDIO events, use to wakeup the SDIO task */ + u8 CCPWM; /* the value write to register CCPWM, which will sync to Host HCPWM */ + u8 reserve2; + u16 CCPWM2; /* the value write to register CCPWM2, which will sync to Host HCPWM2 */ + + s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize); /* to hook the WLan driver TX callback function to handle a Packet TX */ + VOID *pTxCb_Adapter; /* a pointer will be used to call the TX Callback function, + which is from the TX CallBack function register */ + s8 (*pTxCallback_Backup)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize); // Use to back up the registered TX Callback function, for MP/Normal mode switch + VOID *pTxCb_Adapter_Backup; // Backup the pTxCb_Adapter, for MP/Normal mode switch + _LIST FreeTxPktList; /* The list to queue free Tx packets handler */ + _LIST RxPktList; /* The list to queue RX packets */ + _LIST FreeRxPktList; /* The list to queue free Rx packets handler */ + SDIO_TX_PACKET *pTxPktHandler; /* to store allocated TX Packet handler memory address */ + SDIO_RX_PACKET *pRxPktHandler; /* to store allocated RX Packet handler memory address */ + u32 RxInQCnt; /* The packet count for Rx In Queue */ + u32 MemAllocCnt; // Memory allocated count, for debug only + u32 MAllocFailedCnt; // MemAlloc Failed count, for debugging + +// VOID *pHalOp; /* point to HAL operation function table */ +} HAL_SDIO_ADAPTER, *PHAL_SDIO_ADAPTER; + +extern BOOL SDIO_Device_Init_Rom( + IN PHAL_SDIO_ADAPTER pSDIODev +); +extern VOID SDIO_Device_DeInit_Rom( + IN PHAL_SDIO_ADAPTER pSDIODev +); +extern VOID SDIO_Send_C2H_IOMsg_Rom( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 *C2HMsg +); +extern u8 SDIO_Send_C2H_PktMsg_Rom( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u8 *C2HMsg, + IN u16 MsgLen +); +extern VOID SDIO_Register_Tx_Callback_Rom( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize), + IN VOID *pAdapter +); +extern s8 SDIO_Rx_Callback_Rom( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN VOID *pData, + IN u16 Offset, + IN u16 Length, + IN u8 CmdType +); + +#else // else of "#if SDIO_BOOT_DRIVER" +typedef struct _HAL_SDIO_ADAPTER_ { +// u8 *pTxBuff; /* point to the SDIO TX Buffer */ +// u8 *pTxBuffAligned; /* point to the SDIO TX Buffer with 4-bytes aligned */ +// u32 TXFifoRPtr; /* The SDIO TX(Host->Device) FIFO buffer read pointer */ + + u8 *pTXBDAddr; /* The TX_BD start address */ + PSDIO_TX_BD pTXBDAddrAligned; /* The TX_BD start address, it must be 4-bytes aligned */ + PSDIO_TX_BD_HANDLE pTXBDHdl; /* point to the allocated memory for TX_BD Handle array */ + u16 TXBDWPtr; /* The SDIO TX(Host->Device) BD local write index, different with HW maintained write Index. */ + u16 TXBDRPtr; /* The SDIO TX(Host->Device) BD read index */ + u16 TXBDRPtrReg; /* The SDIO TX(Host->Device) BD read index has been write to HW register */ + + u8 *pRXBDAddr; /* The RX_BD start address */ + PSDIO_RX_BD pRXBDAddrAligned; /* The RX_BD start address, it must be 8-bytes aligned */ + PSDIO_RX_BD_HANDLE pRXBDHdl; /* point to the allocated memory for RX_BD Handle array */ + u16 RXBDWPtr; /* The SDIO RX(Device->Host) BD write index */ + u16 RXBDRPtr; /* The SDIO RX(Device->Host) BD local read index, different with HW maintained Read Index. */ + u16 IntMask; /* The Interrupt Mask */ + u16 IntStatus; /* The Interrupt Status */ + u32 Events; /* The Event to the SDIO Task */ + + u8 CCPWM; /* the value write to register CCPWM, which will sync to Host HCPWM */ + u8 reserve1; + u16 CCPWM2; /* the value write to register CCPWM2, which will sync to Host HCPWM2 */ + u8 CRPWM; /* sync from Host HRPWM */ + u8 reserve2; + u16 CRPWM2; /* sync from Host HRPWM2 */ + +#if !TASK_SCHEDULER_DISABLED + _Sema TxSema; /* Semaphore for SDIO TX, use to wakeup the SDIO TX task */ + _Sema RxSema; /* Semaphore for SDIO RX, use to wakeup the SDIO RX task */ +#else + u32 EventSema; /* Semaphore for SDIO events, use to wakeup the SDIO task */ +#endif + s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize); /* to hook the WLan driver TX callback function to handle a Packet TX */ + VOID *pTxCb_Adapter; /* a pointer will be used to call the TX Callback function, + which is from the TX CallBack function register */ + s8 (*pTxCallback_Backup)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize); // Use to back up the registered TX Callback function, for MP/Normal mode switch + VOID *pTxCb_Adapter_Backup; // Backup the pTxCb_Adapter, for MP/Normal mode switch +#if (CONFIG_INIC_EN == 0) + _LIST FreeTxPktList; /* The list to queue free Tx packets handler */ + SDIO_TX_PACKET *pTxPktHandler; /* to store allocated TX Packet handler memory address */ +#endif + _LIST RxPktList; /* The list to queue RX packets */ + _LIST FreeRxPktList; /* The list to queue free Rx packets handler */ +// _LIST RecyclePktList; /* The list to queue packets handler to be recycled */ + SDIO_RX_PACKET *pRxPktHandler; /* to store allocated RX Packet handler memory address */ + _Mutex RxMutex; /* The Mutex to protect RxPktList */ + u32 RxInQCnt; /* The packet count for Rx In Queue */ +#if SDIO_DEBUG + _Mutex StatisticMutex; /* The Mutex to protect Statistic data */ + u32 MemAllocCnt; // Memory allocated count, for debug only + u32 MAllocFailedCnt; // MemAlloc Failed count, for debugging +#endif + VOID *pHalOp; /* point to HAL operation function table */ + RTL_MAILBOX *pMBox; /* the Mail box for other driver module can send message to SDIO driver */ + +#ifdef PLATFORM_FREERTOS + xTaskHandle xSDIOTxTaskHandle; /* The handle of the SDIO Task for TX, can be used to delte the task */ + xTaskHandle xSDIORxTaskHandle; /* The handle of the SDIO Task speical for RX, can be used to delte the task */ +#endif + u8 RxFifoBusy; /* is the RX BD fetch hardware busy */ + +#if SDIO_MP_MODE +#if !TASK_SCHEDULER_DISABLED + u32 MP_Events; /* The Event to the SDIO Task */ + _Sema MP_EventSema; /* Semaphore for SDIO events, use to wakeup the SDIO task */ + RTL_MAILBOX *pMP_MBox; /* the Mail box for communication with other driver module */ +#ifdef PLATFORM_FREERTOS + xTaskHandle MP_TaskHandle; /* The handle of the MP loopback Task, can be used to delte the task */ +#endif // end of "#ifdef PLATFORM_FREERTOS" +#endif // end of "#if !TASK_SCHEDULER_DISABLED" + // for MP mode + RTL_TIMER *pPeriodTimer; /* a timer to calculate throughput periodically */ + u8 MP_ModeEn; /* is in MP mode */ + u8 MP_LoopBackEn; /* is loop-back enabled */ + u8 MP_ContinueTx; /* is continue TX test enabled */ + u8 MP_ContinueRx; /* is continue RX test enabled */ + u8 MP_ContinueRxMode; /* continue RX test mode: static RX Buf, Dyna-Allocate RX Buf, Pre-Allocate RX Buf */ + u8 MP_CRxInfinite; /* is non-stop SDIO RX, no packet count limit */ + u16 MP_CRxSize; /* SDIO RX test packet size */ + u8 *pMP_CRxBuf; // the buffer for continye RX test + u32 MP_CRxPktCnt; /* SDIO RX test packet count */ + u32 MP_CRxPktPendingCnt; /* SDIO RX test packet pening count */ + u32 MP_TxPktCnt; /* SDIO TX packet count */ + u32 MP_RxPktCnt; /* SDIO RX packet count */ + u32 MP_TxByteCnt; /* SDIO TX Byte count */ + u32 MP_RxByteCnt; /* SDIO RX Byte count */ + u32 MP_TxDropCnt; /* SDIO TX Drop packet count */ + u32 MP_RxDropCnt; /* SDIO RX Drop packet count */ + + u32 MP_TxPktCntInPeriod; /* SDIO TX packet count in a period */ + u32 MP_RxPktCntInPeriod; /* SDIO RX packet count in a period */ + u32 MP_TxByteCntInPeriod; /* SDIO TX Byte count in a period */ + u32 MP_RxByteCntInPeriod; /* SDIO RX Byte count in a period */ + + u32 MP_TxAvgTPWin[SDIO_AVG_TP_WIN_SIZE]; /* a window of SDIO TX byte count history, for average throughput calculation */ + u32 MP_RxAvgTPWin[SDIO_AVG_TP_WIN_SIZE]; /* a window of SDIO RX byte count history, for average throughput calculation */ + u32 MP_TxAvgTPWinSum; /* The sum of all byte-count in the window */ + u32 MP_RxAvgTPWinSum; /* The sum of all byte-count in the window */ + u8 OldestTxAvgWinIdx; /* the index of the oldest TX byte count log */ + u8 TxAvgWinCnt; /* the number of log in the Window */ + u8 OldestRxAvgWinIdx; /* the index of the oldest RX byte count log */ + u8 RxAvgWinCnt; /* the number of log in the Window */ + + _LIST MP_RxPktList; /* The list to queue RX packets, for MP loopback test */ +#endif // end of '#if SDIO_MP_MODE' +} HAL_SDIO_ADAPTER, *PHAL_SDIO_ADAPTER; +#endif // end of "#else of "#if SDIO_BOOT_DRIVER"" + + +typedef struct _HAL_SDIO_OP_ { + BOOL (*HalSdioDevInit)(PHAL_SDIO_ADAPTER pSDIODev); + VOID (*HalSdioDevDeInit)(PHAL_SDIO_ADAPTER pSDIODev); + VOID (*HalSdioSendC2HIOMsg)(PHAL_SDIO_ADAPTER pSDIODev, u32 *C2HMsg); + u8 (*HalSdioSendC2HPktMsg)(PHAL_SDIO_ADAPTER pSDIODev, u8 *C2HMsg, u16 MsgLen); + VOID (*HalSdioRegTxCallback)(PHAL_SDIO_ADAPTER pSDIODev,s8 (*CallbackFun)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize), VOID *pAdapter); + s8 (*HalSdioRxCallback)(PHAL_SDIO_ADAPTER pSDIODev, VOID *pData, u16 Offset, u16 PktSize, u8 CmdType); +#if SDIO_MP_MODE + VOID (*HalSdioDevMPApp)(PHAL_SDIO_ADAPTER pSDIODev, u16 argc, u8 *argv[]); +#endif +}HAL_SDIO_OP, *PHAL_SDIO_OP; + + +extern BOOL SDIO_Device_Init( + IN PHAL_SDIO_ADAPTER pSDIODev +); +extern VOID SDIO_Device_DeInit( + IN PHAL_SDIO_ADAPTER pSDIODev +); +extern VOID SDIO_Send_C2H_IOMsg( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 *C2HMsg +); +extern u8 SDIO_Send_C2H_PktMsg( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u8 *C2HMsg, + IN u16 MsgLen +); +extern VOID SDIO_Register_Tx_Callback( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize), + IN VOID *pAdapter +); +extern s8 SDIO_Rx_Callback( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN VOID *pData, + IN u16 Offset, + IN u16 Length, + IN u8 CmdType +); +#if SDIO_MP_MODE +extern VOID SDIO_DeviceMPApp( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u16 argc, + IN u8 *argv[] +); +#endif + +extern PHAL_SDIO_ADAPTER pgSDIODev; +extern VOID HalSdioInit(VOID); +extern VOID HalSdioDeInit(VOID); +#endif // #ifndef _HAL_SDIO_H_ diff --git a/lib/fwlib/hal_sdr_controller.h b/lib/fwlib/hal_sdr_controller.h new file mode 100644 index 0000000..79487a2 --- /dev/null +++ b/lib/fwlib/hal_sdr_controller.h @@ -0,0 +1,188 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_SDR_CONTROLLER_H_ +#define _HAL_SDR_CONTROLLER_H_ + +typedef enum _DRAM_TYPE_ { + DRAM_DDR_1 = 1, + DRAM_DDR_2 = 2, + DRAM_DDR_3 = 3, + DRAM_DDR_4 = 4, + DRAM_SDR = 8 +}DRAM_TYPE; + +typedef enum _DRAM_COLADDR_WTH_ { + DRAM_COLADDR_8B = 0, + DRAM_COLADDR_9B = 1, + DRAM_COLADDR_10B = 2, + DRAM_COLADDR_11B = 3, + DRAM_COLADDR_12B = 4, + DRAM_COLADDR_13B = 5, + DRAM_COLADDR_14B = 6, + DRAM_COLADDR_15B = 7, + DRAM_COLADDR_16B = 8 +}DRAM_COLADDR_WTH; + +typedef enum _DRAM_BANK_SIZE_ { + DRAM_BANK_2 = 0, + DRAM_BANK_4 = 1, + DRAM_BANK_8 = 2 +}DRAM_BANK_SIZE; + +typedef enum _DRAM_DQ_WIDTH_ { + DRAM_DQ_16 = 0, + DRAM_DQ_32 = 1, + DRAM_HALF_DQ32 = 2 +}DRAM_DQ_WIDTH; + +typedef enum _MODE0_BST_LEN_ { + BST_LEN_4 = 0, + BST_LEN_FLY = 1, + BST_LEN_8 = 2 +}MODE0_BST_LEN; + +typedef enum _MODE0_BST_TYPE_ { + SENQUENTIAL = 0, + INTERLEAVE = 1 +}MODE0_BST_TYPE; + +typedef enum _DFI_RATIO_TYPE_ { + DFI_RATIO_1 = 0, // DFI= 1:1, or SDR + DFI_RATIO_2 = 1, + DFI_RATIO_4 = 2 +}DFI_RATIO_TYPE; + +typedef struct _DRAM_INFO_ { + DRAM_TYPE DeviceType; + DRAM_COLADDR_WTH ColAddrWth; + DRAM_BANK_SIZE Bank; + DRAM_DQ_WIDTH DqWidth; +}DRAM_INFO; + +typedef struct _DRAM_MODE_REG_INFO_ { + MODE0_BST_LEN BstLen; + MODE0_BST_TYPE BstType; + //enum mode0_cas rd_cas; + u32 Mode0Cas; + u32 Mode0Wr; + u32 Mode1DllEnN; + u32 Mode1AllLat; + u32 Mode2Cwl; +}DRAM_MODE_REG_INFO; + +typedef struct _DRAM_TIMING_INFO_ { + u32 TrfcPs; + u32 TrefiPs; + u32 WrMaxTck; + u32 TrcdPs; + u32 TrpPs; + u32 TrasPs; + u32 TrrdTck; + u32 TwrPs; + u32 TwtrTck; + //u32 TrtpPs; + u32 TmrdTck; + u32 TrtpTck; + u32 TccdTck; + u32 TrcPs; +}DRAM_TIMING_INFO; + + +typedef struct _DRAM_DEVICE_INFO_ { + DRAM_INFO *Dev; + DRAM_MODE_REG_INFO *ModeReg; + DRAM_TIMING_INFO *Timing; + u32 DdrPeriodPs; + DFI_RATIO_TYPE *DfiRate; +}DRAM_DEVICE_INFO; + + +//====================================================== +//DRAM Info +#ifdef CONFIG_FPGA + #define DRAM_INFO_TYPE DRAM_SDR + #define DRAM_INFO_COL_ADDR_WTH DRAM_COLADDR_9B + #define DRAM_INFO_BANK_SZ DRAM_BANK_4 + #define DRAM_INFO_DQ_WTH DRAM_DQ_16 +#else + #define DRAM_INFO_TYPE DRAM_SDR + #define DRAM_INFO_COL_ADDR_WTH DRAM_COLADDR_8B + #define DRAM_INFO_BANK_SZ DRAM_BANK_2 + #define DRAM_INFO_DQ_WTH DRAM_DQ_16 +#endif + +//====================================================== +//DRAM Timing +#ifdef CONFIG_SDR_100MHZ +#define DRAM_TIMING_TCK 10000 //ps +#endif +#ifdef CONFIG_SDR_50MHZ +#define DRAM_TIMING_TCK 20000 //ps +#endif +#ifdef CONFIG_SDR_25MHZ +#define DRAM_TIMING_TCK 40000 //ps +#endif +#ifdef CONFIG_SDR_12_5MHZ +#define DRAM_TIMING_TCK 80000 //ps +#endif + +#if 1 +#define DRAM_TIMING_TREF 64000 //us +#define DRAM_ROW_NUM 8192 //depends on row bit number + +#define DRAM_TIMING_TRFC 60000 //ps +#define DRAM_TIMING_TREFI ((u32)((DRAM_TIMING_TREF*1000)/DRAM_ROW_NUM)*1000) //ps +#define DRAM_TIMING_TWRMAXTCK 2 //tck +#define DRAM_TIMING_TRCD 15000 //ps +#define DRAM_TIMING_TRP 15000 //ps +#define DRAM_TIMING_TRAS 42000 //ps +#define DRAM_TIMING_TRRD 2 //tck +#define DRAM_TIMING_TWR ((u32)(DRAM_TIMING_TCK*2)) +#define DRAM_TIMING_TWTR 0 //tck +#define DRAM_TIMING_TMRD 2 //tck +#define DRAM_TIMING_TRTP 0 //tck +#define DRAM_TIMING_TCCD 1 //tck +#define DRAM_TIMING_TRC 60000 //ps +#else + +#define DRAM_TIMING_TREF 66000 //us +#define DRAM_ROW_NUM 8192 //depends on row bit number + +#define DRAM_TIMING_TRFC 66000 //ps +#define DRAM_TIMING_TREFI 63999800 +#define DRAM_TIMING_TWRMAXTCK 2 //tck +#define DRAM_TIMING_TRCD 15000 //ps +#define DRAM_TIMING_TRP 15000 //ps +#define DRAM_TIMING_TRAS 37000 //ps +#define DRAM_TIMING_TRRD 2 //tck +#define DRAM_TIMING_TWR 7000 +#define DRAM_TIMING_TWTR 0 //tck +#define DRAM_TIMING_TMRD 2 //tck +#define DRAM_TIMING_TRTP 0 //tck +#define DRAM_TIMING_TCCD 1 //tck +#define DRAM_TIMING_TRC 60000 //ps +#endif + +#define HAL_SDR_WRITE32(addr, value32) HAL_WRITE32(SDR_CTRL_BASE, addr, value32) +#define HAL_SDR_WRITE16(addr, value16) HAL_WRITE16(SDR_CTRL_BASE, addr, value16) +#define HAL_SDR_WRITE8(addr, value8) HAL_WRITE8(SDR_CTRL_BASE, addr, value8) +#define HAL_SDR_READ32(addr) HAL_READ32(SDR_CTRL_BASE, addr) +#define HAL_SDR_READ16(addr) HAL_READ16(SDR_CTRL_BASE, addr) +#define HAL_SDR_READ8(addr) HAL_READ8(SDR_CTRL_BASE, addr) + +#define HAL_SDRAM_WRITE32(addr, value32) HAL_WRITE32(SDR_SDRAM_BASE, addr, value32) +#define HAL_SDRAM_WRITE16(addr, value16) HAL_WRITE16(SDR_SDRAM_BASE, addr, value16) +#define HAL_SDRAM_WRITE8(addr, value8) HAL_WRITE8(SDR_SDRAM_BASE, addr, value8) +#define HAL_SDRAM_READ32(addr) HAL_READ32(SDR_SDRAM_BASE, addr) +#define HAL_SDRAM_READ16(addr) HAL_READ16(SDR_SDRAM_BASE, addr) +#define HAL_SDRAM_READ8(addr) HAL_READ8(SDR_SDRAM_BASE, addr) + + +#endif // end of "#ifndef _HAL_SDR_CONTROLLER_H_" diff --git a/lib/fwlib/hal_soc_ps_monitor.h b/lib/fwlib/hal_soc_ps_monitor.h new file mode 100644 index 0000000..9e43093 --- /dev/null +++ b/lib/fwlib/hal_soc_ps_monitor.h @@ -0,0 +1,278 @@ +#ifndef _HAL_SOCPWR_ +#define _HAL_SOCPWR_ + + + +#define MAX_BACKUP_SIZE 129 +#define MAXFUNC 10 +#define FSTREG 0xFF + +#define REG_VDR_ANACK_CAL_CTRL 0xA0 + +#define PS_MASK 0xFFFFFFFF + +//pwr state +#define HWACT 0 +#define HWCG 1 +#define HWINACT 2 +#define UNDEF 3 +#define ALLMET 0xff + +//SLP +#define SLP_STIMER BIT0 +#define SLP_GTIMER BIT1 +#define SLP_GPIO BIT2 +#define SLP_WL BIT3 +#define SLP_NFC BIT4 +#define SLP_SDIO BIT5 +#define SLP_USB BIT6 +#define SLP_TIMER33 BIT7 + +//DSTBY +#define DSTBY_STIMER BIT0 +#define DSTBY_NFC BIT1 +#define DSTBY_TIMER33 BIT2 +#define DSTBY_GPIO BIT3 + +//DS wake event +#define DS_TIMER33 BIT0 +#define DS_GPIO BIT1 + +enum power_state_idx{ + ACT = 0, + WFE = 1, + WFI = 2, + SNOOZE = 3, + SLPCG = 4, + SLPPG = 5, + DSTBY = 6, + DSLP = 7, + INACT = 8, + MAXSTATE = 9 +}; + +enum clk_idx{ + ANACK = 0, + A33CK = 1, +}; + + +typedef struct _power_state_{ + u8 FuncIdx; + u8 PowerState; +}POWER_STATE, *pPOWER_STATE; + +typedef struct _reg_power_state_{ + u8 FuncIdx; + u8 PwrState; +}REG_POWER_STATE, *pPREG_POWER_STATE; + +#if 0 +typedef struct _power_state_{ + u8 FuncIdx; + u8 PowerState; + u32 ReqDuration; + u32 RegCount; + u32 RemainDuration; +}POWER_STATE, *pPOWER_STATE; + +typedef struct _reg_power_state_{ + u8 FuncIdx; + u8 PwrState; + u32 ReqDuration; + //u8 StateIdx; +}REG_POWER_STATE, *pPREG_POWER_STATE; +#endif + +typedef struct _power_mgn_{ + u8 ActFuncCount; + POWER_STATE PwrState[MAXFUNC]; + u8 CurrentState; + u8 SDREn; + u32 MSPbackup[MAX_BACKUP_SIZE]; + u32 CPURegbackup[25]; + u32 CPUPSP; + u32 WakeEventFlag; + BOOL SleepFlag; + //u32 CPUReg[13]; + //u32 MSBackUp[128]; +}Power_Mgn, *pPower_Mgn; + +typedef struct _SYS_ADAPTER_ { + u8 function; +}SYS_ADAPTER, *PSYS_ADAPTER; + +extern Power_Mgn PwrAdapter; + +u8 ChangeSoCPwrState( + IN u8 RequestState, + IN u32 ReqCount +); + +VOID PrintCPU(VOID); +void WakeFromSLPPG(void); +VOID SOCPSTestApp(VOID *Data); + + +__inline static VOID +CPURegBackUp( + VOID +) +{ +#if defined (__ICCARM__) + // TODO: IAR has different way using assembly +#elif defined (__GNUC__) + //backup cpu reg + #if 0 + asm volatile + ( + "PUSH {PSR, PC, LR, R12,R3,R2,R1,R0}\n" + ); + #endif + #if 0 + asm volatile + ( + "PUSH {r0,r1,r2,r3,r4}\n" + ); + #endif + + asm volatile + ( + + "MOV %0, r0\n" + :"=r"(PwrAdapter.CPURegbackup[0]) + ::"memory" + ); + + asm volatile + ( + "MOV %0, r1\n" + :"=r"(PwrAdapter.CPURegbackup[1]) + ::"memory" + ); + + asm volatile + ( + "MOV %0, r2\n" + :"=r"(PwrAdapter.CPURegbackup[2]) + ::"memory" + ); + + asm volatile + ( + "MOV %0, r3\n" + :"=r"(PwrAdapter.CPURegbackup[3]) + ::"memory" + ); + + asm volatile + ( + "MOV %0, r4\n" + :"=r"(PwrAdapter.CPURegbackup[4]) + ::"memory" + ); + + asm volatile + ( + "MOV %0, r5\n" + :"=r"(PwrAdapter.CPURegbackup[5]) + ::"memory" + ); + + asm volatile + ( + "MOV %0, r6\n" + :"=r"(PwrAdapter.CPURegbackup[6]) + ::"memory" + ); + + asm volatile + ( + "MOV %0, r7\n" + :"=r"(PwrAdapter.CPURegbackup[7]) + ::"memory" + ); + + asm volatile + ( + "MOV %0, r8\n" + :"=r"(PwrAdapter.CPURegbackup[8]) + ::"memory" + ); + + asm volatile + ( + "MOV %0, r9\n" + :"=r"(PwrAdapter.CPURegbackup[9]) + ::"memory" + ); + + asm volatile + ( + "MOV %0, r10\n" + :"=r"(PwrAdapter.CPURegbackup[10]) + ::"memory" + ); + + asm volatile + ( + "MOV %0, r11\n" + :"=r"(PwrAdapter.CPURegbackup[11]) + ::"memory" + ); + asm volatile + ( + "MOV %0, r12\n" + :"=r"(PwrAdapter.CPURegbackup[12]) + ::"memory" + ); + + asm volatile + ( + "MOV %0, r13\n" + :"=r"(PwrAdapter.CPURegbackup[13]) + ::"memory" + ); + asm volatile + ( + //"MOV %0, r14\n" + "LDR %0, =SLPPG_WAKEUP_POINT\n" + "ADD %0, #1\n" + :"=r"(PwrAdapter.CPURegbackup[14]) + ::"memory" + ); + asm volatile + ( + "LDR %0, =SLPPG_WAKEUP_POINT\n" + "ADD %0, #1\n" + :"=r"(PwrAdapter.CPURegbackup[15]) + ::"memory" + ); + asm volatile + ( + "MRS %0, PSR\n" + :"=r"(PwrAdapter.CPURegbackup[16]) + ::"memory" + ); + +#if 1 + asm volatile + ( + "mov %0, r13\n" + "MOV %1, PC\n" + "MRS %2, CONTROL\n" + "MRS %3, PSP\n" + "MRS %4, MSP\n" + :"=r"(PwrAdapter.CPURegbackup[24]),"=r"(PwrAdapter.CPURegbackup[23]),"=r"(PwrAdapter.CPURegbackup[22]),"=r"(PwrAdapter.CPURegbackup[21]),"=r"(PwrAdapter.CPURegbackup[20]) + ::"memory" + ); +#endif + #ifdef CONFIG_SOC_PS_VERIFY + PrintCPU(); + #endif //#ifdef CONFIG_SOC_PS_VERIFY +#endif //#elif defined (__GNUC__) +} + +VOID RegPowerState(REG_POWER_STATE RegPwrState); + +#endif //_HAL_SOCPWR_ diff --git a/lib/fwlib/hal_spi_flash.h b/lib/fwlib/hal_spi_flash.h new file mode 100644 index 0000000..6a06a5b --- /dev/null +++ b/lib/fwlib/hal_spi_flash.h @@ -0,0 +1,254 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _HAL_SPIFLASH__ +#define _HAL_SPIFLASH__ +//====================================================== +// Header files + +#define SPIC_CALIBRATION_IN_NVM 1 // if store the SPIC calibration data in the NVM +#ifndef CONFIG_IMAGE_SEPARATE // Store SPIC Calibration only for seprated image +#undef SPIC_CALIBRATION_IN_NVM +#define SPIC_CALIBRATION_IN_NVM 0 +#endif + +//====================================================== +// Definition +#define HAL_SPI_WRITE32(addr, value32) HAL_WRITE32(SPI_FLASH_CTRL_BASE, addr, value32) +#define HAL_SPI_WRITE16(addr, value16) HAL_WRITE16(SPI_FLASH_CTRL_BASE, addr, value16) +#define HAL_SPI_WRITE8(addr, value8) HAL_WRITE8(SPI_FLASH_CTRL_BASE, addr, value8) +#define HAL_SPI_READ32(addr) HAL_READ32(SPI_FLASH_CTRL_BASE, addr) +#define HAL_SPI_READ16(addr) HAL_READ16(SPI_FLASH_CTRL_BASE, addr) +#define HAL_SPI_READ8(addr) HAL_READ8(SPI_FLASH_CTRL_BASE, addr) + +typedef struct _SPIC_PARA_MODE_ { + u8 Valid:1; // valid + u8 CpuClk:3; // CPU clock + u8 BitMode:2; // Bit mode + u8 Reserved:2; // reserved +} SPIC_PARA_MODE, *PSPIC_PARA_MODE; + +typedef struct _SPIC_INIT_PARA_ { + u8 BaudRate; + u8 RdDummyCyle; + u8 DelayLine; + union { + u8 Rsvd; + u8 Valid; + SPIC_PARA_MODE Mode; + }; +#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES)) + u8 id[3]; + u8 flashtype; +#endif +}SPIC_INIT_PARA, *PSPIC_INIT_PARA; + + +enum _SPIC_BIT_MODE_ { + SpicOneBitMode = 0, + SpicDualBitMode = 1, + SpicQuadBitMode = 2, +}; + +//====================================================== +// Flash type used +#define FLASH_OTHERS 0 +#define FLASH_MXIC 1 +#define FLASH_WINBOND 2 +#define FLASH_MICRON 3 + +#define FLASH_MXIC_MX25L4006E 1 +#define FLASH_MXIC_MX25L8073E 0 + +// The below parts are based on the flash characteristics +//====== Flash Command Definition ====== +#if FLASH_MXIC_MX25L4006E + #define FLASH_CMD_WREN 0x06 //write enable + #define FLASH_CMD_WRDI 0x04 //write disable + #define FLASH_CMD_WRSR 0x01 //write status register + #define FLASH_CMD_RDID 0x9F //read idenfication + #define FLASH_CMD_RDSR 0x05 //read status register + #define FLASH_CMD_READ 0x03 //read data + #define FLASH_CMD_FREAD 0x0B //fast read data + #define FLASH_CMD_RDSFDP 0x5A //Read SFDP + #define FLASH_CMD_RES 0xAB //Read Electronic ID + #define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID + #define FLASH_CMD_DREAD 0x3B //Double Output Mode command + #define FLASH_CMD_SE 0x20 //Sector Erase + #define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52) + #define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7) + #define FLASH_CMD_PP 0x02 //Page Program + #define FLASH_CMD_DP 0xB9 //Deep Power Down + #define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down +#elif FLASH_MXIC_MX25L8073E + #define FLASH_CMD_WREN 0x06 //write enable + #define FLASH_CMD_WRDI 0x04 //write disable + #define FLASH_CMD_WRSR 0x01 //write status register + #define FLASH_CMD_RDID 0x9F //read idenfication + #define FLASH_CMD_RDSR 0x05 //read status register + #define FLASH_CMD_READ 0x03 //read data + #define FLASH_CMD_FREAD 0x0B //fast read data + #define FLASH_CMD_RDSFDP 0x5A //Read SFDP + #define FLASH_CMD_RES 0xAB //Read Electronic ID + #define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID + #define FLASH_CMD_DREAD 0x3B //Double Output Mode command + #define FLASH_CMD_SE 0x20 //Sector Erase + #define FLASH_CMD_BE 0x52 //Block Erase + #define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7) + #define FLASH_CMD_PP 0x02 //Page Program + #define FLASH_CMD_DP 0xB9 //Deep Power Down + #define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down + #define FLASH_CMD_2READ 0xBB // 2 x I/O read command + #define FLASH_CMD_4READ 0xEB // 4 x I/O read command + #define FLASH_CMD_QREAD 0x6B // 1I / 4O read command + #define FLASH_CMD_4PP 0x38 //quad page program + #define FLASH_CMD_FF 0xFF //Release Read Enhanced + #define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode + #define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode + #define FLASH_CMD_ENSO 0xB1 // enter secured OTP + #define FLASH_CMD_EXSO 0xC1 // exit secured OTP + #define FLASH_CMD_RDSCUR 0x2B // read security register + #define FLASH_CMD_WRSCUR 0x2F // write security register +#else + #define FLASH_CMD_WREN 0x06 //write enable + #define FLASH_CMD_WRDI 0x04 //write disable + #define FLASH_CMD_WRSR 0x01 //write status register + #define FLASH_CMD_RDID 0x9F //read idenfication + #define FLASH_CMD_RDSR 0x05 //read status register + #define FLASH_CMD_READ 0x03 //read data + #define FLASH_CMD_FREAD 0x0B //fast read data + #define FLASH_CMD_RDSFDP 0x5A //Read SFDP + #define FLASH_CMD_RES 0xAB //Read Electronic ID + #define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID + #define FLASH_CMD_DREAD 0x3B //Double Output Mode command + #define FLASH_CMD_SE 0x20 //Sector Erase + #define FLASH_CMD_BE 0x52 //Block Erase + #define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7) + #define FLASH_CMD_PP 0x02 //Page Program + #define FLASH_CMD_DP 0xB9 //Deep Power Down + #define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down + #define FLASH_CMD_2READ 0xBB // 2 x I/O read command + #define FLASH_CMD_4READ 0xEB // 4 x I/O read command + #define FLASH_CMD_QREAD 0x6B // 1I / 4O read command + #define FLASH_CMD_4PP 0x38 //quad page program + #define FLASH_CMD_FF 0xFF //Release Read Enhanced + #define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode + #define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode + #define FLASH_CMD_ENSO 0xB1 // enter secured OTP + #define FLASH_CMD_EXSO 0xC1 // exit secured OTP + #define FLASH_CMD_RDSCUR 0x2B // read security register + #define FLASH_CMD_WRSCUR 0x2F // write security register +#endif //#if FLASH_MXIC_MX25L4006E +// ============================ + +// ===== Flash Parameter Definition ===== +#if FLASH_MXIC_MX25L4006E + #define FLASH_RD_2IO_EN 0 + #define FLASH_RD_2O_EN 1 + #define FLASH_RD_4IO_EN 0 + #define FLASH_RD_4O_EN 0 + #define FLASH_WR_2IO_EN 0 + #define FLASH_WR_2O_EN 0 + #define FLASH_WR_4IO_EN 0 + #define FLASH_WR_4O_EN 0 + + #define FLASH_DM_CYCLE_2O 0x08 + #define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_I) + #define FLASH_VLD_QUAD_CMDS (0) + +#elif FLASH_MXIC_MX25L8073E //This flash model is just for prototype, if you want to use it, + //the code MUST be rechecked according to the flash spec. + #define FLASH_RD_2IO_EN 1 + #define FLASH_RD_2O_EN 0 + #define FLASH_RD_4IO_EN 1 + #define FLASH_RD_4O_EN 0 + #define FLASH_WR_2IO_EN 1 + #define FLASH_WR_2O_EN 0 + #define FLASH_WR_4IO_EN 1 + #define FLASH_WR_4O_EN 0 + + #define FLASH_DM_CYCLE_2O 0x08 + #define FLASH_DM_CYCLE_2IO 0x04 + #define FLASH_DM_CYCLE_4O 0x08 + #define FLASH_DM_CYCLE_4IO 0x04 + + #define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO) + #define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO) +#else + #define FLASH_RD_2IO_EN 1 + #define FLASH_RD_2O_EN 0 + #define FLASH_RD_4IO_EN 1 + #define FLASH_RD_4O_EN 0 + #define FLASH_WR_2IO_EN 1 + #define FLASH_WR_2O_EN 0 + #define FLASH_WR_4IO_EN 1 + #define FLASH_WR_4O_EN 0 + + #define FLASH_DM_CYCLE_2O 0x08 + #define FLASH_DM_CYCLE_2IO 0x04 + #define FLASH_DM_CYCLE_4O 0x08 + #define FLASH_DM_CYCLE_4IO 0x04 + + #define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO) + #define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO) +#endif +#if 0 +//====================================================== +// Function prototype +BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode); + +_LONG_CALL_ +extern VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara); + +// spi-flash controller initialization +_LONG_CALL_ +extern VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode); + +// wait sr[0] = 0, wait transmission done +_LONG_CALL_ +extern VOID SpicWaitBusyDoneRtl8195A(VOID); + +// wait spi-flash status register[0] = 0 +//_LONG_CALL_ +//extern VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara); +#endif + +//====================================================== +// ROM Function prototype +_LONG_CALL_ VOID SpiFlashAppV02(IN VOID *Data); +_LONG_CALL_ROM_ VOID SpicInitRtl8195AV02(IN u8 InitBaudRate,IN u8 SpicBitMode); + +_LONG_CALL_ROM_ VOID SpicEraseFlashRtl8195AV02(VOID); + +_LONG_CALL_ROM_ VOID SpicLoadInitParaFromClockRtl8195AV02(IN u8 CpuClkMode,IN u8 BaudRate,IN PSPIC_INIT_PARA pSpicInitPara); + + +VOID SpicBlockEraseFlashRtl8195A(IN u32 Address); +VOID SpicSectorEraseFlashRtl8195A(IN u32 Address); +VOID SpicDieEraseFlashRtl8195A(IN u32 Address); +VOID SpicWriteProtectFlashRtl8195A(IN u32 Protect); +VOID SpicWaitWipDoneRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara); +VOID SpicWaitOperationDoneRtl8195A(IN SPIC_INIT_PARA SpicInitPara); +VOID SpicRxCmdRefinedRtl8195A(IN u8 cmd,IN SPIC_INIT_PARA SpicInitPara); +u8 SpicGetFlashStatusRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara); +VOID SpicInitRefinedRtl8195A(IN u8 InitBaudRate,IN u8 SpicBitMode); +u32 SpicWaitWipRtl8195A(VOID); +u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk); +VOID SpicDisableRtl8195A(VOID); +VOID SpicDeepPowerDownFlashRtl8195A(VOID); +VOID SpicUserProgramRtl8195A(IN u8 * data, IN SPIC_INIT_PARA SpicInitPara, IN u32 addr, IN u32 * LengthInfo); + +#if SPIC_CALIBRATION_IN_NVM +VOID SpicNVMCalLoad(u8 BitMode, u8 CpuClk); +VOID SpicNVMCalLoadAll(void); +VOID SpicNVMCalStore(u8 BitMode, u8 CpuClk); +#endif // #if SPIC_CALIBRATION_IN_NVM + +#endif //_HAL_SPIFLASH__ diff --git a/lib/fwlib/hal_ssi.h b/lib/fwlib/hal_ssi.h new file mode 100644 index 0000000..5248234 --- /dev/null +++ b/lib/fwlib/hal_ssi.h @@ -0,0 +1,309 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_SSI_H_ +#define _HAL_SSI_H_ + +#include "rtl8195a_ssi.h" + +/** + * LOG Configurations + */ + +extern u32 SSI_DBG_CONFIG; +extern uint8_t SPI0_IS_AS_SLAVE; + + +#define SSI_DBG_ENTRANCE(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENTRANCE)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE ANSI_COLOR_GREEN __VA_ARGS__ ANSI_COLOR_RESET); \ +}while(0) + +#define SSI_DBG_INIT(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +#define SSI_DBG_INIT_V(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_V)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +#define SSI_DBG_INIT_VV(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_VV)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +#define SSI_DBG_PINMUX(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_PINMUX)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +#define SSI_DBG_ENDIS(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENDIS)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +#define SSI_DBG_INT(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +#define SSI_DBG_INT_V(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_V)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +#define SSI_DBG_INT_HNDLR(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_HNDLR)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +#define SSI_DBG_INT_READ(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_READ)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +#define SSI_DBG_INT_WRITE(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_WRITE)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +#define SSI_DBG_STATUS(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_STATUS)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +#define SSI_DBG_FIFO(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_FIFO)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +#define SSI_DBG_READ(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_READ)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +#define SSI_DBG_WRITE(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_WRITE)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +#define SSI_DBG_SLV_CTRL(...) do {\ + if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_SLV_CTRL)) \ + DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ +}while(0) + +typedef enum _SSI_DBG_TYPE_LIST_ { + DBG_TYPE_ENTRANCE = 1 << 0, + DBG_TYPE_INIT = 1 << 1, + DBG_TYPE_INIT_V = 1 << 2, + DBG_TYPE_INIT_VV = 1 << 3, + DBG_TYPE_PINMUX = 1 << 4, + DBG_TYPE_ENDIS = 1 << 5, + DBG_TYPE_INT = 1 << 6, + DBG_TYPE_INT_V = 1 << 7, + DBG_TYPE_INT_HNDLR = 1 << 8, + DBG_TYPE_INT_READ = 1 << 9, + DBG_TYPE_INT_WRITE = 1 << 10, + DBG_TYPE_STATUS = 1 << 11, + DBG_TYPE_FIFO = 1 << 12, + DBG_TYPE_READ = 1 << 13, + DBG_TYPE_WRITE = 1 << 14, + DBG_TYPE_SLV_CTRL = 1 << 15 +} SSI_DBG_TYPE_LIST, *PSSI_DBG_TYPE_LIST; + + typedef struct _SSI_DMA_CONFIG_ { + VOID *pHalGdmaOp; + VOID *pTxHalGdmaAdapter; + VOID *pRxHalGdmaAdapter; + u8 RxDmaBurstSize; + u8 TxDmaBurstSize; + u8 RxDmaEnable; + u8 TxDmaEnable; + IRQ_HANDLE RxGdmaIrqHandle; + IRQ_HANDLE TxGdmaIrqHandle; +}SSI_DMA_CONFIG, *PSSI_DMA_CONFIG; + +/** + * DesignWare SSI Configurations + */ +typedef struct _HAL_SSI_ADAPTOR_ { + SSI_DMA_CONFIG DmaConfig; + IRQ_HANDLE IrqHandle; + // + VOID (*RxCompCallback)(VOID *Para); + VOID *RxCompCbPara; + VOID *RxData; + VOID (*TxCompCallback)(VOID *Para); + VOID *TxCompCbPara; + VOID *TxData; + u32 DmaRxDataLevel; + u32 DmaTxDataLevel; + u32 InterruptPriority; + u32 RxLength; + u32 RxLengthRemainder; + u32 RxThresholdLevel; + u32 TxLength; + u32 TxThresholdLevel; + u32 SlaveSelectEnable; + // + u16 ClockDivider; + u16 DataFrameNumber; + // + u8 ControlFrameSize; + u8 DataFrameFormat; + u8 DataFrameSize; + u8 DmaControl; + u8 Index; + u8 InterruptMask; + u8 MicrowireDirection; + u8 MicrowireHandshaking; + u8 MicrowireTransferMode; + u8 PinmuxSelect; + u8 Role; + u8 SclkPhase; + u8 SclkPolarity; + u8 SlaveOutputEnable; + u8 TransferMode; + u8 TransferMechanism; + + // Extend + u32 Reserved1; + u8 DefaultRxThresholdLevel; +}HAL_SSI_ADAPTOR, *PHAL_SSI_ADAPTOR; + +typedef struct _HAL_SSI_OP_{ + HAL_Status (*HalSsiPinmuxEnable)(VOID *Adaptor); + HAL_Status (*HalSsiPinmuxDisable)(VOID *Adaptor); + HAL_Status (*HalSsiEnable)(VOID *Adaptor); + HAL_Status (*HalSsiDisable)(VOID *Adaptor); + HAL_Status (*HalSsiInit)(VOID *Adaptor); + HAL_Status (*HalSsiSetSclkPolarity)(VOID *Adaptor); + HAL_Status (*HalSsiSetSclkPhase)(VOID *Adaptor); + HAL_Status (*HalSsiWrite)(VOID *Adaptor, u32 value); + HAL_Status (*HalSsiLoadSetting)(VOID *Adaptor, VOID *Setting); + HAL_Status (*HalSsiSetInterruptMask)(VOID *Adaptor); + HAL_Status (*HalSsiSetDeviceRole)(VOID *Adaptor, u32 Role); + HAL_Status (*HalSsiInterruptEnable)(VOID *Adaptor); + HAL_Status (*HalSsiInterruptDisable)(VOID *Adaptor); + HAL_Status (*HalSsiReadInterrupt)(VOID *Adaptor, VOID *RxData, u32 Length); + HAL_Status (*HalSsiSetRxFifoThresholdLevel)(VOID *Adaptor); + HAL_Status (*HalSsiSetTxFifoThresholdLevel)(VOID *Adaptor); + HAL_Status (*HalSsiWriteInterrupt)(VOID *Adaptor, u8 *TxData, u32 Length); + HAL_Status (*HalSsiSetSlaveEnableRegister)(VOID *Adaptor, u32 SlaveIndex); + u32 (*HalSsiBusy)(VOID *Adaptor); + u32 (*HalSsiReadable)(VOID *Adaptor); + u32 (*HalSsiWriteable)(VOID *Adaptor); + u32 (*HalSsiGetInterruptMask)(VOID *Adaptor); + u32 (*HalSsiGetRxFifoLevel)(VOID *Adaptor); + u32 (*HalSsiGetTxFifoLevel)(VOID *Adaptor); + u32 (*HalSsiGetStatus)(VOID *Adaptor); + u32 (*HalSsiGetInterruptStatus)(VOID *Adaptor); + u32 (*HalSsiRead)(VOID *Adaptor); + u32 (*HalSsiGetRawInterruptStatus)(VOID *Adaptor); + u32 (*HalSsiGetSlaveEnableRegister)(VOID *Adaptor); +}HAL_SSI_OP, *PHAL_SSI_OP; + +typedef struct _DW_SSI_DEFAULT_SETTING_ { + VOID (*RxCompCallback)(VOID *Para); + VOID *RxCompCbPara; + VOID *RxData; + VOID (*TxCompCallback)(VOID *Para); + VOID *TxCompCbPara; + VOID *TxData; + u32 DmaRxDataLevel; + u32 DmaTxDataLevel; + u32 InterruptPriority; + u32 RxLength; + u32 RxLengthRemainder; + u32 RxThresholdLevel; + u32 TxLength; + u32 TxThresholdLevel; + u32 SlaveSelectEnable; + // + u16 ClockDivider; + u16 DataFrameNumber; + // + u8 ControlFrameSize; + u8 DataFrameFormat; + u8 DataFrameSize; + u8 DmaControl; + //u8 Index; + u8 InterruptMask; + u8 MicrowireDirection; + u8 MicrowireHandshaking; + u8 MicrowireTransferMode; + //u8 PinmuxSelect; + //u8 Role; + u8 SclkPhase; + u8 SclkPolarity; + u8 SlaveOutputEnable; + u8 TransferMode; + u8 TransferMechanism; +} DW_SSI_DEFAULT_SETTING, *PDW_SSI_DEFAULT_SETTING; + + +struct spi_s { + HAL_SSI_ADAPTOR spi_adp; + HAL_SSI_OP spi_op; + u32 irq_handler; + u32 irq_id; + u32 dma_en; + u32 state; + u8 sclk; +#ifdef CONFIG_GDMA_EN + HAL_GDMA_ADAPTER spi_gdma_adp_tx; + HAL_GDMA_ADAPTER spi_gdma_adp_rx; +#endif +}; + +VOID HalSsiOpInit(VOID *Adaptor); +static __inline__ VOID HalSsiSetSclk( + IN PHAL_SSI_ADAPTOR pHalSsiAdapter, + IN u32 ClkRate) +{ + HalSsiSetSclkRtl8195a((VOID*)pHalSsiAdapter, ClkRate); +} + +HAL_Status HalSsiInit(VOID * Data); +HAL_Status HalSsiDeInit(VOID * Data); +HAL_Status HalSsiEnable(VOID * Data); +HAL_Status HalSsiDisable(VOID * Data); + + +#ifdef CONFIG_GDMA_EN +HAL_Status HalSsiTxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter); +VOID HalSsiTxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter); +HAL_Status HalSsiRxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter); +VOID HalSsiRxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter); + +static __inline__ VOID +HalSsiDmaInit( + IN PHAL_SSI_ADAPTOR pHalSsiAdapter +) +{ + HalSsiDmaInitRtl8195a((void *)pHalSsiAdapter); +} + +static __inline__ HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length) +{ + return (HalSsiDmaSendRtl8195a(Adapter, pTxData, Length)); +} + +static __inline__ HAL_Status HalSsiDmaRecv(VOID *Adapter, u8 *pRxData, u32 Length) +{ + return (HalSsiDmaRecvRtl8195a(Adapter, pRxData, Length)); +} + + +#endif // end of "#ifdef CONFIG_GDMA_EN" + +#endif + diff --git a/lib/fwlib/hal_timer.h b/lib/fwlib/hal_timer.h new file mode 100644 index 0000000..2a1f660 --- /dev/null +++ b/lib/fwlib/hal_timer.h @@ -0,0 +1,59 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_TIMER_H_ +#define _HAL_TIMER_H_ +#include "basic_types.h" +#include "hal_platform.h" +#include "hal_irqn.h" +#include "rtl8195a/rtl8195a_timer.h" + +#define GTIMER_CLK_HZ (32768) +#define GTIMER_TICK_US (1000000/GTIMER_CLK_HZ) + +typedef enum _TIMER_MODE_ { + FREE_RUN_MODE = 0, + USER_DEFINED = 1 +}TIMER_MODE, *PTIMER_MODE; + + +typedef struct _TIMER_ADAPTER_ { + + u32 TimerLoadValueUs; + u32 TimerIrqPriority; + TIMER_MODE TimerMode; + IRQ_HANDLE IrqHandle; + u8 TimerId; + u8 IrqDis; + +}TIMER_ADAPTER, *PTIMER_ADAPTER; + + +typedef struct _HAL_TIMER_OP_ { + u32 (*HalGetTimerId)(u32 *TimerId); + BOOL (*HalTimerInit)(VOID *Data); + u32 (*HalTimerReadCount)(u32 TimerId); + VOID (*HalTimerIrqClear)(u32 TimerId); + VOID (*HalTimerDis)(u32 TimerId); + VOID (*HalTimerEn)(u32 TimerId); + VOID (*HalTimerDumpReg)(u32 TimerId); +}HAL_TIMER_OP, *PHAL_TIMER_OP; + +VOID HalTimerOpInit_Patch( + IN VOID *Data +); + + +//====================================================== +// ROM Function prototype +_LONG_CALL_ VOID HalTimerOpInitV02(IN VOID *Data); + +//#define HalTimerOpInit HalTimerOpInit_Patch + +#endif diff --git a/lib/fwlib/hal_uart.h b/lib/fwlib/hal_uart.h new file mode 100644 index 0000000..625382d --- /dev/null +++ b/lib/fwlib/hal_uart.h @@ -0,0 +1,204 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_UART_H_ +#define _HAL_UART_H_ + +#include "rtl8195a_uart.h" + +/** + * RUART Configurations + */ +#define UART_WAIT_FOREVER 0xffffffff + +typedef struct _UART_DMA_CONFIG_ { + u8 TxDmaEnable; + u8 RxDmaEnable; + u8 TxDmaBurstSize; + u8 RxDmaBurstSize; + VOID *pHalGdmaOp; + VOID *pTxHalGdmaAdapter; + VOID *pRxHalGdmaAdapter; + IRQ_HANDLE TxGdmaIrqHandle; + IRQ_HANDLE RxGdmaIrqHandle; +}UART_DMA_CONFIG, *PUART_DMA_CONFIG; + +typedef struct _HAL_RUART_ADAPTER_ { + u32 BaudRate; + u32 FlowControl; + u32 FifoControl; + u32 Interrupts; + u32 TxCount; // how many byte to TX + u32 RxCount; // how many bytes to RX + u8 *pTxBuf; + u8 *pRxBuf; + HAL_UART_State State; // UART state + u8 Status; // Transfer Status + u8 Locked; // is UART locked for operation + u8 UartIndex; + u8 WordLen; // word length select: 0 -> 7 bits, 1 -> 8 bits + u8 StopBit; // word length select: 0 -> 1 stop bit, 1 -> 2 stop bit + u8 Parity; // parity check enable + u8 ParityType; // parity check type + u8 StickParity; + u8 ModemStatus; // the modem status + u8 DmaEnable; + u8 TestCaseNumber; + u8 PinmuxSelect; + BOOL PullMode; + IRQ_HANDLE IrqHandle; + PUART_DMA_CONFIG DmaConfig; + VOID (*ModemStatusInd)(VOID *pAdapter); // modem status indication interrupt handler + VOID (*TxTDCallback)(VOID *pAdapter); // User Tx Done callback function + VOID (*RxDRCallback)(VOID *pAdapter); // User Rx Data ready callback function + VOID (*TxCompCallback)(VOID *para); // User Tx complete callback function + VOID (*RxCompCallback)(VOID *para); // User Rx complete callback function + VOID *TxTDCbPara; // the pointer agrument for TxTDCallback + VOID *RxDRCbPara; // the pointer agrument for RxDRCallback + VOID *TxCompCbPara; // the pointer argument for TxCompCbPara + VOID *RxCompCbPara; // the pointer argument for RxCompCallback + VOID (*EnterCritical)(void); + VOID (*ExitCritical)(void); + + //1 New member only can be added below: members above must be fixed for ROM code + u32 *pDefaultBaudRateTbl; // point to the table of pre-defined baud rate + u8 *pDefaultOvsrRTbl; // point to the table of OVSR for pre-defined baud rate + u16 *pDefaultDivTbl; // point to the table of DIV for pre-defined baud rate + u8 *pDefOvsrAdjBitTbl_10; // point to the table of OVSR-Adj bits for 10 bits + u8 *pDefOvsrAdjBitTbl_9; // point to the table of OVSR-Adj bits for 9 bits + u8 *pDefOvsrAdjBitTbl_8; // point to the table of OVSR-Adj bits for 8 bits + u16 *pDefOvsrAdjTbl_10; // point to the table of OVSR-Adj for pre-defined baud rate + u16 *pDefOvsrAdjTbl_9; // point to the table of OVSR-Adj for pre-defined baud rate + u16 *pDefOvsrAdjTbl_8; // point to the table of OVSR-Adj for pre-defined baud rate + u32 BaudRateUsing; // Current using Baud-Rate + +#if CONFIG_CHIP_E_CUT + u8 TxState; + u8 RxState; + u32 TxInitSize; // how many byte to TX at atart + u32 RxInitSize; // how many bytes to RX at start + + VOID (*RuartEnterCritical)(VOID *para); // enter critical: disable UART interrupt + VOID (*RuartExitCritical)(VOID *para); // exit critical: re-enable UART interrupt + VOID (*TaskYield)(VOID *para); // User Task Yield: do a context switch while waitting + VOID *TaskYieldPara; // the agrument (pointer) for TaskYield +#endif // #if CONFIG_CHIP_E_CUT +}HAL_RUART_ADAPTER, *PHAL_RUART_ADAPTER; + +typedef struct _HAL_RUART_OP_ { + VOID (*HalRuartAdapterLoadDef)(VOID *pAdp, u8 UartIdx); // Load UART adapter default setting + VOID (*HalRuartTxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load TX GDMA default setting + VOID (*HalRuartRxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load RX GDMA default setting + HAL_Status (*HalRuartResetRxFifo)(VOID *Data); + HAL_Status (*HalRuartInit)(VOID *Data); + VOID (*HalRuartDeInit)(VOID *Data); + HAL_Status (*HalRuartPutC)(VOID *Data, u8 TxData); + u32 (*HalRuartSend)(VOID *Data, u8 *pTxData, u32 Length, u32 Timeout); + HAL_Status (*HalRuartIntSend)(VOID *Data, u8 *pTxData, u32 Length); + HAL_Status (*HalRuartDmaSend)(VOID *Data, u8 *pTxData, u32 Length); + HAL_Status (*HalRuartStopSend)(VOID *Data); + HAL_Status (*HalRuartGetC)(VOID *Data, u8 *pRxByte); + u32 (*HalRuartRecv)(VOID *Data, u8 *pRxData, u32 Length, u32 Timeout); + HAL_Status (*HalRuartIntRecv)(VOID *Data, u8 *pRxData, u32 Length); + HAL_Status (*HalRuartDmaRecv)(VOID *Data, u8 *pRxData, u32 Length); + HAL_Status (*HalRuartStopRecv)(VOID *Data); + u8 (*HalRuartGetIMR)(VOID *Data); + VOID (*HalRuartSetIMR)(VOID *Data); + u32 (*HalRuartGetDebugValue)(VOID *Data, u32 DbgSel); + VOID (*HalRuartDmaInit)(VOID *Data); + VOID (*HalRuartRTSCtrl)(VOID *Data, BOOLEAN RtsCtrl); + VOID (*HalRuartRegIrq)(VOID *Data); + VOID (*HalRuartIntEnable)(VOID *Data); + VOID (*HalRuartIntDisable)(VOID *Data); +}HAL_RUART_OP, *PHAL_RUART_OP; + +typedef struct _RUART_DATA_ { + PHAL_RUART_ADAPTER pHalRuartAdapter; + BOOL PullMode; + u8 BinaryData; + u8 SendBuffer; + u8 RecvBuffer; +}RUART_DATA, *PRUART_DATA; + +typedef struct _RUART_ADAPTER_ { + PHAL_RUART_OP pHalRuartOp; + PHAL_RUART_ADAPTER pHalRuartAdapter; + PUART_DMA_CONFIG pHalRuartDmaCfg; +}RUART_ADAPTER, *PRUART_ADAPTER; + +extern VOID +HalRuartOpInit( + IN VOID *Data +); + +extern HAL_Status +HalRuartTxGdmaInit( + PHAL_RUART_OP pHalRuartOp, + PHAL_RUART_ADAPTER pHalRuartAdapter, + PUART_DMA_CONFIG pUartGdmaConfig +); + +extern VOID +HalRuartTxGdmaDeInit( + PUART_DMA_CONFIG pUartGdmaConfig +); + +extern HAL_Status +HalRuartRxGdmaInit( + PHAL_RUART_OP pHalRuartOp, + PHAL_RUART_ADAPTER pHalRuartAdapter, + PUART_DMA_CONFIG pUartGdmaConfig +); + +extern VOID +HalRuartRxGdmaDeInit( + PUART_DMA_CONFIG pUartGdmaConfig +); + +extern HAL_Status +HalRuartResetTxFifo( + VOID *Data +); + +extern HAL_Status +HalRuartSetBaudRate( + IN VOID *Data +); + +extern HAL_Status +HalRuartInit( + IN VOID *Data +); + +extern VOID +HalRuartDeInit( + IN VOID *Data +); + +extern HAL_Status +HalRuartDisable( + IN VOID *Data +); + +extern HAL_Status +HalRuartEnable( + IN VOID *Data +); + +HAL_Status +HalRuartFlowCtrl( + IN VOID *Data +); + +extern const HAL_RUART_OP _HalRuartOp; +extern HAL_Status RuartLock (PHAL_RUART_ADAPTER pHalRuartAdapter); +extern VOID RuartUnLock (PHAL_RUART_ADAPTER pHalRuartAdapter); + +#endif + diff --git a/lib/fwlib/hal_usb.h b/lib/fwlib/hal_usb.h new file mode 100644 index 0000000..3de8fa2 --- /dev/null +++ b/lib/fwlib/hal_usb.h @@ -0,0 +1,15 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _HAL_USB_H_ +#define _HAL_USB_H_ + +#include "rtl8195a_usb.h" + +#endif //_HAL_USB_H_ \ No newline at end of file diff --git a/lib/fwlib/hal_util.h b/lib/fwlib/hal_util.h new file mode 100644 index 0000000..183eb4c --- /dev/null +++ b/lib/fwlib/hal_util.h @@ -0,0 +1,252 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ +#ifndef _HAL_UTIL_H_ +#define _HAL_UTIL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Simple doubly linked list implementation. + * + * Some of the internal functions ("__xxx") are useful when + * manipulating whole lists rather than single entries, as + * sometimes we already know the next/prev entries and we can + * generate better code by using them directly rather than + * using the generic single-entry routines. + */ +struct LIST_HEADER { + struct LIST_HEADER *Next, *Prev; +}; + +typedef struct LIST_HEADER _LIST; + +//#define RTL_LIST_HEAD_INIT(name) { &(name), &(name) } + +#define RTL_INIT_LIST_HEAD(ptr) do { \ + (ptr)->Next = (ptr); (ptr)->Prev = (ptr); \ +} while (0) + + +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ + static __inline__ VOID + __List_Add( + IN struct LIST_HEADER * New, + IN struct LIST_HEADER * Prev, + IN struct LIST_HEADER * Next +) +{ + Next->Prev = New; + New->Next = Next; + New->Prev = Prev; + Prev->Next = New; +} + +/* + * Delete a list entry by making the prev/next entries + * point to each other. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ + static __inline__ VOID + __List_Del( + IN struct LIST_HEADER * Prev, + IN struct LIST_HEADER * Next + ) +{ + Next->Prev = Prev; + Prev->Next = Next; +} + +/** + * ListDel - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty on entry does not return true after this, the entry is in an undefined state. + */ +static __inline__ VOID +ListDel( + IN struct LIST_HEADER *Entry +) +{ + __List_Del(Entry->Prev, Entry->Next); +} + +/** + * ListDelInit - deletes entry from list and reinitialize it. + * @entry: the element to delete from the list. + */ +static __inline__ VOID +ListDelInit( + IN struct LIST_HEADER *Entry +) +{ + __List_Del(Entry->Prev, Entry->Next); + RTL_INIT_LIST_HEAD(Entry); + +} + +/** + * ListEmpty - tests whether a list is empty + * @head: the list to test. + */ +static __inline__ u32 +ListEmpty( + IN struct LIST_HEADER *Head +) +{ + return Head->Next == Head; +} + +/** + * ListSplice - join two lists + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static __inline__ VOID +ListSplice( + IN struct LIST_HEADER *List, + IN struct LIST_HEADER *Head +) +{ + struct LIST_HEADER *First = List->Next; + + if (First != List) { + struct LIST_HEADER *Last = List->Prev; + struct LIST_HEADER *At = Head->Next; + + First->Prev = Head; + Head->Next = First; + + Last->Next = At; + At->Prev = Last; + } +} + +static __inline__ VOID +ListAdd( + IN struct LIST_HEADER *New, + IN struct LIST_HEADER *head +) +{ + __List_Add(New, head, head->Next); +} + + +static __inline__ VOID +ListAddTail( + IN struct LIST_HEADER *New, + IN struct LIST_HEADER *head +) +{ + __List_Add(New, head->Prev, head); +} + +static __inline VOID +RtlInitListhead( + IN _LIST *list +) +{ + RTL_INIT_LIST_HEAD(list); +} + + +/* +For the following list_xxx operations, +caller must guarantee the atomic context. +Otherwise, there will be racing condition. +*/ +static __inline u32 +RtlIsListEmpty( + IN _LIST *phead +) +{ + + if (ListEmpty(phead)) + return _TRUE; + else + return _FALSE; + +} + +static __inline VOID +RtlListInsertHead( + IN _LIST *plist, + IN _LIST *phead +) +{ + ListAdd(plist, phead); +} + +static __inline VOID +RtlListInsertTail( + IN _LIST *plist, + IN _LIST *phead +) +{ + ListAddTail(plist, phead); +} + + +static __inline _LIST +*RtlListGetNext( + IN _LIST *plist +) +{ + return plist->Next; +} + +static __inline VOID +RtlListDelete( + IN _LIST *plist +) +{ + ListDelInit(plist); +} + +#define RTL_LIST_CONTAINOR(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) + +#ifndef CONTAINER_OF +#define CONTAINER_OF(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) +#endif +/* +#define list_entry(ptr, type, member) \ + CONTAINER_OF(ptr, type, member) + +#define list_first_entry(ptr, type, member) \ + list_entry((ptr)->Next, type, member) + +#define list_next_entry(pos, member, type) \ + list_entry((pos)->member.Next, type, member) + +#define list_for_each_entry(pos, head, member, type) \ + for (pos = list_first_entry(head, type, member); \ + &pos->member != (head); \ + pos = list_next_entry(pos, member, type)) +#define list_for_each(pos, head) \ + for (pos = (head)->Next; pos != (head); pos = pos->Next) +*/ + +#ifndef BIT + #define BIT(x) ( 1 << (x)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif //_HAL_UTIL_H_ diff --git a/lib/fwlib/hal_vector_table.h b/lib/fwlib/hal_vector_table.h new file mode 100644 index 0000000..e1eb2fb --- /dev/null +++ b/lib/fwlib/hal_vector_table.h @@ -0,0 +1,53 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _HAL_VECTOR_TABLE_H_ +#define _HAL_VECTOR_TABLE_H_ + + + + +extern _LONG_CALL_ROM_ VOID +VectorTableInitRtl8195A( + IN u32 StackP +); + +extern _LONG_CALL_ROM_ VOID +VectorTableInitForOSRtl8195A( + IN VOID *PortSVC, + IN VOID *PortPendSVH, + IN VOID *PortSysTick +); + +extern _LONG_CALL_ROM_ BOOL +VectorIrqRegisterRtl8195A( + IN PIRQ_HANDLE pIrqHandle +); + +extern _LONG_CALL_ROM_ BOOL +VectorIrqUnRegisterRtl8195A( + IN PIRQ_HANDLE pIrqHandle +); + + +extern _LONG_CALL_ROM_ VOID +VectorIrqEnRtl8195A( + IN PIRQ_HANDLE pIrqHandle +); + +extern _LONG_CALL_ROM_ VOID +VectorIrqDisRtl8195A( + IN PIRQ_HANDLE pIrqHandle +); + + +extern _LONG_CALL_ROM_ VOID +HalPeripheralIntrHandle(VOID); +#endif //_HAL_VECTOR_TABLE_H_ diff --git a/lib/fwlib/rtl8195a/rtl8195a.h b/lib/fwlib/rtl8195a/rtl8195a.h new file mode 100644 index 0000000..83c47e7 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a.h @@ -0,0 +1,157 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ +#ifndef _HAL_8195A_H_ +#define _HAL_8195A_H_ + +#include "platform_autoconf.h" +#include "basic_types.h" +#include "section_config.h" +#include "rtl8195a_sys_on.h" +#include "rtl8195a_peri_on.h" +#include "hal_platform.h" +#include "hal_pinmux.h" +#include "hal_api.h" +#include "hal_peri_on.h" +#include "hal_misc.h" +#include "hal_irqn.h" +#include "hal_vector_table.h" +#include "hal_diag.h" +#include "hal_spi_flash.h" +#include "hal_timer.h" +#include "hal_util.h" +#include "hal_efuse.h" +#include "hal_soc_ps_monitor.h" +#include "diag.h" +#include "hal_common.h" +#include "hal_soc_ps_monitor.h" + +/* ---------------------------------------------------------------------------- + -- Cortex M3 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration + * @{ + */ + +#define __CM3_REV 0x0200 /**< Core revision r0p0 */ +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 1 /**< Vendor specific implementation of SysTickConfig is defined */ + +#include "core_cm3.h" + +#ifdef CONFIG_TIMER_EN +#include "hal_timer.h" +#endif + +#ifdef CONFIG_GDMA_EN +#include "hal_gdma.h" +#include "rtl8195a_gdma.h" +#endif + +#ifdef CONFIG_GPIO_EN +#include "hal_gpio.h" +#include "rtl8195a_gpio.h" +#endif + +#ifdef CONFIG_SPI_COM_EN +#include "hal_ssi.h" +#include "rtl8195a_ssi.h" +#endif + +#ifdef CONFIG_UART_EN +#include "hal_uart.h" +#include "rtl8195a_uart.h" +#endif + +#ifdef CONFIG_I2C_EN +#include "hal_i2c.h" +#include "rtl8195a_i2c.h" +#endif + +#ifdef CONFIG_PCM_EN +#include "hal_pcm.h" +#include "rtl8195a_pcm.h" +#endif + +#ifdef CONFIG_PWM_EN +#include "hal_pwm.h" +#include "rtl8195a_pwm.h" +#endif + +#ifdef CONFIG_I2S_EN +#include "hal_i2s.h" +#include "rtl8195a_i2s.h" +#endif + +#ifdef CONFIG_DAC_EN +#include "hal_dac.h" +#include "rtl8195a_dac.h" +#endif + + +#include "hal_adc.h" +#include "rtl8195a_adc.h" + + +#ifdef CONFIG_SDR_EN +#endif + +#ifdef CONFIG_SPIC_EN +#endif + +#ifdef CONFIG_SDIO_DEVICE_EN +#include "hal_sdio.h" +#endif + +#ifdef CONFIG_NFC_EN +#include "hal_nfc.h" +#include "rtl8195a_nfc.h" +#endif + +#ifdef CONFIG_WDG +#include "rtl8195a_wdt.h" +#endif + +#ifdef CONFIG_USB_EN +#include "hal_usb.h" +#include "rtl8195a_usb.h" +#endif + + +// firmware information, located at the header of Image2 +#define FW_VERSION (0x0100) +#define FW_SUBVERSION (0x0001) +#define FW_CHIP_ID (0x8195) +#define FW_CHIP_VER (0x01) +#define FW_BUS_TYPE (0x01) // the iNIC firmware type: USB/SDIO +#define FW_INFO_RSV1 (0x00) // the firmware information reserved +#define FW_INFO_RSV2 (0x00) // the firmware information reserved +#define FW_INFO_RSV3 (0x00) // the firmware information reserved +#define FW_INFO_RSV4 (0x00) // the firmware information reserved + +#define FLASH_RESERVED_DATA_BASE 0x8000 // reserve 32K for Image1 +#define FLASH_SYSTEM_DATA_ADDR 0x9000 // reserve 32K+4K for Image1 + Reserved data +// Flash Map for Calibration data +#define FLASH_CAL_DATA_BASE 0xA000 +#define FLASH_CAL_DATA_ADDR(_offset) (FLASH_CAL_DATA_BASE + _offset) +#define FLASH_CAL_DATA_SIZE 0x1000 +#define FLASH_SECTOR_SIZE 0x1000 +// SPIC Calibration Data +#define FLASH_SPIC_PARA_OFFSET 0x80 +#define FLASH_SPIC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SPIC_PARA_OFFSET) +// SDRC Calibration Data +#define FLASH_SDRC_PARA_OFFSET 0x180 +#define FLASH_SDRC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SDRC_PARA_OFFSET) +// ADC Calibration Data +#define FLASH_ADC_PARA_OFFSET 0x200 +#define FLASH_ADC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_ADC_PARA_OFFSET) + +#endif //_HAL_8195A_H_ diff --git a/lib/fwlib/rtl8195a/rtl8195a_adc.h b/lib/fwlib/rtl8195a/rtl8195a_adc.h new file mode 100644 index 0000000..48240b0 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_adc.h @@ -0,0 +1,350 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _RTL8195A_ADC_H_ +#define _RTL8195A_ADC_H_ + + +//================ Register Bit Field ========================== +//2 REG_ADC_FIFO_READ + +#define BIT_SHIFT_ADC_FIFO_RO 0 +#define BIT_MASK_ADC_FIFO_RO 0xffffffffL +#define BIT_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO) +#define BIT_CTRL_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO) +#define BIT_GET_ADC_FIFO_RO(x) (((x) >> BIT_SHIFT_ADC_FIFO_RO) & BIT_MASK_ADC_FIFO_RO) + + +//2 REG_ADC_CONTROL + +#define BIT_SHIFT_ADC_DBG_SEL 24 +#define BIT_MASK_ADC_DBG_SEL 0x7 +#define BIT_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL) +#define BIT_CTRL_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL) +#define BIT_GET_ADC_DBG_SEL(x) (((x) >> BIT_SHIFT_ADC_DBG_SEL) & BIT_MASK_ADC_DBG_SEL) + + +#define BIT_SHIFT_ADC_THRESHOLD 16 +#define BIT_MASK_ADC_THRESHOLD 0x3f +#define BIT_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD) +#define BIT_CTRL_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD) +#define BIT_GET_ADC_THRESHOLD(x) (((x) >> BIT_SHIFT_ADC_THRESHOLD) & BIT_MASK_ADC_THRESHOLD) + + +#define BIT_SHIFT_ADC_BURST_SIZE 8 +#define BIT_MASK_ADC_BURST_SIZE 0x1f +#define BIT_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE) +#define BIT_CTRL_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE) +#define BIT_GET_ADC_BURST_SIZE(x) (((x) >> BIT_SHIFT_ADC_BURST_SIZE) & BIT_MASK_ADC_BURST_SIZE) + +#define BIT_ADC_ENDIAN BIT(3) +#define BIT_SHIFT_ADC_ENDIAN 3 +#define BIT_MASK_ADC_ENDIAN 0x1 +#define BIT_CTRL_ADC_ENDIAN(x) (((x) & BIT_MASK_ADC_ENDIAN) << BIT_SHIFT_ADC_ENDIAN) + +#define BIT_ADC_OVERWRITE BIT(2) +#define BIT_SHIFT_ADC_OVERWRITE 2 +#define BIT_MASK_ADC_OVERWRITE 0x1 +#define BIT_CTRL_ADC_OVERWRITE(x) (((x) & BIT_MASK_ADC_OVERWRITE) << BIT_SHIFT_ADC_OVERWRITE) + +#define BIT_ADC_ONESHOT BIT(1) +#define BIT_SHIFT_ADC_ONESHOT 1 +#define BIT_MASK_ADC_ONESHOT 0x1 +#define BIT_CTRL_ADC_ONESHOT(x) (((x) & BIT_MASK_ADC_ONESHOT) << BIT_SHIFT_ADC_ONESHOT) + +#define BIT_ADC_COMP_ONLY BIT(0) +#define BIT_SHIFT_ADC_COMP_ONLY 0 +#define BIT_MASK_ADC_COMP_ONLY 0x1 +#define BIT_CTRL_ADC_COMP_ONLY(x) (((x) & BIT_MASK_ADC_COMP_ONLY) << BIT_SHIFT_ADC_COMP_ONLY) + + +//2 REG_ADC_INTR_EN +#define BIT_ADC_AWAKE_CPU_EN BIT(7) +#define BIT_SHIFT_ADC_AWAKE_CPU_EN 7 +#define BIT_MASK_ADC_AWAKE_CPU_EN 0x1 +#define BIT_CTRL_ADC_AWAKE_CPU_EN(x) (((x) & BIT_MASK_ADC_AWAKE_CPU_EN) << BIT_SHIFT_ADC_AWAKE_CPU_EN) + +#define BIT_ADC_FIFO_RD_ERROR_EN BIT(6) +#define BIT_SHIFT_ADC_FIFO_RD_ERROR_EN 6 +#define BIT_MASK_ADC_FIFO_RD_ERROR_EN 0x1 +#define BIT_CTRL_ADC_FIFO_RD_ERROR_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_EN) << BIT_SHIFT_ADC_FIFO_RD_ERROR_EN) + +#define BIT_ADC_FIFO_RD_REQ_EN BIT(5) +#define BIT_SHIFT_ADC_FIFO_RD_REQ_EN 5 +#define BIT_MASK_ADC_FIFO_RD_REQ_EN 0x1 +#define BIT_CTRL_ADC_FIFO_RD_REQ_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_EN) << BIT_SHIFT_ADC_FIFO_RD_REQ_EN) + +#define BIT_ADC_FIFO_FULL_EN BIT(4) +#define BIT_SHIFT_ADC_FIFO_FULL_EN 4 +#define BIT_MASK_ADC_FIFO_FULL_EN 0x1 +#define BIT_CTRL_ADC_FIFO_FULL_EN(x) (((x) & BIT_MASK_ADC_FIFO_FULL_EN) << BIT_SHIFT_ADC_FIFO_FULL_EN) + +#define BIT_ADC_COMP_3_EN BIT(3) +#define BIT_SHIFT_ADC_COMP_3_EN 3 +#define BIT_MASK_ADC_COMP_3_EN 0x1 +#define BIT_CTRL_ADC_COMP_3_EN(x) (((x) & BIT_MASK_ADC_COMP_3_EN) << BIT_SHIFT_ADC_COMP_3_EN) + +#define BIT_ADC_COMP_2_EN BIT(2) +#define BIT_SHIFT_ADC_COMP_2_EN 2 +#define BIT_MASK_ADC_COMP_2_EN 0x1 +#define BIT_CTRL_ADC_COMP_2_EN(x) (((x) & BIT_MASK_ADC_COMP_2_EN) << BIT_SHIFT_ADC_COMP_2_EN) + +#define BIT_ADC_COMP_1_EN BIT(1) +#define BIT_SHIFT_ADC_COMP_1_EN 1 +#define BIT_MASK_ADC_COMP_1_EN 0x1 +#define BIT_CTRL_ADC_COMP_1_EN(x) (((x) & BIT_MASK_ADC_COMP_1_EN) << BIT_SHIFT_ADC_COMP_1_EN) + +#define BIT_ADC_COMP_0_EN BIT(0) +#define BIT_SHIFT_ADC_COMP_0_EN 0 +#define BIT_MASK_ADC_COMP_0_EN 0x1 +#define BIT_CTRL_ADC_COMP_0_EN(x) (((x) & BIT_MASK_ADC_COMP_0_EN) << BIT_SHIFT_ADC_COMP_0_EN) + + +//2 REG_ADC_INTR_STS +#define BIT_ADC_FIFO_THRESHOLD BIT(7) +#define BIT_SHIFT_ADC_FIFO_THRESHOLD 7 +#define BIT_MASK_ADC_FIFO_THRESHOLD 0x1 +#define BIT_CTRL_ADC_FIFO_THRESHOLD(x) (((x) & BIT_MASK_ADC_FIFO_THRESHOLD) << BIT_SHIFT_ADC_FIFO_THRESHOLD) + +#define BIT_ADC_FIFO_RD_ERROR_ST BIT(6) +#define BIT_SHIFT_ADC_FIFO_RD_ERROR_ST 6 +#define BIT_MASK_ADC_FIFO_RD_ERROR_ST 0x1 +#define BIT_CTRL_ADC_FIFO_RD_ERROR_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_ST) << BIT_SHIFT_ADC_FIFO_RD_ERROR_ST) + +#define BIT_ADC_FIFO_RD_REQ_ST BIT(5) +#define BIT_SHIFT_ADC_FIFO_RD_REQ_ST 5 +#define BIT_MASK_ADC_FIFO_RD_REQ_ST 0x1 +#define BIT_CTRL_ADC_FIFO_RD_REQ_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_ST) << BIT_SHIFT_ADC_FIFO_RD_REQ_ST) + +#define BIT_ADC_FIFO_FULL_ST BIT(4) +#define BIT_SHIFT_ADC_FIFO_FULL_ST 4 +#define BIT_MASK_ADC_FIFO_FULL_ST 0x1 +#define BIT_CTRL_ADC_FIFO_FULL_ST(x) (((x) & BIT_MASK_ADC_FIFO_FULL_ST) << BIT_SHIFT_ADC_FIFO_FULL_ST) + +#define BIT_ADC_COMP_3_ST BIT(3) +#define BIT_SHIFT_ADC_COMP_3_ST 3 +#define BIT_MASK_ADC_COMP_3_ST 0x1 +#define BIT_CTRL_ADC_COMP_3_ST(x) (((x) & BIT_MASK_ADC_COMP_3_ST) << BIT_SHIFT_ADC_COMP_3_ST) + +#define BIT_ADC_COMP_2_ST BIT(2) +#define BIT_SHIFT_ADC_COMP_2_ST 2 +#define BIT_MASK_ADC_COMP_2_ST 0x1 +#define BIT_CTRL_ADC_COMP_2_ST(x) (((x) & BIT_MASK_ADC_COMP_2_ST) << BIT_SHIFT_ADC_COMP_2_ST) + +#define BIT_ADC_COMP_1_ST BIT(1) +#define BIT_SHIFT_ADC_COMP_1_ST 1 +#define BIT_MASK_ADC_COMP_1_ST 0x1 +#define BIT_CTRL_ADC_COMP_1_ST(x) (((x) & BIT_MASK_ADC_COMP_1_ST) << BIT_SHIFT_ADC_COMP_1_ST) + +#define BIT_ADC_COMP_0_ST BIT(0) +#define BIT_SHIFT_ADC_COMP_0_ST 0 +#define BIT_MASK_ADC_COMP_0_ST 0x1 +#define BIT_CTRL_ADC_COMP_0_ST(x) (((x) & BIT_MASK_ADC_COMP_0_ST) << BIT_SHIFT_ADC_COMP_0_ST) + + +//2 REG_ADC_COMP_VALUE_L + +#define BIT_SHIFT_ADC_COMP_TH_1 16 +#define BIT_MASK_ADC_COMP_TH_1 0xffff +#define BIT_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1) +#define BIT_CTRL_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1) +#define BIT_GET_ADC_COMP_TH_1(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_1) & BIT_MASK_ADC_COMP_TH_1) + + +#define BIT_SHIFT_ADC_COMP_TH_0 0 +#define BIT_MASK_ADC_COMP_TH_0 0xffff +#define BIT_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0) +#define BIT_CTRL_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0) +#define BIT_GET_ADC_COMP_TH_0(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_0) & BIT_MASK_ADC_COMP_TH_0) + + +//2 REG_ADC_COMP_VALUE_H + +#define BIT_SHIFT_ADC_COMP_TH_3 16 +#define BIT_MASK_ADC_COMP_TH_3 0xffff +#define BIT_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3) +#define BIT_CTRL_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3) +#define BIT_GET_ADC_COMP_TH_3(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_3) & BIT_MASK_ADC_COMP_TH_3) + + +#define BIT_SHIFT_ADC_COMP_TH_2 0 +#define BIT_MASK_ADC_COMP_TH_2 0xffff +#define BIT_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2) +#define BIT_CTRL_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2) +#define BIT_GET_ADC_COMP_TH_2(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_2) & BIT_MASK_ADC_COMP_TH_2) + + +//2 REG_ADC_COMP_SET + +#define BIT_SHIFT_ADC_GREATER_THAN 0 +#define BIT_MASK_ADC_GREATER_THAN 0xf +#define BIT_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN) +#define BIT_CTRL_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN) +#define BIT_GET_ADC_GREATER_THAN(x) (((x) >> BIT_SHIFT_ADC_GREATER_THAN) & BIT_MASK_ADC_GREATER_THAN) + + +//2 REG_ADC_POWER + +#define BIT_SHIFT_ADC_PWR_CUT_CNTR 16 +#define BIT_MASK_ADC_PWR_CUT_CNTR 0xff +#define BIT_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR) +#define BIT_CTRL_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR) +#define BIT_GET_ADC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_ADC_PWR_CUT_CNTR) & BIT_MASK_ADC_PWR_CUT_CNTR) + +#define BIT_ADC_FIFO_ON_ST BIT(11) +#define BIT_SHIFT_ADC_FIFO_ON_ST 11 +#define BIT_MASK_ADC_FIFO_ON_ST 0x1 +#define BIT_CTRL_ADC_FIFO_ON_ST(x) (((x) & BIT_MASK_ADC_FIFO_ON_ST) << BIT_SHIFT_ADC_FIFO_ON_ST) + +#define BIT_ADC_ISO_ON_ST BIT(10) +#define BIT_SHIFT_ADC_ISO_ON_ST 10 +#define BIT_MASK_ADC_ISO_ON_ST 0x1 +#define BIT_CTRL_ADC_ISO_ON_ST(x) (((x) & BIT_MASK_ADC_ISO_ON_ST) << BIT_SHIFT_ADC_ISO_ON_ST) + +#define BIT_ADC_PWR33_ON_ST BIT(9) +#define BIT_SHIFT_ADC_PWR33_ON_ST 9 +#define BIT_MASK_ADC_PWR33_ON_ST 0x1 +#define BIT_CTRL_ADC_PWR33_ON_ST(x) (((x) & BIT_MASK_ADC_PWR33_ON_ST) << BIT_SHIFT_ADC_PWR33_ON_ST) + +#define BIT_ADC_PWR12_ON_ST BIT(8) +#define BIT_SHIFT_ADC_PWR12_ON_ST 8 +#define BIT_MASK_ADC_PWR12_ON_ST 0x1 +#define BIT_CTRL_ADC_PWR12_ON_ST(x) (((x) & BIT_MASK_ADC_PWR12_ON_ST) << BIT_SHIFT_ADC_PWR12_ON_ST) + +#define BIT_ADC_ISO_MANUAL BIT(3) +#define BIT_SHIFT_ADC_ISO_MANUAL 3 +#define BIT_MASK_ADC_ISO_MANUAL 0x1 +#define BIT_CTRL_ADC_ISO_MANUAL(x) (((x) & BIT_MASK_ADC_ISO_MANUAL) << BIT_SHIFT_ADC_ISO_MANUAL) + +#define BIT_ADC_PWR33_MANUAL BIT(2) +#define BIT_SHIFT_ADC_PWR33_MANUAL 2 +#define BIT_MASK_ADC_PWR33_MANUAL 0x1 +#define BIT_CTRL_ADC_PWR33_MANUAL(x) (((x) & BIT_MASK_ADC_PWR33_MANUAL) << BIT_SHIFT_ADC_PWR33_MANUAL) + +#define BIT_ADC_PWR12_MANUAL BIT(1) +#define BIT_SHIFT_ADC_PWR12_MANUAL 1 +#define BIT_MASK_ADC_PWR12_MANUAL 0x1 +#define BIT_CTRL_ADC_PWR12_MANUAL(x) (((x) & BIT_MASK_ADC_PWR12_MANUAL) << BIT_SHIFT_ADC_PWR12_MANUAL) + +#define BIT_ADC_PWR_AUTO BIT(0) +#define BIT_SHIFT_ADC_PWR_AUTO 0 +#define BIT_MASK_ADC_PWR_AUTO 0x1 +#define BIT_CTRL_ADC_PWR_AUTO(x) (((x) & BIT_MASK_ADC_PWR_AUTO) << BIT_SHIFT_ADC_PWR_AUTO) + + +//2 REG_ADC_ANAPAR_AD0 + +#define BIT_SHIFT_ADC_ANAPAR_AD0 2 +#define BIT_MASK_ADC_ANAPAR_AD0 0x3fffffff +#define BIT_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0) +#define BIT_CTRL_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0) +#define BIT_GET_ADC_ANAPAR_AD0(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD0) & BIT_MASK_ADC_ANAPAR_AD0) + +#define BIT_ADC_AUDIO_EN BIT(1) +#define BIT_SHIFT_ADC_AUDIO_EN 1 +#define BIT_MASK_ADC_AUDIO_EN 0x1 +#define BIT_CTRL_ADC_AUDIO_EN(x) (((x) & BIT_MASK_ADC_AUDIO_EN) << BIT_SHIFT_ADC_AUDIO_EN) + +#define BIT_ADC_EN_MANUAL BIT(0) +#define BIT_SHIFT_ADC_EN_MANUAL 0 +#define BIT_MASK_ADC_EN_MANUAL 0x1 +#define BIT_CTRL_ADC_EN_MANUAL(x) (((x) & BIT_MASK_ADC_EN_MANUAL) << BIT_SHIFT_ADC_EN_MANUAL) + + +//2 REG_ADC_ANAPAR_AD1 + +#define BIT_SHIFT_ADC_ANAPAR_AD1 0 +#define BIT_MASK_ADC_ANAPAR_AD1 0xffffffffL +#define BIT_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1) +#define BIT_CTRL_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1) +#define BIT_GET_ADC_ANAPAR_AD1(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD1) & BIT_MASK_ADC_ANAPAR_AD1) + + +//2 REG_ADC_ANAPAR_AD2 + +#define BIT_SHIFT_ADC_ANAPAR_AD2 0 +#define BIT_MASK_ADC_ANAPAR_AD2 0xffffffffL +#define BIT_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2) +#define BIT_CTRL_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2) +#define BIT_GET_ADC_ANAPAR_AD2(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD2) & BIT_MASK_ADC_ANAPAR_AD2) + + +//2 REG_ADC_ANAPAR_AD3 + +#define BIT_SHIFT_ADC_ANAPAR_AD3 0 +#define BIT_MASK_ADC_ANAPAR_AD3 0xffffffffL +#define BIT_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3) +#define BIT_CTRL_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3) +#define BIT_GET_ADC_ANAPAR_AD3(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD3) & BIT_MASK_ADC_ANAPAR_AD3) + + +//2 REG_ADC_ANAPAR_AD4 + +#define BIT_SHIFT_ADC_ANAPAR_AD4 0 +#define BIT_MASK_ADC_ANAPAR_AD4 0xffffffffL +#define BIT_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4) +#define BIT_CTRL_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4) +#define BIT_GET_ADC_ANAPAR_AD4(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD4) & BIT_MASK_ADC_ANAPAR_AD4) + + +//2 REG_ADC_ANAPAR_AD5 + +#define BIT_SHIFT_ADC_ANAPAR_AD5 0 +#define BIT_MASK_ADC_ANAPAR_AD5 0xffffffffL +#define BIT_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5) +#define BIT_CTRL_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5) +#define BIT_GET_ADC_ANAPAR_AD5(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD5) & BIT_MASK_ADC_ANAPAR_AD5) + + +//2 REG_ADC_CALI_DATA + +#define BIT_SHIFT_ADC_CALI_DATA_6 16 +#define BIT_MASK_ADC_CALI_DATA_6 0xffff +#define BIT_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6) +#define BIT_CTRL_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6) +#define BIT_GET_ADC_CALI_DATA_6(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_6) & BIT_MASK_ADC_CALI_DATA_6) + + +#define BIT_SHIFT_ADC_CALI_DATA_0 0 +#define BIT_MASK_ADC_CALI_DATA_0 0xffff +#define BIT_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0) +#define BIT_CTRL_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0) +#define BIT_GET_ADC_CALI_DATA_0(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_0) & BIT_MASK_ADC_CALI_DATA_0) + +//================ Register Reg Field ========================= +#define REG_ADC_FIFO_READ 0x0000 +#define REG_ADC_CONTROL 0x0004 +#define REG_ADC_INTR_EN 0x0008 +#define REG_ADC_INTR_STS 0x000C +#define REG_ADC_COMP_VALUE_L 0x0010 +#define REG_ADC_COMP_VALUE_H 0x0014 +#define REG_ADC_COMP_SET 0x0018 +#define REG_ADC_POWER 0x001C +#define REG_ADC_ANAPAR_AD0 0x0020 +#define REG_ADC_ANAPAR_AD1 0x0024 +#define REG_ADC_ANAPAR_AD2 0x0028 +#define REG_ADC_ANAPAR_AD3 0x002C +#define REG_ADC_ANAPAR_AD4 0x0030 +#define REG_ADC_ANAPAR_AD5 0x0034 +#define REG_ADC_CALI_DATA 0x0038 + +//================ ADC HAL related enumeration ================== + +//================ ADC Function Prototypes ===================== +#define HAL_ADC_WRITE32(addr, value) HAL_WRITE32(ADC_REG_BASE,addr,value) +#define HAL_ADC_READ32(addr) HAL_READ32(ADC_REG_BASE,addr) + +RTK_STATUS HalADCInit8195a(IN VOID *Data); +RTK_STATUS HalADCDeInit8195a(IN VOID *Data); +RTK_STATUS HalADCEnableRtl8195a(IN VOID *Data); +RTK_STATUS HalADCIntrCtrl8195a(IN VOID *Data); +u32 HalADCReceiveRtl8195a(IN VOID *Data); +u32 HalADCReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg); + +#endif diff --git a/lib/fwlib/rtl8195a/rtl8195a_dac.h b/lib/fwlib/rtl8195a/rtl8195a_dac.h new file mode 100644 index 0000000..c3a9861 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_dac.h @@ -0,0 +1,294 @@ +#ifndef _RTL8195A_DAC_H_ +#define _RTL8195A_DAC_H_ + +//================ Register Bit Field ========================== +//2 REG_DAC0_FIFO_WR + +#define BIT_SHIFT_DAC0_FIFO_WO 0 +#define BIT_MASK_DAC0_FIFO_WO 0xffffffffL +#define BIT_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO) +#define BIT_CTRL_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO) +#define BIT_GET_DAC0_FIFO_WO(x) (((x) >> BIT_SHIFT_DAC0_FIFO_WO) & BIT_MASK_DAC0_FIFO_WO) + + +//2 REG_DAC_CTRL + +#define BIT_SHIFT_DAC_DELTA_SIGMA 25 +#define BIT_MASK_DAC_DELTA_SIGMA 0x7 +#define BIT_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA) +#define BIT_CTRL_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA) +#define BIT_GET_DAC_DELTA_SIGMA(x) (((x) >> BIT_SHIFT_DAC_DELTA_SIGMA) & BIT_MASK_DAC_DELTA_SIGMA) + +#define BIT_DAC_BYPASS_DSC BIT(24) +#define BIT_SHIFT_DAC_BYPASS_DSC 24 +#define BIT_MASK_DAC_BYPASS_DSC 0x1 +#define BIT_CTRL_DAC_BYPASS_DSC(x) (((x) & BIT_MASK_DAC_BYPASS_DSC) << BIT_SHIFT_DAC_BYPASS_DSC) + + +#define BIT_SHIFT_DAC_DSC_DBG_SEL 19 +#define BIT_MASK_DAC_DSC_DBG_SEL 0x3 +#define BIT_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL) +#define BIT_CTRL_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL) +#define BIT_GET_DAC_DSC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DSC_DBG_SEL) & BIT_MASK_DAC_DSC_DBG_SEL) + + +#define BIT_SHIFT_DAC_DBG_SEL 16 +#define BIT_MASK_DAC_DBG_SEL 0x7 +#define BIT_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL) +#define BIT_CTRL_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL) +#define BIT_GET_DAC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DBG_SEL) & BIT_MASK_DAC_DBG_SEL) + + +#define BIT_SHIFT_DAC_BURST_SIZE 8 +#define BIT_MASK_DAC_BURST_SIZE 0xf +#define BIT_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE) +#define BIT_CTRL_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE) +#define BIT_GET_DAC_BURST_SIZE(x) (((x) >> BIT_SHIFT_DAC_BURST_SIZE) & BIT_MASK_DAC_BURST_SIZE) + +#define BIT_DAC_FILTER_SETTLE BIT(4) +#define BIT_SHIFT_DAC_FILTER_SETTLE 4 +#define BIT_MASK_DAC_FILTER_SETTLE 0x1 +#define BIT_CTRL_DAC_FILTER_SETTLE(x) (((x) & BIT_MASK_DAC_FILTER_SETTLE) << BIT_SHIFT_DAC_FILTER_SETTLE) + +#define BIT_DAC_OV_OPTION BIT(3) +#define BIT_SHIFT_DAC_OV_OPTION 3 +#define BIT_MASK_DAC_OV_OPTION 0x1 +#define BIT_CTRL_DAC_OV_OPTION(x) (((x) & BIT_MASK_DAC_OV_OPTION) << BIT_SHIFT_DAC_OV_OPTION) + +#define BIT_DAC_ENDIAN BIT(2) +#define BIT_SHIFT_DAC_ENDIAN 2 +#define BIT_MASK_DAC_ENDIAN 0x1 +#define BIT_CTRL_DAC_ENDIAN(x) (((x) & BIT_MASK_DAC_ENDIAN) << BIT_SHIFT_DAC_ENDIAN) + +#define BIT_DAC_SPEED BIT(1) +#define BIT_SHIFT_DAC_SPEED 1 +#define BIT_MASK_DAC_SPEED 0x1 +#define BIT_CTRL_DAC_SPEED(x) (((x) & BIT_MASK_DAC_SPEED) << BIT_SHIFT_DAC_SPEED) + +#define BIT_DAC_FIFO_EN BIT(0) +#define BIT_SHIFT_DAC_FIFO_EN 0 +#define BIT_MASK_DAC_FIFO_EN 0x1 +#define BIT_CTRL_DAC_FIFO_EN(x) (((x) & BIT_MASK_DAC_FIFO_EN) << BIT_SHIFT_DAC_FIFO_EN) + + +//2 REG_DAC_INTR_CTRL +#define BIT_DAC_DSC_OVERFLOW1_EN BIT(6) +#define BIT_SHIFT_DAC_DSC_OVERFLOW1_EN 6 +#define BIT_MASK_DAC_DSC_OVERFLOW1_EN 0x1 +#define BIT_CTRL_DAC_DSC_OVERFLOW1_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW1_EN) + +#define BIT_DAC_DSC_OVERFLOW0_EN BIT(5) +#define BIT_SHIFT_DAC_DSC_OVERFLOW0_EN 5 +#define BIT_MASK_DAC_DSC_OVERFLOW0_EN 0x1 +#define BIT_CTRL_DAC_DSC_OVERFLOW0_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW0_EN) + +#define BIT_DAC__WRITE_ERROR_EN BIT(4) +#define BIT_SHIFT_DAC__WRITE_ERROR_EN 4 +#define BIT_MASK_DAC__WRITE_ERROR_EN 0x1 +#define BIT_CTRL_DAC__WRITE_ERROR_EN(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_EN) << BIT_SHIFT_DAC__WRITE_ERROR_EN) + +#define BIT_DAC_FIFO_STOP_EN BIT(3) +#define BIT_SHIFT_DAC_FIFO_STOP_EN 3 +#define BIT_MASK_DAC_FIFO_STOP_EN 0x1 +#define BIT_CTRL_DAC_FIFO_STOP_EN(x) (((x) & BIT_MASK_DAC_FIFO_STOP_EN) << BIT_SHIFT_DAC_FIFO_STOP_EN) + +#define BIT_DAC_FIFO_OVERFLOW_EN BIT(2) +#define BIT_SHIFT_DAC_FIFO_OVERFLOW_EN 2 +#define BIT_MASK_DAC_FIFO_OVERFLOW_EN 0x1 +#define BIT_CTRL_DAC_FIFO_OVERFLOW_EN(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_EN) << BIT_SHIFT_DAC_FIFO_OVERFLOW_EN) + +#define BIT_DAC_FIFO_WR_REQ_EN BIT(1) +#define BIT_SHIFT_DAC_FIFO_WR_REQ_EN 1 +#define BIT_MASK_DAC_FIFO_WR_REQ_EN 0x1 +#define BIT_CTRL_DAC_FIFO_WR_REQ_EN(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_EN) << BIT_SHIFT_DAC_FIFO_WR_REQ_EN) + +#define BIT_DAC_FIFO_FULL_EN BIT(0) +#define BIT_SHIFT_DAC_FIFO_FULL_EN 0 +#define BIT_MASK_DAC_FIFO_FULL_EN 0x1 +#define BIT_CTRL_DAC_FIFO_FULL_EN(x) (((x) & BIT_MASK_DAC_FIFO_FULL_EN) << BIT_SHIFT_DAC_FIFO_FULL_EN) + + +//2 REG_DAC_INTR_STS +#define BIT_DAC_DSC_OVERFLOW1_ST BIT(6) +#define BIT_SHIFT_DAC_DSC_OVERFLOW1_ST 6 +#define BIT_MASK_DAC_DSC_OVERFLOW1_ST 0x1 +#define BIT_CTRL_DAC_DSC_OVERFLOW1_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW1_ST) + +#define BIT_DAC_DSC_OVERFLOW0_ST BIT(5) +#define BIT_SHIFT_DAC_DSC_OVERFLOW0_ST 5 +#define BIT_MASK_DAC_DSC_OVERFLOW0_ST 0x1 +#define BIT_CTRL_DAC_DSC_OVERFLOW0_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW0_ST) + +#define BIT_DAC__WRITE_ERROR_ST BIT(4) +#define BIT_SHIFT_DAC__WRITE_ERROR_ST 4 +#define BIT_MASK_DAC__WRITE_ERROR_ST 0x1 +#define BIT_CTRL_DAC__WRITE_ERROR_ST(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_ST) << BIT_SHIFT_DAC__WRITE_ERROR_ST) + +#define BIT_DAC_FIFO_STOP_ST BIT(3) +#define BIT_SHIFT_DAC_FIFO_STOP_ST 3 +#define BIT_MASK_DAC_FIFO_STOP_ST 0x1 +#define BIT_CTRL_DAC_FIFO_STOP_ST(x) (((x) & BIT_MASK_DAC_FIFO_STOP_ST) << BIT_SHIFT_DAC_FIFO_STOP_ST) + +#define BIT_DAC_FIFO_OVERFLOW_ST BIT(2) +#define BIT_SHIFT_DAC_FIFO_OVERFLOW_ST 2 +#define BIT_MASK_DAC_FIFO_OVERFLOW_ST 0x1 +#define BIT_CTRL_DAC_FIFO_OVERFLOW_ST(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_ST) << BIT_SHIFT_DAC_FIFO_OVERFLOW_ST) + +#define BIT_DAC_FIFO_WR_REQ_ST BIT(1) +#define BIT_SHIFT_DAC_FIFO_WR_REQ_ST 1 +#define BIT_MASK_DAC_FIFO_WR_REQ_ST 0x1 +#define BIT_CTRL_DAC_FIFO_WR_REQ_ST(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_ST) << BIT_SHIFT_DAC_FIFO_WR_REQ_ST) + +#define BIT_DAC_FIFO_FULL_ST BIT(0) +#define BIT_SHIFT_DAC_FIFO_FULL_ST 0 +#define BIT_MASK_DAC_FIFO_FULL_ST 0x1 +#define BIT_CTRL_DAC_FIFO_FULL_ST(x) (((x) & BIT_MASK_DAC_FIFO_FULL_ST) << BIT_SHIFT_DAC_FIFO_FULL_ST) + + +//2 REG_DAC_PWR_CTRL + +#define BIT_SHIFT_DAC_PWR_CUT_CNTR 16 +#define BIT_MASK_DAC_PWR_CUT_CNTR 0xff +#define BIT_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR) +#define BIT_CTRL_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR) +#define BIT_GET_DAC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_DAC_PWR_CUT_CNTR) & BIT_MASK_DAC_PWR_CUT_CNTR) + +#define BIT_ST_DAC_FIFO_ON BIT(11) +#define BIT_SHIFT_ST_DAC_FIFO_ON 11 +#define BIT_MASK_ST_DAC_FIFO_ON 0x1 +#define BIT_CTRL_ST_DAC_FIFO_ON(x) (((x) & BIT_MASK_ST_DAC_FIFO_ON) << BIT_SHIFT_ST_DAC_FIFO_ON) + +#define BIT_ST_DAC_ISO_ON BIT(10) +#define BIT_SHIFT_ST_DAC_ISO_ON 10 +#define BIT_MASK_ST_DAC_ISO_ON 0x1 +#define BIT_CTRL_ST_DAC_ISO_ON(x) (((x) & BIT_MASK_ST_DAC_ISO_ON) << BIT_SHIFT_ST_DAC_ISO_ON) + +#define BIT_ST_DAC_PWR33_ON BIT(9) +#define BIT_SHIFT_ST_DAC_PWR33_ON 9 +#define BIT_MASK_ST_DAC_PWR33_ON 0x1 +#define BIT_CTRL_ST_DAC_PWR33_ON(x) (((x) & BIT_MASK_ST_DAC_PWR33_ON) << BIT_SHIFT_ST_DAC_PWR33_ON) + +#define BIT_ST_DAC_PWR12_ON BIT(8) +#define BIT_SHIFT_ST_DAC_PWR12_ON 8 +#define BIT_MASK_ST_DAC_PWR12_ON 0x1 +#define BIT_CTRL_ST_DAC_PWR12_ON(x) (((x) & BIT_MASK_ST_DAC_PWR12_ON) << BIT_SHIFT_ST_DAC_PWR12_ON) + +#define BIT_DAC_ISO_MANU BIT(3) +#define BIT_SHIFT_DAC_ISO_MANU 3 +#define BIT_MASK_DAC_ISO_MANU 0x1 +#define BIT_CTRL_DAC_ISO_MANU(x) (((x) & BIT_MASK_DAC_ISO_MANU) << BIT_SHIFT_DAC_ISO_MANU) + +#define BIT_DAC_PWR33_MANU BIT(2) +#define BIT_SHIFT_DAC_PWR33_MANU 2 +#define BIT_MASK_DAC_PWR33_MANU 0x1 +#define BIT_CTRL_DAC_PWR33_MANU(x) (((x) & BIT_MASK_DAC_PWR33_MANU) << BIT_SHIFT_DAC_PWR33_MANU) + +#define BIT_DAC_PWR12_MANU BIT(1) +#define BIT_SHIFT_DAC_PWR12_MANU 1 +#define BIT_MASK_DAC_PWR12_MANU 0x1 +#define BIT_CTRL_DAC_PWR12_MANU(x) (((x) & BIT_MASK_DAC_PWR12_MANU) << BIT_SHIFT_DAC_PWR12_MANU) + +#define BIT_DAC_PWR_AUTO BIT(0) +#define BIT_SHIFT_DAC_PWR_AUTO 0 +#define BIT_MASK_DAC_PWR_AUTO 0x1 +#define BIT_CTRL_DAC_PWR_AUTO(x) (((x) & BIT_MASK_DAC_PWR_AUTO) << BIT_SHIFT_DAC_PWR_AUTO) + + +//2 REG_DAC_ANAPAR_DA0 + +#define BIT_SHIFT_PWR_ALL_CNTR 12 +#define BIT_MASK_PWR_ALL_CNTR 0xfffff +#define BIT_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR) +#define BIT_CTRL_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR) +#define BIT_GET_PWR_ALL_CNTR(x) (((x) >> BIT_SHIFT_PWR_ALL_CNTR) & BIT_MASK_PWR_ALL_CNTR) + + +#define BIT_SHIFT_PWR_FUP_CNTR 0 +#define BIT_MASK_PWR_FUP_CNTR 0xfff +#define BIT_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR) +#define BIT_CTRL_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR) +#define BIT_GET_PWR_FUP_CNTR(x) (((x) >> BIT_SHIFT_PWR_FUP_CNTR) & BIT_MASK_PWR_FUP_CNTR) + + +//2 REG_DAC_ANAPAR_DA1 +#define BIT_FUP_EN BIT(31) +#define BIT_SHIFT_FUP_EN 31 +#define BIT_MASK_FUP_EN 0x1 +#define BIT_CTRL_FUP_EN(x) (((x) & BIT_MASK_FUP_EN) << BIT_SHIFT_FUP_EN) + + +#define BIT_SHIFT_ANAPAR_DA 8 +#define BIT_MASK_ANAPAR_DA 0x7fffff +#define BIT_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA) +#define BIT_CTRL_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA) +#define BIT_GET_ANAPAR_DA(x) (((x) >> BIT_SHIFT_ANAPAR_DA) & BIT_MASK_ANAPAR_DA) + +#define BIT_D_POW_DACVREF BIT(7) +#define BIT_SHIFT_D_POW_DACVREF 7 +#define BIT_MASK_D_POW_DACVREF 0x1 +#define BIT_CTRL_D_POW_DACVREF(x) (((x) & BIT_MASK_D_POW_DACVREF) << BIT_SHIFT_D_POW_DACVREF) + +#define BIT_D_POW_VREF2 BIT(6) +#define BIT_SHIFT_D_POW_VREF2 6 +#define BIT_MASK_D_POW_VREF2 0x1 +#define BIT_CTRL_D_POW_VREF2(x) (((x) & BIT_MASK_D_POW_VREF2) << BIT_SHIFT_D_POW_VREF2) + +#define BIT_D_POW_MBIAS BIT(5) +#define BIT_SHIFT_D_POW_MBIAS 5 +#define BIT_MASK_D_POW_MBIAS 0x1 +#define BIT_CTRL_D_POW_MBIAS(x) (((x) & BIT_MASK_D_POW_MBIAS) << BIT_SHIFT_D_POW_MBIAS) + +#define BIT_D_POW_DIV4 BIT(4) +#define BIT_SHIFT_D_POW_DIV4 4 +#define BIT_MASK_D_POW_DIV4 0x1 +#define BIT_CTRL_D_POW_DIV4(x) (((x) & BIT_MASK_D_POW_DIV4) << BIT_SHIFT_D_POW_DIV4) + +#define BIT_D_POW_DF1SE_R BIT(3) +#define BIT_SHIFT_D_POW_DF1SE_R 3 +#define BIT_MASK_D_POW_DF1SE_R 0x1 +#define BIT_CTRL_D_POW_DF1SE_R(x) (((x) & BIT_MASK_D_POW_DF1SE_R) << BIT_SHIFT_D_POW_DF1SE_R) + +#define BIT_D_POW_DF2SE_L BIT(2) +#define BIT_SHIFT_D_POW_DF2SE_L 2 +#define BIT_MASK_D_POW_DF2SE_L 0x1 +#define BIT_CTRL_D_POW_DF2SE_L(x) (((x) & BIT_MASK_D_POW_DF2SE_L) << BIT_SHIFT_D_POW_DF2SE_L) + +#define BIT_D_POW_DAC_R BIT(1) +#define BIT_SHIFT_D_POW_DAC_R 1 +#define BIT_MASK_D_POW_DAC_R 0x1 +#define BIT_CTRL_D_POW_DAC_R(x) (((x) & BIT_MASK_D_POW_DAC_R) << BIT_SHIFT_D_POW_DAC_R) + +#define BIT_D_POW_DAC_L BIT(0) +#define BIT_SHIFT_D_POW_DAC_L 0 +#define BIT_MASK_D_POW_DAC_L 0x1 +#define BIT_CTRL_D_POW_DAC_L(x) (((x) & BIT_MASK_D_POW_DAC_L) << BIT_SHIFT_D_POW_DAC_L) + + +//================ Register Reg Field ========================= +#define REG_DAC0_FIFO_WR 0x0000 +#define REG_DAC_CTRL 0x0004 +#define REG_DAC_INTR_CTRL 0x0008 +#define REG_DAC_INTR_STS 0x000C +#define REG_DAC_PWR_CTRL 0x0010 +#define REG_DAC_ANAPAR_DA0 0x0014 +#define REG_DAC_ANAPAR_DA1 0x0018 + + +//================ DAC HAL related enumeration ================== + + +//================ DAC HAL Macro =========================== +#define HAL_DAC_WRITE32(dacidx, addr, value) HAL_WRITE32(DAC_REG_BASE+dacidx*0x800 \ + ,addr,value) +#define HAL_DAC_READ32(dacidx, addr) HAL_READ32(DAC_REG_BASE+dacidx*0x800,addr) + + +//================ DAC Function Prototypes ===================== +RTK_STATUS HalDACInit8195a(IN VOID *Data); +RTK_STATUS HalDACDeInit8195a(IN VOID *Data); +RTK_STATUS HalDACEnableRtl8195a(IN VOID *Data); +RTK_STATUS HalDACIntrCtrl8195a(IN VOID *Data); +u8 HalDACSendRtl8195a(IN VOID *Data); +u32 HalDACReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg); + +#endif diff --git a/lib/fwlib/rtl8195a/rtl8195a_gdma.h b/lib/fwlib/rtl8195a/rtl8195a_gdma.h new file mode 100644 index 0000000..f8a4f95 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_gdma.h @@ -0,0 +1,522 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _RTL8195A_GDMA_H_ +#define _RTL8195A_GDMA_H_ + +// Define GDMA Handshake interface with peripheral, 0 -> GDMA0, 1-> GDMA1 +// Set this Hnadshake interface map to register REG_PESOC_SOC_CTRL +#define GDMA_HANDSHAKE_UART0_TX 0 +#define GDMA_HANDSHAKE_UART0_RX 1 +#define GDMA_HANDSHAKE_UART1_TX 2 +#define GDMA_HANDSHAKE_UART1_RX 3 +#define GDMA_HANDSHAKE_UART2_TX 14 // Only on GDMA 0, hardware fixed +#define GDMA_HANDSHAKE_UART2_RX 14 // Only on GDMA 1, hardware fixed + +#define GDMA_HANDSHAKE_SSI0_TX 4 +#define GDMA_HANDSHAKE_SSI0_RX 5 +#define GDMA_HANDSHAKE_SSI1_TX 6 +#define GDMA_HANDSHAKE_SSI1_RX 7 +#define GDMA_HANDSHAKE_SSI2_TX 15 // Only on GDMA 0, hardware fixed +#define GDMA_HANDSHAKE_SSI2_RX 15 // Only on GDMA 1, hardware fixed + +#define GDMA_HANDSHAKE_I2C0_TX 8 +#define GDMA_HANDSHAKE_I2C0_RX 9 +#define GDMA_HANDSHAKE_I2C1_TX 10 +#define GDMA_HANDSHAKE_I2C1_RX 11 + +#define GDMA_HANDSHAKE_ADC 12 +#define GDMA_HANDSHAKE_DAC0 13 // Only on GDMA 0, hardware fixed +#define GDMA_HANDSHAKE_DAC1 13 // Only on GDMA 1, hardware fixed + +#define HAL_GDMAX_READ32(GdmaIndex, addr) \ + HAL_READ32(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr) +#define HAL_GDMAX_WRITE32(GdmaIndex, addr, value) \ + HAL_WRITE32((GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF)), addr, value) +#define HAL_GDMAX_READ16(GdmaIndex, addr) \ + HAL_READ16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr) +#define HAL_GDMAX_WRITE16(GdmaIndex, addr, value) \ + HAL_WRITE16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value) +#define HAL_GDMAX_READ8(GdmaIndex, addr) \ + HAL_READ8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr) +#define HAL_GDMAX_WRITE8(GdmaIndex, addr, value) \ + HAL_WRITE8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value) + + +#define GDMA_CH_MAX 0x06 + +#define REG_GDMA_CH_OFF 0x058 +#define REG_GDMA_CH_SAR 0x000 +#define REG_GDMA_CH_DAR 0x008 +#define REG_GDMA_CH_LLP 0x010 +#define REG_GDMA_CH_CTL 0x018 +#define REG_GDMA_CH_SSTAT 0x020 +#define REG_GDMA_CH_DSTAT 0x028 +#define REG_GDMA_CH_SSTATAR 0x030 +#define REG_GDMA_CH_DSTATAR 0x038 +#define REG_GDMA_CH_CFG 0x040 +#define REG_GDMA_CH_SGR 0x048 +#define REG_GDMA_CH_DSR 0x050 + +//3 Interrupt Registers +#define REG_GDMA_RAW_INT_BASE 0x2C0 +#define REG_GDMA_RAW_INT_TFR 0x2C0 +#define REG_GDMA_RAW_INT_BLOCK 0x2c8 +#define REG_GDMA_RAW_INT_SRC_TRAN 0x2D0 +#define REG_GDMA_RAW_INT_DST_TRAN 0x2D8 +#define REG_GDMA_RAW_INT_ERR 0x2E0 + +#define REG_GDMA_STATUS_INT_BASE 0x2E8 +#define REG_GDMA_STATUS_INT_TFR 0x2E8 +#define REG_GDMA_STATUS_INT_BLOCK 0x2F0 +#define REG_GDMA_STATUS_INT_SRC_TRAN 0x2F8 +#define REG_GDMA_STATUS_INT_DST_TRAN 0x300 +#define REG_GDMA_STATUS_INT_ERR 0x308 + +#define REG_GDMA_MASK_INT_BASE 0x310 +#define REG_GDMA_MASK_INT_TFR 0x310 +#define REG_GDMA_MASK_INT_BLOCK 0x318 +#define REG_GDMA_MASK_INT_SRC_TRAN 0x320 +#define REG_GDMA_MASK_INT_DST_TRAN 0x328 +#define REG_GDMA_MASK_INT_INT_ERR 0x330 + +#define REG_GDMA_CLEAR_INT_BASE 0x338 +#define REG_GDMA_CLEAR_INT_TFR 0x338 +#define REG_GDMA_CLEAR_INT_BLOCK 0x340 +#define REG_GDMA_CLEAR_INT_SRC_TRAN 0x348 +#define REG_GDMA_CLEAR_INT_DST_TRAN 0x350 +#define REG_GDMA_CLEAR_INT_ERR 0x358 +#define REG_GDMA_STATUS_INT 0x360 + +//3 Software handshaking Registers +#define REG_GDMA_REQ_SRC 0x368 +#define REG_GDMA_REQ_DST 0x370 +#define REG_GDMA_REQ_SGL_REQ 0x378 +#define REG_GDMA_REQ_DST_REQ 0x380 +#define REG_GDMA_REQ_LST_SRC 0x388 +#define REG_GDMA_REQ_LST_DST 0x390 + +//3 Miscellaneous Registers +#define REG_GDMA_DMAC_CFG 0x398 +#define REG_GDMA_CH_EN 0x3A0 +#define REG_GDMA_DMA_ID 0x3A8 +#define REG_GDMA_DMA_TEST 0x3B0 +#define REG_GDMA_DMA_COM_PARAMS6 0x3C8 +#define REG_GDMA_DMA_COM_PARAMS5 0x3D0 +#define REG_GDMA_DMA_COM_PARAMS4 0x3D8 +#define REG_GDMA_DMA_COM_PARAMS3 0x3E0 +#define REG_GDMA_DMA_COM_PARAMS2 0x3E8 +#define REG_GDMA_DMA_COM_PARAMS1 0x3F0 +#define REG_GDMA_DMA_COM_PARAMS0 0x3F8 + +//3 CTL Register Bit Control +#define BIT_SHIFT_CTLX_LO_INT_EN 0 +#define BIT_MASK_CTLX_LO_INT_EN 0x1 +#define BIT_CTLX_LO_INT_EN(x)(((x) & BIT_MASK_CTLX_LO_INT_EN) << BIT_SHIFT_CTLX_LO_INT_EN) +#define BIT_INVC_CTLX_LO_INT_EN (~(BIT_MASK_CTLX_LO_INT_EN << BIT_SHIFT_CTLX_LO_INT_EN)) + +#define BIT_SHIFT_CTLX_LO_DST_TR_WIDTH 1 +#define BIT_MASK_CTLX_LO_DST_TR_WIDTH 0x7 +#define BIT_CTLX_LO_DST_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_DST_TR_WIDTH) << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH) +#define BIT_INVC_CTLX_LO_DST_TR_WIDTH (~(BIT_MASK_CTLX_LO_DST_TR_WIDTH << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH)) + +#define BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH 4 +#define BIT_MASK_CTLX_LO_SRC_TR_WIDTH 0x7 +#define BIT_CTLX_LO_SRC_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_SRC_TR_WIDTH) << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH) +#define BIT_INVC_CTLX_LO_SRC_TR_WIDTH (~(BIT_MASK_CTLX_LO_SRC_TR_WIDTH << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH)) + +#define BIT_SHIFT_CTLX_LO_DINC 7 +#define BIT_MASK_CTLX_LO_DINC 0x3 +#define BIT_CTLX_LO_DINC(x)(((x) & BIT_MASK_CTLX_LO_DINC) << BIT_SHIFT_CTLX_LO_DINC) +#define BIT_INVC_CTLX_LO_DINC (~(BIT_MASK_CTLX_LO_DINC << BIT_SHIFT_CTLX_LO_DINC)) + +#define BIT_SHIFT_CTLX_LO_SINC 9 +#define BIT_MASK_CTLX_LO_SINC 0x3 +#define BIT_CTLX_LO_SINC(x)(((x) & BIT_MASK_CTLX_LO_SINC) << BIT_SHIFT_CTLX_LO_SINC) +#define BIT_INVC_CTLX_LO_SINC (~(BIT_MASK_CTLX_LO_SINC << BIT_SHIFT_CTLX_LO_SINC)) + +#define BIT_SHIFT_CTLX_LO_DEST_MSIZE 11 +#define BIT_MASK_CTLX_LO_DEST_MSIZE 0x7 +#define BIT_CTLX_LO_DEST_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_DEST_MSIZE) << BIT_SHIFT_CTLX_LO_DEST_MSIZE) +#define BIT_INVC_CTLX_LO_DEST_MSIZE (~(BIT_MASK_CTLX_LO_DEST_MSIZE << BIT_SHIFT_CTLX_LO_DEST_MSIZE)) + +#define BIT_SHIFT_CTLX_LO_SRC_MSIZE 14 +#define BIT_MASK_CTLX_LO_SRC_MSIZE 0x7 +#define BIT_CTLX_LO_SRC_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_SRC_MSIZE) << BIT_SHIFT_CTLX_LO_SRC_MSIZE) +#define BIT_INVC_CTLX_LO_SRC_MSIZE (~(BIT_MASK_CTLX_LO_SRC_MSIZE << BIT_SHIFT_CTLX_LO_SRC_MSIZE)) + + +#define BIT_SHIFT_CTLX_LO_SRC_GATHER_EN 17 +#define BIT_MASK_CTLX_LO_SRC_GATHER_EN 0x1 +#define BIT_CTLX_LO_SRC_GATHER_EN(x)(((x) & BIT_MASK_CTLX_LO_SRC_GATHER_EN) << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN) +#define BIT_INVC_CTLX_LO_SRC_GATHER_EN (~(BIT_MASK_CTLX_LO_SRC_GATHER_EN << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN)) + + +#define BIT_SHIFT_CTLX_LO_DST_SCATTER_EN 18 +#define BIT_MASK_CTLX_LO_DST_SCATTER_EN 0x1 +#define BIT_CTLX_LO_DST_SCATTER_EN(x)(((x) & BIT_MASK_CTLX_LO_DST_SCATTER_EN) << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN) +#define BIT_INVC_CTLX_LO_DST_SCATTER_EN (~(BIT_MASK_CTLX_LO_DST_SCATTER_EN << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN)) + + +#define BIT_SHIFT_CTLX_LO_TT_FC 20 +#define BIT_MASK_CTLX_LO_TT_FC 0x7 +#define BIT_CTLX_LO_TT_FC(x)(((x) & BIT_MASK_CTLX_LO_TT_FC) << BIT_SHIFT_CTLX_LO_TT_FC) +#define BIT_INVC_CTLX_LO_TT_FC (~(BIT_MASK_CTLX_LO_TT_FC << BIT_SHIFT_CTLX_LO_TT_FC)) + + +#define BIT_SHIFT_CTLX_LO_DMS 23 +#define BIT_MASK_CTLX_LO_DMS 0x3 +#define BIT_CTLX_LO_DMS(x)(((x) & BIT_MASK_CTLX_LO_DMS) << BIT_MASK_CTLX_LO_DMS) +#define BIT_INVC_CTLX_LO_DMS (~(BIT_MASK_CTLX_LO_DMS << BIT_SHIFT_CTLX_LO_DMS)) + + +#define BIT_SHIFT_CTLX_LO_SMS 25 +#define BIT_MASK_CTLX_LO_SMS 0x3 +#define BIT_CTLX_LO_SMS(x)(((x) & BIT_MASK_CTLX_LO_SMS) << BIT_SHIFT_CTLX_LO_SMS) +#define BIT_INVC_CTLX_LO_SMS (~(BIT_MASK_CTLX_LO_SMS << BIT_SHIFT_CTLX_LO_SMS)) + + +#define BIT_SHIFT_CTLX_LO_LLP_DST_EN 27 +#define BIT_MASK_CTLX_LO_LLP_DST_EN 0x1 +#define BIT_CTLX_LO_LLP_DST_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_DST_EN) << BIT_SHIFT_CTLX_LO_LLP_DST_EN) +#define BIT_INVC_CTLX_LO_LLP_DST_EN (~(BIT_MASK_CTLX_LO_LLP_DST_EN << BIT_SHIFT_CTLX_LO_LLP_DST_EN)) + +#define BIT_SHIFT_CTLX_LO_LLP_SRC_EN 28 +#define BIT_MASK_CTLX_LO_LLP_SRC_EN 0x1 +#define BIT_CTLX_LO_LLP_SRC_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_SRC_EN) << BIT_SHIFT_CTLX_LO_LLP_SRC_EN) +#define BIT_INVC_CTLX_LO_LLP_SRC_EN (~(BIT_MASK_CTLX_LO_LLP_SRC_EN << BIT_SHIFT_CTLX_LO_LLP_SRC_EN)) + + +#define BIT_SHIFT_CTLX_UP_BLOCK_BS 0 +#define BIT_MASK_CTLX_UP_BLOCK_BS 0xFFF +#define BIT_CTLX_UP_BLOCK_BS(x)(((x) & BIT_MASK_CTLX_UP_BLOCK_BS) << BIT_SHIFT_CTLX_UP_BLOCK_BS) +#define BIT_INVC_CTLX_UP_BLOCK_BS (~(BIT_MASK_CTLX_UP_BLOCK_BS << BIT_SHIFT_CTLX_UP_BLOCK_BS)) + + +#define BIT_SHIFT_CTLX_UP_DONE 12 +#define BIT_MASK_CTLX_UP_DONE 0x1 +#define BIT_CTLX_UP_DONE(x)(((x) & BIT_MASK_CTLX_UP_DONE) << BIT_SHIFT_CTLX_UP_DONE) +#define BIT_INVC_CTLX_UP_DONE (~(BIT_MASK_CTLX_UP_DONE << BIT_SHIFT_CTLX_UP_DONE)) + + +//3 CFG Register Bit Control +#define BIT_SHIFT_CFGX_LO_CH_PRIOR 5 +#define BIT_MASK_CFGX_LO_CH_PRIOR 0x7 +#define BIT_CFGX_LO_CH_PRIOR(x)(((x) & BIT_MASK_CFGX_LO_CH_PRIOR) << BIT_SHIFT_CFGX_LO_CH_PRIOR) +#define BIT_INVC_CFGX_LO_CH_PRIOR (~(BIT_MASK_CFGX_LO_CH_PRIOR << BIT_SHIFT_CFGX_LO_CH_PRIOR)) + + +#define BIT_SHIFT_CFGX_LO_CH_SUSP 8 +#define BIT_MASK_CFGX_LO_CH_SUSP 0x1 +#define BIT_CFGX_LO_CH_SUSP(x)(((x) & BIT_MASK_CFGX_LO_CH_SUSP) << BIT_SHIFT_CFGX_LO_CH_SUSP) +#define BIT_INVC_CFGX_LO_CH_SUSP (~(BIT_MASK_CFGX_LO_CH_SUSP << BIT_SHIFT_CFGX_LO_CH_SUSP)) + + +#define BIT_SHIFT_CFGX_LO_FIFO_EMPTY 9 +#define BIT_MASK_CFGX_LO_FIFO_EMPTY 0x1 +#define BIT_CFGX_LO_FIFO_EMPTY(x)(((x) & BIT_MASK_CFGX_LO_FIFO_EMPTY) << BIT_SHIFT_CFGX_LO_FIFO_EMPTY) +#define BIT_INVC_CFGX_LO_FIFO_EMPTY (~(BIT_MASK_CFGX_LO_FIFO_EMPTY << BIT_SHIFT_CFGX_LO_FIFO_EMPTY)) + + +#define BIT_SHIFT_CFGX_LO_HS_SEL_DST 10 +#define BIT_MASK_CFGX_LO_HS_SEL_DST 0x1 +#define BIT_CFGX_LO_HS_SEL_DST(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_DST) << BIT_SHIFT_CFGX_LO_HS_SEL_DST) +#define BIT_INVC_CFGX_LO_HS_SEL_DST (~(BIT_MASK_CFGX_LO_HS_SEL_DST << BIT_SHIFT_CFGX_LO_HS_SEL_DST)) + +#define BIT_SHIFT_CFGX_LO_HS_SEL_SRC 11 +#define BIT_MASK_CFGX_LO_HS_SEL_SRC 0x1 +#define BIT_CFGX_LO_HS_SEL_SRC(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_SRC) << BIT_SHIFT_CFGX_LO_HS_SEL_SRC) +#define BIT_INVC_CFGX_LO_HS_SEL_SRC (~(BIT_MASK_CFGX_LO_HS_SEL_SRC << BIT_SHIFT_CFGX_LO_HS_SEL_SRC)) + +#define BIT_SHIFT_CFGX_LO_LOCK_CH_L 12 +#define BIT_MASK_CFGX_LO_LOCK_CH_L 0x3 +#define BIT_CFGX_LO_LOCK_CH_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH_L) << BIT_SHIFT_CFGX_LO_LOCK_CH_L) +#define BIT_INVC_CFGX_LO_LOCK_CH_L (~(BIT_MASK_CFGX_LO_LOCK_CH_L << BIT_SHIFT_CFGX_LO_LOCK_CH_L)) + +#define BIT_SHIFT_CFGX_LO_LOCK_B_L 14 +#define BIT_MASK_CFGX_LO_LOCK_B_L 0x3 +#define BIT_CFGX_LO_LOCK_B_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B_L) << BIT_SHIFT_CFGX_LO_LOCK_B_L) +#define BIT_INVC_CFGX_LO_LOCK_B_L (~(BIT_MASK_CFGX_LO_LOCK_B_L << BIT_SHIFT_CFGX_LO_LOCK_B_L)) + +#define BIT_SHIFT_CFGX_LO_LOCK_CH 16 +#define BIT_MASK_CFGX_LO_LOCK_CH 0x1 +#define BIT_CFGX_LO_LOCK_CH(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH) << BIT_SHIFT_CFGX_LO_LOCK_CH) +#define BIT_INVC_CFGX_LO_LOCK_CH (~(BIT_MASK_CFGX_LO_LOCK_CH << BIT_SHIFT_CFGX_LO_LOCK_CH)) + +#define BIT_SHIFT_CFGX_LO_LOCK_B 17 +#define BIT_MASK_CFGX_LO_LOCK_B 0x1 +#define BIT_CFGX_LO_LOCK_B(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B) << BIT_SHIFT_CFGX_LO_LOCK_B) +#define BIT_INVC_CFGX_LO_LOCK_B (~(BIT_MASK_CFGX_LO_LOCK_B << BIT_SHIFT_CFGX_LO_LOCK_B)) + +#define BIT_SHIFT_CFGX_LO_DST_HS_POL 18 +#define BIT_MASK_CFGX_LO_DST_HS_POL 0x1 +#define BIT_CFGX_LO_DST_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_DST_HS_POL) << BIT_SHIFT_CFGX_LO_DST_HS_POL) +#define BIT_INVC_CFGX_LO_DST_HS_POL (~(BIT_MASK_CFGX_LO_DST_HS_POL << BIT_SHIFT_CFGX_LO_DST_HS_POL)) + +#define BIT_SHIFT_CFGX_LO_SRC_HS_POL 19 +#define BIT_MASK_CFGX_LO_SRC_HS_POL 0x1 +#define BIT_CFGX_LO_SRC_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_SRC_HS_POL) << BIT_SHIFT_CFGX_LO_SRC_HS_POL) +#define BIT_INVC_CFGX_LO_SRC_HS_POL (~(BIT_MASK_CFGX_LO_SRC_HS_POL << BIT_SHIFT_CFGX_LO_SRC_HS_POL)) + +#define BIT_SHIFT_CFGX_LO_MAX_ABRST 20 +#define BIT_MASK_CFGX_LO_MAX_ABRST 0x3FF +#define BIT_CFGX_LO_MAX_ABRST(x)(((x) & BIT_MASK_CFGX_LO_MAX_ABRST) << BIT_SHIFT_CFGX_LO_MAX_ABRST) +#define BIT_INVC_CFGX_LO_MAX_ABRST (~(BIT_MASK_CFGX_LO_MAX_ABRST << BIT_SHIFT_CFGX_LO_MAX_ABRST)) + +#define BIT_SHIFT_CFGX_LO_RELOAD_SRC 30 +#define BIT_MASK_CFGX_LO_RELOAD_SRC 0x1 +#define BIT_CFGX_LO_RELOAD_SRC(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_SRC) << BIT_SHIFT_CFGX_LO_RELOAD_SRC) +#define BIT_INVC_CFGX_LO_RELOAD_SRC (~(BIT_MASK_CFGX_LO_RELOAD_SRC << BIT_SHIFT_CFGX_LO_RELOAD_SRC)) + +#define BIT_SHIFT_CFGX_LO_RELOAD_DST 31 +#define BIT_MASK_CFGX_LO_RELOAD_DST 0x1 +#define BIT_CFGX_LO_RELOAD_DST(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_DST) << BIT_SHIFT_CFGX_LO_RELOAD_DST) +#define BIT_INVC_CFGX_LO_RELOAD_DST (~(BIT_MASK_CFGX_LO_RELOAD_DST << BIT_SHIFT_CFGX_LO_RELOAD_DST)) + +#define BIT_SHIFT_CFGX_UP_FCMODE 0 +#define BIT_MASK_CFGX_UP_FCMODE 0x1 +#define BIT_CFGX_UP_FCMODE(x)(((x) & BIT_MASK_CFGX_UP_FCMODE) << BIT_SHIFT_CFGX_UP_FCMODE) +#define BIT_INVC_CFGX_UP_FCMODE (~(BIT_MASK_CFGX_UP_FCMODE << BIT_SHIFT_CFGX_UP_FCMODE)) + +#define BIT_SHIFT_CFGX_UP_FIFO_MODE 1 +#define BIT_MASK_CFGX_UP_FIFO_MODE 0x1 +#define BIT_CFGX_UP_FIFO_MODE(x)(((x) & BIT_MASK_CFGX_UP_FIFO_MODE) << BIT_SHIFT_CFGX_UP_FIFO_MODE) +#define BIT_INVC_CFGX_UP_FIFO_MODE (~(BIT_MASK_CFGX_UP_FIFO_MODE << BIT_SHIFT_CFGX_UP_FIFO_MODE)) + +#define BIT_SHIFT_CFGX_UP_PROTCTL 2 +#define BIT_MASK_CFGX_UP_PROTCTL 0x7 +#define BIT_CFGX_UP_PROTCTL(x)(((x) & BIT_MASK_CFGX_UP_PROTCTL) << BIT_SHIFT_CFGX_UP_PROTCTL) +#define BIT_INVC_CFGX_UP_PROTCTL (~(BIT_MASK_CFGX_UP_PROTCTL << BIT_SHIFT_CFGX_UP_PROTCTL)) + +#define BIT_SHIFT_CFGX_UP_DS_UPD_EN 5 +#define BIT_MASK_CFGX_UP_DS_UPD_EN 0x1 +#define BIT_CFGX_UP_DS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_DS_UPD_EN) << BIT_SHIFT_CFGX_UP_DS_UPD_EN) +#define BIT_INVC_CFGX_UP_DS_UPD_EN (~(BIT_MASK_CFGX_UP_DS_UPD_EN << BIT_SHIFT_CFGX_UP_DS_UPD_EN)) + +#define BIT_SHIFT_CFGX_UP_SS_UPD_EN 6 +#define BIT_MASK_CFGX_UP_SS_UPD_EN 0x1 +#define BIT_CFGX_UP_SS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_SS_UPD_EN) << BIT_SHIFT_CFGX_UP_SS_UPD_EN) +#define BIT_INVC_CFGX_UP_SS_UPD_EN (~(BIT_MASK_CFGX_UP_SS_UPD_EN << BIT_SHIFT_CFGX_UP_SS_UPD_EN)) + +#define BIT_SHIFT_CFGX_UP_SRC_PER 7 +#define BIT_MASK_CFGX_UP_SRC_PER 0xF +#define BIT_CFGX_UP_SRC_PER(x)(((x) & BIT_MASK_CFGX_UP_SRC_PER) << BIT_SHIFT_CFGX_UP_SRC_PER) +#define BIT_INVC_CFGX_UP_SRC_PER (~(BIT_MASK_CFGX_UP_SRC_PER << BIT_SHIFT_CFGX_UP_SRC_PER)) + +#define BIT_SHIFT_CFGX_UP_DEST_PER 11 +#define BIT_MASK_CFGX_UP_DEST_PER 0xF +#define BIT_CFGX_UP_DEST_PER(x)(((x) & BIT_MASK_CFGX_UP_DEST_PER) << BIT_SHIFT_CFGX_UP_DEST_PER) +#define BIT_INVC_CFGX_UP_DEST_PER (~(BIT_MASK_CFGX_UP_DEST_PER << BIT_SHIFT_CFGX_UP_DEST_PER)) + +typedef enum _GDMA_CHANNEL_NUM_ { + GdmaNoCh = 0x0000, + GdmaCh0 = 0x0101, + GdmaCh1 = 0x0202, + GdmaCh2 = 0x0404, + GdmaCh3 = 0x0808, + GdmaCh4 = 0x1010, + GdmaCh5 = 0x2020, + GdmaCh6 = 0x4040, + GdmaCh7 = 0x8080, + GdmaAllCh = 0xffff +}GDMA_CHANNEL_NUM, *PGDMA_CHANNEL_NUM; + + +//3 CTL register struct + +typedef enum _GDMA_CTL_TT_FC_TYPE_ { + TTFCMemToMem = 0x00, + TTFCMemToPeri = 0x01, + TTFCPeriToMem = 0x02 +}GDMA_CTL_TT_FC_TYPE, *PGDMA_CTL_TT_FC_TYPE; + +//Max type = Bus Width +typedef enum _GDMA_CTL_TR_WIDTH_ { + TrWidthOneByte = 0x00, + TrWidthTwoBytes = 0x01, + TrWidthFourBytes = 0x02 +}GDMA_CTL_TR_WIDTH, *PGDMA_CTL_TR_WIDTH; + +typedef enum _GDMA_CTL_MSIZE_ { + MsizeOne = 0x00, + MsizeFour = 0x01, + MsizeEight = 0x02 +}GDMA_CTL_MSIZE, *PGDMA_CTL_MSIZE; + +typedef enum _GDMA_INC_TYPE_ { + IncType = 0x00, + DecType = 0x01, + NoChange = 0x02 +}GDMA_INC_TYPE, *PGDMA_INC_TYPE; + + +typedef struct _GDMA_CTL_REG_ { + GDMA_CTL_TT_FC_TYPE TtFc; + GDMA_CTL_TR_WIDTH DstTrWidth; + GDMA_CTL_TR_WIDTH SrcTrWidth; + GDMA_INC_TYPE Dinc; + GDMA_INC_TYPE Sinc; + GDMA_CTL_MSIZE DestMsize; + GDMA_CTL_MSIZE SrcMsize; + + u8 IntEn :1; // Bit 0 + u8 SrcGatherEn :1; // Bit 1 + u8 DstScatterEn :1; // Bit 2 + u8 LlpDstEn :1; // Bit 3 + u8 LlpSrcEn :1; // Bit 4 + u8 Done :1; // Bit 5 + u8 Rsvd6To7 :2; //Bit 6 -7 + u16 BlockSize; + +}GDMA_CTL_REG, *PGDMA_CTL_REG; + + +//3 CFG Register Structure + +typedef enum _GDMA_CH_PRIORITY_ { + Prior0 = 0, + Prior1 = 1, + Prior2 = 2, + Prior3 = 3, + Prior4 = 4, + Prior5 = 5, + Prior6 = 6, + Prior7 = 7 +}GDMA_CH_PRIORITY, *PGDMA_CH_PRIORITY; + +typedef enum _GDMA_LOCK_LEVEL_ { + OverComplDmaTransfer = 0x00, + OverComplDmaBlockTransfer = 0x01, + OverComplDmaTransation = 0x02 +}GDMA_LOCK_LEVEL, *PGDMA_LOCK_LEVEL; + + +typedef struct _GDMA_CFG_REG_ { + GDMA_CH_PRIORITY ChPrior; + GDMA_LOCK_LEVEL LockBL; + GDMA_LOCK_LEVEL LockChL; + u16 MaxAbrst; + u8 SrcPer; + u8 DestPer; + u16 ChSusp :1; //Bit 0 + u16 FifoEmpty :1; //Bit 1 + u16 HsSelDst :1; //Bit 2 + u16 HsSelSrc :1; //Bit 3 + u16 LockCh :1; //Bit 4 + u16 LockB :1; //Bit 5 + u16 DstHsPol :1; //Bit 6 + u16 SrcHsPol :1; //Bit 7 + u16 ReloadSrc :1; //Bit 8 + u16 ReloadDst :1; //Bit 9 + u16 FifoMode :1; //Bit 10 + u16 DsUpdEn :1; //Bit 11 + u16 SsUpdEn :1; //Bit 12 + u16 Rsvd13To15 :3; +}GDMA_CFG_REG, *PGDMA_CFG_REG; + +typedef enum _GDMA_ISR_TYPE_ { + TransferType = 0x1, + BlockType = 0x2, + SrcTransferType = 0x4, + DstTransferType = 0x8, + ErrType = 0x10 +}GDMA_ISR_TYPE, *PGDMA_ISR_TYPE; + + +VOID +HalGdmaOnOffRtl8195a ( + IN VOID *Data +); + +BOOL +HalGdamChInitRtl8195a( + IN VOID *Data +); + +BOOL +HalGdmaChSetingRtl8195a( + IN VOID *Data +); + +BOOL +HalGdmaChBlockSetingRtl8195a( + IN VOID *Data +); + + +VOID +HalGdmaChDisRtl8195a ( + IN VOID *Data +); + +VOID +HalGdmaChEnRtl8195a ( + IN VOID *Data +); + +VOID +HalGdmaChIsrEnAndDisRtl8195a ( + IN VOID *Data +); + +u8 +HalGdmaChIsrCleanRtl8195a ( + IN VOID *Data +); + +VOID +HalGdmaChCleanAutoSrcRtl8195a ( + IN VOID *Data +); + +VOID +HalGdmaChCleanAutoDstRtl8195a ( + IN VOID *Data +); + +u32 +HalGdmaQueryDArRtl8195a( + IN VOID *Data +); + +u32 +HalGdmaQuerySArRtl8195a( + IN VOID *Data +); + +BOOL +HalGdmaQueryChEnRtl8195a ( + IN VOID *Data +); + +#ifdef CONFIG_CHIP_E_CUT +_LONG_CALL_ BOOL +HalGdmaChBlockSetingRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ u32 +HalGdmaQueryDArRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ u32 +HalGdmaQuerySArRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ BOOL +HalGdmaQueryChEnRtl8195a_V04 ( + IN VOID *Data +); + +#endif // #ifdef CONFIG_CHIP_E_CUT + +#endif diff --git a/lib/fwlib/rtl8195a/rtl8195a_gpio.h b/lib/fwlib/rtl8195a/rtl8195a_gpio.h new file mode 100644 index 0000000..a5ba6cc --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_gpio.h @@ -0,0 +1,352 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _RTL8195A_GPIO_H_ +#define _RTL8195A_GPIO_H_ + +#include "hal_api.h" +#include "hal_gpio.h" + +#define GPIO_PORTA_DR 0x00 // data register +#define GPIO_PORTA_DDR 0x04 // data direction +#define GPIO_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software + +#define GPIO_PORTB_DR 0x0c // data register +#define GPIO_PORTB_DDR 0x10 // data direction +#define GPIO_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software + +#define GPIO_PORTC_DR 0x18 // data register +#define GPIO_PORTC_DDR 0x1c // data direction +#define GPIO_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software + +//1 Only the PORTA can be configured to generate interrupts +#define GPIO_INT_EN 0x30 // Interrupt enable register +#define GPIO_INT_MASK 0x34 // Interrupt mask +#define GPIO_INT_TYPE 0x38 // Interrupt type(level/edge) register +#define GPIO_INT_POLARITY 0x3C // Interrupt polarity(Active low/high) register +#define GPIO_INT_STATUS 0x40 // Interrupt status +#define GPIO_INT_RAWSTATUS 0x44 // Interrupt status without mask +#define GPIO_DEBOUNCE 0x48 // Interrupt signal debounce +#define GPIO_PORTA_EOI 0x4c // Clear interrupt + +#define GPIO_EXT_PORTA 0x50 // GPIO IN read or OUT read back +#define GPIO_EXT_PORTB 0x54 // GPIO IN read or OUT read back +#define GPIO_EXT_PORTC 0x58 // GPIO IN read or OUT read back + +#define GPIO_INT_SYNC 0x60 // Is level-sensitive interrupt being sync sith PCLK + +enum { + HAL_GPIO_HIGHZ = 0, + HAL_GPIO_PULL_LOW = 1, + HAL_GPIO_PULL_HIGH = 2 +}; + +//====================================================== +// ROM Function prototype +extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter; + +static __inline HAL_Status +GPIO_Lock ( + VOID +) +{ + HAL_Status Status; + + if (_pHAL_Gpio_Adapter->EnterCritical) { + _pHAL_Gpio_Adapter->EnterCritical(); + } + + if(_pHAL_Gpio_Adapter->Locked) { + Status = HAL_BUSY; + } + else { + _pHAL_Gpio_Adapter->Locked = 1; + Status = HAL_OK; + } + + if (_pHAL_Gpio_Adapter->ExitCritical) { + _pHAL_Gpio_Adapter->ExitCritical(); + } + + return Status; +} + + +static __inline VOID +GPIO_UnLock ( + VOID +) +{ + if (_pHAL_Gpio_Adapter->EnterCritical) { + _pHAL_Gpio_Adapter->EnterCritical(); + } + + _pHAL_Gpio_Adapter->Locked = 0; + + if (_pHAL_Gpio_Adapter->ExitCritical) { + _pHAL_Gpio_Adapter->ExitCritical(); + } +} + + +_LONG_CALL_ extern u32 +HAL_GPIO_IrqHandler_8195a( + IN VOID *pData +); + +_LONG_CALL_ extern u32 +HAL_GPIO_MbedIrqHandler_8195a( + IN VOID *pData +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_IntCtrl_8195a( + HAL_GPIO_PIN *GPIO_Pin, + u32 En +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_Init_8195a( + HAL_GPIO_PIN *GPIO_Pin +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_DeInit_8195a( + HAL_GPIO_PIN *GPIO_Pin +); + +_LONG_CALL_ HAL_GPIO_PIN_STATE +HAL_GPIO_ReadPin_8195a( + HAL_GPIO_PIN *GPIO_Pin +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_WritePin_8195a( + HAL_GPIO_PIN *GPIO_Pin, + HAL_GPIO_PIN_STATE Pin_State +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_RegIrq_8195a( + IN PIRQ_HANDLE pIrqHandle +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_UnRegIrq_8195a( + IN PIRQ_HANDLE pIrqHandle +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_UserRegIrq_8195a( + HAL_GPIO_PIN *GPIO_Pin, + VOID *IrqHandler, + VOID *IrqData +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_UserUnRegIrq_8195a( + HAL_GPIO_PIN *GPIO_Pin +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_MaskIrq_8195a( + HAL_GPIO_PIN *GPIO_Pin +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_UnMaskIrq_8195a( + HAL_GPIO_PIN *GPIO_Pin +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_IntDebounce_8195a( + HAL_GPIO_PIN *GPIO_Pin, + u8 Enable +); + +_LONG_CALL_ u32 +HAL_GPIO_GetIPPinName_8195a( + u32 chip_pin +); + +_LONG_CALL_ HAL_Status +HAL_GPIO_PullCtrl_8195a( + u32 chip_pin, + u8 pull_type +); + +_LONG_CALL_ u32 +GPIO_GetChipPinName_8195a( + u32 port, + u32 pin +); + +_LONG_CALL_ VOID +GPIO_PullCtrl_8195a( + u32 chip_pin, + u8 pull_type +); + +_LONG_CALL_ VOID +GPIO_Int_SetType_8195a( + u8 pin_num, + u8 int_mode +); + + +_LONG_CALL_ HAL_Status HAL_GPIO_IntCtrl_8195aV02(HAL_GPIO_PIN *GPIO_Pin, u32 En); +_LONG_CALL_ u32 GPIO_Int_Clear_8195aV02(u32 irq_clr); + +HAL_Status +HAL_GPIO_ClearISR_8195a( + HAL_GPIO_PIN *GPIO_Pin +); + + +/********** HAL In-Line Functions **********/ + +/** + * @brief De-Initializes a GPIO Pin, reset it as default setting. + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. + * + * @retval HAL_Status + */ +static __inline VOID +HAL_GPIO_DeInit( + HAL_GPIO_PIN *GPIO_Pin +) +{ + HAL_GPIO_DeInit_8195a(GPIO_Pin); +} + +/** + * @brief Reads the specified input port pin. + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. + * + * @retval The input port pin current status(High or Low). + */ +static __inline s32 +HAL_GPIO_ReadPin( + HAL_GPIO_PIN *GPIO_Pin +) +{ + return (s32)HAL_GPIO_ReadPin_8195a(GPIO_Pin); +} + +/** + * @brief Write the specified output port pin. + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. + * + * @param Pin_State: The state going to be set to the assigned GPIO pin. + * + * @retval None + */ +static __inline VOID +HAL_GPIO_WritePin( + HAL_GPIO_PIN *GPIO_Pin, + u32 Value +) +{ + HAL_GPIO_WritePin_8195a(GPIO_Pin, (HAL_GPIO_PIN_STATE)Value); +} + +/** + * @brief To register a user interrupt handler for a specified pin + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. + * + * @param IrqHandler: The IRQ handler to be assigned to the specified pin + * + * @param IrqData: The pointer will be pass the the IRQ handler + * + * @retval None + */ +static __inline VOID +HAL_GPIO_UserRegIrq( + HAL_GPIO_PIN *GPIO_Pin, + VOID *IrqHandler, + VOID *IrqData +) +{ + HAL_GPIO_UserRegIrq_8195a(GPIO_Pin, IrqHandler, IrqData); +} + +/** + * @brief To un-register a user interrupt handler for a specified pin + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. + * + * @retval None + */ +static __inline VOID +HAL_GPIO_UserUnRegIrq( + HAL_GPIO_PIN *GPIO_Pin +) +{ + HAL_GPIO_UserUnRegIrq_8195a(GPIO_Pin); +} + + +/** + * @brief Enable/Disable GPIO interrupt + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization. + * + * @param En: Enable (1) or Disable (0) + * + * @retval HAL_Status + */ +static __inline VOID +HAL_GPIO_IntCtrl( + HAL_GPIO_PIN *GPIO_Pin, + u32 En +) +{ + HAL_GPIO_IntCtrl_8195a(GPIO_Pin, En); +} + +/** + * @brief Mask the interrupt of a specified pin + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. + * + * @retval None + */ +static __inline VOID +HAL_GPIO_MaskIrq( + HAL_GPIO_PIN *GPIO_Pin +) +{ + HAL_GPIO_MaskIrq_8195a(GPIO_Pin); +} + + +/** + * @brief UnMask the interrupt of a specified pin + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. + * + * @retval None + */ +static __inline VOID +HAL_GPIO_UnMaskIrq( + HAL_GPIO_PIN *GPIO_Pin +) +{ + HAL_GPIO_ClearISR_8195a(GPIO_Pin); + HAL_GPIO_UnMaskIrq_8195a(GPIO_Pin); +} + + +#endif // end of "#define _RTL8195A_GPIO_H_" + diff --git a/lib/fwlib/rtl8195a/rtl8195a_i2c.h b/lib/fwlib/rtl8195a/rtl8195a_i2c.h new file mode 100644 index 0000000..4e34db8 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_i2c.h @@ -0,0 +1,851 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _RTL8195A_I2C_H_ +#define _RTL8195A_I2C_H_ + +#include "hal_api.h" + +//================ Register Bit Field ================== +//2 REG_DW_I2C_IC_CON +#define BIT_IC_CON_IC_SLAVE_DISABLE BIT(6) +#define BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE 6 +#define BIT_MASK_IC_CON_IC_SLAVE_DISABLE 0x1 +#define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(x) (((x) & BIT_MASK_IC_CON_IC_SLAVE_DISABLE) << BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE) + +#define BIT_IC_CON_IC_RESTART_EN BIT(5) +#define BIT_SHIFT_IC_CON_IC_RESTART_EN 5 +#define BIT_MASK_IC_CON_IC_RESTART_EN 0x1 +#define BIT_CTRL_IC_CON_IC_RESTART_EN(x) (((x) & BIT_MASK_IC_CON_IC_RESTART_EN) << BIT_SHIFT_IC_CON_IC_RESTART_EN) + +#define BIT_IC_CON_IC_10BITADDR_MASTER BIT(4) +#define BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER 4 +#define BIT_MASK_IC_CON_IC_10BITADDR_MASTER 0x1 +#define BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER) + +#define BIT_IC_CON_IC_10BITADDR_SLAVE BIT(3) +#define BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE 3 +#define BIT_MASK_IC_CON_IC_10BITADDR_SLAVE 0x1 +#define BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_SLAVE) << BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE) + + +#define BIT_SHIFT_IC_CON_SPEED 1 +#define BIT_MASK_IC_CON_SPEED 0x3 +#define BIT_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED) +#define BIT_CTRL_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED) +#define BIT_GET_IC_CON_SPEED(x) (((x) >> BIT_SHIFT_IC_CON_SPEED) & BIT_MASK_IC_CON_SPEED) + +#define BIT_IC_CON_MASTER_MODE BIT(0) +#define BIT_SHIFT_IC_CON_MASTER_MODE 0 +#define BIT_MASK_IC_CON_MASTER_MODE 0x1 +#define BIT_CTRL_IC_CON_MASTER_MODE(x) (((x) & BIT_MASK_IC_CON_MASTER_MODE) << BIT_SHIFT_IC_CON_MASTER_MODE) + + +//2 REG_DW_I2C_IC_TAR +#define BIT_IC_TAR_IC_10BITADDR_MASTER BIT(12) +#define BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER 12 +#define BIT_MASK_IC_TAR_IC_10BITADDR_MASTER 0x1 +#define BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_TAR_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER) + +#define BIT_IC_TAR_SPECIAL BIT(11) +#define BIT_SHIFT_IC_TAR_SPECIAL 11 +#define BIT_MASK_IC_TAR_SPECIAL 0x1 +#define BIT_CTRL_IC_TAR_SPECIAL(x) (((x) & BIT_MASK_IC_TAR_SPECIAL) << BIT_SHIFT_IC_TAR_SPECIAL) + +#define BIT_IC_TAR_GC_OR_START BIT(10) +#define BIT_SHIFT_IC_TAR_GC_OR_START 10 +#define BIT_MASK_IC_TAR_GC_OR_START 0x1 +#define BIT_CTRL_IC_TAR_GC_OR_START(x) (((x) & BIT_MASK_IC_TAR_GC_OR_START) << BIT_SHIFT_IC_TAR_GC_OR_START) + + +#define BIT_SHIFT_IC_TAR 0 +#define BIT_MASK_IC_TAR 0x3ff +#define BIT_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR) +#define BIT_CTRL_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR) +#define BIT_GET_IC_TAR(x) (((x) >> BIT_SHIFT_IC_TAR) & BIT_MASK_IC_TAR) + + +//2 REG_DW_I2C_IC_SAR + +#define BIT_SHIFT_IC_SAR 0 +#define BIT_MASK_IC_SAR 0x3ff +#define BIT_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR) +#define BIT_CTRL_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR) +#define BIT_GET_IC_SAR(x) (((x) >> BIT_SHIFT_IC_SAR) & BIT_MASK_IC_SAR) + + +//2 REG_DW_I2C_IC_HS_MADDR + +#define BIT_SHIFT_IC_HS_MADDR 0 +#define BIT_MASK_IC_HS_MADDR 0x7 +#define BIT_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR) +#define BIT_CTRL_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR) +#define BIT_GET_IC_HS_MADDR(x) (((x) >> BIT_SHIFT_IC_HS_MADDR) & BIT_MASK_IC_HS_MADDR) + + +//2 REG_DW_I2C_IC_DATA_CMD +#define BIT_IC_DATA_CMD_RESTART BIT(10) +#define BIT_SHIFT_IC_DATA_CMD_RESTART 10 +#define BIT_MASK_IC_DATA_CMD_RESTART 0x1 +#define BIT_CTRL_IC_DATA_CMD_RESTART(x) (((x) & BIT_MASK_IC_DATA_CMD_RESTART) << BIT_SHIFT_IC_DATA_CMD_RESTART) + +#define BIT_IC_DATA_CMD_STOP BIT(9) +#define BIT_SHIFT_IC_DATA_CMD_STOP 9 +#define BIT_MASK_IC_DATA_CMD_STOP 0x1 +#define BIT_CTRL_IC_DATA_CMD_STOP(x) (((x) & BIT_MASK_IC_DATA_CMD_STOP) << BIT_SHIFT_IC_DATA_CMD_STOP) + +#define BIT_IC_DATA_CMD_CMD BIT(8) +#define BIT_SHIFT_IC_DATA_CMD_CMD 8 +#define BIT_MASK_IC_DATA_CMD_CMD 0x1 +#define BIT_CTRL_IC_DATA_CMD_CMD(x) (((x) & BIT_MASK_IC_DATA_CMD_CMD) << BIT_SHIFT_IC_DATA_CMD_CMD) + + +#define BIT_SHIFT_IC_DATA_CMD_DAT 0 +#define BIT_MASK_IC_DATA_CMD_DAT 0xff +#define BIT_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT) +#define BIT_CTRL_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT) +#define BIT_GET_IC_DATA_CMD_DAT(x) (((x) >> BIT_SHIFT_IC_DATA_CMD_DAT) & BIT_MASK_IC_DATA_CMD_DAT) + + +//2 REG_DW_I2C_IC_SS_SCL_HCNT + +#define BIT_SHIFT_IC_SS_SCL_HCNT 0 +#define BIT_MASK_IC_SS_SCL_HCNT 0xffff +#define BIT_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT) +#define BIT_CTRL_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT) +#define BIT_GET_IC_SS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_HCNT) & BIT_MASK_IC_SS_SCL_HCNT) + + +//2 REG_DW_I2C_IC_SS_SCL_LCNT + +#define BIT_SHIFT_IC_SS_SCL_LCNT 0 +#define BIT_MASK_IC_SS_SCL_LCNT 0xffff +#define BIT_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT) +#define BIT_CTRL_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT) +#define BIT_GET_IC_SS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_LCNT) & BIT_MASK_IC_SS_SCL_LCNT) + + +//2 REG_DW_I2C_IC_FS_SCL_HCNT + +#define BIT_SHIFT_IC_FS_SCL_HCNT 0 +#define BIT_MASK_IC_FS_SCL_HCNT 0xffff +#define BIT_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT) +#define BIT_CTRL_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT) +#define BIT_GET_IC_FS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_HCNT) & BIT_MASK_IC_FS_SCL_HCNT) + + +//2 REG_DW_I2C_IC_FS_SCL_LCNT + +#define BIT_SHIFT_IC_FS_SCL_LCNT 0 +#define BIT_MASK_IC_FS_SCL_LCNT 0xffff +#define BIT_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT) +#define BIT_CTRL_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT) +#define BIT_GET_IC_FS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_LCNT) & BIT_MASK_IC_FS_SCL_LCNT) + + +//2 REG_DW_I2C_IC_HS_SCL_HCNT + +#define BIT_SHIFT_IC_HS_SCL_HCNT 0 +#define BIT_MASK_IC_HS_SCL_HCNT 0xffff +#define BIT_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT) +#define BIT_CTRL_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT) +#define BIT_GET_IC_HS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_HCNT) & BIT_MASK_IC_HS_SCL_HCNT) + + +//2 REG_DW_I2C_IC_HS_SCL_LCNT + +#define BIT_SHIFT_IC_HS_SCL_LCNT 0 +#define BIT_MASK_IC_HS_SCL_LCNT 0xffff +#define BIT_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT) +#define BIT_CTRL_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT) +#define BIT_GET_IC_HS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_LCNT) & BIT_MASK_IC_HS_SCL_LCNT) + + +//2 REG_DW_I2C_IC_INTR_STAT +#define BIT_IC_INTR_STAT_R_GEN_CALL BIT(11) +#define BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL 11 +#define BIT_MASK_IC_INTR_STAT_R_GEN_CALL 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_GEN_CALL) << BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL) + +#define BIT_IC_INTR_STAT_R_START_DET BIT(10) +#define BIT_SHIFT_IC_INTR_STAT_R_START_DET 10 +#define BIT_MASK_IC_INTR_STAT_R_START_DET 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_START_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_START_DET) << BIT_SHIFT_IC_INTR_STAT_R_START_DET) + +#define BIT_IC_INTR_STAT_R_STOP_DET BIT(9) +#define BIT_SHIFT_IC_INTR_STAT_R_STOP_DET 9 +#define BIT_MASK_IC_INTR_STAT_R_STOP_DET 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_STOP_DET) << BIT_SHIFT_IC_INTR_STAT_R_STOP_DET) + +#define BIT_IC_INTR_STAT_R_ACTIVITY BIT(8) +#define BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY 8 +#define BIT_MASK_IC_INTR_STAT_R_ACTIVITY 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_ACTIVITY) << BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY) + +#define BIT_IC_INTR_STAT_R_RX_DONE BIT(7) +#define BIT_SHIFT_IC_INTR_STAT_R_RX_DONE 7 +#define BIT_MASK_IC_INTR_STAT_R_RX_DONE 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_DONE) << BIT_SHIFT_IC_INTR_STAT_R_RX_DONE) + +#define BIT_IC_INTR_STAT_R_TX_ABRT BIT(6) +#define BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT 6 +#define BIT_MASK_IC_INTR_STAT_R_TX_ABRT 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_ABRT) << BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT) + +#define BIT_IC_INTR_STAT_R_RD_REQ BIT(5) +#define BIT_SHIFT_IC_INTR_STAT_R_RD_REQ 5 +#define BIT_MASK_IC_INTR_STAT_R_RD_REQ 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RD_REQ) << BIT_SHIFT_IC_INTR_STAT_R_RD_REQ) + +#define BIT_IC_INTR_STAT_R_TX_EMPTY BIT(4) +#define BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY 4 +#define BIT_MASK_IC_INTR_STAT_R_TX_EMPTY 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_EMPTY) << BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY) + +#define BIT_IC_INTR_STAT_R_TX_OVER BIT(3) +#define BIT_SHIFT_IC_INTR_STAT_R_TX_OVER 3 +#define BIT_MASK_IC_INTR_STAT_R_TX_OVER 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_TX_OVER) + +#define BIT_IC_INTR_STAT_R_RX_FULL BIT(2) +#define BIT_SHIFT_IC_INTR_STAT_R_RX_FULL 2 +#define BIT_MASK_IC_INTR_STAT_R_RX_FULL 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_FULL) << BIT_SHIFT_IC_INTR_STAT_R_RX_FULL) + +#define BIT_IC_INTR_STAT_R_RX_OVER BIT(1) +#define BIT_SHIFT_IC_INTR_STAT_R_RX_OVER 1 +#define BIT_MASK_IC_INTR_STAT_R_RX_OVER 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_RX_OVER) + +#define BIT_IC_INTR_STAT_R_RX_UNDER BIT(0) +#define BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER 0 +#define BIT_MASK_IC_INTR_STAT_R_RX_UNDER 0x1 +#define BIT_CTRL_IC_INTR_STAT_R_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_UNDER) << BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER) + + +//2 REG_DW_I2C_IC_INTR_MASK +#define BIT_IC_INTR_MASK_M_GEN_CALL BIT(11) +#define BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL 11 +#define BIT_MASK_IC_INTR_MASK_M_GEN_CALL 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_GEN_CALL) << BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL) + +#define BIT_IC_INTR_MASK_M_START_DET BIT(10) +#define BIT_SHIFT_IC_INTR_MASK_M_START_DET 10 +#define BIT_MASK_IC_INTR_MASK_M_START_DET 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_START_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_START_DET) << BIT_SHIFT_IC_INTR_MASK_M_START_DET) + +#define BIT_IC_INTR_MASK_M_STOP_DET BIT(9) +#define BIT_SHIFT_IC_INTR_MASK_M_STOP_DET 9 +#define BIT_MASK_IC_INTR_MASK_M_STOP_DET 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_STOP_DET) << BIT_SHIFT_IC_INTR_MASK_M_STOP_DET) + +#define BIT_IC_INTR_MASK_M_ACTIVITY BIT(8) +#define BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY 8 +#define BIT_MASK_IC_INTR_MASK_M_ACTIVITY 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_ACTIVITY) << BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY) + +#define BIT_IC_INTR_MASK_M_RX_DONE BIT(7) +#define BIT_SHIFT_IC_INTR_MASK_M_RX_DONE 7 +#define BIT_MASK_IC_INTR_MASK_M_RX_DONE 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_DONE) << BIT_SHIFT_IC_INTR_MASK_M_RX_DONE) + +#define BIT_IC_INTR_MASK_M_TX_ABRT BIT(6) +#define BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT 6 +#define BIT_MASK_IC_INTR_MASK_M_TX_ABRT 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_ABRT) << BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT) + +#define BIT_IC_INTR_MASK_M_RD_REQ BIT(5) +#define BIT_SHIFT_IC_INTR_MASK_M_RD_REQ 5 +#define BIT_MASK_IC_INTR_MASK_M_RD_REQ 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RD_REQ) << BIT_SHIFT_IC_INTR_MASK_M_RD_REQ) + +#define BIT_IC_INTR_MASK_M_TX_EMPTY BIT(4) +#define BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY 4 +#define BIT_MASK_IC_INTR_MASK_M_TX_EMPTY 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_EMPTY) << BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY) + +#define BIT_IC_INTR_MASK_M_TX_OVER BIT(3) +#define BIT_SHIFT_IC_INTR_MASK_M_TX_OVER 3 +#define BIT_MASK_IC_INTR_MASK_M_TX_OVER 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_TX_OVER) + +#define BIT_IC_INTR_MASK_M_RX_FULL BIT(2) +#define BIT_SHIFT_IC_INTR_MASK_M_RX_FULL 2 +#define BIT_MASK_IC_INTR_MASK_M_RX_FULL 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_FULL) << BIT_SHIFT_IC_INTR_MASK_M_RX_FULL) + +#define BIT_IC_INTR_MASK_M_RX_OVER BIT(1) +#define BIT_SHIFT_IC_INTR_MASK_M_RX_OVER 1 +#define BIT_MASK_IC_INTR_MASK_M_RX_OVER 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_RX_OVER) + +#define BIT_IC_INTR_MASK_M_RX_UNDER BIT(0) +#define BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER 0 +#define BIT_MASK_IC_INTR_MASK_M_RX_UNDER 0x1 +#define BIT_CTRL_IC_INTR_MASK_M_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_UNDER) << BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER) + + +//2 REG_DW_I2C_IC_RAW_INTR_STAT +#define BIT_IC_RAW_INTR_STAT_GEN_CALL BIT(11) +#define BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL 11 +#define BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_GEN_CALL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL) << BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL) + +#define BIT_IC_RAW_INTR_STAT_START_DET BIT(10) +#define BIT_SHIFT_IC_RAW_INTR_STAT_START_DET 10 +#define BIT_MASK_IC_RAW_INTR_STAT_START_DET 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_START_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_START_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_START_DET) + +#define BIT_IC_RAW_INTR_STAT_STOP_DET BIT(9) +#define BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET 9 +#define BIT_MASK_IC_RAW_INTR_STAT_STOP_DET 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_STOP_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_STOP_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET) + +#define BIT_IC_RAW_INTR_STAT_ACTIVITY BIT(8) +#define BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY 8 +#define BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_ACTIVITY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY) << BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY) + +#define BIT_IC_RAW_INTR_STAT_RX_DONE BIT(7) +#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE 7 +#define BIT_MASK_IC_RAW_INTR_STAT_RX_DONE 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_RX_DONE(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_DONE) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE) + +#define BIT_IC_RAW_INTR_STAT_TX_ABRT BIT(6) +#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT 6 +#define BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_TX_ABRT(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT) + +#define BIT_IC_RAW_INTR_STAT_RD_REQ BIT(5) +#define BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ 5 +#define BIT_MASK_IC_RAW_INTR_STAT_RD_REQ 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_RD_REQ(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RD_REQ) << BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ) + +#define BIT_IC_RAW_INTR_STAT_TX_EMPTY BIT(4) +#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY 4 +#define BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_TX_EMPTY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY) + +#define BIT_IC_RAW_INTR_STAT_TX_OVER BIT(3) +#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER 3 +#define BIT_MASK_IC_RAW_INTR_STAT_TX_OVER 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_TX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER) + +#define BIT_IC_RAW_INTR_STAT_RX_FULL BIT(2) +#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL 2 +#define BIT_MASK_IC_RAW_INTR_STAT_RX_FULL 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_RX_FULL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_FULL) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL) + +#define BIT_IC_RAW_INTR_STAT_RX_OVER BIT(1) +#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER 1 +#define BIT_MASK_IC_RAW_INTR_STAT_RX_OVER 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_RX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER) + +#define BIT_IC_RAW_INTR_STAT_RX_UNDER BIT(0) +#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER 0 +#define BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER 0x1 +#define BIT_CTRL_IC_RAW_INTR_STAT_RX_UNDER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER) + + +//2 REG_DW_I2C_IC_RX_TL + +#define BIT_SHIFT_IC_RX_TL 0 +#define BIT_MASK_IC_RX_TL 0xff +#define BIT_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL) +#define BIT_CTRL_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL) +#define BIT_GET_IC_RX_TL(x) (((x) >> BIT_SHIFT_IC_RX_TL) & BIT_MASK_IC_RX_TL) + + +//2 REG_DW_I2C_IC_TX_TL + +#define BIT_SHIFT_IC_TX_TL 0 +#define BIT_MASK_IC_TX_TL 0xff +#define BIT_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL) +#define BIT_CTRL_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL) +#define BIT_GET_IC_TX_TL(x) (((x) >> BIT_SHIFT_IC_TX_TL) & BIT_MASK_IC_TX_TL) + + +//2 REG_DW_I2C_IC_CLR_INTR +#define BIT_IC_CLR_INTR BIT(0) +#define BIT_SHIFT_IC_CLR_INTR 0 +#define BIT_MASK_IC_CLR_INTR 0x1 +#define BIT_CTRL_IC_CLR_INTR(x) (((x) & BIT_MASK_IC_CLR_INTR) << BIT_SHIFT_IC_CLR_INTR) + + +//2 REG_DW_I2C_IC_CLR_RX_UNDER +#define BIT_IC_CLR_RX_UNDER BIT(0) +#define BIT_SHIFT_IC_CLR_RX_UNDER 0 +#define BIT_MASK_IC_CLR_RX_UNDER 0x1 +#define BIT_CTRL_IC_CLR_RX_UNDER(x) (((x) & BIT_MASK_IC_CLR_RX_UNDER) << BIT_SHIFT_IC_CLR_RX_UNDER) + + +//2 REG_DW_I2C_IC_CLR_RX_OVER +#define BIT_IC_CLR_RX_OVER BIT(0) +#define BIT_SHIFT_IC_CLR_RX_OVER 0 +#define BIT_MASK_IC_CLR_RX_OVER 0x1 +#define BIT_CTRL_IC_CLR_RX_OVER(x) (((x) & BIT_MASK_IC_CLR_RX_OVER) << BIT_SHIFT_IC_CLR_RX_OVER) + + +//2 REG_DW_I2C_IC_CLR_TX_OVER +#define BIT_IC_CLR_TX_OVER BIT(0) +#define BIT_SHIFT_IC_CLR_TX_OVER 0 +#define BIT_MASK_IC_CLR_TX_OVER 0x1 +#define BIT_CTRL_IC_CLR_TX_OVER(x) (((x) & BIT_MASK_IC_CLR_TX_OVER) << BIT_SHIFT_IC_CLR_TX_OVER) + + +//2 REG_DW_I2C_IC_CLR_RD_REQ +#define BIT_IC_CLR_RD_REQ BIT(0) +#define BIT_SHIFT_IC_CLR_RD_REQ 0 +#define BIT_MASK_IC_CLR_RD_REQ 0x1 +#define BIT_CTRL_IC_CLR_RD_REQ(x) (((x) & BIT_MASK_IC_CLR_RD_REQ) << BIT_SHIFT_IC_CLR_RD_REQ) + + +//2 REG_DW_I2C_IC_CLR_TX_ABRT +#define BIT_CLR_RD_REQ BIT(0) +#define BIT_SHIFT_CLR_RD_REQ 0 +#define BIT_MASK_CLR_RD_REQ 0x1 +#define BIT_CTRL_CLR_RD_REQ(x) (((x) & BIT_MASK_CLR_RD_REQ) << BIT_SHIFT_CLR_RD_REQ) + + +//2 REG_DW_I2C_IC_CLR_RX_DONE +#define BIT_IC_CLR_RX_DONE BIT(0) +#define BIT_SHIFT_IC_CLR_RX_DONE 0 +#define BIT_MASK_IC_CLR_RX_DONE 0x1 +#define BIT_CTRL_IC_CLR_RX_DONE(x) (((x) & BIT_MASK_IC_CLR_RX_DONE) << BIT_SHIFT_IC_CLR_RX_DONE) + + +//2 REG_DW_I2C_IC_CLR_ACTIVITY +#define BIT_IC_CLR_ACTIVITY BIT(0) +#define BIT_SHIFT_IC_CLR_ACTIVITY 0 +#define BIT_MASK_IC_CLR_ACTIVITY 0x1 +#define BIT_CTRL_IC_CLR_ACTIVITY(x) (((x) & BIT_MASK_IC_CLR_ACTIVITY) << BIT_SHIFT_IC_CLR_ACTIVITY) + + +//2 REG_DW_I2C_IC_CLR_STOP_DET +#define BIT_IC_CLR_STOP_DET BIT(0) +#define BIT_SHIFT_IC_CLR_STOP_DET 0 +#define BIT_MASK_IC_CLR_STOP_DET 0x1 +#define BIT_CTRL_IC_CLR_STOP_DET(x) (((x) & BIT_MASK_IC_CLR_STOP_DET) << BIT_SHIFT_IC_CLR_STOP_DET) + + +//2 REG_DW_I2C_IC_CLR_START_DET +#define BIT_IC_CLR_START_DET BIT(0) +#define BIT_SHIFT_IC_CLR_START_DET 0 +#define BIT_MASK_IC_CLR_START_DET 0x1 +#define BIT_CTRL_IC_CLR_START_DET(x) (((x) & BIT_MASK_IC_CLR_START_DET) << BIT_SHIFT_IC_CLR_START_DET) + + +//2 REG_DW_I2C_IC_CLR_GEN_CALL +#define BIT_IC_CLR_GEN_CALL BIT(0) +#define BIT_SHIFT_IC_CLR_GEN_CALL 0 +#define BIT_MASK_IC_CLR_GEN_CALL 0x1 +#define BIT_CTRL_IC_CLR_GEN_CALL(x) (((x) & BIT_MASK_IC_CLR_GEN_CALL) << BIT_SHIFT_IC_CLR_GEN_CALL) + + +//2 REG_DW_I2C_IC_ENABLE +#define BIT_IC_ENABLE BIT(0) +#define BIT_SHIFT_IC_ENABLE 0 +#define BIT_MASK_IC_ENABLE 0x1 +#define BIT_CTRL_IC_ENABLE(x) (((x) & BIT_MASK_IC_ENABLE) << BIT_SHIFT_IC_ENABLE) + + +//2 REG_DW_I2C_IC_STATUS +#define BIT_IC_STATUS_SLV_ACTIVITY BIT(6) +#define BIT_SHIFT_IC_STATUS_SLV_ACTIVITY 6 +#define BIT_MASK_IC_STATUS_SLV_ACTIVITY 0x1 +#define BIT_CTRL_IC_STATUS_SLV_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_SLV_ACTIVITY) << BIT_SHIFT_IC_STATUS_SLV_ACTIVITY) + +#define BIT_IC_STATUS_MST_ACTIVITY BIT(5) +#define BIT_SHIFT_IC_STATUS_MST_ACTIVITY 5 +#define BIT_MASK_IC_STATUS_MST_ACTIVITY 0x1 +#define BIT_CTRL_IC_STATUS_MST_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_MST_ACTIVITY) << BIT_SHIFT_IC_STATUS_MST_ACTIVITY) + +#define BIT_IC_STATUS_RFF BIT(4) +#define BIT_SHIFT_IC_STATUS_RFF 4 +#define BIT_MASK_IC_STATUS_RFF 0x1 +#define BIT_CTRL_IC_STATUS_RFF(x) (((x) & BIT_MASK_IC_STATUS_RFF) << BIT_SHIFT_IC_STATUS_RFF) + +#define BIT_IC_STATUS_RFNE BIT(3) +#define BIT_SHIFT_IC_STATUS_RFNE 3 +#define BIT_MASK_IC_STATUS_RFNE 0x1 +#define BIT_CTRL_IC_STATUS_RFNE(x) (((x) & BIT_MASK_IC_STATUS_RFNE) << BIT_SHIFT_IC_STATUS_RFNE) + +#define BIT_IC_STATUS_TFE BIT(2) +#define BIT_SHIFT_IC_STATUS_TFE 2 +#define BIT_MASK_IC_STATUS_TFE 0x1 +#define BIT_CTRL_IC_STATUS_TFE(x) (((x) & BIT_MASK_IC_STATUS_TFE) << BIT_SHIFT_IC_STATUS_TFE) + +#define BIT_IC_STATUS_TFNF BIT(1) +#define BIT_SHIFT_IC_STATUS_TFNF 1 +#define BIT_MASK_IC_STATUS_TFNF 0x1 +#define BIT_CTRL_IC_STATUS_TFNF(x) (((x) & BIT_MASK_IC_STATUS_TFNF) << BIT_SHIFT_IC_STATUS_TFNF) + +#define BIT_IC_STATUS_ACTIVITY BIT(0) +#define BIT_SHIFT_IC_STATUS_ACTIVITY 0 +#define BIT_MASK_IC_STATUS_ACTIVITY 0x1 +#define BIT_CTRL_IC_STATUS_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_ACTIVITY) << BIT_SHIFT_IC_STATUS_ACTIVITY) + + +//2 REG_DW_I2C_IC_TXFLR + +#define BIT_SHIFT_IC_TXFLR 0 +#define BIT_MASK_IC_TXFLR 0x3f +#define BIT_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR) +#define BIT_CTRL_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR) +#define BIT_GET_IC_TXFLR(x) (((x) >> BIT_SHIFT_IC_TXFLR) & BIT_MASK_IC_TXFLR) + + +//2 REG_DW_I2C_IC_RXFLR + +#define BIT_SHIFT_IC_RXFLR 0 +#define BIT_MASK_IC_RXFLR 0x1f +#define BIT_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR) +#define BIT_CTRL_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR) +#define BIT_GET_IC_RXFLR(x) (((x) >> BIT_SHIFT_IC_RXFLR) & BIT_MASK_IC_RXFLR) + + +//2 REG_DW_I2C_IC_SDA_HOLD + +#define BIT_SHIFT_IC_SDA_HOLD 0 +#define BIT_MASK_IC_SDA_HOLD 0xffff +#define BIT_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD) +#define BIT_CTRL_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD) +#define BIT_GET_IC_SDA_HOLD(x) (((x) >> BIT_SHIFT_IC_SDA_HOLD) & BIT_MASK_IC_SDA_HOLD) + + +//2 REG_DW_I2C_IC_TX_ABRT_SOURCE +#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX BIT(15) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 15 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST BIT(14) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 14 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO BIT(13) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 13 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO) + +#define BIT_IC_TX_ABRT_SOURCE_ARB_LOST BIT(12) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST 12 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ARB_LOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS BIT(11) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 11 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT BIT(10) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 10 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT BIT(9) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 9 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT BIT(8) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 8 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET BIT(7) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 7 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET BIT(6) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 6 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ BIT(5) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 5 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK BIT(4) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 4 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK BIT(3) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 3 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK BIT(2) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 2 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK BIT(1) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 1 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK) + +#define BIT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK BIT(0) +#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0 +#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0x1 +#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK) + + +//2 REG_DW_I2C_IC_SLV_DATA_NACK_ONLY +#define BIT_IC_SLV_DATA_NACK_ONLY BIT(0) +#define BIT_SHIFT_IC_SLV_DATA_NACK_ONLY 0 +#define BIT_MASK_IC_SLV_DATA_NACK_ONLY 0x1 +#define BIT_CTRL_IC_SLV_DATA_NACK_ONLY(x) (((x) & BIT_MASK_IC_SLV_DATA_NACK_ONLY) << BIT_SHIFT_IC_SLV_DATA_NACK_ONLY) + + +//2 REG_DW_I2C_IC_DMA_CR +#define BIT_IC_DMA_CR_TDMAE BIT(1) +#define BIT_SHIFT_IC_DMA_CR_TDMAE 1 +#define BIT_MASK_IC_DMA_CR_TDMAE 0x1 +#define BIT_CTRL_IC_DMA_CR_TDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_TDMAE) << BIT_SHIFT_IC_DMA_CR_TDMAE) + +#define BIT_IC_DMA_CR_RDMAE BIT(0) +#define BIT_SHIFT_IC_DMA_CR_RDMAE 0 +#define BIT_MASK_IC_DMA_CR_RDMAE 0x1 +#define BIT_CTRL_IC_DMA_CR_RDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_RDMAE) << BIT_SHIFT_IC_DMA_CR_RDMAE) + + +//2 REG_DW_I2C_IC_DMA_TDLR + +#define BIT_SHIFT_IC_DMA_TDLR_DMATDL 0 +#define BIT_MASK_IC_DMA_TDLR_DMATDL 0x1f +#define BIT_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL) +#define BIT_CTRL_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL) +#define BIT_GET_IC_DMA_TDLR_DMATDL(x) (((x) >> BIT_SHIFT_IC_DMA_TDLR_DMATDL) & BIT_MASK_IC_DMA_TDLR_DMATDL) + + +//2 REG_DW_I2C_IC_DMA_RDLR + +#define BIT_SHIFT_IC_DMA_RDLR_DMARDL 0 +#define BIT_MASK_IC_DMA_RDLR_DMARDL 0xf +#define BIT_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL) +#define BIT_CTRL_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL) +#define BIT_GET_IC_DMA_RDLR_DMARDL(x) (((x) >> BIT_SHIFT_IC_DMA_RDLR_DMARDL) & BIT_MASK_IC_DMA_RDLR_DMARDL) + + +//2 REG_DW_I2C_IC_SDA_SETUP + +#define BIT_SHIFT_IC_SDA_SETUP 0 +#define BIT_MASK_IC_SDA_SETUP 0xff +#define BIT_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP) +#define BIT_CTRL_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP) +#define BIT_GET_IC_SDA_SETUP(x) (((x) >> BIT_SHIFT_IC_SDA_SETUP) & BIT_MASK_IC_SDA_SETUP) + + +//2 REG_DW_I2C_IC_ACK_GENERAL_CALL +#define BIT_IC_ACK_GENERAL_CALL BIT(0) +#define BIT_SHIFT_IC_ACK_GENERAL_CALL 0 +#define BIT_MASK_IC_ACK_GENERAL_CALL 0x1 +#define BIT_CTRL_IC_ACK_GENERAL_CALL(x) (((x) & BIT_MASK_IC_ACK_GENERAL_CALL) << BIT_SHIFT_IC_ACK_GENERAL_CALL) + + +//2 REG_DW_I2C_IC_ENABLE_STATUS +#define BIT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST BIT(2) +#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 2 +#define BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 0x1 +#define BIT_CTRL_IC_ENABLE_STATUS_SLV_RX_DATA_LOST(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST) + +#define BIT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY BIT(1) +#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 1 +#define BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 0x1 +#define BIT_CTRL_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY) + +#define BIT_IC_ENABLE_STATUS_IC_EN BIT(0) +#define BIT_SHIFT_IC_ENABLE_STATUS_IC_EN 0 +#define BIT_MASK_IC_ENABLE_STATUS_IC_EN 0x1 +#define BIT_CTRL_IC_ENABLE_STATUS_IC_EN(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_IC_EN) << BIT_SHIFT_IC_ENABLE_STATUS_IC_EN) + + +//2 REG_DW_I2C_IC_COMP_PARAM_1 + +#define BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 16 +#define BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 0xff +#define BIT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) +#define BIT_CTRL_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) +#define BIT_GET_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) + + +#define BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 8 +#define BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 0xff +#define BIT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) +#define BIT_CTRL_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) +#define BIT_GET_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) + +#define BIT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS BIT(7) +#define BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 7 +#define BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 0x1 +#define BIT_CTRL_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS) << BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS) + +#define BIT_IC_COMP_PARAM_1_HAS_DMA BIT(6) +#define BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA 6 +#define BIT_MASK_IC_COMP_PARAM_1_HAS_DMA 0x1 +#define BIT_CTRL_IC_COMP_PARAM_1_HAS_DMA(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HAS_DMA) << BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA) + +#define BIT_IC_COMP_PARAM_1_INTR_IO BIT(5) +#define BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO 5 +#define BIT_MASK_IC_COMP_PARAM_1_INTR_IO 0x1 +#define BIT_CTRL_IC_COMP_PARAM_1_INTR_IO(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_INTR_IO) << BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO) + +#define BIT_IC_COMP_PARAM_1_HC_COUNT_VALUES BIT(4) +#define BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES 4 +#define BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES 0x1 +#define BIT_CTRL_IC_COMP_PARAM_1_HC_COUNT_VALUES(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES) << BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES) + + +#define BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE 2 +#define BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE 0x3 +#define BIT_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) +#define BIT_CTRL_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) +#define BIT_GET_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) + + +#define BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH 0 +#define BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH 0x3 +#define BIT_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) +#define BIT_CTRL_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) +#define BIT_GET_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) + + +//2 REG_DW_I2C_IC_COMP_VERSION + +#define BIT_SHIFT_IC_COMP_VERSION 0 +#define BIT_MASK_IC_COMP_VERSION 0xffffffffL +#define BIT_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION) +#define BIT_CTRL_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION) +#define BIT_GET_IC_COMP_VERSION(x) (((x) >> BIT_SHIFT_IC_COMP_VERSION) & BIT_MASK_IC_COMP_VERSION) + + +//2 REG_DW_I2C_IC_COMP_TYPE + +#define BIT_SHIFT_IC_COMP_TYPE 0 +#define BIT_MASK_IC_COMP_TYPE 0xffffffffL +#define BIT_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE) +#define BIT_CTRL_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE) +#define BIT_GET_IC_COMP_TYPE(x) (((x) >> BIT_SHIFT_IC_COMP_TYPE) & BIT_MASK_IC_COMP_TYPE) + +//======================== Register Address Definition ======================== +#define REG_DW_I2C_IC_CON 0x0000 +#define REG_DW_I2C_IC_TAR 0x0004 +#define REG_DW_I2C_IC_SAR 0x0008 +#define REG_DW_I2C_IC_HS_MADDR 0x000C +#define REG_DW_I2C_IC_DATA_CMD 0x0010 +#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014 +#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018 +#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C +#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020 +#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024 +#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028 +#define REG_DW_I2C_IC_INTR_STAT 0x002C +#define REG_DW_I2C_IC_INTR_MASK 0x0030 +#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034 +#define REG_DW_I2C_IC_RX_TL 0x0038 +#define REG_DW_I2C_IC_TX_TL 0x003C +#define REG_DW_I2C_IC_CLR_INTR 0x0040 +#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044 +#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048 +#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C +#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050 +#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054 +#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058 +#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C +#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060 +#define REG_DW_I2C_IC_CLR_START_DET 0x0064 +#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068 +#define REG_DW_I2C_IC_ENABLE 0x006C +#define REG_DW_I2C_IC_STATUS 0x0070 +#define REG_DW_I2C_IC_TXFLR 0x0074 +#define REG_DW_I2C_IC_RXFLR 0x0078 +#define REG_DW_I2C_IC_SDA_HOLD 0x007C +#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080 +#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084 +#define REG_DW_I2C_IC_DMA_CR 0x0088 +#define REG_DW_I2C_IC_DMA_TDLR 0x008C +#define REG_DW_I2C_IC_DMA_RDLR 0x0090 +#define REG_DW_I2C_IC_SDA_SETUP 0x0094 +#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098 +#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C +#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4 +#define REG_DW_I2C_IC_COMP_VERSION 0x00F8 +#define REG_DW_I2C_IC_COMP_TYPE 0x00FC + +//====================================================== +// I2C related enumeration +// I2C Address Mode +typedef enum _I2C_ADDR_MODE_ { + I2C_ADDR_7BIT = 0, + I2C_ADDR_10BIT = 1, +}I2C_ADDR_MODE,*PI2C_ADDR_MODE; + +// I2C Speed Mode +typedef enum _I2C_SPD_MODE_ { + I2C_SS_MODE = 1, + I2C_FS_MODE = 2, + I2C_HS_MODE = 3, +}I2C_SPD_MODE,*PI2C_SPD_MODE; + +//I2C Timing Parameters +#define I2C_SS_MIN_SCL_HTIME 4000 //the unit is ns. +#define I2C_SS_MIN_SCL_LTIME 4700 //the unit is ns. + +#define I2C_FS_MIN_SCL_HTIME 600 //the unit is ns. +#define I2C_FS_MIN_SCL_LTIME 1300 //the unit is ns. + +#define I2C_HS_MIN_SCL_HTIME_100 60 //the unit is ns, with bus loading = 100pf +#define I2C_HS_MIN_SCL_LTIME_100 120 //the unit is ns., with bus loading = 100pf + +#define I2C_HS_MIN_SCL_HTIME_400 160 //the unit is ns, with bus loading = 400pf +#define I2C_HS_MIN_SCL_LTIME_400 320 //the unit is ns., with bus loading = 400pf + + +//====================================================== +//I2C Essential functions and macros +_LONG_CALL_ROM_ VOID HalI2CWrite32(IN u8 I2CIdx, IN u8 I2CReg, IN u32 I2CVal); +_LONG_CALL_ROM_ u32 HalI2CRead32(IN u8 I2CIdx, IN u8 I2CReg); + +#define HAL_I2C_WRITE32(I2CIdx, addr, value) HalI2CWrite32(I2CIdx,addr,value) +#define HAL_I2C_READ32(I2CIdx, addr) HalI2CRead32(I2CIdx,addr) + +// Rtl8195a I2C function prototypes +_LONG_CALL_ HAL_Status HalI2CEnableRtl8195a(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CInit8195a(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CDeInit8195a(IN VOID *Data); +_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195a(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CSendRtl8195a(IN VOID *Data); +_LONG_CALL_ u8 HalI2CReceiveRtl8195a(IN VOID *Data); +_LONG_CALL_ROM_ HAL_Status HalI2CIntrCtrl8195a(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CClrIntrRtl8195a(IN VOID *Data); +_LONG_CALL_ROM_ HAL_Status HalI2CClrAllIntrRtl8195a(IN VOID *Data); +_LONG_CALL_ HAL_Status HalI2CDMACtrl8195a(IN VOID *Data); +_LONG_CALL_ u32 HalI2CReadRegRtl8195a(IN VOID *Data, IN u8 I2CReg); +_LONG_CALL_ HAL_Status HalI2CWriteRegRtl8195a(IN VOID *Data, IN u8 I2CReg, IN u32 RegVal); + +//Rtl8195a I2C V02 function prototype +_LONG_CALL_ HAL_Status HalI2CSendRtl8195aV02(IN VOID *Data); +#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT) +_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data); +#elif defined(CONFIG_CHIP_E_CUT) +_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data); +#endif +//Rtl8195a I2C V02 function prototype END + +HAL_Status HalI2CInit8195a_Patch(IN VOID *Data); +HAL_Status HalI2CSendRtl8195a_Patch(IN VOID *Data); +HAL_Status HalI2CSetCLKRtl8195a_Patch(IN VOID *Data); + +#endif diff --git a/lib/fwlib/rtl8195a/rtl8195a_i2s.h b/lib/fwlib/rtl8195a/rtl8195a_i2s.h new file mode 100644 index 0000000..33a0bf8 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_i2s.h @@ -0,0 +1,617 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _RTL8195A_I2S_H_ +#define _RTL8195A_I2S_H_ + + +//=============== Register Bit Field Definition ==================== +// REG_I2S_CONTROL +#define BIT_CTLX_I2S_EN BIT(0) +#define BIT_SHIFT_CTLX_I2S_EN 0 +#define BIT_MASK_CTLX_I2S_EN 0x1 +#define BIT_CTRL_CTLX_I2S_EN(x) (((x) & BIT_MASK_CTLX_I2S_EN) << BIT_SHIFT_CTLX_I2S_EN) + +#define BIT_SHIFT_CTLX_I2S_TRX_ACT 1 +#define BIT_MASK_CTLX_I2S_TRX_ACT 0x3 +#define BIT_CTRL_CTLX_I2S_TRX_ACT(x) (((x) & BIT_MASK_CTLX_I2S_TRX_ACT) << BIT_SHIFT_CTLX_I2S_TRX_ACT) +#define BIT_GET_CTLX_I2S_TRX_ACT(x) (((x) >> BIT_SHIFT_CTLX_I2S_TRX_ACT) & BIT_MASK_CTLX_I2S_TRX_ACT) + +#define BIT_SHIFT_CTLX_I2S_CH_NUM 3 +#define BIT_MASK_CTLX_I2S_CH_NUM 0x3 +#define BIT_CTRL_CTLX_I2S_CH_NUM(x) (((x) & BIT_MASK_CTLX_I2S_CH_NUM) << BIT_SHIFT_CTLX_I2S_CH_NUM) +#define BIT_GET_CTLX_I2S_CH_NUM(x) (((x) >> BIT_SHIFT_CTLX_I2S_CH_NUM) & BIT_MASK_CTLX_I2S_CH_NUM) + +#define BIT_CTLX_I2S_WL BIT(6) +#define BIT_SHIFT_CTLX_I2S_WL 6 +#define BIT_MASK_CTLX_I2S_WL 0x1 +#define BIT_CTRL_CTLX_I2S_WL(x) (((x) & BIT_MASK_CTLX_I2S_WL) << BIT_SHIFT_CTLX_I2S_WL) + +#define BIT_CTLX_I2S_LRSWAP BIT(10) +#define BIT_SHIFT_CTLX_I2S_LRSWAP 10 +#define BIT_MASK_CTLX_I2S_LRSWAP 0x1 +#define BIT_CTRL_CTLX_I2S_LRSWAP(x) (((x) & BIT_MASK_CTLX_I2S_LRSWAP) << BIT_SHIFT_CTLX_I2S_LRSWAP) + +#define BIT_CTLX_I2S_SCK_INV BIT(11) +#define BIT_SHIFT_CTLX_I2S_SCK_INV 11 +#define BIT_MASK_CTLX_I2S_SCK_INV 0x1 +#define BIT_CTRL_CTLX_I2S_SCK_INV(x) (((x) & BIT_MASK_CTLX_I2S_SCK_INV) << BIT_SHIFT_CTLX_I2S_SCK_INV) + +#define BIT_CTLX_I2S_ENDIAN_SWAP BIT(12) +#define BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP 12 +#define BIT_MASK_CTLX_I2S_ENDIAN_SWAP 0x1 +#define BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_I2S_ENDIAN_SWAP) << BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP) + +#define BIT_CTLX_I2S_SLAVE_MODE BIT(29) +#define BIT_SHIFT_CTLX_I2S_SLAVE_MODE 29 +#define BIT_MASK_CTLX_I2S_SLAVE_MODE 0x1 +#define BIT_CTRL_CTLX_I2S_SLAVE_MODE(x) (((x) & BIT_MASK_CTLX_I2S_SLAVE_MODE) << BIT_SHIFT_CTLX_I2S_SLAVE_MODE) + +#define BIT_CTLX_I2S_CLK_SRC BIT(30) +#define BIT_SHIFT_CTLX_I2S_CLK_SRC 30 +#define BIT_MASK_CTLX_I2S_CLK_SRC 0x1 +#define BIT_CTRL_CTLX_I2S_CLK_SRC(x) (((x) & BIT_MASK_CTLX_I2S_CLK_SRC) << BIT_SHIFT_CTLX_I2S_CLK_SRC) + +#define BIT_CTLX_I2S_SW_RSTN BIT(31) +#define BIT_SHIFT_CTLX_I2S_SW_RSTN 31 +#define BIT_MASK_CTLX_I2S_SW_RSTN 0x1 +#define BIT_CTRL_CTLX_I2S_SW_RSTN(x) (((x) & BIT_MASK_CTLX_I2S_SW_RSTN) << BIT_SHIFT_CTLX_I2S_SW_RSTN) + +// REG_I2S_SETTING +#define BIT_SHIFT_SETTING_I2S_PAGE_SZ 0 +#define BIT_MASK_SETTING_I2S_PAGE_SZ 0xFFF +#define BIT_CTRL_SETTING_I2S_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_SZ) << BIT_SHIFT_SETTING_I2S_PAGE_SZ) +#define BIT_GET_SETTING_I2S_PAGE_SZ(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_SZ) & BIT_MASK_SETTING_I2S_PAGE_SZ) + +#define BIT_SHIFT_SETTING_I2S_PAGE_NUM 12 +#define BIT_MASK_SETTING_I2S_PAGE_NUM 0x3 +#define BIT_CTRL_SETTING_I2S_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_NUM) << BIT_SHIFT_SETTING_I2S_PAGE_NUM) +#define BIT_GET_SETTING_I2S_PAGE_NUM(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_NUM) & BIT_MASK_SETTING_I2S_PAGE_NUM) + +#define BIT_SHIFT_SETTING_I2S_SAMPLE_RATE 14 +#define BIT_MASK_SETTING_I2S_SAMPLE_RATE 0x7 +#define BIT_CTRL_SETTING_I2S_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_I2S_SAMPLE_RATE) << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE) +#define BIT_GET_SETTING_I2S_SAMPLE_RATE(x) (((x) >> BIT_SHIFT_SETTING_I2S_SAMPLE_RATE) & BIT_MASK_SETTING_I2S_SAMPLE_RATE) + +// i2s trx page own bit +#define BIT_PAGE_I2S_OWN_BIT BIT(31) +#define BIT_SHIFT_PAGE_I2S_OWN_BIT 31 +#define BIT_MASK_PAGE_I2S_OWN_BIT 0x1 +#define BIT_CTRL_PAGE_I2S_OWN_BIT(x) (((x) & BIT_MASK_PAGE_I2S_OWN_BIT) << BIT_SHIFT_PAGE_I2S_OWN_BIT) + +//=============== Register Address Definition ==================== +#define REG_I2S_PAGE_OWN_OFF 0x004 + +#define REG_I2S_CTL 0x000 +#define REG_I2S_TX_PAGE_PTR 0x004 +#define REG_I2S_RX_PAGE_PTR 0x008 +#define REG_I2S_SETTING 0x00C + +#define REG_I2S_TX_MASK_INT 0x010 +#define REG_I2S_TX_STATUS_INT 0x014 +#define REG_I2S_RX_MASK_INT 0x018 +#define REG_I2S_RX_STATUS_INT 0x01c + + +#define REG_I2S_TX_PAGE0_OWN 0x020 +#define REG_I2S_TX_PAGE1_OWN 0x024 +#define REG_I2S_TX_PAGE2_OWN 0x028 +#define REG_I2S_TX_PAGE3_OWN 0x02C +#define REG_I2S_RX_PAGE0_OWN 0x030 +#define REG_I2S_RX_PAGE1_OWN 0x034 +#define REG_I2S_RX_PAGE2_OWN 0x038 +#define REG_I2S_RX_PAGE3_OWN 0x03C + +/*I2S Essential Functions and Macros*/ +VOID +HalI2SWrite32( + IN u8 I2SIdx, + IN u8 I2SReg, + IN u32 I2SVal +); + +u32 +HalI2SRead32( + IN u8 I2SIdx, + IN u8 I2SReg +); + +/* +#define HAL_I2SX_READ32(I2sIndex, addr) \ + HAL_READ32(I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF), addr) +#define HAL_I2SX_WRITE32(I2sIndex, addr, value) \ + HAL_WRITE32((I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF)), addr, value) +*/ + +#define HAL_I2S_WRITE32(I2SIdx, addr, value) HalI2SWrite32(I2SIdx,addr,value) +#define HAL_I2S_READ32(I2SIdx, addr) HalI2SRead32(I2SIdx,addr) + +/* I2S debug output*/ +#define I2S_PREFIX "RTL8195A[i2s]: " +#define I2S_PREFIX_LVL " [i2s_DBG]: " + +typedef enum _I2S_DBG_LVL_ { + HAL_I2S_LVL = 0x01, + SAL_I2S_LVL = 0x02, + VERI_I2S_LVL = 0x03, +}I2S_DBG_LVL,*PI2S_DBG_LVL; + +#ifdef CONFIG_DEBUG_LOG +#ifdef CONFIG_DEBUG_LOG_I2S_HAL + + #define DBG_8195A_I2S(...) do{ \ + _DbgDump("\r"I2S_PREFIX __VA_ARGS__);\ + }while(0) + + + #define I2SDBGLVL 0xFF + #define DBG_8195A_I2S_LVL(LVL,...) do{\ + if (LVL&I2SDBGLVL){\ + _DbgDump("\r"I2S_PREFIX_LVL __VA_ARGS__);\ + }\ + }while(0) +#else + #define DBG_I2S_LOG_PERD 100 + #define DBG_8195A_I2S(...) + #define DBG_8195A_I2S_LVL(...) +#endif +#else + #define DBG_I2S_LOG_PERD 100 + #define DBG_8195A_I2S(...) + #define DBG_8195A_I2S_LVL(...) +#endif + +/* +#define REG_I2S_PAGE_OWN_OFF 0x004 +#define REG_I2S_CTL 0x000 +#define REG_I2S_TX_PAGE_PTR 0x004 +#define REG_I2S_RX_PAGE_PTR 0x008 +#define REG_I2S_SETTING 0x00C + +#define REG_I2S_TX_MASK_INT 0x010 +#define REG_I2S_TX_STATUS_INT 0x014 +#define REG_I2S_RX_MASK_INT 0x018 +#define REG_I2S_RX_STATUS_INT 0x01c + + + +#define REG_I2S_TX_PAGE0_OWN 0x020 +#define REG_I2S_TX_PAGE1_OWN 0x024 +#define REG_I2S_TX_PAGE2_OWN 0x028 +#define REG_I2S_TX_PAGE3_OWN 0x02C +#define REG_I2S_RX_PAGE0_OWN 0x030 +#define REG_I2S_RX_PAGE1_OWN 0x034 +#define REG_I2S_RX_PAGE2_OWN 0x038 +#define REG_I2S_RX_PAGE3_OWN 0x03C +*/ +/* template +#define BIT_SHIFT_CTLX_ 7 +#define BIT_MASK_CTLX_ 0x1 +#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_) +#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_)) +*//* +#define BIT_SHIFT_CTLX_IIS_EN 0 +#define BIT_MASK_CTLX_IIS_EN 0x1 +#define BIT_CTLX_IIS_EN(x) (((x) & BIT_MASK_CTLX_IIS_EN) << BIT_SHIFT_CTLX_IIS_EN) +#define BIT_INV_CTLX_IIS_EN (~(BIT_MASK_CTLX_IIS_EN << BIT_SHIFT_CTLX_IIS_EN)) + +#define BIT_SHIFT_CTLX_TRX 1 +#define BIT_MASK_CTLX_TRX 0x3 +#define BIT_CTLX_TRX(x) (((x) & BIT_MASK_CTLX_TRX) << BIT_SHIFT_CTLX_TRX) +#define BIT_INV_CTLX_TRX (~(BIT_MASK_CTLX_TRX << BIT_SHIFT_CTLX_TRX)) + +#define BIT_SHIFT_CTLX_CH_NUM 3 +#define BIT_MASK_CTLX_CH_NUM 0x3 +#define BIT_CTLX_CH_NUM(x) (((x) & BIT_MASK_CTLX_CH_NUM) << BIT_SHIFT_CTLX_CH_NUM) +#define BIT_INV_CTLX_CH_NUM (~(BIT_MASK_CTLX_CH_NUM << BIT_SHIFT_CTLX_CH_NUM)) + +#define BIT_SHIFT_CTLX_EDGE_SW 5 +#define BIT_MASK_CTLX_EDGE_SW 0x1 +#define BIT_CTLX_EDGE_SW(x) (((x) & BIT_MASK_CTLX_EDGE_SW) << BIT_SHIFT_CTLX_EDGE_SW) +#define BIT_INV_CTLX_EDGE_SW (~(BIT_MASK_CTLX_EDGE_SW << BIT_SHIFT_CTLX_EDGE_SW)) + +#define BIT_SHIFT_CTLX_WL 6 +#define BIT_MASK_CTLX_WL 0x1 +#define BIT_CTLX_WL(x) (((x) & BIT_MASK_CTLX_WL) << BIT_SHIFT_CTLX_WL) +#define BIT_INV_CTLX_WL (~(BIT_MASK_CTLX_WL << BIT_SHIFT_CTLX_WL)) + +#define BIT_SHIFT_CTLX_LOOP_BACK 7 +#define BIT_MASK_CTLX_LOOP_BACK 0x1 +#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK) +#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK)) + + +#define BIT_SHIFT_CTLX_FORMAT 8 +#define BIT_MASK_CTLX_FORMAT 0x3 +#define BIT_CTLX_FORMAT(x) (((x) & BIT_MASK_CTLX_FORMAT) << BIT_SHIFT_CTLX_FORMAT) +#define BIT_INV_CTLX_FORMAT (~(BIT_MASK_CTLX_FORMAT << BIT_SHIFT_CTLX_FORMAT)) + +#define BIT_SHIFT_CTLX_LRSWAP 10 +#define BIT_MASK_CTLX_LRSWAP 0x1 +#define BIT_CTLX_LRSWAP(x) (((x) & BIT_MASK_CTLX_LRSWAP) << BIT_SHIFT_CTLX_LRSWAP) +#define BIT_INV_CTLX_LRSWAP (~(BIT_MASK_CTLX_LRSWAP << BIT_SHIFT_CTLX_LRSWAP)) + +#define BIT_SHIFT_CTLX_SCK_INV 11 +#define BIT_MASK_CTLX_SCK_INV 0x1 +#define BIT_CTLX_SCK_INV(x) (((x) & BIT_MASK_CTLX_SCK_INV) << BIT_SHIFT_CTLX_SCK_INV) +#define BIT_INV_CTLX_SCK_INV (~(BIT_MASK_CTLX_SCK_INV << BIT_SHIFT_CTLX_SCK_INV)) + +#define BIT_SHIFT_CTLX_ENDIAN_SWAP 12 +#define BIT_MASK_CTLX_ENDIAN_SWAP 0x1 +#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP) +#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP)) + + +#define BIT_SHIFT_CTLX_DEBUG_SWITCH 15 +#define BIT_MASK_CTLX_DEBUG_SWITCH 0x3 +#define BIT_CTLX_DEBUG_SWITCH(x) (((x) & BIT_MASK_CTLX_DEBUG_SWITCH) << BIT_SHIFT_CTLX_DEBUG_SWITCH) +#define BIT_INV_CTLX_DEBUG_SWITCH (~(BIT_MASK_CTLX_DEBUG_SWITCH << BIT_SHIFT_CTLX_DEBUG_SWITCH)) + +#define BIT_SHIFT_CTLX_SLAVE_SEL 29 +#define BIT_MASK_CTLX_SLAVE_SEL 0x1 +#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL) +#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL)) + + +#define BIT_SHIFT_CTLX_CLK_SRC 30 +#define BIT_MASK_CTLX_CLK_SRC 0x1 +#define BIT_CTLX_CLK_SRC(x) (((x) & BIT_MASK_CTLX_CLK_SRC) << BIT_SHIFT_CTLX_CLK_SRC) +#define BIT_INV_CTLX_CLK_SRC (~(BIT_MASK_CTLX_CLK_SRC << BIT_SHIFT_CTLX_CLK_SRC)) + + + +#define BIT_SHIFT_CTLX_SW_RSTN 31 +#define BIT_MASK_CTLX_SW_RSTN 0x1 +#define BIT_CTLX_SW_RSTN(x) (((x) & BIT_MASK_CTLX_SW_RSTN) << BIT_SHIFT_CTLX_SW_RSTN) +#define BIT_INV_CTLX_SW_RSTN (~(BIT_MASK_CTLX_SW_RSTN << BIT_SHIFT_CTLX_SW_RSTN)) + + +#define BIT_SHIFT_SETTING_PAGE_SZ 0 +#define BIT_MASK_SETTING_PAGE_SZ 0xFFF +#define BIT_SETTING_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_PAGE_SZ) << BIT_SHIFT_SETTING_PAGE_SZ) +#define BIT_INV_SETTING_PAGE_SZ (~(BIT_MASK_SETTING_PAGE_SZ << BIT_SHIFT_SETTING_PAGE_SZ)) + +#define BIT_SHIFT_SETTING_PAGE_NUM 12 +#define BIT_MASK_SETTING_PAGE_NUM 0x3 +#define BIT_SETTING_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_PAGE_NUM) << BIT_SHIFT_SETTING_PAGE_NUM) +#define BIT_INV_SETTING_PAGE_NUM (~(BIT_MASK_SETTING_PAGE_NUM << BIT_SHIFT_SETTING_PAGE_NUM)) + +#define BIT_SHIFT_SETTING_SAMPLE_RATE 14 +#define BIT_MASK_SETTING_SAMPLE_RATE 0x7 +#define BIT_SETTING_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_SAMPLE_RATE) << BIT_SHIFT_SETTING_SAMPLE_RATE) +#define BIT_INV_SETTING_SAMPLE_RATE (~(BIT_MASK_SETTING_SAMPLE_RATE << BIT_SHIFT_SETTING_SAMPLE_RATE)) +*/ + +typedef enum _I2S_CTL_FORMAT { + FormatI2s = 0x00, + FormatLeftJustified = 0x01, + FormatRightJustified = 0x02 +}I2S_CTL_FORMAT, *PI2S_CTL_FORMAT; + +typedef enum _I2S_CTL_CHNUM { + ChannelStereo = 0x00, + Channel5p1 = 0x01, + ChannelMono = 0x02 +}I2S_CTL_CHNUM, *PI2S_CTL_CHNUM; + +typedef enum _I2S_CTL_TRX_ACT { + RxOnly = 0x00, + TxOnly = 0x01, + TXRX = 0x02 +}I2S_CTL_TRX_ACT, *PI2S_CTL_TRX_ACT; +/* +typedef struct _I2S_CTL_REG_ { + I2S_CTL_FORMAT Format; + I2S_CTL_CHNUM ChNum; + I2S_CTL_TRX_ACT TrxAct; + + u32 I2s_En :1; // Bit 0 + u32 Rsvd1to4 :4; // Bit 1-4 is TrxAct, ChNum + u32 EdgeSw :1; // Bit 5 Edge switch + u32 WordLength :1; // Bit 6 + u32 LoopBack :1; // Bit 7 + u32 Rsvd8to9 :2; // Bit 8-9 is Format + u32 DacLrSwap :1; // Bit 10 + u32 SckInv :1; // Bit 11 + u32 EndianSwap :1; // Bit 12 + u32 Rsvd13to14 :2; // Bit 11-14 + u32 DebugSwitch :2; // Bit 15-16 + u32 Rsvd17to28 :12; // Bit 17-28 + u32 SlaveMode :1; // Bit 29 + u32 SR44p1KHz :1; // Bit 30 + u32 SwRstn :1; // Bit 31 +} I2S_CTL_REG, *PI2S_CTL_REG; +*/ +typedef enum _I2S_SETTING_PAGE_NUM { + I2s1Page = 0x00, + I2s2Page = 0x01, + I2s3Page = 0x02, + I2s4Page = 0x03 +}I2S_SETTING_PAGE_NUM, *PI2S_SETTING_PAGE_NUM; + +//sampling rate +typedef enum _I2S_SETTING_SR { + I2sSR8K = 0x00, + I2sSR16K = 0x01, + I2sSR24K = 0x02, + I2sSR32K = 0x03, + I2sSR48K = 0x05, + I2sSR44p1K = 0x15, + I2sSR96K = 0x06, + I2sSR88p2K = 0x16 +}I2S_SETTING_SR, *PI2S_SETTING_SR; +/* +typedef struct _I2S_SETTING_REG_ { + I2S_SETTING_PAGE_NUM PageNum; + I2S_SETTING_SR SampleRate; + + u32 PageSize:12; // Bit 0-11 +}I2S_SETTING_REG, *PI2S_SETTING_REG; + +typedef enum _I2S_TX_ISR { + I2sTxP0OK = 0x01, + I2sTxP1OK = 0x02, + I2sTxP2OK = 0x04, + I2sTxP3OK = 0x08, + I2sTxPageUn = 0x10, + I2sTxFifoEmpty = 0x20 +}I2S_TX_ISR, *PI2S_TX_ISR; + +typedef enum _I2S_RX_ISR { + I2sRxP0OK = 0x01, + I2sRxP1OK = 0x02, + I2sRxP2OK = 0x04, + I2sRxP3OK = 0x08, + I2sRxPageUn = 0x10, + I2sRxFifoFull = 0x20 +}I2S_RX_ISR, *PI2S_RX_ISR; +*/ + +/* Hal I2S function prototype*/ +RTK_STATUS +HalI2SInitRtl8195a( + IN VOID *Data +); + +RTK_STATUS +HalI2SInitRtl8195a_Patch( + IN VOID *Data +); + +RTK_STATUS +HalI2SDeInitRtl8195a( + IN VOID *Data +); + +RTK_STATUS +HalI2STxRtl8195a( + IN VOID *Data, + IN u8 *pBuff +); + +RTK_STATUS +HalI2SRxRtl8195a( + IN VOID *Data, + OUT u8 *pBuff +); + +RTK_STATUS +HalI2SEnableRtl8195a( + IN VOID *Data +); + +RTK_STATUS +HalI2SIntrCtrlRtl8195a( + IN VOID *Data +); + +u32 +HalI2SReadRegRtl8195a( + IN VOID *Data, + IN u8 I2SReg +); + +RTK_STATUS +HalI2SSetRateRtl8195a( + IN VOID *Data +); + +RTK_STATUS +HalI2SSetWordLenRtl8195a( + IN VOID *Data +); + +RTK_STATUS +HalI2SSetChNumRtl8195a( + IN VOID *Data +); + +RTK_STATUS +HalI2SSetPageNumRtl8195a( + IN VOID *Data +); + +RTK_STATUS +HalI2SSetPageSizeRtl8195a( + IN VOID *Data +); + +RTK_STATUS +HalI2SSetDirectionRtl8195a( + IN VOID *Data +); + +RTK_STATUS +HalI2SSetDMABufRtl8195a( + IN VOID *Data +); + +RTK_STATUS +HalI2SClrIntrRtl8195a( + IN VOID *Data +); + +RTK_STATUS +HalI2SClrAllIntrRtl8195a( + IN VOID *Data +); + +RTK_STATUS +HalI2SDMACtrlRtl8195a( + IN VOID *Data +); + +u8 +HalI2SGetTxPageRtl8195a( + IN VOID *Data +); + +u8 +HalI2SGetRxPageRtl8195a( + IN VOID *Data +); + +RTK_STATUS +HalI2SPageSendRtl8195a( + IN VOID *Data, + IN u8 PageIdx +); + +#if 0 +RTK_STATUS +HalI2SPageRecvRtl8195a( + IN VOID *Data, + IN u8 PageIdx +); +#else +RTK_STATUS +HalI2SPageRecvRtl8195a( + IN VOID *Data +); +#endif + +RTK_STATUS +HalI2SClearAllOwnBitRtl8195a( + IN VOID *Data +); + + +// HAL functions Wrapper +static __inline VOID +HalI2SSetRate( + IN VOID *Data +) +{ + HalI2SSetRateRtl8195a(Data); +} + +static __inline VOID +HalI2SSetWordLen( + IN VOID *Data +) +{ + HalI2SSetWordLenRtl8195a(Data); +} + +static __inline VOID +HalI2SSetChNum( + IN VOID *Data +) +{ + HalI2SSetChNumRtl8195a(Data); +} + +static __inline VOID +HalI2SSetPageNum( + IN VOID *Data +) +{ + HalI2SSetPageNumRtl8195a(Data); +} + +static __inline VOID +HalI2SSetPageSize( + IN VOID *Data +) +{ + HalI2SSetPageSizeRtl8195a(Data); +} + +static __inline VOID +HalI2SSetDirection( + IN VOID *Data +) +{ + HalI2SSetDirectionRtl8195a(Data); +} + +static __inline VOID +HalI2SSetDMABuf( + IN VOID *Data +) +{ + HalI2SSetDMABufRtl8195a(Data); +} + +static __inline u8 +HalI2SGetTxPage( + IN VOID *Data +) +{ + return HalI2SGetTxPageRtl8195a(Data); +} + +static __inline u8 +HalI2SGetRxPage( + IN VOID *Data +) +{ + return HalI2SGetRxPageRtl8195a(Data); +} + +static __inline VOID +HalI2SPageSend( + IN VOID *Data, + IN u8 PageIdx +) +{ + HalI2SPageSendRtl8195a(Data, PageIdx); +} + +#if 0 +static __inline VOID +HalI2SPageRecv( + IN VOID *Data, + IN u8 PageIdx +) +{ + HalI2SPageRecvRtl8195a(Data, PageIdx); +} +#else +static __inline VOID +HalI2SPageRecv( + IN VOID *Data +) +{ + HalI2SPageRecvRtl8195a(Data); +} +#endif + +static __inline VOID +HalI2SClearAllOwnBit( + IN VOID *Data +) +{ + HalI2SClearAllOwnBitRtl8195a(Data); +} + +#endif /* _RTL8195A_I2S_H_ */ + + diff --git a/lib/fwlib/rtl8195a/rtl8195a_mii.h b/lib/fwlib/rtl8195a/rtl8195a_mii.h new file mode 100644 index 0000000..56ebbdc --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_mii.h @@ -0,0 +1,674 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _RTL8195A_MII_H_ +#define _RTL8195A_MII_H_ + +#include "basic_types.h" +#include "hal_api.h" + + +#define ETHERNET_REG_BASE 0x40050000 +#define ETHERNET_MODULE_BASE ETHERNET_REG_BASE + 0x0000 +#define CPU_INTERFACE_BASE ETHERNET_REG_BASE + 0x1300 + +/* Ethernet Module registers */ +#define REG_RTL_MII_IDR0 0x0000 // Table 2 IDR0 (Offset 0000h-0003h, R/W) +#define REG_RTL_MII_IDR4 0x0004 // Table 3 IDR4 (Offset 0004h-0007h, R/W) +#define REG_RTL_MII_MAR0 0x0008 // Table 4 MAR0 (Offset 0008h-000bh, R/W) +#define REG_RTL_MII_MAR4 0x000C // Table 5 MAR4 (Offset 000ch-000fh, R/W) +#define REG_RTL_MII_CR 0x0038 // Table 21 Command Register (COM_REG, Offset 0038-003Bh, R/W) +#define REG_RTL_MII_IMRISR 0x003C // Table 22 + Table 23 +#define REG_RTL_MII_TCR 0x0040 // Table 24 Transmit Configuration Register (TC_REG, Offset 0040h-0043h, R/W) +#define REG_RTL_MII_RCR 0x0044 // Table 25 Receive Configuration Register (RC_REG, Offset 0044h-0047h, R/W) +#define REG_RTL_MII_CTCR 0x0048 // Table 26 CPU Tag Control Register (CPUTAG_REG, Offset 0048h-004bh, R/W) +#define REG_RTL_MII_CONFIG 0x004C // Table 27 Configuration Register (CONFIG_REG, Offset 004ch-004fh, R/W) +#define REG_RTL_MII_CTCR1 0x0050 // Table 28 CPUTAG1 Register (CPUTAG1_REG, Offset 0050h-0053h, R/W) +#define REG_RTL_MII_MSR 0x0058 // Table 29 Media Status Register (MS_reg: Offset 0058h – 005bh, R/W) +#define REG_RTL_MII_MIIAR 0x005C // Table 30 MII Access Register (MIIA_REG, Offset 005c-005fh, R/W) +#define REG_RTL_MII_VR 0x0064 // Table 32 VLAN Register (VLAN_REG, Offset 0064-0067h, R/W) +#define REG_RTL_MII_IMR0 0x00D0 // Table 50 IMR0_REG (IMR0_REG, Offset D0h-D3h) +#define REG_RTL_MII_IMR1 0x00D4 // Table 51 IMR1_REG (IMR1_REG, Offset d4h-d7h) +#define REG_RTL_MII_ISR1 0x00D8 // Table 52 ISR1 Register (ISR1_REG, Offset D8h-DBh) +#define REG_RTL_MII_INTR 0x00DC // Table 53 Interrupt routing register (INTR_REG, Offset DCh-DFh) +#define REG_RTL_MII_CCR 0x00E4 // Table xx Clock Control Register (CLKCTL_REG, Offset E4h-E7h) + +/* CPU Interface registers */ +#define REG_RTL_MII_TXFDP1 0x1300 // Table 55 TxFDP1 register (TXFDP1_REG, offset 1300h-1303h) +#define REG_RTL_MII_TXCDO1 0x1304 // Table 56 TxCDO1 register (TXCDO1_REG, offset 1304h-1305h) +#define REG_RTL_MII_TXFDP2 0x1310 // Table 57 TxFDP2 register (TXFDP2_REG, offset 1310h-1313h) +#define REG_RTL_MII_TXCDO2 0x1314 // Table 58 TxCDO2 register (TXCDO2_REG, offset 1314h-1315h) +#define REG_RTL_MII_TXFDP3 0x1320 // Table 59 TxFDP3 register (TXFDP3_REG, offset 1320h-1323h) +#define REG_RTL_MII_TXCDO3 0x1324 // Table 60 TxCDO3 register (TXCDO3_REG, offset 1324h-1325h) +#define REG_RTL_MII_TXFDP4 0x1330 // Table 61 TxFDP4 register (TXFDP4_REG, offset 1330h-1333h) +#define REG_RTL_MII_TXCDO4 0x1334 // Table 62 TxCDO4 register (TXCDO4_REG, offset 1334h-1335h) +#define REG_RTL_MII_TXFDP5 0x1340 // Table 63 TxFDP5 register (TXFDP5_REG, offset 1340h-1343h) +#define REG_RTL_MII_TXCDO5 0x1344 // Table 64 TxCDO5 register (TXCDO5_REG, offset 1344h-1345h) +#define REG_RTL_MII_RXFDP2 0x1390 // Table 66 RxFDP2 register (RXFDP#_REG, offset 1390h-1393h) +#define REG_RTL_MII_RXFDP1 0x13F0 // Table 71 RxFDP1 register (RXFDP1_REG, offset 13F0h-13F3h) +#define REG_RTL_MII_RXRS1 0x13F6 // Table 73 Rx Ring Size1 register (RX_RS1_REG, offset 13F6h-13F7h) + +#define REG_RTL_MII_RX_PSE1 0x142C // Table 77 Rx_Pse_Des_Thres_1_h (RX_PSE1_REG, Offset 142ch) +#define REG_RTL_MII_ETNRXCPU1 0x1430 // Table 79 EhtrntRxCPU_Des_Num1 (ETNRXCPU1_REG, Offset 1430h-1433h) +#define REG_RTL_MII_IOCMD 0x1434 // Table 80 Ethernet_IO_CMD (ETN_IO_CMD_REG, Offset 1434h-1437h) +#define REG_RTL_MII_IOCMD1 0x1438 // Table 81 Ethernet_IO_CMD1 (IO_CMD1_REG: Offset 1438h-143bh) + + +#define HAL_MII_READ32(addr) \ + HAL_READ32(ETHERNET_REG_BASE, addr) +#define HAL_MII_WRITE32(addr, value) \ + HAL_WRITE32(ETHERNET_REG_BASE, addr, value) +#define HAL_MII_READ16(addr) \ + HAL_READ16(ETHERNET_REG_BASE, addr) +#define HAL_MII_WRITE16(addr, value) \ + HAL_WRITE16(ETHERNET_REG_BASE, addr, value) +#define HAL_MII_READ8(addr) \ + HAL_READ8(ETHERNET_REG_BASE, addr) +#define HAL_MII_WRITE8(addr, value) \ + HAL_WRITE8(ETHERNET_REG_BASE, addr, value) + +#define CMD_CONFIG 0x00081000 + +//2014-04-29 yclin (disable [27] r_en_precise_dma) +// #define CMD1_CONFIG 0x39000000 +#define CMD1_CONFIG 0x31000000 + +// #define MAX_RX_DESC_SIZE 6 +#define MAX_RX_DESC_SIZE 1 +#define MAX_TX_DESC_SIZE 5 + +// 0058h +#define BIT_SHIFT_MSR_FORCE_SPEED_SELECT 16 +#define BIT_MASK_MSR_FORCE_SPEED_SELECT 0x3 +#define BIT_MSR_FORCE_SPEED_SELECT(x)(((x) & BIT_MASK_MSR_FORCE_SPEED_SELECT) << BIT_SHIFT_MSR_FORCE_SPEED_SELECT) +#define BIT_INVC_MSR_FORCE_SPEED_SELECT (~(BIT_MASK_MSR_FORCE_SPEED_SELECT << BIT_SHIFT_MSR_FORCE_SPEED_SELECT)) + +#define BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE 10 +#define BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE 0x1 +#define BIT_MSR_FORCE_SPEED_MODE_ENABLE(x)(((x) & BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE) << BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE) +#define BIT_INVC_MSR_FORCE_SPEED_MODE_ENABLE (~(BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE << BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE)) + +// 1434h +#define BIT_SHIFT_IOCMD_RXENABLE 5 +#define BIT_MASK_IOCMD_RXENABLE 0x1 +#define BIT_IOCMD_RXENABLE(x)(((x) & BIT_MASK_IOCMD_RXENABLE) << BIT_SHIFT_IOCMD_RXENABLE) +#define BIT_INVC_IOCMD_RXENABLE (~(BIT_MASK_IOCMD_RXENABLE << BIT_SHIFT_IOCMD_RXENABLE)) + +#define BIT_SHIFT_IOCMD_TXENABLE 4 +#define BIT_MASK_IOCMD_TXENABLE 0x1 +#define BIT_IOCMD_TXENABLE(x)(((x) & BIT_MASK_IOCMD_TXENABLE) << BIT_SHIFT_IOCMD_TXENABLE) +#define BIT_INVC_IOCMD_TXENABLE (~(BIT_MASK_IOCMD_TXENABLE << BIT_SHIFT_IOCMD_TXENABLE)) + +#define BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE 0 +#define BIT_MASK_IOCMD_FIRST_DMATX_ENABLE 0x1 +#define BIT_IOCMD_FIRST_DMATX_ENABLE(x)(((x) & BIT_MASK_IOCMD_FIRST_DMATX_ENABLE) << BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE) +#define BIT_INVC_IOCMD_FIRST_DMATX_ENABLE (~(BIT_MASK_IOCMD_FIRST_DMATX_ENABLE << BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE)) + +// 1438h +#define BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE 16 +#define BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE 0x1 +#define BIT_IOCMD1_FIRST_DMARX_ENABLE(x)(((x) & BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE) << BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE) +#define BIT_INVC_IOCMD1_FIRST_DMARX_ENABLE (~(BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE << BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE)) + + +/** + * 1.4.1.7 Tx command descriptor used in RL6266 + * 5 dobule words + */ +typedef struct _TX_INFO_ { + union { + struct { + u32 own:1; //31 + u32 eor:1; //30 + u32 fs:1; //29 + u32 ls:1; //28 + u32 ipcs:1; //27 + u32 l4cs:1; //26 + u32 keep:1; //25 + u32 blu:1; //24 + u32 crc:1; //23 + u32 vsel:1; //22 + u32 dislrn:1; //21 + u32 cputag_ipcs:1; //20 + u32 cputag_l4cs:1; //19 + u32 cputag_psel:1; //18 + u32 rsvd:1; //17 + u32 data_length:17; //0~16 + } bit; + u32 dw; //double word + } opts1; + + u32 addr; + + union { + struct { + u32 cputag:1; //31 + u32 aspri:1; //30 + u32 cputag_pri:3; //27~29 + u32 tx_vlan_action:2; //25~26 + u32 tx_pppoe_action:2; //23~24 + u32 tx_pppoe_idx:3; //20~22 + u32 efid:1; //19 + u32 enhance_fid:3; //16~18 + u32 vidl:8; // 8~15 + u32 prio:3; // 5~7 + u32 cfi:1; // 4 + u32 vidh:4; // 0~3 + } bit; + u32 dw; //double word + } opts2; + + union { + struct { + u32 extspa:3; //29~31 + u32 tx_portmask:6; //23~28 + u32 tx_dst_stream_id:7; //16~22 + u32 rsvd:14; // 2~15 + u32 l34keep:1; // 1 + u32 ptp:1; // 0 + } bit; + u32 dw; //double word + } opts3; + + union { + struct { + u32 lgsen:1; //31 + u32 lgmss:11; //20~30 + u32 rsvd:20; // 0~19 + } bit; + u32 dw; //double word + } opts4; + +} TX_INFO, *PTX_INFO; + +typedef struct _RX_INFO_ { + union{ + struct{ + u32 own:1; //31 + u32 eor:1; //30 + u32 fs:1; //29 + u32 ls:1; //28 + u32 crcerr:1; //27 + u32 ipv4csf:1; //26 + u32 l4csf:1; //25 + u32 rcdf:1; //24 + u32 ipfrag:1; //23 + u32 pppoetag:1; //22 + u32 rwt:1; //21 + u32 pkttype:4; //20-17 + u32 l3routing:1; //16 + u32 origformat:1; //15 + u32 pctrl:1; //14 +#ifdef CONFIG_RG_JUMBO_FRAME + u32 data_length:14; //13~0 +#else + u32 rsvd:2; //13~12 + u32 data_length:12; //11~0 +#endif + }bit; + u32 dw; //double word + }opts1; + + u32 addr; + + union{ + struct{ + u32 cputag:1; //31 + u32 ptp_in_cpu_tag_exist:1; //30 + u32 svlan_tag_exist:1; //29 + u32 rsvd_2:2; //27~28 + u32 pon_stream_id:7; //20~26 + u32 rsvd_1:3; //17~19 + u32 ctagva:1; //16 + u32 cvlan_tag:16; //15~0 + }bit; + u32 dw; //double word + }opts2; + + union{ + struct{ + u32 src_port_num:5; //27~31 + u32 dst_port_mask:6; //21~26 + u32 reason:8; //13~20 + u32 internal_priority:3; //10~12 + u32 ext_port_ttl_1:5; //5~9 + u32 rsvd:5; //4~0 + }bit; + u32 dw; //double word + }opts3; +} RX_INFO, *PRX_INFO; + +/** + * GMAC_STATUS_REGS + */ +// TX/RX Descriptor Common +#define BIT_SHIFT_GMAC_DESCOWN 31 +#define BIT_MASK_GMAC_DESCOWN 0x1 +#define BIT_GMAC_DESCOWN(x)(((x) & BIT_MASK_GMAC_DESCOWN) << BIT_SHIFT_GMAC_DESCOWN) +#define BIT_INVC_GMAC_DESCOWN (~(BIT_MASK_GMAC_DESCOWN << BIT_SHIFT_GMAC_DESCOWN)) + +#define BIT_SHIFT_GMAC_RINGEND 30 +#define BIT_MASK_GMAC_RINGEND 0x1 +#define BIT_GMAC_RINGEND(x)(((x) & BIT_MASK_GMAC_RINGEND) << BIT_SHIFT_GMAC_RINGEND) +#define BIT_INVC_GMAC_RINGEND (~(BIT_MASK_GMAC_RINGEND << BIT_SHIFT_GMAC_RINGEND)) + +#define BIT_SHIFT_GMAC_FIRSTFRAG 29 +#define BIT_MASK_GMAC_FIRSTFRAG 0x1 +#define BIT_GMAC_FIRSTFRAG(x)(((x) & BIT_MASK_GMAC_FIRSTFRAG) << BIT_SHIFT_GMAC_FIRSTFRAG) +#define BIT_INVC_GMAC_FIRSTFRAG (~(BIT_MASK_GMAC_FIRSTFRAG << BIT_SHIFT_GMAC_FIRSTFRAG)) + +#define BIT_SHIFT_GMAC_LASTFRAG 28 +#define BIT_MASK_GMAC_LASTFRAG 0x1 +#define BIT_GMAC_LASTFRAG(x)(((x) & BIT_MASK_GMAC_LASTFRAG) << BIT_SHIFT_GMAC_LASTFRAG) +#define BIT_INVC_GMAC_LASTFRAG (~(BIT_MASK_GMAC_LASTFRAG << BIT_SHIFT_GMAC_LASTFRAG)) + +// TX Descriptor opts1 +#define BIT_SHIFT_GMAC_IPCS 27 +#define BIT_MASK_GMAC_IPCS 0x1 +#define BIT_GMAC_IPCS(x)(((x) & BIT_MASK_GMAC_IPCS) << BIT_SHIFT_GMAC_IPCS) +#define BIT_INVC_GMAC_IPCS (~(BIT_MASK_GMAC_IPCS << BIT_SHIFT_GMAC_IPCS)) + +#define BIT_SHIFT_GMAC_L4CS 26 +#define BIT_MASK_GMAC_L4CS 0x1 +#define BIT_GMAC_L4CS(x)(((x) & BIT_MASK_GMAC_L4CS) << BIT_SHIFT_GMAC_L4CS) +#define BIT_INVC_GMAC_L4CS (~(BIT_MASK_GMAC_L4CS << BIT_SHIFT_GMAC_L4CS)) + +#define BIT_SHIFT_GMAC_KEEP 25 +#define BIT_MASK_GMAC_KEEP 0x1 +#define BIT_GMAC_KEEP(x)(((x) & BIT_MASK_GMAC_KEEP) << BIT_SHIFT_GMAC_KEEP) +#define BIT_INVC_GMAC_KEEP (~(BIT_MASK_GMAC_KEEP << BIT_SHIFT_GMAC_KEEP)) + +#define BIT_SHIFT_GMAC_BLU 24 +#define BIT_MASK_GMAC_BLU 0x1 +#define BIT_GMAC_BLU(x)(((x) & BIT_MASK_GMAC_BLU) << BIT_SHIFT_GMAC_BLU) +#define BIT_INVC_GMAC_BLU (~(BIT_MASK_GMAC_BLU << BIT_SHIFT_GMAC_BLU)) + +#define BIT_SHIFT_GMAC_TXCRC 23 +#define BIT_MASK_GMAC_TXCRC 0x1 +#define BIT_GMAC_TXCRC(x)(((x) & BIT_MASK_GMAC_TXCRC) << BIT_SHIFT_GMAC_TXCRC) +#define BIT_INVC_GMAC_TXCRC (~(BIT_MASK_GMAC_TXCRC << BIT_SHIFT_GMAC_TXCRC)) + +#define BIT_SHIFT_GMAC_VSEL 22 +#define BIT_MASK_GMAC_VSEL 0x1 +#define BIT_GMAC_VSEL(x)(((x) & BIT_MASK_GMAC_VSEL) << BIT_SHIFT_GMAC_VSEL) +#define BIT_INVC_GMAC_VSEL (~(BIT_MASK_GMAC_VSEL << BIT_SHIFT_GMAC_VSEL)) + +#define BIT_SHIFT_GMAC_DISLRN 21 +#define BIT_MASK_GMAC_DISLRN 0x1 +#define BIT_GMAC_DISLRN(x)(((x) & BIT_MASK_GMAC_DISLRN) << BIT_SHIFT_GMAC_DISLRN) +#define BIT_INVC_GMAC_DISLRN (~(BIT_MASK_GMAC_DISLRN << BIT_SHIFT_GMAC_DISLRN)) + +#define BIT_SHIFT_GMAC_CPUTAG_IPCS 20 +#define BIT_MASK_GMAC_CPUTAG_IPCS 0x1 +#define BIT_GMAC_CPUTAG_IPCS(x)(((x) & BIT_MASK_GMAC_CPUTAG_IPCS) << BIT_SHIFT_GMAC_CPUTAG_IPCS) +#define BIT_INVC_GMAC_CPUTAG_IPCS (~(BIT_MASK_GMAC_CPUTAG_IPCS << BIT_SHIFT_GMAC_CPUTAG_IPCS)) + +#define BIT_SHIFT_GMAC_CPUTAG_L4CS 19 +#define BIT_MASK_GMAC_CPUTAG_L4CS 0x1 +#define BIT_GMAC_CPUTAG_L4CS(x)(((x) & BIT_MASK_GMAC_CPUTAG_L4CS) << BIT_SHIFT_GMAC_CPUTAG_L4CS) +#define BIT_INVC_GMAC_CPUTAG_L4CS (~(BIT_MASK_GMAC_CPUTAG_L4CS << BIT_SHIFT_GMAC_CPUTAG_L4CS)) + +#define BIT_SHIFT_GMAC_CPUTAG_PSEL 18 +#define BIT_MASK_GMAC_CPUTAG_PSEL 0x1 +#define BIT_GMAC_CPUTAG_PSEL(x)(((x) & BIT_MASK_GMAC_CPUTAG_PSEL) << BIT_SHIFT_GMAC_CPUTAG_PSEL) +#define BIT_INVC_GMAC_CPUTAG_PSEL (~(BIT_MASK_GMAC_CPUTAG_PSEL << BIT_SHIFT_GMAC_CPUTAG_PSEL)) + + +#if 0 +enum RE8670_STATUS_REGS +{ + /*TX/RX share */ + DescOwn = (1 << 31), /* Descriptor is owned by NIC */ + RingEnd = (1 << 30), /* End of descriptor ring */ + FirstFrag = (1 << 29), /* First segment of a packet */ + LastFrag = (1 << 28), /* Final segment of a packet */ + + /*Tx descriptor opt1*/ + IPCS = (1 << 27), + L4CS = (1 << 26), + KEEP = (1 << 25), + BLU = (1 << 24), + TxCRC = (1 << 23), + VSEL = (1 << 22), + DisLrn = (1 << 21), + CPUTag_ipcs = (1 << 20), + CPUTag_l4cs = (1 << 19), + + /*Tx descriptor opt2*/ + CPUTag = (1 << 31), + aspri = (1 << 30), + CPRI = (1 << 27), + TxVLAN_int = (0 << 25), //intact + TxVLAN_ins = (1 << 25), //insert + TxVLAN_rm = (2 << 25), //remove + TxVLAN_re = (3 << 25), //remark + //TxPPPoEAct = (1 << 23), + TxPPPoEAct = 23, + //TxPPPoEIdx = (1 << 20), + TxPPPoEIdx = 20, + Efid = (1 << 19), + //Enhan_Fid = (1 << 16), + Enhan_Fid = 16, + /*Tx descriptor opt3*/ + SrcExtPort = 29, + TxDesPortM = 23, + TxDesStrID = 16, + TxDesVCM = 0, + /*Tx descriptor opt4*/ + /*Rx descriptor opt1*/ + CRCErr = (1 << 27), + IPV4CSF = (1 << 26), + L4CSF = (1 << 25), + RCDF = (1 << 24), + IP_FRAG = (1 << 23), + PPPoE_tag = (1 << 22), + RWT = (1 << 21), + PktType = (1 << 17), + RxProtoIP = 1, + RxProtoPPTP = 2, + RxProtoICMP = 3, + RxProtoIGMP = 4, + RxProtoTCP = 5, + RxProtoUDP = 6, + RxProtoIPv6 = 7, + RxProtoICMPv6 = 8, + RxProtoTCPv6 = 9, + RxProtoUDPv6 = 10, + L3route = (1 << 16), + OrigFormat = (1 << 15), + PCTRL = (1 << 14), + /*Rx descriptor opt2*/ + PTPinCPU = (1 << 30), + SVlanTag = (1 << 29), + /*Rx descriptor opt3*/ + SrcPort = (1 << 27), + DesPortM = (1 << 21), + Reason = (1 << 13), + IntPriority = (1 << 10), + ExtPortTTL = (1 << 5), +}; + +enum _DescStatusBit { + DescOwn = (1 << 31), /* Descriptor is owned by NIC */ + RingEnd = (1 << 30), /* End of descriptor ring */ + FirstFrag = (1 << 29), /* First segment of a packet */ + LastFrag = (1 << 28), /* Final segment of a packet */ + + /* Tx private */ + LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ + MSSShift = 16, /* MSS value position */ + MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ + IPCS = (1 << 18), /* Calculate IP checksum */ + UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ + TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ + TxVlanTag = (1 << 17), /* Add VLAN tag */ + + /* Rx private */ + PID1 = (1 << 18), /* Protocol ID bit 1/2 */ + PID0 = (1 << 17), /* Protocol ID bit 2/2 */ + +#define RxProtoUDP (PID1) +#define RxProtoTCP (PID0) +#define RxProtoIP (PID1 | PID0) +#define RxProtoMask RxProtoIP + + IPFail = (1 << 16), /* IP checksum failed */ + UDPFail = (1 << 15), /* UDP/IP checksum failed */ + TCPFail = (1 << 14), /* TCP/IP checksum failed */ + RxVlanTag = (1 << 16), /* VLAN tag available */ +}; +#endif + +typedef struct _PHY_MODE_INFO_ { + u8 PhyAddress; + u8 PhyMode; + u8 PhyInterface; +} PHY_MODE_INFO, *PPHY_MODE_INFO; + +typedef enum _PHY_MODE_SWITCH_ { + PHY_MODE_DISABLE = 0, + PHY_MODE_ENABLE = 1 +} PHY_MODE_SWITCH, *PPHY_MODE_SWITCH; + +typedef enum _PHY_INTERFACE_SELECT_ { + PHY_INTERFACE_ONE_WORKS = 0, + PHY_INTERFACE_ZERO_WORKS = 1 +} PHY_INTERFACE_SELECT, *PPHY_INTERFACE_SELECT; + +typedef enum _GMAC_MSR_FORCE_SPEED_ { + FORCE_SPD_100M = 0, + FORCE_SPD_10M = 1, + FORCE_SPD_GIGA = 2, + NO_FORCE_SPD = 3 +}GMAC_MSR_FORCE_SPEED, *PGMAC_MSR_FORCE_SPEED; + +// typedef enum _GMAC_INTERRUPT_MASK_ { +// GMAC_IMR_ROK = BIT0, +// GMAC_IMR_CNT_WRAP = BIT1, +// GMAC_IMR_RER_RUNT = BIT2, +// // BIT3 Reserved +// GMAC_IMR_RER_OVF = BIT4, +// GMAC_IMR_RDU = BIT5, +// GMAC_IMR_TOK_TI = BIT6, +// GMAC_IMR_TER = BIT7, +// GMAC_IMR_LINKCHG = BIT8, +// GMAC_IMR_TDU = BIT9, +// GMAC_IMR_SWINT = BIT10, +// GMAC_IMR_RDU2 = BIT11, +// GMAC_IMR_RDU3 = BIT12, +// GMAC_IMR_RDU4 = BIT13, +// GMAC_IMR_RDU5 = BIT14, +// GMAC_IMR_RDU6 = BIT15, +// } GMAC_INTERRUPT_MASK, *PGMAC_INTERRUPT_MASK; + +typedef enum _GMAC_INTERRUPT_MASK_ { + GMAC_IMR_ROK = BIT16, + GMAC_IMR_CNT_WRAP = BIT17, + GMAC_IMR_RER_RUNT = BIT18, + // BIT19 Reserved + GMAC_IMR_RER_OVF = BIT20, + GMAC_IMR_RDU = BIT21, + GMAC_IMR_TOK_TI = BIT22, + GMAC_IMR_TER = BIT23, + GMAC_IMR_LINKCHG = BIT24, + GMAC_IMR_TDU = BIT25, + GMAC_IMR_SWINT = BIT26, + GMAC_IMR_RDU2 = BIT27, + GMAC_IMR_RDU3 = BIT28, + GMAC_IMR_RDU4 = BIT29, + GMAC_IMR_RDU5 = BIT30, + GMAC_IMR_RDU6 = BIT31, +} GMAC_INTERRUPT_MASK, *PGMAC_INTERRUPT_MASK; + +typedef enum _GMAC_INTERRUPT_STATUS_ { + GMAC_ISR_ROK = BIT0, + GMAC_ISR_CNT_WRAP = BIT1, + GMAC_ISR_RER_RUNT = BIT2, + // BIT3 Reserved + GMAC_ISR_RER_OVF = BIT4, + GMAC_ISR_RDU = BIT5, + GMAC_ISR_TOK_TI = BIT6, + GMAC_ISR_TER = BIT7, + GMAC_ISR_LINKCHG = BIT8, + GMAC_ISR_TDU = BIT9, + GMAC_ISR_SWINT = BIT10, + GMAC_ISR_RDU2 = BIT11, + GMAC_ISR_RDU3 = BIT12, + GMAC_ISR_RDU4 = BIT13, + GMAC_ISR_RDU5 = BIT14, + GMAC_ISR_RDU6 = BIT15, +} GMAC_INTERRUPT_STATUS, *PGMAC_INTERRUPT_STATUS; + +typedef enum _GMAC_TX_VLAN_ACTION_ { + INTACT = 0, + INSERT_VLAN_HDR = 1, + REMOVE_VLAN_HDR = 2, + REMARKING_VID = 3 +}GMAC_TX_VLAN_ACTION, *PGMAC_TX_VLAN_ACTION; + +typedef enum _GMAC_RX_PACKET_TYPE_ { + TYPE_ETHERNET = 0, + TYPE_IPV4 = 1, + TYPE_IPV4_PPTP = 2, + TYPE_IPV4_ICMP = 3, + TYPE_IPV4_IGMP = 4, + TYPE_IPV4_TCP = 5, + TYPE_IPV4_UDP = 6, + TYPE_IPV6 = 7, + TYPE_ICMPV6 = 8, + TYPE_IPV6_TCP = 9, + TYPE_IPV6_UDP = 10 +}GMAC_RX_PACKET_TYPE, *PGMAC_RX_PACKET_TYPE; + + +/* + +// Memory Map of DW_apb_ssi +#define REG_DW_SSI_CTRLR0 0x00 // 16 bits +#define REG_DW_SSI_CTRLR1 0x04 // 16 bits +#define REG_DW_SSI_SSIENR 0x08 // 1 bit +#define REG_DW_SSI_RX_SAMPLE_DLY 0xF0 // 8 bits +#define REG_DW_SSI_RSVD_0 0xF4 // 32 bits +#define REG_DW_SSI_RSVD_1 0xF8 // 32 bits +#define REG_DW_SSI_RSVD_2 0xFC // 32 bits + +// CTRLR0 0x00 // 16 bits, 6.2.1 +// DFS Reset Value: 0x7 +#define BIT_SHIFT_CTRLR0_DFS 0 +#define BIT_MASK_CTRLR0_DFS 0xF +#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS) +#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS)) + +#define BIT_SHIFT_CTRLR0_FRF 4 +#define BIT_MASK_CTRLR0_FRF 0x3 +#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF) +#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF)) + +#define BIT_SHIFT_CTRLR0_SCPH 6 +#define BIT_MASK_CTRLR0_SCPH 0x1 +#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH) +#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH)) + +// CTRLR1 0x04 // 16 bits +#define BIT_SHIFT_CTRLR1_NDF 0 +#define BIT_MASK_CTRLR1_NDF 0xFFFF +#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF) +#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF)) + +// TXFLTR 0x18 // Variable Length +#define BIT_SHIFT_TXFTLR_TFT 0 +#define BIT_MASK_TXFTLR_TFT 0x3F // (TX_ABW-1):0 +#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT) +#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT)) + +// TXFLR 0x20 // see [READ ONLY] +#define BIT_MASK_TXFLR_TXTFL 0x7F // (TX_ABW):0 + +// RXFLR 0x24 // see [READ ONLY] +#define BIT_MASK_RXFLR_RXTFL 0x7F // (RX_ABW):0 + +// SR 0x28 // 7 bits [READ ONLY] +#define BIT_SR_BUSY BIT0 +#define BIT_SR_TFNF BIT1 +#define BIT_SR_TFE BIT2 +#define BIT_SR_RFNE BIT3 +#define BIT_SR_RFF BIT4 +#define BIT_SR_TXE BIT5 +#define BIT_SR_DCOL BIT6 + +#define BIT_IMR_TXEIM BIT0 +#define BIT_IMR_TXOIM BIT1 +#define BIT_IMR_RXUIM BIT2 +#define BIT_IMR_RXOIM BIT3 +#define BIT_IMR_RXFIM BIT4 +#define BIT_IMR_MSTIM BIT5 + +// ISR 0x30 // 6 bits [READ ONLY] +#define BIT_ISR_TXEIS BIT0 +#define BIT_ISR_TXOIS BIT1 +#define BIT_ISR_RXUIS BIT2 +#define BIT_ISR_RXOIS BIT3 +#define BIT_ISR_RXFIS BIT4 +#define BIT_ISR_MSTIS BIT5 + +*/ + +BOOL +HalMiiGmacInitRtl8195a( + IN VOID *Data + ); + +BOOL +HalMiiInitRtl8195a( + IN VOID *Data + ); + +BOOL +HalMiiGmacResetRtl8195a( + IN VOID *Data + ); + +BOOL +HalMiiGmacEnablePhyModeRtl8195a( + IN VOID *Data + ); + +u32 +HalMiiGmacXmitRtl8195a( + IN VOID *Data + ); + +VOID +HalMiiGmacCleanTxRingRtl8195a( + IN VOID *Data + ); + +VOID +HalMiiGmacFillTxInfoRtl8195a( + IN VOID *Data + ); + +VOID +HalMiiGmacFillRxInfoRtl8195a( + IN VOID *Data + ); + +VOID +HalMiiGmacTxRtl8195a( + IN VOID *Data + ); + +VOID +HalMiiGmacRxRtl8195a( + IN VOID *Data + ); + +VOID +HalMiiGmacSetDefaultEthIoCmdRtl8195a( + IN VOID *Data + ); + +VOID +HalMiiGmacInitIrqRtl8195a( + IN VOID *Data + ); + +u32 +HalMiiGmacGetInterruptStatusRtl8195a( + VOID + ); + +VOID +HalMiiGmacClearInterruptStatusRtl8195a( + u32 IsrStatus + ); + +#endif + diff --git a/lib/fwlib/rtl8195a/rtl8195a_nfc.h b/lib/fwlib/rtl8195a/rtl8195a_nfc.h new file mode 100644 index 0000000..a1c12b6 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_nfc.h @@ -0,0 +1,153 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _RTL8195A_NFC_H_ +#define _RTL8195A_NFC_H_ + +#include "hal_api.h" +//#include "osdep_api.h" +#ifdef CONFIG_NFC_VERIFY +#include "../test/nfc/rtl8195a_nfc_test.h" +#endif + +#if CONFIG_NFC_NORMAL +//===================== Register Bit Field Definition ===================== +// TODO: +//===================== Register Address Definition ===================== +//TODO: +//#include "osdep_api.h" +#define N2A_Q_LENGTH 10 +#define N2ARLENGTH 4 +//#define NFCTAGLENGTH 36 // maximum 36*4=144 bytes +#define NFCTAG_BASE 0x7F000 +#define NFCTAG_PAGESIZE 256 +#define NFCTAG_MAXPAGEIDX 16//(4*(1024/NFCTAG_PAGESIZE)) +#define A2NWCLENGTH 4 + +#define FLASHAPPLENGTH 31 +#define FLASHAPP_BASE 0x7E000 +#define FLASH_PAGESIZE 128 +#define FLASH_MAXPAGEIDX 32//(4*(1024/FLASH_PAGESIZE)) + +typedef struct _A2N_CATCH_W_ { + //u8 Vaild; + u8 A2NCatchRPage; + u32 A2NCatchWData[A2NWCLENGTH]; +}A2N_CATCH_W_QUEUE, *PA2N_CATCH_W_QUEUE; + +typedef struct _A2N_MAILBOX_Q_ { + u8 Length; + u8 Response; + u32 Content[A2NWCLENGTH+1]; +}A2N_MAILBOX_Q,*PA2N_MAILBOX_Q; + +typedef struct _N2A_CATCH_R_ { + u8 Vaild; + u8 N2ACatchRPage; + u32 N2ACatchRData[N2ARLENGTH]; +}N2A_CATCH_R_QUEUE, *PN2A_CATCH_R_QUEUE; + + +typedef struct _N2A_R_ { + u8 Vaild; + u8 N2ARPage; +}N2A_R_QUEUE, *PN2A_R_QUEUE; + +typedef struct _N2A_W_ { + u8 Vaild; + u8 N2AWPage; + u32 N2AWData; +}N2A_W_QUEUE, *PN2A_W_QUEUE; + +typedef struct _NFC_ADAPTER_ { + u8 Function; + u32 NFCIsr; + u8 N2ABoxOpen; + u8 A2NSeq; + //u8 NFCTagFlashWIdx; + //u8 NFCTagFlashRIdx; +// u32 NFCTag[NFCTAGLENGTH]; +#if !TASK_SCHEDULER_DISABLED + void * VeriSema; +#else + u32 VeriSema; +#endif +#ifdef PLATFORM_FREERTOS + void * NFCTask; +#else + u32 NFCTask; +#endif +#ifdef CONFIG_NFC_VERIFY + //N2A Write Tag + u8 N2AWQRIdx; + u8 N2AWQWIdx; + N2A_W_QUEUE N2AWQ[N2A_Q_LENGTH]; + //N2A Read Tag + u8 N2ARQRIdx; + u8 N2ARQWIdx; + N2A_R_QUEUE N2ARQ[N2A_Q_LENGTH]; + //N2A Read Catch + u8 N2ARCRIdx; + u8 N2ARCWIdx; + N2A_CATCH_R_QUEUE N2ACatchR[N2A_Q_LENGTH]; +#endif + //A2N Write Catch + //u8 A2NWCRIdx; + //u8 A2NWCWIdx; + //A2N_CATCH_W_QUEUE A2NCatchW[N2A_Q_LENGTH]; + + //A2N Write mailbox queue + u8 A2NWMailBox; + u8 A2NWQRIdx; + u8 A2NWQWIdx; + A2N_MAILBOX_Q A2NMAILQ[N2A_Q_LENGTH]; + + u8 TaskStop; + void *nfc_obj; +}NFC_ADAPTER, *PNFC_ADAPTER; + +typedef enum _N2A_CMD_ { + TAG_READ = 0, + TAG_WRITE = 1, + CATCH_READ_DATA = 2, + NFC_R_PRESENT = 4, + N2A_MAILBOX_STATE = 5, + EXT_CLK_REQ = 6, + MAX_N2ACMD +} N2A_CMD, *PN2A_CMD; + +typedef enum _A2N_CMD_ { + TAG_READ_DATA = 0, + CATCH_READ = 2, + CATCH_WRITE = 3, + A2N_MAILBOX_STATE = 4, + CONFIRM_N2A_BOX_STATE = 5, + EXT_CLK_RSP = 6, + MAX_A2NCMD +} A2N_CMD, *PA2N_CMD; + +// Callback event defination +typedef enum _NFC_HAL_EVENT_ { + NFC_HAL_READER_PRESENT = (1<<0), + NFC_HAL_READ = (1<<1), + NFC_HAL_WRITE = (1<<2), + NFC_HAL_ERR = (1<<3), + NFC_HAL_CACHE_RD = (1<<4) +}NFC_CB_EVENT, *PNFC_CB_EVENT; + +VOID A2NWriteCatch(IN VOID *pNFCAdapte, IN u8 N2AWPage, + IN u8 Length, IN u32 *WData); +VOID A2NReadCatch(IN VOID *pNFCAdapte, IN u8 A2NRPage); +VOID HalNFCDmemInit(IN u32 *pTagData, IN u32 TagLen); +VOID HalNFCInit(PNFC_ADAPTER pNFCAdp); +VOID HalNFCDeinit(PNFC_ADAPTER pNFCAdp); +VOID HalNFCFwDownload(VOID); +#endif //CONFIG_NFC_NORMAL +#endif // #ifndef _RTL8195A_NFC_H_ \ No newline at end of file diff --git a/lib/fwlib/rtl8195a/rtl8195a_pcm.h b/lib/fwlib/rtl8195a/rtl8195a_pcm.h new file mode 100644 index 0000000..c2bd793 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_pcm.h @@ -0,0 +1,449 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _RTL8195A_PCM_H_ +#define _RTL8195A_PCM_H_ + +#include "basic_types.h" +#include "hal_api.h" + +#define HAL_PCMX_READ32(PcmIndex, addr) \ + HAL_READ32(PCM0_REG_BASE+ (PcmIndex*PCM1_REG_OFF), addr) +#define HAL_PCMX_WRITE32(PcmIndex, addr, value) \ + HAL_WRITE32((PCM0_REG_BASE+ (PcmIndex*PCM1_REG_OFF)), addr, value) + +#define REG_PCM_TRXBSA_OFF 0x004 +#define REG_PCM_CTL 0x000 +#define REG_PCM_CHCNR03 0x004 +#define REG_PCM_TSR03 0x008 +#define REG_PCM_BSIZE03 0x00C + +#define REG_PCM_CH0TXBSA 0x010 +#define REG_PCM_CH1TXBSA 0x014 +#define REG_PCM_CH2TXBSA 0x018 +#define REG_PCM_CH3TXBSA 0x01c +#define REG_PCM_CH0RXBSA 0x020 +#define REG_PCM_CH1RXBSA 0x024 +#define REG_PCM_CH2RXBSA 0x028 +#define REG_PCM_CH3RXBSA 0x02c + +#define REG_PCM_IMR03 0x030 +#define REG_PCM_ISR03 0x034 + +#define REG_PCM_CHCNR47 0x038 +#define REG_PCM_TSR47 0x03c +#define REG_PCM_BSIZE47 0x040 +#define REG_PCM_CH4TXBSA 0x044 +#define REG_PCM_CH5TXBSA 0x048 +#define REG_PCM_CH6TXBSA 0x04c +#define REG_PCM_CH7TXBSA 0x050 +#define REG_PCM_CH4RXBSA 0x054 +#define REG_PCM_CH5RXBSA 0x058 +#define REG_PCM_CH6RXBSA 0x05c +#define REG_PCM_CH7RXBSA 0x060 + +#define REG_PCM_IMR47 0x064 +#define REG_PCM_ISR47 0x068 + +#define REG_PCM_CHCNR811 0x06c +#define REG_PCM_TSR811 0x070 +#define REG_PCM_BSIZE811 0x074 +#define REG_PCM_CH8TXBSA 0x078 +#define REG_PCM_CH9TXBSA 0x07c +#define REG_PCM_CH10TXBSA 0x080 +#define REG_PCM_CH11TXBSA 0x084 +#define REG_PCM_CH8RXBSA 0x088 +#define REG_PCM_CH9RXBSA 0x08c +#define REG_PCM_CH10RXBSA 0x090 +#define REG_PCM_CH11RXBSA 0x094 + +#define REG_PCM_IMR811 0x098 +#define REG_PCM_ISR811 0x09c + +#define REG_PCM_CHCNR1215 0x0a0 +#define REG_PCM_TSR1215 0x0a4 +#define REG_PCM_BSIZE1215 0x0a8 +#define REG_PCM_CH12TXBSA 0x0ac +#define REG_PCM_CH13TXBSA 0x0b0 +#define REG_PCM_CH14TXBSA 0x0b4 +#define REG_PCM_CH15TXBSA 0x0b8 +#define REG_PCM_CH12RXBSA 0x0bc +#define REG_PCM_CH13RXBSA 0x0c0 +#define REG_PCM_CH14RXBSA 0x0c4 +#define REG_PCM_CH15RXBSA 0x0c8 + +#define REG_PCM_IMR1215 0x0cc +#define REG_PCM_ISR1215 0x0d0 + +#define REG_PCM_INTMAP 0x0d4 +#define REG_PCM_WTSR03 0x0d8 +#define REG_PCM_WTSR47 0x0dc + +#define REG_PCM_RX_BUFOW 0x0e0 + +/* template +#define BIT_SHIFT_CTLX_ 7 +#define BIT_MASK_CTLX_ 0x1 +#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_) +#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_)) +*/ +#define BIT_SHIFT_CTLX_SLAVE_SEL 8 +#define BIT_MASK_CTLX_SLAVE_SEL 0x1 +#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL) +#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL)) + +#define BIT_SHIFT_CTLX_FSINV 9 +#define BIT_MASK_CTLX_FSINV 0x1 +#define BIT_CTLX_FSINV(x) (((x) & BIT_MASK_CTLX_FSINV) << BIT_SHIFT_CTLX_FSINV) +#define BIT_INV_CTLX_FSINV (~(BIT_MASK_CTLX_FSINV << BIT_SHIFT_CTLX_FSINV)) + +#define BIT_SHIFT_CTLX_PCM_EN 12 +#define BIT_MASK_CTLX_PCM_EN 0x1 +#define BIT_CTLX_PCM_EN(x) (((x) & BIT_MASK_CTLX_PCM_EN) << BIT_SHIFT_CTLX_PCM_EN) +#define BIT_INV_CTLX_PCM_EN (~(BIT_MASK_CTLX_PCM_EN << BIT_SHIFT_CTLX_PCM_EN)) + +#define BIT_SHIFT_CTLX_LINEARMODE 13 +#define BIT_MASK_CTLX_LINEARMODE 0x1 +#define BIT_CTLX_LINEARMODE(x) (((x) & BIT_MASK_CTLX_LINEARMODE) << BIT_SHIFT_CTLX_LINEARMODE) +#define BIT_INV_CTLX_LINEARMODE (~(BIT_MASK_CTLX_LINEARMODE << BIT_SHIFT_CTLX_LINEARMODE)) + +#define BIT_SHIFT_CTLX_LOOP_BACK 14 +#define BIT_MASK_CTLX_LOOP_BACK 0x1 +#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK) +#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK)) + +#define BIT_SHIFT_CTLX_ENDIAN_SWAP 17 +#define BIT_MASK_CTLX_ENDIAN_SWAP 0x1 +#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP) +#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP)) + +#define BIT_SHIFT_CHCNR03_CH0RE 24 +#define BIT_MASK_CHCNR03_CH0RE 0x1 +#define BIT_CHCNR03_CH0RE(x) (((x) & BIT_MASK_CHCNR03_CH0RE) << BIT_SHIFT_CHCNR03_CH0RE) +#define BIT_INV_CHCNR03_CH0RE (~(BIT_MASK_CHCNR03_CH0RE << BIT_SHIFT_CHCNR03_CH0RE)) + +#define BIT_SHIFT_CHCNR03_CH0TE 25 +#define BIT_MASK_CHCNR03_CH0TE 0x1 +#define BIT_CHCNR03_CH0TE(x) (((x) & BIT_MASK_CHCNR03_CH0TE) << BIT_SHIFT_CHCNR03_CH0TE) +#define BIT_INV_CHCNR03_CH0TE (~(BIT_MASK_CHCNR03_CH0TE << BIT_SHIFT_CHCNR03_CH0TE)) + +#define BIT_SHIFT_CHCNR03_CH1RE 16 +#define BIT_MASK_CHCNR03_CH1RE 0x1 +#define BIT_CHCNR03_CH1RE(x) (((x) & BIT_MASK_CHCNR03_CH1RE) << BIT_SHIFT_CHCNR03_CH1RE) +#define BIT_INV_CHCNR03_CH1RE (~(BIT_MASK_CHCNR03_CH1RE << BIT_SHIFT_CHCNR03_CH1RE)) + +#define BIT_SHIFT_CHCNR03_CH1TE 17 +#define BIT_MASK_CHCNR03_CH1TE 0x1 +#define BIT_CHCNR03_CH1TE(x) (((x) & BIT_MASK_CHCNR03_CH1TE) << BIT_SHIFT_CHCNR03_CH1TE) +#define BIT_INV_CHCNR03_CH1TE (~(BIT_MASK_CHCNR03_CH1TE << BIT_SHIFT_CHCNR03_CH1TE)) + +#define BIT_SHIFT_CHCNR03_CH2RE 8 +#define BIT_MASK_CHCNR03_CH2RE 0x1 +#define BIT_CHCNR03_CH2RE(x) (((x) & BIT_MASK_CHCNR03_CH2RE) << BIT_SHIFT_CHCNR03_CH2RE) +#define BIT_INV_CHCNR03_CH2RE (~(BIT_MASK_CHCNR03_CH2RE << BIT_SHIFT_CHCNR03_CH2RE)) + +#define BIT_SHIFT_CHCNR03_CH2TE 9 +#define BIT_MASK_CHCNR03_CH2TE 0x1 +#define BIT_CHCNR03_CH2TE(x) (((x) & BIT_MASK_CHCNR03_CH2TE) << BIT_SHIFT_CHCNR03_CH2TE) +#define BIT_INV_CHCNR03_CH2TE (~(BIT_MASK_CHCNR03_CH2TE << BIT_SHIFT_CHCNR03_CH2TE)) + +#define BIT_SHIFT_CHCNR03_CH3RE 0 +#define BIT_MASK_CHCNR03_CH3RE 0x1 +#define BIT_CHCNR03_CH3RE(x) (((x) & BIT_MASK_CHCNR03_CH3RE) << BIT_SHIFT_CHCNR03_CH3RE) +#define BIT_INV_CHCNR03_CH3RE (~(BIT_MASK_CHCNR03_CH3RE << BIT_SHIFT_CHCNR03_CH3RE)) + +#define BIT_SHIFT_CHCNR03_CH3TE 1 +#define BIT_MASK_CHCNR03_CH3TE 0x1 +#define BIT_CHCNR03_CH3TE(x) (((x) & BIT_MASK_CHCNR03_CH3TE) << BIT_SHIFT_CHCNR03_CH3TE) +#define BIT_INV_CHCNR03_CH3TE (~(BIT_MASK_CHCNR03_CH3TE << BIT_SHIFT_CHCNR03_CH3TE)) + +#define BIT_SHIFT_CHCNR03_CH0MUA 26 +#define BIT_MASK_CHCNR03_CH0MUA 0x1 +#define BIT_CHCNR03_CH0MUA(x) (((x) & BIT_MASK_CHCNR03_CH0MUA) << BIT_SHIFT_CHCNR03_CH0MUA) +#define BIT_INV_CHCNR03_CH0MUA (~(BIT_MASK_CHCNR03_CH0MUA << BIT_SHIFT_CHCNR03_CH0MUA)) + +#define BIT_SHIFT_CHCNR03_CH0BAND 27 +#define BIT_MASK_CHCNR03_CH0BAND 0x1 +#define BIT_CHCNR03_CH0BAND(x) (((x) & BIT_MASK_CHCNR03_CH0BAND) << BIT_SHIFT_CHCNR03_CH0BAND) +#define BIT_INV_CHCNR03_CH0BAND (~(BIT_MASK_CHCNR03_CH0BAND << BIT_SHIFT_CHCNR03_CH0BAND)) + +#define BIT_SHIFT_TSR03_CH0TSA 24 +#define BIT_MASK_TSR03_CH0TSA 0x1F +#define BIT_TSR03_CH0TSA(x) (((x) & BIT_MASK_TSR03_CH0TSA) << BIT_SHIFT_TSR03_CH0TSA) +#define BIT_INV_TSR03_CH0TSA (~(BIT_MASK_TSR03_CH0TSA << BIT_SHIFT_TSR03_CH0TSA)) + +#define BIT_SHIFT_BSIZE03_CH0BSIZE 24 +#define BIT_MASK_BSIZE03_CH0BSIZE 0xFF +#define BIT_BSIZE03_CH0BSIZE(x) (((x) & BIT_MASK_BSIZE03_CH0BSIZE) << BIT_SHIFT_BSIZE03_CH0BSIZE) +#define BIT_INV_BSIZE03_CH0BSIZE (~(BIT_MASK_BSIZE03_CH0BSIZE << BIT_SHIFT_BSIZE03_CH0BSIZE)) + +typedef struct _PCM_CTL_REG_ { + u32 FCNT :8; // Bit 0-7 + u32 SlaveMode :1; // Bit 8 + u32 FsInv :1; // Bit 9 + u32 Rsvd10to11 :1; // Bit 10-11 + u32 Pcm_En :1; // Bit 12 + u32 LinearMode :1; // Bit 13 + u32 LoopBack :1; // Bit 14 + u32 Rsvd15to16 :2; // Bit 15-16 + u32 EndianSwap :1; // Bit 17 + u32 Rsvd18to31 :14; // Bit 18-31 +} PCM_CTL_REG, *PPCM_CTL_REG; + + + +typedef struct _PCM_CHCNR03_REG_ { + u32 CH3RE :1; // Bit 0 + u32 CH3TE :1; // Bit 1 + u32 CH3MuA :1; // Bit 2 + u32 CH3Band :1; // Bit 3 + u32 CH3SlicSel:4; // Bit 4-7 + u32 CH2RE :1; // Bit 8 + u32 CH2TE :1; // Bit 9 + u32 CH2MuA :1; // Bit 10 + u32 CH2Band :1; // Bit 11 + u32 CH2SlicSel:4; // Bit 12-15 + u32 CH1RE :1; // Bit 16 + u32 CH1TE :1; // Bit 17 + u32 CH1MuA :1; // Bit 18 + u32 CH1Band :1; // Bit 19 + u32 CH1SlicSel:4; // Bit 20-23 + u32 CH0RE :1; // Bit 24 + u32 CH0TE :1; // Bit 25 + u32 CH0MuA :1; // Bit 26 + u32 CH0Band :1; // Bit 27 + u32 CH0SlicSel:4; // Bit 28-31 +}PCM_CHCNR03_REG, *PPCM_CHCNR03_REG; + +typedef struct _PCM_TSR03_REG_ { + u32 CH3TSA :5; // Bit 0-4 + u32 Rsvd5to7 :3; // Bit 5-7 + u32 CH2TSA :5; // Bit 8-12 + u32 Rsvd13to15:3; // Bit 13-15 + u32 CH1TSA :5; // Bit 16-20 + u32 Rsvd21to23:3; // Bit 21-23 + u32 CH0TSA :5; // Bit 24-28 + u32 Rsvd29to31:3; // Bit 29-31 +}PCM_TSR03_REG, *PPCM_TSR03_REG; + +typedef struct _PCM_BSIZE03_REG_ { + u32 CH3BSize :8; // Bit 0-7 + u32 CH2BSize :8; // Bit 8-15 + u32 CH1BSize :8; // Bit 16-23 + u32 CH0BSize :8; // Bit 24-31 +}PCM_BSIZE03_REG, *PPCM_BSIZE03_REG; + +typedef struct _PCM_ISR03_REG_ { + u32 CH3RXP1UA :1; // Bit 0 + u32 CH3RXP0UA :1; // Bit 1 + u32 CH3TXP1UA :1; // Bit 2 + u32 CH3TXP0UA :1; // Bit 3 + u32 CH3RXP1IP :1; // Bit 4 + u32 CH3RXP0IP :1; // Bit 5 + u32 CH3TXP1IP :1; // Bit 6 + u32 CH3TXP0IP :1; // Bit 7 + u32 CH2RXP1UA :1; // Bit 8 + u32 CH2RXP0UA :1; // Bit 9 + u32 CH2TXP1UA :1; // Bit 10 + u32 CH2TXP0UA :1; // Bit 11 + u32 CH2RXP1IP :1; // Bit 12 + u32 CH2RXP0IP :1; // Bit 13 + u32 CH2TXP1IP :1; // Bit 14 + u32 CH2TXP0IP :1; // Bit 15 + u32 CH1RXP1UA :1; // Bit 16 + u32 CH1RXP0UA :1; // Bit 17 + u32 CH1TXP1UA :1; // Bit 18 + u32 CH1TXP0UA :1; // Bit 19 + u32 CH1RXP1IP :1; // Bit 20 + u32 CH1RXP0IP :1; // Bit 21 + u32 CH1TXP1IP :1; // Bit 22 + u32 CH1TXP0IP :1; // Bit 23 + u32 CH0RXP1UA :1; // Bit 24 + u32 CH0RXP0UA :1; // Bit 25 + u32 CH0TXP1UA :1; // Bit 26 + u32 CH0TXP0UA :1; // Bit 27 + u32 CH0RXP1IP :1; // Bit 28 + u32 CH0RXP0IP :1; // Bit 29 + u32 CH0TXP1IP :1; // Bit 30 + u32 CH0TXP0IP :1; // Bit 31 +}PCM_ISR03_REG, *PPCM_ISR03_REG; + +typedef enum _PCM_ISR015 { + PcmCh3P1RBU = 0x00000001, //ch0-3 + PcmCh3P0RBU = 0x00000002, + PcmCh3P1TBU = 0x00000004, + PcmCh3P0TBU = 0x00000008, + PcmCh3P1ROK = 0x00000010, + PcmCh3P0ROK = 0x00000020, + PcmCh3P1TOK = 0x00000040, + PcmCh3P0TOK = 0x00000080, + PcmCh2P1RBU = 0x00000100, + PcmCh2P0RBU = 0x00000200, + PcmCh2P1TBU = 0x00000400, + PcmCh2P0TBU = 0x00000800, + PcmCh2P1ROK = 0x00001000, + PcmCh2P0ROK = 0x00002000, + PcmCh2P1TOK = 0x00004000, + PcmCh2P0TOK = 0x00008000, + PcmCh1P1RBU = 0x00010000, + PcmCh1P0RBU = 0x00020000, + PcmCh1P1TBU = 0x00040000, + PcmCh1P0TBU = 0x00080000, + PcmCh1P1ROK = 0x00100000, + PcmCh1P0ROK = 0x00200000, + PcmCh1P1TOK = 0x00400000, + PcmCh1P0TOK = 0x00800000, + PcmCh0P1RBU = 0x01000000, + PcmCh0P0RBU = 0x02000000, + PcmCh0P1TBU = 0x04000000, + PcmCh0P0TBU = 0x08000000, + PcmCh0P1ROK = 0x10000000, + PcmCh0P0ROK = 0x20000000, + PcmCh0P1TOK = 0x40000000, + PcmCh0P0TOK = 0x80000000, + + PcmCh7P1RBU = 0x00000001, //ch4-7 + PcmCh7P0RBU = 0x00000002, + PcmCh7P1TBU = 0x00000004, + PcmCh7P0TBU = 0x00000008, + PcmCh7P1ROK = 0x00000010, + PcmCh7P0ROK = 0x00000020, + PcmCh7P1TOK = 0x00000040, + PcmCh7P0TOK = 0x00000080, + PcmCh6P1RBU = 0x00000100, + PcmCh6P0RBU = 0x00000200, + PcmCh6P1TBU = 0x00000400, + PcmCh6P0TBU = 0x00000800, + PcmCh6P1ROK = 0x00001000, + PcmCh6P0ROK = 0x00002000, + PcmCh6P1TOK = 0x00004000, + PcmCh6P0TOK = 0x00008000, + PcmCh5P1RBU = 0x00010000, + PcmCh5P0RBU = 0x00020000, + PcmCh5P1TBU = 0x00040000, + PcmCh5P0TBU = 0x00080000, + PcmCh5P1ROK = 0x00100000, + PcmCh5P0ROK = 0x00200000, + PcmCh5P1TOK = 0x00400000, + PcmCh5P0TOK = 0x00800000, + PcmCh4P1RBU = 0x01000000, + PcmCh4P0RBU = 0x02000000, + PcmCh4P1TBU = 0x04000000, + PcmCh4P0TBU = 0x08000000, + PcmCh4P1ROK = 0x10000000, + PcmCh4P0ROK = 0x20000000, + PcmCh4P1TOK = 0x40000000, + PcmCh4P0TOK = 0x80000000, + + PcmCh11P1RBU = 0x00000001, //ch8-11 + PcmCh11P0RBU = 0x00000002, + PcmCh11P1TBU = 0x00000004, + PcmCh11P0TBU = 0x00000008, + PcmCh11P1ROK = 0x00000010, + PcmCh11P0ROK = 0x00000020, + PcmCh11P1TOK = 0x00000040, + PcmCh11P0TOK = 0x00000080, + PcmCh10P1RBU = 0x00000100, + PcmCh10P0RBU = 0x00000200, + PcmCh10P1TBU = 0x00000400, + PcmCh10P0TBU = 0x00000800, + PcmCh10P1ROK = 0x00001000, + PcmCh10P0ROK = 0x00002000, + PcmCh10P1TOK = 0x00004000, + PcmCh10P0TOK = 0x00008000, + PcmCh9P1RBU = 0x00010000, + PcmCh9P0RBU = 0x00020000, + PcmCh9P1TBU = 0x00040000, + PcmCh9P0TBU = 0x00080000, + PcmCh9P1ROK = 0x00100000, + PcmCh9P0ROK = 0x00200000, + PcmCh9P1TOK = 0x00400000, + PcmCh9P0TOK = 0x00800000, + PcmCh8P1RBU = 0x01000000, + PcmCh8P0RBU = 0x02000000, + PcmCh8P1TBU = 0x04000000, + PcmCh8P0TBU = 0x08000000, + PcmCh8P1ROK = 0x10000000, + PcmCh8P0ROK = 0x20000000, + PcmCh8P1TOK = 0x40000000, + PcmCh8P0TOK = 0x80000000, + + PcmCh15P1RBU = 0x00000001, //ch12-15 + PcmCh15P0RBU = 0x00000002, + PcmCh15P1TBU = 0x00000004, + PcmCh15P0TBU = 0x00000008, + PcmCh15P1ROK = 0x00000010, + PcmCh15P0ROK = 0x00000020, + PcmCh15P1TOK = 0x00000040, + PcmCh15P0TOK = 0x00000080, + PcmCh14P1RBU = 0x00000100, + PcmCh14P0RBU = 0x00000200, + PcmCh14P1TBU = 0x00000400, + PcmCh14P0TBU = 0x00000800, + PcmCh14P1ROK = 0x00001000, + PcmCh14P0ROK = 0x00002000, + PcmCh14P1TOK = 0x00004000, + PcmCh14P0TOK = 0x00008000, + PcmCh13P1RBU = 0x00010000, + PcmCh13P0RBU = 0x00020000, + PcmCh13P1TBU = 0x00040000, + PcmCh13P0TBU = 0x00080000, + PcmCh13P1ROK = 0x00100000, + PcmCh13P0ROK = 0x00200000, + PcmCh13P1TOK = 0x00400000, + PcmCh13P0TOK = 0x00800000, + PcmCh12P1RBU = 0x01000000, + PcmCh12P0RBU = 0x02000000, + PcmCh12P1TBU = 0x04000000, + PcmCh12P0TBU = 0x08000000, + PcmCh12P1ROK = 0x10000000, + PcmCh12P0ROK = 0x20000000, + PcmCh12P1TOK = 0x40000000, + PcmCh12P0TOK = 0x80000000 +}PCM_ISR015, *PPCM_ISR015; + +VOID +HalPcmOnOffRtl8195a( + IN VOID *Data +); + +BOOL +HalPcmInitRtl8195a( + IN VOID *Data +); + +BOOL +HalPcmSettingRtl8195a( + IN VOID *Data +); + +BOOL +HalPcmEnRtl8195a( + IN VOID *Data +); + +BOOL +HalPcmIsrEnAndDisRtl8195a( + IN VOID *Data +); + +BOOL +HalPcmDumpRegRtl8195a( + IN VOID *Data +); + +BOOL +HalPcmRtl8195a( + IN VOID *Data +); + +#endif /* _RTL8195A_PCM_H_ */ + + diff --git a/lib/fwlib/rtl8195a/rtl8195a_peri_on.h b/lib/fwlib/rtl8195a/rtl8195a_peri_on.h new file mode 100644 index 0000000..da99b98 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_peri_on.h @@ -0,0 +1,1251 @@ +#ifndef __INC_RTL8195A_PERI_ON_H +#define __INC_RTL8195A_PERI_ON_H + +#define CPU_OPT_WIDTH 0x1F + +//2 REG_NOT_VALID + +//2 REG_PEON_PWR_CTRL +#define BIT_SOC_UAHV_EN BIT(2) +#define BIT_SOC_UALV_EN BIT(1) +#define BIT_SOC_USBD_EN BIT(0) + +//2 REG_PON_ISO_CTRL + +//2 REG_NOT_VALID +#define BIT_ISO_OSC32K_EN BIT(4) +//#define BIT_ISO_USBA_EN BIT(1) +//#define BIT_ISO_USBD_EN BIT(0) + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_SOC_FUNC_EN +#define BIT_SOC_SECURITY_ENGINE_EN BIT(20) +#define BIT_SOC_GTIMER_EN BIT(16) +#define BIT_SOC_GDMA1_EN BIT(14) +#define BIT_SOC_GDMA0_EN BIT(13) +#define BIT_SOC_LOG_UART_EN BIT(12) +#define BIT_SOC_CPU_EN BIT(8) +#define BIT_SOC_MEM_CTRL_EN BIT(6) +#define BIT_SOC_FLASH_EN BIT(4) +#define BIT_SOC_LXBUS_EN BIT(2) +#define BIT_SOC_OCP_EN BIT(1) +#define BiT_SOC_FUN_EN BIT(0) + +//2 REG_SOC_HCI_COM_FUNC_EN +#define BIT_SOC_HCI_WL_MACON_EN BIT(16) +#define BIT_SOC_HCI_SM_SEL BIT(13) +#define BIT_SOC_HCI_MII_EN BIT(12) +#define BIT_SOC_HCI_OTG_RST_MUX BIT(5) +#define BIT_SOC_HCI_OTG_EN BIT(4) +#define BIT_SOC_HCI_SDIOD_ON_RST_MUX BIT(3) +#define BIT_SOC_HCI_SDIOH_EN BIT(2) +#define BIT_SOC_HCI_SDIOD_OFF_EN BIT(1) +#define BIT_SOC_HCI_SDIOD_ON_EN BIT(0) + +//2 REG_SOC_PERI_FUNC0_EN +#define BIT_PERI_PCM1_EN BIT(29) +#define BIT_PERI_PCM0_EN BIT(28) +#define BIT_PERI_I2S1_EN BIT(25) +#define BIT_PERI_I2S0_EN BIT(24) +#define BIT_PERI_I2C3_EN BIT(19) +#define BIT_PERI_I2C2_EN BIT(18) +#define BIT_PERI_I2C1_EN BIT(17) +#define BIT_PERI_I2C0_EN BIT(16) +#define BIT_PERI_SPI2_EN BIT(10) +#define BIT_PERI_SPI1_EN BIT(9) +#define BIT_PERI_SPI0_EN BIT(8) +#define BIT_PERI_UART2_EN BIT(2) +#define BIT_PERI_UART1_EN BIT(1) +#define BIT_PERI_UART0_EN BIT(0) + +//2 REG_SOC_PERI_FUNC1_EN +#define BIT_PERI_GPIO_EN BIT(8) +#define BIT_PERI_DAC1_EN BIT(5) +#define BIT_PERI_DAC0_EN BIT(4) +#define BIT_PERI_ADC0_EN BIT(0) + +//2 REG_SOC_PERI_BD_FUNC0_EN +#define BIT_PERI_UART2_BD_EN BIT(2) +#define BIT_PERI_UART1_BD_EN BIT(1) +#define BIT_PERI_UART0_BD_EN BIT(0) + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_PESOC_CLK_CTRL +#define BIT_SOC_SLPCK_BTCMD_EN BIT(29) +#define BIT_SOC_ACTCK_BTCMD_EN BIT(28) +#define BIT_SOC_SLPCK_GPIO_EN BIT(25) +#define BIT_SOC_ACTCK_GPIO_EN BIT(24) +#define BIT_SOC_SLPCK_GDMA1_EN BIT(19) +#define BIT_SOC_ACTCK_GDMA1_EN BIT(18) +#define BIT_SOC_SLPCK_GDMA0_EN BIT(17) +#define BIT_SOC_ACTCK_GDMA0_EN BIT(16) +#define BIT_SOC_SLPCK_TIMER_EN BIT(15) +#define BIT_SOC_ACTCK_TIMER_EN BIT(14) +#define BIT_SOC_SLPCK_LOG_UART_EN BIT(13) +#define BIT_SOC_ACTCK_LOG_UART_EN BIT(12) +#define BIT_SOC_SLPCK_SDR_EN BIT(11) +#define BIT_SOC_ACTCK_SDR_EN BIT(10) +#define BIT_SOC_SLPCK_FLASH_EN BIT(9) +#define BIT_SOC_ACTCK_FLASH_EN BIT(8) +#define BIT_SOC_SLPCK_VENDOR_REG_EN BIT(7) +#define BIT_SOC_ACTCK_VENDOR_REG_EN BIT(6) +#define BIT_SOC_SLPCK_TRACE_EN BIT(5) +#define BIT_SOC_ACTCK_TRACE_EN BIT(4) +#define BIT_SOC_CKE_PLFM BIT(2) +#define BIT_SOC_CKE_OCP BIT(0) + +//2 REG_PESOC_PERI_CLK_CTRL0 +#define BIT_SOC_SLPCK_SPI2_EN BIT(21) +#define BIT_SOC_ACTCK_SPI2_EN BIT(20) +#define BIT_SOC_SLPCK_SPI1_EN BIT(19) +#define BIT_SOC_ACTCK_SPI1_EN BIT(18) +#define BIT_SOC_SLPCK_SPI0_EN BIT(17) +#define BIT_SOC_ACTCK_SPI0_EN BIT(16) +#define BIT_SOC_SLPCK_UART2_EN BIT(5) +#define BIT_SOC_ACTCK_UART2_EN BIT(4) +#define BIT_SOC_SLPCK_UART1_EN BIT(3) +#define BIT_SOC_ACTCK_UART1_EN BIT(2) +#define BIT_SOC_SLPCK_UART0_EN BIT(1) +#define BIT_SOC_ACTCK_UART0_EN BIT(0) + +//2 REG_PESOC_PERI_CLK_CTRL1 +#define BIT_SOC_SLPCK_DAC_EN BIT(29) +#define BIT_SOC_ACTCK_DAC_EN BIT(28) +#define BIT_SOC_SLPCK_ADC_EN BIT(25) +#define BIT_SOC_ACTCK_ADC_EN BIT(24) +#define BIT_SOC_SLPCK_PCM_EN BIT(21) +#define BIT_SOC_ACTCK_PCM_EN BIT(20) +#define BIT_SOC_SLPCK_I2S_EN BIT(17) +#define BIT_SOC_ACTCK_I2S_EN BIT(16) +#define BIT_SOC_SLPCK_I2C3_EN BIT(7) +#define BIT_SOC_ACTCK_I2C3_EN BIT(6) +#define BIT_SOC_SLPCK_I2C2_EN BIT(5) +#define BIT_SOC_ACTCK_I2C2_EN BIT(4) +#define BIT_SOC_SLPCK_I2C1_EN BIT(3) +#define BIT_SOC_ACTCK_I2C1_EN BIT(2) +#define BIT_SOC_SLPCK_I2C0_EN BIT(1) +#define BIT_SOC_ACTCK_I2C0_EN BIT(0) + +//2 REG_PESOC_CLK_CTRL3 + +//2 REG_PESOC_HCI_CLK_CTRL0 +#define BIT_SOC_SLPCK_MII_MPHY_EN BIT(25) +#define BIT_SOC_ACTCK_MII_MPHY_EN BIT(24) +#define BIT_SOC_SLPCK_OTG_EN BIT(5) +#define BIT_SOC_ACTCK_OTG_EN BIT(4) +#define BIT_SOC_SLPCK_SDIO_HST_EN BIT(3) +#define BIT_SOC_ACTCK_SDIO_HST_EN BIT(2) +#define BIT_SOC_SLPCK_SDIO_DEV_EN BIT(1) +#define BIT_SOC_ACTCK_SDIO_DEV_EN BIT(0) + +//2 REG_PESOC_COM_CLK_CTRL1 +#define BIT_SOC_NFC_CAL_EN BIT(18) +#define BIT_SOC_SLPCK_NFC_EN BIT(17) +#define BIT_SOC_ACTCK_NFC_EN BIT(16) +#define BIT_SOC_SLPCK_SECURITY_ENG_EN BIT(5) +#define BIT_SOC_ACTCK_SECURITY_ENG_EN BIT(4) +#define BIT_SOC_SLPCK_WL_EN BIT(1) +#define BIT_SOC_ACTCK_WL_EN BIT(0) + +//2 REG_PESOC_HW_ENG_CLK_CTRL + +//2 REG_RSVD + +//2 REG_PESOC_CLK_SEL +#define BIT_PESOC_SPI1_SCLK_SEL BIT(18) + +#define BIT_SHIFT_PESOC_PERI_SCLK_SEL 16 +#define BIT_MASK_PESOC_PERI_SCLK_SEL 0x3 +#define BIT_PESOC_PERI_SCLK_SEL(x) (((x) & BIT_MASK_PESOC_PERI_SCLK_SEL) << BIT_SHIFT_PESOC_PERI_SCLK_SEL) + + +#define BIT_SHIFT_PESOC_SDR_CK_SEL 10 +#define BIT_MASK_PESOC_SDR_CK_SEL 0x3 +#define BIT_PESOC_SDR_CK_SEL(x) (((x) & BIT_MASK_PESOC_SDR_CK_SEL) << BIT_SHIFT_PESOC_SDR_CK_SEL) + + +#define BIT_SHIFT_PESOC_FLASH_CK_SEL 8 +#define BIT_MASK_PESOC_FLASH_CK_SEL 0x3 +#define BIT_PESOC_FLASH_CK_SEL(x) (((x) & BIT_MASK_PESOC_FLASH_CK_SEL) << BIT_SHIFT_PESOC_FLASH_CK_SEL) + + +#define BIT_SHIFT_PESOC_TRACE_CK_SEL 4 +#define BIT_MASK_PESOC_TRACE_CK_SEL 0x3 +#define BIT_PESOC_TRACE_CK_SEL(x) (((x) & BIT_MASK_PESOC_TRACE_CK_SEL) << BIT_SHIFT_PESOC_TRACE_CK_SEL) + + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_SYS_ANACK_CAL_CTRL +#define BIT_SYS_ANACK_CAL_CMD BIT(15) +#define BIT_SYS_ANACK_CAL_SEL BIT(14) + +#define BIT_SHIFT_SYS_ANACK_CAL_RPT 0 +#define BIT_MASK_SYS_ANACK_CAL_RPT 0x3fff +#define BIT_SYS_ANACK_CAL_RPT(x) (((x) & BIT_MASK_SYS_ANACK_CAL_RPT) << BIT_SHIFT_SYS_ANACK_CAL_RPT) + + +//2 REG_OSC32K_CTRL + +#define BIT_SHIFT_32K_BIAS_CURRENT 16 +#define BIT_MASK_32K_BIAS_CURRENT 0xffff +#define BIT_32K_BIAS_CURRENT(x) (((x) & BIT_MASK_32K_BIAS_CURRENT) << BIT_SHIFT_32K_BIAS_CURRENT) + + +#define BIT_SHIFT_32K_RESISTOR_COM 2 +#define BIT_MASK_32K_RESISTOR_COM 0x3 +#define BIT_32K_RESISTOR_COM(x) (((x) & BIT_MASK_32K_RESISTOR_COM) << BIT_SHIFT_32K_RESISTOR_COM) + +#define BIT_32K_DBG_SEL BIT(1) +#define BIT_32K_POW_CKGEN_EN BIT(0) + +//2 REG_OSC32K_REG_CTRL0 +#define BIT_32K_REG_INDIRT_CMD BIT(23) + +#define BIT_SHIFT_32K_REG_INDIRT_ADDR 16 +#define BIT_MASK_32K_REG_INDIRT_ADDR 0x3f +#define BIT_32K_REG_INDIRT_ADDR(x) (((x) & BIT_MASK_32K_REG_INDIRT_ADDR) << BIT_SHIFT_32K_REG_INDIRT_ADDR) + + +#define BIT_SHIFT_32K_REG_INDIRT_WDATA 0 +#define BIT_MASK_32K_REG_INDIRT_WDATA 0xffff +#define BIT_32K_REG_INDIRT_WDATA(x) (((x) & BIT_MASK_32K_REG_INDIRT_WDATA) << BIT_SHIFT_32K_REG_INDIRT_WDATA) + + +//2 REG_OSC32K_REG_CTRL1 + +#define BIT_SHIFT_32K_REG_INDIRT_RDATA 0 +#define BIT_MASK_32K_REG_INDIRT_RDATA 0xffff +#define BIT_32K_REG_INDIRT_RDATA(x) (((x) & BIT_MASK_32K_REG_INDIRT_RDATA) << BIT_SHIFT_32K_REG_INDIRT_RDATA) + + +//2 REG_THERMAL_METER_CTRL + +#define BIT_SHIFT_TEMP_VALUE 24 +#define BIT_MASK_TEMP_VALUE 0x3f +#define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE) + + +#define BIT_SHIFT_TEMP_DELTA 16 +#define BIT_MASK_TEMP_DELTA 0x3f +#define BIT_TEMP_DELTA(x) (((x) & BIT_MASK_TEMP_DELTA) << BIT_SHIFT_TEMP_DELTA) + +#define BIT_THERMAL_METER_EN BIT(15) +#define BIT_THERMAL_METER_VALID BIT(14) + +#define BIT_SHIFT_THERMAL_METER_TIMER 0 +#define BIT_MASK_THERMAL_METER_TIMER 0xfff +#define BIT_THERMAL_METER_TIMER(x) (((x) & BIT_MASK_THERMAL_METER_TIMER) << BIT_SHIFT_THERMAL_METER_TIMER) + + +//2 REG_UART_MUX_CTRL + +#define BIT_SHIFT_UART2_PIN_SEL 9 +#define BIT_MASK_UART2_PIN_SEL 0x7 +#define BIT_UART2_PIN_SEL(x) (((x) & BIT_MASK_UART2_PIN_SEL) << BIT_SHIFT_UART2_PIN_SEL) + +#define BIT_UART2_PIN_EN BIT(8) + +#define BIT_SHIFT_UART1_PIN_SEL 5 +#define BIT_MASK_UART1_PIN_SEL 0x7 +#define BIT_UART1_PIN_SEL(x) (((x) & BIT_MASK_UART1_PIN_SEL) << BIT_SHIFT_UART1_PIN_SEL) + +#define BIT_UART1_PIN_EN BIT(4) + +#define BIT_SHIFT_UART0_PIN_SEL 1 +#define BIT_MASK_UART0_PIN_SEL 0x7 +#define BIT_UART0_PIN_SEL(x) (((x) & BIT_MASK_UART0_PIN_SEL) << BIT_SHIFT_UART0_PIN_SEL) + +#define BIT_UART0_PIN_EN BIT(0) + +//2 REG_SPI_MUX_CTRL +#define BIT_SPI0_MULTI_CS_EN BIT(28) + +#define BIT_SHIFT_SPI2_PIN_SEL 9 +#define BIT_MASK_SPI2_PIN_SEL 0x7 +#define BIT_SPI2_PIN_SEL(x) (((x) & BIT_MASK_SPI2_PIN_SEL) << BIT_SHIFT_SPI2_PIN_SEL) + +#define BIT_SPI2_PIN_EN BIT(8) + +#define BIT_SHIFT_SPI1_PIN_SEL 5 +#define BIT_MASK_SPI1_PIN_SEL 0x7 +#define BIT_SPI1_PIN_SEL(x) (((x) & BIT_MASK_SPI1_PIN_SEL) << BIT_SHIFT_SPI1_PIN_SEL) + +#define BIT_SPI1_PIN_EN BIT(4) + +#define BIT_SHIFT_SPI0_PIN_SEL 1 +#define BIT_MASK_SPI0_PIN_SEL 0x7 +#define BIT_SPI0_PIN_SEL(x) (((x) & BIT_MASK_SPI0_PIN_SEL) << BIT_SHIFT_SPI0_PIN_SEL) + +#define BIT_SPI0_PIN_EN BIT(0) + +//2 REG_I2C_MUX_CTRL + +#define BIT_SHIFT_I2C3_PIN_SEL 13 +#define BIT_MASK_I2C3_PIN_SEL 0x7 +#define BIT_I2C3_PIN_SEL(x) (((x) & BIT_MASK_I2C3_PIN_SEL) << BIT_SHIFT_I2C3_PIN_SEL) + +#define BIT_I2C3_PIN_EN BIT(12) + +#define BIT_SHIFT_I2C2_PIN_SEL 9 +#define BIT_MASK_I2C2_PIN_SEL 0x7 +#define BIT_I2C2_PIN_SEL(x) (((x) & BIT_MASK_I2C2_PIN_SEL) << BIT_SHIFT_I2C2_PIN_SEL) + +#define BIT_I2C2_PIN_EN BIT(8) + +#define BIT_SHIFT_I2C1_PIN_SEL 5 +#define BIT_MASK_I2C1_PIN_SEL 0x7 +#define BIT_I2C1_PIN_SEL(x) (((x) & BIT_MASK_I2C1_PIN_SEL) << BIT_SHIFT_I2C1_PIN_SEL) + +#define BIT_I2C1_PIN_EN BIT(4) + +#define BIT_SHIFT_I2C0_PIN_SEL 1 +#define BIT_MASK_I2C0_PIN_SEL 0x7 +#define BIT_I2C0_PIN_SEL(x) (((x) & BIT_MASK_I2C0_PIN_SEL) << BIT_SHIFT_I2C0_PIN_SEL) + +#define BIT_I2C0_PIN_EN BIT(0) + +//2 REG_I2S_MUX_CTRL/ REG_PCM_MUX_CTRL + +//2 REG_NOT_VALID + +#define BIT_SHIFT_PCM1_PIN_SEL 21 +#define BIT_MASK_PCM1_PIN_SEL 0x7 +#define BIT_PCM1_PIN_SEL(x) (((x) & BIT_MASK_PCM1_PIN_SEL) << BIT_SHIFT_PCM1_PIN_SEL) + +#define BIT_PCM1_PIN_EN BIT(20) + +#define BIT_SHIFT_PCM0_PIN_SEL 17 +#define BIT_MASK_PCM0_PIN_SEL 0x7 +#define BIT_PCM0_PIN_SEL(x) (((x) & BIT_MASK_PCM0_PIN_SEL) << BIT_SHIFT_PCM0_PIN_SEL) + +#define BIT_PCM0_PIN_EN BIT(16) + +//2 REG_NOT_VALID + +#define BIT_SHIFT_I2S1_PIN_SEL 6 +#define BIT_MASK_I2S1_PIN_SEL 0x3 +#define BIT_I2S1_PIN_SEL(x) (((x) & BIT_MASK_I2S1_PIN_SEL) << BIT_SHIFT_I2S1_PIN_SEL) + +#define BIT_I2S1_MCK_EN BIT(5) +#define BIT_I2S1_PIN_EN BIT(4) + +#define BIT_SHIFT_I2S0_PIN_SEL 2 +#define BIT_MASK_I2S0_PIN_SEL 0x3 +#define BIT_I2S0_PIN_SEL(x) (((x) & BIT_MASK_I2S0_PIN_SEL) << BIT_SHIFT_I2S0_PIN_SEL) + +#define BIT_I2S0_MCK_EN BIT(1) +#define BIT_I2S0_PIN_EN BIT(0) + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_HCI_PINMUX_CTRL +#define BIT_HCI_MII_PIN_EN BIT(24) +#define BIT_HCI_SDIOH_PIN_EN BIT(1) +#define BIT_HCI_SDIOD_PIN_EN BIT(0) + +//2 REG_WL_PINMUX_CTRL +#define BIT_NFC_PIN_EN BIT(16) +#define BIT_WL_BTCMD_PIN_EN BIT(13) +#define BIT_WL_BTCOEX_PIN_EN BIT(12) +#define BIT_WL_ANT1_PIN_EN BIT(9) +#define BIT_WL_ANT0_PIN_EN BIT(8) + +#define BIT_SHIFT_WL_LED_PIN_SEL 1 +#define BIT_MASK_WL_LED_PIN_SEL 0x3 +#define BIT_WL_LED_PIN_SEL(x) (((x) & BIT_MASK_WL_LED_PIN_SEL) << BIT_SHIFT_WL_LED_PIN_SEL) + +#define BIT_WL_LED_PIN_EN BIT(0) + +//2 REG_BT_PINMUX_CTRL + +//2 REG_PWM_PINMUX_CTRL + +#define BIT_SHIFT_ETE3_PIN_SEL 29 +#define BIT_MASK_ETE3_PIN_SEL 0x3 +#define BIT_ETE3_PIN_SEL(x) (((x) & BIT_MASK_ETE3_PIN_SEL) << BIT_SHIFT_ETE3_PIN_SEL) + +#define BIT_ETE3_PIN_EN BIT(28) + +#define BIT_SHIFT_ETE2_PIN_SEL 25 +#define BIT_MASK_ETE2_PIN_SEL 0x3 +#define BIT_ETE2_PIN_SEL(x) (((x) & BIT_MASK_ETE2_PIN_SEL) << BIT_SHIFT_ETE2_PIN_SEL) + +#define BIT_ETE2_PIN_EN BIT(24) + +#define BIT_SHIFT_ETE1_PIN_SEL 21 +#define BIT_MASK_ETE1_PIN_SEL 0x3 +#define BIT_ETE1_PIN_SEL(x) (((x) & BIT_MASK_ETE1_PIN_SEL) << BIT_SHIFT_ETE1_PIN_SEL) + +#define BIT_ETE1_PIN_EN BIT(20) + +#define BIT_SHIFT_ETE0_PIN_SEL 17 +#define BIT_MASK_ETE0_PIN_SEL 0x3 +#define BIT_ETE0_PIN_SEL(x) (((x) & BIT_MASK_ETE0_PIN_SEL) << BIT_SHIFT_ETE0_PIN_SEL) + +#define BIT_ETE0_PIN_EN BIT(16) + +#define BIT_SHIFT_PWM3_PIN_SEL 13 +#define BIT_MASK_PWM3_PIN_SEL 0x3 +#define BIT_PWM3_PIN_SEL(x) (((x) & BIT_MASK_PWM3_PIN_SEL) << BIT_SHIFT_PWM3_PIN_SEL) + +#define BIT_PWM3_PIN_EN BIT(12) + +#define BIT_SHIFT_PWM2_PIN_SEL 9 +#define BIT_MASK_PWM2_PIN_SEL 0x3 +#define BIT_PWM2_PIN_SEL(x) (((x) & BIT_MASK_PWM2_PIN_SEL) << BIT_SHIFT_PWM2_PIN_SEL) + +#define BIT_PWM2_PIN_EN BIT(8) + +#define BIT_SHIFT_PWM1_PIN_SEL 5 +#define BIT_MASK_PWM1_PIN_SEL 0x3 +#define BIT_PWM1_PIN_SEL(x) (((x) & BIT_MASK_PWM1_PIN_SEL) << BIT_SHIFT_PWM1_PIN_SEL) + +#define BIT_PWM1_PIN_EN BIT(4) + +#define BIT_SHIFT_PWM0_PIN_SEL 1 +#define BIT_MASK_PWM0_PIN_SEL 0x3 +#define BIT_PWM0_PIN_SEL(x) (((x) & BIT_MASK_PWM0_PIN_SEL) << BIT_SHIFT_PWM0_PIN_SEL) + +#define BIT_PWM0_PIN_EN BIT(0) + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_CPU_PERIPHERAL_CTRL + +#define BIT_SHIFT_LOG_UART_PIN_SEL 22 +#define BIT_MASK_LOG_UART_PIN_SEL 0x3 +#define BIT_LOG_UART_PIN_SEL(x) (((x) & BIT_MASK_LOG_UART_PIN_SEL) << BIT_SHIFT_LOG_UART_PIN_SEL) + +#define BIT_LOG_UART_IR_EN BIT(21) +#define BIT_LOG_UART_PIN_EN BIT(20) +#define BIT_TRACE_PIN_EN BIT(17) +#define BIT_SDR_PIN_EN BIT(4) + +#define BIT_SHIFT_SPI_FLSH_PIN_SEL 1 +#define BIT_MASK_SPI_FLSH_PIN_SEL 0x3 +#define BIT_SPI_FLSH_PIN_SEL(x) (((x) & BIT_MASK_SPI_FLSH_PIN_SEL) << BIT_SHIFT_SPI_FLSH_PIN_SEL) + +#define BIT_SPI_FLSH_PIN_EN BIT(0) + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_HCI_CTRL_STATUS_0 + +//2 REG_HCI_CTRL_STATUS_1 + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_PESOC_MEM_CTRL + +#define BIT_SHIFT_PESOC_SDR_DDL_CTRL 16 +#define BIT_MASK_PESOC_SDR_DDL_CTRL 0xff +#define BIT_PESOC_SDR_DDL_CTRL(x) (((x) & BIT_MASK_PESOC_SDR_DDL_CTRL) << BIT_SHIFT_PESOC_SDR_DDL_CTRL) + + +#define BIT_SHIFT_PESOC_FLASH_DDL_CTRL 0 +#define BIT_MASK_PESOC_FLASH_DDL_CTRL 0xff +#define BIT_PESOC_FLASH_DDL_CTRL(x) (((x) & BIT_MASK_PESOC_FLASH_DDL_CTRL) << BIT_SHIFT_PESOC_FLASH_DDL_CTRL) + + +//2 REG_PESOC_SOC_CTRL + +#define BIT_SHIFT_PESOC_GDMA_CFG 16 +#define BIT_MASK_PESOC_GDMA_CFG 0x1fff +#define BIT_PESOC_GDMA_CFG(x) (((x) & BIT_MASK_PESOC_GDMA_CFG) << BIT_SHIFT_PESOC_GDMA_CFG) + +#define BIT_PESOC_MII_LX_SLV_SWAP_SEL BIT(13) +#define BIT_PESOC_MII_LX_MST_SWAP_SEL BIT(12) +#define BIT_PESOC_MII_LX_WRAPPER_EN BIT(11) +#define BIT_PESOC_LX_SLV_SWAP_SEL BIT(10) +#define BIT_PESOC_LX_MST_SWAP_SEL BIT(9) +#define BIT_PESOC_LX_WL_SWAP_SEL BIT(8) + +#define BIT_SHIFT_PESOC_SRAM_MUX_CFG 0 +#define BIT_MASK_PESOC_SRAM_MUX_CFG 0x7 +#define BIT_PESOC_SRAM_MUX_CFG(x) (((x) & BIT_MASK_PESOC_SRAM_MUX_CFG) << BIT_SHIFT_PESOC_SRAM_MUX_CFG) + + +//2 REG_PESOC_PERI_CTRL +#define BIT_SOC_FUNC_SPI_RN BIT(8) + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID +#define BIT_FW_CTRL_INT0 BIT(24) + +//2 REG_NOT_VALID + +//2 REG_GPIO_SHTDN_CTRL +#define BIT_GPIO_GPK_SHTDN_N BIT(10) +#define BIT_GPIO_GPJ_SHTDN_N BIT(9) +#define BIT_GPIO_GPI_SHTDN_N BIT(8) +#define BIT_GPIO_GPH_SHTDN_N BIT(7) +#define BIT_GPIO_GPG_SHTDN_N BIT(6) +#define BIT_GPIO_GPF_SHTDN_N BIT(5) +#define BIT_GPIO_GPE_SHTDN_N BIT(4) +#define BIT_GPIO_GPD_SHTDN_N BIT(3) +#define BIT_GPIO_GPC_SHTDN_N BIT(2) +#define BIT_GPIO_GPB_SHTDN_N BIT(1) +#define BIT_GPIO_GPA_SHTDN_N BIT(0) + +//2 REG_GPIO_DRIVING_CTRL +#define BIT_GPIO_GPK_DRV_SEL BIT(20) +#define BIT_GPIO_GPJ_DRV_SEL BIT(18) +#define BIT_GPIO_GPI_DRV_SEL BIT(16) +#define BIT_GPIO_GPH_DRV_SEL BIT(14) +#define BIT_GPIO_GPG_DRV_SEL BIT(12) +#define BIT_GPIO_GPF_DRV_SEL BIT(10) +#define BIT_GPIO_GPE_DRV_SEL BIT(8) +#define BIT_GPIO_GPD_DRV_SEL BIT(6) +#define BIT_GPIO_GPC_DRV_SEL BIT(4) +#define BIT_GPIO_GPB_DRV_SEL BIT(2) +#define BIT_GPIO_GPA_DRV_SEL BIT(0) + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_GPIO_PULL_CTRL0 + +#define BIT_SHIFT_GPIO_GPB7_PULL_CTRL 30 +#define BIT_MASK_GPIO_GPB7_PULL_CTRL 0x3 +#define BIT_GPIO_GPB7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB7_PULL_CTRL) << BIT_SHIFT_GPIO_GPB7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPB6_PULL_CTRL 28 +#define BIT_MASK_GPIO_GPB6_PULL_CTRL 0x3 +#define BIT_GPIO_GPB6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB6_PULL_CTRL) << BIT_SHIFT_GPIO_GPB6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPB5_PULL_CTRL 26 +#define BIT_MASK_GPIO_GPB5_PULL_CTRL 0x3 +#define BIT_GPIO_GPB5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB5_PULL_CTRL) << BIT_SHIFT_GPIO_GPB5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPB4_PULL_CTRL 24 +#define BIT_MASK_GPIO_GPB4_PULL_CTRL 0x3 +#define BIT_GPIO_GPB4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB4_PULL_CTRL) << BIT_SHIFT_GPIO_GPB4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPB3_PULL_CTRL 22 +#define BIT_MASK_GPIO_GPB3_PULL_CTRL 0x3 +#define BIT_GPIO_GPB3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB3_PULL_CTRL) << BIT_SHIFT_GPIO_GPB3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPB2_PULL_CTRL 20 +#define BIT_MASK_GPIO_GPB2_PULL_CTRL 0x3 +#define BIT_GPIO_GPB2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB2_PULL_CTRL) << BIT_SHIFT_GPIO_GPB2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPB1_PULL_CTRL 18 +#define BIT_MASK_GPIO_GPB1_PULL_CTRL 0x3 +#define BIT_GPIO_GPB1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB1_PULL_CTRL) << BIT_SHIFT_GPIO_GPB1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPB0_PULL_CTRL 16 +#define BIT_MASK_GPIO_GPB0_PULL_CTRL 0x3 +#define BIT_GPIO_GPB0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPB0_PULL_CTRL) << BIT_SHIFT_GPIO_GPB0_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA7_PULL_CTRL 14 +#define BIT_MASK_GPIO_GPA7_PULL_CTRL 0x3 +#define BIT_GPIO_GPA7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA7_PULL_CTRL) << BIT_SHIFT_GPIO_GPA7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA6_PULL_CTRL 12 +#define BIT_MASK_GPIO_GPA6_PULL_CTRL 0x3 +#define BIT_GPIO_GPA6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA6_PULL_CTRL) << BIT_SHIFT_GPIO_GPA6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA5_PULL_CTRL 10 +#define BIT_MASK_GPIO_GPA5_PULL_CTRL 0x3 +#define BIT_GPIO_GPA5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA5_PULL_CTRL) << BIT_SHIFT_GPIO_GPA5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA4_PULL_CTRL 8 +#define BIT_MASK_GPIO_GPA4_PULL_CTRL 0x3 +#define BIT_GPIO_GPA4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA4_PULL_CTRL) << BIT_SHIFT_GPIO_GPA4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA3_PULL_CTRL 6 +#define BIT_MASK_GPIO_GPA3_PULL_CTRL 0x3 +#define BIT_GPIO_GPA3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA3_PULL_CTRL) << BIT_SHIFT_GPIO_GPA3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA2_PULL_CTRL 4 +#define BIT_MASK_GPIO_GPA2_PULL_CTRL 0x3 +#define BIT_GPIO_GPA2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA2_PULL_CTRL) << BIT_SHIFT_GPIO_GPA2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA1_PULL_CTRL 2 +#define BIT_MASK_GPIO_GPA1_PULL_CTRL 0x3 +#define BIT_GPIO_GPA1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA1_PULL_CTRL) << BIT_SHIFT_GPIO_GPA1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPA0_PULL_CTRL 0 +#define BIT_MASK_GPIO_GPA0_PULL_CTRL 0x3 +#define BIT_GPIO_GPA0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPA0_PULL_CTRL) << BIT_SHIFT_GPIO_GPA0_PULL_CTRL) + + +//2 REG_GPIO_PULL_CTRL1 + +#define BIT_SHIFT_GPIO_GPD7_PULL_CTRL 29 +#define BIT_MASK_GPIO_GPD7_PULL_CTRL 0x7 +#define BIT_GPIO_GPD7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD7_PULL_CTRL) << BIT_SHIFT_GPIO_GPD7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD6_PULL_CTRL 28 +#define BIT_MASK_GPIO_GPD6_PULL_CTRL 0x3 +#define BIT_GPIO_GPD6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD6_PULL_CTRL) << BIT_SHIFT_GPIO_GPD6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD5_PULL_CTRL 26 +#define BIT_MASK_GPIO_GPD5_PULL_CTRL 0x3 +#define BIT_GPIO_GPD5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD5_PULL_CTRL) << BIT_SHIFT_GPIO_GPD5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD4_PULL_CTRL 24 +#define BIT_MASK_GPIO_GPD4_PULL_CTRL 0x3 +#define BIT_GPIO_GPD4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD4_PULL_CTRL) << BIT_SHIFT_GPIO_GPD4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD3_PULL_CTRL 22 +#define BIT_MASK_GPIO_GPD3_PULL_CTRL 0x3 +#define BIT_GPIO_GPD3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD3_PULL_CTRL) << BIT_SHIFT_GPIO_GPD3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD2_PULL_CTRL 20 +#define BIT_MASK_GPIO_GPD2_PULL_CTRL 0x3 +#define BIT_GPIO_GPD2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD2_PULL_CTRL) << BIT_SHIFT_GPIO_GPD2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD1_PULL_CTRL 18 +#define BIT_MASK_GPIO_GPD1_PULL_CTRL 0x3 +#define BIT_GPIO_GPD1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD1_PULL_CTRL) << BIT_SHIFT_GPIO_GPD1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD0_PULL_CTRL 16 +#define BIT_MASK_GPIO_GPD0_PULL_CTRL 0x3 +#define BIT_GPIO_GPD0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD0_PULL_CTRL) << BIT_SHIFT_GPIO_GPD0_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC7_PULL_CTRL 14 +#define BIT_MASK_GPIO_GPC7_PULL_CTRL 0x3 +#define BIT_GPIO_GPC7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC7_PULL_CTRL) << BIT_SHIFT_GPIO_GPC7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC6_PULL_CTRL 12 +#define BIT_MASK_GPIO_GPC6_PULL_CTRL 0x3 +#define BIT_GPIO_GPC6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC6_PULL_CTRL) << BIT_SHIFT_GPIO_GPC6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC5_PULL_CTRL 10 +#define BIT_MASK_GPIO_GPC5_PULL_CTRL 0x3 +#define BIT_GPIO_GPC5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC5_PULL_CTRL) << BIT_SHIFT_GPIO_GPC5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC4_PULL_CTRL 8 +#define BIT_MASK_GPIO_GPC4_PULL_CTRL 0x3 +#define BIT_GPIO_GPC4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC4_PULL_CTRL) << BIT_SHIFT_GPIO_GPC4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC3_PULL_CTRL 6 +#define BIT_MASK_GPIO_GPC3_PULL_CTRL 0x3 +#define BIT_GPIO_GPC3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC3_PULL_CTRL) << BIT_SHIFT_GPIO_GPC3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC2_PULL_CTRL 4 +#define BIT_MASK_GPIO_GPC2_PULL_CTRL 0x3 +#define BIT_GPIO_GPC2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC2_PULL_CTRL) << BIT_SHIFT_GPIO_GPC2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC1_PULL_CTRL 2 +#define BIT_MASK_GPIO_GPC1_PULL_CTRL 0x3 +#define BIT_GPIO_GPC1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC1_PULL_CTRL) << BIT_SHIFT_GPIO_GPC1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC0_PULL_CTRL 0 +#define BIT_MASK_GPIO_GPC0_PULL_CTRL 0x3 +#define BIT_GPIO_GPC0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC0_PULL_CTRL) << BIT_SHIFT_GPIO_GPC0_PULL_CTRL) + + +//2 REG_GPIO_PULL_CTRL2 + +#define BIT_SHIFT_GPIO_GPF5_PULL_CTRL 26 +#define BIT_MASK_GPIO_GPF5_PULL_CTRL 0x3 +#define BIT_GPIO_GPF5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF5_PULL_CTRL) << BIT_SHIFT_GPIO_GPF5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPF4_PULL_CTRL 24 +#define BIT_MASK_GPIO_GPF4_PULL_CTRL 0x3 +#define BIT_GPIO_GPF4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF4_PULL_CTRL) << BIT_SHIFT_GPIO_GPF4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPF3_PULL_CTRL 22 +#define BIT_MASK_GPIO_GPF3_PULL_CTRL 0x3 +#define BIT_GPIO_GPF3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF3_PULL_CTRL) << BIT_SHIFT_GPIO_GPF3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPF2_PULL_CTRL 20 +#define BIT_MASK_GPIO_GPF2_PULL_CTRL 0x3 +#define BIT_GPIO_GPF2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF2_PULL_CTRL) << BIT_SHIFT_GPIO_GPF2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPF1_PULL_CTRL 18 +#define BIT_MASK_GPIO_GPF1_PULL_CTRL 0x3 +#define BIT_GPIO_GPF1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF1_PULL_CTRL) << BIT_SHIFT_GPIO_GPF1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPF0_PULL_CTRL 16 +#define BIT_MASK_GPIO_GPF0_PULL_CTRL 0x3 +#define BIT_GPIO_GPF0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPF0_PULL_CTRL) << BIT_SHIFT_GPIO_GPF0_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE7_PULL_CTRL 14 +#define BIT_MASK_GPIO_GPE7_PULL_CTRL 0x3 +#define BIT_GPIO_GPE7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE7_PULL_CTRL) << BIT_SHIFT_GPIO_GPE7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE6_PULL_CTRL 12 +#define BIT_MASK_GPIO_GPE6_PULL_CTRL 0x3 +#define BIT_GPIO_GPE6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE6_PULL_CTRL) << BIT_SHIFT_GPIO_GPE6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE5_PULL_CTRL 10 +#define BIT_MASK_GPIO_GPE5_PULL_CTRL 0x3 +#define BIT_GPIO_GPE5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE5_PULL_CTRL) << BIT_SHIFT_GPIO_GPE5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE4_PULL_CTRL 8 +#define BIT_MASK_GPIO_GPE4_PULL_CTRL 0x3 +#define BIT_GPIO_GPE4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE4_PULL_CTRL) << BIT_SHIFT_GPIO_GPE4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE3_PULL_CTRL 6 +#define BIT_MASK_GPIO_GPE3_PULL_CTRL 0x3 +#define BIT_GPIO_GPE3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE3_PULL_CTRL) << BIT_SHIFT_GPIO_GPE3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE2_PULL_CTRL 4 +#define BIT_MASK_GPIO_GPE2_PULL_CTRL 0x3 +#define BIT_GPIO_GPE2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE2_PULL_CTRL) << BIT_SHIFT_GPIO_GPE2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE1_PULL_CTRL 2 +#define BIT_MASK_GPIO_GPE1_PULL_CTRL 0x3 +#define BIT_GPIO_GPE1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE1_PULL_CTRL) << BIT_SHIFT_GPIO_GPE1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE0_PULL_CTRL 0 +#define BIT_MASK_GPIO_GPE0_PULL_CTRL 0x3 +#define BIT_GPIO_GPE0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE0_PULL_CTRL) << BIT_SHIFT_GPIO_GPE0_PULL_CTRL) + + +//2 REG_NOT_VALID + +#define BIT_SHIFT_GPIO_GPH7_PULL_CTRL 30 +#define BIT_MASK_GPIO_GPH7_PULL_CTRL 0x3 +#define BIT_GPIO_GPH7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH7_PULL_CTRL) << BIT_SHIFT_GPIO_GPH7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPH6_PULL_CTRL 28 +#define BIT_MASK_GPIO_GPH6_PULL_CTRL 0x3 +#define BIT_GPIO_GPH6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH6_PULL_CTRL) << BIT_SHIFT_GPIO_GPH6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPH5_PULL_CTRL 26 +#define BIT_MASK_GPIO_GPH5_PULL_CTRL 0x3 +#define BIT_GPIO_GPH5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH5_PULL_CTRL) << BIT_SHIFT_GPIO_GPH5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPH4_PULL_CTRL 24 +#define BIT_MASK_GPIO_GPH4_PULL_CTRL 0x3 +#define BIT_GPIO_GPH4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH4_PULL_CTRL) << BIT_SHIFT_GPIO_GPH4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPH3_PULL_CTRL 22 +#define BIT_MASK_GPIO_GPH3_PULL_CTRL 0x3 +#define BIT_GPIO_GPH3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH3_PULL_CTRL) << BIT_SHIFT_GPIO_GPH3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPH2_PULL_CTRL 20 +#define BIT_MASK_GPIO_GPH2_PULL_CTRL 0x3 +#define BIT_GPIO_GPH2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH2_PULL_CTRL) << BIT_SHIFT_GPIO_GPH2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPH1_PULL_CTRL 18 +#define BIT_MASK_GPIO_GPH1_PULL_CTRL 0x3 +#define BIT_GPIO_GPH1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH1_PULL_CTRL) << BIT_SHIFT_GPIO_GPH1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPH0_PULL_CTRL 16 +#define BIT_MASK_GPIO_GPH0_PULL_CTRL 0x3 +#define BIT_GPIO_GPH0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPH0_PULL_CTRL) << BIT_SHIFT_GPIO_GPH0_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG7_PULL_CTRL 14 +#define BIT_MASK_GPIO_GPG7_PULL_CTRL 0x3 +#define BIT_GPIO_GPG7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG7_PULL_CTRL) << BIT_SHIFT_GPIO_GPG7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG6_PULL_CTRL 12 +#define BIT_MASK_GPIO_GPG6_PULL_CTRL 0x3 +#define BIT_GPIO_GPG6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG6_PULL_CTRL) << BIT_SHIFT_GPIO_GPG6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG5_PULL_CTRL 10 +#define BIT_MASK_GPIO_GPG5_PULL_CTRL 0x3 +#define BIT_GPIO_GPG5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG5_PULL_CTRL) << BIT_SHIFT_GPIO_GPG5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG4_PULL_CTRL 8 +#define BIT_MASK_GPIO_GPG4_PULL_CTRL 0x3 +#define BIT_GPIO_GPG4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG4_PULL_CTRL) << BIT_SHIFT_GPIO_GPG4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG3_PULL_CTRL 6 +#define BIT_MASK_GPIO_GPG3_PULL_CTRL 0x3 +#define BIT_GPIO_GPG3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG3_PULL_CTRL) << BIT_SHIFT_GPIO_GPG3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG2_PULL_CTRL 4 +#define BIT_MASK_GPIO_GPG2_PULL_CTRL 0x3 +#define BIT_GPIO_GPG2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG2_PULL_CTRL) << BIT_SHIFT_GPIO_GPG2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG1_PULL_CTRL 2 +#define BIT_MASK_GPIO_GPG1_PULL_CTRL 0x3 +#define BIT_GPIO_GPG1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG1_PULL_CTRL) << BIT_SHIFT_GPIO_GPG1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPG0_PULL_CTRL 0 +#define BIT_MASK_GPIO_GPG0_PULL_CTRL 0x3 +#define BIT_GPIO_GPG0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPG0_PULL_CTRL) << BIT_SHIFT_GPIO_GPG0_PULL_CTRL) + + +//2 REG_GPIO_PULL_CTRL4 + +#define BIT_SHIFT_GPIO_GPJ6_PULL_CTRL 28 +#define BIT_MASK_GPIO_GPJ6_PULL_CTRL 0x3 +#define BIT_GPIO_GPJ6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ6_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPJ5_PULL_CTRL 26 +#define BIT_MASK_GPIO_GPJ5_PULL_CTRL 0x3 +#define BIT_GPIO_GPJ5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ5_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPJ4_PULL_CTRL 24 +#define BIT_MASK_GPIO_GPJ4_PULL_CTRL 0x3 +#define BIT_GPIO_GPJ4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ4_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPJ3_PULL_CTRL 22 +#define BIT_MASK_GPIO_GPJ3_PULL_CTRL 0x3 +#define BIT_GPIO_GPJ3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ3_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPJ2_PULL_CTRL 20 +#define BIT_MASK_GPIO_GPJ2_PULL_CTRL 0x3 +#define BIT_GPIO_GPJ2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ2_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPJ1_PULL_CTRL 18 +#define BIT_MASK_GPIO_GPJ1_PULL_CTRL 0x3 +#define BIT_GPIO_GPJ1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ1_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPJ0_PULL_CTRL 16 +#define BIT_MASK_GPIO_GPJ0_PULL_CTRL 0x3 +#define BIT_GPIO_GPJ0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPJ0_PULL_CTRL) << BIT_SHIFT_GPIO_GPJ0_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI7_PULL_CTRL 14 +#define BIT_MASK_GPIO_GPI7_PULL_CTRL 0x3 +#define BIT_GPIO_GPI7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI7_PULL_CTRL) << BIT_SHIFT_GPIO_GPI7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI6_PULL_CTRL 12 +#define BIT_MASK_GPIO_GPI6_PULL_CTRL 0x3 +#define BIT_GPIO_GPI6_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI6_PULL_CTRL) << BIT_SHIFT_GPIO_GPI6_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI5_PULL_CTRL 10 +#define BIT_MASK_GPIO_GPI5_PULL_CTRL 0x3 +#define BIT_GPIO_GPI5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI5_PULL_CTRL) << BIT_SHIFT_GPIO_GPI5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI4_PULL_CTRL 8 +#define BIT_MASK_GPIO_GPI4_PULL_CTRL 0x3 +#define BIT_GPIO_GPI4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI4_PULL_CTRL) << BIT_SHIFT_GPIO_GPI4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI3_PULL_CTRL 6 +#define BIT_MASK_GPIO_GPI3_PULL_CTRL 0x3 +#define BIT_GPIO_GPI3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI3_PULL_CTRL) << BIT_SHIFT_GPIO_GPI3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI2_PULL_CTRL 4 +#define BIT_MASK_GPIO_GPI2_PULL_CTRL 0x3 +#define BIT_GPIO_GPI2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI2_PULL_CTRL) << BIT_SHIFT_GPIO_GPI2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI1_PULL_CTRL 2 +#define BIT_MASK_GPIO_GPI1_PULL_CTRL 0x3 +#define BIT_GPIO_GPI1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI1_PULL_CTRL) << BIT_SHIFT_GPIO_GPI1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPI0_PULL_CTRL 0 +#define BIT_MASK_GPIO_GPI0_PULL_CTRL 0x3 +#define BIT_GPIO_GPI0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPI0_PULL_CTRL) << BIT_SHIFT_GPIO_GPI0_PULL_CTRL) + + +//2 REG_GPIO_PULL_CTRL5 + +#define BIT_SHIFT_GPIO_GPEA_PULL_CTRL 20 +#define BIT_MASK_GPIO_GPEA_PULL_CTRL 0x3 +#define BIT_GPIO_GPEA_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPEA_PULL_CTRL) << BIT_SHIFT_GPIO_GPEA_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE9_PULL_CTRL 18 +#define BIT_MASK_GPIO_GPE9_PULL_CTRL 0x3 +#define BIT_GPIO_GPE9_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE9_PULL_CTRL) << BIT_SHIFT_GPIO_GPE9_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPE8_PULL_CTRL 16 +#define BIT_MASK_GPIO_GPE8_PULL_CTRL 0x3 +#define BIT_GPIO_GPE8_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPE8_PULL_CTRL) << BIT_SHIFT_GPIO_GPE8_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPK7_PULL_CTRL 12 +#define BIT_MASK_GPIO_GPK7_PULL_CTRL 0x3 +#define BIT_GPIO_GPK7_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK7_PULL_CTRL) << BIT_SHIFT_GPIO_GPK7_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPK5_PULL_CTRL 10 +#define BIT_MASK_GPIO_GPK5_PULL_CTRL 0x3 +#define BIT_GPIO_GPK5_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK5_PULL_CTRL) << BIT_SHIFT_GPIO_GPK5_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPK4_PULL_CTRL 8 +#define BIT_MASK_GPIO_GPK4_PULL_CTRL 0x3 +#define BIT_GPIO_GPK4_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK4_PULL_CTRL) << BIT_SHIFT_GPIO_GPK4_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPK3_PULL_CTRL 6 +#define BIT_MASK_GPIO_GPK3_PULL_CTRL 0x3 +#define BIT_GPIO_GPK3_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK3_PULL_CTRL) << BIT_SHIFT_GPIO_GPK3_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPK2_PULL_CTRL 4 +#define BIT_MASK_GPIO_GPK2_PULL_CTRL 0x3 +#define BIT_GPIO_GPK2_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK2_PULL_CTRL) << BIT_SHIFT_GPIO_GPK2_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPK1_PULL_CTRL 2 +#define BIT_MASK_GPIO_GPK1_PULL_CTRL 0x3 +#define BIT_GPIO_GPK1_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK1_PULL_CTRL) << BIT_SHIFT_GPIO_GPK1_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPK0_PULL_CTRL 0 +#define BIT_MASK_GPIO_GPK0_PULL_CTRL 0x3 +#define BIT_GPIO_GPK0_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPK0_PULL_CTRL) << BIT_SHIFT_GPIO_GPK0_PULL_CTRL) + + +//2 REG_GPIO_PULL_CTRL6 + +#define BIT_SHIFT_GPIO_GPD9_PULL_CTRL 18 +#define BIT_MASK_GPIO_GPD9_PULL_CTRL 0x3 +#define BIT_GPIO_GPD9_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD9_PULL_CTRL) << BIT_SHIFT_GPIO_GPD9_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPD8_PULL_CTRL 16 +#define BIT_MASK_GPIO_GPD8_PULL_CTRL 0x3 +#define BIT_GPIO_GPD8_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPD8_PULL_CTRL) << BIT_SHIFT_GPIO_GPD8_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC9_PULL_CTRL 2 +#define BIT_MASK_GPIO_GPC9_PULL_CTRL 0x3 +#define BIT_GPIO_GPC9_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC9_PULL_CTRL) << BIT_SHIFT_GPIO_GPC9_PULL_CTRL) + + +#define BIT_SHIFT_GPIO_GPC8_PULL_CTRL 0 +#define BIT_MASK_GPIO_GPC8_PULL_CTRL 0x3 +#define BIT_GPIO_GPC8_PULL_CTRL(x) (((x) & BIT_MASK_GPIO_GPC8_PULL_CTRL) << BIT_SHIFT_GPIO_GPC8_PULL_CTRL) + + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_PERI_PWM0_CTRL +#define BIT_PERI_PWM0_EN BIT(31) + +#define BIT_SHIFT_PERI_PWM0_GT_SEL 24 +#define BIT_MASK_PERI_PWM0_GT_SEL 0xf +#define BIT_PERI_PWM0_GT_SEL(x) (((x) & BIT_MASK_PERI_PWM0_GT_SEL) << BIT_SHIFT_PERI_PWM0_GT_SEL) + + +#define BIT_SHIFT_PERI_PWM0_DUTY 12 +#define BIT_MASK_PERI_PWM0_DUTY 0x3ff +#define BIT_PERI_PWM0_DUTY(x) (((x) & BIT_MASK_PERI_PWM0_DUTY) << BIT_SHIFT_PERI_PWM0_DUTY) + + +#define BIT_SHIFT_PERI_PWM0_PERIOD 0 +#define BIT_MASK_PERI_PWM0_PERIOD 0x3ff +#define BIT_PERI_PWM0_PERIOD(x) (((x) & BIT_MASK_PERI_PWM0_PERIOD) << BIT_SHIFT_PERI_PWM0_PERIOD) + + +//2 REG_PERI_PWM1_CTRL +#define BIT_PERI_PWM1_EN BIT(31) + +#define BIT_SHIFT_PERI_PWM1_GT_SEL 24 +#define BIT_MASK_PERI_PWM1_GT_SEL 0xf +#define BIT_PERI_PWM1_GT_SEL(x) (((x) & BIT_MASK_PERI_PWM1_GT_SEL) << BIT_SHIFT_PERI_PWM1_GT_SEL) + + +#define BIT_SHIFT_PERI_PWM1_DUTY 12 +#define BIT_MASK_PERI_PWM1_DUTY 0x3ff +#define BIT_PERI_PWM1_DUTY(x) (((x) & BIT_MASK_PERI_PWM1_DUTY) << BIT_SHIFT_PERI_PWM1_DUTY) + + +#define BIT_SHIFT_PERI_PWM1_PERIOD 0 +#define BIT_MASK_PERI_PWM1_PERIOD 0x3ff +#define BIT_PERI_PWM1_PERIOD(x) (((x) & BIT_MASK_PERI_PWM1_PERIOD) << BIT_SHIFT_PERI_PWM1_PERIOD) + + +//2 REG_PERI_PWM2_CTRL +#define BIT_PERI_PWM2_EN BIT(31) + +#define BIT_SHIFT_PERI_PWM2_GT_SEL 24 +#define BIT_MASK_PERI_PWM2_GT_SEL 0xf +#define BIT_PERI_PWM2_GT_SEL(x) (((x) & BIT_MASK_PERI_PWM2_GT_SEL) << BIT_SHIFT_PERI_PWM2_GT_SEL) + + +#define BIT_SHIFT_PERI_PWM2_DUTY 12 +#define BIT_MASK_PERI_PWM2_DUTY 0x3ff +#define BIT_PERI_PWM2_DUTY(x) (((x) & BIT_MASK_PERI_PWM2_DUTY) << BIT_SHIFT_PERI_PWM2_DUTY) + + +#define BIT_SHIFT_PERI_PWM2_PERIOD 0 +#define BIT_MASK_PERI_PWM2_PERIOD 0x3ff +#define BIT_PERI_PWM2_PERIOD(x) (((x) & BIT_MASK_PERI_PWM2_PERIOD) << BIT_SHIFT_PERI_PWM2_PERIOD) + + +//2 REG_PERI_PWM3_CTRL +#define BIT_PERI_PWM3_EN BIT(31) + +#define BIT_SHIFT_PERI_PWM3_GT_SEL 24 +#define BIT_MASK_PERI_PWM3_GT_SEL 0xf +#define BIT_PERI_PWM3_GT_SEL(x) (((x) & BIT_MASK_PERI_PWM3_GT_SEL) << BIT_SHIFT_PERI_PWM3_GT_SEL) + + +#define BIT_SHIFT_PERI_PWM3_DUTY 12 +#define BIT_MASK_PERI_PWM3_DUTY 0x3ff +#define BIT_PERI_PWM3_DUTY(x) (((x) & BIT_MASK_PERI_PWM3_DUTY) << BIT_SHIFT_PERI_PWM3_DUTY) + + +#define BIT_SHIFT_PERI_PWM3_PERIOD 0 +#define BIT_MASK_PERI_PWM3_PERIOD 0x3ff +#define BIT_PERI_PWM3_PERIOD(x) (((x) & BIT_MASK_PERI_PWM3_PERIOD) << BIT_SHIFT_PERI_PWM3_PERIOD) + + +//2 REG_PERI_TIM_EVT_CTRL +#define BIT_PERI_GT_EVT3_EN BIT(31) + +#define BIT_SHIFT_PERI_GT_EVT3_SRC_SEL 28 +#define BIT_MASK_PERI_GT_EVT3_SRC_SEL 0x7 +#define BIT_PERI_GT_EVT3_SRC_SEL(x) (((x) & BIT_MASK_PERI_GT_EVT3_SRC_SEL) << BIT_SHIFT_PERI_GT_EVT3_SRC_SEL) + + +#define BIT_SHIFT_PERI_GT_EVT3_PULSE_DUR 24 +#define BIT_MASK_PERI_GT_EVT3_PULSE_DUR 0xf +#define BIT_PERI_GT_EVT3_PULSE_DUR(x) (((x) & BIT_MASK_PERI_GT_EVT3_PULSE_DUR) << BIT_SHIFT_PERI_GT_EVT3_PULSE_DUR) + +#define BIT_PERI_GT_EVT2_EN BIT(23) + +#define BIT_SHIFT_PERI_GT_EVT2_SRC_SEL 20 +#define BIT_MASK_PERI_GT_EVT2_SRC_SEL 0x7 +#define BIT_PERI_GT_EVT2_SRC_SEL(x) (((x) & BIT_MASK_PERI_GT_EVT2_SRC_SEL) << BIT_SHIFT_PERI_GT_EVT2_SRC_SEL) + + +#define BIT_SHIFT_PERI_GT_EVT2_PULSE_DUR 16 +#define BIT_MASK_PERI_GT_EVT2_PULSE_DUR 0xf +#define BIT_PERI_GT_EVT2_PULSE_DUR(x) (((x) & BIT_MASK_PERI_GT_EVT2_PULSE_DUR) << BIT_SHIFT_PERI_GT_EVT2_PULSE_DUR) + +#define BIT_PERI_GT_EVT1_EN BIT(15) + +#define BIT_SHIFT_PERI_GT_EVT1_SRC_SEL 12 +#define BIT_MASK_PERI_GT_EVT1_SRC_SEL 0x7 +#define BIT_PERI_GT_EVT1_SRC_SEL(x) (((x) & BIT_MASK_PERI_GT_EVT1_SRC_SEL) << BIT_SHIFT_PERI_GT_EVT1_SRC_SEL) + + +#define BIT_SHIFT_PERI_GT_EVT1_PULSE_DUR 8 +#define BIT_MASK_PERI_GT_EVT1_PULSE_DUR 0xf +#define BIT_PERI_GT_EVT1_PULSE_DUR(x) (((x) & BIT_MASK_PERI_GT_EVT1_PULSE_DUR) << BIT_SHIFT_PERI_GT_EVT1_PULSE_DUR) + +#define BIT_PERI_GT_EVT0_EN BIT(7) + +#define BIT_SHIFT_PERI_GT_EVT0_SRC_SEL 4 +#define BIT_MASK_PERI_GT_EVT0_SRC_SEL 0x7 +#define BIT_PERI_GT_EVT0_SRC_SEL(x) (((x) & BIT_MASK_PERI_GT_EVT0_SRC_SEL) << BIT_SHIFT_PERI_GT_EVT0_SRC_SEL) + + +#define BIT_SHIFT_PERI_GT_EVT0_PULSE_DUR 0 +#define BIT_MASK_PERI_GT_EVT0_PULSE_DUR 0xf +#define BIT_PERI_GT_EVT0_PULSE_DUR(x) (((x) & BIT_MASK_PERI_GT_EVT0_PULSE_DUR) << BIT_SHIFT_PERI_GT_EVT0_PULSE_DUR) + + +//2 REG_PERI_EGTIM_CTRL + +#define BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL 12 +#define BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL 0x3 +#define BIT_PERI_EGTIM_PIN_GROUP2_OPT_SEL(x) (((x) & BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL) << BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL) + + +#define BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL 10 +#define BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL 0x3 +#define BIT_PERI_EGTIM_PIN_GROUP1_OPT_SEL(x) (((x) & BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL) << BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL) + + +#define BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL 8 +#define BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL 0x3 +#define BIT_PERI_EGTIM_PIN_GROUP0_OPT_SEL(x) (((x) & BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL) << BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL) + + +//2 REG_NOT_VALID + +#define BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL 4 +#define BIT_MASK_PERI_EGTIM_REF_SIG_SEL 0x3 +#define BIT_PERI_EGTIM_REF_SIG_SEL(x) (((x) & BIT_MASK_PERI_EGTIM_REF_SIG_SEL) << BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL) + +#define BIT_PERI_EGTIM_EN BIT(0) + +//2 REG_NOT_VALID + +//2 REG_PEON_CFG + +//2 REG_PEON_STATUS +#define BIT_PEON_SDIO_ALDN BIT(0) + + +//========== Register Address Definition ==================// +#define REG_PEON_PWR_CTRL 0x0200 +#define REG_PON_ISO_CTRL 0x0204 +#define REG_SOC_FUNC_EN 0x0210 +#define REG_SOC_HCI_COM_FUNC_EN 0x0214 +#define REG_SOC_PERI_FUNC0_EN 0x0218 +#define REG_SOC_PERI_FUNC1_EN 0x021C +#define REG_SOC_PERI_BD_FUNC0_EN 0x0220 +#define REG_PESOC_CLK_CTRL 0x0230 +#define REG_PESOC_PERI_CLK_CTRL0 0x0234 +#define REG_PESOC_PERI_CLK_CTRL1 0x0238 +#define REG_PESOC_CLK_CTRL3 0x023C +#define REG_PESOC_HCI_CLK_CTRL0 0x0240 +#define REG_PESOC_COM_CLK_CTRL1 0x0244 +#define REG_PESOC_HW_ENG_CLK_CTRL 0x0248 +#define REG_PESOC_CLK_SEL 0x0250 +#define REG_SYS_ANACK_CAL_CTRL 0x026C +#define REG_OSC32K_CTRL 0x0270 +#define REG_OSC32K_REG_CTRL0 0x0274 +#define REG_OSC32K_REG_CTRL1 0x0278 +#define REG_THERMAL_METER_CTRL 0x027C +#define REG_UART_MUX_CTRL 0x0280 +#define REG_SPI_MUX_CTRL 0x0284 +#define REG_I2C_MUX_CTRL 0x0288 +#define REG_I2S_MUX_CTRL 0x028C +#define REG_HCI_PINMUX_CTRL 0x02A0 +#define REG_WL_PINMUX_CTRL 0x02A4 +#define REG_BT_PINMUX_CTRL 0x02A8 +#define REG_PWM_PINMUX_CTRL 0x02AC +#define REG_CPU_PERIPHERAL_CTRL 0x02C0 +#define REG_HCI_CTRL_STATUS_0 0x02E0 +#define REG_HCI_CTRL_STATUS_1 0x02E4 +#define REG_PESOC_MEM_CTRL 0x0300 +#define REG_PESOC_SOC_CTRL 0x0304 +#define REG_PESOC_PERI_CTRL 0x0308 +#define REG_GPIO_SHTDN_CTRL 0x0320 +#define REG_GPIO_DRIVING_CTRL 0x0324 +#define REG_GPIO_PULL_CTRL0 0x0330 +#define REG_GPIO_PULL_CTRL1 0x0334 +#define REG_GPIO_PULL_CTRL2 0x0338 +#define REG_GPIO_PULL_CTRL3 0x033C +#define REG_GPIO_PULL_CTRL4 0x0340 +#define REG_GPIO_PULL_CTRL5 0x0344 +#define REG_GPIO_PULL_CTRL6 0x0348 +#define REG_PERI_PWM0_CTRL 0x0360 +#define REG_PERI_PWM1_CTRL 0x0364 +#define REG_PERI_PWM2_CTRL 0x0368 +#define REG_PERI_PWM3_CTRL 0x036C +#define REG_PERI_TIM_EVT_CTRL 0x0370 +#define REG_PERI_EGTIM_CTRL 0x0374 +#define REG_PEON_CFG 0x03F0 +#define REG_PEON_STATUS 0x03F4 + + +#endif // end of "#ifndef __INC_RTL8195A_PERI_ON_H" diff --git a/lib/fwlib/rtl8195a/rtl8195a_pwm.h b/lib/fwlib/rtl8195a/rtl8195a_pwm.h new file mode 100644 index 0000000..ddf166b --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_pwm.h @@ -0,0 +1,37 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _RTL8195A_PWM_H_ +#define _RTL8195A_PWM_H_ + +extern void +HAL_Pwm_SetDuty_8195a( + HAL_PWM_ADAPTER *pPwmAdapt, + u32 period, + u32 pulse_width +); + +extern HAL_Status +HAL_Pwm_Init_8195a( + HAL_PWM_ADAPTER *pPwmAdapt +); + +extern void +HAL_Pwm_Enable_8195a( + HAL_PWM_ADAPTER *pPwmAdapt +); + +extern void +HAL_Pwm_Disable_8195a( + HAL_PWM_ADAPTER *pPwmAdapt +); + + +#endif diff --git a/lib/fwlib/rtl8195a/rtl8195a_sdio.h b/lib/fwlib/rtl8195a/rtl8195a_sdio.h new file mode 100644 index 0000000..33ec5c4 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_sdio.h @@ -0,0 +1,1019 @@ + /* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _RTL8195A_SDIO_H_ +#define _RTL8195A_SDIO_H_ + +#include "hal_api.h" +#include "hal_util.h" +#if defined(CONFIG_SDIO_BOOT_SIM) || defined(CONFIG_SDIO_BOOT_ROM) +#define SDIO_BOOT_DRIVER 1 // is this SDIO driver works for booting +#else +#include "osdep_api.h" +#define SDIO_BOOT_DRIVER 0 // is this SDIO driver works for booting +#endif + +#if defined(__IAR_SYSTEMS_ICC__) //for IAR SDK +#include "autoconf.h" +#endif + +#ifndef CONFIG_INIC_EN +#define CONFIG_INIC_EN 0 +#endif +#if CONFIG_INIC_EN +#define CONFIG_INIC_SKB_TX 0 //use SKB for trx to improve the throughput +#define CONFIG_INIC_SKB_RX 0 +#endif + +#ifndef PRIORITIE_OFFSET //PRIORITIE_OFFSET in FreeRTOSConfig.h +#define PRIORITIE_OFFSET 0 +#endif + +#define SDIO_DEBUG 0 +#define SDIO_MP_MODE 0 // if includes MP mode function +#define SDIO_MAX_WAIT_RX_DMA 100 // Wait RX DMA done +#define SDIO_RX_PKT_SIZE_OVER_16K 0 /* is support SDIO RX packet size > 16K. if true, + a big packet will be transmited via multiple RX_BD */ +#define SDIO_MAILBOX_SIZE 10 // the maximum number of message block can be stored in this mailbox +#define SDIO_PERIODICAL_TIMER_INTERVAL 2000 // in ms, the interval of SDIO periodical timer +#define SDIO_AVG_TP_WIN_SIZE 20 // the number of entry to log the byte count for every periodical timer statistic, to calculate throughput + +#define HAL_SDIO_READ32(addr) HAL_READ32(SDIO_DEVICE_REG_BASE, addr) +#define HAL_SDIO_WRITE32(addr, value) HAL_WRITE32(SDIO_DEVICE_REG_BASE, addr, value) +#define HAL_SDIO_READ16(addr) HAL_READ16(SDIO_DEVICE_REG_BASE, addr) +#define HAL_SDIO_WRITE16(addr, value) HAL_WRITE16(SDIO_DEVICE_REG_BASE, addr, value) +#define HAL_SDIO_READ8(addr) HAL_READ8(SDIO_DEVICE_REG_BASE, addr) +#define HAL_SDIO_WRITE8(addr, value) HAL_WRITE8(SDIO_DEVICE_REG_BASE, addr, value) + +/***** Register Address *****/ +#define REG_SPDIO_TXBD_ADDR 0xA0 // 4 Bytes +#define REG_SPDIO_TXBD_SIZE 0xA4 // 4 Bytes +#define REG_SPDIO_TXBD_WPTR 0xA8 // 2 Bytes +#define REG_SPDIO_TXBD_RPTR 0xAC // 2 Bytes +#define REG_SPDIO_RXBD_ADDR 0xB0 // 4 Bytes +#define REG_SPDIO_RXBD_SIZE 0xB4 // 2 Bytes +#define REG_SPDIO_RXBD_C2H_WPTR 0xB6 // 2 Bytes +#define REG_SPDIO_RXBD_C2H_RPTR 0xB8 // 2 Bytes +#define REG_SPDIO_HCI_RX_REQ 0xBA // 1 Byte +#define REG_SPDIO_CPU_RST_DMA 0xBB // 1 Byte +#define REG_SPDIO_RX_REQ_ADDR 0xBC // 2 Bytes +#define REG_SPDIO_CPU_INT_MASK 0xC0 // 2 Bytes +#define REG_SPDIO_CPU_INT_STAS 0xC2 // 2 Bytes +#define REG_SPDIO_CCPWM 0xC4 // 1 Byts +#define REG_SPDIO_CPU_IND 0xC5 // 1 Byte +#define REG_SPDIO_CCPWM2 0xC6 // 2 Bytes +#define REG_SPDIO_CPU_H2C_MSG 0xC8 // 4 Bytes +#define REG_SPDIO_CPU_C2H_MSG 0xCC // 4 Bytes +#define REG_SPDIO_CRPWM 0xD0 // 1 Bytes +#define REG_SPDIO_CRPWM2 0xD2 // 2 Bytes +#define REG_SPDIO_AHB_DMA_CTRL 0xD4 // 4 Bytes +#define REG_SPDIO_RXBD_CNT 0xD8 // 4 Bytes +#define REG_SPDIO_TX_BUF_UNIT_SZ 0xD9 // 1 Bytes +#define REG_SPDIO_RX_BD_FREE_CNT 0xDA // 2 Bytes +#define REG_SPDIO_CPU_H2C_MSG_EXT 0xDC // 4 Bytes +#define REG_SPDIO_CPU_C2H_MSG_EXT 0xE0 // 4 Bytes + +// Register REG_SPDIO_CPU_RST_DMA +#define BIT_CPU_RST_SDIO_DMA BIT(7) + +// Register REG_SPDIO_CPU_INT_MASK, REG_SPDIO_CPU_INT_STAS +#define BIT_TXFIFO_H2C_OVF BIT(0) +#define BIT_H2C_BUS_RES_FAIL BIT(1) +#define BIT_H2C_DMA_OK BIT(2) +#define BIT_C2H_DMA_OK BIT(3) +#define BIT_H2C_MSG_INT BIT(4) +#define BIT_RPWM1_INT BIT(5) +#define BIT_RPWM2_INT BIT(6) +#define BIT_SDIO_RST_CMD_INT BIT(7) +#define BIT_RXBD_FLAG_ERR_INT BIT(8) +#define BIT_RX_BD_AVAI_INT BIT(9) +#define BIT_HOST_WAKE_CPU_INT BIT(10) + +// Register REG_SPDIO_CPU_IND +#define BIT_SYSTEM_TRX_RDY_IND BIT(0) + +// Register REG_SPDIO_HCI_RX_REQ +#define BIT_HCI_RX_REQ BIT(0) + +/* Register for SOC_HCI_COM_FUN_EN */ +#define BIT_SOC_HCI_SDIOD_OFF_EN BIT(1) // SDIO Function Block on Power_Off domain +#define BIT_SOC_HCI_SDIOD_ON_EN BIT(0) // SDIO Function Block on Power_On domain + +/* Register REG_PESOC_HCI_CLK_CTRL0 */ +#define BIT_SOC_SLPCK_SDIO_HST_EN BIT(3) // SDIO_HST clock enable when CPU sleep command +#define BIT_SOC_ACTCK_SDIO_HST_EN BIT(2) // SDIO_HST clock enable in CPU run mode +#define BIT_SOC_SLPCK_SDIO_DEV_EN BIT(1) // SDIO_DEV clock enable when CPU sleep command +#define BIT_SOC_ACTCK_SDIO_DEV_EN BIT(0) // SDIO_DEV clock enable in CPU run mode + +/***** Structer for each Register *****/ +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) +// Little Endian +// Register REG_SPDIO_HCI_RX_REQ @ 0xBA +typedef struct _SPDIO_HCI_RX_REQ { + u8 HCI_RX_REQ:1; /* bit[0], CPU trigger this bit to enable SDIO IP RX transfer by fetch BD info */ + u8 Reserved:7; /* bit[7:1], Reserved */ +} SPDIO_HCI_RX_REQ, *PSPDIO_HCI_RX_REQ; + +// Register REG_SPDIO_CPU_RST_DMA @ 0xBB +typedef struct _SPDIO_CPU_RST_DMA { + u8 Reserved:7; /* bit[6:0], Reserved */ + u8 CPU_RST_SDIO:1; /* bit[7], CPU set this bit to reset SDIO DMA */ +} SPDIO_CPU_RST_DMA, *PSPDIO_CPU_RST_DMA; + +// Register REG_SPDIO_CPU_INT_MASK @ 0xC0 +typedef struct _SPDIO_CPU_INT_MASK { + u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */ + u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */ + u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */ + u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */ + u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */ + u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */ + u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */ + u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */ + u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */ + u16 Reserved:7; /* bit[15:9], Reserved */ +} SPDIO_CPU_INT_MASK, *PSPDIO_CPU_INT_MASK; + +// Register REG_SPDIO_CPU_INT_STATUS @ 0xC2 +typedef struct _SPDIO_CPU_INT_STAS { + u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */ + u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */ + u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */ + u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */ + u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */ + u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */ + u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */ + u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */ + u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */ + u16 Reserved:7; /* bit[15:9], Reserved */ +} SPDIO_CPU_INT_STAS, *PSPDIO_CPU_INT_STAS; + +// Register REG_SPDIO_CCPWM @ 0xC4 +typedef struct _SPDIO_CCPWM { + u8 :1; /* bit[0] */ + u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */ + u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */ + u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */ + u8 Reserved:3; /* bit[6:4], Reserved */ + u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */ +} SPDIO_CCPWM, *PSPDIO_CCPWM; + +// Register REG_SPDIO_CPU_IND @ 0xC5 +typedef struct _SPDIO_CPU_IND { + u8 SYS_TRX_RDY:1; /* bit[0], To indicate the Host system that CPU is ready for TRX + , to be sync to 0x87[0] */ + u8 Reserved:7; /* bit[7:1], Reserved */ +} SPDIO_CPU_IND, *PSPDIO_CPU_IND; + +// Register REG_SPDIO_CPU_H2C_MSG @ 0xC8 +typedef struct _SPDIO_CPU_H2C_MSG { + u32 CPU_H2C_MSG:30; /* bit[30:0], Host CPU to FW message, sync from REG_SDIO_H2C_MSG */ + u32 Reserved:1; /* bit[31], Reserved */ +} SPDIO_CPU_H2C_MSG, *PSPDIO_CPU_H2C_MSG; + +// Register REG_SPDIO_CPU_C2H_MSG @ 0xCC +typedef struct _SPDIO_CPU_C2H_MSG { + u32 CPU_C2H_MSG:30; /* bit[30:0], FW to Host CPU message, sync to REG_SDIO_C2H_MSG */ + u32 Reserved:1; /* bit[31], Reserved */ +} SPDIO_CPU_C2H_MSG, *PSPDIO_CPU_C2H_MSG; + +// Register REG_SPDIO_CRPWM @ 0xD0 +typedef struct _SPDIO_CRPWM { + u8 :1; /* bit[0] */ + u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */ + u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */ + u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */ + u8 Reserved:3; /* bit[6:4], Reserved */ + u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */ +} SPDIO_CRPWM, *PSPDIO_CRPWM; + +// Register REG_SPDIO_AHB_DMA_CTRL @ 0xD4 +typedef struct _SPDIO_AHB_DMA_CTRL { + u32 TXFF_WLEVEL:7; /* bit[6:0], SPDIO TX FIFO water level */ + u32 :1; /* bit[7] */ + u32 RXFF_WLEVEL:7; /* bit[14:8], SPDIO RX FIFO water level */ + u32 :1; /* bit[15] */ + u32 AHB_DMA_CS:4; /* bit[19:16], AHB DMA state */ + u32 :1; /* bit[20] */ + u32 AHB_MASTER_RDY:1; /* bit[21], AHB Master Hready signal */ + u32 AHB_DMA_TRANS:2; /* bit[23:22], AHB DMA Trans value, for debugging */ + u32 AHB_BUSY_WAIT_CNT:4; /* bit[27:24], timeout for AHB controller to wait busy */ + u32 AHB_BURST_TYPE:3; /* bit[30:28], AHB burst type */ + u32 DISPATCH_TXAGG:1; /* bit[31], Enable to dispatch aggregated TX packet */ +} SPDIO_AHB_DMA_CTRL, *PSPDIO_AHB_DMA_CTRL; + +#else /* else of '#if LITTLE_ENDIAN' */ +// Big Endian +typedef struct _SPDIO_HCI_RX_REQ { + u8 Reserved:7; /* bit[7:1], Reserved */ + u8 HCI_RX_REQ:1; /* bit[0], CPU trigger this bit to enable SDIO IP RX transfer by fetch BD info */ +} SPDIO_HCI_RX_REQ, *PSPDIO_HCI_RX_REQ; + +// Register REG_SPDIO_CPU_RST_DMA @ 0xBB +typedef struct _SPDIO_CPU_RST_DMA { + u8 CPU_RST_SDIO:1; /* bit[7], CPU set this bit to reset SDIO DMA */ + u8 Reserved:7; /* bit[6:0], Reserved */ +} SPDIO_CPU_RST_DMA, *PSPDIO_CPU_RST_DMA; + +// Register REG_SPDIO_CPU_INT_MASK @ 0xC0 +typedef struct _SPDIO_CPU_INT_MASK { + u16 Reserved:7; /* bit[15:9], Reserved */ + u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */ + u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */ + u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */ + u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */ + u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */ + u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */ + u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */ + u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */ + u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */ +} SPDIO_CPU_INT_MASK, *PSPDIO_CPU_INT_MASK; + +// Register REG_SPDIO_CPU_INT_STAS @ 0xC2 +typedef struct _SPDIO_CPU_INT_STAS { + u16 Reserved:7; /* bit[15:9], Reserved */ + u16 BD_FLAG_ERR_INT:1; /* bit[8], set 0 to mask BD_FLAG_ERR_INT */ + u16 SDIO_RST_CMD_INT:1; /* bit[7], set 0 to mask SDIO_RST_CMD_INT */ + u16 RPWM2_INT:1; /* bit[6], set 0 to mask RPWM2_INT */ + u16 RPWM_INT:1; /* bit[5], set 0 to mask RPWM_INT */ + u16 H2C_MSG_INT:1; /* bit[4], set 0 to mask H2C_MSG_INT_INT */ + u16 C2H_DMA_OK:1; /* bit[3], set 0 to mask C2H_DMA_OK_INT */ + u16 H2C_DMA_OK:1; /* bit[2], set 0 to mask H2C_DMA_OK_INT */ + u16 H2C_BUS_RES_FAIL:1; /* bit[1], set 0 to mask H2C_BUS_RES_FAIL_INT */ + u16 TXFIFO_H2C_OVF:1; /* bit[0], set 0 to mask TXFIFO_H2C_OVF_INT */ +} SPDIO_CPU_INT_STAS, *PSPDIO_CPU_INT_STAS; + +// Register REG_SPDIO_CCPWM @ 0xC4 +typedef struct _SPDIO_CCPWM { + u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */ + u8 Reserved:3; /* bit[6:4], Reserved */ + u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */ + u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */ + u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */ + u8 :1; /* bit[0] */ +} SPDIO_CCPWM, *PSPDIO_CCPWM; + +// Register REG_SPDIO_CPU_IND @ 0xC5 +typedef struct _SPDIO_CPU_IND { + u8 Reserved:7; /* bit[7:1], Reserved */ + u8 SYS_TRX_RDY:1; /* bit[0], To indicate the Host system that CPU is ready for TRX + , to be sync to 0x87[0] */ +} SPDIO_CPU_IND, *PSPDIO_CPU_IND; + +// Register REG_SPDIO_CPU_H2C_MSG @ 0xC8 +typedef struct _SPDIO_CPU_H2C_MSG { + u32 Reserved:1; /* bit[31], Reserved */ + u32 CPU_H2C_MSG:30; /* bit[30:0], Host CPU to FW message */ +} SPDIO_CPU_H2C_MSG, *PSPDIO_CPU_H2C_MSG; + +// Register REG_SPDIO_CPU_C2H_MSG @ 0xCC +typedef struct _SPDIO_CPU_C2H_MSG { + u32 Reserved:1; /* bit[31], Reserved */ + u32 CPU_C2H_MSG:30; /* bit[30:0], FW to Host CPU message, sync to REG_SDIO_C2H_MSG */ +} SPDIO_CPU_C2H_MSG, *PSPDIO_CPU_C2H_MSG; + +// Register REG_SPDIO_CRPWM @ 0xD0 +typedef struct _SPDIO_CRPWM { + u8 TOGGLING:1; /* bit[7], issue interrupt when 0->1 or 1->0 */ + u8 Reserved:3; /* bit[6:4], Reserved */ + u8 WWLAN:1; /* bit[3], 0/1: "Wake on WLAN"/"Normal" state */ + u8 RPS_ST:1; /* bit[2], 0/1: AP Register Sleep/Active state */ + u8 WLAN_TRX:1; /* bit[1], 0: WLAN Off; 1: WLAN On */ + u8 :1; /* bit[0] */ +} SPDIO_CRPWM, *PSPDIO_CRPWM; + +// Register REG_SPDIO_AHB_DMA_CTRL @ 0xD4 +typedef struct _SPDIO_AHB_DMA_CTRL { + u32 DISPATCH_TXAGG:1; /* bit[31], Enable to dispatch aggregated TX packet */ + u32 AHB_BURST_TYPE:3; /* bit[30:28], AHB burst type */ + u32 AHB_BUSY_WAIT_CNT:4; /* bit[27:24], timeout for AHB controller to wait busy */ + u32 AHB_DMA_TRANS:2; /* bit[23:22], AHB DMA Trans value, for debugging */ + u32 AHB_MASTER_RDY:1; /* bit[21], AHB Master Hready signal */ + u32 :1; /* bit[20] */ + u32 AHB_DMA_CS:4; /* bit[19:16], AHB DMA state */ + u32 :1; /* bit[15] */ + u32 RXFF_WLEVEL:7; /* bit[14:8], SPDIO RX FIFO water level */ + u32 :1; /* bit[7] */ + u32 TXFF_WLEVEL:7; /* bit[6:0], SPDIO TX FIFO water level */ +} SPDIO_AHB_DMA_CTRL, *PSPDIO_AHB_DMA_CTRL; + +#endif /* end of '#if LITTLE_ENDIAN' */ + + +//#define TX_FIFO_ADDR 0x0000 +//#define TX_FIFO_SIZE 0x8000 + +//TX BD setting +#if SDIO_BOOT_DRIVER +// for build ROM library +#define SDIO_TX_BD_NUM 2 // Number of TX BD +#define SDIO_TX_BD_BUF_SIZE (2048+32) // the size of a TX BD pointed buffer, WLan header = 26 bytes +#define SDIO_TX_PKT_NUM 10 // Number of TX packet handler + +//RX BD setting +#define RX_BD_FREE_TH 4 // trigger the interrupt when free RX BD over this threshold + +#define MAX_RX_BD_BUF_SIZE 16380 // the Maximum size for a RX_BD point to, make it 4-bytes aligned + +#define SDIO_RX_PKT_NUM 3 // Number of RX packet handler +//#define SDIO_RX_BD_NUM 10 // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least +#define SDIO_RX_BD_NUM (SDIO_RX_PKT_NUM*2) // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least +#define SDIO_RX_BD_BUF_SIZE (2048+24) // the size of a RX BD pointed buffer, sizeof(RX Desc) = 26 bytes +#define MIN_RX_BD_SEND_PKT 2 /* the minum needed RX_BD to send a Packet to Host, we need 2: + one for RX_Desc, the other for payload */ + +// CCPWM2 bit map definition for Firmware download +#define SDIO_INIT_DONE (BIT0) +#define SDIO_MEM_WR_DONE (BIT1) +#define SDIO_MEM_RD_DONE (BIT2) +#define SDIO_MEM_ST_DONE (BIT3) + +#define SDIO_CPWM2_TOGGLE (BIT15) + +#else +#if CONFIG_INIC_EN +//TX BD setting +#define SDIO_TX_BD_NUM 34 // Number of TX BD +#define SDIO_TX_BD_BUF_SIZE 1540 //1514+24 +//#define SDIO_TX_PKT_NUM 1 // not used + +//RX BD setting +#define RX_BD_FREE_TH 5 // trigger the interrupt when free RX BD over this threshold +#define SDIO_RX_BD_BUF_SIZE 1540 //1514+24 +#define MAX_RX_BD_BUF_SIZE 16380 // the Maximum size for a RX_BD point to, make it 4-bytes aligned +#define SDIO_RX_BD_NUM 34 // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least +#define SDIO_RX_PKT_NUM 128 // Number of RX packet handler +#define MIN_RX_BD_SEND_PKT 2 /* the minum needed RX_BD to send a Packet to Host, we need 2: + one for RX_Desc, the other for payload */ + +#else +#define SDIO_TX_BD_NUM 24 // Number of TX BD +#define SDIO_TX_BD_BUF_SIZE (2048+32) // the size of a TX BD pointed buffer, WLan header = 26 bytes +#define SDIO_TX_PKT_NUM 128 // Number of TX packet handler + +//RX BD setting +#define RX_BD_FREE_TH 5 // trigger the interrupt when free RX BD over this threshold + +#define SDIO_RX_BD_BUF_SIZE 2048 +#define MAX_RX_BD_BUF_SIZE 16380 // the Maximum size for a RX_BD point to, make it 4-bytes aligned + +//#define SDIO_TX_FIFO_SIZE (1024*64) // 64K +#define SDIO_RX_BD_NUM 24 // Number of RX BD, to make 32K of bus aggregation, it needs 22 RX_BD at least +#define SDIO_RX_PKT_NUM 128 // Number of RX packet handler +#define MIN_RX_BD_SEND_PKT 2 /* the minum needed RX_BD to send a Packet to Host, we need 2: + one for RX_Desc, the other for payload */ +#endif +#endif + +#define SDIO_IRQ_PRIORITY 10 + +/* SDIO Events */ +#define SDIO_EVENT_IRQ BIT(0) // Interrupt triggered +#define SDIO_EVENT_RX_PKT_RDY BIT(1) // A new SDIO packet ready +#define SDIO_EVENT_C2H_DMA_DONE BIT(2) // Interrupt of C2H DMA done triggered +#define SDIO_EVENT_DUMP BIT(3) // SDIO status dump periodically Enable +#define SDIO_EVENT_TXBD_REFILL BIT(4) // To refill TX BD buffer +#define SDIO_EVENT_EXIT BIT(28) // Request to exit the SDIO task +#define SDIO_EVENT_MP_STOPPED BIT(29) // The SDIO task is stopped +#define SDIO_EVENT_TX_STOPPED BIT(30) // The SDIO task is stopped +#define SDIO_EVENT_RX_STOPPED BIT(31) // The SDIO task is stopped + +#define SDIO_TASK_PRIORITY 1 // it can be 0(lowest) ~ configMAX_PRIORITIES-1(highest) +#define SDIO_MP_TASK_PRIORITY 2 // it can be 0(lowest) ~ configMAX_PRIORITIES-1(highest) +//#if SDIO_TASK_PRIORITY > (configMAX_PRIORITIES - 1) +#if SDIO_TASK_PRIORITY > (4 - 1) +#error "SDIO Task Priority Should be 0~(configMAX_PRIORITIES-1)" +#endif + +//#define TX_RX_PACKET_SIZE 0x144 + +typedef struct _SDIO_TX_BD_ { + u32 Address; /* The TX buffer physical address, it must be 4-bytes aligned */ +}SDIO_TX_BD, *PSDIO_TX_BD; + +#define TX_BD_STRUCTURE_SIZE (sizeof(SDIO_TX_BD)) + + +/* The RX Buffer Descriptor format */ + +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) +typedef struct _SDIO_RX_BD_ { + u32 BuffSize:14; /* bit[13:0], RX Buffer Size, Maximum 16384-1 */ + u32 LS:1; /* bit[14], is the Last Segment ? */ + u32 FS:1; /* bit[15], is the First Segment ? */ + u32 Seq:16; /* bit[31:16], The sequence number, it's no use for now */ + u32 PhyAddr; /* The RX buffer physical address, it must be 4-bytes aligned */ +} SDIO_RX_BD, *PSDIO_RX_BD; +#else +typedef struct _SDIO_RX_BD_ { + u32 Seq:16; /* bit[31:16], The sequence number, be used for ?? */ + u32 FS:1; /* bit[15], is the First Segment ? */ + u32 LS:1; /* bit[14], is the Last Segment ? */ + u32 BuffSize:14; /* bit[13:0], RX Buffer Size, Maximum 16384 */ + u32 PhyAddr; /* The RX buffer physical address, it must be 4-bytes aligned */ +} SDIO_RX_BD, *PSDIO_RX_BD; +#endif +#define RX_BD_STRUCTURE_SIZE (sizeof(SDIO_RX_BD)) + +// TODO: This data structer just for test, we should modify it for the normal driver +typedef struct _SDIO_TX_DESC{ + // u4Byte 0 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 txpktsize:16; // bit[15:0] + u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) + u32 bus_agg_num:8; // bit[31:24], the bus aggregation number +#else + u32 bus_agg_num:8; // bit[31:24], the bus aggregation number + u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) + u32 txpktsize:16; // bit[15:0] +#endif + + // u4Byte 1 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 type:8; // bit[7:0], the packet type + u32 rsvd0:24; +#else + u32 rsvd0:24; + u32 type:8; // bit[7:0], the packet type +#endif + + // u4Byte 2 + u32 rsvd1; + + // u4Byte 3 + u32 rsvd2; + + // u4Byte 4 + u32 rsvd3; + + // u4Byte 5 + u32 rsvd4; +} SDIO_TX_DESC, *PSDIO_TX_DESC; + +// TX Desc for Memory Write command +typedef struct _SDIO_TX_DESC_MW{ + // u4Byte 0 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 txpktsize:16; // bit[15:0] + u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) + u32 bus_agg_num:8; // bit[31:24], the bus aggregation number +#else + u32 bus_agg_num:8; // bit[31:24], the bus aggregation number + u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) + u32 txpktsize:16; // bit[15:0] +#endif + + // u4Byte 1 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 type:8; // bit[7:0], the packet type + u32 reply:1; // bit[8], request to send a reply message + u32 rsvd0:23; +#else + u32 rsvd0:23; + u32 reply:1; // bit[8], request to send a reply message + u32 type:8; // bit[7:0], the packet type +#endif + + // u4Byte 2 + u32 start_addr; // memory write start address + + // u4Byte 3 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 write_len:16; // bit[15:0], the length to write + u32 rsvd2:16; // bit[31:16] +#else + u32 rsvd2:16; // bit[31:16] + u32 write_len:16; // bit[15:0], the length to write +#endif + + // u4Byte 4 + u32 rsvd3; + + // u4Byte 5 + u32 rsvd4; +} SDIO_TX_DESC_MW, *PSDIO_TX_DESC_MW; + +// TX Desc for Memory Read command +typedef struct _SDIO_TX_DESC_MR{ + // u4Byte 0 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 txpktsize:16; // bit[15:0] + u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) + u32 bus_agg_num:8; // bit[31:24], the bus aggregation number +#else + u32 bus_agg_num:8; // bit[31:24], the bus aggregation number + u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) + u32 txpktsize:16; // bit[15:0] +#endif + + // u4Byte 1 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 type:8; // bit[7:0], the packet type + u32 rsvd0:24; +#else + u32 rsvd0:24; + u32 type:8; // bit[7:0], the packet type +#endif + + // u4Byte 2 + u32 start_addr; // memory write start address + + // u4Byte 3 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 read_len:16; // bit[15:0], the length to read + u32 rsvd2:16; // bit[31:16] +#else + u32 rsvd2:16; // bit[31:16] + u32 read_len:16; // bit[15:0], the length to read +#endif + + // u4Byte 4 + u32 rsvd3; + + // u4Byte 5 + u32 rsvd4; +} SDIO_TX_DESC_MR, *PSDIO_TX_DESC_MR; + +// TX Desc for Memory Set command +typedef struct _SDIO_TX_DESC_MS{ + // u4Byte 0 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 txpktsize:16; // bit[15:0] + u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) + u32 bus_agg_num:8; // bit[31:24], the bus aggregation number +#else + u32 bus_agg_num:8; // bit[31:24], the bus aggregation number + u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) + u32 txpktsize:16; // bit[15:0] +#endif + + // u4Byte 1 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 type:8; // bit[7:0], the packet type + u32 data:8; // bit[8:15], the value to be written to the memory + u32 reply:1; // bit[16], request to send a reply message + u32 rsvd0:15; +#else + u32 rsvd0:15; + u32 reply:1; // bit[16], request to send a reply message + u32 data:8; // bit[8:15], the value to be written to the memory + u32 type:8; // bit[7:0], the packet type +#endif + + // u4Byte 2 + u32 start_addr; // memory write start address + + // u4Byte 3 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 write_len:16; // bit[15:0], the length to write + u32 rsvd2:16; // bit[31:16] +#else + u32 rsvd2:16; // bit[31:16] + u32 write_len:16; // bit[15:0], the length to write +#endif + + // u4Byte 4 + u32 rsvd3; + + // u4Byte 5 + u32 rsvd4; +} SDIO_TX_DESC_MS, *PSDIO_TX_DESC_MS; + +// TX Desc for Jump to Start command +typedef struct _SDIO_TX_DESC_JS{ + // u4Byte 0 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 txpktsize:16; // bit[15:0] + u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) + u32 bus_agg_num:8; // bit[31:24], the bus aggregation number +#else + u32 bus_agg_num:8; // bit[31:24], the bus aggregation number + u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) + u32 txpktsize:16; // bit[15:0] +#endif + + // u4Byte 1 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 type:8; // bit[7:0], the packet type + u32 rsvd0:24; +#else + u32 rsvd0:24; + u32 type:8; // bit[7:0], the packet type +#endif + + // u4Byte 2 + u32 start_fun; // the pointer of the startup function + + // u4Byte 3 + u32 rsvd2; + + // u4Byte 4 + u32 rsvd3; + + // u4Byte 5 + u32 rsvd4; +} SDIO_TX_DESC_JS, *PSDIO_TX_DESC_JS; + + +#define SIZE_TX_DESC (sizeof(SDIO_TX_DESC)) +// define the TX BD buffer size with unite of 64 byets +/* Be carefull!! the setting of hardware's TX BD buffer size may exceed the real size of + the TX BD buffer size, and then it may cause the hardware DMA write the buffer overflow */ +#define SDIO_TX_BUF_SZ_UNIT 64 +#define SDIO_TX_BD_BUF_USIZE ((((SDIO_TX_BD_BUF_SIZE+sizeof(SDIO_TX_DESC)-1)/SDIO_TX_BUF_SZ_UNIT)+1)&0xff) + +typedef struct _SDIO_TX_BD_BUFFER_ { + SDIO_TX_DESC TX_Desc; + u8 TX_Buffer[SDIO_TX_BD_BUF_SIZE]; +}SDIO_TX_BD_BUFFER, *PSDIO_TX_BD_BUFFER; + + +// TODO: This data structer just for test, we should modify it for the normal driver +typedef struct _SDIO_RX_DESC{ + // u4Byte 0 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 pkt_len:16; // bit[15:0], the packet size + u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc + u32 rsvd0:6; // bit[29:24] + u32 icv:1; // bit[30], ICV error + u32 crc:1; // bit[31], CRC error +#else + u32 crc:1; // bit[31], CRC error + u32 icv:1; // bit[30], ICV error + u32 rsvd0:6; // bit[29:24] + u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc + u32 pkt_len:16; // bit[15:0], the packet size +#endif + + // u4Byte 1 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 type:8; // bit[7:0], the type of this packet + u32 rsvd1:24; // bit[31:8] +#else + u32 rsvd1:24; // bit[31:8] + u32 type:8; // bit[7:0], the type of this packet +#endif + + // u4Byte 2 + u32 rsvd2; + + // u4Byte 3 + u32 rsvd3; + + // u4Byte 4 + u32 rsvd4; + + // u4Byte 5 + u32 rsvd5; +} SDIO_RX_DESC, *PSDIO_RX_DESC; + +// For memory read command +typedef struct _SDIO_RX_DESC_MR{ + // u4Byte 0 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 pkt_len:16; // bit[15:0], the packet size + u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc + u32 rsvd0:8; // bit[31:24] +#else + u32 rsvd0:8; // bit[31:24] + u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc + u32 pkt_len:16; // bit[15:0], the packet size +#endif + + // u4Byte 1 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 type:8; // bit[7:0], the type of this packet + u32 rsvd1:24; // bit[31:8] +#else + u32 rsvd1:24; // bit[31:8] + u32 type:8; // bit[7:0], the type of this packet +#endif + + // u4Byte 2 + u32 start_addr; + + // u4Byte 3 + u32 rsvd2; + + // u4Byte 4 + u32 rsvd3; + + // u4Byte 5 + u32 rsvd4; +} SDIO_RX_DESC_MR, *PSDIO_RX_DESC_MR; + +// For memory write reply command +typedef struct _SDIO_RX_DESC_MW{ + // u4Byte 0 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 pkt_len:16; // bit[15:0], the packet size + u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc + u32 rsvd0:8; // bit[31:24] +#else + u32 rsvd0:8; // bit[31:24] + u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc + u32 pkt_len:16; // bit[15:0], the packet size +#endif + + // u4Byte 1 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 type:8; // bit[7:0], the type of this packet + u32 rsvd1:24; // bit[31:8] +#else + u32 rsvd1:24; // bit[31:8] + u32 type:8; // bit[7:0], the type of this packet +#endif + + // u4Byte 2 + u32 start_addr; + + // u4Byte 3 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 write_len:16; // bit[15:0], the type of this packet + u32 result:8; // bit[23:16], the result of memory write command + u32 rsvd2:8; // bit[31:24] +#else + u32 rsvd2:8; // bit[31:24] + u32 result:8; // bit[23:16], the result of memory write command + u32 write_len:16; // bit[15:0], the type of this packet +#endif + + // u4Byte 4 + u32 rsvd3; + + // u4Byte 5 + u32 rsvd4; +} SDIO_RX_DESC_MW, *PSDIO_RX_DESC_MW; + +// For memory set reply command +typedef struct _SDIO_RX_DESC_MS{ + // u4Byte 0 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 pkt_len:16; // bit[15:0], the packet size + u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc + u32 rsvd0:8; // bit[31:24] +#else + u32 rsvd0:8; // bit[31:24] + u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc + u32 pkt_len:16; // bit[15:0], the packet size +#endif + + // u4Byte 1 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 type:8; // bit[7:0], the type of this packet + u32 rsvd1:24; // bit[31:8] +#else + u32 rsvd1:24; // bit[31:8] + u32 type:8; // bit[7:0], the type of this packet +#endif + + // u4Byte 2 + u32 start_addr; + + // u4Byte 3 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 write_len:16; // bit[15:0], the type of this packet + u32 result:8; // bit[23:16], the result of memory write command + u32 rsvd2:8; // bit[31:24] +#else + u32 rsvd2:8; // bit[31:24] + u32 result:8; // bit[23:16], the result of memory write command + u32 write_len:16; // bit[15:0], the type of this packet +#endif + + // u4Byte 4 + u32 rsvd3; + + // u4Byte 5 + u32 rsvd4; +} SDIO_RX_DESC_MS, *PSDIO_RX_DESC_MS; + +#define SIZE_RX_DESC (sizeof(SDIO_RX_DESC)) + +typedef struct _SDIO_RX_BD_BUFFER_ { + SDIO_RX_DESC RX_Desc; + u8 RX_Buffer[SDIO_RX_BD_BUF_SIZE]; +}SDIO_RX_BD_BUFFER, *PSDIO_RX_BD_BUFFER; + + +/* The data structer for a packet fordwarding to the WLan driver to transmit it */ +// TODO: This data structer just for test, we may need modify it for the normal driver +typedef struct _SDIO_TX_PACKET_ { + u8 *pHeader; // Point to the 1st byte of the packets + u16 PktSize; // the size (bytes) of this packet + _LIST list; // the link list to chain packets + u8 isDyna; // is Dynamic allocated +} SDIO_TX_PACKET, *PSDIO_TX_PACKET; + +/* the data structer to bind a TX_BD with a TX Packet */ +typedef struct _SDIO_TX_BD_HANDLE_ { + SDIO_TX_BD *pTXBD; // Point to the TX_BD buffer +#if CONFIG_INIC_EN +#if CONFIG_INIC_SKB_TX + struct sk_buff *skb; +#endif +#endif + SDIO_TX_PACKET *pPkt; // point to the Tx Packet + u8 isPktEnd; // For a packet over 1 BD , this flag to indicate is this BD contains a packet end + u8 isFree; // is this TX BD free +} SDIO_TX_BD_HANDLE, *PSDIO_TX_BD_HANDLE; + +/* The data structer for a packet which from the WLan driver to send to the Host */ +// TODO: This data structer just for test, we may need modify it for the normal driver + +#if SDIO_BOOT_DRIVER +typedef struct _SDIO_RX_PACKET_ { +// SDIO_RX_DESC RxDesc; // The RX Descriptor for this packet, to be send to Host ahead this packet + u8 *pData; // point to the head of payload of this packet + u16 Offset; // the offset from the pData to the payload buffer + _LIST list; // the link list to chain packets + u8 PktBuf[SDIO_RX_BD_BUF_SIZE]; // the Rx_Desc + payload data buffer, the first 24 bytes is reserved for RX_DESC +} SDIO_RX_PACKET, *PSDIO_RX_PACKET; +#else +typedef struct _SDIO_RX_PACKET_ { + SDIO_RX_DESC RxDesc; // The RX Descriptor for this packet, to be send to Host ahead this packet +#if CONFIG_INIC_EN +#if CONFIG_INIC_SKB_RX + struct sk_buff *skb; +#endif +#endif + u8 *pData; // point to the head of payload of this packet + u16 Offset; // the offset from the pData to the payload buffer + _LIST list; // the link list to chain packets + u8 isDyna; // is Dynamic allocated +} SDIO_RX_PACKET, *PSDIO_RX_PACKET; +#endif + +/* the data structer to bind a RX_BD with a RX Packet */ +typedef struct _SDIO_RX_BD_HANDLE_ { + SDIO_RX_BD *pRXBD; // Point to the RX_BD buffer + SDIO_RX_PACKET *pPkt; // point to the Rx Packet + u8 isPktEnd; // For a packet over 1 BD , this flag to indicate is this BD contains a packet end + u8 isFree; // is this RX BD free (DMA done and its RX packet has been freed) +} SDIO_RX_BD_HANDLE, *PSDIO_RX_BD_HANDLE; + +#if SDIO_MP_MODE +typedef struct _SDIO_MP_CMD_ { + u8 cmd_name[16]; + u32 cmd_type; +} SDIO_MP_CMD, *PSDIO_MP_CMD; + +typedef enum _SDIO_MP_CMD_TYPE_{ + SDIO_MP_START=1, + SDIO_MP_STOP=2, + SDIO_MP_LOOPBACK=3, + SDIO_MP_STATUS=4, + SDIO_MP_READ_REG8=5, + SDIO_MP_READ_REG16=6, + SDIO_MP_READ_REG32=7, + SDIO_MP_WRITE_REG8=8, + SDIO_MP_WRITE_REG16=9, + SDIO_MP_WRITE_REG32=10, + SDIO_MP_WAKEUP=11, // wakeup the SDIO task manually, for debugging + SDIO_MP_DUMP=12, // start/stop to dump the SDIO status periodically + SDIO_MP_CTX=13, // setup continue TX test + SDIO_MP_CRX=14, // setup continue RX test + SDIO_MP_CRX_DA=15, // setup continue RX with dynamic allocate RX Buf test + SDIO_MP_CRX_STOP=16, // setup continue RX test + SDIO_MP_DBG_MSG=17, // Debug message On/Off + +}SDIO_MP_CMD_TYPE; + +typedef enum _SDIO_CRX_MODE_{ + SDIO_CRX_STATIC_BUF = 1, + SDIO_CRX_DYNA_BUF = 2, +} SDIO_CRX_MODE; + +typedef struct _SDIO_MP_RX_PACKET_ { + _LIST list; // this member MUST be the 1st one, the link list to chain packets + u8 *pData; // point to the head of payload of this packet + u16 Offset; // the offset from the pData to the payload + u16 DataLen; // the data length of this packet +} SDIO_MP_RX_PACKET, *PSDIO_MP_RX_PACKET; + +#endif // end of '#if SDIO_MP_MODE' + +#define SDIO_CMD_TX_ETH 0x83 // request to TX a 802.3 packet +#define SDIO_CMD_TX_WLN 0x81 // request to TX a 802.11 packet +#define SDIO_CMD_H2C 0x11 // H2C(host to device) command packet +#define SDIO_CMD_MEMRD 0x51 // request to read a block of memory data +#define SDIO_CMD_MEMWR 0x53 // request to write a block of memory +#define SDIO_CMD_MEMST 0x55 // request to set a block of memory with a value +#define SDIO_CMD_STARTUP 0x61 // request to jump to the start up function + +#define SDIO_CMD_RX_ETH 0x82 // indicate a RX 802.3 packet +#define SDIO_CMD_RX_WLN 0x80 // indicate a RX 802.11 packet +#define SDIO_CMD_C2H 0x10 // C2H(device to host) command packet +#define SDIO_CMD_MEMRD_RSP 0x50 // response to memory block read command +#define SDIO_CMD_MEMWR_RSP 0x52 // response to memory write command +#define SDIO_CMD_MEMST_RSP 0x54 // response to memory set command +#define SDIO_CMD_STARTED 0x60 // indicate the program has jumped to the given function + +enum SDIO_RPWM2_BITS { + RPWM2_ACT_BIT = BIT0, // Active + RPWM2_SLEEP_BIT = 0, // Sleep + RPWM2_DSTANDBY_BIT = BIT1, // Deep Standby + RPWM2_PG_BIT = 0, // Power Gated + RPWM2_FBOOT_BIT = BIT2, // fast reboot + RPWM2_NBOOT_BIT = 0, // normal reboot + RPWM2_WKPIN_A5_BIT = BIT3, // enable GPIO A5 wakeup + RPWM2_WKPIN_C7_BIT = BIT4, // enable GPIO C7 wakeup + RPWM2_WKPIN_D5_BIT = BIT5, // enable GPIO D5 wakeup + RPWM2_WKPIN_E3_BIT = BIT6, // enable GPIO E3 wakeup + RPWM2_PIN_A5_LV_BIT = BIT7, // GPIO A5 wakeup level + RPWM2_PIN_C7_LV_BIT = BIT8, // GPIO C7 wakeup level + RPWM2_PIN_D5_LV_BIT = BIT9, // GPIO D5 wakeup level + RPWM2_PIN_E3_LV_BIT = BIT10, // GPIO E3 wakeup level + RPWM2_CG_BIT = BIT11, // Clock Gated + RPWM2_ACK_BIT = BIT14, // Acknowledge + RPWM2_TOGGLE_BIT = BIT15, // Toggle bit +}; + +enum SDIO_CPWM2_BITS { + CPWM2_ACT_BIT = BIT0, // Active + CPWM2_DSTANDBY_BIT = BIT1, // Deep Standby + CPWM2_FBOOT_BIT = BIT2, // fast reboot + CPWM2_INIC_FW_RDY_BIT = BIT3, // is the iNIC FW(1) or Boot FW(0) + + CPWM2_TOGGLE_BIT = BIT15, // Toggle bit +}; + +#ifdef CONFIG_SDIO_DEVICE_VERIFY + +#define TX_BD_STRUCTURE_NUM 10 +#define RX_BD_STRUCTURE_NUM 10 +#define TX_BD_BUFFER_SIZE 0x1000//0x2000//0x800 +#define RX_BD_BUFFER_SIZE 0x400//0x800 + +#define SDIO_RAM_ADDR_BASE 0x20080000 +#define SDIO_BUFFER_HEAD(addr) SDIO_RAM_ADDR_BASE + addr +#define HAL_SDIO_BUFFER_READ8(addr) HAL_READ8(SDIO_RAM_ADDR_BASE, addr) +#define HAL_SDIO_BUFFER_READ32(addr) HAL_READ32(SDIO_RAM_ADDR_BASE, addr) +#define HAL_SDIO_BUFFER_WRITE32(addr, value) HAL_WRITE32(SDIO_RAM_ADDR_BASE, addr, value) + +//#define RX_BD_ADDR 0x8000 +//#define RX_BUFFER_ADDR 0x8050 + +typedef enum _SDIO_TEST_FUNC_ { + SDIO_TEST_INIT, // 0 + SDIO_TEST_INT_ON, // 1 + SDIO_TEST_INT_OFF, // 2 + SDIO_HCI_RX_REQ, // 3 + SDIO_RESET_TXFIFIO, // 4 + SDIO_CPU_RST_DMA, // 5 + SDIO_CPU_CLR_INT_REG, // 6 + SDIO_TIMER_TEST, // 7 + SDIO_TEST_DEBUG, // 8 + SDIO_TEST, // 9 + SDIO_HELP = 0xff +}SDIO_TEST_FUNC, *PSDIO_TEST_FUNC; + +typedef struct _SDIO_TEST_ADAPTER_ { + u32 TXWritePtr; + u32 TXReadPtr; + u16 RXWritePtr; + u16 RXReadPtr; + u16 IntMask; + u16 IntStatus; +} SDIO_TEST_ADAPTER, *PSDIO_TEST_ADAPTER; + + +VOID +MovePKTToRX( + IN u32 Source, IN u32 Destination, IN u32 PKTSize +); + +BOOL +PacketProcess( + IN SDIO_TEST_ADAPTER *pDevStatus +); + +VOID +SdioDeviceIrqHandleFunc( + IN VOID *DATA +); + +VOID +SdioDeviceTestApp( + IN u32 Data +); + +VOID +InitRXBD(VOID); + +VOID +InitTXFIFO(VOID); + +VOID +IrqRegister(VOID); + +#endif // end of "#ifdef CONFIG_SDIO_DEVICE_VERIFY" + +#endif /* #ifndef _RTL8195A_SDIO_H_ */ diff --git a/lib/fwlib/rtl8195a/rtl8195a_sdio_host.h b/lib/fwlib/rtl8195a/rtl8195a_sdio_host.h new file mode 100644 index 0000000..ee1f892 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_sdio_host.h @@ -0,0 +1,295 @@ + /* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _RTL8195A_SDIO_HOST_H_ +#define _RTL8195A_SDIO_HOST_H_ + +#include "hal_api.h" +#include "osdep_api.h" + + + + +#ifdef CONFIG_SDIO_HOST_VERIFY + +#define HAL_MMC_HOST_READ32(addr) HAL_READ32(SDIO_HOST_REG_BASE, addr) +#define HAL_MMC_HOST_WRITE32(addr, value) HAL_WRITE32(SDIO_HOST_REG_BASE, addr, value) +#define HAL_MMC_HOST_READ16(addr) HAL_READ16(SDIO_HOST_REG_BASE, addr) +#define HAL_MMC_HOST_WRITE16(addr, value) HAL_WRITE16(SDIO_HOST_REG_BASE, addr, value) +#define HAL_MMC_HOST_READ8(addr) HAL_READ8(SDIO_HOST_REG_BASE, addr) +#define HAL_MMC_HOST_WRITE8(addr, value) HAL_WRITE8(SDIO_HOST_REG_BASE, addr, value) + +/* RTL8195A Register */ +// REG_SOC_HCI_COM_FUNC_EN (0x214) +#define SD_DEVICE_IP_ON_BLK BIT0 +#define SD_DEVICE_IP_OFF_BLK BIT1 +#define SD_HOST_IP_BLK BIT2 + +// REG_PESOC_HCI_CLK_CTRL0 (0x240) +#define SD_HOST_CLKEN_IN_CPU_RUN_MODE BIT2 + +// REG_HCI_PINMUX_CTRL (0x2A0) +#define SD_DEVICE_MODE_PINMUX_EN BIT0 +#define SD_HOST_MODE_PINMUX_EN BIT1 + +// 0x40059000 +#define SD_HOST_CARD_DETECT_CIRCUIT BIT10 + + + +/* SD Host Register */ +#define REG_SDMA_SYS_ADDR_ARG 0x00 // 4byte +#define REG_BLOCK_SIZE 0x04 // 2byte +#define REG_BLOCK_COUNT 0x06 // 2byte +#define REG_ARGUMENT1 0x08 // 4byte +#define REG_TRANSFER_MODE 0x0C // 2byte +#define REG_COMMAND 0x0E // 2byte +#define REG_RESPONSE0 0x10 // 4byte +#define REG_RESPONSE2 0x14 // 4byte +#define REG_RESPONSE4 0x18 // 4byte +#define REG_RESPONSE6 0x1C // 4byte +#define REG_BUFFER_DATA_PORT 0x20 // 4byte +#define REG_PRESENT_STATE 0x24 // 4byte +#define REG_HOST_CONTROL1 0x28 // 1byte +#define REG_POWER_CONTROL 0x29 // 1byte +#define REG_BLOCK_GAP_CONTROL 0x2A // 1byte +#define REG_WAKEUP_CONTROL 0x2B // 1byte +#define REG_CLOCK_CONTROL 0x2C // 2byte +#define REG_TIMEOUT_CONTROL 0x2E // 1byte +#define REG_SW_RESET 0x2F // 1byte +#define REG_NORMAL_INT_STATUS 0x30 // 2byte +#define REG_ERROR_INT_STATUS 0x32 // 2byte +#define REG_NORMAL_INT_STATUS_ENABLE 0x34 // 2byte +#define REG_ERROR_INT_STATUS_ENABLE 0x36 // 2byte +#define REG_NORMAL_INT_SIGNAL_ENABLE 0x38 // 2byte +#define REG_ERROR_INT_SIGNAL_ENABLE 0x3A // 2byte +#define REG_CAPABILITIES 0x40 // 8byte +#define REG_ADMA_ADDRESS 0x58 // 8byte + +// Transfer Mode (0x0C) +#define BIT_DMA_EN BIT0 +#define BIT_BLK_CNT_EN BIT1 +#define BIT_AUTO_CMD12_EN BIT2 +#define BIT_AUTO_CMD23_EN BIT3 +#define BIT_READ_TRANS BIT4 +#define BIT_MULTI_BLK BIT5 + +// Present State (0x24) +#define BIT_CMD_INHIBIT_CMD BIT0 +#define BIT_CMD_INHIBIT_DAT BIT1 +#define BIT_CARD_INSERTED BIT16 +#define BIT_WRITE_PROTECT_SWITCH_PIN BIT19 + +// Power Control (0x29) +#define BIT_POWER_33 0xE +#define BIT_POWER_30 0xC +#define BIT_POWER_18 0xA + +// Clock Control (0x2C) +#define BIT_INTERNAL_CLK_EN BIT0 +#define BIT_INTERNAL_CLK_STABLE BIT1 +#define BIT_SD_CLK_EN BIT2 + +// Software Reset (0x2F) +#define BIT_SW_RESET_ALL BIT0 +#define BIT_SW_RESET_CMD_LINE BIT1 +#define BIT_SW_RESET_DAT_LINE BIT2 + +// Norma Interrupt Status (0x30) +#define BIT_COMMAND_COMPLETE BIT0 +#define BIT_TRANSFER_COMPLETE BIT1 +#define BIT_BLOCK_GAP_EVENT BIT2 +#define BIT_DMA_INT BIT3 +#define BIT_BUFFER_WRITE_RDY BIT4 +#define BIT_BUFFER_READ_RDY BIT5 +#define BIT_CARD_INSERTION BIT6 +#define BIT_CARD_REMOVAL BIT7 +#define BIT_CARD_INT BIT8 +#define BIT_ERROR_INT BIT15 + +// Error Interrupt Status (0x32) +#define BIT_DATA_TIME_OUT_ERROR BIT4 +#define BIT_DATA_CRC_ERROR BIT5 +#define BIT_ADMA_ERROR BIT9 + +// Capabilities (0x40) +#define BIT_VDD_33 BIT24 +#define BIT_VDD_30 BIT25 +#define BIT_VDD_18 BIT26 + + +#define ENABLE 1 +#define DISABLE 0 + +#define ADMA_DESC_NUM 50 + +#define BUFFER_UNIT_SIZE 512 + +typedef enum _MMC_HOST_TEST_FUNC_ { + MMC_HOST_TEST_HW_INIT, // 0 + MMC_HOST_TEST_CARD_INIT, // 1 + MMC_HOST_TEST_SEND_CMD, // 2 + MMC_HOST_TEST_DEBUG, // 3 + MMC_HOST_TEST_SW_RESET, // 4 + MMC_HOST_TEST_READ_SINGLE, // 5 + MMC_HOST_TEST_WRITE_SINGLE, // 6 + MMC_HOST_TEST_READ_MULTI, // 7 + MMC_HOST_TEST_WRITE_MULTI, // 8 + MMC_HOST_TEST_SINGLE_LONGRUN, // 9 + MMC_HOST_TEST_MULTI_LONGRUN, // 10 + MMC_HOST_TEST_CARD_DETECTION, // 11 + MMC_HOST_TEST_WRITE_PROTECT, // 12 + MMC_HOST_TEST_REGISTER_RW // 13 +}MMC_HOST_TEST_FUNC; + +typedef enum _RESPONSE_TYPE_ { + No_Response, // 00b + Response_136, // 01b + Response_48, // 10b + Response_48_Busy // 11b +}RESPONSE_TYPE; + +typedef enum _COMMAND_TYPE_ { + Normal, // 00b + Suspend, // 01b + Resume, // 10b + Abort // 11b +}COMMAND_TYPE; + +typedef enum _DATA_PRESENT_ { + No_Data_Present, // 00b + Data_Present, // 01b +}DATA_PRESENT; + +typedef enum _SUPPLY_VOLTAGE_ { + MMC_VDD_27_28 = BIT15, + MMC_VDD_28_29 = BIT16, + MMC_VDD_29_30 = BIT17, + MMC_VDD_30_31 = BIT18, + MMC_VDD_31_32 = BIT19, + MMC_VDD_32_33 = BIT20, + MMC_VDD_33_34 = BIT21, + MMC_VDD_34_35 = BIT22, + MMC_VDD_35_36 = BIT23, +}SUPPLY_VOLTAGE; + +typedef enum _COMMAND_INDEX_ { + GO_IDLE_STATE = 0, + ALL_SEND_CID = 2, + SEND_RELATIVE_ADDR = 3, + SET_BUS_WIDTH = 6, + SELECT_CARD = 7, + SEND_IF_COND = 8, + SEND_CSD = 9, + STOP_TRANSMISSION = 12, + SEND_STATUS = 13, + READ_SINGLE_BLOCK = 17, + READ_MULTIPLE_BLOCK = 18, + WRITE_BLOCK = 24, + WRITE_MULTIPLE_BLOCK = 25, + SD_SEND_OP_COND = 41, + APP_CMD = 55, +}COMMAND_INDEX; + +typedef enum _TRANSFER_CONFIG_ { + Read_Data = 0, + Write_Data = 1, + Single_Block = 0, + Multiple_Block = 1, +}TRANSFER_CONFIG; + +typedef enum _ERROR_STATUS_ { + General_Error, // 0 + CRC_Error, // 1 + TIME_OUT_ERROR, // 2 + CRC_Error_NeedCMD12, // 3 + Transfer_OK // 4 +}ERROR_STATUS; + +typedef enum _CARD_CURRENT_STATE_ { + IDLE_STATE, + READY_STATE, + IDENT_STATE, + STBY_STATE, + TRAN_STATE, + DATA_STATE, + RCV_STATE, + PRG_STATE, + DIS_STATE, + UNKNOWN_STATE +}CARD_CURRENT_STATE; + +typedef struct _COMMAND_FORMAT_ +{ + u16 Resp_Type:2; + u16 Rsvd0:1; + u16 CMD_CRC_Chk:1; + u16 CMD_Idx_Chk:1; + u16 Data_Present:1; + u16 CMD_Type:2; + u16 CMD_Idx:6; + u16 Rsvd1:2; +}COMMAND_FORMAT, *PCOMMAND_FPRMAT; + +typedef struct _MMC_COMMAND +{ + COMMAND_FORMAT Cmd_Format; + u32 Arg; +}MMC_COMMAND; + +typedef struct _MMC_HOST_ +{ + u32 OCR_Avail; + u32 Resp[4]; + u32 CID[4]; + u32 RCA; +}MMC_HOST, *PMMC_HOST; + +typedef struct _ADMA_ATTR_ +{ + u16 Valid:1; + u16 End:1; + u16 Int:1; + u16 Rsvd1:1; + u16 Act1:1; + u16 Act2:1; + u16 Rsvd2:10; +}ADMA_ATTR, *PADMA_ATTR; +// 24 bytes +typedef struct _ADMA_DESC_TABLE_ +{ + // 1st buffer desc + ADMA_ATTR Attribute1; + u16 Length1; + u32 Address1; + // 2nd buffer desc + ADMA_ATTR Attribute2; + u16 Length2; + u32 Address2; + // 3rd buffer desc + ADMA_ATTR Attribute3; + u16 Length3; + u32 Address3; +}ADMA_DESC_TABLE, *PADMA_DESC_TABLE; +// 1024 bytes +typedef struct _ADMA_BUFFER_ +{ + u8 Data1[512]; /* 1st buffer */ + u8 Data2[512]; /* 2nd buffer */ +}ADMA_BUFFER, *PADMA_BUFFER; + + +VOID +SdHostTestApp( + IN u8 *argv[] +); +#endif // end of "#ifdef CONFIG_SDIO_HOST_VERIFY" + +#endif /* #ifndef _RTL8195A_SDIO_HOST_H_ */ diff --git a/lib/fwlib/rtl8195a/rtl8195a_sdr.h b/lib/fwlib/rtl8195a/rtl8195a_sdr.h new file mode 100644 index 0000000..05a13fa --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_sdr.h @@ -0,0 +1,379 @@ +#ifndef _RTL8195A_SDR_H +#define _RTL8195A_SDR_H + +#define MS_0_CTRL_BASE BSP_MS_I_DRAMC_0_BASE +#define MS_0_CTRL_PHY_BASE (BSP_MS_I_DRAMC_0_BASE) +#define MS_0_WRAP_BASE (MS_0_CTRL_BASE + 0x200) + +#define MS_1_CTRL_BASE BSP_MS_I_DRAMC_1_BASE +#define MS_1_CTRL_PHY_BASE (BSP_MS_I_DRAMC_1_BASE) +#define MS_1_WRAP_BASE (MS_1_CTRL_BASE + 0x200) + +#define MS_PCTL_CCR_OFFSET 0x000 +#define MS_PCTL_DCR_OFFSET 0x004 +#define MS_PCTL_IOCR_OFFSET 0x008 +#define MS_PCTL_CSR_OFFSET 0x00c +#define MS_PCTL_DRR_OFFSET 0x010 +#define MS_PCTL_TPR0_OFFSET 0x014 +#define MS_PCTL_TPR1_OFFSET 0x018 +#define MS_PCTL_TPR2_OFFSET 0x01c +#define MS_PCTL_MR_OFFSET 0x020 +#define MS_PCTL_EMR1_OFFSET 0x024 +#define MS_PCTL_EMR2_OFFSET 0x028 +#define MS_PCTL_EMR3_OFFSET 0x02c +#define MS_PCTL_CSR2_OFFSET 0x030 +#define MS_PCTL_SRST_OFFSET 0x034 +#define MS_PCTL_DTR2_OFFSET 0x038 +#define MS_PCTL_DTR3_OFFSET 0x03c +#define MS_PCTL_GDLLCR_OFFSET 0x040 +#define MS_PCTL_DLLCR0_OFFSET 0x044 +#define MS_PCTL_DLLCR1_OFFSET 0x048 +#define MS_PCTL_DLLCR2_OFFSET 0x04c +#define MS_PCTL_DLLCR3_OFFSET 0x050 +#define MS_PCTL_DLLCR4_OFFSET 0x054 +#define MS_PCTL_DLLCR5_OFFSET 0x058 +#define MS_PCTL_DLLCR6_OFFSET 0x05c +#define MS_PCTL_DLLCR7_OFFSET 0x060 +#define MS_PCTL_DLLCR8_OFFSET 0x064 +#define MS_PCTL_DQTR0_OFFSET 0x068 +#define MS_PCTL_DQTR1_OFFSET 0x06c +#define MS_PCTL_DQTR2_OFFSET 0x070 +#define MS_PCTL_DQTR3_OFFSET 0x074 +#define MS_PCTL_DQTR4_OFFSET 0x078 +#define MS_PCTL_DQTR5_OFFSET 0x07c +#define MS_PCTL_DQTR6_OFFSET 0x080 +#define MS_PCTL_DQTR7_OFFSET 0x084 +#define MS_PCTL_DQSTR_OFFSET 0x088 +#define MS_PCTL_DQSBTR_OFFSET 0x08c +#define MS_PCTL_ODTCR_OFFSET 0x090 +#define MS_PCTL_DTR0_OFFSET 0x094 +#define MS_PCTL_DTR1_OFFSET 0x098 +#define MS_PCTL_DTAR_OFFSET 0x09c +#define MS_PCTL_ZQCR0_OFFSET 0x0a0 +#define MS_PCTL_ZQCR1_OFFSET 0x0a4 +#define MS_PCTL_ZQSR_OFFSET 0x0a8 +#define MS_PCTL_RSLR0_OFFSET 0x0ac +#define MS_PCTL_RSLR1_OFFSET 0x0b0 +#define MS_PCTL_RSLR2_OFFSET 0x0b4 +#define MS_PCTL_RSLR3_OFFSET 0x0b8 +#define MS_PCTL_RDGR0_OFFSET 0x0bc +#define MS_PCTL_RDGR1_OFFSET 0x0c0 +#define MS_PCTL_RDGR2_OFFSET 0x0c4 +#define MS_PCTL_RDGR3_OFFSET 0x0c8 +#define MS_PCTL_MXSL_OFFSET 0x0cc + +#define MS_PCTL_BCR_OFFSET 0x0d0 +#define MS_PCTL_BALR0_OFFSET 0x0d4 +#define MS_PCTL_BALR1_OFFSET 0x0d8 +#define MS_PCTL_BDR0_OFFSET 0x0dc +#define MS_PCTL_BDR1_OFFSET 0x0e0 +#define MS_PCTL_BBR_OFFSET 0x0e4 +#define MS_PCTL_BSR_OFFSET 0x0e8 +#define MS_PCTL_BYR_OFFSET 0x0ec +#define MS_PCTL_BFA_OFFSET 0x0f0 +#define MS_PCTL_IDR_OFFSET 0x0f8 +#define MS_PCTL_ERR_OFFSET 0x0fc + +#define MS_WRAP_SCR_OFFSET 0x224 +#define MS_WRAP_QCR_OFFSET 0x230 +#define MS_WRAP_PCR_OFFSET 0x234 +#define MS_WRAP_QTR0_OFFSET 0x240 +#define MS_WRAP_QTR1_OFFSET 0x244 +#define MS_WRAP_QTR2_OFFSET 0x248 +#define MS_WRAP_QTR3_OFFSET 0x24c +#define MS_WRAP_QTR4_OFFSET 0x250 +#define MS_WRAP_QTR5_OFFSET 0x254 +#define MS_WRAP_QTR6_OFFSET 0x258 +#define MS_WRAP_QTR7_OFFSET 0x25c +#define MS_WRAP_QTR8_OFFSET 0x260 +#define MS_WRAP_QTR9_OFFSET 0x264 +#define MS_WRAP_QTR10_OFFSET 0x268 +#define MS_WRAP_QTR11_OFFSET 0x26c +#define MS_WRAP_QTR12_OFFSET 0x270 +#define MS_WRAP_QTR13_OFFSET 0x274 +#define MS_WRAP_QTR14_OFFSET 0x278 +#define MS_WRAP_QTR15_OFFSET 0x27c + +#define MS_PHY_DLY0 0x100 +#define MS_PHY_DLY1_RST 0x104 +#define MS_PHY_DLY_CLK 0x108 +#define MS_PHY_DLY_ST 0x10c +#define MS_PHY_DLY_NUM 0x100 + +#define PCTL_CCR_INIT_BFO 0 +#define PCTL_CCR_INIT_BFW 1 +#define PCTL_CCR_DTT_BFO 1 +#define PCTL_CCR_DTT_BFW 1 +#define PCTL_CCR_BTT_BFO 2 +#define PCTL_CCR_BTT_BFW 1 +#define PCTL_CCR_DPIT_BFO 3 +#define PCTL_CCR_DPIT_BFW 1 +#define PCTL_CCR_FLUSH_FIFO_BFO 8 +#define PCTL_CCR_FLUSH_FIFO_BFW 1 + +#define PCTL_DCR_DDR3_BFO 0 +#define PCTL_DCR_DDR3_BFW 1 +#define PCTL_DCR_SDR_BFO 1 +#define PCTL_DCR_SDR_BFW 1 +#define PCTL_DCR_DQ32_BFO 4 +#define PCTL_DCR_DQ32_BFW 1 +#define PCTL_DCR_DFI_RATE_BFO 8 +#define PCTL_DCR_DFI_RATE_BFW 3 + +#define PCTL_IOCR_RD_PIPE_BFO 8 +#define PCTL_IOCR_RD_PIPE_BFW 4 +#define PCTL_IOCR_TPHY_WD_BFO 12 +#define PCTL_IOCR_TPHY_WD_BFW 5 +#define PCTL_IOCR_TPHY_WL_BFO 17 +#define PCTL_IOCR_TPHY_WL_BFW 3 +#define PCTL_IOCR_TPHY_RD_EN_BFO 20 +#define PCTL_IOCR_TPHY_RD_EN_BFW 5 + +#define PCTL_CSR_MEM_IDLE_BFO 8 +#define PCTL_CSR_MEM_IDLE_BFW 1 +#define PCTL_CSR_DT_IDLE_BFO 9 +#define PCTL_CSR_DT_IDLE_BFW 1 +#define PCTL_CSR_BIST_IDLE_BFO 10 +#define PCTL_CSR_BIST_IDLE_BFW 1 +#define PCTL_CSR_DT_FAIL_BFO 11 +#define PCTL_CSR_DT_FAIL_BFW 1 +#define PCTL_CSR_BT_FAIL_BFO 12 +#define PCTL_CSR_BT_FAIL_BFW 1 + +#define PCTL_DRR_TRFC_BFO 0 +#define PCTL_DRR_TRFC_BFW 7 +#define PCTL_DRR_TREF_BFO 8 +#define PCTL_DRR_TREF_BFW 24 +#define PCTL_DRR_REF_NUM_BFO 24 +#define PCTL_DRR_REF_NUM_BFW 4 +#define PCTL_DRR_REF_DIS_BFO 28 +#define PCTL_DRR_REF_DIS_BFW 1 + +#define PCTL_TPR0_TRP_BFO 0 +#define PCTL_TPR0_TRP_BFW 4 +#define PCTL_TPR0_TRAS_BFO 4 +#define PCTL_TPR0_TRAS_BFW 5 +#define PCTL_TPR0_TWR_BFO 9 +#define PCTL_TPR0_TWR_BFW 4 +#define PCTL_TPR0_TRTP_BFO 13 +#define PCTL_TPR0_TRTP_BFW 3 + +#define PCTL_TPR1_TRRD_BFO 0 +#define PCTL_TPR1_TRRD_BFW 4 +#define PCTL_TPR1_TRC_BFO 4 +#define PCTL_TPR1_TRC_BFW 6 +#define PCTL_TPR1_TRCD_BFO 10 +#define PCTL_TPR1_TRCD_BFW 4 +#define PCTL_TPR1_TCCD_BFO 14 +#define PCTL_TPR1_TCCD_BFW 3 +#define PCTL_TPR1_TWTR_BFO 17 +#define PCTL_TPR1_TWTR_BFW 3 +#define PCTL_TPR1_TRTW_BFO 20 +#define PCTL_TPR1_TRTW_BFW 4 + +#define PCTL_TPR2_INIT_REF_NUM_BFO 0 +#define PCTL_TPR2_INIT_REF_NUM_BFW 4 +#define PCTL_TPR2_INIT_NS_EN_BFO 4 +#define PCTL_TPR2_INIT_NS_EN_BFW 1 +#define PCTL_TPR2_TMRD_BFO 5 +#define PCTL_TPR2_TMRD_BFW 2 + +#define PCTL_MR_BL_BFO 0 +#define PCTL_MR_BL_BFW 3 +#define PCTL_MR_BT_BFO 3 +#define PCTL_MR_BT_BFW 1 +#define PCTL_MR_CAS_BFO 4 +#define PCTL_MR_CAS_BFW 3 +#define PCTL_MR_OP_BFO 8 +#define PCTL_MR_OP_BFW 12 + +#define PCTL_EMR1_ADDLAT_BFO 3 +#define PCTL_EMR1_ADDLAT_BFW 3 + +#define PCTL_CMD_DPIN_RSTN_BFO 0 +#define PCTL_CMD_DPIN_RSTN_BFW 1 +#define PCTL_CMD_DPIN_CKE_BFO 1 +#define PCTL_CMD_DPIN_CKE_BFW 1 +#define PCTL_CMD_DPIN_ODT_BFO 2 +#define PCTL_CMD_DPIN_ODT_BFW 1 + +#define PCTL_BCR_STOP_BFO 0 +#define PCTL_BCR_STOP_BFW 1 +#define PCTL_BCR_CMP_BFO 1 +#define PCTL_BCR_CMP_BFW 1 +#define PCTL_BCR_LOOP_BFO 2 +#define PCTL_BCR_LOOP_BFW 1 +#define PCTL_BCR_DIS_MASK_BFO 3 +#define PCTL_BCR_DIS_MASK_BFW 1 +#define PCTL_BCR_AT_STOP_BFO 4 +#define PCTL_BCR_AT_STOP_BFW 1 +#define PCTL_BCR_FLUSH_CMD_BFO 8 +#define PCTL_BCR_FLUSH_CMD_BFW 1 +#define PCTL_BCR_FLUSH_WD_BFO 9 +#define PCTL_BCR_FLUSH_WD_BFW 1 +#define PCTL_BCR_FLUSH_RGD_BFO 10 +#define PCTL_BCR_FLUSH_RGD_BFW 1 +#define PCTL_BCR_FLUSH_RD_BFO 11 +#define PCTL_BCR_FLUSH_RD_BFW 1 +#define PCTL_BCR_FLUSH_RD_EXPC_BFO 16 +#define PCTL_BCR_FLUSH_RD_EXPC_BFW 14 + +#define PCTL_BST_ERR_FST_TH_BFO 0 +#define PCTL_BST_ERR_FST_TH_BFW 12 +#define PCTL_BST_ERR_CNT_BFO 16 +#define PCTL_BST_ERR_CNT_BFW 14 + +#define PCTL_BSRAM0_CMD_LEVEL_BFO 0 +#define PCTL_BSRAM0_CMD_LEVEL_BFW 12 +#define PCTL_BSRAM0_WD_LEVEL_BFO 16 +#define PCTL_BSRAM0_WD_LEVEL_BFW 14 + +#define PCTL_BSRAM1_RG_LEVEL_BFO 0 +#define PCTL_BSRAM1_RG_LEVEL_BFW 14 +#define PCTL_BSRAM1_RD_LEVEL_BFO 16 +#define PCTL_BSRAM1_RD_LEVEL_BFW 14 + +#define WRAP_MISC_PAGE_SIZE_BFO 0 +#define WRAP_MISC_PAGE_SIZE_BFW 4 +#define WRAP_MISC_BANK_SIZE_BFO 4 +#define WRAP_MISC_BANK_SIZE_BFW 2 +#define WRAP_MISC_BST_SIZE_BFO 6 +#define WRAP_MISC_BST_SIZE_BFW 2 +#define WRAP_MISC_DDR_PARAL_BFO 8 +#define WRAP_MISC_DDR_PARAL_BFW 1 + +struct ms_rxi310_portmap { + volatile unsigned int ccr; /* 0x000 */ + volatile unsigned int dcr; /* 0x004 */ + volatile unsigned int iocr; /* 0x008 */ + volatile unsigned int csr; /* 0x00c */ + volatile unsigned int drr; /* 0x010 */ + volatile unsigned int tpr0; /* 0x014 */ + volatile unsigned int tpr1; /* 0x018 */ + volatile unsigned int tpr2; /* 0x01c */ + volatile unsigned int mr; /* 0x020 */ + volatile unsigned int emr1; /* 0x024 */ + volatile unsigned int emr2; /* 0x028 */ + volatile unsigned int emr3; /* 0x02c */ + volatile unsigned int cdpin; /* 0x030 */ + volatile unsigned int tdpin; /* 0x034 */ + volatile unsigned int dtr2; /* 0x038 */ + volatile unsigned int dtr3; /* 0x03c */ + volatile unsigned int gdllcr; /* 0x040 */ + volatile unsigned int dllcr0; /* 0x044 */ + volatile unsigned int dllcr1; /* 0x048 */ + volatile unsigned int dllcr2; /* 0x04c */ + volatile unsigned int dllcr3; /* 0x050 */ + volatile unsigned int dllcr4; /* 0x054 */ + volatile unsigned int dllcr5; /* 0x058 */ + volatile unsigned int dllcr6; /* 0x05c */ + volatile unsigned int dllcr7; /* 0x060 */ + volatile unsigned int dllcr8; /* 0x064 */ + volatile unsigned int dqtr0; /* 0x068 */ + volatile unsigned int dqtr1; /* 0x06c */ + volatile unsigned int dqtr2; /* 0x070 */ + volatile unsigned int dqtr3; /* 0x074 */ + volatile unsigned int dqtr4; /* 0x078 */ + volatile unsigned int dqtr5; /* 0x07c */ + volatile unsigned int dqtr6; /* 0x080 */ + volatile unsigned int dqtr7; /* 0x084 */ + volatile unsigned int dqstr; /* 0x088 */ + volatile unsigned int dqsbtr; /* 0x08c */ + volatile unsigned int odtcr; /* 0x090 */ + volatile unsigned int dtr0; /* 0x094 */ + volatile unsigned int dtr1; /* 0x098 */ + volatile unsigned int dtar; /* 0x09c */ + volatile unsigned int zqcr0; /* 0x0a0 */ + volatile unsigned int zqcr1; /* 0x0a4 */ + volatile unsigned int zqsr; /* 0x0a8 */ + volatile unsigned int rslr0; /* 0x0ac */ + volatile unsigned int rslr1; /* 0x0b0 */ + volatile unsigned int rslr2; /* 0x0b4 */ + volatile unsigned int rslr3; /* 0x0b8 */ + volatile unsigned int rdgr0; /* 0x0bc */ + volatile unsigned int rdgr1; /* 0x0c0 */ + volatile unsigned int rdgr2; /* 0x0c4 */ + volatile unsigned int rdgr3; /* 0x0c8 */ + volatile unsigned int mxsl; /* 0x0cc */ + volatile unsigned int bcr; /* 0x0d0 */ + volatile unsigned int bst; /* 0x0d4 */ + volatile unsigned int bsram0; /* 0x0d8 */ + volatile unsigned int bsram1; /* 0x0dc */ + volatile unsigned int bdr1; /* 0x0e0 */ + volatile unsigned int bbr; /* 0x0e4 */ + volatile unsigned int bsr; /* 0x0e8 */ + volatile unsigned int byr; /* 0x0ec */ + volatile unsigned int bfa; /* 0x0f0 */ + volatile unsigned int pctl_svn; /* 0x0f4 */ + volatile unsigned int pctl_idr; /* 0x0f8 */ + volatile unsigned int err; /* 0x0fc */ + + // SDR_PHY CONTROL REGISTER + volatile unsigned int phy_dly0; /* 0x100 */ + volatile unsigned int phy_dly1_rst; /* 0x104 */ + volatile unsigned int phy_dly_clk; /* 0x108 */ + volatile unsigned int phy_dly_st; /* 0x10c */ + volatile unsigned int phy_dly_num; /* 0x110 */ + volatile unsigned int reserved0[68]; + + // WRAP CONTROL REGISTER + volatile unsigned int misc; /* 0x224 */ + volatile unsigned int cq_ver; /* 0x228 */ + volatile unsigned int cq_mon; /* 0x22c */ + volatile unsigned int wq_ver; /* 0x230 */ + volatile unsigned int wq_mon; /* 0x234 */ + volatile unsigned int rq_ver; /* 0x240 */ + volatile unsigned int rq_mon; /* 0x244 */ + volatile unsigned int reserved1[22]; + volatile unsigned int wwrap_idr; /* 0x2a0 */ + volatile unsigned int wrap_svn; /* 0x2a4 */ + +}; //ms_rxi310_portmap + +#define QFIFO_CMD_BANK_BFO (35 - QFIFO_CMD_WRRD_BFO) // [38:35] +#define QFIFO_CMD_BANK_BFW 4 +#define QFIFO_CMD_PAGE_BFO (20 - QFIFO_CMD_WRRD_BFO) // [34:20] +#define QFIFO_CMD_PAGE_BFW 15 +#define QFIFO_CMD_COLU_BFO (7 - QFIFO_CMD_WRRD_BFO) // [19: 7] +#define QFIFO_CMD_COLU_BFW 13 // [19: 7] +#define QFIFO_BST_LEN_BFO (3 - QFIFO_CMD_WRRD_BFO) // [6:3] +#define QFIFO_BST_LEN_BFW 4 // [6:3] +#define QFIFO_CMD_WRRD_BFO 2 // [2], remove bit[1:0] +#define QFIFO_CMD_WRRD_BFW 1 // [2], remove bit[1:0] + +//====================================================// + +#define REG_SDR_CCR 0x00 +#define REG_SDR_DCR 0x04 +#define REG_SDR_IOCR 0x08 +#define REG_SDR_CSR 0x0C +#define REG_SDR_DRR 0x10 +#define REG_SDR_TPR0 0x14 +#define REG_SDR_TPR1 0x18 +#define REG_SDR_TPR2 0x1C +#define REG_SDR_MR 0x20 +#define REG_SDR_EMR1 0x24 +#define REG_SDR_EMR2 0x28 +#define REG_SDR_EMR3 0x2C +#define REG_SDR_CMD_DPIN 0x30 +#define REG_SDR_TIE_DPIN 0x34 +#define REG_SDR_BCR 0xD0 +#define REG_SDR_BST 0xD4 +#define REG_SDR_BSRAM0 0xD8 +#define REG_SDR_BSRAM1 0xDC +#define REG_SDR_PCTL_SVN_ID 0xF4 +#define REG_SDR_PCTL_IDR 0xF8 +#define REG_SDR_DLY0 0x100 + +#define REG_SDR_DLY1 0x104 +#define REG_SDR_DCM_RST 0x104 + +#define REG_SDR_DLY_CLK_PHA 0x108 +#define REG_SDR_DLY_ST 0x10C + +#define REG_SDR_MISC 0x224 +#define REG_SDR_OCP_WRAP_IDR 0x2A0 +#define REG_SDR_OCP_WRAP_VERSION 0x2A4 + + +#endif // end of "#ifndef _RTL8195A_SDR_H" diff --git a/lib/fwlib/rtl8195a/rtl8195a_spi_flash.h b/lib/fwlib/rtl8195a/rtl8195a_spi_flash.h new file mode 100644 index 0000000..1ac2c16 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_spi_flash.h @@ -0,0 +1,990 @@ +#ifndef _RTL8195A_SPI_FLASH_H +#define _RTL8195A_SPI_FLASH_H + +#define CPU_OPT_WIDTH 0x1F + +//2 REG_NOT_VALID + +//2 REG_SPIC_CTRLR0 + +#define BIT_SHIFT_CK_MTIMES 23 +#define BIT_MASK_CK_MTIMES 0x1f +#define BIT_CK_MTIMES(x) (((x) & BIT_MASK_CK_MTIMES) << BIT_SHIFT_CK_MTIMES) +#define BIT_CTRL_CK_MTIMES(x) (((x) & BIT_MASK_CK_MTIMES) << BIT_SHIFT_CK_MTIMES) +#define BIT_GET_CK_MTIMES(x) (((x) >> BIT_SHIFT_CK_MTIMES) & BIT_MASK_CK_MTIMES) + +#define BIT_FAST_RD BIT(22) +#define BIT_SHIFT_FAST_RD 22 +#define BIT_MASK_FAST_RD 0x1 +#define BIT_CTRL_FAST_RD(x) (((x) & BIT_MASK_FAST_RD) << BIT_SHIFT_FAST_RD) + + +#define BIT_SHIFT_CMD_CH 20 +#define BIT_MASK_CMD_CH 0x3 +#define BIT_CMD_CH(x) (((x) & BIT_MASK_CMD_CH) << BIT_SHIFT_CMD_CH) +#define BIT_CTRL_CMD_CH(x) (((x) & BIT_MASK_CMD_CH) << BIT_SHIFT_CMD_CH) +#define BIT_GET_CMD_CH(x) (((x) >> BIT_SHIFT_CMD_CH) & BIT_MASK_CMD_CH) + + +#define BIT_SHIFT_DATA_CH 18 +#define BIT_MASK_DATA_CH 0x3 +#define BIT_DATA_CH(x) (((x) & BIT_MASK_DATA_CH) << BIT_SHIFT_DATA_CH) +#define BIT_CTRL_DATA_CH(x) (((x) & BIT_MASK_DATA_CH) << BIT_SHIFT_DATA_CH) +#define BIT_GET_DATA_CH(x) (((x) >> BIT_SHIFT_DATA_CH) & BIT_MASK_DATA_CH) + + +#define BIT_SHIFT_ADDR_CH 16 +#define BIT_MASK_ADDR_CH 0x3 +#define BIT_ADDR_CH(x) (((x) & BIT_MASK_ADDR_CH) << BIT_SHIFT_ADDR_CH) +#define BIT_CTRL_ADDR_CH(x) (((x) & BIT_MASK_ADDR_CH) << BIT_SHIFT_ADDR_CH) +#define BIT_GET_ADDR_CH(x) (((x) >> BIT_SHIFT_ADDR_CH) & BIT_MASK_ADDR_CH) + + +#define BIT_SHIFT_TMOD 8 +#define BIT_MASK_TMOD 0x3 +#define BIT_TMOD(x) (((x) & BIT_MASK_TMOD) << BIT_SHIFT_TMOD) +#define BIT_CTRL_TMOD(x) (((x) & BIT_MASK_TMOD) << BIT_SHIFT_TMOD) +#define BIT_GET_TMOD(x) (((x) >> BIT_SHIFT_TMOD) & BIT_MASK_TMOD) + +#define BIT_SCPOL BIT(7) +#define BIT_SHIFT_SCPOL 7 +#define BIT_MASK_SCPOL 0x1 +#define BIT_CTRL_SCPOL(x) (((x) & BIT_MASK_SCPOL) << BIT_SHIFT_SCPOL) + +#define BIT_SCPH BIT(6) +#define BIT_SHIFT_SCPH 6 +#define BIT_MASK_SCPH 0x1 +#define BIT_CTRL_SCPH(x) (((x) & BIT_MASK_SCPH) << BIT_SHIFT_SCPH) + +//2 REG_SPIC_CTRLR1 + +#define BIT_SHIFT_NDF 0 +#define BIT_MASK_NDF 0xfff +#define BIT_NDF(x) (((x) & BIT_MASK_NDF) << BIT_SHIFT_NDF) +#define BIT_CTRL_NDF(x) (((x) & BIT_MASK_NDF) << BIT_SHIFT_NDF) +#define BIT_GET_NDF(x) (((x) >> BIT_SHIFT_NDF) & BIT_MASK_NDF) + + +//2 REG_SPIC_SSIENR +#define BIT_ATCK_CMD BIT(1) +#define BIT_SHIFT_ATCK_CMD 1 +#define BIT_MASK_ATCK_CMD 0x1 +#define BIT_CTRL_ATCK_CMD(x) (((x) & BIT_MASK_ATCK_CMD) << BIT_SHIFT_ATCK_CMD) + +#define BIT_SPIC_EN BIT(0) +#define BIT_SHIFT_SPIC_EN 0 +#define BIT_MASK_SPIC_EN 0x1 +#define BIT_CTRL_SPIC_EN(x) (((x) & BIT_MASK_SPIC_EN) << BIT_SHIFT_SPIC_EN) + +//2 REG_SPIC_MWCR + +//2 REG_SPIC_SER +#define BIT_SER BIT(0) +#define BIT_SHIFT_SER 0 +#define BIT_MASK_SER 0x1 +#define BIT_CTRL_SER(x) (((x) & BIT_MASK_SER) << BIT_SHIFT_SER) + +//2 REG_SPIC_BAUDR + +#define BIT_SHIFT_SCKDV 0 +#define BIT_MASK_SCKDV 0xffff +#define BIT_SCKDV(x) (((x) & BIT_MASK_SCKDV) << BIT_SHIFT_SCKDV) +#define BIT_CTRL_SCKDV(x) (((x) & BIT_MASK_SCKDV) << BIT_SHIFT_SCKDV) +#define BIT_GET_SCKDV(x) (((x) >> BIT_SHIFT_SCKDV) & BIT_MASK_SCKDV) + + +//2 REG_SPIC_TXFTLR + +#define BIT_SHIFT_TFT 0 +#define BIT_MASK_TFT 0x1f +#define BIT_TFT(x) (((x) & BIT_MASK_TFT) << BIT_SHIFT_TFT) +#define BIT_CTRL_TFT(x) (((x) & BIT_MASK_TFT) << BIT_SHIFT_TFT) +#define BIT_GET_TFT(x) (((x) >> BIT_SHIFT_TFT) & BIT_MASK_TFT) + + +//2 REG_SPIC_RXFTLR + +#define BIT_SHIFT_RFT 0 +#define BIT_MASK_RFT 0x1f +#define BIT_RFT(x) (((x) & BIT_MASK_RFT) << BIT_SHIFT_RFT) +#define BIT_CTRL_RFT(x) (((x) & BIT_MASK_RFT) << BIT_SHIFT_RFT) +#define BIT_GET_RFT(x) (((x) >> BIT_SHIFT_RFT) & BIT_MASK_RFT) + + +//2 REG_SPIC_TXFLR + +#define BIT_SHIFT_TXFL 0 +#define BIT_MASK_TXFL 0x3f +#define BIT_TXFL(x) (((x) & BIT_MASK_TXFL) << BIT_SHIFT_TXFL) +#define BIT_CTRL_TXFL(x) (((x) & BIT_MASK_TXFL) << BIT_SHIFT_TXFL) +#define BIT_GET_TXFL(x) (((x) >> BIT_SHIFT_TXFL) & BIT_MASK_TXFL) + + +//2 REG_SPIC_RXFLR + +#define BIT_SHIFT_RXFL 0 +#define BIT_MASK_RXFL 0x3f +#define BIT_RXFL(x) (((x) & BIT_MASK_RXFL) << BIT_SHIFT_RXFL) +#define BIT_CTRL_RXFL(x) (((x) & BIT_MASK_RXFL) << BIT_SHIFT_RXFL) +#define BIT_GET_RXFL(x) (((x) >> BIT_SHIFT_RXFL) & BIT_MASK_RXFL) + + +//2 REG_SPIC_SR +#define BIT_TXE BIT(5) +#define BIT_SHIFT_TXE 5 +#define BIT_MASK_TXE 0x1 +#define BIT_CTRL_TXE(x) (((x) & BIT_MASK_TXE) << BIT_SHIFT_TXE) + +#define BIT_RFF BIT(4) +#define BIT_SHIFT_RFF 4 +#define BIT_MASK_RFF 0x1 +#define BIT_CTRL_RFF(x) (((x) & BIT_MASK_RFF) << BIT_SHIFT_RFF) + +#define BIT_RFNE BIT(3) +#define BIT_SHIFT_RFNE 3 +#define BIT_MASK_RFNE 0x1 +#define BIT_CTRL_RFNE(x) (((x) & BIT_MASK_RFNE) << BIT_SHIFT_RFNE) + +#define BIT_TFE BIT(2) +#define BIT_SHIFT_TFE 2 +#define BIT_MASK_TFE 0x1 +#define BIT_CTRL_TFE(x) (((x) & BIT_MASK_TFE) << BIT_SHIFT_TFE) + +#define BIT_TFNF BIT(1) +#define BIT_SHIFT_TFNF 1 +#define BIT_MASK_TFNF 0x1 +#define BIT_CTRL_TFNF(x) (((x) & BIT_MASK_TFNF) << BIT_SHIFT_TFNF) + +#define BIT_BUSY BIT(0) +#define BIT_SHIFT_BUSY 0 +#define BIT_MASK_BUSY 0x1 +#define BIT_CTRL_BUSY(x) (((x) & BIT_MASK_BUSY) << BIT_SHIFT_BUSY) + +//2 REG_SPIC_IMR +#define BIT_TXSIM BIT(9) +#define BIT_SHIFT_TXSIM 9 +#define BIT_MASK_TXSIM 0x1 +#define BIT_CTRL_TXSIM(x) (((x) & BIT_MASK_TXSIM) << BIT_SHIFT_TXSIM) + +#define BIT_ACEIM BIT(8) +#define BIT_SHIFT_ACEIM 8 +#define BIT_MASK_ACEIM 0x1 +#define BIT_CTRL_ACEIM(x) (((x) & BIT_MASK_ACEIM) << BIT_SHIFT_ACEIM) + +#define BIT_BYEIM BIT(7) +#define BIT_SHIFT_BYEIM 7 +#define BIT_MASK_BYEIM 0x1 +#define BIT_CTRL_BYEIM(x) (((x) & BIT_MASK_BYEIM) << BIT_SHIFT_BYEIM) + +#define BIT_WBEIM BIT(6) +#define BIT_SHIFT_WBEIM 6 +#define BIT_MASK_WBEIM 0x1 +#define BIT_CTRL_WBEIM(x) (((x) & BIT_MASK_WBEIM) << BIT_SHIFT_WBEIM) + +#define BIT_FSEIM BIT(5) +#define BIT_SHIFT_FSEIM 5 +#define BIT_MASK_FSEIM 0x1 +#define BIT_CTRL_FSEIM(x) (((x) & BIT_MASK_FSEIM) << BIT_SHIFT_FSEIM) + +#define BIT_RXFIM BIT(4) +#define BIT_SHIFT_RXFIM 4 +#define BIT_MASK_RXFIM 0x1 +#define BIT_CTRL_RXFIM(x) (((x) & BIT_MASK_RXFIM) << BIT_SHIFT_RXFIM) + +#define BIT_RXOIM BIT(3) +#define BIT_SHIFT_RXOIM 3 +#define BIT_MASK_RXOIM 0x1 +#define BIT_CTRL_RXOIM(x) (((x) & BIT_MASK_RXOIM) << BIT_SHIFT_RXOIM) + +#define BIT_RXUIM BIT(2) +#define BIT_SHIFT_RXUIM 2 +#define BIT_MASK_RXUIM 0x1 +#define BIT_CTRL_RXUIM(x) (((x) & BIT_MASK_RXUIM) << BIT_SHIFT_RXUIM) + +#define BIT_TXOIM BIT(1) +#define BIT_SHIFT_TXOIM 1 +#define BIT_MASK_TXOIM 0x1 +#define BIT_CTRL_TXOIM(x) (((x) & BIT_MASK_TXOIM) << BIT_SHIFT_TXOIM) + +#define BIT_TXEIM BIT(0) +#define BIT_SHIFT_TXEIM 0 +#define BIT_MASK_TXEIM 0x1 +#define BIT_CTRL_TXEIM(x) (((x) & BIT_MASK_TXEIM) << BIT_SHIFT_TXEIM) + +//2 REG_SPIC_ISR +#define BIT_TXSIS BIT(9) +#define BIT_SHIFT_TXSIS 9 +#define BIT_MASK_TXSIS 0x1 +#define BIT_CTRL_TXSIS(x) (((x) & BIT_MASK_TXSIS) << BIT_SHIFT_TXSIS) + +#define BIT_ACEIS BIT(8) +#define BIT_SHIFT_ACEIS 8 +#define BIT_MASK_ACEIS 0x1 +#define BIT_CTRL_ACEIS(x) (((x) & BIT_MASK_ACEIS) << BIT_SHIFT_ACEIS) + +#define BIT_BYEIS BIT(7) +#define BIT_SHIFT_BYEIS 7 +#define BIT_MASK_BYEIS 0x1 +#define BIT_CTRL_BYEIS(x) (((x) & BIT_MASK_BYEIS) << BIT_SHIFT_BYEIS) + +#define BIT_WBEIS BIT(6) +#define BIT_SHIFT_WBEIS 6 +#define BIT_MASK_WBEIS 0x1 +#define BIT_CTRL_WBEIS(x) (((x) & BIT_MASK_WBEIS) << BIT_SHIFT_WBEIS) + +#define BIT_FSEIS BIT(5) +#define BIT_SHIFT_FSEIS 5 +#define BIT_MASK_FSEIS 0x1 +#define BIT_CTRL_FSEIS(x) (((x) & BIT_MASK_FSEIS) << BIT_SHIFT_FSEIS) + +#define BIT_RXFIS BIT(4) +#define BIT_SHIFT_RXFIS 4 +#define BIT_MASK_RXFIS 0x1 +#define BIT_CTRL_RXFIS(x) (((x) & BIT_MASK_RXFIS) << BIT_SHIFT_RXFIS) + +#define BIT_RXOIS BIT(3) +#define BIT_SHIFT_RXOIS 3 +#define BIT_MASK_RXOIS 0x1 +#define BIT_CTRL_RXOIS(x) (((x) & BIT_MASK_RXOIS) << BIT_SHIFT_RXOIS) + +#define BIT_RXUIS BIT(2) +#define BIT_SHIFT_RXUIS 2 +#define BIT_MASK_RXUIS 0x1 +#define BIT_CTRL_RXUIS(x) (((x) & BIT_MASK_RXUIS) << BIT_SHIFT_RXUIS) + +#define BIT_TXOIS BIT(1) +#define BIT_SHIFT_TXOIS 1 +#define BIT_MASK_TXOIS 0x1 +#define BIT_CTRL_TXOIS(x) (((x) & BIT_MASK_TXOIS) << BIT_SHIFT_TXOIS) + +#define BIT_TXEIS BIT(0) +#define BIT_SHIFT_TXEIS 0 +#define BIT_MASK_TXEIS 0x1 +#define BIT_CTRL_TXEIS(x) (((x) & BIT_MASK_TXEIS) << BIT_SHIFT_TXEIS) + +//2 REG_SPIC_RISR +#define BIT_ACEIR BIT(8) +#define BIT_SHIFT_ACEIR 8 +#define BIT_MASK_ACEIR 0x1 +#define BIT_CTRL_ACEIR(x) (((x) & BIT_MASK_ACEIR) << BIT_SHIFT_ACEIR) + +#define BIT_BYEIR BIT(7) +#define BIT_SHIFT_BYEIR 7 +#define BIT_MASK_BYEIR 0x1 +#define BIT_CTRL_BYEIR(x) (((x) & BIT_MASK_BYEIR) << BIT_SHIFT_BYEIR) + +#define BIT_WBEIR BIT(6) +#define BIT_SHIFT_WBEIR 6 +#define BIT_MASK_WBEIR 0x1 +#define BIT_CTRL_WBEIR(x) (((x) & BIT_MASK_WBEIR) << BIT_SHIFT_WBEIR) + +#define BIT_FSEIR BIT(5) +#define BIT_SHIFT_FSEIR 5 +#define BIT_MASK_FSEIR 0x1 +#define BIT_CTRL_FSEIR(x) (((x) & BIT_MASK_FSEIR) << BIT_SHIFT_FSEIR) + +#define BIT_RXFIR BIT(4) +#define BIT_SHIFT_RXFIR 4 +#define BIT_MASK_RXFIR 0x1 +#define BIT_CTRL_RXFIR(x) (((x) & BIT_MASK_RXFIR) << BIT_SHIFT_RXFIR) + +#define BIT_RXOIR BIT(3) +#define BIT_SHIFT_RXOIR 3 +#define BIT_MASK_RXOIR 0x1 +#define BIT_CTRL_RXOIR(x) (((x) & BIT_MASK_RXOIR) << BIT_SHIFT_RXOIR) + +#define BIT_RXUIR BIT(2) +#define BIT_SHIFT_RXUIR 2 +#define BIT_MASK_RXUIR 0x1 +#define BIT_CTRL_RXUIR(x) (((x) & BIT_MASK_RXUIR) << BIT_SHIFT_RXUIR) + +#define BIT_TXOIR BIT(1) +#define BIT_SHIFT_TXOIR 1 +#define BIT_MASK_TXOIR 0x1 +#define BIT_CTRL_TXOIR(x) (((x) & BIT_MASK_TXOIR) << BIT_SHIFT_TXOIR) + +#define BIT_TXEIR BIT(0) +#define BIT_SHIFT_TXEIR 0 +#define BIT_MASK_TXEIR 0x1 +#define BIT_CTRL_TXEIR(x) (((x) & BIT_MASK_TXEIR) << BIT_SHIFT_TXEIR) + +//2 REG_SPIC_TXOICR +#define BIT_TXOICR BIT(0) +#define BIT_SHIFT_TXOICR 0 +#define BIT_MASK_TXOICR 0x1 +#define BIT_CTRL_TXOICR(x) (((x) & BIT_MASK_TXOICR) << BIT_SHIFT_TXOICR) + +//2 REG_SPIC_RXOICR +#define BIT_RXOCIR BIT(0) +#define BIT_SHIFT_RXOCIR 0 +#define BIT_MASK_RXOCIR 0x1 +#define BIT_CTRL_RXOCIR(x) (((x) & BIT_MASK_RXOCIR) << BIT_SHIFT_RXOCIR) + +//2 REG_SPC_RXUICR +#define BIT_RXUICR BIT(0) +#define BIT_SHIFT_RXUICR 0 +#define BIT_MASK_RXUICR 0x1 +#define BIT_CTRL_RXUICR(x) (((x) & BIT_MASK_RXUICR) << BIT_SHIFT_RXUICR) + +//2 REG_SPIC_MSTICR +#define BIT_MSTICR BIT(0) +#define BIT_SHIFT_MSTICR 0 +#define BIT_MASK_MSTICR 0x1 +#define BIT_CTRL_MSTICR(x) (((x) & BIT_MASK_MSTICR) << BIT_SHIFT_MSTICR) + +//2 REG_SPIC_ICR + +#define BIT_SHIFT_ICR 0 +#define BIT_MASK_ICR 0xff +#define BIT_ICR(x) (((x) & BIT_MASK_ICR) << BIT_SHIFT_ICR) +#define BIT_CTRL_ICR(x) (((x) & BIT_MASK_ICR) << BIT_SHIFT_ICR) +#define BIT_GET_ICR(x) (((x) >> BIT_SHIFT_ICR) & BIT_MASK_ICR) + + +//2 REG_SPIC_DMACR + +//2 REG_SPIC_DMATDLR0 + +//2 REG_SPIC_DMATDLR1 + +//2 REG_SPIC_IDR + +#define BIT_SHIFT_IDCODE 0 +#define BIT_MASK_IDCODE 0xffffffffL +#define BIT_IDCODE(x) (((x) & BIT_MASK_IDCODE) << BIT_SHIFT_IDCODE) +#define BIT_CTRL_IDCODE(x) (((x) & BIT_MASK_IDCODE) << BIT_SHIFT_IDCODE) +#define BIT_GET_IDCODE(x) (((x) >> BIT_SHIFT_IDCODE) & BIT_MASK_IDCODE) + + +//2 REG_SPIC_VERSION + +#define BIT_SHIFT_SPIC_VERSION 0 +#define BIT_MASK_SPIC_VERSION 0xffffffffL +#define BIT_SPIC_VERSION(x) (((x) & BIT_MASK_SPIC_VERSION) << BIT_SHIFT_SPIC_VERSION) +#define BIT_CTRL_SPIC_VERSION(x) (((x) & BIT_MASK_SPIC_VERSION) << BIT_SHIFT_SPIC_VERSION) +#define BIT_GET_SPIC_VERSION(x) (((x) >> BIT_SHIFT_SPIC_VERSION) & BIT_MASK_SPIC_VERSION) + + +//2 REG_SPIC_DR0 + +#define BIT_SHIFT_DR0 0 +#define BIT_MASK_DR0 0xffffffffL +#define BIT_DR0(x) (((x) & BIT_MASK_DR0) << BIT_SHIFT_DR0) +#define BIT_CTRL_DR0(x) (((x) & BIT_MASK_DR0) << BIT_SHIFT_DR0) +#define BIT_GET_DR0(x) (((x) >> BIT_SHIFT_DR0) & BIT_MASK_DR0) + + +//2 REG_SPIC_DR1 + +#define BIT_SHIFT_DR1 0 +#define BIT_MASK_DR1 0xffffffffL +#define BIT_DR1(x) (((x) & BIT_MASK_DR1) << BIT_SHIFT_DR1) +#define BIT_CTRL_DR1(x) (((x) & BIT_MASK_DR1) << BIT_SHIFT_DR1) +#define BIT_GET_DR1(x) (((x) >> BIT_SHIFT_DR1) & BIT_MASK_DR1) + + +//2 REG_SPIC_DR2 + +#define BIT_SHIFT_DR2 0 +#define BIT_MASK_DR2 0xffffffffL +#define BIT_DR2(x) (((x) & BIT_MASK_DR2) << BIT_SHIFT_DR2) +#define BIT_CTRL_DR2(x) (((x) & BIT_MASK_DR2) << BIT_SHIFT_DR2) +#define BIT_GET_DR2(x) (((x) >> BIT_SHIFT_DR2) & BIT_MASK_DR2) + + +//2 REG_SPIC_DR3 + +#define BIT_SHIFT_DR3 0 +#define BIT_MASK_DR3 0xffffffffL +#define BIT_DR3(x) (((x) & BIT_MASK_DR3) << BIT_SHIFT_DR3) +#define BIT_CTRL_DR3(x) (((x) & BIT_MASK_DR3) << BIT_SHIFT_DR3) +#define BIT_GET_DR3(x) (((x) >> BIT_SHIFT_DR3) & BIT_MASK_DR3) + + +//2 REG_SPIC_DR4 + +#define BIT_SHIFT_DR4 0 +#define BIT_MASK_DR4 0xffffffffL +#define BIT_DR4(x) (((x) & BIT_MASK_DR4) << BIT_SHIFT_DR4) +#define BIT_CTRL_DR4(x) (((x) & BIT_MASK_DR4) << BIT_SHIFT_DR4) +#define BIT_GET_DR4(x) (((x) >> BIT_SHIFT_DR4) & BIT_MASK_DR4) + + +//2 REG_SPIC_DR5 + +#define BIT_SHIFT_DR5 0 +#define BIT_MASK_DR5 0xffffffffL +#define BIT_DR5(x) (((x) & BIT_MASK_DR5) << BIT_SHIFT_DR5) +#define BIT_CTRL_DR5(x) (((x) & BIT_MASK_DR5) << BIT_SHIFT_DR5) +#define BIT_GET_DR5(x) (((x) >> BIT_SHIFT_DR5) & BIT_MASK_DR5) + + +//2 REG_SPIC_DR6 + +#define BIT_SHIFT_DR6 0 +#define BIT_MASK_DR6 0xffffffffL +#define BIT_DR6(x) (((x) & BIT_MASK_DR6) << BIT_SHIFT_DR6) +#define BIT_CTRL_DR6(x) (((x) & BIT_MASK_DR6) << BIT_SHIFT_DR6) +#define BIT_GET_DR6(x) (((x) >> BIT_SHIFT_DR6) & BIT_MASK_DR6) + + +//2 REG_SPIC_DR7 + +#define BIT_SHIFT_DR7 0 +#define BIT_MASK_DR7 0xffffffffL +#define BIT_DR7(x) (((x) & BIT_MASK_DR7) << BIT_SHIFT_DR7) +#define BIT_CTRL_DR7(x) (((x) & BIT_MASK_DR7) << BIT_SHIFT_DR7) +#define BIT_GET_DR7(x) (((x) >> BIT_SHIFT_DR7) & BIT_MASK_DR7) + + +//2 REG_SPIC_DR8 + +#define BIT_SHIFT_DR8 0 +#define BIT_MASK_DR8 0xffffffffL +#define BIT_DR8(x) (((x) & BIT_MASK_DR8) << BIT_SHIFT_DR8) +#define BIT_CTRL_DR8(x) (((x) & BIT_MASK_DR8) << BIT_SHIFT_DR8) +#define BIT_GET_DR8(x) (((x) >> BIT_SHIFT_DR8) & BIT_MASK_DR8) + + +//2 REG_SPIC_DR9 + +#define BIT_SHIFT_DR9 0 +#define BIT_MASK_DR9 0xffffffffL +#define BIT_DR9(x) (((x) & BIT_MASK_DR9) << BIT_SHIFT_DR9) +#define BIT_CTRL_DR9(x) (((x) & BIT_MASK_DR9) << BIT_SHIFT_DR9) +#define BIT_GET_DR9(x) (((x) >> BIT_SHIFT_DR9) & BIT_MASK_DR9) + + +//2 REG_SPIC_DR10 + +#define BIT_SHIFT_DR10 0 +#define BIT_MASK_DR10 0xffffffffL +#define BIT_DR10(x) (((x) & BIT_MASK_DR10) << BIT_SHIFT_DR10) +#define BIT_CTRL_DR10(x) (((x) & BIT_MASK_DR10) << BIT_SHIFT_DR10) +#define BIT_GET_DR10(x) (((x) >> BIT_SHIFT_DR10) & BIT_MASK_DR10) + + +//2 REG_SPIC_DR11 + +#define BIT_SHIFT_DR11 0 +#define BIT_MASK_DR11 0xffffffffL +#define BIT_DR11(x) (((x) & BIT_MASK_DR11) << BIT_SHIFT_DR11) +#define BIT_CTRL_DR11(x) (((x) & BIT_MASK_DR11) << BIT_SHIFT_DR11) +#define BIT_GET_DR11(x) (((x) >> BIT_SHIFT_DR11) & BIT_MASK_DR11) + + +//2 REG_SPIC_DR12 + +#define BIT_SHIFT_DR12 0 +#define BIT_MASK_DR12 0xffffffffL +#define BIT_DR12(x) (((x) & BIT_MASK_DR12) << BIT_SHIFT_DR12) +#define BIT_CTRL_DR12(x) (((x) & BIT_MASK_DR12) << BIT_SHIFT_DR12) +#define BIT_GET_DR12(x) (((x) >> BIT_SHIFT_DR12) & BIT_MASK_DR12) + + +//2 REG_SPIC_DR13 + +#define BIT_SHIFT_DR13 0 +#define BIT_MASK_DR13 0xffffffffL +#define BIT_DR13(x) (((x) & BIT_MASK_DR13) << BIT_SHIFT_DR13) +#define BIT_CTRL_DR13(x) (((x) & BIT_MASK_DR13) << BIT_SHIFT_DR13) +#define BIT_GET_DR13(x) (((x) >> BIT_SHIFT_DR13) & BIT_MASK_DR13) + + +//2 REG_SPIC_DR14 + +#define BIT_SHIFT_DR14 0 +#define BIT_MASK_DR14 0xffffffffL +#define BIT_DR14(x) (((x) & BIT_MASK_DR14) << BIT_SHIFT_DR14) +#define BIT_CTRL_DR14(x) (((x) & BIT_MASK_DR14) << BIT_SHIFT_DR14) +#define BIT_GET_DR14(x) (((x) >> BIT_SHIFT_DR14) & BIT_MASK_DR14) + + +//2 REG_SPIC_DR15 + +#define BIT_SHIFT_DR15 0 +#define BIT_MASK_DR15 0xffffffffL +#define BIT_DR15(x) (((x) & BIT_MASK_DR15) << BIT_SHIFT_DR15) +#define BIT_CTRL_DR15(x) (((x) & BIT_MASK_DR15) << BIT_SHIFT_DR15) +#define BIT_GET_DR15(x) (((x) >> BIT_SHIFT_DR15) & BIT_MASK_DR15) + + +//2 REG_SPIC_DR16 + +#define BIT_SHIFT_DR16 0 +#define BIT_MASK_DR16 0xffffffffL +#define BIT_DR16(x) (((x) & BIT_MASK_DR16) << BIT_SHIFT_DR16) +#define BIT_CTRL_DR16(x) (((x) & BIT_MASK_DR16) << BIT_SHIFT_DR16) +#define BIT_GET_DR16(x) (((x) >> BIT_SHIFT_DR16) & BIT_MASK_DR16) + + +//2 REG_SPIC_DR17 + +#define BIT_SHIFT_DR17 0 +#define BIT_MASK_DR17 0xffffffffL +#define BIT_DR17(x) (((x) & BIT_MASK_DR17) << BIT_SHIFT_DR17) +#define BIT_CTRL_DR17(x) (((x) & BIT_MASK_DR17) << BIT_SHIFT_DR17) +#define BIT_GET_DR17(x) (((x) >> BIT_SHIFT_DR17) & BIT_MASK_DR17) + + +//2 REG_SPIC_DR18 + +#define BIT_SHIFT_DR18 0 +#define BIT_MASK_DR18 0xffffffffL +#define BIT_DR18(x) (((x) & BIT_MASK_DR18) << BIT_SHIFT_DR18) +#define BIT_CTRL_DR18(x) (((x) & BIT_MASK_DR18) << BIT_SHIFT_DR18) +#define BIT_GET_DR18(x) (((x) >> BIT_SHIFT_DR18) & BIT_MASK_DR18) + + +//2 REG_SPIC_DR19 + +#define BIT_SHIFT_DR19 0 +#define BIT_MASK_DR19 0xffffffffL +#define BIT_DR19(x) (((x) & BIT_MASK_DR19) << BIT_SHIFT_DR19) +#define BIT_CTRL_DR19(x) (((x) & BIT_MASK_DR19) << BIT_SHIFT_DR19) +#define BIT_GET_DR19(x) (((x) >> BIT_SHIFT_DR19) & BIT_MASK_DR19) + + +//2 REG_SPIC_DR20 + +#define BIT_SHIFT_DR20 0 +#define BIT_MASK_DR20 0xffffffffL +#define BIT_DR20(x) (((x) & BIT_MASK_DR20) << BIT_SHIFT_DR20) +#define BIT_CTRL_DR20(x) (((x) & BIT_MASK_DR20) << BIT_SHIFT_DR20) +#define BIT_GET_DR20(x) (((x) >> BIT_SHIFT_DR20) & BIT_MASK_DR20) + + +//2 REG_SPIC_DR21 + +#define BIT_SHIFT_DR21 0 +#define BIT_MASK_DR21 0xffffffffL +#define BIT_DR21(x) (((x) & BIT_MASK_DR21) << BIT_SHIFT_DR21) +#define BIT_CTRL_DR21(x) (((x) & BIT_MASK_DR21) << BIT_SHIFT_DR21) +#define BIT_GET_DR21(x) (((x) >> BIT_SHIFT_DR21) & BIT_MASK_DR21) + + +//2 REG_SPIC_DR22 + +#define BIT_SHIFT_DR22 0 +#define BIT_MASK_DR22 0xffffffffL +#define BIT_DR22(x) (((x) & BIT_MASK_DR22) << BIT_SHIFT_DR22) +#define BIT_CTRL_DR22(x) (((x) & BIT_MASK_DR22) << BIT_SHIFT_DR22) +#define BIT_GET_DR22(x) (((x) >> BIT_SHIFT_DR22) & BIT_MASK_DR22) + + +//2 REG_SPIC_DR23 + +#define BIT_SHIFT_DR23 0 +#define BIT_MASK_DR23 0xffffffffL +#define BIT_DR23(x) (((x) & BIT_MASK_DR23) << BIT_SHIFT_DR23) +#define BIT_CTRL_DR23(x) (((x) & BIT_MASK_DR23) << BIT_SHIFT_DR23) +#define BIT_GET_DR23(x) (((x) >> BIT_SHIFT_DR23) & BIT_MASK_DR23) + + +//2 REG_SPIC_DR24 + +#define BIT_SHIFT_DR24 0 +#define BIT_MASK_DR24 0xffffffffL +#define BIT_DR24(x) (((x) & BIT_MASK_DR24) << BIT_SHIFT_DR24) +#define BIT_CTRL_DR24(x) (((x) & BIT_MASK_DR24) << BIT_SHIFT_DR24) +#define BIT_GET_DR24(x) (((x) >> BIT_SHIFT_DR24) & BIT_MASK_DR24) + + +//2 REG_SPIC_DR25 + +#define BIT_SHIFT_DR25 0 +#define BIT_MASK_DR25 0xffffffffL +#define BIT_DR25(x) (((x) & BIT_MASK_DR25) << BIT_SHIFT_DR25) +#define BIT_CTRL_DR25(x) (((x) & BIT_MASK_DR25) << BIT_SHIFT_DR25) +#define BIT_GET_DR25(x) (((x) >> BIT_SHIFT_DR25) & BIT_MASK_DR25) + + +//2 REG_SPIC_DR26 + +#define BIT_SHIFT_DR26 0 +#define BIT_MASK_DR26 0xffffffffL +#define BIT_DR26(x) (((x) & BIT_MASK_DR26) << BIT_SHIFT_DR26) +#define BIT_CTRL_DR26(x) (((x) & BIT_MASK_DR26) << BIT_SHIFT_DR26) +#define BIT_GET_DR26(x) (((x) >> BIT_SHIFT_DR26) & BIT_MASK_DR26) + + +//2 REG_SPIC_DR27 + +#define BIT_SHIFT_DR27 0 +#define BIT_MASK_DR27 0xffffffffL +#define BIT_DR27(x) (((x) & BIT_MASK_DR27) << BIT_SHIFT_DR27) +#define BIT_CTRL_DR27(x) (((x) & BIT_MASK_DR27) << BIT_SHIFT_DR27) +#define BIT_GET_DR27(x) (((x) >> BIT_SHIFT_DR27) & BIT_MASK_DR27) + + +//2 REG_SPIC_DR28 + +#define BIT_SHIFT_DR28 0 +#define BIT_MASK_DR28 0xffffffffL +#define BIT_DR28(x) (((x) & BIT_MASK_DR28) << BIT_SHIFT_DR28) +#define BIT_CTRL_DR28(x) (((x) & BIT_MASK_DR28) << BIT_SHIFT_DR28) +#define BIT_GET_DR28(x) (((x) >> BIT_SHIFT_DR28) & BIT_MASK_DR28) + + +//2 REG_SPIC_DR29 + +#define BIT_SHIFT_DR29 0 +#define BIT_MASK_DR29 0xffffffffL +#define BIT_DR29(x) (((x) & BIT_MASK_DR29) << BIT_SHIFT_DR29) +#define BIT_CTRL_DR29(x) (((x) & BIT_MASK_DR29) << BIT_SHIFT_DR29) +#define BIT_GET_DR29(x) (((x) >> BIT_SHIFT_DR29) & BIT_MASK_DR29) + + +//2 REG_SPIC_DR30 + +#define BIT_SHIFT_DR30 0 +#define BIT_MASK_DR30 0xffffffffL +#define BIT_DR30(x) (((x) & BIT_MASK_DR30) << BIT_SHIFT_DR30) +#define BIT_CTRL_DR30(x) (((x) & BIT_MASK_DR30) << BIT_SHIFT_DR30) +#define BIT_GET_DR30(x) (((x) >> BIT_SHIFT_DR30) & BIT_MASK_DR30) + + +//2 REG_SPIC_DR31 + +#define BIT_SHIFT_DR31 0 +#define BIT_MASK_DR31 0xffffffffL +#define BIT_DR31(x) (((x) & BIT_MASK_DR31) << BIT_SHIFT_DR31) +#define BIT_CTRL_DR31(x) (((x) & BIT_MASK_DR31) << BIT_SHIFT_DR31) +#define BIT_GET_DR31(x) (((x) >> BIT_SHIFT_DR31) & BIT_MASK_DR31) + + +//2 REG_SPIC_READ_FAST_SINGLE + +#define BIT_SHIFT_FRD_CMD 0 +#define BIT_MASK_FRD_CMD 0xff +#define BIT_FRD_CMD(x) (((x) & BIT_MASK_FRD_CMD) << BIT_SHIFT_FRD_CMD) +#define BIT_CTRL_FRD_CMD(x) (((x) & BIT_MASK_FRD_CMD) << BIT_SHIFT_FRD_CMD) +#define BIT_GET_FRD_CMD(x) (((x) >> BIT_SHIFT_FRD_CMD) & BIT_MASK_FRD_CMD) + + +//2 REG_SPIC_READ_DUAL_DATA + +#define BIT_SHIFT_RD_DUAL_O_CMD 0 +#define BIT_MASK_RD_DUAL_O_CMD 0xff +#define BIT_RD_DUAL_O_CMD(x) (((x) & BIT_MASK_RD_DUAL_O_CMD) << BIT_SHIFT_RD_DUAL_O_CMD) +#define BIT_CTRL_RD_DUAL_O_CMD(x) (((x) & BIT_MASK_RD_DUAL_O_CMD) << BIT_SHIFT_RD_DUAL_O_CMD) +#define BIT_GET_RD_DUAL_O_CMD(x) (((x) >> BIT_SHIFT_RD_DUAL_O_CMD) & BIT_MASK_RD_DUAL_O_CMD) + + +//2 REG_SPIC_READ_DUAL_ADDR_DATA + +#define BIT_SHIFT_RD_DUAL_IO_CMD 0 +#define BIT_MASK_RD_DUAL_IO_CMD 0xff +#define BIT_RD_DUAL_IO_CMD(x) (((x) & BIT_MASK_RD_DUAL_IO_CMD) << BIT_SHIFT_RD_DUAL_IO_CMD) +#define BIT_CTRL_RD_DUAL_IO_CMD(x) (((x) & BIT_MASK_RD_DUAL_IO_CMD) << BIT_SHIFT_RD_DUAL_IO_CMD) +#define BIT_GET_RD_DUAL_IO_CMD(x) (((x) >> BIT_SHIFT_RD_DUAL_IO_CMD) & BIT_MASK_RD_DUAL_IO_CMD) + + +//2 REG_SPIC_READ_QUAD_DATA + +#define BIT_SHIFT_RD_QUAD_O_CMD 0 +#define BIT_MASK_RD_QUAD_O_CMD 0xff +#define BIT_RD_QUAD_O_CMD(x) (((x) & BIT_MASK_RD_QUAD_O_CMD) << BIT_SHIFT_RD_QUAD_O_CMD) +#define BIT_CTRL_RD_QUAD_O_CMD(x) (((x) & BIT_MASK_RD_QUAD_O_CMD) << BIT_SHIFT_RD_QUAD_O_CMD) +#define BIT_GET_RD_QUAD_O_CMD(x) (((x) >> BIT_SHIFT_RD_QUAD_O_CMD) & BIT_MASK_RD_QUAD_O_CMD) + + +//2 REG_SPIC_READ_QUAD_ADDR_DATA + +#define BIT_SHIFT_RD_QUAD_IO_CMD 0 +#define BIT_MASK_RD_QUAD_IO_CMD 0xff +#define BIT_RD_QUAD_IO_CMD(x) (((x) & BIT_MASK_RD_QUAD_IO_CMD) << BIT_SHIFT_RD_QUAD_IO_CMD) +#define BIT_CTRL_RD_QUAD_IO_CMD(x) (((x) & BIT_MASK_RD_QUAD_IO_CMD) << BIT_SHIFT_RD_QUAD_IO_CMD) +#define BIT_GET_RD_QUAD_IO_CMD(x) (((x) >> BIT_SHIFT_RD_QUAD_IO_CMD) & BIT_MASK_RD_QUAD_IO_CMD) + + +//2 REG_SPIC_WRITE_SIGNLE + +#define BIT_SHIFT_WR_CMD 0 +#define BIT_MASK_WR_CMD 0xff +#define BIT_WR_CMD(x) (((x) & BIT_MASK_WR_CMD) << BIT_SHIFT_WR_CMD) +#define BIT_CTRL_WR_CMD(x) (((x) & BIT_MASK_WR_CMD) << BIT_SHIFT_WR_CMD) +#define BIT_GET_WR_CMD(x) (((x) >> BIT_SHIFT_WR_CMD) & BIT_MASK_WR_CMD) + + +//2 REG_SPIC_WRITE_DUAL_DATA + +#define BIT_SHIFT_WR_DUAL_I_CMD 0 +#define BIT_MASK_WR_DUAL_I_CMD 0xff +#define BIT_WR_DUAL_I_CMD(x) (((x) & BIT_MASK_WR_DUAL_I_CMD) << BIT_SHIFT_WR_DUAL_I_CMD) +#define BIT_CTRL_WR_DUAL_I_CMD(x) (((x) & BIT_MASK_WR_DUAL_I_CMD) << BIT_SHIFT_WR_DUAL_I_CMD) +#define BIT_GET_WR_DUAL_I_CMD(x) (((x) >> BIT_SHIFT_WR_DUAL_I_CMD) & BIT_MASK_WR_DUAL_I_CMD) + + +//2 REG_SPIC_WRITE_DUAL_ADDR_DATA + +#define BIT_SHIFT_WR_DUAL_II_CMD 0 +#define BIT_MASK_WR_DUAL_II_CMD 0xff +#define BIT_WR_DUAL_II_CMD(x) (((x) & BIT_MASK_WR_DUAL_II_CMD) << BIT_SHIFT_WR_DUAL_II_CMD) +#define BIT_CTRL_WR_DUAL_II_CMD(x) (((x) & BIT_MASK_WR_DUAL_II_CMD) << BIT_SHIFT_WR_DUAL_II_CMD) +#define BIT_GET_WR_DUAL_II_CMD(x) (((x) >> BIT_SHIFT_WR_DUAL_II_CMD) & BIT_MASK_WR_DUAL_II_CMD) + + +//2 REG_SPIC_WRITE_QUAD_DATA + +#define BIT_SHIFT_WR_QUAD_I_CMD 0 +#define BIT_MASK_WR_QUAD_I_CMD 0xff +#define BIT_WR_QUAD_I_CMD(x) (((x) & BIT_MASK_WR_QUAD_I_CMD) << BIT_SHIFT_WR_QUAD_I_CMD) +#define BIT_CTRL_WR_QUAD_I_CMD(x) (((x) & BIT_MASK_WR_QUAD_I_CMD) << BIT_SHIFT_WR_QUAD_I_CMD) +#define BIT_GET_WR_QUAD_I_CMD(x) (((x) >> BIT_SHIFT_WR_QUAD_I_CMD) & BIT_MASK_WR_QUAD_I_CMD) + + +//2 REG_SPIC_WRITE_QUAD_ADDR_DATA + +#define BIT_SHIFT_WR_QUAD_II_CMD 0 +#define BIT_MASK_WR_QUAD_II_CMD 0xff +#define BIT_WR_QUAD_II_CMD(x) (((x) & BIT_MASK_WR_QUAD_II_CMD) << BIT_SHIFT_WR_QUAD_II_CMD) +#define BIT_CTRL_WR_QUAD_II_CMD(x) (((x) & BIT_MASK_WR_QUAD_II_CMD) << BIT_SHIFT_WR_QUAD_II_CMD) +#define BIT_GET_WR_QUAD_II_CMD(x) (((x) >> BIT_SHIFT_WR_QUAD_II_CMD) & BIT_MASK_WR_QUAD_II_CMD) + + +//2 REG_SPIC_WRITE_ENABLE + +#define BIT_SHIFT_WR_EN_CMD 0 +#define BIT_MASK_WR_EN_CMD 0xff +#define BIT_WR_EN_CMD(x) (((x) & BIT_MASK_WR_EN_CMD) << BIT_SHIFT_WR_EN_CMD) +#define BIT_CTRL_WR_EN_CMD(x) (((x) & BIT_MASK_WR_EN_CMD) << BIT_SHIFT_WR_EN_CMD) +#define BIT_GET_WR_EN_CMD(x) (((x) >> BIT_SHIFT_WR_EN_CMD) & BIT_MASK_WR_EN_CMD) + + +//2 REG_SPIC_READ_STATUS + +#define BIT_SHIFT_RD_ST_CMD 0 +#define BIT_MASK_RD_ST_CMD 0xff +#define BIT_RD_ST_CMD(x) (((x) & BIT_MASK_RD_ST_CMD) << BIT_SHIFT_RD_ST_CMD) +#define BIT_CTRL_RD_ST_CMD(x) (((x) & BIT_MASK_RD_ST_CMD) << BIT_SHIFT_RD_ST_CMD) +#define BIT_GET_RD_ST_CMD(x) (((x) >> BIT_SHIFT_RD_ST_CMD) & BIT_MASK_RD_ST_CMD) + + +//2 REG_SPIC_CTRLR2 + +#define BIT_SHIFT_FIFO_ENTRY 4 +#define BIT_MASK_FIFO_ENTRY 0xf +#define BIT_FIFO_ENTRY(x) (((x) & BIT_MASK_FIFO_ENTRY) << BIT_SHIFT_FIFO_ENTRY) +#define BIT_CTRL_FIFO_ENTRY(x) (((x) & BIT_MASK_FIFO_ENTRY) << BIT_SHIFT_FIFO_ENTRY) +#define BIT_GET_FIFO_ENTRY(x) (((x) >> BIT_SHIFT_FIFO_ENTRY) & BIT_MASK_FIFO_ENTRY) + +#define BIT_WR_SEQ BIT(3) +#define BIT_SHIFT_WR_SEQ 3 +#define BIT_MASK_WR_SEQ 0x1 +#define BIT_CTRL_WR_SEQ(x) (((x) & BIT_MASK_WR_SEQ) << BIT_SHIFT_WR_SEQ) + +#define BIT_WPN_DNUM BIT(2) +#define BIT_SHIFT_WPN_DNUM 2 +#define BIT_MASK_WPN_DNUM 0x1 +#define BIT_CTRL_WPN_DNUM(x) (((x) & BIT_MASK_WPN_DNUM) << BIT_SHIFT_WPN_DNUM) + +#define BIT_WPN_SET BIT(1) +#define BIT_SHIFT_WPN_SET 1 +#define BIT_MASK_WPN_SET 0x1 +#define BIT_CTRL_WPN_SET(x) (((x) & BIT_MASK_WPN_SET) << BIT_SHIFT_WPN_SET) + +#define BIT_SO_DUM BIT(0) +#define BIT_SHIFT_SO_DUM 0 +#define BIT_MASK_SO_DUM 0x1 +#define BIT_CTRL_SO_DUM(x) (((x) & BIT_MASK_SO_DUM) << BIT_SHIFT_SO_DUM) + +//2 REG_SPIC_FBAUDR + +#define BIT_SHIFT_FSCKDV 0 +#define BIT_MASK_FSCKDV 0xfff +#define BIT_FSCKDV(x) (((x) & BIT_MASK_FSCKDV) << BIT_SHIFT_FSCKDV) +#define BIT_CTRL_FSCKDV(x) (((x) & BIT_MASK_FSCKDV) << BIT_SHIFT_FSCKDV) +#define BIT_GET_FSCKDV(x) (((x) >> BIT_SHIFT_FSCKDV) & BIT_MASK_FSCKDV) + + +//2 REG_SPIC_ADDR_LENGTH + +#define BIT_SHIFT_ADDR_PHASE_LENGTH 0 +#define BIT_MASK_ADDR_PHASE_LENGTH 0x3 +#define BIT_ADDR_PHASE_LENGTH(x) (((x) & BIT_MASK_ADDR_PHASE_LENGTH) << BIT_SHIFT_ADDR_PHASE_LENGTH) +#define BIT_CTRL_ADDR_PHASE_LENGTH(x) (((x) & BIT_MASK_ADDR_PHASE_LENGTH) << BIT_SHIFT_ADDR_PHASE_LENGTH) +#define BIT_GET_ADDR_PHASE_LENGTH(x) (((x) >> BIT_SHIFT_ADDR_PHASE_LENGTH) & BIT_MASK_ADDR_PHASE_LENGTH) + + +//2 REG_SPIC_AUTO_LENGTH + +#define BIT_SHIFT_CS_H_WR_DUM_LEN 28 +#define BIT_MASK_CS_H_WR_DUM_LEN 0xf +#define BIT_CS_H_WR_DUM_LEN(x) (((x) & BIT_MASK_CS_H_WR_DUM_LEN) << BIT_SHIFT_CS_H_WR_DUM_LEN) +#define BIT_CTRL_CS_H_WR_DUM_LEN(x) (((x) & BIT_MASK_CS_H_WR_DUM_LEN) << BIT_SHIFT_CS_H_WR_DUM_LEN) +#define BIT_GET_CS_H_WR_DUM_LEN(x) (((x) >> BIT_SHIFT_CS_H_WR_DUM_LEN) & BIT_MASK_CS_H_WR_DUM_LEN) + + +#define BIT_SHIFT_CS_H_RD_DUM_LEN 26 +#define BIT_MASK_CS_H_RD_DUM_LEN 0x3 +#define BIT_CS_H_RD_DUM_LEN(x) (((x) & BIT_MASK_CS_H_RD_DUM_LEN) << BIT_SHIFT_CS_H_RD_DUM_LEN) +#define BIT_CTRL_CS_H_RD_DUM_LEN(x) (((x) & BIT_MASK_CS_H_RD_DUM_LEN) << BIT_SHIFT_CS_H_RD_DUM_LEN) +#define BIT_GET_CS_H_RD_DUM_LEN(x) (((x) >> BIT_SHIFT_CS_H_RD_DUM_LEN) & BIT_MASK_CS_H_RD_DUM_LEN) + + +#define BIT_SHIFT_AUTO_DUM_LEN 18 +#define BIT_MASK_AUTO_DUM_LEN 0xff +#define BIT_AUTO_DUM_LEN(x) (((x) & BIT_MASK_AUTO_DUM_LEN) << BIT_SHIFT_AUTO_DUM_LEN) +#define BIT_CTRL_AUTO_DUM_LEN(x) (((x) & BIT_MASK_AUTO_DUM_LEN) << BIT_SHIFT_AUTO_DUM_LEN) +#define BIT_GET_AUTO_DUM_LEN(x) (((x) >> BIT_SHIFT_AUTO_DUM_LEN) & BIT_MASK_AUTO_DUM_LEN) + + +#define BIT_SHIFT_AUTO_ADDR__LENGTH 16 +#define BIT_MASK_AUTO_ADDR__LENGTH 0x3 +#define BIT_AUTO_ADDR__LENGTH(x) (((x) & BIT_MASK_AUTO_ADDR__LENGTH) << BIT_SHIFT_AUTO_ADDR__LENGTH) +#define BIT_CTRL_AUTO_ADDR__LENGTH(x) (((x) & BIT_MASK_AUTO_ADDR__LENGTH) << BIT_SHIFT_AUTO_ADDR__LENGTH) +#define BIT_GET_AUTO_ADDR__LENGTH(x) (((x) >> BIT_SHIFT_AUTO_ADDR__LENGTH) & BIT_MASK_AUTO_ADDR__LENGTH) + + +#define BIT_SHIFT_RD_DUMMY_LENGTH 0 +#define BIT_MASK_RD_DUMMY_LENGTH 0xffff +#define BIT_RD_DUMMY_LENGTH(x) (((x) & BIT_MASK_RD_DUMMY_LENGTH) << BIT_SHIFT_RD_DUMMY_LENGTH) +#define BIT_CTRL_RD_DUMMY_LENGTH(x) (((x) & BIT_MASK_RD_DUMMY_LENGTH) << BIT_SHIFT_RD_DUMMY_LENGTH) +#define BIT_GET_RD_DUMMY_LENGTH(x) (((x) >> BIT_SHIFT_RD_DUMMY_LENGTH) & BIT_MASK_RD_DUMMY_LENGTH) + + +//2 REG_SPIC_VALID_CMD +#define BIT_WR_BLOCKING BIT(9) +#define BIT_SHIFT_WR_BLOCKING 9 +#define BIT_MASK_WR_BLOCKING 0x1 +#define BIT_CTRL_WR_BLOCKING(x) (((x) & BIT_MASK_WR_BLOCKING) << BIT_SHIFT_WR_BLOCKING) + +#define BIT_WR_QUAD_II BIT(8) +#define BIT_SHIFT_WR_QUAD_II 8 +#define BIT_MASK_WR_QUAD_II 0x1 +#define BIT_CTRL_WR_QUAD_II(x) (((x) & BIT_MASK_WR_QUAD_II) << BIT_SHIFT_WR_QUAD_II) + +#define BIT_WR_QUAD_I BIT(7) +#define BIT_SHIFT_WR_QUAD_I 7 +#define BIT_MASK_WR_QUAD_I 0x1 +#define BIT_CTRL_WR_QUAD_I(x) (((x) & BIT_MASK_WR_QUAD_I) << BIT_SHIFT_WR_QUAD_I) + +#define BIT_WR_DUAL_II BIT(6) +#define BIT_SHIFT_WR_DUAL_II 6 +#define BIT_MASK_WR_DUAL_II 0x1 +#define BIT_CTRL_WR_DUAL_II(x) (((x) & BIT_MASK_WR_DUAL_II) << BIT_SHIFT_WR_DUAL_II) + +#define BIT_WR_DUAL_I BIT(5) +#define BIT_SHIFT_WR_DUAL_I 5 +#define BIT_MASK_WR_DUAL_I 0x1 +#define BIT_CTRL_WR_DUAL_I(x) (((x) & BIT_MASK_WR_DUAL_I) << BIT_SHIFT_WR_DUAL_I) + +#define BIT_RD_QUAD_IO BIT(4) +#define BIT_SHIFT_RD_QUAD_IO 4 +#define BIT_MASK_RD_QUAD_IO 0x1 +#define BIT_CTRL_RD_QUAD_IO(x) (((x) & BIT_MASK_RD_QUAD_IO) << BIT_SHIFT_RD_QUAD_IO) + +#define BIT_RD_QUAD_O BIT(3) +#define BIT_SHIFT_RD_QUAD_O 3 +#define BIT_MASK_RD_QUAD_O 0x1 +#define BIT_CTRL_RD_QUAD_O(x) (((x) & BIT_MASK_RD_QUAD_O) << BIT_SHIFT_RD_QUAD_O) + +#define BIT_RD_DUAL_IO BIT(2) +#define BIT_SHIFT_RD_DUAL_IO 2 +#define BIT_MASK_RD_DUAL_IO 0x1 +#define BIT_CTRL_RD_DUAL_IO(x) (((x) & BIT_MASK_RD_DUAL_IO) << BIT_SHIFT_RD_DUAL_IO) + +#define BIT_RD_DUAL_I BIT(1) +#define BIT_SHIFT_RD_DUAL_I 1 +#define BIT_MASK_RD_DUAL_I 0x1 +#define BIT_CTRL_RD_DUAL_I(x) (((x) & BIT_MASK_RD_DUAL_I) << BIT_SHIFT_RD_DUAL_I) + +#define BIT_FRD_SINGEL BIT(0) +#define BIT_SHIFT_FRD_SINGEL 0 +#define BIT_MASK_FRD_SINGEL 0x1 +#define BIT_CTRL_FRD_SINGEL(x) (((x) & BIT_MASK_FRD_SINGEL) << BIT_SHIFT_FRD_SINGEL) + +//2 REG_SPIC_FLASE_SIZE + +#define BIT_SHIFT_FLASE_SIZE 0 +#define BIT_MASK_FLASE_SIZE 0xf +#define BIT_FLASE_SIZE(x) (((x) & BIT_MASK_FLASE_SIZE) << BIT_SHIFT_FLASE_SIZE) +#define BIT_CTRL_FLASE_SIZE(x) (((x) & BIT_MASK_FLASE_SIZE) << BIT_SHIFT_FLASE_SIZE) +#define BIT_GET_FLASE_SIZE(x) (((x) >> BIT_SHIFT_FLASE_SIZE) & BIT_MASK_FLASE_SIZE) + + +//2 REG_SPIC_FLUSH_FIFO +#define BIT_FLUSH_FIFO BIT(0) +#define BIT_SHIFT_FLUSH_FIFO 0 +#define BIT_MASK_FLUSH_FIFO 0x1 +#define BIT_CTRL_FLUSH_FIFO(x) (((x) & BIT_MASK_FLUSH_FIFO) << BIT_SHIFT_FLUSH_FIFO) + +//=================== Register Address Definition ============================// +#define REG_SPIC_CTRLR0 0x0000//O +#define REG_SPIC_CTRLR1 0x0004//O +#define REG_SPIC_SSIENR 0x0008//O +#define REG_SPIC_MWCR 0x000C +#define REG_SPIC_SER 0x0010//O +#define REG_SPIC_BAUDR 0x0014//O +#define REG_SPIC_TXFTLR 0x0018 +#define REG_SPIC_RXFTLR 0x001C//O +#define REG_SPIC_TXFLR 0x0020//O +#define REG_SPIC_RXFLR 0x0024 +#define REG_SPIC_SR 0x0028 +#define REG_SPIC_IMR 0x002C//O +#define REG_SPIC_ISR 0x0030 +#define REG_SPIC_RISR 0x0034 +#define REG_SPIC_TXOICR 0x0038 +#define REG_SPIC_RXOICR 0x003C +#define REG_SPC_RXUICR 0x0040 +#define REG_SPIC_MSTICR 0x0044 +#define REG_SPIC_ICR 0x0048 +#define REG_SPIC_DMACR 0x004C +#define REG_SPIC_DMATDLR0 0x0050 +#define REG_SPIC_DMATDLR1 0x0054 +#define REG_SPIC_IDR 0x0058 +#define REG_SPIC_VERSION 0x005C +#define REG_SPIC_DR0 0x0060 +#define REG_SPIC_DR1 0x0064 +#define REG_SPIC_DR2 0x0068 +#define REG_SPIC_DR3 0x006C +#define REG_SPIC_DR4 0x0070 +#define REG_SPIC_DR5 0x0074 +#define REG_SPIC_DR6 0x0078 +#define REG_SPIC_DR7 0x007C +#define REG_SPIC_DR8 0x0080 +#define REG_SPIC_DR9 0x0084 +#define REG_SPIC_DR10 0x0088 +#define REG_SPIC_DR11 0x008C +#define REG_SPIC_DR12 0x0090 +#define REG_SPIC_DR13 0x0094 +#define REG_SPIC_DR14 0x0098 +#define REG_SPIC_DR15 0x009C +#define REG_SPIC_DR16 0x00A0 +#define REG_SPIC_DR17 0x00A4 +#define REG_SPIC_DR18 0x00A8 +#define REG_SPIC_DR19 0x00AC +#define REG_SPIC_DR20 0x00B0 +#define REG_SPIC_DR21 0x00B4 +#define REG_SPIC_DR22 0x00B8 +#define REG_SPIC_DR23 0x00BC +#define REG_SPIC_DR24 0x00C0 +#define REG_SPIC_DR25 0x00C4 +#define REG_SPIC_DR26 0x00C8 +#define REG_SPIC_DR27 0x00CC +#define REG_SPIC_DR28 0x00D0 +#define REG_SPIC_DR29 0x00D4 +#define REG_SPIC_DR30 0x00D8 +#define REG_SPIC_DR31 0x00DC +#define REG_SPIC_READ_FAST_SINGLE 0x00E0//O +#define REG_SPIC_READ_DUAL_DATA 0x00E4//O +#define REG_SPIC_READ_DUAL_ADDR_DATA 0x00E8//O +#define REG_SPIC_READ_QUAD_DATA 0x00EC//O +#define REG_SPIC_READ_QUAD_ADDR_DATA 0x00F0//O +#define REG_SPIC_WRITE_SIGNLE 0x00F4//O +#define REG_SPIC_WRITE_DUAL_DATA 0x00F8//O +#define REG_SPIC_WRITE_DUAL_ADDR_DATA 0x00FC//O +#define REG_SPIC_WRITE_QUAD_DATA 0x0100//O +#define REG_SPIC_WRITE_QUAD_ADDR_DATA 0x0104//O +#define REG_SPIC_WRITE_ENABLE 0x0108//O +#define REG_SPIC_READ_STATUS 0x010C//O +#define REG_SPIC_CTRLR2 0x0110//O +#define REG_SPIC_FBAUDR 0x0114//O +#define REG_SPIC_ADDR_LENGTH 0x0118//O +#define REG_SPIC_AUTO_LENGTH 0x011C//O +#define REG_SPIC_VALID_CMD 0x0120//O +#define REG_SPIC_FLASE_SIZE 0x0124//O +#define REG_SPIC_FLUSH_FIFO 0x0128//O + +#endif // end of "#ifndef _RTL8195A_SPI_FLASH_H" diff --git a/lib/fwlib/rtl8195a/rtl8195a_ssi.h b/lib/fwlib/rtl8195a/rtl8195a_ssi.h new file mode 100644 index 0000000..3e940e2 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_ssi.h @@ -0,0 +1,498 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _RTL8195A_SSI_H_ +#define _RTL8195A_SSI_H_ + +#define SSI_DUMMY_DATA 0x00 // for master mode, we need to push a Dummy data to TX FIFO for read + +#define SSI_CLK_SPI1 (PLATFORM_CLOCK/2) +#define SSI_CLK_SPI0_2 (PLATFORM_CLOCK/4) + +/* Parameters of DW_apb_ssi for RTL8195A */ +#define SSI_TX_FIFO_DEPTH 64 +#define TX_ABW 6 // 1-8, log2(SSI_TX_FIFO_DEPTH) +#define SSI_RX_FIFO_DEPTH 64 +#define RX_ABW 6 // 1-8, log2(SSI_RX_FIFO_DEPTH) + +#define SSI0_REG_BASE 0x40042000 +#define SSI1_REG_BASE 0x40042400 +#define SSI2_REG_BASE 0x40042800 + +/* Memory Map of DW_apb_ssi */ +#define REG_DW_SSI_CTRLR0 0x00 // 16 bits +#define REG_DW_SSI_CTRLR1 0x04 // 16 bits +#define REG_DW_SSI_SSIENR 0x08 // 1 bit +#define REG_DW_SSI_MWCR 0x0C // 3 bits +#define REG_DW_SSI_SER 0x10 // +#define REG_DW_SSI_BAUDR 0x14 // 16 bits +#define REG_DW_SSI_TXFTLR 0x18 // TX_ABW +#define REG_DW_SSI_RXFTLR 0x1C // RX_ABW +#define REG_DW_SSI_TXFLR 0x20 // +#define REG_DW_SSI_RXFLR 0x24 // +#define REG_DW_SSI_SR 0x28 // 7 bits +#define REG_DW_SSI_IMR 0x2C // +#define REG_DW_SSI_ISR 0x30 // 6 bits +#define REG_DW_SSI_RISR 0x34 // 6 bits +#define REG_DW_SSI_TXOICR 0x38 // 1 bits +#define REG_DW_SSI_RXOICR 0x3C // 1 bits +#define REG_DW_SSI_RXUICR 0x40 // 1 bits +#define REG_DW_SSI_MSTICR 0x44 // 1 bits +#define REG_DW_SSI_ICR 0x48 // 1 bits +#define REG_DW_SSI_DMACR 0x4C // 2 bits +#define REG_DW_SSI_DMATDLR 0x50 // TX_ABW +#define REG_DW_SSI_DMARDLR 0x54 // RX_ABW +#define REG_DW_SSI_IDR 0x58 // 32 bits +#define REG_DW_SSI_COMP_VERSION 0x5C // 32 bits +#define REG_DW_SSI_DR 0x60 // 16 bits 0x60-0xEC +#define REG_DW_SSI_RX_SAMPLE_DLY 0xF0 // 8 bits +#define REG_DW_SSI_RSVD_0 0xF4 // 32 bits +#define REG_DW_SSI_RSVD_1 0xF8 // 32 bits +#define REG_DW_SSI_RSVD_2 0xFC // 32 bits + +// CTRLR0 0x00 // 16 bits, 6.2.1 +// DFS Reset Value: 0x7 +#define BIT_SHIFT_CTRLR0_DFS 0 +#define BIT_MASK_CTRLR0_DFS 0xF +#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS) +#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS)) + +#define BIT_SHIFT_CTRLR0_FRF 4 +#define BIT_MASK_CTRLR0_FRF 0x3 +#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF) +#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF)) + +#define BIT_SHIFT_CTRLR0_SCPH 6 +#define BIT_MASK_CTRLR0_SCPH 0x1 +#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH) +#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH)) + +#define BIT_SHIFT_CTRLR0_SCPOL 7 +#define BIT_MASK_CTRLR0_SCPOL 0x1 +#define BIT_CTRLR0_SCPOL(x)(((x) & BIT_MASK_CTRLR0_SCPOL) << BIT_SHIFT_CTRLR0_SCPOL) +#define BIT_INVC_CTRLR0_SCPOL (~(BIT_MASK_CTRLR0_SCPOL << BIT_SHIFT_CTRLR0_SCPOL)) + +#define BIT_SHIFT_CTRLR0_TMOD 8 +#define BIT_MASK_CTRLR0_TMOD 0x3 +#define BIT_CTRLR0_TMOD(x)(((x) & BIT_MASK_CTRLR0_TMOD) << BIT_SHIFT_CTRLR0_TMOD) +#define BIT_INVC_CTRLR0_TMOD (~(BIT_MASK_CTRLR0_TMOD << BIT_SHIFT_CTRLR0_TMOD)) + +#define BIT_SHIFT_CTRLR0_SLV_OE 10 +#define BIT_MASK_CTRLR0_SLV_OE 0x1 +#define BIT_CTRLR0_SLV_OE(x)(((x) & BIT_MASK_CTRLR0_SLV_OE) << BIT_SHIFT_CTRLR0_SLV_OE) +#define BIT_INVC_CTRLR0_SLV_OE (~(BIT_MASK_CTRLR0_SLV_OE << BIT_SHIFT_CTRLR0_SLV_OE)) + +#define BIT_SHIFT_CTRLR0_SRL 11 +#define BIT_MASK_CTRLR0_SRL 0x1 +#define BIT_CTRLR0_SRL(x)(((x) & BIT_MASK_CTRLR0_SRL) << BIT_SHIFT_CTRLR0_SRL) +#define BIT_INVC_CTRLR0_SRL (~(BIT_MASK_CTRLR0_SRL << BIT_SHIFT_CTRLR0_SRL)) + +#define BIT_SHIFT_CTRLR0_CFS 12 +#define BIT_MASK_CTRLR0_CFS 0xF +#define BIT_CTRLR0_CFS(x)(((x) & BIT_MASK_CTRLR0_CFS) << BIT_SHIFT_CTRLR0_CFS) +#define BIT_INVC_CTRLR0_CFS (~(BIT_MASK_CTRLR0_CFS << BIT_SHIFT_CTRLR0_CFS)) + +// CTRLR1 0x04 // 16 bits +#define BIT_SHIFT_CTRLR1_NDF 0 +#define BIT_MASK_CTRLR1_NDF 0xFFFF +#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF) +#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF)) + +// SSIENR 0x08 // 1 bit +#define BIT_SHIFT_SSIENR_SSI_EN 0 +#define BIT_MASK_SSIENR_SSI_EN 0x1 +#define BIT_SSIENR_SSI_EN(x)(((x) & BIT_MASK_SSIENR_SSI_EN) << BIT_SHIFT_SSIENR_SSI_EN) +#define BIT_INVC_SSIENR_SSI_EN (~(BIT_MASK_SSIENR_SSI_EN << BIT_SHIFT_SSIENR_SSI_EN)) + +// MWCR 0x0c // 3 bits +#define BIT_SHIFT_MWCR_MWMOD 0 +#define BIT_MASK_MWCR_MWMOD 0x1 +#define BIT_MWCR_MWMOD(x)(((x) & BIT_MASK_MWCR_MWMOD) << BIT_SHIFT_MWCR_MWMOD) +#define BIT_INVC_MWCR_MWMOD (~(BIT_MASK_MWCR_MWMOD << BIT_SHIFT_MWCR_MWMOD)) + +#define BIT_SHIFT_MWCR_MDD 1 +#define BIT_MASK_MWCR_MDD 0x1 +#define BIT_MWCR_MDD(x)(((x) & BIT_MASK_MWCR_MDD) << BIT_SHIFT_MWCR_MDD) +#define BIT_INVC_MWCR_MDD (~(BIT_MASK_MWCR_MDD << BIT_SHIFT_MWCR_MDD)) + +#define BIT_SHIFT_MWCR_MHS 2 +#define BIT_MASK_MWCR_MHS 0x1 +#define BIT_MWCR_MHS(x)(((x) & BIT_MASK_MWCR_MHS) << BIT_SHIFT_MWCR_MHS) +#define BIT_INVC_MWCR_MHS (~(BIT_MASK_MWCR_MHS << BIT_SHIFT_MWCR_MHS)) + +// SER 0x10 // Variable Length +#define BIT_SHIFT_SER_SER 0 +#define BIT_MASK_SER_SER 0xFF +#define BIT_SER_SER(x)(((x) & BIT_MASK_SER_SER) << BIT_SHIFT_SER_SER) +#define BIT_INVC_SER_SER (~(BIT_MASK_SER_SER << BIT_SHIFT_SER_SER)) + +// BAUDR 0x14 // 16 bits +#define BIT_SHIFT_BAUDR_SCKDV 0 +#define BIT_MASK_BAUDR_SCKDV 0xFFFF +#define BIT_BAUDR_SCKDV(x)(((x) & BIT_MASK_BAUDR_SCKDV) << BIT_SHIFT_BAUDR_SCKDV) +#define BIT_INVC_BAUDR_SCKDV (~(BIT_MASK_BAUDR_SCKDV << BIT_SHIFT_BAUDR_SCKDV)) + +// TXFLTR 0x18 // Variable Length +#define BIT_SHIFT_TXFTLR_TFT 0 +#define BIT_MASK_TXFTLR_TFT 0x3F // (TX_ABW-1):0 +#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT) +#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT)) + +// RXFLTR 0x1c // Variable Length +#define BIT_SHIFT_RXFTLR_RFT 0 +#define BIT_MASK_RXFTLR_RFT 0x3F // (RX_ABW-1):0 +#define BIT_RXFTLR_RFT(x)(((x) & BIT_MASK_RXFTLR_RFT) << BIT_SHIFT_RXFTLR_RFT) +#define BIT_INVC_RXFTLR_RFT (~(BIT_MASK_RXFTLR_RFT << BIT_SHIFT_RXFTLR_RFT)) + +// TXFLR 0x20 // see [READ ONLY] +#define BIT_MASK_TXFLR_TXTFL 0x7F // (TX_ABW):0 + +// RXFLR 0x24 // see [READ ONLY] +#define BIT_MASK_RXFLR_RXTFL 0x7F // (RX_ABW):0 + +// SR 0x28 // 7 bits [READ ONLY] +#define BIT_SR_BUSY BIT0 +#define BIT_SR_TFNF BIT1 +#define BIT_SR_TFE BIT2 +#define BIT_SR_RFNE BIT3 +#define BIT_SR_RFF BIT4 +#define BIT_SR_TXE BIT5 +#define BIT_SR_DCOL BIT6 + +// IMR 0x2c // see +#define BIT_SHIFT_IMR_TXEIM 0 +#define BIT_MASK_IMR_TXEIM 0x1 +// #define BIT_IMR_TXEIM(x)(((x) & BIT_MASK_IMR_TXEIM) << BIT_SHIFT_IMR_TXEIM) +#define BIT_INVC_IMR_TXEIM (~(BIT_MASK_IMR_TXEIM << BIT_SHIFT_IMR_TXEIM)) + +#define BIT_SHIFT_IMR_TXOIM 1 +#define BIT_MASK_IMR_TXOIM 0x1 +// #define BIT_IMR_TXOIM(x)(((x) & BIT_MASK_IMR_TXOIM) << BIT_SHIFT_IMR_TXOIM) +#define BIT_INVC_IMR_TXOIM (~(BIT_MASK_IMR_TXOIM << BIT_SHIFT_IMR_TXOIM)) + +#define BIT_SHIFT_IMR_RXUIM 2 +#define BIT_MASK_IMR_RXUIM 0x1 +// #define BIT_IMR_RXUIM(x)(((x) & BIT_MASK_IMR_RXUIM) << BIT_SHIFT_IMR_RXUIM) +#define BIT_INVC_IMR_RXUIM (~(BIT_MASK_IMR_RXUIM << BIT_SHIFT_IMR_RXUIM)) + +#define BIT_SHIFT_IMR_RXOIM 3 +#define BIT_MASK_IMR_RXOIM 0x1 +// #define BIT_IMR_RXOIM(x)(((x) & BIT_MASK_IMR_RXOIM) << BIT_SHIFT_IMR_RXOIM) +#define BIT_INVC_IMR_RXOIM (~(BIT_MASK_IMR_RXOIM << BIT_SHIFT_IMR_RXOIM)) + +#define BIT_SHIFT_IMR_RXFIM 4 +#define BIT_MASK_IMR_RXFIM 0x1 +// #define BIT_IMR_RXFIM(x)(((x) & BIT_MASK_IMR_RXFIM) << BIT_SHIFT_IMR_RXFIM) +#define BIT_INVC_IMR_RXFIM (~(BIT_MASK_IMR_RXFIM << BIT_SHIFT_IMR_RXFIM)) + +#define BIT_SHIFT_IMR_MSTIM 5 +#define BIT_MASK_IMR_MSTIM 0x1 +// #define BIT_IMR_MSTIM(x)(((x) & BIT_MASK_IMR_MSTIM) << BIT_SHIFT_IMR_MSTIM) +#define BIT_INVC_IMR_MSTIM (~(BIT_MASK_IMR_MSTIM << BIT_SHIFT_IMR_MSTIM)) + +#define BIT_IMR_TXEIM BIT0 +#define BIT_IMR_TXOIM BIT1 +#define BIT_IMR_RXUIM BIT2 +#define BIT_IMR_RXOIM BIT3 +#define BIT_IMR_RXFIM BIT4 +#define BIT_IMR_MSTIM BIT5 + +// ISR 0x30 // 6 bits [READ ONLY] +#define BIT_ISR_TXEIS BIT0 +#define BIT_ISR_TXOIS BIT1 +#define BIT_ISR_RXUIS BIT2 +#define BIT_ISR_RXOIS BIT3 +#define BIT_ISR_RXFIS BIT4 +#define BIT_ISR_MSTIS BIT5 + +// RISR 0x34 // 6 bits [READ ONLY] +#define BIT_RISR_TXEIR BIT0 +#define BIT_RISR_TXOIR BIT1 +#define BIT_RISR_RXUIR BIT2 +#define BIT_RISR_RXOIR BIT3 +#define BIT_RISR_RXFIR BIT4 +#define BIT_RISR_MSTIR BIT5 + +// TXOICR 0x38 // 1 bits [READ ONLY] +// RXOICR 0x3c // 1 bits [READ ONLY] +// RXUICR 0x40 // 1 bits [READ ONLY] +// MSTICR 0x44 // 1 bits [READ ONLY] +// ICR 0x48 // 1 bits [READ ONLY] + +// DMACR 0x4c // 2 bits +#define BIT_SHIFT_DMACR_RDMAE 0 +#define BIT_MASK_DMACR_RDMAE 0x1 +#define BIT_DMACR_RDMAE(x)(((x) & BIT_MASK_DMACR_RDMAE) << BIT_SHIFT_DMACR_RDMAE) +#define BIT_INVC_DMACR_RDMAE (~(BIT_MASK_DMACR_RDMAE << BIT_SHIFT_DMACR_RDMAE)) + +#define BIT_SHIFT_DMACR_TDMAE 1 +#define BIT_MASK_DMACR_TDMAE 0x1 +#define BIT_DMACR_TDMAE(x)(((x) & BIT_MASK_DMACR_TDMAE) << BIT_SHIFT_DMACR_TDMAE) +#define BIT_INVC_DMACR_TDMAE (~(BIT_MASK_DMACR_TDMAE << BIT_SHIFT_DMACR_TDMAE)) + +// DMATDLR 0x50 +#define BIT_SHIFT_DMATDLR_DMATDL 0 +#define BIT_MASK_DMATDLR_DMATDL 0x3F // (TX_ABW-1):0 +#define BIT_DMATDLR_DMATDL(x)(((x) & BIT_MASK_DMATDLR_DMATDL) << BIT_SHIFT_DMATDLR_DMATDL) +#define BIT_INVC_DMATDLR_DMATDL (~(BIT_MASK_DMATDLR_DMATDL << BIT_SHIFT_DMATDLR_DMATDL)) + +// DMARDLR 0x54 +#define BIT_SHIFT_DMARDLR_DMARDL 0 +#define BIT_MASK_DMARDLR_DMARDL 0x3F // (RX_ABW-1):0 +#define BIT_DMARDLR_DMARDL(x)(((x) & BIT_MASK_DMARDLR_DMARDL) << BIT_SHIFT_DMARDLR_DMARDL) +#define BIT_INVC_DMARDLR_DMARDL (~(BIT_MASK_DMARDLR_DMARDL << BIT_SHIFT_DMARDLR_DMARDL)) + +// IDR 0x58 // 32 bits [READ ONLY] +// COMP_VERSION 0x5c // 32 bits [READ ONLY] + +// DR 0x60 // 16 bits 0x60-0xEC +#define BIT_SHIFT_DR_DR 0 +#define BIT_MASK_DR_DR 0xFFFF +#define BIT_DR_DR(x)(((x) & BIT_MASK_DR_DR) << BIT_SHIFT_DR_DR) +#define BIT_INVC_DR_DR (~(BIT_MASK_DR_DR << BIT_SHIFT_DR_DR)) + +// RX_SAMPLE_DLY 0xF0 // 8 bits +#define BIT_SHIFT_RX_SAMPLE_DLY_RSD 0 +#define BIT_MASK_RX_SAMPLE_DLY_RSD 0xFFFF +#define BIT_RX_SAMPLE_DLY_RSD(x)(((x) & BIT_MASK_RX_SAMPLE_DLY_RSD) << BIT_SHIFT_RX_SAMPLE_DLY_RSD) +#define BIT_INVC_RX_SAMPLE_DLY_RSD (~(BIT_MASK_RX_SAMPLE_DLY_RSD << BIT_SHIFT_RX_SAMPLE_DLY_RSD)) + +// RSVD_0 0xF4 // 32 bits +// RSVD_1 0xF8 // 32 bits +// RSVD_2 0xFC // 32 bits + +// SSI0 Pinmux +#define BIT_SHIFT_SSI0_PIN_EN 0 +#define BIT_MASK_SSI0_PIN_EN 0x1 +#define BIT_SSI0_PIN_EN(x)(((x) & BIT_MASK_SSI0_PIN_EN) << BIT_SHIFT_SSI0_PIN_EN) +#define BIT_INVC_SSI0_PIN_EN (~(BIT_MASK_SSI0_PIN_EN << BIT_SHIFT_SSI0_PIN_EN)) + +#define BIT_SHIFT_SSI0_PIN_SEL 1 +#define BIT_MASK_SSI0_PIN_SEL 0x7 +#define BIT_SSI0_PIN_SEL(x)(((x) & BIT_MASK_SSI0_PIN_SEL) << BIT_SHIFT_SSI0_PIN_SEL) +#define BIT_INVC_SSI0_PIN_SEL (~(BIT_MASK_SSI0_PIN_SEL << BIT_SHIFT_SSI0_PIN_SEL)) + +// SSI1 Pinmux +#define BIT_SHIFT_SSI1_PIN_EN 4 +#define BIT_MASK_SSI1_PIN_EN 0x1 +#define BIT_SSI1_PIN_EN(x)(((x) & BIT_MASK_SSI1_PIN_EN) << BIT_SHIFT_SSI1_PIN_EN) +#define BIT_INVC_SSI1_PIN_EN (~(BIT_MASK_SSI1_PIN_EN << BIT_SHIFT_SSI1_PIN_EN)) + +#define BIT_SHIFT_SSI1_PIN_SEL 5 +#define BIT_MASK_SSI1_PIN_SEL 0x7 +#define BIT_SSI1_PIN_SEL(x)(((x) & BIT_MASK_SSI1_PIN_SEL) << BIT_SHIFT_SSI1_PIN_SEL) +#define BIT_INVC_SSI1_PIN_SEL (~(BIT_MASK_SSI1_PIN_SEL << BIT_SHIFT_SSI1_PIN_SEL)) + +// SSI2 Pinmux +#define BIT_SHIFT_SSI2_PIN_EN 8 +#define BIT_MASK_SSI2_PIN_EN 0x1 +#define BIT_SSI2_PIN_EN(x)(((x) & BIT_MASK_SSI2_PIN_EN) << BIT_SHIFT_SSI2_PIN_EN) +#define BIT_INVC_SSI2_PIN_EN (~(BIT_MASK_SSI2_PIN_EN << BIT_SHIFT_SSI2_PIN_EN)) + +#define BIT_SHIFT_SSI2_PIN_SEL 9 +#define BIT_MASK_SSI2_PIN_SEL 0x7 +#define BIT_SSI2_PIN_SEL(x)(((x) & BIT_MASK_SSI2_PIN_SEL) << BIT_SHIFT_SSI2_PIN_SEL) +#define BIT_INVC_SSI2_PIN_SEL (~(BIT_MASK_SSI2_PIN_SEL << BIT_SHIFT_SSI2_PIN_SEL)) + +// SSI0 Multiple Chip Selection (Pinmux Select is controlled by BIT_SSI0_PIN_SEL) +#define BIT_SHIFT_SSI0_MULTI_CS_EN 28 +#define BIT_MASK_SSI0_MULTI_CS_EN 0x1 +#define BIT_SSI0_MULTI_CS_EN(x)(((x) & BIT_MASK_SSI0_MULTI_CS_EN) << BIT_SHIFT_SSI0_MULTI_CS_EN) +#define BIT_INVC_SSI0_MULTI_CS_EN (~(BIT_MASK_SSI0_MULTI_CS_EN << BIT_SHIFT_SSI0_MULTI_CS_EN)) + + +#define HAL_SSI_READ32(SsiIndex, addr) \ + HAL_READ32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr) +#define HAL_SSI_WRITE32(SsiIndex, addr, value) \ + HAL_WRITE32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value) +#define HAL_SSI_READ16(SsiIndex, addr) \ + HAL_READ16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr) +#define HAL_SSI_WRITE16(SsiIndex, addr, value) \ + HAL_WRITE16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value) +#define HAL_SSI_READ8(SsiIndex, addr) \ + HAL_READ8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr) +#define HAL_SSI_WRITE8(SsiIndex, addr, value) \ + HAL_WRITE8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value) + + +// SSI Pinmux Select +typedef enum _SSI0_PINMUX_SELECT_ { + SSI0_MUX_TO_GPIOE = S0, + SSI0_MUX_TO_GPIOC = S1 +}SSI0_PINMUX_SELECT, *PSSI0_PINMUX_SELECT; + +typedef enum _SSI1_PINMUX_SELECT_ { + SSI1_MUX_TO_GPIOA = S0, + SSI1_MUX_TO_GPIOB = S1, + SSI1_MUX_TO_GPIOD = S2 +}SSI1_PINMUX_SELECT, *PSSI1_PINMUX_SELECT; + +typedef enum _SSI2_PINMUX_SELECT_ { + SSI2_MUX_TO_GPIOG = S0, + SSI2_MUX_TO_GPIOE = S1, + SSI2_MUX_TO_GPIOD = S2 +}SSI2_PINMUX_SELECT, *PSSI2_PINMUX_SELECT; + +typedef enum _SSI0_MULTI_CS_PINMUX_SELECT_ { + SSI0_CS_MUX_TO_GPIOE = S0, + SSI0_CS_MUX_TO_GPIOC = S1 +}SSI0_MULTI_CS_PINMUX_SELECT, *PSSI0_MULTI_CS_PINMUX_SELECT; + +typedef enum _SSI_CTRLR0_TMOD_ { + TMOD_TR = 0, + TMOD_TO = 1, + TMOD_RO = 2, + TMOD_EEPROM_R = 3 +}SSI_CTRLR0_TMOD, *PSSI_CTRLR0_TMOD; + +typedef enum _SSI_CTRLR0_SCPOL_ { + SCPOL_INACTIVE_IS_LOW = 0, + SCPOL_INACTIVE_IS_HIGH = 1 +}SSI_CTRLR0_SCPOL, *PSSI_CTRLR0_SCPOL; + +typedef enum _SSI_CTRLR0_SCPH_ { + SCPH_TOGGLES_IN_MIDDLE = 0, + SCPH_TOGGLES_AT_START = 1 +}SSI_CTRLR0_SCPH, *PSSI_CTRLR0_SCPH; + +typedef enum _SSI_CTRLR0_DFS_ { + DFS_4_BITS = 3, + DFS_5_BITS = 4, + DFS_6_BITS = 5, + DFS_7_BITS = 6, + DFS_8_BITS = 7, + DFS_9_BITS = 8, + DFS_10_BITS = 9, + DFS_11_BITS = 10, + DFS_12_BITS = 11, + DFS_13_BITS = 12, + DFS_14_BITS = 13, + DFS_15_BITS = 14, + DFS_16_BITS = 15, +}SSI_CTRLR0_DFS, *PSSI_CTRLR0_DFS; + +typedef enum _SSI_CTRLR0_CFS_ { + CFS_1_BIT = 0, + CFS_2_BITS = 1, + CFS_3_BITS = 2, + CFS_4_BITS = 3, + CFS_5_BITS = 4, + CFS_6_BITS = 5, + CFS_7_BITS = 6, + CFS_8_BITS = 7, + CFS_9_BITS = 8, + CFS_10_BITS = 9, + CFS_11_BITS = 10, + CFS_12_BITS = 11, + CFS_13_BITS = 12, + CFS_14_BITS = 13, + CFS_15_BITS = 14, + CFS_16_BITS = 15 +}SSI_CTRLR0_CFS, *PSSI_CTRLR0_CFS; + +typedef enum _SSI_CTRLR0_SLV_OE_ { + SLV_TXD_ENABLE = 0, + SLV_TXD_DISABLE = 1 +}SSI_CTRLR0_SLV_OE, *PSSI_CTRLR0_SLV_OE; + +typedef enum _SSI_ROLE_SELECT_ { + SSI_SLAVE = 0, + SSI_MASTER = 1 +}SSI_ROLE_SELECT, *PSSI_ROLE_SELECT; + +typedef enum _SSI_FRAME_FORMAT_ { + FRF_MOTOROLA_SPI = 0, + FRF_TI_SSP = 1, + FRF_NS_MICROWIRE = 2, + FRF_RSVD = 3 +}SSI_FRAME_FORMAT, *PSSI_FRAME_FORMAT; + +typedef enum _SSI_DMACR_ENABLE_ { + SSI_NODMA = 0, + SSI_RXDMA_ENABLE = 1, + SSI_TXDMA_ENABLE = 2, + SSI_TRDMA_ENABLE = 3 +}SSI_DMACR_ENABLE, *PSSI_DMACR_ENABLE; + +typedef enum _SSI_MWCR_HANDSHAKE_ { + MW_HANDSHAKE_DISABLE = 0, + MW_HANDSHAKE_ENABLE = 1 +}SSI_MWCR_HANDSHAKE, *PSSI_MWCR_HANDSHAKE; + +typedef enum _SSI_MWCR_DIRECTION_ { + MW_DIRECTION_SLAVE_TO_MASTER = 0, + MW_DIRECTION_MASTER_TO_SLAVE = 1 +}SSI_MWCR_DIRECTION, *PSSI_MWCR_DIRECTION; + +typedef enum _SSI_MWCR_TMOD_ { + MW_TMOD_NONSEQUENTIAL = 0, + MW_TMOD_SEQUENTIAL = 1 +}SSI_MWCR_TMOD, *PSSI_MWCR_TMOD; + +typedef enum _SSI_DATA_TRANSFER_MECHANISM_ { + SSI_DTM_BASIC, + SSI_DTM_INTERRUPT, + SSI_DTM_DMA +}SSI_DATA_TRANSFER_MECHANISM, *PSSI_DATA_TRANSFER_MECHANISM; + + +_LONG_CALL_ HAL_Status HalSsiPinmuxEnableRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiEnableRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiDisableRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiInitRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiSetSclkPolarityRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiSetSclkPhaseRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiWriteRtl8195a(VOID *Adaptor, u32 value); +_LONG_CALL_ HAL_Status HalSsiLoadSettingRtl8195a(VOID *Adaptor, VOID *Setting); +_LONG_CALL_ HAL_Status HalSsiSetInterruptMaskRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiSetDeviceRoleRtl8195a(VOID *Adaptor, u32 Role); +_LONG_CALL_ HAL_Status HalSsiInterruptEnableRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiInterruptDisableRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiReadInterruptRtl8195a(VOID *Adaptor, VOID *RxData, u32 Length); +_LONG_CALL_ HAL_Status HalSsiSetRxFifoThresholdLevelRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiSetTxFifoThresholdLevelRtl8195a(VOID *Adaptor); +_LONG_CALL_ HAL_Status HalSsiWriteInterruptRtl8195a(VOID *Adaptor, VOID *TxData, u32 Length); +_LONG_CALL_ HAL_Status HalSsiSetSlaveEnableRegisterRtl8195a(VOID *Adaptor, u32 SlaveIndex); +_LONG_CALL_ u32 HalSsiBusyRtl8195a(VOID *Adaptor); +_LONG_CALL_ u32 HalSsiWriteableRtl8195a(VOID *Adaptor); +_LONG_CALL_ u32 HalSsiReadableRtl8195a(VOID *Adaptor); +_LONG_CALL_ u32 HalSsiGetInterruptMaskRtl8195a(VOID *Adaptor); +_LONG_CALL_ u32 HalSsiGetRxFifoLevelRtl8195a(VOID *Adaptor); +_LONG_CALL_ u32 HalSsiGetTxFifoLevelRtl8195a(VOID *Adaptor); +_LONG_CALL_ u32 HalSsiGetStatusRtl8195a(VOID *Adaptor); +_LONG_CALL_ u32 HalSsiGetInterruptStatusRtl8195a(VOID *Adaptor); +_LONG_CALL_ u32 HalSsiReadRtl8195a(VOID *Adaptor); +_LONG_CALL_ u32 HalSsiGetRawInterruptStatusRtl8195a(VOID *Adaptor); +_LONG_CALL_ u32 HalSsiGetSlaveEnableRegisterRtl8195a(VOID *Adaptor); + +_LONG_CALL_ VOID _SsiReadInterrupt(VOID *Adaptor); +_LONG_CALL_ VOID _SsiWriteInterrupt(VOID *Adaptor); +_LONG_CALL_ u32 _SsiIrqHandle(VOID *Adaptor); + +// ROM code patch +VOID _SsiReadInterruptRtl8195a(VOID *Adapter); +VOID _SsiWriteInterruptRtl8195a(VOID *Adapter); +HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor); +HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor); +HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor); +HAL_Status HalSsiDeInitRtl8195a(VOID * Adapter); +HAL_Status HalSsiClockOffRtl8195a(VOID * Adapter); +HAL_Status HalSsiClockOnRtl8195a(VOID * Adapter); +VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate); +HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length); +HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length); +#ifdef CONFIG_GDMA_EN +VOID HalSsiTxGdmaLoadDefRtl8195a(VOID *Adapter); +VOID HalSsiRxGdmaLoadDefRtl8195a(VOID *Adapter); +VOID HalSsiDmaInitRtl8195a(VOID *Adapter); +HAL_Status HalSsiDmaSendRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length); +HAL_Status HalSsiDmaRecvRtl8195a(VOID *Adapter, u8 *pRxData, u32 Length); +#endif // end of "#ifdef CONFIG_GDMA_EN" + +#endif diff --git a/lib/fwlib/rtl8195a/rtl8195a_sys_on.h b/lib/fwlib/rtl8195a/rtl8195a_sys_on.h new file mode 100644 index 0000000..2c5ef62 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_sys_on.h @@ -0,0 +1,1093 @@ +#ifndef __INC_RTL8195A_SYS_ON_BIT_H +#define __INC_RTL8195A_SYS_ON_BIT_H + +#define CPU_OPT_WIDTH 0x1F + +//2 REG_NOT_VALID + +//2 REG_SYS_PWR_CTRL + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID +#define BIT_SYS_PWR_SOC_EN BIT(2) +#define BIT_SYS_PWR_RET_MEM_EN BIT(1) +#define BIT_SYS_PWR_PEON_EN BIT(0) + +//2 REG_SYS_ISO_CTRL + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID +#define BIT_SYS_ISO_SYSPLL BIT(7) + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID +#define BIT_SYS_ISO_SOC BIT(2) +#define BIT_SYS_ISO_RET_MEM BIT(1) +#define BIT_SYS_ISO_PEON BIT(0) + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_SYS_FUNC_EN +#define BIT_SYS_AMACRO_EN BIT(31) +#define BIT_SYS_PWRON_TRAP_SHTDN_N BIT(30) +#define BIT_SYS_FEN_SIC_MST BIT(25) +#define BIT_SYS_FEN_SIC BIT(24) + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID +#define BIT_SOC_SYSPEON_EN BIT(4) + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID +#define BIT_SYS_FEN_EELDR BIT(0) + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_SYS_CLK_CTRL0 + +//2 REG_NOT_VALID +#define BIT_SOC_OCP_IOBUS_CK_EN BIT(2) +#define BIT_SYSON_CK_EELDR_EN BIT(1) +#define BIT_SYSON_CK_SYSREG_EN BIT(0) + +//2 REG_SYS_CLK_CTRL1 + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +#define BIT_SHIFT_PESOC_OCP_CPU_CK_SEL 4 +#define BIT_MASK_PESOC_OCP_CPU_CK_SEL 0x7 +#define BIT_PESOC_OCP_CPU_CK_SEL(x) (((x) & BIT_MASK_PESOC_OCP_CPU_CK_SEL) << BIT_SHIFT_PESOC_OCP_CPU_CK_SEL) + + +//2 REG_NOT_VALID +#define BIT_PESOC_EELDR_CK_SEL BIT(0) + +//2 REG_SYS_SWR_CTRL3 + +//2 REG_RSV_CTRL + +//2 REG_RF_CTRL + +//2 REG_SYS_EFUSE_SYSCFG0 + +#define BIT_SHIFT_SYS_EEROM_SWR_PAR_05_00 24 +#define BIT_MASK_SYS_EEROM_SWR_PAR_05_00 0x3f +#define BIT_SYS_EEROM_SWR_PAR_05_00(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_05_00) << BIT_SHIFT_SYS_EEROM_SWR_PAR_05_00) + + +#define BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04 20 +#define BIT_MASK_SYS_EEROM_LDO_PAR_07_04 0xf +#define BIT_SYS_EEROM_LDO_PAR_07_04(x) (((x) & BIT_MASK_SYS_EEROM_LDO_PAR_07_04) << BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04) + +#define BIT_SYS_CHIPPDN_EN BIT(17) +#define BIT_SYS_EEROM_B12V_EN BIT(16) + +#define BIT_SHIFT_SYS_EEROM_VID1 8 +#define BIT_MASK_SYS_EEROM_VID1 0xff +#define BIT_SYS_EEROM_VID1(x) (((x) & BIT_MASK_SYS_EEROM_VID1) << BIT_SHIFT_SYS_EEROM_VID1) + + +#define BIT_SHIFT_SYS_EEROM_VID0 0 +#define BIT_MASK_SYS_EEROM_VID0 0xff +#define BIT_SYS_EEROM_VID0(x) (((x) & BIT_MASK_SYS_EEROM_VID0) << BIT_SHIFT_SYS_EEROM_VID0) + + +//2 REG_SYS_EFUSE_SYSCFG1 + +#define BIT_SHIFT_SYS_PDSPL_STL 24 +#define BIT_MASK_SYS_PDSPL_STL 0x3 +#define BIT_SYS_PDSPL_STL(x) (((x) & BIT_MASK_SYS_PDSPL_STL) << BIT_SHIFT_SYS_PDSPL_STL) + + +#define BIT_SHIFT_SYS_PDSOC_STL 22 +#define BIT_MASK_SYS_PDSOC_STL 0x3 +#define BIT_SYS_PDSOC_STL(x) (((x) & BIT_MASK_SYS_PDSOC_STL) << BIT_SHIFT_SYS_PDSOC_STL) + + +#define BIT_SHIFT_SYS_PDPON_STL 20 +#define BIT_MASK_SYS_PDPON_STL 0x3 +#define BIT_SYS_PDPON_STL(x) (((x) & BIT_MASK_SYS_PDPON_STL) << BIT_SHIFT_SYS_PDPON_STL) + + +#define BIT_SHIFT_SYS_SWREG_XRT 18 +#define BIT_MASK_SYS_SWREG_XRT 0x3 +#define BIT_SYS_SWREG_XRT(x) (((x) & BIT_MASK_SYS_SWREG_XRT) << BIT_SHIFT_SYS_SWREG_XRT) + + +#define BIT_SHIFT_SYS_SWSLC_STL 16 +#define BIT_MASK_SYS_SWSLC_STL 0x3 +#define BIT_SYS_SWSLC_STL(x) (((x) & BIT_MASK_SYS_SWSLC_STL) << BIT_SHIFT_SYS_SWSLC_STL) + + +#define BIT_SHIFT_SYS_EEROM_SWR_PAR_46_45 14 +#define BIT_MASK_SYS_EEROM_SWR_PAR_46_45 0x3 +#define BIT_SYS_EEROM_SWR_PAR_46_45(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_46_45) << BIT_SHIFT_SYS_EEROM_SWR_PAR_46_45) + + +#define BIT_SHIFT_SYS_EEROM_SWR_PAR_40_39 12 +#define BIT_MASK_SYS_EEROM_SWR_PAR_40_39 0x3 +#define BIT_SYS_EEROM_SWR_PAR_40_39(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_40_39) << BIT_SHIFT_SYS_EEROM_SWR_PAR_40_39) + + +#define BIT_SHIFT_SYS_EEROM_SWR_PAR_33_26 4 +#define BIT_MASK_SYS_EEROM_SWR_PAR_33_26 0xff +#define BIT_SYS_EEROM_SWR_PAR_33_26(x) (((x) & BIT_MASK_SYS_EEROM_SWR_PAR_33_26) << BIT_SHIFT_SYS_EEROM_SWR_PAR_33_26) + + +#define BIT_SHIFT_SYS_EEROM_SWSLD_VOL 0 +#define BIT_MASK_SYS_EEROM_SWSLD_VOL 0x7 +#define BIT_SYS_EEROM_SWSLD_VOL(x) (((x) & BIT_MASK_SYS_EEROM_SWSLD_VOL) << BIT_SHIFT_SYS_EEROM_SWSLD_VOL) + + +//2 REG_SYS_EFUSE_SYSCFG2 + +#define BIT_SHIFT_SYS_EERROM_ANAPAR_SPLL_24_15 21 +#define BIT_MASK_SYS_EERROM_ANAPAR_SPLL_24_15 0x3ff +#define BIT_SYS_EERROM_ANAPAR_SPLL_24_15(x) (((x) & BIT_MASK_SYS_EERROM_ANAPAR_SPLL_24_15) << BIT_SHIFT_SYS_EERROM_ANAPAR_SPLL_24_15) + + +#define BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_05_02 16 +#define BIT_MASK_SYS_EEROM_ANAPAR_SPLL_05_02 0xf +#define BIT_SYS_EEROM_ANAPAR_SPLL_05_02(x) (((x) & BIT_MASK_SYS_EEROM_ANAPAR_SPLL_05_02) << BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_05_02) + + +#define BIT_SHIFT_SYS_EEROM_XTAL_STEL_SEL 12 +#define BIT_MASK_SYS_EEROM_XTAL_STEL_SEL 0x3 +#define BIT_SYS_EEROM_XTAL_STEL_SEL(x) (((x) & BIT_MASK_SYS_EEROM_XTAL_STEL_SEL) << BIT_SHIFT_SYS_EEROM_XTAL_STEL_SEL) + + +#define BIT_SHIFT_SYS_EEROM_XTAL_FREQ_SEL 8 +#define BIT_MASK_SYS_EEROM_XTAL_FREQ_SEL 0xf +#define BIT_SYS_EEROM_XTAL_FREQ_SEL(x) (((x) & BIT_MASK_SYS_EEROM_XTAL_FREQ_SEL) << BIT_SHIFT_SYS_EEROM_XTAL_FREQ_SEL) + + +//2 REG_SYS_EFUSE_SYSCFG3 + +#define BIT_SHIFT_SYS_DBG_PINGP_EN 28 +#define BIT_MASK_SYS_DBG_PINGP_EN 0xf +#define BIT_SYS_DBG_PINGP_EN(x) (((x) & BIT_MASK_SYS_DBG_PINGP_EN) << BIT_SHIFT_SYS_DBG_PINGP_EN) + + +#define BIT_SHIFT_SYS_DBG_SEL 16 +#define BIT_MASK_SYS_DBG_SEL 0xfff +#define BIT_SYS_DBG_SEL(x) (((x) & BIT_MASK_SYS_DBG_SEL) << BIT_SHIFT_SYS_DBG_SEL) + + +#define BIT_SHIFT_SYS_DBGBY3_LOC_SEL 14 +#define BIT_MASK_SYS_DBGBY3_LOC_SEL 0x3 +#define BIT_SYS_DBGBY3_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY3_LOC_SEL) << BIT_SHIFT_SYS_DBGBY3_LOC_SEL) + + +#define BIT_SHIFT_SYS_DBGBY2_LOC_SEL 12 +#define BIT_MASK_SYS_DBGBY2_LOC_SEL 0x3 +#define BIT_SYS_DBGBY2_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY2_LOC_SEL) << BIT_SHIFT_SYS_DBGBY2_LOC_SEL) + + +#define BIT_SHIFT_SYS_DBGBY1_LOC_SEL 10 +#define BIT_MASK_SYS_DBGBY1_LOC_SEL 0x3 +#define BIT_SYS_DBGBY1_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY1_LOC_SEL) << BIT_SHIFT_SYS_DBGBY1_LOC_SEL) + + +#define BIT_SHIFT_SYS_DBGBY0_LOC_SEL 8 +#define BIT_MASK_SYS_DBGBY0_LOC_SEL 0x3 +#define BIT_SYS_DBGBY0_LOC_SEL(x) (((x) & BIT_MASK_SYS_DBGBY0_LOC_SEL) << BIT_SHIFT_SYS_DBGBY0_LOC_SEL) + +#define BIT_SYS_EEROM_ANAPAR_SPLL_49 BIT(3) + +#define BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_27_25 0 +#define BIT_MASK_SYS_EEROM_ANAPAR_SPLL_27_25 0x7 +#define BIT_SYS_EEROM_ANAPAR_SPLL_27_25(x) (((x) & BIT_MASK_SYS_EEROM_ANAPAR_SPLL_27_25) << BIT_SHIFT_SYS_EEROM_ANAPAR_SPLL_27_25) + + +//2 REG_SYS_EFUSE_SYSCFG4 + +#define BIT_SHIFT_SYS_GPIOA_E2 1 +#define BIT_MASK_SYS_GPIOA_E2 0x7 +#define BIT_SYS_GPIOA_E2(x) (((x) & BIT_MASK_SYS_GPIOA_E2) << BIT_SHIFT_SYS_GPIOA_E2) + +#define BIT_SYS_GPIOA_H3L1 BIT(0) + +//2 REG_SYS_EFUSE_SYSCFG5 + +//2 REG_NOT_VALID + +//2 REG_SYS_EFUSE_SYSCFG6 + +#define BIT_SHIFT_SYS_SPIC_INIT_BAUD_RATE_SEL 26 +#define BIT_MASK_SYS_SPIC_INIT_BAUD_RATE_SEL 0x3 +#define BIT_SYS_SPIC_INIT_BAUD_RATE_SEL(x) (((x) & BIT_MASK_SYS_SPIC_INIT_BAUD_RATE_SEL) << BIT_SHIFT_SYS_SPIC_INIT_BAUD_RATE_SEL) + + +#define BIT_SHIFT_SYS_CPU_CLK_SEL 24 +#define BIT_MASK_SYS_CPU_CLK_SEL 0x3 +#define BIT_SYS_CPU_CLK_SEL(x) (((x) & BIT_MASK_SYS_CPU_CLK_SEL) << BIT_SHIFT_SYS_CPU_CLK_SEL) + + +//2 REG_SYS_EFUSE_SYSCFG7 +#define BIT_SYS_MEM_RMV_SIGN BIT(31) +#define BIT_SYS_MEM_RMV_1PRF1 BIT(29) +#define BIT_SYS_MEM_RMV_1PRF0 BIT(28) +#define BIT_SYS_MEM_RMV_1PSR BIT(27) +#define BIT_SYS_MEM_RMV_1PHSR BIT(26) +#define BIT_SYS_MEM_RMV_ROM BIT(25) + +#define BIT_SHIFT_SYS_MEM_RME_CPU 22 +#define BIT_MASK_SYS_MEM_RME_CPU 0x7 +#define BIT_SYS_MEM_RME_CPU(x) (((x) & BIT_MASK_SYS_MEM_RME_CPU) << BIT_SHIFT_SYS_MEM_RME_CPU) + + +#define BIT_SHIFT_SYS_MEM_RME_WLAN 19 +#define BIT_MASK_SYS_MEM_RME_WLAN 0x7 +#define BIT_SYS_MEM_RME_WLAN(x) (((x) & BIT_MASK_SYS_MEM_RME_WLAN) << BIT_SHIFT_SYS_MEM_RME_WLAN) + +#define BIT_SYS_MEM_RME_USB BIT(18) +#define BIT_SYS_MEM_RME_SDIO BIT(17) + +//2 REG_SYS_REGU_CTRL0 + +#define BIT_SHIFT_SYS_REGU_LDO25M_ADJ 20 +#define BIT_MASK_SYS_REGU_LDO25M_ADJ 0xf +#define BIT_SYS_REGU_LDO25M_ADJ(x) (((x) & BIT_MASK_SYS_REGU_LDO25M_ADJ) << BIT_SHIFT_SYS_REGU_LDO25M_ADJ) + +#define BIT_SYS_REGU_ANACK_4M_EN BIT(19) +#define BIT_SYS_REGU_ANACK_4M_SEL BIT(18) +#define BIT_SYS_REGU_PC_EF_EN BIT(17) +#define BIT_SYS_REGU_LDOH12_SLP_EN BIT(16) + +#define BIT_SHIFT_SYS_REGU_LDOH12_ADJ 12 +#define BIT_MASK_SYS_REGU_LDOH12_ADJ 0xf +#define BIT_SYS_REGU_LDOH12_ADJ(x) (((x) & BIT_MASK_SYS_REGU_LDOH12_ADJ) << BIT_SHIFT_SYS_REGU_LDOH12_ADJ) + + +#define BIT_SHIFT_SYS_REGU_LDO25E_ADJ 8 +#define BIT_MASK_SYS_REGU_LDO25E_ADJ 0xf +#define BIT_SYS_REGU_LDO25E_ADJ(x) (((x) & BIT_MASK_SYS_REGU_LDO25E_ADJ) << BIT_SHIFT_SYS_REGU_LDO25E_ADJ) + +#define BIT_SYS_REGU_DSLEPM_EN BIT(7) +#define BIT_SYS_REGU_PC_33V_EN BIT(3) +#define BIT_SYS_REGU_PC_EF25_EN BIT(2) +#define BIT_SYS_REGU_LDO25M_EN BIT(1) +#define BIT_SYS_REGU_LDO25E_EN BIT(0) + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_SYS_SWR_CTRL0 + +#define BIT_SHIFT_SYS_SWR12_COMP_R2 30 +#define BIT_MASK_SYS_SWR12_COMP_R2 0x3 +#define BIT_SYS_SWR12_COMP_R2(x) (((x) & BIT_MASK_SYS_SWR12_COMP_R2) << BIT_SHIFT_SYS_SWR12_COMP_R2) + + +#define BIT_SHIFT_SYS_SWR12_COMP_R1 28 +#define BIT_MASK_SYS_SWR12_COMP_R1 0x3 +#define BIT_SYS_SWR12_COMP_R1(x) (((x) & BIT_MASK_SYS_SWR12_COMP_R1) << BIT_SHIFT_SYS_SWR12_COMP_R1) + + +#define BIT_SHIFT_SYS_SWR12_COMP_C3 26 +#define BIT_MASK_SYS_SWR12_COMP_C3 0x3 +#define BIT_SYS_SWR12_COMP_C3(x) (((x) & BIT_MASK_SYS_SWR12_COMP_C3) << BIT_SHIFT_SYS_SWR12_COMP_C3) + + +#define BIT_SHIFT_SYS_SWR12_COMP_C2 24 +#define BIT_MASK_SYS_SWR12_COMP_C2 0x3 +#define BIT_SYS_SWR12_COMP_C2(x) (((x) & BIT_MASK_SYS_SWR12_COMP_C2) << BIT_SHIFT_SYS_SWR12_COMP_C2) + + +#define BIT_SHIFT_SYS_SWR12_COMP_C1 22 +#define BIT_MASK_SYS_SWR12_COMP_C1 0x3 +#define BIT_SYS_SWR12_COMP_C1(x) (((x) & BIT_MASK_SYS_SWR12_COMP_C1) << BIT_SHIFT_SYS_SWR12_COMP_C1) + +#define BIT_SYS_SWR12_COMP_TYPE_L BIT(21) +#define BIT_SYS_SWR12_FPWM_MD BIT(20) + +#define BIT_SHIFT_SYS_SPSLDO_VOL 17 +#define BIT_MASK_SYS_SPSLDO_VOL 0x7 +#define BIT_SYS_SPSLDO_VOL(x) (((x) & BIT_MASK_SYS_SPSLDO_VOL) << BIT_SHIFT_SYS_SPSLDO_VOL) + + +#define BIT_SHIFT_SYS_SWR12_IN 14 +#define BIT_MASK_SYS_SWR12_IN 0x7 +#define BIT_SYS_SWR12_IN(x) (((x) & BIT_MASK_SYS_SWR12_IN) << BIT_SHIFT_SYS_SWR12_IN) + + +#define BIT_SHIFT_SYS_SWR12_STD 12 +#define BIT_MASK_SYS_SWR12_STD 0x3 +#define BIT_SYS_SWR12_STD(x) (((x) & BIT_MASK_SYS_SWR12_STD) << BIT_SHIFT_SYS_SWR12_STD) + + +#define BIT_SHIFT_SYS_SWR12_VOL 8 +#define BIT_MASK_SYS_SWR12_VOL 0xf +#define BIT_SYS_SWR12_VOL(x) (((x) & BIT_MASK_SYS_SWR12_VOL) << BIT_SHIFT_SYS_SWR12_VOL) + + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID +#define BIT_SYS_SWR_EN BIT(1) +#define BIT_SYS_SWR_LDO_EN BIT(0) + +//2 REG_SYS_SWR_CTRL1 +#define BIT_SYS_SW12_PFM_SEL BIT(25) +#define BIT_SYS_SW12_AUTO_ZCD_L BIT(24) +#define BIT_SYS_SW12_AUTO_MODE BIT(23) +#define BIT_SYS_SW12_LDOF_L BIT(22) +#define BIT_SYS_SW12_OCPS_L BIT(21) + +#define BIT_SHIFT_SYS_SW12_TBOX 17 +#define BIT_MASK_SYS_SW12_TBOX 0x3 +#define BIT_SYS_SW12_TBOX(x) (((x) & BIT_MASK_SYS_SW12_TBOX) << BIT_SHIFT_SYS_SW12_TBOX) + + +#define BIT_SHIFT_SYS_SW12_NONOVRLAP_DLY 15 +#define BIT_MASK_SYS_SW12_NONOVRLAP_DLY 0x3 +#define BIT_SYS_SW12_NONOVRLAP_DLY(x) (((x) & BIT_MASK_SYS_SW12_NONOVRLAP_DLY) << BIT_SHIFT_SYS_SW12_NONOVRLAP_DLY) + +#define BIT_SYS_SW12_CLAMP_DUTY BIT(14) +#define BIT_SYS_SWR12_BYPASS_SSR BIT(13) +#define BIT_SYS_SWR12_ZCDOUT_EN BIT(12) +#define BIT_SYS_SWR12_POW_ZCD BIT(11) +#define BIT_SYS_SW12_AREN BIT(10) + +#define BIT_SHIFT_SYS_SWR12_OCP_CUR 7 +#define BIT_MASK_SYS_SWR12_OCP_CUR 0x7 +#define BIT_SYS_SWR12_OCP_CUR(x) (((x) & BIT_MASK_SYS_SWR12_OCP_CUR) << BIT_SHIFT_SYS_SWR12_OCP_CUR) + +#define BIT_SYS_SWR12_OCP_EN BIT(6) + +#define BIT_SHIFT_SYS_SWR12_SAWTOOTH_CF_L 4 +#define BIT_MASK_SYS_SWR12_SAWTOOTH_CF_L 0x3 +#define BIT_SYS_SWR12_SAWTOOTH_CF_L(x) (((x) & BIT_MASK_SYS_SWR12_SAWTOOTH_CF_L) << BIT_SHIFT_SYS_SWR12_SAWTOOTH_CF_L) + + +#define BIT_SHIFT_SYS_SWR12_SAWTOOTH_CFC_L 2 +#define BIT_MASK_SYS_SWR12_SAWTOOTH_CFC_L 0x3 +#define BIT_SYS_SWR12_SAWTOOTH_CFC_L(x) (((x) & BIT_MASK_SYS_SWR12_SAWTOOTH_CFC_L) << BIT_SHIFT_SYS_SWR12_SAWTOOTH_CFC_L) + + +#define BIT_SHIFT_SYS_SWR12_COMP_R3 0 +#define BIT_MASK_SYS_SWR12_COMP_R3 0x3 +#define BIT_SYS_SWR12_COMP_R3(x) (((x) & BIT_MASK_SYS_SWR12_COMP_R3) << BIT_SHIFT_SYS_SWR12_COMP_R3) + + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_SYS_XTAL_CTRL0 +#define BIT_SYS_XTAL_XQSEL BIT(31) +#define BIT_SYS_XTAL_XQSEL_RF BIT(30) + +#define BIT_SHIFT_SYS_XTAL_SC_XO 24 +#define BIT_MASK_SYS_XTAL_SC_XO 0x3f +#define BIT_SYS_XTAL_SC_XO(x) (((x) & BIT_MASK_SYS_XTAL_SC_XO) << BIT_SHIFT_SYS_XTAL_SC_XO) + + +#define BIT_SHIFT_SYS_XTAL_SC_XI 18 +#define BIT_MASK_SYS_XTAL_SC_XI 0x3f +#define BIT_SYS_XTAL_SC_XI(x) (((x) & BIT_MASK_SYS_XTAL_SC_XI) << BIT_SHIFT_SYS_XTAL_SC_XI) + + +#define BIT_SHIFT_SYS_XTAL_GMN 13 +#define BIT_MASK_SYS_XTAL_GMN 0x1f +#define BIT_SYS_XTAL_GMN(x) (((x) & BIT_MASK_SYS_XTAL_GMN) << BIT_SHIFT_SYS_XTAL_GMN) + + +#define BIT_SHIFT_SYS_XTAL_GMP 8 +#define BIT_MASK_SYS_XTAL_GMP 0x1f +#define BIT_SYS_XTAL_GMP(x) (((x) & BIT_MASK_SYS_XTAL_GMP) << BIT_SHIFT_SYS_XTAL_GMP) + +#define BIT_SYS_XTAL_EN BIT(1) +#define BIT_SYS_XTAL_BGMB_EN BIT(0) + +//2 REG_SYS_XTAL_CTRL1 + +#define BIT_SHIFT_SYS_XTAL_COUNTER_MUX 25 +#define BIT_MASK_SYS_XTAL_COUNTER_MUX 0x3 +#define BIT_SYS_XTAL_COUNTER_MUX(x) (((x) & BIT_MASK_SYS_XTAL_COUNTER_MUX) << BIT_SHIFT_SYS_XTAL_COUNTER_MUX) + +#define BIT_SYS_XTAL_DELAY_SYSPLL BIT(24) +#define BIT_SYS_XTAL_DELAY_USB BIT(23) +#define BIT_SYS_XTAL_DELAY_WLAFE BIT(22) +#define BIT_SYS_XTAL_AGPIO_SEL BIT(21) + +#define BIT_SHIFT_SYS_XTAL_DRV_AGPIO 19 +#define BIT_MASK_SYS_XTAL_DRV_AGPIO 0x3 +#define BIT_SYS_XTAL_DRV_AGPIO(x) (((x) & BIT_MASK_SYS_XTAL_DRV_AGPIO) << BIT_SHIFT_SYS_XTAL_DRV_AGPIO) + + +#define BIT_SHIFT_SYS_XTAL_AGPIO 16 +#define BIT_MASK_SYS_XTAL_AGPIO 0x7 +#define BIT_SYS_XTAL_AGPIO(x) (((x) & BIT_MASK_SYS_XTAL_AGPIO) << BIT_SHIFT_SYS_XTAL_AGPIO) + + +#define BIT_SHIFT_SYS_XTAL_DRV_SYSPLL 14 +#define BIT_MASK_SYS_XTAL_DRV_SYSPLL 0x3 +#define BIT_SYS_XTAL_DRV_SYSPLL(x) (((x) & BIT_MASK_SYS_XTAL_DRV_SYSPLL) << BIT_SHIFT_SYS_XTAL_DRV_SYSPLL) + +#define BIT_SYS_XTAL_GATE_SYSPLL BIT(13) + +#define BIT_SHIFT_SYS_XTAL_DRV_USB 11 +#define BIT_MASK_SYS_XTAL_DRV_USB 0x3 +#define BIT_SYS_XTAL_DRV_USB(x) (((x) & BIT_MASK_SYS_XTAL_DRV_USB) << BIT_SHIFT_SYS_XTAL_DRV_USB) + +#define BIT_SYS_XTAL_GATE_USB BIT(10) + +#define BIT_SHIFT_SYS_XTAL_DRV_WLAFE 8 +#define BIT_MASK_SYS_XTAL_DRV_WLAFE 0x3 +#define BIT_SYS_XTAL_DRV_WLAFE(x) (((x) & BIT_MASK_SYS_XTAL_DRV_WLAFE) << BIT_SHIFT_SYS_XTAL_DRV_WLAFE) + +#define BIT_SYS_XTAL_GATE_WLAFE BIT(7) + +#define BIT_SHIFT_SYS_XTAL_DRV_RF2 5 +#define BIT_MASK_SYS_XTAL_DRV_RF2 0x3 +#define BIT_SYS_XTAL_DRV_RF2(x) (((x) & BIT_MASK_SYS_XTAL_DRV_RF2) << BIT_SHIFT_SYS_XTAL_DRV_RF2) + +#define BIT_SYS_XTAL_GATE_RF2 BIT(4) + +#define BIT_SHIFT_SYS_XTAL_DRV_RF1 3 +#define BIT_MASK_SYS_XTAL_DRV_RF1 0x3 +#define BIT_SYS_XTAL_DRV_RF1(x) (((x) & BIT_MASK_SYS_XTAL_DRV_RF1) << BIT_SHIFT_SYS_XTAL_DRV_RF1) + +#define BIT_SYS_XTAL_GATE_RF1 BIT(1) + +#define BIT_SHIFT_SYS_XTAL_LDO 0 +#define BIT_MASK_SYS_XTAL_LDO 0x3 +#define BIT_SYS_XTAL_LDO(x) (((x) & BIT_MASK_SYS_XTAL_LDO) << BIT_SHIFT_SYS_XTAL_LDO) + + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_SYS_SYSPLL_CTRL0 + +#define BIT_SHIFT_SYS_SYSPLL_LPF_R3 29 +#define BIT_MASK_SYS_SYSPLL_LPF_R3 0x7 +#define BIT_SYS_SYSPLL_LPF_R3(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_R3) << BIT_SHIFT_SYS_SYSPLL_LPF_R3) + + +#define BIT_SHIFT_SYS_SYSPLL_LPF_CS 27 +#define BIT_MASK_SYS_SYSPLL_LPF_CS 0x3 +#define BIT_SYS_SYSPLL_LPF_CS(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_CS) << BIT_SHIFT_SYS_SYSPLL_LPF_CS) + + +#define BIT_SHIFT_SYS_SYSPLL_LPF_CP 25 +#define BIT_MASK_SYS_SYSPLL_LPF_CP 0x3 +#define BIT_SYS_SYSPLL_LPF_CP(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_CP) << BIT_SHIFT_SYS_SYSPLL_LPF_CP) + + +#define BIT_SHIFT_SYS_SYSPLL_LPF_C3 23 +#define BIT_MASK_SYS_SYSPLL_LPF_C3 0x3 +#define BIT_SYS_SYSPLL_LPF_C3(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_C3) << BIT_SHIFT_SYS_SYSPLL_LPF_C3) + +#define BIT_SYS_SYSPLL_WDOG_ENB BIT(22) +#define BIT_SYS_SYSPLL_CKTST_EN BIT(21) + +#define BIT_SHIFT_SYS_SYSPLL_MONCK_SEL 18 +#define BIT_MASK_SYS_SYSPLL_MONCK_SEL 0x7 +#define BIT_SYS_SYSPLL_MONCK_SEL(x) (((x) & BIT_MASK_SYS_SYSPLL_MONCK_SEL) << BIT_SHIFT_SYS_SYSPLL_MONCK_SEL) + + +#define BIT_SHIFT_SYS_SYSPLL_CP_IOFFSET 13 +#define BIT_MASK_SYS_SYSPLL_CP_IOFFSET 0x1f +#define BIT_SYS_SYSPLL_CP_IOFFSET(x) (((x) & BIT_MASK_SYS_SYSPLL_CP_IOFFSET) << BIT_SHIFT_SYS_SYSPLL_CP_IOFFSET) + +#define BIT_SYS_SYSPLL_CP_IDOUBLE BIT(12) + +#define BIT_SHIFT_SYS_SYSPLL_CP_BIAS 9 +#define BIT_MASK_SYS_SYSPLL_CP_BIAS 0x7 +#define BIT_SYS_SYSPLL_CP_BIAS(x) (((x) & BIT_MASK_SYS_SYSPLL_CP_BIAS) << BIT_SHIFT_SYS_SYSPLL_CP_BIAS) + +#define BIT_SYS_SYSPLL_FREF_EDGE BIT(8) +#define BIT_SYS_SYSPLL_EN BIT(1) +#define BIT_SYS_SYSPLL_LVPC_EN BIT(0) + +//2 REG_SYS_SYSPLL_CTRL1 +#define BIT_SYS_SYSPLL_CK500K_SEL BIT(15) +#define BIT_SYS_SYSPLL_CK200M_EN BIT(14) +#define BIT_SYS_SYSPLL_CKSDR_EN BIT(13) + +#define BIT_SHIFT_SYS_SYSPLL_CKSDR_DIV 11 +#define BIT_MASK_SYS_SYSPLL_CKSDR_DIV 0x3 +#define BIT_SYS_SYSPLL_CKSDR_DIV(x) (((x) & BIT_MASK_SYS_SYSPLL_CKSDR_DIV) << BIT_SHIFT_SYS_SYSPLL_CKSDR_DIV) + +#define BIT_SYS_SYSPLL_CK24P576_EN BIT(9) +#define BIT_SYS_SYSPLL_CK22P5792_EN BIT(8) +#define BIT_SYS_SYSPLL_CK_PS_EN BIT(6) + +#define BIT_SHIFT_SYS_SYSPLL_CK_PS_SEL 3 +#define BIT_MASK_SYS_SYSPLL_CK_PS_SEL 0x7 +#define BIT_SYS_SYSPLL_CK_PS_SEL(x) (((x) & BIT_MASK_SYS_SYSPLL_CK_PS_SEL) << BIT_SHIFT_SYS_SYSPLL_CK_PS_SEL) + + +#define BIT_SHIFT_SYS_SYSPLL_LPF_RS 0 +#define BIT_MASK_SYS_SYSPLL_LPF_RS 0x7 +#define BIT_SYS_SYSPLL_LPF_RS(x) (((x) & BIT_MASK_SYS_SYSPLL_LPF_RS) << BIT_SHIFT_SYS_SYSPLL_LPF_RS) + + +//2 REG_SYS_SYSPLL_CTRL2 + +#define BIT_SHIFT_XTAL_DRV_RF_LATCH 0 +#define BIT_MASK_XTAL_DRV_RF_LATCH 0xffffffffL +#define BIT_XTAL_DRV_RF_LATCH(x) (((x) & BIT_MASK_XTAL_DRV_RF_LATCH) << BIT_SHIFT_XTAL_DRV_RF_LATCH) + + +//2 REG_RSVD + +//2 REG_RSVD + +#define BIT_SHIFT_PESOC_CPU_OCP_CK_SEL 0 +#define BIT_MASK_PESOC_CPU_OCP_CK_SEL 0x7 +#define BIT_PESOC_CPU_OCP_CK_SEL(x) (((x) & BIT_MASK_PESOC_CPU_OCP_CK_SEL) << BIT_SHIFT_PESOC_CPU_OCP_CK_SEL) + + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_ + +//2 REG_SYS_ANA_TIM_CTRL + +#define BIT_SHIFT_SYS_ANACK_TU_TIME 16 +#define BIT_MASK_SYS_ANACK_TU_TIME 0x3f +#define BIT_SYS_ANACK_TU_TIME(x) (((x) & BIT_MASK_SYS_ANACK_TU_TIME) << BIT_SHIFT_SYS_ANACK_TU_TIME) + +#define BIT_SYS_DSBYCNT_EN BIT(15) + +#define BIT_SHIFT_SYS_DSTDY_TIM_SCAL 8 +#define BIT_MASK_SYS_DSTDY_TIM_SCAL 0xf +#define BIT_SYS_DSTDY_TIM_SCAL(x) (((x) & BIT_MASK_SYS_DSTDY_TIM_SCAL) << BIT_SHIFT_SYS_DSTDY_TIM_SCAL) + + +#define BIT_SHIFT_SYS_DSTBY_TIM_PERIOD 0 +#define BIT_MASK_SYS_DSTBY_TIM_PERIOD 0xff +#define BIT_SYS_DSTBY_TIM_PERIOD(x) (((x) & BIT_MASK_SYS_DSTBY_TIM_PERIOD) << BIT_SHIFT_SYS_DSTBY_TIM_PERIOD) + + +//2 REG_SYS_DSLP_TIM_CTRL + +#define BIT_SHIFT_SYS_REGU_ASIF_EN 24 +#define BIT_MASK_SYS_REGU_ASIF_EN 0xff +#define BIT_SYS_REGU_ASIF_EN(x) (((x) & BIT_MASK_SYS_REGU_ASIF_EN) << BIT_SHIFT_SYS_REGU_ASIF_EN) + + +#define BIT_SHIFT_SYS_REGU_ASIF_THP_DA 20 +#define BIT_MASK_SYS_REGU_ASIF_THP_DA 0x3 +#define BIT_SYS_REGU_ASIF_THP_DA(x) (((x) & BIT_MASK_SYS_REGU_ASIF_THP_DA) << BIT_SHIFT_SYS_REGU_ASIF_THP_DA) + + +#define BIT_SHIFT_SYS_REGU_ASIF_TPD_CK 18 +#define BIT_MASK_SYS_REGU_ASIF_TPD_CK 0x3 +#define BIT_SYS_REGU_ASIF_TPD_CK(x) (((x) & BIT_MASK_SYS_REGU_ASIF_TPD_CK) << BIT_SHIFT_SYS_REGU_ASIF_TPD_CK) + + +#define BIT_SHIFT_SYS_REGU_ASIF_TSP_DA 16 +#define BIT_MASK_SYS_REGU_ASIF_TSP_DA 0x3 +#define BIT_SYS_REGU_ASIF_TSP_DA(x) (((x) & BIT_MASK_SYS_REGU_ASIF_TSP_DA) << BIT_SHIFT_SYS_REGU_ASIF_TSP_DA) + +#define BIT_SYS_REGU_ASIF_POLL BIT(15) +#define BIT_SYS_REGU_ASIF_MODE BIT(14) +#define BIT_SYS_REGU_ASIF_WE BIT(12) + +#define BIT_SHIFT_SYS_REGU_ASIF_AD 8 +#define BIT_MASK_SYS_REGU_ASIF_AD 0xf +#define BIT_SYS_REGU_ASIF_AD(x) (((x) & BIT_MASK_SYS_REGU_ASIF_AD) << BIT_SHIFT_SYS_REGU_ASIF_AD) + + +#define BIT_SHIFT_SYS_REGU_ASIF_WD 0 +#define BIT_MASK_SYS_REGU_ASIF_WD 0xff +#define BIT_SYS_REGU_ASIF_WD(x) (((x) & BIT_MASK_SYS_REGU_ASIF_WD) << BIT_SHIFT_SYS_REGU_ASIF_WD) + + +//2 REG_SYS_DSLP_TIM_CAL_CTRL +#define BIT_SYS_DSLP_TIM_EN BIT(24) + +#define BIT_SHIFT_SYS_DSLP_TIM_PERIOD 0 +#define BIT_MASK_SYS_DSLP_TIM_PERIOD 0x7fffff +#define BIT_SYS_DSLP_TIM_PERIOD(x) (((x) & BIT_MASK_SYS_DSLP_TIM_PERIOD) << BIT_SHIFT_SYS_DSLP_TIM_PERIOD) + + +//2 REG_RSVD + +//2 REG_SYS_DEBUG_CTRL +#define BIT_SYS_DBG_PIN_EN BIT(0) + +//2 REG_SYS_PINMUX_CTRL +#define BIT_EEPROM_PIN_EN BIT(4) +#define BIT_SIC_PIN_EN BIT(0) + +//2 REG_SYS_GPIO_DSTBY_WAKE_CTRL0 +#define BIT_SYS_GPIOE3_WEVENT_STS BIT(27) +#define BIT_SYS_GPIOD5_WEVENT_STS BIT(26) +#define BIT_SYS_GPIOC7_WEVENT_STS BIT(25) +#define BIT_SYS_GPIOA5_WEVENT_STS BIT(24) +#define BIT_SYS_GPIO_GPE3_PULL_CTRL_EN BIT(19) +#define BIT_SYS_GPIO_GPD5_PULL_CTRL_EN BIT(18) +#define BIT_SYS_GPIO_GPC7_PULL_CTRL_EN BIT(17) +#define BIT_SYS_GPIO_GPA5_PULL_CTRL_EN BIT(16) +#define BIT_SYS_GPIOE3_WINT_MODE BIT(11) +#define BIT_SYS_GPIOD5_WINT_MODE BIT(10) +#define BIT_SYS_GPIOC7_WINT_MODE BIT(9) +#define BIT_SYS_GPIOA5_WINT_MODE BIT(8) +#define BIT_SYS_GPIOE3_PIN_EN BIT(3) +#define BIT_SYS_GPIOD5_PIN_EN BIT(2) +#define BIT_SYS_GPIOC7_PIN_EN BIT(1) +#define BIT_SYS_GPIOA5_PIN_EN BIT(0) + +//2 REG_SYS_GPIO_DSTBY_WAKE_CTRL1 +#define BIT_SYS_GPIOE3_SHTDN_N BIT(19) +#define BIT_SYS_GPIOD5_SHTDN_N BIT(18) +#define BIT_SYS_GPIOC7_SHTDN_N BIT(17) +#define BIT_SYS_GPIOA5_SHTDN_N BIT(16) + +#define BIT_SHIFT_SYS_WINT_DEBOUNCE_TIM_SCAL 8 +#define BIT_MASK_SYS_WINT_DEBOUNCE_TIM_SCAL 0x3 +#define BIT_SYS_WINT_DEBOUNCE_TIM_SCAL(x) (((x) & BIT_MASK_SYS_WINT_DEBOUNCE_TIM_SCAL) << BIT_SHIFT_SYS_WINT_DEBOUNCE_TIM_SCAL) + +#define BIT_SYS_GPIOE3_WINT_DEBOUNCE_EN BIT(3) +#define BIT_SYS_GPIOD5_WINT_DEBOUNCE_EN BIT(2) +#define BIT_SYS_GPIOC7_WINT_DEBOUNCE_EN BIT(1) +#define BIT_SYS_GPIOA5_WINT_DEBOUNCE_EN BIT(0) + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_SYS_DEBUG_REG + +#define BIT_SHIFT_SYS_DBG_VALUE 0 +#define BIT_MASK_SYS_DBG_VALUE 0xffffffffL +#define BIT_SYS_DBG_VALUE(x) (((x) & BIT_MASK_SYS_DBG_VALUE) << BIT_SHIFT_SYS_DBG_VALUE) + + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_SYS_EEPROM_CTRL0 + +#define BIT_SHIFT_EFUSE_UNLOCK 24 +#define BIT_MASK_EFUSE_UNLOCK 0xff +#define BIT_EFUSE_UNLOCK(x) (((x) & BIT_MASK_EFUSE_UNLOCK) << BIT_SHIFT_EFUSE_UNLOCK) + + +//2 REG_NOT_VALID +#define BIT_SYS_EFUSE_LDALL BIT(16) + +#define BIT_SHIFT_SYS_EEPROM_VPDIDX 8 +#define BIT_MASK_SYS_EEPROM_VPDIDX 0xff +#define BIT_SYS_EEPROM_VPDIDX(x) (((x) & BIT_MASK_SYS_EEPROM_VPDIDX) << BIT_SHIFT_SYS_EEPROM_VPDIDX) + + +#define BIT_SHIFT_SYS_EEPROM_MD 6 +#define BIT_MASK_SYS_EEPROM_MD 0x3 +#define BIT_SYS_EEPROM_MD(x) (((x) & BIT_MASK_SYS_EEPROM_MD) << BIT_SHIFT_SYS_EEPROM_MD) + +#define BIT_SYS_AUTOLOAD_SUS BIT(5) +#define BIT_SYS_EEPROM_SEL BIT(4) +#define BIT_SYS_EEPROM_EECS BIT(3) +#define BIT_SYS_EEPROM_EESK BIT(2) +#define BIT_SYS_EEPROM_EEDI BIT(1) +#define BIT_SYS_EEPROM_EEDO BIT(0) + +//2 REG_SYS_EEPROM_CTRL1 + +#define BIT_SHIFT_SYS_EEPROM_VPD 0 +#define BIT_MASK_SYS_EEPROM_VPD 0xffffffffL +#define BIT_SYS_EEPROM_VPD(x) (((x) & BIT_MASK_SYS_EEPROM_VPD) << BIT_SHIFT_SYS_EEPROM_VPD) + + +//2 REG_SYS_EFUSE_CTRL +#define BIT_SYS_EF_RWFLAG BIT(31) + +#define BIT_SHIFT_SYS_EF_PGPD 28 +#define BIT_MASK_SYS_EF_PGPD 0x7 +#define BIT_SYS_EF_PGPD(x) (((x) & BIT_MASK_SYS_EF_PGPD) << BIT_SHIFT_SYS_EF_PGPD) + + +#define BIT_SHIFT_SYS_EF_RDT 24 +#define BIT_MASK_SYS_EF_RDT 0xf +#define BIT_SYS_EF_RDT(x) (((x) & BIT_MASK_SYS_EF_RDT) << BIT_SHIFT_SYS_EF_RDT) + + +#define BIT_SHIFT_SYS_EF_PGTS 20 +#define BIT_MASK_SYS_EF_PGTS 0xf +#define BIT_SYS_EF_PGTS(x) (((x) & BIT_MASK_SYS_EF_PGTS) << BIT_SHIFT_SYS_EF_PGTS) + +#define BIT_SYS_EF_PDWN BIT(19) +#define BIT_SYS_EF_ALDEN BIT(18) + +#define BIT_SHIFT_SYS_EF_ADDR 8 +#define BIT_MASK_SYS_EF_ADDR 0x3ff +#define BIT_SYS_EF_ADDR(x) (((x) & BIT_MASK_SYS_EF_ADDR) << BIT_SHIFT_SYS_EF_ADDR) + + +#define BIT_SHIFT_SYS_EF_DATA 0 +#define BIT_MASK_SYS_EF_DATA 0xff +#define BIT_SYS_EF_DATA(x) (((x) & BIT_MASK_SYS_EF_DATA) << BIT_SHIFT_SYS_EF_DATA) + + +//2 REG_SYS_EFUSE_TEST +#define BIT_SYS_EF_CRES_SEL BIT(26) + +#define BIT_SHIFT_SYS_EF_SCAN_START 16 +#define BIT_MASK_SYS_EF_SCAN_START 0x1ff +#define BIT_SYS_EF_SCAN_START(x) (((x) & BIT_MASK_SYS_EF_SCAN_START) << BIT_SHIFT_SYS_EF_SCAN_START) + + +#define BIT_SHIFT_SYS_EF_SCAN_END 12 +#define BIT_MASK_SYS_EF_SCAN_END 0xf +#define BIT_SYS_EF_SCAN_END(x) (((x) & BIT_MASK_SYS_EF_SCAN_END) << BIT_SHIFT_SYS_EF_SCAN_END) + +#define BIT_SYS_EF_FORCE_PGMEN BIT(11) + +#define BIT_SHIFT_SYS_EF_CELL_SEL 8 +#define BIT_MASK_SYS_EF_CELL_SEL 0x3 +#define BIT_SYS_EF_CELL_SEL(x) (((x) & BIT_MASK_SYS_EF_CELL_SEL) << BIT_SHIFT_SYS_EF_CELL_SEL) + +#define BIT_SYS_EF_TRPT BIT(7) + +#define BIT_SHIFT_SYS_EF_SCAN_TTHD 0 +#define BIT_MASK_SYS_EF_SCAN_TTHD 0x7f +#define BIT_SYS_EF_SCAN_TTHD(x) (((x) & BIT_MASK_SYS_EF_SCAN_TTHD) << BIT_SHIFT_SYS_EF_SCAN_TTHD) + + +//2 REG_SYS_DSTBY_INFO0 + +//2 REG_NOT_VALID + +//2 REG_SYS_DSTBY_INFO1 + +//2 REG_SYS_DSTBY_INFO2 + +//2 REG_NOT_VALID + +//2 REG_SYS_DSTBY_INFO3 + +//2 REG_SYS_SLP_WAKE_EVENT_MSK0 +#define BIT_SYSON_WEVT_GPIO_DSTBY_MSK BIT(29) +#define BIT_SYSON_WEVT_A33_MSK BIT(28) +#define BIT_SYSON_WEVT_ADC_MSK BIT(26) +#define BIT_SYSON_WEVT_I2C_MSK BIT(24) +#define BIT_SYSON_WEVT_SPI_MSK BIT(22) +#define BIT_SYSON_WEVT_UART_MSK BIT(20) +#define BIT_SYSON_WEVT_USB_MSK BIT(16) +#define BIT_SYSON_WEVT_SDIO_MSK BIT(14) +#define BIT_SYSON_WEVT_NFC_MSK BIT(9) +#define BIT_SYSON_WEVT_WLAN_MSK BIT(8) +#define BIT_SYSON_WEVT_GPIO_MSK BIT(4) +#define BIT_SYSON_WEVT_CHIP_EN_MSK BIT(3) +#define BIT_SYSON_WEVT_OVER_CURRENT_MSK BIT(2) +#define BIT_SYSON_WEVT_GTIM_MSK BIT(1) +#define BIT_SYSON_WEVT_SYSTIM_MSK BIT(0) + +//2 REG_SYS_SLP_WAKE_EVENT_MSK1 + +//2 REG_SYS_SLP_WAKE_EVENT_STATUS0 +#define BIT_SYSON_WEVT_GPIO_DSTBY_STS BIT(29) +#define BIT_SYSON_WEVT_A33_STS BIT(28) +#define BIT_SYSON_WEVT_ADC_STS BIT(26) +#define BIT_SYSON_WEVT_I2C_STS BIT(24) +#define BIT_SYSON_WEVT_SPI_STS BIT(22) +#define BIT_SYSON_WEVT_UART_STS BIT(20) +#define BIT_SYSON_WEVT_USB_STS BIT(16) +#define BIT_SYSON_WEVT_SDIO_STS BIT(14) +#define BIT_SYSON_WEVT_NFC_STS BIT(9) +#define BIT_SYSON_WEVT_WLAN_STS BIT(8) +#define BIT_SYSON_WEVT_GPIO_STS BIT(4) +#define BIT_SYSON_WEVT_CHIP_EN_STS BIT(3) +#define BIT_SYSON_WEVT_OVER_CURRENT_STS BIT(2) +#define BIT_SYSON_WEVT_GTIM_STS BIT(1) +#define BIT_SYSON_WEVT_SYSTIM_STS BIT(0) + +//2 REG_SYS_SLP_WAKE_EVENT_STATUS1 + +//2 REG_SYS_SNF_WAKE_EVENT_MSK0 + +#define BIT_SHIFT_SYS_WKPERI_IMR0 1 +#define BIT_MASK_SYS_WKPERI_IMR0 0x7fffffffL +#define BIT_SYS_WKPERI_IMR0(x) (((x) & BIT_MASK_SYS_WKPERI_IMR0) << BIT_SHIFT_SYS_WKPERI_IMR0) + +#define BIT_SYSON_SNFEVT_ADC_MSK BIT(0) + +//2 REG_SYS_SNF_WAKE_EVENT_STATUS + +#define BIT_SHIFT_SYS_WKPERI_ISR0 1 +#define BIT_MASK_SYS_WKPERI_ISR0 0x7fffffffL +#define BIT_SYS_WKPERI_ISR0(x) (((x) & BIT_MASK_SYS_WKPERI_ISR0) << BIT_SHIFT_SYS_WKPERI_ISR0) + +#define BIT_SYSON_SNFEVT_ADC_STS BIT(0) + +//2 REG_SYS_PWRMGT_CTRL +#define BIT_SYSON_REGU_DSLP BIT(7) + +//2 REG_NOT_VALID +#define BIT_SYSON_PM_CMD_SLP BIT(2) +#define BIT_SYSON_PM_CMD_DSTBY BIT(1) +#define BIT_SYSON_PM_CMD_DSLP BIT(0) + +//2 REG_RSVD + +//2 REG_SYS_PWRMGT_OPTION +#define BIT_SYSON_PMOPT_NORM_SYSCLK_SEL BIT(30) +#define BIT_SYSON_PMOPT_NORM_SYSPLL_EN BIT(29) +#define BIT_SYSON_PMOPT_NORM_XTAL_EN BIT(28) +#define BIT_SYSON_PMOPT_NORM_EN_SOC BIT(27) +#define BIT_SYSON_PMOPT_NORM_EN_PWM BIT(26) +#define BIT_SYSON_PMOPT_NORM_EN_SWR BIT(25) +#define BIT_SYSON_PMOPT_NORM_LPLDO_SEL BIT(24) +#define BIT_SYSON_PMOPT_SNZ_SYSCLK_SEL BIT(22) +#define BIT_SYSON_PMOPT_SNZ_SYSPLL_EN BIT(21) +#define BIT_SYSON_PMOPT_SNZ_XTAL_EN BIT(20) +#define BIT_SYSON_PMOPT_SNZ_EN_SOC BIT(19) +#define BIT_SYSON_PMOPT_SNZ_EN_PWM BIT(18) +#define BIT_SYSON_PMOPT_SNZ_EN_SWR BIT(17) +#define BIT_SYSON_PMOPT_SNZ_LPLDO_SEL BIT(16) +#define BIT_SYSON_PMOPT_SLP_SYSCLK_SEL BIT(14) +#define BIT_SYSON_PMOPT_SLP_SYSPLL_EN BIT(13) +#define BIT_SYSON_PMOPT_SLP_XTAL_EN BIT(12) +#define BIT_SYSON_PMOPT_SLP_EN_SOC BIT(11) +#define BIT_SYSON_PMOPT_SLP_EN_PWM BIT(10) +#define BIT_SYSON_PMOPT_SLP_EN_SWR BIT(9) +#define BIT_SYSON_PMOPT_SLP_LPLDO_SEL BIT(8) +#define BIT_SYSON_PMOPT_DSTBY_SYSCLK_SEL BIT(6) +#define BIT_SYSON_PMOPT_DSTBY_SYSPLL_EN BIT(5) +#define BIT_SYSON_PMOPT_DSTBY_XTAL_EN BIT(4) +#define BIT_SYSON_PMOPT_DSTBY_EN_SOC BIT(3) +#define BIT_SYSON_PMOPT_DSTBY_EN_PWM BIT(2) +#define BIT_SYSON_PMOPT_DSTBY_EN_SWR BIT(1) +#define BIT_SYSON_PMOPT_DSTBY_LPLDO_SEL BIT(0) + +//2 REG_SYS_PWRMGT_OPTION_EXT +#define BIT_SYSON_PMOPT_SLP_ANACK_SEL BIT(2) +#define BIT_SYSON_PMOPT_SLP_ANACK_EN BIT(1) +#define BIT_SYSON_PMOPT_SLP_SWR_ADJ BIT(0) + +//2 REG_SYS_DSLP_WEVENT +#define BIT_SYSON_DSLP_GPIO BIT(2) +#define BIT_SYSON_DSLP_NFC BIT(1) +#define BIT_SYSON_DSLP_WTIMER33 BIT(0) + +//2 REG_SYS_PERI_MONITOR +#define BIT_SYSON_ISO33_NFC BIT(0) + +//2 REG_SYS_SYSTEM_CFG0 +#define BIT_SYSCFG_BD_PKG_SEL BIT(31) + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +#define BIT_SHIFT_VENDOR_ID 8 +#define BIT_MASK_VENDOR_ID 0xf +#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) + + +#define BIT_SHIFT_CHIP_VER 4 +#define BIT_MASK_CHIP_VER 0xf +#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) + + +#define BIT_SHIFT_RF_RL_ID 0 +#define BIT_MASK_RF_RL_ID 0xf +#define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID) + + +//2 REG_SYS_SYSTEM_CFG1 + +#define BIT_SHIFT_SYSCFG_TRP_ICFG 28 +#define BIT_MASK_SYSCFG_TRP_ICFG 0xf +#define BIT_SYSCFG_TRP_ICFG(x) (((x) & BIT_MASK_SYSCFG_TRP_ICFG) << BIT_SHIFT_SYSCFG_TRP_ICFG) + +#define BIT_SYSCFG_TRP_BOOT_SEL_ BIT(27) +#define BIT_SysCFG_TRP_SPSLDO_SEL BIT(26) +#define BIT_V15_VLD BIT(16) +#define BIT_SYS_SYSPLL_CLK_RDY BIT(9) +#define BIT_SYS_XCLK_VLD BIT(8) +#define BIT_SYSCFG_ALDN_STS BIT(0) + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + +//2 REG_RSVD + +//2 REG_NOT_VALID + +//2 REG_NOT_VALID + + +//================= Register Address Definition =====================// +#define REG_SYS_PWR_CTRL 0x0000 +#define REG_SYS_ISO_CTRL 0x0002 +#define REG_SYS_FUNC_EN 0x0008 +#define REG_SYS_CLK_CTRL0 0x0010 +#define REG_SYS_CLK_CTRL1 0x0014 +#define REG_SYS_EFUSE_SYSCFG0 0x0020 +#define REG_SYS_EFUSE_SYSCFG1 0x0024 +#define REG_SYS_EFUSE_SYSCFG2 0x0028 +#define REG_SYS_EFUSE_SYSCFG3 0x002C +#define REG_SYS_EFUSE_SYSCFG4 0x0030 +#define REG_SYS_EFUSE_SYSCFG5 0x0034 +#define REG_SYS_EFUSE_SYSCFG6 0x0038 +#define REG_SYS_EFUSE_SYSCFG7 0x003C +#define REG_SYS_REGU_CTRL0 0x0040 +#define REG_SYS_SWR_CTRL0 0x0048 +#define REG_SYS_SWR_CTRL1 0x004C +#define REG_SYS_XTAL_CTRL0 0x0060 +#define REG_SYS_XTAL_CTRL1 0x0064 +#define REG_SYS_SYSPLL_CTRL0 0x0070 +#define REG_SYS_SYSPLL_CTRL1 0x0074 +#define REG_SYS_SYSPLL_CTRL2 0x0078 +#define REG_SYS_ANA_TIM_CTRL 0x0090 +#define REG_SYS_DSLP_TIM_CTRL 0x0094 +#define REG_SYS_DSLP_TIM_CAL_CTRL 0x0098 +#define REG_SYS_DEBUG_CTRL 0x00A0 +#define REG_SYS_PINMUX_CTRL 0x00A4 +#define REG_SYS_GPIO_DSTBY_WAKE_CTRL0 0x00A8 +#define REG_SYS_GPIO_DSTBY_WAKE_CTRL1 0x00AC +#define REG_SYS_DEBUG_REG 0x00BC +#define REG_SYS_EEPROM_CTRL0 0x00E0 +#define REG_SYS_EEPROM_CTRL1 0x00E4 +#define REG_SYS_EFUSE_CTRL 0x00E8 +#define REG_SYS_EFUSE_TEST 0x00EC +#define REG_SYS_DSTBY_INFO0 0x00F0 +#define REG_SYS_DSTBY_INFO1 0x00F4 +#define REG_SYS_DSTBY_INFO2 0x00F8 +#define REG_SYS_DSTBY_INFO3 0x00FC +#define REG_SYS_SLP_WAKE_EVENT_MSK0 0x0100 +#define REG_SYS_SLP_WAKE_EVENT_MSK1 0x0104 +#define REG_SYS_SLP_WAKE_EVENT_STATUS0 0x0108 +#define REG_SYS_SLP_WAKE_EVENT_STATUS1 0x010C +#define REG_SYS_SNF_WAKE_EVENT_MSK0 0x0110 +#define REG_SYS_SNF_WAKE_EVENT_STATUS 0x0114 +#define REG_SYS_PWRMGT_CTRL 0x0118 +#define REG_SYS_PWRMGT_OPTION 0x0120 +#define REG_SYS_PWRMGT_OPTION_EXT 0x0124 +#define REG_SYS_DSLP_WEVENT 0x0130 +#define REG_SYS_PERI_MONITOR 0x0134 +#define REG_SYS_SYSTEM_CFG0 0x01F0 +#define REG_SYS_SYSTEM_CFG1 0x01F4 +#define REG_SYS_SYSTEM_CFG2 0x01F8 + +#endif diff --git a/lib/fwlib/rtl8195a/rtl8195a_timer.h b/lib/fwlib/rtl8195a/rtl8195a_timer.h new file mode 100644 index 0000000..da4a540 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_timer.h @@ -0,0 +1,222 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _RTL8195A_TIMER_H_ +#define _RTL8195A_TIMER_H_ + + +#define TIMER_TICK_US 31 + +#define TIMER_LOAD_COUNT_OFF 0x00 +#define TIMER_CURRENT_VAL_OFF 0x04 +#define TIMER_CTL_REG_OFF 0x08 +#define TIMER_EOI_OFF 0x0c +#define TIMER_INT_STATUS_OFF 0x10 +#define TIMER_INTERVAL 0x14 +#define TIMERS_INT_STATUS_OFF 0xa0 +#define TIMERS_EOI_OFF 0xa4 +#define TIMERS_RAW_INT_STATUS_OFF 0xa8 +#define TIMERS_COMP_VER_OFF 0xac + +#define MAX_TIMER_VECTOR_TABLE_NUM 6 + +#define HAL_TIMER_READ32(addr) (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr) +#define HAL_TIMER_WRITE32(addr, value) ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value) +#define HAL_TIMER_READ16(addr) (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr) +#define HAL_TIMER_WRITE16(addr, value) ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value) +#define HAL_TIMER_READ8(addr) (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr) +#define HAL_TIMER_WRITE8(addr, value) ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value) + +_LONG_CALL_ u32 +HalGetTimerIdRtl8195a( + IN u32 *TimerID +); + +_LONG_CALL_ BOOL +HalTimerInitRtl8195a( + IN VOID *Data +); + +_LONG_CALL_ u32 +HalTimerReadCountRtl8195a( + IN u32 TimerId +); + +_LONG_CALL_ VOID +HalTimerIrqClearRtl8195a( + IN u32 TimerId +); + +_LONG_CALL_ VOID +HalTimerDisRtl8195a( + IN u32 TimerId +); + +_LONG_CALL_ VOID +HalTimerEnRtl8195a( + IN u32 TimerId +); + +_LONG_CALL_ VOID +HalTimerDumpRegRtl8195a( + IN u32 TimerId +); + +// ROM Code patch +HAL_Status +HalTimerInitRtl8195a_Patch( + IN VOID *Data +); + +u32 +HalTimerReadCountRtl8195a_Patch( + IN u32 TimerId +); + +VOID +HalTimerReLoadRtl8195a_Patch( + IN u32 TimerId, + IN u32 LoadUs +); + +u32 +HalTimerReadCountRtl8195a_Patch( + IN u32 TimerId +); + +VOID +HalTimerIrqEnRtl8195a( + IN u32 TimerId +); + +VOID +HalTimerIrqDisRtl8195a( + IN u32 TimerId +); + +VOID +HalTimerEnRtl8195a_Patch( + IN u32 TimerId +); + +VOID +HalTimerDisRtl8195a_Patch( + IN u32 TimerId +); + +VOID +HalTimerDeInitRtl8195a_Patch( + IN VOID *Data +); + +#ifdef CONFIG_CHIP_C_CUT + +__weak _LONG_CALL_ +VOID +HalTimerIrq2To7HandleV02( + IN VOID *Data +); + +__weak _LONG_CALL_ +HAL_Status +HalTimerIrqRegisterRtl8195aV02( + IN VOID *Data +); + +__weak _LONG_CALL_ +HAL_Status +HalTimerInitRtl8195aV02( + IN VOID *Data +); + +__weak _LONG_CALL_ +u32 +HalTimerReadCountRtl8195aV02( + IN u32 TimerId +); + +__weak _LONG_CALL_ +VOID +HalTimerReLoadRtl8195aV02( + IN u32 TimerId, + IN u32 LoadUs +); + +__weak _LONG_CALL_ +HAL_Status +HalTimerIrqUnRegisterRtl8195aV02( + IN VOID *Data +); + +__weak _LONG_CALL_ +VOID +HalTimerDeInitRtl8195aV02( + IN VOID *Data +); + +#endif // end of "#ifdef CONFIG_CHIP_C_CUT" + +// HAL functions wrapper +static __inline HAL_Status +HalTimerInit( + IN VOID *Data +) +{ + return (HalTimerInitRtl8195a_Patch(Data)); +} + +static __inline VOID +HalTimerEnable( + IN u32 TimerId +) +{ + HalTimerIrqEnRtl8195a(TimerId); + HalTimerEnRtl8195a_Patch(TimerId); +} + +static __inline VOID +HalTimerDisable( + IN u32 TimerId +) +{ + HalTimerDisRtl8195a_Patch(TimerId); +} + +static __inline VOID +HalTimerReLoad( + IN u32 TimerId, + IN u32 LoadUs +) +{ + HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs); +} + +#ifndef CONFIG_CHIP_C_CUT + +static __inline VOID +HalTimerDeInit( + IN VOID *Data +) +{ + HalTimerDeInitRtl8195a_Patch(Data); +} + +#else + +static __inline VOID +HalTimerDeInit( + IN VOID *Data +) +{ + HalTimerDeInitRtl8195aV02(Data); +} + +#endif // end of "#ifndef CONFIG_CHIP_C_CUT" + +#endif //_RTL8195A_TIMER_H_ diff --git a/lib/fwlib/rtl8195a/rtl8195a_uart.h b/lib/fwlib/rtl8195a/rtl8195a_uart.h new file mode 100644 index 0000000..c13191c --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_uart.h @@ -0,0 +1,532 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#ifndef _RTL8195A_UART_H_ +#define _RTL8195A_UART_H_ + +#define MAX_UART_INDEX 2 + +#define RUART_DLL_OFF 0x00 +#define RUART_DLM_OFF 0x04 //RW, DLAB = 1 +#define RUART_INTERRUPT_EN_REG_OFF 0x04 +#define RUART_IER_ERBI 0x01 //BIT0, Enable Received Data Available Interrupt (rx trigger) +#define RUART_IER_ETBEI (1<<1) //BIT1, Enable Transmitter FIFO Empty Interrupt (tx fifo empty) +#define RUART_IER_ELSI (1<<2) //BIT2, Enable Receiver Line Status Interrupt (receiver line status) +#define RUART_IER_EDSSI (1<<3) //BIT3, Enable Modem Status Interrupt (modem status transition) + +#define RUART_INT_ID_REG_OFF 0x08 //[R] +#define RUART_IIR_INT_PEND 0x01 +#define RUART_IIR_INT_ID (0x07<<1) //011(3), 010(2), 110(6), 001(1), 000(0) +#define RUART_FIFO_CTL_REG_OFF 0x08 //[W] +#define RUART_FIFO_CTL_REG_CLEAR_RXFIFO (1<<1) //BIT1, 0x02, Write 1 clear +#define RUART_FIFO_CTL_REG_CLEAR_TXFIFO (1<<2) //BIT2, 0x04, Write 1 clear +#define RUART_FIFO_CTL_REG_DMA_ENABLE 0x08 //BIT3 + +#define FIFO_CTL_DEFAULT_WITH_FIFO_DMA 0xC9 +#define FIFO_CTL_DEFAULT_WITH_FIFO 0xC1 + +#define RUART_MODEM_CTL_REG_OFF 0x10 +#define RUART_MCR_RTS BIT1 +#define RUART_MCL_AUTOFLOW_ENABLE (1<<5) //BIT5, 0x20 + +#define RUART_LINE_CTL_REG_OFF 0x0C +#define RUART_LINE_CTL_REG_DLAB_ENABLE (1<<7) //BIT7, 0x80 + +#define RUART_LINE_STATUS_REG_OFF 0x14 +#define RUART_LINE_STATUS_REG_DR 0x01 //BIT0, Data Ready indicator +#define RUART_LINE_STATUS_ERR_OVERRUN (1<<1) //BIT1, Over Run +#define RUART_LINE_STATUS_ERR_PARITY (1<<2) //BIT2, Parity error +#define RUART_LINE_STATUS_ERR_FRAMING (1<<3) //BIT3, Framing error +#define RUART_LINE_STATUS_ERR_BREAK (1<<4) //BIT4, Break interrupt error +#define RUART_LINE_STATUS_REG_THRE (1<<5) //BIT5, 0x20, Transmit Holding Register Empty Interrupt enable +#define RUART_LINE_STATUS_REG_TEMT (1<<6) //BIT6, 0x40, Transmitter Empty indicator(bit) +#define RUART_LINE_STATUS_ERR_RXFIFO (1<<7) //BIT7, RX FIFO error +#define RUART_LINE_STATUS_ERR (RUART_LINE_STATUS_ERR_OVERRUN|RUART_LINE_STATUS_ERR_PARITY| \ + RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \ + RUART_LINE_STATUS_ERR_RXFIFO) //Line status error + +#define RUART_MODEM_STATUS_REG_OFF 0x18 //Modem Status Register +#define RUART_SCRATCH_PAD_REG_OFF 0x1C //Scratch Pad Register +#define RUART_SP_REG_RXBREAK_INT_STATUS (1<<7) //BIT7, 0x80, Write 1 clear +#define RUART_SP_REG_DBG_SEL (0x0F<<8) //[11:8], Debug port selection +#define RUART_SP_REG_XFACTOR_ADJ (0x7FF<<16) //[26:16] + +#define RUART_STS_REG_OFF 0x20 +#define RUART_STS_REG_RESET_RCV (1<<3) //BIT3, 0x08, Reset Uart Receiver +#define RUART_STS_REG_XFACTOR 0xF<<4 + +#define RUART_REV_BUF_REG_OFF 0x24 //Receiver Buffer Register +#define RUART_TRAN_HOLD_REG_OFF 0x24 //Transmitter Holding Register + +#define RUART_MISC_CTL_REG_OFF 0x28 +#define RUART_TXDMA_BURSTSIZE_MASK 0xF8 //7:3 +#define RUART_RXDMA_BURSTSIZE_MASK 0x1F00 //12:8 + +#define RUART_DEBUG_REG_OFF 0x3C + +// RUART_LINE_CTL_REG_OFF (0x0C) +#define BIT_SHIFT_LCR_WLS 0 // word length select: 0: 7 bits, 1: 8bits +#define BIT_MASK_LCR_WLS_8BITS 0x1 +#define BIT_LCR_WLS(x)(((x) & BIT_MASK_LCR_WLS_8BITS) << BIT_SHIFT_LCR_WLS) +#define BIT_CLR_LCR_WLS (~(BIT_MASK_LCR_WLS_8BITS << BIT_SHIFT_LCR_WLS)) + +#define BIT_SHIFT_LCR_STB 2 // Stop bit select: 0: no stop bit, 1: 1 stop bit +#define BIT_MASK_LCR_STB_EN 0x1 +#define BIT_LCR_STB_EN(x)(((x) & BIT_MASK_LCR_STB_EN) << BIT_SHIFT_LCR_STB) +#define BIT_INVC_LCR_STB_EN (~(BIT_MASK_LCR_STB_EN << BIT_SHIFT_LCR_STB)) + +#define BIT_SHIFT_LCR_PARITY_EN 3 +#define BIT_MASK_LCR_PARITY_EN 0x1 +#define BIT_LCR_PARITY_EN(x)(((x) & BIT_MASK_LCR_PARITY_EN) << BIT_SHIFT_LCR_PARITY_EN) +#define BIT_INVC_LCR_PARITY_EN (~(BIT_MASK_LCR_PARITY_EN << BIT_SHIFT_LCR_PARITY_EN)) + +#define BIT_SHIFT_LCR_PARITY_TYPE 4 +#define BIT_MASK_LCR_PARITY_TYPE 0x1 +#define BIT_LCR_PARITY_TYPE(x)(((x) & BIT_MASK_LCR_PARITY_TYPE) << BIT_SHIFT_LCR_PARITY_TYPE) +#define BIT_INVC_LCR_PARITY_TYPE (~(BIT_MASK_LCR_PARITY_TYPE << BIT_SHIFT_LCR_PARITY_TYPE)) + +#define BIT_SHIFT_LCR_STICK_PARITY_EN 5 +#define BIT_MASK_LCR_STICK_PARITY_EN 0x1 +#define BIT_LCR_STICK_PARITY_EN(x)(((x) & BIT_MASK_LCR_STICK_PARITY_EN) << BIT_SHIFT_LCR_STICK_PARITY_EN) +#define BIT_INVC_LCR_STICK_PARITY_EN (~(BIT_MASK_LCR_STICK_PARITY_EN << BIT_SHIFT_LCR_STICK_PARITY_EN)) + +#define BIT_SHIFT_LCR_BREAK_CTRL 6 +#define BIT_MASK_LCR_BREAK_CTRL 0x1 +#define BIT_UART_LCR_BREAK_CTRL ((BIT_MASK_LCR_BREAK_CTRL) << BIT_SHIFT_LCR_BREAK_CTRL) + +#define RUART_BAUD_RATE_2400 2400 +#define RUART_BAUD_RATE_4800 4800 +#define RUART_BAUD_RATE_9600 9600 +#define RUART_BAUD_RATE_19200 19200 +#define RUART_BAUD_RATE_38400 38400 +#define RUART_BAUD_RATE_57600 57600 +#define RUART_BAUD_RATE_115200 115200 +#define RUART_BAUD_RATE_921600 921600 +#define RUART_BAUD_RATE_1152000 1152000 + +#define HAL_RUART_READ32(UartIndex, addr) \ + HAL_READ32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr) +#define HAL_RUART_WRITE32(UartIndex, addr, value) \ + HAL_WRITE32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value) +#define HAL_RUART_READ16(UartIndex, addr) \ + HAL_READ16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr) +#define HAL_RUART_WRITE16(UartIndex, addr, value) \ + HAL_WRITE16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value) +#define HAL_RUART_READ8(UartIndex, addr) \ + HAL_READ8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr) +#define HAL_RUART_WRITE8(UartIndex, addr, value) \ + HAL_WRITE8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value) + +#define UART_OVSR_POOL_MIN 1000 +#define UART_OVSR_POOL_MAX 2090 +#define DIVISOR_RESOLUTION 10 +#define JITTER_LIMIT 100 +#define UART_SCLK (200000000*5/12) + +typedef struct _RUART_SPEED_SETTING_ { + u32 BaudRate; + u32 Ovsr; + u32 Div; + u16 Ovsr_adj; + u8 Ovsr_adj_max_bits; // 9: No parity, 10: with Parity + u8 Ovsr_adj_bits; + u16 *Ovsr_adj_map; + u32 max_err; // 10 ~ 100: 30 + u32 Ovsr_min; // 10 ~ 20: 1000 + u32 Ovsr_max; // 10 ~ 20: 2000 + u32 divisor_resolution; // 1 ~ 20: 10 + u32 jitter_lim; // 50 ~ 100: 100 + u32 sclk; // 83.33333 MHz +}RUART_SPEED_SETTING, *PRUART_SPEED_SETTING; + +typedef enum _UART_RXFIFO_TRIGGER_LEVEL_ { + OneByte = 0x00, + FourBytes = 0x01, + EightBytes = 0x10, + FourteenBytes = 0x11 +}UART_RXFIFO_TRIGGER_LEVEL, *PUART_RXFIFO_TRIGGER_LEVEL; + +typedef enum _RUART0_PINMUX_SELECT_ { + RUART0_MUX_TO_GPIOC = S0, + RUART0_MUX_TO_GPIOE = S1, + RUART0_MUX_TO_GPIOA = S2 +}RUART0_PINMUX_SELECT, *PRUART0_PINMUX_SELECT; + +typedef enum _RUART1_PINMUX_SELECT_ { + RUART1_MUX_TO_GPIOD = S0, + RUART1_MUX_TO_GPIOE = S1, + RUART1_MUX_TO_GPIOB = S2 +}RUART1_PINMUX_SELECT, *PRUART1_PINMUX_SELECT; + +typedef enum _RUART2_PINMUX_SELECT_ { + RUART2_MUX_TO_GPIOA = S0, + RUART2_MUX_TO_GPIOC = S1, + RUART2_MUX_TO_GPIOD = S2 +}RUART2_PINMUX_SELECT, *PRUART2_PINMUX_SELECT; + +typedef enum _RUART_FLOW_CONTROL_ { + AUTOFLOW_DISABLE = 0, + AUTOFLOW_ENABLE = 1 +}RUART_FLOW_CONTROL, *PRUART_FLOW_CONTROL; + +typedef enum _RUART_WORD_LEN_SEL_ { + RUART_WLS_7BITS = 0, + RUART_WLS_8BITS = 1 +}RUART_WORD_LEN_SEL, *PRUART_WORD_LEN_SEL; + +typedef enum _RUART_STOP_BITS_ { + RUART_STOP_BIT_1 = 0, + RUART_STOP_BIT_2 = 1 +}RUART_STOP_BITS, *PRUART_STOP_BITS; + +typedef enum _RUART_PARITY_CONTROL_ { + RUART_PARITY_DISABLE = 0, + RUART_PARITY_ENABLE = 1 +}RUART_PARITY_CONTROL, *PRUART_PARITY_CONTROL; + +typedef enum _RUART_PARITY_TYPE_ { + RUART_ODD_PARITY = 0, + RUART_EVEN_PARITY = 1 +}RUART_PARITY_TYPE, *PRUART_PARITY_TYPE; + +typedef enum _RUART_STICK_PARITY_CONTROL_ { + RUART_STICK_PARITY_DISABLE = 0, + RUART_STICK_PARITY_ENABLE = 1 +}RUART_STICK_PARITY_CONTROL, *PRUART_STICK_PARITY_CONTROL; + +typedef enum _UART_INT_ID_ { + ModemStatus = 0, + TxFifoEmpty = 1, + ReceiverDataAvailable = 2, + ReceivLineStatus = 3, + TimeoutIndication = 6 +}UART_INT_ID, *PUART_INT_ID; + +typedef enum _HAL_UART_State_ +{ + HAL_UART_STATE_NULL = 0x00, // UART hardware not been initial yet + HAL_UART_STATE_READY = 0x10, // UART is initialed, ready to use + HAL_UART_STATE_BUSY = 0x20, // UART hardware is busy on configuration + HAL_UART_STATE_BUSY_TX = 0x21, // UART is buzy on TX + HAL_UART_STATE_BUSY_RX = 0x22, // UART is busy on RX + HAL_UART_STATE_BUSY_TX_RX = 0x23, // UART is busy on TX an RX + HAL_UART_STATE_TIMEOUT = 0x30, // Transfer timeout + HAL_UART_STATE_ERROR = 0x40 // UART Error +}HAL_UART_State, *PHAL_UART_State; + +typedef enum _HAL_UART_Status_ +{ + HAL_UART_STATUS_OK = 0x00, // Transfer OK + HAL_UART_STATUS_TIMEOUT = 0x01, // Transfer Timeout + HAL_UART_STATUS_ERR_OVERRUN = 0x02, // RX Over run + HAL_UART_STATUS_ERR_PARITY = 0x04, // Parity error + HAL_UART_STATUS_ERR_FRAM = 0x08, // Framing Error + HAL_UART_STATUS_ERR_BREAK = 0x10, // Break Interrupt + HAL_UART_STATUS_ERR_PARA = 0x20, // Parameter error + HAL_UART_STATUS_ERR_RXFIFO = 0x80, // RX FIFO error +}HAL_UART_Status, *PHAL_UART_Status; + +u32 +HalRuartGetDebugValueRtl8195a( + IN VOID* Data, + IN u32 DbgSel + ); + +#if 0 +u32 +FindElementIndex( + u32 Element, + u32* Array + ); +#endif + +VOID +RuartResetRxFifoRtl8195a( + IN u8 UartIndex + ); +#if 0 +VOID +RuartBusDomainEnableRtl8195a( + IN u8 UartIndex + ); +#endif + +HAL_Status +HalRuartResetRxFifoRtl8195a( + IN VOID *Data + ); + +HAL_Status +HalRuartInitRtl8195a( + IN VOID *Data + ); + +VOID +HalRuartDeInitRtl8195a( + IN VOID *Data ///< RUART Adapter + ); + +HAL_Status +HalRuartPutCRtl8195a( + IN VOID *Data, + IN u8 TxData + ); + +u32 +HalRuartSendRtl8195a( + IN VOID *Data, + IN u8 *pTxData, + IN u32 Length, + IN u32 Timeout + ); + +HAL_Status +HalRuartIntSendRtl8195a( + IN VOID *Data, // PHAL_RUART_ADAPTER + IN u8 *pTxData, // the Buffer to be send + IN u32 Length // the length of data to be send + ); + +HAL_Status +HalRuartDmaSendRtl8195a( + IN VOID *Data, // PHAL_RUART_ADAPTER + IN u8 *pTxData, // the Buffer to be send + IN u32 Length // the length of data to be send +); + +HAL_Status +HalRuartStopSendRtl8195a( + IN VOID *Data // PHAL_RUART_ADAPTER +); + +HAL_Status +HalRuartGetCRtl8195a( + IN VOID *Data, + OUT u8 *pRxByte + ); + +u32 +HalRuartRecvRtl8195a( + IN VOID *Data, + IN u8 *pRxData, + IN u32 Length, + IN u32 Timeout + ); + +HAL_Status +HalRuartIntRecvRtl8195a( + IN VOID *Data, ///< RUART Adapter + IN u8 *pRxData, ///< Rx buffer + IN u32 Length // buffer length + ); + +HAL_Status +HalRuartDmaRecvRtl8195a( + IN VOID *Data, ///< RUART Adapter + IN u8 *pRxData, ///< Rx buffer + IN u32 Length // buffer length + ); + +HAL_Status +HalRuartStopRecvRtl8195a( + IN VOID *Data // PHAL_RUART_ADAPTER +); + +u8 +HalRuartGetIMRRtl8195a( + IN VOID *Data + ); + +_LONG_CALL_ VOID +HalRuartSetIMRRtl8195a( + IN VOID *Data + ); + +VOID +HalRuartDmaInitRtl8195a( + IN VOID *Data + ); + +VOID +HalRuartRTSCtrlRtl8195a( + IN VOID *Data, + IN BOOLEAN RtsCtrl + ); + +VOID +HalRuartRegIrqRtl8195a( + IN VOID *Data + ); + +VOID +HalRuartIntEnableRtl8195a( + IN VOID *Data + ); + +VOID +HalRuartIntDisableRtl8195a( + IN VOID *Data + ); + +VOID +HalRuartAdapterLoadDefRtl8195a( + IN VOID *pAdp, + IN u8 UartIdx +); + +VOID +HalRuartTxGdmaLoadDefRtl8195a( + IN VOID *pAdp, + IN VOID *pCfg +); + +VOID +HalRuartRxGdmaLoadDefRtl8195a( + IN VOID *pAdp, + IN VOID *pCfg +); + +_LONG_CALL_ HAL_Status HalRuartIntSendRtl8195aV02( + IN VOID *Data, // PHAL_RUART_ADAPTER + IN u8 *pTxData, // the Buffer to be send + IN u32 Length // the length of data to be send +); + +_LONG_CALL_ HAL_Status +HalRuartIntRecvRtl8195aV02( + IN VOID *Data, ///< RUART Adapter + IN u8 *pRxData, ///< Rx buffer + IN u32 Length // buffer length +); + +_LONG_CALL_ s32 +FindElementIndex_v02( + u32 Element, ///< RUART Baudrate + u32* Array, ///< Pre-defined Baudrate Array + u32 ElementNo +); + +_LONG_CALL_ HAL_Status HalRuartInitRtl8195a_v02(IN VOID *Data); + +// New added function 2015/04/20 +HAL_Status +HalRuartResetTxFifoRtl8195a( + IN VOID *Data ///< RUART Adapter + ); + +HAL_Status +HalRuartSetBaudRateRtl8195a( + IN VOID *Data + ); + +HAL_Status +HalRuartEnableRtl8195a( + IN VOID *Data +); + +HAL_Status +HalRuartDisableRtl8195a( + IN VOID *Data +); + +HAL_Status +HalRuartFlowCtrlRtl8195a( + IN VOID *Data +); + +HAL_Status +HalRuartDmaSendRtl8195a_Patch( + IN VOID *Data, + IN u8 *pTxData, + IN u32 Length +); + +HAL_Status +RuartIsTimeout ( + u32 StartCount, + u32 TimeoutCnt +); + +HAL_Status +HalRuartStopRecvRtl8195a_Patch( + IN VOID *Data +); + +HAL_Status +HalRuartStopSendRtl8195a_Patch( + IN VOID *Data +); + +VOID +HalRuartEnterCriticalRtl8195a( + IN VOID *Data +); + +VOID +HalRuartExitCriticalRtl8195a( + IN VOID *Data +); + +#if CONFIG_CHIP_E_CUT +_LONG_CALL_ HAL_Status +HalRuartSetBaudRateRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ HAL_Status +HalRuartInitRtl8195a_V04( + IN VOID *Data ///< RUART Adapter +); + +_LONG_CALL_ HAL_Status +HalRuartEnableRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ HAL_Status +HalRuartDisableRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ HAL_Status +HalRuartFlowCtrlRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ HAL_Status +HalRuartDmaSendRtl8195a_V04( + IN VOID *Data, + IN u8 *pTxData, + IN u32 Length +); + +_LONG_CALL_ HAL_Status +HalRuartStopRecvRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ HAL_Status +HalRuartStopSendRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ VOID +HalRuartEnterCriticalRtl8195a_V04( + IN VOID *Data +); + +_LONG_CALL_ VOID +HalRuartExitCriticalRtl8195a_V04( + IN VOID *Data +); + +#endif // #if CONFIG_CHIP_E_CUT + +#endif diff --git a/lib/fwlib/rtl8195a/rtl8195a_wdt.h b/lib/fwlib/rtl8195a/rtl8195a_wdt.h new file mode 100644 index 0000000..edbedd2 --- /dev/null +++ b/lib/fwlib/rtl8195a/rtl8195a_wdt.h @@ -0,0 +1,86 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2014 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _RTL8195A_WDT_H_ +#define _RTL8195A_WDT_H_ + +#define WDGTIMERELY (10*1024) //us + +typedef struct _WDG_REG_ { + u16 WdgScalar; + u8 WdgEnByte; + u8 WdgClear:1; + u8 WdgCunLimit:4; + u8 Rsvd:1; + u8 WdgMode:1; + u8 WdgToISR:1; +}WDG_REG, *PWDG_REG; + +typedef struct _WDG_ADAPTER_ { + + WDG_REG Ctrl; + IRQ_HANDLE IrqHandle; + TIMER_ADAPTER WdgGTimer; + VOID (*UserCallback)(u32 callback_id); // User callback function + u32 callback_id; +}WDG_ADAPTER, *PWDG_ADAPTER; + +typedef enum _WDG_CNTLMT_ { + CNT1H = 0, + CNT3H = 1, + CNT7H = 2, + CNTFH = 3, + CNT1FH = 4, + CNT3FH = 5, + CNT7FH = 6, + CNTFFH = 7, + CNT1FFH = 8, + CNT3FFH = 9, + CNT7FFH = 10, + CNTFFFH = 11 +}WDG_CNTLMT, *PWDG_CNTLMT; + + +typedef enum _WDG_MODE_ { + INT_MODE = 0, + RESET_MODE = 1 +}WDG_MODE, *PWDG_MODE; + +extern VOID +WDGInitial( + IN u32 Period +); + +extern VOID +WDGIrqInitial( + VOID +); + +extern VOID +WDGIrqInitial( + VOID +); + +extern VOID +WDGStop( + VOID +); + +extern VOID +WDGRefresh( + VOID +); + +extern VOID +WDGIrqCallBackReg( + IN VOID *CallBack, + IN u32 Id +); + +#endif //_RTL8195A_WDT_H_ diff --git a/lib/fwlib/rtl8195a/src/rtl8195a_adc.c b/lib/fwlib/rtl8195a/src/rtl8195a_adc.c new file mode 100644 index 0000000..62656aa --- /dev/null +++ b/lib/fwlib/rtl8195a/src/rtl8195a_adc.c @@ -0,0 +1,387 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "platform_autoconf.h" +#include "diag.h" +#include "rtl8195a_adc.h" +#include "hal_adc.h" + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// HalI2CInit8195a +// +// Description: +// To initialize I2C module by using the given data. +// +// Arguments: +// [in] VOID *Data - +// The I2C parameter data struct. +// +// Return: +// The status of the DeInit process. +// _EXIT_SUCCESS if the initialization succeeded. +// _EXIT_FAILURE if the initialization failed. +// +// Note: +// None +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//--------------------------------------------------------------------------------------------------- +RTK_STATUS +HalADCInit8195a( + IN VOID *Data +) +{ + PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data; + u32 AdcTempDat; + u8 AdcTempIdx = pHalAdcInitData->ADCIdx; + + /* Enable ADC power cut */ +/* + AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER); + AdcTempDat |= BIT_ADC_PWR_AUTO; + HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat); +*/ + + /* ADC Control register set-up*/ + AdcTempDat = 0; + AdcTempDat |= (BIT_CTRL_ADC_COMP_ONLY(pHalAdcInitData->ADCCompOnly) | + BIT_CTRL_ADC_ONESHOT(pHalAdcInitData->ADCOneShotEn) | + BIT_CTRL_ADC_OVERWRITE(pHalAdcInitData->ADCOverWREn) | + BIT_CTRL_ADC_ENDIAN(pHalAdcInitData->ADCEndian) | + BIT_CTRL_ADC_BURST_SIZE(pHalAdcInitData->ADCBurstSz) | + BIT_CTRL_ADC_THRESHOLD(pHalAdcInitData->ADCOneShotTD) | + BIT_CTRL_ADC_DBG_SEL(pHalAdcInitData->ADCDbgSel)); + HAL_ADC_WRITE32(REG_ADC_CONTROL,AdcTempDat); + + DBG_8195A_ADC_LVL(HAL_ADC_LVL,"REG_ADC_CONTROL:%x\n", HAL_ADC_READ32(REG_ADC_CONTROL)); + + /* ADC compare value and compare method setting*/ + switch (AdcTempIdx) { + case ADC0_SEL: + AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_L); + AdcTempDat &= ~(BIT_ADC_COMP_TH_0(0xFFFF)); + AdcTempDat |= BIT_CTRL_ADC_COMP_TH_0(pHalAdcInitData->ADCCompTD); + HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat); + break; + + case ADC1_SEL: + AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_L); + AdcTempDat &= ~(BIT_ADC_COMP_TH_1(0xFFFF)); + AdcTempDat |= BIT_CTRL_ADC_COMP_TH_1(pHalAdcInitData->ADCCompTD); + HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat); + break; + + case ADC2_SEL: + AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_H); + AdcTempDat &= ~(BIT_ADC_COMP_TH_2(0xFFFF)); + AdcTempDat |= BIT_CTRL_ADC_COMP_TH_2(pHalAdcInitData->ADCCompTD); + HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat); + break; + + case ADC3_SEL: + AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_H); + AdcTempDat &= ~(BIT_ADC_COMP_TH_3(0xFFFF)); + AdcTempDat |= BIT_CTRL_ADC_COMP_TH_3(pHalAdcInitData->ADCCompTD); + HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat); + break; + default: + return _EXIT_FAILURE; + } + + /* ADC compare mode setting */ + AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_SET); + AdcTempDat &= (~(0x01 << pHalAdcInitData->ADCIdx)); + AdcTempDat |= (BIT_CTRL_ADC_COMP_0_EN(pHalAdcInitData->ADCCompCtrl) << + pHalAdcInitData->ADCIdx); + HAL_ADC_WRITE32(REG_ADC_COMP_SET, AdcTempDat); + + /* ADC audio mode set-up */ + AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0); + AdcTempDat &= ~(BIT_ADC_AUDIO_EN); + AdcTempDat |= BIT_CTRL_ADC_AUDIO_EN(pHalAdcInitData->ADCAudioEn); + HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat); + + /* ADC enable manually setting */ + AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0); + AdcTempDat &= ~(BIT_ADC_EN_MANUAL); + AdcTempDat |= BIT_CTRL_ADC_EN_MANUAL(pHalAdcInitData->ADCEnManul); + HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat); + + + /* ADC analog parameter 0 */ + AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0); + DBG_ADC_INFO("AD0:%x\n", AdcTempDat); + //AdcTempDat |= (BIT0); + if (pHalAdcInitData->ADCInInput == 1){ + AdcTempDat &= (~BIT14); + } + else { + AdcTempDat |= (BIT14); + } + AdcTempDat &= (~(BIT3|BIT2)); + + /* Adjust VCM for C-Cut*/ +#ifdef CONFIG_CHIP_C_CUT + AdcTempDat |= (BIT22); +#endif + + HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat); + AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0); + DBG_ADC_INFO("AD0:%x\n", AdcTempDat); + + /* ADC analog parameter 1 */ + AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD1); + AdcTempDat &= (~BIT1); + AdcTempDat |= (BIT2|BIT0); + HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1, AdcTempDat); + AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD1); + DBG_ADC_INFO("AD1:%x\n", AdcTempDat); + + /* ADC analog parameter 2 */ + AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD2); + DBG_ADC_INFO("AD2:%x\n", AdcTempDat); + AdcTempDat = 0x67884400; + HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD2, AdcTempDat); + AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD2); + DBG_ADC_INFO("AD2:%x\n", AdcTempDat); + + /* ADC analog parameter 3 */ + AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD3); + DBG_ADC_INFO("AD3:%x\n", AdcTempDat); + AdcTempDat = 0x77780039; + HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD3, AdcTempDat); + AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD3); + DBG_ADC_INFO("AD3:%x\n", AdcTempDat); + + /* ADC analog parameter 4 */ + AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD4); + DBG_ADC_INFO("AD4:%x\n", AdcTempDat); + AdcTempDat = 0x0004d501; + HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD4, AdcTempDat); + AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD4); + DBG_ADC_INFO("AD4:%x\n", AdcTempDat); + + /* ADC analog parameter 5 */ + AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD5); + DBG_ADC_INFO("AD5:%x\n", AdcTempDat); + AdcTempDat = 0x1E010800; + HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD5, AdcTempDat); + AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD5); + DBG_ADC_INFO("AD5:%x\n", AdcTempDat); + + return _EXIT_SUCCESS; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// HalI2CInit8195a +// +// Description: +// To initialize I2C module by using the given data. +// +// Arguments: +// [in] VOID *Data - +// The I2C parameter data struct. +// +// Return: +// The status of the DeInit process. +// _EXIT_SUCCESS if the initialization succeeded. +// _EXIT_FAILURE if the initialization failed. +// +// Note: +// None +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//--------------------------------------------------------------------------------------------------- +RTK_STATUS +HalADCDeInit8195a( + IN VOID *Data +) +{ + u32 AdcTempDat; + + AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER); + AdcTempDat &= ~(BIT_ADC_PWR_AUTO); + HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat); + + return _EXIT_SUCCESS; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// HalI2CIntrCtrl8195a +// +// Description: +// Modify the I2C interrupt mask according to the given value +// +// Arguments: +// [in] VOID *Data - +// The I2C parameter data struct. +// +// Return: +// The status of the enable process. +// _EXIT_SUCCESS if the de-initialization succeeded. +// _EXIT_FAILURE if the de-initialization failed. +// +// Note: +// None +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-02-18. +// +//--------------------------------------------------------------------------------------------------- +RTK_STATUS +HalADCEnableRtl8195a( + IN VOID *Data +){ + PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data; + u32 AdcTempDat; + DBG_ADC_INFO("HalADCEnableRtl8195a\n"); + + AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER); + + AdcTempDat &= (~BIT_ADC_PWR_AUTO); + AdcTempDat |= 0x02; + HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat); + AdcTempDat |= 0x04; + HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat); + AdcTempDat &= (~0x08); + HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat); + + AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_POWER); + DBG_ADC_INFO("HalADCEnableRtl8195a, power reg:%x\n",AdcTempDat); + return _EXIT_SUCCESS; +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// HalI2CIntrCtrl8195a +// +// Description: +// Modify the I2C interrupt mask according to the given value +// +// Arguments: +// [in] VOID *Data - +// The I2C parameter data struct. +// +// Return: +// The status of the enable process. +// _EXIT_SUCCESS if the de-initialization succeeded. +// _EXIT_FAILURE if the de-initialization failed. +// +// Note: +// None +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-02-18. +// +//--------------------------------------------------------------------------------------------------- +RTK_STATUS +HalADCIntrCtrl8195a( + IN VOID *Data +){ + PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data; + + HAL_ADC_WRITE32(REG_ADC_INTR_EN, pHalAdcInitData->ADCIntrMSK); + + return _EXIT_SUCCESS; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// HalI2CReceiveRtl8195a +// +// Description: +// Directly read one data byte a I2C data fifo. +// +// Arguments: +// [in] VOID *Data - +// The I2C parameter data struct. +// +// Return: +// The first data fifo content. +// +// Note: +// None +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-02-18. +// +//--------------------------------------------------------------------------------------------------- +u32 +HalADCReceiveRtl8195a( + IN VOID *Data +){ + u32 AdcTempDat; + + AdcTempDat = HAL_ADC_READ32(REG_ADC_FIFO_READ); + + return (AdcTempDat); +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// HalI2CReadRegRtl8195a +// +// Description: +// Directly read a I2C register according to the register offset. +// +// Arguments: +// [in] VOID *Data - +// The I2C parameter data struct. +// [in] I2CReg - +// The I2C register offset. +// +// Return: +// The register content in u32 format. +// +// Note: +// None +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-02-18. +// +//--------------------------------------------------------------------------------------------------- +u32 +HalADCReadRegRtl8195a( + IN VOID *Data, + IN u8 I2CReg +){ + u32 AdcTempDat; + + AdcTempDat = HAL_ADC_READ32(I2CReg); + return (AdcTempDat); +} + diff --git a/lib/fwlib/rtl8195a/src/rtl8195a_dac.c b/lib/fwlib/rtl8195a/src/rtl8195a_dac.c new file mode 100644 index 0000000..a9bc7a7 --- /dev/null +++ b/lib/fwlib/rtl8195a/src/rtl8195a_dac.c @@ -0,0 +1,269 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "rtl8195a.h" +#include "rtl8195a_dac.h" +#include "hal_dac.h" + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// HalDACInit8195a +// +// Description: +// To initialize DAC module by using the given data. +// +// Arguments: +// [in] VOID *Data - +// The DAC parameter data struct. +// +// Return: +// The status of the DeInit process. +// _EXIT_SUCCESS if the initialization succeeded. +// _EXIT_FAILURE if the initialization failed. +// +// Note: +// None +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-15. +// +//--------------------------------------------------------------------------------------------------- +RTK_STATUS +HalDACInit8195a( + IN VOID *Data +){ + PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data; + u32 DacTempDat; + u8 DacTempIdx = pHalDacInitData->DACIdx; + + /* Enable DAC power cut */ + DacTempDat = HAL_DAC_READ32(0, REG_DAC_PWR_CTRL); + DacTempDat |= BIT_DAC_PWR_AUTO; + + HAL_DAC_WRITE32(0, REG_DAC_PWR_CTRL, DacTempDat); + + /* Disable DAC module first */ + HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, 0); + + /* Setup DAC module */ + DacTempDat = 0; + DacTempDat |= (BIT_CTRL_DAC_SPEED(pHalDacInitData->DACDataRate) | + BIT_CTRL_DAC_ENDIAN(pHalDacInitData->DACEndian) | + BIT_CTRL_DAC_FILTER_SETTLE(pHalDacInitData->DACFilterSet) | + BIT_CTRL_DAC_BURST_SIZE(pHalDacInitData->DACBurstSz) | + BIT_CTRL_DAC_DBG_SEL(pHalDacInitData->DACDbgSel) | + BIT_CTRL_DAC_DSC_DBG_SEL(pHalDacInitData->DACDscDbgSel) | + BIT_CTRL_DAC_BYPASS_DSC(pHalDacInitData->DACBPDsc) | + BIT_CTRL_DAC_DELTA_SIGMA(pHalDacInitData->DACDeltaSig)); + + HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat); + + return _EXIT_SUCCESS; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// HalI2CInit8195a +// +// Description: +// To initialize I2C module by using the given data. +// +// Arguments: +// [in] VOID *Data - +// The I2C parameter data struct. +// +// Return: +// The status of the DeInit process. +// _EXIT_SUCCESS if the initialization succeeded. +// _EXIT_FAILURE if the initialization failed. +// +// Note: +// None +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//--------------------------------------------------------------------------------------------------- +RTK_STATUS +HalDACDeInit8195a( + IN VOID *Data +){ + PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data; + u32 DacTempDat; + + DacTempDat = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_CTRL); + DacTempDat &= (~BIT_DAC_FIFO_EN); + HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_CTRL ,DacTempDat); + + return _EXIT_SUCCESS; +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// HalI2CIntrCtrl8195a +// +// Description: +// Modify the I2C interrupt mask according to the given value +// +// Arguments: +// [in] VOID *Data - +// The I2C parameter data struct. +// +// Return: +// The status of the enable process. +// _EXIT_SUCCESS if the de-initialization succeeded. +// _EXIT_FAILURE if the de-initialization failed. +// +// Note: +// None +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-02-18. +// +//--------------------------------------------------------------------------------------------------- +RTK_STATUS +HalDACEnableRtl8195a( + IN VOID *Data +){ + PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data; + u32 DacTempDat; + u8 DacTempIdx = pHalDacInitData->DACIdx; + + DacTempDat = HAL_DAC_READ32(DacTempIdx, REG_DAC_CTRL); + DacTempDat &= (~BIT_DAC_FIFO_EN); + + DacTempDat |= BIT_CTRL_DAC_FIFO_EN(pHalDacInitData->DACEn); + HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat); + + return _EXIT_SUCCESS; +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// HalI2CIntrCtrl8195a +// +// Description: +// Modify the I2C interrupt mask according to the given value +// +// Arguments: +// [in] VOID *Data - +// The I2C parameter data struct. +// +// Return: +// The status of the enable process. +// _EXIT_SUCCESS if the de-initialization succeeded. +// _EXIT_FAILURE if the de-initialization failed. +// +// Note: +// None +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-02-18. +// +//--------------------------------------------------------------------------------------------------- +RTK_STATUS +HalDACIntrCtrl8195a( + IN VOID *Data +){ + PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data; + + HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_INTR_CTRL, pHalDacInitData->DACIntrMSK); + + return _EXIT_SUCCESS; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// HalI2CReceiveRtl8195a +// +// Description: +// Directly read one data byte a I2C data fifo. +// +// Arguments: +// [in] VOID *Data - +// The I2C parameter data struct. +// +// Return: +// The first data fifo content. +// +// Note: +// None +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-02-18. +// +//--------------------------------------------------------------------------------------------------- +u8 +HalDACSendRtl8195a( + IN VOID *Data +){ + + + return (0); +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// HalDACReadRegRtl8195a +// +// Description: +// +// +// Arguments: +// [in] VOID *Data - +// The DAC parameter data struct. +// [in] I2CReg - +// The DAC register offset. +// +// Return: +// The DAC register content in u32 format. +// +// Note: +// None +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-15. +// +//--------------------------------------------------------------------------------------------------- +u32 +HalDACReadRegRtl8195a( + IN VOID *Data, + IN u8 I2CReg +){ + PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data; + + //DBG_8195A_DAC("dac read reg idx:%x\n",pHalDacInitData->DACIdx); + //DBG_8195A_DAC("dac read reg offset:%x\n",I2CReg); + + return (u32)HAL_DAC_READ32(pHalDacInitData->DACIdx, I2CReg); +} + diff --git a/lib/fwlib/rtl8195a/src/rtl8195a_gdma.c b/lib/fwlib/rtl8195a/src/rtl8195a_gdma.c new file mode 100644 index 0000000..3c5f8dd --- /dev/null +++ b/lib/fwlib/rtl8195a/src/rtl8195a_gdma.c @@ -0,0 +1,291 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "rtl8195a.h" +#include "rtl8195a_gdma.h" +#include "hal_gdma.h" + +#ifndef CONFIG_CHIP_E_CUT +BOOL +HalGdmaChBlockSetingRtl8195a( + IN VOID *Data +) +{ + PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data; + PGDMA_CH_LLI_ELE pLliEle; + struct GDMA_CH_LLI *pGdmaChLli; + struct BLOCK_SIZE_LIST *pGdmaChBkLi; + u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock; + u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp; + u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex; + u8 ChNum = pHalGdmaAdapter->ChNum; + u32 ChEn = pHalGdmaAdapter->ChEn; + u8 GdmaChIsrBitmap = (ChEn & 0xFF); + u8 PendingIsrIndex; + + + pLliEle = pHalGdmaAdapter->pLlix->pLliEle; + pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli; + pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList; + + + //4 1) Check chanel is avaliable + if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) { + //4 Disable Channel + DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n"); + + HalGdmaChDisRtl8195a(Data); + + } + + //4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran, Error + for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) { + + u32 PendRaw, PendStstus; + PendRaw = HAL_GDMAX_READ32(GdmaIndex, + (REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8)); + PendStstus = HAL_GDMAX_READ32(GdmaIndex, + (REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8)); + + if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) { + //4 Clear Pending Isr + HAL_GDMAX_WRITE32(GdmaIndex, + (REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8), + (PendStstus & (GdmaChIsrBitmap)) + ); + + } + } + + //4 Fill in SARx register + HAL_GDMAX_WRITE32(GdmaIndex, + (REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF), + (pHalGdmaAdapter->ChSar) + ); + + + //4 Fill in DARx register + HAL_GDMAX_WRITE32(GdmaIndex, + (REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF), + (pHalGdmaAdapter->ChDar) + ); + + + + //4 3) Process CTLx + CtlxLow = HAL_GDMAX_READ32(GdmaIndex, + (REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF)); + + //4 Clear Config low register bits + CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN & + BIT_INVC_CTLX_LO_DST_TR_WIDTH & + BIT_INVC_CTLX_LO_SRC_TR_WIDTH & + BIT_INVC_CTLX_LO_DINC & + BIT_INVC_CTLX_LO_SINC & + BIT_INVC_CTLX_LO_DEST_MSIZE & + BIT_INVC_CTLX_LO_SRC_MSIZE & + BIT_INVC_CTLX_LO_TT_FC & + BIT_INVC_CTLX_LO_LLP_DST_EN & + BIT_INVC_CTLX_LO_LLP_SRC_EN); + + CtlxUp = HAL_GDMAX_READ32(GdmaIndex, + (REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4)); + + //4 Clear Config upper register bits + CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS & + BIT_INVC_CTLX_UP_DONE); + + + CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) | + BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) | + BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) | + BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) | + BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) | + BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) | + BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) | + BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) | + BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) | + BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) | + CtlxLow; + + CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) | + BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) | + CtlxUp; + + //4 Fill in CTLx register + HAL_GDMAX_WRITE32(GdmaIndex, + (REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF), + CtlxLow + ); + + HAL_GDMAX_WRITE32(GdmaIndex, + (REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4), + CtlxUp + ); + + //4 4) Program CFGx + + CfgxLow = HAL_GDMAX_READ32(GdmaIndex, + (REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF)); + + CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR & + BIT_INVC_CFGX_LO_CH_SUSP & + BIT_INVC_CFGX_LO_HS_SEL_DST & + BIT_INVC_CFGX_LO_HS_SEL_SRC & + BIT_INVC_CFGX_LO_LOCK_CH_L & + BIT_INVC_CFGX_LO_LOCK_B_L & + BIT_INVC_CFGX_LO_LOCK_CH & + BIT_INVC_CFGX_LO_LOCK_B & + BIT_INVC_CFGX_LO_RELOAD_SRC & + BIT_INVC_CFGX_LO_RELOAD_DST); + + CfgxUp = HAL_GDMAX_READ32(GdmaIndex, + (REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4)); + + CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE & + BIT_INVC_CFGX_UP_DS_UPD_EN & + BIT_INVC_CFGX_UP_SS_UPD_EN & + BIT_INVC_CFGX_UP_SRC_PER & + BIT_INVC_CFGX_UP_DEST_PER); + + CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) | + BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) | + BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) | + BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) | + BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) | + BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) | + BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) | + BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) | + BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) | + BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) | + CfgxLow; + + CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) | + BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) | + BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) | + BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) | + BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) | + CfgxUp; + + HAL_GDMAX_WRITE32(GdmaIndex, + (REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF), + CfgxLow + ); + + HAL_GDMAX_WRITE32(GdmaIndex, + (REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4), + CfgxUp + ); + + + + //4 Check 4 Bytes Alignment + if ((u32)(pLliEle) & 0x3) { + DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!!!!\n", + pHalGdmaAdapter->pLli); + return _FALSE; + } + + HAL_GDMAX_WRITE32(GdmaIndex, + (REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF), + pLliEle + ); + + //4 Update the first llp0 + pLliEle->CtlxLow = CtlxLow; + pLliEle->CtlxUp = CtlxUp; + pLliEle->Llpx = (u32)pGdmaChLli->pLliEle; + DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount); + + pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz; + + while (MultiBlockCount > 1) { + MultiBlockCount--; + DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount); + pLliEle = pGdmaChLli->pLliEle; + + if (NULL == pLliEle) { + DBG_GDMA_ERR("pLliEle Null Point!!!!!\n"); + return _FALSE; + } + + //4 Clear the last element llp enable bit + if (1 == MultiBlockCount) { + if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 1){ + CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN & + BIT_INVC_CTLX_LO_LLP_SRC_EN); + } + } + //4 Update block size for transfer + CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS); + CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize); + + //4 Update tje Lli and Block size list point to next llp + pGdmaChLli = pGdmaChLli->pNextLli; + pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz; + + //4 Updatethe Llpx context + pLliEle->CtlxLow = CtlxLow; + pLliEle->CtlxUp = CtlxUp; + pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle); + + } + + return _TRUE; +} + +u32 +HalGdmaQueryDArRtl8195a( + IN VOID *Data +) +{ + PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data; + u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex; + u8 ChNum = pHalGdmaAdapter->ChNum; + u32 dar; + + dar = HAL_GDMAX_READ32(GdmaIndex, + (REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF)); + + return dar; +} + +u32 +HalGdmaQuerySArRtl8195a( + IN VOID *Data +) +{ + PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data; + u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex; + u8 ChNum = pHalGdmaAdapter->ChNum; + u32 dar; + + dar = HAL_GDMAX_READ32(GdmaIndex, + (REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF)); + + return dar; +} + +BOOL +HalGdmaQueryChEnRtl8195a ( + IN VOID *Data +) +{ + + PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data; + + if (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN) & (pHalGdmaAdapter->ChEn)) { + return 1; + } else { + return 0; + } +} + +#endif diff --git a/lib/fwlib/rtl8195a/src/rtl8195a_gpio.c b/lib/fwlib/rtl8195a/src/rtl8195a_gpio.c new file mode 100644 index 0000000..ccb7696 --- /dev/null +++ b/lib/fwlib/rtl8195a/src/rtl8195a_gpio.c @@ -0,0 +1,53 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#include "rtl8195a.h" +#include "hal_gpio.h" +#include "rtl8195a_gpio.h" +#include "gpio_irq_api.h" + +extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter; + +/** + * @brief Clear the pending interrupt of a specified pin + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin. + * + * @retval None + */ +HAL_Status +HAL_GPIO_ClearISR_8195a( + HAL_GPIO_PIN *GPIO_Pin +) +{ + u8 port_num; + u8 pin_num; + HAL_GPIO_PIN_MODE pin_mode; + + port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name); + pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name); + pin_mode = GPIO_Pin->pin_mode; + + if ((pin_mode & HAL_GPIO_PIN_INT_MODE)==0 || (port_num != GPIO_PORT_A)) { + DBG_GPIO_WARN("HAL_GPIO_ClearISR_8195a: This pin(%x:%x) is'nt an interrupt pin\n", GPIO_Pin->pin_name, GPIO_Pin->pin_mode); + return HAL_ERR_PARA; + } + + if (GPIO_Lock() != HAL_OK) { + return HAL_BUSY; + } + + // Clear pending interrupt before unmask it + HAL_WRITE32(GPIO_REG_BASE, GPIO_PORTA_EOI, (1<I2CIdx; + u8 *pDat = pHalI2CInitData->I2CRWData; + u8 I2CCmd = pHalI2CInitData->I2CCmd; + u8 I2CStop = pHalI2CInitData->I2CStop; + u8 I2CReSTR= pHalI2CInitData->I2CReSTR; + + DBG_I2C_INFO("HalI2CSendRtl8195a\n"); + DBG_I2C_INFO("I2C Index: %x\n",I2CIdx); + + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DATA_CMD, + *(pDat) | + BIT_CTRL_IC_DATA_CMD_RESTART(I2CReSTR)| + BIT_CTRL_IC_DATA_CMD_CMD(I2CCmd) | + BIT_CTRL_IC_DATA_CMD_STOP(I2CStop)); + + return (HAL_OK); +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// HalI2CInit8195a +// +// Description: +// To initialize I2C module by using the given data. +// +// Arguments: +// [in] VOID *Data - +// The I2C parameter data struct. +// +// Return: +// The status of the DeInit process. +// _EXIT_SUCCESS if the initialization succeeded. +// _EXIT_FAILURE if the initialization failed. +// +// Note: +// None +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//--------------------------------------------------------------------------------------------------- +HAL_Status +HalI2CInit8195a_Patch( + IN VOID *Data +) +{ + PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data; + + u8 Master; + u8 I2CIdx; + u8 SpdMd; + u8 AddrMd; + u8 ReSTR; + u8 StartByte; + u8 Specical; + u8 GC; + u16 I2CAckAddr; + u16 SdaHd; + u8 SdaSetup; + u8 RXTL; + u8 TXTL; + u8 SlvNoAck; + u32 INTRMsk; + u8 TxDMARqLv; + u8 RxDMARqLv; + + /* Get the I2C parameters*/ + I2CIdx = pHalI2CInitData->I2CIdx; + SpdMd = pHalI2CInitData->I2CSpdMod; + AddrMd = pHalI2CInitData->I2CAddrMod; + I2CAckAddr = pHalI2CInitData->I2CAckAddr; + Master = pHalI2CInitData->I2CMaster; + SdaHd = pHalI2CInitData->I2CSdaHd; + SdaSetup = pHalI2CInitData->I2CSetup; + + ReSTR = pHalI2CInitData->I2CReSTR; + GC = pHalI2CInitData->I2CGC; + StartByte = pHalI2CInitData->I2CStartB; + SlvNoAck = pHalI2CInitData->I2CSlvNoAck; + + RXTL = pHalI2CInitData->I2CRXTL; + TXTL = pHalI2CInitData->I2CTXTL; + + TxDMARqLv = pHalI2CInitData->I2CTxDMARqLv; + RxDMARqLv = pHalI2CInitData->I2CRxDMARqLv; + + /* Disable the IC first */ + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_ENABLE,BIT_CTRL_IC_ENABLE(0)); + + /* Master case*/ + if (Master) { + /*RESTART MUST be set in these condition in Master mode. + But it might be NOT compatible in old slaves.*/ + if ((AddrMd == I2C_ADDR_10BIT) || (SpdMd == I2C_HS_MODE)) + ReSTR = 1; + + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_CON, + (BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(1) | + BIT_CTRL_IC_CON_IC_RESTART_EN(ReSTR) | + BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(AddrMd) | + BIT_CTRL_IC_CON_SPEED(SpdMd) | + BIT_CTRL_IC_CON_MASTER_MODE(Master))); + + DBG_I2C_INFO("Init master, IC_CON%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_CON, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_CON)); + + + /* To set target addr.*/ + Specical = 0; + if ((GC!=0) || (StartByte!=0)) + Specical = 1; + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_TAR, + (BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(AddrMd) | + BIT_CTRL_IC_TAR_SPECIAL(Specical) | + BIT_CTRL_IC_TAR_GC_OR_START(StartByte) | + BIT_CTRL_IC_TAR(I2CAckAddr))); + + /* To Set I2C clock*/ + HalI2CSetCLKRtl8195a_Patch(pHalI2CInitData); + + + DBG_I2C_INFO("Init master, IC_TAR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_TAR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_TAR)); + + } /*if (Master)*/ + else { + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_CON, + BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(AddrMd) | + BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(Master) | + BIT_CTRL_IC_CON_SPEED(SpdMd)| + BIT_CTRL_IC_CON_MASTER_MODE(Master)); + + DBG_I2C_INFO("Init slave, IC_CON%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_CON, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_CON)); + + + /* To set slave addr. */ + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SAR,BIT_CTRL_IC_SAR(I2CAckAddr)); + + DBG_I2C_INFO("Init slave, IC_SAR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_SAR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SAR)); + + + /* To set slave no ack */ + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SLV_DATA_NACK_ONLY,BIT_CTRL_IC_SLV_DATA_NACK_ONLY(SlvNoAck)); + + /* Set ack general call. */ + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_ACK_GENERAL_CALL,BIT_CTRL_IC_ACK_GENERAL_CALL(pHalI2CInitData->I2CSlvAckGC)); + + + + DBG_I2C_INFO("Init slave, I2C_IC_ACK_GC%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_ACK_GENERAL_CALL, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_ACK_GENERAL_CALL)); + + /* to set SDA hold time */ + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(SdaHd)); + //4 + /* to set SDA setup time */ + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_SETUP,BIT_CTRL_IC_SDA_SETUP(SdaSetup)); + } + + /* To set TX_Empty Level */ + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_TX_TL,TXTL); + + /* To set RX_Full Level */ + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_RX_TL,RXTL); + + /* To set TX/RX FIFO level */ + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DMA_TDLR,TxDMARqLv); + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DMA_RDLR,RxDMARqLv); + + + DBG_I2C_INFO("Init i2c dev, I2C_IC_DMA_TDLR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_DMA_TDLR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_DMA_TDLR)); + DBG_I2C_INFO("Init i2c dev, I2C_IC_DMA_RDLR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_DMA_RDLR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_DMA_RDLR)); + + + /*I2C Clear all interrupts first*/ + HalI2CClrAllIntrRtl8195a(pHalI2CInitData); + + /*I2C Disable all interrupts first*/ + INTRMsk = pHalI2CInitData->I2CIntrMSK; + pHalI2CInitData->I2CIntrMSK = 0; + HalI2CIntrCtrl8195a(pHalI2CInitData); + pHalI2CInitData->I2CIntrMSK = INTRMsk; + + return HAL_OK; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// HalI2CSetCLKRtl8195a +// +// Description: +// To set I2C bus clock rate. +// +// Arguments: +// [in] VOID *Data - +// The I2C parameter data struct. +// +// Return: +// The status of the enable process. +// _EXIT_SUCCESS if the de-initialization succeeded. +// _EXIT_FAILURE if the de-initialization failed. +// +// Note: +// None +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-02-18. +// +//--------------------------------------------------------------------------------------------------- +HAL_Status +HalI2CSetCLKRtl8195a_Patch( + IN VOID *Data +) +{ + PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data; + u8 SpdMd = pHalI2CInitData->I2CSpdMod; + u32 I2CClk = pHalI2CInitData->I2CClk; + u8 I2CIdx = pHalI2CInitData->I2CIdx; + u32 ICHLcnt; + u32 ICHtime; + u32 ICLtime; + + /* Get the IC-Clk setting first for the following process*/ +#ifdef CONFIG_FPGA + u32 IcClk = SYSTEM_CLK/1000000; +#else + u32 IcClk; + u32 ClkSELTmp = 0; + u32 CpuClkTmp = 0; + + #if defined(CONFIG_CHIP_A_CUT) + CpuClkTmp = StartupHalGetCpuClk(); + #elif (defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)) + CpuClkTmp = HalGetCpuClk(); + #endif + + DBG_I2C_INFO("%s, CPU Clk:%x\n",__func__, CpuClkTmp); + + ClkSELTmp = HAL_READ32(PERI_ON_BASE, REG_PESOC_CLK_SEL); + ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3))); + HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp); + IcClk = (CpuClkTmp/1000000)>>1; + +#if 0 + if ((I2CClk > 0) && (I2CClk <= 400)) { + ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3))); + HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp); + IcClk = ClkSELTmp/1000000; /*actually it's 12.5MHz*/ + } + else { + ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3))); + HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp); + IcClk = 100; + } +#endif +#endif + + switch (SpdMd) + { + case I2C_SS_MODE: + { + ICHtime = ((1000000/I2CClk)*I2C_SS_MIN_SCL_HTIME)/(I2C_SS_MIN_SCL_HTIME+I2C_SS_MIN_SCL_LTIME); + ICLtime = ((1000000/I2CClk)*I2C_SS_MIN_SCL_LTIME)/(I2C_SS_MIN_SCL_HTIME+I2C_SS_MIN_SCL_LTIME); + + ICHLcnt = (ICHtime * IcClk)/1000; + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT,ICHLcnt); + + + DBG_I2C_INFO("IC_SS_SCL_HCNT%d[%2x]: %x\n", I2CIdx, + REG_DW_I2C_IC_SS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT)); + + + ICHLcnt = (ICLtime * IcClk)/1000; + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT,ICHLcnt); + + + DBG_I2C_INFO("IC_SS_SCL_LCNT%d[%2x]: %x\n", I2CIdx, + REG_DW_I2C_IC_SS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT)); + + break; + } + + case I2C_FS_MODE: + { + ICHtime = ((1000000/I2CClk)*I2C_FS_MIN_SCL_HTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME); + ICLtime = ((1000000/I2CClk)*I2C_FS_MIN_SCL_LTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME); + + ICHLcnt = (ICHtime * IcClk)/1000; + if (ICHLcnt>4)/*this part is according to the fine-tune result*/ + ICHLcnt -= 4; + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT,ICHLcnt); + + + DBG_I2C_INFO("IC_FS_SCL_HCNT%d[%2x]: %x\n", I2CIdx, + REG_DW_I2C_IC_FS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT)); + + + ICHLcnt = (ICLtime * IcClk)/1000; + if (ICHLcnt>3)/*this part is according to the fine-tune result*/ + ICHLcnt -= 3; + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT,ICHLcnt); + + + DBG_I2C_INFO("IC_FS_SCL_LCNT%d[%2x]: %x\n", I2CIdx, + REG_DW_I2C_IC_FS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT)); + + break; + } + + case I2C_HS_MODE: + { + ICHLcnt = 400; + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT,ICHLcnt); + + ICHLcnt = 470; + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT,ICHLcnt); + + ICHLcnt = 60; + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT,ICHLcnt); + + ICHLcnt = 130; + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT,ICHLcnt); + + ICHtime = ((1000000/I2CClk)*I2C_HS_MIN_SCL_HTIME_100)/(I2C_HS_MIN_SCL_HTIME_100+I2C_HS_MIN_SCL_LTIME_100); + ICLtime = ((1000000/I2CClk)*I2C_HS_MIN_SCL_LTIME_100)/(I2C_HS_MIN_SCL_HTIME_100+I2C_HS_MIN_SCL_LTIME_100); + + + DBG_I2C_INFO("ICHtime:%x\n",ICHtime); + DBG_I2C_INFO("ICLtime:%x\n",ICLtime); + + + ICHLcnt = (ICHtime * IcClk)/1000; + if (ICHLcnt>8)/*this part is according to the fine-tune result*/ + ICHLcnt -= 3; + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_HS_SCL_HCNT,ICHLcnt); + + + DBG_I2C_INFO("IC_HS_SCL_HCNT%d[%2x]: %x\n", I2CIdx, + REG_DW_I2C_IC_HS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_HS_SCL_HCNT)); + + + ICHLcnt = (ICLtime * IcClk)/1000; + if (ICHLcnt>6)/*this part is according to the fine-tune result*/ + ICHLcnt -= 6; + HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_HS_SCL_LCNT,ICHLcnt); + + + DBG_I2C_INFO("IC_HS_SCL_LCNT%d[%2x]: %x\n", I2CIdx, + REG_DW_I2C_IC_HS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_HS_SCL_LCNT)); + + + break; + } + + default: + break; + } + + return HAL_OK; +} +#endif \ No newline at end of file diff --git a/lib/fwlib/rtl8195a/src/rtl8195a_i2s.c b/lib/fwlib/rtl8195a/src/rtl8195a_i2s.c new file mode 100644 index 0000000..553934a --- /dev/null +++ b/lib/fwlib/rtl8195a/src/rtl8195a_i2s.c @@ -0,0 +1,395 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "rtl8195a.h" +#include "rtl8195a_i2s.h" +#include "hal_i2s.h" + +extern void * +_memset( void *s, int c, SIZE_T n ); + +RTK_STATUS +HalI2SInitRtl8195a_Patch( + IN VOID *Data +) +{ + PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data; + + u8 I2SIdx; + //u8 I2SEn; + u8 I2SMaster; + u8 I2SWordLen; + u8 I2SChNum; + u8 I2SPageNum; + u16 I2SPageSize; + u16 I2SRate; + u32 I2STxIntrMSK; + u32 I2SRxIntrMSK; + u8 I2STRxAct; + u8 *I2STxData; + u8 *I2SRxData; + + u32 Tmp; + + I2SIdx = pHalI2SInitData->I2SIdx; + //I2SEn = pHalI2SInitData->I2SEn; + I2SMaster = pHalI2SInitData->I2SMaster; + I2SWordLen = pHalI2SInitData->I2SWordLen; + I2SChNum = pHalI2SInitData->I2SChNum; + I2SPageNum = pHalI2SInitData->I2SPageNum; + I2SPageSize = pHalI2SInitData->I2SPageSize; + I2SRate = pHalI2SInitData->I2SRate; + I2STRxAct = pHalI2SInitData->I2STRxAct; + I2STxData = pHalI2SInitData->I2STxData; + I2SRxData = pHalI2SInitData->I2SRxData; + + + /* Disable the I2S first, and reset to default */ + HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) | + BIT_CTRL_CTLX_I2S_SW_RSTN(1)); + HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) | + BIT_CTRL_CTLX_I2S_SW_RSTN(0)); + HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) | + BIT_CTRL_CTLX_I2S_SW_RSTN(1)); + + Tmp = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL); + Tmp |= BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(1); + + if (I2SRate&0x10) + { + Tmp |= BIT_CTRL_CTLX_I2S_CLK_SRC(1); + } + + Tmp |= (BIT_CTRL_CTLX_I2S_WL(I2SWordLen) | BIT_CTRL_CTLX_I2S_CH_NUM(I2SChNum) | + BIT_CTRL_CTLX_I2S_SLAVE_MODE(I2SMaster) | BIT_CTRL_CTLX_I2S_TRX_ACT(I2STRxAct)); + /* set 44.1khz clock source, word length, channel number, master or slave, trx act */ + HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, Tmp); + + Tmp = BIT_CTRL_SETTING_I2S_PAGE_SZ(I2SPageSize) | BIT_CTRL_SETTING_I2S_PAGE_NUM(I2SPageNum) | + BIT_CTRL_SETTING_I2S_SAMPLE_RATE(I2SRate); + /* set page size, page number, sample rate */ + HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, Tmp); + + /* need tx rx buffer? need rx page own bit */ + if (I2STxData != NULL) { + HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (u32)I2STxData); + } + + if (I2SRxData != NULL) { + HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (u32)I2SRxData); + } + + pHalI2SInitData->I2STxIdx = 0; + pHalI2SInitData->I2SRxIdx = 0; + pHalI2SInitData->I2SHWTxIdx = 0; + pHalI2SInitData->I2SHWRxIdx = 0; + /* I2S Clear all interrupts first */ + HalI2SClrAllIntrRtl8195a(pHalI2SInitData); + + /* I2S Disable all interrupts first */ + I2STxIntrMSK = pHalI2SInitData->I2STxIntrMSK; + I2SRxIntrMSK = pHalI2SInitData->I2SRxIntrMSK; + pHalI2SInitData->I2STxIntrMSK = 0; + pHalI2SInitData->I2SRxIntrMSK = 0; + HalI2SIntrCtrlRtl8195a(pHalI2SInitData); + pHalI2SInitData->I2STxIntrMSK = I2STxIntrMSK; + pHalI2SInitData->I2SRxIntrMSK = I2SRxIntrMSK; + + return _EXIT_SUCCESS; +} + +RTK_STATUS +HalI2SSetRateRtl8195a( + IN VOID *Data +) +{ + PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data; + u8 I2SIdx; + u32 reg_value; + + I2SIdx = pHalI2SInitData->I2SIdx; + + reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL); + reg_value &= ~(BIT_MASK_CTLX_I2S_CLK_SRC << BIT_SHIFT_CTLX_I2S_CLK_SRC); + if (pHalI2SInitData->I2SRate&0x10) + { + reg_value |= BIT_CTRL_CTLX_I2S_CLK_SRC(1); + } + HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value); + + reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING); + reg_value &= ~(BIT_MASK_SETTING_I2S_SAMPLE_RATE << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE); + reg_value |= BIT_CTRL_SETTING_I2S_SAMPLE_RATE(pHalI2SInitData->I2SRate); + HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value); + + return _EXIT_SUCCESS; +} + +RTK_STATUS +HalI2SSetWordLenRtl8195a( + IN VOID *Data +) +{ + PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data; + u8 I2SIdx; + u32 reg_value; + + I2SIdx = pHalI2SInitData->I2SIdx; + reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL); + reg_value &= ~(BIT_MASK_CTLX_I2S_WL << BIT_SHIFT_CTLX_I2S_WL); + reg_value |= BIT_CTRL_CTLX_I2S_WL(pHalI2SInitData->I2SWordLen); + HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value); + + return _EXIT_SUCCESS; +} + +RTK_STATUS +HalI2SSetChNumRtl8195a( + IN VOID *Data +) +{ + PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data; + u8 I2SIdx; + u32 reg_value; + + I2SIdx = pHalI2SInitData->I2SIdx; + reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL); + reg_value &= ~(BIT_MASK_CTLX_I2S_CH_NUM << BIT_SHIFT_CTLX_I2S_CH_NUM); + reg_value |= BIT_CTRL_CTLX_I2S_CH_NUM(pHalI2SInitData->I2SChNum); + HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value); + + return _EXIT_SUCCESS; +} + +RTK_STATUS +HalI2SSetPageNumRtl8195a( + IN VOID *Data +) +{ + PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data; + u8 I2SIdx; + u32 reg_value; + + I2SIdx = pHalI2SInitData->I2SIdx; + + reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING); + reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM); + reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum); + HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value); + + return _EXIT_SUCCESS; +} + +RTK_STATUS +HalI2SSetPageSizeRtl8195a( + IN VOID *Data +) +{ + PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data; + u8 I2SIdx; + u32 reg_value; + + I2SIdx = pHalI2SInitData->I2SIdx; + + reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING); + reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ); + reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize); + HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value); + + return _EXIT_SUCCESS; +} + +RTK_STATUS +HalI2SSetDirectionRtl8195a( + IN VOID *Data +) +{ + PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data; + u8 I2SIdx; + u32 reg_value; + + I2SIdx = pHalI2SInitData->I2SIdx; + + reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL); + reg_value &= ~(BIT_MASK_CTLX_I2S_TRX_ACT << BIT_SHIFT_CTLX_I2S_TRX_ACT); + reg_value |= BIT_CTRL_CTLX_I2S_TRX_ACT(pHalI2SInitData->I2STRxAct); + HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value); + + return _EXIT_SUCCESS; +} + +RTK_STATUS +HalI2SSetDMABufRtl8195a( + IN VOID *Data +) +{ + PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data; + u8 I2SIdx; + u32 reg_value; + u32 page_num; + + I2SIdx = pHalI2SInitData->I2SIdx; + + reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING); + reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ); + reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM); + reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize); + reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum); + HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value); + + page_num = pHalI2SInitData->I2SPageNum + 1; + if (pHalI2SInitData->I2STxData) { + HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2STxData); + pHalI2SInitData->I2STxIntrMSK = (1<I2STxIntrMSK = 0; + } + + if (pHalI2SInitData->I2SRxData) { + HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2SRxData); + pHalI2SInitData->I2SRxIntrMSK = (1<I2SRxIntrMSK = 0; + + } + + // According to the page number to modify the ISR mask + HalI2SIntrCtrlRtl8195a(pHalI2SInitData); + + return _EXIT_SUCCESS; +} + +u8 +HalI2SGetTxPageRtl8195a( + IN VOID *Data +) +{ + PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data; + + u8 I2SIdx; + u16 I2STxIdx = pHalI2SInitData->I2STxIdx; + u32 reg; + + I2SIdx = pHalI2SInitData->I2SIdx; + + reg = HAL_I2S_READ32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(I2STxIdx<<2)); + if ((reg & (1<<31)) == 0) { + return I2STxIdx; + } else { + return 0xFF; + } +} + +u8 +HalI2SGetRxPageRtl8195a( + IN VOID *Data +) +{ + PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data; + + u8 I2SIdx; + u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx; + u32 reg; + + I2SIdx = pHalI2SInitData->I2SIdx; + + reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2)); + if ((reg & (1<<31)) == 0) { + return I2SRxIdx; + } else { + return 0xFF; + } +} + +RTK_STATUS +HalI2SPageSendRtl8195a( + IN VOID *Data, + IN u8 PageIdx +) +{ + PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data; + u16 I2STxIdx = pHalI2SInitData->I2STxIdx; + u8 I2SPageNum = pHalI2SInitData->I2SPageNum; + u8 I2SIdx; + + if (I2STxIdx != PageIdx) { + DBG_I2S_ERR("HalI2SPageSendRtl8195a: UnExpected Page Index. TxPage=%d, Expected:%d\r\n", + PageIdx, I2STxIdx); + } + + I2SIdx = pHalI2SInitData->I2SIdx; + + HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN+4*PageIdx, 1<<31); + I2STxIdx = PageIdx+1; + if (I2STxIdx > I2SPageNum) { + I2STxIdx = 0; + } + pHalI2SInitData->I2STxIdx = I2STxIdx; + + return _EXIT_SUCCESS; +} + +RTK_STATUS +HalI2SPageRecvRtl8195a( + IN VOID *Data +) +{ + PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data; + u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx; + u8 I2SPageNum = pHalI2SInitData->I2SPageNum; + u32 reg; + u8 I2SIdx; + + I2SIdx = pHalI2SInitData->I2SIdx; + reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2)); + if ((reg & (1<<31)) != 0) { + DBG_I2S_ERR("HalI2SPageRecvRtl8195a: No Idle Rx Page\r\n"); + return _EXIT_FAILURE; + } + + HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx<<2), 1<<31); + I2SRxIdx += 1; + if (I2SRxIdx > I2SPageNum) { + I2SRxIdx = 0; + } + pHalI2SInitData->I2SRxIdx = I2SRxIdx; + + return _EXIT_SUCCESS; +} + +RTK_STATUS +HalI2SClearAllOwnBitRtl8195a( + IN VOID *Data +) +{ + PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data; + u8 I2SIdx; + u32 i; + + I2SIdx = pHalI2SInitData->I2SIdx; + + for (i=0;i<4;i++) { + HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(i<<2), 0); + HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(i<<2), 0); + } + + return _EXIT_SUCCESS; +} + +RTK_STATUS +HalI2SDMACtrlRtl8195a( + IN VOID *Data +) +{ + + return _EXIT_SUCCESS; +} + + diff --git a/lib/fwlib/rtl8195a/src/rtl8195a_mii.c b/lib/fwlib/rtl8195a/src/rtl8195a_mii.c new file mode 100644 index 0000000..4f43d03 --- /dev/null +++ b/lib/fwlib/rtl8195a/src/rtl8195a_mii.c @@ -0,0 +1,325 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "rtl8195a.h" +#include "rtl8195a_mii.h" +#include "hal_mii.h" + + + +VOID MiiIrqHandle (IN VOID *Data); + +VOID MiiIrqHandle (IN VOID *Data) { + u32 RegValue = HalMiiGmacGetInterruptStatusRtl8195a(); +#ifdef CONFIG_MII_VERIFY + extern volatile u8 isRxOK; + extern volatile u8 isTxOK; + extern volatile u8 RxIntCnt; + + +// DBG_8195A("ISR = 0x%08X\n", RegValue); + if(RegValue & GMAC_ISR_ROK) { + HalMiiGmacClearInterruptStatusRtl8195a(0x00410001); + isRxOK = 1; + RxIntCnt++; + } + + if(RegValue & GMAC_ISR_TOK_TI) { + HalMiiGmacClearInterruptStatusRtl8195a(0x00410040); + isTxOK = 1; + } +#else + +#endif +} + + +VOID +ConfigDebugPort_E4(u32 DebugSelect) { + u32 RegValue; + + + RegValue = HAL_MII_READ32(REG_RTL_MII_CCR); + RegValue |= DebugSelect << 2; + HAL_MII_WRITE32(REG_RTL_MII_CCR, RegValue); +} + + +/** + * MII Initialize. + * + * MII Initialize. + * + * Initialization Steps: + * I. Rtl8195A Board Configurations: + * 1. MII Function Enable & AHB mux + * + * @return runtime status value. + */ +BOOL +HalMiiGmacInitRtl8195a( + IN VOID *Data + ) +{ + u32 RegValue; + + + /* 1. enable MII Pinmux & disable SDIO Host/Device mode Pinmux */ + RegValue = HAL_READ32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL); + RegValue |= BIT24; + RegValue &= ~(BIT0 | BIT1); // Important! + HAL_WRITE32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL, RegValue); + + /* 2. enable MII IP block (214, 12) */ + RegValue = HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN); + RegValue |= BIT12; + HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, RegValue); + + /* 3. Lexra2AHB Function Enable (304, 11) */ + RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_SOC_CTRL); + RegValue |= BIT11; + HAL_WRITE32(PERI_ON_BASE, REG_PESOC_SOC_CTRL, RegValue); + + /* 4. enable MII bus clock (240, 24|25) */ + RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0); + RegValue |= (BIT24 | BIT25); + HAL_WRITE32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0, RegValue); + + /* 5. */ + RegValue = HAL_READ32(SYSTEM_CTRL_BASE, 0x74) & 0xFFFFC7FF; + HAL_WRITE32(SYSTEM_CTRL_BASE, 0x74, (RegValue | 0x00003000)); + + /* 6. AHB mux: select MII (214, 13) */ + RegValue = HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN); + RegValue |= BIT13; + HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, RegValue); + + /* 7. Vendor Register Clock Enable (230, 6|7) */ + RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_CLK_CTRL); + RegValue |= (BIT6 | BIT7); + HAL_WRITE32(PERI_ON_BASE, REG_PESOC_CLK_CTRL, RegValue); + + /* 8. Enable GMAC Lexra Timeout (090, 16|17|18) */ + RegValue = HAL_READ32(VENDOR_REG_BASE, 0x0090); + RegValue |= (BIT16 | BIT17 | BIT18); + HAL_WRITE32(VENDOR_REG_BASE, 0x0090, RegValue); + + /* 9. Endian Swap Control (304, 12|13) */ + RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_SOC_CTRL); + RegValue |= (BIT12 | BIT13); + HAL_WRITE32(PERI_ON_BASE, REG_PESOC_SOC_CTRL, RegValue); + + return _TRUE; +} + + +BOOL +HalMiiInitRtl8195a( + IN VOID *Data + ) +{ + return _TRUE; +} + + +BOOL +HalMiiGmacResetRtl8195a( + IN VOID *Data + ) +{ + HAL_MII_WRITE32(REG_RTL_MII_CR, (HAL_MII_READ32(REG_RTL_MII_CR) | BIT0)); + + return _TRUE; +} + + +BOOL +HalMiiGmacEnablePhyModeRtl8195a( + IN VOID *Data + ) +{ + return _TRUE; +} + + +u32 +HalMiiGmacXmitRtl8195a( + IN VOID *Data + ) +{ + return 0; +} + + +VOID +HalMiiGmacCleanTxRingRtl8195a( + IN VOID *Data + ) +{ +} + + +VOID +HalMiiGmacFillTxInfoRtl8195a( + IN VOID *Data + ) +{ + PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data; + PTX_INFO pTx_Info = pMiiAdapter->pTx_Info; + VOID* TxBuffer = pMiiAdapter->TxBuffer; + + + pTx_Info->opts1.dw = 0xBC8001FE; + /* pTx_Info->opts1.dw = 0xBC800080; // size: 128 */ + + pTx_Info->addr = (u32)TxBuffer; + pTx_Info->opts2.dw = 0x0400279F; + pTx_Info->opts3.dw = 0x00000000; + /* pTx_Info->opts4.dw = 0x57800000; */ + pTx_Info->opts4.dw = 0x1FE00000; + + HAL_MII_WRITE32(REG_RTL_MII_TXFDP1, pTx_Info); +} + + +VOID +HalMiiGmacFillRxInfoRtl8195a( + IN VOID *Data + ) +{ + PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data; + PRX_INFO pRx_Info = pMiiAdapter->pRx_Info; + VOID* RxBuffer = pMiiAdapter->RxBuffer; + + + /* pRx_Info->opts1.dw = 0x80000200; //Data Length: 4095(FFF), 512(200) */ + pRx_Info->opts1.dw = 0x800001FC; //Data Length: 4095(FFF), 512(200) + /* pRx_Info->opts1.dw = 0x8000007F; */ + + pRx_Info->addr = (u32)RxBuffer; + pRx_Info->opts2.dw = 0x00000000; + pRx_Info->opts3.dw = 0x00000000; + + HAL_MII_WRITE32(REG_RTL_MII_RXFDP1, pRx_Info); +} + + +VOID +HalMiiGmacTxRtl8195a( + IN VOID *Data + ) +{ + u32 RegValue; + + + RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD); + RegValue |= BIT_IOCMD_TXENABLE(1); + HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue); + + RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD); + RegValue |= BIT_IOCMD_FIRST_DMATX_ENABLE(1); + HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue); +} + + +VOID +HalMiiGmacRxRtl8195a( + IN VOID *Data + ) +{ + u32 RegValue; + + + RegValue = HAL_MII_READ32(REG_RTL_MII_TCR); + + HAL_MII_WRITE32(REG_RTL_MII_TCR, 0x00000D00); // loopback R2T mode + + RegValue = HAL_MII_READ32(REG_RTL_MII_RCR); + HAL_MII_WRITE32(REG_RTL_MII_RCR, 0x0000007F); + + RegValue = HAL_MII_READ32(REG_RTL_MII_ETNRXCPU1); + HAL_MII_WRITE32(REG_RTL_MII_ETNRXCPU1, 0x1F0A0F00); + + RegValue = HAL_MII_READ32(REG_RTL_MII_RX_PSE1); + HAL_MII_WRITE32(REG_RTL_MII_RX_PSE1, 0x00000022); + + RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1); + RegValue |= BIT_IOCMD1_FIRST_DMARX_ENABLE(1); + HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, RegValue); + + RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD); + RegValue |= BIT_IOCMD_RXENABLE(1); + HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue); +} + + +VOID +HalMiiGmacSetDefaultEthIoCmdRtl8195a( + IN VOID *Data + ) +{ + u32 RegValue; + + + RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD); + HAL_MII_WRITE32(REG_RTL_MII_IOCMD, CMD_CONFIG); + + RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1); + HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, CMD1_CONFIG); + + //2014-04-29 yclin (disable 0x40051438[27] r_en_precise_dma) { + RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1); + RegValue = RegValue & 0xF7FFFFFF; + HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, RegValue); + // } +} + + +VOID +HalMiiGmacInitIrqRtl8195a( + IN VOID *Data + ) +{ + IRQ_HANDLE MiiIrqHandle_Master; + PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data; + + + MiiIrqHandle_Master.Data = (u32) (pMiiAdapter); + MiiIrqHandle_Master.IrqNum = GMAC_IRQ; + MiiIrqHandle_Master.IrqFun = (IRQ_FUN) MiiIrqHandle; + MiiIrqHandle_Master.Priority = 0; + InterruptRegister(&MiiIrqHandle_Master); + InterruptEn(&MiiIrqHandle_Master); +} + + +u32 +HalMiiGmacGetInterruptStatusRtl8195a( + VOID + ) +{ + u32 RegValue; + + + RegValue = HAL_MII_READ32(REG_RTL_MII_IMRISR); + + return RegValue; +} + + +VOID +HalMiiGmacClearInterruptStatusRtl8195a( + u32 IsrStatus + ) +{ + HAL_MII_WRITE32(REG_RTL_MII_IMRISR, IsrStatus); +} + + diff --git a/lib/fwlib/rtl8195a/src/rtl8195a_nfc.c b/lib/fwlib/rtl8195a/src/rtl8195a_nfc.c new file mode 100644 index 0000000..875e51e --- /dev/null +++ b/lib/fwlib/rtl8195a/src/rtl8195a_nfc.c @@ -0,0 +1,1921 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#include "rtl8195a.h" + +//#include "autoconf.h" +//#include "diag.h" +//#include "hal_peri_on.h" +#include "rtl8195a_nfc.h" +#include "osdep_api.h" +//#include "hal_nfc.h" +//#include "rtl8195a_peri_on.h" +//#include "rtl8195a_sys_on.h" +//#include "hal_platform.h" + +#ifdef CONFIG_NFC_NORMAL + +extern void nfc_tagwrite_callback(PNFC_ADAPTER pNFCAdp, uint32_t page, uint32_t wr_data); +extern void nfc_event_callback(PNFC_ADAPTER pNFCAdp, uint32_t event); +extern void nfc_tagread_callback(PNFC_ADAPTER pNFCAdp, uint32_t page); +extern void nfc_cache_read_callback(PNFC_ADAPTER pNFCAdp, uint32_t start_pg, uint32_t *pbuf); + +extern VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara); +extern VOID SpicSectorEraseFlashRtl8195A(u32 Address); +extern VOID SpicWaitBusyDoneRtl8195A(VOID); +extern VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara); + + +VOID WriteA2NMailbox(IN VOID *pNFCAdapte); +VOID A2NWriteInQueue(IN VOID *pNFCAdapte, IN VOID *pBuff); +VOID A2NWriteDeQueue(IN VOID *pNFCAdapte); +VOID N2AReadTag(IN VOID *pNFCAdapte, IN u8 N2ARPage); +u32 HalNFCRead32(IN u32 Addr); +VOID HalNFCWrite32(IN u32 Addr, IN u32 Data); +VOID N2AWriteTag(IN VOID *pNFCAdapte, IN u8 N2AWPage); +VOID N2AReadCatch(IN VOID *pNFCAdapte, IN u8 N2ACatchRPage); +VOID NFCReaderPresent(IN VOID *pNFCAdapte, IN u8 State); +VOID N2AMailboxState(IN VOID *pNFCAdapte, IN u8 State, IN u8 Seq); +VOID NFC25MClkReq(IN VOID *pNFCAdapte, IN u8 OP, IN u8 Seq); + +//demo +u8 NFCFWIMEM[]={ +0x01, 0x10, 0x00, 0x65, 0x00, 0x68, 0xA8, 0xB9, 0x00, 0x65, 0x40, 0xF0, 0x20, 0x69, 0x89, 0xB9, +0x00, 0x65, 0x13, 0xF7, 0x20, 0x6A, 0x80, 0xF0, 0x08, 0x4A, 0x7E, 0xF0, 0x2D, 0x68, 0x7E, 0xF0, +0x0C, 0x48, 0x00, 0xDA, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x13, 0xF7, 0x20, 0x6A, +0x08, 0x4A, 0x00, 0x9A, 0x00, 0x65, 0x00, 0xF0, 0x20, 0x69, 0xFF, 0xF4, 0x1F, 0x49, 0x2C, 0xE8, +0x00, 0xDA, 0x00, 0x65, 0x13, 0xF7, 0x20, 0x6A, 0x80, 0xF0, 0x04, 0x4A, 0x00, 0x68, 0x00, 0xDA, +0x00, 0x65, 0x13, 0xF7, 0x20, 0x6A, 0x80, 0xF0, 0x00, 0x4A, 0x02, 0xF0, 0x20, 0x68, 0xFF, 0x48, +0x00, 0xDA, 0x00, 0x65, 0x10, 0xF0, 0x20, 0x68, 0x00, 0xF4, 0x01, 0x48, 0x00, 0xE8, 0x00, 0x65, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0xDF, 0xF7, 0x04, 0x63, 0x0E, 0xD2, 0x0D, 0xD3, 0x0C, 0xD0, 0x0B, 0xD1, 0x0A, 0xD4, 0x09, 0xD5, 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0x50, 0x00, 0x00, 0x9F, +0xF2, 0x00, 0x00, 0xA0, 0x08, 0x00, 0x00, 0x9F, 0x10, 0x00, 0x00, 0x9F, 0x02, 0x01, 0x70, 0x00, +0x01, 0x01, 0x70, 0x00, 0x88, 0x00, 0x00, 0x9F, 0x6C, 0xB0, 0x6C, 0xB0, 0x24, 0x01, 0x00, 0x94, +0x00, 0x00, 0x20, 0x00, 0x2C, 0x00, 0x00, 0x94, 0x28, 0x00, 0x00, 0x94, 0x68, 0x01, 0x00, 0x94, +0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0xFE, 0xFF, 0x02, 0x00, 0x6C, 0x00, 0x00, 0x94, +0x00, 0x00, 0x02, 0x00, 0xFF, 0xFF, 0xFD, 0xFF, 0x20, 0x01, 0x00, 0x94, 0x70, 0x00, 0x00, 0x94, +0x00, 0xD0, 0x80, 0x3D, 0x00, 0x90, 0x80, 0x3D, 0x5C, 0x00, 0x00, 0x9F, 0xFF, 0xFF, 0xFF, 0x00, +0x58, 0x00, 0x00, 0x9F, 0x25, 0x00, 0x01, 0x00, 0x24, 0x00, 0x01, 0x00, 0x68, 0x00, 0x00, 0x9F, +0x25, 0x64, 0x2E, 0x00, 0x25, 0x68, 0x68, 0x58, 0x3A, 0x00, 0x00, 0x00, 0x30, 0x31, 0x32, 0x33, +0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x00, 0x00, 0x00, 0x00, +0x67, 0x66, 0x66, 0x66, +}; + + +//NFC_ADAPTER NFCAdapter; +IRQ_FUN LpPeriIrqFunTable[32]; +u32 LpPeriIrqDataTable[32]; + +VOID +WriteA2NMailbox( + IN VOID *pNFCAdapte +) +{ + PNFC_ADAPTER pNFCAdp = (PNFC_ADAPTER) pNFCAdapte; + u8 i = 0; + u32 RegTemp; + + if (!(pNFCAdp->A2NMAILQ[pNFCAdp->A2NWQRIdx].Response)) { + pNFCAdp->A2NMAILQ[pNFCAdp->A2NWQRIdx].Content[0] = + (pNFCAdp->A2NMAILQ[pNFCAdp->A2NWQRIdx].Content[0]|(pNFCAdp->A2NSeq << 8)); + pNFCAdp->A2NSeq++; + } + + for(i = 0; i < pNFCAdp->A2NMAILQ[pNFCAdp->A2NWQRIdx].Length; i++) { + HalDelayUs(30); + HAL_WRITE32(NFC_INTERFACE_BASE, 0x10, pNFCAdp->A2NMAILQ[pNFCAdp->A2NWQRIdx].Content[i]); + } + + HalDelayUs(30); + RegTemp = HAL_READ32(NFC_INTERFACE_BASE,0x24)|BIT1; + HAL_WRITE32(NFC_INTERFACE_BASE, 0x24, RegTemp); + + RegTemp = (HAL_READ32(NFC_INTERFACE_BASE,0x24)&(~BIT1)); + HAL_WRITE32(NFC_INTERFACE_BASE, 0x24, RegTemp); +} + +VOID +A2NWriteInQueue( + IN VOID *pNFCAdapte, + IN VOID *pBuff +) +{ + PNFC_ADAPTER pNFCAdp = (PNFC_ADAPTER) pNFCAdapte; + PA2N_MAILBOX_Q pA2NWData = (PA2N_MAILBOX_Q) pBuff; + u8 Idx; + + //Q full handle + if ((pNFCAdp->A2NWQWIdx == (pNFCAdp->A2NWQRIdx - 1))|| + ((pNFCAdp->A2NWQRIdx == 0)&&(pNFCAdp->A2NWQWIdx == N2A_Q_LENGTH - 1))){ + + DBG_8195A("A2N write Mailbox Queue full !!\n"); + } + + for (Idx = 0; Idx < pA2NWData->Length; Idx++) { + pNFCAdp->A2NMAILQ[pNFCAdp->A2NWQWIdx].Content[Idx] = pA2NWData->Content[Idx]; + } + + pNFCAdp->A2NMAILQ[pNFCAdp->A2NWQWIdx].Length = pA2NWData->Length; + pNFCAdp->A2NMAILQ[pNFCAdp->A2NWQWIdx].Response = pA2NWData->Response; + pNFCAdp->A2NWQWIdx++; + + if (pNFCAdp->A2NWQWIdx == N2A_Q_LENGTH){ + pNFCAdp->A2NWQWIdx = 0; + } + + //check qu and enable task + if (pNFCAdp->A2NWQWIdx != pNFCAdp->A2NWQRIdx){ + pNFCAdp->A2NWMailBox = TRUE; + RtlUpSema(&(pNFCAdp->VeriSema)); + } + + + #if 0 + { + u8 i = 0; + u8 j = 0; + DBG_8195A("A2N idx = 0x%x \n", pNFCAdp->A2NWMailBox); + DBG_8195A("A2N write R idx = 0x%x \n", pNFCAdp->A2NWQRIdx); + DBG_8195A("A2N write W idx = 0x%x \n", pNFCAdp->A2NWQWIdx); + + for(i = 0;iA2NWQWIdx;i++) { + + DBG_8195A("A2N write queue %d, length = 0x%x \n", i, pNFCAdp->A2NMAILQ[i].Length); + DBG_8195A("A2N write queue %d, response = 0x%x \n", i, pNFCAdp->A2NMAILQ[i].Response); + for(j = 0;j < 5; j++) { + DBG_8195A("A2N write queue %d, data = 0x%x \n", i, pNFCAdp->A2NMAILQ[i].Content[j]); + } + } + } + #endif +} + +VOID +A2NWriteDeQueue( + IN VOID *pNFCAdapte +) +{ + PNFC_ADAPTER pNFCAdp = (PNFC_ADAPTER) pNFCAdapte; + u32 TimeIdx = 0; + + while(((HAL_READ32(NFC_INTERFACE_BASE, 0x14)>>1) & 0xf)!= 0){ + DBG_8195A("A2N Mailbox W MISC 0x%08x\n", ((HAL_READ32(NFC_INTERFACE_BASE, 0x14)>>1) & 0xf)); + HalDelayUs(30); + TimeIdx++; + if (TimeIdx > 10000){ + + DBG_8195A("A2N Mailbox write timeout\n"); + + //check qu and enable task + if (pNFCAdp->A2NWQWIdx != pNFCAdp->A2NWQRIdx){ + pNFCAdp->A2NWMailBox = TRUE; + RtlUpSema(&(pNFCAdp->VeriSema)); + } + return; + } + }; + + WriteA2NMailbox(pNFCAdapte); + + pNFCAdp->A2NWQRIdx++; + if (pNFCAdp->A2NWQRIdx == N2A_Q_LENGTH) { + pNFCAdp->A2NWQRIdx = 0; + } + + //check qu and enable task + if (pNFCAdp->A2NWQWIdx != pNFCAdp->A2NWQRIdx){ + pNFCAdp->A2NWMailBox = TRUE; + RtlUpSema(&(pNFCAdp->VeriSema)); + } + else { + pNFCAdp->A2NWMailBox = FALSE; + } +} + + +//cmd 0 +VOID +N2AReadTag( + IN VOID *pNFCAdapte, + IN u8 N2ARPage +) +{ + PNFC_ADAPTER pNFCAdp = (PNFC_ADAPTER)pNFCAdapte; + + nfc_tagread_callback (pNFCAdp, N2ARPage); +} + +VOID +A2NWriteCatch( + IN VOID *pNFCAdapte, + IN u8 N2AWPage, + IN u8 Length, + IN u32 *WData +) +{ + PNFC_ADAPTER pNFCAdp = (PNFC_ADAPTER)pNFCAdapte; + u8 Idx; + A2N_MAILBOX_Q DataTemp; + + DataTemp.Length = Length+1; + DataTemp.Response = 0; + DataTemp.Content[0] = (CATCH_WRITE|(DataTemp.Length<<5)|(N2AWPage<<16)); + for (Idx = 0; Idx < Length; Idx++) { + DataTemp.Content[Idx+1] = WData[Idx]; + } + A2NWriteInQueue(pNFCAdp, &DataTemp); +} + + +VOID +A2NReadCatch( + IN VOID *pNFCAdapte, + IN u8 A2NRPage +) +{ + A2N_MAILBOX_Q DataTemp; + + DataTemp.Length = 1; + DataTemp.Response = 0; + DataTemp.Content[0] = (CATCH_READ|(DataTemp.Length<<5)|(A2NRPage<<16)); + + A2NWriteInQueue((PNFC_ADAPTER)pNFCAdapte, &DataTemp); +} + +//cmd 1 +VOID +N2AWriteTag( + IN VOID *pNFCAdapte, + IN u8 N2AWPage +) +{ + PNFC_ADAPTER pNFCAdp = (PNFC_ADAPTER)pNFCAdapte; + u32 wr_data; + + wr_data = HAL_READ32(NFC_INTERFACE_BASE, 0x18); + nfc_tagwrite_callback(pNFCAdp, N2AWPage, wr_data); +} + + +//cmd 3 +VOID +N2AReadCatch( + IN VOID *pNFCAdapte, + IN u8 N2ACatchRPage +) +{ + PNFC_ADAPTER pNFCAdp = (PNFC_ADAPTER)pNFCAdapte; + u32 TagBuf[4]; + + TagBuf[0] = HAL_READ32(NFC_INTERFACE_BASE, 0x18); + TagBuf[1] = HAL_READ32(NFC_INTERFACE_BASE, 0x18); + TagBuf[2] = HAL_READ32(NFC_INTERFACE_BASE, 0x18); + TagBuf[3] = HAL_READ32(NFC_INTERFACE_BASE, 0x18); + + nfc_cache_read_callback(pNFCAdp, N2ACatchRPage, TagBuf); +} + +//cmd 4 +VOID +NFCReaderPresent( + IN VOID *pNFCAdapte, + IN u8 State +) +{ + PNFC_ADAPTER pNFCAdp = (PNFC_ADAPTER)pNFCAdapte; + + if (State) { + DBG_8195A("NFC Reader Present\n"); + + //call app + nfc_event_callback(pNFCAdp, NFC_HAL_READER_PRESENT); + } +} + + +//cmd 5 +VOID +N2AMailboxState( + IN VOID *pNFCAdapte, + IN u8 State, + IN u8 Seq +) +{ + A2N_MAILBOX_Q MailData; + PNFC_ADAPTER pNFCAdp = (PNFC_ADAPTER)pNFCAdapte; + + pNFCAdp->N2ABoxOpen = State; + DBG_8195A("N2A Mailbox State = %d\n", pNFCAdp->N2ABoxOpen); + + if (State) { + MailData.Length = 1; + MailData.Response = 1; + MailData.Content[0] = (CONFIRM_N2A_BOX_STATE)|(0x1<<5)|((Seq|BIT7)<<8)|(ON<<16); + //WriteA2NMailbox(1, &MailData, 1); + A2NWriteInQueue(pNFCAdp, &MailData); + } +} + + +//cmd 6 +VOID +NFC25MClkReq( + IN VOID *pNFCAdapte, + IN u8 OP, + IN u8 Seq +) +{ + PNFC_ADAPTER pNFCAdp = (PNFC_ADAPTER)pNFCAdapte; + A2N_MAILBOX_Q MailData; + u32 RegTemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1); + if (OP) { + RegTemp = ((RegTemp & 0xFFFFC7FF)|(BIT_SYS_SYSPLL_CKSDR_EN|BIT_SYS_SYSPLL_CKSDR_DIV(2))); + } + else { + RegTemp = RegTemp & 0xFFFFC7FF; + } + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, RegTemp); + + //write mailbox + MailData.Length = 1; + MailData.Response = 1; + MailData.Content[0] = (EXT_CLK_RSP)|(0x1<<5)|((Seq|BIT7)<<8)|(ON<<16); + //WriteA2NMailbox(pNFCAdp, &MailData); + A2NWriteInQueue(pNFCAdp, &MailData); +} + + +VOID +NFCRoutine( + IN VOID *pNFCAdapte +) +{ + u32 N2ARData, N2AMISC; + u8 N2ARB2; + u8 Seq; + PNFC_ADAPTER pNFCAdp = (PNFC_ADAPTER)pNFCAdapte; + + //N2A MEM DATA + if (pNFCAdp->NFCIsr & (BIT0|BIT6)) { + pNFCAdp->NFCIsr &= ~(BIT6|BIT0); + + N2AMISC = ((HAL_READ32(NFC_INTERFACE_BASE, 0x1c)>>1)&0xf); + //DBG_8195A("NFC 0x1C = 0x%x \n", N2AMISC); + while (N2AMISC != 0){ + + N2ARData = HAL_READ32(NFC_INTERFACE_BASE, 0x18); + N2ARB2 = ((u8)(N2ARData>>16)); + Seq = (u8)(N2ARData>>8); + //DBG_8195A("NFC 0x18 = 0x%x \n", N2ARData); + + switch(N2ARData & 0x1F) { + case TAG_READ: + //get data + N2AReadTag(pNFCAdapte, N2ARB2); + //call app + + break; + case TAG_WRITE: + //get data + N2AWriteTag(pNFCAdapte, N2ARB2); + //call app + + break; + case CATCH_READ_DATA: + //get data + N2AReadCatch(pNFCAdapte, N2ARB2); + //call app + + break; + case NFC_R_PRESENT: + NFCReaderPresent(pNFCAdapte, N2ARB2); + break; + case N2A_MAILBOX_STATE: + N2AMailboxState(pNFCAdapte, N2ARB2, Seq); + break; + case EXT_CLK_REQ: + NFC25MClkReq(pNFCAdapte, N2ARB2, Seq); + break; + default: + break; + } + + N2AMISC = ((HAL_READ32(NFC_INTERFACE_BASE, 0x1c)>>1)&0xf); + } + } + + if(pNFCAdp->A2NWMailBox){ + A2NWriteDeQueue(pNFCAdp); + } + //enable int + //A2NWRITE32(0x68, 0xff00); +} + + +VOID +NFCTaskHandle( + IN VOID *pNFCAdapte +) +{ + PNFC_ADAPTER pNFCAdp = (PNFC_ADAPTER)pNFCAdapte; + + #if !TASK_SCHEDULER_DISABLED//#if !TASK_SCHEDULER_DISABLED(>>) + for (;;)//start of for(;;) + { + //4 waiting for start command + RtlDownSema(&(pNFCAdp->VeriSema)); + + if (pNFCAdp->TaskStop) { + break; // task stopping, break the for loop + } + NFCRoutine(pNFCAdapte); + + }//end of for(;;) + + pNFCAdp->TaskStop = 0; +#if ( INCLUDE_vTaskDelete == 1 ) + vTaskDelete(NULL); +#endif + #endif +} + +VOID +LPIrqHandle( + IN VOID *pNFCAdapte +) +{ + u32 LpIrqStatus, CheckIndex, ExactIrqStatus, TableIndex; + + //DBG_8195A("Enter ISR\n"); + + LpIrqStatus = HAL_READ32(VENDOR_REG_BASE, LP_PERI_EXT_IRQ_STATUS); + + //Save exact IRQ status + ExactIrqStatus = LpIrqStatus & + HAL_READ32(VENDOR_REG_BASE, LP_PERI_EXT_IRQ_EN); + + //Check exact IRQ function + for(CheckIndex = 0;CheckIndex<32;CheckIndex++) { + if (ExactIrqStatus & BIT_(CheckIndex)) { + TableIndex = CheckIndex; + LpPeriIrqFunTable[TableIndex]((VOID *)(LpPeriIrqDataTable[TableIndex])); + } + } + + //Clear sub-rout IRQ + HAL_WRITE32(VENDOR_REG_BASE, LP_PERI_EXT_IRQ_STATUS, LpIrqStatus); + +} + +VOID +NFCIrqHandle( + IN VOID *pNFCAdapte +) +{ + PNFC_ADAPTER pNFCAdp = (PNFC_ADAPTER)pNFCAdapte; + u32 ISR = HalNFCRead32(0x68); + pNFCAdp->NFCIsr = (((u8)((ISR&0xbf00)>>8))&((u8)ISR)); + //DBG_8195A("A2N 0x68 = 0x%x\n", ISR); + + //stop int + //ISR = ISR&0xff; + + HalNFCWrite32(0x68, ISR); + + //DBG_8195A("After clean ISR A2N 0x68 = 0x%x\n", A2NREAD32(0x68)); + RtlUpSema(&(pNFCAdp->VeriSema)); +} + +VOID HalNFCDmemInit( + IN u32 *pTagData, + IN u32 TagLen +) +{ + if (pTagData == NULL) { + return; + } + + u32 pgidx, dmemidx; + for (pgidx = 0, dmemidx = 0; pgidx> 0); + NFCFWDMEM[dmemidx++] = (u8)((pTagData[pgidx] & 0x0000FF00) >> 8); + NFCFWDMEM[dmemidx++] = (u8)((pTagData[pgidx] & 0x00FF0000) >> 16); + NFCFWDMEM[dmemidx++] = (u8)((pTagData[pgidx] & 0xFF000000) >> 24); + } +} + +VOID +HalNFCInit( + PNFC_ADAPTER pNFCAdp +) +{ + u32 Rtemp = 0; + + _memset(pNFCAdp, 0, sizeof(NFC_ADAPTER)); + + //Enable NFC clk 0x244[17:16] = 3 + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_PESOC_COM_CLK_CTRL1)|0x00030000; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_PESOC_COM_CLK_CTRL1, Rtemp); + + //Enable A33 interface + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) | 0x80000000); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //Enabel NFC and release IOS33_Ameba + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009401); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //polling ISO33_NFC 0x134 [0] = 0 + while ( (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PERI_MONITOR)&BIT0) != 0 ){}; + + //DBG_8195A("NFC Initialization Finish\n"); + + //CLK 25M + { + u32 RegTemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1); + + RegTemp = ((RegTemp & 0xFFFFC7FF)|(BIT_SYS_SYSPLL_CKSDR_EN|BIT_SYS_SYSPLL_CKSDR_DIV(2))); + //RegTemp = ((RegTemp & 0xFFFFC7FF)|BIT13|BIT12); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, RegTemp); + HAL_WRITE32(SYSTEM_CTRL_BASE, 0x244, HAL_READ32(SYSTEM_CTRL_BASE, 0x244)|BIT18); + } + + + //Init INT + { + IRQ_HANDLE NfcHandle; + NfcHandle.Data = (u32) (pNFCAdp); + NfcHandle.IrqNum = LP_EXTENSION_IRQ;//NFC_IRQ; + NfcHandle.IrqFun = (IRQ_FUN) LPIrqHandle; + NfcHandle.Priority = 3; + + InterruptRegister(&NfcHandle); + InterruptEn(&NfcHandle); + + LpPeriIrqFunTable[1] = (IRQ_FUN)((u32)NFCIrqHandle | 0x1); + + LpPeriIrqDataTable[1] = (u32)(pNFCAdp); + //level trigger + HAL_WRITE32(VENDOR_REG_BASE, LP_PERI_EXT_IRQ_MODE,0); + //enable imr + HAL_WRITE32(VENDOR_REG_BASE, LP_PERI_EXT_IRQ_EN, + (HAL_READ32(VENDOR_REG_BASE, LP_PERI_EXT_IRQ_EN) | BIT1)); + HalNFCWrite32(0x68, 0xBF00); + + } + + #if !TASK_SCHEDULER_DISABLED + { + u32 NFCTmpSts; + //create task + RtlInitSema(&(pNFCAdp->VeriSema),0); + NFCTmpSts = xTaskCreate( NFCTaskHandle, (const char *)"NFC_TASK", + ((1024*4)/sizeof(portBASE_TYPE)), (void *)pNFCAdp, 1, &(pNFCAdp->NFCTask)); + if (pdTRUE != NFCTmpSts ) { + DBG_NFC_ERR("HalNFCInit: Create Task Err(%d)!!\n", NFCTmpSts); + } + } + #endif + +} + +VOID +HalNFCDeinit( + PNFC_ADAPTER pNFCAdp +) +{ + u32 i; + u32 Rtemp = 0; + + pNFCAdp->TaskStop = 1; + RtlUpSema(&(pNFCAdp->VeriSema)); + // wait sometime for the task be stooped + for(i=0;i<1000;i++) { + if (pNFCAdp->TaskStop == 0) { + break; + } + else { + RtlMsleepOS(100); + } + } + //4 free the task semaphore + RtlFreeSema(&(pNFCAdp->VeriSema)); + _memset(pNFCAdp, 0, sizeof(NFC_ADAPTER)); + + //4 Disable NFC clk + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_PESOC_COM_CLK_CTRL1)&0xFFFCFFFF; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_PESOC_COM_CLK_CTRL1, Rtemp); + + //4 Enable A33 interface + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) | 0x80000000); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009404); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); +} + + +u32 +HalNFCRead32( + IN u32 Addr +) +{ + //byte0: test type, byte1: Base address, byte2: offset + + u32 Rtemp = 0; + u32 Idxtemp = 0; + + //full addr + HAL_WRITE32(NFC_INTERFACE_BASE, 0x0, (0x1f000000+Addr)); + //R_cmd + HAL_WRITE32(NFC_INTERFACE_BASE, 0x4, 0x2f); + #if 1 + //polling 0x4[7]=1 + while(1) { + if( (HAL_READ32(NFC_INTERFACE_BASE, 0x4)&BIT7) == 0 ){ + Idxtemp++; + if((Idxtemp)%10000 == 0) { + DBG_8195A("Idxtemp: 0x%x\n", Idxtemp); + } + if (Idxtemp > 0x0fffff) { + DBG_8195A("A2N_OCP_MISC_R_IN_WHILE: 0x%x\r\n", HAL_READ32(NFC_INTERFACE_BASE, 0x4)); + DBG_8195A("Read FAIL!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!1\r\n"); + return 0; + } + } + else { + //DBG_8195A("A2N_OCP_MISC_R_IN_WHILE: 0x%x\n", HAL_READ32(NFC_INTERFACE_BASE, 0x4)); + HAL_WRITE32(NFC_INTERFACE_BASE, 0x4, BIT7); + Rtemp = HAL_READ32(NFC_INTERFACE_BASE, 0xc); + break; + } + } + #endif + //DBG_8195A("A2N_MEM_MISC: 0x%x\n", Rtemp); + return Rtemp; +} + +VOID +HalNFCWrite32( + IN u32 Addr, + IN u32 Data +) +{ + //byte0: test type, byte1: Base address, byte2: offset, byte3:value + u32 Idxtemp = 0; + + //full addr + HAL_WRITE32(NFC_INTERFACE_BASE, 0x0, 0x1f000000+Addr); + //full data + HAL_WRITE32(NFC_INTERFACE_BASE, 0x8, Data); + //W_cmd + HAL_WRITE32(NFC_INTERFACE_BASE, 0x4, 0x1f); + + //polling 0x4[7]=1 + while(1) { + if( (HAL_READ32(NFC_INTERFACE_BASE, 0x4)&BIT7) == 0 ){ + Idxtemp++; + if((Idxtemp)%10000 == 0) { + DBG_8195A("Idxtemp: 0x%x\n", Idxtemp); + } + if (Idxtemp > 0x0fffff) { + DBG_8195A("A2N_OCP_MISC_R_IN_WHILE: 0x%x\r\n", HAL_READ32(NFC_INTERFACE_BASE, 0x4)); + DBG_8195A("write FAIL!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!1\r\n"); + return; + } + } + else { + //DBG_8195A("A2N_OCP_MISC_W_IN_WHILE: 0x%x\n", HAL_READ32(NFC_INTERFACE_BASE, 0x4)); + HAL_WRITE32(NFC_INTERFACE_BASE, 0x4, BIT7); + break; + } + } +} + +VOID +HalNFCFwFullMEM( + IN VOID *Data, + IN u32 NFCFwLength +) +{ + u32 *NFCFW; + NFCFW = (u32*) Data; + u32 Idx, NFCFwTemp, RTemp; + u8 Temp = (NFCFwLength%4); + u32 IdxTemp = ((NFCFwLength-Temp)/4); + u8 MEMTemp = 0; +// u8 MEMCnt = 0; + + u32 FWChkSum = 0; + + HalNFCWrite32(0x4C, 0x0); + + //write fw to MEM + for (Idx = 0; Idx < IdxTemp; Idx++ ) { + + NFCFwTemp = *(NFCFW+Idx); + HAL_WRITE32(NFC_INTERFACE_BASE, 0x10, NFCFwTemp); + + //cal chksum + FWChkSum ^= NFCFwTemp; + MEMTemp++; + HalDelayUs(1); + + if (MEMTemp == 8) { + + MEMTemp = 0; + + //check mem empty + while(1){ + + RTemp = HAL_READ32(NFC_INTERFACE_BASE, 0x14); +// MEMCnt = (((u8)(RTemp & 0x1e)) >> 1); + + if ( RTemp & BIT6) { + break; + } + else { + } + } + } + } + + HalDelayUs(200); + + while(1){ + RTemp = HAL_READ32(NFC_INTERFACE_BASE, 0x14); + if ( RTemp & BIT6) { + break; + } + else { + } + } + + //write chksum + HAL_WRITE32(NFC_INTERFACE_BASE, 0x10, FWChkSum); + + while(1){ + RTemp = HAL_READ32(NFC_INTERFACE_BASE, 0x14); + if ( RTemp & BIT6) { + break; + } + else { + } + } +} + + +VOID +HalNFCFwDownload( + VOID +) +{ + u32 Rtemp = 0; + + //switch free run clock from 500K to 80M + HalNFCWrite32(0x88, 0xf06cf06c); + + //2 Download NFC FW + //3 Download IMEM + //setting fw download + HalNFCWrite32(0x48, 0x1); + + //reset NFC CPU + HalNFCWrite32(0x20, 0x1234FFFF); + + //switch IMEM + HAL_WRITE32(NFC_INTERFACE_BASE, 0x14, 0); + + //write fw to MEM + HalNFCFwFullMEM(NFCFWIMEM,sizeof(NFCFWIMEM)); + HalDelayUs(100); + + Rtemp = HalNFCRead32(0x48); + if(Rtemp & BIT1) { + //DBG_8195A("NFC FW Download IMEM SUCCESS \n"); + } + else { + DBG_8195A("NFC FW Download IMEM FAIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! \n"); + return; + } + + //3 Download DMEM + //setting fw download + HalNFCWrite32(0x48, 0x1); + + //switch DMEM + HAL_WRITE32(NFC_INTERFACE_BASE, 0x14, 1); + + //write fw to MEM + HalNFCFwFullMEM(NFCFWDMEM,sizeof(NFCFWDMEM)); + + HalDelayUs(100); + Rtemp = HalNFCRead32(0x48); + if(Rtemp & BIT1) { + //DBG_8195A("NFC FW Download DMEM SUCCESS \n"); + } + else { + DBG_8195A("NFC FW Download DMEM FAIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! \n"); + return; + } + + //Reset CPU + HalNFCWrite32(0x48, 0x80); + + DBG_8195A("NFC REBOOT SUCCESS \n"); +} + +#endif //CONFIG_NFC_EN diff --git a/lib/fwlib/rtl8195a/src/rtl8195a_pcm.c b/lib/fwlib/rtl8195a/src/rtl8195a_pcm.c new file mode 100644 index 0000000..abf6b18 --- /dev/null +++ b/lib/fwlib/rtl8195a/src/rtl8195a_pcm.c @@ -0,0 +1,360 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "platform_autoconf.h" +#include "diag.h" +#include "rtl8195a_pcm.h" +#include "hal_pcm.h" + +extern void * +_memset( void *s, int c, SIZE_T n ); + +VOID +HalPcmOnOffRtl8195a ( + IN VOID *Data +) +{ + PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data; + //todo on off pcm + +} + +//default sampling rate 8khz, linear, 10ms frame size, time slot 0 , tx+rx +// master mode, enable endian swap +// Question: need local tx/rx page? +BOOL +HalPcmInitRtl8195a( + IN VOID *Data +) +{ + + PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data; + _memset((void *)pHalPcmAdapter, 0, sizeof(HAL_PCM_ADAPTER)); + + //4 1) Initial PcmChCNR03 Register + pHalPcmAdapter->PcmChCNR03.CH0MuA = 0; + pHalPcmAdapter->PcmChCNR03.CH0Band = 0; + + + //4 1) Initial PcmTSR03 Register + pHalPcmAdapter->PcmTSR03.CH0TSA = 0; + + //4 1) Initial PcmBSize03 Register + pHalPcmAdapter->PcmBSize03.CH0BSize = 39; // 40word= 8khz*0.01s*1ch*2byte/4byte + + + //4 2) Initial Ctl Register + + pHalPcmAdapter->PcmCtl.Pcm_En = 1; + pHalPcmAdapter->PcmCtl.SlaveMode = 0; + pHalPcmAdapter->PcmCtl.FsInv = 0; + pHalPcmAdapter->PcmCtl.LinearMode = 0; + pHalPcmAdapter->PcmCtl.LoopBack = 0; + pHalPcmAdapter->PcmCtl.EndianSwap = 1; + + return _TRUE; +} + + +BOOL +HalPcmSettingRtl8195a( + IN VOID *Data +) +{ + + PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data; + u8 PcmIndex = pHalPcmAdapter->PcmIndex; + u8 PcmCh = pHalPcmAdapter->PcmCh; + u32 RegCtl, RegChCNR03, RegTSR03, RegBSize03; + u32 Isr03; + + PcmCh=0; + //4 1) Check Pcm index is avaliable + if (HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03) & (BIT24|BIT25)) { + //4 Pcm index is running, stop first + DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh); + + return _FALSE; + } + + //4 2) Check if there are the pending isr + + + Isr03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_ISR03); + Isr03 &= 0xff000000; + //4 Clear Pending Isr + HAL_PCMX_WRITE32(PcmIndex, REG_PCM_ISR03, Isr03); + //} + + + //4 3) Process RegCtl + RegCtl = HAL_PCMX_READ32(PcmIndex, REG_PCM_CTL); + + //4 Clear Ctl register bits + RegCtl &= ( BIT_INV_CTLX_SLAVE_SEL & + BIT_INV_CTLX_FSINV & + BIT_INV_CTLX_PCM_EN & + BIT_INV_CTLX_LINEARMODE & + BIT_INV_CTLX_LOOP_BACK & + BIT_INV_CTLX_ENDIAN_SWAP); + + RegCtl = BIT_CTLX_SLAVE_SEL(pHalPcmAdapter->PcmCtl.SlaveMode) | + BIT_CTLX_FSINV(pHalPcmAdapter->PcmCtl.FsInv) | + BIT_CTLX_PCM_EN(pHalPcmAdapter->PcmCtl.Pcm_En) | + BIT_CTLX_LINEARMODE(pHalPcmAdapter->PcmCtl.LinearMode) | + BIT_CTLX_LOOP_BACK(pHalPcmAdapter->PcmCtl.LoopBack) | + BIT_CTLX_ENDIAN_SWAP(pHalPcmAdapter->PcmCtl.EndianSwap) | + RegCtl; + + HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CTL, RegCtl); + //4 4) Program ChCNR03 Register + + RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03); + + RegChCNR03 &= (BIT_INV_CHCNR03_CH0RE & + BIT_INV_CHCNR03_CH0TE & + BIT_INV_CHCNR03_CH0MUA & + BIT_INV_CHCNR03_CH0BAND); + + RegChCNR03 = BIT_CHCNR03_CH0RE(pHalPcmAdapter->PcmChCNR03.CH0RE) | + BIT_CHCNR03_CH0TE(pHalPcmAdapter->PcmChCNR03.CH0TE) | + BIT_CHCNR03_CH0MUA(pHalPcmAdapter->PcmChCNR03.CH0MuA) | + BIT_CHCNR03_CH0BAND(pHalPcmAdapter->PcmChCNR03.CH0Band) | + RegChCNR03; + + DBG_8195A_DMA("RegChCNR03 data:0x%x\n", RegChCNR03); + + HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03); + // time slot + RegTSR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_TSR03); + + RegTSR03 &= (BIT_INV_TSR03_CH0TSA); + RegTSR03 = BIT_TSR03_CH0TSA(pHalPcmAdapter->PcmTSR03.CH0TSA) | + RegTSR03; + + DBG_8195A_DMA("RegTSR03 data:0x%x\n", RegTSR03); + + HAL_PCMX_WRITE32(PcmIndex, REG_PCM_TSR03, RegTSR03); + + // buffer size + RegBSize03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_BSIZE03); + + RegBSize03 &= (BIT_INV_BSIZE03_CH0BSIZE); + RegBSize03 = BIT_BSIZE03_CH0BSIZE(pHalPcmAdapter->PcmBSize03.CH0BSize) | + RegBSize03; + + DBG_8195A_DMA("RegBSize03 data:0x%x\n", RegBSize03); + + HAL_PCMX_WRITE32(PcmIndex, REG_PCM_BSIZE03, RegBSize03); + + + + + return _TRUE; +} + +BOOL +HalPcmEnRtl8195a( + IN VOID *Data +) +{ + + PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data; + u8 PcmIndex = pHalPcmAdapter->PcmIndex; + u8 PcmCh = pHalPcmAdapter->PcmCh; + u32 RegChCNR03; + + PcmCh=0; + pHalPcmAdapter->Enable = 1; + + + //4 1) Check Pcm index is avaliable + RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03); + if (RegChCNR03 & (BIT24|BIT25)) { + //4 Pcm index is running, stop first + DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh); + + return _FALSE; + } + + HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03|BIT24|BIT25); + pHalPcmAdapter->PcmChCNR03.CH0RE = 1; + pHalPcmAdapter->PcmChCNR03.CH0TE = 1; + + return _TRUE; +} + +BOOL +HalPcmDisRtl8195a( + IN VOID *Data +) +{ + + PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data; + u8 PcmIndex = pHalPcmAdapter->PcmIndex; + u8 PcmCh = pHalPcmAdapter->PcmCh; + u32 RegChCNR03; + + PcmCh=0; + pHalPcmAdapter->Enable = 0; + + + RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03); + + HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03&(~(BIT24|BIT25))); + pHalPcmAdapter->PcmChCNR03.CH0RE = 0; + pHalPcmAdapter->PcmChCNR03.CH0TE = 0; + + return _TRUE; +} + + + +BOOL +HalPcmIsrEnAndDisRtl8195a ( + IN VOID *Data +) +{ +/* + PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data; + u32 IsrMask, Addr, IsrCtrl; + u8 IsrTypeIndex = 0; + + for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) { + + if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) { + Addr = (REG_GDMA_MASK_INT_BASE + IsrTypeIndex*8); + + IsrMask = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, Addr); + + IsrCtrl = ((pHalGdmaAdapter->IsrCtrl)?(pHalGdmaAdapter->ChEn | IsrMask): + ((~pHalGdmaAdapter->ChEn) & IsrMask)); + + HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex, + Addr, + IsrCtrl + ); + + } + } +*/ + return _TRUE; +} + + + +BOOL +HalPcmDumpRegRtl8195a ( + IN VOID *Data +) +{ +/* + PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data; + HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex, + REG_GDMA_CH_EN, + (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)| + (pHalGdmaAdapter->ChEn)) + ); +*/ + return _TRUE; +} + +BOOL +HalPcmRtl8195a ( + IN VOID *Data +) +{ +/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data; + HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex, + REG_GDMA_CH_EN, + (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)& + ~(pHalGdmaAdapter->ChEn)) + ); +*/ + return _TRUE; +} +/* +u8 +HalGdmaChIsrCleanRtl8195a ( + IN VOID *Data +) +{ + PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data; + u32 IsrStatus; + u8 IsrTypeIndex = 0, IsrActBitMap = 0; + + for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) { + + IsrStatus = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, + (REG_GDMA_RAW_INT_BASE + IsrTypeIndex*8)); + +// DBG_8195A_DMA("Isr Type %d: Isr Status 0x%x\n", IsrTypeIndex, IsrStatus); + + IsrStatus = (IsrStatus & (pHalGdmaAdapter->ChEn & 0xFF)); + + if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) { + HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex, + (REG_GDMA_CLEAR_INT_BASE+ (IsrTypeIndex*8)), + (IsrStatus)// & (pHalGdmaAdapter->ChEn & 0xFF)) + ); + IsrActBitMap |= BIT_(IsrTypeIndex); + + } + + } + return IsrActBitMap; + +} + + +VOID +HalGdmaChCleanAutoSrcRtl8195a ( + IN VOID *Data +) +{ + u32 CfgxLow; + PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data; + CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, + (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)); + + CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_SRC; + + HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex, + (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF), + CfgxLow + ); + + DBG_8195A_DMA("CFG Low data:0x%x\n", + HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF))); +} + +VOID +HalGdmaChCleanAutoDstRtl8195a ( + IN VOID *Data +) +{ + u32 CfgxLow; + PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data; + CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, + (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)); + + CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_DST; + + HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex, + (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF), + CfgxLow + ); + DBG_8195A_DMA("CFG Low data:0x%x\n", + HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF))); + +} +*/ + + diff --git a/lib/fwlib/rtl8195a/src/rtl8195a_pwm.c b/lib/fwlib/rtl8195a/src/rtl8195a_pwm.c new file mode 100644 index 0000000..dd5163e --- /dev/null +++ b/lib/fwlib/rtl8195a/src/rtl8195a_pwm.c @@ -0,0 +1,219 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "rtl8195a.h" +#include "hal_peri_on.h" + +#ifdef CONFIG_PWM_EN +#include "rtl8195a_pwm.h" +#include "hal_pwm.h" + +extern HAL_PWM_ADAPTER PWMPin[]; + +extern HAL_TIMER_OP HalTimerOp; + +/** + * @brief Configure a G-Timer to generate a tick with certain time. + * + * @param pwm_id: the PWM pin index + * @param tick_time: the time (micro-second) of a tick + * + * @retval None + */ +void +Pwm_SetTimerTick_8195a( + HAL_PWM_ADAPTER *pPwmAdapt, + u32 tick_time +) +{ + TIMER_ADAPTER TimerAdapter; + + + if (tick_time <= MIN_GTIMER_TIMEOUT) { + tick_time = MIN_GTIMER_TIMEOUT; + } + else { + tick_time = (((tick_time-1)/TIMER_TICK_US)+1) * TIMER_TICK_US; + } + + // Initial a G-Timer for the PWM pin + if (pPwmAdapt->tick_time != tick_time) { + TimerAdapter.IrqDis = 1; // Disable Irq + TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) NULL; + TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ; + TimerAdapter.IrqHandle.Priority = 0; + TimerAdapter.IrqHandle.Data = (u32)NULL; + TimerAdapter.TimerId = pPwmAdapt->gtimer_id; + TimerAdapter.TimerIrqPriority = 0; + TimerAdapter.TimerLoadValueUs = tick_time-1; + TimerAdapter.TimerMode = 1; // auto-reload with user defined value + + HalTimerOp.HalTimerInit((VOID*) &TimerAdapter); + pPwmAdapt->tick_time = tick_time; + DBG_PWM_INFO("%s: Timer_Id=%d Count=%d\n", __FUNCTION__, pPwmAdapt->gtimer_id, tick_time); + } + +} + + +/** + * @brief Set the duty ratio of the PWM pin. + * + * @param pwm_id: the PWM pin index + * @param period: the period time, in micro-second. + * @param pulse_width: the pulse width time, in micro-second. + * + * @retval None + */ +void +HAL_Pwm_SetDuty_8195a( + HAL_PWM_ADAPTER *pPwmAdapt, + u32 period, + u32 pulse_width +) +{ + u32 RegAddr; + u32 RegValue; + u32 period_tick; + u32 pulsewidth_tick; + u32 tick_time; + u8 timer_id; + u8 pwm_id; + + pwm_id = pPwmAdapt->pwm_id; + // Adjust the tick time to a proper value + if (period < (MIN_GTIMER_TIMEOUT*2)) { + DBG_PWM_ERR ("HAL_Pwm_SetDuty_8195a: Invalid PWM period(%d), too short!!\n", period); + tick_time = MIN_GTIMER_TIMEOUT; + period = MIN_GTIMER_TIMEOUT*2; + } + else { + tick_time = period / 0x3fc; + if (tick_time < MIN_GTIMER_TIMEOUT) { + tick_time = MIN_GTIMER_TIMEOUT; + } + } + + Pwm_SetTimerTick_8195a(pPwmAdapt, tick_time); + tick_time = pPwmAdapt->tick_time; +#if 0 + // Check if current tick time needs adjustment + if ((pPwmAdapt->tick_time << 12) <= period) { + // need a longger tick time + } + else if ((pPwmAdapt->tick_time >> 2) >= period) { + // need a shorter tick time + } +#endif + period_tick = period/tick_time; + if (period_tick == 0) { + period_tick = 1; + } + + if (pulse_width >= period) { +// pulse_width = period-1; + pulse_width = period; + } + pulsewidth_tick = pulse_width/tick_time; + if (pulsewidth_tick == 0) { +// pulsewidth_tick = 1; + } + + timer_id = pPwmAdapt->gtimer_id; + + pPwmAdapt->period = period_tick & 0x3ff; + pPwmAdapt->pulsewidth = pulsewidth_tick & 0x3ff; + + RegAddr = REG_PERI_PWM0_CTRL + (pwm_id*4); + RegValue = BIT31 | (timer_id<<24) | (pulsewidth_tick<<12) | period_tick; + + HAL_WRITE32(PERI_ON_BASE, RegAddr, RegValue); +} + +/** + * @brief Initializes and enable a PWM control pin. + * + * @param pwm_id: the PWM pin index + * @param sel: pin mux selection + * @param timer_id: the G-timer index assigned to this PWM + * + * @retval HAL_Status + */ +HAL_Status +HAL_Pwm_Init_8195a( + HAL_PWM_ADAPTER *pPwmAdapt +) +{ + u32 pwm_id; + u32 pin_sel; + + pwm_id = pPwmAdapt->pwm_id; + pin_sel = pPwmAdapt->sel; + // Initial a G-Timer for the PWM pin + Pwm_SetTimerTick_8195a(pPwmAdapt, MIN_GTIMER_TIMEOUT); + + // Set default duty ration + HAL_Pwm_SetDuty_8195a(pPwmAdapt, 20000, 10000); + + // Configure the Pin Mux + PinCtrl((PWM0+pwm_id), pin_sel, 1); + + return HAL_OK; +} + + +/** + * @brief Enable a PWM control pin. + * + * @param pwm_id: the PWM pin index + * + * @retval None + */ +void +HAL_Pwm_Enable_8195a( + HAL_PWM_ADAPTER *pPwmAdapt +) +{ + u32 pwm_id; + + pwm_id = pPwmAdapt->pwm_id; + // Configure the Pin Mux + if (!pPwmAdapt->enable) { + PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 1); + HalTimerOp.HalTimerEn(pPwmAdapt->gtimer_id); + pPwmAdapt->enable = 1; + } +} + + +/** + * @brief Disable a PWM control pin. + * + * @param pwm_id: the PWM pin index + * + * @retval None + */ +void +HAL_Pwm_Disable_8195a( + HAL_PWM_ADAPTER *pPwmAdapt +) +{ + u32 pwm_id; + + pwm_id = pPwmAdapt->pwm_id; + // Configure the Pin Mux + if (pPwmAdapt->enable) { + PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 0); + HalTimerOp.HalTimerDis(pPwmAdapt->gtimer_id); + pPwmAdapt->enable = 0; + } +} + +#endif //CONFIG_PWM_EN diff --git a/lib/fwlib/rtl8195a/src/rtl8195a_sdio_device.c b/lib/fwlib/rtl8195a/src/rtl8195a_sdio_device.c new file mode 100644 index 0000000..1b9980e --- /dev/null +++ b/lib/fwlib/rtl8195a/src/rtl8195a_sdio_device.c @@ -0,0 +1,3177 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#include "rtl8195a.h" +#include "hal_sdio.h" +#include "mailbox.h" + +#if CONFIG_INIC_EN +#include "freertos_pmu.h" +extern struct sk_buff *rltk_wlan_alloc_skb(unsigned int total_len); +extern unsigned char *skb_put(struct sk_buff * skb, unsigned int len); +extern void inic_sdio_free_data(unsigned char *data); +#if (CONFIG_INIC_SKB_TX == 0) //pre-allocated memory for SDIO TX BD +ALIGNMTO(4) char inic_TX_Buf[SDIO_TX_BD_NUM][SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT]; +#endif +#endif + +extern PHAL_SDIO_ADAPTER pgSDIODev; + +#ifdef CONFIG_SOC_PS_MODULE +//extern RAM_START_FUNCTION gRamWakeupFun; +extern u8 __ram_start_table_start__[]; +extern _LONG_CALL_ VOID HalCpuClkConfig(u8 CpuType); +extern _LONG_CALL_ VOID VectorTableInitRtl8195A(u32 StackP); +extern _LONG_CALL_ VOID HalReInitPlatformLogUartV02(VOID); +extern _LONG_CALL_ VOID HalInitPlatformTimerV02(VOID); +extern VOID InfraStart(VOID); +extern VOID SleepPG(u8 Option, u32 SDuration); +extern VOID PSHalInitPlatformLogUart(VOID); +extern VOID HalReInitPlatformTimer(VOID); +extern VOID DeepStandby(u8 Option, u32 SDuration, u8 GpioOption); +extern VOID QueryRegPwrState(u8 FuncIdx, u8* RegState, u8* HwState); +#endif + +/****************************************************************************** + * Function Prototype Declaration + ******************************************************************************/ +BOOL SDIO_Device_Init( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +VOID SDIO_Device_DeInit( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +VOID SDIO_IRQ_Handler( + IN VOID *pData +); + +VOID SDIO_Interrupt_Init( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +VOID SDIO_Interrupt_DeInit( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +VOID SDIO_Enable_Interrupt( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 IntMask +); + +VOID SDIO_Disable_Interrupt( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 IntMask +); + +VOID SDIO_Clear_ISR( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 IntMask +); + +VOID SDIO_TxTask( + IN VOID *pData +); + +VOID SDIO_RxTask( + IN VOID *pData +); + +static __inline VOID SDIO_Wakeup_Task( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +static VOID SDIO_SetEvent( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 Event +); + +static VOID SDIO_ClearEvent( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 Event +); + +static BOOL SDIO_IsEventPending( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 Event +); + +VOID SDIO_IRQ_Handler_BH( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +VOID SDIO_RX_IRQ_Handler_BH( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +VOID SDIO_TX_BD_Buf_Refill( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +VOID SDIO_TX_FIFO_DataReady( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +PSDIO_RX_PACKET SDIO_Alloc_Rx_Pkt( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +VOID SDIO_Free_Rx_Pkt( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN PSDIO_RX_PACKET pPkt +); + +VOID SDIO_Recycle_Rx_BD ( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +VOID SDIO_Process_H2C_IOMsg( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +VOID SDIO_Send_C2H_IOMsg( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 *C2HMsg +); + +VOID SDIO_Process_H2C_PktMsg( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u8 *H2CMsg +); + +u8 SDIO_Send_C2H_PktMsg( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u8 *C2HMsg, + IN u16 MsgLen +); + +u8 SDIO_Process_RPWM( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +u8 SDIO_Process_RPWM2( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +VOID SDIO_Reset_Cmd( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +VOID SDIO_Return_Rx_Data( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +VOID SDIO_Register_Tx_Callback( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN s8 (*CallbackFun)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize), + IN VOID *pAdapter +); + +s8 SDIO_Rx_Callback( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN VOID *pData, + IN u16 Offset, + IN u16 Length, + IN u8 CmdType +); + +s8 SDIO_Handle_MsgBlk( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN MSG_BLK *pMblk +); + +#if SDIO_MP_MODE +VOID SDIO_PeriodicalTimerCallback( + void *pContex +); + +u8 SDIO_MapMPCmd( + IN char *CmdStr, + IN u16 *Offset +); + +VOID SDIO_DumpMPStatus( + IN PHAL_SDIO_ADAPTER pSDIODev + ); + +VOID SDIO_StatisticDump( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +s8 SDIO_MP_Loopback( + IN VOID *pAdapter, + IN u8 *pData, + IN u16 Offset, + IN u16 PktSize +); + +s8 SDIO_MP_ContinueTx( + IN VOID *pAdapter, + IN u8 *pData, + IN u16 Offset, + IN u16 PktSize +); + +VOID SDIO_MP_ContinueRx( + IN PHAL_SDIO_ADAPTER pSDIODev +); + +VOID SDIO_DeviceMPApp( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u16 argc, + IN u8 *argv[] +); +#endif /* endof '#if SDIO_MP_MODE' */ + +/****************************************************************************** + * Global Variable Declaration + ******************************************************************************/ + +#if SDIO_MP_MODE +const SDIO_MP_CMD SDIO_MPCmdTable[] = { + {"mp_start", SDIO_MP_START}, + {"mp_stop", SDIO_MP_STOP}, + {"mp_loopback", SDIO_MP_LOOPBACK}, + {"status", SDIO_MP_STATUS}, + {"read_reg8", SDIO_MP_READ_REG8}, + {"read_reg16", SDIO_MP_READ_REG16}, + {"read_reg32", SDIO_MP_READ_REG32}, + {"write_reg8", SDIO_MP_WRITE_REG8}, + {"write_reg16", SDIO_MP_WRITE_REG16}, + {"write_reg32", SDIO_MP_WRITE_REG32}, + {"wakeup", SDIO_MP_WAKEUP}, + {"dump", SDIO_MP_DUMP}, + {"ctx", SDIO_MP_CTX}, + {"crx", SDIO_MP_CRX}, + {"crx_da", SDIO_MP_CRX_DA}, + {"crx_stop", SDIO_MP_CRX_STOP}, + {"dbg_msg", SDIO_MP_DBG_MSG} +}; + +const u8 MP_WlanHdr[]={ + 0x88,0x01,0x00,0x00,0xff,0xff,0xff,0xff,0xff,0xff, + 0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00, + 0x00,0x01,0x10,0x00,0x06,0x00}; +#endif + +/****************************************************************************** + * External Function & Variable Declaration + ******************************************************************************/ +extern PHAL_SDIO_ADAPTER pgSDIODev; + +extern u32 Strtoul( + IN const u8 *nptr, + IN u8 **endptr, + IN u32 base +); + +/****************************************************************************** + * Function: SDIO_Device_Init + * Desc: SDIO device driver initialization. + * 1. Allocate SDIO TX FIFO buffer and initial TX related register. + * 2. Allocate SDIO RX Buffer Descriptor and RX Buffer. Initial RX related + * register. + * 3. Register the Interrupt function. + * 4. Create the SDIO Task and allocate resource(Semaphore). + * + ******************************************************************************/ +BOOL SDIO_Device_Init( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + int i; + SDIO_TX_PACKET *pTxPkt; + SDIO_RX_PACKET *pPkt; + SDIO_TX_BD_HANDLE *pTxBdHdl; + SDIO_RX_BD_HANDLE *pRxBdHdl; + int ret; + u32 reg_value; + + DBG_SDIO_INFO("SDIO_Device_Init==>\n"); + + // Clean boot from wakeup bit + reg_value = HAL_READ32(PERI_ON_BASE, REG_SOC_FUNC_EN); + reg_value &= ~(BIT(29)); + HAL_WRITE32(PERI_ON_BASE, REG_SOC_FUNC_EN, reg_value); + + /* SDIO Function Enable */ + SDIOD_ON_FCTRL(ON); + SDIOD_OFF_FCTRL(ON); + + /* Enable Clock for SDIO function */ + ACTCK_SDIOD_CCTRL(ON); + SLPCK_SDIOD_CCTRL(ON); + + // Reset SDIO DMA + HAL_SDIO_WRITE8(REG_SPDIO_CPU_RST_DMA, BIT_CPU_RST_SDIO_DMA); + + /* Initial SDIO TX BD */ + DBG_SDIO_INFO("Tx BD Init==>\n"); + +// TODO: initial TX BD + pSDIODev->pTXBDAddr = RtlZmalloc((SDIO_TX_BD_NUM * sizeof(SDIO_TX_BD))+3); + if (NULL == pSDIODev->pTXBDAddr) { + DBG_SDIO_ERR("SDIO_Device_Init: Malloc for TX_BD Err!!\n"); + goto SDIO_INIT_ERR; + } + pSDIODev->pTXBDAddrAligned = (PSDIO_TX_BD)(((((u32)pSDIODev->pTXBDAddr - 1) >> 2) + 1) << 2); // Make it 4-bytes aligned + HAL_SDIO_WRITE32(REG_SPDIO_TXBD_ADDR, pSDIODev->pTXBDAddrAligned); + HAL_SDIO_WRITE16(REG_SPDIO_TXBD_SIZE, SDIO_TX_BD_NUM); + /* Set TX_BUFF_UNIT_SIZE */ +#if 0 + reg = HAL_SDIO_READ32(REG_SPDIO_RXBD_CNT); + reg &= ~((0xff)<<8); + reg |= (SDIO_TX_BD_BUF_USIZE<<8); + HAL_SDIO_WRITE32(REG_SPDIO_RXBD_CNT, reg); +#endif + HAL_SDIO_WRITE8(REG_SPDIO_TX_BUF_UNIT_SZ, SDIO_TX_BD_BUF_USIZE); + + DBG_SDIO_INFO("Tx BD Buf Unit Size(%d), Reg=0x%x\n", SDIO_TX_BD_BUF_USIZE, HAL_SDIO_READ8(REG_SPDIO_TX_BUF_UNIT_SZ)); + + /* Set DISPATCH_TXAGG_PKT */ + HAL_SDIO_WRITE32(REG_SPDIO_AHB_DMA_CTRL, HAL_SDIO_READ32(REG_SPDIO_AHB_DMA_CTRL)|BIT31); + // Reset HW TX BD pointer + pSDIODev->TXBDWPtr = HAL_SDIO_READ32(REG_SPDIO_TXBD_WPTR); + pSDIODev->TXBDRPtr = pSDIODev->TXBDWPtr; + pSDIODev->TXBDRPtrReg = pSDIODev->TXBDWPtr; + HAL_SDIO_WRITE32(REG_SPDIO_TXBD_RPTR, pSDIODev->TXBDRPtrReg); + + DBG_SDIO_INFO("TXBDWPtr=0x%x TXBDRPtr=0x%x\n", pSDIODev->TXBDWPtr, pSDIODev->TXBDRPtr); + + pSDIODev->pTXBDHdl = (PSDIO_TX_BD_HANDLE)RtlZmalloc(SDIO_TX_BD_NUM * sizeof(SDIO_TX_BD_HANDLE)); + if (NULL == pSDIODev->pTXBDHdl) { + DBG_SDIO_ERR("SDIO_Device_Init: Malloc for TX_BD Handle Err!!\n"); + goto SDIO_INIT_ERR; + } + + for (i=0;ipTXBDHdl + i; + pTxBdHdl->pTXBD = pSDIODev->pTXBDAddrAligned + i; +#if CONFIG_INIC_EN +#if CONFIG_INIC_SKB_TX +//allocate wlan skb here + pTxBdHdl->skb = rltk_wlan_alloc_skb(SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT); + DBG_SDIO_INFO("SDIO_Device_Init: pTxBdHdl->pkt @ 0x%x\n", pTxBdHdl->skb); + if(pTxBdHdl->skb) + pTxBdHdl->pTXBD->Address = (u32)pTxBdHdl->skb->tail; + else + DBG_SDIO_ERR("SDIO_Device_Init: rltk_wlan_alloc_skb (%d) failed!!\n", SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT); +#else + pTxBdHdl->pTXBD->Address = (u32)(&inic_TX_Buf[i][0]); +#endif +#else + // Allocate buffer for each TX BD + pTxBdHdl->pTXBD->Address = (u32)RtlMalloc(SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT); +#if SDIO_DEBUG + pSDIODev->MemAllocCnt++; +#endif +#endif + if (NULL == (u32*)(pTxBdHdl->pTXBD->Address)) { + // Memory Allocate Failed + int j; + + for (j=0;jpTXBDHdl + j; + pTxBdHdl->pTXBD = pSDIODev->pTXBDAddrAligned + j; + if (pTxBdHdl->pTXBD->Address) { +#if CONFIG_INIC_EN +#if CONFIG_INIC_SKB_TX + //free wlan skb here + dev_kfree_skb_any(pTxBdHdl->skb); +#endif + pTxBdHdl->pTXBD->Address =(u32)NULL; +#else + RtlMfree((u8 *)pTxBdHdl->pTXBD->Address, (SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT)); +#endif + } + } + goto SDIO_INIT_ERR; + } + pTxBdHdl->isFree = 1; + DBG_SDIO_INFO("TX_BD%d @ 0x%x 0x%x\n", i, pTxBdHdl, pTxBdHdl->pTXBD); + } + +#if (CONFIG_INIC_EN == 0) + RtlInitListhead(&pSDIODev->FreeTxPktList); // Init the list for free packet handler + /* Allocate memory for TX Packets handler */ + pSDIODev->pTxPktHandler = (SDIO_TX_PACKET *)(RtlZmalloc(sizeof(SDIO_TX_PACKET)*SDIO_TX_PKT_NUM)); + if (NULL == pSDIODev->pTxPktHandler) { + DBG_SDIO_ERR("SDIO_Device_Init: Malloc for TX PKT Handler Err!!\n"); + goto SDIO_INIT_ERR; + } + /* Add all TX packet handler into the Free Queue(list) */ + for (i=0;ipTxPktHandler + i; + RtlListInsertTail(&pTxPkt->list, &pSDIODev->FreeTxPktList); + } +#endif + /* Init RX BD and RX Buffer */ + pSDIODev->pRXBDAddr = RtlZmalloc((SDIO_RX_BD_NUM * sizeof(SDIO_RX_BD))+7); + if (NULL == pSDIODev->pRXBDAddr) { + DBG_SDIO_ERR("SDIO_Device_Init: Malloc for RX_BD Err!!\n"); + goto SDIO_INIT_ERR; + } + pSDIODev->pRXBDAddrAligned = (PSDIO_RX_BD)(((((u32)pSDIODev->pRXBDAddr - 1) >> 3) + 1) << 3); // Make it 8-bytes aligned + HAL_SDIO_WRITE32(REG_SPDIO_RXBD_ADDR, pSDIODev->pRXBDAddrAligned); + HAL_SDIO_WRITE16(REG_SPDIO_RXBD_SIZE, SDIO_RX_BD_NUM); + + // Set the threshold of free RX BD count to trigger interrupt + HAL_SDIO_WRITE16(REG_SPDIO_RX_BD_FREE_CNT, RX_BD_FREE_TH); + DBG_SDIO_INFO("Rx BD Free Cnt(%d), Reg=0x%x\n", RX_BD_FREE_TH, HAL_SDIO_READ16(REG_SPDIO_RX_BD_FREE_CNT)); + + pSDIODev->pRXBDHdl = (PSDIO_RX_BD_HANDLE)RtlZmalloc(SDIO_RX_BD_NUM * sizeof(SDIO_RX_BD_HANDLE)); + if (NULL == pSDIODev->pRXBDHdl) { + DBG_SDIO_ERR("SDIO_Device_Init: Malloc for RX_BD Handle Err!!\n"); + goto SDIO_INIT_ERR; + } + + for (i=0;ipRXBDHdl + i; + pRxBdHdl->pRXBD = pSDIODev->pRXBDAddrAligned + i; + pRxBdHdl->isFree = 1; + DBG_SDIO_INFO("RX_BD%d @ 0x%x 0x%x\n", i, pRxBdHdl, pRxBdHdl->pRXBD); + } + + + RtlInitListhead(&pSDIODev->FreeRxPktList); // Init the list for free packet handler + /* Allocate memory for RX Packets handler */ + pSDIODev->pRxPktHandler = (SDIO_RX_PACKET *)(RtlZmalloc(sizeof(SDIO_RX_PACKET)*SDIO_RX_PKT_NUM)); + if (NULL == pSDIODev->pRxPktHandler) { + DBG_SDIO_ERR("SDIO_Device_Init: Malloc for RX PKT Handler Err!!\n"); + goto SDIO_INIT_ERR; + } + /* Add all RX packet handler into the Free Queue(list) */ + for (i=0;ipRxPktHandler + i; + RtlListInsertTail(&pPkt->list, &pSDIODev->FreeRxPktList); + } + RtlInitListhead(&pSDIODev->RxPktList); // Init the list for RX packet to be send to the SDIO bus +// RtlInitListhead(&pSDIODev->RecyclePktList); // Init the list for packet to be recycled after the SDIO RX DMA is done + + RtlMutexInit(&pSDIODev->RxMutex); +#if SDIO_DEBUG + RtlMutexInit(&pSDIODev->StatisticMutex); +#endif + /* Create a Semaphone for SDIO Sync control */ +#if !TASK_SCHEDULER_DISABLED + RtlInitSema(&(pSDIODev->TxSema), 0); + if (NULL == pSDIODev->TxSema){ + DBG_SDIO_ERR("SDIO_Device_Init Create Semaphore Err!!\n"); + goto SDIO_INIT_ERR; + } + + RtlInitSema(&(pSDIODev->RxSema), 0); + if (NULL == pSDIODev->RxSema){ + DBG_SDIO_ERR("SDIO_Device_Init Create RX Semaphore Err!!\n"); + goto SDIO_INIT_ERR; + } + + /* create a Mailbox for other driver module to send message to SDIO driver */ + pSDIODev->pMBox = RtlMailboxCreate(MBOX_ID_SDIO, SDIO_MAILBOX_SIZE, &(pSDIODev->RxSema)); + if (NULL == pSDIODev->pMBox) { + DBG_SDIO_ERR("SDIO_Device_Init Create Mailbox Err!!\n"); + goto SDIO_INIT_ERR; + } +#if SDIO_MP_MODE + pSDIODev->pPeriodTimer = RtlTimerCreate("SDIO_Periodical", SDIO_PERIODICAL_TIMER_INTERVAL, SDIO_PeriodicalTimerCallback, pSDIODev, 1); +#endif + /* Create the SDIO task */ +#ifdef PLATFORM_FREERTOS + ret = xTaskCreate( SDIO_TxTask, "SDIO_TX_TASK", ((1024*2)/sizeof(portBASE_TYPE)), (void *)pSDIODev, SDIO_TASK_PRIORITY + PRIORITIE_OFFSET, &pSDIODev->xSDIOTxTaskHandle); + if (pdTRUE != ret ) + { + DBG_SDIO_ERR("SDIO_Device_Init: Create Task Err(%d)!!\n", ret); + goto SDIO_INIT_ERR; + } + + ret = xTaskCreate( SDIO_RxTask, "SDIO_RX_TASK", ((1024*1)/sizeof(portBASE_TYPE)), (void *)pSDIODev, SDIO_TASK_PRIORITY + PRIORITIE_OFFSET, &pSDIODev->xSDIORxTaskHandle); + if (pdTRUE != ret ) + { + DBG_SDIO_ERR("SDIO_Device_Init: Create RX Task Err(%d)!!\n", ret); + goto SDIO_INIT_ERR; + } + +#endif +#endif // end of "#if !TASK_SCHEDULER_DISABLED" +#if SDIO_MP_MODE +//1 for MP mode test only + pSDIODev->MP_ModeEn = 1; +// SDIO_Register_Tx_Callback(pSDIODev, (VOID *)SDIO_MP_Loopback, (VOID *) pSDIODev); +// pSDIODev->MP_LoopBackEn = 1; +//End +#endif +#if TASK_SCHEDULER_DISABLED + /* enable the interrupt */ + SDIO_Interrupt_Init(pSDIODev); + + /* Indicate the Host system that the TX/RX is ready */ + HAL_SDIO_WRITE8(REG_SPDIO_CPU_IND, \ + HAL_SDIO_READ8(REG_SPDIO_CPU_IND)|BIT_SYSTEM_TRX_RDY_IND); +#endif + pSDIODev->CRPWM = HAL_SDIO_READ8(REG_SPDIO_CRPWM); + pSDIODev->CRPWM2 = HAL_SDIO_READ16(REG_SPDIO_CRPWM2); + + // Indicate Host this is a iNIC FW + pSDIODev->CCPWM2 |= CPWM2_INIC_FW_RDY_BIT; + pSDIODev->CCPWM2 ^= CPWM2_TOGGLE_BIT; + HAL_SDIO_WRITE16(REG_SPDIO_CCPWM2, pSDIODev->CCPWM2); + +#if !PURE_SDIO_INIC +#ifdef CONFIG_SOC_PS_MODULE + { + REG_POWER_STATE SDIOPwrState; + + // To register a new peripheral device power state + SDIOPwrState.FuncIdx = SDIOD; + SDIOPwrState.PwrState = ACT; + RegPowerState(SDIOPwrState); + } +#endif +#endif + + DBG_SDIO_INFO("<==SDIO_Device_Init\n"); + + return SUCCESS; + + SDIO_INIT_ERR: +#if !TASK_SCHEDULER_DISABLED + if (pSDIODev->TxSema) { + RtlFreeSema(&pSDIODev->TxSema); + pSDIODev->TxSema = NULL; + } + + if (pSDIODev->RxSema) { + RtlFreeSema(&pSDIODev->RxSema); + pSDIODev->RxSema = NULL; + } +#endif + + if (pSDIODev->RxMutex) { + RtlMutexFree(&pSDIODev->RxMutex); + } +#if SDIO_DEBUG + if (pSDIODev->StatisticMutex) { + RtlMutexFree(&pSDIODev->StatisticMutex); + } +#endif + if (pSDIODev->pRxPktHandler) { + RtlMfree((u8*)pSDIODev->pRxPktHandler, sizeof(SDIO_RX_PACKET)*SDIO_RX_PKT_NUM); + pSDIODev->pRxPktHandler = NULL; + } + + if (pSDIODev->pRXBDHdl) { + RtlMfree((u8 *)pSDIODev->pRXBDHdl, SDIO_RX_BD_NUM * sizeof(SDIO_RX_BD_HANDLE)); + pSDIODev->pRXBDHdl = NULL; + } + + if (pSDIODev->pRXBDAddr) { + RtlMfree((u8 *)pSDIODev->pRXBDAddr, (SDIO_RX_BD_NUM * sizeof(SDIO_RX_BD))+7); + pSDIODev->pRXBDAddr = NULL; + } +#if (CONFIG_INIC_EN == 0) + if (pSDIODev->pTxPktHandler) { + RtlMfree((u8 *)pSDIODev->pTxPktHandler, (sizeof(SDIO_TX_PACKET)*SDIO_TX_PKT_NUM)); + pSDIODev->pTxPktHandler = NULL; + } +#endif + if ((pSDIODev->pTXBDHdl) && (pSDIODev->pTXBDAddr)) { + for (i=0;ipTXBDHdl + i; + if (pTxBdHdl->pTXBD->Address) { + +#if CONFIG_INIC_EN +#if CONFIG_INIC_SKB_TX + //free wlan skb here + dev_kfree_skb_any(pTxBdHdl->skb); +#endif +#else + RtlMfree((u8 *)pTxBdHdl->pTXBD->Address, (SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT)); +#endif + pTxBdHdl->pTXBD->Address = (u32)NULL; + } + } + } + + if (pSDIODev->pTXBDHdl) { + RtlMfree((u8 *)pSDIODev->pTXBDHdl, (SDIO_TX_BD_NUM * sizeof(SDIO_TX_BD_HANDLE))); + pSDIODev->pTXBDHdl = NULL; + } + + if (pSDIODev->pTXBDAddr) { + RtlMfree(pSDIODev->pTXBDAddr, ((SDIO_TX_BD_NUM * sizeof(SDIO_TX_BD))+3)); + pSDIODev->pTXBDAddr = NULL; + pSDIODev->pTXBDAddrAligned = NULL; + } + +#if !TASK_SCHEDULER_DISABLED + if (pSDIODev->pMBox) { + RtlMailboxDel(pSDIODev->pMBox); + pSDIODev->pMBox = NULL; + } +#if SDIO_MP_MODE + if (pSDIODev->pPeriodTimer) { + RtlTimerDelete(pSDIODev->pPeriodTimer); + pSDIODev->pPeriodTimer = NULL; + } +#endif +#endif + return FAIL; +} + + +/****************************************************************************** + * Function: SDIO_Device_DeInit + * Desc: SDIO device driver free resource. This function should be called in + * a task. + * 1. Free TX FIFO buffer + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +//TODO: Call this function in a task + +VOID SDIO_Device_DeInit( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + int i=0; + SDIO_TX_BD_HANDLE *pTxBdHdl; + + if (NULL == pSDIODev) + return; + + // Indicate the Host that Ameba is InActived + pSDIODev->CCPWM2 = HAL_SDIO_READ16(REG_SPDIO_CCPWM2); + pSDIODev->CCPWM2 &= ~(CPWM2_ACT_BIT); + pSDIODev->CCPWM2 ^= CPWM2_TOGGLE_BIT; + HAL_SDIO_WRITE16(REG_SPDIO_CCPWM2, pSDIODev->CCPWM2); + +#if !TASK_SCHEDULER_DISABLED + /* Exit the SDIO task */ +#if 0 + // if this function is called by TX Task, then the TX task cannot be stopped + while (1) { + SDIO_SetEvent(pSDIODev, SDIO_EVENT_EXIT); + SDIO_Wakeup_Task(pSDIODev); + if (SDIO_IsEventPending(pSDIODev, SDIO_EVENT_TX_STOPPED) && + SDIO_IsEventPending(pSDIODev, (u32)SDIO_EVENT_RX_STOPPED)) { + SDIO_ClearEvent(pSDIODev, SDIO_EVENT_EXIT); + break; // break the while loop + } + RtlMsleepOS(10); + i++; + if (i> 100) { + DBG_SDIO_ERR("SDIO_Device_DeInit: Delete SDIO Task Failed with Timeout\n"); + break; + } + } +#endif +#if SDIO_MP_MODE + if (pSDIODev->pPeriodTimer) { + RtlTimerDelete(pSDIODev->pPeriodTimer); + pSDIODev->pPeriodTimer = NULL; + } +#endif + /* Delete the Mailbox */ + if (pSDIODev->pMBox) { + RtlMailboxDel(pSDIODev->pMBox); + pSDIODev->pMBox = NULL; + } + + /* Delete the Semaphore */ + if (pSDIODev->TxSema) { + RtlFreeSema(&pSDIODev->TxSema); + pSDIODev->TxSema = NULL; + } + + if (pSDIODev->RxSema) { + RtlFreeSema(&pSDIODev->RxSema); + pSDIODev->RxSema = NULL; + } +#endif + + if (pSDIODev->RxMutex) { + RtlMutexFree(&pSDIODev->RxMutex); + } +#if SDIO_DEBUG + if (pSDIODev->StatisticMutex) { + RtlMutexFree(&pSDIODev->StatisticMutex); + } +#endif + if (pSDIODev->pRxPktHandler) { + RtlMfree((u8*)pSDIODev->pRxPktHandler, sizeof(SDIO_RX_PACKET)*SDIO_RX_PKT_NUM); + pSDIODev->pRxPktHandler = NULL; + } + + if (pSDIODev->pRXBDHdl) { + RtlMfree((u8 *)pSDIODev->pRXBDHdl, SDIO_RX_BD_NUM * sizeof(SDIO_RX_BD_HANDLE)); + pSDIODev->pRXBDHdl = NULL; + } + + /* Free RX BD */ + if (pSDIODev->pRXBDAddr) { + RtlMfree((u8 *)pSDIODev->pRXBDAddr, (SDIO_RX_BD_NUM * sizeof(SDIO_RX_BD))+7); + pSDIODev->pRXBDAddr = NULL; + } + + /* Free TX FIFO Buffer */ + for (i=0;ipTXBDHdl + i; + if (pTxBdHdl->pTXBD->Address) { +#if CONFIG_INIC_EN +#if CONFIG_INIC_SKB_TX + //free wlan skb here + dev_kfree_skb_any(pTxBdHdl->skb); +#endif +#else + RtlMfree((u8 *)pTxBdHdl->pTXBD->Address, (SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT)); +#endif + pTxBdHdl->pTXBD->Address = (u32)NULL; + } + } +#if (CONFIG_INIC_EN == 0) + if (pSDIODev->pTxPktHandler) { + RtlMfree((u8 *)pSDIODev->pTxPktHandler, (sizeof(SDIO_TX_PACKET)*SDIO_TX_PKT_NUM)); + pSDIODev->pTxPktHandler = NULL; + } +#endif + if (pSDIODev->pTXBDHdl) { + RtlMfree((u8 *)pSDIODev->pTXBDHdl, (SDIO_TX_BD_NUM * sizeof(SDIO_TX_BD_HANDLE))); + pSDIODev->pTXBDHdl = NULL; + } + + if (pSDIODev->pTXBDAddr) { + RtlMfree(pSDIODev->pTXBDAddr, ((SDIO_TX_BD_NUM * sizeof(SDIO_TX_BD))+3)); + pSDIODev->pTXBDAddr = NULL; + pSDIODev->pTXBDAddrAligned = NULL; + } + SDIO_Disable_Interrupt(pSDIODev, 0xffff); + SDIO_Interrupt_DeInit(pSDIODev); + + // Reset SDIO DMA + HAL_SDIO_WRITE8(REG_SPDIO_CPU_RST_DMA, BIT_CPU_RST_SDIO_DMA); + + /* Enable Clock for SDIO function */ +// ACTCK_SDIOD_CCTRL(OFF); + + /* SDIO Function Enable */ +// SDIOD_ON_FCTRL(OFF); + SDIOD_OFF_FCTRL(OFF); +} + +#if TASK_SCHEDULER_DISABLED +/****************************************************************************** + * Function: SDIO_TaskUp + * Desc: For the Task scheduler no running case, use this function to run the + * SDIO task main loop. + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_TaskUp( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + u16 ISRStatus; + +// DiagPrintf("SDIO_TaskUp==>\n"); + pSDIODev->EventSema++; + if (pSDIODev->EventSema > 1000) { + pSDIODev->EventSema = 1000; + } + if (pSDIODev->EventSema == 1) { + while (pSDIODev->EventSema > 0) { + ISRStatus = HAL_SDIO_READ16(REG_SPDIO_CPU_INT_STAS); + pSDIODev->IntStatus |= ISRStatus; + HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_STAS, ISRStatus); // clean the ISR + SDIO_SetEvent(pSDIODev, SDIO_EVENT_IRQ|SDIO_EVENT_C2H_DMA_DONE); + + SDIO_TxTask(pSDIODev); + SDIO_RxTask(pSDIODev); + + pSDIODev->EventSema--; + } + } +// DiagPrintf("<==SDIO_TaskUp\n"); +} +#endif + +/****************************************************************************** + * Function: SDIO_IRQ_Handler + * Desc: SDIO device interrupt service routine + * 1. Read & clean the interrupt status + * 2. Wake up the SDIO task to handle the IRQ event + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_IRQ_Handler( + IN VOID *pData +) +{ + PHAL_SDIO_ADAPTER pSDIODev = pData; + u16 ISRStatus; + + ISRStatus = HAL_SDIO_READ16(REG_SPDIO_CPU_INT_STAS); + DBG_SDIO_INFO("%s:ISRStatus=0x%x\n", __FUNCTION__, ISRStatus); + + pSDIODev->IntStatus |= ISRStatus; + HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_STAS, ISRStatus); // clean the ISR +#if !TASK_SCHEDULER_DISABLED + if (ISRStatus & BIT_C2H_DMA_OK) { + SDIO_SetEvent(pSDIODev, SDIO_EVENT_C2H_DMA_DONE); + RtlUpSemaFromISR(&pSDIODev->RxSema); + } + + if (ISRStatus & ~BIT_C2H_DMA_OK) { + SDIO_SetEvent(pSDIODev, SDIO_EVENT_IRQ); + RtlUpSemaFromISR(&pSDIODev->TxSema); + } +#else + SDIO_SetEvent(pSDIODev, SDIO_EVENT_IRQ|SDIO_EVENT_C2H_DMA_DONE); + SDIO_TaskUp(pSDIODev); +#endif +} + +/****************************************************************************** + * Function: SDIO_Interrupt_Init + * Desc: SDIO device interrupt initialization. + * 1. Register the ISR + * 2. Initial the IMR register + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_Interrupt_Init( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + IRQ_HANDLE SdioIrqHandle; + + pSDIODev->IntMask = BIT_H2C_DMA_OK | BIT_C2H_DMA_OK | BIT_H2C_MSG_INT | BIT_RPWM1_INT | \ + BIT_RPWM2_INT |BIT_H2C_BUS_RES_FAIL | BIT_RXBD_FLAG_ERR_INT; + HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_STAS, pSDIODev->IntMask); // Clean pending interrupt first + + SdioIrqHandle.Data = (u32) pSDIODev; + SdioIrqHandle.IrqNum = SDIO_DEVICE_IRQ; + SdioIrqHandle.IrqFun = (IRQ_FUN) SDIO_IRQ_Handler; + SdioIrqHandle.Priority = SDIO_IRQ_PRIORITY; + + InterruptRegister(&SdioIrqHandle); + InterruptEn(&SdioIrqHandle); + + HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_MASK, pSDIODev->IntMask); +} + +/****************************************************************************** + * Function: SDIO_Interrupt_DeInit + * Desc: SDIO device interrupt De-Initial. + * 1. UnRegister the ISR + * 2. Initial the IMR register with 0 + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_Interrupt_DeInit( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + IRQ_HANDLE SdioIrqHandle; + + HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_STAS, 0xffff); // Clean pending interrupt first + + SdioIrqHandle.Data = (u32) pSDIODev; + SdioIrqHandle.IrqNum = SDIO_DEVICE_IRQ; + SdioIrqHandle.Priority = SDIO_IRQ_PRIORITY; + + InterruptDis(&SdioIrqHandle); + InterruptUnRegister(&SdioIrqHandle); +} + +/****************************************************************************** + * Function: SDIO_Enable_Interrupt + * Desc: SDIO enable interrupt by modify the interrupt mask + * + * Para: + * pSDIODev: The SDIO device data structor. + * IntMask: The bit map to enable the interrupt. + ******************************************************************************/ +__inline VOID SDIO_Enable_Interrupt( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 IntMask +) +{ + RtlEnterCritical(); + pSDIODev->IntMask |= IntMask; + HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_MASK, pSDIODev->IntMask); + RtlExitCritical(); +} + +/****************************************************************************** + * Function: SDIO_Disable_Interrupt + * Desc: SDIO disable interrupt by modify the interrupt mask + * + * Para: + * pSDIODev: The SDIO device data structor. + * IntMask: The bit map to disable the interrupt. + ******************************************************************************/ +__inline VOID SDIO_Disable_Interrupt( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 IntMask +) +{ + RtlEnterCritical(); + pSDIODev->IntMask &= ~IntMask; + HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_MASK, pSDIODev->IntMask); + RtlExitCritical(); +} + +/****************************************************************************** + * Function: SDIO_Clear_ISR + * Desc: SDIO clear ISR bit map. + * + * Para: + * pSDIODev: The SDIO device data structor. + * IntMask: The bit map to be clean. + ******************************************************************************/ +__inline VOID SDIO_Clear_ISR( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 IntMask +) +{ + RtlEnterCritical(); + pSDIODev->IntStatus &= ~IntMask; + RtlExitCritical(); +} + +/****************************************************************************** + * Function: SDIO_TxTask + * Desc: The SDIO task handler. This is the main function of the SDIO device + * driver. + * 1. Handle interrupt events. + * * SDIO TX data ready + * * Error handling + * 2. + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_TxTask( + IN VOID *pData +) +{ + PHAL_SDIO_ADAPTER pSDIODev = pData; + + /* Initial resource */ +#if !TASK_SCHEDULER_DISABLED + /* enable the interrupt */ + SDIO_Interrupt_Init(pSDIODev); + + // Update the power state indication + pSDIODev->CCPWM2 = HAL_SDIO_READ16(REG_SPDIO_CCPWM2); + pSDIODev->CCPWM2 |= CPWM2_ACT_BIT; + pSDIODev->CCPWM2 ^= CPWM2_TOGGLE_BIT; + HAL_SDIO_WRITE16(REG_SPDIO_CCPWM2, pSDIODev->CCPWM2); + + /* Indicate the Host system that the TX/RX is ready */ + HAL_SDIO_WRITE8(REG_SPDIO_CPU_IND, \ + HAL_SDIO_READ8(REG_SPDIO_CPU_IND)|BIT_SYSTEM_TRX_RDY_IND); +#if SDIO_MP_MODE + if (pSDIODev->pPeriodTimer) { + RtlTimerStart(pSDIODev->pPeriodTimer, 0); + } +#endif +#endif + +#if !TASK_SCHEDULER_DISABLED + for (;;) +#endif + { + /* Task blocked and wait the semaphore(events) here */ +#if !TASK_SCHEDULER_DISABLED + RtlDownSema(&pSDIODev->TxSema); +#endif + if (SDIO_IsEventPending(pSDIODev, SDIO_EVENT_IRQ)) { + SDIO_ClearEvent(pSDIODev, SDIO_EVENT_IRQ); + SDIO_IRQ_Handler_BH(pSDIODev); + } + + if (SDIO_IsEventPending(pSDIODev, SDIO_EVENT_TXBD_REFILL)) { + SDIO_ClearEvent(pSDIODev, SDIO_EVENT_TXBD_REFILL); + SDIO_TX_BD_Buf_Refill(pSDIODev); + } + +#if !TASK_SCHEDULER_DISABLED + if (SDIO_IsEventPending(pSDIODev, SDIO_EVENT_EXIT)) { + break; // break the loop to exit the task + } +#endif + } + +#if !TASK_SCHEDULER_DISABLED +#if SDIO_MP_MODE + if (pSDIODev->pPeriodTimer) { + RtlTimerStop(pSDIODev->pPeriodTimer, 0); + } +#endif + SDIO_SetEvent(pSDIODev, SDIO_EVENT_TX_STOPPED); + DBG_SDIO_INFO("SDIO TX Task Stopped!\n"); +#if ( INCLUDE_vTaskDelete == 1 ) + vTaskDelete(NULL); +#endif +#endif +} + +/****************************************************************************** + * Function: SDIO_RxTask + * Desc: The SDIO RX task handler. This is the main function of the SDIO device + * driver to handle SDIO RX. + * 1. Handle interrupt events. + * * SDIO RX done + * 2. Send RX data back to the host by fill RX_BD to hardware. + * 3. Handle messages from mailbox + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_RxTask( + IN VOID *pData +) +{ + PHAL_SDIO_ADAPTER pSDIODev = pData; + MSG_BLK Mblk; + +#if !TASK_SCHEDULER_DISABLED + for (;;) +#endif + { + /* Task blocked and wait the semaphore(events) here */ +#if !TASK_SCHEDULER_DISABLED + RtlDownSema(&pSDIODev->RxSema); +#endif + if (SDIO_IsEventPending(pSDIODev, SDIO_EVENT_C2H_DMA_DONE)) { + SDIO_ClearEvent(pSDIODev, SDIO_EVENT_C2H_DMA_DONE); + SDIO_RX_IRQ_Handler_BH(pSDIODev); + } + +#if SDIO_MP_MODE + if (pSDIODev->MP_ContinueRx) { + SDIO_MP_ContinueRx(pSDIODev); + } +#endif // end of "#if SDIO_MP_MODE" + + if (SDIO_IsEventPending(pSDIODev, SDIO_EVENT_RX_PKT_RDY)) { + SDIO_ClearEvent(pSDIODev, SDIO_EVENT_RX_PKT_RDY); + SDIO_Return_Rx_Data(pSDIODev); + } + +#if !TASK_SCHEDULER_DISABLED + /* handle message block in the mailbox */ + do { + if (_SUCCESS == RtlMailboxReceive(MBOX_ID_SDIO, &Mblk, MBOX_WAIT_NONE, 0)) { + SDIO_Handle_MsgBlk(pSDIODev, &Mblk); + } + else { + break; // no more message pending, break the while loop + } + } while (1); + + if (SDIO_IsEventPending(pSDIODev, SDIO_EVENT_EXIT)) { + break; // break the loop to exit the task + } +#endif + } + +#if !TASK_SCHEDULER_DISABLED + SDIO_SetEvent(pSDIODev, (u32)SDIO_EVENT_RX_STOPPED); + DBG_SDIO_INFO("SDIO RX Task Stopped!\n"); +#if ( INCLUDE_vTaskDelete == 1 ) + vTaskDelete(NULL); +#endif +#endif +} + + +/****************************************************************************** + * Function: SDIO_Wakeup_Task + * Desc: Send a semaphore to wake up the task. + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +static __inline VOID SDIO_Wakeup_Task( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ +#if !TASK_SCHEDULER_DISABLED + RtlUpSema(&pSDIODev->TxSema); + RtlUpSema(&pSDIODev->RxSema); +#else + SDIO_TaskUp(pSDIODev); +#endif +} + +/****************************************************************************** + * Function: SDIO_SetEvent + * Desc: Set an event and wake up SDIO task to handle it. + * + * Para: + * pSDIODev: The SDIO device data structor. + * Event: The event to be set. + ******************************************************************************/ +static VOID SDIO_SetEvent( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 Event +) +{ + RtlEnterCritical(); + pSDIODev->Events |= Event; + RtlExitCritical(); +} + +/****************************************************************************** + * Function: SDIO_ClearEvent + * Desc: Clean a SDIO event. + * + * Para: + * pSDIODev: The SDIO device data structor. + * Event: The event to be cleaned. + ******************************************************************************/ +static VOID SDIO_ClearEvent( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 Event +) +{ + RtlEnterCritical(); + pSDIODev->Events &= ~Event; + RtlExitCritical(); +} + +/****************************************************************************** + * Function: SDIO_IsEventPending + * Desc: To check is a event pending. + * + * Para: + * pSDIODev: The SDIO device data structor. + * Event: The event to check. + ******************************************************************************/ +static BOOL SDIO_IsEventPending( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 Event +) +{ + BOOL ret; + + RtlEnterCritical(); + ret = (pSDIODev->Events & Event) ? 1:0; + RtlExitCritical(); + + return ret; +} + +/****************************************************************************** + * Function: SDIO_IRQ_Handler_BH + * Desc: Process the SDIO IRQ, the button helf. + * 1. SDIO TX data ready. + * 2. H2C command ready. + * 3. Host driver RPWM status updated. + * 4. SDIO RX data transfer done. + * 5. SDIO HW/BUS errors. + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_IRQ_Handler_BH( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + u32 IntStatus; + + DBG_SDIO_INFO("%s @1 IntStatus=0x%x\n", __FUNCTION__, pSDIODev->IntStatus); + + RtlEnterCritical(); + IntStatus = pSDIODev->IntStatus; + RtlExitCritical(); + + if (IntStatus & BIT_H2C_DMA_OK) { + SDIO_Clear_ISR(pSDIODev, BIT_H2C_DMA_OK); + SDIO_Disable_Interrupt(pSDIODev, BIT_H2C_DMA_OK); + SDIO_TX_FIFO_DataReady(pSDIODev); + SDIO_Enable_Interrupt(pSDIODev, BIT_H2C_DMA_OK); + } + + if (IntStatus & BIT_H2C_MSG_INT) { + SDIO_Clear_ISR(pSDIODev, BIT_H2C_MSG_INT); + SDIO_Process_H2C_IOMsg(pSDIODev); + } + + if (IntStatus & BIT_RPWM1_INT) { + SDIO_Clear_ISR(pSDIODev, BIT_RPWM1_INT); + SDIO_Process_RPWM(pSDIODev); + } + + if (IntStatus & BIT_RPWM2_INT) { + SDIO_Clear_ISR(pSDIODev, BIT_RPWM2_INT); + SDIO_Process_RPWM2(pSDIODev); + } + + if (IntStatus & BIT_SDIO_RST_CMD_INT) { + SDIO_Clear_ISR(pSDIODev, BIT_SDIO_RST_CMD_INT); + SDIO_Reset_Cmd(pSDIODev); + } + + DBG_SDIO_INFO("%s @2 IntStatus=0x%x\n", __FUNCTION__, pSDIODev->IntStatus); +} + +/****************************************************************************** + * Function: SDIO_RX_IRQ_Handler_BH + * Desc: Process the SDIO RX IRQ, the button helf. + * 1. SDIO RX data transfer done. + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_RX_IRQ_Handler_BH( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + u32 IntStatus; + + RtlEnterCritical(); + IntStatus = pSDIODev->IntStatus; + RtlExitCritical(); + + if (IntStatus & BIT_C2H_DMA_OK) { + SDIO_Clear_ISR(pSDIODev, BIT_C2H_DMA_OK); + RtlDownMutex(&pSDIODev->RxMutex); + pSDIODev->RxFifoBusy = 0; + RtlUpMutex(&pSDIODev->RxMutex); + SDIO_Recycle_Rx_BD(pSDIODev); +// SDIO_Return_Rx_Data(pSDIODev); + } +} + + +/****************************************************************************** + * Function: SDIO_TX_BD_Buf_Refill + * Desc: To refill all TX BD buffer. + * 1. Check all TX BD buffer + * 2. Allocate a new buffer for TX BD buffer is invalid + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_TX_BD_Buf_Refill( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + u32 i,j; + PSDIO_TX_BD_HANDLE pTxBdHdl; + #define WAIT_TIMEOUT 100 + + for (i=0;ipTXBDHdl + pSDIODev->TXBDRPtrReg; + if (NULL == (u32*)(pTxBdHdl->pTXBD->Address)) { + for (j=0;jskb = rltk_wlan_alloc_skb(SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT); + if(pTxBdHdl->skb) + pTxBdHdl->pTXBD->Address = (u32)pTxBdHdl->skb->tail; +#endif +#else + pTxBdHdl->pTXBD->Address = (u32)RtlMalloc(SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT); +#endif + if (NULL == (u32*)(pTxBdHdl->pTXBD->Address)) { + DBG_SDIO_WARN("%s Alloc Mem(size=%d) Failed\n", __FUNCTION__, SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT); + RtlMsleepOS(20); + } + else { +#if SDIO_DEBUG + pSDIODev->MemAllocCnt++; +#endif + pSDIODev->TXBDRPtrReg++; + if (pSDIODev->TXBDRPtrReg >= SDIO_TX_BD_NUM) { + pSDIODev->TXBDRPtrReg = 0; + } + HAL_SDIO_WRITE16(REG_SPDIO_TXBD_RPTR, pSDIODev->TXBDRPtrReg); + break; // break the for loop + } + } + if (j == WAIT_TIMEOUT) { + break; // break the for loop + } + } + else { + break; // break the for loop + } + } + + if (pSDIODev->TXBDRPtrReg != pSDIODev->TXBDRPtr) { + DBG_SDIO_ERR("SDIO_TX_BD_Buf_Refill Err: TXBDRPtrReg=%d TXBDRPtr=%d\n", pSDIODev->TXBDRPtrReg, pSDIODev->TXBDRPtr); + } +} + + +/****************************************************************************** + * Function: SDIO_TX_FIFO_DataReady + * Desc: Handle the SDIO FIFO data ready interrupt. + * 1. Send those data to the target driver via callback fun., like WLan. + * 2. Allocate a buffer for the TX BD + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_TX_FIFO_DataReady( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + PSDIO_TX_BD_HANDLE pTxBdHdl; + PSDIO_TX_DESC pTxDesc; + volatile u16 TxBDWPtr=0; + u32 processed_pkt_cnt=0; + u8 isForceBreak=0; + s8 ret=FAIL; + u32 mem_alloc_failed=0; + u32 reg; + + +// DBG_SDIO_INFO("SDIO_TX_FIFO_DataReady==>\n"); + + TxBDWPtr = HAL_SDIO_READ16(REG_SPDIO_TXBD_WPTR); + if (TxBDWPtr == pSDIODev->TXBDRPtr) { + if ((pSDIODev->IntStatus & BIT_TXFIFO_H2C_OVF) == 0) { + DBG_SDIO_WARN("SDIO TX Data Read False Triggered!!, TXBDWPtr=0x%x\n", TxBDWPtr); + return; + } + else { + reg = HAL_SDIO_READ32(REG_SPDIO_AHB_DMA_CTRL); + DBG_SDIO_WARN("SDIO TX Overflow Case: Reg DMA_CTRL==0x%x %x %x %x\n", (reg>> 24)&0xff , (reg>>16)&0xff, (reg>>8)&0xff, (reg)&0xff); + } + } + + do { + DBG_SDIO_INFO("SDIO_TX_DataReady: TxBDWPtr=%d TxBDRPtr=%d\n", TxBDWPtr, pSDIODev->TXBDRPtr); + pTxBdHdl = pSDIODev->pTXBDHdl + pSDIODev->TXBDRPtr; + pTxDesc = (PSDIO_TX_DESC)(pTxBdHdl->pTXBD->Address); + + DBG_SDIO_INFO("SDIO_TX_DataReady: PktSz=%d Offset=%d\n", pTxDesc->txpktsize, pTxDesc->offset); + if ((pTxDesc->txpktsize + pTxDesc->offset) <= (SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT)) { + // use the callback function to fordward this packet to target(WLan) driver + if (pSDIODev->Tx_Callback) { +#if CONFIG_INIC_EN +#if CONFIG_INIC_SKB_TX + ret = pSDIODev->Tx_Callback(pSDIODev->pTxCb_Adapter, (u8*)pTxBdHdl->skb, pTxDesc->offset, pTxDesc->txpktsize); // includes TX Desc +#else + ret = pSDIODev->Tx_Callback(pSDIODev->pTxCb_Adapter, (u8*)pTxBdHdl->pTXBD->Address, pTxDesc->offset, pTxDesc->txpktsize); // includes TX Desc +#endif +#else + ret = pSDIODev->Tx_Callback(pSDIODev->pTxCb_Adapter, (u8*)pTxBdHdl->pTXBD->Address, pTxDesc->offset, pTxDesc->txpktsize); // includes TX Desc +#endif +#if 0 + ret = pSDIODev->Tx_Callback(pSDIODev->pTxCb_Adapter, // doesn't include TX Desc + (u8*)(pTxBdHdl->pTXBD->Address+pTxDesc->offset), + pTxDesc->txpktsize); +#endif + } + else { + ret = FAIL; + DBG_SDIO_ERR("SDIO TX_Callback is Null!\n"); + } + } + else { + // Invalid packet, Just drop it + DBG_SDIO_WARN("SDIO_TX_DataReady Err: Incorrect TxDesc, PktSz=%d Offset=%d BufSize=%d\n", pTxDesc->txpktsize, pTxDesc->offset, \ + (SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT)); + ret = SUCCESS; // pretend we call the TX callback OK + } + processed_pkt_cnt++; + if (SUCCESS != ret) { + // may be is caused by TX queue is full, so we skip it and try again later + isForceBreak = 1; + break; // break the while loop + } + else { +#if SDIO_MP_MODE + pSDIODev->MP_TxPktCnt++; + pSDIODev->MP_TxByteCnt += pTxDesc->txpktsize; + + pSDIODev->MP_TxPktCntInPeriod++; + pSDIODev->MP_TxByteCntInPeriod += pTxDesc->txpktsize; +#endif + pSDIODev->TXBDRPtr++; + if (pSDIODev->TXBDRPtr >= SDIO_TX_BD_NUM) { + pSDIODev->TXBDRPtr = 0; + } + + // allocate a new buffer for this TX BD + // buf once if the memory allocation failed, we will try it later + if (mem_alloc_failed == 0) { +#if CONFIG_INIC_EN +#if CONFIG_INIC_SKB_TX//or use bss for tx bd, not need to re-allocate memory + //allocate wlan skb for each TX BD + pTxBdHdl->skb = rltk_wlan_alloc_skb(SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT); + if(pTxBdHdl->skb) + pTxBdHdl->pTXBD->Address = (u32)pTxBdHdl->skb->tail; + else + pTxBdHdl->pTXBD->Address = (u32)NULL; +#endif +#else + // Allocate buffer for each TX BD + pTxBdHdl->pTXBD->Address = (u32)RtlMalloc(SDIO_TX_BD_BUF_USIZE*SDIO_TX_BUF_SZ_UNIT); +#endif + if (NULL == (u32*)(pTxBdHdl->pTXBD->Address)) { + // memory allocate error + // once memory allocate failed, stop to allocate new buffer for TX BD buffer + //, we refill TX BD buffer later + DBG_SDIO_WARN("%s: Alloc new TX BD Buf Failed\n", __FUNCTION__); + mem_alloc_failed++; + SDIO_SetEvent(pSDIODev, SDIO_EVENT_TXBD_REFILL); + } + else { +#if SDIO_DEBUG + pSDIODev->MemAllocCnt++; +#endif + pSDIODev->TXBDRPtrReg = pSDIODev->TXBDRPtr; + HAL_SDIO_WRITE16(REG_SPDIO_TXBD_RPTR, pSDIODev->TXBDRPtrReg); + } + } + else { + pTxBdHdl->pTXBD->Address = (u32)NULL; + } + } + + TxBDWPtr = HAL_SDIO_READ16(REG_SPDIO_TXBD_WPTR); + if (isForceBreak) { + break; // break the TX FIFO DMA Done processing + } + } while (pSDIODev->TXBDRPtr != TxBDWPtr); + + // if not all TX data were processed, set an event to trigger SDIO_Task to process them later + if (isForceBreak) { + DBG_SDIO_WARN("SDIO_TX Force Break: TXBDWP=0x%x TXBDRP=0x%x\n", TxBDWPtr, pSDIODev->TXBDRPtr); + RtlEnterCritical(); + if ((pSDIODev->IntStatus & BIT_TXFIFO_H2C_OVF) != 0) { + if (pSDIODev->TXBDRPtr != TxBDWPtr) { + pSDIODev->IntStatus &= ~BIT_TXFIFO_H2C_OVF; + } + } + pSDIODev->IntStatus |= BIT_H2C_DMA_OK; + RtlExitCritical(); + SDIO_SetEvent(pSDIODev, SDIO_EVENT_IRQ); +#if !TASK_SCHEDULER_DISABLED + RtlUpSema(&pSDIODev->TxSema); +#else + SDIO_TaskUp(pSDIODev); +#endif + } + else { + if ((pSDIODev->IntStatus & BIT_TXFIFO_H2C_OVF) != 0) { + SDIO_Clear_ISR(pSDIODev, BIT_TXFIFO_H2C_OVF); + } + } +} + +/****************************************************************************** + * Function: SDIO_Alloc_Rx_Pkt + * Desc: Allocate a RX Packet Handle from the queue. + * + * Para: + * pSDIODev: The SDIO device data structor. + * + * Return: + * The allocated RX packet handler. + ******************************************************************************/ +PSDIO_RX_PACKET SDIO_Alloc_Rx_Pkt( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + _LIST *plist; + SDIO_RX_PACKET *pPkt; + u32 loop_cnt; + + RtlDownMutex(&pSDIODev->RxMutex); + if (RtlIsListEmpty(&pSDIODev->FreeRxPktList)) { + RtlUpMutex(&pSDIODev->RxMutex); + loop_cnt = 0; + do { + pPkt =(SDIO_RX_PACKET *)RtlZmalloc(sizeof(SDIO_RX_PACKET)); + if (NULL != pPkt) { + pPkt->isDyna = 1; // this packet handler is dynamic allocated + DBG_SDIO_WARN("Warn! No Free RX PKT, Use Dyna Alloc\n"); + } + else { + RtlMsleepOS(10); + loop_cnt++; + if (loop_cnt > 100) { + DBG_SDIO_ERR("SDIO_Alloc_Rx_Pkt: Err!! Allocate RX PKT Failed!!\n"); + break; + } + } + }while (NULL == pPkt); + return pPkt; + } + + plist = RtlListGetNext(&pSDIODev->FreeRxPktList); + pPkt = CONTAINER_OF(plist, SDIO_RX_PACKET, list); + + RtlListDelete(&pPkt->list); + RtlUpMutex(&pSDIODev->RxMutex); + return pPkt; +} + +/****************************************************************************** + * Function: SDIO_Free_Rx_Pkt + * Desc: Put a RX Packet Handle back to the queue. + * + * Para: + * pSDIODev: The SDIO device data structor. + * pPkt: The packet handler to be free. + * + ******************************************************************************/ +VOID SDIO_Free_Rx_Pkt( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN PSDIO_RX_PACKET pPkt +) +{ + if (pPkt->isDyna) { + RtlMfree((u8 *)pPkt, sizeof(SDIO_RX_PACKET)); + } + else { + RtlDownMutex(&pSDIODev->RxMutex); + RtlListInsertTail(&pPkt->list, &pSDIODev->FreeRxPktList); + RtlUpMutex(&pSDIODev->RxMutex); + } +} + +/****************************************************************************** + * Function: SDIO_Recycle_Rx_BD + * Desc: To recycle some RX BD when C2H RX DMA done. + * 1. Free the RX packet. + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_Recycle_Rx_BD ( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + SDIO_RX_BD_HANDLE *pRxBdHdl; + SDIO_RX_BD *pRXBD; + u32 PktSize; + u32 FreeCnt=0; // for debugging + + DBG_SDIO_INFO("SDIO_Recycle_Rx_BD==> %d %d\n", HAL_SDIO_READ16(REG_SPDIO_RXBD_C2H_RPTR), pSDIODev->RXBDRPtr); + SDIO_Disable_Interrupt(pSDIODev, BIT_C2H_DMA_OK); + while (HAL_SDIO_READ16(REG_SPDIO_RXBD_C2H_RPTR) != pSDIODev->RXBDRPtr) + { + pRxBdHdl = pSDIODev->pRXBDHdl + pSDIODev->RXBDRPtr; + pRXBD = pSDIODev->pRXBDAddrAligned + pSDIODev->RXBDRPtr; + if (!pRxBdHdl->isFree) { + if (pRxBdHdl->isPktEnd && (NULL != pRxBdHdl->pPkt)) { + /* Free this packet */ + // TODO: The RX_DESC format may needs to be refined + PktSize = pRxBdHdl->pPkt->RxDesc.pkt_len; +#if SDIO_MP_MODE + if ((pSDIODev->MP_CRxPktPendingCnt > 0)) { + pSDIODev->MP_CRxPktPendingCnt--; + } + + if (((pSDIODev->MP_CRxPktCnt == 0) && (pSDIODev->MP_CRxPktPendingCnt == 0)) || + (SDIO_CRX_DYNA_BUF == pSDIODev->MP_ContinueRxMode)) +#endif + { +#if CONFIG_INIC_EN +#if CONFIG_INIC_SKB_RX + dev_kfree_skb_any(pRxBdHdl->pPkt->skb); + pRxBdHdl->pPkt->skb = NULL; +#else + inic_sdio_free_data((u8 *) (pRxBdHdl->pPkt->pData)); +#endif + pRxBdHdl->pPkt->pData = NULL; +#else + RtlMfree((u8 *) (pRxBdHdl->pPkt->pData), (pRxBdHdl->pPkt->Offset+PktSize)); // free packet buffer +#if SDIO_DEBUG + RtlDownMutex(&pSDIODev->StatisticMutex); + pSDIODev->MemAllocCnt--; + RtlUpMutex(&pSDIODev->StatisticMutex); +#endif +#endif +#if SDIO_MP_MODE + pSDIODev->pMP_CRxBuf = NULL; +#endif + } + + _memset((void *)&(pRxBdHdl->pPkt->RxDesc), 0, sizeof(SDIO_RX_DESC)); + RtlDownMutex(&pSDIODev->RxMutex); + RtlListInsertTail(&pRxBdHdl->pPkt->list, &pSDIODev->FreeRxPktList); // Put packet handle to free queue + RtlUpMutex(&pSDIODev->RxMutex); + FreeCnt++; + pRxBdHdl->isPktEnd = 0; + pRxBdHdl->pPkt = NULL; + DBG_SDIO_INFO("SDIO_Recycle_Rx_BD: Recycle Pkt, RXBDRPtr=%d\n", pSDIODev->RXBDRPtr); +#if SDIO_MP_MODE + pSDIODev->MP_RxPktCnt++; + pSDIODev->MP_RxByteCnt += PktSize; + + pSDIODev->MP_RxPktCntInPeriod++; + pSDIODev->MP_RxByteCntInPeriod += PktSize; +#endif + } + _memset((void *)pRXBD , 0, sizeof(SDIO_RX_BD)); // clean this RX_BD + pRxBdHdl->isFree = 1; + } + else { + DBG_SDIO_WARN("SDIO_Recycle_Rx_BD: Warring, Recycle a Free RX_BD,RXBDRPtr=%d\n",pSDIODev->RXBDRPtr); + } + pSDIODev->RXBDRPtr++; + if (pSDIODev->RXBDRPtr >= SDIO_RX_BD_NUM) { + pSDIODev->RXBDRPtr -= SDIO_RX_BD_NUM; + } + } + SDIO_Enable_Interrupt(pSDIODev, BIT_C2H_DMA_OK); + DBG_SDIO_INFO("<==SDIO_Recycle_Rx_BD(%d)\n", FreeCnt); + +} + +/****************************************************************************** + * Function: SDIO_Process_H2C_IOMsg + * Desc: Handle the interrupt for HC2 message ready. Read the H2C_MSG register + * and process the H2C message. + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_Process_H2C_IOMsg( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + u32 H2CMsg; + + // TODO: define H2C message type & format, currently we have 30 bits message only, may needs to extend the HW register + H2CMsg = HAL_SDIO_READ32(REG_SPDIO_CPU_H2C_MSG); + DBG_SDIO_INFO("H2C_MSG: 0x%x\n", H2CMsg); + // TODO: May needs to handle endian free + switch (H2CMsg) + { + default: + break; + } + // TODO: Some H2C message needs to be fordward to WLan driver +} + +/****************************************************************************** + * Function: SDIO_Send_C2H_IOMsg + * Desc: Send C2H message to the Host. + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_Send_C2H_IOMsg( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u32 *C2HMsg +) +{ + u32 TmpC2HMsg; + + // TODO: define C2H message type & format, currently we have 30 bits message only, may needs to extend the HW register + + // TODO: May needs to handle endian free + TmpC2HMsg = HAL_SDIO_READ32(REG_SPDIO_CPU_C2H_MSG); + TmpC2HMsg = ((TmpC2HMsg ^ (u32)BIT(31)) & (u32)BIT(31)) | *C2HMsg; + HAL_SDIO_WRITE32(REG_SPDIO_CPU_C2H_MSG, TmpC2HMsg); +} + +/****************************************************************************** + * Function: SDIO_Process_H2C_PktMsg + * Desc: Handle the packet H2C message which from block write(CMD53). + * + * Para: + * pSDIODev: The SDIO device data structor. + * H2CMsg: point to the buffer of the H2C message received. + ******************************************************************************/ +VOID SDIO_Process_H2C_PktMsg( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u8 *H2CMsg +) +{ + + // TODO: define H2C message type & format + DBG_SDIO_INFO("H2C_MSG: 0x%x\n", *H2CMsg); + // TODO: May needs to handle endian free + // TODO: Some H2C message needs to be fordward to WLan driver +} + +/****************************************************************************** + * Function: SDIO_Send_C2H_PktMsg + * Desc: To send a C2H message to the Host through the block read command. + * + * Para: + * pSDIODev: The SDIO device data structor. + * H2CMsg: point to the buffer of the H2C message received. + * MsgLen: The length of this message. + ******************************************************************************/ +u8 SDIO_Send_C2H_PktMsg( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u8 *C2HMsg, + IN u16 MsgLen +) +{ + u8 *MsgBuf; + PSDIO_RX_DESC pRxDesc; + SDIO_RX_PACKET *pPkt; + + // TODO: define H2C message type & format + DBG_SDIO_INFO("C2H_MSG: 0x%x\n", *C2HMsg); + // TODO: May needs to handle endian free + + MsgBuf = RtlZmalloc(MsgLen); + if (NULL == MsgBuf) { + DBG_SDIO_ERR("SDIO_Send_C2H_PktMsg: Malloc Err!!\n"); + return FAIL; + } + _memcpy((void *)(MsgBuf), (void *)C2HMsg, MsgLen); + + pPkt = SDIO_Alloc_Rx_Pkt(pSDIODev); + if (pPkt == NULL) { + DBG_SDIO_ERR("RX Callback Err!! No Free RX PKT!\n"); + return FAIL; + } + pRxDesc = &pPkt->RxDesc; + pRxDesc->type = SDIO_CMD_C2H; + pRxDesc->pkt_len = MsgLen; + pRxDesc->offset = sizeof(SDIO_RX_DESC); + pPkt->pData = MsgBuf; + pPkt->Offset = 0; + RtlDownMutex(&pSDIODev->RxMutex); + RtlListInsertTail(&pPkt->list, &pSDIODev->RxPktList); + pSDIODev->RxInQCnt++; + RtlUpMutex(&pSDIODev->RxMutex); + SDIO_SetEvent(pSDIODev, SDIO_EVENT_RX_PKT_RDY); +#if !TASK_SCHEDULER_DISABLED + if (pSDIODev->RxInQCnt == 1) { + RtlUpSema(&pSDIODev->RxSema); + } +#else + SDIO_TaskUp(pSDIODev); +#endif + + return SUCCESS; + +} + +#ifdef CONFIG_SOC_PS_MODULE +/****************************************************************************** + * Function: SDIO_Wakeup_From_PG + * Desc: To handle the process of system wakeup from power gated. + * + * Para: None + ******************************************************************************/ +VOID SDIO_Wakeup_From_PG(VOID) +{ + ConfigDebugErr = 0xffffffff; + ConfigDebugInfo = _DBG_SDIO_; + ConfigDebugWarn = _DBG_SDIO_; + + HalCpuClkConfig(CLK_200M); + VectorTableInitRtl8195A(0x1FFFFFFC); + +#if CONFIG_CHIP_C_CUT + HalReInitPlatformLogUartV02(); +#else + PSHalInitPlatformLogUart(); +#endif + +#ifdef CONFIG_TIMER_MODULE +#if CONFIG_CHIP_C_CUT + HalInitPlatformTimerV02(); +#else + HalReInitPlatformTimer(); +#endif +// HalDelayUs(1000); +#endif + + InfraStart(); +} +#endif + +#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1) +VOID SDIO_Pre_Sleep_Callback(u32 expected_idle_time){ + /* Indicate the Host system that the TX/RX is not ready */ + HAL_SDIO_WRITE8(REG_SPDIO_CPU_IND, \ + HAL_SDIO_READ8(REG_SPDIO_CPU_IND)&~BIT_SYSTEM_TRX_RDY_IND); +} +VOID SDIO_Post_Sleep_Callback(u32 expected_idle_time){ + /* Indicate the Host system that the TX/RX is ready */ + HAL_SDIO_WRITE8(REG_SPDIO_CPU_IND, \ + HAL_SDIO_READ8(REG_SPDIO_CPU_IND)|BIT_SYSTEM_TRX_RDY_IND); +} +#endif + +/****************************************************************************** + * Function: SDIO_Process_RPWM + * Desc: To handle RPWM interrupt. + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +u8 SDIO_Process_RPWM( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + u8 rpwm; + + rpwm = HAL_SDIO_READ8(REG_SPDIO_CRPWM); + + DBG_SDIO_INFO ("RPWM1: 0x%x\n", rpwm); + // TODO: forward this RPWM message to WLan + return 0; +} + +/****************************************************************************** + * Function: SDIO_Process_RPWM + * Desc: To handle RPWM interrupt. + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +u8 SDIO_Process_RPWM2( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + u16 rpwm; + u32 reg_value;; + PRAM_FUNCTION_START_TABLE pRamStartFun = (PRAM_FUNCTION_START_TABLE) __ram_start_table_start__; + + rpwm = HAL_SDIO_READ16(REG_SPDIO_CRPWM2); + + DBG_SDIO_INFO ("RPWM2: 0x%x\n", rpwm); + +#ifdef CONFIG_SOC_PS_MODULE + if ((rpwm&RPWM2_TOGGLE_BIT) != (pSDIODev->CRPWM2&RPWM2_TOGGLE_BIT)) { + pSDIODev->CRPWM2 = rpwm; + // Tgoole bit changed, means it's a new RPWM command + if ((rpwm & RPWM2_ACT_BIT) == 0) { + // request to enter sleep mode + pSDIODev->CCPWM2 = HAL_SDIO_READ16(REG_SPDIO_CCPWM2); + pSDIODev->CCPWM2 &= ~(CPWM2_ACT_BIT); + +#if PURE_SDIO_INIC + SDIO_Device_DeInit(pSDIODev); +#endif + if ((rpwm & RPWM2_DSTANDBY_BIT) == 0) { + pSDIODev->CCPWM2 &= ~(CPWM2_DSTANDBY_BIT); + if((rpwm & RPWM2_CG_BIT)){ + //enter clock gated state + pSDIODev->CCPWM2 ^= CPWM2_TOGGLE_BIT; + HAL_SDIO_WRITE16(REG_SPDIO_CCPWM2, pSDIODev->CCPWM2); +#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1) + add_wakeup_event(SLEEP_WAKEUP_BY_SDIO); + register_pre_sleep_callback(SDIO_Pre_Sleep_Callback); + register_post_sleep_callback(SDIO_Post_Sleep_Callback); + release_wakelock(WAKELOCK_SDIO_DEVICE); +#endif + } + else{ + // enter power gated state + if ((rpwm & RPWM2_FBOOT_BIT)) { + pSDIODev->CCPWM2 |= CPWM2_FBOOT_BIT; + // setup the trap to call the wakeup callback when booting + reg_value = HAL_READ32(PERI_ON_BASE, REG_SOC_FUNC_EN); + reg_value |= BIT(29); + HAL_WRITE32(PERI_ON_BASE, REG_SOC_FUNC_EN, reg_value); + // Assign the RAM start address after boot from wakeup + pRamStartFun->RamWakeupFun = SDIO_Wakeup_From_PG; + } + pSDIODev->CCPWM2 ^= CPWM2_TOGGLE_BIT; + HAL_SDIO_WRITE16(REG_SPDIO_CCPWM2, pSDIODev->CCPWM2); + +#if PURE_SDIO_INIC + SleepPG(SLP_SDIO, 0); +#endif + } + } else { + // enter Deep Standby state + pSDIODev->CCPWM2 |= CPWM2_DSTANDBY_BIT; + pSDIODev->CCPWM2 &= ~(CPWM2_FBOOT_BIT); + pSDIODev->CCPWM2 ^= CPWM2_TOGGLE_BIT; + HAL_SDIO_WRITE16(REG_SPDIO_CCPWM2, pSDIODev->CCPWM2); +#if PURE_SDIO_INIC + { + u8 gpio_option, i; + u16 gpio_pin, gpio_en, gpio_act, gpio_lv; + + + gpio_option = 0; + gpio_pin = RPWM2_WKPIN_A5_BIT; + gpio_lv = RPWM2_PIN_A5_LV_BIT; + gpio_en = BIT0; + gpio_act = BIT4; + // Loop 4 to check 4 GPIO wake up event + for (i=0;i<4;i++) { + if (rpwm & gpio_pin) { + gpio_option |= gpio_en; + if (rpwm & gpio_lv) { + // Active High + gpio_option |= gpio_act; + } + } + gpio_pin = gpio_pin << 1; + gpio_lv = gpio_lv << 1; + gpio_en = gpio_en << 1; + gpio_act = gpio_act << 1; + } + + DeepStandby(DSTBY_GPIO, 0, gpio_option); + } +#endif + } +#if !PURE_SDIO_INIC + { + REG_POWER_STATE SDIOPwrState; + u8 HwState; + + SDIOPwrState.FuncIdx = SDIOD; + QueryRegPwrState(SDIOD, &(SDIOPwrState.PwrState), &HwState); + + if (SDIOPwrState.PwrState == ACT) { + SDIOPwrState.PwrState = INACT; + RegPowerState(SDIOPwrState); + } + } +#endif + } else { +#if !PURE_SDIO_INIC + +#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1) + acquire_wakelock(WAKELOCK_SDIO_DEVICE); +#endif + + // Request to Active SDIO iNIC + REG_POWER_STATE SDIOPwrState; + + // Let the power management task know SDIO is in active + SDIOPwrState.FuncIdx = SDIOD; + SDIOPwrState.PwrState = ACT; + RegPowerState(SDIOPwrState); + + pSDIODev->CCPWM2 |= CPWM2_ACT_BIT; + pSDIODev->CCPWM2 ^= CPWM2_TOGGLE_BIT; + HAL_SDIO_WRITE16(REG_SPDIO_CCPWM2, pSDIODev->CCPWM2); +#endif + } + } +#endif // #ifdef CONFIG_SOC_PS_MODULE + return 0; +} + +/****************************************************************************** + * Function: SDIO_Reset_Cmd + * Desc: Handle the SDIO Reset Command interrupt. We did nothing currently. + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_Reset_Cmd( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + // TODO: + return; +} + +/****************************************************************************** + * Function: SDIO_Return_Rx_Data + * Desc: To send all packets in the RX packet list to the Host system via the + * SDIO bus. + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_Return_Rx_Data( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + SDIO_RX_PACKET *pPkt=NULL; + SDIO_RX_DESC *pRxDesc; + SDIO_RX_BD_HANDLE *pRxBdHdl; + _LIST *plist; + SDIO_RX_BD *pRXBD; + u32 Offset=0; + u16 RxBdWrite=0; // to count how much RX_BD used in a Transaction + u16 RxBdRdPtr=0; // RX_BD read pointer + u32 pkt_size; + u8 isForceBreak=0; + u8 isListEmpty; +#if SDIO_RX_PKT_SIZE_OVER_16K + u8 needed_rxbd_num; +#endif + +// DBG_SDIO_INFO("SDIO_Return_Rx_Data==> RXBDWPtr=%d\n", pSDIODev->RXBDWPtr); + RtlDownMutex(&pSDIODev->RxMutex); + if (RtlIsListEmpty(&pSDIODev->RxPktList)) { + RtlUpMutex(&pSDIODev->RxMutex); +// DBG_SDIO_INFO("SDIO_Return_Rx_Data: Queue is empty\n"); + return; + } + + if (pSDIODev->RxFifoBusy) { + RtlUpMutex(&pSDIODev->RxMutex); + SDIO_SetEvent(pSDIODev, SDIO_EVENT_RX_PKT_RDY); + return; + } + RtlUpMutex(&pSDIODev->RxMutex); + + RxBdRdPtr = pSDIODev->RXBDRPtr; + + // since we always need to wait the HW to fetch RX BD done, + // so it seems no need to check the RX BD Read Pointer again +#if 0 + /* Check if we shoule handle the RX_BD recycle ? */ + if (RxBdRdPtr != HAL_SDIO_READ16(REG_SPDIO_RXBD_C2H_RPTR)) { + SDIO_Recycle_Rx_BD(pSDIODev); + RxBdRdPtr = pSDIODev->RXBDRPtr; + } +#endif + do { + /* check if RX_BD available */ + RtlDownMutex(&pSDIODev->RxMutex); + plist = RtlListGetNext(&pSDIODev->RxPktList); + RtlUpMutex(&pSDIODev->RxMutex); + pPkt = CONTAINER_OF(plist, SDIO_RX_PACKET, list); + pRxDesc = &(pPkt->RxDesc); +#if SDIO_RX_PKT_SIZE_OVER_16K + needed_rxbd_num = ((pRxDesc->pkt_len - 1)/MAX_RX_BD_BUF_SIZE) + MIN_RX_BD_SEND_PKT; +#endif + if (RxBdRdPtr != pSDIODev->RXBDWPtr) { + if (pSDIODev->RXBDWPtr > RxBdRdPtr) { +#if SDIO_RX_PKT_SIZE_OVER_16K + if ((pSDIODev->RXBDWPtr - RxBdRdPtr) >= (SDIO_RX_BD_NUM - needed_rxbd_num)) +#else + if ((pSDIODev->RXBDWPtr - RxBdRdPtr) >= (SDIO_RX_BD_NUM - MIN_RX_BD_SEND_PKT)) +#endif + { + DBG_SDIO_WARN("SDIO_Return_Rx_Data: No Available RX_BD, ReadPtr=%d WritePtr=%d\n", \ + RxBdRdPtr, pSDIODev->RXBDWPtr); + isForceBreak = 1; + break; // break the while loop + } + } + else { +#if SDIO_RX_PKT_SIZE_OVER_16K + if ((RxBdRdPtr - pSDIODev->RXBDWPtr) <= needed_rxbd_num) +#else + if ((RxBdRdPtr - pSDIODev->RXBDWPtr) <= MIN_RX_BD_SEND_PKT) +#endif + { + DBG_SDIO_WARN("SDIO_Return_Rx_Data: No Available RX_BD, ReadPtr=%d WritePtr=%d\n", RxBdRdPtr, pSDIODev->RXBDWPtr); + isForceBreak = 1; + break; // break the while loop + } + } + } + + RtlDownMutex(&pSDIODev->RxMutex); + RtlListDelete(&pPkt->list); // remove it from the SDIO RX packet Queue + pSDIODev->RxInQCnt--; + RtlUpMutex(&pSDIODev->RxMutex); + + // TODO: Add RX_DESC before the packet + + /* a SDIO RX packet will use at least 2 RX_BD, the 1st one is for RX_Desc, + other RX_BDs are for packet payload */ + /* Use a RX_BD to transmit RX_Desc */ + pRXBD = pSDIODev->pRXBDAddrAligned + pSDIODev->RXBDWPtr; // get the RX_BD head + pRxBdHdl = pSDIODev->pRXBDHdl + pSDIODev->RXBDWPtr; + if (!pRxBdHdl->isFree) { + DBG_SDIO_ERR("SDIO_Return_Rx_Data: Allocated a non-free RX_BD\n"); + } + pRxBdHdl->isFree = 0; + pRxBdHdl->pPkt = pPkt; + pRXBD->FS = 1; + pRXBD->PhyAddr = (u32)((u8 *)pRxDesc); + pRXBD->BuffSize = sizeof(SDIO_RX_DESC); + pRxBdHdl->isPktEnd = 0; + pSDIODev->RXBDWPtr += 1; + if (pSDIODev->RXBDWPtr >= SDIO_RX_BD_NUM) { + pSDIODev->RXBDWPtr -= SDIO_RX_BD_NUM; + } + RxBdWrite++; + + /* Take RX_BD to transmit packet payload */ + pkt_size = pRxDesc->pkt_len; + Offset = 0; + do { + pRXBD = pSDIODev->pRXBDAddrAligned + pSDIODev->RXBDWPtr; // get the RX_BD head + pRxBdHdl = pSDIODev->pRXBDHdl + pSDIODev->RXBDWPtr; + pRxBdHdl->isFree = 0; + pRxBdHdl->pPkt = pPkt; + pRXBD->FS = 0; + pRXBD->PhyAddr = (u32)(((u8 *)pPkt->pData)+pPkt->Offset); +#if SDIO_RX_PKT_SIZE_OVER_16K + if ((pkt_size - Offset) <= MAX_RX_BD_BUF_SIZE) { + pRXBD->BuffSize = pkt_size - Offset; + pRxBdHdl->isPktEnd = 1; + } + else { + pRXBD->BuffSize = MAX_RX_BD_BUF_SIZE; + pRxBdHdl->isPktEnd = 0; + DBG_SDIO_INFO("SDIO_Return_Rx_Data: Split RX_BD, Offset=%d PktSize=%d\n", \ + Offset, pkt_size); + } +#else + if (pkt_size > MAX_RX_BD_BUF_SIZE) { + // if come to here, please enable "SDIO_RX_PKT_SIZE_OVER_16K" + DBG_SDIO_ERR("SDIO_Return_Rx_Data: The Packet Size bigger than 16K\n"); + pkt_size = MAX_RX_BD_BUF_SIZE; + } + pRXBD->BuffSize = pkt_size; + pRxBdHdl->isPktEnd = 1; +#endif + Offset += pRXBD->BuffSize; + // Move the RX_BD Write pointer forward + RxBdWrite++; + pSDIODev->RXBDWPtr += 1; + if (pSDIODev->RXBDWPtr >= SDIO_RX_BD_NUM) { + pSDIODev->RXBDWPtr -= SDIO_RX_BD_NUM; + } + + if (Offset >= pkt_size) { + pRXBD->LS = 1; +// HAL_SDIO_WRITE16(REG_SPDIO_RXBD_C2H_WPTR, pSDIODev->RXBDWPtr); +// HAL_SDIO_WRITE8(REG_SPDIO_HCI_RX_REQ, BIT_HCI_RX_REQ); +// DBG_SDIO_INFO("SDIO_Return_Rx_Data:RXBDWPtr=%d\n", pSDIODev->RXBDWPtr); + } + } while (Offset < pkt_size); + + if (RxBdWrite >= (SDIO_RX_BD_NUM - MIN_RX_BD_SEND_PKT)) { + isForceBreak = 1; + break; // break the while loop + } + + RtlDownMutex(&pSDIODev->RxMutex); + isListEmpty = RtlIsListEmpty(&pSDIODev->RxPktList); + RtlUpMutex(&pSDIODev->RxMutex); + } while(!isListEmpty); + + if (RxBdWrite > 0) { + RtlDownMutex(&pSDIODev->RxMutex); + HAL_SDIO_WRITE16(REG_SPDIO_RXBD_C2H_WPTR, pSDIODev->RXBDWPtr); + HAL_SDIO_WRITE8(REG_SPDIO_HCI_RX_REQ, BIT_HCI_RX_REQ); + pSDIODev->RxFifoBusy = 1; + RtlUpMutex(&pSDIODev->RxMutex); + } + + if (isForceBreak) { +// SDIO_Recycle_Rx_BD(pSDIODev); + // function end with insufficient resource, set event to try again later + SDIO_SetEvent(pSDIODev, SDIO_EVENT_RX_PKT_RDY); +#if !TASK_SCHEDULER_DISABLED + RtlMsleepOS(1); // no resource, sleep a while + RtlUpSema(&pSDIODev->RxSema); +#else + SDIO_TaskUp(pSDIODev); +#endif + } + DBG_SDIO_INFO("SDIO_Return_Rx_Data(%d)<==\n", RxBdWrite); + +} + +/****************************************************************************** + * Function: SDIO_Register_Tx_Callback + * Desc: For a TX data target driver to register its TX callback function, so + * the SDIO driver can use it to fordward a TX packet to the target driver. + * + * Para: + * pSDIODev: point to the SDIO device handler + * CallbackFun: The function pointer of the callback + * pAdapter: a pointer will be use to call the registered CallBack function. + * It can be used to point to a handler of the caller, like WLan + * Adapter. + ******************************************************************************/ +VOID SDIO_Register_Tx_Callback( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN s8 (*CallbackFun)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize), + IN VOID *pAdapter +) +{ + pSDIODev->Tx_Callback = CallbackFun; + pSDIODev->pTxCb_Adapter = pAdapter; +} + +/****************************************************************************** + * Function: SDIO_Rx_Callback + * Desc: The callback function for an packet receiving, which be called from + * the Target (WLan) driver to send a packet to the SDIO host. + * + * Para: + * pSDIODev: Point to the SDIO device data structer. + * pData: Point to the head of the data to be return to the Host system. + * Length: The length of the data to be send, in byte. + * + * Return: + * The result, SUCCESS or FAIL. + ******************************************************************************/ +s8 SDIO_Rx_Callback( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN VOID *pData, + IN u16 Offset, + IN u16 PktSize, + IN u8 CmdType +) +{ + PSDIO_RX_DESC pRxDesc; + SDIO_RX_PACKET *pPkt; +#if CONFIG_INIC_EN +#if CONFIG_INIC_SKB_RX + struct sk_buff *skb = (struct sk_buff *)pData; +#endif +#endif + + pPkt = SDIO_Alloc_Rx_Pkt(pSDIODev); + if (pPkt == NULL) { + DBG_SDIO_ERR("RX Callback Err!! No Free RX PKT!\n"); + return FAIL; + } + pRxDesc = &pPkt->RxDesc; + pRxDesc->type = CmdType; + pRxDesc->pkt_len = PktSize; +#if CONFIG_INIC_EN +#if CONFIG_INIC_SKB_RX + pRxDesc->offset = sizeof(SDIO_RX_DESC)+Offset;//for data alignment reason + pPkt->skb = skb; + pPkt->pData = skb->data; + pPkt->Offset = 0; +#else //CONFIG_INIC_SKB_RX + pRxDesc->offset = sizeof(SDIO_RX_DESC); + pPkt->pData = pData; + pPkt->Offset = Offset; +#endif//CONFIG_INIC_SKB_RX +#else //CONFIG_INIC_EN + pRxDesc->offset = sizeof(SDIO_RX_DESC); + pPkt->pData = pData; + pPkt->Offset = Offset; +#endif //CONFIG_INIC_EN + RtlDownMutex(&pSDIODev->RxMutex); + RtlListInsertTail(&pPkt->list, &pSDIODev->RxPktList); + pSDIODev->RxInQCnt++; + RtlUpMutex(&pSDIODev->RxMutex); + SDIO_SetEvent(pSDIODev, SDIO_EVENT_RX_PKT_RDY); +#if !TASK_SCHEDULER_DISABLED + if (pSDIODev->RxInQCnt == 1) { + RtlUpSema(&pSDIODev->RxSema); + } +#else + SDIO_TaskUp(pSDIODev); +#endif + + return SUCCESS; +} + +/****************************************************************************** + * Function: SDIO_Handle_MsgBlk + * Desc: Process a message block. + * + * Para: + * pSDIODev: Point to the SDIO device data structer. + * MSG_BLK: The message block to be processed. + * Length: The length of the data to be send, in byte. + * + * Return: + * The result, SUCCESS or FAIL. + ******************************************************************************/ +s8 SDIO_Handle_MsgBlk( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN MSG_BLK *pMblk +) +{ + s8 ret=SUCCESS; + + DBG_SDIO_INFO("SDIO_Handle_MsgBlk==> MsgType=%d\n", pMblk->MsgType); + switch (pMblk->MsgType) { + case MSG_SDIO_RX_PKT: + ret = SDIO_Rx_Callback(pSDIODev, pMblk->pBuf, pMblk->Reserved, pMblk->DateLen, SDIO_CMD_RX_ETH); //pMblk->Reserved = Offset + if (SUCCESS != ret) { + // failed to send this packet to the host, drop it + RtlMfree((u8 *) pMblk->pBuf, (pMblk->Reserved + pMblk->DateLen)); // pMblk->Reserved = Offset +#if SDIO_DEBUG + RtlDownMutex(&pSDIODev->StatisticMutex); + pSDIODev->MemAllocCnt--; + RtlUpMutex(&pSDIODev->StatisticMutex); +#endif +#if SDIO_MP_MODE + pSDIODev->MP_RxDropCnt++; +#endif + } + break; + + case MSG_SDIO_C2H: + break; + + case MSG_SDIO_RPWM: + break; + + default: + DBG_SDIO_WARN("SDIO_Handle_MsgBlk: UnKnown MsgType %d\n", pMblk->MsgType); + break; + } + + return ret; +} + +#if SDIO_MP_MODE + +/****************************************************************************** + * Function: SDIO_PeriodicalTimerCallback + * Desc: The callback function of the 1 Sec timer. It be used to statistic the + * throughput and update the status or something need to do periodically. + * + * Para: + * pContex: this pointer actually is the pointer of the SDIO device. + * + * Return: None + ******************************************************************************/ +VOID SDIO_PeriodicalTimerCallback( + void *pContex +) +{ + PHAL_SDIO_ADAPTER pSDIODev = pContex; + + if (SDIO_IsEventPending(pSDIODev, SDIO_EVENT_DUMP)) { + SDIO_StatisticDump(pSDIODev); +} +} + +#if !TASK_SCHEDULER_DISABLED +/****************************************************************************** + * Function: SDIO_MP_Task + * Desc: The SDIO MP test task handler. This is the main function of the SDIO + * device MP test mode. + * + * Para: + * pSDIODev: The SDIO device data structor. + ******************************************************************************/ +VOID SDIO_MP_Task( + IN VOID *pData +) +{ + PHAL_SDIO_ADAPTER pSDIODev = pData; + MSG_BLK Mblk_r; + MSG_BLK Mblk_w; + SDIO_MP_RX_PACKET *pRxPkt; + _LIST *plist; + int malloc_err_cnt=0; + + DiagPrintf("SDIO_MP_Task Started...\n"); + RtlInitListhead(&pSDIODev->MP_RxPktList); + + /* Initial resource */ + for (;;) + { + /* Task blocked and wait the semaphore(events) here */ + RtlDownSema(&pSDIODev->MP_EventSema); + /* handle message block in the mailbox */ + do { + if (_SUCCESS == RtlMailboxReceive(MBOX_ID_SDIO_MP, &Mblk_r, MBOX_WAIT_NONE, 0)) { + switch (Mblk_r.MsgType) { + case MSG_SDIO_MP_LOOP_TXPKT: + pRxPkt = NULL; + malloc_err_cnt = 0; + do { + pRxPkt = (SDIO_MP_RX_PACKET *)RtlZmalloc(sizeof(SDIO_MP_RX_PACKET)); + if (NULL != pRxPkt) { + pRxPkt->pData = Mblk_r.pBuf; + pRxPkt->Offset = Mblk_r.Reserved; + pRxPkt->DataLen = Mblk_r.DateLen; + RtlListInsertTail(&pRxPkt->list, &pSDIODev->MP_RxPktList); + } + else { + RtlMsleepOS(10); + malloc_err_cnt++; + if (malloc_err_cnt > 100) { + DBG_SDIO_ERR("SDIO_MP_Task: Malloc for Rx Pkt Failed\n"); + // no memory to handle this packet, drop it + RtlMfree(Mblk_r.pBuf, (Mblk_r.Reserved+Mblk_r.DateLen)); + pSDIODev->MP_RxDropCnt++; +#if SDIO_DEBUG + RtlDownMutex(&pSDIODev->StatisticMutex); + pSDIODev->MemAllocCnt--; + RtlUpMutex(&pSDIODev->StatisticMutex); +#endif + break; // break the while loop + } + } + }while (NULL == pRxPkt); + break; + + default: + DBG_SDIO_WARN("SDIO_MP_TASK: UnKnown MsgType %d\n", Mblk_r.MsgType); + break; + } + } + else { + break; // no more message pending, break the while loop + } + } while (1); + + while (!RtlIsListEmpty(&pSDIODev->MP_RxPktList)) { + plist = RtlListGetNext(&pSDIODev->MP_RxPktList); + pRxPkt = CONTAINER_OF(plist, SDIO_MP_RX_PACKET, list); + RtlListDelete(&pRxPkt->list); + + Mblk_w.MsgType = MSG_SDIO_RX_PKT; + Mblk_w.pBuf = pRxPkt->pData; + Mblk_w.Reserved = pRxPkt->Offset; + Mblk_w.DateLen = pRxPkt->DataLen; + if (_SUCCESS != RtlMailboxSendToBack(MBOX_ID_SDIO, &Mblk_w, 2000, 0)) { + DBG_SDIO_ERR("SDIO_MP_Task: Send MSG_SDIO_RX_PKT FAILED\n"); + RtlListInsertHead(&pRxPkt->list, &pSDIODev->MP_RxPktList); + break; + } + else { + RtlMfree((u8 *)pRxPkt, sizeof(SDIO_MP_RX_PACKET)); + } + } + + RtlEnterCritical(); + if (pSDIODev->MP_Events & SDIO_EVENT_EXIT) { + pSDIODev->MP_Events &= ~SDIO_EVENT_EXIT; + RtlExitCritical(); + DBG_SDIO_INFO("SDIO_MP_Task Exiting...\n"); + break; // break the loop to exit the task + } + RtlExitCritical(); + } + + RtlEnterCritical(); + pSDIODev->MP_Events |= SDIO_EVENT_MP_STOPPED; + RtlExitCritical(); + DBG_SDIO_INFO("SDIO_MP_Task Stoped!\n"); +#if ( INCLUDE_vTaskDelete == 1 ) + vTaskDelete(NULL); +#endif +} +#endif // end of "#if !TASK_SCHEDULER_DISABLED" + +/****************************************************************************** + * Function: SDIO_MapMPCmd + * Desc: Map a MP command string to a MP command type. + * + * Para: + * CmdStr: point to the command string buffer + * + * return: + * The MP command type + * + ******************************************************************************/ +u8 SDIO_MapMPCmd( + IN char *CmdStr, + IN u16 *Offset +) +{ + char cmd_str[16]; + u16 i; + u16 str_len=0; + u16 entry_num; + u8 mp_cmd=0xff; + + for (i=0;i<16;i++) { + if ((' ' != *(CmdStr+i)) && ('=' != *(CmdStr+i)) && (*(CmdStr+i))) { + cmd_str[i] = *(CmdStr+i); + str_len++; + } + else { + break; + } + } + + *Offset = str_len+1; + + entry_num = sizeof(SDIO_MPCmdTable)/sizeof(SDIO_MP_CMD); + + for (i=0;iMP_ModeEn); + DiagPrintf("MP_Loopback=%d\n", pSDIODev->MP_LoopBackEn); + DiagPrintf("TX: Packet Count=%d, Byte Count=%d\n", pSDIODev->MP_TxPktCnt, pSDIODev->MP_TxByteCnt); + DiagPrintf("TX: TX_BD_WPTR=%d, TX_BD_RPTR=%d\n", HAL_SDIO_READ16(REG_SPDIO_TXBD_WPTR), HAL_SDIO_READ16(REG_SPDIO_TXBD_RPTR)); + DiagPrintf("RX: Packet Count=%d, Byte Count=%d\n", pSDIODev->MP_RxPktCnt, pSDIODev->MP_RxByteCnt); + DiagPrintf("RX: RXBDWPtr=%d, RXBDRPtr=%d\n", pSDIODev->RXBDWPtr, pSDIODev->RXBDRPtr); +#if SDIO_DEBUG + DiagPrintf("RX: InQueueCount=%d MemAllocatedCnt=%d\n", pSDIODev->RxInQCnt, pSDIODev->MemAllocCnt); +#endif + DiagPrintf("TxDropPkt=%d RxDropPkt=%d\n", pSDIODev->MP_TxDropCnt, pSDIODev->MP_RxDropCnt); +} + +/****************************************************************************** + * Function: SDIO_StatisticDump + * Desc: Periodical dump SDIO throughput and other status. + * + * Para: + * pSDIODev: The SDIO device data structor. + * + * return: None + * + ******************************************************************************/ +VOID SDIO_StatisticDump( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + unsigned long tp; // throughput + u32 oldest_byte_cnt; + u32 tx_avg_tp=0; // in Kbps + u32 rx_avg_tp=0; // in Kbps + + // calculate the TX throughput + if (pSDIODev->TxAvgWinCnt >= SDIO_AVG_TP_WIN_SIZE) { + // flush the oldest one and add the newest one + oldest_byte_cnt = pSDIODev->MP_TxAvgTPWin[pSDIODev->OldestTxAvgWinIdx]; + + if (pSDIODev->MP_TxAvgTPWinSum >= oldest_byte_cnt) { + pSDIODev->MP_TxAvgTPWinSum -= oldest_byte_cnt; + pSDIODev->MP_TxAvgTPWin[pSDIODev->OldestTxAvgWinIdx] = pSDIODev->MP_TxByteCntInPeriod; + pSDIODev->OldestTxAvgWinIdx++; + if (SDIO_AVG_TP_WIN_SIZE <= pSDIODev->OldestTxAvgWinIdx) { + pSDIODev->OldestTxAvgWinIdx = 0; + } + + if (0 == pSDIODev->MP_TxAvgTPWinSum) { + // reset the statistic + pSDIODev->TxAvgWinCnt = 0; + pSDIODev->OldestTxAvgWinIdx = 0; + } + } + else { + pSDIODev->MP_TxAvgTPWinSum = 0; + // reset the statistic + if (pSDIODev->MP_TxByteCntInPeriod > 0) + pSDIODev->TxAvgWinCnt = 1; + else + pSDIODev->TxAvgWinCnt = 0; + pSDIODev->OldestTxAvgWinIdx = 0; + } + pSDIODev->MP_TxAvgTPWinSum += pSDIODev->MP_TxByteCntInPeriod; + tx_avg_tp = (pSDIODev->MP_TxAvgTPWinSum << 3) / (SDIO_PERIODICAL_TIMER_INTERVAL * SDIO_AVG_TP_WIN_SIZE); + } + else { + if ((pSDIODev->MP_TxAvgTPWinSum > 0) || (pSDIODev->MP_TxByteCntInPeriod > 0)) { + pSDIODev->MP_TxAvgTPWinSum += pSDIODev->MP_TxByteCntInPeriod; + pSDIODev->MP_TxAvgTPWin[pSDIODev->TxAvgWinCnt] = pSDIODev->MP_TxByteCntInPeriod; + pSDIODev->TxAvgWinCnt++; + tx_avg_tp = (pSDIODev->MP_TxAvgTPWinSum << 3) / (SDIO_PERIODICAL_TIMER_INTERVAL * pSDIODev->TxAvgWinCnt); + } + } + + // calculate the RX throughput + if (pSDIODev->RxAvgWinCnt >= SDIO_AVG_TP_WIN_SIZE) { + // flush the oldest one and add the newest one + oldest_byte_cnt = pSDIODev->MP_RxAvgTPWin[pSDIODev->OldestRxAvgWinIdx]; + if (pSDIODev->MP_RxAvgTPWinSum >= oldest_byte_cnt) { + pSDIODev->MP_RxAvgTPWinSum -= oldest_byte_cnt; + pSDIODev->MP_RxAvgTPWin[pSDIODev->OldestRxAvgWinIdx] = pSDIODev->MP_RxByteCntInPeriod; + pSDIODev->OldestRxAvgWinIdx++; + if (SDIO_AVG_TP_WIN_SIZE <= pSDIODev->OldestRxAvgWinIdx) { + pSDIODev->OldestRxAvgWinIdx = 0; + } + + if (0 == pSDIODev->MP_RxAvgTPWinSum) { + // reset the statistic + pSDIODev->RxAvgWinCnt = 0; + pSDIODev->OldestRxAvgWinIdx = 0; + } + } + else { + pSDIODev->MP_RxAvgTPWinSum = 0; + // reset the statistic + if (pSDIODev->MP_RxByteCntInPeriod > 0) + pSDIODev->RxAvgWinCnt = 1; + else + pSDIODev->RxAvgWinCnt = 0; + + pSDIODev->OldestRxAvgWinIdx = 0; + } + pSDIODev->MP_RxAvgTPWinSum += pSDIODev->MP_RxByteCntInPeriod; + + rx_avg_tp = (pSDIODev->MP_RxAvgTPWinSum << 3) / (SDIO_PERIODICAL_TIMER_INTERVAL * SDIO_AVG_TP_WIN_SIZE); + } + else { + if ((pSDIODev->MP_RxAvgTPWinSum > 0) || (pSDIODev->MP_RxByteCntInPeriod > 0)) { + pSDIODev->MP_RxAvgTPWinSum += pSDIODev->MP_RxByteCntInPeriod; + pSDIODev->MP_RxAvgTPWin[pSDIODev->RxAvgWinCnt] = pSDIODev->MP_RxByteCntInPeriod; + pSDIODev->RxAvgWinCnt++; + rx_avg_tp = (pSDIODev->MP_RxAvgTPWinSum << 3) / (SDIO_PERIODICAL_TIMER_INTERVAL * pSDIODev->RxAvgWinCnt); + } + } + + if ((pSDIODev->MP_TxByteCntInPeriod > 0) || (pSDIODev->MP_RxByteCntInPeriod > 0)) { + DiagPrintf("SDIO Dump:\n"); + tp = (pSDIODev->MP_TxByteCntInPeriod << 3)/(SDIO_PERIODICAL_TIMER_INTERVAL/1000); + if (tp > 1000) { + DiagPrintf("TX: Packet Count=%d, Byte Count=%d, TP=%d Kbps\n", pSDIODev->MP_TxPktCntInPeriod, pSDIODev->MP_TxByteCntInPeriod, tp/1000); + } + else { + DiagPrintf("TX: Packet Count=%d, Byte Count=%d, TP=%d bps\n", pSDIODev->MP_TxPktCntInPeriod, pSDIODev->MP_TxByteCntInPeriod, tp); + } + tp = (pSDIODev->MP_RxByteCntInPeriod << 3)/(SDIO_PERIODICAL_TIMER_INTERVAL/1000); + if (tp > 1000) { + DiagPrintf("RX: Packet Count=%d, Byte Count=%d, TP=%d Kbps\n", pSDIODev->MP_RxPktCntInPeriod, pSDIODev->MP_RxByteCntInPeriod, tp/1000); + } + else { + DiagPrintf("RX: Packet Count=%d, Byte Count=%d, TP=%d bps\n", pSDIODev->MP_RxPktCntInPeriod, pSDIODev->MP_RxByteCntInPeriod, tp); + } + + pSDIODev->MP_TxPktCntInPeriod = 0; + pSDIODev->MP_TxByteCntInPeriod = 0; + pSDIODev->MP_RxPktCntInPeriod = 0; + pSDIODev->MP_RxByteCntInPeriod = 0; + } + + if ((tx_avg_tp > 0) || (rx_avg_tp > 0)) { + DiagPrintf("TX Avg TP=%d Kbps, RX Avg TP=%d Kbps\n", tx_avg_tp, rx_avg_tp); + } +} + +/****************************************************************************** + * Function: SDIO_MP_Loopback + * Desc: The loopback test function for MP mode. + * + * Para: + * pAdapter: a pointer which got from the callback function register, + * here it point to the SDIO device itself. + * pData: The pointer of the SDIO TX data buffer. + * PktSize: The size (in byte) of this SDIO TX data. + * + * return: + * The result of this function, SUCCESS or FAILED. + * + ******************************************************************************/ +s8 SDIO_MP_Loopback( + IN VOID *pAdapter, + IN u8 *pData, + IN u16 Offset, + IN u16 PktSize +) +{ +#if TASK_SCHEDULER_DISABLED + PHAL_SDIO_ADAPTER pSDIODev=(PHAL_SDIO_ADAPTER)pAdapter; +#endif + s8 ret; + + MSG_BLK MBlk; + +// DBG_SDIO_INFO("SDIO_MP_Loopback==>\n"); + + +#if TASK_SCHEDULER_DISABLED + ret = SDIO_Rx_Callback(pSDIODev, pData, Offset, PktSize, SDIO_CMD_RX_ETH); +#else + // Mailbox test, use message to replace call SDIO_Rx_Callback directly + MBlk.MsgType = MSG_SDIO_MP_LOOP_TXPKT; + MBlk.pBuf = pData; + MBlk.Reserved = (u8)Offset; + MBlk.DateLen = PktSize; + if (_SUCCESS == RtlMailboxSendToBack(MBOX_ID_SDIO_MP, &MBlk, 2000, 0)) { + ret = SUCCESS; + } + else { + DBG_SDIO_ERR("SDIO_MP_Loopback FAILED\n"); + ret = FAIL; + } +#endif + return ret; +} + +/****************************************************************************** + * Function: SDIO_MP_ContinueTx + * Desc: The continue TX test function for MP mode. We just drop the TX packet. + * + * Para: + * pAdapter: a pointer which got from the callback function register, + * here it point to the SDIO device itself. + * pData: The pointer of the SDIO TX data buffer. + * PktSize: The size (in byte) of this SDIO TX data. + * + * return: + * The result of this function, SUCCESS or FAILED. + * + ******************************************************************************/ +s8 SDIO_MP_ContinueTx( + IN VOID *pAdapter, + IN u8 *pData, + IN u16 Offset, + IN u16 PktSize +) +{ + PHAL_SDIO_ADAPTER pSDIODev=(PHAL_SDIO_ADAPTER)pAdapter; + + RtlMfree(pData, (Offset+PktSize)); +#if SDIO_DEBUG + RtlDownMutex(&pSDIODev->StatisticMutex); + pSDIODev->MemAllocCnt--; + RtlUpMutex(&pSDIODev->StatisticMutex); +#endif + return SUCCESS; +} + +/****************************************************************************** + * Function: SDIO_MP_ContinueRx + * Desc: Process Continue RX test. + * + * Para: + * pSDIODev: The SDIO device adapter. + * + * return: None + * + ******************************************************************************/ +VOID SDIO_MP_ContinueRx( + IN PHAL_SDIO_ADAPTER pSDIODev +) +{ + u8 *pRxBuf=NULL; + s8 ret; + + while (1) { + if (pSDIODev->MP_CRxPktPendingCnt > 10) { + break; + } + + if (pSDIODev->MP_ContinueRxMode == SDIO_CRX_STATIC_BUF) { + pRxBuf = pSDIODev->pMP_CRxBuf; + } + else if (pSDIODev->MP_ContinueRxMode == SDIO_CRX_DYNA_BUF) { + pRxBuf = RtlMalloc(pSDIODev->MP_CRxSize+26); // 26: Wlan header +#if SDIO_DEBUG + pSDIODev->MemAllocCnt++; +#endif + if (NULL != pRxBuf) { + _memcpy(pRxBuf, MP_WlanHdr, 26); + _memset((pRxBuf+26), 0x3E, pSDIODev->MP_CRxSize); + } + } + + if (NULL != pRxBuf) { + ret = SDIO_Rx_Callback(pSDIODev, pRxBuf, 0, pSDIODev->MP_CRxSize+26, SDIO_CMD_RX_ETH); + if (SUCCESS == ret) { + if (pSDIODev->MP_CRxPktCnt > 0) { + pSDIODev->MP_CRxPktCnt--; + pSDIODev->MP_CRxPktPendingCnt++; + if (0 == pSDIODev->MP_CRxPktCnt) { + pSDIODev->MP_ContinueRx = 0; + break; // break the while loop + } + } + if (pSDIODev->MP_CRxPktPendingCnt > 10) { + break; + } + } + else { + if (pSDIODev->MP_ContinueRxMode == SDIO_CRX_DYNA_BUF) { + RtlMfree(pRxBuf, pSDIODev->MP_CRxSize+26); +#if SDIO_DEBUG + pSDIODev->MemAllocCnt--; +#endif + } +#if !TASK_SCHEDULER_DISABLED + RtlMsleepOS(10); // no resource, sleep a while + RtlUpSema(&pSDIODev->RxSema); +#else + SDIO_TaskUp(pSDIODev); +#endif + break; + } + } + else { +#if !TASK_SCHEDULER_DISABLED + RtlMsleepOS(10); // no resource, sleep a while + RtlUpSema(&pSDIODev->RxSema); +#else + SDIO_TaskUp(pSDIODev); +#endif + break; + } + } +} + +/****************************************************************************** + * Function: SDIO_DeviceMPApp + * Desc: To handle SDIO MP command + * + * Para: + * pData: point to the command buffer + * + ******************************************************************************/ +VOID SDIO_DeviceMPApp( + IN PHAL_SDIO_ADAPTER pSDIODev, + IN u16 argc, + IN u8 *argv[] +) +{ + u8 cmd_type; + u16 offset=0; + u32 arg1, arg2; + int ret; + int i; + + DBG_SDIO_INFO("==>MP_App: arg_num=%d cmd_str=%s\n", argc, (char *)argv[0]); + + cmd_type = SDIO_MapMPCmd((char *)argv[0], &offset); + DBG_SDIO_INFO("MP_App: MP_Cmdtype=%d\n", cmd_type); + + switch (cmd_type) + { + case SDIO_MP_START: + if (!pSDIODev->MP_ModeEn) { + pSDIODev->MP_ModeEn = 1; + pSDIODev->MP_TxPktCnt = 0; /* SDIO TX packet count */ + pSDIODev->MP_RxPktCnt = 0; /* SDIO RX packet count */ + pSDIODev->MP_TxByteCnt = 0; /* SDIO TX Byte count */ + pSDIODev->MP_RxByteCnt = 0; /* SDIO RX Byte count */ + DiagPrintf("SDIO MP Started!\n"); + } + else { + DiagPrintf("In SDIO MP Mode already!\n"); + } + break; + + case SDIO_MP_STOP: + pSDIODev->MP_ModeEn = 0; + DiagPrintf("SDIO MP Stoped!\n"); + break; + + case SDIO_MP_LOOPBACK: + DBG_SDIO_INFO("MP_App: argv[1]=%s\n", argv[1]); + if (pSDIODev->MP_ModeEn == 0) { + DiagPrintf("Not in MP mode!! Please start MP mode first.\n"); + break; + } + arg1 = Strtoul((const u8*)(argv[1]), (u8 **)NULL, 10); + if (arg1) { + if (pSDIODev->MP_LoopBackEn == 0) { + // Create a Task for MP loopback test +#if !TASK_SCHEDULER_DISABLED + RtlInitSema(&(pSDIODev->MP_EventSema), 0); + if (NULL == pSDIODev->MP_EventSema){ + DBG_SDIO_ERR("SDIO MP_Loopback Create Semaphore Err!!\n"); + break; // break the switch case + } + + /* create a Mailbox for other driver module to send message to SDIO driver */ + pSDIODev->pMP_MBox = RtlMailboxCreate(MBOX_ID_SDIO_MP, SDIO_MAILBOX_SIZE, &(pSDIODev->MP_EventSema)); + if (NULL == pSDIODev->pMBox) { + DBG_SDIO_ERR("SDIO MP_Loopback Create Mailbox Err!!\n"); + break; // break the switch case + } + + /* Create the SDIO task */ +#ifdef PLATFORM_FREERTOS + ret = xTaskCreate( SDIO_MP_Task, "SDIO_MP_TASK", ((256*4)/sizeof(portBASE_TYPE)), (void *)pSDIODev, SDIO_MP_TASK_PRIORITY, &pSDIODev->MP_TaskHandle); + if (pdTRUE != ret ) + { + DBG_SDIO_ERR("SDIO MP Create Task Err(%d)!!\n", ret); + break; + } +#endif + DiagPrintf("SDIO MP Task Created\n"); +#endif // end of "#if !TASK_SCHEDULER_DISABLED" + + // Backup origional TX Callback function + pSDIODev->pTxCallback_Backup = pSDIODev->Tx_Callback; + pSDIODev->pTxCb_Adapter_Backup = (VOID *)pSDIODev->pTxCb_Adapter; + DiagPrintf("Register SDIO TX Callback with Loopback function\n"); + SDIO_Register_Tx_Callback(pSDIODev, &SDIO_MP_Loopback, (VOID *) pSDIODev); + pSDIODev->MP_LoopBackEn = 1; + } + else { + DiagPrintf("SDIO MP LoopBack is On already!\n"); + } + } + else { + if (pSDIODev->MP_LoopBackEn) { + // Restore origional TX Callback function + DiagPrintf("Restore SDIO TX Callback...\n"); + SDIO_Register_Tx_Callback(pSDIODev, pSDIODev->pTxCallback_Backup, pSDIODev->pTxCb_Adapter_Backup); + pSDIODev->MP_LoopBackEn = 0; +#if !TASK_SCHEDULER_DISABLED + /* Exit the SDIO task */ + if (pSDIODev->MP_TaskHandle) { + RtlEnterCritical(); + pSDIODev->MP_Events |= SDIO_EVENT_EXIT; + RtlExitCritical(); + RtlUpSema(&pSDIODev->MP_EventSema); + i=0; + while (1) { + RtlEnterCritical(); + if (pSDIODev->MP_Events & SDIO_EVENT_MP_STOPPED) { + RtlExitCritical(); + break; + } + RtlExitCritical(); + RtlMsleepOS(10); + i++; + if (i> 100) { + DBG_SDIO_ERR("Delete SDIO MP Task Failed with Timeout\n"); + break; + } + } + } + + /* Delete the Mailbox */ + if (pSDIODev->pMP_MBox) { + RtlMailboxDel(pSDIODev->pMP_MBox); + pSDIODev->pMP_MBox = NULL; + } + + /* Delete the Semaphore */ + if (pSDIODev->MP_EventSema) { + RtlFreeSema(&pSDIODev->MP_EventSema); + pSDIODev->MP_EventSema = NULL; + } + DiagPrintf("SDIO MP Task Deleted\n"); +#endif + + } + } + DiagPrintf("SDIO MP LoopBack=%d\n", pSDIODev->MP_LoopBackEn); + break; + + case SDIO_MP_STATUS: + SDIO_DumpMPStatus(pSDIODev); + break; + + case SDIO_MP_READ_REG8: + arg1 = Strtoul((const u8*)(argv[1]), (u8 **)NULL, 16); + DiagPrintf("SDIO_Reg[%x]=%x\n", arg1, HAL_SDIO_READ8(arg1)); + break; + + case SDIO_MP_READ_REG16: + arg1 = Strtoul((const u8*)(argv[1]), (u8 **)NULL, 16); + DiagPrintf("SDIO_Reg[%x]=%x\n", arg1, HAL_SDIO_READ16(arg1)); + break; + + case SDIO_MP_READ_REG32: + arg1 = Strtoul((const u8*)(argv[1]), (u8 **)NULL, 16); + DiagPrintf("SDIO_Reg[%x]=%x\n", arg1, HAL_SDIO_READ32(arg1)); + break; + + case SDIO_MP_WRITE_REG8: + arg1 = Strtoul((const u8*)(argv[1]), (u8 **)NULL, 16); + arg2 = Strtoul((const u8*)(argv[2]), (u8 **)NULL, 16); + HAL_SDIO_WRITE8(arg1, arg2); + DiagPrintf("Write Reg[%x]=%x, Readback:%x\n", arg1, arg2, HAL_SDIO_READ8(arg1)); + break; + + case SDIO_MP_WRITE_REG16: + arg1 = Strtoul((const u8*)(argv[1]), (u8 **)NULL, 16); + arg2 = Strtoul((const u8*)(argv[2]), (u8 **)NULL, 16); + HAL_SDIO_WRITE16(arg1, arg2); + DiagPrintf("Write Reg[%x]=%x, Readback:%x\n", arg1, arg2, HAL_SDIO_READ16(arg1)); + break; + + case SDIO_MP_WRITE_REG32: + arg1 = Strtoul((const u8*)(argv[1]), (u8 **)NULL, 16); + arg2 = Strtoul((const u8*)(argv[2]), (u8 **)NULL, 16); + HAL_SDIO_WRITE32(arg1, arg2); + DiagPrintf("Write Reg[%x]=%x, Readback:%x\n", arg1, arg2, HAL_SDIO_READ32(arg1)); + break; + + case SDIO_MP_WAKEUP: + SDIO_Wakeup_Task(pSDIODev); + break; + + case SDIO_MP_DUMP: + arg1 = Strtoul((const u8*)(argv[1]), (u8 **)NULL, 10); + if (arg1) { + if (!SDIO_IsEventPending(pSDIODev, SDIO_EVENT_DUMP)) { + // reset statistic + for (i=0;iMP_TxAvgTPWin[i] = 0; + pSDIODev->MP_RxAvgTPWin[i] = 0; + } + pSDIODev->MP_TxAvgTPWinSum = 0; + pSDIODev->MP_RxAvgTPWinSum = 0; + pSDIODev->OldestTxAvgWinIdx = 0; + pSDIODev->OldestRxAvgWinIdx = 0; + pSDIODev->TxAvgWinCnt = 0; + pSDIODev->RxAvgWinCnt = 0; + } + SDIO_SetEvent(pSDIODev, SDIO_EVENT_DUMP); + } + else { + SDIO_ClearEvent(pSDIODev, SDIO_EVENT_DUMP); + } + DiagPrintf("SDIO Dump %d\n", arg1); + break; + + case SDIO_MP_CTX: + arg1 = Strtoul((const u8*)(argv[1]), (u8 **)NULL, 10); + if (arg1) { + if (!pSDIODev->MP_ContinueTx) { + // Backup origional TX Callback function + pSDIODev->pTxCallback_Backup = pSDIODev->Tx_Callback; + pSDIODev->pTxCb_Adapter_Backup = (VOID *)pSDIODev->pTxCb_Adapter; + DiagPrintf("Register SDIO TX Callback with Continue TX Test function\n"); + SDIO_Register_Tx_Callback(pSDIODev, &SDIO_MP_ContinueTx, (VOID *) pSDIODev); + pSDIODev->MP_ContinueTx = 1; + } + DiagPrintf("SDIO Continue TX Test Enabled\n"); + } + else { + if (pSDIODev->MP_ContinueTx) { + // Restore origional TX Callback function + DiagPrintf("Restore SDIO TX Callback...\n"); + SDIO_Register_Tx_Callback(pSDIODev, pSDIODev->pTxCallback_Backup, pSDIODev->pTxCb_Adapter_Backup); + pSDIODev->MP_ContinueTx = 0; + DiagPrintf("SDIO Continue TX Test Disabled\n"); + } + else { + DiagPrintf("SDIO Continue TX Test Didn't Enabled\n"); + } + } + break; + + case SDIO_MP_CRX: + case SDIO_MP_CRX_DA: + if(SDIO_MP_CRX == cmd_type) { + pSDIODev->MP_ContinueRxMode = SDIO_CRX_STATIC_BUF; + } + else if (SDIO_MP_CRX_DA == cmd_type) { + pSDIODev->MP_ContinueRxMode = SDIO_CRX_DYNA_BUF; + } + + if (pSDIODev->MP_ContinueRx) { + DiagPrintf("SDIO Continue RX Test Running\n"); + break; + } + pSDIODev->MP_ContinueRx = 1; + arg1 = Strtoul((const u8*)(argv[1]), (u8 **)NULL, 10); + if (arg1 < 16) { + DiagPrintf("SDIO RX Test Min Pkt Size is 16\n"); + arg1 = 16; + } + + if (arg1 > 4096) { + DiagPrintf("SDIO RX Test Max Pkt Size is 4096\n"); + arg1 = 4096; + } + pSDIODev->MP_CRxSize = arg1; + arg2 = Strtoul((const u8*)(argv[2]), (u8 **)NULL, 10); + pSDIODev->MP_CRxPktCnt = arg2; + if (arg2 == 0) { + pSDIODev->MP_CRxInfinite = 1; + } + + if (SDIO_CRX_STATIC_BUF == pSDIODev->MP_ContinueRxMode) { + if (NULL == pSDIODev->pMP_CRxBuf) { + pSDIODev->pMP_CRxBuf = RtlMalloc(pSDIODev->MP_CRxSize+26); // 26: Wlan header + DiagPrintf("SDIO RX Test: pBuf @ 0x%x\n", (u32)pSDIODev->pMP_CRxBuf); + if (((u32)(pSDIODev->pMP_CRxBuf) & 0x03) != 0) { + DiagPrintf("SDIO RX Test: pBuf Not 4-bytes Aligned!!\n"); + } +#if SDIO_DEBUG + pSDIODev->MemAllocCnt++; +#endif + if (NULL != pSDIODev->pMP_CRxBuf) { + _memcpy(pSDIODev->pMP_CRxBuf, MP_WlanHdr, 26); + _memset((pSDIODev->pMP_CRxBuf+26), 0x3E, pSDIODev->MP_CRxSize); + } + } + + if (pSDIODev->pMP_CRxBuf) { + DiagPrintf("SDIO RX Test(Static RX Buf): PktSize=%d, PktCount=%d\n", pSDIODev->MP_CRxSize, pSDIODev->MP_CRxPktCnt); + SDIO_Wakeup_Task(pSDIODev); + } + else { + pSDIODev->MP_ContinueRx = 0; + pSDIODev->MP_CRxInfinite= 0; + pSDIODev->MP_CRxPktCnt = 0; + DiagPrintf("SDIO RX Test: Mem Allocate Failed\n"); + } + } + + if (SDIO_CRX_DYNA_BUF == pSDIODev->MP_ContinueRxMode) { + DiagPrintf("SDIO RX Test(Dyna-Allocate RX Buf): PktSize=%d, PktCount=%d\n", pSDIODev->MP_CRxSize, pSDIODev->MP_CRxPktCnt); + SDIO_Wakeup_Task(pSDIODev); + } + + break; + + case SDIO_MP_CRX_STOP: + pSDIODev->MP_ContinueRx = 0; + pSDIODev->MP_CRxPktCnt = 0; + pSDIODev->MP_CRxInfinite= 0; + DiagPrintf("SDIO RX Test Stopping...\n"); + break; + + case SDIO_MP_DBG_MSG: + arg1 = Strtoul((const u8*)(argv[1]), (u8 **)NULL, 10); + if (arg1) { + ConfigDebugInfo |= _DBG_SDIO_; + ConfigDebugWarn |= _DBG_SDIO_; + DiagPrintf("SDIO Debug Message On.\n"); + } + else { + ConfigDebugInfo &= ~_DBG_SDIO_; + ConfigDebugWarn &= ~_DBG_SDIO_; + DiagPrintf("SDIO Debug Message Off.\n"); + } + break; + + default: + DiagPrintf("SDIO_DeviceMPApp: Unknown Cmd=%s\n", argv[0]); + DiagPrintf("==== SDIO Command Help ====\n"); + DiagPrintf("SDIO mp_start : Enter MP mode\n"); + DiagPrintf("SDIO mp_stop : Exit MP mode(Switch back to Normal mode)\n"); + DiagPrintf("SDIO mp_loopback <1/0> : enable/disable data path loopback test\n"); + DiagPrintf("SDIO ctx <1/0> : Start/Stop SDIO continue TX test\n"); + DiagPrintf("SDIO crx : Start SDIO continue RX test with static RX Buffer\n"); + DiagPrintf("SDIO crx_da : Start SDIO continue RX test with Dynamic Allocate RX Buffer\n"); + DiagPrintf("SDIO crx_stop : Stop SDIO continue RX test\n"); + DiagPrintf("SDIO status : Dump current SDIO driver status\n"); + DiagPrintf("SDIO read_reg8 : Read SDIO register via 1-byte access\n"); + DiagPrintf("SDIO read_reg16 : Read SDIO register via 2-bytes access\n"); + DiagPrintf("SDIO read_reg32 : Read SDIO register via 4-bytes access\n"); + DiagPrintf("SDIO write_reg8 : Write SDIO register via 1-byte access\n"); + DiagPrintf("SDIO write_reg16 : Write SDIO register via 2-bytes access\n"); + DiagPrintf("SDIO write_reg32 : Write SDIO register via 4-bytes access\n"); + DiagPrintf("SDIO dump <1/0> : Start/Stop to dump SDIO throughput statistic periodically.\n"); + break; + } +} +#endif /* endof '#if SDIO_MP_MODE' */ + diff --git a/lib/fwlib/rtl8195a/src/rtl8195a_ssi.c b/lib/fwlib/rtl8195a/src/rtl8195a_ssi.c new file mode 100644 index 0000000..dbf2bb5 --- /dev/null +++ b/lib/fwlib/rtl8195a/src/rtl8195a_ssi.c @@ -0,0 +1,1271 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#include "rtl8195a.h" +#include "rtl8195a_ssi.h" +#include "hal_ssi.h" + +extern _LONG_CALL_ +HAL_Status HalSsiInitRtl8195a(VOID *Adaptor); + +extern _LONG_CALL_ +u32 HalGetCpuClk(VOID); + + +VOID _SsiReadInterruptRtl8195a(VOID *Adapter) +{ + SSI_DBG_ENTRANCE("_SsiReadInterrupt()\n"); + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter; + u32 ReceiveLevel; + volatile u32 Readable = HalSsiReadableRtl8195a(Adapter); + u8 Index = pHalSsiAdapter->Index; + + while (Readable) { + ReceiveLevel = HalSsiGetRxFifoLevelRtl8195a(Adapter); + + while (ReceiveLevel--) { + if (pHalSsiAdapter->RxData != NULL) { + if ((pHalSsiAdapter->DataFrameSize+1) > 8) { + // 16~9 bits mode + *((u16*)(pHalSsiAdapter->RxData)) = (u16)(HAL_SSI_READ32(Index, REG_DW_SSI_DR)); + pHalSsiAdapter->RxData = (VOID*)(((u16*)pHalSsiAdapter->RxData) + 1); + } + else { + // 8~4 bits mode + *((u8*)(pHalSsiAdapter->RxData)) = (u8)(HAL_SSI_READ32(Index, REG_DW_SSI_DR)); + pHalSsiAdapter->RxData = (VOID*)(((u8*)pHalSsiAdapter->RxData) + 1); + } + } + else { + // for Master mode, doing TX also will got RX data, so drop the dummy data + HAL_SSI_READ32(Index, REG_DW_SSI_DR); + } + + if (pHalSsiAdapter->RxLength > 0) { + pHalSsiAdapter->RxLength--; + } +#if 0 + else if (pHalSsiAdapter->RxLengthRemainder > 0) { + pHalSsiAdapter->RxLengthRemainder--; + } + + // Fixed length receive Complete. (RxLength & RxLengthRemainder == 0) + if ((pHalSsiAdapter->RxLength == 0) && (pHalSsiAdapter->RxLengthRemainder == 0)) { + break; + } +#endif + if (pHalSsiAdapter->RxLength == 0) { + break; + } + } + + if (pHalSsiAdapter->RxLength == 0) { + break; + } + + Readable = HalSsiReadableRtl8195a(Adapter); + } + + if ((pHalSsiAdapter->RxLength > 0) && + (pHalSsiAdapter->RxLength < (pHalSsiAdapter->RxThresholdLevel+1))) { + SSI_DBG_INT_READ("Setting Rx FIFO Threshold Level to 1\n"); + pHalSsiAdapter->RxThresholdLevel = 0; + HalSsiSetRxFifoThresholdLevelRtl8195a((VOID*)pHalSsiAdapter); + } + + if (pHalSsiAdapter->RxLength == 0) { + DBG_SSI_INFO("_SsiReadInterruptRtl8195a: RX_Done\r\n"); + pHalSsiAdapter->InterruptMask &= ~(BIT_IMR_RXFIM | BIT_IMR_RXOIM | BIT_IMR_RXUIM); + HalSsiSetInterruptMaskRtl8195a((VOID*)pHalSsiAdapter); +// if (pHalSsiAdapter->RxData != NULL) { + if (pHalSsiAdapter->RxCompCallback != NULL) { + pHalSsiAdapter->RxCompCallback(pHalSsiAdapter->RxCompCbPara); + } +// } + } + +} + + +VOID _SsiWriteInterruptRtl8195a(VOID *Adapter) +{ + SSI_DBG_ENTRANCE("_SsiWriteInterrupt()\n"); + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter; + u32 Writeable = HalSsiWriteableRtl8195a(Adapter); + u32 TxWriteMax = SSI_TX_FIFO_DEPTH - pHalSsiAdapter->TxThresholdLevel; + u8 Index = pHalSsiAdapter->Index; + + if (Writeable) { + /* Disable Tx FIFO Empty IRQ */ + pHalSsiAdapter->InterruptMask &= ~ BIT_IMR_TXEIM; + HalSsiSetInterruptMaskRtl8195a((VOID*)pHalSsiAdapter); + + while (TxWriteMax--) { + if ((pHalSsiAdapter->DataFrameSize+1) > 8) { + // 16~9 bits mode + if (pHalSsiAdapter->TxData != NULL) { + HAL_SSI_WRITE16(Index, REG_DW_SSI_DR, *((u16*)(pHalSsiAdapter->TxData))); + pHalSsiAdapter->TxData = (VOID*)(((u16*)pHalSsiAdapter->TxData) + 1); + } + else { + // For master mode: Push a dummy to TX FIFO for Read + if (pHalSsiAdapter->Role == SSI_MASTER) { + HAL_SSI_WRITE16(Index, REG_DW_SSI_DR, (u16)SSI_DUMMY_DATA); // Dummy byte + } + } + } + else { + // 8~4 bits mode + if (pHalSsiAdapter->TxData != NULL) { + HAL_SSI_WRITE8(Index, REG_DW_SSI_DR, *((u8*)(pHalSsiAdapter->TxData))); + pHalSsiAdapter->TxData = (VOID*)(((u8*)pHalSsiAdapter->TxData) + 1); + } + else { + // For master mode: Push a dummy to TX FIFO for Read + if (pHalSsiAdapter->Role == SSI_MASTER) { + HAL_SSI_WRITE8(Index, REG_DW_SSI_DR, (u8)SSI_DUMMY_DATA); // Dummy byte + } + } + } + + pHalSsiAdapter->TxLength--; + + if (pHalSsiAdapter->TxLength == 0) + break; + } + + /* Enable Tx FIFO Empty IRQ */ + pHalSsiAdapter->InterruptMask |= BIT_IMR_TXEIM; + HalSsiSetInterruptMaskRtl8195a((VOID*)pHalSsiAdapter); + } + + if (pHalSsiAdapter->TxLength == 0) { + DBG_SSI_INFO("_SsiWriteInterruptRtl8195a: TX_Done\r\n"); + pHalSsiAdapter->InterruptMask &= ~(BIT_IMR_TXOIM | BIT_IMR_TXEIM); + HalSsiSetInterruptMaskRtl8195a((VOID*)pHalSsiAdapter); + // If it's not a dummy TX for master read SPI, then call the TX_done callback + if (pHalSsiAdapter->TxData != NULL) { + if (pHalSsiAdapter->TxCompCallback != NULL) { + pHalSsiAdapter->TxCompCallback(pHalSsiAdapter->TxCompCbPara); + } + } + } +} + + +u32 _SsiIrqHandleRtl8195a(VOID *Adaptor) +{ + SSI_DBG_ENTRANCE("_SsiIrqHandle()\n"); + PHAL_SSI_ADAPTOR pHalSsiAdaptor = (PHAL_SSI_ADAPTOR) Adaptor; + u32 InterruptStatus = HalSsiGetInterruptStatusRtl8195a(Adaptor); + u8 Index = pHalSsiAdaptor->Index; + + if (InterruptStatus & BIT_ISR_TXOIS) { + SSI_DBG_INT_HNDLR("[INT][SSI%d] Transmit FIFO Overflow Interrupt\n", Index); + HAL_SSI_READ32(Index, REG_DW_SSI_TXOICR); + } + + if (InterruptStatus & BIT_ISR_RXUIS) { + SSI_DBG_INT_HNDLR("[INT][SSI%d] Receive FIFO Underflow Interrupt\n", Index); + HAL_SSI_READ32(Index, REG_DW_SSI_RXUICR); + } + + if (InterruptStatus & BIT_ISR_RXOIS) { + SSI_DBG_INT_HNDLR("[INT][SSI%d] Receive FIFO Overflow Interrupt\n", Index); + HAL_SSI_READ32(Index, REG_DW_SSI_RXOICR); + } + + if (InterruptStatus & BIT_ISR_MSTIS) { + SSI_DBG_INT_HNDLR("[INT][SSI%d] Multi-Master Contention Interrupt\n", Index); + /* Another master is actively transferring data */ + /* TODO: Do reading data... */ + HAL_SSI_READ32(Index, REG_DW_SSI_MSTICR); + } + + if ((InterruptStatus & BIT_ISR_RXFIS) ) { + SSI_DBG_INT_HNDLR("[INT][SSI%d] Receive FIFO Full Interrupt\n", Index); + _SsiReadInterruptRtl8195a(Adaptor); + } + + if (InterruptStatus & BIT_ISR_TXEIS) { + /* Tx FIFO is empty, need to transfer data */ + SSI_DBG_INT_HNDLR("[INT][SSI%d] Transmit FIFO Empty Interrupt\n", Index); + _SsiWriteInterruptRtl8195a(Adaptor); + } + + return 0; +} + +HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor) +{ + SSI_DBG_ENTRANCE("HalSsiInitRtl8195a()\n"); + PHAL_SSI_ADAPTOR pHalSsiAdaptor = (PHAL_SSI_ADAPTOR) Adaptor; + volatile IRQn_Type IrqNum; + u32 IRQ_UNKNOWN = -999; + u32 Ctrlr0Value = 0; + u32 Ctrlr1Value = 0; + u32 SerValue = 0; + u32 BaudrValue = 0; + u32 TxftlrValue = 0; + u32 RxftlrValue = 0; + u32 MwcrValue = 0; + u8 MicrowireTransferMode = pHalSsiAdaptor->MicrowireTransferMode; + u8 DataFrameFormat = pHalSsiAdaptor->DataFrameFormat; + u8 TransferMode = pHalSsiAdaptor->TransferMode; + u8 Index = pHalSsiAdaptor->Index; + u8 Role = pHalSsiAdaptor->Role; + + if (Index > 2) { + DBG_SSI_ERR("HalSsiInitRtl8195a: Invalid SSI Idx %d\r\n", Index); + return HAL_ERR_PARA; + } + HalSsiPinmuxEnableRtl8195a_Patch(pHalSsiAdaptor); + HalSsiDisableRtl8195a(Adaptor); + + /* REG_DW_SSI_CTRLR0 */ + Ctrlr0Value |= BIT_CTRLR0_DFS(pHalSsiAdaptor->DataFrameSize); + Ctrlr0Value |= BIT_CTRLR0_FRF(pHalSsiAdaptor->DataFrameFormat); + Ctrlr0Value |= BIT_CTRLR0_SCPH(pHalSsiAdaptor->SclkPhase); + Ctrlr0Value |= BIT_CTRLR0_SCPOL(pHalSsiAdaptor->SclkPolarity); + Ctrlr0Value |= BIT_CTRLR0_TMOD(pHalSsiAdaptor->TransferMode); + Ctrlr0Value |= BIT_CTRLR0_CFS(pHalSsiAdaptor->ControlFrameSize); + + if (Role == SSI_SLAVE) + Ctrlr0Value |= BIT_CTRLR0_SLV_OE(pHalSsiAdaptor->SlaveOutputEnable); + + SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_CTRLR0 Value: %X\n", Index, Ctrlr0Value); + + HAL_SSI_WRITE32(Index, REG_DW_SSI_CTRLR0, Ctrlr0Value); + + SSI_DBG_INIT("[2] SSI%d REG_DW_SSI_CTRLR0(%X) = %X\n", Index, + SSI0_REG_BASE + (SSI_REG_OFF * Index) + REG_DW_SSI_CTRLR0, + HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0)); + + /* REG_DW_SSI_TXFTLR */ + TxftlrValue = BIT_TXFTLR_TFT(pHalSsiAdaptor->TxThresholdLevel); + SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_TXFTLR Value: %X\n", Index, TxftlrValue); + + HAL_SSI_WRITE32(Index, REG_DW_SSI_TXFTLR, TxftlrValue); + + SSI_DBG_INIT("[2] SSI%d REG_DW_SSI_TXFTLR(%X) = %X\n", Index, + SSI0_REG_BASE + (SSI_REG_OFF * Index) + REG_DW_SSI_TXFTLR, + HAL_SSI_READ32(Index, REG_DW_SSI_TXFTLR)); + + /* REG_DW_SSI_RXFTLR */ + RxftlrValue = BIT_RXFTLR_RFT(pHalSsiAdaptor->RxThresholdLevel); + SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_RXFTLR Value: %X\n", Index, RxftlrValue); + + HAL_SSI_WRITE32(Index, REG_DW_SSI_RXFTLR, RxftlrValue); + + SSI_DBG_INIT("[2] SSI%d REG_DW_SSI_RXFTLR(%X) = %X\n", Index, + SSI0_REG_BASE + (SSI_REG_OFF * Index) + REG_DW_SSI_RXFTLR, + HAL_SSI_READ32(Index, REG_DW_SSI_RXFTLR)); + /** + * Master Only + * REG_DW_SSI_CTRLR1, REG_DW_SSI_SER, REG_DW_SSI_BAUDR + */ + if (Role & SSI_MASTER) { + if ((TransferMode == TMOD_RO) || (TransferMode == TMOD_EEPROM_R) || + ((DataFrameFormat == FRF_NS_MICROWIRE) && (MicrowireTransferMode == MW_TMOD_SEQUENTIAL))) { + Ctrlr1Value = BIT_CTRLR1_NDF(pHalSsiAdaptor->DataFrameNumber); + SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_CTRLR1 Value: %X\n", Index, Ctrlr1Value); + + HAL_SSI_WRITE32(Index, REG_DW_SSI_CTRLR1, Ctrlr1Value); + + SSI_DBG_INIT("[2] SSI%d REG_DW_SSI_CTRLR1(%X) = %X\n", Index, + SSI0_REG_BASE + (SSI_REG_OFF * Index) + REG_DW_SSI_CTRLR1, + HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR1)); + } + + SerValue = BIT_SER_SER(1 << (pHalSsiAdaptor->SlaveSelectEnable)); + SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_SER Value: %X\n", Index, SerValue); + + //HAL_SSI_WRITE32(Index, REG_DW_SSI_SER, SerValue); + HalSsiSetSlaveEnableRegisterRtl8195a(Adaptor, pHalSsiAdaptor->SlaveSelectEnable); + + SSI_DBG_INIT("[2] SSI%d REG_DW_SSI_SER(%X) = %X\n", Index, + SSI0_REG_BASE + (SSI_REG_OFF * Index) + REG_DW_SSI_SER, + HalSsiGetSlaveEnableRegisterRtl8195a(Adaptor)); + + BaudrValue = BIT_BAUDR_SCKDV(pHalSsiAdaptor->ClockDivider); + SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_BAUDR Value: %X\n", Index, BaudrValue); + + HAL_SSI_WRITE32(Index, REG_DW_SSI_BAUDR, BaudrValue); + + SSI_DBG_INIT("[2] SSI%d REG_DW_SSI_BAUDR(%X) = %X\n", Index, + SSI0_REG_BASE + (SSI_REG_OFF * Index) + REG_DW_SSI_BAUDR, + HAL_SSI_READ32(Index, REG_DW_SSI_BAUDR)); + } + + // Microwire + MwcrValue |= BIT_MWCR_MWMOD(pHalSsiAdaptor->MicrowireTransferMode); + MwcrValue |= BIT_MWCR_MDD(pHalSsiAdaptor->MicrowireDirection); + MwcrValue |= BIT_MWCR_MHS(pHalSsiAdaptor->MicrowireHandshaking); + SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_MWCR Value: %X\n", Index, MwcrValue); + + HAL_SSI_WRITE32(Index, REG_DW_SSI_MWCR, MwcrValue); + + SSI_DBG_INIT("[2] SSI%d REG_DW_SSI_MWCR(%X) = %X\n", Index, + SSI0_REG_BASE + (SSI_REG_OFF * Index) + REG_DW_SSI_MWCR, + HAL_SSI_READ32(Index, REG_DW_SSI_MWCR)); + + SSI_DBG_INIT("SSI%d TransferMechanism: %d\n", Index, pHalSsiAdaptor->TransferMechanism); + if (pHalSsiAdaptor->TransferMechanism == SSI_DTM_INTERRUPT) + { + SSI_DBG_INIT("SSI%d Interrupt initialize, Interrupt: %X\n", Index, pHalSsiAdaptor->InterruptMask); + switch (Index) { + case 0: + IrqNum = SPI0_IRQ; + break; + case 1: + IrqNum = SPI1_IRQ; + break; + case 2: + IrqNum = SPI2_IRQ; + break; + default: + IrqNum = IRQ_UNKNOWN; + break; + } + + if (likely(IrqNum != IRQ_UNKNOWN)) { + /* REG_DW_SSI_IMR */ + HalSsiSetInterruptMaskRtl8195a(Adaptor); + + pHalSsiAdaptor->IrqHandle.Data = (u32)pHalSsiAdaptor; + pHalSsiAdaptor->IrqHandle.IrqFun = (IRQ_FUN)_SsiIrqHandleRtl8195a; + pHalSsiAdaptor->IrqHandle.IrqNum = (IRQn_Type)IrqNum; + pHalSsiAdaptor->IrqHandle.Priority = pHalSsiAdaptor->InterruptPriority; + + InterruptRegister(&pHalSsiAdaptor->IrqHandle); + InterruptEn(&pHalSsiAdaptor->IrqHandle); + } + else { + SSI_DBG_INIT("Unknown SSI Index.\n"); + pHalSsiAdaptor->TransferMechanism = SSI_DTM_BASIC; + } + } + + HalSsiEnableRtl8195a(Adaptor); + + return HAL_OK; +} + +HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor) +{ + SSI_DBG_ENTRANCE("HalSsiPinmuxEnableRtl8195a()\n"); + PHAL_SSI_ADAPTOR pHalSsiAdaptor = (PHAL_SSI_ADAPTOR) Adaptor; + volatile HAL_Status Result; + u32 PinmuxSelect = pHalSsiAdaptor->PinmuxSelect; + u8 Index = pHalSsiAdaptor->Index; + + SSI_DBG_PINMUX("[1] SSI%d REG_SSI_MUX_CTRL(%X) = %X\n", Index, + PERI_ON_BASE + REG_SPI_MUX_CTRL, + HAL_READ32(PERI_ON_BASE, REG_SPI_MUX_CTRL)); + + switch (Index) + { + case 0: + { + ACTCK_SPI0_CCTRL(ON); + SLPCK_SPI0_CCTRL(ON); + PinCtrl(SPI0, PinmuxSelect, ON); + SPI0_FCTRL(ON); + Result = HAL_OK; + break; + } + case 1: + { + ACTCK_SPI1_CCTRL(ON); + SLPCK_SPI1_CCTRL(ON); + PinCtrl(SPI1, PinmuxSelect, ON); + SPI1_FCTRL(ON); + Result = HAL_OK; + break; + } + case 2: + { + ACTCK_SPI2_CCTRL(ON); + SLPCK_SPI2_CCTRL(ON); + PinCtrl(SPI2, PinmuxSelect, ON); + SPI2_FCTRL(ON); + Result = HAL_OK; + break; + } + default: + { + DBG_SSI_ERR("Invalid SSI Index %d!\n", Index); + Result = HAL_ERR_PARA; + break; + } + } + + SSI_DBG_PINMUX("[2] SSI%d REG_SSI_MUX_CTRL(%X) = %X\n", Index, + PERI_ON_BASE + REG_SPI_MUX_CTRL, + HAL_READ32(PERI_ON_BASE, REG_SPI_MUX_CTRL)); + + return Result; +} + +HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor) +{ + SSI_DBG_ENTRANCE("HalSsiPinmuxEnableRtl8195a()\n"); + PHAL_SSI_ADAPTOR pHalSsiAdaptor = (PHAL_SSI_ADAPTOR) Adaptor; + volatile HAL_Status Result; + u32 PinmuxSelect = pHalSsiAdaptor->PinmuxSelect; + u8 Index = pHalSsiAdaptor->Index; + + SSI_DBG_PINMUX("[1] SSI%d REG_SSI_MUX_CTRL(%X) = %X\n", Index, + PERI_ON_BASE + REG_SPI_MUX_CTRL, + HAL_READ32(PERI_ON_BASE, REG_SPI_MUX_CTRL)); + + switch (Index) + { + case 0: + { + ACTCK_SPI0_CCTRL(OFF); + SLPCK_SPI0_CCTRL(OFF); + PinCtrl(SPI0, PinmuxSelect, OFF); + SPI0_FCTRL(OFF); + Result = HAL_OK; + break; + } + case 1: + { + ACTCK_SPI1_CCTRL(OFF); + SLPCK_SPI1_CCTRL(OFF); + PinCtrl(SPI1, PinmuxSelect, OFF); + SPI1_FCTRL(OFF); + Result = HAL_OK; + break; + } + case 2: + { + ACTCK_SPI2_CCTRL(OFF); + SLPCK_SPI2_CCTRL(OFF); + PinCtrl(SPI2, PinmuxSelect, OFF); + SPI2_FCTRL(OFF); + Result = HAL_OK; + break; + } + default: + { + DBG_SSI_ERR("Invalid SSI Index %d!\n", Index); + Result = HAL_ERR_PARA; + break; + } + } + + SSI_DBG_PINMUX("[2] SSI%d REG_SSI_MUX_CTRL(%X) = %X\n", Index, + PERI_ON_BASE + REG_SPI_MUX_CTRL, + HAL_READ32(PERI_ON_BASE, REG_SPI_MUX_CTRL)); + + return Result; +} + +HAL_Status HalSsiDeInitRtl8195a(VOID *Adapter) +{ + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter; + u8 Index; + volatile HAL_Status Result; + + Index = pHalSsiAdapter->Index; + + if(Index > 2){ + DBG_SSI_ERR("Invalid SSI Index %d!\n", Index); + return HAL_ERR_PARA; + } + + HalSsiInterruptDisableRtl8195a(pHalSsiAdapter); + HalSsiDisableRtl8195a(pHalSsiAdapter); + + Result = HalSsiPinmuxDisableRtl8195a(pHalSsiAdapter); + if(Result != HAL_OK){ + DBG_SSI_ERR("Pinmux Disable Error\n"); + return Result; + } + + return Result; +} + +HAL_Status HalSsiClockOnRtl8195a(VOID *Adapter) +{ + PHAL_SSI_ADAPTOR pHalSsiAdaptor = (PHAL_SSI_ADAPTOR) Adapter; + volatile HAL_Status Result; + u8 Index = pHalSsiAdaptor->Index; + + switch (Index) + { + case 0: + { + ACTCK_SPI0_CCTRL(ON); + SLPCK_SPI0_CCTRL(ON); + Result = HAL_OK; + break; + } + case 1: + { + ACTCK_SPI1_CCTRL(ON); + SLPCK_SPI1_CCTRL(ON); + Result = HAL_OK; + break; + } + case 2: + { + ACTCK_SPI2_CCTRL(ON); + SLPCK_SPI2_CCTRL(ON); + Result = HAL_OK; + break; + } + default: + { + DBG_SSI_ERR("Invalid SSI Index %d!\n", Index); + Result = HAL_ERR_PARA; + break; + } + } + return Result; +} + +HAL_Status HalSsiClockOffRtl8195a(VOID *Adapter) +{ + PHAL_SSI_ADAPTOR pHalSsiAdaptor = (PHAL_SSI_ADAPTOR) Adapter; + volatile HAL_Status Result; + u8 Index = pHalSsiAdaptor->Index; + + switch (Index) + { + case 0: + { + ACTCK_SPI0_CCTRL(OFF); + SLPCK_SPI0_CCTRL(OFF); + Result = HAL_OK; + break; + } + case 1: + { + ACTCK_SPI1_CCTRL(OFF); + SLPCK_SPI1_CCTRL(OFF); + Result = HAL_OK; + break; + } + case 2: + { + ACTCK_SPI2_CCTRL(OFF); + SLPCK_SPI2_CCTRL(OFF); + Result = HAL_OK; + break; + } + default: + { + DBG_SSI_ERR("Invalid SSI Index %d!\n", Index); + Result = HAL_ERR_PARA; + break; + } + } + return Result; + +} + +VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate) +{ + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter; + u32 ssi_clk; + u32 ClockDivider; + u32 SsiEn; + u32 RegValue; + u32 SystemClock; + u8 spi_idx = pHalSsiAdapter->Index; + + // Set SCLK Freq only available for Master mode + // For Slave mode, the baud rate is depends on the Master side, max rate = ssi_clk/2 + // Fsclk_out = Fssi_clk/SCKDV + SystemClock = HalGetCpuClk(); + + if (spi_idx == 1) { + ssi_clk = SystemClock >> 1; + RegValue = HAL_READ32(SYSTEM_CTRL_BASE, 0x250); + if (ClkRate > (ssi_clk/2)) { + // Use High speed clock: Fixed Freq. + RegValue |= BIT18; + ssi_clk = (200000000*5/6) >> 1; + } + else { + // Use Normal speed clock: CPU_Clk/2 + RegValue &= ~BIT18; + } + HAL_WRITE32(SYSTEM_CTRL_BASE, 0x250, RegValue); + } + else { + ssi_clk = SystemClock >> 2; + } + + if (pHalSsiAdapter->Role == SSI_MASTER) { + if (ClkRate > (ssi_clk/2)) { + DBG_SSI_ERR("spi_frequency: Freq %d is too high, available highest Freq=%d\r\n", ClkRate, (ssi_clk/2)); + ClockDivider = 2; + } + else { + ClockDivider = ssi_clk/ClkRate + 1; + if ((ssi_clk%ClkRate) > (ClkRate/2)) { + ClockDivider++; + } + if (ClockDivider >= 0xFFFF) { + // devider is 16 bits + ClockDivider = 0xFFFE; + } + ClockDivider &= 0xFFFE; // bit 0 always is 0 + } + DBG_SSI_INFO("spi_frequency: Set SCLK Freq=%d\r\n", (ssi_clk/ClockDivider)); + pHalSsiAdapter->ClockDivider = ClockDivider; + + SsiEn = HAL_SSI_READ32(spi_idx, REG_DW_SSI_SSIENR); // Backup SSI_EN register + + // Disable SSI first, so we can modify the Clock Divider + RegValue = SsiEn & BIT_INVC_SSIENR_SSI_EN; + HAL_SSI_WRITE32(spi_idx, REG_DW_SSI_SSIENR, RegValue); + HAL_SSI_WRITE32(spi_idx, REG_DW_SSI_BAUDR, (pHalSsiAdapter->ClockDivider & 0xFFFF)); + // recover the SSI_EN setting + HAL_SSI_WRITE32(spi_idx, REG_DW_SSI_SSIENR, SsiEn); + } + else { + if (ClkRate > (ssi_clk/10)) { + DBG_SSI_ERR("spi_frequency: Freq %d is too high, available highest Freq=%d\r\n", ClkRate, (ssi_clk/10)); + } + } +} + +HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length) +{ + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter; + u32 RxFifoThresholdLevel; + u8 Index = pHalSsiAdapter->Index; + + DBG_SSI_INFO("HalSsiIntReadRtl8195a: Idx=%d, RxData=0x%x, Len=0x%x\r\n", Index, RxData, Length); + if (HalSsiBusyRtl8195a(Adapter)) { + // As a Slave mode, if the peer(Master) side is power off, the BUSY flag is always on + DBG_SSI_WARN("HalSsiIntReadRtl8195a: SSI%d is busy\n", Index); + return HAL_BUSY; + } + + if (Length == 0) { + SSI_DBG_INT_READ("SSI%d RxData addr: 0x%X, Length: %d\n", Index, RxData, Length); + return HAL_ERR_PARA; + } + + if (Length > (pHalSsiAdapter->DefaultRxThresholdLevel)) { + RxFifoThresholdLevel = pHalSsiAdapter->DefaultRxThresholdLevel; + } + else { + RxFifoThresholdLevel = 0; + } + + if (pHalSsiAdapter->RxThresholdLevel != RxFifoThresholdLevel) { + DBG_SSI_INFO("Setting Rx FIFO Threshold Level to %d\n", RxFifoThresholdLevel); + pHalSsiAdapter->RxThresholdLevel = RxFifoThresholdLevel; + HalSsiSetRxFifoThresholdLevelRtl8195a((VOID*)pHalSsiAdapter); + } + + if ((pHalSsiAdapter->DataFrameSize+1) > 8) { + // 16~9 bits mode + pHalSsiAdapter->RxLength = Length >> 1; // 2 bytes(16 bit) every transfer + } + else { + // 8~4 bits mode + pHalSsiAdapter->RxLength = Length; // 1 byte(8 bit) every transfer + } + + pHalSsiAdapter->RxData = RxData; + DBG_SSI_INFO("SSI%d RxData addr: 0x%X, Length: %d\n", Index, + pHalSsiAdapter->RxData, pHalSsiAdapter->RxLength); + + pHalSsiAdapter->InterruptMask |= BIT_IMR_RXFIM | BIT_IMR_RXOIM | BIT_IMR_RXUIM; + HalSsiSetInterruptMaskRtl8195a((VOID*)pHalSsiAdapter); + + return HAL_OK; +} + + +HAL_Status +HalSsiIntWriteRtl8195a( + IN VOID *Adapter, // PHAL_SSI_ADAPTOR + IN u8 *pTxData, // the Buffer to be send + IN u32 Length // the length of data to be send +) +{ + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter; + + DBG_SSI_INFO("HalSsiIntWriteRtl8195a: Idx=%d, RxData=0x%x, Len=0x%x\r\n", pHalSsiAdapter->Index, pTxData, Length); + if ((Length == 0)) { + DBG_SSI_ERR("HalSsiIntSendRtl8195a: Err: pTxData=0x%x, Length=%d\n", pTxData, Length); + return HAL_ERR_PARA; + } + + if ((pHalSsiAdapter->DataFrameSize+1) > 8) { + // 16~9 bits mode + pHalSsiAdapter->TxLength = Length >> 1; // 2 bytes(16 bit) every transfer + } + else { + // 8~4 bits mode + pHalSsiAdapter->TxLength = Length; // 1 byte(8 bit) every transfer + } + + pHalSsiAdapter->TxData = (void*)pTxData; + pHalSsiAdapter->InterruptMask |= BIT_IMR_TXOIM | BIT_IMR_TXEIM; + HalSsiSetInterruptMaskRtl8195a((VOID*)pHalSsiAdapter); + + return HAL_OK; +} + +#ifdef CONFIG_GDMA_EN +/** + * GDMA IRQ Handler + */ +VOID SsiTxGdmaIrqHandle (VOID *Data) +{ + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data; + PSSI_DMA_CONFIG pDmaConfig = &pHalSsiAdapter->DmaConfig;; + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + PHAL_GDMA_OP pHalGdmaOp; + + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter; + pHalGdmaOp = (PHAL_GDMA_OP)pDmaConfig->pHalGdmaOp; + + /* Maintain Block Count */ +#if 0 + u8 IsrTypeMap = 0; + /* Clear Pending ISR */ + IsrTypeMap = pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter); + + if (IsrTypeMap & BlockType) { + DBG_SSI_WARN("DMA Block %d\n",pHalGdmaAdapter->MuliBlockCunt); + pHalGdmaAdapter->MuliBlockCunt++; + } +#else + /* Clear Pending ISR */ + pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter); +#endif + +#if 0 + /* Set SSI DMA Disable */ + HAL_SSI_WRITE32(pHalSsiAdapter->Index, REG_DW_SSI_DMACR, \ + (HAL_SSI_READ32(pHalSsiAdapter->Index, REG_DW_SSI_DMACR) & ~SSI_TXDMA_ENABLE)); +#endif + pHalGdmaOp->HalGdmaChDis((VOID*)(pHalGdmaAdapter)); + // Call user TX complete callback + if (NULL != pHalSsiAdapter->TxCompCallback) { + pHalSsiAdapter->TxCompCallback(pHalSsiAdapter->TxCompCbPara); + } +} + +VOID SsiRxGdmaIrqHandle (VOID *Data) +{ + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data; + PSSI_DMA_CONFIG pDmaConfig = &pHalSsiAdapter->DmaConfig;; + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + PHAL_GDMA_OP pHalGdmaOp; + + + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter; + pHalGdmaOp = (PHAL_GDMA_OP)pDmaConfig->pHalGdmaOp; + + /* Maintain Block Count */ +#if 0 + u8 IsrTypeMap = 0; + /* Clear Pending ISR */ + IsrTypeMap = pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter); + + if (IsrTypeMap & BlockType) { + DBG_SSI_WARN("DMA Block %d\n",pHalGdmaAdapter->MuliBlockCunt); + pHalGdmaAdapter->MuliBlockCunt++; + } +#else + /* Clear Pending ISR */ + pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter); + +#endif + + /* Set SSI DMA Disable */ + HAL_SSI_WRITE32(pHalSsiAdapter->Index, REG_DW_SSI_DMACR, \ + (HAL_SSI_READ32(pHalSsiAdapter->Index, REG_DW_SSI_DMACR) & ~SSI_RXDMA_ENABLE)); + pHalGdmaOp->HalGdmaChDis((VOID*)(pHalGdmaAdapter)); + // Call user RX complete callback + if (NULL != pHalSsiAdapter->RxCompCallback) { + pHalSsiAdapter->RxCompCallback(pHalSsiAdapter->RxCompCbPara); + } + +} + +VOID +HalSsiTxGdmaLoadDefRtl8195a( + IN VOID *Adapter +) +{ + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter; + PSSI_DMA_CONFIG pDmaConfig; + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + u8 *pDst; + u8 DmaIdx; + u8 DmaCh; + u8 DstPer; + u8 ssi_idx; + u32 DmaChEn; + IRQn_Type IrqNum; + + if ((NULL == pHalSsiAdapter)) { + return; + } + pDmaConfig = &pHalSsiAdapter->DmaConfig; + + ssi_idx = pHalSsiAdapter->Index; + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter; + if (NULL == pHalGdmaAdapter) { + DBG_SSI_ERR("HalSsiTxGdmaLoadDefRtl8195a: HalGdmaAdapter is NULL\r\n"); + return; + } + _memset((void *)pHalGdmaAdapter, 0, sizeof(HAL_GDMA_ADAPTER)); + + pHalSsiAdapter->DmaControl |= SSI_TXDMA_ENABLE; + if ((pHalSsiAdapter->DataFrameSize+1) > 8) { + // 16~9 bits mode + pHalSsiAdapter->DmaTxDataLevel = 48; // When TX FIFO entity number <=48 then DMA Request asserted + } + else { + // 8~4 bits mode + pHalSsiAdapter->DmaTxDataLevel = 56; // When TX FIFO entity number <=56 then DMA Request asserted + } + + switch (ssi_idx) { + case 0: + pDst = (u8*) (SSI0_REG_BASE + REG_DW_SSI_DR); + DmaIdx = 0; + DmaCh = 1; + DmaChEn = GdmaCh1; + IrqNum = GDMA0_CHANNEL1_IRQ; + DstPer = GDMA_HANDSHAKE_SSI0_TX; + break; + + case 1: + pDst = (u8*) (SSI1_REG_BASE + REG_DW_SSI_DR); + DmaIdx = 1; + DmaCh = 1; + DmaChEn = GdmaCh1; + IrqNum = GDMA1_CHANNEL1_IRQ; + DstPer = GDMA_HANDSHAKE_SSI1_TX; + break; + + case 2: + pDst = (u8*) (SSI2_REG_BASE + REG_DW_SSI_DR); + DmaIdx = 0; // SPI2 TX only can use GDMA0 + DmaCh = 3; + DmaChEn = GdmaCh3; + IrqNum = GDMA0_CHANNEL3_IRQ; + DstPer = GDMA_HANDSHAKE_SSI2_TX; + break; + + default: + return; + } + + pHalGdmaAdapter->GdmaCtl.TtFc = TTFCMemToPeri; + pHalGdmaAdapter->GdmaCtl.Done = 1; + pHalGdmaAdapter->MuliBlockCunt = 0; + pHalGdmaAdapter->MaxMuliBlock = 1; + pHalGdmaAdapter->GdmaCfg.DestPer = DstPer; + pHalGdmaAdapter->ChDar = (u32)pDst; + pHalGdmaAdapter->GdmaIndex = DmaIdx; + pHalGdmaAdapter->ChNum = DmaCh; + pHalGdmaAdapter->ChEn = DmaChEn; + pHalGdmaAdapter->GdmaIsrType = (BlockType|TransferType|ErrType); + pHalGdmaAdapter->IsrCtrl = ENABLE; + pHalGdmaAdapter->GdmaOnOff = ON; + + pHalGdmaAdapter->GdmaCtl.IntEn = 1; + pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeOne; + pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeFour; + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte; + pHalGdmaAdapter->GdmaCtl.Dinc = NoChange; + pHalGdmaAdapter->GdmaCtl.Sinc = IncType; + + pDmaConfig->TxGdmaIrqHandle.Data = (u32)pHalSsiAdapter; + pDmaConfig->TxGdmaIrqHandle.IrqNum = IrqNum; + pDmaConfig->TxGdmaIrqHandle.IrqFun = (IRQ_FUN)SsiTxGdmaIrqHandle; + pDmaConfig->TxGdmaIrqHandle.Priority = 0x10; +} + + +VOID +HalSsiRxGdmaLoadDefRtl8195a( + IN VOID *Adapter +) +{ + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter; + PSSI_DMA_CONFIG pDmaConfig; + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + u8 *pSrc; + u8 DmaIdx; + u8 DmaCh; + u8 SrcPer; + u8 ssi_idx; + u32 DmaChEn; + IRQn_Type IrqNum; + + if ((NULL == pHalSsiAdapter)) { + return; + } + + pDmaConfig = &pHalSsiAdapter->DmaConfig; + + ssi_idx = pHalSsiAdapter->Index; + + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter; + if (NULL == pHalGdmaAdapter) { + return; + } + + _memset((void *)pHalGdmaAdapter, 0, sizeof(HAL_GDMA_ADAPTER)); + + pHalSsiAdapter->DmaControl |= SSI_RXDMA_ENABLE; + if ((pHalSsiAdapter->DataFrameSize+1) > 8) { + // 16~9 bits mode + pHalSsiAdapter->DmaRxDataLevel = 7; // RX FIFO stored bytes > (DMARDLR(7) + 1) then request DMA transfer + } + else { + // 8~4 bits mode + pHalSsiAdapter->DmaRxDataLevel = 3; // RX FIFO stored bytes > (DMARDLR(3) + 1) then request DMA transfer + } + switch (ssi_idx) { + case 0: + pSrc = (u8*) (SSI0_REG_BASE + REG_DW_SSI_DR); + DmaIdx = 0; + DmaCh = 2; + DmaChEn = GdmaCh2; + SrcPer = GDMA_HANDSHAKE_SSI0_RX; + IrqNum = GDMA0_CHANNEL2_IRQ; + break; + + case 1: + pSrc = (u8*) (SSI1_REG_BASE + REG_DW_SSI_DR); + DmaIdx = 1; + DmaCh = 2; + DmaChEn = GdmaCh2; + SrcPer = GDMA_HANDSHAKE_SSI1_RX; + IrqNum = GDMA1_CHANNEL2_IRQ; + break; + + case 2: + pSrc = (u8*) (SSI2_REG_BASE + REG_DW_SSI_DR); + DmaIdx = 1; // SSI2 RX only can use GDMA1 + DmaCh = 3; + DmaChEn = GdmaCh3; + SrcPer = GDMA_HANDSHAKE_SSI2_RX; + IrqNum = GDMA1_CHANNEL3_IRQ; + break; + + default: + return; + } + + pHalGdmaAdapter->GdmaCtl.TtFc = TTFCPeriToMem; + pHalGdmaAdapter->GdmaCtl.Done = 1; + pHalGdmaAdapter->GdmaCfg.ReloadSrc = 1; + pHalGdmaAdapter->GdmaCfg.SrcPer = SrcPer; + pHalGdmaAdapter->MuliBlockCunt = 0; + pHalGdmaAdapter->MaxMuliBlock = 1; + pHalGdmaAdapter->ChSar = (u32)pSrc; + pHalGdmaAdapter->GdmaIndex = DmaIdx; + pHalGdmaAdapter->ChNum = DmaCh; + pHalGdmaAdapter->ChEn = DmaChEn; + pHalGdmaAdapter->GdmaIsrType = (BlockType|TransferType|ErrType); + pHalGdmaAdapter->IsrCtrl = ENABLE; + pHalGdmaAdapter->GdmaOnOff = ON; + + pHalGdmaAdapter->GdmaCtl.IntEn = 1; + pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight; + pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeFour; + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthTwoBytes; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes; + pHalGdmaAdapter->GdmaCtl.Dinc = IncType; + pHalGdmaAdapter->GdmaCtl.Sinc = NoChange; + + pDmaConfig->RxGdmaIrqHandle.Data = (u32)pHalSsiAdapter; + pDmaConfig->RxGdmaIrqHandle.IrqNum = IrqNum; + pDmaConfig->RxGdmaIrqHandle.IrqFun = (IRQ_FUN)SsiRxGdmaIrqHandle; + pDmaConfig->RxGdmaIrqHandle.Priority = 0x10; +} + +VOID +HalSsiDmaInitRtl8195a( + IN VOID *Adapter +) +{ + u32 RegValue; + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter; + PSSI_DMA_CONFIG pDmaConfig; + PHAL_GDMA_ADAPTER pTxHalGdmaAdapter; + PHAL_GDMA_ADAPTER pRxHalGdmaAdapter; + u8 ssi_idx; + u32 hdk_tx_bit; + u32 hdk_rx_bit; + u32 DmatdlrValue = 0; + u32 DmardlrValue = 0; + + pDmaConfig = &pHalSsiAdapter->DmaConfig; + pTxHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter; + pRxHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter; + ssi_idx = pHalSsiAdapter->Index; + + // Set REG_PESOC_SOC_CTRL[28:16] to configure the GDMA handshake connection + // SSI2 handshake connection is hardware fixed + if (ssi_idx != 2) { + hdk_tx_bit = 16+pTxHalGdmaAdapter->GdmaCfg.DestPer; + hdk_rx_bit = 16+pRxHalGdmaAdapter->GdmaCfg.SrcPer; + } + else { + hdk_tx_bit = 0; + hdk_rx_bit = 0; + } + + HalSsiDisableRtl8195a(pHalSsiAdapter); + + RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_SOC_CTRL); + if (pHalSsiAdapter->DmaControl & SSI_TXDMA_ENABLE) { + // TX DMA is enabled + if (pTxHalGdmaAdapter->GdmaIndex ==0) { + ACTCK_GDMA0_CCTRL(ON); + GDMA0_FCTRL(ON); + if (hdk_tx_bit != 0) { + RegValue &= ~(1<DmaTxDataLevel); + HAL_SSI_WRITE32(ssi_idx, REG_DW_SSI_DMATDLR, DmatdlrValue); + + /* Set SSI DMA Enable */ + HAL_SSI_WRITE32(pHalSsiAdapter->Index, REG_DW_SSI_DMACR, \ + (HAL_SSI_READ32(pHalSsiAdapter->Index, REG_DW_SSI_DMACR) | SSI_TXDMA_ENABLE)); + } + + if (pHalSsiAdapter->DmaControl & SSI_RXDMA_ENABLE) { + // RX DMA is enabled + if (pRxHalGdmaAdapter->GdmaIndex ==0) { + ACTCK_GDMA0_CCTRL(ON); + GDMA0_FCTRL(ON); + if (hdk_rx_bit != 0) { + RegValue &= ~(1<DmaRxDataLevel); + HAL_SSI_WRITE32(ssi_idx, REG_DW_SSI_DMARDLR, DmardlrValue); + // the RX DMA will be enabled at read start. + } + + HAL_WRITE32(PERI_ON_BASE, REG_PESOC_SOC_CTRL, RegValue); + + HalSsiEnableRtl8195a(pHalSsiAdapter); +} + +HAL_Status +HalSsiDmaSendRtl8195a( + IN VOID *Adapter, // PHAL_SSI_ADAPTOR + IN u8 *pTxData, // the Buffer to be send + IN u32 Length // the length of data to be send +) +{ + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter; + PSSI_DMA_CONFIG pDmaConfig; + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + PHAL_GDMA_OP pHalGdmaOp; + + + if ((pTxData == NULL) || (Length == 0)) { + DBG_SSI_ERR("HalSsiDmaSendRtl8195a: Err: pTxData=0x%x, Length=%d\n", pTxData, Length); + return HAL_ERR_PARA; + } + pDmaConfig = &pHalSsiAdapter->DmaConfig; + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter; + + pHalSsiAdapter->TxLength = Length; + pHalSsiAdapter->TxData = (void*)pTxData; + + // Cofigure GDMA transfer + if ((pHalSsiAdapter->DataFrameSize+1) > 8) { + // 16~9 bits mode + if (((Length & 0x03)==0) && + (((u32)(pTxData) & 0x03)==0)) { + // 4-bytes aligned, move 4 bytes each transfer + pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeFour; + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes; + pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthTwoBytes; + pHalGdmaAdapter->GdmaCtl.BlockSize = Length >> 2; + } + else if (((Length & 0x01)==0) && + (((u32)(pTxData) & 0x01)==0)) { + // 2-bytes aligned, move 2 bytes each transfer + pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight; + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthTwoBytes; + pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthTwoBytes; + pHalGdmaAdapter->GdmaCtl.BlockSize = Length >> 1; + } + else { + DBG_SSI_ERR("HalSsiDmaSendRtl8195a: Aligment Err: pTxData=0x%x, Length=%d\n", pTxData, Length); + return HAL_ERR_PARA; + } + } + else { + // 8~4 bits mode + if (((Length & 0x03)==0) && + (((u32)(pTxData) & 0x03)==0)) { + // 4-bytes aligned, move 4 bytes each transfer + pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeOne; + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes; + pHalGdmaAdapter->GdmaCtl.BlockSize = Length >> 2; + } + else { + pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeFour; + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte; + pHalGdmaAdapter->GdmaCtl.BlockSize = Length; + } + pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeFour; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte; + } + + DBG_SSI_INFO("SrcMsize=%d SrcTrWidth=%d DestMsize=%d DstTrWidth=%d BlockSize=%d\n", \ + pHalGdmaAdapter->GdmaCtl.SrcMsize, pHalGdmaAdapter->GdmaCtl.SrcTrWidth, \ + pHalGdmaAdapter->GdmaCtl.DestMsize, pHalGdmaAdapter->GdmaCtl.DstTrWidth, \ + pHalGdmaAdapter->GdmaCtl.BlockSize); + + if (pHalGdmaAdapter->GdmaCtl.BlockSize > 4096) { + // over Maximum block size 4096 + DBG_SSI_ERR("HalSsiDmaSendRtl8195a: GDMA Block Size(%d) too big\n", pHalGdmaAdapter->GdmaCtl.BlockSize); + return HAL_ERR_PARA; + } + + pHalGdmaAdapter->ChSar = (u32)pTxData; + + // Enable GDMA for TX + pHalGdmaOp = (PHAL_GDMA_OP)pDmaConfig->pHalGdmaOp; + pHalGdmaOp->HalGdmaChSeting((VOID*)(pHalGdmaAdapter)); + pHalGdmaOp->HalGdmaChEn((VOID*)(pHalGdmaAdapter)); + +#if 0 + /* Set SSI DMA Enable */ + // TODO: protect the enable DMA register, it may collision with the DMA disable in the GDMA done ISR + HAL_SSI_WRITE32(pHalSsiAdapter->Index, REG_DW_SSI_DMACR, \ + (HAL_SSI_READ32(pHalSsiAdapter->Index, REG_DW_SSI_DMACR) | SSI_TXDMA_ENABLE)); +#endif + + return HAL_OK; +} + +HAL_Status +HalSsiDmaRecvRtl8195a( + IN VOID *Adapter, // PHAL_SSI_ADAPTOR + IN u8 *pRxData, ///< Rx buffer + IN u32 Length // buffer length +) +{ + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter; + PSSI_DMA_CONFIG pDmaConfig; + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + PHAL_GDMA_OP pHalGdmaOp; + + if ((pRxData == NULL) || (Length == 0)) { + DBG_SSI_ERR("HalRuartDmaRecvRtl8195a: Null Err: pRxData=0x%x, Length=%d\n", pRxData, Length); + return HAL_ERR_PARA; + } + + pDmaConfig = &pHalSsiAdapter->DmaConfig; + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter; + + pHalSsiAdapter->RxLength = Length; + pHalSsiAdapter->RxData = (void*)pRxData; + + // Cofigure GDMA transfer + if ((pHalSsiAdapter->DataFrameSize+1) > 8) { + // 16~9 bits mode + pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight; + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthTwoBytes; + pHalGdmaAdapter->GdmaCtl.BlockSize = Length >> 1; + + if (((Length & 0x03)==0) && + (((u32)(pRxData) & 0x03)==0)) { + // 4-bytes aligned, move 4 bytes each transfer + pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeFour; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes; + } + else if (((Length & 0x01)==0) && + (((u32)(pRxData) & 0x01)==0)) { + // 2-bytes aligned, move 2 bytes each transfer + pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthTwoBytes; + } + else { + DBG_SSI_ERR("HalSsiDmaSendRtl8195a: Aligment Err: pTxData=0x%x, Length=%d\n", pRxData, Length); + return HAL_ERR_PARA; + } + } + else { + // 8~4 bits mode + pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeFour; + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte; + pHalGdmaAdapter->GdmaCtl.BlockSize = Length; + if (((Length & 0x03)==0) && + (((u32)(pRxData) & 0x03)==0)) { + // 4-bytes aligned, move 4 bytes each transfer + pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeOne; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes; + } + else { + pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeFour; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte; + } + } + + if (pHalGdmaAdapter->GdmaCtl.BlockSize > 4096) { + // over Maximum block size 4096 + DBG_SSI_ERR("HalRuartDmaRecvRtl8195a: GDMA Block Size(%d) too big\n", pHalGdmaAdapter->GdmaCtl.BlockSize); + return HAL_ERR_PARA; + } + + pHalGdmaAdapter->ChDar = (u32)pRxData; + + // Enable GDMA for RX + pHalGdmaOp = (PHAL_GDMA_OP)pDmaConfig->pHalGdmaOp; + pHalGdmaOp->HalGdmaChSeting((VOID*)(pHalGdmaAdapter)); + pHalGdmaOp->HalGdmaChEn((VOID*)(pHalGdmaAdapter)); + + /* Set SSI DMA Enable */ + // TODO: protect the enable DMA register, it may collision with the DMA disable in the GDMA TX done ISR + HAL_SSI_WRITE32(pHalSsiAdapter->Index, REG_DW_SSI_DMACR, \ + (HAL_SSI_READ32(pHalSsiAdapter->Index, REG_DW_SSI_DMACR) | SSI_RXDMA_ENABLE)); + + return HAL_OK; +} + +#endif // end of "#ifdef CONFIG_GDMA_EN" diff --git a/lib/fwlib/rtl8195a/src/rtl8195a_timer.c b/lib/fwlib/rtl8195a/src/rtl8195a_timer.c new file mode 100644 index 0000000..86aca78 --- /dev/null +++ b/lib/fwlib/rtl8195a/src/rtl8195a_timer.c @@ -0,0 +1,323 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ +#include "rtl8195a.h" +#include "rtl8195a_timer.h" + +extern u32 gTimerRecord; +extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM]; + +#ifdef CONFIG_CHIP_A_CUT +HAL_RAM_BSS_SECTION u32 gTimerRecord; +#endif + +#ifdef CONFIG_CHIP_C_CUT +extern u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM]; +#else +u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM]; +#endif + +VOID +HalTimerIrq2To7Handle_Patch( + IN VOID *Data +) +{ + u32 TimerIrqStatus = 0, CheckIndex; + IRQ_FUN pHandler; + + TimerIrqStatus = HAL_TIMER_READ32(TIMERS_INT_STATUS_OFF); + + DBG_TIMER_INFO("%s:TimerIrqStatus: 0x%x\n",__FUNCTION__, TimerIrqStatus); + + for (CheckIndex = 2; CheckIndex<8; CheckIndex++) { + + //3 Check IRQ status bit and Timer X IRQ enable bit + if ((TimerIrqStatus & BIT_(CheckIndex)) && + (HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_CTL_REG_OFF) & BIT0)) { + //3 Execute Timer callback function + pHandler = Timer2To7VectorTable[CheckIndex-2]; + if (pHandler != NULL) { + pHandler((void*)Timer2To7HandlerData[CheckIndex-2]); + } + //3 Clear Timer ISR + HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_EOI_OFF); + } + } +} + +HAL_Status +HalTimerIrqRegisterRtl8195a_Patch( + IN VOID *Data +) +{ + PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data; + IRQ_HANDLE TimerIrqHandle; + //IRQ_FUN BackUpIrqFun = NULL; + + if (pHalTimerAdap->TimerId > 7) { + DBG_TIMER_ERR("%s: No Support Timer ID %d!\r\n", __FUNCTION__, pHalTimerAdap->TimerId); + return HAL_ERR_PARA; + } + else { + if (pHalTimerAdap->TimerId > 1) { + + TimerIrqHandle.IrqNum = TIMER2_7_IRQ; + TimerIrqHandle.IrqFun = (IRQ_FUN) HalTimerIrq2To7Handle_Patch; + + Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = + (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun; + Timer2To7HandlerData[pHalTimerAdap->TimerId-2] = + (uint32_t) pHalTimerAdap->IrqHandle.Data; + } + else { + TimerIrqHandle.IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ); + TimerIrqHandle.IrqFun = (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun; + } + TimerIrqHandle.Data = (u32)pHalTimerAdap; + InterruptRegister(&TimerIrqHandle); + } + + return HAL_OK; +} + +#ifndef CONFIG_CHIP_C_CUT +// Patch for A/B Cut +HAL_Status +HalTimerInitRtl8195a_Patch( + IN VOID *Data +) +{ + PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data; + HAL_Status ret=HAL_OK; + u32 ControlReg; + + if ((gTimerRecord & (1<TimerId)) != 0) { + DBG_TIMER_ERR ("%s:Error! Timer %d is occupied!\r\n", __FUNCTION__, pHalTimerAdap->TimerId); + return HAL_BUSY; + } + + //4 1) Config Timer Setting + ControlReg = ((u32)pHalTimerAdap->TimerMode<<1)|((u32)pHalTimerAdap->IrqDis<<2); + /* + set TimerControlReg + 0: Timer enable (0,disable; 1,enable) + 1: Timer Mode (0, free-running mode; 1, user-defined count mode) + 2: Timer Interrupt Mask (0, not masked; 1,masked) + */ + HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF), + ControlReg); + + if (pHalTimerAdap->TimerMode) { + //User-defined Mode + HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs); + } + else { + // set TimerLoadCount Register + HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_LOAD_COUNT_OFF), + 0xFFFFFFFF); + } + + //4 2) Setting Timer IRQ + if (!pHalTimerAdap->IrqDis) { + if (pHalTimerAdap->IrqHandle.IrqFun != NULL) { + //4 2.1) Initial TimerIRQHandle + ret = HalTimerIrqRegisterRtl8195a_Patch(pHalTimerAdap); + if (HAL_OK != ret) { + DBG_TIMER_ERR ("%s: Timer %d Register IRQ Err!\r\n", __FUNCTION__, pHalTimerAdap->TimerId); + return ret; + } + //4 2.2) Enable TimerIRQ for Platform + InterruptEn((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle); + } + else { + DBG_TIMER_ERR ("%s: Timer %d ISR Handler is NULL!\r\n", __FUNCTION__, pHalTimerAdap->TimerId); + return HAL_ERR_PARA; + } + } + + //4 4) Enable Timer +// HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF), +// (ControlReg|0x1)); + + gTimerRecord |= (1<TimerId); + + return ret; +} + +#else +// Patch for C Cut +HAL_Status +HalTimerInitRtl8195a_Patch( + IN VOID *Data +) +{ + PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data; + HAL_Status ret=HAL_OK; + + ret = HalTimerInitRtl8195aV02(Data); + + // Patch the Rom code to load the correct count value + if (pHalTimerAdap->TimerMode) { + //User-defined Mode + HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs); + } + + return ret; +} +#endif + +HAL_Status +HalTimerIrqUnRegisterRtl8195a_Patch( + IN VOID *Data +) +{ + PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data; + PIRQ_HANDLE pTimerIrqHandle; + u32 i; + + pTimerIrqHandle = &pHalTimerAdap->IrqHandle; + + if (pHalTimerAdap->TimerId > 7) { + DBG_TIMER_ERR("%s:Error: No Support Timer ID!\n", __FUNCTION__); + return HAL_ERR_PARA; + } + else { + if (pHalTimerAdap->TimerId > 1) { + pTimerIrqHandle->IrqNum = TIMER2_7_IRQ; + Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = NULL; + for (i=0;iIrqHandle); + InterruptUnRegister(pTimerIrqHandle); + } + } + else { + pTimerIrqHandle->IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ); + InterruptUnRegister(pTimerIrqHandle); + } + + } + + return HAL_OK; +} + + +VOID +HalTimerDeInitRtl8195a_Patch( + IN VOID *Data +) +{ + PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data; + u32 timer_id; + + timer_id = pHalTimerAdap->TimerId; + HalTimerDisRtl8195a (timer_id); + if (!pHalTimerAdap->IrqDis) { + if (pHalTimerAdap->IrqHandle.IrqFun != NULL) { + HalTimerIrqUnRegisterRtl8195a_Patch(pHalTimerAdap); + } + } + + gTimerRecord &= ~(1<TimerId); +} + +VOID +HalTimerReLoadRtl8195a_Patch( + IN u32 TimerId, + IN u32 LoadUs +) +{ + u32 LoadCount = 0; + u32 ms125; // how many 125ms + u32 remain_us; + + ms125 = LoadUs/125000; + remain_us = LoadUs - (ms125*125000); + LoadCount = ms125 * (GTIMER_CLK_HZ/8); + LoadCount += (remain_us*GTIMER_CLK_HZ)/1000000; + if (LoadCount == 0) { + LoadCount = 1; + } + +// DBG_TIMER_INFO("%s: Load Count=0x%x\r\n", __FUNCTION__, LoadCount); + // set TimerLoadCount Register + HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_LOAD_COUNT_OFF), + LoadCount); +} + +u32 +HalTimerReadCountRtl8195a_Patch( + IN u32 TimerId +) +{ + u32 TimerCountOld; + u32 TimerCountNew; + u32 TimerRDCnt; + + TimerRDCnt = 0; + TimerCountOld = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF); + while(1) { + TimerCountNew = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF); + + if (TimerCountOld == TimerCountNew) { + return (u32)TimerCountOld; + } + else { + TimerRDCnt++; + TimerCountOld = TimerCountNew; + + if (TimerRDCnt >= 2){ + return (u32)TimerCountOld; + } + } + } +} + +VOID +HalTimerIrqEnRtl8195a( + IN u32 TimerId +) +{ + HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF), + HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~(BIT2))); +} + +VOID +HalTimerIrqDisRtl8195a( + IN u32 TimerId +) +{ + HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF), + HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT2)); +} + +VOID +HalTimerEnRtl8195a_Patch( + IN u32 TimerId +) +{ + HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF), + HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT0)); +} + +VOID +HalTimerDisRtl8195a_Patch( + IN u32 TimerId +) +{ + // Disable Timer will alos disable the IRQ, so need to re-enable the IRQ when re-enable the timer + HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF), + HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~BIT0)); +} + diff --git a/lib/fwlib/rtl8195a/src/rtl8195a_uart.c b/lib/fwlib/rtl8195a/src/rtl8195a_uart.c new file mode 100644 index 0000000..eafcde6 --- /dev/null +++ b/lib/fwlib/rtl8195a/src/rtl8195a_uart.c @@ -0,0 +1,1013 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "rtl8195a.h" +#include "rtl8195a_uart.h" +#include "hal_uart.h" +#include "hal_gdma.h" + +u8 +HalRuartGetChipVerRtl8195a(VOID) +{ + u8 chip_ver; + + chip_ver = (HAL_READ32(SYSTEM_CTRL_BASE, 0x01F0) >> 4) & 0x0f; + return chip_ver; +} + +/** + * Reset RUART Tx FIFO. + * + * Reset RUART Receiver and Rx FIFO wrapper function. + * It will check LINE_STATUS_REG until reset action completion. + * + * @return BOOL + */ +HAL_Status +HalRuartResetTxFifoRtl8195a( + IN VOID *Data ///< RUART Adapter + ) +{ + PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data; + u8 UartIndex = pHalRuartAdapter->UartIndex; + u32 rx_trigger_lv; + u32 RegValue; + + // Backup the RX FIFO trigger Level setting + rx_trigger_lv = HAL_RUART_READ32(UartIndex, RUART_FIFO_CTL_REG_OFF); + rx_trigger_lv &= 0xC0; // only keep the bit[7:6] + + /* Step 2: Enable clear_txfifo */ + RegValue = (FIFO_CTL_DEFAULT_WITH_FIFO_DMA | RUART_FIFO_CTL_REG_CLEAR_TXFIFO) & (~0xC0); + RegValue |= rx_trigger_lv; + HAL_RUART_WRITE32(UartIndex, RUART_FIFO_CTL_REG_OFF, RegValue); + + //TODO: Check Defautl Value + RegValue = (FIFO_CTL_DEFAULT_WITH_FIFO_DMA & (~0xC0)) | rx_trigger_lv; + HAL_RUART_WRITE32(UartIndex, RUART_FIFO_CTL_REG_OFF, RegValue); + + return HAL_OK; +} + +HAL_Status +HalRuartGenBaudRateRtl8195a( + IN RUART_SPEED_SETTING *pBaudSetting +) +{ + u32 baud_rate; + u32 min_divisor=0; + u32 min_err=0xffffffff; + u32 uart_ovsr; + u32 uart_ovsr_mod; + u32 min_uart_ovsr; // ovsr with mini err + u32 min_uart_ovsr_mod; + u32 uart_clock; + u32 divisor_temp; + u32 max_jitter_temp; + u32 err_temp; + u32 uart_ovsr_target; + u32 uart_ovsrs_actual; + u32 ovsr_adj; + u32 adj_bits; + u32 div_res; + u32 uart_ovsrs_actual_mod; + + baud_rate = pBaudSetting->BaudRate; + if (baud_rate >= 1000000) { + baud_rate /= 100; + uart_clock = pBaudSetting->sclk; + } else { + baud_rate /= 2; + uart_clock = pBaudSetting->sclk*50; // UART clock is 1/2 CPU clock + } + + div_res = pBaudSetting->divisor_resolution; + while ((min_err > pBaudSetting->max_err) && (div_res > 0)) { + uart_ovsr = pBaudSetting->Ovsr_max; + while(uart_ovsr >= pBaudSetting->Ovsr_min) { + divisor_temp = ((uart_clock/baud_rate)/uart_ovsr); + max_jitter_temp = 0; + if (divisor_temp > 0) { + max_jitter_temp = 100000/uart_ovsr; + if (max_jitter_temp >= pBaudSetting->jitter_lim) { + err_temp = 100; + } else { + err_temp = (uart_clock/divisor_temp)/((uart_ovsr/100)*100); + if (err_temp > baud_rate) { + err_temp = (err_temp - baud_rate)*1000 / baud_rate; + } else { + err_temp = (baud_rate - err_temp)*1000 / baud_rate; + } + + if (err_temp < min_err) { + min_err = err_temp; + min_divisor = divisor_temp; + min_uart_ovsr = uart_ovsr/100; + min_uart_ovsr_mod = uart_ovsr%100; + } else if (err_temp == min_err) { + uart_ovsr_mod = uart_ovsr%100; + // we perfer OVSR bigger and adj bits smaller + if (((uart_ovsr/100) >= min_uart_ovsr) && (uart_ovsr_mod < min_uart_ovsr_mod)) { + min_err = err_temp; + min_divisor = divisor_temp; + min_uart_ovsr = uart_ovsr/100; + min_uart_ovsr_mod = uart_ovsr_mod; + } + } + } + } + uart_ovsr -= div_res; + } + div_res = div_res >> 1; + } + + uart_ovsr_target = (uart_clock/baud_rate)/min_divisor; + + ovsr_adj = 0; + adj_bits = 0; + uart_ovsrs_actual = uart_ovsr_target/100; + uart_ovsrs_actual_mod = uart_ovsr_target%100; + if (uart_ovsrs_actual_mod > 0) { + adj_bits = (uart_ovsrs_actual_mod*pBaudSetting->Ovsr_adj_max_bits)/100; + if ((uart_ovsrs_actual_mod - ((adj_bits*100)/pBaudSetting->Ovsr_adj_max_bits)) > 4) { + adj_bits++; + } + + if (adj_bits > (pBaudSetting->Ovsr_adj_max_bits-1)) { + DBG_UART_WARN("HalRuartGenBaudRateRtl8195a: adj_bits=%d\r\n", adj_bits); + adj_bits = pBaudSetting->Ovsr_adj_max_bits-1; + } + } + ovsr_adj = pBaudSetting->Ovsr_adj_map[adj_bits]; +// DBG_8195A("baud_rate=%d uart_clock=%d uart_ovsr_target=%d min_divisor=%d adj_bits=%d\r\n", baud_rate, uart_clock, uart_ovsr_target, min_divisor, adj_bits); + + pBaudSetting->Ovsr = uart_ovsrs_actual; + pBaudSetting->Div = min_divisor; + pBaudSetting->Ovsr_adj = ovsr_adj; + pBaudSetting->Ovsr_adj_bits = adj_bits; + + DBG_UART_INFO("HalRuartGenBaudRateRtl8195a: BaudRate=%d ovsr=%d divisor=%d ovsr_adj=0x%x\r\n", + pBaudSetting->BaudRate, uart_ovsrs_actual, min_divisor, ovsr_adj); + + return HAL_OK; +} + +HAL_Status +HalRuartDumpBaudRateTableRtl8195a( + IN VOID *Data +) +{ + PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data; + RUART_SPEED_SETTING RuartSpeedSetting; + u32 Divisor; + u32 Ovsr; + u32 Ovsr_adj; + u32 i; + u32 j; + u32 adj; + + RuartSpeedSetting.max_err = 3; + RuartSpeedSetting.Ovsr_min = UART_OVSR_POOL_MIN; + RuartSpeedSetting.Ovsr_max = UART_OVSR_POOL_MAX; + RuartSpeedSetting.divisor_resolution = DIVISOR_RESOLUTION; + RuartSpeedSetting.jitter_lim = JITTER_LIMIT; + RuartSpeedSetting.sclk = UART_SCLK; + + if (pHalRuartAdapter->pDefaultBaudRateTbl != NULL) { + // for debugging + DBG_8195A("==== 10 Bit ====\r\n"); + i = 0; + RuartSpeedSetting.Ovsr_adj_map = pHalRuartAdapter->pDefOvsrAdjTbl_10; + RuartSpeedSetting.Ovsr_adj_max_bits = 10; + while (pHalRuartAdapter->pDefaultBaudRateTbl[i] < 0xffffffff) { + RuartSpeedSetting.BaudRate = pHalRuartAdapter->pDefaultBaudRateTbl[i]; + if (HalRuartGenBaudRateRtl8195a(&RuartSpeedSetting) == HAL_OK) { + Divisor = RuartSpeedSetting.Div; + Ovsr = RuartSpeedSetting.Ovsr; + Ovsr_adj = RuartSpeedSetting.Ovsr_adj; + adj = 0; + for (j=0;j<10;j++) { + if (Ovsr_adj & (1<pDefaultBaudRateTbl[i], Ovsr, Divisor, Ovsr_adj, adj); + } + i++; + } + + + DBG_8195A("==== 9 Bit ====\r\n"); + i = 0; + RuartSpeedSetting.Ovsr_adj_map = pHalRuartAdapter->pDefOvsrAdjTbl_9; + RuartSpeedSetting.Ovsr_adj_max_bits = 9; + while (pHalRuartAdapter->pDefaultBaudRateTbl[i] < 0xffffffff) { + RuartSpeedSetting.BaudRate = pHalRuartAdapter->pDefaultBaudRateTbl[i]; + if (HalRuartGenBaudRateRtl8195a(&RuartSpeedSetting) == HAL_OK) { + Divisor = RuartSpeedSetting.Div; + Ovsr = RuartSpeedSetting.Ovsr; + Ovsr_adj = RuartSpeedSetting.Ovsr_adj; + adj = 0; + for (j=0;j<10;j++) { + if (Ovsr_adj & (1<pDefaultBaudRateTbl[i], Ovsr, Divisor, Ovsr_adj, adj); + } + i++; + } + + DBG_8195A("==== 8 Bit ====\r\n"); + i = 0; + RuartSpeedSetting.Ovsr_adj_map = pHalRuartAdapter->pDefOvsrAdjTbl_8; + RuartSpeedSetting.Ovsr_adj_max_bits = 8; + while (pHalRuartAdapter->pDefaultBaudRateTbl[i] < 0xffffffff) { + RuartSpeedSetting.BaudRate = pHalRuartAdapter->pDefaultBaudRateTbl[i]; + if (HalRuartGenBaudRateRtl8195a(&RuartSpeedSetting) == HAL_OK) { + Divisor = RuartSpeedSetting.Div; + Ovsr = RuartSpeedSetting.Ovsr; + Ovsr_adj = RuartSpeedSetting.Ovsr_adj; + adj = 0; + for (j=0;j<10;j++) { + if (Ovsr_adj & (1<pDefaultBaudRateTbl[i], Ovsr, Divisor, Ovsr_adj, adj); + } + i++; + } + } + + return HAL_OK; +} + +HAL_Status +HalRuartSetBaudRateRtl8195a( + IN VOID *Data +) +{ + PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data; + RUART_SPEED_SETTING RuartSpeedSetting; + u32 RegValue; + u32 Dll, Dlm; + u8 UartIndex; + u32 Divisor; + u32 Ovsr; + u32 Ovsr_adj; + u32 i; + u32 cpu_clk; + u32 baud_rate_temp; + u32 err; + u8 is_defined_baud; + u8 word_bits; + u8 adj_bits; + +#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) + u8 chip_ver; + + // get chip version + chip_ver = HalRuartGetChipVerRtl8195a(); +#endif + + if (pHalRuartAdapter->WordLen == RUART_WLS_8BITS) { + word_bits = 8+1; // 1 start bit + 8 data bit + } else { + word_bits = 7+1; + } + + if (pHalRuartAdapter->Parity == RUART_PARITY_ENABLE) { + word_bits++; // 1 parity bit + } + + is_defined_baud = 0; + + if (pHalRuartAdapter->pDefaultBaudRateTbl != NULL) { + i = 0; + while (pHalRuartAdapter->pDefaultBaudRateTbl[i] < 0xffffffff) { + if (pHalRuartAdapter->pDefaultBaudRateTbl[i] == pHalRuartAdapter->BaudRate) { + Divisor = pHalRuartAdapter->pDefaultDivTbl[i]; + Ovsr = pHalRuartAdapter->pDefaultOvsrRTbl[i]; + switch (word_bits) { + case 9: + adj_bits = pHalRuartAdapter->pDefOvsrAdjBitTbl_9[i]; + Ovsr_adj = pHalRuartAdapter->pDefOvsrAdjTbl_9[adj_bits]; + break; + case 10: + adj_bits = pHalRuartAdapter->pDefOvsrAdjBitTbl_10[i]; + Ovsr_adj = pHalRuartAdapter->pDefOvsrAdjTbl_10[adj_bits]; + break; + case 8: + adj_bits = pHalRuartAdapter->pDefOvsrAdjBitTbl_8[i]; + Ovsr_adj = pHalRuartAdapter->pDefOvsrAdjTbl_8[adj_bits]; + break; + + default: + adj_bits = pHalRuartAdapter->pDefOvsrAdjBitTbl_9[i]; + Ovsr_adj = pHalRuartAdapter->pDefOvsrAdjTbl_9[adj_bits]; + break; + } + // Verify again + cpu_clk = UART_SCLK; + baud_rate_temp = cpu_clk/Ovsr/Divisor; + if (baud_rate_temp > pHalRuartAdapter->BaudRate) { + err = baud_rate_temp - pHalRuartAdapter->BaudRate; + } else { + err = pHalRuartAdapter->BaudRate - baud_rate_temp; + } + + // Tolerance is 10% + // If the err is too big, it may caused by "the baud rate table is not for this CPU clock" + if (err < (pHalRuartAdapter->BaudRate/10)) { + is_defined_baud = 1; + } + break; // break the while loop + } else { + i++; + } + } + } + + if (is_defined_baud == 0) { + + switch (word_bits) { + case 9: + RuartSpeedSetting.Ovsr_adj_map = pHalRuartAdapter->pDefOvsrAdjTbl_9; + break; + + case 10: + RuartSpeedSetting.Ovsr_adj_map = pHalRuartAdapter->pDefOvsrAdjTbl_10; + break; + + case 8: + RuartSpeedSetting.Ovsr_adj_map = pHalRuartAdapter->pDefOvsrAdjTbl_8; + break; + + default: + word_bits = 9; + RuartSpeedSetting.Ovsr_adj_map = pHalRuartAdapter->pDefOvsrAdjTbl_9; + break; + } + DBG_UART_INFO("BaudRate(%d) not in the Lookup table \n", pHalRuartAdapter->BaudRate); + RuartSpeedSetting.Ovsr_adj_max_bits = word_bits; + RuartSpeedSetting.max_err = 3; + RuartSpeedSetting.Ovsr_min = UART_OVSR_POOL_MIN; + RuartSpeedSetting.Ovsr_max = UART_OVSR_POOL_MAX; + RuartSpeedSetting.divisor_resolution = DIVISOR_RESOLUTION; + RuartSpeedSetting.jitter_lim = JITTER_LIMIT; + RuartSpeedSetting.sclk = UART_SCLK; + RuartSpeedSetting.BaudRate = pHalRuartAdapter->BaudRate; +#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) + if (chip_ver < 2) { + // A or B Cut + // workround: +2% bias + RuartSpeedSetting.BaudRate = (pHalRuartAdapter->BaudRate * 102)/100; + } +#endif + if (HalRuartGenBaudRateRtl8195a(&RuartSpeedSetting) == HAL_OK) { + Divisor = RuartSpeedSetting.Div; + Ovsr = RuartSpeedSetting.Ovsr; + Ovsr_adj = RuartSpeedSetting.Ovsr_adj; + } else { + DBG_UART_ERR("Invalid BaudRate(%d), Force Baud Rateit as 9600\n", + pHalRuartAdapter->BaudRate); + Divisor = 434; + Ovsr = 20; + Ovsr_adj = 0; + } + } + + UartIndex = pHalRuartAdapter->UartIndex; + + DBG_UART_INFO("HalRuartSetBaudRateRtl8195a: BaudRate:%d Divisor:%d Ovsr:%d Ovsr_ADj:0x%x\n", + pHalRuartAdapter->BaudRate, Divisor, Ovsr, Ovsr_adj); + + Dll = Divisor & 0xFF; + Dlm = (Divisor & 0xFF00) >> 8; + + /* Set DLAB bit to 1 to access DLL/DLM */ + RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF); + RegValue |= RUART_LINE_CTL_REG_DLAB_ENABLE; + HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue); + + HAL_RUART_WRITE32(UartIndex, RUART_DLL_OFF, Dll); + HAL_RUART_WRITE32(UartIndex, RUART_DLM_OFF, Dlm); + + /** + * Clean Rx break signal interrupt status at initial stage. + */ + RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF); + RegValue |= RUART_SP_REG_RXBREAK_INT_STATUS; + HAL_RUART_WRITE32(UartIndex, RUART_SCRATCH_PAD_REG_OFF, RegValue); + + /* Set OVSR(xfactor) */ + RegValue = HAL_RUART_READ32(UartIndex, RUART_STS_REG_OFF); + RegValue &= ~(RUART_STS_REG_XFACTOR); + RegValue |= (((Ovsr - 5) << 4) & RUART_STS_REG_XFACTOR); + HAL_RUART_WRITE32(UartIndex, RUART_STS_REG_OFF, RegValue); + + /* Set OVSR_ADJ[10:0] (xfactor_adj[26:16]) */ + RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF); + RegValue &= ~(RUART_SP_REG_XFACTOR_ADJ); + RegValue |= ((Ovsr_adj << 16) & RUART_SP_REG_XFACTOR_ADJ); + HAL_RUART_WRITE32(UartIndex, RUART_SCRATCH_PAD_REG_OFF, RegValue); + + /* clear DLAB bit */ + RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF); + RegValue &= ~(RUART_LINE_CTL_REG_DLAB_ENABLE); + HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue); + pHalRuartAdapter->BaudRateUsing = pHalRuartAdapter->BaudRate; + + return HAL_OK; +} + + +HAL_Status +HalRuartInitRtl8195a_Patch( + IN VOID *Data ///< RUART Adapter +) +{ + /* DBG_ENTRANCE; */ + u32 RegValue; + u8 UartIndex; + u8 PinmuxSelect; + + PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data; + + UartIndex = pHalRuartAdapter->UartIndex; + PinmuxSelect = pHalRuartAdapter->PinmuxSelect; + + if (UartIndex > 2) { + DBG_UART_ERR(ANSI_COLOR_MAGENTA"HalRuartInitRtl8195a: Invalid UART Index\n"ANSI_COLOR_RESET); + return HAL_ERR_PARA; + } + + DBG_UART_INFO("HalRuartInitRtl8195a: [UART %d] PinSel=%d\n", UartIndex, PinmuxSelect); + if(( PinmuxSelect == RUART0_MUX_TO_GPIOE ) && ((UartIndex == 0) || (UartIndex == 1))) { + DBG_UART_WARN(ANSI_COLOR_MAGENTA"UART Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET); + } + + // switch Pin from EEPROM to UART0 + if(( PinmuxSelect == RUART0_MUX_TO_GPIOC ) && (UartIndex == 0)) { + RegValue = HAL_READ32(SYSTEM_CTRL_BASE, 0xa4); + if (RegValue & 0x10) { + DBG_UART_WARN("UART Pin may conflict with EEPROM\n"); +// HAL_WRITE32(SYSTEM_CTRL_BASE, 0xa4, (RegValue & (~0x10))); + } + } + + switch (UartIndex) { + case 0: + /* UART 0 */ + ACTCK_UART0_CCTRL(ON); + SLPCK_UART0_CCTRL(ON); + PinCtrl(UART0, PinmuxSelect, ON); + UART0_FCTRL(ON); + UART0_BD_FCTRL(ON); + break; + + case 1: + /* UART 1 */ + ACTCK_UART1_CCTRL(ON); + SLPCK_UART1_CCTRL(ON); + PinCtrl(UART1, PinmuxSelect, ON); + UART1_FCTRL(ON); + UART1_BD_FCTRL(ON); + break; + + case 2: + /* UART 1 */ + ACTCK_UART2_CCTRL(ON); + SLPCK_UART2_CCTRL(ON); + PinCtrl(UART2, PinmuxSelect, ON); + UART2_FCTRL(ON); + UART2_BD_FCTRL(ON); + break; + + default: + DBG_UART_ERR("Invalid UART Index(%d)\n", UartIndex); + return HAL_ERR_PARA; + } + + /* Reset RX FIFO */ + HalRuartResetRxFifoRtl8195a(Data); + DBG_UART_INFO(ANSI_COLOR_CYAN"HAL UART Init[UART %d]\n"ANSI_COLOR_RESET, UartIndex); + + /* Disable all interrupts */ + HAL_RUART_WRITE32(UartIndex, RUART_INTERRUPT_EN_REG_OFF, 0x00); + + /* Set Baudrate Division */ + if (pHalRuartAdapter->BaudRateUsing != pHalRuartAdapter->BaudRate) { + HalRuartSetBaudRateRtl8195a(pHalRuartAdapter); + } + + /** + * Clean Rx break signal interrupt status at initial stage. + */ + RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF); + RegValue |= RUART_SP_REG_RXBREAK_INT_STATUS; + HAL_RUART_WRITE32(UartIndex, RUART_SCRATCH_PAD_REG_OFF, RegValue); + +// DBG_UART_INFO("[R] UART%d INT_EN(0x04) = %x\n", UartIndex, pHalRuartAdapter->Interrupts); + RegValue = ((pHalRuartAdapter->Interrupts) & 0xFF); + HAL_RUART_WRITE32(UartIndex, RUART_INTERRUPT_EN_REG_OFF, RegValue); +// DBG_UART_INFO("[W] UART%d INT_EN(0x04) = %x\n", UartIndex, RegValue); + + /* Configure FlowControl */ + if (pHalRuartAdapter->FlowControl == AUTOFLOW_ENABLE) { + RegValue = HAL_RUART_READ32(UartIndex, RUART_MODEM_CTL_REG_OFF); + RegValue |= RUART_MCL_AUTOFLOW_ENABLE; + HAL_RUART_WRITE32(UartIndex, RUART_MODEM_CTL_REG_OFF, RegValue); + } + + /* RUART DMA Initialization */ +// HalRuartDmaInitRtl8195a(pHalRuartAdapter); + + DBG_UART_INFO("[R] UART%d LCR(0x%02X): %X\n", UartIndex, RUART_LINE_CTL_REG_OFF, HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF)); + RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF); + + /* PARITY CONTROL */ + RegValue &= BIT_CLR_LCR_WLS; + RegValue |= BIT_LCR_WLS(pHalRuartAdapter->WordLen); + + RegValue &= BIT_INVC_LCR_STB_EN; + RegValue |= BIT_LCR_STB_EN(pHalRuartAdapter->StopBit); + + RegValue &= BIT_INVC_LCR_PARITY_EN; + RegValue |= BIT_LCR_PARITY_EN(pHalRuartAdapter->Parity); + + /* PARITY TYPE SELECT */ + RegValue &= BIT_INVC_LCR_PARITY_TYPE; + RegValue |= BIT_LCR_PARITY_TYPE(pHalRuartAdapter->ParityType); + + /* STICK PARITY CONTROL */ + RegValue &= BIT_INVC_LCR_STICK_PARITY_EN; + RegValue |= BIT_LCR_STICK_PARITY_EN(pHalRuartAdapter->StickParity); + + HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue); + DBG_UART_INFO("[W] UART%d LCR(0x%02X): %X\n", UartIndex, RUART_LINE_CTL_REG_OFF, HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF)); + + /* Need to assert RTS during initial stage. */ + if (pHalRuartAdapter->FlowControl == AUTOFLOW_ENABLE) { + HalRuartRTSCtrlRtl8195a(Data, 1); + } + pHalRuartAdapter->State = HAL_UART_STATE_READY; + + return HAL_OK; +} + +HAL_Status +HalRuartEnableRtl8195a( + IN VOID *Data +) +{ + PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data; + u8 UartIndex; + + // Enable IP Clock + UartIndex = pHalRuartAdapter->UartIndex; + switch (UartIndex) { + case 0: + /* UART 0 */ + ACTCK_UART0_CCTRL(ON); + SLPCK_UART0_CCTRL(ON); + break; + + case 1: + /* UART 1 */ + ACTCK_UART1_CCTRL(ON); + SLPCK_UART1_CCTRL(ON); + break; + + case 2: + /* UART 1 */ + ACTCK_UART2_CCTRL(ON); + SLPCK_UART2_CCTRL(ON); + break; + + default: + DBG_UART_ERR("Invalid UART Index(%d)\n", UartIndex); + return HAL_ERR_PARA; + } + + return HAL_OK; +} + +HAL_Status +HalRuartDisableRtl8195a( + IN VOID *Data +) +{ + PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data; + u8 UartIndex; + + // Gate IP Clock + UartIndex = pHalRuartAdapter->UartIndex; + switch (UartIndex) { + case 0: + /* UART 0 */ + ACTCK_UART0_CCTRL(OFF); + SLPCK_UART0_CCTRL(OFF); + break; + + case 1: + /* UART 1 */ + ACTCK_UART1_CCTRL(OFF); + SLPCK_UART1_CCTRL(OFF); + break; + + case 2: + /* UART 1 */ + ACTCK_UART2_CCTRL(OFF); + SLPCK_UART2_CCTRL(OFF); + break; + + default: + DBG_UART_ERR("Invalid UART Index(%d)\n", UartIndex); + return HAL_ERR_PARA; + } + + return HAL_OK; +} + +HAL_Status +HalRuartFlowCtrlRtl8195a( + IN VOID *Data +) +{ + u32 UartIndex; + u32 RegValue; + PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data; + + UartIndex = pHalRuartAdapter->UartIndex; + + RegValue = HAL_RUART_READ32(UartIndex, RUART_MODEM_CTL_REG_OFF); + if (!pHalRuartAdapter->FlowControl) { + // No Auto Flow Control: no flow control or flow controled by software + RegValue &= ~(RUART_MCL_AUTOFLOW_ENABLE); + } + else { + RegValue |= RUART_MCL_AUTOFLOW_ENABLE; + } + HAL_RUART_WRITE32(UartIndex, RUART_MODEM_CTL_REG_OFF, RegValue); + + return HAL_OK; +} + +/** + * RUART send a data buffer by DMA(non-block) mode. + * + * RUART send data. + * + * @return VOID + */ +HAL_Status +HalRuartDmaSendRtl8195a_Patch( + IN VOID *Data, // PHAL_RUART_ADAPTER + IN u8 *pTxData, // the Buffer to be send + IN u32 Length // the length of data to be send + ) +{ + PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)Data; +// u8 UartIndex = pHalRuartAdapter->UartIndex; + PUART_DMA_CONFIG pUartGdmaConfig; + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + PHAL_GDMA_OP pHalGdmaOp; + HAL_UART_State State; + + State = pHalRuartAdapter->State; + if ((State != HAL_UART_STATE_READY) && (State != HAL_UART_STATE_BUSY_RX)) { + DBG_UART_WARN("HalRuartDmaSendRtl8195a: on Busy, State=%d\n", State); + return HAL_BUSY; + } + + if ((pTxData == NULL) || (Length == 0)) { + pHalRuartAdapter->Status = HAL_UART_STATUS_ERR_PARA; + DBG_UART_ERR("HalRuartDmaSendRtl8195a: Err: pTxData=0x%x, Length=%d\n", pTxData, Length); + return HAL_ERR_PARA; + } + + if (HAL_OK != RuartLock(pHalRuartAdapter)) { + DBG_UART_WARN("HalRuartDmaSendRtl8195a:Unable to Lock, Statu=%d\n", State); + return HAL_BUSY; + } + + if (State == HAL_UART_STATE_READY) { + pHalRuartAdapter->State = HAL_UART_STATE_BUSY_TX; + } + else { + pHalRuartAdapter->State = HAL_UART_STATE_BUSY_TX_RX; + } + + pHalRuartAdapter->Status = HAL_UART_STATUS_OK; + pHalRuartAdapter->pTxBuf = pTxData; + pHalRuartAdapter->TxCount = Length; +#if 0 + while (pHalRuartAdapter->TxCount > 0) { + if (HAL_RUART_READ32(UartIndex, RUART_LINE_STATUS_REG_OFF) & + (RUART_LINE_STATUS_REG_THRE)) { + HAL_RUART_WRITE32(UartIndex, RUART_TRAN_HOLD_REG_OFF, (*(pHalRuartAdapter->pTxBuf))); + pHalRuartAdapter->TxCount--; + pHalRuartAdapter->pTxBuf++; + } + else { + break; + } + } + + if (0 == pHalRuartAdapter->TxCount) { + if (State == HAL_UART_STATE_READY) { + pHalRuartAdapter->State = HAL_UART_STATE_READY; + } + else { + pHalRuartAdapter->State = HAL_UART_STATE_BUSY_RX; + } + + // Call user TX complete callback + if (NULL != pHalRuartAdapter->TxCompCallback) { + pHalRuartAdapter->TxCompCallback(pHalRuartAdapter->TxCompCbPara); + } + } + else +#endif + { + // Enable GDMA for TX + pUartGdmaConfig = pHalRuartAdapter->DmaConfig; + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter; + pHalGdmaOp = (PHAL_GDMA_OP)pUartGdmaConfig->pHalGdmaOp; + + if (((pHalRuartAdapter->TxCount & 0x03)==0) && + (((u32)(pHalRuartAdapter->pTxBuf) & 0x03)==0)) { + // 4-bytes aligned, move 4 bytes each transfer + pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeOne; + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes; + pHalGdmaAdapter->GdmaCtl.BlockSize = pHalRuartAdapter->TxCount >> 2; + } + else{ + // move 1 byte each transfer + pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeFour; + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte; + pHalGdmaAdapter->GdmaCtl.BlockSize = pHalRuartAdapter->TxCount; + } + + if (pHalGdmaAdapter->GdmaCtl.BlockSize > 4096) { + // over Maximum block size 4096 + RuartUnLock(pHalRuartAdapter); + return HAL_ERR_PARA; + } + + pHalGdmaAdapter->ChSar = (u32)(pHalRuartAdapter->pTxBuf); + + pHalGdmaOp->HalGdmaOnOff((VOID*)(pHalGdmaAdapter)); + pHalGdmaOp->HalGdmaChIsrEnAndDis((VOID*)(pHalGdmaAdapter)); + pHalGdmaOp->HalGdmaChSeting((VOID*)(pHalGdmaAdapter)); + pHalGdmaOp->HalGdmaChEn((VOID*)(pHalGdmaAdapter)); + } + + RuartUnLock(pHalRuartAdapter); + + return HAL_OK; +} + +/** + * Stop non-blocking UART TX + * + * + * @return VOID + */ +HAL_Status +HalRuartStopRecvRtl8195a_Patch( + IN VOID *Data // PHAL_RUART_ADAPTER + ) +{ + PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)Data; + PUART_DMA_CONFIG pUartGdmaConfig; + HAL_UART_State State; + u32 DMA_Dar; + u32 RecvdCnt; + + State = pHalRuartAdapter->State; + if ((State != HAL_UART_STATE_BUSY_RX) && (State != HAL_UART_STATE_BUSY_TX_RX)) { + DBG_UART_WARN("HalRuartStopRecvRtl8195a: Not in TX state, State=%d\n", State); + return HAL_OK; + } + + if (HAL_OK != RuartLock(pHalRuartAdapter)) { + DBG_UART_WARN("HalRuartStopRecvRtl8195a:Unable to Lock, Statu=%d\n", State); + return HAL_BUSY; + } + + // Disable Rx interrupt + pHalRuartAdapter->Interrupts &= ~(RUART_IER_ERBI | RUART_IER_ELSI); + HalRuartSetIMRRtl8195a (pHalRuartAdapter); + + pUartGdmaConfig = pHalRuartAdapter->DmaConfig; + if (NULL != pUartGdmaConfig) { + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + PHAL_GDMA_OP pHalGdmaOp; + u8 IsrTypeMap; + + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pRxHalGdmaAdapter; + pHalGdmaOp = (PHAL_GDMA_OP)pUartGdmaConfig->pHalGdmaOp; + + if ((NULL != pHalGdmaAdapter) && (NULL != pHalGdmaOp) && + (HalGdmaQueryChEnRtl8195a((VOID*)pHalGdmaAdapter))) { + // Clean Auto Reload Bit + pHalGdmaOp->HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter); + // Clear Pending ISR + IsrTypeMap = pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter); + pHalGdmaOp->HalGdmaChDis((VOID*)(pHalGdmaAdapter)); + + DMA_Dar = HalGdmaQueryDArRtl8195a((VOID*)pHalGdmaAdapter); + RecvdCnt = DMA_Dar - (u32)(pHalRuartAdapter->pRxBuf); +// DBG_8195A("%s: got %d bytes\r\n", __FUNCTION__, RecvdCnt); + pHalRuartAdapter->RxCount -= RecvdCnt; + pHalRuartAdapter->pRxBuf += RecvdCnt; + } + } + + while (HalRuartGetCRtl8195a(pHalRuartAdapter, pHalRuartAdapter->pRxBuf) == HAL_OK) { + pHalRuartAdapter->RxCount--; + pHalRuartAdapter->pRxBuf++; + } + + if (pHalRuartAdapter->State == HAL_UART_STATE_BUSY_RX) { + pHalRuartAdapter->State = HAL_UART_STATE_READY; + } + else { + pHalRuartAdapter->State = HAL_UART_STATE_BUSY_TX; + } + + RuartUnLock(pHalRuartAdapter); + + return HAL_OK; + +} + +/** + * Stop non-blocking UART TX + * + * + * @return VOID + */ +HAL_Status +HalRuartStopSendRtl8195a_Patch( + IN VOID *Data // PHAL_RUART_ADAPTER + ) +{ + PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)Data; + PUART_DMA_CONFIG pUartGdmaConfig; + HAL_UART_State State; + u32 DMA_Sar; + u32 TxedCnt; + + State = pHalRuartAdapter->State; + if ((State != HAL_UART_STATE_BUSY_TX) && (State != HAL_UART_STATE_BUSY_TX_RX)) { + DBG_UART_WARN("HalRuartDmaSendRtl8195a: Not in TX state, State=%d\n", State); + return HAL_OK; + } + + if (HAL_OK != RuartLock(pHalRuartAdapter)) { + DBG_UART_WARN("HalRuartDmaSendRtl8195a:Unable to Lock, Statu=%d\n", State); + return HAL_BUSY; + } + + // Disable Tx FIFO empty interrupt + pHalRuartAdapter->Interrupts &= ~RUART_IER_ETBEI; + HalRuartSetIMRRtl8195a (pHalRuartAdapter); + + pUartGdmaConfig = pHalRuartAdapter->DmaConfig; + if (NULL != pUartGdmaConfig) { + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + PHAL_GDMA_OP pHalGdmaOp; + u8 IsrTypeMap; + + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter; + pHalGdmaOp = (PHAL_GDMA_OP)pUartGdmaConfig->pHalGdmaOp; + + if ((NULL != pHalGdmaAdapter) && (NULL != pHalGdmaOp) && + (HalGdmaQueryChEnRtl8195a((VOID*)pHalGdmaAdapter))) { + // Clean Auto Reload Bit + pHalGdmaOp->HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter); + // Clear Pending ISR + IsrTypeMap = pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter); + pHalGdmaOp->HalGdmaChDis((VOID*)(pHalGdmaAdapter)); + + DMA_Sar = HalGdmaQuerySArRtl8195a((VOID*)pHalGdmaAdapter); + TxedCnt = DMA_Sar - (u32)(pHalRuartAdapter->pTxBuf); +// DBG_8195A("%s: got %d bytes\r\n", __FUNCTION__, RecvdCnt); + pHalRuartAdapter->TxCount -= TxedCnt; + pHalRuartAdapter->pTxBuf += TxedCnt; + } + } + + if (State == HAL_UART_STATE_BUSY_TX) { + pHalRuartAdapter->State = HAL_UART_STATE_READY; + } + else { + pHalRuartAdapter->State = HAL_UART_STATE_BUSY_RX; + } + + RuartUnLock(pHalRuartAdapter); + + return HAL_OK; + +} + +VOID +HalRuartEnterCriticalRtl8195a( + IN VOID *Data ///< RUART Adapter +) +{ + PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data; +#ifdef CONFIG_GDMA_EN + PUART_DMA_CONFIG pUartGdmaConfig; +#endif + + InterruptDis(&pHalRuartAdapter->IrqHandle); + +#ifdef CONFIG_GDMA_EN + pUartGdmaConfig = pHalRuartAdapter->DmaConfig; + if (NULL != pUartGdmaConfig) { + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pRxHalGdmaAdapter; + if (pHalGdmaAdapter->ChEn != 0) { + InterruptDis(&pUartGdmaConfig->RxGdmaIrqHandle); + } + + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter; + if (pHalGdmaAdapter->ChEn != 0) { + InterruptDis(&pUartGdmaConfig->TxGdmaIrqHandle); + } + } +#endif +} + +VOID +HalRuartExitCriticalRtl8195a( + IN VOID *Data ///< RUART Adapter + ) +{ + PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data; +#ifdef CONFIG_GDMA_EN + PUART_DMA_CONFIG pUartGdmaConfig; +#endif + + InterruptEn(&pHalRuartAdapter->IrqHandle); + +#ifdef CONFIG_GDMA_EN + pUartGdmaConfig = pHalRuartAdapter->DmaConfig; + if (NULL != pUartGdmaConfig) { + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pRxHalGdmaAdapter; + if (pHalGdmaAdapter->ChEn != 0) { + InterruptEn(&pUartGdmaConfig->RxGdmaIrqHandle); + } + + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter; + if (pHalGdmaAdapter->ChEn != 0) { + InterruptEn(&pUartGdmaConfig->TxGdmaIrqHandle); + } + } +#endif +} + +VOID +HalRuartDumpRegRtl8195a( + IN VOID *Data +) +{ + PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data; + u8 UartIndex; + u32 i; + u32 RegValue; + + UartIndex = pHalRuartAdapter->UartIndex; + + /* Set DLAB bit to 1 to access DLL/DLM */ + RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF); + RegValue |= RUART_LINE_CTL_REG_DLAB_ENABLE; + HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue); + + for (i=0;i<0x40;i++) { + DBG_8195A("UART Reg[0x%x] = 0x%x\r\n", i, HAL_RUART_READ8(UartIndex, i)); + } + +/* clear DLAB bit */ + RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF); + RegValue &= ~(RUART_LINE_CTL_REG_DLAB_ENABLE); + HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue); +} diff --git a/lib/fwlib/rtl8195a_usb.h b/lib/fwlib/rtl8195a_usb.h new file mode 100644 index 0000000..2543e79 --- /dev/null +++ b/lib/fwlib/rtl8195a_usb.h @@ -0,0 +1,111 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _RTL8195A_USB_H_ +#define _RTL8195A_USB_H_ + + +// common command for USB +#define USB_CMD_TX_ETH 0x83 // request to TX a 802.3 packet +#define USB_CMD_TX_WLN 0x81 // request to TX a 802.11 packet +#define USB_CMD_H2C 0x11 // H2C(host to device) command packet +#define USB_CMD_MEMRD 0x51 // request to read a block of memory data +#define USB_CMD_MEMWR 0x53 // request to write a block of memory +#define USB_CMD_MEMST 0x55 // request to set a block of memory with a value +#define USB_CMD_STARTUP 0x61 // request to jump to the start up function + +#define USB_CMD_RX_ETH 0x82 // indicate a RX 802.3 packet +#define USB_CMD_RX_WLN 0x80 // indicate a RX 802.11 packet +#define USB_CMD_C2H 0x10 // C2H(device to host) command packet +#define USB_CMD_MEMRD_RSP 0x50 // response to memory block read command +#define USB_CMD_MEMWR_RSP 0x52 // response to memory write command +#define USB_CMD_MEMST_RSP 0x54 // response to memory set command +#define USB_CMD_STARTED 0x60 // indicate the program has jumped to the given function + + +// TODO: This data structer just for test, we should modify it for the normal driver +typedef struct _USB_TX_DESC{ + // u4Byte 0 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 txpktsize:16; // bit[15:0] + u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) + u32 bus_agg_num:8; // bit[31:24], the bus aggregation number +#else + u32 bus_agg_num:8; // bit[31:24], the bus aggregation number + u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC) + u32 txpktsize:16; // bit[15:0] +#endif + + // u4Byte 1 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 type:8; // bit[7:0], the packet type + u32 rsvd0:24; +#else + u32 rsvd0:24; + u32 type:8; // bit[7:0], the packet type +#endif + + // u4Byte 2 + u32 rsvd1; + + // u4Byte 3 + u32 rsvd2; + + // u4Byte 4 + u32 rsvd3; + + // u4Byte 5 + u32 rsvd4; +} USB_TX_DESC, *PUSB_TX_DESC; + +#define SIZE_USB_TX_DESC sizeof(USB_TX_DESC) + +// TODO: This data structer just for test, we should modify it for the normal driver +typedef struct _USB_RX_DESC{ + // u4Byte 0 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 pkt_len:16; // bit[15:0], the packet size + u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc + u32 rsvd0:6; // bit[29:24] + u32 icv:1; // bit[30], ICV error + u32 crc:1; // bit[31], CRC error +#else + u32 crc:1; // bit[31], CRC error + u32 icv:1; // bit[30], ICV error + u32 rsvd0:6; // bit[29:24] + u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc + u32 pkt_len:16; // bit[15:0], the packet size +#endif + + // u4Byte 1 +#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN) + u32 type:8; // bit[7:0], the type of this packet + u32 rsvd1:24; // bit[31:8] +#else + u32 rsvd1:24; // bit[31:8] + u32 type:8; // bit[7:0], the type of this packet +#endif + + // u4Byte 2 + u32 rsvd2; + + // u4Byte 3 + u32 rsvd3; + + // u4Byte 4 + u32 rsvd4; + + // u4Byte 5 + u32 rsvd5; +} USB_RX_DESC, *PUSB_RX_DESC; + +#define SIZE_USB_RX_DESC sizeof(USB_RX_DESC) + +#endif // #ifndef _RTL8195A_USB_H_ + diff --git a/lib/fwlib/src/hal_32k.c b/lib/fwlib/src/hal_32k.c new file mode 100644 index 0000000..5394d2c --- /dev/null +++ b/lib/fwlib/src/hal_32k.c @@ -0,0 +1,293 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "rtl8195a.h" + +#ifdef CONFIG_TIMER_MODULE + +VOID +En32KCalibration( + VOID +) +{ + u32 Rtemp; + u32 Ttemp = 0; + + //DiagPrintf("32K clock source calibration\n"); + + //set parameter + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0); + //offset 1 = 0x1500 + Rtemp = 0x811500; + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp); + HalDelayUs(40); + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0); + + //offset 2 = 0x01c0 + Rtemp = 0x8201c0; + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp); + HalDelayUs(40); + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0); + + //offset 4 = 0x0100 + Rtemp = 0x840100; + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp); + HalDelayUs(40); + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0); + + //offset 0 = 0xf980 + Rtemp = 0x80f980; + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp); + HalDelayUs(40); + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0); + + while(1) { + //Polling LOCK + Rtemp = 0x110000; + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp); + //DiagPrintf("Polling lock\n"); + HalDelayUs(40); + + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL1); + if ((Rtemp & 0x3000) != 0x0){ + //DiagPrintf("32.768 Calibration Success\n", Ttemp); + break; + } + else { + Ttemp++; + HalDelayUs(30); + //DiagPrintf("Check lock: %d\n", Ttemp); + //DiagPrintf("0x278: %x\n", Rtemp); + if (Ttemp > 100000) { /*Delay 100ms*/ + DiagPrintf("32K Calibration Fail!!\n", Ttemp); + break; + } + } + } +} + +#if CONFIG_WDG +WDG_ADAPTER WDGAdapter; +extern HAL_TIMER_OP HalTimerOp; + +#ifdef CONFIG_WDG_NORMAL +VOID +WDGInitial( + IN u32 Period +) +{ + u8 CountId; + u16 DivFactor; + u32 CountTemp; + u32 CountProcess = 0; + u32 DivFacProcess = 0; + u32 PeriodProcess = 100*Period; + u32 MinPeriodTemp = 0xFFFFFFFF; + u32 PeriodTemp = 0; + u32 *Reg = (u32*)&(WDGAdapter.Ctrl); + + DBG_8195A(" Period = 0x%08x\n", Period); + + for (CountId = 0; CountId < 12; CountId++) { + CountTemp = ((0x00000001 << (CountId+1))-1); + DivFactor = (u16)((PeriodProcess)/(CountTemp*3)); + + if (DivFactor > 0) { + PeriodTemp = 3*(DivFactor+1)*CountTemp; + if (PeriodProcess < PeriodTemp) { + if (MinPeriodTemp > PeriodTemp) { + MinPeriodTemp = PeriodTemp; + CountProcess = CountId; + DivFacProcess = DivFactor; + } + } + } + } + + DBG_8195A("WdgScalar = 0x%08x\n", DivFacProcess); + DBG_8195A("WdgCunLimit = 0x%08x\n", CountProcess); + + WDGAdapter.Ctrl.WdgScalar = DivFacProcess; + WDGAdapter.Ctrl.WdgEnByte = 0; + WDGAdapter.Ctrl.WdgClear = 1; + WDGAdapter.Ctrl.WdgCunLimit = CountProcess; + WDGAdapter.Ctrl.WdgMode = RESET_MODE; + WDGAdapter.Ctrl.WdgToISR = 0; + + HAL_WRITE32(VENDOR_REG_BASE, 0, (*Reg)); + +} + +VOID +WDGIrqHandle +( + IN VOID *Data +) +{ + u32 temp; + WDG_REG *CtrlReg; + + if (NULL != WDGAdapter.UserCallback) { + WDGAdapter.UserCallback(WDGAdapter.callback_id); + } + + // Clear ISR + temp = HAL_READ32(VENDOR_REG_BASE, 0); + CtrlReg = (WDG_REG*)&temp; + CtrlReg->WdgToISR = 1; // write 1 clear + HAL_WRITE32(VENDOR_REG_BASE, 0, (temp)); +} + +VOID +WDGIrqInitial( + VOID +) +{ + u32 *Temp = (u32*)&(WDGAdapter.Ctrl); + + WDGAdapter.IrqHandle.Data = (u32)&WDGAdapter; + WDGAdapter.IrqHandle.IrqFun = (IRQ_FUN)WDGIrqHandle; + WDGAdapter.IrqHandle.IrqNum = WDG_IRQ; + WDGAdapter.IrqHandle.Priority = 0; + + InterruptRegister(&(WDGAdapter.IrqHandle)); + InterruptEn(&(WDGAdapter.IrqHandle)); + + WDGAdapter.Ctrl.WdgToISR = 1; // clear ISR first + WDGAdapter.Ctrl.WdgMode = INT_MODE; + HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp))); + WDGAdapter.Ctrl.WdgToISR = 0; +} + +VOID +WDGStart( + VOID +) +{ + u32 *Temp = (u32*)&(WDGAdapter.Ctrl); + WDGAdapter.Ctrl.WdgEnByte = 0xA5; + HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp))); +} + +VOID +WDGStop( + VOID +) +{ + u32 *Temp = (u32*)&(WDGAdapter.Ctrl); + WDGAdapter.Ctrl.WdgEnByte = 0; + HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp))); +} + +VOID +WDGRefresh( + VOID +) +{ + u32 *Temp = (u32*)&(WDGAdapter.Ctrl); + WDGAdapter.Ctrl.WdgClear = 1; + HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp))); +} + +VOID +WDGIrqCallBackReg( + IN VOID *CallBack, + IN u32 Id +) +{ + WDGAdapter.UserCallback = (VOID (*)(u32))CallBack; + WDGAdapter.callback_id = Id; +} + +#endif + +#ifdef CONFIG_WDG_TEST +VOID +WDGIrqHandle +( + IN VOID *Data +) +{ +} + + +VOID +WDGGtimerHandle +( + IN VOID *Data +) +{ + u32 *Temp = (u32*)&(WDGAdapter.Ctrl); + WDGAdapter.Ctrl.WdgClear = 1; + DBG_8195A("reset WDG\n"); + if (HAL_READ32(SYSTEM_CTRL_BASE,REG_SYS_DSTBY_INFO2) == 0) { + HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp))); + } +} + + +VOID +InitWDGIRQ(VOID) +{ + u32 *Temp = (u32*)&(WDGAdapter.Ctrl); + + WDGAdapter.Ctrl.WdgScalar = 0x96; + WDGAdapter.Ctrl.WdgEnByte = 0xA5; + WDGAdapter.Ctrl.WdgClear = 1; + WDGAdapter.Ctrl.WdgCunLimit = CNTFFFH; + WDGAdapter.Ctrl.WdgMode = RESET_MODE; + WDGAdapter.Ctrl.WdgToISR = 0; + + if (WDGAdapter.Ctrl.WdgMode == INT_MODE) { + + WDGAdapter.IrqHandle.Data = NULL; + WDGAdapter.IrqHandle.IrqFun = (IRQ_FUN)WDGIrqHandle; + WDGAdapter.IrqHandle.IrqNum = WDG_IRQ; + WDGAdapter.IrqHandle.Priority = 0; + + InterruptRegister(&(WDGAdapter.IrqHandle)); + InterruptEn(&(WDGAdapter.IrqHandle)); + } + else { + + WDGAdapter.WdgGTimer.TimerIrqPriority = 0; + WDGAdapter.WdgGTimer.TimerMode = USER_DEFINED; + WDGAdapter.WdgGTimer.IrqDis = OFF; + WDGAdapter.WdgGTimer.TimerId = 2;// + WDGAdapter.WdgGTimer.IrqHandle.IrqFun = (IRQ_FUN)WDGGtimerHandle; + WDGAdapter.WdgGTimer.IrqHandle.IrqNum = TIMER2_7_IRQ; + WDGAdapter.WdgGTimer.IrqHandle.Priority = 0; + WDGAdapter.WdgGTimer.IrqHandle.Data = NULL; + + if ((WDGAdapter.Ctrl.WdgCunLimit == CNTFFFH)&&(WDGAdapter.Ctrl.WdgScalar >= 0x8429)){ + WDGAdapter.WdgGTimer.TimerLoadValueUs = 0xFFFFFFFF - WDGTIMERELY; + } + else { + WDGAdapter.WdgGTimer.TimerLoadValueUs = (BIT0 << (WDGAdapter.Ctrl.WdgCunLimit+1)) + *WDGAdapter.Ctrl.WdgScalar*TIMER_TICK_US - WDGTIMERELY; + } + + HalTimerOp.HalTimerInit((VOID*) &(WDGAdapter.WdgGTimer)); + } + //fill reg + HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp))); +} + + +//WDG +VOID HalWdgInit( + VOID +) +{ + +} +#endif //CONFIG_WDG_TEST +#endif //CONFIG_WDG +#endif //#ifdef CONFIG_TIMER_MODULE diff --git a/lib/fwlib/src/hal_adc.c b/lib/fwlib/src/hal_adc.c new file mode 100644 index 0000000..dc30447 --- /dev/null +++ b/lib/fwlib/src/hal_adc.c @@ -0,0 +1,1603 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#include "basic_types.h" +#include "diag.h" +#include "rand.h" +#include "section_config.h" +#include "rtl_utility.h" +#include "osdep_api.h" +#include "hal_adc.h" +#include "hal_gdma.h" +#include "hal_timer.h" + +#define ADC_STATIC_ALLOC 0 + +static volatile u32 ADCDatBuf[2]; +static volatile u8 ADCFullStsFlag; +static RTK_STATUS +RtkADCPinMuxDeInit( + IN PSAL_ADC_HND pSalADCHND +); + +static RTK_STATUS +RtkADCIrqDeInit( + IN PSAL_ADC_HND pSalADCHND +); + +static RTK_STATUS +RtkADCDMADeInit( + IN PSAL_ADC_HND pSalADCHND +); +/* DAC SAL global variables declaration when kernel disabled */ +#ifndef CONFIG_KERNEL + SRAM_BF_DATA_SECTION + HAL_ADC_OP HalADCOpSAL; +#endif + +#if ADC0_USED /*#if ADC0_USED*/ +#if ADC_STATIC_ALLOC + SRAM_BF_DATA_SECTION + SAL_ADC_MNGT_ADPT SalADC0MngtAdpt; + + SRAM_BF_DATA_SECTION + SAL_ADC_HND_PRIV SalADC0HndPriv; + + SRAM_BF_DATA_SECTION + HAL_ADC_INIT_DAT HalADC0InitData; + + SRAM_BF_DATA_SECTION + IRQ_HANDLE ADC0IrqHandleDat; + + SRAM_BF_DATA_SECTION + HAL_GDMA_ADAPTER HalADC0GdmaAdpt; + + SRAM_BF_DATA_SECTION + HAL_GDMA_OP HalADC0GdmaOp; + + SRAM_BF_DATA_SECTION + IRQ_HANDLE ADC0GDMAIrqHandleDat; + + SRAM_BF_DATA_SECTION + SAL_ADC_USER_CB SalADC0UserCB; + + SRAM_BF_DATA_SECTION + SAL_ADC_USERCB_ADPT SalADC0UserCBAdpt[SAL_ADC_USER_CB_NUM]; +#endif +#endif /*#if ADC0_USED*/ + +#if ADC1_USED /*#if ADC1_USED*/ +#if ADC_STATIC_ALLOC + SRAM_BF_DATA_SECTION + SAL_ADC_MNGT_ADPT SalADC1MngtAdpt; + + SRAM_BF_DATA_SECTION + SAL_ADC_HND_PRIV SalADC1HndPriv; + + SRAM_BF_DATA_SECTION + HAL_ADC_INIT_DAT HalADC1InitData; + + SRAM_BF_DATA_SECTION + IRQ_HANDLE ADC1IrqHandleDat; + + SRAM_BF_DATA_SECTION + HAL_GDMA_ADAPTER HalADC1GdmaAdpt; + + SRAM_BF_DATA_SECTION + HAL_GDMA_OP HalADC1GdmaOp; + + SRAM_BF_DATA_SECTION + IRQ_HANDLE ADC1GDMAIrqHandleDat; + + SRAM_BF_DATA_SECTION + SAL_ADC_USER_CB SalADC1UserCB; + + SRAM_BF_DATA_SECTION + SAL_ADC_USERCB_ADPT SalADC1UserCBAdpt[SAL_ADC_USER_CB_NUM]; +#endif +#endif /*#if ADC1_USED*/ + +#if ADC2_USED /*#if ADC2_USED*/ +#if ADC_STATIC_ALLOC + SRAM_BF_DATA_SECTION + SAL_ADC_MNGT_ADPT SalADC2MngtAdpt; + + SRAM_BF_DATA_SECTION + SAL_ADC_HND_PRIV SalADC2HndPriv; + + SRAM_BF_DATA_SECTION + HAL_ADC_INIT_DAT HalADC2InitData; + + SRAM_BF_DATA_SECTION + IRQ_HANDLE ADC2IrqHandleDat; + + SRAM_BF_DATA_SECTION + HAL_GDMA_ADAPTER HalADC2GdmaAdpt; + + SRAM_BF_DATA_SECTION + HAL_GDMA_OP HalADC2GdmaOp; + + SRAM_BF_DATA_SECTION + IRQ_HANDLE ADC2GDMAIrqHandleDat; + + SRAM_BF_DATA_SECTION + SAL_ADC_USER_CB SalADC2UserCB; + + SRAM_BF_DATA_SECTION + SAL_ADC_USERCB_ADPT SalADC2UserCBAdpt[SAL_ADC_USER_CB_NUM]; +#endif +#endif /*#if ADC2_USED*/ + +#if ADC3_USED /*#if ADC3_USED*/ +#if ADC_STATIC_ALLOC + SRAM_BF_DATA_SECTION + SAL_ADC_MNGT_ADPT SalADC3MngtAdpt; + + SRAM_BF_DATA_SECTION + SAL_ADC_HND_PRIV SalADC3HndPriv; + + SRAM_BF_DATA_SECTION + HAL_ADC_INIT_DAT HalADC3InitData; + + SRAM_BF_DATA_SECTION + IRQ_HANDLE ADC3IrqHandleDat; + + SRAM_BF_DATA_SECTION + HAL_GDMA_ADAPTER HalADC3GdmaAdpt; + + SRAM_BF_DATA_SECTION + HAL_GDMA_OP HalADC3GdmaOp; + + SRAM_BF_DATA_SECTION + IRQ_HANDLE ADC3GDMAIrqHandleDat; + + SRAM_BF_DATA_SECTION + SAL_ADC_USER_CB SalADC3UserCB; + + SRAM_BF_DATA_SECTION + SAL_ADC_USERCB_ADPT SalADC3UserCBAdpt[SAL_ADC_USER_CB_NUM]; +#endif +#endif /*#if ADC3_USED*/ + +/* Global variables */ +u8 SalAdcInitialFlag = 0; +#ifdef CONFIG_SOC_PS_MODULE +u8 SalAdcEnableState = 0; +#endif + +HAL_ADC_INIT_DAT SalAdcInitialDatKeep = {.ADCIdx = 0, + .ADCEn = 0, + .ADCEndian = 0, + .ADCBurstSz = 0, + .ADCCompOnly = 0, + .ADCOneShotEn = 0, + .ADCOverWREn = 0, + .ADCOneShotTD = 0, + .ADCCompCtrl = 0, + .ADCCompTD = 0, + .ADCDataRate = 0, + .ADCAudioEn = 0, + .ADCEnManul = 0, + .ADCDbgSel = 0, + .RSVD0 = 0, + .ADCData = (u32 *)NULL, + .ADCPWCtrl = 0, + .ADCIntrMSK = 0}; + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CGetMngtAdpt +// +// Description: +// According to the input index, all the memory space are allocated and all the +// related pointers are assigned. The management adapter pointer will be +// returned. +// +// Arguments: +// [in] u8 I2CIdx - +// I2C module index +// +// Return: +// PSAL_I2C_MNGT_ADPT +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//--------------------------------------------------------------------------------------------------- +VOID HalADCOpInit( + IN VOID *Data +) +{ + PHAL_ADC_OP pHalAdcOp = (PHAL_ADC_OP) Data; + + pHalAdcOp->HalADCInit = HalADCInit8195a; + pHalAdcOp->HalADCDeInit = HalADCDeInit8195a; + pHalAdcOp->HalADCEnable = HalADCEnableRtl8195a; + pHalAdcOp->HalADCReceive = HalADCReceiveRtl8195a; + pHalAdcOp->HalADCIntrCtrl = HalADCIntrCtrl8195a; + pHalAdcOp->HalADCReadReg = HalADCReadRegRtl8195a; +} + +#ifndef CONFIG_MBED_ENABLED +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CGetMngtAdpt +// +// Description: +// According to the input index, all the memory space are allocated and all the +// related pointers are assigned. The management adapter pointer will be +// returned. +// +// Arguments: +// [in] u8 I2CIdx - +// I2C module index +// +// Return: +// PSAL_I2C_MNGT_ADPT +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//--------------------------------------------------------------------------------------------------- +PSAL_ADC_MNGT_ADPT +RtkADCGetMngtAdpt( + IN u8 ADCIdx +){ + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PSAL_ADC_USERCB_ADPT pSalADCUserCBAdpt = NULL; + + /* If the kernel is available, Memory-allocation is used. */ +#if (!ADC_STATIC_ALLOC) + pSalADCMngtAdpt = (PSAL_ADC_MNGT_ADPT)RtlZmalloc(sizeof(SAL_ADC_MNGT_ADPT)); + pSalADCMngtAdpt->pSalHndPriv = (PSAL_ADC_HND_PRIV)RtlZmalloc(sizeof(SAL_ADC_HND_PRIV)); + pSalADCMngtAdpt->pHalInitDat = (PHAL_ADC_INIT_DAT)RtlZmalloc(sizeof(HAL_ADC_INIT_DAT)); + pSalADCMngtAdpt->pHalOp = (PHAL_ADC_OP)RtlZmalloc(sizeof(HAL_ADC_OP)); + pSalADCMngtAdpt->pIrqHnd = (PIRQ_HANDLE)RtlZmalloc(sizeof(IRQ_HANDLE)); + pSalADCMngtAdpt->pUserCB = (PSAL_ADC_USER_CB)RtlZmalloc(sizeof(SAL_ADC_USER_CB)); + pSalADCMngtAdpt->pHalGdmaAdp = (PHAL_GDMA_ADAPTER)RtlZmalloc(sizeof(HAL_GDMA_ADAPTER)); + pSalADCMngtAdpt->pHalGdmaOp = (PHAL_GDMA_OP)RtlZmalloc(sizeof(HAL_GDMA_OP)); + pSalADCMngtAdpt->pIrqGdmaHnd = (PIRQ_HANDLE)RtlZmalloc(sizeof(IRQ_HANDLE)); + pSalADCUserCBAdpt = (PSAL_ADC_USERCB_ADPT)RtlZmalloc((sizeof(SAL_ADC_USERCB_ADPT)*SAL_ADC_USER_CB_NUM)); +#else + switch (ADCIdx){ + case ADC0_SEL: + { + pSalADCMngtAdpt = &SalADC0MngtAdpt; + pSalADCMngtAdpt->pSalHndPriv = &SalADC0HndPriv; + pSalADCMngtAdpt->pHalInitDat = &HalADC0InitData; + pSalADCMngtAdpt->pHalOp = &HalADCOpSAL; + pSalADCMngtAdpt->pIrqHnd = &ADC0IrqHandleDat; + pSalADCMngtAdpt->pHalGdmaAdp = &HalADC0GdmaAdpt; + pSalADCMngtAdpt->pHalGdmaOp = &HalADC0GdmaOp; + pSalADCMngtAdpt->pIrqGdmaHnd = &ADC0GDMAIrqHandleDat; + pSalADCMngtAdpt->pUserCB = &SalADC0UserCB; + pSalADCUserCBAdpt = &SalADC0UserCBAdpt; + break; + } + + case ADC1_SEL: + { + pSalADCMngtAdpt = &SalADC1MngtAdpt; + pSalADCMngtAdpt->pSalHndPriv = &SalADC1HndPriv; + pSalADCMngtAdpt->pHalInitDat = &HalADC1InitData; + pSalADCMngtAdpt->pHalOp = &HalADCOpSAL; + pSalADCMngtAdpt->pIrqHnd = &ADC1IrqHandleDat; + pSalADCMngtAdpt->pHalGdmaAdp = &HalADC1GdmaAdpt; + pSalADCMngtAdpt->pHalGdmaOp = &HalADC1GdmaOp; + pSalADCMngtAdpt->pIrqGdmaHnd = &ADC1GDMAIrqHandleDat; + pSalADCMngtAdpt->pUserCB = &SalADC1UserCB; + pSalADCUserCBAdpt = &SalADC1UserCBAdpt; + break; + } + + case ADC2_SEL: + { + pSalADCMngtAdpt = &SalADC2MngtAdpt; + pSalADCMngtAdpt->pSalHndPriv = &SalADC2HndPriv; + pSalADCMngtAdpt->pHalInitDat = &HalADC2InitData; + pSalADCMngtAdpt->pHalOp = &HalADCOpSAL; + pSalADCMngtAdpt->pIrqHnd = &ADC2IrqHandleDat; + pSalADCMngtAdpt->pHalGdmaAdp = &HalADC2GdmaAdpt; + pSalADCMngtAdpt->pHalGdmaOp = &HalADC2GdmaOp; + pSalADCMngtAdpt->pIrqGdmaHnd = &ADC2GDMAIrqHandleDat; + pSalADCMngtAdpt->pUserCB = &SalADC2UserCB; + pSalADCUserCBAdpt = &SalADC2UserCBAdpt; + break; + } + + case ADC3_SEL: + { + pSalADCMngtAdpt = &SalADC3MngtAdpt; + pSalADCMngtAdpt->pSalHndPriv = &SalADC3HndPriv; + pSalADCMngtAdpt->pHalInitDat = &HalADC3InitData; + pSalADCMngtAdpt->pHalOp = &HalADCOpSAL; + pSalADCMngtAdpt->pIrqHnd = &ADC3IrqHandleDat; + pSalADCMngtAdpt->pHalGdmaAdp = &HalADC3GdmaAdpt; + pSalADCMngtAdpt->pHalGdmaOp = &HalADC3GdmaOp; + pSalADCMngtAdpt->pIrqGdmaHnd = &ADC3GDMAIrqHandleDat; + pSalADCMngtAdpt->pUserCB = &SalADC3UserCB; + pSalADCUserCBAdpt = &SalADC3UserCBAdpt; + break; + } + default + break; + } +#endif + + /*To assign user callback pointers*/ + pSalADCMngtAdpt->pUserCB->pTXCB = pSalADCUserCBAdpt; + pSalADCMngtAdpt->pUserCB->pTXCCB = (pSalADCUserCBAdpt+1); + pSalADCMngtAdpt->pUserCB->pRXCB = (pSalADCUserCBAdpt+2); + pSalADCMngtAdpt->pUserCB->pRXCCB = (pSalADCUserCBAdpt+3); + pSalADCMngtAdpt->pUserCB->pRDREQCB = (pSalADCUserCBAdpt+4); + pSalADCMngtAdpt->pUserCB->pERRCB = (pSalADCUserCBAdpt+5); + pSalADCMngtAdpt->pUserCB->pDMATXCB = (pSalADCUserCBAdpt+6); + pSalADCMngtAdpt->pUserCB->pDMATXCCB = (pSalADCUserCBAdpt+7); + pSalADCMngtAdpt->pUserCB->pDMARXCB = (pSalADCUserCBAdpt+8); + pSalADCMngtAdpt->pUserCB->pDMARXCCB = (pSalADCUserCBAdpt+9); + + /*To assign the rest pointers*/ + pSalADCMngtAdpt->pSalHndPriv->ppSalADCHnd = (void**)&(pSalADCMngtAdpt->pSalHndPriv); + + /* To assign the default (ROM) HAL OP initialization function */ + pSalADCMngtAdpt->pHalOpInit = &HalADCOpInit; + + /* To assign the default (ROM) HAL GDMA OP initialization function */ + pSalADCMngtAdpt->pHalGdmaOpInit = &HalGdmaOpInit; + + /* To assign the default (ROM) SAL interrupt function */ + pSalADCMngtAdpt->pSalIrqFunc = &ADCISRHandle; + + /* To assign the default (ROM) SAL DMA TX interrupt function */ + pSalADCMngtAdpt->pSalDMAIrqFunc = &ADCGDMAISRHandle; + + return pSalADCMngtAdpt; +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CFreeMngtAdpt +// +// Description: +// Free all the previous allocated memory space. +// +// Arguments: +// [in] PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt - +// I2C SAL management adapter pointer +// +// +// Return: +// The status of the enable process. +// _EXIT_SUCCESS if the RtkI2CFreeMngtAdpt succeeded. +// _EXIT_FAILURE if the RtkI2CFreeMngtAdpt failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//--------------------------------------------------------------------------------------------------- +RTK_STATUS +RtkADCFreeMngtAdpt( + IN PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt +){ +#ifdef CONFIG_KERNEL + RtlMfree((u8 *)pSalADCMngtAdpt->pUserCB->pTXCB, (sizeof(SAL_ADC_USERCB_ADPT)*SAL_ADC_USER_CB_NUM)); + RtlMfree((u8 *)pSalADCMngtAdpt->pIrqGdmaHnd, sizeof(IRQ_HANDLE)); + RtlMfree((u8 *)pSalADCMngtAdpt->pHalGdmaOp, sizeof(HAL_GDMA_OP)); + RtlMfree((u8 *)pSalADCMngtAdpt->pHalGdmaAdp, sizeof(HAL_GDMA_ADAPTER)); + RtlMfree((u8 *)pSalADCMngtAdpt->pUserCB, sizeof(SAL_ADC_USER_CB)); + RtlMfree((u8 *)pSalADCMngtAdpt->pIrqHnd, sizeof(IRQ_HANDLE)); + RtlMfree((u8 *)pSalADCMngtAdpt->pHalOp, sizeof(HAL_ADC_OP)); + RtlMfree((u8 *)pSalADCMngtAdpt->pHalInitDat, sizeof(HAL_ADC_INIT_DAT)); + RtlMfree((u8 *)pSalADCMngtAdpt->pSalHndPriv, sizeof(SAL_ADC_HND_PRIV)); + RtlMfree((u8 *)pSalADCMngtAdpt, sizeof(SAL_ADC_MNGT_ADPT)); +#else + ; +#endif + + return _EXIT_SUCCESS; +} +#endif + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// I2CISRHandle +// +// Description: +// I2C Interrupt Service Routine. +// According to the input pointer to SAL_I2C_HND, all the rest pointers will be +// found and be used to the rest part of this servie routine. +// The following types of interrupt will be taken care: +// - General Call (providing General Call Callback). Slave receives a general call. +// - STOP Bit (NOT providing General Call Callback) +// - START Bit (NOTproviding General Call Callback) +// - I2C Activity (NOTproviding General Call Callback) +// - RX Done (providing Error Callback). The slave transmitter does NOT +// receive a proper NACK for the end of whole transfer. +// - TX Abort (providing Error Call Callback). The Master/Slave +// transmitting is terminated. +// - RD Req (providing TX and TXC Callback). Slave gets a Read Request +// and starts a slave-transmitter operation. The slave transmit +// data will be written into slave TX FIFO from user data buffer. +// - TX Empty (providing TX and TXC Callback). Master TX FIFO is empty. +// The user transmit data will be written into master TX FIFO +// from user data buffer. +// - TX Over (providing Error Callback). Master TX FIFO is Overflow. +// - RX Full (providing RX and RXC Callback). Master/Slave RX FIFO contains +// data. And the received data will be put into Master/Slave user +// receive data buffer. +// - RX Over (providing Error Callback). Master/Slave RX FIFO is Overflow. +// - RX Under (providing Error Callback). Master/Slave RX FIFO is Underflow. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// NA +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//---------------------------------------------------------------------------------------------------- +VOID +ADCISRHandle( + IN VOID *Data +){ +#ifdef CONFIG_DEBUG_LOG_ADC_HAL + PSAL_ADC_HND pSalADCHND = (PSAL_ADC_HND) Data; + PSAL_ADC_HND_PRIV pSalADCHNDPriv = NULL; + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PHAL_ADC_INIT_DAT pHalADCInitDat = NULL; + PHAL_ADC_OP pHalADCOP = NULL; + PSAL_ADC_USER_CB pSalADCUserCB = NULL; + u8 ADCIrqIdx; + + /* To get the SAL_I2C_MNGT_ADPT pointer, and parse the rest pointers */ + pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv); + pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv); + pHalADCInitDat = pSalADCMngtAdpt->pHalInitDat; + pHalADCOP = pSalADCMngtAdpt->pHalOp; + ADCIrqIdx = pHalADCInitDat->ADCIdx; + pSalADCUserCB = pSalADCHND->pUserCB; + + DBG_8195A_ADC_LVL(HAL_ADC_LVL,"ADC INTR STS:%x\n",pHalADCOP->HalADCReadReg(pHalADCInitDat, REG_ADC_INTR_STS)); +#else + PSAL_ADC_HND pSalADCHND = (PSAL_ADC_HND) Data; + PSAL_ADC_HND_PRIV pSalADCHNDPriv = NULL; + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PHAL_ADC_INIT_DAT pHalADCInitDat = NULL; + PHAL_ADC_OP pHalADCOP = NULL; + + u8 ADCIrqIdx; + + + /* To get the SAL_I2C_MNGT_ADPT pointer, and parse the rest pointers */ + pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv); + pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv); + pHalADCInitDat = pSalADCMngtAdpt->pHalInitDat; + pHalADCOP = pSalADCMngtAdpt->pHalOp; + ADCIrqIdx = pHalADCInitDat->ADCIdx; + + DBG_ADC_INFO("ADC INTR STS:%x\n",pHalADCOP->HalADCReadReg(pHalADCInitDat, REG_ADC_INTR_STS)); + if (pSalADCHND->OpType == ADC_RDREG_TYPE){ + ADCFullStsFlag = 1; + ADCDatBuf[0] = (u32)HAL_ADC_READ32(REG_ADC_FIFO_READ); + ADCDatBuf[1] = (u32)HAL_ADC_READ32(REG_ADC_FIFO_READ); + pSalADCHND->pInitDat->ADCIntrMSK = 0; + pHalADCOP->HalADCIntrCtrl(pSalADCHND->pInitDat); + } + else + pHalADCOP->HalADCReadReg(pHalADCInitDat, REG_ADC_INTR_STS); + +#endif +} + +VOID +ADCGDMAISRHandle( + IN VOID *Data +){ + + /* DBG_ENTRANCE; */ + PSAL_ADC_HND pSalADCHND = (PSAL_ADC_HND) Data; + PSAL_ADC_HND_PRIV pSalADCHNDPriv = NULL; + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + + PHAL_ADC_OP pHalADCOP = NULL; + PSAL_ADC_USER_CB pSalADCUserCB = NULL; + + PHAL_GDMA_ADAPTER pHalADCGdmaAdapter; + PHAL_GDMA_OP pHalADCGdmaOp; + + + u8 IsrTypeMap = 0; + + /* To get the SAL_I2C_MNGT_ADPT pointer, and parse the rest pointers */ + pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv); + pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv); + + pHalADCOP = pSalADCMngtAdpt->pHalOp; + + pSalADCUserCB = pSalADCHND->pUserCB; + + pHalADCGdmaAdapter = pSalADCMngtAdpt->pHalGdmaAdp; + pHalADCGdmaOp = pSalADCMngtAdpt->pHalGdmaOp; + + DBG_8195A_ADC_LVL(HAL_ADC_LVL,"%s\n",__func__); + + if ((pHalADCGdmaAdapter->MaxMuliBlock) == pHalADCGdmaAdapter->MuliBlockCunt+1) { + pSalADCHND->pInitDat->ADCIntrMSK = 0; + pHalADCOP->HalADCIntrCtrl(pSalADCHND->pInitDat); + + /* Clear ADC Status */ + HAL_ADC_READ32(REG_ADC_INTR_STS); + + pSalADCHND->pInitDat->ADCEn = ADC_DISABLE; + pHalADCOP->HalADCEnable(pSalADCHND->pInitDat); + pHalADCGdmaOp->HalGdmaChCleanAutoSrc(pHalADCGdmaAdapter); + pHalADCGdmaOp->HalGdmaChDis(pHalADCGdmaAdapter); + pSalADCHND->DevSts = ADC_STS_IDLE; + + if (pSalADCUserCB->pDMARXCCB->USERCB != NULL) { + pSalADCUserCB->pDMARXCCB->USERCB((VOID*)pSalADCUserCB->pDMARXCCB->USERData); + } + } + + //3 Clear Pending ISR + IsrTypeMap = pHalADCGdmaOp->HalGdmaChIsrClean((VOID*)pHalADCGdmaAdapter); + + //3 Maintain Block Count + if (IsrTypeMap & BlockType) { + pHalADCGdmaAdapter->MuliBlockCunt++; + } +} + +RTK_STATUS +RtkADCPinMuxInit( + IN PSAL_ADC_HND pSalADCHND +){ + + u32 ADCLocalTemp; + + /* Check the I2C index first */ + if (RtkADCIdxChk(pSalADCHND->DevNum)) + return _EXIT_FAILURE; + + ADCLocalTemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL2); + ADCLocalTemp |= BIT25; + + /* To release DAC delta sigma clock gating */ + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SYS_SYSPLL_CTRL2,ADCLocalTemp); + + /* Turn on DAC active clock */ + ACTCK_ADC_CCTRL(ON); + + /* Enable DAC0 module */ + ADC0_FCTRL(ON); + + return _EXIT_SUCCESS; + +} + +static RTK_STATUS +RtkADCPinMuxDeInit( + IN PSAL_ADC_HND pSalADCHND +){ + + u32 ADCLocalTemp; + + /* Check the I2C index first */ + if (RtkADCIdxChk(pSalADCHND->DevNum)) + return _EXIT_FAILURE; + + /* Turn on DAC active clock */ + ACTCK_ADC_CCTRL(OFF); + + /* Enable DAC1 module */ + ADC0_FCTRL(OFF); + + ADCLocalTemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL2); + ADCLocalTemp &= (~BIT25); + + /* To release DAC delta sigma clock gating */ + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SYS_SYSPLL_CTRL2,ADCLocalTemp); + return _EXIT_SUCCESS; +} + + +#if ADC_INTR_OP_TYPE +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CIrqInit +// +// Description: +// I2C interrupt initialization function. +// For I2C interrupt operation mode, I2C module MUST register itself to the platform +// by providing the interrupt handler which contains interrupt input data (arguments), +// interrupt service routine, interrupt number, interrupt priority. And then the interrupt +// should be enabled. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C interrupt initialization process. +// _EXIT_SUCCESS if the RtkI2CIrqInit succeeded. +// _EXIT_FAILURE if the RtkI2CIrqInit failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +static RTK_STATUS +RtkADCIrqInit( + IN PSAL_ADC_HND pSalADCHND +){ + + PSAL_ADC_HND_PRIV pSalADCHNDPriv = NULL; + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PIRQ_HANDLE pIrqHandle = NULL; + + /* To Get the SAL_I2C_MNGT_ADPT Pointer */ + pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv); + pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv); + pIrqHandle = pSalADCMngtAdpt->pIrqHnd; +/* + if (RtkADCIdxChk(pSalADCHND->DevNum)) + return _EXIT_FAILURE; +*/ + + pIrqHandle->Data = (u32)(pSalADCHND); + pIrqHandle->IrqNum = ADC_IRQ; + pIrqHandle->IrqFun = (IRQ_FUN)pSalADCMngtAdpt->pSalIrqFunc; + pIrqHandle->Priority = 5; + InterruptRegister(pIrqHandle); + InterruptEn(pIrqHandle); + + return _EXIT_SUCCESS; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CIrqDeInit +// +// Description: +// I2C interrupt de-initialization function. +// According to the given I2C device number, the I2C interrupt will be unreigster +// from the platform and the relative interrupt handler will be cleared. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C interrupt de-initialization process. +// _EXIT_SUCCESS if the RtkI2CIrqDeInit succeeded. +// _EXIT_FAILURE if the RtkI2CIrqDeInit failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +static RTK_STATUS +RtkADCIrqDeInit( + IN PSAL_ADC_HND pSalADCHND +){ + + PSAL_ADC_HND_PRIV pSalADCHNDPriv = NULL; + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PIRQ_HANDLE pIrqHandle = NULL; + + /* To Get the SAL_I2C_MNGT_ADPT Pointer */ + pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv); + pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv); + pIrqHandle = pSalADCMngtAdpt->pIrqHnd; +/* + if (RtkADCIdxChk(pSalADCHND->DevNum)) + return _EXIT_FAILURE; +*/ + InterruptUnRegister(pIrqHandle); + return _EXIT_SUCCESS; + +} + +#endif + + +#if ADC_DMA_OP_TYPE +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CIrqInit +// +// Description: +// I2C interrupt initialization function. +// For I2C interrupt operation mode, I2C module MUST register itself to the platform +// by providing the interrupt handler which contains interrupt input data (arguments), +// interrupt service routine, interrupt number, interrupt priority. And then the interrupt +// should be enabled. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C interrupt initialization process. +// _EXIT_SUCCESS if the RtkI2CIrqInit succeeded. +// _EXIT_FAILURE if the RtkI2CIrqInit failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +static RTK_STATUS +RtkADCDMAInit( + IN PSAL_ADC_HND pSalADCHND +){ + PSAL_ADC_HND_PRIV pSalADCHNDPriv = NULL; + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PHAL_GDMA_ADAPTER pHALADCGdmaAdpt = NULL; + PHAL_GDMA_OP pHALADCGdmaOp = NULL; + PIRQ_HANDLE pIrqHandleADCGdma = NULL; + + /* To Get the SAL_I2C_MNGT_ADPT Pointer */ + pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv); + pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv); + + pHALADCGdmaAdpt = pSalADCMngtAdpt->pHalGdmaAdp; + pHALADCGdmaOp = pSalADCMngtAdpt->pHalGdmaOp; + pIrqHandleADCGdma = pSalADCMngtAdpt->pIrqGdmaHnd; +/* + if (RtkADCIdxChk(pSalADCHND->DevNum)) + return _EXIT_FAILURE; +*/ + //HalGdmaOpInit(pHALADCGdmaOp); + pSalADCMngtAdpt->pHalGdmaOpInit(pHALADCGdmaOp); + _memset((void *)pHALADCGdmaAdpt, 0, sizeof(HAL_GDMA_ADAPTER)); + + pHALADCGdmaAdpt->GdmaCtl.IntEn = 1; + + //ADC RX DMA + pHALADCGdmaAdpt->GdmaCtl.SrcTrWidth = TrWidthFourBytes; + pHALADCGdmaAdpt->GdmaCtl.DstTrWidth = TrWidthFourBytes; + pHALADCGdmaAdpt->GdmaCtl.SrcMsize = MsizeEight; + pHALADCGdmaAdpt->GdmaCtl.DestMsize = MsizeEight; + + pHALADCGdmaAdpt->GdmaCtl.Sinc = NoChange; + pHALADCGdmaAdpt->GdmaCtl.Dinc = IncType; + + pHALADCGdmaAdpt->GdmaCtl.Done = 1; + pHALADCGdmaAdpt->GdmaCtl.TtFc = (GDMA_CTL_TT_FC_TYPE)0x2; + + pHALADCGdmaAdpt->GdmaCfg.SrcPer = 12; + pHALADCGdmaAdpt->GdmaCfg.ReloadSrc = 1; + + pHALADCGdmaAdpt->MuliBlockCunt = 0; + pHALADCGdmaAdpt->MaxMuliBlock = 1;//MaxLlp; + + pHALADCGdmaAdpt->GdmaIsrType = (BlockType|TransferType|ErrType); + pHALADCGdmaAdpt->IsrCtrl = ENABLE; + pHALADCGdmaAdpt->GdmaOnOff = ON; + + pHALADCGdmaAdpt->ChNum = 4; + pHALADCGdmaAdpt->ChEn = GdmaCh4; + + pHALADCGdmaAdpt->TestItem = 3; + DBG_ADC_INFO("pSalADCHND->DevNum:%x\n",pSalADCHND->DevNum); + + pHALADCGdmaAdpt->GdmaIndex = 1; + pIrqHandleADCGdma->IrqNum = GDMA1_CHANNEL4_IRQ; + + /* GDMA interrupt register */ + pIrqHandleADCGdma->Data = (u32) (pSalADCHND); + pIrqHandleADCGdma->IrqFun = (IRQ_FUN) pSalADCMngtAdpt->pSalDMAIrqFunc; + pIrqHandleADCGdma->Priority = 2; + InterruptRegister(pIrqHandleADCGdma); + InterruptEn(pIrqHandleADCGdma); + + /* GDMA initialization */ + /* Enable the whole GDMA module first */ + if (pHALADCGdmaAdpt->GdmaIndex == 0) { + ACTCK_GDMA0_CCTRL(ON); + SLPCK_GDMA0_CCTRL(ON); + GDMA0_FCTRL(ON); + } + else { + ACTCK_GDMA1_CCTRL(ON); + SLPCK_GDMA1_CCTRL(ON); + GDMA1_FCTRL(ON); + } + + pHALADCGdmaOp->HalGdmaOnOff((VOID*)pHALADCGdmaAdpt); + pHALADCGdmaOp->HalGdmaChIsrEnAndDis((VOID*)pHALADCGdmaAdpt); + //pHALADCGdmaOp->HalGdmaChSeting((VOID*)pHALADCGdmaAdpt); + + return _EXIT_SUCCESS; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CIrqDeInit +// +// Description: +// I2C interrupt de-initialization function. +// According to the given I2C device number, the I2C interrupt will be unreigster +// from the platform and the relative interrupt handler will be cleared. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C interrupt de-initialization process. +// _EXIT_SUCCESS if the RtkI2CIrqDeInit succeeded. +// _EXIT_FAILURE if the RtkI2CIrqDeInit failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +static RTK_STATUS +RtkADCDMADeInit( + IN PSAL_ADC_HND pSalADCHND +){ + PSAL_ADC_HND_PRIV pSalADCHNDPriv = NULL; + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + + PHAL_GDMA_ADAPTER pHALADCGdmaAdpt = NULL; + PHAL_GDMA_OP pHALADCGdmaOp = NULL; + PIRQ_HANDLE pIrqHandleADCGdma = NULL; + + /*To Get the SAL_I2C_MNGT_ADPT Pointer*/ + pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv); + pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv); + + pHALADCGdmaAdpt = pSalADCMngtAdpt->pHalGdmaAdp; + pHALADCGdmaOp = pSalADCMngtAdpt->pHalGdmaOp; + pIrqHandleADCGdma = pSalADCMngtAdpt->pIrqGdmaHnd; + + if (RtkADCIdxChk(pSalADCHND->DevNum)) + return _EXIT_FAILURE; + + //HalGdmaOpInit(pHALADCGdmaOp); + pSalADCMngtAdpt->pHalGdmaOpInit(pHALADCGdmaOp); + + pHALADCGdmaAdpt->IsrCtrl = DISABLE; + pHALADCGdmaOp->HalGdmaChIsrEnAndDis((VOID*)pHALADCGdmaAdpt); + pHALADCGdmaOp->HalGdmaChIsrClean((VOID*)pHALADCGdmaAdpt); + pHALADCGdmaOp->HalGdmaChDis((VOID*)pHALADCGdmaAdpt); + + InterruptUnRegister(pIrqHandleADCGdma); +#if 0 + _memset((void *)pIrqHandleDACGdma , 0, sizeof(IRQ_HANDLE)); + _memset((void *)pHALDACGdmaOp , 0, sizeof(HAL_GDMA_OP)); + _memset((void *)pHALDACGdmaAdpt , 0, sizeof(HAL_GDMA_ADAPTER)); +#endif + return _EXIT_SUCCESS; + +} +#endif + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CInit +// +// Description: +// According to the given I2C index, the related SAL_I2C_MNGT_ADPT pointer used +// for retrieving each I2C data sturcture pointer will be reversely parsed first. +// Then, initializing I2C HAL operation, initializing I2C interrupt (if needed), +// initializing I2C DMA (if needed) and initializing I2C pinmux will be done. +// User specified I2C configuration will be assigned to I2C initial data structure +// (PHAL_I2C_INIT_DAT pHalI2CInitDat). I2C HAL initialization is executed after +// all the configuration data taken. +// In the end, I2C module is enabled as a final step of the whole initialization. +// For a slave ack General Call support, an additional step may be followed after +// the above steps. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C initialization process. +// _EXIT_SUCCESS if the RtkI2CInit succeeded. +// _EXIT_FAILURE if the RtkI2CInit failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +RTK_STATUS +RtkADCInit( + IN VOID *Data +){ + PSAL_ADC_HND pSalADCHND = (PSAL_ADC_HND) Data; + PSAL_ADC_HND_PRIV pSalADCHNDPriv = NULL; + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PHAL_ADC_INIT_DAT pHalADCInitDat = NULL; + PHAL_ADC_OP pHalADCOP = NULL; + +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE adcPwrState; +#endif + + DBG_ADC_INFO("%s\n",__func__); + /* To Get the SAL_ADC_MNGT_ADPT Pointer */ + pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv); + pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv); + + pHalADCInitDat = pSalADCMngtAdpt->pHalInitDat; + pHalADCOP = pSalADCMngtAdpt->pHalOp; + + /* Check the input I2C index first */ + if (RtkADCIdxChk(pSalADCHND->DevNum)) + return _EXIT_FAILURE; + +#if 0 + /* Check the input I2C operation type */ + if (RtkI2COpTypeChk(pSalI2CHND)) + return _EXIT_FAILURE; +#endif + + /* ADC Initial data check, if the setting is different from the previous initial data, + an warning is shown on Log-Uart and directly return from this function */ + if (SalAdcInitialFlag != 0) { + if (_memcmp(pHalADCInitDat, &SalAdcInitialDatKeep, sizeof(HAL_ADC_INIT_DAT))) { + pSalADCMngtAdpt->pHalOpInit(pHalADCOP); + /* DAC Device Status Update */ + pSalADCHND->DevSts = ADC_STS_IDLE; + DBG_ADC_WARN("The ADC initial value is different from the previous value.\n"); + } + } + else { + /* ADC Initialize HAL Operations */ + //HalADCOpInit(pHalADCOP); + pSalADCMngtAdpt->pHalOpInit(pHalADCOP); + + /* ADC Interrupt Initialization */ +#if ADC_INTR_OP_TYPE + RtkADCIrqInit(pSalADCHND); +#endif + + /* ADC DMA Initialization */ +#if ADC_DMA_OP_TYPE + RtkADCDMAInit(pSalADCHND); +#endif + + /* ADC Function and Clock Enable*/ + RtkADCPinMuxInit(pSalADCHND); + pHalADCOP->HalADCInit(pSalADCHND->pInitDat); + + if (pSalADCHND->OpType == ADC_DMA_TYPE){ + pSalADCHND->pInitDat->ADCIntrMSK = (BIT_ADC_FIFO_RD_REQ_EN | + BIT_ADC_FIFO_RD_ERROR_EN); + } + else if (pSalADCHND->OpType == ADC_INTR_TYPE){ + pSalADCHND->pInitDat->ADCIntrMSK = (BIT_ADC_FIFO_FULL_EN | + BIT_ADC_FIFO_RD_REQ_EN | + BIT_ADC_FIFO_RD_ERROR_EN); + } + else{ + pSalADCHND->pInitDat->ADCIntrMSK = 0; + } + + + if (pHalADCInitDat->ADCOneShotEn == ADC_FEATURE_ENABLED) { + pSalADCHND->pInitDat->ADCIntrMSK |= BIT_ADC_AWAKE_CPU_EN; + } + pHalADCOP->HalADCIntrCtrl(pSalADCHND->pInitDat); + + //pSalADCHND->pInitDat->ADCEn = ADC_ENABLE; + //pHalADCOP->HalADCEnable(pSalADCHND->pInitDat); + + if (pHalADCInitDat->ADCOneShotEn == ADC_FEATURE_ENABLED) { + HAL_TIMER_WRITE32(TIMER_INTERVAL, 30); + HAL_TIMER_WRITE32(0x1C, 3); + } + + SalAdcInitialFlag |= (0x01 << pSalADCHND->DevNum); + _memcpy(&SalAdcInitialDatKeep, pSalADCHND->pInitDat, sizeof(HAL_ADC_INIT_DAT)); + } + + /* DAC Device Status Update */ + pSalADCHND->DevSts = ADC_STS_IDLE; + +#ifdef CONFIG_SOC_PS_MODULE + // To register a new peripheral device power state + adcPwrState.FuncIdx = ADC0; + adcPwrState.PwrState = ACT; + RegPowerState(adcPwrState); + + SalAdcEnableState |= (0x01 << pSalADCHND->DevNum); +#endif + + return _EXIT_SUCCESS; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CInit +// +// Description: +// According to the given I2C index, the related SAL_I2C_MNGT_ADPT pointer used +// for retrieving each I2C data sturcture pointer will be reversely parsed first. +// Then, initializing I2C HAL operation, initializing I2C interrupt (if needed), +// initializing I2C DMA (if needed) and initializing I2C pinmux will be done. +// User specified I2C configuration will be assigned to I2C initial data structure +// (PHAL_I2C_INIT_DAT pHalI2CInitDat). I2C HAL initialization is executed after +// all the configuration data taken. +// In the end, I2C module is enabled as a final step of the whole initialization. +// For a slave ack General Call support, an additional step may be followed after +// the above steps. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C initialization process. +// _EXIT_SUCCESS if the RtkI2CInit succeeded. +// _EXIT_FAILURE if the RtkI2CInit failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +RTK_STATUS +RtkADCDeInit( + IN VOID *Data +){ + PSAL_ADC_HND pSalADCHND = (PSAL_ADC_HND) Data; + PSAL_ADC_HND_PRIV pSalADCHNDPriv = NULL; + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PHAL_ADC_INIT_DAT pHalADCInitDat = NULL; + PHAL_ADC_OP pHalADCOP = NULL; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE adcPwrState; + u8 HwState; +#endif + + /* To Get the SAL_ADC_MNGT_ADPT Pointer */ + pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv); + pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv); + + pHalADCInitDat = pSalADCMngtAdpt->pHalInitDat; + pHalADCOP = pSalADCMngtAdpt->pHalOp; + + /* Check the input ADC index first */ + if (RtkADCIdxChk(pSalADCHND->DevNum)) + return _EXIT_FAILURE; + + SalAdcInitialFlag &= (~(0x01 << pSalADCHND->DevNum)); + + if (SalAdcInitialFlag == 0) { +#ifdef CONFIG_SOC_PS_MODULE + adcPwrState.FuncIdx = ADC0; + QueryRegPwrState(adcPwrState.FuncIdx, &(adcPwrState.PwrState), &HwState); + + // if the power state isn't ACT, then switch the power state back to ACT first + if ((adcPwrState.PwrState != ACT) && (adcPwrState.PwrState != INACT)) { + RtkADCEnablePS(Data); + QueryRegPwrState(adcPwrState.FuncIdx, &(adcPwrState.PwrState), &HwState); + } + + if (adcPwrState.PwrState == ACT) { + adcPwrState.PwrState = INACT; + RegPowerState(adcPwrState); + } +#endif + + /* ADC Initialize HAL Operations */ + HalADCOpInit(pHalADCOP); + + RtkADCPinMuxDeInit(pSalADCHND); + + /* ADC Interrupt Initialization */ +#if ADC_INTR_OP_TYPE + RtkADCIrqDeInit(pSalADCHND); +#endif + + /* ADC DMA Initialization */ +#if ADC_DMA_OP_TYPE + RtkADCDMADeInit(pSalADCHND); +#endif + + pHalADCInitDat->ADCEn = ADC_DISABLE; + pHalADCOP->HalADCEnable(pHalADCInitDat); + pHalADCOP->HalADCDeInit(pHalADCInitDat); + + /* ADC Function and Clock Enable*/ + RtkADCPinMuxDeInit(pSalADCHND); + } + + return _EXIT_SUCCESS; +} + +u32 +RtkADCReceive( + IN VOID *Data +){ + PSAL_ADC_HND pSalADCHND = (PSAL_ADC_HND) Data; + PSAL_ADC_HND_PRIV pSalADCHNDPriv = NULL; + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PHAL_GDMA_ADAPTER pHALADCGdmaAdpt = NULL; + PHAL_GDMA_OP pHALADCGdmaOp = NULL; + + + + //PIRQ_HANDLE pIrqHandleADCGdma = NULL; + u32 AdcTempDat; + + /* To Get the SAL_I2C_MNGT_ADPT Pointer */ + pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv); + pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv); + + pHALADCGdmaAdpt = pSalADCMngtAdpt->pHalGdmaAdp; + pHALADCGdmaOp = pSalADCMngtAdpt->pHalGdmaOp; + + + + if (pSalADCHND->OpType == ADC_DMA_TYPE) { + /* Clear ADC Status */ + HAL_ADC_READ32(REG_ADC_INTR_STS); + + HalGdmaOpInit(pHALADCGdmaOp); + pHALADCGdmaAdpt->GdmaCtl.BlockSize = pSalADCHND->pRXBuf->DataLen; + pHALADCGdmaAdpt->ChSar = (u32)(ADC_REG_BASE); + pHALADCGdmaAdpt->ChDar = (u32)pSalADCHND->pRXBuf->pDataBuf; + pHALADCGdmaAdpt->MuliBlockCunt = 0; + + pHALADCGdmaOp->HalGdmaChSeting(pHALADCGdmaAdpt); + pHALADCGdmaOp->HalGdmaChEn(pHALADCGdmaAdpt); + + pSalADCHND->DevSts = ADC_STS_RX_ING; + AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER); + AdcTempDat |= BIT_ADC_PWR_AUTO; + HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat); + return _EXIT_SUCCESS; + } + return _EXIT_FAILURE; +} + +extern u32 +HalDelayUs( + IN u32 us +); + +u32 +RtkADCReceiveBuf( + IN VOID *Data, + IN u32 *pBuf +){ + PSAL_ADC_HND pSalADCHND = (PSAL_ADC_HND) Data; + PSAL_ADC_HND_PRIV pSalADCHNDPriv = NULL; + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + + + + PHAL_ADC_OP pHalADCOP = NULL; + + //PIRQ_HANDLE pIrqHandleADCGdma = NULL; + u32 AdcTempDat; + + /* To Get the SAL_I2C_MNGT_ADPT Pointer */ + pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv); + pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv); + + + + + pHalADCOP = pSalADCMngtAdpt->pHalOp; + + + + /* Clear ADC Status */ + //HAL_ADC_READ32(REG_ADC_INTR_STS); + AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_INTR_STS); + DBG_ADC_INFO("RtkADCReceiveBuf, INTR:%x\n", AdcTempDat); + //AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_INTR_STS); + //DBG_8195A(">>INTR:%x\n",AdcTempDat); + + ADCFullStsFlag = 0; + HalDelayUs(2000); + + DBG_ADC_INFO("RtkADCReceiveBuf, Check to enable ADC manully or not\n"); + AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_POWER); + if (unlikely((AdcTempDat & 0x00000008) == 0)) { + ; + } + else { + + pSalADCHND->pInitDat->ADCEn = ADC_ENABLE; + pHalADCOP->HalADCEnable(pSalADCHND->pInitDat); + //AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_POWER); + } + + + pSalADCHND->pInitDat->ADCIntrMSK = (BIT_ADC_FIFO_FULL_EN); + pHalADCOP->HalADCIntrCtrl(pSalADCHND->pInitDat); + pSalADCHND->DevSts = ADC_STS_IDLE; + AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0); + + if ((AdcTempDat & 0x00000001) == 0){ + + AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0); + DBG_ADC_INFO("RtkADCReceiveBuf, Before set, Reg AD0:%x\n", AdcTempDat); + AdcTempDat |= (0x01); + HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat); + AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0); + DBG_ADC_INFO("RtkADCReceiveBuf, After set, Reg AD0:%x\n", AdcTempDat); + + //AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_POWER); + + + } + else{ + ; + } + + while (ADCFullStsFlag == 0){ + } + + AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0); + DBG_ADC_INFO("RtkADCReceiveBuf, End of ADC, Before set, AD0:%x\n", AdcTempDat); + AdcTempDat &= (~0x01); + HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat); + AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0); + DBG_ADC_INFO("RtkADCReceiveBuf, End of ADC, After set, AD0:%x\n", AdcTempDat); + + + + /* Clear ADC Status */ + HAL_ADC_READ32(REG_ADC_INTR_STS); + ADCFullStsFlag = 0; + + *pBuf = (u32)ADCDatBuf[0]; + *(pBuf+1) = (u32)ADCDatBuf[1]; + ADCDatBuf[0] = 0; + ADCDatBuf[1] = 0; + + return _EXIT_SUCCESS; +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CGetSalHnd +// +// Description: +// Allocation of lower layer memory spaces will be done by invoking RtkI2CGetMngtAdpt +// in this function and return a SAL_I2C_HND pointer to upper layer. +// According to the given I2C index, RtkI2CGetMngtAdpt will allocate all the memory +// space such as SAL_I2C_HND, HAL_I2C_INIT_DAT, SAL_I2C_USER_CB etc. +// +// +// Arguments: +// [in] u8 I2CIdx - +// I2C Index +// +// Return: +// PSAL_I2C_HND +// A pointer to SAL_I2C_HND which is allocated in the lower layer. +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +PSAL_ADC_HND +RtkADCGetSalHnd( + IN u8 ADCIdx +){ + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PSAL_ADC_HND pSalADCHND = NULL; + + /* Check the user define setting and the given index */ + if (RtkADCIdxChk(ADCIdx)) { + return (PSAL_ADC_HND)NULL; + } + + /* Invoke RtkI2CGetMngtAdpt to get the I2C SAL management adapter pointer */ + pSalADCMngtAdpt = RtkADCGetMngtAdpt(ADCIdx); + + /* Assign the private SAL handle to public SAL handle */ + pSalADCHND = &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); + + /* Assign the internal HAL initial data pointer to the SAL handle */ + pSalADCHND->pInitDat = pSalADCMngtAdpt->pHalInitDat; + + /* Assign the internal user callback pointer to the SAL handle */ + pSalADCHND->pUserCB = pSalADCMngtAdpt->pUserCB; + + return &(pSalADCMngtAdpt->pSalHndPriv->SalADCHndPriv); + +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CGetSalHnd +// +// Description: +// Allocation of lower layer memory spaces will be done by invoking RtkI2CGetMngtAdpt +// in this function and return a SAL_I2C_HND pointer to upper layer. +// According to the given I2C index, RtkI2CGetMngtAdpt will allocate all the memory +// space such as SAL_I2C_HND, HAL_I2C_INIT_DAT, SAL_I2C_USER_CB etc. +// +// +// Arguments: +// [in] u8 I2CIdx - +// I2C Index +// +// Return: +// PSAL_I2C_HND +// A pointer to SAL_I2C_HND which is allocated in the lower layer. +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +RTK_STATUS +RtkADCFreeSalHnd( + IN PSAL_ADC_HND pSalADCHND +){ + PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL; + PSAL_ADC_HND_PRIV pSalADCHNDPriv = NULL; + + /* To get the SAL_DAC_MNGT_ADPT pointer */ + pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv); + pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv); + + /* Invoke RtkDACFreeMngtAdpt to free all the lower layer memory space */ + return (RtkADCFreeMngtAdpt(pSalADCMngtAdpt)); +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CLoadDefault +// +// Description: +// Accrording the given I2C index, the default I2C configuration is done. +// +// +// Arguments: +// [in] PSAL_I2C_HND pSalI2CHND - +// SAL I2C handle +// +// Return: +// The status of the loading I2C default configuration. +// _EXIT_SUCCESS if the RtkI2CLoadDefault succeeded. +// _EXIT_FAILURE if the RtkI2CLoadDefault failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +RTK_STATUS +RtkADCLoadDefault( + IN VOID *Data +){ + PSAL_ADC_HND pSalADCHND = (PSAL_ADC_HND) Data; + + /* Check the input ADC index first */ + if (RtkADCIdxChk(pSalADCHND->DevNum)) + return _EXIT_FAILURE; + + /* Load SAL handle default value */ + pSalADCHND->PinMux = 0; + pSalADCHND->OpType = ADC_RDREG_TYPE; + pSalADCHND->DevSts = ADC_STS_UNINITIAL; + pSalADCHND->ADCExd = 0; + pSalADCHND->ErrType = (u32)NULL; + + /* Load HAL initial data structure default value */ + pSalADCHND->pInitDat->ADCIdx = pSalADCHND->DevNum; + pSalADCHND->pInitDat->ADCEn = ADC_DISABLE; + pSalADCHND->pInitDat->ADCEndian = ADC_DATA_ENDIAN_LITTLE; + pSalADCHND->pInitDat->ADCBurstSz = 8; + pSalADCHND->pInitDat->ADCCompOnly = ADC_FEATURE_DISABLED; + pSalADCHND->pInitDat->ADCOneShotEn = ADC_FEATURE_DISABLED; + pSalADCHND->pInitDat->ADCOverWREn = ADC_FEATURE_DISABLED; + pSalADCHND->pInitDat->ADCOneShotTD = 8; + pSalADCHND->pInitDat->ADCCompCtrl = ADC_COMP_SMALLER_THAN; + pSalADCHND->pInitDat->ADCCompTD = 8; + pSalADCHND->pInitDat->ADCDataRate = 0; + pSalADCHND->pInitDat->ADCAudioEn = ADC_FEATURE_DISABLED; + pSalADCHND->pInitDat->ADCEnManul = ADC_FEATURE_DISABLED; + pSalADCHND->pInitDat->ADCDbgSel = ADC_DBG_SEL_DISABLE; + pSalADCHND->pInitDat->ADCPWCtrl = 0; + pSalADCHND->pInitDat->ADCIntrMSK = ADC_FEATURE_DISABLED; + pSalADCHND->pInitDat->ADCAnaParAd3 = 0; + return _EXIT_SUCCESS; +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkADCDisablePS +// +// Description: +// ADC disable opertion by setting clock disable. +// +// Arguments: +// [in] VOID *Data - +// ADC SAL handle +// +// Return: +// The status of the ADC disable process. +// HAL_OK if the RtkADCDisablePS succeeded. +// HAL_ERR_PARA if the RtkADCDisablePS failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2015-06-15. +// +//---------------------------------------------------------------------------------------------------- +HAL_Status +RtkADCDisablePS( + IN VOID *Data +){ + + PSAL_ADC_HND pSalADCHND = (PSAL_ADC_HND) Data; + u8 adcIdx = pSalADCHND->DevNum; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE adcPwrState; +#endif + + if (RtkADCIdxChk(adcIdx)) + return HAL_ERR_UNKNOWN; + + +#ifdef CONFIG_SOC_PS_MODULE + SalAdcEnableState &= (~(0x01 << pSalADCHND->DevNum)); + + if (SalAdcEnableState == 0) { + // To register a new peripheral device power state + adcPwrState.FuncIdx = ADC0; + adcPwrState.PwrState = SLPCG; + RegPowerState(adcPwrState); + } +#endif + + return HAL_OK; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkADCEnablePS +// +// Description: +// ADC enable opertion by setting clock enable. +// +// Arguments: +// [in] VOID *Data - +// ADC SAL handle +// +// Return: +// The status of the ADC enable process. +// HAL_OK if the RtkADCEnablePS succeeded. +// HAL_ERR_PARA if the RtkADCEnablePS failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2015-06-15. +// +//---------------------------------------------------------------------------------------------------- +HAL_Status +RtkADCEnablePS( + IN VOID *Data +){ + + PSAL_ADC_HND pSalADCHND = (PSAL_ADC_HND) Data; + u8 adcIdx = pSalADCHND->DevNum; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE adcPwrState; +#endif + + if (RtkADCIdxChk(adcIdx)) + return HAL_ERR_UNKNOWN; + +#ifdef CONFIG_SOC_PS_MODULE + SalAdcEnableState |= (0x01 << pSalADCHND->DevNum); + + // To register a new peripheral device power state + adcPwrState.FuncIdx = ADC0; + adcPwrState.PwrState = ACT; + RegPowerState(adcPwrState); +#endif + + return HAL_OK; +} + diff --git a/lib/fwlib/src/hal_common.c b/lib/fwlib/src/hal_common.c new file mode 100644 index 0000000..6594168 --- /dev/null +++ b/lib/fwlib/src/hal_common.c @@ -0,0 +1,23 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#include "rtl8195a.h" +#include "hal_common.h" + +extern HAL_TIMER_OP HalTimerOp; + +HAL_Status +HalCommonInit(void){ + +#ifdef CONFIG_TIMER_MODULE + HalTimerOpInit_Patch((VOID*)(&HalTimerOp)); +#endif + + return HAL_OK; +} diff --git a/lib/fwlib/src/hal_dac.c b/lib/fwlib/src/hal_dac.c new file mode 100644 index 0000000..516bebd --- /dev/null +++ b/lib/fwlib/src/hal_dac.c @@ -0,0 +1,1450 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#include "rtl8195a.h" +#include "rtl_utility.h" +#include "osdep_api.h" +#include "hal_dac.h" +#include "hal_gdma.h" + +#define DAC_STATIC_ALLOC 0 + +/* DAC SAL global variables declaration when kernel disabled */ + +#if DAC_STATIC_ALLOC + SRAM_BF_DATA_SECTION + HAL_DAC_OP HalDACOpSAL; +#endif + + +#if DAC0_USED /*#if DAC0_USED*/ +#if DAC_STATIC_ALLOC + SRAM_BF_DATA_SECTION + SAL_DAC_MNGT_ADPT SalDAC0MngtAdpt; + + SRAM_BF_DATA_SECTION + SAL_DAC_HND_PRIV SalDAC0HndPriv; + + SRAM_BF_DATA_SECTION + HAL_DAC_INIT_DAT HalDAC0InitData; + + SRAM_BF_DATA_SECTION + IRQ_HANDLE DAC0IrqHandleDat; + + SRAM_BF_DATA_SECTION + HAL_GDMA_ADAPTER HalDAC0GdmaAdpt; + + SRAM_BF_DATA_SECTION + HAL_GDMA_OP HalDAC0GdmaOp; + + SRAM_BF_DATA_SECTION + IRQ_HANDLE DAC0GDMAIrqHandleDat; + + SRAM_BF_DATA_SECTION + SAL_DAC_USER_CB SalDAC0UserCB; + + SRAM_BF_DATA_SECTION + SAL_DAC_DMA_USER_DEF SalDAC0DmaUserDef; + + SRAM_BF_DATA_SECTION + SAL_DAC_USERCB_ADPT SalDAC0UserCBAdpt[SAL_DAC_USER_CB_NUM]; +#endif +#endif /*#if DAC0_USED*/ + +#if DAC1_USED /*#if DAC1_USED*/ +#if DAC_STATIC_ALLOC + + SRAM_BF_DATA_SECTION + SAL_DAC_MNGT_ADPT SalDAC1MngtAdpt; + + SRAM_BF_DATA_SECTION + SAL_DAC_HND_PRIV SalDAC1HndPriv; + + SRAM_BF_DATA_SECTION + HAL_DAC_INIT_DAT HalDAC1InitData; + + SRAM_BF_DATA_SECTION + IRQ_HANDLE DAC1IrqHandleDat; + + SRAM_BF_DATA_SECTION + HAL_GDMA_ADAPTER HalDAC1GdmaAdpt; + + SRAM_BF_DATA_SECTION + HAL_GDMA_OP HalDAC1GdmaOp; + + SRAM_BF_DATA_SECTION + IRQ_HANDLE DAC1GDMAIrqHandleDat; + + SRAM_BF_DATA_SECTION + SAL_DAC_USER_CB SalDAC1UserCB; + + SRAM_BF_DATA_SECTION + SAL_DAC_DMA_USER_DEF SalDAC1DmaUserDef; + + SRAM_BF_DATA_SECTION + SAL_DAC_USERCB_ADPT SalDAC1UserCBAdpt[SAL_DAC_USER_CB_NUM]; +#endif +#endif /*#if DAC1_USED*/ + +/* Function prototype */ +VOID DACISRHandle(IN VOID *Data); +VOID DACGDMAISRHandle(IN VOID * Data); +VOID DACGDMALLPISRHandle(IN VOID *Data); + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CGetMngtAdpt +// +// Description: +// According to the input index, all the memory space are allocated and all the +// related pointers are assigned. The management adapter pointer will be +// returned. +// +// Arguments: +// [in] u8 I2CIdx - +// I2C module index +// +// Return: +// PSAL_I2C_MNGT_ADPT +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//--------------------------------------------------------------------------------------------------- +VOID HalDACOpInit( + IN VOID *Data +) +{ + PHAL_DAC_OP pHalDacOp = (PHAL_DAC_OP) Data; + + pHalDacOp->HalDACInit = HalDACInit8195a; + pHalDacOp->HalDACDeInit = HalDACDeInit8195a; + pHalDacOp->HalDACEnable = HalDACEnableRtl8195a; + pHalDacOp->HalDACSend = HalDACSendRtl8195a; + pHalDacOp->HalDACIntrCtrl = HalDACIntrCtrl8195a; + pHalDacOp->HalDACReadReg = HalDACReadRegRtl8195a; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CGetMngtAdpt +// +// Description: +// According to the input index, all the memory space are allocated and all the +// related pointers are assigned. The management adapter pointer will be +// returned. +// +// Arguments: +// [in] u8 I2CIdx - +// I2C module index +// +// Return: +// PSAL_I2C_MNGT_ADPT +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//--------------------------------------------------------------------------------------------------- +PSAL_DAC_MNGT_ADPT +RtkDACGetMngtAdpt( + IN u8 DACIdx +){ + PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt = NULL; + PSAL_DAC_USERCB_ADPT pSalDACUserCBAdpt = NULL; + + /* If the kernel is available, Memory-allocation is used. */ +#if !DAC_STATIC_ALLOC + + pSalDACMngtAdpt = (PSAL_DAC_MNGT_ADPT)RtlZmalloc(sizeof(SAL_DAC_MNGT_ADPT)); + pSalDACMngtAdpt->pSalHndPriv = (PSAL_DAC_HND_PRIV)RtlZmalloc(sizeof(SAL_DAC_HND_PRIV)); + pSalDACMngtAdpt->pHalInitDat = (PHAL_DAC_INIT_DAT)RtlZmalloc(sizeof(HAL_DAC_INIT_DAT)); + pSalDACMngtAdpt->pHalOp = (PHAL_DAC_OP)RtlZmalloc(sizeof(HAL_DAC_OP)); + pSalDACMngtAdpt->pIrqHnd = (PIRQ_HANDLE)RtlZmalloc(sizeof(IRQ_HANDLE)); + pSalDACMngtAdpt->pUserCB = (PSAL_DAC_USER_CB)RtlZmalloc(sizeof(SAL_DAC_USER_CB)); + pSalDACMngtAdpt->pDMAConf = (PSAL_DAC_DMA_USER_DEF)RtlZmalloc(sizeof(SAL_DAC_DMA_USER_DEF)); + pSalDACMngtAdpt->pHalGdmaAdp = (PHAL_GDMA_ADAPTER)RtlZmalloc(sizeof(HAL_GDMA_ADAPTER)); + pSalDACMngtAdpt->pHalGdmaOp = (PHAL_GDMA_OP)RtlZmalloc(sizeof(HAL_GDMA_OP)); + pSalDACMngtAdpt->pIrqGdmaHnd = (PIRQ_HANDLE)RtlZmalloc(sizeof(IRQ_HANDLE)); + pSalDACUserCBAdpt = (PSAL_DAC_USERCB_ADPT)RtlZmalloc((sizeof(SAL_DAC_USERCB_ADPT)*SAL_DAC_USER_CB_NUM)); +#else + switch (DACIdx){ + case DAC0_SEL: + { + pSalDACMngtAdpt = &SalDAC0MngtAdpt; + pSalDACMngtAdpt->pSalHndPriv = &SalDAC0HndPriv; + pSalDACMngtAdpt->pHalInitDat = &HalDAC0InitData; + pSalDACMngtAdpt->pHalOp = &HalDACOpSAL; + pSalDACMngtAdpt->pIrqHnd = &DAC0IrqHandleDat; + pSalDACMngtAdpt->pUserCB = &SalDAC0UserCB; + pSalDACMngtAdpt->pDMAConf = &SalDAC0DmaUserDef; + pSalDACMngtAdpt->pHalGdmaAdp = &HalDAC0GdmaAdpt; + pSalDACMngtAdpt->pHalGdmaOp = &HalDAC0GdmaOp; + pSalDACMngtAdpt->pIrqGdmaHnd = &DAC0IrqHandleDat; + pSalDACUserCBAdpt = &SalDAC0UserCBAdpt; + break; + } + + case DAC1_SEL: + { + pSalDACMngtAdpt = &SalDAC1MngtAdpt; + pSalDACMngtAdpt->pSalHndPriv = &SalDAC1HndPriv; + pSalDACMngtAdpt->pHalInitDat = &HalDAC1InitData; + pSalDACMngtAdpt->pHalOp = &HalDACOpSAL; + pSalDACMngtAdpt->pIrqHnd = &DAC1IrqHandleDat; + pSalDACMngtAdpt->pUserCB = &SalDAC1UserCB; + pSalDACMngtAdpt->pDMAConf = &SalDAC1DmaUserDef; + pSalDACMngtAdpt->pHalGdmaAdp = &HalDAC1GdmaAdpt; + pSalDACMngtAdpt->pHalGdmaOp = &HalDAC1GdmaOp; + pSalDACMngtAdpt->pIrqGdmaHnd = &DAC1IrqHandleDat; + pSalDACUserCBAdpt = &SalDAC1UserCBAdpt; + break; + } + + default: + break; + } +#endif + + /*To assign user callback pointers*/ + pSalDACMngtAdpt->pUserCB->pTXCB = pSalDACUserCBAdpt; + pSalDACMngtAdpt->pUserCB->pTXCCB = (pSalDACUserCBAdpt+1); + pSalDACMngtAdpt->pUserCB->pRXCB = (pSalDACUserCBAdpt+2); + pSalDACMngtAdpt->pUserCB->pRXCCB = (pSalDACUserCBAdpt+3); + pSalDACMngtAdpt->pUserCB->pRDREQCB = (pSalDACUserCBAdpt+4); + pSalDACMngtAdpt->pUserCB->pERRCB = (pSalDACUserCBAdpt+5); + pSalDACMngtAdpt->pUserCB->pDMATXCB = (pSalDACUserCBAdpt+6); + pSalDACMngtAdpt->pUserCB->pDMATXCCB = (pSalDACUserCBAdpt+7); + pSalDACMngtAdpt->pUserCB->pDMARXCB = (pSalDACUserCBAdpt+8); + pSalDACMngtAdpt->pUserCB->pDMARXCCB = (pSalDACUserCBAdpt+9); + + /*To assign the rest pointers*/ + pSalDACMngtAdpt->pSalHndPriv->ppSalDACHnd = (void**)&(pSalDACMngtAdpt->pSalHndPriv); + + /* To assign the default HAL OP initialization function */ + pSalDACMngtAdpt->pHalOpInit = &HalDACOpInit; + + /* To assign the default HAL GDMA OP initialization function */ + pSalDACMngtAdpt->pHalGdmaOpInit = &HalGdmaOpInit; + + /* To assign the default SAL interrupt function */ + pSalDACMngtAdpt->pSalIrqFunc = &DACISRHandle; + + /* To assign the default SAL DMA interrupt function */ + pSalDACMngtAdpt->pSalDMAIrqFunc = &DACGDMAISRHandle; + + return pSalDACMngtAdpt; +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CFreeMngtAdpt +// +// Description: +// Free all the previous allocated memory space. +// +// Arguments: +// [in] PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt - +// I2C SAL management adapter pointer +// +// +// Return: +// The status of the enable process. +// _EXIT_SUCCESS if the RtkI2CFreeMngtAdpt succeeded. +// _EXIT_FAILURE if the RtkI2CFreeMngtAdpt failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//--------------------------------------------------------------------------------------------------- +RTK_STATUS +RtkDACFreeMngtAdpt( + IN PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt +){ +#if !DAC_STATIC_ALLOC + RtlMfree((u8 *)pSalDACMngtAdpt->pUserCB->pTXCB, (sizeof(SAL_DAC_USERCB_ADPT)*SAL_DAC_USER_CB_NUM)); + RtlMfree((u8 *)pSalDACMngtAdpt->pIrqGdmaHnd, sizeof(IRQ_HANDLE)); + RtlMfree((u8 *)pSalDACMngtAdpt->pHalGdmaOp, sizeof(HAL_GDMA_OP)); + RtlMfree((u8 *)pSalDACMngtAdpt->pHalGdmaAdp, sizeof(HAL_GDMA_ADAPTER)); + RtlMfree((u8 *)pSalDACMngtAdpt->pDMAConf, sizeof(SAL_DAC_DMA_USER_DEF)); + RtlMfree((u8 *)pSalDACMngtAdpt->pUserCB, sizeof(SAL_DAC_USER_CB)); + RtlMfree((u8 *)pSalDACMngtAdpt->pIrqHnd, sizeof(IRQ_HANDLE)); + RtlMfree((u8 *)pSalDACMngtAdpt->pHalOp, sizeof(HAL_DAC_OP)); + RtlMfree((u8 *)pSalDACMngtAdpt->pHalInitDat, sizeof(HAL_DAC_INIT_DAT)); + RtlMfree((u8 *)pSalDACMngtAdpt->pSalHndPriv, sizeof(SAL_DAC_HND_PRIV)); + RtlMfree((u8 *)pSalDACMngtAdpt, sizeof(SAL_DAC_MNGT_ADPT)); +#else + ; +#endif + + return _EXIT_SUCCESS; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// I2CISRHandle +// +// Description: +// I2C Interrupt Service Routine. +// According to the input pointer to SAL_I2C_HND, all the rest pointers will be +// found and be used to the rest part of this servie routine. +// The following types of interrupt will be taken care: +// - General Call (providing General Call Callback). Slave receives a general call. +// - STOP Bit (NOT providing General Call Callback) +// - START Bit (NOTproviding General Call Callback) +// - I2C Activity (NOTproviding General Call Callback) +// - RX Done (providing Error Callback). The slave transmitter does NOT +// receive a proper NACK for the end of whole transfer. +// - TX Abort (providing Error Call Callback). The Master/Slave +// transmitting is terminated. +// - RD Req (providing TX and TXC Callback). Slave gets a Read Request +// and starts a slave-transmitter operation. The slave transmit +// data will be written into slave TX FIFO from user data buffer. +// - TX Empty (providing TX and TXC Callback). Master TX FIFO is empty. +// The user transmit data will be written into master TX FIFO +// from user data buffer. +// - TX Over (providing Error Callback). Master TX FIFO is Overflow. +// - RX Full (providing RX and RXC Callback). Master/Slave RX FIFO contains +// data. And the received data will be put into Master/Slave user +// receive data buffer. +// - RX Over (providing Error Callback). Master/Slave RX FIFO is Overflow. +// - RX Under (providing Error Callback). Master/Slave RX FIFO is Underflow. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// NA +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//---------------------------------------------------------------------------------------------------- +VOID +DACISRHandle( + IN VOID *Data +){ +#ifdef CONFIG_DEBUG_LOG_DAC_HAL + PSAL_DAC_HND pSalDACHND = (PSAL_DAC_HND) Data; + PSAL_DAC_HND_PRIV pSalDACHNDPriv = NULL; + PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt = NULL; + PHAL_DAC_INIT_DAT pHalDACInitDat = NULL; + PHAL_DAC_OP pHalDACOP = NULL; + PSAL_DAC_USER_CB pSalDACUserCB = NULL; + u8 DACIrqIdx; + + /* To get the SAL_I2C_MNGT_ADPT pointer, and parse the rest pointers */ + pSalDACHNDPriv = CONTAINER_OF(pSalDACHND, SAL_DAC_HND_PRIV, SalDACHndPriv); + pSalDACMngtAdpt = CONTAINER_OF(pSalDACHNDPriv->ppSalDACHnd, SAL_DAC_MNGT_ADPT, pSalHndPriv); + pHalDACInitDat = pSalDACMngtAdpt->pHalInitDat; + pHalDACOP = pSalDACMngtAdpt->pHalOp; + DACIrqIdx = pHalDACInitDat->DACIdx; + pSalDACUserCB = pSalDACHND->pUserCB; + + DBG_DAC_INFO("DAC INTR STS:%x\n",pHalDACOP->HalDACReadReg(pHalDACInitDat, REG_DAC_INTR_STS)); + if ((pHalDACOP->HalDACReadReg(pHalDACInitDat, REG_DAC_INTR_STS)) & BIT_DAC_FIFO_STOP_ST){ + pHalDACInitDat->DACEn = DAC_DISABLE; + pHalDACOP->HalDACEnable((void *)pHalDACInitDat); + } +#else + /* To reduce warning */ + PSAL_DAC_HND pSalDACHND = (PSAL_DAC_HND) Data; + PSAL_DAC_HND_PRIV pSalDACHNDPriv = NULL; + PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt = NULL; + PHAL_DAC_INIT_DAT pHalDACInitDat = NULL; + PHAL_DAC_OP pHalDACOP = NULL; + + + + /* To get the SAL_I2C_MNGT_ADPT pointer, and parse the rest pointers */ + pSalDACHNDPriv = CONTAINER_OF(pSalDACHND, SAL_DAC_HND_PRIV, SalDACHndPriv); + pSalDACMngtAdpt = CONTAINER_OF(pSalDACHNDPriv->ppSalDACHnd, SAL_DAC_MNGT_ADPT, pSalHndPriv); + pHalDACInitDat = pSalDACMngtAdpt->pHalInitDat; + pHalDACOP = pSalDACMngtAdpt->pHalOp; + + + pHalDACOP->HalDACReadReg(pHalDACInitDat, REG_DAC_INTR_STS); +#endif +} + +VOID +DACGDMAISRHandle( + IN VOID *Data +){ + + PSAL_DAC_HND pSalDACHND = (PSAL_DAC_HND) Data; + PSAL_DAC_HND_PRIV pSalDACHNDPriv = NULL; + PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt = NULL; + + PHAL_GDMA_ADAPTER pHalDACGdmaAdapter = NULL; + PHAL_GDMA_OP pHalDACGdmaOp = NULL; + PSAL_DAC_USER_CB pSalDACUserCB = NULL; + + u8 IsrTypeMap = 0; + DBG_8195A_DAC_LVL(HAL_DAC_LVL,"%s\n",__func__); + + + pSalDACHNDPriv = CONTAINER_OF(pSalDACHND, SAL_DAC_HND_PRIV, SalDACHndPriv); + pSalDACMngtAdpt = CONTAINER_OF(pSalDACHNDPriv->ppSalDACHnd, SAL_DAC_MNGT_ADPT, pSalHndPriv); + + pHalDACGdmaAdapter = pSalDACMngtAdpt->pHalGdmaAdp; + pHalDACGdmaOp = pSalDACMngtAdpt->pHalGdmaOp; + pSalDACUserCB = pSalDACMngtAdpt->pUserCB; + + pSalDACMngtAdpt->pHalGdmaOpInit(pHalDACGdmaOp); + + if ((pHalDACGdmaAdapter->MaxMuliBlock) == pHalDACGdmaAdapter->MuliBlockCunt+1) { + pHalDACGdmaOp->HalGdmaChCleanAutoSrc(pHalDACGdmaAdapter); + pHalDACGdmaOp->HalGdmaChDis(pHalDACGdmaAdapter); + pSalDACHND->DevSts = DAC_STS_IDLE; + if (pSalDACUserCB->pDMATXCCB->USERCB != NULL) + { + pSalDACUserCB->pDMATXCCB->USERCB((void*)pSalDACUserCB->pDMATXCCB->USERData); + } + } + else { + //pHalDACGdmaOp->HalGdmaChCleanAutoSrc(pHalDACGdmaAdapter); + pSalDACHND->DevSts = DAC_STS_TX_ING; + + if (pSalDACUserCB->pDMATXCB->USERCB != NULL){ + pSalDACUserCB->pDMATXCB->USERCB((void*)pSalDACUserCB->pDMATXCB->USERData);} + } + + //3 Clear Pending ISR + IsrTypeMap = pHalDACGdmaOp->HalGdmaChIsrClean((VOID*)pHalDACGdmaAdapter); + + //3 Maintain Block Count + if (IsrTypeMap & BlockType) { + pHalDACGdmaAdapter->MuliBlockCunt++; + } + +} + +VOID +DACGDMALLPISRHandle( + IN VOID *Data +){ + PSAL_DAC_HND pSalDACHND = (PSAL_DAC_HND) Data; + PSAL_DAC_HND_PRIV pSalDACHNDPriv = NULL; + PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt = NULL; + + PHAL_GDMA_ADAPTER pHalDACGdmaAdapter = NULL; + PHAL_GDMA_OP pHalDACGdmaOp = NULL; + + u8 IsrTypeMap; + + pSalDACHNDPriv = CONTAINER_OF(pSalDACHND, SAL_DAC_HND_PRIV, SalDACHndPriv); + pSalDACMngtAdpt = CONTAINER_OF(pSalDACHNDPriv->ppSalDACHnd, SAL_DAC_MNGT_ADPT, pSalHndPriv); + + pHalDACGdmaAdapter = pSalDACMngtAdpt->pHalGdmaAdp; + pHalDACGdmaOp = pSalDACMngtAdpt->pHalGdmaOp; + + + pSalDACMngtAdpt->pHalGdmaOpInit(pHalDACGdmaOp); +#if 0 + PGDMA_ADAPTER pGdmaAdapte = (PGDMA_ADAPTER) Data; + PHAL_GDMA_ADAPTER pHalGdmaAdapter = pGdmaAdapte->pHalGdmaAdapter; + PGDMA_CH_LLI_ELE pGdmaChLliEle; + struct GDMA_CH_LLI *pGdmaChLli = pHalGdmaAdapter->pLlix; + struct BLOCK_SIZE_LIST *pBlockSizeList = pHalGdmaAdapter->pBlockSizeList; + u32 TotalBlockSize = 0; + u8 IsrTypeMap, BlockIndex; + u8 *pSrc = NULL, *pDst = NULL; + DBG_8195A_DMA("Enter Gdma0 Channel 5 ISr =====>\n"); +#endif + + + + if ((pHalDACGdmaAdapter->MaxMuliBlock) == pHalDACGdmaAdapter->MuliBlockCunt) { + //HalGdmaOp.HalGdmaChCleanAutoSrc(pHalGdmaAdapter); + //DAC0_FCTRL(OFF); + + //HalGdmaOp.HalGdmaChCleanAutoDst(pHalGdmaAdapter); + pHalDACGdmaOp->HalGdmaChDis(pHalDACGdmaAdapter); + + DBG_8195A("dma done\n"); + } + + + IsrTypeMap = pHalDACGdmaOp->HalGdmaChIsrClean((VOID*)pHalDACGdmaAdapter); + + if (IsrTypeMap & BlockType) { + pHalDACGdmaAdapter->MuliBlockCunt++; + } +} + +static RTK_STATUS +RtkDACPinMuxInit( + IN PSAL_DAC_HND pSalDACHND +){ + u32 DACLocalTemp; + + /* Check the I2C index first */ + if (RtkDACIdxChk(pSalDACHND->DevNum)) + return _EXIT_FAILURE; + + DACLocalTemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL2); + DACLocalTemp |= BIT26; + + /* To release DAC delta sigma clock gating */ + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SYS_SYSPLL_CTRL2,DACLocalTemp); + + switch (pSalDACHND->DevNum){ +#if DAC0_USED + case DAC0_SEL: + { + /* Turn on DAC active clock */ + ACTCK_DAC_CCTRL(ON); + + /* Enable DAC0 module */ + DAC0_FCTRL(ON); + break; + } +#endif +#if DAC1_USED + case DAC1_SEL: + { + /* Turn on DAC active clock */ + ACTCK_DAC_CCTRL(ON); + + /* Enable DAC1 module */ + DAC1_FCTRL(ON); + break; + } +#endif + default: + return _EXIT_FAILURE; + } + + return _EXIT_SUCCESS; +} + +static RTK_STATUS +RtkDACPinMuxDeInit( + IN PSAL_DAC_HND pSalDACHND +){ + + u32 DACLocalTemp; + + /* Check the I2C index first */ + if (RtkDACIdxChk(pSalDACHND->DevNum)) + return _EXIT_FAILURE; + + switch (pSalDACHND->DevNum){ +#if DAC0_USED + case DAC0_SEL: + { + /* Turn on DAC active clock */ + ACTCK_DAC_CCTRL(OFF); + + /* Enable DAC0 module */ + DAC0_FCTRL(OFF); + break; + } +#endif +#if DAC1_USED + case DAC1_SEL: + { + /* Turn on DAC active clock */ + ACTCK_DAC_CCTRL(OFF); + + /* Enable DAC1 module */ + DAC1_FCTRL(OFF); + break; + } +#endif + default: + return _EXIT_FAILURE; + } + + + DACLocalTemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL2); + DACLocalTemp &= (~BIT26); + + /* To release DAC delta sigma clock gating */ + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SYS_SYSPLL_CTRL2,DACLocalTemp); + + return _EXIT_SUCCESS; +} + + +#if DAC_INTR_OP_TYPE +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CIrqInit +// +// Description: +// I2C interrupt initialization function. +// For I2C interrupt operation mode, I2C module MUST register itself to the platform +// by providing the interrupt handler which contains interrupt input data (arguments), +// interrupt service routine, interrupt number, interrupt priority. And then the interrupt +// should be enabled. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C interrupt initialization process. +// _EXIT_SUCCESS if the RtkI2CIrqInit succeeded. +// _EXIT_FAILURE if the RtkI2CIrqInit failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +static RTK_STATUS +RtkDACIrqInit( + IN PSAL_DAC_HND pSalDACHND +){ + PSAL_DAC_HND_PRIV pSalDACHNDPriv = NULL; + PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt = NULL; + PIRQ_HANDLE pIrqHandle = NULL; + + /* To Get the SAL_I2C_MNGT_ADPT Pointer */ + pSalDACHNDPriv = CONTAINER_OF(pSalDACHND, SAL_DAC_HND_PRIV, SalDACHndPriv); + pSalDACMngtAdpt = CONTAINER_OF(pSalDACHNDPriv->ppSalDACHnd, SAL_DAC_MNGT_ADPT, pSalHndPriv); + pIrqHandle = pSalDACMngtAdpt->pIrqHnd; + + if (RtkDACIdxChk(pSalDACHND->DevNum)) + return _EXIT_FAILURE; + + switch (pSalDACHND->DevNum){ +#if DAC0_USED + case DAC0_SEL: + { + pIrqHandle->Data = (u32) (pSalDACHND); + pIrqHandle->IrqNum = DAC0_IRQ; + pIrqHandle->IrqFun = (IRQ_FUN) pSalDACMngtAdpt->pSalIrqFunc; + pIrqHandle->Priority = 5; + InterruptRegister(pIrqHandle); + InterruptEn(pIrqHandle); + break; + } +#endif +#if DAC1_USED + case DAC1_SEL: + { + pIrqHandle->Data = (u32) (pSalDACHND); + pIrqHandle->IrqNum = DAC1_IRQ; + pIrqHandle->IrqFun = (IRQ_FUN) pSalDACMngtAdpt->pSalIrqFunc;; + pIrqHandle->Priority = 5; + InterruptRegister(pIrqHandle); + InterruptEn(pIrqHandle); + break; + } +#endif + default: + return _EXIT_FAILURE; + } + + + + return _EXIT_SUCCESS; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CIrqDeInit +// +// Description: +// I2C interrupt de-initialization function. +// According to the given I2C device number, the I2C interrupt will be unreigster +// from the platform and the relative interrupt handler will be cleared. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C interrupt de-initialization process. +// _EXIT_SUCCESS if the RtkI2CIrqDeInit succeeded. +// _EXIT_FAILURE if the RtkI2CIrqDeInit failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +static RTK_STATUS +RtkDACIrqDeInit( + IN PSAL_DAC_HND pSalDACHND +){ + PSAL_DAC_HND_PRIV pSalDACHNDPriv = NULL; + PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt = NULL; + PIRQ_HANDLE pIrqHandle = NULL; + + /*To Get the SAL_I2C_MNGT_ADPT Pointer*/ + pSalDACHNDPriv = CONTAINER_OF(pSalDACHND, SAL_DAC_HND_PRIV, SalDACHndPriv); + pSalDACMngtAdpt = CONTAINER_OF(pSalDACHNDPriv->ppSalDACHnd, SAL_DAC_MNGT_ADPT, pSalHndPriv); + pIrqHandle = pSalDACMngtAdpt->pIrqHnd; + + if (RtkDACIdxChk(pSalDACHND->DevNum)) + return _EXIT_FAILURE; + + InterruptUnRegister(pIrqHandle); + return _EXIT_SUCCESS; +} + +#endif + + +#if DAC_DMA_OP_TYPE +const u16 DACDmaChNo[10] = {GdmaNoCh ,GdmaCh0, + GdmaCh1 ,GdmaCh2, + GdmaCh3 ,GdmaCh4, + GdmaCh5 ,GdmaCh6, + GdmaCh7 ,GdmaAllCh}; + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CIrqInit +// +// Description: +// I2C interrupt initialization function. +// For I2C interrupt operation mode, I2C module MUST register itself to the platform +// by providing the interrupt handler which contains interrupt input data (arguments), +// interrupt service routine, interrupt number, interrupt priority. And then the interrupt +// should be enabled. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C interrupt initialization process. +// _EXIT_SUCCESS if the RtkI2CIrqInit succeeded. +// _EXIT_FAILURE if the RtkI2CIrqInit failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +static RTK_STATUS +RtkDACDMAInit( + IN PSAL_DAC_HND pSalDACHND +){ + PSAL_DAC_HND_PRIV pSalDACHNDPriv = NULL; + PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt = NULL; + PHAL_GDMA_ADAPTER pHALDACGdmaAdpt = NULL; + PHAL_GDMA_OP pHALDACGdmaOp = NULL; + PIRQ_HANDLE pIrqHandleDACGdma = NULL; + PSAL_DAC_DMA_USER_DEF pSalDACDmaUserDef = NULL; + + + + /* To Get the SAL_I2C_MNGT_ADPT Pointer */ + pSalDACHNDPriv = CONTAINER_OF(pSalDACHND, SAL_DAC_HND_PRIV, SalDACHndPriv); + pSalDACMngtAdpt = CONTAINER_OF(pSalDACHNDPriv->ppSalDACHnd, SAL_DAC_MNGT_ADPT, pSalHndPriv); + + pHALDACGdmaAdpt = pSalDACMngtAdpt->pHalGdmaAdp; + pHALDACGdmaOp = pSalDACMngtAdpt->pHalGdmaOp; + pIrqHandleDACGdma = pSalDACMngtAdpt->pIrqGdmaHnd; + pSalDACDmaUserDef = pSalDACHND->pDMAConf; + + if (RtkDACIdxChk(pSalDACHND->DevNum)) + return _EXIT_FAILURE; + + if (pSalDACHND->DACInType == DAC_INPUT_SINGLE_WR) + return _EXIT_SUCCESS; + + /* GDMA operation initialization */ + //HalGdmaOpInit(pHalI2CGdmaOp); + _memset((void *)pHALDACGdmaAdpt, 0, sizeof(HAL_GDMA_ADAPTER)); + pSalDACMngtAdpt->pHalGdmaOpInit(pHALDACGdmaOp); + pHALDACGdmaOp->HalGdamChInit((VOID*)(pHALDACGdmaAdpt)); + + + + pHALDACGdmaAdpt->GdmaIndex = pSalDACHND->DevNum; + pHALDACGdmaAdpt->GdmaCtl.IntEn = 1; + pHALDACGdmaAdpt->ChNum = pSalDACDmaUserDef->TxChNo; + + pHALDACGdmaAdpt->ChEn = DACDmaChNo[pHALDACGdmaAdpt->ChNum+1]; + pHALDACGdmaAdpt->IsrCtrl = ENABLE; + pHALDACGdmaAdpt->GdmaOnOff = ON; + + + /* GDMA initialization */ + /* Enable the whole GDMA module first */ + if (pHALDACGdmaAdpt->GdmaIndex == 0) { + ACTCK_GDMA0_CCTRL(ON); + SLPCK_GDMA0_CCTRL(ON); + GDMA0_FCTRL(ON); + } + else { + ACTCK_GDMA1_CCTRL(ON); + SLPCK_GDMA1_CCTRL(ON); + GDMA1_FCTRL(ON); + } + + if (pSalDACHND->DACInType == DAC_INPUT_DMA_ONEBLK) { + //DAC TX DMA + pHALDACGdmaAdpt->GdmaCtl.SrcTrWidth = pSalDACDmaUserDef->TxDatSrcWdth; + pHALDACGdmaAdpt->GdmaCtl.DstTrWidth = pSalDACDmaUserDef->TxDatDstWdth; + pHALDACGdmaAdpt->GdmaCtl.SrcMsize = pSalDACDmaUserDef->TxDatSrcBstSz; + pHALDACGdmaAdpt->GdmaCtl.DestMsize = pSalDACDmaUserDef->TxDatDstBstSz; + + pHALDACGdmaAdpt->GdmaCtl.Sinc = IncType; + pHALDACGdmaAdpt->GdmaCtl.Dinc = NoChange; + + pHALDACGdmaAdpt->GdmaCtl.Done = 1; + pHALDACGdmaAdpt->GdmaCtl.TtFc = 0x01; + + pHALDACGdmaAdpt->GdmaCfg.DestPer = 13; + pHALDACGdmaAdpt->GdmaCfg.ReloadSrc = 1; + + pHALDACGdmaAdpt->MuliBlockCunt = 1; + pHALDACGdmaAdpt->MaxMuliBlock = pSalDACHND->pDMAConf->MaxMultiBlk; + + pHALDACGdmaAdpt->GdmaIsrType = (BlockType|TransferType|ErrType); + + + pHALDACGdmaAdpt->TestItem = 3; + + + //pSalDACMngtAdpt->pSalDMAIrqFunc = &DACGDMAISRHandle; + } + else if (pSalDACHND->DACInType == DAC_INPUT_DMA_LLP) { + //DAC TX DMA + pHALDACGdmaAdpt->GdmaCtl.SrcTrWidth = pSalDACDmaUserDef->TxDatSrcWdth; + pHALDACGdmaAdpt->GdmaCtl.DstTrWidth = pSalDACDmaUserDef->TxDatDstWdth; + pHALDACGdmaAdpt->GdmaCtl.SrcMsize = pSalDACDmaUserDef->TxDatSrcBstSz; + pHALDACGdmaAdpt->GdmaCtl.DestMsize = pSalDACDmaUserDef->TxDatDstBstSz; + + pHALDACGdmaAdpt->GdmaCtl.Dinc = NoChange; + + pHALDACGdmaAdpt->GdmaCtl.Done = 1; + pHALDACGdmaAdpt->GdmaCtl.TtFc = 0x01; + pHALDACGdmaAdpt->GdmaCtl.LlpSrcEn = 1; + + pHALDACGdmaAdpt->GdmaCfg.DestPer = 13; + + pHALDACGdmaAdpt->GdmaIsrType = (BlockType|ErrType); + + /* Enable LLP control */ + pHALDACGdmaAdpt->Llpctrl = pSalDACDmaUserDef->LlpCtrl; + + pHALDACGdmaAdpt->MuliBlockCunt = 1; + pHALDACGdmaAdpt->MaxMuliBlock = pSalDACDmaUserDef->MaxMultiBlk; + + pHALDACGdmaAdpt->TestItem = 9; + + //pSalDACMngtAdpt->pSalDMAIrqFunc = &DACGDMALLPISRHandle; + } + + + /* GDMA interrupt register */ + pIrqHandleDACGdma->Data = (u32) (pSalDACHND); + pIrqHandleDACGdma->IrqNum = GDMA0_CHANNEL0_IRQ + pHALDACGdmaAdpt->ChNum + + ((pHALDACGdmaAdpt->GdmaIndex)*6); + pIrqHandleDACGdma->IrqFun = (IRQ_FUN) pSalDACMngtAdpt->pSalDMAIrqFunc; + pIrqHandleDACGdma->Priority = 2; + InterruptRegister(pIrqHandleDACGdma); + InterruptEn(pIrqHandleDACGdma); + + + pHALDACGdmaOp->HalGdmaOnOff((VOID*)pHALDACGdmaAdpt); + pHALDACGdmaOp->HalGdmaChIsrEnAndDis((VOID*)pHALDACGdmaAdpt); + +#if 0 + /* Enable GDMA according to the DMA type */ + if (pSalDACHND->DACInType == DAC_INPUT_DMA_ONEBLK) { + pHALDACGdmaOp->HalGdmaChSeting((VOID*)pHALDACGdmaAdpt); + } + else if (pSalDACHND->DACInType == DAC_INPUT_DMA_LLP){ + //pHALDACGdmaOp->HalGdmaChBlockSeting((VOID*)(pHALDACGdmaAdpt)); + } +#endif + return _EXIT_SUCCESS; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CIrqDeInit +// +// Description: +// I2C interrupt de-initialization function. +// According to the given I2C device number, the I2C interrupt will be unreigster +// from the platform and the relative interrupt handler will be cleared. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C interrupt de-initialization process. +// _EXIT_SUCCESS if the RtkI2CIrqDeInit succeeded. +// _EXIT_FAILURE if the RtkI2CIrqDeInit failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +static RTK_STATUS +RtkDACDMADeInit( + IN PSAL_DAC_HND pSalDACHND +){ + PSAL_DAC_HND_PRIV pSalDACHNDPriv = NULL; + PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt = NULL; + + PHAL_GDMA_ADAPTER pHALDACGdmaAdpt = NULL; + PHAL_GDMA_OP pHALDACGdmaOp = NULL; + PIRQ_HANDLE pIrqHandleDACGdma = NULL; + + /*To Get the SAL_I2C_MNGT_ADPT Pointer*/ + pSalDACHNDPriv = CONTAINER_OF(pSalDACHND, SAL_DAC_HND_PRIV, SalDACHndPriv); + pSalDACMngtAdpt = CONTAINER_OF(pSalDACHNDPriv->ppSalDACHnd, SAL_DAC_MNGT_ADPT, pSalHndPriv); + + pHALDACGdmaAdpt = pSalDACMngtAdpt->pHalGdmaAdp; + pHALDACGdmaOp = pSalDACMngtAdpt->pHalGdmaOp; + pIrqHandleDACGdma = pSalDACMngtAdpt->pIrqGdmaHnd; + + if (RtkDACIdxChk(pSalDACHND->DevNum)) + return _EXIT_FAILURE; + + HalGdmaOpInit(pHALDACGdmaOp); + + pHALDACGdmaAdpt->IsrCtrl = DISABLE; + pHALDACGdmaOp->HalGdmaChIsrEnAndDis((VOID*)pHALDACGdmaAdpt); + pHALDACGdmaOp->HalGdmaChIsrClean((VOID*)pHALDACGdmaAdpt); + pHALDACGdmaOp->HalGdmaChDis((VOID*)pHALDACGdmaAdpt); + + InterruptUnRegister(pIrqHandleDACGdma); +#if 0 + _memset((void *)pIrqHandleDACGdma , 0, sizeof(IRQ_HANDLE)); + _memset((void *)pHALDACGdmaOp , 0, sizeof(HAL_GDMA_OP)); + _memset((void *)pHALDACGdmaAdpt , 0, sizeof(HAL_GDMA_ADAPTER)); +#endif + return _EXIT_SUCCESS; +} + +#endif + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CInit +// +// Description: +// According to the given I2C index, the related SAL_I2C_MNGT_ADPT pointer used +// for retrieving each I2C data sturcture pointer will be reversely parsed first. +// Then, initializing I2C HAL operation, initializing I2C interrupt (if needed), +// initializing I2C DMA (if needed) and initializing I2C pinmux will be done. +// User specified I2C configuration will be assigned to I2C initial data structure +// (PHAL_I2C_INIT_DAT pHalI2CInitDat). I2C HAL initialization is executed after +// all the configuration data taken. +// In the end, I2C module is enabled as a final step of the whole initialization. +// For a slave ack General Call support, an additional step may be followed after +// the above steps. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C initialization process. +// _EXIT_SUCCESS if the RtkI2CInit succeeded. +// _EXIT_FAILURE if the RtkI2CInit failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +RTK_STATUS +RtkDACInit( + IN VOID *Data +){ + PSAL_DAC_HND pSalDACHND = (PSAL_DAC_HND) Data; + PSAL_DAC_HND_PRIV pSalDACHNDPriv = NULL; + PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt = NULL; + //PHAL_DAC_INIT_DAT pHalDACInitDat = NULL; + PHAL_DAC_OP pHalDACOP = NULL; + + u32 DacTemp; + + /* To Get the SAL_I2C_MNGT_ADPT Pointer */ + pSalDACHNDPriv = CONTAINER_OF(pSalDACHND, SAL_DAC_HND_PRIV, SalDACHndPriv); + pSalDACMngtAdpt = CONTAINER_OF(pSalDACHNDPriv->ppSalDACHnd, SAL_DAC_MNGT_ADPT, pSalHndPriv); + + //pHalDACInitDat = pSalDACMngtAdpt->pHalInitDat; + pHalDACOP = pSalDACMngtAdpt->pHalOp; + + /* Check the input I2C index first */ + if (RtkDACIdxChk(pSalDACHND->DevNum)) + return _EXIT_FAILURE; + +#if 0 + /* Check the input I2C operation type */ + if (RtkI2COpTypeChk(pSalI2CHND)) + return _EXIT_FAILURE; +#endif + + /* DAC Initialize HAL Operations */ + HalDACOpInit(pHalDACOP); + + /* DAC Interrupt Initialization */ +#if DAC_INTR_OP_TYPE + RtkDACIrqInit(pSalDACHND); +#endif + + /* DAC DMA Initialization */ +#if DAC_DMA_OP_TYPE + RtkDACDMAInit(pSalDACHND); +#endif + + + /* DAC Function and Clock Enable*/ + RtkDACPinMuxInit(pSalDACHND); + + pHalDACOP->HalDACInit(pSalDACHND->pInitDat); + + #if 1 + HAL_DAC_WRITE32(pSalDACHND->DevNum, REG_DAC_INTR_CTRL, + (BIT_DAC_FIFO_FULL_EN | + BIT_DAC_FIFO_OVERFLOW_EN | + BIT_DAC_FIFO_STOP_EN | + BIT_DAC__WRITE_ERROR_EN | + BIT_DAC_DSC_OVERFLOW0_EN | + BIT_DAC_DSC_OVERFLOW1_EN)); + #else + HAL_DAC_WRITE32(pSalDACHND->DevNum, REG_DAC_INTR_CTRL, + (BIT_DAC_FIFO_FULL_EN| + BIT_DAC_FIFO_OVERFLOW_EN| + BIT_DAC_FIFO_STOP_EN| + BIT_DAC__WRITE_ERROR_EN| + BIT_DAC_DSC_OVERFLOW0_EN| + BIT_DAC_DSC_OVERFLOW1_EN)); + #endif + DBG_DAC_INFO("INTR MSK:%x\n", HAL_DAC_READ32(pSalDACHND->DevNum,REG_DAC_INTR_CTRL)); + + + + DacTemp = HAL_DAC_READ32(pSalDACHND->DevNum, REG_DAC_ANAPAR_DA1); + DacTemp |= (BIT31); + HAL_DAC_WRITE32(pSalDACHND->DevNum, REG_DAC_ANAPAR_DA1, DacTemp); + //DBG_DAC_INFO("REG_DAC_ANAPAR_DA1:%08x\n",DacTemp); + DBG_DAC_INFO("REG_DAC_ANAPAR_DA1:%08x\n",HAL_DAC_READ32(pSalDACHND->DevNum, REG_DAC_ANAPAR_DA1)); + DacTemp = HAL_DAC_READ32(pSalDACHND->DevNum, REG_DAC_CTRL); + DacTemp |= BIT3; + HAL_DAC_WRITE32(pSalDACHND->DevNum, REG_DAC_CTRL, DacTemp); + DBG_DAC_INFO("REG_DAC_CTRL:%08x\n",DacTemp); + + pSalDACHND->pInitDat->DACEn = DAC_ENABLE; + pHalDACOP->HalDACEnable(pSalDACHND->pInitDat); + + /* DAC Device Status Update */ + pSalDACHND->DevSts = DAC_STS_IDLE; + + return _EXIT_SUCCESS; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CInit +// +// Description: +// According to the given I2C index, the related SAL_I2C_MNGT_ADPT pointer used +// for retrieving each I2C data sturcture pointer will be reversely parsed first. +// Then, initializing I2C HAL operation, initializing I2C interrupt (if needed), +// initializing I2C DMA (if needed) and initializing I2C pinmux will be done. +// User specified I2C configuration will be assigned to I2C initial data structure +// (PHAL_I2C_INIT_DAT pHalI2CInitDat). I2C HAL initialization is executed after +// all the configuration data taken. +// In the end, I2C module is enabled as a final step of the whole initialization. +// For a slave ack General Call support, an additional step may be followed after +// the above steps. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C initialization process. +// _EXIT_SUCCESS if the RtkI2CInit succeeded. +// _EXIT_FAILURE if the RtkI2CInit failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +RTK_STATUS +RtkDACDeInit( + IN VOID *Data +){ + PSAL_DAC_HND pSalDACHND = (PSAL_DAC_HND) Data; + PSAL_DAC_HND_PRIV pSalDACHNDPriv = NULL; + PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt = NULL; + PHAL_DAC_INIT_DAT pHalDACInitDat = NULL; + PHAL_DAC_OP pHalDACOP = NULL; + + /* To Get the SAL_DAC_MNGT_ADPT Pointer */ + pSalDACHNDPriv = CONTAINER_OF(pSalDACHND, SAL_DAC_HND_PRIV, SalDACHndPriv); + pSalDACMngtAdpt = CONTAINER_OF(pSalDACHNDPriv->ppSalDACHnd, SAL_DAC_MNGT_ADPT, pSalHndPriv); + + pHalDACInitDat = pSalDACMngtAdpt->pHalInitDat; + pHalDACOP = pSalDACMngtAdpt->pHalOp; + + /* Check the input DAC index first */ + if (RtkDACIdxChk(pSalDACHND->DevNum)) + return _EXIT_FAILURE; + + { + /* DAC Initialize HAL Operations */ + HalDACOpInit(pHalDACOP); + + /* DAC Interrupt Initialization */ +#if DAC_INTR_OP_TYPE + RtkDACIrqDeInit(pSalDACHND); +#endif + + /* DAC DMA Initialization */ +#if DAC_DMA_OP_TYPE + RtkDACDMADeInit(pSalDACHND); +#endif + + pHalDACInitDat->DACEn = DAC_DISABLE; + pHalDACOP->HalDACEnable(pHalDACInitDat); + pHalDACOP->HalDACDeInit(pHalDACInitDat); + + /* DAC Function and Clock Enable*/ + RtkDACPinMuxDeInit(pSalDACHND); + } + + return _EXIT_SUCCESS; +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CInit +// +// Description: +// According to the given I2C index, the related SAL_I2C_MNGT_ADPT pointer used +// for retrieving each I2C data sturcture pointer will be reversely parsed first. +// Then, initializing I2C HAL operation, initializing I2C interrupt (if needed), +// initializing I2C DMA (if needed) and initializing I2C pinmux will be done. +// User specified I2C configuration will be assigned to I2C initial data structure +// (PHAL_I2C_INIT_DAT pHalI2CInitDat). I2C HAL initialization is executed after +// all the configuration data taken. +// In the end, I2C module is enabled as a final step of the whole initialization. +// For a slave ack General Call support, an additional step may be followed after +// the above steps. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C initialization process. +// _EXIT_SUCCESS if the RtkI2CInit succeeded. +// _EXIT_FAILURE if the RtkI2CInit failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +RTK_STATUS +RtkDACSend( + IN VOID *Data +){ + PSAL_DAC_HND pSalDACHND = (PSAL_DAC_HND) Data; + PSAL_DAC_HND_PRIV pSalDACHNDPriv = NULL; + PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt = NULL; + PHAL_GDMA_ADAPTER pHALDACGdmaAdpt = NULL; + PHAL_GDMA_OP pHALDACGdmaOp = NULL; + PSAL_DAC_DMA_USER_DEF pSalDACDmaUserDef = NULL; + //PIRQ_HANDLE pIrqHandleDACGdma = NULL; + + /* To Get the SAL_I2C_MNGT_ADPT Pointer */ + pSalDACHNDPriv = CONTAINER_OF(pSalDACHND, SAL_DAC_HND_PRIV, SalDACHndPriv); + pSalDACMngtAdpt = CONTAINER_OF(pSalDACHNDPriv->ppSalDACHnd, SAL_DAC_MNGT_ADPT, pSalHndPriv); + + pHALDACGdmaAdpt = pSalDACMngtAdpt->pHalGdmaAdp; + pHALDACGdmaOp = pSalDACMngtAdpt->pHalGdmaOp; + pSalDACDmaUserDef = pSalDACMngtAdpt->pDMAConf; + + switch (pSalDACHND->DACInType) { + case DAC_INPUT_SINGLE_WR: + { + break; + } + case DAC_INPUT_DMA_ONEBLK: + { + HalGdmaOpInit(pHALDACGdmaOp); + + pHALDACGdmaAdpt->GdmaCtl.BlockSize = pSalDACHND->pTXBuf->DataLen; + pHALDACGdmaAdpt->ChSar = (u32)pSalDACHND->pTXBuf->pDataBuf; + pHALDACGdmaAdpt->ChDar = (u32)(DAC_REG_BASE+(pSalDACHND->DevNum*0x800)); + + DBG_DAC_INFO("src addr:%x\n", pHALDACGdmaAdpt->ChSar); + DBG_DAC_INFO("dst addr:%x\n", pHALDACGdmaAdpt->ChDar); + pHALDACGdmaOp->HalGdmaChSeting(pHALDACGdmaAdpt); + + pHALDACGdmaOp->HalGdmaChEn(pHALDACGdmaAdpt); + break; + } + case DAC_INPUT_DMA_LLP: + { + pHALDACGdmaAdpt->Rsvd4to7 = 1; + pHALDACGdmaAdpt->pLlix = (struct GDMA_CH_LLI *)pSalDACDmaUserDef->pLlix; + pHALDACGdmaAdpt->pBlockSizeList = (struct BLOCK_SIZE_LIST *)pSalDACDmaUserDef->pBlockSizeList; + pHALDACGdmaAdpt->ChDar = (u32)(DAC_REG_BASE+(pSalDACHND->DevNum*0x800)); + pHALDACGdmaOp->HalGdmaChBlockSeting(pHALDACGdmaAdpt); + + pHALDACGdmaOp->HalGdmaChEn(pHALDACGdmaAdpt); + break; + } + + default: + return _EXIT_FAILURE; + } + + + return _EXIT_SUCCESS; +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CGetSalHnd +// +// Description: +// Allocation of lower layer memory spaces will be done by invoking RtkI2CGetMngtAdpt +// in this function and return a SAL_I2C_HND pointer to upper layer. +// According to the given I2C index, RtkI2CGetMngtAdpt will allocate all the memory +// space such as SAL_I2C_HND, HAL_I2C_INIT_DAT, SAL_I2C_USER_CB etc. +// +// +// Arguments: +// [in] u8 I2CIdx - +// I2C Index +// +// Return: +// PSAL_I2C_HND +// A pointer to SAL_I2C_HND which is allocated in the lower layer. +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +PSAL_DAC_HND +RtkDACGetSalHnd( + IN u8 DACIdx +){ + PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt = NULL; + PSAL_DAC_HND pSalDACHND = NULL; + + /* Check the user define setting and the given index */ + if (RtkDACIdxChk(DACIdx)) { + return (PSAL_DAC_HND)NULL; + } + + /* Invoke RtkI2CGetMngtAdpt to get the I2C SAL management adapter pointer */ + pSalDACMngtAdpt = RtkDACGetMngtAdpt(DACIdx); + + /* Assign the private SAL handle to public SAL handle */ + pSalDACHND = &(pSalDACMngtAdpt->pSalHndPriv->SalDACHndPriv); + + /* Assign the internal HAL initial data pointer to the SAL handle */ + pSalDACHND->pInitDat = pSalDACMngtAdpt->pHalInitDat; + + /* Assign the internal user callback pointer to the SAL handle */ + pSalDACHND->pUserCB = pSalDACMngtAdpt->pUserCB; + + /* Assign the internal user DMA config to the SAL handle */ + pSalDACHND->pDMAConf = pSalDACMngtAdpt->pDMAConf; + + return &(pSalDACMngtAdpt->pSalHndPriv->SalDACHndPriv); +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CGetSalHnd +// +// Description: +// Allocation of lower layer memory spaces will be done by invoking RtkI2CGetMngtAdpt +// in this function and return a SAL_I2C_HND pointer to upper layer. +// According to the given I2C index, RtkI2CGetMngtAdpt will allocate all the memory +// space such as SAL_I2C_HND, HAL_I2C_INIT_DAT, SAL_I2C_USER_CB etc. +// +// +// Arguments: +// [in] u8 I2CIdx - +// I2C Index +// +// Return: +// PSAL_I2C_HND +// A pointer to SAL_I2C_HND which is allocated in the lower layer. +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +RTK_STATUS +RtkDACFreeSalHnd( + IN PSAL_DAC_HND pSalDACHND +){ + PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt = NULL; + PSAL_DAC_HND_PRIV pSalDACHNDPriv = NULL; + + /* To get the SAL_DAC_MNGT_ADPT pointer */ + pSalDACHNDPriv = CONTAINER_OF(pSalDACHND, SAL_DAC_HND_PRIV, SalDACHndPriv); + pSalDACMngtAdpt = CONTAINER_OF(pSalDACHNDPriv->ppSalDACHnd, SAL_DAC_MNGT_ADPT, pSalHndPriv); + + /* Invoke RtkDACFreeMngtAdpt to free all the lower layer memory space */ + return (RtkDACFreeMngtAdpt(pSalDACMngtAdpt)); + +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CLoadDefault +// +// Description: +// Accrording the given I2C index, the default I2C configuration is done. +// +// +// Arguments: +// [in] PSAL_I2C_HND pSalI2CHND - +// SAL I2C handle +// +// Return: +// The status of the loading I2C default configuration. +// _EXIT_SUCCESS if the RtkI2CLoadDefault succeeded. +// _EXIT_FAILURE if the RtkI2CLoadDefault failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +RTK_STATUS +RtkDACLoadDefault( + IN VOID *Data +){ + PSAL_DAC_HND pSalDACHND = (PSAL_DAC_HND) Data; + + /* Check the input DAC index first */ + if (RtkDACIdxChk(pSalDACHND->DevNum)) + return _EXIT_FAILURE; + + /* Load SAL handle default value */ + pSalDACHND->PinMux = 0; + pSalDACHND->OpType = DAC_POLL_TYPE; + pSalDACHND->DevSts = DAC_STS_UNINITIAL; + pSalDACHND->DACExd = 0; + pSalDACHND->ErrType = (u32)NULL; + + /* Load HAL initial data structure default value */ + pSalDACHND->pInitDat->DACIdx = pSalDACHND->DevNum; + pSalDACHND->pInitDat->DACEn = DAC_DISABLE; + pSalDACHND->pInitDat->DACDataRate = DAC_DATA_RATE_250K; + pSalDACHND->pInitDat->DACEndian = DAC_DATA_ENDIAN_LITTLE; + pSalDACHND->pInitDat->DACBurstSz = 7; + pSalDACHND->pInitDat->DACDbgSel = DAC_DBG_SEL_DISABLE; + pSalDACHND->pInitDat->DACDscDbgSel = DAC_DSC_DBG_SEL_DISABLE; + pSalDACHND->pInitDat->DACBPDsc = DAC_BYPASS_DSC_SEL_DISABLE; + pSalDACHND->pInitDat->DACDeltaSig = 0; + pSalDACHND->pInitDat->DACAnaCtrl0 = 0; + pSalDACHND->pInitDat->DACAnaCtrl1 = 0; + pSalDACHND->pInitDat->DACIntrMSK = DAC_FEATURE_DISABLED; + + /* Load DAC DMA user configuration default value */ + pSalDACHND->pDMAConf->MaxMultiBlk = 5000; + pSalDACHND->pDMAConf->TxDatSrcWdth = TrWidthFourBytes; + pSalDACHND->pDMAConf->TxDatSrcBstSz = MsizeFour; + pSalDACHND->pDMAConf->TxDatDstWdth = TrWidthFourBytes; + pSalDACHND->pDMAConf->TxDatDstBstSz = MsizeFour; + pSalDACHND->pDMAConf->TxChNo = 4; + + return _EXIT_SUCCESS; +} diff --git a/lib/fwlib/src/hal_gdma.c b/lib/fwlib/src/hal_gdma.c new file mode 100644 index 0000000..79f8e20 --- /dev/null +++ b/lib/fwlib/src/hal_gdma.c @@ -0,0 +1,574 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "rtl8195a.h" +#include "hal_gdma.h" + +#define MAX_GDMA_INDX 1 +#define MAX_GDMA_CHNL 6 + +static u8 HalGdmaReg[MAX_GDMA_INDX+1]; + +const HAL_GDMA_CHNL GDMA_Chnl_Option[] = { + {0,0,GDMA0_CHANNEL0_IRQ,0}, + {1,0,GDMA1_CHANNEL0_IRQ,0}, + {0,1,GDMA0_CHANNEL1_IRQ,0}, + {1,1,GDMA1_CHANNEL1_IRQ,0}, + {0,2,GDMA0_CHANNEL2_IRQ,0}, + {1,2,GDMA1_CHANNEL2_IRQ,0}, + {0,3,GDMA0_CHANNEL3_IRQ,0}, + {1,3,GDMA1_CHANNEL3_IRQ,0}, + {0,4,GDMA0_CHANNEL4_IRQ,0}, + {1,4,GDMA1_CHANNEL4_IRQ,0}, + {0,5,GDMA0_CHANNEL5_IRQ,0}, + {1,5,GDMA1_CHANNEL5_IRQ,0}, + + {0xff,0,0,0} // end +}; + +const HAL_GDMA_CHNL GDMA_Multi_Block_Chnl_Option[] = { + {0,4,GDMA0_CHANNEL4_IRQ,0}, + {1,4,GDMA1_CHANNEL4_IRQ,0}, + {0,5,GDMA0_CHANNEL5_IRQ,0}, + {1,5,GDMA1_CHANNEL5_IRQ,0}, + + {0xff,0,0,0} // end +}; + + +const u16 HalGdmaChnlEn[6] = { + GdmaCh0, GdmaCh1, GdmaCh2, GdmaCh3, + GdmaCh4, GdmaCh5 +}; + + + +VOID HalGdmaOpInit( + IN VOID *Data +) +{ + PHAL_GDMA_OP pHalGdmaOp = (PHAL_GDMA_OP) Data; + + pHalGdmaOp->HalGdmaOnOff = HalGdmaOnOffRtl8195a; + pHalGdmaOp->HalGdamChInit = HalGdamChInitRtl8195a; + pHalGdmaOp->HalGdmaChDis = HalGdmaChDisRtl8195a; + pHalGdmaOp->HalGdmaChEn = HalGdmaChEnRtl8195a; + pHalGdmaOp->HalGdmaChSeting = HalGdmaChSetingRtl8195a; +#ifndef CONFIG_CHIP_E_CUT + pHalGdmaOp->HalGdmaChBlockSeting = HalGdmaChBlockSetingRtl8195a; +#else + pHalGdmaOp->HalGdmaChBlockSeting = HalGdmaChBlockSetingRtl8195a_V04; +#endif + pHalGdmaOp->HalGdmaChIsrEnAndDis = HalGdmaChIsrEnAndDisRtl8195a; + pHalGdmaOp->HalGdmaChIsrClean = HalGdmaChIsrCleanRtl8195a; + pHalGdmaOp->HalGdmaChCleanAutoSrc = HalGdmaChCleanAutoSrcRtl8195a; + pHalGdmaOp->HalGdmaChCleanAutoDst = HalGdmaChCleanAutoDstRtl8195a; +} + +VOID HalGdmaOn(PHAL_GDMA_ADAPTER pHalGdmaAdapter) +{ + pHalGdmaAdapter->GdmaOnOff = ON; + HalGdmaOnOffRtl8195a((VOID*)pHalGdmaAdapter); +} + +VOID HalGdmaOff(PHAL_GDMA_ADAPTER pHalGdmaAdapter) +{ + pHalGdmaAdapter->GdmaOnOff = OFF; + HalGdmaOnOffRtl8195a((VOID*)pHalGdmaAdapter); +} + +BOOL HalGdmaChInit(PHAL_GDMA_ADAPTER pHalGdmaAdapter) +{ + return (HalGdamChInitRtl8195a((VOID*)pHalGdmaAdapter)); +} + +VOID HalGdmaChDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter) +{ + HalGdmaChDisRtl8195a((VOID*)pHalGdmaAdapter); +} + +VOID HalGdmaChEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter) +{ + HalGdmaChEnRtl8195a((VOID*)pHalGdmaAdapter); +} + +BOOL HalGdmaChSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter) +{ + return (HalGdmaChSetingRtl8195a((VOID*)pHalGdmaAdapter)); +} + +BOOL HalGdmaChBlockSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter) +{ +#ifndef CONFIG_CHIP_E_CUT + return (HalGdmaChBlockSetingRtl8195a((VOID*)pHalGdmaAdapter)); +#else + return (HalGdmaChBlockSetingRtl8195a_V04((VOID*)pHalGdmaAdapter)); +#endif +} + +VOID HalGdmaChIsrEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter) +{ + pHalGdmaAdapter->IsrCtrl = ENABLE; + HalGdmaChIsrEnAndDisRtl8195a((VOID*)pHalGdmaAdapter); +} + +VOID HalGdmaChIsrDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter) +{ + pHalGdmaAdapter->IsrCtrl = DISABLE; + HalGdmaChIsrEnAndDisRtl8195a((VOID*)pHalGdmaAdapter); +} + +u8 HalGdmaChIsrClean(PHAL_GDMA_ADAPTER pHalGdmaAdapter) +{ + return (HalGdmaChIsrCleanRtl8195a((VOID*)pHalGdmaAdapter)); +} + +VOID HalGdmaChCleanAutoSrc(PHAL_GDMA_ADAPTER pHalGdmaAdapter) +{ + HalGdmaChCleanAutoSrcRtl8195a((VOID*)pHalGdmaAdapter); +} + +VOID HalGdmaChCleanAutoDst(PHAL_GDMA_ADAPTER pHalGdmaAdapter) +{ + HalGdmaChCleanAutoDstRtl8195a((VOID*)pHalGdmaAdapter); +} + +HAL_Status HalGdmaChnlRegister (u8 GdmaIdx, u8 ChnlNum) +{ + u32 mask; + + if ((GdmaIdx > MAX_GDMA_INDX) || (ChnlNum > MAX_GDMA_CHNL)) { + // Invalid GDMA Index or Channel Number + return HAL_ERR_PARA; + } + + mask = 1 << ChnlNum; + + if ((HalGdmaReg[GdmaIdx] & mask) != 0) { + return HAL_BUSY; + } + else { +#if 1 + if (HalGdmaReg[GdmaIdx] == 0) { + if (GdmaIdx == 0) { + ACTCK_GDMA0_CCTRL(ON); + GDMA0_FCTRL(ON); + } + else { + ACTCK_GDMA1_CCTRL(ON); + GDMA1_FCTRL(ON); + } + } +#endif + HalGdmaReg[GdmaIdx] |= mask; + return HAL_OK; + } +} + +VOID HalGdmaChnlUnRegister (u8 GdmaIdx, u8 ChnlNum) +{ + u32 mask; + + if ((GdmaIdx > MAX_GDMA_INDX) || (ChnlNum > MAX_GDMA_CHNL)) { + // Invalid GDMA Index or Channel Number + return; + } + + mask = 1 << ChnlNum; + + HalGdmaReg[GdmaIdx] &= ~mask; +#if 1 + if (HalGdmaReg[GdmaIdx] == 0) { + if (GdmaIdx == 0) { + ACTCK_GDMA0_CCTRL(OFF); + GDMA0_FCTRL(OFF); + } + else { + ACTCK_GDMA1_CCTRL(OFF); + GDMA1_FCTRL(OFF); + } + } +#endif +} + +PHAL_GDMA_CHNL HalGdmaChnlAlloc (HAL_GDMA_CHNL *pChnlOption) +{ + HAL_GDMA_CHNL *pgdma_chnl; + + pgdma_chnl = pChnlOption; + if (pChnlOption == NULL) { + // Use default GDMA Channel Option table + pgdma_chnl = (HAL_GDMA_CHNL*)&GDMA_Chnl_Option[0]; + } + else{ + pgdma_chnl = (HAL_GDMA_CHNL*) pgdma_chnl; + } + + while (pgdma_chnl->GdmaIndx <= MAX_GDMA_INDX) { + if (HalGdmaChnlRegister(pgdma_chnl->GdmaIndx, pgdma_chnl->GdmaChnl) == HAL_OK) { + // This GDMA Channel is available + break; + } + pgdma_chnl += 1; + } + + if (pgdma_chnl->GdmaIndx > MAX_GDMA_INDX) { + pgdma_chnl = NULL; + } + + return pgdma_chnl; +} + +VOID HalGdmaChnlFree (HAL_GDMA_CHNL *pChnl) +{ + IRQ_HANDLE IrqHandle; + + IrqHandle.IrqNum = pChnl->IrqNum; + InterruptDis(&IrqHandle); + InterruptUnRegister(&IrqHandle); + HalGdmaChnlUnRegister(pChnl->GdmaIndx, pChnl->GdmaChnl); +} + +VOID HalGdmaMemIrqHandler(VOID *pData) +{ + PHAL_GDMA_OBJ pHalGdmaObj=(PHAL_GDMA_OBJ)pData; + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + PIRQ_HANDLE pGdmaIrqHandle; + + pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter); + pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle); + // Clean Auto Reload Bit + HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter); + + // Clear Pending ISR + HalGdmaChIsrClean((VOID*)pHalGdmaAdapter); + + HalGdmaChDis((VOID*)(pHalGdmaAdapter)); + pHalGdmaObj->Busy = 0; + + if (pGdmaIrqHandle->IrqFun != NULL) { + pGdmaIrqHandle->IrqFun((VOID*)pGdmaIrqHandle->Data); + } +} + +BOOL HalGdmaMemCpyAggrInit(PHAL_GDMA_OBJ pHalGdmaObj) +{ + HAL_GDMA_CHNL *pgdma_chnl; + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + PIRQ_HANDLE pGdmaIrqHandle; + IRQ_HANDLE IrqHandle; + + pgdma_chnl = HalGdmaChnlAlloc((PHAL_GDMA_CHNL) &GDMA_Multi_Block_Chnl_Option[0]); // get a whatever GDMA channel + if (NULL == pgdma_chnl) { + DBG_GDMA_ERR("%s: Cannot allocate a GDMA Channel\n", __FUNCTION__); + return _FALSE; + } + + pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter); + pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle); + + DBG_GDMA_INFO("%s: Use GDMA%d CH%d\n", __FUNCTION__, pgdma_chnl->GdmaIndx, pgdma_chnl->GdmaChnl); + + _memset((void *)pHalGdmaAdapter, 0, sizeof(HAL_GDMA_ADAPTER)); + + pHalGdmaAdapter->GdmaCtl.TtFc = TTFCMemToMem; + pHalGdmaAdapter->GdmaCtl.Done = 1; + pHalGdmaAdapter->MuliBlockCunt = 0; + pHalGdmaAdapter->MaxMuliBlock = 1; + pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl; + pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx; + pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl; + pHalGdmaAdapter->GdmaIsrType = (TransferType|ErrType); + pHalGdmaAdapter->IsrCtrl = ENABLE; + pHalGdmaAdapter->GdmaOnOff = ON; + pHalGdmaAdapter->GdmaCtl.IntEn = 1; + pHalGdmaAdapter->Rsvd4to7 = 1; + pHalGdmaAdapter->Llpctrl = 1; + pGdmaIrqHandle->IrqNum = pgdma_chnl->IrqNum; + pGdmaIrqHandle->Priority = 0x10; + + IrqHandle.IrqFun = (IRQ_FUN) HalGdmaMemIrqHandler; + IrqHandle.Data = (u32) pHalGdmaObj; + IrqHandle.IrqNum = pGdmaIrqHandle->IrqNum; + IrqHandle.Priority = pGdmaIrqHandle->Priority; + + InterruptRegister(&IrqHandle); + InterruptEn(&IrqHandle); + pHalGdmaObj->Busy = 0; + + return _TRUE; +} + + +VOID HalGdmaMultiBlockSetting(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock) +{ + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + u8 BlockNumber; + u8 BlockIndex; + u8 FourBytesAlign; + + BlockNumber = pHalGdmaObj->BlockNum; + pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter); + + pHalGdmaAdapter->GdmaCtl.LlpSrcEn = 1; + pHalGdmaAdapter->GdmaCtl.LlpDstEn = 1; + + if(((pHalGdmaBlock[0].SrcAddr & 0x03) == 0) &&((pHalGdmaBlock[0].DstAddr & 0x03) == 0) + && ((pHalGdmaBlock[0].BlockLength & 0X03) == 0)){ + pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight; + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes; + pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes; + FourBytesAlign = 1; + } + else{ + pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight; + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte; + pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte; + FourBytesAlign = 0; + } + + for(BlockIndex = 0; BlockIndex < BlockNumber; BlockIndex++){ + + pHalGdmaObj->GdmaChLli[BlockIndex].Sarx = pHalGdmaBlock[BlockIndex].SrcAddr; + pHalGdmaObj->GdmaChLli[BlockIndex].Darx = pHalGdmaBlock[BlockIndex].DstAddr; + pHalGdmaObj->BlockSizeList[BlockIndex].pNextBlockSiz = &pHalGdmaObj->BlockSizeList[BlockIndex + 1]; + + if(FourBytesAlign){ + pHalGdmaObj->BlockSizeList[BlockIndex].BlockSize = pHalGdmaBlock[BlockIndex].BlockLength >> 2; + } + else{ + pHalGdmaObj->BlockSizeList[BlockIndex].BlockSize = pHalGdmaBlock[BlockIndex].BlockLength; + } + + pHalGdmaObj->Lli[BlockIndex].pLliEle = (GDMA_CH_LLI_ELE*) &pHalGdmaObj->GdmaChLli[BlockIndex]; + pHalGdmaObj->Lli[BlockIndex].pNextLli = &pHalGdmaObj->Lli[BlockIndex + 1]; + + + if(BlockIndex == BlockNumber - 1){ + pHalGdmaObj->BlockSizeList[BlockIndex].pNextBlockSiz = NULL; + pHalGdmaObj->Lli[BlockIndex].pNextLli = NULL; + } + //DBG_GDMA_INFO("Lli[%d].pLiEle = %x\r\n", BlockIndex,Lli[BlockIndex].pLliEle); + //DBG_GDMA_INFO("Lli[%d].pNextLli = %x\r\n", BlockIndex,Lli[BlockIndex].pNextLli); + } + + pHalGdmaAdapter->pBlockSizeList = (struct BLOCK_SIZE_LIST*) &pHalGdmaObj->BlockSizeList; + pHalGdmaAdapter->pLlix = (struct GDMA_CH_LLI*) &pHalGdmaObj->Lli; + //DBG_GDMA_INFO("pHalGdmaAdapter->pBlockSizeList = %x\r\n", pHalGdmaAdapter->pBlockSizeList); + //DBG_GDMA_INFO("pHalGdmaAdapter->pLlix = %x\r\n", pHalGdmaAdapter->pLlix ); +} + +VOID HalGdmaLLPMemAlign(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock) +{ + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + PGDMA_CH_LLI_ELE pLliEle; + struct GDMA_CH_LLI *pGdmaChLli; + struct BLOCK_SIZE_LIST *pGdmaChBkLi; + u32 CtlxLow; + u32 CtlxUp; + u8 BlockNumber; + u8 BlockIndex; + + pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter); + BlockNumber = pHalGdmaObj->BlockNum; + + pLliEle = pHalGdmaAdapter->pLlix->pLliEle; + pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli; + pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList; + + //4 Move to the second block to configure Memory Alginment setting + pLliEle->Llpx = (u32) pGdmaChLli->pLliEle; + pGdmaChBkLi = pGdmaChBkLi ->pNextBlockSiz; + + for(BlockIndex = 1; BlockIndex < BlockNumber; BlockIndex++){ + pLliEle = pGdmaChLli->pLliEle; + CtlxLow = pLliEle->CtlxLow; + CtlxLow &= (BIT_INVC_CTLX_LO_DST_TR_WIDTH & BIT_INVC_CTLX_LO_SRC_TR_WIDTH); + CtlxUp = pLliEle->CtlxUp; + CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS); + + if(((pHalGdmaBlock[BlockIndex].SrcAddr & 0x03) == 0) &&((pHalGdmaBlock[BlockIndex].DstAddr & 0x03) == 0) + && ((pHalGdmaBlock[BlockIndex].BlockLength & 0X03) == 0)){ + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes; + pGdmaChBkLi->BlockSize = pHalGdmaBlock[BlockIndex].BlockLength>> 2; + + } + else{ + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte; + pGdmaChBkLi->BlockSize = pHalGdmaBlock[BlockIndex].BlockLength; + } + + CtlxLow |= (BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) | + BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth)); + CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize); + + pGdmaChLli = pGdmaChLli->pNextLli; + pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz; + pLliEle->CtlxLow = CtlxLow; + pLliEle->CtlxUp = CtlxUp; + pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle); + + } +} + +VOID HalGdmaMemAggr(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock) +{ + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + + u8 BlockNumber; + + BlockNumber = pHalGdmaObj->BlockNum; + pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter); + + if (pHalGdmaObj->Busy) { + DBG_GDMA_ERR("%s: ==> GDMA is Busy\r\n", __FUNCTION__); + return; + } + pHalGdmaObj->Busy = 1; + + pHalGdmaAdapter->MaxMuliBlock = BlockNumber; + pHalGdmaAdapter->ChSar = pHalGdmaBlock[0].SrcAddr; + pHalGdmaAdapter->ChDar = pHalGdmaBlock[0].DstAddr; + + HalGdmaMultiBlockSetting(pHalGdmaObj, pHalGdmaBlock); + HalGdmaOn((pHalGdmaAdapter)); + HalGdmaChIsrEn((pHalGdmaAdapter)); + HalGdmaChBlockSeting((pHalGdmaAdapter)); + HalGdmaLLPMemAlign(pHalGdmaObj, pHalGdmaBlock); + HalGdmaChEn((pHalGdmaAdapter)); + +} + + + +BOOL HalGdmaMemCpyInit(PHAL_GDMA_OBJ pHalGdmaObj) +{ + HAL_GDMA_CHNL *pgdma_chnl; + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + PIRQ_HANDLE pGdmaIrqHandle; + IRQ_HANDLE IrqHandle; + + pgdma_chnl = HalGdmaChnlAlloc(NULL); // get a whatever GDMA channel + if (NULL == pgdma_chnl) { + DBG_GDMA_ERR("%s: Cannot allocate a GDMA Channel\n", __FUNCTION__); + return _FALSE; + } + + pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter); + pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle); + + DBG_GDMA_INFO("%s: Use GDMA%d CH%d\n", __FUNCTION__, pgdma_chnl->GdmaIndx, pgdma_chnl->GdmaChnl); +#if 0 + if (pgdma_chnl->GdmaIndx == 0) { + ACTCK_GDMA0_CCTRL(ON); + GDMA0_FCTRL(ON); + } + else if (pgdma_chnl->GdmaIndx == 1) { + ACTCK_GDMA1_CCTRL(ON); + GDMA1_FCTRL(ON); + } +#endif + _memset((void *)pHalGdmaAdapter, 0, sizeof(HAL_GDMA_ADAPTER)); + +// pHalGdmaAdapter->GdmaCtl.TtFc = TTFCMemToMem; + pHalGdmaAdapter->GdmaCtl.Done = 1; +// pHalGdmaAdapter->MuliBlockCunt = 0; +// pHalGdmaAdapter->MaxMuliBlock = 1; + pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl; + pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx; + pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl; + pHalGdmaAdapter->GdmaIsrType = (TransferType|ErrType); + pHalGdmaAdapter->IsrCtrl = ENABLE; + pHalGdmaAdapter->GdmaOnOff = ON; + + pHalGdmaAdapter->GdmaCtl.IntEn = 1; +// pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight; +// pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight; +// pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes; +// pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes; +// pHalGdmaAdapter->GdmaCtl.Dinc = IncType; +// pHalGdmaAdapter->GdmaCtl.Sinc = IncType; + + pGdmaIrqHandle->IrqNum = pgdma_chnl->IrqNum; + pGdmaIrqHandle->Priority = 10; + + IrqHandle.IrqFun = (IRQ_FUN) HalGdmaMemIrqHandler; + IrqHandle.Data = (u32) pHalGdmaObj; + IrqHandle.IrqNum = pGdmaIrqHandle->IrqNum; + IrqHandle.Priority = pGdmaIrqHandle->Priority; + + InterruptRegister(&IrqHandle); + InterruptEn(&IrqHandle); + pHalGdmaObj->Busy = 0; + + return _TRUE; +} + +VOID HalGdmaMemCpyDeInit(PHAL_GDMA_OBJ pHalGdmaObj) +{ + HAL_GDMA_CHNL GdmaChnl; + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + PIRQ_HANDLE pGdmaIrqHandle; + + pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter); + pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle); + + GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex; + GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum; + GdmaChnl.IrqNum = pGdmaIrqHandle->IrqNum; + HalGdmaChnlFree(&GdmaChnl); +} + +// If multi-task using the same GDMA Object, then it needs a mutex to protect this procedure +VOID* HalGdmaMemCpy(PHAL_GDMA_OBJ pHalGdmaObj, void* pDest, void* pSrc, u32 len) +{ + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + + if (pHalGdmaObj->Busy) { + DBG_GDMA_ERR("%s: ==> GDMA is Busy\r\n", __FUNCTION__); + return 0; + } + pHalGdmaObj->Busy = 1; + pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter); + + DBG_GDMA_INFO("%s: ==> Src=0x%x Dst=0x%x Len=%d\r\n", __FUNCTION__, pSrc, pDest, len); + if ((((u32)pSrc & 0x03)==0) && + (((u32)pDest & 0x03)==0) && + ((len & 0x03)== 0)) { + // 4-bytes aligned, move 4 bytes each transfer + pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight; + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes; + pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes; + pHalGdmaAdapter->GdmaCtl.BlockSize = len >> 2; + } + else { + pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight; + pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte; + pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight; + pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte; + pHalGdmaAdapter->GdmaCtl.BlockSize = len; + } + + pHalGdmaAdapter->ChSar = (u32)pSrc; + pHalGdmaAdapter->ChDar = (u32)pDest; + pHalGdmaAdapter->PacketLen = len; + + HalGdmaOn((pHalGdmaAdapter)); + HalGdmaChIsrEn((pHalGdmaAdapter)); + HalGdmaChSeting((pHalGdmaAdapter)); + HalGdmaChEn((pHalGdmaAdapter)); + + return (pDest); +} diff --git a/lib/fwlib/src/hal_gpio.c b/lib/fwlib/src/hal_gpio.c new file mode 100644 index 0000000..d2cb94e --- /dev/null +++ b/lib/fwlib/src/hal_gpio.c @@ -0,0 +1,145 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#include "rtl8195a.h" + +#ifdef CONFIG_GPIO_EN + +HAL_GPIO_DATA_SECTION HAL_GPIO_ADAPTER gHAL_Gpio_Adapter; +extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter; + +extern VOID GPIO_PullCtrl_8195a(u32 chip_pin, u8 pull_type); + +/** + * @brief To get the GPIO IP Pin name for the given chip pin name + * + * @param chip_pin: The chip pin name. + * + * @retval The gotten GPIO IP pin name + */ +HAL_GPIO_TEXT_SECTION u32 +HAL_GPIO_GetPinName( + u32 chip_pin +) +{ + return HAL_GPIO_GetIPPinName_8195a((u32)chip_pin); +} + +/** + * @brief Set the GPIO pad Pull type + * + * @param pin: The pin for pull type control. + * @param mode: the pull type for the pin. + * @return None + */ +VOID +HAL_GPIO_PullCtrl( + u32 pin, + u32 mode +) +{ + u8 pull_type; + + DBG_GPIO_INFO("%s: pin=0x%x mode=%d\n ", __FUNCTION__, (u32)pin, (u32)mode); + + switch (mode) { + case hal_PullNone: + pull_type = DIN_PULL_NONE; + break; + + case hal_PullDown: + pull_type = DIN_PULL_LOW; + break; + + case hal_PullUp: + pull_type = DIN_PULL_HIGH; + break; + + case hal_OpenDrain: + default: + pull_type = DIN_PULL_NONE; + break; + } + +// HAL_GPIO_PullCtrl_8195a (pin, pull_type); + GPIO_PullCtrl_8195a (pin, pull_type); +} + + +/** + * @brief Initializes a GPIO Pin by the GPIO_Pin parameters. + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization. + * + * @retval HAL_Status + */ +HAL_GPIO_TEXT_SECTION VOID +HAL_GPIO_Init( + HAL_GPIO_PIN *GPIO_Pin +) +{ + if (_pHAL_Gpio_Adapter == NULL) { + _pHAL_Gpio_Adapter = &gHAL_Gpio_Adapter; + DBG_GPIO_INFO("%s: Initial GPIO Adapter\n ", __FUNCTION__); + } + + HAL_GPIO_Init_8195a(GPIO_Pin); +} + +/** + * @brief Initializes a GPIO Pin as a interrupt signal + * + * @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization. + * + * @retval HAL_Status + */ +VOID +HAL_GPIO_Irq_Init( + HAL_GPIO_PIN *GPIO_Pin +) +{ + if (_pHAL_Gpio_Adapter == NULL) { + _pHAL_Gpio_Adapter = &gHAL_Gpio_Adapter; + DBG_GPIO_INFO("%s: Initial GPIO Adapter\n ", __FUNCTION__); + } + + if (_pHAL_Gpio_Adapter->IrqHandle.IrqFun == NULL) { + _pHAL_Gpio_Adapter->IrqHandle.IrqFun = HAL_GPIO_MbedIrqHandler_8195a; + _pHAL_Gpio_Adapter->IrqHandle.Priority = 8; + HAL_GPIO_RegIrq_8195a(&_pHAL_Gpio_Adapter->IrqHandle); + InterruptEn(&_pHAL_Gpio_Adapter->IrqHandle); + DBG_GPIO_INFO("%s: Initial GPIO IRQ Adapter\n ", __FUNCTION__); + } + + DBG_GPIO_INFO("%s: GPIO(name=0x%x)(mode=%d)\n ", __FUNCTION__, GPIO_Pin->pin_name, + GPIO_Pin->pin_mode); + HAL_GPIO_MaskIrq_8195a(GPIO_Pin); + HAL_GPIO_Init_8195a(GPIO_Pin); +} + +/** + * @brief UnInitial GPIO Adapter + * + * + * @retval HAL_Status + */ +VOID +HAL_GPIO_IP_DeInit( + VOID +) +{ + if (_pHAL_Gpio_Adapter != NULL) { + InterruptDis(&_pHAL_Gpio_Adapter->IrqHandle); + HAL_GPIO_UnRegIrq_8195a(&_pHAL_Gpio_Adapter->IrqHandle); + _pHAL_Gpio_Adapter = NULL; + } + +} + +#endif // CONFIG_GPIO_EN diff --git a/lib/fwlib/src/hal_i2c.c b/lib/fwlib/src/hal_i2c.c new file mode 100644 index 0000000..3984c91 --- /dev/null +++ b/lib/fwlib/src/hal_i2c.c @@ -0,0 +1,2694 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#include "rtl8195a.h" +#include +#include "hal_i2c.h" + +//--------------------------------------------------------------------------------------------------- +//External functions +//--------------------------------------------------------------------------------------------------- +extern HAL_TIMER_OP HalTimerOp; + +#define I2C_STATIC_ALLOC 1 +/* I2C SAL global variables declaration when kernel disabled */ +#ifdef I2C_STATIC_ALLOC + HAL_I2C_OP HalI2COpSAL; +#endif + +#if I2C0_USED /*#if I2C0_USED*/ +#ifdef I2C_STATIC_ALLOC + SAL_I2C_MNGT_ADPT SalI2C0MngtAdpt; + + SAL_I2C_HND_PRIV SalI2C0HndPriv; + + HAL_I2C_INIT_DAT HalI2C0InitData; + + IRQ_HANDLE I2C0IrqHandleDat; + + HAL_GDMA_ADAPTER HalI2C0TxGdmaAdpt; + + HAL_GDMA_ADAPTER HalI2C0RxGdmaAdpt; + + HAL_GDMA_OP HalI2C0GdmaOp; + + IRQ_HANDLE I2C0TxGdmaIrqHandleDat; + + IRQ_HANDLE I2C0RxGdmaIrqHandleDat; + + SAL_I2C_USER_CB SalI2C0UserCB; + + SAL_I2C_USERCB_ADPT SalI2C0UserCBAdpt[SAL_USER_CB_NUM]; + + SAL_I2C_DMA_USER_DEF SalI2C0DmaUserDef; +#endif +#endif /*#if I2C0_USED*/ + +#if I2C1_USED /*#if I2C1_USED*/ +#ifdef I2C_STATIC_ALLOC + SAL_I2C_MNGT_ADPT SalI2C1MngtAdpt; + + SAL_I2C_HND_PRIV SalI2C1HndPriv; + + HAL_I2C_INIT_DAT HalI2C1InitData; + + IRQ_HANDLE I2C1IrqHandleDat; + + HAL_GDMA_ADAPTER HalI2C1TxGdmaAdpt; + + HAL_GDMA_ADAPTER HalI2C1RxGdmaAdpt; + + HAL_GDMA_OP HalI2C1GdmaOp; + + IRQ_HANDLE I2C1TxGdmaIrqHandleDat; + + IRQ_HANDLE I2C1RxGdmaIrqHandleDat; + + SAL_I2C_USER_CB SalI2C1UserCB; + + SAL_I2C_USERCB_ADPT SalI2C1UserCBAdpt[SAL_USER_CB_NUM]; + + SAL_I2C_DMA_USER_DEF SalI2C1DmaUserDef; +#endif +#endif /*#if I2C1_USED*/ + +#if I2C2_USED /*#if I2C2_USED*/ +#ifdef I2C_STATIC_ALLOC + + SAL_I2C_MNGT_ADPT SalI2C2MngtAdpt; + + SAL_I2C_HND_PRIV SalI2C2HndPriv; + + HAL_I2C_INIT_DAT HalI2C2InitData; + + IRQ_HANDLE I2C2IrqHandleDat; + + HAL_GDMA_ADAPTER HalI2C2TxGdmaAdpt; + + HAL_GDMA_ADAPTER HalI2C2RxGdmaAdpt; + + HAL_GDMA_OP HalI2C2GdmaOp; + + IRQ_HANDLE I2C2TxGdmaIrqHandleDat; + + IRQ_HANDLE I2C2RxGdmaIrqHandleDat; + + SAL_I2C_USER_CB SalI2C2UserCB; + + SAL_I2C_USERCB_ADPT SalI2C2UserCBAdpt[SAL_USER_CB_NUM]; + + SAL_I2C_DMA_USER_DEF SalI2C2DmaUserDef; +#endif +#endif /*#if I2C2_USED*/ + +#if I2C3_USED /*#if I2C3_USED*/ +#ifdef I2C_STATIC_ALLOC + + SAL_I2C_MNGT_ADPT SalI2C3MngtAdpt; + + SAL_I2C_HND_PRIV SalI2C3HndPriv; + + HAL_I2C_INIT_DAT HalI2C3InitData; + + IRQ_HANDLE I2C3IrqHandleDat; + + HAL_GDMA_ADAPTER HalI2C3TxGdmaAdpt; + + HAL_GDMA_ADAPTER HalI2C3RxGdmaAdpt; + + HAL_GDMA_OP HalI2C3GdmaOp; + + IRQ_HANDLE I2C3TxGdmaIrqHandleDat; + + IRQ_HANDLE I2C3RxGdmaIrqHandleDat; + + SAL_I2C_USER_CB SalI2C3UserCB; + + SAL_I2C_USERCB_ADPT SalI2C3UserCBAdpt[SAL_USER_CB_NUM]; + + SAL_I2C_DMA_USER_DEF SalI2C3DmaUserDef; +#endif +#endif /*#if I2C3_USED*/ + +/* Used only for A~C Version */ +#ifndef CONFIG_CHIP_E_CUT + + + +VOID +HalI2COpInit_Patch( + IN VOID *Data +) +{ + PHAL_I2C_OP pHalI2COp = (PHAL_I2C_OP) Data; + + pHalI2COp->HalI2CInit = HalI2CInit8195a_Patch; + DBG_I2C_INFO("HalOpInit->HalI2CInit:%x\n",pHalI2COp->HalI2CInit); + + pHalI2COp->HalI2CDeInit = HalI2CDeInit8195a; + DBG_I2C_INFO("HalOpInit->HalI2CDeInit:%x\n",pHalI2COp->HalI2CDeInit); + + pHalI2COp->HalI2CSend = HalI2CSendRtl8195a_Patch; + DBG_I2C_INFO("HalOpInit->HalI2CSend:%x\n",pHalI2COp->HalI2CSend); + + pHalI2COp->HalI2CReceive = HalI2CReceiveRtl8195a; + DBG_I2C_INFO("HalOpInit->HalI2CReceive:%x\n",pHalI2COp->HalI2CReceive); + + pHalI2COp->HalI2CEnable = HalI2CEnableRtl8195a; + DBG_I2C_INFO("HalOpInit->HalI2CEnable:%x\n",pHalI2COp->HalI2CEnable); + + pHalI2COp->HalI2CIntrCtrl = HalI2CIntrCtrl8195a; + DBG_I2C_INFO("HalOpInit->HalI2CIntrCtrl:%x\n",pHalI2COp->HalI2CIntrCtrl); + + pHalI2COp->HalI2CReadReg = HalI2CReadRegRtl8195a; + DBG_I2C_INFO("HalOpInit->HalI2CReadReg:%x\n",pHalI2COp->HalI2CReadReg); + + pHalI2COp->HalI2CWriteReg = HalI2CWriteRegRtl8195a; + DBG_I2C_INFO("pHalI2COp->HalI2CWriteReg:%x\n",pHalI2COp->HalI2CWriteReg); + + pHalI2COp->HalI2CSetCLK = HalI2CSetCLKRtl8195a_Patch; + DBG_I2C_INFO("HalOpInit->HalI2CSetCLK:%x\n",pHalI2COp->HalI2CSetCLK); + + pHalI2COp->HalI2CMassSend = HalI2CMassSendRtl8195a; + DBG_I2C_INFO("HalOpInit->HalI2CMassSend:%x\n",pHalI2COp->HalI2CMassSend); + + pHalI2COp->HalI2CClrIntr = HalI2CClrIntrRtl8195a; + DBG_I2C_INFO("HalOpInit->HalI2CClrIntr:%x\n",pHalI2COp->HalI2CClrIntr); + + pHalI2COp->HalI2CClrAllIntr = HalI2CClrAllIntrRtl8195a; + DBG_I2C_INFO("HalOpInit->HalI2CClrAllIntr:%x\n",pHalI2COp->HalI2CClrAllIntr); + + pHalI2COp->HalI2CDMACtrl = HalI2CDMACtrl8195a; + DBG_I2C_INFO("HalOpInit->HalI2CDMACtrl:%x\n",pHalI2COp->HalI2CDMACtrl); +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// I2CISRHandle +// +// Description: +// I2C Interrupt Service Routine. +// According to the input pointer to SAL_I2C_HND, all the rest pointers will be +// found and be used to the rest part of this servie routine. +// The following types of interrupt will be taken care: +// - General Call (providing General Call Callback). Slave receives a general call. +// - STOP Bit (NOT providing General Call Callback) +// - START Bit (NOTproviding General Call Callback) +// - I2C Activity (NOTproviding General Call Callback) +// - RX Done (providing Error Callback). The slave transmitter does NOT +// receive a proper NACK for the end of whole transfer. +// - TX Abort (providing Error Call Callback). The Master/Slave +// transmitting is terminated. +// - RD Req (providing TX and TXC Callback). Slave gets a Read Request +// and starts a slave-transmitter operation. The slave transmit +// data will be written into slave TX FIFO from user data buffer. +// - TX Empty (providing TX and TXC Callback). Master TX FIFO is empty. +// The user transmit data will be written into master TX FIFO +// from user data buffer. +// - TX Over (providing Error Callback). Master TX FIFO is Overflow. +// - RX Full (providing RX and RXC Callback). Master/Slave RX FIFO contains +// data. And the received data will be put into Master/Slave user +// receive data buffer. +// - RX Over (providing Error Callback). Master/Slave RX FIFO is Overflow. +// - RX Under (providing Error Callback). Master/Slave RX FIFO is Underflow. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// NA +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//---------------------------------------------------------------------------------------------------- +VOID +I2CISRHandle_Patch( + IN VOID *Data +){ + PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data; + PSAL_I2C_HND_PRIV pSalI2CHNDPriv = NULL; + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PHAL_I2C_INIT_DAT pHalI2CInitDat = NULL; + PHAL_I2C_OP pHalI2COP = NULL; + PSAL_I2C_USER_CB pSalI2CUserCB = NULL; + u32 I2CLocalTemp = 0; + u32 I2CInTOTcnt = 0; + u32 I2CIrqIdx = 0; + u32 InTimeoutCount = 0; + u32 InStartCount = 0; + volatile u32 I2CLocalRawSts = 0; + + + /* To get the SAL_I2C_MNGT_ADPT pointer, and parse the rest pointers */ + pSalI2CHNDPriv = CONTAINER_OF(pSalI2CHND, SAL_I2C_HND_PRIV, SalI2CHndPriv); + pSalI2CMngtAdpt = CONTAINER_OF(pSalI2CHNDPriv->ppSalI2CHnd, SAL_I2C_MNGT_ADPT, pSalHndPriv); + pHalI2CInitDat = pSalI2CMngtAdpt->pHalInitDat; + pHalI2COP = pSalI2CMngtAdpt->pHalOp; + I2CInTOTcnt = pSalI2CMngtAdpt->InnerTimeOut; + I2CIrqIdx = pHalI2CInitDat->I2CIdx; + pSalI2CUserCB = pSalI2CHND->pUserCB; + //DBG_8195A("NEW ISR\n"); + /* I2C General Call Intr*/ + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) & + BIT_CTRL_IC_INTR_STAT_R_GEN_CALL(1)) { + + DBG_I2C_WARN("I2C%d INTR_GEN_CALL\n",I2CIrqIdx); + + /* Clear I2C interrupt */ + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_GEN_CALL; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + + /* Invoke I2C General Call callback if available*/ + if (pSalI2CUserCB->pGENCALLCB->USERCB != NULL) { + pSalI2CUserCB->pGENCALLCB->USERCB((void *)pSalI2CUserCB->pGENCALLCB->USERData); + } + } + + /* I2C START DET Intr */ + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) & + BIT_CTRL_IC_INTR_STAT_R_START_DET(1)) { + + DBG_I2C_WARN("I2C%d INTR_START_DET\n",I2CIrqIdx); + + /* Clear I2C interrupt */ + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_START_DET; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + } + + /* I2C STOP DET Intr */ + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) & + BIT_CTRL_IC_INTR_STAT_R_STOP_DET(1)) { + + DBG_I2C_WARN("I2C%d INTR_STOP_DET\n",I2CIrqIdx); + + /* Clear I2C interrupt */ + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_STOP_DET; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + } + + /* I2C Activity Intr */ + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) & + BIT_CTRL_IC_INTR_STAT_R_ACTIVITY(1)) { + + DBG_I2C_WARN("I2C%d INTR_ACTIVITY\n",I2CIrqIdx); + + /* Clear I2C interrupt */ + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_ACTIVITY; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + } + + /* I2C RX Done Intr */ + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) & + BIT_CTRL_IC_INTR_STAT_R_RX_DONE(1)) { + //DBG_8195A("rxdone\n"); + DBG_I2C_ERR("I2C%d INTR_RX_DONE\n",I2CIrqIdx); + DBG_I2C_ERR("I2C%d IC_TXFLR:%2x\n",I2CIrqIdx, + pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_TXFLR)); + + /* Clear I2C interrupt */ + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_RX_DONE; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_ERROR; + + /* Update I2C error type */ + pSalI2CHND->ErrType |= I2C_ERR_SLV_TX_NACK; + + /* Invoke I2C error callback if available */ + if (pSalI2CUserCB->pERRCB->USERCB != NULL) + pSalI2CUserCB->pERRCB->USERCB((void *)pSalI2CUserCB->pERRCB->USERData); + } + + /* I2C TX Abort Intr */ + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) & + BIT_CTRL_IC_INTR_STAT_R_TX_ABRT(1)) { + //DBG_8195A("abort\n"); + DBG_I2C_ERR("!!!I2C%d INTR_TX_ABRT!!!\n",I2CIrqIdx); + DBG_I2C_ERR("I2C%d IC_TX_ABRT_SOURCE[%2x]: %x\n", I2CIrqIdx, REG_DW_I2C_IC_TX_ABRT_SOURCE, + pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_TX_ABRT_SOURCE)); + DBG_I2C_ERR("Dev Sts:%x\n",pSalI2CHND->DevSts); + DBG_I2C_ERR("rx len:%x\n",pSalI2CHND->pRXBuf->DataLen); + DBG_I2C_ERR("tx len:%x\n",pSalI2CHND->pTXBuf->DataLen); + DBG_I2C_ERR("raw sts:%x\n",pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_RAW_INTR_STAT)); + DBG_I2C_ERR("ic sts:%x\n",pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS)); + /* Clear I2C Interrupt */ + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_TX_ABRT; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + I2CLocalTemp = pSalI2CHND->DevSts; + + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_ERROR; + + /* Update I2C error type */ + pSalI2CHND->ErrType |= I2C_ERR_TX_ABRT; + + /* Invoke I2C error callback */ + if (pSalI2CUserCB->pERRCB->USERCB != NULL) + pSalI2CUserCB->pERRCB->USERCB((void *)pSalI2CUserCB->pERRCB->USERData); + + if (pSalI2CHND->I2CExd & I2C_EXD_MTR_ADDR_RTY) { + if (pSalI2CHND->I2CMaster == I2C_MASTER_MODE) { + if ((I2CLocalTemp == I2C_STS_RX_READY) || (I2CLocalTemp == I2C_STS_RX_ING)) { + /* Clear Abort source */ + pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_CLR_TX_ABRT); + + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_RX_ING; + + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS) + & BIT_IC_STATUS_TFNF) { + if (pSalI2CMngtAdpt->MstRDCmdCnt > 0) { + pHalI2CInitDat->I2CCmd = I2C_READ_CMD; + pHalI2CInitDat->I2CDataLen= 1; + pHalI2CInitDat->I2CRWData = pSalI2CHND->pRXBuf->pDataBuf; + pHalI2CInitDat->I2CStop = I2C_STOP_DIS; + if ((pSalI2CMngtAdpt->MstRDCmdCnt == 1) && ((pSalI2CHND->I2CExd & I2C_EXD_MTR_HOLD_BUS) == 0)) + pHalI2CInitDat->I2CStop = I2C_STOP_EN; + //DBG_8195A("A0\n"); + pSalI2CMngtAdpt->MstRDCmdCnt--; + pHalI2COP->HalI2CMassSend(pHalI2CInitDat); + } + + } + } + else if ((I2CLocalTemp == I2C_STS_TX_READY) || (I2CLocalTemp == I2C_STS_TX_ING)){ + /* Clear Abort source */ + pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_CLR_TX_ABRT); + + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_TX_ING; + + /* Return to the former transfer status */ + pSalI2CHND->pTXBuf->pDataBuf--; + pSalI2CHND->pTXBuf->DataLen++; + + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS) + & BIT_IC_STATUS_TFNF) { + pHalI2CInitDat->I2CCmd = I2C_WRITE_CMD; + pHalI2CInitDat->I2CDataLen= 1; + pHalI2CInitDat->I2CRWData = pSalI2CHND->pTXBuf->pDataBuf; + pHalI2CInitDat->I2CStop = I2C_STOP_DIS; + if ((pSalI2CHND->pTXBuf->DataLen == 1) && ((pSalI2CHND->I2CExd & I2C_EXD_MTR_HOLD_BUS) == 0)) + pHalI2CInitDat->I2CStop = I2C_STOP_EN; + + pHalI2COP->HalI2CMassSend(pHalI2CInitDat); + + pSalI2CHND->pTXBuf->pDataBuf++; + pSalI2CHND->pTXBuf->DataLen--; + } + } + } + } + } + + /* I2C RD REQ Intr */ + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) & + BIT_CTRL_IC_INTR_STAT_R_RD_REQ(1)) { + /* Confirm it's slave mode */ + if (pSalI2CHND->I2CMaster == I2C_SLAVE_MODE) { + //DBG_8195A("rq\n"); + if (pSalI2CHND->pTXBuf->DataLen>0) { + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_TX_ING; + + /* Invoke I2C TX callback if available */ + if (pSalI2CUserCB->pTXCB->USERCB != NULL) + pSalI2CUserCB->pTXCB->USERCB((void *)pSalI2CUserCB->pTXCB->USERData); + + /* I2C Slave transmits data to Master. If the TX FIFO is NOT full, + write one byte from slave TX buffer to TX FIFO. */ + if ((pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_STATUS) + & (BIT_IC_STATUS_TFNF)) == BIT_IC_STATUS_TFNF) { + pHalI2CInitDat->I2CCmd = I2C_WRITE_CMD; + pHalI2CInitDat->I2CDataLen= 1; + pHalI2CInitDat->I2CRWData = pSalI2CHND->pTXBuf->pDataBuf; + pHalI2CInitDat->I2CStop = I2C_STOP_DIS; + if ((pSalI2CHND->pTXBuf->DataLen == 1) && ((pSalI2CHND->I2CExd & I2C_EXD_MTR_HOLD_BUS) == 0)) + pHalI2CInitDat->I2CStop = I2C_STOP_EN; + + pHalI2COP->HalI2CMassSend(pHalI2CInitDat); + + pSalI2CHND->pTXBuf->pDataBuf++; + pSalI2CHND->pTXBuf->DataLen--; + } + } + + /* To clear Read Request Intr */ + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_RD_REQ; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + + /* To check I2C slave TX data length. If all the data are transmitted, + mask all the interrupts and invoke the user callback */ + if (!pSalI2CHND->pTXBuf->DataLen) { + /* This is a software patch */ + pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_RAW_INTR_STAT); + HalDelayUs(1000); + + /* Disable I2C TX Related Interrupts */ + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_INTR_MASK); + I2CLocalTemp &= ~(BIT_IC_INTR_MASK_M_TX_ABRT | + BIT_IC_INTR_MASK_M_TX_OVER | + BIT_IC_INTR_MASK_M_RX_DONE | + BIT_IC_INTR_MASK_M_RD_REQ); + pHalI2CInitDat->I2CIntrMSK = I2CLocalTemp; + pHalI2COP->HalI2CIntrCtrl(pHalI2CInitDat); + pHalI2COP->HalI2CClrAllIntr(pHalI2CInitDat); + + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_IDLE; + + /* Invoke I2C TX complete callback if available */ + if (pSalI2CUserCB->pTXCCB->USERCB != NULL) + pSalI2CUserCB->pTXCCB->USERCB((void *)pSalI2CUserCB->pTXCCB->USERData); + } + } + } + + /* I2C TX Empty Intr */ + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) & + BIT_CTRL_IC_INTR_STAT_R_TX_EMPTY(1)) { + /* Confirm it's master mode */ + if (pSalI2CHND->I2CMaster == I2C_MASTER_MODE) { + + /* To check I2C master TX data length. If all the data are transmitted, + mask all the interrupts and invoke the user callback */ + if (!pSalI2CHND->pTXBuf->DataLen) { + /* I2C Disable TX Related Interrupts */ + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_INTR_MASK); + I2CLocalTemp &= ~(BIT_IC_INTR_MASK_M_TX_ABRT | + BIT_IC_INTR_MASK_M_TX_EMPTY | + BIT_IC_INTR_MASK_M_TX_OVER); + pHalI2CInitDat->I2CIntrMSK = I2CLocalTemp; + pHalI2COP->HalI2CIntrCtrl(pHalI2CInitDat); + + /* Clear all I2C pending interrupts */ + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_IDLE; + + /* Invoke I2C TX Complete callback */ + if (pSalI2CUserCB->pTXCCB->USERCB != NULL) + pSalI2CUserCB->pTXCCB->USERCB((void *)pSalI2CUserCB->pTXCCB->USERData); + } + + if (pSalI2CHND->pTXBuf->DataLen > 0) { + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_TX_ING; + + /* Invoke I2C TX callback if available */ + if (pSalI2CUserCB->pTXCB->USERCB != NULL) + pSalI2CUserCB->pTXCB->USERCB((void *)pSalI2CUserCB->pTXCB->USERData); + + /* Check I2C TX FIFO status. If it's not full, one byte data will be written into it. */ + if ((pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_STATUS) + & (BIT_IC_STATUS_TFNF)) == BIT_IC_STATUS_TFNF) { + pHalI2CInitDat->I2CCmd = I2C_WRITE_CMD; + pHalI2CInitDat->I2CDataLen= 1; + pHalI2CInitDat->I2CRWData = pSalI2CHND->pTXBuf->pDataBuf; + pHalI2CInitDat->I2CStop = I2C_STOP_DIS; + pHalI2CInitDat->I2CReSTR = 1; + if ((pSalI2CHND->pTXBuf->DataLen == 1) && ((pSalI2CHND->I2CExd & I2C_EXD_MTR_HOLD_BUS) == 0)) + pHalI2CInitDat->I2CStop = I2C_STOP_EN; + + pHalI2COP->HalI2CMassSend(pHalI2CInitDat); + + pSalI2CHND->pTXBuf->pDataBuf++; + pSalI2CHND->pTXBuf->DataLen--; + + } + } + }/*if (pSalI2CHND->I2CMaster == I2C_MASTER_MODE)*/ + } + + /* I2C TX Over Run Intr */ + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) & + BIT_CTRL_IC_INTR_STAT_R_TX_OVER(1)) { + + DBG_I2C_ERR("!!!I2C%d INTR_TX_OVER!!!\n",I2CIrqIdx); + + /* Clear I2C interrupt */ + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_TX_OVER; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_ERROR; + + /* Update I2C error type */ + pSalI2CHND->ErrType |= I2C_ERR_TX_OVER; + + /* Invoke I2C error callback if available */ + if (pSalI2CUserCB->pERRCB->USERCB != NULL) + pSalI2CUserCB->pERRCB->USERCB((void *)pSalI2CUserCB->pERRCB->USERData); + } + + /* I2C RX Full Intr */ + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) & + BIT_CTRL_IC_INTR_STAT_R_RX_FULL(1)) { + /* Check if it's Master */ + if (pSalI2CHND->I2CMaster == I2C_MASTER_MODE){ + + //DBG_8195A("full\n"); + /* Check if the receive transfer is NOT finished. If it is not, check if there + is data in the RX FIFO and move the data from RX FIFO to user data buffer*/ + if (pSalI2CHND->pRXBuf->DataLen > 0) { + + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_RX_ING; + + /* Invoke I2C RX callback if available */ + if (pSalI2CUserCB->pRXCB->USERCB != NULL) + pSalI2CUserCB->pRXCB->USERCB((void *)pSalI2CUserCB->pRXCB->USERData); + + I2CInTOTcnt = (u32)pSalI2CMngtAdpt->InnerTimeOut; + InTimeoutCount = 0; + /* Calculate internal time out parameters */ + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + + while (1) { + I2CLocalRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS); + if ((I2CLocalRawSts & (BIT_IC_STATUS_RFNE | BIT_IC_STATUS_RFF)) != 0) { + *(pSalI2CHND->pRXBuf->pDataBuf) = + pHalI2COP->HalI2CReceive(pHalI2CInitDat); + //DBG_8195A("rx:%x\n",*(pSalI2CHND->pRXBuf->pDataBuf)); + pSalI2CHND->pRXBuf->pDataBuf++; + pSalI2CHND->pRXBuf->DataLen--; + + if ((pSalI2CHND->pRXBuf->DataLen) == 0) + break; + } + else if ((pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_RAW_INTR_STAT) + & (BIT_IC_RAW_INTR_STAT_RX_OVER | BIT_IC_RAW_INTR_STAT_RX_UNDER)) != 0) { + break; + } + else { + if ((pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS) & BIT_IC_STATUS_RFNE) + == 0){ + break; + } + } + + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_RX_FF_TO; + DBG_I2C_ERR("RX Full Timeout, I2C%2x,1\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + break; + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_RX_FF_TO; + DBG_I2C_ERR("RX Full Timeout, I2C%2x,2\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + break; + } + } + } + } + + /* To check I2C master RX data length. If all the data are received, + mask all the interrupts and invoke the user callback. + Otherwise, the master should send another Read Command to slave for + the next data byte receiving. */ + if (!pSalI2CHND->pRXBuf->DataLen) { + /* I2C Disable RX Related Interrupts */ + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_INTR_MASK); + I2CLocalTemp &= ~(BIT_IC_INTR_MASK_M_RX_FULL | + BIT_IC_INTR_MASK_M_RX_OVER | + BIT_IC_INTR_MASK_M_RX_UNDER| + BIT_IC_INTR_MASK_M_TX_ABRT); + + pHalI2CInitDat->I2CIntrMSK = I2CLocalTemp; + pHalI2COP->HalI2CIntrCtrl(pHalI2CInitDat); + + /* Clear all I2C pending interrupts */ + pHalI2COP->HalI2CClrAllIntr(pHalI2CInitDat); + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_IDLE; + + /* Invoke I2C RX complete callback if available */ + if (pSalI2CUserCB->pRXCCB->USERCB != NULL) + pSalI2CUserCB->pRXCCB->USERCB((void *)pSalI2CUserCB->pRXCCB->USERData); + } + else { + /* If TX FIFO is not full, another Read Command is written into it. */ + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS) + & BIT_IC_STATUS_TFNF) { + if (pSalI2CMngtAdpt->MstRDCmdCnt > 0) { + pHalI2CInitDat->I2CCmd = I2C_READ_CMD; + pHalI2CInitDat->I2CDataLen= 1; + pHalI2CInitDat->I2CRWData = pSalI2CHND->pRXBuf->pDataBuf; + pHalI2CInitDat->I2CStop = I2C_STOP_DIS; + pHalI2CInitDat->I2CReSTR = 1; + if ((pSalI2CMngtAdpt->MstRDCmdCnt == 1) && ((pSalI2CHND->I2CExd & I2C_EXD_MTR_HOLD_BUS) == 0)){ + pHalI2CInitDat->I2CStop = I2C_STOP_EN; + } + pSalI2CMngtAdpt->MstRDCmdCnt--; + pHalI2COP->HalI2CMassSend(pHalI2CInitDat); + } + } + } + + }/*(pSalI2CHND->I2CMaster == I2C_MASTER_MODE)*/ + else{ + /* To check I2C master RX data length. If all the data are received, + mask all the interrupts and invoke the user callback. + Otherwise, if there is data in the RX FIFO and move the data from RX + FIFO to user data buffer*/ + if (pSalI2CHND->pRXBuf->DataLen > 0){ + + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_RX_ING; + + /* Invoke I2C RX callback if available */ + if (pSalI2CUserCB->pRXCB->USERCB != NULL) + pSalI2CUserCB->pRXCB->USERCB((void *)pSalI2CUserCB->pRXCB->USERData); + + if ((pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS) + & (BIT_IC_STATUS_RFNE | BIT_IC_STATUS_RFF)) != 0) { + *(pSalI2CHND->pRXBuf->pDataBuf) = + pHalI2COP->HalI2CReceive(pHalI2CInitDat); + pSalI2CHND->pRXBuf->pDataBuf++; + pSalI2CHND->pRXBuf->DataLen--; + } + } + + /* All data are received. Mask all related interrupts. */ + if (!pSalI2CHND->pRXBuf->DataLen){ + /*I2C Disable RX Related Interrupts*/ + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_INTR_MASK); + I2CLocalTemp &= ~(BIT_IC_INTR_MASK_M_RX_FULL | + BIT_IC_INTR_MASK_M_RX_OVER | + BIT_IC_INTR_MASK_M_RX_UNDER); + + pHalI2CInitDat->I2CIntrMSK = I2CLocalTemp; + pHalI2COP->HalI2CIntrCtrl(pHalI2CInitDat); + + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_IDLE; + + /* Invoke I2C RX complete callback if available */ + if (pSalI2CUserCB->pRXCCB->USERCB != NULL) + pSalI2CUserCB->pRXCCB->USERCB((void *)pSalI2CUserCB->pRXCCB->USERData); + } + } + } + + /*I2C RX Over Run Intr*/ + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) & + BIT_CTRL_IC_INTR_STAT_R_RX_OVER(1)) { + + DBG_I2C_ERR("I2C%d INTR_RX_OVER\n",I2CIrqIdx); + + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_RX_OVER; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_ERROR; + + /* Update I2C error type */ + pSalI2CHND->ErrType |= I2C_ERR_RX_OVER; + + /* Invoke I2C error callback if available */ + if (pSalI2CUserCB->pERRCB->USERCB != NULL) + pSalI2CUserCB->pERRCB->USERCB((void *)pSalI2CUserCB->pERRCB->USERData); + } + + /*I2C RX Under Run Intr*/ + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) & + BIT_CTRL_IC_INTR_STAT_R_RX_UNDER(1)) { + + DBG_I2C_ERR("!!!I2C%d INTR_RX_UNDER!!!\n",I2CIrqIdx); + + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_RX_UNDER; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + + /* Update I2C device status */ + pSalI2CHND->DevSts = I2C_STS_ERROR; + + /* Update I2C error type */ + pSalI2CHND->ErrType |= I2C_ERR_RX_UNDER; + + /* Invoke I2C error callback if available */ + if (pSalI2CUserCB->pERRCB->USERCB != NULL) + pSalI2CUserCB->pERRCB->USERCB((void *)pSalI2CUserCB->pERRCB->USERData); + } +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CSend +// +// Description: +// To execute Master-Transmitter and Slave-Transmitter operation. +// There are 3 operation mode in this function which are separated by compile-time +// flag. +// For Master-Transmitter, the User Register Address flag is checked first. +// User Register Address may be sent before any formal transfer, no matter in +// Poll-, Intr- or DMA- Mode. +// +// In Poll-Mode, no matter it's master or slave mode, the transfer will be done in +// this function by checking the transfer length. +// -Master in Poll-Mode: +// a. Send the User Register Address if needed. +// b. Check if all the data are transmitted. If it's NOT, checking the TX FIFO +// status is done for writing data from user TX buffer to I2C TX FIFO when +// TX FIFO is NOT full. +// TX data length decrements one after writing one byte into TX FIFO. +// c. b is executed circularly till the TX buffer data length is zero. +// +// -Slave in Poll-Mode: +// Slave could send data only when it received a Read Commmand matched +// with its own I2C address from other I2C master. Once a slave correctly +// received a Read Command matched with its own addr., a Read-Request +// flag is set at the same time. +// In this Poll-Mode, the slave checks the Read-Request flag to decide +// if it could send its TX buffer data. +// a. Check if the Read-Request flag is set or not. If the flag is set, it should +// check if TX buffer data length is zero. If it's NOT, +// the I2C TX FIFO status will be checked for the following operation. +// b. If the TX FIFO is NOT empty, slave will write one byte data from TX data +// buffer to TX FIFO. +// c. a and b are executed circularly till the TX buffer data length is zero. +//---------------------------------------------------------------------- +// In Intr-Mode, this function is used to unmask the realted I2C interrupt for +// the following interrupt operations. +// -Master in Intr-Mode: +// a. Send the User Register Address if needed. +// b. Unmask the TX-Empty and realted error interrupts. +// +// -Slave in Intr-Mode: +// a. Unmask the RD-Req and realted error interrupts. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C send process. +// _EXIT_SUCCESS if the RtkI2CSend succeeded. +// _EXIT_FAILURE if the RtkI2CSend failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +HAL_Status +RtkI2CSend_Patch( + IN VOID *Data +){ + PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data; + PSAL_I2C_HND_PRIV pSalI2CHNDPriv = NULL; + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PHAL_I2C_INIT_DAT pHalI2CInitDat = NULL; + PHAL_I2C_OP pHalI2COP = NULL; + + PHAL_GDMA_ADAPTER pHalI2CTxGdmaAdpt = NULL; + PHAL_GDMA_OP pHalI2CGdmaOp = NULL; + + u32 I2CLocalTemp = 0; + u32 I2CInTOTcnt = 0; + u32 InTimeoutCount = 0; + u32 InStartCount = 0; + u32 I2CChkRawSts = 0; + u32 I2CChkRawSts2 = 0; + u32 I2CDataLenBak = 0; + u32 I2CDataPtrBak = 0; + u32 I2CInTOTcntIntr = 0; + u32 InTimeoutCountIntr = 0; + u32 InStartCountIntr = 0; + + /* To Get the SAL_I2C_MNGT_ADPT Pointer */ + pSalI2CHNDPriv = CONTAINER_OF(pSalI2CHND, SAL_I2C_HND_PRIV, SalI2CHndPriv); + pSalI2CMngtAdpt = CONTAINER_OF(pSalI2CHNDPriv->ppSalI2CHnd, SAL_I2C_MNGT_ADPT, pSalHndPriv); + + + + pHalI2CInitDat = pSalI2CMngtAdpt->pHalInitDat; + + pHalI2COP = pSalI2CMngtAdpt->pHalOp; + + + pHalI2CTxGdmaAdpt = pSalI2CMngtAdpt->pHalTxGdmaAdp; + pHalI2CGdmaOp = pSalI2CMngtAdpt->pHalGdmaOp; + + /* Check if it's Master Mode */ + if (pSalI2CHND->I2CMaster == I2C_MASTER_MODE) { + //DBG_8195A("m\n"); + /* Master run-time update target address */ + if (pSalI2CHND->I2CExd & I2C_EXD_MTR_ADDR_UPD) { + + /* Calculate user time out parameters */ + I2CInTOTcnt = pSalI2CHND->TimeOut; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + + /* Check Master activity status */ + while ((pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS)) & BIT_IC_STATUS_MST_ACTIVITY) { + /* Time-Out check */ + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_ADD_TO; + DBG_I2C_ERR("RtkI2CSend Timeout, I2C%2x,1\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_ADD_TO; + DBG_I2C_ERR("RtkI2CSend Timeout, I2C%2x,2\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + } + /* Calculate user time out parameters */ + I2CInTOTcnt = pSalI2CHND->TimeOut; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + + /* Check TX FIFO status */ + while (!((pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS)) & BIT_IC_STATUS_TFE)) { + /* Time-Out check */ + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_ADD_TO; + DBG_I2C_ERR("RtkI2CSend Timeout, I2C%2x,3\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_ADD_TO; + DBG_I2C_ERR("RtkI2CSend Timeout, I2C%2x,4\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + } + + I2CLocalTemp = 0; + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_TAR); + I2CLocalTemp &= (~BIT_MASK_IC_TAR); + I2CLocalTemp |= BIT_CTRL_IC_TAR(pSalI2CHND->pTXBuf->TargetAddr); + /* Update Master Target address */ + pHalI2COP->HalI2CWriteReg(pHalI2CInitDat, REG_DW_I2C_IC_TAR, I2CLocalTemp); + } + + RtkI2CSendUserAddr(pSalI2CHND, 0); + + /* #if I2C_POLL_OP_TYPE */ + if (pSalI2CHND->OpType == I2C_POLL_TYPE) { /* if (pSalI2CHND->OpType == I2C_POLL_TYPE) */ + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_TX_READY; + + /* Calculate user time out parameters */ + I2CInTOTcnt = pSalI2CHND->TimeOut; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + + /* Send data till the TX buffer data length is zero */ + for (;pSalI2CHND->pTXBuf->DataLen>0;) { + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_TX_ING; + + /* Check I2C TX FIFO status */ + if ((pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_STATUS) + & (BIT_IC_STATUS_TFNF)) == BIT_IC_STATUS_TFNF) { + /* Wrtie data into I2C TX FIFO */ + pHalI2CInitDat->I2CCmd = I2C_WRITE_CMD; + pHalI2CInitDat->I2CDataLen= 1; + pHalI2CInitDat->I2CRWData = pSalI2CHND->pTXBuf->pDataBuf; + pHalI2CInitDat->I2CStop = I2C_STOP_DIS; + if ((pSalI2CHND->pTXBuf->DataLen == 1) && ((pSalI2CHND->I2CExd & I2C_EXD_MTR_HOLD_BUS) == 0)) + pHalI2CInitDat->I2CStop = I2C_STOP_EN; + pHalI2COP->HalI2CMassSend(pHalI2CInitDat); + + pSalI2CHND->pTXBuf->pDataBuf++; + pSalI2CHND->pTXBuf->DataLen--; + } + else { + /* Time-Out check */ + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_CMD_TO; + DBG_I2C_ERR("RtkI2CSend Timeout, I2C%2x,5\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_CMD_TO; + DBG_I2C_ERR("RtkI2CSend Timeout, I2C%2x,6\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + } + + if (pSalI2CHND->I2CExd & I2C_EXD_MTR_ADDR_RTY) { + HalDelayUs(((1000*30)/pHalI2CInitDat->I2CClk)); //the 10 is for ten bit time + + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_RAW_INTR_STAT) & + BIT_IC_RAW_INTR_STAT_TX_ABRT) { + pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_CLR_TX_ABRT); + pSalI2CHND->pTXBuf->pDataBuf--; + pSalI2CHND->pTXBuf->DataLen++; + } + } + } + + /* Calculate user time out parameters */ + I2CInTOTcnt = pSalI2CMngtAdpt->InnerTimeOut; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + /* I2C Wait TX FIFO Empty */ + while (1) { + if ((pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_STATUS) + & (BIT_IC_STATUS_TFE | BIT_IC_STATUS_TFNF)) == + (BIT_IC_STATUS_TFE | BIT_IC_STATUS_TFNF)){ + break; + } + else { + /* Time-Out check */ + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_FF_TO; + DBG_I2C_ERR("RtkI2CSend Timeout, I2C%2x,7\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_FF_TO; + DBG_I2C_ERR("RtkI2CSend Timeout, I2C%2x,8\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + } + } + + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_IDLE; + }/* if (pSalI2CHND->OpType == I2C_POLL_TYPE) */ + /* #if I2C_POLL_OP_TYPE */ + +#if I2C_INTR_OP_TYPE + if (pSalI2CHND->OpType == I2C_INTR_TYPE) { /* if (pSalI2CHND->OpType == I2C_INTR_TYPE) */ + /* Calculate user time out parameters */ + InTimeoutCount = 0; + InStartCount = 0; + I2CInTOTcnt = pSalI2CHND->TimeOut; + + InTimeoutCountIntr = 0; + InStartCountIntr = 0; + I2CInTOTcntIntr = pSalI2CHND->AddRtyTimeOut; + + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + + InTimeoutCountIntr = (I2CInTOTcntIntr*1000/TIMER_TICK_US); + InStartCountIntr = HalTimerOp.HalTimerReadCount(1); + + + I2CDataLenBak = (u32)(pSalI2CHND->pTXBuf->DataLen); + I2CDataPtrBak = (u32)(pSalI2CHND->pTXBuf->pDataBuf); + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_IDLE; + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_TX_ABRT; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + pHalI2COP->HalI2CClrAllIntr(pHalI2CInitDat); + + /* Send data till the TX buffer data length is zero */ + for (;;) { +SEND_I2C_WR_CMD_INTR: + + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_TX_ING; + + /* Check I2C TX FIFO status */ + /* Fill TX FIFO only when it's completely empty */ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS); + if ((I2CChkRawSts & BIT_IC_STATUS_TFE) == BIT_IC_STATUS_TFE) { + if (pSalI2CHND->pTXBuf->DataLen > 0) { + /* Wrtie data into I2C TX FIFO */ + pHalI2CInitDat->I2CCmd = I2C_WRITE_CMD; + pHalI2CInitDat->I2CDataLen= 1; + pHalI2CInitDat->I2CRWData = pSalI2CHND->pTXBuf->pDataBuf; + pHalI2CInitDat->I2CStop = I2C_STOP_DIS; + + if ((pSalI2CHND->pTXBuf->DataLen == 1) && ((pSalI2CHND->I2CExd & I2C_EXD_MTR_HOLD_BUS) == 0)) + pHalI2CInitDat->I2CStop = I2C_STOP_EN; + + pHalI2COP->HalI2CMassSend(pHalI2CInitDat); + + pSalI2CHND->pTXBuf->pDataBuf++; + pSalI2CHND->pTXBuf->DataLen--; + } + } + + if (pSalI2CHND->I2CExd & I2C_EXD_MTR_ADDR_RTY) { + u32 I2CInTOTcntRty = 0; + u32 InTimeoutCountRty = 0; + u32 InStartCountRty = 0; + + /* SEND_I2C_WR_CMD_INTR Time-Out check */ + if (InTimeoutCountIntr > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCountIntr, InTimeoutCountIntr)) { + /* Reset the data count before status return */ + pSalI2CHND->pTXBuf->pDataBuf--; + pSalI2CHND->pTXBuf->DataLen++; + return HAL_TIMEOUT; + } + } + + /* Calculate user master retry local time out parameters */ + InTimeoutCountRty = 0; + InStartCountRty = 0; + I2CInTOTcntRty = pSalI2CHND->TimeOut; + + if ((I2CInTOTcntRty != 0) && (I2CInTOTcntRty!= I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCountRty= (I2CInTOTcntRty*1000/TIMER_TICK_US); + InStartCountRty= HalTimerOp.HalTimerReadCount(1); + } + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS); + while ((I2CChkRawSts & BIT_IC_STATUS_TFE) == 0) { + I2CChkRawSts2 = pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_RAW_INTR_STAT); + if ((I2CChkRawSts2 & BIT_IC_RAW_INTR_STAT_TX_ABRT) != 0){ + break; + } + + /* Time-Out check */ + if (InTimeoutCountRty > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCountRty, InTimeoutCountRty)) { + break; + } + } + else { + if (I2CInTOTcntRty == 0) { + break; + } + } + + /* Read I2C IC status again */ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS); + } + + HalDelayUs((u32)((1000*30)/pHalI2CInitDat->I2CClk)); //the 10 is for ten bit time + + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_RAW_INTR_STAT); + if (I2CChkRawSts & BIT_IC_RAW_INTR_STAT_TX_ABRT) { + RtkI2CDeInitForPS(pSalI2CHND); + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) == BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + RtkI2CInitForPS(pSalI2CHND); + + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) != BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + + pSalI2CHND->DevSts = I2C_STS_TX_READY; + pSalI2CHND->ErrType = 0; + pSalI2CHND->pTXBuf->DataLen = (u16)I2CDataLenBak; + pSalI2CHND->pTXBuf->pDataBuf= (u8*)I2CDataPtrBak; + /* Calculate user time out parameters */ + InTimeoutCount = 0; + InStartCount = 0; + I2CInTOTcnt = pSalI2CHND->TimeOut; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + goto SEND_I2C_WR_CMD_INTR; + + } + else if (((u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS) & BIT_IC_STATUS_TFE) != BIT_IC_STATUS_TFE) { + { + RtkI2CDeInitForPS(pSalI2CHND); + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) == BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + RtkI2CInitForPS(pSalI2CHND); + + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) != BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + + pSalI2CHND->DevSts = I2C_STS_TX_READY; + pSalI2CHND->ErrType = 0; + pSalI2CHND->pTXBuf->DataLen = (u16)I2CDataLenBak; + pSalI2CHND->pTXBuf->pDataBuf= (u8 *)I2CDataPtrBak; + /* Calculate user time out parameters */ + InTimeoutCount = 0; + InStartCount = 0; + I2CInTOTcnt = pSalI2CHND->TimeOut; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + goto SEND_I2C_WR_CMD_INTR; + } + } + else { + /* I2C Enable TX Related Interrupts */ + I2CLocalTemp = 0; + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_INTR_MASK); + I2CLocalTemp |= (BIT_IC_INTR_MASK_M_TX_ABRT | + BIT_IC_INTR_MASK_M_TX_EMPTY | + BIT_IC_INTR_MASK_M_TX_OVER); + pHalI2CInitDat->I2CIntrMSK = I2CLocalTemp; + pHalI2COP->HalI2CIntrCtrl(pHalI2CInitDat); + + break; + } + } + else { + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS); + while ((I2CChkRawSts & BIT_IC_STATUS_TFE) == 0) { + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS); + } + + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS); + if (I2CChkRawSts & BIT_IC_STATUS_TFE) { + /* I2C Enable TX Related Interrupts */ + I2CLocalTemp = 0; + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_INTR_MASK); + I2CLocalTemp |= (BIT_IC_INTR_MASK_M_TX_ABRT | + BIT_IC_INTR_MASK_M_TX_EMPTY | + BIT_IC_INTR_MASK_M_TX_OVER); + pHalI2CInitDat->I2CIntrMSK = I2CLocalTemp; + pHalI2COP->HalI2CIntrCtrl(pHalI2CInitDat); + break; + } + } + + /* Time-Out check */ + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_FF_TO; + //DBG_I2C_ERR("RtkI2CSend Timeout, I2C%2x,7\n",pSalI2CHND->DevNum); + //DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + RtkI2CDeInitForPS(pSalI2CHND); + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) == BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + RtkI2CInitForPS(pSalI2CHND); + + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) != BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + return HAL_TIMEOUT; + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_FF_TO; + + RtkI2CDeInitForPS(pSalI2CHND); + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) == BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + RtkI2CInitForPS(pSalI2CHND); + + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) != BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + return HAL_TIMEOUT; + } + } + } + } /* if (pSalI2CHND->OpType == I2C_INTR_TYPE) */ +#endif + + /* if (pSalI2CHND->OpType == I2C_DMA_TYPE) */ + if (pSalI2CHND->OpType == I2C_DMA_TYPE) { + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_TX_READY; + + /* I2C Enable TX Related Interrupts */ + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_INTR_MASK); + I2CLocalTemp |= (BIT_IC_INTR_MASK_M_TX_ABRT | + BIT_IC_INTR_MASK_M_TX_OVER); + pHalI2CInitDat->I2CIntrMSK = I2CLocalTemp; + pHalI2COP->HalI2CIntrCtrl(pHalI2CInitDat); + + //HalGdmaOpInit(pHalI2CGdmaOp); + pSalI2CMngtAdpt->pHalGdmaOpInit(pHalI2CGdmaOp); + pHalI2CTxGdmaAdpt->GdmaCtl.BlockSize = pSalI2CHND->pTXBuf->DataLen; + pHalI2CTxGdmaAdpt->ChSar = (u32)pSalI2CHND->pTXBuf->pDataBuf; + pHalI2CTxGdmaAdpt->ChDar = (u32)(I2C0_REG_BASE+REG_DW_I2C_IC_DATA_CMD+ + pSalI2CHND->DevNum*0x400); + pHalI2CGdmaOp->HalGdmaChSeting(pHalI2CTxGdmaAdpt); + pHalI2CGdmaOp->HalGdmaChEn(pHalI2CTxGdmaAdpt); + pSalI2CHND->DevSts = I2C_STS_TX_ING; + pHalI2CInitDat->I2CDMACtrl = BIT_CTRL_IC_DMA_CR_TDMAE(1); + pHalI2COP->HalI2CDMACtrl(pHalI2CInitDat); + + } + /* if (pSalI2CHND->OpType == I2C_DMA_TYPE) */ + + }/* if (pSalI2CHND->I2CMaster == I2C_MASTER_MODE) */ + else{ + /* #if I2C_POLL_OP_TYPE */ + if (pSalI2CHND->OpType == I2C_POLL_TYPE) { + /* Calculate user time out parameters */ + I2CInTOTcnt = pSalI2CHND->TimeOut; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_TX_READY; + + /* Send data till the TX buffer data length is zero */ + for (;pSalI2CHND->pTXBuf->DataLen>0;) { + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_TX_ING; + + /* Check I2C RD Request flag */ + if ((pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_RAW_INTR_STAT)) + & BIT_IC_RAW_INTR_STAT_RD_REQ) { + + /* Check I2C TX FIFO status */ + if ((pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_STATUS) + & (BIT_IC_STATUS_TFNF)) == BIT_IC_STATUS_TFNF) { + pHalI2CInitDat->I2CDataLen= 1; + pHalI2CInitDat->I2CRWData = pSalI2CHND->pTXBuf->pDataBuf; + pHalI2COP->HalI2CMassSend(pHalI2CInitDat); + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_RD_REQ; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + pSalI2CHND->pTXBuf->pDataBuf++; + pSalI2CHND->pTXBuf->DataLen--; + } + } + else { + /* Time-Out check */ + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_FF_TO; + DBG_I2C_ERR("RtkI2CSend Timeout, I2C%2x,9\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_FF_TO; + DBG_I2C_ERR("RtkI2CSend Timeout, I2C%2x,10\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + } + } + + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_IDLE; + } + /* #if I2C_POLL_OP_TYPE */ + + /* #if I2C_INTR_OP_TYPE */ + if (pSalI2CHND->OpType == I2C_INTR_TYPE) { + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_IDLE; + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_TX_ABRT; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_TX_OVER; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_RD_REQ; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_ACTIVITY; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + pHalI2COP->HalI2CClrAllIntr(pHalI2CInitDat); + pSalI2CHND->DevSts = I2C_STS_TX_READY; + + /* I2C Enable TX Related Interrupts. In Slave-Transmitter, the below + interrupts should be enabled. */ + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_INTR_MASK); + I2CLocalTemp |= (BIT_IC_INTR_MASK_M_TX_ABRT | + BIT_IC_INTR_MASK_M_TX_OVER | + BIT_IC_INTR_MASK_M_RX_DONE | + BIT_IC_INTR_MASK_M_RD_REQ); + pHalI2CInitDat->I2CIntrMSK = I2CLocalTemp; + pHalI2COP->HalI2CIntrCtrl(pHalI2CInitDat); + } + /* #if I2C_INTR_OP_TYPE */ + + /* #if I2C_DMA_OP_TYPE */ + ; + /* #if I2C_DMA_OP_TYPE */ + } + + return HAL_OK; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CReceive +// +// Description: +// To execute Master-Receiver and Slave-Receiver operation. +// There are 3 operation mode in this function which are separated by compile-time +// flag. +// For Master-Receiver, the User Register Address flag is checked first. +// User Register Address may be sent before any formal transfer, no matter in +// Poll-, Intr- or DMA- Mode. +// +// For Master-Receiver, the I2C master have to send a Read Command for receiving +// one byte from the other I2C slave. +// +// In Poll-Mode, no matter it's master or slave mode, the transfer will be done in +// this function by checking the transfer length. +// -Master in Poll-Mode: +// a. Send the User Register Address if needed. +// b. Check if all the data are received. If it's NOT, checking the TX FIFO +// status will be done. If the TX FIFO it's full, a Read Command will be +// wirtten into the TX FIFO. +// c. After b, the I2C master contineously polls the RX FIFO status to see +// if there is a received data. If it received one, it will move the data from +// I2C RX FIFO into user RX data buffer. +// d. b and c are executed circularly till the RX buffer data length is zero. +// +// -Slave in Poll-Mode: +// a. Check if all the data are received. +// b. The I2C slave contineously polls the RX FIFO status to see +// if there is a received data. If it received one, it will move the data from +// I2C RX FIFO into user RX data buffer. +// c. a and b are executed circularly till the RX buffer data length is zero. +// +//---------------------------------------------------------------------- +// In Intr-Mode, this function is used to unmask the realted I2C interrupt for +// the following interrupt operations. +// -Master in Intr-Mode: +// a. Send the User Register Address if needed. +// b. Unmask the RX-Full and realted error interrupts. +// c. Write one or two Read Command into master TX FIFO for requesting +// another slave providing data. +// +// -Slave in Intr-Mode: +// a. Unmask the RX-Full and realted error interrupts. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C receive process. +// _EXIT_SUCCESS if the RtkI2CReceive succeeded. +// _EXIT_FAILURE if the RtkI2CReceive failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +HAL_Status +RtkI2CReceive_Patch( + IN VOID *Data +){ + PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data; + PSAL_I2C_HND_PRIV pSalI2CHNDPriv = NULL; + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PHAL_I2C_INIT_DAT pHalI2CInitDat = NULL; + PHAL_I2C_OP pHalI2COP = NULL; +#if I2C_DMA_OP_TYPE + PHAL_GDMA_ADAPTER pHalI2CRxGdmaAdpt = NULL; + PHAL_GDMA_OP pHalI2CGdmaOp = NULL; +#endif + + u32 I2CLocalTemp = 0; + u32 I2CInTOTcnt = 0; + u32 InTimeoutCount = 0; + u32 InStartCount = 0; + u32 I2CLocalLen = 0; + u32 I2CChkRawSts = 0; + u32 I2CChkRawSts2 = 0; + u32 I2CDataLenBak = 0; + u32 I2CDataPtrBak = 0; + u32 I2CInTOTcntRty = 0; + u32 InTimeoutCountRty = 0; + u32 InStartCountRty = 0; + u32 I2CInTOTcntIntr = 0; + u32 InTimeoutCountIntr = 0; + u32 InStartCountIntr = 0; + + /*To Get the SAL_I2C_MNGT_ADPT Pointer*/ + pSalI2CHNDPriv = CONTAINER_OF(pSalI2CHND, SAL_I2C_HND_PRIV, SalI2CHndPriv); + pSalI2CMngtAdpt = CONTAINER_OF(pSalI2CHNDPriv->ppSalI2CHnd, SAL_I2C_MNGT_ADPT, pSalHndPriv); + pHalI2CInitDat = pSalI2CMngtAdpt->pHalInitDat; + pHalI2COP = pSalI2CMngtAdpt->pHalOp; +#if I2C_DMA_OP_TYPE + pHalI2CRxGdmaAdpt = pSalI2CMngtAdpt->pHalRxGdmaAdp; + pHalI2CGdmaOp = pSalI2CMngtAdpt->pHalGdmaOp; +#endif + + if (pSalI2CHND->I2CMaster == I2C_MASTER_MODE)/*if (pSalI2CHND->I2CMaster == I2C_MASTER_MODE)*/ + { + /* Master run-time update target address */ + if (pSalI2CHND->I2CExd & I2C_EXD_MTR_ADDR_UPD) { + /* Calculate user time out parameters */ + I2CInTOTcnt = pSalI2CHND->TimeOut; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + + /* Check Master activity status */ + while ((pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS)) & BIT_IC_STATUS_MST_ACTIVITY) { + pHalI2COP->HalI2CClrAllIntr(pHalI2CInitDat); + //DBG_8195A("~\n"); + /* Time-Out check */ + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO; + DBG_I2C_ERR("RtkI2CReceive Timeout, I2C%2x,1\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO; + DBG_I2C_ERR("RtkI2CReceive Timeout, I2C%2x,2\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + } + + /* Calculate user time out parameters */ + I2CInTOTcnt = pSalI2CHND->TimeOut; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + + /* Check TX FIFO status */ + while (!((pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS)) & BIT_IC_STATUS_TFE)) { + /* Time-Out check */ + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO; + DBG_I2C_ERR("RtkI2CReceive Timeout, I2C%2x,3\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_RX_ADD_TO; + DBG_I2C_ERR("RtkI2CReceive Timeout, I2C%2x,4\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + } + + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_TAR); + I2CLocalTemp &= (~BIT_MASK_IC_TAR); + I2CLocalTemp |= BIT_CTRL_IC_TAR(pSalI2CHND->pRXBuf->TargetAddr); + /* Update Master Target address */ + pHalI2COP->HalI2CWriteReg(pHalI2CInitDat, REG_DW_I2C_IC_TAR, I2CLocalTemp); + } + + +#if I2C_USER_REG_ADDR /*I2C_USER_REG_ADDR*/ + RtkI2CSendUserAddr(pSalI2CHND, 1); +#endif /*I2C_USER_REG_ADDR*/ + +#if I2C_POLL_OP_TYPE/*I2C_POLL_OP_TYPE*/ + if (pSalI2CHND->OpType == I2C_POLL_TYPE) + { + //DBG_8195A("p\n"); + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_RX_READY; + + pSalI2CMngtAdpt->MstRDCmdCnt = pSalI2CHND->pRXBuf->DataLen; + I2CLocalTemp = pSalI2CHND->pRXBuf->DataLen; + + /* Calculate user time out parameters */ + I2CInTOTcnt = pSalI2CHND->TimeOut; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + + /* Receive data till the RX buffer data length is zero */ + for ( ;pSalI2CHND->pRXBuf->DataLen>0; ) { +SEND_I2C_RD_CMD: + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_RX_ING; + /* Check I2C TX FIFO status. If it's NOT full, a Read command is written + into the TX FIFO.*/ + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS) + & BIT_IC_STATUS_TFNF) { + if (pSalI2CMngtAdpt->MstRDCmdCnt > 0) { + pHalI2CInitDat->I2CCmd = I2C_READ_CMD; + pHalI2CInitDat->I2CDataLen= 1; + pHalI2CInitDat->I2CRWData = pSalI2CHND->pRXBuf->pDataBuf; + pHalI2CInitDat->I2CStop = I2C_STOP_DIS; + if ((pSalI2CMngtAdpt->MstRDCmdCnt == 1) && ((pSalI2CHND->I2CExd & I2C_EXD_MTR_HOLD_BUS) == 0)){ + pHalI2CInitDat->I2CStop = I2C_STOP_EN; + } + pHalI2COP->HalI2CMassSend(pHalI2CInitDat); + if (pSalI2CMngtAdpt->MstRDCmdCnt > 0) + pSalI2CMngtAdpt->MstRDCmdCnt--; + } + } + + if (I2CLocalTemp == pSalI2CHND->pRXBuf->DataLen){ + if (pSalI2CHND->I2CExd & I2C_EXD_MTR_ADDR_RTY) { + HalDelayUs(((1000*30)/pHalI2CInitDat->I2CClk)); //the 10 is for ten bit time + if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_RAW_INTR_STAT) & + BIT_IC_RAW_INTR_STAT_TX_ABRT) { + pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_CLR_TX_ABRT); + pSalI2CMngtAdpt->MstRDCmdCnt++; + goto SEND_I2C_RD_CMD; + } + } + } + + /* Contineously poll the I2C RX FIFO status */ + while (1) { + if ((pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS) + & (BIT_IC_STATUS_RFNE | BIT_IC_STATUS_RFF)) != 0) { + *(pSalI2CHND->pRXBuf->pDataBuf) = + pHalI2COP->HalI2CReceive(pHalI2CInitDat); + + pSalI2CHND->pRXBuf->pDataBuf++; + pSalI2CHND->pRXBuf->DataLen--; + + if (!pSalI2CHND->pRXBuf->DataLen) { + break; + } + } + else { + break; + } + } + + /* Time-Out check */ + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_RX_FF_TO; + DBG_I2C_ERR("RtkI2CReceive Timeout, I2C%2x,5\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_RX_FF_TO; + DBG_I2C_ERR("RtkI2CReceive Timeout, I2C%2x,6\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + + } + + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_IDLE; + } +#endif/*I2C_POLL_OP_TYPE*/ + +#if I2C_INTR_OP_TYPE/*I2C_INTR_OP_TYPE*/ + if (pSalI2CHND->OpType == I2C_INTR_TYPE) { + /* Calculate user time out parameters */ + InTimeoutCount= 0; + InStartCount = 0; + I2CInTOTcnt = pSalI2CMngtAdpt->InnerTimeOut; + + InTimeoutCountIntr = 0; + InStartCountIntr = 0; + I2CInTOTcntIntr = pSalI2CHND->AddRtyTimeOut; + + if ((I2CInTOTcnt!= 0) && (I2CInTOTcnt!= I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount= HalTimerOp.HalTimerReadCount(1); + } + + InTimeoutCountIntr = (I2CInTOTcntIntr*1000/TIMER_TICK_US); + InStartCountIntr = HalTimerOp.HalTimerReadCount(1); + + I2CDataLenBak = (u32)(pSalI2CHND->pRXBuf->DataLen); + I2CDataPtrBak = (u32)(pSalI2CHND->pRXBuf->pDataBuf); + + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_RX_READY; + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_TX_ABRT; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_ACTIVITY; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + pHalI2COP->HalI2CClrAllIntr(pHalI2CInitDat); + + /* Clear RX FIFO */ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_RXFLR); + while (I2CChkRawSts > 0){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_RXFLR); + } + + /* To fill the Master Read Command into TX FIFO */ + pSalI2CMngtAdpt->MstRDCmdCnt = pSalI2CHND->pRXBuf->DataLen; + I2CLocalLen = 2;//pSalI2CHND->pRXBuf->DataLen; + pSalI2CHND->DevSts = I2C_STS_RX_READY; + + + while (1) { +SEND_I2C_RD_CMD_INTR: + + /* Calculate user time out parameters */ + InTimeoutCountRty = 0; + InStartCountRty = 0; + I2CInTOTcntRty = pSalI2CHND->TimeOut; + + if ((I2CInTOTcntRty != 0) && (I2CInTOTcntRty!= I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCountRty= (I2CInTOTcntRty*1000/TIMER_TICK_US); + InStartCountRty= HalTimerOp.HalTimerReadCount(1); + } + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS); + + if ((pSalI2CMngtAdpt->MstRDCmdCnt > 0) && (I2CLocalLen > 0)){ + pHalI2CInitDat->I2CCmd = I2C_READ_CMD; + pHalI2CInitDat->I2CDataLen= 1; + pHalI2CInitDat->I2CRWData = pSalI2CHND->pRXBuf->pDataBuf; + pHalI2CInitDat->I2CStop = I2C_STOP_DIS; + + if ((pSalI2CMngtAdpt->MstRDCmdCnt == 1) && ((pSalI2CHND->I2CExd & I2C_EXD_MTR_HOLD_BUS) == 0)){ + pHalI2CInitDat->I2CStop = I2C_STOP_EN; + } + + pHalI2COP->HalI2CMassSend(pHalI2CInitDat); + } + + if (pSalI2CHND->I2CExd & I2C_EXD_MTR_ADDR_RTY) { + + /* SEND_I2C_WR_CMD_INTR Time-Out check */ + if (InTimeoutCountIntr > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCountIntr, InTimeoutCountIntr)) { + return HAL_TIMEOUT; + } + } + + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS); + while ((I2CChkRawSts & BIT_IC_STATUS_TFE) == 0) { + I2CChkRawSts2 = pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_RAW_INTR_STAT); + if ((I2CChkRawSts2 & BIT_IC_RAW_INTR_STAT_TX_ABRT) != 0){ + break; + } + + /* Time-Out check */ + if (InTimeoutCountRty > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCountRty, InTimeoutCountRty)) { + break; + } + } + else { + if (I2CInTOTcntRty == 0) { + break; + } + } + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS); + + } + + HalDelayUs(((1000*30)/pHalI2CInitDat->I2CClk)); //the 10 is for ten bit time + + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_RAW_INTR_STAT); + I2CChkRawSts2 = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS); + if (I2CChkRawSts & BIT_IC_RAW_INTR_STAT_TX_ABRT) { + + RtkI2CDeInitForPS(pSalI2CHND); + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) == BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + RtkI2CInitForPS(pSalI2CHND); + + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) != BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + pSalI2CHND->DevSts = I2C_STS_RX_READY; + pSalI2CHND->ErrType = 0; + pSalI2CHND->pRXBuf->DataLen = (u16)I2CDataLenBak; + pSalI2CHND->pRXBuf->pDataBuf= (u8 *)I2CDataPtrBak; + + /* Calculate user time out parameters */ + InTimeoutCount = 0; + InStartCount = 0; + I2CInTOTcnt = pSalI2CMngtAdpt->InnerTimeOut; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + goto SEND_I2C_RD_CMD_INTR; + } + else if ((I2CChkRawSts2 & BIT_IC_STATUS_TFE) != BIT_IC_STATUS_TFE){ + RtkI2CDeInitForPS(pSalI2CHND); + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) == BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + RtkI2CInitForPS(pSalI2CHND); + + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) != BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + pSalI2CHND->DevSts = I2C_STS_RX_READY; + pSalI2CHND->ErrType = 0; + pSalI2CHND->pRXBuf->DataLen = (u16)I2CDataLenBak; + pSalI2CHND->pRXBuf->pDataBuf= (u8 *)I2CDataPtrBak; + + /* Calculate user time out parameters */ + InTimeoutCount = 0; + InStartCount = 0; + I2CInTOTcnt = pSalI2CMngtAdpt->InnerTimeOut; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + goto SEND_I2C_RD_CMD_INTR; + } + else { + I2CChkRawSts2 = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS); + { + if (I2CLocalLen>0){ + I2CLocalLen--; + pSalI2CMngtAdpt->MstRDCmdCnt --; + } + } + } + } + else { + if (I2CLocalLen>0) { + I2CLocalLen--; + pSalI2CMngtAdpt->MstRDCmdCnt --; + } + } + + if ((I2CLocalLen == 0) || (pSalI2CHND->pRXBuf->DataLen == 1)){ + pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_TX_ABRT; + pHalI2COP->HalI2CClrIntr(pHalI2CInitDat); + I2CLocalTemp = 0; + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_INTR_MASK); + I2CLocalTemp |= (BIT_IC_INTR_MASK_M_RX_FULL | + BIT_IC_INTR_MASK_M_RX_OVER | + BIT_IC_INTR_MASK_M_RX_UNDER|BIT_IC_INTR_MASK_M_TX_ABRT); + pHalI2CInitDat->I2CIntrMSK = I2CLocalTemp; + pHalI2COP->HalI2CIntrCtrl(pHalI2CInitDat); + break; + } + + /* Time-Out check */ + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_FF_TO; + + RtkI2CDeInitForPS(pSalI2CHND); + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) == BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + RtkI2CInitForPS(pSalI2CHND); + + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) != BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + return HAL_TIMEOUT; + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_TX_FF_TO; + + RtkI2CDeInitForPS(pSalI2CHND); + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) == BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + RtkI2CInitForPS(pSalI2CHND); + + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + while((I2CChkRawSts & BIT_IC_ENABLE_STATUS_IC_EN) != BIT_IC_ENABLE_STATUS_IC_EN){ + I2CChkRawSts = (u32)pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_ENABLE_STATUS); + } + return HAL_TIMEOUT; + } + } + } + + } +#endif/*I2C_INTR_OP_TYPE*/ + }/*if (pSalI2CHND->I2CMaster == I2C_MASTER_MODE)*/ + else + { +#if I2C_POLL_OP_TYPE + if (pSalI2CHND->OpType == I2C_POLL_TYPE) { + /* Calculate user time out parameters */ + I2CInTOTcnt = pSalI2CHND->TimeOut; + if ((I2CInTOTcnt != 0) && (I2CInTOTcnt != I2C_TIMEOOUT_ENDLESS)) { + InTimeoutCount = (I2CInTOTcnt*1000/TIMER_TICK_US); + InStartCount = HalTimerOp.HalTimerReadCount(1); + } + + /* Receive data till the RX buffer data length is zero */ + for (;pSalI2CHND->pRXBuf->DataLen>0; ) { + if ((pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_STATUS) + & (BIT_IC_STATUS_RFNE | BIT_IC_STATUS_RFF)) != 0) { + *(pSalI2CHND->pRXBuf->pDataBuf) = + pHalI2COP->HalI2CReceive(pHalI2CInitDat); + pSalI2CHND->pRXBuf->pDataBuf++; + pSalI2CHND->pRXBuf->DataLen--; + } + else { + /* Time-Out check */ + if (InTimeoutCount > 0) { + if (HAL_TIMEOUT == I2CIsTimeout(InStartCount, InTimeoutCount)) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_RX_FF_TO; + DBG_I2C_ERR("RtkI2CReceive Timeout, I2C%2x,9\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + else { + if (I2CInTOTcnt == 0) { + pSalI2CHND->DevSts = I2C_STS_TIMEOUT; + pSalI2CHND->ErrType = I2C_ERR_RX_FF_TO; + DBG_I2C_ERR("RtkI2CReceive Timeout, I2C%2x,10\n",pSalI2CHND->DevNum); + DBG_I2C_ERR("DevSts:%x, ErrType:%x\n", pSalI2CHND->DevSts, pSalI2CHND->ErrType); + return HAL_TIMEOUT; + } + } + } + } + + /* I2C Device Status Update */ + pSalI2CHND->DevSts = I2C_STS_IDLE; + } +#endif + +#if I2C_INTR_OP_TYPE/*I2C_INTR_OP_TYPE*/ + if (pSalI2CHND->OpType == I2C_INTR_TYPE) { + pSalI2CHND->DevSts = I2C_STS_RX_READY; + + /*I2C Enable RX Related Interrupts*/ + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_INTR_MASK); + I2CLocalTemp |= (BIT_IC_INTR_MASK_M_RX_FULL | + BIT_IC_INTR_MASK_M_RX_OVER | + BIT_IC_INTR_MASK_M_RX_UNDER); + pHalI2CInitDat->I2CIntrMSK = I2CLocalTemp; + pHalI2COP->HalI2CIntrCtrl(pHalI2CInitDat); + } +#endif/*I2C_INTR_OP_TYPE*/ + +#if I2C_DMA_OP_TYPE/*I2C_INTR_OP_TYPE*/ + if (pSalI2CHND->OpType == I2C_DMA_TYPE) { + pSalI2CHND->DevSts = I2C_STS_RX_READY; + + /*I2C Enable RX Related Interrupts*/ + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_INTR_MASK); + I2CLocalTemp |= (BIT_IC_INTR_MASK_M_RX_OVER | + BIT_IC_INTR_MASK_M_RX_UNDER); + pHalI2CInitDat->I2CIntrMSK = I2CLocalTemp; + pHalI2COP->HalI2CIntrCtrl(pHalI2CInitDat); + + //HalGdmaOpInit(pHalI2CGdmaOp); + pSalI2CMngtAdpt->pHalGdmaOpInit(pHalI2CGdmaOp); + + pHalI2CRxGdmaAdpt->GdmaCtl.BlockSize = pSalI2CHND->pRXBuf->DataLen; + pHalI2CRxGdmaAdpt->ChSar = (u32)(I2C0_REG_BASE+REG_DW_I2C_IC_DATA_CMD+ + pSalI2CHND->DevNum*0x400); + pHalI2CRxGdmaAdpt->ChDar = (u32)pSalI2CHND->pRXBuf->pDataBuf; + + pHalI2CGdmaOp->HalGdmaChSeting(pHalI2CRxGdmaAdpt); + pHalI2CGdmaOp->HalGdmaChEn(pHalI2CRxGdmaAdpt); + pSalI2CHND->DevSts = I2C_STS_RX_ING; + pHalI2CInitDat->I2CDMACtrl = BIT_CTRL_IC_DMA_CR_RDMAE(1); + pHalI2COP->HalI2CDMACtrl(pHalI2CInitDat); + } +#endif/*I2C_INTR_OP_TYPE*/ + + } + + return HAL_OK; +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CInitForPS +// +// Description: +// Add power state registeration for I2C initail process. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C initialization process. +// HAL_OK if the RtkI2CInitForPS succeeded. +// HAL_ERR_UNKNOWN if the RtkI2CInitForPS failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2015-05-31. +// +//---------------------------------------------------------------------------------------------------- +HAL_Status +RtkI2CInitForPS( + IN VOID *Data +){ + + u8 i2cInitSts = HAL_OK; + PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE i2cPwrState; +#endif + + i2cInitSts = RtkI2CInit(pSalI2CHND); + +#ifdef CONFIG_SOC_PS_MODULE + // To register a new peripheral device power state + if (i2cInitSts == HAL_OK){ + i2cPwrState.FuncIdx = I2C0 + pSalI2CHND->DevNum; + i2cPwrState.PwrState = ACT; + RegPowerState(i2cPwrState); + } +#endif + + return i2cInitSts; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CDeInitForPS +// +// Description: +// Add power state registeration for I2C deinitail process. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C deinitialization process. +// HAL_OK if the RtkI2CDeInitForPS succeeded. +// HAL_ERR_UNKNOWN if the RtkI2CDeInitForPS failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2015-05-31. +// +//---------------------------------------------------------------------------------------------------- +HAL_Status +RtkI2CDeInitForPS( + IN VOID *Data +){ + u8 i2cInitSts = HAL_OK; + PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE i2cPwrState; + u8 HwState; +#endif + + if (pSalI2CHND == NULL) + return HAL_ERR_UNKNOWN; + + /* Check the input I2C index first */ + if (RtkI2CIdxChk(pSalI2CHND->DevNum)) + return HAL_ERR_UNKNOWN; + +#ifdef CONFIG_SOC_PS_MODULE + i2cPwrState.FuncIdx = I2C0 + pSalI2CHND->DevNum; + + QueryRegPwrState(i2cPwrState.FuncIdx, &(i2cPwrState.PwrState), &HwState); + + // if the power state isn't ACT, then switch the power state back to ACT first + if ((i2cPwrState.PwrState != ACT) && (i2cPwrState.PwrState != INACT)) { + RtkI2CEnablePS(Data); + QueryRegPwrState(i2cPwrState.FuncIdx, &(i2cPwrState.PwrState), &HwState); + } + + if (i2cPwrState.PwrState == ACT) { + i2cPwrState.PwrState = INACT; + RegPowerState(i2cPwrState); + } +#endif + + i2cInitSts = RtkI2CDeInit(pSalI2CHND); + + return i2cInitSts; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CDisablePS +// +// Description: +// I2C disable opertion by setting clock disable. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C disable process. +// HAL_OK if the RtkI2CDisablePS succeeded. +// HAL_ERR_PARA if the RtkI2CDisablePS failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2015-05-31. +// +//---------------------------------------------------------------------------------------------------- +HAL_Status +RtkI2CDisablePS( + IN VOID *Data +){ + + PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data; + u8 i2cIdx = pSalI2CHND->DevNum; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE i2cPwrState; +#endif + + if (RtkI2CIdxChk(i2cIdx)) + return HAL_ERR_UNKNOWN; + + switch (i2cIdx) { + case 0: + { + /* I2C 0 */ + ACTCK_I2C0_CCTRL(OFF); + SLPCK_I2C0_CCTRL(OFF); + break; + } + case 1: + { + /* I2C 1 */ + ACTCK_I2C1_CCTRL(OFF); + SLPCK_I2C1_CCTRL(OFF); + break; + } + case 2: + { + /* I2C 2 */ + ACTCK_I2C2_CCTRL(OFF); + SLPCK_I2C2_CCTRL(OFF); + break; + } + case 3: + { + /* I2C 3 */ + ACTCK_I2C3_CCTRL(OFF); + SLPCK_I2C3_CCTRL(OFF); + break; + } + default: + { + return HAL_ERR_PARA; + } + } + +#ifdef CONFIG_SOC_PS_MODULE + // To register a new peripheral device power state + i2cPwrState.FuncIdx = I2C0 + pSalI2CHND->DevNum; + i2cPwrState.PwrState = SLPCG; + RegPowerState(i2cPwrState); +#endif + + return HAL_OK; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CEnablePS +// +// Description: +// I2C enable opertion by setting clock enable. +// +// Arguments: +// [in] VOID *Data - +// I2C SAL handle +// +// Return: +// The status of the I2C enable process. +// HAL_OK if the RtkI2CEnablePS succeeded. +// HAL_ERR_PARA if the RtkI2CEnablePS failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2015-05-31. +// +//---------------------------------------------------------------------------------------------------- +HAL_Status +RtkI2CEnablePS( + IN VOID *Data +){ + + PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data; + u8 i2cIdx = pSalI2CHND->DevNum; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE i2cPwrState; +#endif + + if (RtkI2CIdxChk(i2cIdx)) + return HAL_ERR_UNKNOWN; + + switch (i2cIdx) { + case 0: + { + /* I2C 0 */ + ACTCK_I2C0_CCTRL(ON); + SLPCK_I2C0_CCTRL(ON); + break; + } + case 1: + { + /* I2C 1 */ + ACTCK_I2C1_CCTRL(ON); + SLPCK_I2C1_CCTRL(ON); + break; + } + case 2: + { + /* I2C 2 */ + ACTCK_I2C2_CCTRL(ON); + SLPCK_I2C2_CCTRL(ON); + break; + } + case 3: + { + /* I2C 3 */ + ACTCK_I2C3_CCTRL(ON); + SLPCK_I2C3_CCTRL(ON); + break; + } + default: + { + return HAL_ERR_PARA; + } + } + +#ifdef CONFIG_SOC_PS_MODULE + // To register a new peripheral device power state + i2cPwrState.FuncIdx = I2C0 + pSalI2CHND->DevNum; + i2cPwrState.PwrState = ACT; + RegPowerState(i2cPwrState); +#endif + + return HAL_OK; +} +#endif + +#ifndef CONFIG_MBED_ENABLED +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CGetMngtAdpt +// +// Description: +// According to the input index, all the memory space are allocated and all the +// related pointers are assigned. The management adapter pointer will be +// returned. +// +// Arguments: +// [in] u8 I2CIdx - +// I2C module index +// +// Return: +// PSAL_I2C_MNGT_ADPT +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//--------------------------------------------------------------------------------------------------- +PSAL_I2C_MNGT_ADPT +RtkI2CGetMngtAdpt( + IN u8 I2CIdx +){ + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_USERCB_ADPT pSalI2CUserCBAdpt = NULL; + + /* If the kernel is available, Memory-allocation is used. */ +#ifdef I2C_STATIC_ALLOC + + pSalI2CMngtAdpt = (PSAL_I2C_MNGT_ADPT)RtlZmalloc(sizeof(SAL_I2C_MNGT_ADPT)); + pSalI2CMngtAdpt->pSalHndPriv = (PSAL_I2C_HND_PRIV)RtlZmalloc(sizeof(SAL_I2C_HND_PRIV)); + pSalI2CMngtAdpt->pHalInitDat = (PHAL_I2C_INIT_DAT)RtlZmalloc(sizeof(HAL_I2C_INIT_DAT)); + pSalI2CMngtAdpt->pHalOp = (PHAL_I2C_OP)RtlZmalloc(sizeof(HAL_I2C_OP)); + pSalI2CMngtAdpt->pIrqHnd = (PIRQ_HANDLE)RtlZmalloc(sizeof(IRQ_HANDLE)); + pSalI2CMngtAdpt->pHalTxGdmaAdp = (PHAL_GDMA_ADAPTER)RtlZmalloc(sizeof(HAL_GDMA_ADAPTER)); + pSalI2CMngtAdpt->pHalRxGdmaAdp = (PHAL_GDMA_ADAPTER)RtlZmalloc(sizeof(HAL_GDMA_ADAPTER)); + pSalI2CMngtAdpt->pHalGdmaOp = (PHAL_GDMA_OP)RtlZmalloc(sizeof(HAL_GDMA_OP)); + pSalI2CMngtAdpt->pIrqTxGdmaHnd = (PIRQ_HANDLE)RtlZmalloc(sizeof(IRQ_HANDLE)); + pSalI2CMngtAdpt->pIrqRxGdmaHnd = (PIRQ_HANDLE)RtlZmalloc(sizeof(IRQ_HANDLE)); + pSalI2CMngtAdpt->pUserCB = (PSAL_I2C_USER_CB)RtlZmalloc(sizeof(SAL_I2C_USER_CB)); + pSalI2CMngtAdpt->pDMAConf = (PSAL_I2C_DMA_USER_DEF)RtlZmalloc(sizeof(SAL_I2C_DMA_USER_DEF)); + pSalI2CUserCBAdpt = (PSAL_I2C_USERCB_ADPT)RtlZmalloc((sizeof(SAL_I2C_USERCB_ADPT)*SAL_USER_CB_NUM)); +#else + switch (I2CIdx){ + case I2C0_SEL: + { + pSalI2CMngtAdpt = &SalI2C0MngtAdpt; + pSalI2CMngtAdpt->pSalHndPriv = &SalI2C0HndPriv; + pSalI2CMngtAdpt->pHalInitDat = &HalI2C0InitData; + pSalI2CMngtAdpt->pHalOp = &HalI2COpSAL; + pSalI2CMngtAdpt->pIrqHnd = &I2C0IrqHandleDat; + pSalI2CMngtAdpt->pHalTxGdmaAdp = &HalI2C0TxGdmaAdpt; + pSalI2CMngtAdpt->pHalRxGdmaAdp = &HalI2C0RxGdmaAdpt; + pSalI2CMngtAdpt->pHalGdmaOp = &HalI2C0GdmaOp; + pSalI2CMngtAdpt->pIrqTxGdmaHnd = &I2C0TxGdmaIrqHandleDat; + pSalI2CMngtAdpt->pIrqRxGdmaHnd = &I2C0RxGdmaIrqHandleDat; + pSalI2CMngtAdpt->pUserCB = &SalI2C0UserCB; + pSalI2CMngtAdpt->pDMAConf = &SalI2C0DmaUserDef; + pSalI2CUserCBAdpt = (PSAL_I2C_USERCB_ADPT)&SalI2C0UserCBAdpt; + break; + } + + case I2C1_SEL: + { + pSalI2CMngtAdpt = &SalI2C1MngtAdpt; + pSalI2CMngtAdpt->pSalHndPriv = &SalI2C1HndPriv; + pSalI2CMngtAdpt->pHalInitDat = &HalI2C1InitData; + pSalI2CMngtAdpt->pHalOp = &HalI2COpSAL; + pSalI2CMngtAdpt->pIrqHnd = &I2C1IrqHandleDat; + pSalI2CMngtAdpt->pHalTxGdmaAdp = &HalI2C1TxGdmaAdpt; + pSalI2CMngtAdpt->pHalRxGdmaAdp = &HalI2C1RxGdmaAdpt; + pSalI2CMngtAdpt->pHalGdmaOp = &HalI2C1GdmaOp; + pSalI2CMngtAdpt->pIrqTxGdmaHnd = &I2C1TxGdmaIrqHandleDat; + pSalI2CMngtAdpt->pIrqRxGdmaHnd = &I2C1RxGdmaIrqHandleDat; + pSalI2CMngtAdpt->pUserCB = &SalI2C1UserCB; + pSalI2CMngtAdpt->pDMAConf = &SalI2C1DmaUserDef; + pSalI2CUserCBAdpt = (PSAL_I2C_USERCB_ADPT)&SalI2C1UserCBAdpt; + break; + } + + case I2C2_SEL: + { + pSalI2CMngtAdpt = &SalI2C2MngtAdpt; + pSalI2CMngtAdpt->pSalHndPriv = &SalI2C2HndPriv; + pSalI2CMngtAdpt->pHalInitDat = &HalI2C2InitData; + pSalI2CMngtAdpt->pHalOp = &HalI2COpSAL; + pSalI2CMngtAdpt->pIrqHnd = &I2C2IrqHandleDat; + pSalI2CMngtAdpt->pHalTxGdmaAdp = &HalI2C2TxGdmaAdpt; + pSalI2CMngtAdpt->pHalRxGdmaAdp = &HalI2C2RxGdmaAdpt; + pSalI2CMngtAdpt->pHalGdmaOp = &HalI2C2GdmaOp; + pSalI2CMngtAdpt->pIrqTxGdmaHnd = &I2C2TxGdmaIrqHandleDat; + pSalI2CMngtAdpt->pIrqRxGdmaHnd = &I2C2RxGdmaIrqHandleDat; + pSalI2CMngtAdpt->pUserCB = &SalI2C2UserCB; + pSalI2CMngtAdpt->pDMAConf = &SalI2C2DmaUserDef; + pSalI2CUserCBAdpt = (PSAL_I2C_USERCB_ADPT)&SalI2C2UserCBAdpt; + break; + } + + case I2C3_SEL: + { + pSalI2CMngtAdpt = &SalI2C3MngtAdpt; + pSalI2CMngtAdpt->pSalHndPriv = &SalI2C3HndPriv; + pSalI2CMngtAdpt->pHalInitDat = &HalI2C3InitData; + pSalI2CMngtAdpt->pHalOp = &HalI2COpSAL; + pSalI2CMngtAdpt->pIrqHnd = &I2C3IrqHandleDat; + pSalI2CMngtAdpt->pHalTxGdmaAdp = &HalI2C3TxGdmaAdpt; + pSalI2CMngtAdpt->pHalRxGdmaAdp = &HalI2C3RxGdmaAdpt; + pSalI2CMngtAdpt->pHalGdmaOp = &HalI2C3GdmaOp; + pSalI2CMngtAdpt->pIrqTxGdmaHnd = &I2C3TxGdmaIrqHandleDat; + pSalI2CMngtAdpt->pIrqRxGdmaHnd = &I2C3RxGdmaIrqHandleDat; + pSalI2CMngtAdpt->pUserCB = &SalI2C3UserCB; + pSalI2CMngtAdpt->pDMAConf = &SalI2C3DmaUserDef; + pSalI2CUserCBAdpt = (PSAL_I2C_USERCB_ADPT)&SalI2C3UserCBAdpt; + break; + } + + default + break; + } +#endif + + /*To assign user callback pointers*/ + pSalI2CMngtAdpt->pUserCB->pTXCB = pSalI2CUserCBAdpt; + pSalI2CMngtAdpt->pUserCB->pTXCCB = (pSalI2CUserCBAdpt+1); + pSalI2CMngtAdpt->pUserCB->pRXCB = (pSalI2CUserCBAdpt+2); + pSalI2CMngtAdpt->pUserCB->pRXCCB = (pSalI2CUserCBAdpt+3); + pSalI2CMngtAdpt->pUserCB->pRDREQCB = (pSalI2CUserCBAdpt+4); + pSalI2CMngtAdpt->pUserCB->pERRCB = (pSalI2CUserCBAdpt+5); + pSalI2CMngtAdpt->pUserCB->pDMATXCB = (pSalI2CUserCBAdpt+6); + pSalI2CMngtAdpt->pUserCB->pDMATXCCB = (pSalI2CUserCBAdpt+7); + pSalI2CMngtAdpt->pUserCB->pDMARXCB = (pSalI2CUserCBAdpt+8); + pSalI2CMngtAdpt->pUserCB->pDMARXCCB = (pSalI2CUserCBAdpt+9); + pSalI2CMngtAdpt->pUserCB->pGENCALLCB= (pSalI2CUserCBAdpt+10); + + /*To assign the rest pointers*/ + pSalI2CMngtAdpt->MstRDCmdCnt = 0; + pSalI2CMngtAdpt->InnerTimeOut = 2000; // inner time-out count, 2000 ms + pSalI2CMngtAdpt->pSalHndPriv->ppSalI2CHnd = (void**)&(pSalI2CMngtAdpt->pSalHndPriv); + + /* To assign the default (ROM) HAL OP initialization function */ +#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT) + pSalI2CMngtAdpt->pHalOpInit = HalI2COpInit_Patch; +#elif defined(CONFIG_CHIP_E_CUT) + // TODO: E-Cut + pSalI2CMngtAdpt->pHalOpInit = HalI2COpInitV02; +#endif + + /* To assign the default (ROM) HAL GDMA OP initialization function */ + pSalI2CMngtAdpt->pHalGdmaOpInit = HalGdmaOpInit; + + /* To assign the default (ROM) SAL interrupt function */ +#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT) + pSalI2CMngtAdpt->pSalIrqFunc = I2CISRHandle_Patch; +#elif defined(CONFIG_CHIP_E_CUT) + pSalI2CMngtAdpt->pSalIrqFunc = I2CISRHandleV02; +#endif + + /* To assign the default (ROM) SAL DMA TX interrupt function */ + pSalI2CMngtAdpt->pSalDMATxIrqFunc = I2CTXGDMAISRHandle; + + /* To assign the default (ROM) SAL DMA RX interrupt function */ + pSalI2CMngtAdpt->pSalDMARxIrqFunc = I2CRXGDMAISRHandle; + + return pSalI2CMngtAdpt; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CFreeMngtAdpt +// +// Description: +// Free all the previous allocated memory space. +// +// Arguments: +// [in] PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt - +// I2C SAL management adapter pointer +// +// +// Return: +// The status of the enable process. +// _EXIT_SUCCESS if the RtkI2CFreeMngtAdpt succeeded. +// _EXIT_FAILURE if the RtkI2CFreeMngtAdpt failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-02. +// +//--------------------------------------------------------------------------------------------------- +HAL_Status +RtkI2CFreeMngtAdpt( + IN PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt +){ +#ifdef I2C_STATIC_ALLOC + RtlMfree((u8 *)pSalI2CMngtAdpt->pUserCB->pTXCB, (sizeof(SAL_I2C_USERCB_ADPT)*SAL_USER_CB_NUM)); + RtlMfree((u8 *)pSalI2CMngtAdpt->pDMAConf, (sizeof(SAL_I2C_DMA_USER_DEF))); + RtlMfree((u8 *)pSalI2CMngtAdpt->pIrqRxGdmaHnd, (sizeof(IRQ_HANDLE))); + RtlMfree((u8 *)pSalI2CMngtAdpt->pIrqTxGdmaHnd, (sizeof(IRQ_HANDLE))); + RtlMfree((u8 *)pSalI2CMngtAdpt->pHalGdmaOp, (sizeof(HAL_GDMA_OP))); + RtlMfree((u8 *)pSalI2CMngtAdpt->pHalRxGdmaAdp, (sizeof(HAL_GDMA_ADAPTER))); + RtlMfree((u8 *)pSalI2CMngtAdpt->pHalTxGdmaAdp, (sizeof(HAL_GDMA_ADAPTER))); + RtlMfree((u8 *)pSalI2CMngtAdpt->pUserCB, sizeof(SAL_I2C_USER_CB)); + RtlMfree((u8 *)pSalI2CMngtAdpt->pIrqHnd, sizeof(IRQ_HANDLE)); + RtlMfree((u8 *)pSalI2CMngtAdpt->pHalOp, sizeof(HAL_I2C_OP)); + RtlMfree((u8 *)pSalI2CMngtAdpt->pHalInitDat, sizeof(HAL_I2C_INIT_DAT)); + RtlMfree((u8 *)pSalI2CMngtAdpt->pSalHndPriv, sizeof(SAL_I2C_HND_PRIV)); + RtlMfree((u8 *)pSalI2CMngtAdpt, sizeof(SAL_I2C_MNGT_ADPT)); +#else + ; +#endif + + return HAL_OK; +} + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CGetSalHnd +// +// Description: +// Allocation of lower layer memory spaces will be done by invoking RtkI2CGetMngtAdpt +// in this function and return a SAL_I2C_HND pointer to upper layer. +// According to the given I2C index, RtkI2CGetMngtAdpt will allocate all the memory +// space such as SAL_I2C_HND, HAL_I2C_INIT_DAT, SAL_I2C_USER_CB etc. +// +// +// Arguments: +// [in] u8 I2CIdx - +// I2C Index +// +// Return: +// PSAL_I2C_HND +// A pointer to SAL_I2C_HND which is allocated in the lower layer. +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +PSAL_I2C_HND +RtkI2CGetSalHnd( + IN u8 I2CIdx +){ + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND pSalI2CHND = NULL; + + /* Check the user define setting and the given index */ + if (RtkI2CIdxChk(I2CIdx)) { + return (PSAL_I2C_HND)NULL; + } + + /* Invoke RtkI2CGetMngtAdpt to get the I2C SAL management adapter pointer */ + pSalI2CMngtAdpt = RtkI2CGetMngtAdpt(I2CIdx); + + /* Assign the private SAL handle to public SAL handle */ + pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); + + /* Assign the internal HAL initial data pointer to the SAL handle */ + pSalI2CHND->pInitDat = pSalI2CMngtAdpt->pHalInitDat; + + /* Assign the internal user callback pointer to the SAL handle */ + pSalI2CHND->pUserCB = pSalI2CMngtAdpt->pUserCB; + + /* Assign the internal user define DMA configuration to the SAL handle */ + pSalI2CHND->pDMAConf = pSalI2CMngtAdpt->pDMAConf; + + return &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv); +} + + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkI2CFreeSalHnd +// +// Description: +// Based on the given pSalI2CHND, the top layer management adapter pointer could +// be reversely parsed. And free memory space is done by RtkI2CFreeMngtAdpt. +// +// +// Arguments: +// [in] PSAL_I2C_HND pSalI2CHND - +// SAL I2C handle +// +// Return: +// The status of the free SAL memory space process. +// _EXIT_SUCCESS if the RtkI2CFreeSalHnd succeeded. +// _EXIT_FAILURE if the RtkI2CFreeSalHnd failed. +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//---------------------------------------------------------------------------------------------------- +HAL_Status +RtkI2CFreeSalHnd( + IN PSAL_I2C_HND pSalI2CHND +){ + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PSAL_I2C_HND_PRIV pSalI2CHNDPriv = NULL; + + /* To get the SAL_I2C_MNGT_ADPT pointer */ + pSalI2CHNDPriv = CONTAINER_OF(pSalI2CHND, SAL_I2C_HND_PRIV, SalI2CHndPriv); + pSalI2CMngtAdpt = CONTAINER_OF(pSalI2CHNDPriv->ppSalI2CHnd, SAL_I2C_MNGT_ADPT, pSalHndPriv); + + /* Invoke RtkI2CFreeMngtAdpt to free all the lower layer memory space */ + return (RtkI2CFreeMngtAdpt(pSalI2CMngtAdpt)); +} + +#endif // end of "#ifndef CONFIG_MBED_ENABLED" + +//--------------------------------------------------------------------------------------------------- +//Function Name: +// RtkSalI2CSts +// +// Description: +// Get i2c status +// +// Arguments: +// A SAL operation adapter pointer +// +// Return: +// NA +// +// Note: +// NA +// +// See Also: +// NA +// +// Author: +// By Jason Deng, 2014-04-03. +// +//--------------------------------------------------------------------------------------------------- +u32 +RtkSalI2CSts( + IN VOID *Data +){ + PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data; + PSAL_I2C_HND_PRIV pSalI2CHNDPriv = NULL; + PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL; + PHAL_I2C_INIT_DAT pHalI2CInitDat = NULL; + PHAL_I2C_OP pHalI2COP = NULL; + u32 I2CLocalTemp; + + + /* To Get the SAL_I2C_MNGT_ADPT Pointer */ + pSalI2CHNDPriv = CONTAINER_OF(pSalI2CHND, SAL_I2C_HND_PRIV, SalI2CHndPriv); + pSalI2CMngtAdpt = CONTAINER_OF(pSalI2CHNDPriv->ppSalI2CHnd, SAL_I2C_MNGT_ADPT, pSalHndPriv); + + pHalI2CInitDat = pSalI2CMngtAdpt->pHalInitDat; + pHalI2COP = pSalI2CMngtAdpt->pHalOp; + + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_RAW_INTR_STAT); + + if (I2CLocalTemp & BIT_IC_RAW_INTR_STAT_GEN_CALL) { + return 2; + } + else if (I2CLocalTemp & BIT_IC_RAW_INTR_STAT_RD_REQ) { + return 1; + } + + I2CLocalTemp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat, REG_DW_I2C_IC_STATUS); + + if (I2CLocalTemp & BIT_IC_STATUS_RFNE) { + return 3; + } + + return 0; +} diff --git a/lib/fwlib/src/hal_i2s.c b/lib/fwlib/src/hal_i2s.c new file mode 100644 index 0000000..015107a --- /dev/null +++ b/lib/fwlib/src/hal_i2s.c @@ -0,0 +1,535 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "rtl8195a.h" +#include "hal_i2s.h" +#include "rand.h" +#include "rtl_utility.h" + + +//1 need to be modified + + +/*====================================================== + Local used variables +*/ +SRAM_BF_DATA_SECTION +HAL_I2S_OP HalI2SOpSAL={0}; + + +VOID +I2SISRHandle( + IN VOID *Data +) +{ + PHAL_I2S_ADAPTER pI2SAdp = (PHAL_I2S_ADAPTER) Data; + PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL; + PHAL_I2S_INIT_DAT pI2SCfg = pI2SAdp->pInitDat; + u32 I2STxIsr, I2SRxIsr; + u8 I2SPageNum = pI2SCfg->I2SPageNum+1; +// u32 I2SPageSize = (pI2SAdp->I2SPageSize+1)<<2; + u32 i; + u32 pbuf; + + I2STxIsr = pHalI2SOP->HalI2SReadReg(pI2SCfg, REG_I2S_TX_STATUS_INT); + I2SRxIsr = pHalI2SOP->HalI2SReadReg(pI2SCfg, REG_I2S_RX_STATUS_INT); + + pI2SCfg->I2STxIntrClr = I2STxIsr; + pI2SCfg->I2SRxIntrClr = I2SRxIsr; + pHalI2SOP->HalI2SClrIntr(pI2SCfg); + + for (i=0 ; iI2SHWTxIdx)) { +// pbuf = ((u32)(pI2SCfg->I2STxData)) + (I2SPageSize*pI2SCfg->I2SHWTxIdx); + pbuf = (u32)pI2SAdp->TxPageList[pI2SCfg->I2SHWTxIdx]; + pI2SAdp->UserCB.TxCCB(pI2SAdp->UserCB.TxCBId, (char*)pbuf); + I2STxIsr &= ~(1<I2SHWTxIdx); + pI2SCfg->I2SHWTxIdx += 1; + if (pI2SCfg->I2SHWTxIdx == I2SPageNum) { + pI2SCfg->I2SHWTxIdx = 0; + } + } + + if (I2SRxIsr & (1<I2SHWRxIdx)) { +// pbuf = ((u32)(pI2SCfg->I2SRxData)) + (I2SPageSize*pI2SCfg->I2SHWRxIdx); + pbuf = (u32)pI2SAdp->RxPageList[pI2SCfg->I2SHWRxIdx]; + pI2SAdp->UserCB.RxCCB(pI2SAdp->UserCB.RxCBId, (char*)pbuf); + I2SRxIsr &= ~(1<I2SHWRxIdx); + pI2SCfg->I2SHWRxIdx += 1; + if (pI2SCfg->I2SHWRxIdx == I2SPageNum) { + pI2SCfg->I2SHWRxIdx = 0; + } + } + } +} + + +static HAL_Status +RtkI2SIrqInit( + IN PHAL_I2S_ADAPTER pI2SAdapter +) +{ + PIRQ_HANDLE pIrqHandle; + + if (pI2SAdapter->DevNum > I2S_MAX_ID) { + DBG_I2S_ERR("RtkI2SIrqInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum); + return HAL_ERR_PARA; + } + + pIrqHandle = &pI2SAdapter->IrqHandle; + + switch (pI2SAdapter->DevNum){ + case I2S0_SEL: + pIrqHandle->IrqNum = I2S0_PCM0_IRQ; + break; + + case I2S1_SEL: + pIrqHandle->IrqNum = I2S1_PCM1_IRQ; + break; + + default: + return HAL_ERR_PARA; + } + + pIrqHandle->Data = (u32) (pI2SAdapter); + pIrqHandle->IrqFun = (IRQ_FUN) I2SISRHandle; + pIrqHandle->Priority = 3; + InterruptRegister(pIrqHandle); + InterruptEn(pIrqHandle); + + return HAL_OK; +} + +static HAL_Status +RtkI2SIrqDeInit( + IN PHAL_I2S_ADAPTER pI2SAdapter +) +{ + if (pI2SAdapter->DevNum > I2S_MAX_ID) { + DBG_I2S_ERR("RtkI2SIrqDeInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum); + return HAL_ERR_PARA; + } + + InterruptDis(&pI2SAdapter->IrqHandle); + InterruptUnRegister(&pI2SAdapter->IrqHandle); + + return HAL_OK; +} + +static HAL_Status +RtkI2SPinMuxInit( + IN PHAL_I2S_ADAPTER pI2SAdapter +) +{ + u32 I2Stemp; + + if (pI2SAdapter->DevNum > I2S_MAX_ID) { + DBG_I2S_ERR("RtkI2SPinMuxInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum); + return HAL_ERR_PARA; + } + + // enable system pll + I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) | (1<<9) | (1<<10); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp); + + switch (pI2SAdapter->DevNum){ + case I2S0_SEL: + ACTCK_I2S_CCTRL(ON); + SLPCK_I2S_CCTRL(ON); + LXBUS_FCTRL(ON); // enable lx bus for i2s + + /*I2S0 Pin Mux Setting*/ + PinCtrl(I2S0, pI2SAdapter->PinMux, ON); + if (pI2SAdapter->PinMux == I2S_S0) { + DBG_I2S_WARN(ANSI_COLOR_MAGENTA"I2S0 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET); + } + I2S0_MCK_CTRL(ON); + I2S0_PIN_CTRL(ON); + I2S0_FCTRL(ON); + + break; + case I2S1_SEL: + ACTCK_I2S_CCTRL(ON); + SLPCK_I2S_CCTRL(ON); + LXBUS_FCTRL(ON); // enable lx bus for i2s + + /*I2S1 Pin Mux Setting*/ + PinCtrl(I2S1, pI2SAdapter->PinMux, ON); + if (pI2SAdapter->PinMux == I2S_S2) { + DBG_I2S_WARN(ANSI_COLOR_MAGENTA"I2S1 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET); + } + I2S1_MCK_CTRL(ON); + I2S1_PIN_CTRL(ON); + I2S0_FCTRL(ON); //i2s 1 is control by bit 24 BIT_PERI_I2S0_EN + I2S1_FCTRL(ON); + break; + default: + return HAL_ERR_PARA; + } + + return HAL_OK; +} + + +static HAL_Status +RtkI2SPinMuxDeInit( + IN PHAL_I2S_ADAPTER pI2SAdapter +) +{ + if (pI2SAdapter->DevNum > I2S_MAX_ID) { + DBG_I2S_ERR("RtkI2SPinMuxDeInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum); + return HAL_ERR_PARA; + } + + switch (pI2SAdapter->DevNum){ + case I2S0_SEL: + /*I2S0 Pin Mux Setting*/ + //ACTCK_I2C0_CCTRL(OFF); + PinCtrl(I2S0, pI2SAdapter->PinMux, OFF); + I2S0_MCK_CTRL(OFF); + I2S0_PIN_CTRL(OFF); + //I2S0_FCTRL(OFF); + + break; + case I2S1_SEL: + /*I2S1 Pin Mux Setting*/ + //ACTCK_I2C1_CCTRL(OFF); + PinCtrl(I2S1, pI2SAdapter->PinMux, OFF); + I2S1_MCK_CTRL(OFF); + I2S1_PIN_CTRL(OFF); + //I2S1_FCTRL(OFF); + break; + default: + return HAL_ERR_PARA; + } + + return HAL_OK; +} + + +HAL_Status +RtkI2SInit( + IN VOID *Data +) +{ + PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data; + PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL; + PHAL_I2S_INIT_DAT pI2SCfg; + + if (pI2SAdapter == 0) { + DBG_I2S_ERR("RtkI2SInit: Null Pointer\r\n"); + return HAL_ERR_PARA; + } + + if (pI2SAdapter->DevNum > I2S_MAX_ID) { + DBG_I2S_ERR("RtkI2SInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum); + return HAL_ERR_PARA; + } + + pI2SCfg = pI2SAdapter->pInitDat; + + /*I2S Initialize HAL Operations*/ + HalI2SOpInit(pHalI2SOP); + + /*I2S Interrupt Initialization*/ + RtkI2SIrqInit(pI2SAdapter); + + /*I2S Pin Mux Initialization*/ + RtkI2SPinMuxInit(pI2SAdapter); + + /*I2S Load User Setting*/ + pI2SCfg->I2SIdx = pI2SAdapter->DevNum; + + /*I2S HAL Initialization*/ + pHalI2SOP->HalI2SInit(pI2SCfg); + + /*I2S Device Status Update*/ + pI2SAdapter->DevSts = I2S_STS_INITIALIZED; + + /*I2S Enable Module*/ + pI2SCfg->I2SEn = I2S_ENABLE; + pHalI2SOP->HalI2SEnable(pI2SCfg); + + /*I2S Device Status Update*/ + pI2SAdapter->DevSts = I2S_STS_IDLE; + + return HAL_OK; +} + +HAL_Status +RtkI2SDeInit( + IN VOID *Data +) +{ + PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data; + PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL; + PHAL_I2S_INIT_DAT pI2SCfg; + u32 I2Stemp; + + if (pI2SAdapter == 0) { + DBG_I2S_ERR("RtkI2SDeInit: Null Pointer\r\n"); + return HAL_ERR_PARA; + } + + pI2SCfg = pI2SAdapter->pInitDat; + + /*I2S Disable Module*/ + pI2SCfg->I2SEn = I2S_DISABLE; + pHalI2SOP->HalI2SEnable(pI2SCfg); + HalI2SClearAllOwnBit((VOID*)pI2SCfg); + + /*I2C HAL DeInitialization*/ + //pHalI2SOP->HalI2SDeInit(pI2SCfg); + + /*I2S Interrupt DeInitialization*/ + RtkI2SIrqDeInit(pI2SAdapter); + + /*I2S Pin Mux DeInitialization*/ + RtkI2SPinMuxDeInit(pI2SAdapter); + + /*I2S HAL DeInitialization*/ + pHalI2SOP->HalI2SDeInit(pI2SCfg); + + /*I2S CLK Source Close*/ + I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) & (~((1<<9) | (1<<10))); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp); + + /*I2S Device Status Update*/ + pI2SAdapter->DevSts = I2S_STS_UNINITIAL; + + return HAL_OK; +} + +HAL_Status +RtkI2SEnable( + IN VOID *Data +) +{ + PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data; + PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL; + PHAL_I2S_INIT_DAT pI2SCfg; + u32 I2Stemp; + + // Enable IP Clock + I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) | (1<<9) | (1<<10); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp); + ACTCK_I2S_CCTRL(ON); + SLPCK_I2S_CCTRL(ON); + + pI2SCfg = pI2SAdapter->pInitDat; + pI2SCfg->I2SEn = I2S_ENABLE; + pHalI2SOP->HalI2SEnable(pI2SCfg); + + return HAL_OK; +} + +HAL_Status +RtkI2SDisable( + IN VOID *Data +) +{ + PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data; + PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL; + PHAL_I2S_INIT_DAT pI2SCfg; + u32 I2Stemp; + + pI2SCfg = pI2SAdapter->pInitDat; + pI2SCfg->I2SEn = I2S_DISABLE; + pHalI2SOP->HalI2SEnable(pI2SCfg); + + // Gate IP Clock + ACTCK_I2S_CCTRL(OFF); + SLPCK_I2S_CCTRL(OFF); + + // Close I2S bus clock(WS,SCLK,MCLK). If needs that clock, mark this. + I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) & (~((1<<9) | (1<<10))); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp); + + return HAL_OK; +} + +RTK_STATUS +RtkI2SIoCtrl( + IN VOID *Data +) +{ + return _EXIT_SUCCESS; +} + +RTK_STATUS +RtkI2SPowerCtrl( + IN VOID *Data +) +{ + return _EXIT_SUCCESS; +} + +HAL_Status +RtkI2SLoadDefault( + IN VOID *Adapter, + IN VOID *Setting +) +{ + PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Adapter; + PHAL_I2S_INIT_DAT pI2SCfg = pI2SAdapter->pInitDat; + PHAL_I2S_DEF_SETTING pLoadSetting = (PHAL_I2S_DEF_SETTING)Setting; + + if (pI2SAdapter == 0) { + DBG_I2S_ERR("RtkI2SLoadDefault: Null Pointer\r\n"); + return HAL_ERR_PARA; + } + + if (pI2SAdapter->pInitDat == NULL) { + DBG_I2S_ERR("RtkI2SLoadDefault: pInitDat is NULL!\r\n", pI2SAdapter->DevNum); + return HAL_ERR_PARA; + } + + pI2SAdapter->DevSts = pLoadSetting->DevSts; + pI2SAdapter->ErrType = 0; + pI2SAdapter->TimeOut = 0; + + pI2SCfg->I2SIdx = pI2SAdapter->DevNum; + pI2SCfg->I2SEn = I2S_DISABLE; + pI2SCfg->I2SMaster = pLoadSetting->I2SMaster; + pI2SCfg->I2SWordLen = pLoadSetting->I2SWordLen; + pI2SCfg->I2SChNum = pLoadSetting->I2SChNum; + pI2SCfg->I2SPageNum = pLoadSetting->I2SPageNum; + pI2SCfg->I2SPageSize = pLoadSetting->I2SPageSize; + pI2SCfg->I2SRate = pLoadSetting->I2SRate; + pI2SCfg->I2STRxAct = pLoadSetting->I2STRxAct; + pI2SCfg->I2STxIntrMSK = pLoadSetting->I2STxIntrMSK; + pI2SCfg->I2SRxIntrMSK = pLoadSetting->I2SRxIntrMSK; + + return HAL_OK; +} + +VOID HalI2SOpInit( + IN VOID *Data +) +{ + PHAL_I2S_OP pHalI2SOp = (PHAL_I2S_OP) Data; + + pHalI2SOp->HalI2SInit = HalI2SInitRtl8195a_Patch; + pHalI2SOp->HalI2SDeInit = HalI2SDeInitRtl8195a; + pHalI2SOp->HalI2STx = HalI2STxRtl8195a; + pHalI2SOp->HalI2SRx = HalI2SRxRtl8195a; + pHalI2SOp->HalI2SEnable = HalI2SEnableRtl8195a; + pHalI2SOp->HalI2SIntrCtrl = HalI2SIntrCtrlRtl8195a; + pHalI2SOp->HalI2SReadReg = HalI2SReadRegRtl8195a; + pHalI2SOp->HalI2SSetRate = HalI2SSetRateRtl8195a; + pHalI2SOp->HalI2SSetWordLen = HalI2SSetWordLenRtl8195a; + pHalI2SOp->HalI2SSetChNum = HalI2SSetChNumRtl8195a; + pHalI2SOp->HalI2SSetPageNum = HalI2SSetPageNumRtl8195a; + pHalI2SOp->HalI2SSetPageSize = HalI2SSetPageSizeRtl8195a; + pHalI2SOp->HalI2SClrIntr = HalI2SClrIntrRtl8195a; + pHalI2SOp->HalI2SClrAllIntr = HalI2SClrAllIntrRtl8195a; + pHalI2SOp->HalI2SDMACtrl = HalI2SDMACtrlRtl8195a; +} + +HAL_Status +HalI2SInit( + IN VOID *Data +) +{ + HAL_Status ret; + PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data; + +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE I2sPwrState; +#endif + + ret = RtkI2SInit(Data); +#ifdef CONFIG_SOC_PS_MODULE + if(ret == HAL_OK) { + // To register a new peripheral device power state + I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum; + I2sPwrState.PwrState = ACT; + RegPowerState(I2sPwrState); + } +#endif + + return ret; + +} + +VOID +HalI2SDeInit( + IN VOID *Data +) +{ +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE I2sPwrState; + PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data; + u8 HwState; + + I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum; + QueryRegPwrState(I2sPwrState.FuncIdx, &(I2sPwrState.PwrState), &HwState); + + // if the power state isn't ACT, then switch the power state back to ACT first + if ((I2sPwrState.PwrState != ACT) && (I2sPwrState.PwrState != INACT)) { + HalI2SEnable(Data); + QueryRegPwrState(I2sPwrState.FuncIdx, &(I2sPwrState.PwrState), &HwState); + } + + if (I2sPwrState.PwrState == ACT) { + I2sPwrState.PwrState = INACT; + RegPowerState(I2sPwrState); + } +#endif + + RtkI2SDeInit(Data); + +} + + +HAL_Status +HalI2SDisable( + IN VOID *Data +) +{ + HAL_Status ret; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE I2sPwrState; + PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data; +#endif + + ret = RtkI2SDisable(Data); +#ifdef CONFIG_SOC_PS_MODULE + if (ret == HAL_OK) { + I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum; + I2sPwrState.PwrState = SLPCG; + RegPowerState(I2sPwrState); + } +#endif + return ret; +} + +HAL_Status +HalI2SEnable( + IN VOID *Data +) +{ + HAL_Status ret; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE I2sPwrState; + PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data; +#endif + + ret = RtkI2SEnable(Data); +#ifdef CONFIG_SOC_PS_MODULE + if (ret == HAL_OK) { + I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum; + I2sPwrState.PwrState = ACT; + RegPowerState(I2sPwrState); + } +#endif + return ret; +} + diff --git a/lib/fwlib/src/hal_mii.c b/lib/fwlib/src/hal_mii.c new file mode 100644 index 0000000..e8520e6 --- /dev/null +++ b/lib/fwlib/src/hal_mii.c @@ -0,0 +1,42 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "hal_mii.h" + +VOID +HalMiiOpInit( + IN VOID *Data + ) +{ + PHAL_MII_OP pHalMiiOp = (PHAL_MII_OP) Data; + + pHalMiiOp->HalMiiGmacInit = HalMiiGmacInitRtl8195a; + pHalMiiOp->HalMiiInit = HalMiiInitRtl8195a; + pHalMiiOp->HalMiiGmacReset = HalMiiGmacResetRtl8195a; + pHalMiiOp->HalMiiGmacEnablePhyMode = HalMiiGmacEnablePhyModeRtl8195a; + pHalMiiOp->HalMiiGmacXmit = HalMiiGmacXmitRtl8195a; + pHalMiiOp->HalMiiGmacCleanTxRing = HalMiiGmacCleanTxRingRtl8195a; + pHalMiiOp->HalMiiGmacFillTxInfo = HalMiiGmacFillTxInfoRtl8195a; + pHalMiiOp->HalMiiGmacFillRxInfo = HalMiiGmacFillRxInfoRtl8195a; + pHalMiiOp->HalMiiGmacTx = HalMiiGmacTxRtl8195a; + pHalMiiOp->HalMiiGmacRx = HalMiiGmacRxRtl8195a; + pHalMiiOp->HalMiiGmacSetDefaultEthIoCmd = HalMiiGmacSetDefaultEthIoCmdRtl8195a; + pHalMiiOp->HalMiiGmacInitIrq = HalMiiGmacInitIrqRtl8195a; + pHalMiiOp->HalMiiGmacGetInterruptStatus = HalMiiGmacGetInterruptStatusRtl8195a; + pHalMiiOp->HalMiiGmacClearInterruptStatus = HalMiiGmacClearInterruptStatusRtl8195a; +#if 0 + pHalMiiOp-> = Rtl8195a; + pHalMiiOp-> = Rtl8195a; + pHalMiiOp-> = Rtl8195a; + pHalMiiOp-> = Rtl8195a; + pHalMiiOp-> = Rtl8195a; +#endif +} + diff --git a/lib/fwlib/src/hal_nfc.c b/lib/fwlib/src/hal_nfc.c new file mode 100644 index 0000000..bafa43e --- /dev/null +++ b/lib/fwlib/src/hal_nfc.c @@ -0,0 +1,20 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "rtl8195a.h" +#include "hal_nfc.h" + +VOID HalNFCOpInit( + IN VOID *Data +) +{ + +} + diff --git a/lib/fwlib/src/hal_pcm.c b/lib/fwlib/src/hal_pcm.c new file mode 100644 index 0000000..5ccf96a --- /dev/null +++ b/lib/fwlib/src/hal_pcm.c @@ -0,0 +1,28 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "hal_pcm.h" + +VOID HalPcmOpInit( + IN VOID *Data +) +{ + PHAL_PCM_OP pHalPcmOp = (PHAL_PCM_OP) Data; + + pHalPcmOp->HalPcmOnOff = HalPcmOnOffRtl8195a; + pHalPcmOp->HalPcmInit = HalPcmInitRtl8195a; + pHalPcmOp->HalPcmSetting = HalPcmSettingRtl8195a; + pHalPcmOp->HalPcmEn = HalPcmEnRtl8195a; + pHalPcmOp->HalPcmIsrEnAndDis= HalPcmIsrEnAndDisRtl8195a; + pHalPcmOp->HalPcmDumpReg= HalPcmDumpRegRtl8195a; + pHalPcmOp->HalPcm= HalPcmRtl8195a; +} + + diff --git a/lib/fwlib/src/hal_pwm.c b/lib/fwlib/src/hal_pwm.c new file mode 100644 index 0000000..0e8432d --- /dev/null +++ b/lib/fwlib/src/hal_pwm.c @@ -0,0 +1,131 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "rtl8195a.h" + +#ifdef CONFIG_PWM_EN +#include "hal_pwm.h" +#include "hal_timer.h" + +HAL_PWM_ADAPTER PWMPin[MAX_PWM_CTRL_PIN]; +const u8 PWMTimerIdx[MAX_PWM_CTRL_PIN]= {3,4,5,6}; // the G-timer ID used for PWM pin 0~3 + +/** + * @brief Initializes and enable a PWM control pin. + * + * @param pwm_id: the PWM pin index + * @param sel: pin mux selection + * + * @retval HAL_Status + */ +HAL_Status +HAL_Pwm_Init( + u32 pwm_id, + u32 sel +) +{ + HAL_PWM_ADAPTER *pPwmAdapt; + u32 timer_id; + + DBG_PWM_INFO("%s: Init PWM for PWM %d, Sel %d\n", __FUNCTION__, pwm_id, sel); + + if ((pwm_id >= MAX_PWM_CTRL_PIN) || (sel > 3)) { + DBG_PWM_ERR ("HAL_Pwm_Init: Invalid PWM index(%d), sel(%d)\n", pwm_id, sel); + return HAL_ERR_PARA; + } + + pPwmAdapt = &PWMPin[pwm_id]; + pPwmAdapt->pwm_id = pwm_id; + pPwmAdapt->sel = sel; + timer_id = PWMTimerIdx[pwm_id]; + pPwmAdapt->gtimer_id = timer_id; + + return HAL_Pwm_Init_8195a (pPwmAdapt); +} + + +/** + * @brief Disable a PWM control pin. + * + * @param pwm_id: the PWM pin index + * + * @retval None + */ +void +HAL_Pwm_Enable( + u32 pwm_id +) +{ + HAL_PWM_ADAPTER *pPwmAdapt; + + if (pwm_id >= MAX_PWM_CTRL_PIN) { + DBG_PWM_ERR ("HAL_Pwm_Enable: Invalid PWM index(%d)\n", pwm_id); + return; + } + pPwmAdapt = &PWMPin[pwm_id]; + + HAL_Pwm_Enable_8195a(pPwmAdapt); +} + + +/** + * @brief Disable a PWM control pin. + * + * @param pwm_id: the PWM pin index + * + * @retval None + */ +void +HAL_Pwm_Disable( + u32 pwm_id +) +{ + HAL_PWM_ADAPTER *pPwmAdapt; + + if (pwm_id >= MAX_PWM_CTRL_PIN) { + DBG_PWM_ERR ("HAL_Pwm_Disable: Invalid PWM index(%d)\n", pwm_id); + return; + } + pPwmAdapt = &PWMPin[pwm_id]; + + HAL_Pwm_Disable_8195a(pPwmAdapt); +} + +/** + * @brief Set the duty ratio of the PWM pin. + * + * @param pwm_id: the PWM pin index + * @param period: the period time, in micro-second. + * @param pulse_width: the pulse width time, in micro-second. + * + * @retval None + */ +void +HAL_Pwm_SetDuty( + u32 pwm_id, + u32 period, + u32 pulse_width +) +{ + HAL_PWM_ADAPTER *pPwmAdapt; + + if (pwm_id >= MAX_PWM_CTRL_PIN) { + DBG_PWM_ERR ("HAL_Pwm_SetDuty: Invalid PWM index(%d)\n", pwm_id); + return; + } + +// DBG_PWM_INFO("%s: Period%d Pulse%d\n", __FUNCTION__, period, pulse_width); + pPwmAdapt = &PWMPin[pwm_id]; + + HAL_Pwm_SetDuty_8195a(pPwmAdapt, period, pulse_width); +} + + +#endif // end of "#ifdef CONFIG_PWM_EN" diff --git a/lib/fwlib/src/hal_sdr_controller.c b/lib/fwlib/src/hal_sdr_controller.c new file mode 100644 index 0000000..4d939a7 --- /dev/null +++ b/lib/fwlib/src/hal_sdr_controller.c @@ -0,0 +1,971 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ +#include "rtl8195a.h" +#include "hal_sdr_controller.h" +#include "rtl8195a_sdr.h" +#if 0 +#define HAL_SDR_WRITE32(addr, value32) HAL_WRITE32(SDR_CTRL_BASE, addr, value32) +#define HAL_SDR_WRITE16(addr, value16) HAL_WRITE16(SDR_CTRL_BASE, addr, value16) +#define HAL_SDR_WRITE8(addr, value8) HAL_WRITE8(SDR_CTRL_BASE, addr, value8) +#define HAL_SDR_READ32(addr) HAL_READ32(SDR_CTRL_BASE, addr) +#define HAL_SDR_READ16(addr) HAL_READ16(SDR_CTRL_BASE, addr) +#define HAL_SDR_READ8(addr) HAL_READ8(SDR_CTRL_BASE, addr) + +#define HAL_SDRAM_WRITE32(addr, value32) HAL_WRITE32(SDR_SDRAM_BASE, addr, value32) +#define HAL_SDRAM_WRITE16(addr, value16) HAL_WRITE16(SDR_SDRAM_BASE, addr, value16) +#define HAL_SDRAM_WRITE8(addr, value8) HAL_WRITE8(SDR_SDRAM_BASE, addr, value8) +#define HAL_SDRAM_READ32(addr) HAL_READ32(SDR_SDRAM_BASE, addr) +#define HAL_SDRAM_READ16(addr) HAL_READ16(SDR_SDRAM_BASE, addr) +#define HAL_SDRAM_READ8(addr) HAL_READ8(SDR_SDRAM_BASE, addr) +#endif + + + +HAL_CUT_B_RAM_DATA_SECTION +DRAM_INFO SdrDramDev = { + DRAM_INFO_TYPE, + DRAM_INFO_COL_ADDR_WTH, + DRAM_INFO_BANK_SZ, + DRAM_INFO_DQ_WTH +}; + + +HAL_CUT_B_RAM_DATA_SECTION +DRAM_MODE_REG_INFO SdrDramModeReg = { + BST_LEN_4, + SENQUENTIAL, + 0x3, // Mode0Cas: 3 + 0x0, // Mode0Wr + 0, // Mode1DllEnN + 0, // Mode1AllLat + 0 // Mode2Cwl +}; + +HAL_CUT_B_RAM_DATA_SECTION +DRAM_TIMING_INFO SdrDramTiming = { + DRAM_TIMING_TRFC, // TrfcPs; + DRAM_TIMING_TREFI, // TrefiPs; + DRAM_TIMING_TWRMAXTCK, // WrMaxTck; + DRAM_TIMING_TRCD, // TrcdPs; + DRAM_TIMING_TRP, // TrpPs; + DRAM_TIMING_TRAS, // TrasPs; + DRAM_TIMING_TRRD, // TrrdTck; + DRAM_TIMING_TWR, // TwrPs; + DRAM_TIMING_TWTR, // TwtrTck; + //13090, // TrtpPs; + DRAM_TIMING_TMRD, // TmrdTck; + DRAM_TIMING_TRTP, // TrtpTck; + DRAM_TIMING_TCCD, // TccdTck; + DRAM_TIMING_TRC // TrcPs; +}; + +HAL_CUT_B_RAM_DATA_SECTION +DRAM_DEVICE_INFO SdrDramInfo = { + &SdrDramDev, + &SdrDramModeReg, + &SdrDramTiming, + DRAM_TIMING_TCK, + DFI_RATIO_1 +}; + + +#define FPGA +#define FPGA_TEMP +#define SDR_CLK_DLY_CTRL 0x40000300 +#define MIN_RD_PIPE 0x0 +#define MAX_RD_PIPE 0x7 + +#define SUPPORT_DRAM_KED + + +#ifdef FPGA +#ifdef FPGA_TEMP +#define MAX_TAP_DLY 0xC +#else +#define MAX_TAP_DLY 0x7F +#define SPEC_MAX_TAP 0xFF +#endif +#else +#define MAX_TAP_DLY 99 // 0~99 +#define SPEC_MAX_TAP 99 +#define WINDOW_COMBIN // combine window [0~a] and [b~99] (for asic mode) +#endif + +#define TAP_DLY 0x1 +#define REC_NUM 512 + + +u32 SdrControllerInit(VOID); +VOID DramInit(DRAM_DEVICE_INFO *); +s32 MemTest(u32 loop_cnt); +u32 SdrCalibration(VOID); +u32 Sdr_Rand2(VOID); + +//3 Note: stack overfloat if the arrary is declared in the task +HAL_CUT_B_RAM_DATA_SECTION +u32 AvaWds[2][REC_NUM]; + +HAL_CUT_B_RAM_DATA_SECTION +unsigned int rand_x = 123456789; + +#ifdef CONFIG_SDR_EN + +#ifdef CONFIG_SDR_VERIFY +enum{ + LLT, + TXRPT, + RXBUFF, + TXBUFF, +}; +#define REPORT_OFFSET 0x8000 +#define RAMASK_OFFSET 0x8800 +#define LLT_H_ADDR 0x650 +#define TXREPORT_H_ADDR 0x660 +#define RXBUFF_H_ADDR 0x670 +#define TXBUFF_H_ADDR 0x680 + +#define REG_PKTBUF_DBG_CTRL_8723B 0x0140 + +int +rt_rpt_h_addr(u8 rpt) +{ + u32 r_val, offset; + + if (rpt == LLT){ + offset = LLT_H_ADDR; + } + else if (rpt == TXRPT){ + offset = TXREPORT_H_ADDR; + } + else if (rpt == RXBUFF){ + offset = RXBUFF_H_ADDR; + } + else if (rpt == TXBUFF){ + offset = TXBUFF_H_ADDR; + } + else { + } + + r_val = ((HAL_READ32(WIFI_REG_BASE, REG_PKTBUF_DBG_CTRL_8723B)&0xFFFFF000)|offset); + HAL_WRITE32(WIFI_REG_BASE, REG_PKTBUF_DBG_CTRL_8723B, r_val); +} + + + +int +rt_txrpt_read32(u8 macid, u8 offset) +{ + u32 r_val; + + rt_rpt_h_addr(TXRPT); + r_val = HAL_READ32(WIFI_REG_BASE, (REPORT_OFFSET + macid*4 + offset)); + + return r_val; +} + +int +rt_txrpt_read16(u8 macid, u8 offset) +{ + u16 r_val; + + rt_rpt_h_addr(TXRPT); + r_val = HAL_READ16(WIFI_REG_BASE, (REPORT_OFFSET + macid*8 + offset)); + + return r_val; +} + +int +rt_txrpt_read8(u8 macid, u8 offset) +{ + u8 r_val; + + rt_rpt_h_addr(TXRPT); + r_val = HAL_READ8(WIFI_REG_BASE, (REPORT_OFFSET + macid*16 + offset)); + + return r_val; +} + +int +rt_txrpt_read_1b(u8 macid, u8 offset, u8 bit_offset) +{ + u8 r_val = ((rt_txrpt_read8(macid, offset) & BIT(bit_offset))?1:0); + + return r_val; +} + + +int +rt_txrpt_write32(u8 macid, u8 offset, u32 val) +{ + rt_rpt_h_addr(TXRPT); + HAL_WRITE32(WIFI_REG_BASE, (REPORT_OFFSET + macid*4 + offset), val); +} + +int +rt_txrpt_write16(u8 macid, u8 offset, u16 val) +{ + rt_rpt_h_addr(TXRPT); + HAL_WRITE16(WIFI_REG_BASE, (REPORT_OFFSET + macid*8 + offset), val); +} + +int +rt_txrpt_write8(u8 macid, u8 offset, u8 val) +{ + rt_rpt_h_addr(TXRPT); + DBG_8195A("Write addr %x %x\n", (REPORT_OFFSET + macid*16 + offset), val); + HAL_WRITE8(WIFI_REG_BASE, (REPORT_OFFSET + macid*16 + offset), val); +} + +int +rt_txrpt_write_1b(u8 macid, u8 offset, u8 bit_offset, u8 val) +{ + u8 r_val = rt_txrpt_read8(macid, offset); + + if (val){ + r_val |= BIT(bit_offset); + } + else { + r_val &= (~BIT(bit_offset)); + } + + HAL_WRITE8(WIFI_REG_BASE, (REPORT_OFFSET + macid*16 + offset), r_val); +} + + +u8 +ReadTxrptsdr8( + IN u8 Macid, + IN u8 Offset) +{ + u8 r_val; + + r_val = rt_txrpt_read8(Macid, Offset); + return r_val; +} + +VOID +WriteTxrptsdr8( + IN u8 Macid, + IN u8 Offset, + IN u8 Val) +{ + rt_txrpt_write8(Macid, Offset, Val); +} + +VOID +SdrTestApp( + IN VOID *Data +) +{ + u32 *Cmd =(u32*)Data; + u32 Loop, LoopIndex, Value32, Addr, Loop1, LoopIndex1; + + switch (Cmd[0]) { + case 1: + DBG_8195A("Initial SDR\n"); + + //1 "SdrControllerInit" is located in Image1, so we shouldn't call it in Image2 + if (!SdrControllerInit()) { + DBG_8195A("SDR Calibartion Fail!!!!\n"); + } + break; + case 2: + Loop = Cmd[1]; + Loop1 = Cmd[2]; + DBG_8195A("Verify SDR: Loop = 0x%08x Loop1 = 0x%08x\n",Loop, Loop1); + + for (LoopIndex1=0; LoopIndex1 < Loop1; LoopIndex1++) { + + for (LoopIndex=0; LoopIndex < Loop; LoopIndex++) { + Value32 = Rand2(); + Addr = Rand2(); + Addr &= 0x1FFFFF; + Addr &= (~0x3); + + if (!(LoopIndex & 0xFFFFF)) { + DBG_8195A("Alive: LOOP = 0x%08x, LOOP = 0x%08x\n",LoopIndex1, LoopIndex); + } + + // DBG_8195A("Value: 0x%x; Addr: 0x%x\n", Value32, Addr+SDR_SDRAM_BASE); + HAL_SDRAM_WRITE32(Addr, Value32); + + if (Value32 != HAL_SDRAM_READ32(Addr)) { + DBG_8195A("Loop:%d; Addr: 0x%08x => CheckData error: W: 0x%08x /R:0x%x\n" + ,LoopIndex + ,Addr + ,Value32 + ,HAL_SDRAM_READ32(Addr)); + + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO2, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO2)+1); + break; + } + } + } + DBG_8195A("Verify SDR Success\n"); + break; + + case 3: + DBG_8195A("WL read RPT MACID %x\n", Cmd[1]); + { + u8 i =0; + for(i=0;i<16;i++) { + DBG_8195A("WL RPT offset %d = %x\n", i, ReadTxrptsdr8(Cmd[1],i)); + } + } + break; + case 4: + DBG_8195A("WL write RPT MACID %x\n", Cmd[1]); + { + u8 i =0; + for(i=0;i<16;i++) { + WriteTxrptsdr8(Cmd[1],i,Cmd[2]); + //DBG_8195A("WL RPT offset %d = %x\n", i, ReadTxrptsdr8(Cmd[1],i)); + } + } + break; + default: + break; + } + +} + +#endif + +HAL_SDRC_TEXT_SECTION +VOID +SdrCtrlInit( +VOID +){ + HAL_WRITE32(0x40000000, 0x40, + ((HAL_READ32(0x40000000, 0x40)&0xfffff)|0xe00000)); + LDO25M_CTRL(ON); +} + +HAL_SDRC_TEXT_SECTION +u32 +SdrControllerInit( +VOID +) +{ + DBG_8195A("SDR Controller Init\n"); + + HAL_WRITE32(0x40000000, 0x40, + ((HAL_READ32(0x40000000, 0x40)&0xfffff)|0x300000)); + + SRAM_MUX_CFG(0x2); + + SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE); + + HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4,0); + + ACTCK_SDR_CCTRL(ON); + + SLPCK_SDR_CCTRL(ON); + + PinCtrl(SDR, 0, ON); + + HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4,0); + + MEM_CTRL_FCTRL(ON); + + HalDelayUs(3000); + + // sdr initialization + DramInit(&SdrDramInfo); + + // sdr calibration + if(!SdrCalibration()) { + return 0; + } + else { + return 1; + } +} + + +HAL_SDRC_TEXT_SECTION +VOID +DramInit ( + IN DRAM_DEVICE_INFO *DramInfo +) +{ + u32 CsBstLen = 0; // 0:bst_4, 1:bst_8 + u32 CasWr = 0;//, CasWrT; // cas write latency + u32 CasRd = 0, CasRdT = 0, CrlSrt = 0; // cas read latency + u32 AddLat; + u32 DramEmr2 = 0, DramMr0 = 0; + u32 CrTwr, DramMaxWr, DramWr; + u32 CrTrtw = 0, CrTrtwT = 0; + u32 DrmaPeriod; + DRAM_TYPE DdrType; + DRAM_DQ_WIDTH DqWidth; + DRAM_COLADDR_WTH Page; + u32 DfiRate; + volatile struct ms_rxi310_portmap *ms_ctrl_0_map; + ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE; + ms_ctrl_0_map = ms_ctrl_0_map; + + DfiRate = 1 << (u32) (DramInfo->DfiRate); + DrmaPeriod = (DramInfo->DdrPeriodPs)*(DfiRate); // according DFI_RATE to setting + + // In PHY, write latency == 3 + DramMaxWr= (DramInfo->Timing->WrMaxTck)/(DfiRate) +1; + DramWr = ((DramInfo->Timing->TwrPs) / DrmaPeriod)+1; + CrTwr = ((DramInfo->Timing->TwrPs) / DrmaPeriod) + 3; + + if (CrTwr < DramMaxWr) { + CrTwr = CrTwr; + } + else { + CrTwr = DramMaxWr; + } + + if ((DramInfo->Dev->DeviceType) == DRAM_DDR_2) { + DdrType = DRAM_DDR_2; + if (DramInfo->ModeReg->BstLen == BST_LEN_4) { + CsBstLen = 0; //bst_4 + CrTrtwT = 2+2; //4/2+2 + DramMr0 = 0x2; + } + else { // BST_LEN_8 + CsBstLen = 1; // bst_8 + CrTrtwT = 4+2; // 8/2+2 + DramMr0 = 0x3; + } + CasRd = DramInfo->ModeReg->Mode0Cas; + AddLat = DramInfo->ModeReg ->Mode1AllLat; + CasWr = CasRd + AddLat -1; + DramEmr2 = 0; + + DramMr0 =(((DramWr%6)-1) << (PCTL_MR_OP_BFO+1)) | // write_recovery + (0 << PCTL_MR_OP_BFO ) | // dll + (DramInfo->ModeReg->Mode0Cas << PCTL_MR_CAS_BFO ) | + (DramInfo->ModeReg->BstType << PCTL_MR_BT_BFO ) | + DramMr0; + } + else if ((DramInfo->Dev->DeviceType) == DRAM_DDR_3) { + DdrType = DRAM_DDR_3; + if (DramInfo->ModeReg->BstLen == BST_LEN_4) { + CsBstLen = 0; //bst_4 + DramMr0 = 0x2; + } + else { // BST_LEN_8 + CsBstLen = 1; // bst_8 + DramMr0 = 0x0; + } + + CrlSrt = (DramInfo->ModeReg->Mode0Cas >> 1); + if (((DramInfo->ModeReg->Mode0Cas) & 0x1) ) { + CasRdT = CrlSrt+ 12; + } + else { + CasRdT = CrlSrt+ 4; + } + + if (DramInfo->ModeReg->Mode1AllLat == 1) { // CL-1 + AddLat = CasRd -1; + } + else if (DramInfo->ModeReg->Mode1AllLat == 2){ // CL-2 + AddLat = CasRd -2; + } + else { + AddLat = 0; + } + + CasRd = CasRdT + AddLat; + + CasWr = DramInfo->ModeReg->Mode2Cwl + 5 + AddLat; + + DramEmr2 = DramInfo->ModeReg->Mode2Cwl << 3; + + if (DramWr == 16) { + DramWr = 0; + } + else if (DramWr <= 9) { // 5< wr <= 9 + DramWr = DramWr - 4; + } + else { + DramWr = (DramWr + 1) / 2; + } + + DramMr0 =(DramWr << (PCTL_MR_OP_BFO+1) ) | // write_recovery + (0 << PCTL_MR_OP_BFO ) | // dll + ((DramInfo->ModeReg->Mode0Cas >>1 ) << PCTL_MR_CAS_BFO ) | + (DramInfo->ModeReg->BstType << PCTL_MR_BT_BFO ) | + ((DramInfo->ModeReg->Mode0Cas & 0x1) << 2 ) | + DramMr0; + + CrTrtwT = (CasRdT + 6) - CasWr; + + } // ddr2/ddr3 + else if ((DramInfo->Dev->DeviceType) == DRAM_SDR) { + DdrType = DRAM_SDR; + if (DramInfo->ModeReg->BstLen == BST_LEN_4) { + DramMr0 = 2; // bst_4 + CsBstLen = 0; //bst_4 + CasRd = 0x2; + } + else { // BST_LEN_8 + DramMr0 = 3; // bst_8 + CsBstLen = 1; // bst_8 + CasRd = 0x3; + } + + CasWr = 0; + + DramMr0 =(CasRd << PCTL_MR_CAS_BFO) | + (DramInfo->ModeReg->BstType << PCTL_MR_BT_BFO ) | + DramMr0; + + CrTrtwT = 0; // tic: CasRd + rd_rtw + rd_pipe + } // SDR + + + // countting tRTW + if ((CrTrtwT & 0x1)) { + CrTrtw = (CrTrtwT+1) /(DfiRate); + } + else { + CrTrtw = CrTrtwT /(DfiRate); + } + + DqWidth = (DramInfo->Dev->DqWidth); + Page = DramInfo->Dev->ColAddrWth +1; // DQ16 -> memory:byte_unit *2 + if (DqWidth == DRAM_DQ_32) { // paralle dq_16 => Page + 1 + Page = Page +1; + } +#if 1 + + // WRAP_MISC setting + HAL_SDR_WRITE32(REG_SDR_MISC,( + (Page << WRAP_MISC_PAGE_SIZE_BFO) | + (DramInfo->Dev->Bank << WRAP_MISC_BANK_SIZE_BFO) | + (CsBstLen << WRAP_MISC_BST_SIZE_BFO ) | + (DqWidth << WRAP_MISC_DDR_PARAL_BFO) + )); + // PCTL setting + HAL_SDR_WRITE32(REG_SDR_DCR,( + (0x2 << PCTL_DCR_DFI_RATE_BFO) | + (DqWidth << PCTL_DCR_DQ32_BFO ) | + (DdrType << PCTL_DCR_DDR3_BFO ) + )); + + HAL_SDR_WRITE32(REG_SDR_IOCR,( + ((CasRd -4)/(DfiRate) << PCTL_IOCR_TPHY_RD_EN_BFO ) | + (0 << PCTL_IOCR_TPHY_WL_BFO ) | + (((CasWr -3)/(DfiRate)) << PCTL_IOCR_TPHY_WD_BFO ) | + (0 << PCTL_IOCR_RD_PIPE_BFO ) + )); + + if ((DramInfo->Dev->DeviceType) != SDR) { // DDR2/3 + HAL_SDR_WRITE32(REG_SDR_EMR2,DramEmr2); + HAL_SDR_WRITE32(REG_SDR_EMR1,( + (1 << 2 ) | //RTT + (1 << 1 ) | //D.I.C + (DramInfo->ModeReg->Mode1DllEnN ) + )); + } // DDR2/3 + + HAL_SDR_WRITE32(REG_SDR_MR,DramMr0); + + HAL_SDR_WRITE32(REG_SDR_DRR, ( + (0 << PCTL_DRR_REF_DIS_BFO) | + (9 << PCTL_DRR_REF_NUM_BFO) | + ((((DramInfo->Timing->TrefiPs)/DrmaPeriod)+1) << PCTL_DRR_TREF_BFO ) | + ((((DramInfo->Timing->TrfcPs)/DrmaPeriod)+1) << PCTL_DRR_TRFC_BFO ) + )); + + HAL_SDR_WRITE32(REG_SDR_TPR0,( + ((((DramInfo->Timing->TrtpTck)/DfiRate)+1) << PCTL_TPR0_TRTP_BFO) | + (CrTwr << PCTL_TPR0_TWR_BFO ) | + ((((DramInfo->Timing->TrasPs)/DrmaPeriod)+1) << PCTL_TPR0_TRAS_BFO) | + ((((DramInfo->Timing->TrpPs)/DrmaPeriod)+1) << PCTL_TPR0_TRP_BFO ) + )); + + HAL_SDR_WRITE32(REG_SDR_TPR1, ( + (CrTrtw << PCTL_TPR1_TRTW_BFO) | + ((((DramInfo->Timing->TwtrTck)/DfiRate)+3) << PCTL_TPR1_TWTR_BFO) | + ((((DramInfo->Timing->TccdTck)/DfiRate)+1) << PCTL_TPR1_TCCD_BFO) | + ((((DramInfo->Timing->TrcdPs)/DrmaPeriod)+1) << PCTL_TPR1_TRCD_BFO) | + ((((DramInfo->Timing->TrcPs)/DrmaPeriod)+1) << PCTL_TPR1_TRC_BFO ) | + (((DramInfo->Timing->TrrdTck/DfiRate)+1) << PCTL_TPR1_TRRD_BFO) + )); + + HAL_SDR_WRITE32(REG_SDR_TPR2, ( + (DramInfo->Timing->TmrdTck << PCTL_TPR2_TMRD_BFO ) | + (0 << PCTL_TPR2_INIT_NS_EN_BFO ) | + (2 << PCTL_TPR2_INIT_REF_NUM_BFO) + )); + + // set all_mode _idle + HAL_SDR_WRITE32(REG_SDR_CSR,0x700); + + // start to init + HAL_SDR_WRITE32(REG_SDR_CCR,0x01); + while ((HAL_SDR_READ32(REG_SDR_CCR)& 0x1) == 0x0); + + // enter mem_mode + HAL_SDR_WRITE32(REG_SDR_CSR,0x600); +#else + // WRAP_MISC setting + ms_ctrl_0_map->misc = //0x12; + ( + (Page << WRAP_MISC_PAGE_SIZE_BFO) | + (DramInfo->Dev->Bank << WRAP_MISC_BANK_SIZE_BFO) | + (CsBstLen << WRAP_MISC_BST_SIZE_BFO ) | + (DqWidth << WRAP_MISC_DDR_PARAL_BFO) + ); + // PCTL setting + ms_ctrl_0_map->dcr = //0x208; + ( + (0x2 << PCTL_DCR_DFI_RATE_BFO) | + (DqWidth << PCTL_DCR_DQ32_BFO ) | + (DdrType << PCTL_DCR_DDR3_BFO ) + ); + + ms_ctrl_0_map->iocr = ( + ((CasRd -4)/(DfiRate) << PCTL_IOCR_TPHY_RD_EN_BFO ) | + (0 << PCTL_IOCR_TPHY_WL_BFO ) | + (((CasWr -3)/(DfiRate)) << PCTL_IOCR_TPHY_WD_BFO ) | + (0 << PCTL_IOCR_RD_PIPE_BFO ) + ); + + if ((DramInfo->Dev->DeviceType) != SDR) { // DDR2/3 + ms_ctrl_0_map->emr2 = DramEmr2; + + ms_ctrl_0_map->emr1 = ( + (1 << 2 ) | //RTT + (1 << 1 ) | //D.I.C + (DramInfo->ModeReg->Mode1DllEnN ) + ); + } // DDR2/3 + + ms_ctrl_0_map->mr = DramMr0; + + ms_ctrl_0_map->drr = ( + (0 << PCTL_DRR_REF_DIS_BFO) | + (9 << PCTL_DRR_REF_NUM_BFO) | + ((((DramInfo->Timing->TrefiPs)/DrmaPeriod)+1)<< PCTL_DRR_TREF_BFO ) | + ((((DramInfo->Timing->TrfcPs)/DrmaPeriod)+1) << PCTL_DRR_TRFC_BFO ) + ); + + ms_ctrl_0_map->tpr0= ( + ((((DramInfo->Timing->TrtpTck)/DfiRate)+1) << PCTL_TPR0_TRTP_BFO) | + (CrTwr << PCTL_TPR0_TWR_BFO ) | + ((((DramInfo->Timing->TrasPs)/DrmaPeriod)+1) << PCTL_TPR0_TRAS_BFO) | + ((((DramInfo->Timing->TrpPs)/DrmaPeriod)+1) << PCTL_TPR0_TRP_BFO ) + ); + + ms_ctrl_0_map->tpr1= ( + (CrTrtw << PCTL_TPR1_TRTW_BFO) | + ((((DramInfo->Timing->TwtrTck)/DfiRate)+3) << PCTL_TPR1_TWTR_BFO) | + ((((DramInfo->Timing->TccdTck)/DfiRate)+1) << PCTL_TPR1_TCCD_BFO) | + ((((DramInfo->Timing->TrcdPs)/DrmaPeriod)+1) << PCTL_TPR1_TRCD_BFO) | + ((((DramInfo->Timing->TrcPs)/DrmaPeriod)+1) << PCTL_TPR1_TRC_BFO ) | + (((DramInfo->Timing->TrrdTck/DfiRate)+1) << PCTL_TPR1_TRRD_BFO) + ); + + ms_ctrl_0_map->tpr2= ( + (DramInfo->Timing->TmrdTck << PCTL_TPR2_TMRD_BFO ) | + (0 << PCTL_TPR2_INIT_NS_EN_BFO ) | + (2 << PCTL_TPR2_INIT_REF_NUM_BFO) + ); + // set all_mode _idle + ms_ctrl_0_map->csr = 0x700; + + // start to init + ms_ctrl_0_map->ccr = 0x1; + while (((ms_ctrl_0_map->ccr)& 0x1) == 0x0); + + // enter mem_mode + ms_ctrl_0_map->csr= 0x600; +#endif +} // DramInit + + //3 +extern void * +_memset( void *s, int c, SIZE_T n ); + +HAL_SDRC_TEXT_SECTION +u32 +SdrCalibration( + VOID +) +{ +#ifdef FPGA +#ifdef FPGA_TEMP +// u32 Value32; +#endif +#else +// u32 Value32; +#endif + u32 RdPipe = 0, TapCnt = 0, Pass = 0, AvaWdsCnt = 0; + u32 RdPipeCounter, RecNum[2], RecRdPipe[2];//, AvaWds[2][REC_NUM]; + BOOL RdPipeFlag, PassFlag = 0, Result; + + Result = _FALSE; + +#ifdef SUPPORT_DRAM_KED + // read calibration data from system data 0x5d~0x6c + SPIC_INIT_PARA SpicInitPara; + u32 valid; + union { u8 b[4]; u32 l;} value; + u32 CpuType = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70)) >> 4); + + valid = RdPipe = TapCnt = 0xFFFFFFFF; + value.l = HAL_READ32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType); + if((value.b[0]^value.b[1])==0xFF) + valid = value.b[0]; + //DiagPrintf("dump1 %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]); + value.l = HAL_READ32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType+4); + if((value.b[0]^value.b[1])==0xFF) + RdPipe = value.b[0]; + if((value.b[2]^value.b[3])==0xFF) + TapCnt = value.b[2]; + //DiagPrintf("dump2 %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]); + + if((valid==1)&&(RdPipe!=0xFFFFFFFF)&&(TapCnt!=0xFFFFFFFF)){ + // wait DRAM settle down + HalDelayUs(10); + // load previous dram Ked data + HAL_SDR_WRITE32(REG_SDR_IOCR, ((HAL_SDR_READ32(REG_SDR_IOCR) & 0xff) | (RdPipe << PCTL_IOCR_RD_PIPE_BFO))); + SDR_DDL_FCTRL(TapCnt); + if(MemTest(3)) + return _TRUE; + } +#endif + + _memset((u8*)AvaWds, 0, sizeof(u32)*REC_NUM*2); + + volatile struct ms_rxi310_portmap *ms_ctrl_0_map; + ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE; + ms_ctrl_0_map = ms_ctrl_0_map; + PassFlag = PassFlag; + RdPipeCounter =0; + +// DBG_8195A("%d\n",__LINE__); + + for(RdPipe=MIN_RD_PIPE; RdPipe<=MAX_RD_PIPE; RdPipe++) { +// ms_ctrl_0_map->iocr = (ms_ctrl_0_map->iocr & 0xff) | (RdPipe << PCTL_IOCR_RD_PIPE_BFO); + HAL_SDR_WRITE32(REG_SDR_IOCR, ((HAL_SDR_READ32(REG_SDR_IOCR) & 0xff) | (RdPipe << PCTL_IOCR_RD_PIPE_BFO))); + + DBG_SDR_INFO("IOCR: 0x%x; Write: 0x%x\n",HAL_SDR_READ32(REG_SDR_IOCR), (RdPipe << PCTL_IOCR_RD_PIPE_BFO)); +// DBG_8195A("IOCR: 0x%x; Write: 0x%x\n",ms_ctrl_0_map->iocr, (RdPipe << PCTL_IOCR_RD_PIPE_BFO)); + + RdPipeFlag = _FALSE; + PassFlag = _FALSE; + AvaWdsCnt = 0; + + for(TapCnt=0; TapCnt < (MAX_TAP_DLY+1); TapCnt++) { + // Modify clk delay +#ifdef FPGA +#ifdef FPGA_TEMP + SDR_DDL_FCTRL(TapCnt); +// Value32 = (RD_DATA(SDR_CLK_DLY_CTRL) & 0xFF00FFFF); +// Value32 = (Value32 | (TapCnt << 16)); +// WR_DATA(SDR_CLK_DLY_CTRL, Value32); +#else + HAL_SDR_WRITE32(REG_SDR_DLY0, TapCnt); +// ms_ctrl_0_map->phy_dly0 = TapCnt; +#endif + DBG_SDR_INFO("DLY: 0x%x; Write: 0x%x\n",HAL_PERI_ON_READ32(REG_PESOC_MEM_CTRL), TapCnt); +#else + SDR_DDL_FCTRL(TapCnt); +// Value32 = (RD_DATA(SDR_CLK_DLY_CTRL) & 0xFF00FFFF); +// Value32 = (Value32 | (TapCnt << 16)); +// WR_DATA(SDR_CLK_DLY_CTRL, Value32); +#endif + + Pass = MemTest(10000); + PassFlag = _FALSE; + + if(Pass==_TRUE) { // PASS + + if (!RdPipeFlag) { + DBG_SDR_INFO("%d Time Pass\n", RdPipeCounter); + RdPipeCounter++; + RdPipeFlag = _TRUE; + RecRdPipe[RdPipeCounter - 1] = RdPipe; + } + + AvaWds[RdPipeCounter-1][AvaWdsCnt] = TapCnt; + AvaWdsCnt++; + + RecNum[RdPipeCounter-1] = AvaWdsCnt; + + if((TapCnt+TAP_DLY)>=MAX_TAP_DLY) { + break; + } + + PassFlag = _TRUE; + + DBG_SDR_INFO("Verify Pass => RdPipe:%d; TapCnt: %d\n", RdPipe, TapCnt); + + } + else { // FAIL +// if(PassFlag==_TRUE) { +// break; +// } +// else { + if (RdPipeCounter > 0) { + RdPipeCounter++; + if (RdPipeCounter < 3) { + RecNum[RdPipeCounter-1] = 0; + RecRdPipe[RdPipeCounter - 1] = RdPipe; + } + break; + } +// } + } + } + + + if (RdPipeCounter > 2) { + u8 BestRangeIndex, BestIndex; + + #ifdef CONFIG_SDR_VERIFY //to reduce log + u32 i; + DBG_SDR_INFO("Avaliable RdPipe 0\n"); + + for (i=0;i<256;i++) { + DBG_SDR_INFO("%d\n", AvaWds[0][i]); + } + DBG_SDR_INFO("Avaliable RdPipe 1\n"); + for (i=0;i<256;i++) { + DBG_SDR_INFO("%d\n", AvaWds[1][i]); + } + #endif + + DBG_SDR_INFO("Rec 0 => total counter %d; RdPipe:%d;\n", RecNum[0], RecRdPipe[0]); + DBG_SDR_INFO("Rec 1 => total counter %d; RdPipe:%d;\n", RecNum[1], RecRdPipe[1]); + + BestRangeIndex = (RecNum[0] > RecNum[1]) ? 0 : 1; + + BestIndex = RecNum[BestRangeIndex]>>1; + + DBG_SDR_INFO("The Finial RdPipe: %d; TpCnt: 0x%x\n", RecRdPipe[BestRangeIndex], AvaWds[BestRangeIndex][BestIndex]); + + // set RdPipe and tap_dly +// ms_ctrl_0_map->iocr = (ms_ctrl_0_map->iocr & 0xff) | (RecRdPipe[BestRangeIndex] << PCTL_IOCR_RD_PIPE_BFO); + HAL_SDR_WRITE32(REG_SDR_IOCR, ((HAL_SDR_READ32(REG_SDR_IOCR) & 0xff) | (RecRdPipe[BestRangeIndex] << PCTL_IOCR_RD_PIPE_BFO))); + +#ifdef FPGA +#ifdef FPGA_TEMP + SDR_DDL_FCTRL(AvaWds[BestRangeIndex][BestIndex]); + +// Value32 = (RD_DATA(SDR_CLK_DLY_CTRL) & 0xFF00FFFF); +// Value32 = Value32 | (AvaWds[BestRangeIndex][BestIndex] << 16); +// WR_DATA(SDR_CLK_DLY_CTRL, Value32); +#else + HAL_SDR_WRITE32(REG_SDR_DLY0, AvaWds[BestRangeIndex][BestIndex]); +// ms_ctrl_0_map->phy_dly0 = AvaWds[BestRangeIndex][BestIndex]; +#endif +#else + SDR_DDL_FCTRL(AvaWds[BestRangeIndex][BestIndex]); +// Value32 = (RD_DATA(SDR_CLK_DLY_CTRL) & 0xFF00FFFF); +// Value32 = Value32 | (AvaWds[BestRangeIndex][BestIndex] << 16); +// WR_DATA(SDR_CLK_DLY_CTRL, Value32); +#endif + #ifdef SUPPORT_DRAM_KED + RdPipe = RecRdPipe[BestRangeIndex]; + TapCnt = AvaWds[BestRangeIndex][BestIndex]; + + value.b[0] = (u8)RdPipe; + value.b[1] = ~value.b[0]; + value.b[2] = (u8)TapCnt; + value.b[3] = ~value.b[2]; + //DiagPrintf("dump1w %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]); + HAL_WRITE32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType+4, value.l); + SpicWaitWipDoneRefinedRtl8195A(SpicInitPara); + + valid = 1; + value.b[0] = (u8)valid; + value.b[1] = ~value.b[0]; + value.b[2] = 0xFF; + value.b[3] = 0xFF; + //DiagPrintf("dump1w %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]); + HAL_WRITE32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType, value.l); + SpicWaitWipDoneRefinedRtl8195A(SpicInitPara); + #endif + Result = _TRUE; + break; + } + + if (RdPipeCounter == 0) { + + DBG_SDR_INFO("NOT Find RdPipe\n"); + } + } + + return Result; +} // SdrCalibration + + + + +HAL_SDRC_TEXT_SECTION +VOID +ChangeRandSeed( + IN u32 Seed +) +{ + rand_x = Seed; +} + +HAL_SDRC_TEXT_SECTION +u32 +Sdr_Rand2( + VOID +) +{ + HAL_RAM_DATA_SECTION static unsigned int y = 362436; + + HAL_RAM_DATA_SECTION static unsigned int z = 521288629; + + HAL_RAM_DATA_SECTION static unsigned int c = 7654321; + + unsigned long long t, a= 698769069; + + rand_x = 69069 * rand_x + 12345; + y ^= (y << 13); y ^= (y >> 17); y ^= (y << 5); + t = a * z + c; c = (t >> 32); z = t; + + return rand_x + y + z; +} + +HAL_SDRC_TEXT_SECTION +s32 +MemTest( + u32 LoopCnt +) +{ + u32 LoopIndex = 0; + u32 Value32, Addr; + for (LoopIndex = 0; LoopIndex 0x%x != 0x%x\n",LoopIndex, + Addr, Value32, HAL_SDRAM_READ32(Addr)); + return _FALSE; + } + else { + // HAL_SDRAM_WRITE32(Addr, 0); + } + } + return _TRUE; + +} // MemTest + +#endif // end of "#ifdef CONFIG_SDR_EN" diff --git a/lib/fwlib/src/hal_soc_ps_monitor.c b/lib/fwlib/src/hal_soc_ps_monitor.c new file mode 100644 index 0000000..2777912 --- /dev/null +++ b/lib/fwlib/src/hal_soc_ps_monitor.c @@ -0,0 +1,3449 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ +#include "rtl8195a.h" +#include "hal_soc_ps_monitor.h" + +#include "PinNames.h" +#include "gpio_api.h" + + +#ifdef CONFIG_SOC_PS_MODULE +extern VOID UartLogIrqHandleRam(VOID * Data); +#if defined (__ICCARM__) +extern void xPortPendSVHandler( void ); +#elif defined (__GNUC__) +extern void xPortPendSVHandler( void ) __attribute__ (( naked )); +#endif +extern void xPortSysTickHandler( void ); +extern void vPortSVCHandler( void ); +extern u32 HalGetCpuClk(VOID); +extern _LONG_CALL_ u32 HalDelayUs(u32 us); + +extern COMMAND_TABLE UartLogRomCmdTable[]; +extern HAL_TIMER_OP HalTimerOp; +extern u32 STACK_TOP; // which is defined in vectors.s + +SYS_ADAPTER SYSAdapte; + +Power_Mgn PwrAdapter; + +VOID ReFillCpuClk(VOID); +extern u8 __ram_start_table_start__[]; + +u32 +PatchHalLogUartInit( + IN LOG_UART_ADAPTER UartAdapter +) +{ + u32 SetData; + u32 Divisor; + u32 Dlh; + u32 Dll; + u32 SysClock; + + /* + Interrupt enable Register + 7: THRE Interrupt Mode Enable + 2: Enable Receiver Line Status Interrupt + 1: Enable Transmit Holding Register Empty Interrupt + 0: Enable Received Data Available Interrupt + */ + // disable all interrupts + HAL_UART_WRITE32(UART_INTERRUPT_EN_REG_OFF, 0); + + /* + Line Control Register + 7: DLAB, enable reading and writing DLL and DLH register, and must be cleared after + initial baud rate setup + 3: PEN, parity enable/disable + 2: STOP, stop bit + 1:0 DLS, data length + */ + + // set DLAB bit to 1 + HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, 0x80); + + // set up buad rate division + +#if 0//def CONFIG_FPGA + SysClock = SYSTEM_CLK; + Divisor = (SysClock / (16 * (UartAdapter.BaudRate))); +#else + { + u32 SampleRate,Remaind; + + SysClock = (HalGetCpuClk()>>2); + + SampleRate = (16 * (UartAdapter.BaudRate)); + + Divisor= SysClock/SampleRate; + + Remaind = ((SysClock*10)/SampleRate) - (Divisor*10); + + if (Remaind>4) { + Divisor++; + } + } +#endif + + + Dll = Divisor & 0xff; + Dlh = (Divisor & 0xff00)>>8; + HAL_UART_WRITE32(UART_DLL_OFF, Dll); + HAL_UART_WRITE32(UART_DLH_OFF, Dlh); + + // clear DLAB bit + HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, 0); + + // set data format + SetData = UartAdapter.Parity | UartAdapter.Stop | UartAdapter.DataLength; + HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, SetData); + + /* FIFO Control Register + 7:6 level of receive data available interrupt + 5:4 level of TX empty trigger + 2 XMIT FIFO reset + 1 RCVR FIFO reset + 0 FIFO enable/disable + */ + // FIFO setting, enable FIFO and set trigger level (2 less than full when receive + // and empty when transfer + HAL_UART_WRITE32(UART_FIFO_CTL_REG_OFF, UartAdapter.FIFOControl); + + /* + Interrupt Enable Register + 7: THRE Interrupt Mode enable + 2: Enable Receiver Line status Interrupt + 1: Enable Transmit Holding register empty INT32 + 0: Enable received data available interrupt + */ + HAL_UART_WRITE32(UART_INTERRUPT_EN_REG_OFF, UartAdapter.IntEnReg); + + if (UartAdapter.IntEnReg) { + // Enable Peripheral_IRQ Setting for Log_Uart + HAL_WRITE32(VENDOR_REG_BASE, PERIPHERAL_IRQ_EN, 0x1000000); + + // Enable ARM Cortex-M3 IRQ + NVIC_SetPriorityGrouping(0x3); + NVIC_SetPriority(PERIPHERAL_IRQ, 14); + NVIC_EnableIRQ(PERIPHERAL_IRQ); + } + + + return 0; +} + + +VOID +PSHalInitPlatformLogUart( + VOID +) +{ + IRQ_HANDLE UartIrqHandle; + LOG_UART_ADAPTER UartAdapter; + + //4 Release log uart reset and clock + LOC_UART_FCTRL(OFF); + LOC_UART_FCTRL(ON); + ACTCK_LOG_UART_CCTRL(ON); + + PinCtrl(LOG_UART,S0,ON); + + //4 Register Log Uart Callback function + UartIrqHandle.Data = (u32)NULL;//(u32)&UartAdapter; + UartIrqHandle.IrqNum = UART_LOG_IRQ; + UartIrqHandle.IrqFun = (IRQ_FUN) UartLogIrqHandleRam; + UartIrqHandle.Priority = 0; + + //4 Inital Log uart + UartAdapter.BaudRate = UART_BAUD_RATE_38400; + UartAdapter.DataLength = UART_DATA_LEN_8BIT; + UartAdapter.FIFOControl = 0xC1; + UartAdapter.IntEnReg = 0x00; + UartAdapter.Parity = UART_PARITY_DISABLE; + UartAdapter.Stop = UART_STOP_1BIT; + + //4 Initial Log Uart + PatchHalLogUartInit(UartAdapter); + + //4 Register Isr handle + InterruptRegister(&UartIrqHandle); + + UartAdapter.IntEnReg = 0x05; + + //4 Initial Log Uart for Interrupt + PatchHalLogUartInit(UartAdapter); + + //4 initial uart log parameters before any uartlog operation + //RtlConsolInit(ROM_STAGE,GetRomCmdNum(),(VOID*)&UartLogRomCmdTable);// executing boot seq., + //pUartLogCtl->TaskRdy = 1; +} + + +#ifdef CONFIG_SDR_EN +VOID +SDRWakeUp( + VOID +){ + ACTCK_SDR_CCTRL(ON); + SDR_PIN_FCTRL(ON); + HalDelayUs(10); + HAL_WRITE32(0x40005000, 0x34, 0x3); + HAL_WRITE32(0x40005000, 0x10, HAL_READ32(0x40005000, 0x10)&(~BIT28)); +} + +VOID +SDRSleep( + VOID +){ + gpio_t gpio_obj; + + HAL_WRITE32(0x40005000, 0X10, HAL_READ32(0x40005000, 0x10)|BIT28); + ACTCK_SDR_CCTRL(OFF); + gpio_init(&gpio_obj, PG_1); + gpio_mode(&gpio_obj, PullUp); + gpio_dir(&gpio_obj, PIN_OUTPUT); + gpio_write(&gpio_obj, GPIO_PIN_HIGH); + + gpio_init(&gpio_obj, PG_2); + gpio_mode(&gpio_obj, PullDown); + gpio_dir(&gpio_obj, PIN_OUTPUT); + gpio_write(&gpio_obj, GPIO_PIN_LOW); + + gpio_init(&gpio_obj, PG_3); + gpio_mode(&gpio_obj, PullDown); + gpio_dir(&gpio_obj, PIN_OUTPUT); + gpio_write(&gpio_obj, GPIO_PIN_LOW); + + gpio_init(&gpio_obj, PG_4); + gpio_mode(&gpio_obj, PullDown); + gpio_dir(&gpio_obj, PIN_OUTPUT); + gpio_write(&gpio_obj, GPIO_PIN_LOW); + + gpio_init(&gpio_obj, PJ_1); + gpio_mode(&gpio_obj, PullDown); + gpio_dir(&gpio_obj, PIN_OUTPUT); + gpio_write(&gpio_obj, GPIO_PIN_LOW); + + gpio_init(&gpio_obj, PJ_2); + gpio_mode(&gpio_obj, PullDown); + gpio_dir(&gpio_obj, PIN_OUTPUT); + gpio_write(&gpio_obj, GPIO_PIN_LOW); + + SDR_PIN_FCTRL(OFF); + HAL_WRITE32(0x40005000, 0x34, 0x1); + gpio_init(&gpio_obj, PJ_1); + gpio_mode(&gpio_obj, PullUp); + gpio_dir(&gpio_obj, PIN_OUTPUT); + gpio_write(&gpio_obj, GPIO_PIN_LOW); +} +#endif + +VOID +SYSIrqHandle +( + IN VOID *Data +) +{ + u32 Rtemp; + + //change cpu clk + ReFillCpuClk(); + HalDelayUs(100); + + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) | 0x40000000); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN, Rtemp); + + #ifdef CONFIG_SDR_EN + SDRWakeUp(); + #endif + + //disable DSTBY timer + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, 0); + + //clear wake event IMR + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0, 0); + + //clear wake event ISR + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_STATUS0); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_STATUS0, Rtemp); + + //set event flag + PwrAdapter.WakeEventFlag = _TRUE; +} + +VOID +InitSYSIRQ(VOID) +{ + IRQ_HANDLE SysHandle; + PSYS_ADAPTER pSYSAdapte; + pSYSAdapte = &SYSAdapte; + SysHandle.Data = (u32) (pSYSAdapte); + SysHandle.IrqNum = SYSTEM_ON_IRQ; + SysHandle.IrqFun = (IRQ_FUN) SYSIrqHandle; + SysHandle.Priority = 0; + + InterruptRegister(&SysHandle); + InterruptEn(&SysHandle); + PwrAdapter.WakeEventFlag = _FALSE; +} + +void vWFSSVCHandler( void ) +{ +#if defined (__ICCARM__) + // TODO: IAR has different way using assembly +#elif defined (__GNUC__) + asm volatile + ( + "svcing:\n" + " mov r0, %0 \n" + " ldmia r0!, {r4-r7} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " ldmia r0!, {r8-r11} \n" + " msr psp, r0 \n" /* Restore the task stack pointer. */ + " orr r14, #0xd \n" + " bx r14 \n" + ::"r"(PwrAdapter.CPUPSP):"r0" + ); +#endif +} + + +VOID +WakeFromSLPPG( + VOID +) +{ + //release shutdone + HAL_WRITE32(PERI_ON_BASE, REG_GPIO_SHTDN_CTRL, 0x7FF); + //HAL_WRITE32(PERI_ON_BASE, REG_CPU_PERIPHERAL_CTRL, 0x110001); + //JTAG rst pull high + HAL_WRITE32(PERI_ON_BASE, REG_GPIO_PULL_CTRL2, 0x05555556); + + ReFillCpuClk(); + + //3 Need Modify + VectorTableInitRtl8195A(0x1FFFFFFC); + + //3 Make PendSV, CallSV and SysTick the same priroity as the kernel. + HAL_WRITE32(0xE000ED00, 0x20, 0xF0F00000); + + //3 Initial Log Uart + PSHalInitPlatformLogUart(); + +#ifdef CONFIG_KERNEL + InterruptForOSInit((VOID*)vWFSSVCHandler, + (VOID*)xPortPendSVHandler, + (VOID*)xPortSysTickHandler); +#endif + //CPURegbackup[13] = CPURegbackup[13]-4; + PwrAdapter.CPURegbackup[16] |= 0x1000000 ; + + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-4) ) )= PwrAdapter.CPURegbackup[16]; //PSR + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-8) ) )= PwrAdapter.CPURegbackup[15]; //PC + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-12) ) )= PwrAdapter.CPURegbackup[14]; //LR + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-16) ) )= PwrAdapter.CPURegbackup[12]; //R12 + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-20) ) )= PwrAdapter.CPURegbackup[3]; //R3 + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-24) ) )= PwrAdapter.CPURegbackup[2]; //R2 + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-28) ) )= PwrAdapter.CPURegbackup[1]; //R1 + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-32) ) )= PwrAdapter.CPURegbackup[0]; //R0 + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-36) ) )= PwrAdapter.CPURegbackup[11]; //R11 + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-40) ) )= PwrAdapter.CPURegbackup[10]; //R10 + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-44) ) )= PwrAdapter.CPURegbackup[9]; //R9 + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-48) ) )= PwrAdapter.CPURegbackup[8]; //R8 + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-52) ) )= PwrAdapter.CPURegbackup[7]; //R7 + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-56) ) )= PwrAdapter.CPURegbackup[6]; //R6 + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-60) ) )= PwrAdapter.CPURegbackup[5]; //R5 + ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[13]-64) ) )= PwrAdapter.CPURegbackup[4]; //R4 + PwrAdapter.CPURegbackup[13] = PwrAdapter.CPURegbackup[13]-64; //PSP + PwrAdapter.CPUPSP = PwrAdapter.CPURegbackup[13]; + //CPURegBackUp(); + + asm volatile( + " cpsie i \n" /* Globally enable interrupts. */ + " svc 0 \n" /* System call to start first task. */ + " nop \n" + ); +} + +VOID +DurationScaleAndPeriodOP( + IN u32 SDuration, + OUT u32 *ScaleTemp, + OUT u32 *PeriodTemp +) +{ + u8 Idx = 0; + if (SDuration > 8355){ + SDuration = 0x20A3; + } + + //in unit 128us + SDuration = ((SDuration*125)/16); + + for (Idx = 8; Idx < 32; Idx++) { + + if ( (SDuration & 0xFFFFFF00) > 0 ) { + (*ScaleTemp) = (*ScaleTemp) + 1; + SDuration = (SDuration >> 1); + } + else { + break; + } + } + + *ScaleTemp = ((*ScaleTemp) << 8); + *PeriodTemp = SDuration; +} + + +u32 +CLKCal( + IN u8 ClkSel +) +{ + u32 Rtemp = 0; + u32 RRTemp = 0; + + if( ClkSel ){ + //a33_ck + Rtemp |= 0x10000; + } + + //Enable cal + Rtemp |= 0x800000; + HAL_WRITE32(VENDOR_REG_BASE, REG_VDR_ANACK_CAL_CTRL, Rtemp); + + while( (HAL_READ32(VENDOR_REG_BASE, REG_VDR_ANACK_CAL_CTRL) & BIT23) != 0 ); + Rtemp = ((HAL_READ32(VENDOR_REG_BASE, REG_VDR_ANACK_CAL_CTRL) & 0x3FFF))+1; + + if( ClkSel ){ + //a33_ck + RRTemp = (Rtemp); + } + else { + //anack + RRTemp = ((2133/Rtemp) - 1); + } + + //DiagPrintf("CAL : 0x%x\n", RRTemp); + + return RRTemp; +} + +VOID +BackupCPUClk( + VOID +) +{ + u32 Cpubp; + Cpubp = (HAL_READ32(SYSTEM_CTRL_BASE,REG_SYS_DSTBY_INFO0)&0xFFFFFFF0); + Cpubp |= ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70)) >> 4); + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SYS_DSTBY_INFO0,Cpubp); +} + +VOID +ReFillCpuClk( + VOID +) +{ + u8 CpuClk = ((u8)(HAL_READ32(SYSTEM_CTRL_BASE,REG_SYS_DSTBY_INFO0)& (0xF))); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1, + ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (~0x70)) + |(CpuClk << 4))); +} + +VOID +SleepClkGatted( + IN u32 SDuration +) +{ + u32 Rtemp = 0; + u32 ScaleTemp = 0; + u32 PeriodTemp = 0; + u32 CalTemp = 0; + + //Backup CPU CLK + BackupCPUClk(); + + //truncate duration + SDuration &= 0x0003FFFC; + //2 CSleep + //3 1.1 Set TU timer timescale + //0x4000_0090[21:16] = 6'h1F + //0x4000_0090[15] = 1'b0 => Disable timer + CalTemp = (CLKCal(ANACK) << 16); + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL)& 0xffff7fff & 0xffc0ffff) | CalTemp); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); + + //0x4000_0090[11:8] => Time scale + //0x4000_0090[7:0] => Time period + //max duration 0x7FFFFF us, min 0x80 + DurationScaleAndPeriodOP(SDuration, &ScaleTemp, &PeriodTemp); + + Rtemp = (((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL) & 0xfffff000) | ScaleTemp) | PeriodTemp); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); + + //0x4000_0090[15] = 1'b1 => Enable timer + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL) | 0x00008000; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); + + //3 1.2 Configure platform wake event + //0x4000_0100[0] = 1'b1 => Enable timer and GT as wakeup event to wakeup CPU + Rtemp = 0x00000001; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0, Rtemp); + + //3 1.3 Configure power state option: + // 1.4.3 0x120[15:8]: sleep power mode option0 [11] = 1 + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION) & 0xffff00ff) | 0x74000A00);//A + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp); + + // 1.4.4 0x124[7:0]: sleep power mode option1 [0] =1 + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION_EXT) & 0xffffff00) | 0x00000001); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION_EXT, Rtemp); + + //3 1.5 Enable low power mode + // 1.5.1 0x4000_0118[2] = 1 => for sleep mode + Rtemp = 0x00000004;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000004; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); + + //3 1.6 Wait CHIP enter low power mode + // 1.7 Wait deep standby timer timeout + // 1.8 Wait CHIP resume to norm power mode + HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL); + __WFI(); + +} + + +VOID SleepPwrGatted( + IN u32 SDuration +) +{ + u32 Rtemp = 0; + u32 ScaleTemp = 0; + u32 PeriodTemp = 0; + u32 CalTemp = 0; + + //Backup CPU CLK + BackupCPUClk(); + + //truncate duration + SDuration &= 0x0003FFFC; + + //2 PSleep + //3 1.1 Set TU timer timescale + //0x4000_0090[21:16] = 6'h1F + //0x4000_0090[15] = 1'b0 => Disable timer + CalTemp = (CLKCal(ANACK) << 16); + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL)& 0xffff7fff & 0xffc0ffff) | CalTemp); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); + + //0x4000_0090[11:8] => Time scale + //0x4000_0090[7:0] => Time period + //max duration 0x7FFFFF us, min 0x80 + DurationScaleAndPeriodOP(SDuration, &ScaleTemp, &PeriodTemp); + + Rtemp = (((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL) & 0xfffff000) | ScaleTemp) | PeriodTemp); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); + + //0x4000_0090[15] = 1'b1 => Enable timer + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL) | 0x00008000; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); + + //3 1.2 Configure platform wake event + //0x4000_0100[0] = 1'b1 => Enable timer and GT as wakeup event to wakeup CPU + Rtemp = 0x00000003; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0, Rtemp); + + //3 1.4 Configure power state option: + // 1.4.3 0x120[15:8]: sleep power mode option0: + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION) & 0x00ff00ff) | 0x74000000); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp); + + // 1.4.4 0x124[7:0]: sleep power mode option1: + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION_EXT) & 0xffffff00) | 0x00000003); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION_EXT, Rtemp); + + //3 1.5 Enable low power mode + // 1.5.1 0x4000_0118[2] = 1 => for sleep mode + Rtemp = 0x00000004;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000004; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); + + //3 1.6 Wait CHIP enter low power mode + // 1.7 Wait deep standby timer timeout + // 1.8 Wait CHIP resume to norm power mode + HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL); + __WFI(); + DiagPrintf("YOU CAN'T SEE ME ~~~~!!!!!!!!!!!!!!!!!!!~~~~~slppg~~~~!!!!!!!!!!"); +} + + +VOID +DStandby( + IN u32 SDuration +) +{ + u32 Rtemp = 0; + u32 ScaleTemp = 0; + u32 PeriodTemp = 0; + u32 CalTemp = 0; + + //Backup CPU CLK + BackupCPUClk(); + + //Clear A33 timer event + //Rtemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SOC_SYSON_SLP_WAKE_EVENT_STATUS0); + //HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SOC_SYSON_SLP_WAKE_EVENT_STATUS0, Rtemp); + + //2 Deep Standby mode + //3 1.1 Set TU timer timescale + //0x4000_0090[21:16] = 6'h1F + //0x4000_0090[15] = 1'b0 => Disable timer + CalTemp = (CLKCal(ANACK) << 16); + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL)& 0xffff7fff & 0xffc0ffff) | CalTemp); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); + + //0x4000_0090[11:8] => Time scale + //0x4000_0090[7:0] => Time period + //max duration 0x7FFFFF us, min 0x80 + DurationScaleAndPeriodOP(SDuration, &ScaleTemp, &PeriodTemp); + + Rtemp = (((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL) & 0xfffff000) | ScaleTemp) | PeriodTemp); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); + + //0x4000_0090[15] = 1'b1 => Enable timer + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL) | 0x00008000; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); + + //3 1.3 Configure platform wake event + // 1.3.1 0x4000_0100[0] = 1'b1 => Enable deep standby timer wakeup event to wakeup CPU + Rtemp = 0x00000001; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0, Rtemp); + + //3 1.4 Configure power state option: + // 1.4.4 0x120[7:0]: deep standby power mode option: + Rtemp = 0x74000000; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp); + + // 1.4.5 0x124[7:0]: sleep power mode option1 [0] =1 + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION_EXT) & 0xffffff00) | 0x00000001); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION_EXT, Rtemp); + + //3 1.5 Enable low power mode + // [0x4000_0118[1] = 1 => for deep standby mode] + Rtemp = 0x00000002; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); + + //3 1.6 Wait CHIP enter low power mode + // 1.7 Wait deep standby timer timeout + // 1.8 Wait CHIP resume to norm power mode + HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL); + __WFI(); + + DiagPrintf("YOU CAN'T SEE ME ~~~~!!!!!!!!!!!!!!!!!!!~~~~~~~~~~~~~~~!!!!!!!!!!"); +} + + +VOID +DSleep( + IN u32 SDuration +) +{ + u32 Rtemp = 0; + //u32 ScaleTemp = 0; + //u32 PeriodTemp = 0; + u32 UTemp = 0; + u32 MaxTemp = 0; + + u32 Reada335 = 0; + + //2 Deep Sleep mode: + //3 2.1 Set TU timer timescale + + //3 2.2 Configure deep sleep timer: + //2.2.1 Enable REGU access interface 0x4000_0094[31] = 1 + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) | 0x80000000); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.2 Calibration A33 CLK + UTemp = CLKCal(A33CK); + + //Calculate the max value base on the a33 duration + MaxTemp = 0x7FFFFF*0x100/100000*UTemp/100*0x80; + //DiagPrintf("MaxTemp : 0x%x\n", MaxTemp); + + if ( SDuration >= MaxTemp ) { + SDuration = 0x7FFFFF; + } + else { + //In unit of A33 CLK : max num is bounded by anaclk = 1.5k + SDuration = ((((SDuration)/UTemp)*25/16*25/16*125)); + //DiagPrintf("SDuration : 0x%x\n", SDuration); + } + + DiagPrintf("SDuration : 0x%x\n", SDuration); + + //3 2.2.2 Initialize deep sleep counter + //2.2.2.0 0x4000_0094[15:0] = 16'hD300 => Disable deep sleep counter + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x0000D300); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + //2.2.2.0.1 Clear event + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_WEVENT, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_WEVENT)); + //2.2.2.1 0x4000_0094[15:0] = 16'h9008 => set counter[7:0] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009000 | ((u8)SDuration)); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.2.2 0x4000_0094[15:0] = 16'h9100 => set counter[15:8] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009100 | ((u8)(SDuration >> 8))); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.2.3 0x4000_0094[15:0] = 16'h9200 => set counter[22:16] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009200 | ((u8)(SDuration >> 16))); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.2.4 0x4000_0094[15:0] = 16'hD380 => Enable deep sleep counter + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x0000D380); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + HalDelayUs(1000); + Reada335 = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CAL_CTRL); + DiagPrintf("a33 timer : 0x%x\n", Reada335); + + HalDelayUs(8000); + + //3 2.2.3 + //2.3 Enable low power mode: 0x4000_0118[0] = 1'b1; + Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); + + //2.4 Wait CHIP enter deep sleep mode + //2.5 Wait deep sleep counter timeout + HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL); + __WFI(); + + DiagPrintf("YOU CAN'T SEE ME ~~~~!!!!!!!!!!!!!!!!!!!~~~~~~~~~~~~~~~!!!!!!!!!!"); +} + +VOID +MSBackupProcess( + void +) +{ + + u8 i = 0; + + //backup main stack + for (i = 0; i < (MAX_BACKUP_SIZE-1); i++) { + PwrAdapter.MSPbackup[i] = HAL_READ32(0x1FFFFE00, (0x1FC - (i*4))); + } + + asm volatile + ( + "MRS r0, MSP\n" + "MOV %0, r0\n" + :"=r"(PwrAdapter.MSPbackup[MAX_BACKUP_SIZE-1]) + ::"memory" + ); +} + + +VOID +MSReFillProcess( + VOID +) +{ + u8 i = 0; + + for (i = 0; i < (MAX_BACKUP_SIZE-1); i++) { + + HAL_WRITE32(0x1FFFFE00, (0x1FC - (i*4)), PwrAdapter.MSPbackup[i]); + } + + asm volatile + ( + "MSR MSP, %0\n" + ::"r"(PwrAdapter.MSPbackup[MAX_BACKUP_SIZE-1]):"memory" + ); +} + + +VOID +SoCPSGPIOCtrl( + VOID +) +{ + HAL_WRITE32(PERI_ON_BASE,0x330,0x55555555); + HAL_WRITE32(PERI_ON_BASE,0x334,0x55555555); + HAL_WRITE32(PERI_ON_BASE,0x338,0x05555555); + HAL_WRITE32(PERI_ON_BASE,0x33c,0x55555555); + HAL_WRITE32(PERI_ON_BASE,0x340,0x55555555); + HAL_WRITE32(PERI_ON_BASE,0x344,0x55555555); + HAL_WRITE32(PERI_ON_BASE,0x348,0x55555555); + HAL_WRITE32(PERI_ON_BASE,0x320,0x0); +} + + +VOID +InitSoCPM( + VOID +) +{ + u8 Idx = 0; + PRAM_FUNCTION_START_TABLE pRamStartFun = (PRAM_FUNCTION_START_TABLE) __ram_start_table_start__; + + PwrAdapter.ActFuncCount = 0; + PwrAdapter.CurrentState = ACT; + for (Idx = 0; Idx < MAXSTATE; Idx++) { + PwrAdapter.PwrState[Idx].FuncIdx = 0xFF; + PwrAdapter.PwrState[Idx].PowerState = 0xFF; + } + PwrAdapter.SDREn = _FALSE; + InitSYSIRQ(); + pRamStartFun->RamWakeupFun = WakeFromSLPPG; +} + +u8 +ChangeSoCPwrState( + IN u8 RequestState, + IN u32 ReqCount +) +{ + + //DiagPrintf("Go to sleep"); + + while(1) { + + HalDelayUs(100); + + if (HAL_READ8(LOG_UART_REG_BASE,0x14)&BIT6){ + + break; + } + } + + switch (RequestState) { + + case ACT: + break; + + case WFE: + __WFE(); + break; + + case WFI: + __WFI(); + break; + + //case SNOOZE: + //break; + + case SLPCG: + SleepClkGatted(ReqCount); + break; + + case SLPPG: + //Resume jump to wakeup function + //HAL_WRITE32(PERI_ON_BASE, 0x218, (HAL_READ32(PERI_ON_BASE,0x218)|BIT31)); + + SoCPSGPIOCtrl(); + SleepPwrGatted(ReqCount); + break; + + case DSTBY: + SoCPSGPIOCtrl(); + DStandby(ReqCount); + break; + + case DSLP: + case INACT: + SoCPSGPIOCtrl(); + DSleep(ReqCount); + break; + } + return 0; +} + + +u32 +SoCPwrChk( + IN u8 ReqState, + OUT u8* FailfuncIdx, + OUT u8* FailState +) +{ + u8 Idx = 0; + u32 Result = _FALSE; + + if ( PwrAdapter.ActFuncCount ) { + + for (Idx = 0; Idx < PwrAdapter.ActFuncCount; Idx++) { + + if (PwrAdapter.PwrState[Idx].PowerState < ReqState) { + *FailfuncIdx = PwrAdapter.PwrState[Idx].FuncIdx; + *FailState = PwrAdapter.PwrState[Idx].PowerState; + Result = _FALSE; + break; + } + } + } + else { + *FailfuncIdx = PwrAdapter.PwrState[Idx].FuncIdx; + *FailState = PwrAdapter.PwrState[Idx].PowerState; + Result = _TRUE; + } + return Result; +} + + +VOID +RegPowerState( + REG_POWER_STATE RegPwrState +) +{ + u8 Idx; + u8 StateIdx = 0; + u8 FState = 0; + + for (Idx = 0; Idx < PwrAdapter.ActFuncCount; Idx++) { + if (PwrAdapter.PwrState[Idx].FuncIdx == RegPwrState.FuncIdx) { + StateIdx = Idx; + FState = _TRUE; + break; + } + } + + switch (RegPwrState.PwrState) { + + case INACT : + if (FState) { + for (Idx = StateIdx; Idx < PwrAdapter.ActFuncCount; Idx++) { + PwrAdapter.PwrState[Idx].FuncIdx = PwrAdapter.PwrState[Idx+1].FuncIdx; + PwrAdapter.PwrState[Idx].PowerState = PwrAdapter.PwrState[Idx+1].PowerState; + } + PwrAdapter.ActFuncCount--; + } + else { + } + break; + + default: + + if (FState) { + PwrAdapter.PwrState[StateIdx].PowerState = RegPwrState.PwrState; + } + else { + PwrAdapter.PwrState[PwrAdapter.ActFuncCount].FuncIdx = RegPwrState.FuncIdx; + PwrAdapter.PwrState[PwrAdapter.ActFuncCount].PowerState = RegPwrState.PwrState; + PwrAdapter.ActFuncCount++; + } + + break; + } + + //for debug + #if 0 + for (Idx = 0; Idx < PwrAdapter.ActFuncCount; Idx++) { + DiagPrintf("RegPwrIdx : %d \n", Idx); + DiagPrintf("FuncIdx : %d \n", PwrAdapter.PwrState[Idx].FuncIdx); + DiagPrintf("PowerState : 0x%x \n", PwrAdapter.PwrState[Idx].PowerState); + } + #endif +} + + +VOID +ReadHWPwrState( + IN u8 FuncIdx, + OUT u8* HwState +){ + + switch (FuncIdx){ + case UART0: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC0_EN) & BIT_PERI_UART0_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL0) & BIT_SOC_ACTCK_UART0_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case UART1: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC0_EN) & BIT_PERI_UART1_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL0) & BIT_SOC_ACTCK_UART1_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case UART2: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC0_EN) & BIT_PERI_UART2_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL0) & BIT_SOC_ACTCK_UART2_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case SPI0: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC0_EN) & BIT_PERI_SPI0_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL0) & BIT_SOC_ACTCK_SPI0_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case SPI1: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC0_EN) & BIT_PERI_SPI1_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL0) & BIT_SOC_ACTCK_SPI1_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case SPI2: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC0_EN) & BIT_PERI_SPI2_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL0) & BIT_SOC_ACTCK_SPI2_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case I2C0: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC0_EN) & BIT_PERI_I2C0_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL1) & BIT_SOC_ACTCK_I2C0_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case I2C1: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC0_EN) & BIT_PERI_I2C1_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL1) & BIT_SOC_ACTCK_I2C1_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case I2C2: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC0_EN) & BIT_PERI_I2C2_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL1) & BIT_SOC_ACTCK_I2C2_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else { + *HwState = HWINACT; + } + break; + + case I2C3: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC0_EN) & BIT_PERI_I2C3_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL1) & BIT_SOC_ACTCK_I2C3_EN){ + *HwState = HWACT; + } + else { + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case I2S0: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC0_EN) & BIT_PERI_I2S0_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL1) & BIT_SOC_ACTCK_I2S_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case I2S1: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC0_EN) & BIT_PERI_I2S1_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL1) & BIT_SOC_ACTCK_I2S_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case PCM0: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC0_EN) & BIT_PERI_PCM0_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL1) & BIT_SOC_ACTCK_PCM_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case PCM1: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC0_EN) & BIT_PERI_PCM1_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL1) & BIT_SOC_ACTCK_PCM_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case ADC0: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC1_EN) & BIT_PERI_ADC0_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL1) & BIT_SOC_ACTCK_ADC_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case DAC0: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC1_EN) & BIT_PERI_DAC0_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL1) & BIT_SOC_ACTCK_DAC_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case DAC1: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_PERI_FUNC1_EN) & BIT_PERI_DAC1_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_PERI_CLK_CTRL1) & BIT_SOC_ACTCK_DAC_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case SDIOD: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN) & BIT_SOC_HCI_SDIOD_ON_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0) & BIT_SOC_ACTCK_SDIO_DEV_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case SDIOH: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN) & BIT_SOC_HCI_SDIOH_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0) & BIT_SOC_ACTCK_SDIO_HST_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case USBOTG: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN) & BIT_SOC_HCI_OTG_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0) & BIT_SOC_ACTCK_OTG_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else { + *HwState = HWINACT; + } + break; + + case MII: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN) & BIT_SOC_HCI_MII_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0) & BIT_SOC_ACTCK_MII_MPHY_EN){ + *HwState = HWACT; + } + else { + *HwState = HWCG; + } + } + else{ + *HwState = HWINACT; + } + break; + + case PWM0: + if (HAL_READ32(PERI_ON_BASE, REG_PERI_PWM0_CTRL) & BIT_PERI_PWM0_EN){ + *HwState = HWACT; + } + else { + *HwState = HWINACT; + } + break; + + case PWM1: + if (HAL_READ32(PERI_ON_BASE, REG_PERI_PWM1_CTRL) & BIT_PERI_PWM1_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWINACT; +} + break; + + case PWM2: + if (HAL_READ32(PERI_ON_BASE, REG_PERI_PWM2_CTRL) & BIT_PERI_PWM2_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWINACT; + } + break; + + case PWM3: + if (HAL_READ32(PERI_ON_BASE, REG_PERI_PWM3_CTRL) & BIT_PERI_PWM3_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWINACT; + } + break; + + case ETE0: + if (HAL_READ32(PERI_ON_BASE, REG_PERI_TIM_EVT_CTRL) & BIT_PERI_GT_EVT0_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWINACT; + } + break; + + case ETE1: + if (HAL_READ32(PERI_ON_BASE, REG_PERI_TIM_EVT_CTRL) & BIT_PERI_GT_EVT1_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWINACT; + } + break; + + case ETE2: + if (HAL_READ32(PERI_ON_BASE, REG_PERI_TIM_EVT_CTRL) & BIT_PERI_GT_EVT2_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWINACT; + } + break; + + case ETE3: + if (HAL_READ32(PERI_ON_BASE, REG_PERI_TIM_EVT_CTRL) & BIT_PERI_GT_EVT3_EN){ + *HwState = HWACT; + } + else { + *HwState = HWINACT; + } + break; + + case EGTIM: + if (HAL_READ32(PERI_ON_BASE, REG_PERI_EGTIM_CTRL) & BIT_PERI_EGTIM_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWINACT; + } + break; + + case LOG_UART: + if (HAL_READ32(PERI_ON_BASE, REG_SOC_FUNC_EN) & BIT_SOC_LOG_UART_EN){ + if (HAL_READ32(PERI_ON_BASE, REG_PESOC_CLK_CTRL) & BIT_SOC_ACTCK_LOG_UART_EN){ + *HwState = HWACT; + } + else{ + *HwState = HWCG; + } + } + else { + *HwState = HWINACT; + } + break; + + default: + *HwState = UNDEF; + break; + } + +} + +VOID +QueryRegPwrState( + IN u8 FuncIdx, + OUT u8* RegState, + OUT u8* HwState +){ + u8 Idx = 0; + u8 StateIdx = INACT; + + for (Idx = 0; Idx < PwrAdapter.ActFuncCount; Idx++) { + if (PwrAdapter.PwrState[Idx].FuncIdx == FuncIdx) { + StateIdx = PwrAdapter.PwrState[Idx].PowerState; + break; + } + } + + *RegState = StateIdx; + ReadHWPwrState(FuncIdx, HwState); +} + + +VOID +SetSYSTimer( + IN u32 SDuration +) +{ + u32 Rtemp = 0; + u32 ScaleTemp = 0; + u32 PeriodTemp = 0; + u32 CalTemp = 0; + + //0x4000_0090[15] = 1'b0 => Disable timer + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, 0); + + //calculate scale and period + CalTemp = (CLKCal(ANACK) << 16); + DurationScaleAndPeriodOP(SDuration, &ScaleTemp, &PeriodTemp); + + Rtemp = ((CalTemp | ScaleTemp) | PeriodTemp); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); +} + +VOID +SleepCG( + IN u8 Option, + IN u32 SDuration, + IN u8 ClkSourceEn, + IN u8 SDREn + +) +{ + u32 Rtemp = 0; + u32 WakeEvent = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0); + + //Backup CPU CLK + BackupCPUClk(); + + //Clear event + PwrAdapter.WakeEventFlag = _FALSE; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_STATUS0, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_STATUS0)); + + //3 2 Configure power state option: + // 2.1 power mode option: + if (ClkSourceEn) { + Rtemp = 0x74003900; + } + else { + Rtemp = 0x74000900; + } + + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp); + + // 2.2 sleep power mode option1 + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION_EXT) & 0xffffff00)|0x2); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION_EXT, Rtemp); + + if (Option & SLP_STIMER) { + + //Set TU timer timescale + SetSYSTimer(SDuration); + + //0x4000_0090[15] = 1'b1 => Enable timer + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL) | 0x00008000; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); + + //Enable wake event + WakeEvent |= BIT0; + } + + if (Option & SLP_GTIMER) { + + //Enable wake event + WakeEvent |= BIT1; + } + + if (Option & SLP_GPIO) { + + //Enable wake event + WakeEvent |= BIT4; + } + + if (Option & SLP_WL) { + + //Enable wake event + WakeEvent |= BIT8; + } + + if (Option & SLP_NFC) { + + //Enable wake event + WakeEvent |= BIT28; + } + + if (Option & SLP_SDIO) { + + //Enable wake event + WakeEvent |= BIT14; + } + + if (Option & SLP_USB) { + + //Enable wake event + //WakeEvent |= BIT16; + } + + if (Option & SLP_TIMER33) { + + //Enable wake event + WakeEvent |= BIT28; + } + + while(1) { + + HalDelayUs(100); + + if (HAL_READ8(LOG_UART_REG_BASE,0x14)&BIT6){ + + break; + } + } + + //Set Event + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0, WakeEvent); + + //3 Enable low power mode + //Enable low power mode: + if ((*((volatile u8*)(&PwrAdapter.WakeEventFlag)))!= _TRUE){ + + PwrAdapter.SDREn = SDREn; + #ifdef CONFIG_SDR_EN + SDRSleep(); + #endif + + Rtemp = 0x00000004; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); + + //3 Wait CHIP enter low power mode + // Wait deep standby timer timeout + // Wait CHIP resume to norm power mode + HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL); + //__WFI(); + } +} + + +VOID +SleepPG( + IN u8 Option, + IN u32 SDuration +) +{ + u32 Rtemp = 0; + u32 WakeEvent = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0); + + //Backup CPU CLK + BackupCPUClk(); + + //Clear event + PwrAdapter.WakeEventFlag = _FALSE; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_STATUS0, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_STATUS0)); + + //3 2 Configure power state option: + // 2.1 power mode option: + Rtemp = 0x74000100; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp); + + // 2.2 sleep power mode option1 + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION_EXT) & 0xffffff00)|0x2); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION_EXT, Rtemp); + + if (Option & SLP_STIMER) { + + //Set TU timer timescale + SetSYSTimer(SDuration); + + //0x4000_0090[15] = 1'b1 => Enable timer + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL) | 0x00008000; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); + + //Enable wake event + WakeEvent |= BIT0; + } + + if (Option & SLP_GTIMER) { + + //Enable wake event + WakeEvent |= BIT1; + } + + if (Option & SLP_GPIO) { + + //Enable wake event + WakeEvent |= BIT4; + } + + if (Option & SLP_WL) { + + //Enable wake event + WakeEvent |= BIT8; + } + + if (Option & SLP_NFC) { + + //Enable wake event + WakeEvent |= BIT28; + } + + if (Option & SLP_SDIO) { + + //Enable wake event + WakeEvent |= BIT14; + } + + if (Option & SLP_USB) { + + //Enable wake event + //WakeEvent |= BIT16; + } + + if (Option & SLP_TIMER33) { + + //Enable wake event + WakeEvent |= BIT28; + } + + while(1) { + + HalDelayUs(100); + + if (HAL_READ8(LOG_UART_REG_BASE,0x14)&BIT6){ + + break; + } + } + + //Set Event + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0, WakeEvent); + + //3 Enable low power mode + //Enable low power mode: + if (PwrAdapter.WakeEventFlag != _TRUE){ + + #ifdef CONFIG_SDR_EN + LDO25M_CTRL(OFF); + #endif + + Rtemp = 0x00000004; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); + + //3 Wait CHIP enter low power mode + // Wait deep standby timer timeout + // Wait CHIP resume to norm power mode + HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL); + __WFI(); + } +} + + + +VOID +DSTBYGpioCtrl( + IN u8 PinEn, + IN u8 WMode +) +{ + u32 Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE,REG_SYS_GPIO_DSTBY_WAKE_CTRL0)|PinEn|(PinEn<<16)|(PinEn<<24)); + u32 Stemp = (PinEn<<8); + + if (WMode) { + Rtemp = (Rtemp|Stemp); + } + else { + Rtemp = (Rtemp & (~Stemp)); + } + + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_GPIO_DSTBY_WAKE_CTRL0, Rtemp); + + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE,REG_SYS_GPIO_DSTBY_WAKE_CTRL1)|PinEn|(PinEn<<16)|BIT9); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_GPIO_DSTBY_WAKE_CTRL1, Rtemp); +} + + +VOID +DeepStandby( + IN u8 Option, + IN u32 SDuration, + IN u8 GpioOption +) +{ + u32 Rtemp = 0; + + HAL_WRITE32(0x60008000, 0x80006180, PS_MASK); + + //Clear event + PwrAdapter.WakeEventFlag = _FALSE; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_STATUS0, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_STATUS0)); + + //3 2 Configure power state option: + // 2.1 deep standby power mode option: + Rtemp = 0x74000100; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp); + + // 2.2 sleep power mode option1 + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION_EXT) & 0xffffff00)); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION_EXT, Rtemp); + + if (Option & DSTBY_STIMER) { + + //3 3.1 Set TU timer timescale + SetSYSTimer(SDuration); + + //3 3.2 Configure platform wake event + // 1.3.1 0x4000_0100[0] = 1'b1 => Enable deep standby timer wakeup event to wakeup CPU + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0)|BIT0); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0, Rtemp); + + //0x4000_0090[15] = 1'b1 => Enable timer + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL) | 0x00008000; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); + } + + if (Option & DSTBY_NFC){ + //Enable wake event + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0)|BIT28); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0, Rtemp); + } + + if (Option & DSTBY_TIMER33){ + //Enable wake event + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0)|BIT28); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0, Rtemp); + } + + if (Option & DSTBY_GPIO){ + + if (GpioOption & BIT0) { + DSTBYGpioCtrl(BIT0, (GpioOption & BIT4)); + } + + if (GpioOption & BIT1) { + DSTBYGpioCtrl(BIT1, (GpioOption & BIT5)); + } + + if (GpioOption & BIT2) { + DSTBYGpioCtrl(BIT2, (GpioOption & BIT6)); + } + + if (GpioOption & BIT3) { + DSTBYGpioCtrl(BIT3, (GpioOption & BIT7)); + } + + //Enable wake event + if (GpioOption & 0xF){ + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0)|BIT29); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0, Rtemp); + } + } + + + //3 Enable low power mode + //Enable low power mode: + if (PwrAdapter.WakeEventFlag != _TRUE){ + + SpicDeepPowerDownFlashRtl8195A(); + + #ifdef CONFIG_SDR_EN + LDO25M_CTRL(OFF); + #endif + + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_GPIO_SHTDN_CTRL, 0x0); + + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) & 0xBFFFFFFF); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN, Rtemp); + + Rtemp = 0x00000002; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); + + //3 Wait CHIP enter low power mode + // Wait deep standby timer timeout + // Wait CHIP resume to norm power mode + HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL); + __WFI(); + } +} + + + +VOID +DeepSleep( + IN u8 Option, + IN u32 SDuration +) +{ + u32 Rtemp = 0; + u32 UTemp = 0; + u32 MaxTemp = 0; + + HAL_WRITE32(0x60008000, 0x80006180, PS_MASK); + + //1.1.1 Enable REGU access interface 0x4000_0094[31] = 1 + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) | 0x80000000); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //1.1.2 0x4000_0094[15:0] = 16'hD300 => Disable deep sleep counter + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x0000D300); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + while(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL)&BIT15){}; + + //1.1.3 Clear event + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_WEVENT, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_WEVENT)); + + if (Option & DS_TIMER33){ + //2.1.1 Calibration A33 CLK + UTemp = CLKCal(A33CK); + + //Calculate the max value base on the a33 duration + MaxTemp = ((((0x7FFFFF/3)*500)/UTemp)*25); + + if ( SDuration >= MaxTemp ) { + SDuration = 0x7FFFFF; + } + else { + //In unit of A33 CLK : max num is bounded by anaclk = 1.5k + SDuration = ((((SDuration/3)*500)/UTemp)*25); + } + + //2.1.2 Initialize deep sleep counter + //2.1.3.1 0x4000_0094[15:0] = 16'h9008 => set counter[7:0] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009000 | ((u8)SDuration)); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + while(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL)&BIT15){}; + + //2.1.3.2 0x4000_0094[15:0] = 16'h9100 => set counter[15:8] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009100 | ((u8)(SDuration >> 8))); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + while(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL)&BIT15){}; + + //2.1.3.3 0x4000_0094[15:0] = 16'h9200 => set counter[22:16] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009200 | ((u8)(SDuration >> 16))); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + while(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL)&BIT15){}; + + //2.1.3.4 0x4000_0094[15:0] = 16'hD380 => Enable deep sleep counter + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x0000D380); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + while(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL)&BIT15){}; + } + + if (Option & DS_GPIO) { + //2.2 en GPIO + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009410); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + while(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL)&BIT15){}; + } + + + //0x4000_0100[28] = 1'b1 => Enable A33 wakeup event to wakeup CPU + PwrAdapter.WakeEventFlag = _FALSE; + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0)|BIT28); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0, Rtemp); + + //3 2.3 + //2.3 Enable low power mode: 0x4000_0118[0] = 1'b1; + if (PwrAdapter.WakeEventFlag != _TRUE){ + + SpicDeepPowerDownFlashRtl8195A(); + + #ifdef CONFIG_SDR_EN + LDO25M_CTRL(OFF); + #endif + + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_GPIO_SHTDN_CTRL, 0x0); + + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) & 0xBFFFFFFF); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN, Rtemp); + + Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); + + //2.4 Wait CHIP enter deep sleep mode + //2.5 Wait deep sleep counter timeout + HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL); + __WFI(); + } +} + + +VOID +DSleep_GPIO( + VOID +) +{ + u32 Rtemp = 0; + + //1.1 Clear event + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_WEVENT, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_WEVENT)); + + //2 Deep Sleep mode: + //3 2.2 Configure GPIO: + //2.2.1 Enable REGU access interface 0x4000_0094[31] = 1 + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) | 0x80000000); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009410); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.2 + //2.3 Enable low power mode: 0x4000_0118[0] = 1'b1; + Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); + + //2.4 Wait CHIP enter deep sleep mode + //2.5 Wait deep sleep counter timeout + HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL); + __WFI(); +} + +VOID +DSleep_Timer( + IN u32 SDuration +) +{ + u32 Rtemp = 0; + u32 UTemp = 0; + u32 MaxTemp = 0; + + //2 Deep Sleep mode: + //3 2.1 Set TU timer timescale + + //3 2.2 Configure deep sleep timer: + //2.2.1 Enable REGU access interface 0x4000_0094[31] = 1 + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) | 0x80000000); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.2 0x4000_0094[15:0] = 16'hD300 => Disable deep sleep counter + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x0000D300); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.3 Clear event + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_WEVENT, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_WEVENT)); + + //2.2.4 Calibration A33 CLK + UTemp = CLKCal(A33CK); + + //Calculate the max value base on the a33 duration + MaxTemp = 0x7FFFFF*0x100/100000*UTemp/100*0x80; + + if ( SDuration >= MaxTemp ) { + SDuration = 0x7FFFFF; + } + else { + //In unit of A33 CLK : max num is bounded by anaclk = 1.5k + SDuration = ((((SDuration)/UTemp)*25/16*25/16*125)); + } + + //DiagPrintf("SDuration : 0x%x\n", SDuration); + + //2.2.5 Initialize deep sleep counter + //2.2.5.1 0x4000_0094[15:0] = 16'h9008 => set counter[7:0] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009000 | ((u8)SDuration)); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.5.2 0x4000_0094[15:0] = 16'h9100 => set counter[15:8] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009100 | ((u8)(SDuration >> 8))); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.5.3 0x4000_0094[15:0] = 16'h9200 => set counter[22:16] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009200 | ((u8)(SDuration >> 16))); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.5.4 0x4000_0094[15:0] = 16'hD380 => Enable deep sleep counter + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x0000D380); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //HalDelayUs(1000); + //Rtemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CAL_CTRL); + //DiagPrintf("a33 timer : 0x%x\n", Rtemp); + HalDelayUs(8000); + + //3 2.3 + //2.3 Enable low power mode: 0x4000_0118[0] = 1'b1; + Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); + + //2.4 Wait CHIP enter deep sleep mode + //2.5 Wait deep sleep counter timeout + HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL); + __WFI(); +} + + +VOID +SoCPwrReinitProcess( + VOID +) +{ + //clear resume jumping condition + HAL_WRITE32(PERI_ON_BASE, 0x218, (HAL_READ32(PERI_ON_BASE,0x218)&(~BIT31))); + + #ifdef CONFIG_KERNEL + InterruptForOSInit((VOID*)vPortSVCHandler, + (VOID*)xPortPendSVHandler, + (VOID*)xPortSysTickHandler); + #endif + + //msp stack + MSReFillProcess(); + + //init sys timer + ( * ( ( volatile unsigned long * ) 0xe000e014 ) ) = 0xc34f;//portNVIC_SYSTICK_LOAD_REG + ( * ( ( volatile unsigned long * ) 0xe000e010 ) ) = 0x10007;//portNVIC_SYSTICK_CTRL_REG + + //3 Reinit SYS int + { + IRQ_HANDLE SysHandle; + PSYS_ADAPTER pSYSAdapte; + pSYSAdapte = &SYSAdapte; + SysHandle.Data = (u32) (pSYSAdapte); + SysHandle.IrqNum = SYSTEM_ON_IRQ; + SysHandle.IrqFun = (IRQ_FUN) SYSIrqHandle; + SysHandle.Priority = 0; + + InterruptRegister(&SysHandle); + InterruptEn(&SysHandle); + } + //DiagPrintf("REINIT IRQ0!!!!!!!!!!\n"); + //HAL_WRITE32(0xE000ED00, 0x14, 0x200); + +} + + +VOID +SoCEnterPS( + VOID +) +{ +} + + +VOID +SoCPWRIdleTaskHandle( + VOID +) +{ + //static u32 IdleLoopCount = 0; + static u32 IdleCount = 0; + //u8 Chktemp = 0; + //u32 CMDTemp[6]; + //u32 Rtemp,Rtemp1,Rtemp2; + + //IdleCount++; + //HalDelayUs(1000); + //if ((IdleCount > 5000)||(HAL_READ8(SYSTEM_CTRL_BASE,REG_SOC_SYSON_DSTBY_INFO0+1) == 0x12)) + if (HAL_READ8(SYSTEM_CTRL_BASE, 0xf2) == 0xda) {// { + + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SOC_FUNC_EN, (HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_FUNC_EN)|BIT29)); + + HAL_WRITE32(SYSTEM_CTRL_BASE,0xf0,0); + + #if 0 //slp pg + //backup cpu reg + CPURegBackUp(); + + //backup main stack + MSBackupProcess(); + + //Wait for LogUart print out + while(1) { + HalDelayUs(100); + if (HAL_READ8(LOG_UART_REG_BASE,0x14)&BIT6){ + break; + } + } + + SoCPSGPIOCtrl(); + + ChangeSoCPwrState(SLPPG, 0xFFFFF); + + asm volatile + ( + "SLPPG_WAKEUP_POINT:\n" + ); + + SoCPwrReinitProcess(); + + //DiagPrintf("idle~~~~~~~~~~~~~~~~~\n"); + DiagPrintf("SLP_PG = %d\n", HAL_READ32(SYSTEM_CTRL_BASE,0xf8)); + #endif + asm volatile + ( + "SLPPG_WAKEUP_POINT:\n" + ); + + #if 1 //dslp + //Wait for LogUart print out + while(1) { + HalDelayUs(100); + if (HAL_READ8(LOG_UART_REG_BASE,0x14)&BIT6){ + break; + } + } + + ChangeSoCPwrState(DSTBY, 0xFFFFF); + #endif + + } + + if (IdleCount>500){ + IdleCount = 0; + if (HAL_READ32(SYSTEM_CTRL_BASE,0xf4) ==0) { + HAL_WRITE32(SYSTEM_CTRL_BASE,0xf0,HAL_READ32(SYSTEM_CTRL_BASE,0xf0)|0xda0000); + HAL_WRITE32(SYSTEM_CTRL_BASE,0xf8,HAL_READ32(SYSTEM_CTRL_BASE,0xf8)+1); + DiagPrintf("DSTBY = %d\n", HAL_READ32(SYSTEM_CTRL_BASE,0xf8)); + } + //DiagPrintf("idle~~~~~~~~~~~~~~~~~\n"); + } + else { + HalDelayUs(100000); + IdleCount++; + } +} + +#ifdef CONFIG_SOC_PS_VERIFY +#if 0 +VOID +SoCPwrDecision( + void +) +{ + u8 Idx = 0; + u8 StateIdx = 0; + u8 State = _TRUE; + u8 NextState = 0; + u32 CurrentCount, RemainCount, PTTemp; + + if ( PwrAdapter.ActFuncCount ) { + + //update remaining count + CurrentCount = HalTimerOp.HalTimerReadCount(1); + + for (Idx = 0; Idx < PwrAdapter.ActFuncCount; Idx++) { + + if (PwrAdapter.PwrState[Idx].RegCount < CurrentCount) { + PTTemp = (0xFFFFFFFF - CurrentCount + PwrAdapter.PwrState[Idx].RegCount); + } + else { + PTTemp = (PwrAdapter.PwrState[Idx].RegCount - CurrentCount); + } + + if ( PTTemp < PwrAdapter.PwrState[Idx].ReqDuration ) { + PwrAdapter.PwrState[Idx].RemainDuration = PwrAdapter.PwrState[Idx].ReqDuration - PTTemp; + } + else { + //active this function + if ( PwrAdapter.PwrState[Idx].PowerState > SLPPG ) { + //Todo: re-initial function as GPIO wake + } + PwrAdapter.PwrState[Idx].PowerState = ACT; + PwrAdapter.PwrState[Idx].RemainDuration = 0; + PwrAdapter.PwrState[Idx].ReqDuration = 0; + } + } + + //Select next power mode + for (StateIdx = DSLP; StateIdx >= ACT; StateIdx--) { + + for (Idx = 0; Idx < PwrAdapter.ActFuncCount; Idx++) { + + State = _TRUE; + if (PwrAdapter.PwrState[Idx].PowerState < StateIdx) { + State = _FALSE; + break; + } + } + + if ( State ) { + NextState = StateIdx; + break; + } + } + + //fine min sleep time + RemainCount = PwrAdapter.PwrState[0].RemainDuration; + for (Idx = 0; Idx < PwrAdapter.ActFuncCount; Idx++) { + + if ( RemainCount > PwrAdapter.PwrState[Idx].RemainDuration ) { + + RemainCount = PwrAdapter.PwrState[Idx].RemainDuration; + } + } + + //for debug + #if 1 + DiagPrintf("RemainCount : 0x%x \n", RemainCount); + DiagPrintf("NextState : 0x%x \n", NextState); + #endif + #if 0 + //Change state + if ( NextState > SLPCG ) { + if ( RemainCount > 640 ) { + ChangeSoCPwrState(NextState, RemainCount); + } + else { + ChangeSoCPwrState(SLPCG, RemainCount); + } + } + else { + if (NextState != ACT ) { + ChangeSoCPwrState(NextState, RemainCount); + } + } + #endif + } + else { + //todo: go to DSLP + } +} + + +VOID +RegPowerState( + REG_POWER_STATE RegPwrState +) +{ + u8 Idx = 0; + u8 StateIdx; + u8 FState = 0; + + for (Idx = 0; Idx < PwrAdapter.ActFuncCount; Idx++) { + if (PwrAdapter.PwrState[Idx].FuncIdx == RegPwrState.FuncIdx) { + StateIdx = Idx; + FState = _TRUE; + } + } + + switch (RegPwrState.PwrState) { + + case INACT : + if (FState) { + for (Idx = StateIdx; Idx < PwrAdapter.ActFuncCount; Idx++) { + PwrAdapter.PwrState[Idx].FuncIdx = PwrAdapter.PwrState[Idx+1].FuncIdx; + PwrAdapter.PwrState[Idx].PowerState = PwrAdapter.PwrState[Idx+1].PowerState; + PwrAdapter.PwrState[Idx].ReqDuration = PwrAdapter.PwrState[Idx+1].ReqDuration; + PwrAdapter.PwrState[Idx].RegCount = PwrAdapter.PwrState[Idx+1].RegCount; + } + PwrAdapter.ActFuncCount--; + } + else { + } + break; + + default: + + if (FState) { + PwrAdapter.PwrState[StateIdx].PowerState = RegPwrState.PwrState; + PwrAdapter.PwrState[StateIdx].ReqDuration = RegPwrState.ReqDuration; + PwrAdapter.PwrState[StateIdx].RegCount = HalTimerOp.HalTimerReadCount(1); + } + else { + PwrAdapter.PwrState[PwrAdapter.ActFuncCount].FuncIdx = RegPwrState.FuncIdx; + PwrAdapter.PwrState[PwrAdapter.ActFuncCount].PowerState = RegPwrState.PwrState; + PwrAdapter.PwrState[PwrAdapter.ActFuncCount].ReqDuration = RegPwrState.ReqDuration; + PwrAdapter.PwrState[PwrAdapter.ActFuncCount].RegCount = HalTimerOp.HalTimerReadCount(1); + PwrAdapter.ActFuncCount++; + } + + break; + } + + //for debug + #if 1 + for (Idx = 0; Idx < PwrAdapter.ActFuncCount; Idx++) { + DiagPrintf("RegPwrIdx : %d \n", Idx); + DiagPrintf("FuncIdx : %d \n", PwrAdapter.PwrState[Idx].FuncIdx); + DiagPrintf("PowerState : 0x%x \n", PwrAdapter.PwrState[Idx].PowerState); + DiagPrintf("ReqDuration : 0x%x \n", PwrAdapter.PwrState[Idx].ReqDuration); + DiagPrintf("RegCount : 0x%x \n", PwrAdapter.PwrState[Idx].RegCount); + } + #endif +} +#endif + +#if 0 +VOID +En32KCalibration( + VOID +) +{ + u32 Rtemp; + u32 Ttemp = 0; + + while(1) { + + //set parameter + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0); + Rtemp = 0x80f880; + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp); + + DiagPrintf("cal en\n"); + + //Polling LOCK + Rtemp = 0x110000; + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp); + DiagPrintf("polling lock\n"); + + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL1); + if ((Rtemp & 0x3000) != 0x0){ + break; + } + else { + Ttemp++; + DiagPrintf("check lock: %d\n", Ttemp); + } + } + + Rtemp = 0x884000; + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp); +} +#endif + +VOID +SYSTestIrqHandle +( + IN VOID *Data +) +{ + u32 Rtemp; + static u32 Ttemp = 0; + + //change cpu clk + ReFillCpuClk(); + HalDelayUs(100); + + //JTAG rst pull high + HAL_WRITE32(PERI_ON_BASE, REG_GPIO_PULL_CTRL2, 0x0202aaaa); + + //release shutdone + //HAL_WRITE32(PERI_ON_BASE, REG_GPIO_SHTDN_CTRL, 0x7ff); + + //disable DSTBY timer + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, 0); + + //clear wake event IMR + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0, 0); + + //clear wake event ISR + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_STATUS0); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_STATUS0, Rtemp); + + //HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SOC_SYSON_DSTBY_INFO0, Ttemp); + + //DiagPrintf("Ttemp : %d\n", Ttemp); + + Ttemp++; + //Rtemp = HalTimerOp.HalTimerReadCount(1); + //DiagPrintf("32k counter : %x\n", Rtemp);//32k counter : + //DiagPrintf("\n"); + + //PwrAdapter.SleepFlag = 1; + //DiagPrintf("\n"); + //DiagPrintf("0x234 after slp : %x\n", HAL_READ32(SYSTEM_CTRL_BASE,0x234)+1); + //HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SOC_SYSON_DSTBY_INFO0, HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_SYSON_DSTBY_INFO0)+1); + //HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SOC_SYSON_DSTBY_INFO1, HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_SYSON_DSTBY_INFO1)+1); + //HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SOC_SYSON_DSTBY_INFO2, HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_SYSON_DSTBY_INFO2)+1); + //HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SOC_SYSON_DSTBY_INFO3, HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_SYSON_DSTBY_INFO3)+1); + //DiagPrintf("f0 counter : %x\n", HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_SYSON_DSTBY_INFO0)); + //DiagPrintf("f1 counter : %x\n", HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_SYSON_DSTBY_INFO1)); + //DiagPrintf("f2 counter : %x\n", HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_SYSON_DSTBY_INFO2)); + //DiagPrintf("f3 counter : %x\n", HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_SYSON_DSTBY_INFO3)); + //DiagPrintf("\n"); + //DiagPrintf("ya ~~~~\n"); + + PwrAdapter.WakeEventFlag = _TRUE; +} + +VOID +InitSYSTestIRQ(VOID) +{ + IRQ_HANDLE SysHandle; + PSYS_ADAPTER pSYSAdapte; + pSYSAdapte = &SYSAdapte; + SysHandle.Data = (u32) (pSYSAdapte); + SysHandle.IrqNum = SYSTEM_ON_IRQ; + SysHandle.IrqFun = (IRQ_FUN) SYSIrqHandle; + SysHandle.Priority = 0; + + InterruptRegister(&SysHandle); + InterruptEn(&SysHandle); + PwrAdapter.WakeEventFlag = _FALSE; +} + +VOID +SetA33Timer( + IN u32 SDuration +) +{ + u32 Rtemp = 0; + //u32 ScaleTemp = 0; + //u32 PeriodTemp = 0; + u32 UTemp = 0; + u32 MaxTemp = 0; + + //2 Deep Sleep mode: + //3 2.1 Set TU timer timescale + + //3 2.2 Configure deep sleep timer: + //2.2.1 Enable REGU access interface 0x4000_0094[31] = 1 + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) | 0x80000000); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.2 Calibration A33 CLK + UTemp = CLKCal(A33CK); + DiagPrintf("CAL : 0x%x\n", UTemp); + + //Calculate the max value base on the a33 duration + MaxTemp = 0x7FFFFF*0x100/100000*UTemp/100*0x80; + DiagPrintf("MaxTemp : 0x%x\n", MaxTemp); + + if ( SDuration >= MaxTemp ) { + SDuration = 0x7FFFFF; + } + else { + //In unit of A33 CLK : max num is bounded by anaclk = 1.5k + SDuration = ((((SDuration)/UTemp)*25/16*25/16*125)); + DiagPrintf("SDuration : 0x%x\n", SDuration); + + } + + //3 2.2.2 Initialize deep sleep counter + //2.2.2.1 0x4000_0094[15:0] = 16'h9008 => set counter[7:0] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009000 | ((u8)SDuration)); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.2.2 0x4000_0094[15:0] = 16'h9100 => set counter[15:8] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009100 | ((u8)(SDuration >> 8))); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.2.3 0x4000_0094[15:0] = 16'h9200 => set counter[22:16] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009200 | ((u8)(SDuration >> 16))); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.2.4 0x4000_0094[15:0] = 16'hD380 => Enable deep sleep counter + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x0000D380); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + DiagPrintf("a33 timer : 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CAL_CTRL)); +} + + +VOID +PrintCPU( + VOID +) +{ + + #if 0 + DiagPrintf("r13 : 0x%x\n", PwrAdapter.CPURegbackup[24]); + DiagPrintf("pc : 0x%x\n", PwrAdapter.CPURegbackup[23]); + DiagPrintf("control : 0x%x\n", PwrAdapter.CPURegbackup[22]); + DiagPrintf("psp : 0x%x\n", PwrAdapter.CPURegbackup[21]); + DiagPrintf("msp : 0x%x\n", PwrAdapter.CPURegbackup[20]); + #endif + + #if 0 + u8 i; + for (i = 0; i < 21; i++){ + PwrAdapter.CPURegbackup[i] = ( * ( ( volatile unsigned long * ) (PwrAdapter.CPURegbackup[24]+(i*4)) ) ); + } + #endif + + u8 i; + for (i = 0; i < 25; i++){ + DiagPrintf("CPURegbackup_idx : %d , 0x%x\n", i, PwrAdapter.CPURegbackup[i]); + } + + + #if 1 + for (i = 0; i < 21; i++) { + DiagPrintf("backup_idx : 0x%x , 0x%x\n", PwrAdapter.CPUPSP+(i*4),( * ( ( volatile unsigned long * ) (PwrAdapter.CPUPSP+(i*4)) ) ));//CPURegbackup[1] + } + #endif + + #if 0 + { + u32 cpupspc; + asm volatile + ( + "MRS %0, PSP\n" + :"=r"(cpupspc) + ::"memory" + ); + for (i = 0; i < 21; i++) { + DiagPrintf("stack addr : 0x%x , 0x%x\n", (cpupspc+(i*4)),( * ( ( volatile unsigned long * ) (cpupspc+(i*4)) ) ));//CPURegbackup[1] + } + } + #endif +} + + +VOID +SoCPSMEMTestInit( + IN u32 StartAddr, + IN u32 Length, + IN u32 Pattern +) +{ + u32 Idx; + for( Idx = 0; Idx < Length; Idx += 4 ){ + + HAL_WRITE32(StartAddr,Idx,Pattern); + } +} + +u8 +SoCPSMEMTestChk( + IN u32 StartAddr, + IN u32 Length, + IN u32 Pattern +) +{ + u32 Idx; + + for( Idx = 0; Idx < Length; Idx += 4 ){ + if (HAL_READ32(StartAddr,Idx) != Pattern) { + DiagPrintf("addr 0x%x fail\n", (StartAddr+Idx)); + return 0; + } + } + DiagPrintf("addr 0x%x pass\n", StartAddr); + return 1; +} + + +VOID +SoCPWRIdleTaskHandleTest( + VOID +) +{ + static u32 IdleTemp = 0; + u32 Rtemp,Rtemp1,Rtemp2; + u8 RRtemp,CMDTemp[8],Chktemp; + + if (0){//(HAL_READ8(SYSTEM_CTRL_BASE,REG_SOC_SYSON_DSTBY_INFO0) == 0x0) { + + IdleTemp++; + HalDelayUs(1000); + + if (IdleTemp >= 15000) { + DiagPrintf("\n"); + DiagPrintf("Go to sleep ~~~~ \n"); + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SYS_DSTBY_INFO0,0x12345678); + DiagPrintf("0xf0 : 0x%x\n",HAL_READ32(SYSTEM_CTRL_BASE,REG_SYS_DSTBY_INFO0)); + //a33 reg chk + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) | 0x80000000); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, 0x80008400); + HalDelayUs(1000); + if ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL)&BIT15)==0){ + RRtemp = ((u8)HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL))+1; + } + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009400|RRtemp); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + DiagPrintf("a33 0x4 : 0x%x\n",RRtemp); + + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, 0x80008500); + HalDelayUs(1000); + if ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL)&BIT15)==0){ + DiagPrintf("a33 0x5 before : 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL)); + RRtemp = ((u8)HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL))+1; + } + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009500|RRtemp); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + DiagPrintf("a33 0x5 : 0x%x\n",RRtemp); + + ChangeSoCPwrState(7,0xE8800); + } + } + + ////debug + if (PwrAdapter.SleepFlag) { + PwrAdapter.SleepFlag = 0; + HAL_WRITE32(SYSTEM_CTRL_BASE,0x234, 0xdddddddd); + DiagPrintf("0x234 before slp : %x\n", HAL_READ32(SYSTEM_CTRL_BASE,0x234)); + //cal 32k + //En32KCalibration(); + HalDelayUs(1000); + + ChangeSoCPwrState(5,0xb000); + //HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SOC_SYSON_DSTBY_INFO1, PwrAdapter.SleepFlag); + } + + if (0){//(HAL_READ8(SYSTEM_CTRL_BASE,REG_SOC_SYSON_DSTBY_INFO0) == 0x0) { + + IdleTemp++; + HalDelayUs(1000); + if (IdleTemp > 0xfffff){ + IdleTemp = 0; + __WFI(); + } + } + + if (0){ //((HAL_READ8(SYSTEM_CTRL_BASE,REG_SOC_SYSON_DSTBY_INFO0) == 0x0)) { + IdleTemp++; + HalDelayUs(1000); + if ((IdleTemp > 5000)||(HAL_READ8(SYSTEM_CTRL_BASE,REG_SYS_DSTBY_INFO0+1) == 0x12)){ + + DiagPrintf("\n"); + DiagPrintf("0x20080000 : 0x%x\n", HAL_READ32(0x20080000,0)); + DiagPrintf("0x20080004 : 0x%x\n", HAL_READ32(0x20080000,4)); + DiagPrintf("0x2009F404 : 0x%x\n", HAL_READ32(0x2009F400,4)); + DiagPrintf("0x2009F408 : 0x%x\n", HAL_READ32(0x2009F400,8)); + DiagPrintf("\n"); + + HAL_WRITE32(0x40000000,0x330,0x55559555);//0x55552a2a + //slp pg GPIOD GPIOE + HAL_WRITE32(0x40000000,0x334,0x55555555); + HAL_WRITE32(0x40000000,0x338,0x05555555); + HAL_WRITE32(0x40000000,0x33c,0x55555555); + HAL_WRITE32(0x40000000,0x340,0x55555555); + HAL_WRITE32(0x40000000,0x344,0x55555555); + HAL_WRITE32(0x40000000,0x320,0x0); + + HAL_WRITE32(0x20080000, 0, (HAL_READ32(0x20080000,0)+1)); + HAL_WRITE32(0x20080000, 4, (HAL_READ32(0x20080000,4)+1)); + HAL_WRITE32(0x2009F404, 0, (HAL_READ32(0x2009F400,4)+1)); + HAL_WRITE32(0x2009F408, 0, (HAL_READ32(0x2009F400,8)+1)); + HalDelayUs(10000); + ChangeSoCPwrState(SLPPG, 0xFFFFF); + } + } + //mem test + if (HAL_READ8(0x40000000,0xf1) == 0xaa) { + + CMDTemp[0] = 8; + SOCPSTestApp((VOID*)CMDTemp); + Rtemp = HAL_READ32(0x40080000,0x824); + Rtemp2 = Rtemp; + Rtemp2 = ((Rtemp2 & 0x807fffff) | 0x80000000); + HAL_WRITE32(0x40080000,0x824,Rtemp&0x7fffffff); + HAL_WRITE32(0x40080000,0x824,Rtemp2); + HAL_WRITE32(0x40080000,0x824,(Rtemp|0x80000000)); + Rtemp1 = HAL_READ32(0x40080000,0x820)&BIT8; + if (Rtemp1) { + Rtemp = HAL_READ32(0x40080000,0x8b8)&0xfffff; + } + else { + Rtemp = HAL_READ32(0x40080000,0x8a0)&0xfffff; + } + if(Rtemp== 0x00045678){ + Chktemp = 1; + } + + Chktemp &= SoCPSMEMTestChk(0x20010000,0x20000,0x12345678)&SoCPSMEMTestChk(0x200a0000,0x0FFE0,0x12345678) + &SoCPSMEMTestChk(0x1FFF4000,0x5000,0x12345678); + + if (Chktemp) { + HAL_WRITE32(0x40080000,0x4,(HAL_READ32(0x40080000,0x4)&0xFFFFFFF0)); + HAL_WRITE32(0x40000000,0xfc,(HAL_READ32(0x40000000,0xfc)+1)); + DiagPrintf("run %d times\n", HAL_READ32(0x40000000,0xfc)); + CMDTemp[0] = 1; + CMDTemp[1] = 5; + CMDTemp[2] = 0xff; + SOCPSTestApp((VOID*)CMDTemp); + } + else { + HAL_WRITE32(0x40000000,0xf0,0); + } + + } +} + +//30 +VOID +TimerHandleTset( + IN VOID *Data +) +{ + #if 0 + //static u32 temp = 0; + TIMER_ADAPTER TimerAdapter; + + TimerAdapter.IrqDis = OFF; + //TimerAdapter.IrqHandle = (IRQ_FUN) TimerHandleTset; + TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) TimerHandleTset; + //DBG_8195A("IrqFun : 0x%x\n", TimerAdapter.IrqHandle.IrqFun); + TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ; + TimerAdapter.IrqHandle.Priority = 0; + TimerAdapter.IrqHandle.Data = NULL; + TimerAdapter.TimerId = 2; + TimerAdapter.TimerIrqPriority = 0; + TimerAdapter.TimerLoadValueUs = 4000; + TimerAdapter.TimerMode = USER_DEFINED; + //temp++; + //DBG_8195A("time : 0x%x\n", temp); + + HalTimerOp.HalTimerInit((VOID*) &TimerAdapter); + #endif + DBG_8195A("<<< time out >>>\n"); +} + +extern IRQ_FUN Timer2To7VectorTable[6]; + +//30 +VOID +InitTimerTest( + //IN VOID *Data + VOID +) +{ + //[0]:type, [1]: timerID, [2]: timerMode, [3]: IrqDIS, [4]:period + TIMER_ADAPTER TimerAdapter; + //u32 *TestParameter; + + //TestParameter = (u32*) Data; + + TimerAdapter.IrqDis = 0; // off :0 + //TimerAdapter.IrqHandle = (IRQ_FUN) TimerHandleTset; + TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) TimerHandleTset; + //DBG_8195A("IrqFun : 0x%x\n", TimerAdapter.IrqHandle.IrqFun); + TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ; + TimerAdapter.IrqHandle.Priority = 0; + TimerAdapter.IrqHandle.Data = NULL; + TimerAdapter.TimerId = 5; + TimerAdapter.TimerIrqPriority = 0; + TimerAdapter.TimerLoadValueUs = 0x4EC14; + TimerAdapter.TimerMode = 1; // user_define :1 + + + //mer2To7VectorTable[0] = (IRQ_FUN) TimerHandleTset; + + HalTimerOp.HalTimerInit((VOID*) &TimerAdapter); + //mer2To7VectorTable[0] = (IRQ_FUN) TimerHandleTset; + + +} + + +VOID +GpioPsPullCtrl( + VOID +) +{ + gpio_t gpio_obj; + + gpio_init(&gpio_obj, PA_0); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PA_1); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PA_2); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PA_3); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PA_4); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PA_5); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PA_6); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PA_7); + gpio_mode(&gpio_obj, PullDown); + + gpio_init(&gpio_obj, PB_0); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PB_1); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PB_2); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PB_3); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PB_4); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PB_5); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PB_6); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PB_7); + gpio_mode(&gpio_obj, PullDown); + + gpio_init(&gpio_obj, PC_0); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PC_1); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PC_2); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PC_3); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PC_4); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PC_5); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PC_6); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PC_7); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PC_8); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PC_9); + gpio_mode(&gpio_obj, PullDown); + + gpio_init(&gpio_obj, PD_0); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PD_1); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PD_2); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PD_3); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PD_4); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PD_5); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PD_6); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PD_7); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PD_8); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PD_9); + gpio_mode(&gpio_obj, PullDown); + + gpio_init(&gpio_obj, PE_0); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PE_1); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PE_2); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PE_3); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PE_4); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PE_5); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PE_6); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PE_7); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PE_8); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PE_9); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PE_A); + gpio_mode(&gpio_obj, PullDown); + + gpio_init(&gpio_obj, PF_0); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PF_1); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PF_2); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PF_3); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PF_4); + gpio_mode(&gpio_obj, PullDown); + gpio_init(&gpio_obj, PF_5); + gpio_mode(&gpio_obj, PullDown); + + gpio_init(&gpio_obj, PG_0); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PG_1); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PG_2); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PG_3); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PG_4); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PG_5); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PG_6); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PG_7); + gpio_mode(&gpio_obj, PullUp); + + gpio_init(&gpio_obj, PH_0); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PH_1); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PH_2); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PH_3); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PH_4); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PH_5); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PH_6); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PH_7); + gpio_mode(&gpio_obj, PullUp); + + gpio_init(&gpio_obj, PI_0); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PI_1); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PI_2); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PI_3); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PI_4); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PI_5); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PI_6); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PI_7); + gpio_mode(&gpio_obj, PullUp); + + gpio_init(&gpio_obj, PJ_0); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PJ_1); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PJ_2); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PJ_3); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PJ_4); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PJ_5); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PJ_6); + gpio_mode(&gpio_obj, PullUp); + + + gpio_init(&gpio_obj, PK_0); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PK_1); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PK_2); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PK_3); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PK_4); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PK_5); + gpio_mode(&gpio_obj, PullUp); + gpio_init(&gpio_obj, PK_6); + gpio_mode(&gpio_obj, PullUp); +} + + +VOID +SOCPSTestApp( + VOID *Data +) +{ + u32 *TestParameter; + TestParameter = (u32*) Data; + unsigned int Rtemp, Rtemp1, Rtemp2;//, CalTemp32k, CalTempa33; + static u32 Read32k5 = 0; + static u32 Reada335 = 0; + DiagPrintf("TestParameter[0]: 0x%x\n",TestParameter[0]); + + switch (TestParameter[0]) { + + case 0: + DiagPrintf("SoC PWR Init wlan\n"); + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,0x214)|BIT16; + HAL_WRITE32(SYSTEM_CTRL_BASE,0x214,Rtemp); + + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,0x244)|BIT0; + HAL_WRITE32(SYSTEM_CTRL_BASE,0x244,Rtemp); + + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,0x210)|BIT2; + HAL_WRITE32(SYSTEM_CTRL_BASE,0x210,Rtemp); + + HalDelayUs(100); + + Rtemp = HAL_READ32(WIFI_REG_BASE,0x0)|BIT0; + HAL_WRITE32(WIFI_REG_BASE,0x0,Rtemp); + #if 0 + DiagPrintf("SoC PWR debug setting\n"); + Rtemp = 0; + HAL_WRITE32(SYSTEM_CTRL_BASE,0x33c,Rtemp); + + Rtemp = 0; + HAL_WRITE32(SYSTEM_CTRL_BASE,0x334,Rtemp); + + #if 0 + //en debug + Rtemp = 1;//HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_SYS_DEBUG_CTRL); + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SOC_SYS_DEBUG_CTRL,Rtemp); + + //debug port sel + Rtemp = 0xf0f10004;//HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_EFUSE_SYSCFG3)|0xf0000000; + HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SOC_EFUSE_SYSCFG3, Rtemp); + #endif + + //cal 32k + //En32KCalibration(); + + //en gpio + GPIO_FCTRL(ON); + SLPCK_GPIO_CCTRL(ON); + ACTCK_GPIO_CCTRL(ON); + + //DiagPrintf("debug sel 0x2C : 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_EFUSE_SYSCFG3)); + //DiagPrintf("debug EN 0xA0 : 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_SYS_DEBUG_CTRL)); + //DiagPrintf("PULL CTRL 0x33c: 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE,0x33C)); + //DiagPrintf("debug port : 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_SYS_DEBUG_REG)); + DiagPrintf("0x90 : 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE,0x90)); + #endif + break; + + case 1: + DiagPrintf("SoC PWR TEST : Enter = %d, Period = %d\n",TestParameter[1], TestParameter[2]); + Rtemp = HalTimerOp.HalTimerReadCount(1); + //GPIO + //HAL_WRITE32(0x40001000,0x4,0x4000000); + + //SIC EN + //HAL_WRITE32(0x40000000,0x8,0x81000010); + //HAL_WRITE32(0x40000000,0xA4,0x00000001); + + //Wait for LogUart print out + while(1) { + HalDelayUs(100); + if (HAL_READ8(LOG_UART_REG_BASE,0x14)&BIT6){ + break; + } + } + + #if 0 + + HAL_WRITE32(0x40000000,0x330,0x55559555);//0x55552a2a + //slp pg GPIOD GPIOE + HAL_WRITE32(0x40000000,0x334,0x55555555); + HAL_WRITE32(0x40000000,0x338,0x05555555); + HAL_WRITE32(0x40000000,0x33c,0x55555555); + HAL_WRITE32(0x40000000,0x340,0x55555555); + HAL_WRITE32(0x40000000,0x344,0x55555555); + HAL_WRITE32(0x40000000,0x320,0x0); + #endif + + ChangeSoCPwrState(TestParameter[1], TestParameter[2]); + + Rtemp2 = HalTimerOp.HalTimerReadCount(1); + DiagPrintf("before : %x\n", Rtemp); + DiagPrintf("after : %x\n", Rtemp2); + DiagPrintf("period : %d\n", Rtemp-Rtemp2); + DiagPrintf("0x90 : 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE,0x90)); + break; + + case 2: + #if 1 + + HAL_WRITE32(0x40000000,0x320,0x7ff); + HAL_WRITE32(0x40000000,0x330,0x5565A555); + //slp pg GPIOD GPIOE + HAL_WRITE32(0x40000000,0x334,0x55555555); + HAL_WRITE32(0x40000000,0x338,0x05555555); + HAL_WRITE32(0x40000000,0x33c,0x55555555); + HAL_WRITE32(0x40000000,0x340,0x55555555); + HAL_WRITE32(0x40000000,0x344,0x55555555); + HAL_WRITE32(0x40000000,0x348,0x55555555); + HAL_WRITE32(0x40000000,0x320,0x0); + + HAL_WRITE32(0x40000000,0x8,0x80000011); + #endif + HAL_WRITE32(SYSTEM_CTRL_BASE, 0X120, TestParameter[1]); + HAL_WRITE32(SYSTEM_CTRL_BASE, 0X124, TestParameter[2]); + + if (TestParameter[4] == 0xff) { + //SIC EN + HAL_WRITE32(0x40000000,0x320,0x4); + HAL_WRITE32(0x40000000,0x8,0xC1000010); + HAL_WRITE32(0x40000000,0xA4,0x00000001); + } + + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, TestParameter[3]); + #if 0 + //clear isr + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SOC_SYS_ANA_TIM_CTRL)& 0xffff7fff)); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SOC_SYS_ANA_TIM_CTRL, Rtemp); + + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SOC_SYSON_SLP_WAKE_EVENT_STATUS0); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SOC_SYSON_SLP_WAKE_EVENT_STATUS0, Rtemp); + #endif + break; + + case 3: + HAL_WRITE32(SYSTEM_CTRL_BASE, 0X120, 0x74000e00); + HAL_WRITE32(SYSTEM_CTRL_BASE, 0X124, 2); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, TestParameter[1]); + #if 0 + { + u32 targetunit = 0; + + //cal a33 + Rtemp = CLKCal(A33CK); + + targetunit = (TestParameter[1]/3*250)/Rtemp*50; + if (targetunit > 0x7fffff) { + targetunit = 0x7fffff; + } + + DBG_8195A("targeunit = 0x%08x\n",targetunit); + + targetunit = (50*TestParameter[1]/Rtemp)*250/3; + if (targetunit > 0x7fffff) { + targetunit = 0x7fffff; + } + + DBG_8195A("targeunit = 0x%08x\n",targetunit); + + + } + #endif + #if 0 + //cal a33 + Rtemp = CLKCal(A33CK); + Rtemp1 = (((((TestParameter[1] & 0x0FFFFFFF)<<4)/Rtemp)*20)-1); + DiagPrintf("Rtemp : 0x%x\n", Rtemp); + DiagPrintf("Vendor 0xA0 : 0x%x\n", HAL_READ32(VENDOR_REG_BASE,0xA0)); + DiagPrintf("way1 : 0x%x\n", Rtemp1); + Rtemp2 = (((((TestParameter[1] & 0x0FFFFFFF))/Rtemp)*320)-1); + DiagPrintf("way2 : 0x%x\n", Rtemp2); + + Rtemp = Rtemp1/6; + DiagPrintf("Rtemp1 : %d\n", Rtemp); + Rtemp = 0x7fffffff; + DiagPrintf("Rtemp1 : %d\n", Rtemp); + #endif + break; + + case 4: + DiagPrintf("set timer\n"); + SetA33Timer(TestParameter[1]); + Rtemp = HalTimerOp.HalTimerReadCount(1); + DiagPrintf("32k timer : 0x%x\n", Rtemp); + break; + + case 5: + DiagPrintf("read timer\n"); + Reada335 = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CAL_CTRL); + DiagPrintf("a33 timer : 0x%x\n", Reada335); + Read32k5 = HalTimerOp.HalTimerReadCount(1); + DiagPrintf("32k timer : 0x%x\n", Read32k5); + break; + + case 6: + #if 0 + DiagPrintf("interval cal\n"); + Rtemp1 = HAL_READ32(SYSTEM_CTRL_BASE, REG_SOC_SYS_DSLP_TIM_CAL_CTRL); + Rtemp2 = HalTimerOp.HalTimerReadCount(1); + DiagPrintf("Reada335 : 0x%x\n", Reada335); + DiagPrintf("Read32k5 : 0x%x\n", Read32k5); + DiagPrintf("a33 timer : 0x%x\n", Rtemp1); + DiagPrintf("32k timer : 0x%x\n", Rtemp2); + CalTemp32k = (Read32k5 - Rtemp2); + CalTempa33 = (((Reada335 - Rtemp1)*((HAL_READ32(VENDOR_REG_BASE, REG_VDR_ANACK_CAL_CTRL) & 0x3FFF)+1))/5); + DiagPrintf("a33 timer interval : 0x%x\n", CalTempa33); + DiagPrintf("32k timer interval : 0x%x\n", CalTemp32k); + Read32k5 = Rtemp2; + Reada335 = Rtemp1; + #endif + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL) & 0xffff7000) | 0x7ff); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); + + //0x4000_0090[15] = 1'b1 => Enable timer + Rtemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL) | 0x00008000; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); + + Rtemp = 0x00000001; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0, Rtemp); +#if 0 + HAL_WRITE32(0x40000000,0x330,0x55559555);//0x55552a2a + HAL_WRITE32(0x40000000,0x2C0,0x100001); + //slp pg GPIOD GPIOE + HAL_WRITE32(0x40000000,0x334,0x55555555); + HAL_WRITE32(0x40000000,0x338,0x05555555); + HAL_WRITE32(0x40000000,0x33c,0x55555555); + HAL_WRITE32(0x40000000,0x340,0x55555555); + HAL_WRITE32(0x40000000,0x344,0x55555555); + HAL_WRITE32(0x40000000,0x320,0x0); +#endif + HAL_WRITE32(SYSTEM_CTRL_BASE, 0X120, TestParameter[1]); + HAL_WRITE32(SYSTEM_CTRL_BASE, 0X124, TestParameter[2]); + + if (HAL_READ32(0x40000000,0xf4) == 0x11) { + HAL_WRITE32(0x40000000,0x8,0x80000011); + } + + if (TestParameter[4] == 0xff) { + //SIC EN + HAL_WRITE32(0x40000000,0x8,0x81000010); + HAL_WRITE32(0x40000000,0xA4,0x00000001); + } + + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, TestParameter[3]); + break; + + case 7: + { + u32 Rtemp = 0; + u32 UTemp = 0; + u32 MaxTemp = 0; + u32 Reada335 = 0; + + //2 Deep Sleep mode: + //3 2.1 Set TU timer timescale + + //3 2.2 Configure deep sleep timer: + //2.2.1 Enable REGU access interface 0x4000_0094[31] = 1 + Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) | 0x80000000); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + DiagPrintf("SDuration : 0x%x\n", TestParameter[1]); + + //3 2.2.2 Initialize deep sleep counter + //2.2.2.0 0x4000_0094[15:0] = 16'hD300 => Disable deep sleep counter + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x0000D300); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + //2.2.2.1 0x4000_0094[15:0] = 16'h9008 => set counter[7:0] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009000 | ((u8)TestParameter[1])); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.2.2 0x4000_0094[15:0] = 16'h9100 => set counter[15:8] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009100 | ((u8)(TestParameter[1] >> 8))); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.2.3 0x4000_0094[15:0] = 16'h9200 => set counter[22:16] + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x00009200 | ((u8)(TestParameter[1] >> 16))); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + //2.2.2.4 0x4000_0094[15:0] = 16'hD380 => Enable deep sleep counter + Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) & 0xffff0000) | 0x0000D380); + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp); + + HalDelayUs(1000); + Reada335 = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CAL_CTRL); + DiagPrintf("a33 timer : 0x%x\n", Reada335); + + HalDelayUs(8000); + + //3 2.2.3 + //2.3 Enable low power mode: 0x4000_0118[0] = 1'b1; + Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001; + HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); + + //2.4 Wait CHIP enter deep sleep mode + //2.5 Wait deep sleep counter timeout + //__WFI(); + + DiagPrintf("YOU CAN'T SEE ME ~~~~!!!!!!!!!!!!!!!!!!!~~~~~~~~~~~~~~~!!!!!!!!!!"); + } + break; + + case 8: + DiagPrintf("enable wifi\n"); + + Rtemp = HAL_READ32(0x40000000,0x214)|0x10000; + HAL_WRITE32(0x40000000,0x214,Rtemp); + Rtemp = HAL_READ32(0x40000000,0x244)|0x1; + HAL_WRITE32(0x40000000,0x244,Rtemp); + Rtemp = HAL_READ32(0x40000000,0x210)|0x4; + HAL_WRITE32(0x40000000,0x210,Rtemp); + + Rtemp = HAL_READ32(0x40080000,0x0)&0xFFFFFFDF; + HAL_WRITE32(0x40080000,0x0,Rtemp); + Rtemp = HAL_READ32(0x40080000,0x4)|0x1; + HAL_WRITE32(0x40080000,0x4,Rtemp); + Rtemp = HAL_READ32(0x40080000,0x20)|0x1; + HAL_WRITE32(0x40080000,0x20,Rtemp); + while( (HAL_READ32(0x40080000,0x20)&BIT0)!=0); + + Rtemp = HAL_READ32(0x40080000,0x4)|0x30000; + HAL_WRITE32(0x40080000,0x4,Rtemp); + Rtemp = HAL_READ32(0x40080000,0x4)|0x7000000; + HAL_WRITE32(0x40080000,0x4,Rtemp); + Rtemp = HAL_READ32(0x40080000,0x50)&0xFFFFFF00; + HAL_WRITE32(0x40080000,0x50,Rtemp); + break; + + case 9: + #if 0 + PwrAdapter.CPURegbackup[13] = 0x12340; + PwrAdapter.CPUPSP = PwrAdapter.CPURegbackup[13]; + + asm volatile + ( + + " ldr r3, pxCPUPSPConst23 \n" /* Restore the context. */ + "MOV %0, r3\n" + " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + "MOV %1, r1\n" + " ldr r0, [r1] \n" + "MOV %2, r0\n" + " .align 2 \n" + "pxCPUPSPConst23: .word PwrAdapter.CPUPSP \n" + :"=r"(PwrAdapter.CPURegbackup[0]),"=r"(PwrAdapter.CPURegbackup[1]),"=r"(PwrAdapter.CPURegbackup[2]),"=r"(PwrAdapter.CPURegbackup[3]) + :"r"(PwrAdapter.CPUPSP) + :"memory" + ); + PrintCPU(); + #endif + break; + + case 10: + Rtemp = HAL_READ32(0x40080000,0x824); + Rtemp2 = Rtemp; + Rtemp2 = Rtemp2 & 0x807fffff | (TestParameter[1]<<23) | 0x80000000; + HAL_WRITE32(0x40080000,0x824,Rtemp&0x7fffffff); + HAL_WRITE32(0x40080000,0x824,Rtemp2); + HAL_WRITE32(0x40080000,0x824,Rtemp|0x80000000); + Rtemp1 = HAL_READ32(0x40080000,0x820)&BIT8; + if (Rtemp1) { + Rtemp = HAL_READ32(0x40080000,0x8b8)&0xfffff; + } + else { + Rtemp = HAL_READ32(0x40080000,0x8a0)&0xfffff; + } + DiagPrintf("rf offset: 0x%x, 0x%x\n", TestParameter[1], Rtemp); + break; + + case 11://addr [1]; date [2] + TestParameter[1] &= 0x3f; + Rtemp = (TestParameter[1]<<20)|(TestParameter[2]&0x000fffff)&0x0fffffff; + HAL_WRITE32(0x40080000,0x840,Rtemp); + + //SoCPWRIdleTaskHandle(); + break; + + case 12: + SoCPSMEMTestInit(TestParameter[1],TestParameter[2],TestParameter[3]); + break; + + case 13: + Rtemp = SoCPSMEMTestChk(TestParameter[1],TestParameter[2],TestParameter[3]); + break; + + case 14: + HAL_WRITE32(0x40000000,TestParameter[1],0x12345678); + DiagPrintf("w32: 0x%x\n", HAL_READ32(0x40000000,TestParameter[1])); + HAL_WRITE32(0x40000000,TestParameter[1],0); + HAL_WRITE16(0x40000000,TestParameter[1],0x1234); + DiagPrintf("w16: 0x%x\n", HAL_READ32(0x40000000,TestParameter[1])); + HAL_WRITE32(0x40000000,TestParameter[1],0); + HAL_WRITE8(0x40000000,TestParameter[1],0x12); + DiagPrintf("w8: 0x%x\n", HAL_READ32(0x40000000,TestParameter[1])); + HAL_WRITE32(0x40000000,TestParameter[1],0x12345678); + DiagPrintf("R32: 0x%x\n", HAL_READ32(0x40000000,TestParameter[1])); + DiagPrintf("R16: 0x%x\n", HAL_READ16(0x40000000,TestParameter[1])); + DiagPrintf("R8: 0x%x\n", HAL_READ8(0x40000000,TestParameter[1])); + Rtemp = ((HAL_READ32(0x40000000,0xf4))?1:0); + DiagPrintf("R: 0x%x\n", Rtemp); + break; + + case 15: + asm volatile + ( + "MRS R0, BASEPRI\n" + "MOV %0, R0\n" + :"=r"(Rtemp) + ::"memory" + ); + DiagPrintf("basepri: 0x%x\n", Rtemp); + break; + case 16: + HalDelayUs(10000000); + DSleep_GPIO(); + break; + case 17: + DSleep_Timer(TestParameter[1]); + break; + case 18: + DiagPrintf("WDG CAL\n"); + { + u8 CountId; + u16 DivFactor; + u32 CountTemp; + u32 CountProcess = 0; + u32 DivFacProcess = 0; + u32 MinPeriodTemp = 0xFFFFFFFF; + u32 PeriodTemp = 0; + + DBG_8195A(" Period = %d\n", TestParameter[1]); + + for (CountId = 0; CountId < 12; CountId++) { + CountTemp = ((0x00000001 << (CountId+1))-1); + DivFactor = (u16)((100*TestParameter[1])/(CountTemp*3)); + + if (DivFactor > 0) { + PeriodTemp = 3*(DivFactor+1)*CountTemp; + DBG_8195A("PeriodTemp = %d\n", PeriodTemp); + if ((100*TestParameter[1]) PeriodTemp) { + MinPeriodTemp = PeriodTemp; + CountProcess = CountTemp; + DivFacProcess = DivFactor; + } + } + } + } + DBG_8195A("MinPeriodTemp = %d\n", MinPeriodTemp); + DBG_8195A("WdgScalar = 0x%08x\n", DivFacProcess); + DBG_8195A("WdgCunLimit = 0x%08x\n", CountProcess); + } + break; + + case 19: + DBG_8195A("DeepStandby~~~\n"); + DeepStandby(TestParameter[1],TestParameter[2],TestParameter[3]); + break; + + case 20: + DBG_8195A("SleepCG~~~\n"); + if (TestParameter[1]&BIT1){ + InitTimerTest(); + } + SleepCG(TestParameter[1],TestParameter[2],TestParameter[3],TestParameter[4]); + break; + + case 25: + { + //dslp + DBG_8195A("DSLP~~~\n"); + + HalDelayUs(3000000); + + GpioPsPullCtrl(); + + DeepSleep(TestParameter[1],TestParameter[2]); + } + break; + + case 26: + //dstby + DBG_8195A("DSTBY~~~\n"); + + GpioPsPullCtrl(); + + DeepStandby(TestParameter[1],TestParameter[2],TestParameter[3]); + break; + + case 28: + //slpcg + DBG_8195A("SLPCG~~~\n"); + while(1) { + + HalDelayUs(100); + + if (HAL_READ8(LOG_UART_REG_BASE,0x14)&BIT6){ + + break; + } + } + HAL_WRITE32(SYSTEM_CTRL_BASE, 0X2c0, 0x0); + + GpioPsPullCtrl(); + + SleepCG(TestParameter[2],TestParameter[3],TestParameter[4],TestParameter[5]); + break; + + default: + break; + } + + +} +#endif //CONFIG_SOC_PS_VERIFY +#endif //CONFIG_SOC_PS_MODULE + diff --git a/lib/fwlib/src/hal_ssi.c b/lib/fwlib/src/hal_ssi.c new file mode 100644 index 0000000..0431233 --- /dev/null +++ b/lib/fwlib/src/hal_ssi.c @@ -0,0 +1,377 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#include "rtl8195a.h" +#include "hal_ssi.h" + +const HAL_GDMA_CHNL Ssi2_TX_GDMA_Chnl_Option[] = { + {0,4,GDMA0_CHANNEL4_IRQ,0}, + {0,5,GDMA0_CHANNEL5_IRQ,0}, + {0,3,GDMA0_CHANNEL3_IRQ,0}, + {0,0,GDMA0_CHANNEL0_IRQ,0}, + {0,1,GDMA0_CHANNEL1_IRQ,0}, + {0,2,GDMA0_CHANNEL2_IRQ,0}, + + {0xff,0,0,0} // end +}; + +const HAL_GDMA_CHNL Ssi2_RX_GDMA_Chnl_Option[] = { + {1,4,GDMA1_CHANNEL4_IRQ,0}, + {1,5,GDMA1_CHANNEL5_IRQ,0}, + {1,3,GDMA1_CHANNEL3_IRQ,0}, + {1,0,GDMA1_CHANNEL0_IRQ,0}, + {1,1,GDMA1_CHANNEL1_IRQ,0}, + {1,2,GDMA1_CHANNEL2_IRQ,0}, + + {0xff,0,0,0} // end +}; + +//TODO: Load default Setting: It should be loaded from external setting file. +const DW_SSI_DEFAULT_SETTING SpiDefaultSetting = +{ + .RxCompCallback = NULL, + .RxCompCbPara = NULL, + .RxData = NULL, + .TxCompCallback = NULL, + .TxCompCbPara = NULL, + .TxData = NULL, + .DmaRxDataLevel = 7, // RX FIFO stored bytes > (DMARDLR(7) + 1) then trigger DMA transfer + .DmaTxDataLevel = 48, // TX FIFO free space > (FIFO_SPACE(64)-DMATDLR(48)) then trigger DMA transfer + .InterruptPriority = 0x20, + .RxLength = 0, + .RxLengthRemainder = 0, + .RxThresholdLevel = 7, // if number of entries in th RX FIFO >= (RxThresholdLevel+1), RX interrupt asserted + .TxLength = 0, + .TxThresholdLevel = 8, // if number of entries in th TX FIFO <= TxThresholdLevel, TX interrupt asserted + .SlaveSelectEnable = 0, + .ClockDivider = SSI_CLK_SPI0_2/1000000, // SCLK=1M + .DataFrameNumber = 0, + .ControlFrameSize = CFS_1_BIT, + .DataFrameFormat = FRF_MOTOROLA_SPI, + .DataFrameSize = DFS_8_BITS, + .DmaControl = 0, // default DMA is disable + .InterruptMask = 0x0, + .MicrowireDirection = MW_DIRECTION_MASTER_TO_SLAVE, + .MicrowireHandshaking = MW_HANDSHAKE_DISABLE, + .MicrowireTransferMode = MW_TMOD_NONSEQUENTIAL, + .SclkPhase = SCPH_TOGGLES_AT_START, + .SclkPolarity = SCPOL_INACTIVE_IS_HIGH, + .SlaveOutputEnable = SLV_TXD_ENABLE, // Slave + .TransferMode = TMOD_TR, + .TransferMechanism = SSI_DTM_INTERRUPT +}; + +extern HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor); +extern HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor); +extern HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor); +extern HAL_Status HalSsiDeInitRtl8195a(VOID * Adapter); +extern HAL_Status HalSsiClockOffRtl8195a(VOID * Adapter); +extern HAL_Status HalSsiClockOnRtl8195a(VOID * Adapter); +extern HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length); +extern HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length); +extern VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate); +#ifdef CONFIG_GDMA_EN +extern VOID HalSsiDmaInitRtl8195a(VOID *Adapter); +#endif + +VOID HalSsiOpInit(VOID *Adaptor) +{ + PHAL_SSI_OP pHalSsiOp = (PHAL_SSI_OP) Adaptor; + +// pHalSsiOp->HalSsiPinmuxEnable = HalSsiPinmuxEnableRtl8195a; + pHalSsiOp->HalSsiPinmuxEnable = HalSsiPinmuxEnableRtl8195a_Patch; + pHalSsiOp->HalSsiPinmuxDisable = HalSsiPinmuxDisableRtl8195a; + pHalSsiOp->HalSsiEnable = HalSsiEnableRtl8195a; + pHalSsiOp->HalSsiDisable = HalSsiDisableRtl8195a; +// pHalSsiOp->HalSsiInit = HalSsiInitRtl8195a; + pHalSsiOp->HalSsiInit = HalSsiInitRtl8195a_Patch; + pHalSsiOp->HalSsiSetSclkPolarity = HalSsiSetSclkPolarityRtl8195a; + pHalSsiOp->HalSsiSetSclkPhase = HalSsiSetSclkPhaseRtl8195a; + pHalSsiOp->HalSsiWrite = HalSsiWriteRtl8195a; + pHalSsiOp->HalSsiRead = HalSsiReadRtl8195a; + pHalSsiOp->HalSsiGetRxFifoLevel = HalSsiGetRxFifoLevelRtl8195a; + pHalSsiOp->HalSsiGetTxFifoLevel = HalSsiGetTxFifoLevelRtl8195a; + pHalSsiOp->HalSsiGetStatus = HalSsiGetStatusRtl8195a; + pHalSsiOp->HalSsiGetInterruptStatus = HalSsiGetInterruptStatusRtl8195a; + pHalSsiOp->HalSsiLoadSetting = HalSsiLoadSettingRtl8195a; + pHalSsiOp->HalSsiSetInterruptMask = HalSsiSetInterruptMaskRtl8195a; + pHalSsiOp->HalSsiGetInterruptMask = HalSsiGetInterruptMaskRtl8195a; + pHalSsiOp->HalSsiSetDeviceRole = HalSsiSetDeviceRoleRtl8195a; + pHalSsiOp->HalSsiWriteable = HalSsiWriteableRtl8195a; + pHalSsiOp->HalSsiReadable = HalSsiReadableRtl8195a; + pHalSsiOp->HalSsiBusy = HalSsiBusyRtl8195a; + pHalSsiOp->HalSsiInterruptEnable = HalSsiInterruptEnableRtl8195a; + pHalSsiOp->HalSsiInterruptDisable = HalSsiInterruptDisableRtl8195a; +// pHalSsiOp->HalSsiReadInterrupt = HalSsiReadInterruptRtl8195a; + pHalSsiOp->HalSsiReadInterrupt = HalSsiIntReadRtl8195a; + pHalSsiOp->HalSsiSetRxFifoThresholdLevel = HalSsiSetRxFifoThresholdLevelRtl8195a; + pHalSsiOp->HalSsiSetTxFifoThresholdLevel = HalSsiSetTxFifoThresholdLevelRtl8195a; +// pHalSsiOp->HalSsiWriteInterrupt = HalSsiWriteInterruptRtl8195a; + pHalSsiOp->HalSsiWriteInterrupt = HalSsiIntWriteRtl8195a; + pHalSsiOp->HalSsiGetRawInterruptStatus = HalSsiGetRawInterruptStatusRtl8195a; + pHalSsiOp->HalSsiGetSlaveEnableRegister = HalSsiGetSlaveEnableRegisterRtl8195a; + pHalSsiOp->HalSsiSetSlaveEnableRegister = HalSsiSetSlaveEnableRegisterRtl8195a; +} + + +#ifdef CONFIG_GDMA_EN + +HAL_Status +HalSsiTxGdmaInit( + IN PHAL_SSI_OP pHalSsiOp, + IN PHAL_SSI_ADAPTOR pHalSsiAdapter +) +{ + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + PSSI_DMA_CONFIG pDmaConfig; + HAL_GDMA_CHNL *pgdma_chnl; + PHAL_GDMA_OP pHalGdmaOp; + + if ((NULL == pHalSsiOp) || (NULL == pHalSsiAdapter)) { + return HAL_ERR_PARA; + } + + pDmaConfig = &pHalSsiAdapter->DmaConfig; + + // Load default setting + HalSsiTxGdmaLoadDefRtl8195a((void*)pHalSsiAdapter); + + // Start to patch the default setting + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter; + if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) { + // The default GDMA Channel is not available, try others + if (pHalSsiAdapter->Index == 2) { + // SSI2 TX Only can use GDMA 0 + pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Ssi2_TX_GDMA_Chnl_Option); + } + else { + pgdma_chnl = HalGdmaChnlAlloc(NULL); + } + + if (pgdma_chnl == NULL) { + // No Available DMA channel + return HAL_BUSY; + } + else { + pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx; + pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl; + pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl; + pDmaConfig->TxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum; + } + } + + DBG_SSI_INFO("HalSsiTxGdmaInit: GdmaIndex=%d ChNum=%d \r\n", pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum); + pHalGdmaOp = (PHAL_GDMA_OP)pDmaConfig->pHalGdmaOp; + pHalGdmaOp->HalGdmaOnOff((VOID*)(pHalGdmaAdapter)); + pHalGdmaOp->HalGdmaChIsrEnAndDis((VOID*)(pHalGdmaAdapter)); + + HalSsiDmaInit(pHalSsiAdapter); + InterruptRegister(&pDmaConfig->TxGdmaIrqHandle); + InterruptEn(&pDmaConfig->TxGdmaIrqHandle); + + return HAL_OK; +} + +VOID +HalSsiTxGdmaDeInit( + IN PHAL_SSI_ADAPTOR pHalSsiAdapter +) +{ + PSSI_DMA_CONFIG pDmaConfig; + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + HAL_GDMA_CHNL GdmaChnl; + + if (NULL == pHalSsiAdapter) { + return; + } + + pDmaConfig = &pHalSsiAdapter->DmaConfig; + + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter; + GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex; + GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum; + GdmaChnl.IrqNum = pDmaConfig->TxGdmaIrqHandle.IrqNum; + HalGdmaChnlFree(&GdmaChnl); +} + + +HAL_Status +HalSsiRxGdmaInit( + IN PHAL_SSI_OP pHalSsiOp, + IN PHAL_SSI_ADAPTOR pHalSsiAdapter +) +{ + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + PSSI_DMA_CONFIG pDmaConfig; + HAL_GDMA_CHNL *pgdma_chnl; + PHAL_GDMA_OP pHalGdmaOp; + + if ((NULL == pHalSsiOp) || (NULL == pHalSsiAdapter)) { + return HAL_ERR_PARA; + } + + pDmaConfig = &pHalSsiAdapter->DmaConfig; + // Load default setting + HalSsiRxGdmaLoadDefRtl8195a((void*)pHalSsiAdapter); + + // Start to patch the default setting + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter; + if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) { + // The default GDMA Channel is not available, try others + if (pHalSsiAdapter->Index == 2) { + // SSI2 RX Only can use GDMA 1 + pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Ssi2_RX_GDMA_Chnl_Option); + } + else { + pgdma_chnl = HalGdmaChnlAlloc(NULL); + } + + if (pgdma_chnl == NULL) { + // No Available DMA channel + return HAL_BUSY; + } + else { + pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx; + pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl; + pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl; + pDmaConfig->RxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum; + } + } + + DBG_SSI_INFO("HalSsiRxGdmaInit: GdmaIndex=%d ChNum=%d \r\n", pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum); + pHalGdmaOp = (PHAL_GDMA_OP)pDmaConfig->pHalGdmaOp; + pHalGdmaOp->HalGdmaOnOff((VOID*)(pHalGdmaAdapter)); + pHalGdmaOp->HalGdmaChIsrEnAndDis((VOID*)(pHalGdmaAdapter)); + + HalSsiDmaInit(pHalSsiAdapter); + InterruptRegister(&pDmaConfig->RxGdmaIrqHandle); + InterruptEn(&pDmaConfig->RxGdmaIrqHandle); + + return HAL_OK; +} + +VOID +HalSsiRxGdmaDeInit( + IN PHAL_SSI_ADAPTOR pHalSsiAdapter +) +{ + PSSI_DMA_CONFIG pDmaConfig; + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + HAL_GDMA_CHNL GdmaChnl; + + if (NULL == pHalSsiAdapter) { + return; + } + + pDmaConfig = &pHalSsiAdapter->DmaConfig; + + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter; + GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex; + GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum; + GdmaChnl.IrqNum = pDmaConfig->RxGdmaIrqHandle.IrqNum; + HalGdmaChnlFree(&GdmaChnl); +} + +#endif // end of "#ifdef CONFIG_GDMA_EN" + +HAL_Status +HalSsiInit(VOID *Data) +{ + HAL_Status ret; + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE SsiPwrState; +#endif + ret = HalSsiInitRtl8195a_Patch(pHalSsiAdapter); +#ifdef CONFIG_SOC_PS_MODULE + if(ret == HAL_OK) { + // To register a new peripheral device power state + SsiPwrState.FuncIdx = SPI0+ pHalSsiAdapter->Index; + SsiPwrState.PwrState = ACT; + RegPowerState(SsiPwrState); + } +#endif + + return ret; +} + +HAL_Status +HalSsiDeInit(VOID *Data) +{ + HAL_Status ret; + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE SsiPwrState; + u8 HardwareState; + + SsiPwrState.FuncIdx= SPI0+ pHalSsiAdapter->Index; + QueryRegPwrState(SsiPwrState.FuncIdx, &(SsiPwrState.PwrState), &HardwareState); + + if(SsiPwrState.PwrState != HardwareState){ + DBG_SSI_ERR("Registered State is not the Hardware State"); + return HAL_ERR_UNKNOWN; + } + else{ + if((SsiPwrState.PwrState != INACT) && (SsiPwrState.PwrState !=ACT)){ + DBG_SSI_INFO("Return to ACT state before DeInit"); + HalSsiEnable(pHalSsiAdapter); + QueryRegPwrState(SsiPwrState.FuncIdx, &(SsiPwrState.PwrState), &HardwareState); + } + if(SsiPwrState.PwrState == ACT){ + SsiPwrState.PwrState = INACT; + RegPowerState(SsiPwrState); + } + } +#endif + ret = HalSsiDeInitRtl8195a(pHalSsiAdapter); + return ret; +} + + +HAL_Status +HalSsiEnable(VOID *Data) +{ + HAL_Status ret; + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE SsiPwrState; +#endif + ret = HalSsiClockOnRtl8195a(pHalSsiAdapter); +#ifdef CONFIG_SOC_PS_MODULE + if(ret == HAL_OK) { + // To register a new peripheral device power state + SsiPwrState.FuncIdx = SPI0+ pHalSsiAdapter->Index; + SsiPwrState.PwrState = ACT; + RegPowerState(SsiPwrState); + } +#endif + + return ret; +} + +HAL_Status +HalSsiDisable(VOID *Data) +{ + HAL_Status ret; + PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE SsiPwrState; +#endif + ret = HalSsiClockOffRtl8195a(pHalSsiAdapter); +#ifdef CONFIG_SOC_PS_MODULE + if(ret == HAL_OK) { + // To register a new peripheral device power state + SsiPwrState.FuncIdx = SPI0+ pHalSsiAdapter->Index; + SsiPwrState.PwrState = SLPCG; + RegPowerState(SsiPwrState); + } +#endif + + return ret; +} \ No newline at end of file diff --git a/lib/fwlib/src/hal_timer.c b/lib/fwlib/src/hal_timer.c new file mode 100644 index 0000000..617b593 --- /dev/null +++ b/lib/fwlib/src/hal_timer.c @@ -0,0 +1,32 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "rtl8195a.h" + +VOID +HalTimerOpInit_Patch( + IN VOID *Data +) +{ + PHAL_TIMER_OP pHalTimerOp = (PHAL_TIMER_OP) Data; + + pHalTimerOp->HalGetTimerId = HalGetTimerIdRtl8195a; + pHalTimerOp->HalTimerInit = (BOOL (*)(void*))HalTimerInitRtl8195a_Patch; +#ifdef CONFIG_CHIP_C_CUT + pHalTimerOp->HalTimerReadCount = HalTimerReadCountRtl8195aV02; +#else + pHalTimerOp->HalTimerReadCount = HalTimerReadCountRtl8195a_Patch; +#endif + pHalTimerOp->HalTimerIrqClear = HalTimerIrqClearRtl8195a; + pHalTimerOp->HalTimerDis = HalTimerDisRtl8195a_Patch; + pHalTimerOp->HalTimerEn = HalTimerEnRtl8195a_Patch; + pHalTimerOp->HalTimerDumpReg = HalTimerDumpRegRtl8195a; +} + diff --git a/lib/fwlib/src/hal_uart.c b/lib/fwlib/src/hal_uart.c new file mode 100644 index 0000000..6703357 --- /dev/null +++ b/lib/fwlib/src/hal_uart.c @@ -0,0 +1,871 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + + +#include "rtl8195a.h" +#include "rtl8195a_uart.h" +#include "hal_uart.h" +#include "hal_gdma.h" + +#ifndef CONFIG_CHIP_E_CUT +// Pre-Defined Supported Baud Rate Table for CPU 166 MHz +const u32 DEF_BAUDRATE_TABLE[] = { + 110, 300, 600, 1200, + 2400, 4800, 9600, 14400, + 19200, 28800, 38400, 57600, + 76800, 115200, 128000, 153600, + 230400, 380400, 460800, 500000, + 921600, 1000000, 1382400, 1444400, + 1500000, 1843200, 2000000, 2100000, + 2764800, 3000000, 3250000, 3692300, + 3750000, 4000000, 6000000, + + 56000, 256000, + + // For UART to IR Carrier + 66000, 72000, 73400, 76000, + 80000, 112000, + + // End of the table + 0xffffffff +}; + +const u16 ovsr_adj_table_10bit[10] = { + 0x000, 0x020, 0x044, 0x124, 0x294, 0x2AA, 0x16B, 0x2DB, 0x3BB, 0x3EF +}; + +const u16 ovsr_adj_table_9bit[9] = { + 0x000, 0x010, 0x044, 0x92, 0xAA, 0x155, 0x1B6, 0x1BB, 0x1EF +}; + +const u16 ovsr_adj_table_8bit[8] = { + 0x000, 0x010, 0x044, 0x92, 0xAA, 0xB5, 0xBB, 0xEF +}; + +#if 0 // Old format +#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) + +const u8 DEF_OVSR_166[] = { + 10, 10, 12, 14, + 10, 10, 10, 11, + 14, 11, 14, 11, + 14, 10, 11, 14, + 18, 17, 17, 18, + 17, 13, 19, 18, + 10, 11, 13, 19, + 14, 13, 12, 11, + 10, 10, 13, + + 20, 18, + + // For UART to IR Carrier + 13, 13, 18, 15, + 20, 12, +}; + +const u16 DEF_DIV_166[] = { + 74272, 27233, 11347, 4863, + 3404, 1702, 851, 516, + 304, 258, 152, 129, + 76, 71, 58, 38, + 19, 12, 10, 9, + 5, 6, 3, 3, + 5, 4, 3, 2, + 2, 2, 2, 2, + 2, 2, 1, + + 73, 17, + + // For UART to IR Carrier + 97, 89, 63, 73, + 52, 62, +}; + + +const u16 DEF_OVSR_ADJ_166[] = { + 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, + 0x2AA, 0x3BB, 0x1B6, 0x010, + 0x1B6, 0x2AA, 0x1B6, 0x2DB, + 0x3BB, 0x000, 0x2AA, 0x294, + 0x2DB, 0x2AA, 0x2AA, 0x000 , + 0x3BB, 0x088, 0x2AA, + + 0x000, 0x2DB, + + // For UART to IR Carrier + 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000 +}; +#endif //#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) + +#ifdef CONFIG_CHIP_C_CUT + +const u8 DEF_OVSR_166[] = { + 13, 12, 12, 12, + 18, 10, 10, 11, + 10, 11, 10, 20, + 20, 20, 20, 20, + 20, 18, 20, 12, + 15, 16, 20, 19, + 18, 15, 10, 13, + 15, 13, 12, 11, + 11, 10, 13, + + 16, 18, + + // For UART to IR Carrier + 13, 13, 18, 15, + 20, 12, +}; + +const u16 DEF_DIV_166[] = { + 58275, 23148, 11574, 5787, + 1929, 1736, 868, 526, + 434, 263, 217, 72, + 54, 36, 32, 27, + 18, 12, 9, 13, + 6, 5, 3, 3, + 3, 3, 4, 3, + 2, 2, 2, 2, + 2, 2, 1, + + 93, 18, + + // For UART to IR Carrier + 97, 89, 63, 73, + 52, 62, +}; + +const u16 DEF_OVSR_ADJ_166[] = { + 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000, 0x000, 0x010, + 0x010, 0x010, 0x124, 0x010, + 0x010, 0x088, 0x010, 0x2DB, + 0x000, 0x16B, 0x010, 0x088, + 0x2AA, 0x000, 0x294, 0x088, + 0x000, 0x3BB, 0x3BB, 0x088, + 0x010, 0x294, 0x3BB, + + 0x000, 0x010, + + // For UART to IR Carrier + 0x000, 0x000, 0x000, 0x000, + 0x000, 0x000 +}; + +#endif // #ifdef CONFIG_CHIP_C_CUT +#endif // end of #if 0 // Old format + +#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) +const u8 DEF_OVSR_B_CUT[] = { + 20, 20, 20, 20, + 20, 20, 15, 18, + 13, 15, 18, 13, + 18, 12, 11, 10, + 16, 15, 16, 18, + 11, 20, 19, 14, + 18, 11, 20, 19, + 14, 13, 12, 11, + 21, 20, 13, + + 18, 11, + + // For UART to IR Carrier + 13, 13, 18, 15, + 20, 12 + +}; + +const u16 DEF_DIV_B_CUT[] = { + 37202, 13616, 6808, 3404, + 1702, 851, 567, 315, + 327, 189, 118, 109, + 59, 59, 58, 53, + 22, 14, 11, 9, + 8, 4, 3, 4, + 3, 4, 2, 2, + 2, 2, 2, 2, + 1, 1, 1, + + 81, 29, + + // For UART to IR Carrier + 97, 89, 63, 73, + 52, 62 +}; + +const u8 DEF_OVSR_ADJ_BITS_B_CUT_10B[] = { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 3, 1, 2, + 1, 4, 7, 1, + 2, 1, 4, 5, + 8, 6, 6, 1, + 8, 4, 6, + + 0, 0, + + // For UART to IR Carrier + 0, 0, 0, 0, + 0, 0 + +}; + +const u8 DEF_OVSR_ADJ_BITS_B_CUT_9B[] = { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 3, 1, 1, + 1, 4, 6, 1, + 1, 1, 4, 4, + 7, 6, 5, 1, + 7, 4, 6, + + 0, 0, + + // For UART to IR Carrier + 0, 0, 0, 0, + 0, 0 + +}; + +const u8 DEF_OVSR_ADJ_BITS_B_CUT_8B[] = { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 3, 1, 1, + 1, 4, 6, 1, + 1, 1, 4, 4, + 6, 5, 5, 1, + 6, 4, 5, + + 0, 0, + + // For UART to IR Carrier + 0, 0, 0, 0, + 0, 0 +}; + +#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) + +const u8 DEF_OVSR_C_CUT[] = { + 20, 20, 20, 20, + 20, 20, 20, 14, + 20, 12, 14, 19, + 19, 19, 13, 20, + 19, 18, 20, 15, + 18, 20, 20, 19, + 11, 15, 20, 13, + 15, 13, 12, 11, + 11, 20, 13, + + 16, 13, + + // For UART to IR Carrier + 13, 13, 18, 15, + 20, 12 +}; + +const u16 DEF_DIV_C_CUT[] = { + 37878, 13888, 6944, 3472, + 1736, 868, 434, 413, + 217, 241, 155, 76, + 57, 38, 50, 27, + 19, 12, 9, 11, + 5, 4, 3, 3, + 5, 3, 2, 3, + 2, 2, 2, 2, + 2, 1, 1, + + 93, 25, + + // For UART to IR Carrier + 97, 89, 63, 73, + 52, 62 +}; + +const u8 DEF_OVSR_ADJ_BITS_C_CUT_10B[] = { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 1, + 0, 3, 1, 2, + 1, 8, 1, 2, + 1, 1, 8, 2, + 1, 9, 8, 3, + 1, 8, 9, + + 0, 0, + + // For UART to IR Carrier + 0, 0, 0, 0, + 0, 0 + +}; + +const u8 DEF_OVSR_ADJ_BITS_C_CUT_9B[] = { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 1, + 0, 2, 1, 1, + 1, 8, 1, 2, + 1, 1, 8, 2, + 1, 8, 8, 3, + 1, 8, 8, + + 0, 0, + + // For UART to IR Carrier + 0, 0, 0, 0, + 0, 0 + +}; + +const u8 DEF_OVSR_ADJ_BITS_C_CUT_8B[] = { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 1, + 0, 2, 1, 1, + 1, 7, 1, 2, + 1, 1, 7, 2, + 1, 7, 7, 2, + 1, 7, 7, + + 0, 0, + + // For UART to IR Carrier + 0, 0, 0, 0, + 0, 0 +}; + +#endif // #if !(CONFIG_CHIP_E_CUT) + +extern u32 _UartIrqHandle(VOID *Data); + +extern HAL_Status +HalRuartInitRtl8195a_Patch( + IN VOID *Data ///< RUART Adapter + ); + +#if (CONFIG_CHIP_C_CUT) +extern _LONG_CALL_ HAL_Status +HalRuartInitRtl8195aV02( + IN VOID *Data ///< RUART Adapter + ); +#endif + +extern u8 HalRuartGetChipVerRtl8195a(VOID); + +const HAL_GDMA_CHNL Uart2_TX_GDMA_Chnl_Option[] = { + {0,0,GDMA0_CHANNEL0_IRQ,0}, + {0,1,GDMA0_CHANNEL1_IRQ,0}, + {0,2,GDMA0_CHANNEL2_IRQ,0}, + {0,3,GDMA0_CHANNEL3_IRQ,0}, + {0,4,GDMA0_CHANNEL4_IRQ,0}, + {0,5,GDMA0_CHANNEL5_IRQ,0}, + + {0xff,0,0,0} // end +}; + +const HAL_GDMA_CHNL Uart2_RX_GDMA_Chnl_Option[] = { + {1,0,GDMA1_CHANNEL0_IRQ,0}, + {1,1,GDMA1_CHANNEL1_IRQ,0}, + {1,2,GDMA1_CHANNEL2_IRQ,0}, + {1,3,GDMA1_CHANNEL3_IRQ,0}, + {1,4,GDMA1_CHANNEL4_IRQ,0}, + {1,5,GDMA1_CHANNEL5_IRQ,0}, + + {0xff,0,0,0} // end +}; + +VOID +HalRuartOpInit( + IN VOID *Data +) +{ + PHAL_RUART_OP pHalRuartOp = (PHAL_RUART_OP) Data; + + pHalRuartOp->HalRuartAdapterLoadDef = HalRuartAdapterLoadDefRtl8195a; + pHalRuartOp->HalRuartTxGdmaLoadDef = HalRuartTxGdmaLoadDefRtl8195a; + pHalRuartOp->HalRuartRxGdmaLoadDef = HalRuartRxGdmaLoadDefRtl8195a; + pHalRuartOp->HalRuartResetRxFifo = HalRuartResetRxFifoRtl8195a; +#if CONFIG_CHIP_E_CUT + pHalRuartOp->HalRuartInit = HalRuartInitRtl8195a_V04; +#else + pHalRuartOp->HalRuartInit = HalRuartInitRtl8195a_Patch; // Hardware Init ROM code patch +#endif + pHalRuartOp->HalRuartDeInit = HalRuartDeInitRtl8195a; // Hardware Init + pHalRuartOp->HalRuartPutC = HalRuartPutCRtl8195a; // Send a byte + pHalRuartOp->HalRuartSend = HalRuartSendRtl8195a; // Polling mode Tx + pHalRuartOp->HalRuartIntSend = HalRuartIntSendRtl8195a; // Interrupt mode Tx +#if CONFIG_CHIP_E_CUT + pHalRuartOp->HalRuartDmaSend = HalRuartDmaSendRtl8195a_V04; // DMA mode Tx + pHalRuartOp->HalRuartStopSend = HalRuartStopSendRtl8195a_V04; // Stop non-blocking TX +#else + pHalRuartOp->HalRuartDmaSend = HalRuartDmaSendRtl8195a_Patch; // DMA mode Tx + pHalRuartOp->HalRuartStopSend = HalRuartStopSendRtl8195a_Patch; // Stop non-blocking TX +#endif + pHalRuartOp->HalRuartGetC = HalRuartGetCRtl8195a; // get a byte + pHalRuartOp->HalRuartRecv = HalRuartRecvRtl8195a; // Polling mode Rx + pHalRuartOp->HalRuartIntRecv = HalRuartIntRecvRtl8195a; // Interrupt mode Rx + pHalRuartOp->HalRuartDmaRecv = HalRuartDmaRecvRtl8195a; // DMA mode Rx +#if CONFIG_CHIP_E_CUT + pHalRuartOp->HalRuartStopRecv = HalRuartStopRecvRtl8195a_V04; // Stop non-blocking Rx +#else + pHalRuartOp->HalRuartStopRecv = HalRuartStopRecvRtl8195a_Patch; // Stop non-blocking Rx +#endif + pHalRuartOp->HalRuartGetIMR = HalRuartGetIMRRtl8195a; + pHalRuartOp->HalRuartSetIMR = HalRuartSetIMRRtl8195a; + pHalRuartOp->HalRuartGetDebugValue = HalRuartGetDebugValueRtl8195a; + pHalRuartOp->HalRuartDmaInit = HalRuartDmaInitRtl8195a; + pHalRuartOp->HalRuartRTSCtrl = HalRuartRTSCtrlRtl8195a; + pHalRuartOp->HalRuartRegIrq = HalRuartRegIrqRtl8195a; + pHalRuartOp->HalRuartIntEnable = HalRuartIntEnableRtl8195a; + pHalRuartOp->HalRuartIntDisable = HalRuartIntDisableRtl8195a; +} + +/** + * Load UART HAL default setting + * + * Call this function to load the default setting for UART HAL adapter + * + * + */ +VOID +HalRuartAdapterInit( + PRUART_ADAPTER pRuartAdapter, + u8 UartIdx +) +{ + PHAL_RUART_OP pHalRuartOp; + PHAL_RUART_ADAPTER pHalRuartAdapter; + + if (NULL == pRuartAdapter) { + return; + } + + pHalRuartOp = pRuartAdapter->pHalRuartOp; + pHalRuartAdapter = pRuartAdapter->pHalRuartAdapter; + + if ((NULL == pHalRuartOp) || (NULL == pHalRuartAdapter)) { + return; + } + + // Load default setting + if (pHalRuartOp->HalRuartAdapterLoadDef != NULL) { + pHalRuartOp->HalRuartAdapterLoadDef (pHalRuartAdapter, UartIdx); + pHalRuartAdapter->IrqHandle.Priority = 6; + } + else { + // Initial your UART HAL adapter here + } + + // Start to modify the defualt setting + pHalRuartAdapter->PinmuxSelect = RUART0_MUX_TO_GPIOC; + pHalRuartAdapter->BaudRate = 38400; + +// pHalRuartAdapter->IrqHandle.IrqFun = (IRQ_FUN)_UartIrqHandle; +// pHalRuartAdapter->IrqHandle.Data = (void *)pHalRuartAdapter; + + // Register IRQ + InterruptRegister(&pHalRuartAdapter->IrqHandle); + +} + +/** + * Load UART HAL GDMA default setting + * + * Call this function to load the default setting for UART GDMA + * + * + */ +HAL_Status +HalRuartTxGdmaInit( + PHAL_RUART_OP pHalRuartOp, + PHAL_RUART_ADAPTER pHalRuartAdapter, + PUART_DMA_CONFIG pUartGdmaConfig +) +{ + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + HAL_GDMA_CHNL *pgdma_chnl; + + if ((NULL == pHalRuartOp) || (NULL == pHalRuartAdapter) || (NULL == pUartGdmaConfig)) { + return HAL_ERR_PARA; + } + + // Load default setting + if (pHalRuartOp->HalRuartTxGdmaLoadDef != NULL) { + pHalRuartOp->HalRuartTxGdmaLoadDef (pHalRuartAdapter, pUartGdmaConfig); + pUartGdmaConfig->TxGdmaIrqHandle.Priority = 6; + } + else { + // Initial your GDMA setting here + } + + // Start to patch the default setting + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter; + if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) { + // The default GDMA Channel is not available, try others + if (pHalRuartAdapter->UartIndex == 2) { + // UART2 TX Only can use GDMA 0 + pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Uart2_TX_GDMA_Chnl_Option); + } + else { + pgdma_chnl = HalGdmaChnlAlloc(NULL); + } + + if (pgdma_chnl == NULL) { + // No Available DMA channel + return HAL_BUSY; + } + else { + pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx; + pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl; + pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl; + pUartGdmaConfig->TxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum; + } + } + + // User can assign a Interrupt Handler here +// pUartGdmaConfig->TxGdmaIrqHandle.Data = pHalRuartAdapter; +// pUartGdmaConfig->TxGdmaIrqHandle.IrqFun = (IRQ_FUN)_UartTxDmaIrqHandle +// pUartGdmaConfig->TxGdmaIrqHandle.Priority = 0x20; + + pHalRuartOp->HalRuartDmaInit (pHalRuartAdapter); + InterruptRegister(&pUartGdmaConfig->TxGdmaIrqHandle); + InterruptEn(&pUartGdmaConfig->TxGdmaIrqHandle); + + return HAL_OK; +} + +VOID +HalRuartTxGdmaDeInit( + PUART_DMA_CONFIG pUartGdmaConfig +) +{ + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + HAL_GDMA_CHNL GdmaChnl; + + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter; + GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex; + GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum; + GdmaChnl.IrqNum = pUartGdmaConfig->TxGdmaIrqHandle.IrqNum; + HalGdmaChnlFree(&GdmaChnl); +} + +/** + * Load UART HAL GDMA default setting + * + * Call this function to load the default setting for UART GDMA + * + * + */ +HAL_Status +HalRuartRxGdmaInit( + PHAL_RUART_OP pHalRuartOp, + PHAL_RUART_ADAPTER pHalRuartAdapter, + PUART_DMA_CONFIG pUartGdmaConfig +) +{ + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + HAL_GDMA_CHNL *pgdma_chnl; + + if ((NULL == pHalRuartOp) || (NULL == pHalRuartAdapter) || (NULL == pUartGdmaConfig)) { + return HAL_ERR_PARA; + } + + // Load default setting + if (pHalRuartOp->HalRuartRxGdmaLoadDef != NULL) { + pHalRuartOp->HalRuartRxGdmaLoadDef (pHalRuartAdapter, pUartGdmaConfig); + pUartGdmaConfig->RxGdmaIrqHandle.Priority = 6; + } + else { + // Initial your GDMA setting here + } + + // Start to patch the default setting + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pRxHalGdmaAdapter; + if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) { + // The default GDMA Channel is not available, try others + if (pHalRuartAdapter->UartIndex == 2) { + // UART2 RX Only can use GDMA 1 + pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Uart2_RX_GDMA_Chnl_Option); + } + else { + pgdma_chnl = HalGdmaChnlAlloc(NULL); + } + + if (pgdma_chnl == NULL) { + // No Available DMA channel + return HAL_BUSY; + } + else { + pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx; + pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl; + pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl; + pUartGdmaConfig->RxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum; + } + } + +// pUartGdmaConfig->RxGdmaIrqHandle.Data = pHalRuartAdapter; +// pUartGdmaConfig->RxGdmaIrqHandle.IrqFun = (IRQ_FUN)_UartTxDmaIrqHandle; +// pUartGdmaConfig->RxGdmaIrqHandle.Priority = 0x20; + + pHalRuartOp->HalRuartDmaInit (pHalRuartAdapter); + InterruptRegister(&pUartGdmaConfig->RxGdmaIrqHandle); + InterruptEn(&pUartGdmaConfig->RxGdmaIrqHandle); + + return HAL_OK; +} + +VOID +HalRuartRxGdmaDeInit( + PUART_DMA_CONFIG pUartGdmaConfig +) +{ + PHAL_GDMA_ADAPTER pHalGdmaAdapter; + HAL_GDMA_CHNL GdmaChnl; + + pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pRxHalGdmaAdapter; + GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex; + GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum; + GdmaChnl.IrqNum = pUartGdmaConfig->RxGdmaIrqHandle.IrqNum; + HalGdmaChnlFree(&GdmaChnl); +} + +/** + * Hook a RX indication callback + * + * To hook a callback function which will be called when a got a RX byte + * + * + */ +VOID +HalRuartRxIndHook( + PRUART_ADAPTER pRuartAdapter, + VOID *pCallback, + VOID *pPara +) +{ + PHAL_RUART_ADAPTER pHalRuartAdapter = pRuartAdapter->pHalRuartAdapter; + + pHalRuartAdapter->RxDRCallback = (void (*)(void*))pCallback; + pHalRuartAdapter->RxDRCbPara = pPara; + + // enable RX data ready interrupt + pHalRuartAdapter->Interrupts |= RUART_IER_ERBI | RUART_IER_ELSI; + pRuartAdapter->pHalRuartOp->HalRuartSetIMR(pHalRuartAdapter); +} + + +HAL_Status +HalRuartResetTxFifo( + IN VOID *Data +) +{ + return (HalRuartResetTxFifoRtl8195a(Data)); +} + +HAL_Status +HalRuartSetBaudRate( + IN VOID *Data +) +{ +#if CONFIG_CHIP_E_CUT + return HalRuartSetBaudRateRtl8195a_V04(Data); +#else + return HalRuartSetBaudRateRtl8195a(Data); +#endif +} + +HAL_Status +HalRuartInit( + IN VOID *Data +) +{ + HAL_Status ret; + PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE UartPwrState; +#endif +#if CONFIG_CHIP_E_CUT + pHalRuartAdapter->pDefaultBaudRateTbl = (uint32_t*)BAUDRATE_166_ROM_V04; + pHalRuartAdapter->pDefaultOvsrRTbl = (uint8_t*)OVSR_166_ROM_V04; + pHalRuartAdapter->pDefaultOvsrAdjTbl = (uint16_t*)OVSR_ADJ_166_ROM_V04; + pHalRuartAdapter->pDefaultDivTbl = (uint16_t*)DIV_166_ROM_V04; + ret = HalRuartInitRtl8195a_V04(Data); +#else + pHalRuartAdapter->pDefaultBaudRateTbl = (uint32_t*)DEF_BAUDRATE_TABLE; +#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) + u8 chip_ver; + + chip_ver = HalRuartGetChipVerRtl8195a(); + if (chip_ver < 2) { + pHalRuartAdapter->pDefaultOvsrRTbl = (uint8_t*)DEF_OVSR_B_CUT; + pHalRuartAdapter->pDefaultDivTbl = (uint16_t*)DEF_DIV_B_CUT; + pHalRuartAdapter->pDefOvsrAdjBitTbl_10 = (uint8_t*)DEF_OVSR_ADJ_BITS_B_CUT_10B; + pHalRuartAdapter->pDefOvsrAdjBitTbl_9 = (uint8_t*)DEF_OVSR_ADJ_BITS_B_CUT_9B; + pHalRuartAdapter->pDefOvsrAdjBitTbl_8 = (uint8_t*)DEF_OVSR_ADJ_BITS_B_CUT_8B; + } + else +#endif + { + pHalRuartAdapter->pDefaultOvsrRTbl = (uint8_t*)DEF_OVSR_C_CUT; + pHalRuartAdapter->pDefaultDivTbl = (uint16_t*)DEF_DIV_C_CUT; + pHalRuartAdapter->pDefOvsrAdjBitTbl_10 = (uint8_t*)DEF_OVSR_ADJ_BITS_C_CUT_10B; + pHalRuartAdapter->pDefOvsrAdjBitTbl_9 = (uint8_t*)DEF_OVSR_ADJ_BITS_C_CUT_9B; + pHalRuartAdapter->pDefOvsrAdjBitTbl_8 = (uint8_t*)DEF_OVSR_ADJ_BITS_C_CUT_8B; + } + pHalRuartAdapter->pDefOvsrAdjTbl_10 = (uint16_t*)ovsr_adj_table_10bit; + pHalRuartAdapter->pDefOvsrAdjTbl_9 = (uint16_t*)ovsr_adj_table_9bit; + pHalRuartAdapter->pDefOvsrAdjTbl_8 = (uint16_t*)ovsr_adj_table_8bit; + + ret = HalRuartInitRtl8195a_Patch(Data); +#endif + +#ifdef CONFIG_SOC_PS_MODULE + if(ret == HAL_OK) { + // To register a new peripheral device power state + UartPwrState.FuncIdx = UART0 + pHalRuartAdapter->UartIndex; + UartPwrState.PwrState = ACT; + RegPowerState(UartPwrState); + } +#endif + return ret; +} + +VOID +HalRuartDeInit( + IN VOID *Data +) +{ +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE UartPwrState; + PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data; + u8 HwState; + + UartPwrState.FuncIdx = UART0 + pHalRuartAdapter->UartIndex; + QueryRegPwrState(UartPwrState.FuncIdx, &(UartPwrState.PwrState), &HwState); + + // if the power state isn't ACT, then switch the power state back to ACT first + if ((UartPwrState.PwrState != ACT) && (UartPwrState.PwrState != INACT)) { + HalRuartEnable(Data); + QueryRegPwrState(UartPwrState.FuncIdx, &(UartPwrState.PwrState), &HwState); + } + + if (UartPwrState.PwrState == ACT) { + UartPwrState.PwrState = INACT; + RegPowerState(UartPwrState); + } +#endif + + HalRuartDeInitRtl8195a(Data); +} + +HAL_Status +HalRuartDisable( + IN VOID *Data +) +{ + HAL_Status ret; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE UartPwrState; + PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data; +#endif + +#if CONFIG_CHIP_E_CUT + ret = HalRuartDisableRtl8195a_V04(Data); +#else + ret = HalRuartDisableRtl8195a(Data); +#endif +#ifdef CONFIG_SOC_PS_MODULE + if (ret == HAL_OK) { + UartPwrState.FuncIdx = UART0 + pHalRuartAdapter->UartIndex; + UartPwrState.PwrState = SLPCG; + RegPowerState(UartPwrState); + } +#endif + return ret; +} + +HAL_Status +HalRuartEnable( + IN VOID *Data +) +{ + HAL_Status ret; +#ifdef CONFIG_SOC_PS_MODULE + REG_POWER_STATE UartPwrState; + PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data; +#endif + +#if CONFIG_CHIP_E_CUT + ret = HalRuartEnableRtl8195a_V04(Data); +#else + ret = HalRuartEnableRtl8195a(Data); +#endif +#ifdef CONFIG_SOC_PS_MODULE + if (ret == HAL_OK) { + UartPwrState.FuncIdx = UART0 + pHalRuartAdapter->UartIndex; + UartPwrState.PwrState = ACT; + RegPowerState(UartPwrState); + } +#endif + return ret; +} + +HAL_Status +HalRuartFlowCtrl( + IN VOID *Data +) +{ + HAL_Status ret; + +#if CONFIG_CHIP_E_CUT + ret = HalRuartFlowCtrlRtl8195a_V04((VOID *)Data); +#else + ret = HalRuartFlowCtrlRtl8195a((VOID *)Data); +#endif + return ret; +} + +VOID +HalRuartEnterCritical( + IN VOID *Data +) +{ +#if CONFIG_CHIP_E_CUT + HalRuartEnterCriticalRtl8195a_V04(Data); +#else + HalRuartEnterCriticalRtl8195a(Data); +#endif +} + +VOID +HalRuartExitCritical( + IN VOID *Data +) +{ +#if CONFIG_CHIP_E_CUT + HalRuartExitCriticalRtl8195a_V04(Data); +#else + HalRuartExitCriticalRtl8195a(Data); +#endif +} + diff --git a/lib/libc/assert.h b/lib/libc/assert.h new file mode 100644 index 0000000..946dc03 --- /dev/null +++ b/lib/libc/assert.h @@ -0,0 +1,7 @@ +#ifndef _ASSERT_H_ +#define _ASSERT_H_ + +#include + +#endif + diff --git a/lib/libc/ctype.h b/lib/libc/ctype.h new file mode 100644 index 0000000..ec5f088 --- /dev/null +++ b/lib/libc/ctype.h @@ -0,0 +1,7 @@ +#ifndef _CTYPE_H_ +#define _CTYPE_H_ + +#include + +#endif + diff --git a/lib/libc/libc.c b/lib/libc/libc.c new file mode 100644 index 0000000..3685d28 --- /dev/null +++ b/lib/libc/libc.c @@ -0,0 +1,863 @@ +#include +#include +#include +#include +#include +#if defined (LIBC_GMTIME_R) || defined (LIBC_MKTIME) +#include +#endif + +#ifndef LIBC_FUNCTION_ATTRIBUTE +#define LIBC_FUNCTION_ATTRIBUTE +#endif + +#if defined (LIBC_ALL) || defined (LIBC_PUTCHAR) || defined (LIBC_PUTC) || defined (LIBC_FPUTC) || defined (LIBC_PUTS) || defined (LIBC_FPUTS) || defined (LIBC_PRINTF) || defined (LIBC_FPRINTF) || defined (LIBC_WRITE) +#if defined (GCC_VERSION) || defined (__GNUC__) +ssize_t __attribute__((weak)) write_stdout(const void *buf __attribute__((unused)), size_t count){ + return(count); +} +ssize_t __attribute__((weak, alias("write_stdout"))) write_stderr(const void *buf, size_t count); +// FILE *stdin = NULL; +FILE *stdout = write_stdout; +FILE *stderr = write_stderr; +#else +#warning no weak functions for stdio +FILE *stdout; +FILE *stderr; +#endif +#endif + +#if defined (LIBC_ALL) || defined (LIBC_SNPRINTF) || defined (LIBC_VSNPRINTF) +struct _libc_snprintf_struct{ + char *str; + size_t loc; + size_t maxlen; +}__attribute__((packed)); +#endif + +#if defined (LIBC_ALL) || defined (LIBC_SNPRINTF) || defined (LIBC_VSNPRINTF) +static int LIBC_FUNCTION_ATTRIBUTE _libc_cswrite(void *user, const void *buf, int count); +#endif +#if defined (LIBC_ALL) || defined (LIBC_PRINTF) || defined (LIBC_FPRINTF) || defined (LIBC_SNPRINTF) || defined (LIBC_VSNPRINTF) +typedef ssize_t(*stream_user_t)(void *user, const void *buf, size_t count); +#define _LIBC_PRINT_PAD_RIGHT 1 +#define _LIBC_PRINT_PAD_ZERO 2 +#define _LIBC_PRINT_BUF_LEN 32 // sellesse peavad kõik prinditavad numbrid ära mahtuma +typedef ssize_t(*stream_t)(const void *buf, size_t count); +static int LIBC_FUNCTION_ATTRIBUTE _libc_cvprintf(stream_t cb, void *user, const char *format, va_list ap); +static int LIBC_FUNCTION_ATTRIBUTE _libc_cprints(stream_t cb, void *user, const char *string, int width, int pad); +static int LIBC_FUNCTION_ATTRIBUTE _libc_cprinti(stream_t cb, void *user, int i, int b, int sg, int width, int pad, int letbase); +static int LIBC_FUNCTION_ATTRIBUTE _libc_cprintl(stream_t cb, void *user, long long int i, int b, int sg, int width, int pad, int letbase); +static int LIBC_FUNCTION_ATTRIBUTE _libc_cwrite(stream_t cb, void *user, const void *buf, size_t count); +#endif + +#if defined (LIBC_ALL) || defined (LIBC_PUTCHAR) || defined (LIBC_PRINTF) +int LIBC_FUNCTION_ATTRIBUTE putchar(int c){ + return(fputc(c, stdout)); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_PUTC) +int LIBC_FUNCTION_ATTRIBUTE putc(int c, FILE *stream){ + return(fputc(c, stream)); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_PUTCHAR) || defined (LIBC_PUTC) || defined (LIBC_FPUTC) || defined (LIBC_PRINTF) || defined (LIBC_FPRINTF) +int LIBC_FUNCTION_ATTRIBUTE fputc(int c, FILE *stream){ + stream_t cb; + unsigned char _c; + cb = (stream_t)stream; + _c = c; + cb(&_c, 1); + return(c); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_PUTS) || defined (LIBC_PRINTF) +int LIBC_FUNCTION_ATTRIBUTE puts(const char *s){ + return(fputs(s, stdout)); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_PUTS) || defined (LIBC_FPUTS) || defined (LIBC_PRINTF) || defined (LIBC_FPRINTF) +int LIBC_FUNCTION_ATTRIBUTE fputs(const char *s, FILE *stream){ + stream_t cb; + int sl; + cb = (stream_t)stream; + for(sl = 0; s[sl]; sl++); + cb(s, sl); + cb("\n", 1); + return(sl); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_PRINTF) +int LIBC_FUNCTION_ATTRIBUTE printf(const char *format, ...){ + va_list ap; + int r; + va_start(ap, format); + r = _libc_cvprintf((stream_t)stdout, NULL, format, ap); + va_end(ap); + return(r); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_FPRINTF) +int LIBC_FUNCTION_ATTRIBUTE fprintf(FILE *stream, const char *format, ...){ + va_list ap; + int r; + va_start(ap, format); + r = _libc_cvprintf((stream_t)stream, NULL, format, ap); + va_end(ap); + return(r); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_SNPRINTF) +int LIBC_FUNCTION_ATTRIBUTE snprintf(char *str, size_t size, const char *format, ...){ + va_list ap; + int r; + struct _libc_snprintf_struct s; + s.str = str; + s.loc = 0; + s.maxlen = size; + va_start(ap, format); + r = _libc_cvprintf((stream_t)_libc_cswrite, &s, format, ap); + va_end(ap); + return(r); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_VSNPRINTF) +int LIBC_FUNCTION_ATTRIBUTE vsnprintf(char *str, size_t size, const char *format, va_list ap){ + int r; + struct _libc_snprintf_struct s; + s.str = str; + s.loc = 0; + s.maxlen = size; + r = _libc_cvprintf((stream_t)_libc_cswrite, &s, format, ap); + return(r); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_SNPRINTF) || defined (LIBC_VSNPRINTF) +static int LIBC_FUNCTION_ATTRIBUTE _libc_cswrite(void *user, const void *buf, int count){ + struct _libc_snprintf_struct *s; + int i; + s = (struct _libc_snprintf_struct *)user; + for(i = 0; (i < count) && (s->loc < s->maxlen); i++, s->loc++){ + if((s->maxlen > 1) && (s->loc < (s->maxlen - 1)))s->str[s->loc] = ((char *)buf)[i]; + } + if(s->maxlen){ + if(s->loc < (s->maxlen - 1)){ + s->str[s->loc] = 0; + }else{ + s->str[s->maxlen - 1] = 0; + } + } + return(i); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_PRINTF) || defined (LIBC_FPRINTF) || defined (LIBC_SNPRINTF) || defined (LIBC_VSNPRINTF) +static int LIBC_FUNCTION_ATTRIBUTE _libc_cwrite(stream_t cb, void *user, const void *buf, size_t count){ + stream_user_t cub; + if(user == NULL)return(cb(buf, count)); + cub = (stream_user_t)cb; + return(cub(user, buf, count)); +} + +static int LIBC_FUNCTION_ATTRIBUTE _libc_cvprintf(stream_t cb, void *user, const char *format, va_list ap){ + int width, pad, pc, l; + const char *s, *e; + char c; + pc = 0; + s = e = format; + for( ; *format != 0; format++){ + e = format; + if(*format == '%'){ + format++; + width = pad = 0; + if(*format == '\0')break; + if(*format == '%'){ + pc += _libc_cwrite(cb, user, s, (e - s) + 1); + s = format + 1; + continue; + } + if(*format == '-'){ + format++; + pad = _LIBC_PRINT_PAD_RIGHT; + } + while(*format == '0'){ + format++; + pad |= _LIBC_PRINT_PAD_ZERO; + } + for( ; *format >= '0' && *format <= '9'; format++){ + width *= 10; + width += *format - '0'; + } + if(*format == 's'){ + pc += _libc_cwrite(cb, user, s, (e - s)); + s = va_arg(ap, char *); + pc += _libc_cprints(cb, user, s ? s : "(null)", width, pad); + s = format + 1; + continue; + } + l = 0; + while(*format == 'l'){ + format++; + l++; + } + if(*format == 'd'){ + pc += _libc_cwrite(cb, user, s, (e - s)); + if(!l){ + pc += _libc_cprinti(cb, user, va_arg(ap, int), 10, 1, width, pad, 'a'); + }else if(l == 1){ + pc += _libc_cprintl(cb, user, va_arg(ap, long int), 10, 1, width, pad, 'a'); + }else{ + pc += _libc_cprintl(cb, user, va_arg(ap, long long int), 10, 1, width, pad, 'a'); + } + s = format + 1; + continue; + } + if(*format == 'b'){ + pc += _libc_cwrite(cb, user, s, (e - s)); + if(!l){ + pc += _libc_cprinti(cb, user, va_arg(ap, unsigned int), 2, 0, width, pad, 'a'); + }else if(l == 1){ + pc += _libc_cprintl(cb, user, va_arg(ap, unsigned long int), 2, 0, width, pad, 'a'); + }else{ + pc += _libc_cprintl(cb, user, va_arg(ap, unsigned long long int), 2, 0, width, pad, 'a'); + } + s = format + 1; + continue; + } + if(*format == 'x'){ + pc += _libc_cwrite(cb, user, s, (e - s)); + if(!l){ + pc += _libc_cprinti(cb, user, va_arg(ap, unsigned int), 16, 0, width, pad, 'a'); + }else if(l == 1){ + pc += _libc_cprintl(cb, user, va_arg(ap, unsigned long int), 16, 0, width, pad, 'a'); + }else{ + pc += _libc_cprintl(cb, user, va_arg(ap, unsigned long long int), 16, 0, width, pad, 'a'); + } + s = format + 1; + continue; + } + if(*format == 'X'){ + pc += _libc_cwrite(cb, user, s, (e - s)); + if(!l){ + pc += _libc_cprintl(cb, user, va_arg(ap, unsigned int), 16, 0, width, pad, 'A'); + }else if(l == 1){ + pc += _libc_cprintl(cb, user, va_arg(ap, unsigned long int), 16, 0, width, pad, 'A'); + }else{ + pc += _libc_cprintl(cb, user, va_arg(ap, unsigned long long int), 16, 0, width, pad, 'A'); + } + s = format + 1; + continue; + } + if(*format == 'u'){ + pc += _libc_cwrite(cb, user, s, (e - s)); + if(!l){ + pc += _libc_cprintl(cb, user, va_arg(ap, unsigned int), 10, 0, width, pad, 'a'); + }else if(l == 1){ + pc += _libc_cprintl(cb, user, va_arg(ap, unsigned long int), 10, 0, width, pad, 'a'); + }else{ + pc += _libc_cprintl(cb, user, va_arg(ap, unsigned long long int), 10, 0, width, pad, 'a'); + } + s = format + 1; + continue; + } + if(*format == 'c'){ + pc += _libc_cwrite(cb, user, s, (e - s)); + c = va_arg(ap, int); + pc += _libc_cwrite(cb, user, &c, 1); + s = format + 1; + continue; + } + } + } + if(e >= s){ + pc += _libc_cwrite(cb, user, s, (e - s) + 1); + } + return(pc); +} + +static int LIBC_FUNCTION_ATTRIBUTE _libc_cprints(stream_t cb, void *user, const char *string, int width, int pad){ + int pc, sl, len; + const char *ptr; + char padchar; + pc = 0; + padchar = ' '; + if(width > 0){ + len = 0; + for(ptr = string; *ptr; ++ptr) ++len; + if(len >= width)width = 0; else width -= len; + if(pad & _LIBC_PRINT_PAD_ZERO)padchar = '0'; + } + if(!(pad & _LIBC_PRINT_PAD_RIGHT)){ + for ( ; width > 0; width--){ + pc += _libc_cwrite(cb, user, &padchar, 1); + } + } + for(sl = 0; string[sl]; sl++); + pc += _libc_cwrite(cb, user, string, sl); + for ( ; width > 0; --width) { + pc += _libc_cwrite(cb, user, &padchar, 1); + } + return(pc); +} + +static int LIBC_FUNCTION_ATTRIBUTE _libc_cprinti(stream_t cb, void *user, int i, int b, int sg, int width, int pad, int letbase){ + char print_buf[_LIBC_PRINT_BUF_LEN], *s; + unsigned int u; + int t, neg, pc; + neg = pc = 0; + u = i; + if(i == 0){ + print_buf[0] = '0'; + print_buf[1] = '\0'; + return(_libc_cprints(cb, user, print_buf, width, pad)); + } + if(sg && (b == 10) && (i < 0)){ + neg = 1; + u = -i; + } + s = print_buf + _LIBC_PRINT_BUF_LEN - 1; + *s = '\0'; + while(u){ + t = u % b; + if(t >= 10)t += letbase - '0' - 10; + *--s = t + '0'; + u /= b; + } + if(neg){ + if(width && (pad & _LIBC_PRINT_PAD_ZERO)){ + pc += _libc_cwrite(cb, user, "-", 1); + width--; + }else{ + *--s = '-'; + } + } + return(pc + _libc_cprints(cb, user, s, width, pad)); +} + +// li -> i: workaround et oleks hetkel alati 4 baidine (unsigned long int) +// STM32 või ARM-C3 või vastav GCC ei oska 8 baidist arvu jagada +static int LIBC_FUNCTION_ATTRIBUTE _libc_cprintl(stream_t cb, void *user, long long int li, int b, int sg, int width, int pad, int letbase){ + char print_buf[_LIBC_PRINT_BUF_LEN], *s; + unsigned long int u; + long int i; + int t, neg, pc; + neg = pc = 0; + i = li; + u = i; + if(i == 0){ + print_buf[0] = '0'; + print_buf[1] = '\0'; + return(_libc_cprints(cb, user, print_buf, width, pad)); + } + if(sg && (b == 10) && (i < 0)){ + neg = 1; + u = -i; + } + s = print_buf + _LIBC_PRINT_BUF_LEN - 1; + *s = '\0'; + while(u){ + t = u % b; + if(t >= 10)t += letbase - '0' - 10; + *--s = t + '0'; + u /= b; + } + if(neg){ + if(width && (pad & _LIBC_PRINT_PAD_ZERO)){ + pc += _libc_cwrite(cb, user, "-", 1); + width--; + }else{ + *--s = '-'; + } + } + return(pc + _libc_cprints(cb, user, s, width, pad)); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_WRITE) +ssize_t LIBC_FUNCTION_ATTRIBUTE write(int fd, const void *buf, size_t count){ + stream_t cb; + if(fd == 1){ + if(stdout != NULL){ + cb = (stream_t)stdout; + return(cb(buf, count)); + } + }else if(fd == 2){ + if(stderr != NULL){ + cb = (stream_t)stderr; + return(cb(buf, count)); + }else if(stdout != NULL){ + cb = (stream_t)stdout; + return(cb(buf, count)); + } + } + return(0); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_MEMCPY) +void LIBC_FUNCTION_ATTRIBUTE *memcpy(void *dest, const void *src, size_t n){ + register char *_dest; + register const char *_src; + _dest = dest; + _src = src; + while(n-- > 0)*_dest++ = *_src++; + return(dest); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_MEMMOVE) +void LIBC_FUNCTION_ATTRIBUTE *memmove(void *dest, const void *src, size_t n){ + register char *_dest; + register const char *_src; + _dest = dest; + _src = src; + if(_src < _dest){ /* Moving from low mem to hi mem; start at end. */ + for(_src += n, _dest += n; n; n--){ + *--_dest = *--_src; + } + }else if(_src != _dest){ /* Moving from hi mem to low mem; start at beginning. */ + for( ; n; n--){ + *_dest++ = *_src++; + } + } + return(dest); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_MEMCMP) || defined (LIBC_MEMMEM) +int LIBC_FUNCTION_ATTRIBUTE memcmp(const void *s1, const void *s2, size_t n){ + register const unsigned char *str1; + register const unsigned char *str2; + str1 = (const unsigned char *)s1; + str2 = (const unsigned char *)s2; + while(n-- > 0){ + if(*str1++ != *str2++)return str1[-1] < str2[-1] ? -1 : 1; + } + return(0); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_MEMSET) +void LIBC_FUNCTION_ATTRIBUTE *memset(void *s, int c, size_t n){ + register char *str = s; + while(n-- > 0)*str++ = c; + return(s); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_MEMMEM) +void LIBC_FUNCTION_ATTRIBUTE *memmem(const void *haystack, size_t haystacklen, const void *needle, size_t needlelen){ + const char *begin; + const char *const last_possible = (const char *)haystack + haystacklen - needlelen; + if(needlelen == 0)return((void *)haystack); + if(haystacklen < needlelen)return(NULL); + for(begin = (const char *)haystack; begin <= last_possible; ++begin){ + if(begin[0] == ((const char *)needle)[0] && !memcmp((const void *)&begin[1], (const void *)((const char *)needle + 1), needlelen - 1)){ + return((void *)begin); + } + } + return(NULL); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_STRLEN) +size_t LIBC_FUNCTION_ATTRIBUTE strlen(const char *s){ + register size_t n; + n = 0; + while(*s++)n++; + return(n); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_STRCHR) +char LIBC_FUNCTION_ATTRIBUTE *strchr(const char *s, int c){ + for( ; *s != (char)c; s++) + if(*s == 0)return(0); + return((char *)s); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_STRSTR) +char LIBC_FUNCTION_ATTRIBUTE *strstr(const char *haystack, const char *needle){ + register char *a, *b; + b = (char *)needle; + if(*b == 0)return((char *)haystack); + for( ; *haystack != 0; haystack += 1){ + if(*haystack != *b)continue; + a = (char *)haystack; + while(1){ + if(*b == 0)return((char *)haystack); + if(*a++ != *b++)break; + } + b = (char *)needle; + } + return(NULL); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_STRCMP) +int LIBC_FUNCTION_ATTRIBUTE strcmp(const char *s1, const char *s2){ + for( ; *s1 == *s2; ++s1, ++s2)if(*s1 == 0)return(0); + return(*(unsigned char *)s1 < *(unsigned char *)s2 ? -1 : 1); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_STRNCMP) +int LIBC_FUNCTION_ATTRIBUTE strncmp(const char *s1, const char *s2, size_t n){ + for( ; n > 0; s1++, s2++, n--){ + if(*s1 == 0)return(0); + if(*s1 != *s2)return((*(unsigned char *)s1 < *(unsigned char *)s2) ? -1 : 1); + } + return(0); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_STRCPY) +char LIBC_FUNCTION_ATTRIBUTE *strcpy(char *s1, const char *s2){ + char *s; + s = s1; + while((*s++ = *s2++) != 0); + return(s1); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_STRNCPY) +char LIBC_FUNCTION_ATTRIBUTE *strncpy(char *s1, const char *s2, size_t n){ + char *s; + s = s1; + if(n != 0){ + do{ + if((*s++ = *s2++) == 0){ + while(--n != 0)*s++ = 0; + break; + } + }while(--n != 0); + } + return(s1); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_STRNCAT) +char LIBC_FUNCTION_ATTRIBUTE *strncat(char *s1, const char *s2, size_t n){ + char *d = s1; + if (n != 0) { + while (*d != 0)d++; + do { + if ((*d = *s2++) == 0)break; + d++; + } + while (--n != 0); + *d = 0; + } + return s1; +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_STRCAT) +char LIBC_FUNCTION_ATTRIBUTE *strcat(char *s1, const char *s2){ + char *d = s1; + while (*s1 != 0)s1++; + while ((*s1++ = *s2++) != '\0'); + return d; +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_STRCASECMP) +int LIBC_FUNCTION_ATTRIBUTE strcasecmp(const char *s1, const char *s2){ + for( ; tolower(*s1) == tolower(*s2); ++s1, ++s2)if(*s1 == 0)return(0); + return(tolower(*(unsigned char *)s1) < tolower(*(unsigned char *)s2) ? -1 : 1); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_STRNCASECMP) +int LIBC_FUNCTION_ATTRIBUTE strncasecmp(const char *s1, const char *s2, size_t n){ + for( ; n > 0; s1++, s2++, n--){ + if(*s1 == 0)return(0); + if(tolower(*s1) != tolower(*s2))return((tolower(*(unsigned char *)s1) < tolower(*(unsigned char *)s2)) ? -1 : 1); + } + return(0); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_ATOI) +int LIBC_FUNCTION_ATTRIBUTE atoi(const char *nptr){ + register int num, neg; + register char c; + num = neg = 0; + c = *nptr; + while((c == ' ') || (c == '\n') || (c == '\r') || (c == '\t'))c = *++nptr; + if(c == '-'){ /* get an optional sign */ + neg = 1; + c = *++nptr; + }else if(c == '+'){ + c = *++nptr; + } + + while((c >= '0') && (c <= '9')){ + num = (10 * num) + (c - '0'); + c = *++nptr; + } + if(neg)return(0 - num); + return(num); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_STRTOL) +long int LIBC_FUNCTION_ATTRIBUTE strtol(const char *nptr, char **endptr, int base){ + return(strtoll(nptr, endptr, base)); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_STRTOL) || defined (LIBC_STRTOLL) +long long int LIBC_FUNCTION_ATTRIBUTE strtoll(const char *nptr, char **endptr, int base){ + long long int acc, cutoff; + int c, neg, any, cutlim; + const char *s; + s = nptr; + do{ + c = (unsigned char)*s++; + }while(isspace(c)); + if(c == '-'){ + neg = 1; + c = *s++; + }else{ + neg = 0; + if(c == '+')c = *s++; + } + if(((base == 0) || (base == 16)) && (c == '0') && ((*s == 'x') || (*s == 'X'))){ + c = s[1]; + s += 2; + base = 16; + } + if(base == 0)base = (c == '0') ? 8 : 10; + cutoff = neg ? LLONG_MIN : LLONG_MAX; + cutlim = (int)(cutoff % base); + cutoff /= base; + if(neg){ + if(cutlim > 0){ + cutlim -= base; + cutoff += 1; + } + cutlim = -cutlim; + } + for(acc = 0, any = 0; ; c = (unsigned char)*s++){ + if(isdigit(c)){ + c -= '0'; + }else if(isalpha(c)){ + c -= isupper(c) ? ('A' - 10) : ('a' - 10); + }else{ + break; + } + if(c >= base)break; + if(any < 0)continue; + if(neg){ + if((acc < cutoff) || ((acc == cutoff) && (c > cutlim))){ + any = -1; + acc = LLONG_MIN; + // errno = ERANGE; + }else{ + any = 1; + acc *= base; + acc -= c; + } + }else{ + if((acc > cutoff) || ((acc == cutoff) && (c > cutlim))){ + any = -1; + acc = LLONG_MAX; + // errno = ERANGE; + }else{ + any = 1; + acc *= base; + acc += c; + } + } + } + if(endptr != 0)*endptr = (char *)(any ? (s - 1) : nptr); + return(acc); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_STRTOD) +#define _LIBC_HUGE_VAL (__builtin_huge_val()) +#define _LIBC_DBL_MIN_EXP (__DBL_MIN_EXP__) +#define _LIBC_DBL_MAX_EXP (__DBL_MAX_EXP__) +double LIBC_FUNCTION_ATTRIBUTE strtod(const char *str, char **endptr){ + double number, p10; + int exponent, negative, n, num_digits, num_decimals; + char *p; + + p = (char *)str; + while(isspace(*p))p++; + + negative = 0; + switch(*p){ + case '-': negative = 1; // Fall through to increment position + case '+': p++; + } + + number = 0.; + exponent = num_digits = num_decimals = 0; + + while(isdigit(*p)){ + number = number * 10. + (*p - '0'); + p++; + num_digits++; + } + // Process decimal part + if(*p == '.'){ + p++; + while(isdigit(*p)){ + number = number * 10. + (*p - '0'); + p++; + num_digits++; + num_decimals++; + } + exponent -= num_decimals; + } + if(num_digits == 0){ + // errno = ERANGE; + return(0.0); + } + // Correct for sign + if(negative)number = -number; + // Process an exponent string + if(*p == 'e' || *p == 'E'){ + // Handle optional sign + negative = 0; + switch(*++p){ + case '-': negative = 1; // Fall through to increment pos + case '+': p++; + } + // Process string of digits + n = 0; + while(isdigit(*p)){ + n = n * 10 + (*p - '0'); + p++; + } + if(negative){ + exponent -= n; + }else{ + exponent += n; + } + } + if((exponent < _LIBC_DBL_MIN_EXP) || (exponent > _LIBC_DBL_MAX_EXP)){ + // errno = ERANGE; + return(_LIBC_HUGE_VAL); + } + // Scale the result + p10 = 10.; + n = exponent; + if(n < 0)n = -n; + while(n){ + if(n & 1){ + if(exponent < 0){ + number /= p10; + }else{ + number *= p10; + } + } + n >>= 1; + p10 *= p10; + } + // if (number == _LIBC_HUGE_VAL)errno = ERANGE; + if(endptr)*endptr = p; + return(number); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_ABS) +int LIBC_FUNCTION_ATTRIBUTE abs(int j){ + if(j < 0)return(-j); + return(j); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_ASSERT) +void LIBC_FUNCTION_ATTRIBUTE assert(int expression){ +} +#endif + +#if defined (LIBC_ALL) || defined(LIBC_ABORT) +void LIBC_FUNCTION_ATTRIBUTE abort(void){ +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_GMTIME_R) +#define _LIBC_YEAR0 1900 /* the first year */ +#define _LIBC_EPOCH_YR 1970 /* EPOCH = Jan 1 1970 00:00:00 */ +#define _LIBC_SECS_DAY (24L * 60L * 60L) +#define _LIBC_LEAPYEAR(year) (!((year) % 4) && (((year) % 100) || !((year) % 400))) +#define _LIBC_YEARSIZE(year) (_LIBC_LEAPYEAR(year) ? 366 : 365) +static const int _ytab[2][12] = { + { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }, + { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 } +}; +struct tm * LIBC_FUNCTION_ATTRIBUTE gmtime_r(const time_t *timep, struct tm *result){ + unsigned long dayclock, dayno; + int year; + + year = _LIBC_EPOCH_YR; + dayclock = (unsigned long)*timep % _LIBC_SECS_DAY; + dayno = (unsigned long)*timep / _LIBC_SECS_DAY; + + result->tm_sec = dayclock % 60; + result->tm_min = (dayclock % 3600) / 60; + result->tm_hour = dayclock / 3600; + result->tm_wday = (dayno + 4) % 7; /* day 0 was a thursday */ + while(dayno >= _LIBC_YEARSIZE(year)){ + dayno -= _LIBC_YEARSIZE(year); + year++; + } + result->tm_year = year - _LIBC_YEAR0; + result->tm_yday = dayno; + result->tm_mon = 0; + while(dayno >= _ytab[_LIBC_LEAPYEAR(year)][result->tm_mon]){ + dayno -= _ytab[_LIBC_LEAPYEAR(year)][result->tm_mon]; + result->tm_mon++; + } + result->tm_mday = dayno + 1; + result->tm_isdst = 0; + return(result); +} +#endif + +#if defined (LIBC_ALL) || defined (LIBC_MKTIME) +static const int m_to_d[12] = {0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334}; +time_t LIBC_FUNCTION_ATTRIBUTE mktime(struct tm *tm){ + int month, year; + time_t result; + + month = tm->tm_mon; + year = tm->tm_year + month / 12 + 1900; + month %= 12; + if(month < 0){ + year -= 1; + month += 12; + } + result = (year - 1970) * 365 + (year - 1969) / 4 + m_to_d[month]; + result = (year - 1970) * 365 + m_to_d[month]; + if(month <= 1)year -= 1; + result += (year - 1968) / 4; + result -= (year - 1900) / 100; + result += (year - 1600) / 400; + result += tm->tm_mday; + result -= 1; + result *= 24; + result += tm->tm_hour; + result *= 60; + result += tm->tm_min; + result *= 60; + result += tm->tm_sec; + return(result); +} +#endif + diff --git a/lib/libc/stddef.h b/lib/libc/stddef.h new file mode 100644 index 0000000..38fbe7d --- /dev/null +++ b/lib/libc/stddef.h @@ -0,0 +1,7 @@ +#ifndef _STDDEF_H_ +#define _STDDEF_H_ + +#include + +#endif + diff --git a/lib/libc/stdio.h b/lib/libc/stdio.h new file mode 100644 index 0000000..a31f09a --- /dev/null +++ b/lib/libc/stdio.h @@ -0,0 +1,111 @@ +#ifndef _STDIO_H_ +#define _STDIO_H_ + +#include +#include + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#ifndef LLONG_MAX +#define LLONG_MAX ((long long int)(((unsigned long long int)-1) / 2)) +#endif + +#ifndef LLONG_MIN +#define LLONG_MIN ((long long int)(-1 * (((unsigned long long int)-1) / 2)) - 1) +#endif + +typedef void FILE; + +typedef int32_t ssize_t; +typedef uint32_t size_t; + +ssize_t write_stdout(const void *buf, size_t count); +extern FILE *stdin, *stdout, *stderr; + +int putchar(int c); +int putc(int c, FILE *stream); +int fputc(int c, FILE *stream); +int puts(const char *s); +int fputs(const char *s, FILE *stream); +int printf(const char *format, ...); +int fprintf(FILE *stream, const char *format, ...); +int snprintf(char *str, size_t size, const char *format, ...); +int sprintf(char *str, const char *format, ...); +int vsnprintf(char *str, size_t size, const char *format, va_list ap); + +ssize_t write(int fd, const void *buf, size_t count); + +void *memcpy(void *dest, const void *src, size_t n); +void *memmove(void *dest, const void *src, size_t n); +int memcmp(const void *s1, const void *s2, size_t n); +void *memset(void *s, int c, size_t n); +void *memmem(const void *haystack, size_t haystacklen, const void *needle, size_t needlelen); +size_t strlen(const char *s); /**/ +char *strchr(const char *s, int c); /**/ +char *strstr(const char *haystack, const char *needle); /**/ +int strcmp(const char *s1, const char *s2); /**/ +int strncmp(const char *s1, const char *s2, size_t n); /**/ +char *strcpy(char *s1, const char *s2); +char *strncpy(char *s1, const char *s2, size_t n); /**/ +char *strncat(char *s1, const char *s2, size_t n); /**/ +char *strcat(char *dst, const char *src); /**/ +int strcasecmp(const char *s1, const char *s2); /**/ +int strncasecmp(const char *s1, const char *s2, size_t n); /**/ +int atoi(const char *nptr); /**/ +long int strtol(const char *nptr, char **endptr, int base); /**/ +long long int strtoll(const char *nptr, char **endptr, int base); /**/ +double strtod(const char *str, char **endptr); /**/ + +int abs(int j); + +#ifndef assert +void assert(int expression); +#endif +void abort(void); + +typedef int32_t time_t; +struct tm{ + int tm_sec; /* seconds */ + int tm_min; /* minutes */ + int tm_hour; /* hours */ + int tm_mday; /* day of the month */ + int tm_mon; /* month */ + int tm_year; /* year */ + int tm_wday; /* day of the week */ + int tm_yday; /* day in the year */ + int tm_isdst; /* daylight saving time */ +} +#if defined (GCC_VERSION) +__attribute__((packed)) +#endif +; + +struct tm *gmtime_r(const time_t *timep, struct tm *result); +time_t mktime(struct tm *tm); + +void *calloc(size_t nmemb, size_t size); +void *malloc(size_t size); +void free(void *ptr); +void *realloc(void *ptr, size_t size); + +#define isalnum(c) (isalpha(c) || isdigit(c)) +#define isalpha(c) (isupper(c) || islower(c)) +#define isascii(c) (((c) > 0) && ((c) <= 0x7F)) +#define iscntrl(c) (((c) >= 0) && (((c) <= 0x1F) || ((c) == 0x7F))) +#define isdigit(c) (((c) >= '0') && ((c) <= '9')) +#define isgraph(c) (((c) != ' ') && isprint(c)) +#define isprint(c) (((c) >= ' ') && ((c) <= '~')) +#define ispunct(c) ((((c) > ' ') && ((c) <= '~')) && !isalnum(c)) +#define isspace(c) (((c) == ' ') || ((c) == '\f') || ((c) == '\n') || ((c) == '\r') || ((c) == '\t') || ((c) == '\v')) +#define isupper(c) (((c) >= 'A') && ((c) <= 'Z')) +#define islower(c) (((c) >= 'a') && ((c) <= 'z')) +#define isxdigit(c) (isdigit(c) || (((c) >= 'A') && ((c) <= 'F')) || (((c) >= 'a') && ((c) <= 'f'))) +#define isxupper(c) (isdigit(c) || (((c) >= 'A') && ((c) <= 'F'))) +#define isxlower(c) (isdigit(c) || (((c) >= 'a') && ((c) <= 'f'))) +#define tolower(c) (isupper(c) ? ((c) - 'A' + 'a') : (c)) +#define toupper(c) (islower(c) ? ((c) - 'a' + 'A') : (c)) + +#endif + diff --git a/lib/libc/stdlib.h b/lib/libc/stdlib.h new file mode 100644 index 0000000..1d95752 --- /dev/null +++ b/lib/libc/stdlib.h @@ -0,0 +1,7 @@ +#ifndef _STDLIB_H_ +#define _STDLIB_H_ + +#include + +#endif + diff --git a/lib/libc/string.h b/lib/libc/string.h new file mode 100644 index 0000000..dc5c0be --- /dev/null +++ b/lib/libc/string.h @@ -0,0 +1,7 @@ +#ifndef _STRING_H_ +#define _STRING_H_ + +#include + +#endif + diff --git a/lib/libc/time.h b/lib/libc/time.h new file mode 100644 index 0000000..c6442ff --- /dev/null +++ b/lib/libc/time.h @@ -0,0 +1,7 @@ +#ifndef _TIME_H_ +#define _TIME_H_ + +#include + +#endif + diff --git a/lib/mask.h b/lib/mask.h new file mode 100644 index 0000000..1ef49e7 --- /dev/null +++ b/lib/mask.h @@ -0,0 +1,19 @@ +#ifndef _MASK_H_ +#define _MASK_H_ + +#include + +#define mask8(mask, value) ((((uint8_t)(value)) << __builtin_ctz((mask))) & ((uint8_t)(mask))) +#define mask8_set(target, mask, value) do{ (target) = ((target) & ~((uint8_t)(mask))) | mask8(mask, value); }while(0) +#define mask8_get(target, mask) (((target) & ((uint8_t)(mask))) >> __builtin_ctz((mask))) + +#define mask16(mask, value) ((((uint16_t)(value)) << __builtin_ctz((mask))) & ((uint16_t)(mask))) +#define mask16_set(target, mask, value) do{ (target) = ((target) & ~((uint16_t)(mask))) | mask16(mask, value); }while(0) +#define mask16_get(target, mask) (((target) & ((uint16_t)(mask))) >> __builtin_ctz((mask))) + +#define mask32(mask, value) ((((uint32_t)(value)) << __builtin_ctz((mask))) & ((uint32_t)(mask))) +#define mask32_set(target, mask, value) do{ (target) = ((target) & ~((uint32_t)(mask))) | mask32(mask, value); }while(0) +#define mask32_get(target, mask) (((target) & ((uint32_t)(mask))) >> __builtin_ctz((mask))) + +#endif + diff --git a/lib/rom_lib.h b/lib/rom_lib.h new file mode 100644 index 0000000..9300ad0 --- /dev/null +++ b/lib/rom_lib.h @@ -0,0 +1,94 @@ +#ifndef __PLATFORM_ROMLIB_H__ +#define __PLATFORM_ROMLIB_H__ + + #include + #include + #include + + #include "strproc.h" + #include "basic_types.h" +// #include "fwlib/hal_misc.h" +// #include "rtl_std_lib/include/rtl_lib.h" + +extern uint32_t HalDelayUs(uint32_t us); +extern uint32_t DiagPrintf(const char *fmt, ...); +extern uint32_t HalGetCpuClk(VOID); + +extern void HalInitLogUart(void); +extern void HalLogUartInit(void); + +extern u32 DiagPrintf(IN const char *fmt, ...); + +extern u32 DiagSPrintf(IN u8 *buf, IN const char *fmt, ...); + +extern int prvDiagPrintf(IN const char *fmt, ...); + +extern int prvDiagSPrintf(IN char *buf, IN const char *fmt, ...); + +extern u8 __ram_start_table_start__[]; +extern VOID HalCpuClkConfig(u8 CpuType); +extern VOID VectorTableInitRtl8195A(u32 StackP); +extern VOID HalInitPlatformLogUartV02(VOID); +extern VOID HalReInitPlatformLogUartV02(VOID); +extern VOID HalInitPlatformTimerV02(VOID); + +extern u8 HalPinCtrlRtl8195A( + IN u32 Function, + IN u32 PinLocation, + IN BOOL Operation + ); + +extern void HalShowBuildInfoV02(void); +extern VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode); +extern void UartLogIrqHandle(void); +extern u8 GetRomCmdNum(void); // = 6 + +typedef struct _COMMAND_TABLE_ { + const u8* cmd; + u16 ArgvCnt; + u32 (*func)(u16 argc, u8* argv[]); + const u8* msg; +}COMMAND_TABLE, *PCOMMAND_TABLE; + +extern COMMAND_TABLE UartLogRomCmdTable[]; + + + + #define printf DiagPrintf +// #define printf prvDiagPrintf + #define sprintf(fmt, arg...) DiagSPrintf((u8*)fmt, ##arg) +// #define sprintf rtl_sprintf +// #define sprintf prvDiagSPrintf + #define snprintf DiagSnPrintf + + + #define memchr rtl_memchr + #define memcmp rtl_memcmp + #define memcpy rtl_memcpy + #define memmove rtl_memmove + #define memset rtl_memset + #define strcat rtl_strcat + #define strchr rtl_strchr + #define strcmp(s1, s2) rtl_strcmp((const char *)s1, (const char *)s2) + #define strcpy rtl_strcpy + #define strlen(str) rtl_strlen((const char *)str) + #define strncat rtl_strncat + #define strncmp(s1, s2, n) rtl_strncmp((const char *)s1, (const char *)s2, n) + #define strncpy rtl_strncpy + #define strstr rtl_strstr + #define strsep rtl_strsep + #define strtok rtl_strtok + + #define atoi(str) prvAtoi(str) + #define strpbrk(cs, ct) _strpbrk(cs, ct) // for B-cut ROM + #define sscanf _sscanf + +// #define sscanf rtl_sscanf + #define strnlen rtl_strnlen +// #define strlen rtl_strlen + + #define strstr rtl_strstr + #define vsnprintf rtl_vfprintf_r + + +#endif // __PLATFORM_ROMLIB_H__ diff --git a/lib/rtl_consol.h b/lib/rtl_consol.h new file mode 100644 index 0000000..c27eed8 --- /dev/null +++ b/lib/rtl_consol.h @@ -0,0 +1,133 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _RTK_CONSOL_H_ +#define _RTK_CONSOL_H_ +/* + * Include user defined options first. Anything not defined in these files + * will be set to standard values. Override anything you dont like! + */ + #if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) +#include "platform_opts.h" +#endif + +#include "osdep_api.h" +#include "hal_diag.h" + +#define CONSOLE_PREFIX "#" + + +//Log UART +//UART_LOG_CMD_BUFLEN: only 126 bytes could be used for keeping input +// cmd, the last byte is for string end ('\0'). +#define UART_LOG_CMD_BUFLEN 127 +#define MAX_ARGV 10 + + + +typedef u32 (*ECHOFUNC)(IN u8*,...); //UART LOG echo-function type. + +typedef struct _UART_LOG_BUF_ { + u8 BufCount; //record the input cmd char number. + u8 UARTLogBuf[UART_LOG_CMD_BUFLEN]; //record the input command. +} UART_LOG_BUF, *PUART_LOG_BUF; + + + +typedef struct _UART_LOG_CTL_ { + u8 NewIdx; + u8 SeeIdx; + u8 RevdNo; + u8 EscSTS; + u8 ExecuteCmd; + u8 ExecuteEsc; + u8 BootRdy; + u8 Resvd; + PUART_LOG_BUF pTmpLogBuf; + VOID *pfINPUT; + PCOMMAND_TABLE pCmdTbl; + u32 CmdTblSz; +#ifdef CONFIG_UART_LOG_HISTORY + u32 CRSTS; +#endif +#ifdef CONFIG_UART_LOG_HISTORY + u8 (*pHistoryBuf)[UART_LOG_CMD_BUFLEN]; +#endif +#ifdef CONFIG_KERNEL + u32 TaskRdy; + _Sema Sema; +#else + // Since ROM code will reference this typedef, so keep the typedef same size + u32 TaskRdy; + void *Sema; +#endif +} UART_LOG_CTL, *PUART_LOG_CTL; + + +#define KB_ASCII_NUL 0x00 +#define KB_ASCII_BS 0x08 +#define KB_ASCII_TAB 0x09 +#define KB_ASCII_LF 0x0A +#define KB_ASCII_CR 0x0D +#define KB_ASCII_ESC 0x1B +#define KB_ASCII_SP 0x20 +#define KB_ASCII_BS_7F 0x7F +#define KB_ASCII_LBRKT 0x5B //[ + +#define KB_SPACENO_TAB 1 + +#ifdef CONFIG_UART_LOG_HISTORY +#define UART_LOG_HISTORY_LEN 5 +#endif + +#ifdef CONFIG_DEBUG_LOG +#define _ConsolePrint DiagPrintf +#else +#define _ConsolePrint +#endif + +#ifndef CONSOLE_PREFIX +#define CONSOLE_PREFIX "" +#endif + +#define CONSOLE_8195A(...) do {\ + _ConsolePrint("\r"CONSOLE_PREFIX __VA_ARGS__);\ +}while(0) + + +_LONG_CALL_ VOID +RtlConsolInit( + IN u32 Boot, + IN u32 TBLSz, + IN VOID *pTBL +); + +#if defined(CONFIG_KERNEL) +_LONG_CALL_ VOID +RtlConsolTaskRam( + VOID *Data +); +#endif + +_LONG_CALL_ VOID +RtlConsolTaskRom( + VOID *Data +); + + +_LONG_CALL_ u32 +Strtoul( + IN const u8 *nptr, + IN u8 **endptr, + IN u32 base +); + +void console_init(void); + +#endif //_RTK_CONSOL_H_ diff --git a/lib/rtl_std_lib/include/rt_lib_rom.h b/lib/rtl_std_lib/include/rt_lib_rom.h new file mode 100644 index 0000000..ffe8edb --- /dev/null +++ b/lib/rtl_std_lib/include/rt_lib_rom.h @@ -0,0 +1,254 @@ +/* + * rtl_lib.h + * + * Definitions for RTL library functions + */ + +#ifndef _RTL_LIB_ROM_H_ +#define _RTL_LIB_ROM_H_ + + +#include +#include + +#include + +#include "../libc/rom/string/rom_libc_string.h" +#include "../libgloss/rtl8195a/rom/rom_libgloss_retarget.h" + +#ifndef _PTR +#define _PTR void * +#endif + +#ifndef _AND +#define _AND , +#endif + +#ifndef _NOARGS +#define _NOARGS void +#endif + +#ifndef _CONST +#define _CONST const +#endif + +#ifndef _VOLATILE +#define _VOLATILE volatile +#endif + +#ifndef _SIGNED +#define _SIGNED signed +#endif + +#ifndef _DOTS +#define _DOTS , ... +#endif + +#ifndef _VOID +#define _VOID void +#endif + + +// +// RTL library functions in ROM +// + +#define rtl_memset rtl_memset_v1_00 +#define rtl_memchr rtl_memchr_v1_00 +#define rtl_memmove rtl_memmove_v1_00 +#define rtl_strcmp rtl_strcmp_v1_00 +#define rtl_memcpy rtl_memcpy_v1_00 + + + +extern _ROM_CALL_ void * rtl_memset_v1_00(void * m , int c , size_t n); +extern _ROM_CALL_ void * rtl_memchr_v1_00(const void * src_void , int c , size_t length); +extern _ROM_CALL_ void * rtl_memmove_v1_00( void * dst_void , const void * src_void , size_t length); +extern _ROM_CALL_ int rtl_strcmp_v1_00(const char *s1 , const char *s2); +extern _ROM_CALL_ void * rtl_memcpy_v1_00(void * __restrict dst0 , const void * __restrict src0 , size_t len0); + + +// +// rtl eabi functions +// + +#define rtl_itod rtl_itod_v1_00 +#define rtl_dtoi rtl_dtoi_v1_00 +#define rtl_uitof rtl_uitof_v1_00 +#define rtl_uitod rtl_uitod_v1_00 + + + +#define rtl_dcmpeq rtl_dcmpeq_v1_00 +#define rtl_dcmplt rtl_dcmplt_v1_00 +#define rtl_dcmpgt rtl_dcmpgt_v1_00 + + +#define rtl_dadd rtl_dadd_v1_00 +#define rtl_dsub rtl_dsub_v1_00 +#define rtl_dmul rtl_dmul_v1_00 +#define rtl_ddiv rtl_ddiv_v1_00 + +extern _ROM_CALL_ double rtl_itod_v1_00(int lval); +extern _ROM_CALL_ int rtl_dtoi_v1_00(double d); +extern _ROM_CALL_ float rtl_uitof_v1_00(unsigned int lval); +extern _ROM_CALL_ double rtl_uitod_v1_00(unsigned int lval); + + +extern _ROM_CALL_ int rtl_dcmpeq_v1_00(double a, double b); +extern _ROM_CALL_ int rtl_dcmplt_v1_00(double a, double b); +extern _ROM_CALL_ int rtl_dcmpgt_v1_00(double a, double b); + + +extern _ROM_CALL_ double rtl_dadd_v1_00(double a, double b); +extern _ROM_CALL_ double rtl_dsub_v1_00(double a, double b); +extern _ROM_CALL_ double rtl_dmul_v1_00(double a, double b); +extern _ROM_CALL_ double rtl_ddiv_v1_00(double a, double b); + + +// +// mprec +// + +#include + + +typedef struct _Bigint _Bigint; + + +#define rtl_Balloc rtl_Balloc_v1_00 +#define rtl_Bfree rtl_Bfree_v1_00 +#define rtl_d2b rtl_d2b_v1_00 +#define rtl_i2b rtl_i2b_v1_00 +#define rtl_pow5mult rtl_pow5mult_v1_00 +#define rtl_multadd rtl_multadd_v1_00 +#define rtl_mult rtl_mult_v1_00 +#define rtl_hi0bits rtl_hi0bits_v1_00 +#define rtl_lshift rtl_lshift_v1_00 +#define rtl_cmp rtl_cmp_v1_00 +#define rtl_diff rtl_diff_v1_00 + + +extern _ROM_CALL_ _Bigint * rtl_Balloc_v1_00(struct _reent *ptr, int k); + +extern _ROM_CALL_ void rtl_Bfree_v1_00(struct _reent *ptr, _Bigint * v); + +extern _ROM_CALL_ _Bigint * rtl_d2b_v1_00(struct _reent * ptr, double _d, int *e, int *bits); +extern _ROM_CALL_ _Bigint * rtl_i2b_v1_00(struct _reent *ptr, int i ); +extern _ROM_CALL_ _Bigint * rtl_pow5mult_v1_00(struct _reent * ptr, _Bigint *b, int k); +extern _ROM_CALL_ _Bigint * rtl_multadd_v1_00(struct _reent *ptr, _Bigint * b, int m, int a); +extern _ROM_CALL_ _Bigint * rtl_mult_v1_00(struct _reent *ptr, _Bigint *a, _Bigint *b); +extern _ROM_CALL_ int rtl_hi0bits_v1_00(register __ULong x); +extern _ROM_CALL_ _Bigint *rtl_lshift_v1_00(struct _reent *ptr, _Bigint *b, int k); +extern _ROM_CALL_ int rtl_cmp_v1_00(_Bigint *a, _Bigint *b); +extern _ROM_CALL_ _Bigint *rtl_diff_v1_00(struct _reent* ptr, _Bigint *a, _Bigint *b); + +// +// dtoa +// + +#define rtl_dtoa_r rtl_dtoa_r_v1_00 + +extern char * rtl_dtoa_r_v1_00(struct _reent *ptr, double _d, int mode, int ndigits, int *decpt, int *sign, char **rve); + +// +// mallocr +// +#include +#include + + + +#define __rom_mallocr_init __rom_mallocr_init_v1_00 + +#define rtl_calloc_r rtl_calloc_r_v1_00 +#define rtl_cfree_r rtl_cfree_r_v1_00 +#define rtl_malloc_r rtl_malloc_r_v1_00 +#define rtl_free_r rtl_free_r_v1_00 +#define rtl_realloc_r rtl_realloc_r_v1_00 +#define rtl_memalign_r rtl_memalign_r_v1_00 +#define rtl_valloc_r rtl_valloc_r_v1_00 +#define rtl_pvalloc_r rtl_pvalloc_r_v1_00 + + +extern _ROM_CALL_ void __rom_mallocr_init_v1_00(void); + + +#define RARG struct _reent *reent_ptr, +extern _ROM_CALL_ void* rtl_calloc_r_v1_00(RARG size_t n, size_t elem_size); +extern _ROM_CALL_ void rtl_cfree_r_v1_00(void *mem); +extern _ROM_CALL_ void* rtl_malloc_r_v1_00(RARG size_t bytes); +extern _ROM_CALL_ void rtl_free_r_v1_00(RARG void* mem); +extern _ROM_CALL_ void* rtl_realloc_r_v1_00(RARG void* oldmem, size_t bytes); +extern _ROM_CALL_ void* rtl_memalign_r_v1_00(RARG size_t alignment, size_t bytes); +extern _ROM_CALL_ void* rtl_valloc_r_v1_00(RARG size_t bytes); +extern _ROM_CALL_ void* rtl_pvalloc_r_v1_00(RARG size_t bytes); + + +// +// stdio +// +extern int rtl_errno; + +#ifndef _READ_WRITE_RETURN_TYPE +#define _READ_WRITE_RETURN_TYPE _ssize_t +#endif + +#ifndef _READ_WRITE_BUFSIZE_TYPE +#define _READ_WRITE_BUFSIZE_TYPE int +#endif + +#define rtl_sread rtl_sread_v1_00 +#define rtl_swrite rtl_swrite_v1_00 +#define rtl_seofread rtl_seofread_v1_00 +#define rtl_sseek rtl_sseek_v1_00 +#define rtl_sclose rtl_sclose_v1_00 +#define rtl_sbrk_r rtl_sbrk_r_v1_00 + +extern _ROM_CALL_ _READ_WRITE_RETURN_TYPE rtl_sread_v1_00( + struct _reent *ptr, + void *cookie, + char *buf, + _READ_WRITE_BUFSIZE_TYPE n); + +extern _ROM_CALL_ _READ_WRITE_RETURN_TYPE rtl_swrite_v1_00( + struct _reent *ptr, + void *cookie, + char const *buf, + _READ_WRITE_BUFSIZE_TYPE n); + +extern _ROM_CALL_ _READ_WRITE_RETURN_TYPE rtl_seofread_v1_00( + struct _reent *_ptr, + _PTR cookie, + char *buf, + _READ_WRITE_BUFSIZE_TYPE len); + +extern _ROM_CALL_ _fpos_t rtl_sseek_v1_00( + struct _reent *ptr _AND + void *cookie _AND + _fpos_t offset _AND + int whence); + +extern _ROM_CALL_ int rtl_sclose_v1_00( + struct _reent *ptr _AND + void *cookie); + +extern _ROM_CALL_ void * rtl_sbrk_r_v1_00( + struct _reent *ptr, + ptrdiff_t incr); + +// +// vfprintf +// + +#include +#include + +#define rtl_fflush_r rtl_fflush_r_v1_00 +#define rtl_vfprintf_r rtl_vfprintf_r_v1_00 + +extern _ROM_CALL_ int rtl_fflush_r_v1_00(struct _reent *ptr, register FILE * fp); +extern _ROM_CALL_ int rtl_vfprintf_r_v1_00(struct _reent *, FILE *, const char *, va_list); + + +#endif /* _RTL_LIB_ROM_H_ */ diff --git a/lib/rtl_std_lib/include/rtl_lib.h b/lib/rtl_std_lib/include/rtl_lib.h new file mode 100644 index 0000000..0fcadeb --- /dev/null +++ b/lib/rtl_std_lib/include/rtl_lib.h @@ -0,0 +1,141 @@ +/* + * rtl_lib.h + * + * Definitions for RTL library functions + */ + +#ifndef _RTL_LIB_H_ +#define _RTL_LIB_H_ + + +#include +//#include "diag.h" + + +extern int rtl_errno; + + +void init_rom_libgloss_ram_map(void); + + +// +// RTL library functions for Libc::stdio +// + +extern int rtl_printf(IN const char* fmt, ...); +extern int rtl_sprintf(char* str, const char* fmt, ...); +extern int rtl_snprintf(char* str, size_t size, const char* fmt, ...); + +// +// RTL library functions for string +// + +extern void * rtl_memchr(const void * src_void , int c , size_t length); +extern int rtl_memcmp(const void * m1 , const void * m2 , size_t n); +extern void * rtl_memcpy(void * dst0 , const void * src0 , size_t len0); +extern void * rtl_memmove( void * dst_void , const void * src_void , size_t length); +extern void * rtl_memset(void * m , int c , size_t n); +extern char * rtl_strcat(char * s1 , const char * s2); +extern char * rtl_strchr(const char *s1 , int i); +extern int rtl_strcmp(const char *s1 , const char *s2); +extern char* rtl_strcpy(char *dst0 , const char *src0); +extern size_t rtl_strlen(const char *str); +extern char * rtl_strncat(char * s1 , const char * s2 , size_t n); +extern int rtl_strncmp(const char *s1 , const char *s2 , size_t n); +extern char * rtl_strncpy(char * dst0 , const char * src0 , size_t count); +extern char * rtl_strstr(const char *searchee , const char *lookfor); +extern char * rtl_strsep(char **source_ptr , const char *delim); +extern char * rtl_strtok(char * s , const char * delim); + +// +// RTL library functions for math +// + + +extern double rtl_fabs(double); +extern float rtl_fabsf(float a); +extern float rtl_cos_f32(float a); +extern float rtl_sin_f32(float a); + +extern float rtl_fadd(float a, float b); +extern float rtl_fsub(float a, float b); +extern float rtl_fmul(float a, float b); +extern float rtl_fdiv(float a, float b); + +extern int rtl_fcmplt(float a, float b); +extern int rtl_fcmpgt(float a, float b); + + + + + +// +// RTL eabi functions + +extern double rtl_ftod(float f); + +extern double rtl_ddiv(double a, double b); + + +// +// Macro Library Functions +// + +typedef union +{ + float value; + u32 word; +} ieee_float_shape_type; + +/* Get a 32 bit int from a float. */ + +#define GET_FLOAT_WORD(i,d) \ +do { \ + ieee_float_shape_type gf_u; \ + gf_u.value = (d); \ + (i) = gf_u.word; \ +} while (0) + +/* Set a float from a 32 bit int. */ + +#define SET_FLOAT_WORD(d,i) \ +do { \ + ieee_float_shape_type sf_u; \ + sf_u.word = (i); \ + (d) = sf_u.value; \ +} while (0) + +static inline +float rtl_nanf(void) +{ + float x; + + SET_FLOAT_WORD(x,0x7fc00000); + return x; +} + + +// +// Library Test functions +// + +extern int rtl_lib_test(IN u16 argc, IN u8 *argv[]); +extern int rtl_math_test(IN u16 argc, IN u8 *argv[]); +extern int rtl_string_test(IN u16 argc, IN u8 *argv[]); + + +// +// Macro functions +// + +#undef dbg_printf +#define dbg_printf(fmt, args...) \ + rtl_printf("%s():%d : " fmt "\n", __FUNCTION__, __LINE__, ##args); + + +#undef err_printf +#define err_printf(fmt, args...) \ + rtl_printf("%s():%d : " fmt "\n", __FUNCTION__, __LINE__, ##args); + + +#endif /* _RTL_LIB_H_ */ diff --git a/lib/rtl_std_lib/libc/rom/string/rom_libc_string.h b/lib/rtl_std_lib/libc/rom/string/rom_libc_string.h new file mode 100644 index 0000000..8073fdc --- /dev/null +++ b/lib/rtl_std_lib/libc/rom/string/rom_libc_string.h @@ -0,0 +1,45 @@ +/* + * rom_libc_string.h + * + * Definitions for standard library - libc functions. + */ +#ifndef _ROM_LIBC_STRING_H_ +#define _ROM_LIBC_STRING_H_ + +#include + +#define rtl_memchr rtl_memchr_v1_00 +#define rtl_memcmp rtl_memcmp_v1_00 +#define rtl_memcpy rtl_memcpy_v1_00 +#define rtl_memmove rtl_memmove_v1_00 +#define rtl_memset rtl_memset_v1_00 +#define rtl_strcat rtl_strcat_v1_00 +#define rtl_strchr rtl_strchr_v1_00 +#define rtl_strcmp rtl_strcmp_v1_00 +#define rtl_strcpy rtl_strcpy_v1_00 +#define rtl_strlen rtl_strlen_v1_00 +#define rtl_strncat rtl_strncat_v1_00 +#define rtl_strncmp rtl_strncmp_v1_00 +#define rtl_strncpy rtl_strncpy_v1_00 +#define rtl_strstr rtl_strstr_v1_00 +#define rtl_strsep rtl_strsep_v1_00 +#define rtl_strtok rtl_strtok_v1_00 + +extern _ROM_CALL_ void * rtl_memchr_v1_00(const void * src_void , int c , size_t length); +extern _ROM_CALL_ int rtl_memcmp_v1_00(const void * m1 , const void * m2 , size_t n); +extern _ROM_CALL_ void * rtl_memcpy_v1_00(void * __restrict dst0 , const void * __restrict src0 , size_t len0); +extern _ROM_CALL_ void * rtl_memmove_v1_00( void * dst_void , const void * src_void , size_t length); +extern _ROM_CALL_ void * rtl_memset_v1_00(void * m , int c , size_t n); +extern _ROM_CALL_ char * rtl_strcat_v1_00(char *__restrict s1 , const char *__restrict s2); +extern _ROM_CALL_ char * rtl_strchr_v1_00(const char *s1 , int i); +extern _ROM_CALL_ int rtl_strcmp_v1_00(const char *s1 , const char *s2); +extern _ROM_CALL_ char* rtl_strcpy_v1_00(char *dst0 , const char *src0); +extern _ROM_CALL_ size_t rtl_strlen_v1_00(const char *str); +extern _ROM_CALL_ char * rtl_strncat_v1_00(char *__restrict s1 , const char *__restrict s2 , size_t n); +extern _ROM_CALL_ int rtl_strncmp_v1_00(const char *s1 , const char *s2 , size_t n); +extern _ROM_CALL_ char * rtl_strncpy_v1_00(char *__restrict dst0 , const char *__restrict src0 , size_t count); +extern _ROM_CALL_ char * rtl_strstr_v1_00(const char *searchee , const char *lookfor); +extern _ROM_CALL_ char * rtl_strsep_v1_00(register char **source_ptr , register const char *delim); +extern _ROM_CALL_ char * rtl_strtok_v1_00(register char *__restrict s , register const char *__restrict delim); + +#endif /* _ROM_LIBC_STRING_H_ */ diff --git a/lib/rtl_std_lib/libgloss/rtl8195a/rom/rom_libgloss_retarget.h b/lib/rtl_std_lib/libgloss/rtl8195a/rom/rom_libgloss_retarget.h new file mode 100644 index 0000000..f88ce47 --- /dev/null +++ b/lib/rtl_std_lib/libgloss/rtl8195a/rom/rom_libgloss_retarget.h @@ -0,0 +1,37 @@ +#ifndef ROM_LIBGLOSS_RETARGET_H +#define ROM_LIBGLOSS_RETARGET_H + +#include +#include + +#define rtl_close rtl_close_v1_00 +#define rtl_fstat rtl_fstat_v1_00 +#define rtl_isatty rtl_isatty_v1_00 +#define rtl_lseek rtl_lseek_v1_00 +#define rtl_open rtl_open_v1_00 +#define rtl_read rtl_read_v1_00 +#define rtl_write rtl_write_v1_00 +#define rtl_sbrk rtl_sbrk_v1_00 + +extern _ROM_CALL_ int rtl_close_v1_00(int fildes); +extern _ROM_CALL_ int rtl_fstat_v1_00(int fildes , struct stat *st); +extern _ROM_CALL_ int rtl_isatty_v1_00(int file); +extern _ROM_CALL_ int rtl_lseek_v1_00(int file , int ptr , int dir); +extern _ROM_CALL_ int rtl_open_v1_00(char *file , int flags , int mode); +extern _ROM_CALL_ int rtl_read_v1_00(int file , char *ptr , int len); +extern _ROM_CALL_ int rtl_write_v1_00(int file , const char *ptr , int len); +extern _ROM_CALL_ void* rtl_sbrk_v1_00(int incr); + + +struct _rom_libgloss_ram_map { + int (*libgloss_close)(int fildes); + int (*libgloss_fstat)(int fildes , struct stat *st); + int (*libgloss_isatty)(int file); + int (*libgloss_lseek)(int file , int ptr , int dir); + int (*libgloss_open)(char *file , int flags , int mode); + int (*libgloss_read)(int file , char *ptr , int len); + int (*libgloss_write)(int file , const char *ptr , int len); + void* (*libgloss_sbrk)(int incr); +}; + +#endif /* ROM_LIBGLOSS_RETARGET_H */ diff --git a/lib/strproc.h b/lib/strproc.h new file mode 100644 index 0000000..2920376 --- /dev/null +++ b/lib/strproc.h @@ -0,0 +1,106 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _STRPROC_H_ +#define _STRPROC_H_ + +#include /* for size_t */ +#include "va_list.h" + +#ifndef isprint +#define in_range(c, lo, up) ((u8)c >= lo && (u8)c <= up) +#define isprint(c) in_range(c, 0x20, 0x7f) +#define isdigit(c) in_range(c, '0', '9') +#define isxdigit(c) (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F')) +#define islower(c) in_range(c, 'a', 'z') +#define isspace(c) (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v' || c == ',') +#endif + + +extern _LONG_CALL_ char *_strncpy(char *dest, const char *src, size_t count); +extern _LONG_CALL_ char *_strcpy(char *dest, const char *src); +extern _LONG_CALL_ size_t _strlen(const char *s); +extern _LONG_CALL_ size_t _strnlen(const char *s, size_t count); +extern _LONG_CALL_ int _strcmp(const char *cs, const char *ct); +extern _LONG_CALL_ int _strncmp(const char *cs, const char *ct, size_t count); +extern _LONG_CALL_ int _sscanf(const char *buf, const char *fmt, ...); +extern _LONG_CALL_ char *_strsep(char **s, const char *ct); +extern _LONG_CALL_ char *skip_spaces(const char *str); +extern _LONG_CALL_ int skip_atoi(const char **s); +extern _LONG_CALL_ int _vsscanf(const char *buf, const char *fmt, va_list args); +extern _LONG_CALL_ unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base); +extern _LONG_CALL_ long simple_strtol(const char *cp, char **endp, unsigned int base); +extern _LONG_CALL_ long long simple_strtoll(const char *cp, char **endp, unsigned int base); +extern _LONG_CALL_ unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base); +extern _LONG_CALL_ const char *_parse_integer_fixup_radix(const char *s, unsigned int *base); +extern _LONG_CALL_ unsigned int _parse_integer(const char *s, unsigned int base, unsigned long long *p); +extern _LONG_CALL_ u64 div_u64(u64 dividend, u32 divisor); +extern _LONG_CALL_ s64 div_s64(s64 dividend, s32 divisor); +extern _LONG_CALL_ u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder); +extern _LONG_CALL_ s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder); +extern _LONG_CALL_ char *_strpbrk(const char *cs, const char *ct); +extern _LONG_CALL_ char *_strchr(const char *s, int c); + + +extern _LONG_CALL_ VOID +prvStrCpy( + IN u8 *pDES, + IN const u8 *pSRC +); + +extern _LONG_CALL_ u32 +prvStrLen( + IN const u8 *pSRC +); + +extern _LONG_CALL_ u8 +prvStrCmp( + IN const u8 *string1, + IN const u8 *string2 +); + +extern _LONG_CALL_ u8* +StrUpr( + IN u8 *string +); + +extern _LONG_CALL_ int prvAtoi( + IN const char * s +); + +extern _LONG_CALL_ const char * prvStrStr( + IN const char * str1, + IN const char * str2 +); + + +#ifndef ARDUINO_SDK +/* + * Fast implementation of tolower() for internal usage. Do not use in your + * code. + */ +static inline char _tolower(const char c) +{ + return c | 0x20; +} +#endif + +/* Fast check for octal digit */ +static inline int isodigit(const char c) +{ + return c >= '0' && c <= '7'; +} +#ifndef strtoul +#define strtoul(str, endp, base) simple_strtoul(str, endp, base) +#endif +#ifndef strtol +#define strtol(str, endp, base) simple_strtol(str, endp, base) +#endif + +#endif diff --git a/lib/va_list.h b/lib/va_list.h new file mode 100644 index 0000000..c059df3 --- /dev/null +++ b/lib/va_list.h @@ -0,0 +1,37 @@ +/* + * Routines to access hardware + * + * Copyright (c) 2013 Realtek Semiconductor Corp. + * + * This module is a confidential and proprietary property of RealTek and + * possession or use of this module requires written permission of RealTek. + */ + +#ifndef _VA_LIST_H_ +#define _VA_LIST_H_ + +//#include "platform_autoconf.h" +#include "basic_types.h" + +#ifndef va_arg //this part is adapted from linux (Linux/include/acpi/platform/acenv.h) + +typedef s32 acpi_native_int;//this definition is in (Linux/include/acpi/actypes.h) + +#ifndef _VALIST +#define _VALIST + typedef char *va_list; +#endif /* _VALIST */ + +/* Storage alignment properties */ +#define _AUPBND (sizeof (acpi_native_int) - 1) +#define _ADNBND (sizeof (acpi_native_int) - 1) + +/* Variable argument list macro definitions */ +#define _bnd(X, bnd) (((sizeof (X)) + (bnd)) & (~(bnd))) +#define va_arg(ap, T) (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND)))) +#define va_end(ap) (ap = (va_list) NULL) +#define va_start(ap, A) (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND)))) + +#endif /* va_arg */ + +#endif //_VA_LIST_H_ diff --git a/main.c b/main.c new file mode 100644 index 0000000..5793864 --- /dev/null +++ b/main.c @@ -0,0 +1,36 @@ +/* + * Test "Hello World" + */ + +#include +#include +#include "cortex.h" +#include "rtl8710.h" +#include "rom_lib.h" +#include "hal_pinmux.h" + +int main(void) +{ + int i = 6; + HalPinCtrlRtl8195A(JTAG, 0, 1); + HalInitPlatformLogUartV02(); + HalInitPlatformTimerV02(); + HalShowBuildInfoV02(); + do { + HalDelayUs(1000000); + HalCpuClkConfig(--i); // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz + HalReInitPlatformLogUartV02(); + printf("Hello World : %d\r\n", i); + printf("CPU CLK : %d\r\n", HalGetCpuClk()); + } while(i); + printf("End"); + while(1); +} + +extern uint8_t STACK_TOP; +uint32_t *cortex_vectors[] __attribute__((section(".vectors"))) = { + (uint32_t *)&STACK_TOP, + (uint32_t *)main +}; + + diff --git a/rtl8710_flash_boot.s b/rtl8710_flash_boot.s new file mode 100644 index 0000000..5209c4a --- /dev/null +++ b/rtl8710_flash_boot.s @@ -0,0 +1,46 @@ +#define Seg1LoadAddr 0x10000BC8 + + .syntax unified + .global cortex_vectors + +start: +cortex_vectors: +StartFlashRecord: + .org 0x00000000 +SpicCalibrationPattern: + .word 0x96969999 + .word 0xFC66CC3F + .word 0x03CC33C0 + .word 0x6231DCE5 +SegLoadSize: + .word end - load_address +SegLoadAddr: + .word Seg1LoadAddr +NextImageSeg: + .word 0xFFFF0000 + .word 0xFFFFFFFF +load_address: + .word Seg1LoadAddr + (Init - load_address) + 1 + .word Seg1StartAddr + .word Seg1StartAddr + .word Seg1StartAddr + .word Seg1StartAddr +ImageValidPattern: + .word 0x88167923 // if != -> Image1 Validation Incorrect !!! Please Re-boot and try again, or re-burn the flash image + .word 0xFFFFFFFF + .word 0xFFFFFFFF +EndFlashRecord: +Seg1Start: + +Init: + cpsid f + mov r2, #Seg1StartAddr + ldr r3, [r2, #0] + mov sp, r3 + ldr r3, [r2, #4] + bx r3 + + .org (load_address - StartFlashRecord) + (Seg1StartAddr - Seg1LoadAddr) +address: + .incbin BinFileName +end: