mirror of
https://github.com/pvvx/RTL00_HelloWorld.git
synced 2025-07-31 20:21:03 +00:00
initial
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pvvx
parent
aa9624efbe
commit
56693eef0d
125 changed files with 45637 additions and 1 deletions
293
lib/fwlib/src/hal_32k.c
Normal file
293
lib/fwlib/src/hal_32k.c
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@ -0,0 +1,293 @@
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#include "rtl8195a.h"
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#ifdef CONFIG_TIMER_MODULE
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VOID
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En32KCalibration(
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VOID
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)
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{
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u32 Rtemp;
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u32 Ttemp = 0;
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//DiagPrintf("32K clock source calibration\n");
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//set parameter
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HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
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//offset 1 = 0x1500
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Rtemp = 0x811500;
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HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
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HalDelayUs(40);
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HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
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//offset 2 = 0x01c0
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Rtemp = 0x8201c0;
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HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
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HalDelayUs(40);
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HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
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//offset 4 = 0x0100
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Rtemp = 0x840100;
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HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
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HalDelayUs(40);
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HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
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//offset 0 = 0xf980
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Rtemp = 0x80f980;
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HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
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HalDelayUs(40);
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HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
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while(1) {
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//Polling LOCK
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Rtemp = 0x110000;
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HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
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//DiagPrintf("Polling lock\n");
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HalDelayUs(40);
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Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL1);
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if ((Rtemp & 0x3000) != 0x0){
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//DiagPrintf("32.768 Calibration Success\n", Ttemp);
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break;
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}
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else {
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Ttemp++;
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HalDelayUs(30);
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//DiagPrintf("Check lock: %d\n", Ttemp);
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//DiagPrintf("0x278: %x\n", Rtemp);
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if (Ttemp > 100000) { /*Delay 100ms*/
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DiagPrintf("32K Calibration Fail!!\n", Ttemp);
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break;
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}
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}
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}
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}
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#if CONFIG_WDG
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WDG_ADAPTER WDGAdapter;
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extern HAL_TIMER_OP HalTimerOp;
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#ifdef CONFIG_WDG_NORMAL
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VOID
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WDGInitial(
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IN u32 Period
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)
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{
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u8 CountId;
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u16 DivFactor;
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u32 CountTemp;
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u32 CountProcess = 0;
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u32 DivFacProcess = 0;
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u32 PeriodProcess = 100*Period;
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u32 MinPeriodTemp = 0xFFFFFFFF;
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u32 PeriodTemp = 0;
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u32 *Reg = (u32*)&(WDGAdapter.Ctrl);
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DBG_8195A(" Period = 0x%08x\n", Period);
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for (CountId = 0; CountId < 12; CountId++) {
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CountTemp = ((0x00000001 << (CountId+1))-1);
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DivFactor = (u16)((PeriodProcess)/(CountTemp*3));
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if (DivFactor > 0) {
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PeriodTemp = 3*(DivFactor+1)*CountTemp;
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if (PeriodProcess < PeriodTemp) {
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if (MinPeriodTemp > PeriodTemp) {
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MinPeriodTemp = PeriodTemp;
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CountProcess = CountId;
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DivFacProcess = DivFactor;
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}
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}
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}
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}
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DBG_8195A("WdgScalar = 0x%08x\n", DivFacProcess);
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DBG_8195A("WdgCunLimit = 0x%08x\n", CountProcess);
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WDGAdapter.Ctrl.WdgScalar = DivFacProcess;
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WDGAdapter.Ctrl.WdgEnByte = 0;
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WDGAdapter.Ctrl.WdgClear = 1;
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WDGAdapter.Ctrl.WdgCunLimit = CountProcess;
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WDGAdapter.Ctrl.WdgMode = RESET_MODE;
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WDGAdapter.Ctrl.WdgToISR = 0;
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HAL_WRITE32(VENDOR_REG_BASE, 0, (*Reg));
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}
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VOID
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WDGIrqHandle
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(
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IN VOID *Data
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)
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{
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u32 temp;
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WDG_REG *CtrlReg;
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if (NULL != WDGAdapter.UserCallback) {
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WDGAdapter.UserCallback(WDGAdapter.callback_id);
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}
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// Clear ISR
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temp = HAL_READ32(VENDOR_REG_BASE, 0);
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CtrlReg = (WDG_REG*)&temp;
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CtrlReg->WdgToISR = 1; // write 1 clear
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HAL_WRITE32(VENDOR_REG_BASE, 0, (temp));
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}
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VOID
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WDGIrqInitial(
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VOID
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)
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{
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u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
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WDGAdapter.IrqHandle.Data = (u32)&WDGAdapter;
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WDGAdapter.IrqHandle.IrqFun = (IRQ_FUN)WDGIrqHandle;
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WDGAdapter.IrqHandle.IrqNum = WDG_IRQ;
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WDGAdapter.IrqHandle.Priority = 0;
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InterruptRegister(&(WDGAdapter.IrqHandle));
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InterruptEn(&(WDGAdapter.IrqHandle));
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WDGAdapter.Ctrl.WdgToISR = 1; // clear ISR first
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WDGAdapter.Ctrl.WdgMode = INT_MODE;
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HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
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WDGAdapter.Ctrl.WdgToISR = 0;
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}
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VOID
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WDGStart(
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VOID
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)
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{
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u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
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WDGAdapter.Ctrl.WdgEnByte = 0xA5;
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HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
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}
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VOID
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WDGStop(
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VOID
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)
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{
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u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
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WDGAdapter.Ctrl.WdgEnByte = 0;
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HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
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}
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VOID
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WDGRefresh(
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VOID
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)
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{
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u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
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WDGAdapter.Ctrl.WdgClear = 1;
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HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
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}
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VOID
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WDGIrqCallBackReg(
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IN VOID *CallBack,
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IN u32 Id
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)
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{
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WDGAdapter.UserCallback = (VOID (*)(u32))CallBack;
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WDGAdapter.callback_id = Id;
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}
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#endif
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#ifdef CONFIG_WDG_TEST
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VOID
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WDGIrqHandle
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(
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IN VOID *Data
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)
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{
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}
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VOID
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WDGGtimerHandle
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(
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IN VOID *Data
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)
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{
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u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
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WDGAdapter.Ctrl.WdgClear = 1;
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DBG_8195A("reset WDG\n");
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if (HAL_READ32(SYSTEM_CTRL_BASE,REG_SYS_DSTBY_INFO2) == 0) {
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HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
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}
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}
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VOID
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InitWDGIRQ(VOID)
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{
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u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
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WDGAdapter.Ctrl.WdgScalar = 0x96;
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WDGAdapter.Ctrl.WdgEnByte = 0xA5;
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WDGAdapter.Ctrl.WdgClear = 1;
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WDGAdapter.Ctrl.WdgCunLimit = CNTFFFH;
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WDGAdapter.Ctrl.WdgMode = RESET_MODE;
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WDGAdapter.Ctrl.WdgToISR = 0;
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if (WDGAdapter.Ctrl.WdgMode == INT_MODE) {
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WDGAdapter.IrqHandle.Data = NULL;
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WDGAdapter.IrqHandle.IrqFun = (IRQ_FUN)WDGIrqHandle;
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WDGAdapter.IrqHandle.IrqNum = WDG_IRQ;
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WDGAdapter.IrqHandle.Priority = 0;
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InterruptRegister(&(WDGAdapter.IrqHandle));
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InterruptEn(&(WDGAdapter.IrqHandle));
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}
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else {
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WDGAdapter.WdgGTimer.TimerIrqPriority = 0;
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WDGAdapter.WdgGTimer.TimerMode = USER_DEFINED;
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WDGAdapter.WdgGTimer.IrqDis = OFF;
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WDGAdapter.WdgGTimer.TimerId = 2;//
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WDGAdapter.WdgGTimer.IrqHandle.IrqFun = (IRQ_FUN)WDGGtimerHandle;
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WDGAdapter.WdgGTimer.IrqHandle.IrqNum = TIMER2_7_IRQ;
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WDGAdapter.WdgGTimer.IrqHandle.Priority = 0;
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WDGAdapter.WdgGTimer.IrqHandle.Data = NULL;
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if ((WDGAdapter.Ctrl.WdgCunLimit == CNTFFFH)&&(WDGAdapter.Ctrl.WdgScalar >= 0x8429)){
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WDGAdapter.WdgGTimer.TimerLoadValueUs = 0xFFFFFFFF - WDGTIMERELY;
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}
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else {
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WDGAdapter.WdgGTimer.TimerLoadValueUs = (BIT0 << (WDGAdapter.Ctrl.WdgCunLimit+1))
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*WDGAdapter.Ctrl.WdgScalar*TIMER_TICK_US - WDGTIMERELY;
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}
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HalTimerOp.HalTimerInit((VOID*) &(WDGAdapter.WdgGTimer));
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}
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//fill reg
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HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
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}
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//WDG
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VOID HalWdgInit(
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VOID
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)
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{
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}
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#endif //CONFIG_WDG_TEST
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#endif //CONFIG_WDG
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#endif //#ifdef CONFIG_TIMER_MODULE
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1603
lib/fwlib/src/hal_adc.c
Normal file
1603
lib/fwlib/src/hal_adc.c
Normal file
File diff suppressed because it is too large
Load diff
23
lib/fwlib/src/hal_common.c
Normal file
23
lib/fwlib/src/hal_common.c
Normal file
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@ -0,0 +1,23 @@
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#include "rtl8195a.h"
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#include "hal_common.h"
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extern HAL_TIMER_OP HalTimerOp;
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HAL_Status
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HalCommonInit(void){
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#ifdef CONFIG_TIMER_MODULE
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HalTimerOpInit_Patch((VOID*)(&HalTimerOp));
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#endif
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return HAL_OK;
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}
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1450
lib/fwlib/src/hal_dac.c
Normal file
1450
lib/fwlib/src/hal_dac.c
Normal file
File diff suppressed because it is too large
Load diff
574
lib/fwlib/src/hal_gdma.c
Normal file
574
lib/fwlib/src/hal_gdma.c
Normal file
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@ -0,0 +1,574 @@
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
|
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*
|
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* This module is a confidential and proprietary property of RealTek and
|
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* possession or use of this module requires written permission of RealTek.
|
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*/
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#include "rtl8195a.h"
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#include "hal_gdma.h"
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#define MAX_GDMA_INDX 1
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#define MAX_GDMA_CHNL 6
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static u8 HalGdmaReg[MAX_GDMA_INDX+1];
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const HAL_GDMA_CHNL GDMA_Chnl_Option[] = {
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{0,0,GDMA0_CHANNEL0_IRQ,0},
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{1,0,GDMA1_CHANNEL0_IRQ,0},
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{0,1,GDMA0_CHANNEL1_IRQ,0},
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{1,1,GDMA1_CHANNEL1_IRQ,0},
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{0,2,GDMA0_CHANNEL2_IRQ,0},
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{1,2,GDMA1_CHANNEL2_IRQ,0},
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{0,3,GDMA0_CHANNEL3_IRQ,0},
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{1,3,GDMA1_CHANNEL3_IRQ,0},
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{0,4,GDMA0_CHANNEL4_IRQ,0},
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{1,4,GDMA1_CHANNEL4_IRQ,0},
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{0,5,GDMA0_CHANNEL5_IRQ,0},
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{1,5,GDMA1_CHANNEL5_IRQ,0},
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{0xff,0,0,0} // end
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};
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const HAL_GDMA_CHNL GDMA_Multi_Block_Chnl_Option[] = {
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{0,4,GDMA0_CHANNEL4_IRQ,0},
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{1,4,GDMA1_CHANNEL4_IRQ,0},
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{0,5,GDMA0_CHANNEL5_IRQ,0},
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{1,5,GDMA1_CHANNEL5_IRQ,0},
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{0xff,0,0,0} // end
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};
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const u16 HalGdmaChnlEn[6] = {
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GdmaCh0, GdmaCh1, GdmaCh2, GdmaCh3,
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GdmaCh4, GdmaCh5
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};
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|
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VOID HalGdmaOpInit(
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IN VOID *Data
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)
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{
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PHAL_GDMA_OP pHalGdmaOp = (PHAL_GDMA_OP) Data;
|
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|
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pHalGdmaOp->HalGdmaOnOff = HalGdmaOnOffRtl8195a;
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pHalGdmaOp->HalGdamChInit = HalGdamChInitRtl8195a;
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pHalGdmaOp->HalGdmaChDis = HalGdmaChDisRtl8195a;
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pHalGdmaOp->HalGdmaChEn = HalGdmaChEnRtl8195a;
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pHalGdmaOp->HalGdmaChSeting = HalGdmaChSetingRtl8195a;
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#ifndef CONFIG_CHIP_E_CUT
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pHalGdmaOp->HalGdmaChBlockSeting = HalGdmaChBlockSetingRtl8195a;
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#else
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pHalGdmaOp->HalGdmaChBlockSeting = HalGdmaChBlockSetingRtl8195a_V04;
|
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#endif
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pHalGdmaOp->HalGdmaChIsrEnAndDis = HalGdmaChIsrEnAndDisRtl8195a;
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pHalGdmaOp->HalGdmaChIsrClean = HalGdmaChIsrCleanRtl8195a;
|
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pHalGdmaOp->HalGdmaChCleanAutoSrc = HalGdmaChCleanAutoSrcRtl8195a;
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pHalGdmaOp->HalGdmaChCleanAutoDst = HalGdmaChCleanAutoDstRtl8195a;
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}
|
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|
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VOID HalGdmaOn(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
|
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{
|
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pHalGdmaAdapter->GdmaOnOff = ON;
|
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HalGdmaOnOffRtl8195a((VOID*)pHalGdmaAdapter);
|
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}
|
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|
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VOID HalGdmaOff(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
|
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{
|
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pHalGdmaAdapter->GdmaOnOff = OFF;
|
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HalGdmaOnOffRtl8195a((VOID*)pHalGdmaAdapter);
|
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}
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|
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BOOL HalGdmaChInit(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
|
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{
|
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return (HalGdamChInitRtl8195a((VOID*)pHalGdmaAdapter));
|
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}
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||||
|
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VOID HalGdmaChDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
|
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{
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HalGdmaChDisRtl8195a((VOID*)pHalGdmaAdapter);
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}
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|
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VOID HalGdmaChEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
|
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{
|
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HalGdmaChEnRtl8195a((VOID*)pHalGdmaAdapter);
|
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}
|
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|
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BOOL HalGdmaChSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
|
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{
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return (HalGdmaChSetingRtl8195a((VOID*)pHalGdmaAdapter));
|
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}
|
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|
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BOOL HalGdmaChBlockSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
|
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{
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#ifndef CONFIG_CHIP_E_CUT
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return (HalGdmaChBlockSetingRtl8195a((VOID*)pHalGdmaAdapter));
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#else
|
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return (HalGdmaChBlockSetingRtl8195a_V04((VOID*)pHalGdmaAdapter));
|
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#endif
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}
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|
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VOID HalGdmaChIsrEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
|
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{
|
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pHalGdmaAdapter->IsrCtrl = ENABLE;
|
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HalGdmaChIsrEnAndDisRtl8195a((VOID*)pHalGdmaAdapter);
|
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}
|
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|
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VOID HalGdmaChIsrDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
|
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{
|
||||
pHalGdmaAdapter->IsrCtrl = DISABLE;
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HalGdmaChIsrEnAndDisRtl8195a((VOID*)pHalGdmaAdapter);
|
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}
|
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|
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u8 HalGdmaChIsrClean(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
|
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{
|
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return (HalGdmaChIsrCleanRtl8195a((VOID*)pHalGdmaAdapter));
|
||||
}
|
||||
|
||||
VOID HalGdmaChCleanAutoSrc(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
|
||||
{
|
||||
HalGdmaChCleanAutoSrcRtl8195a((VOID*)pHalGdmaAdapter);
|
||||
}
|
||||
|
||||
VOID HalGdmaChCleanAutoDst(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
|
||||
{
|
||||
HalGdmaChCleanAutoDstRtl8195a((VOID*)pHalGdmaAdapter);
|
||||
}
|
||||
|
||||
HAL_Status HalGdmaChnlRegister (u8 GdmaIdx, u8 ChnlNum)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
if ((GdmaIdx > MAX_GDMA_INDX) || (ChnlNum > MAX_GDMA_CHNL)) {
|
||||
// Invalid GDMA Index or Channel Number
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
mask = 1 << ChnlNum;
|
||||
|
||||
if ((HalGdmaReg[GdmaIdx] & mask) != 0) {
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else {
|
||||
#if 1
|
||||
if (HalGdmaReg[GdmaIdx] == 0) {
|
||||
if (GdmaIdx == 0) {
|
||||
ACTCK_GDMA0_CCTRL(ON);
|
||||
GDMA0_FCTRL(ON);
|
||||
}
|
||||
else {
|
||||
ACTCK_GDMA1_CCTRL(ON);
|
||||
GDMA1_FCTRL(ON);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
HalGdmaReg[GdmaIdx] |= mask;
|
||||
return HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
VOID HalGdmaChnlUnRegister (u8 GdmaIdx, u8 ChnlNum)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
if ((GdmaIdx > MAX_GDMA_INDX) || (ChnlNum > MAX_GDMA_CHNL)) {
|
||||
// Invalid GDMA Index or Channel Number
|
||||
return;
|
||||
}
|
||||
|
||||
mask = 1 << ChnlNum;
|
||||
|
||||
HalGdmaReg[GdmaIdx] &= ~mask;
|
||||
#if 1
|
||||
if (HalGdmaReg[GdmaIdx] == 0) {
|
||||
if (GdmaIdx == 0) {
|
||||
ACTCK_GDMA0_CCTRL(OFF);
|
||||
GDMA0_FCTRL(OFF);
|
||||
}
|
||||
else {
|
||||
ACTCK_GDMA1_CCTRL(OFF);
|
||||
GDMA1_FCTRL(OFF);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
PHAL_GDMA_CHNL HalGdmaChnlAlloc (HAL_GDMA_CHNL *pChnlOption)
|
||||
{
|
||||
HAL_GDMA_CHNL *pgdma_chnl;
|
||||
|
||||
pgdma_chnl = pChnlOption;
|
||||
if (pChnlOption == NULL) {
|
||||
// Use default GDMA Channel Option table
|
||||
pgdma_chnl = (HAL_GDMA_CHNL*)&GDMA_Chnl_Option[0];
|
||||
}
|
||||
else{
|
||||
pgdma_chnl = (HAL_GDMA_CHNL*) pgdma_chnl;
|
||||
}
|
||||
|
||||
while (pgdma_chnl->GdmaIndx <= MAX_GDMA_INDX) {
|
||||
if (HalGdmaChnlRegister(pgdma_chnl->GdmaIndx, pgdma_chnl->GdmaChnl) == HAL_OK) {
|
||||
// This GDMA Channel is available
|
||||
break;
|
||||
}
|
||||
pgdma_chnl += 1;
|
||||
}
|
||||
|
||||
if (pgdma_chnl->GdmaIndx > MAX_GDMA_INDX) {
|
||||
pgdma_chnl = NULL;
|
||||
}
|
||||
|
||||
return pgdma_chnl;
|
||||
}
|
||||
|
||||
VOID HalGdmaChnlFree (HAL_GDMA_CHNL *pChnl)
|
||||
{
|
||||
IRQ_HANDLE IrqHandle;
|
||||
|
||||
IrqHandle.IrqNum = pChnl->IrqNum;
|
||||
InterruptDis(&IrqHandle);
|
||||
InterruptUnRegister(&IrqHandle);
|
||||
HalGdmaChnlUnRegister(pChnl->GdmaIndx, pChnl->GdmaChnl);
|
||||
}
|
||||
|
||||
VOID HalGdmaMemIrqHandler(VOID *pData)
|
||||
{
|
||||
PHAL_GDMA_OBJ pHalGdmaObj=(PHAL_GDMA_OBJ)pData;
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
PIRQ_HANDLE pGdmaIrqHandle;
|
||||
|
||||
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
|
||||
pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
|
||||
// Clean Auto Reload Bit
|
||||
HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter);
|
||||
|
||||
// Clear Pending ISR
|
||||
HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
|
||||
|
||||
HalGdmaChDis((VOID*)(pHalGdmaAdapter));
|
||||
pHalGdmaObj->Busy = 0;
|
||||
|
||||
if (pGdmaIrqHandle->IrqFun != NULL) {
|
||||
pGdmaIrqHandle->IrqFun((VOID*)pGdmaIrqHandle->Data);
|
||||
}
|
||||
}
|
||||
|
||||
BOOL HalGdmaMemCpyAggrInit(PHAL_GDMA_OBJ pHalGdmaObj)
|
||||
{
|
||||
HAL_GDMA_CHNL *pgdma_chnl;
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
PIRQ_HANDLE pGdmaIrqHandle;
|
||||
IRQ_HANDLE IrqHandle;
|
||||
|
||||
pgdma_chnl = HalGdmaChnlAlloc((PHAL_GDMA_CHNL) &GDMA_Multi_Block_Chnl_Option[0]); // get a whatever GDMA channel
|
||||
if (NULL == pgdma_chnl) {
|
||||
DBG_GDMA_ERR("%s: Cannot allocate a GDMA Channel\n", __FUNCTION__);
|
||||
return _FALSE;
|
||||
}
|
||||
|
||||
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
|
||||
pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
|
||||
|
||||
DBG_GDMA_INFO("%s: Use GDMA%d CH%d\n", __FUNCTION__, pgdma_chnl->GdmaIndx, pgdma_chnl->GdmaChnl);
|
||||
|
||||
_memset((void *)pHalGdmaAdapter, 0, sizeof(HAL_GDMA_ADAPTER));
|
||||
|
||||
pHalGdmaAdapter->GdmaCtl.TtFc = TTFCMemToMem;
|
||||
pHalGdmaAdapter->GdmaCtl.Done = 1;
|
||||
pHalGdmaAdapter->MuliBlockCunt = 0;
|
||||
pHalGdmaAdapter->MaxMuliBlock = 1;
|
||||
pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl;
|
||||
pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx;
|
||||
pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl;
|
||||
pHalGdmaAdapter->GdmaIsrType = (TransferType|ErrType);
|
||||
pHalGdmaAdapter->IsrCtrl = ENABLE;
|
||||
pHalGdmaAdapter->GdmaOnOff = ON;
|
||||
pHalGdmaAdapter->GdmaCtl.IntEn = 1;
|
||||
pHalGdmaAdapter->Rsvd4to7 = 1;
|
||||
pHalGdmaAdapter->Llpctrl = 1;
|
||||
pGdmaIrqHandle->IrqNum = pgdma_chnl->IrqNum;
|
||||
pGdmaIrqHandle->Priority = 0x10;
|
||||
|
||||
IrqHandle.IrqFun = (IRQ_FUN) HalGdmaMemIrqHandler;
|
||||
IrqHandle.Data = (u32) pHalGdmaObj;
|
||||
IrqHandle.IrqNum = pGdmaIrqHandle->IrqNum;
|
||||
IrqHandle.Priority = pGdmaIrqHandle->Priority;
|
||||
|
||||
InterruptRegister(&IrqHandle);
|
||||
InterruptEn(&IrqHandle);
|
||||
pHalGdmaObj->Busy = 0;
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
|
||||
VOID HalGdmaMultiBlockSetting(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
u8 BlockNumber;
|
||||
u8 BlockIndex;
|
||||
u8 FourBytesAlign;
|
||||
|
||||
BlockNumber = pHalGdmaObj->BlockNum;
|
||||
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
|
||||
|
||||
pHalGdmaAdapter->GdmaCtl.LlpSrcEn = 1;
|
||||
pHalGdmaAdapter->GdmaCtl.LlpDstEn = 1;
|
||||
|
||||
if(((pHalGdmaBlock[0].SrcAddr & 0x03) == 0) &&((pHalGdmaBlock[0].DstAddr & 0x03) == 0)
|
||||
&& ((pHalGdmaBlock[0].BlockLength & 0X03) == 0)){
|
||||
pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight;
|
||||
pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes;
|
||||
pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
|
||||
pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes;
|
||||
FourBytesAlign = 1;
|
||||
}
|
||||
else{
|
||||
pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight;
|
||||
pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte;
|
||||
pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
|
||||
pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte;
|
||||
FourBytesAlign = 0;
|
||||
}
|
||||
|
||||
for(BlockIndex = 0; BlockIndex < BlockNumber; BlockIndex++){
|
||||
|
||||
pHalGdmaObj->GdmaChLli[BlockIndex].Sarx = pHalGdmaBlock[BlockIndex].SrcAddr;
|
||||
pHalGdmaObj->GdmaChLli[BlockIndex].Darx = pHalGdmaBlock[BlockIndex].DstAddr;
|
||||
pHalGdmaObj->BlockSizeList[BlockIndex].pNextBlockSiz = &pHalGdmaObj->BlockSizeList[BlockIndex + 1];
|
||||
|
||||
if(FourBytesAlign){
|
||||
pHalGdmaObj->BlockSizeList[BlockIndex].BlockSize = pHalGdmaBlock[BlockIndex].BlockLength >> 2;
|
||||
}
|
||||
else{
|
||||
pHalGdmaObj->BlockSizeList[BlockIndex].BlockSize = pHalGdmaBlock[BlockIndex].BlockLength;
|
||||
}
|
||||
|
||||
pHalGdmaObj->Lli[BlockIndex].pLliEle = (GDMA_CH_LLI_ELE*) &pHalGdmaObj->GdmaChLli[BlockIndex];
|
||||
pHalGdmaObj->Lli[BlockIndex].pNextLli = &pHalGdmaObj->Lli[BlockIndex + 1];
|
||||
|
||||
|
||||
if(BlockIndex == BlockNumber - 1){
|
||||
pHalGdmaObj->BlockSizeList[BlockIndex].pNextBlockSiz = NULL;
|
||||
pHalGdmaObj->Lli[BlockIndex].pNextLli = NULL;
|
||||
}
|
||||
//DBG_GDMA_INFO("Lli[%d].pLiEle = %x\r\n", BlockIndex,Lli[BlockIndex].pLliEle);
|
||||
//DBG_GDMA_INFO("Lli[%d].pNextLli = %x\r\n", BlockIndex,Lli[BlockIndex].pNextLli);
|
||||
}
|
||||
|
||||
pHalGdmaAdapter->pBlockSizeList = (struct BLOCK_SIZE_LIST*) &pHalGdmaObj->BlockSizeList;
|
||||
pHalGdmaAdapter->pLlix = (struct GDMA_CH_LLI*) &pHalGdmaObj->Lli;
|
||||
//DBG_GDMA_INFO("pHalGdmaAdapter->pBlockSizeList = %x\r\n", pHalGdmaAdapter->pBlockSizeList);
|
||||
//DBG_GDMA_INFO("pHalGdmaAdapter->pLlix = %x\r\n", pHalGdmaAdapter->pLlix );
|
||||
}
|
||||
|
||||
VOID HalGdmaLLPMemAlign(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
PGDMA_CH_LLI_ELE pLliEle;
|
||||
struct GDMA_CH_LLI *pGdmaChLli;
|
||||
struct BLOCK_SIZE_LIST *pGdmaChBkLi;
|
||||
u32 CtlxLow;
|
||||
u32 CtlxUp;
|
||||
u8 BlockNumber;
|
||||
u8 BlockIndex;
|
||||
|
||||
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
|
||||
BlockNumber = pHalGdmaObj->BlockNum;
|
||||
|
||||
pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
|
||||
pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
|
||||
pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
|
||||
|
||||
//4 Move to the second block to configure Memory Alginment setting
|
||||
pLliEle->Llpx = (u32) pGdmaChLli->pLliEle;
|
||||
pGdmaChBkLi = pGdmaChBkLi ->pNextBlockSiz;
|
||||
|
||||
for(BlockIndex = 1; BlockIndex < BlockNumber; BlockIndex++){
|
||||
pLliEle = pGdmaChLli->pLliEle;
|
||||
CtlxLow = pLliEle->CtlxLow;
|
||||
CtlxLow &= (BIT_INVC_CTLX_LO_DST_TR_WIDTH & BIT_INVC_CTLX_LO_SRC_TR_WIDTH);
|
||||
CtlxUp = pLliEle->CtlxUp;
|
||||
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
|
||||
|
||||
if(((pHalGdmaBlock[BlockIndex].SrcAddr & 0x03) == 0) &&((pHalGdmaBlock[BlockIndex].DstAddr & 0x03) == 0)
|
||||
&& ((pHalGdmaBlock[BlockIndex].BlockLength & 0X03) == 0)){
|
||||
pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes;
|
||||
pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes;
|
||||
pGdmaChBkLi->BlockSize = pHalGdmaBlock[BlockIndex].BlockLength>> 2;
|
||||
|
||||
}
|
||||
else{
|
||||
pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte;
|
||||
pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte;
|
||||
pGdmaChBkLi->BlockSize = pHalGdmaBlock[BlockIndex].BlockLength;
|
||||
}
|
||||
|
||||
CtlxLow |= (BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
|
||||
BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth));
|
||||
CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
|
||||
|
||||
pGdmaChLli = pGdmaChLli->pNextLli;
|
||||
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
|
||||
pLliEle->CtlxLow = CtlxLow;
|
||||
pLliEle->CtlxUp = CtlxUp;
|
||||
pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
VOID HalGdmaMemAggr(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
|
||||
u8 BlockNumber;
|
||||
|
||||
BlockNumber = pHalGdmaObj->BlockNum;
|
||||
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
|
||||
|
||||
if (pHalGdmaObj->Busy) {
|
||||
DBG_GDMA_ERR("%s: ==> GDMA is Busy\r\n", __FUNCTION__);
|
||||
return;
|
||||
}
|
||||
pHalGdmaObj->Busy = 1;
|
||||
|
||||
pHalGdmaAdapter->MaxMuliBlock = BlockNumber;
|
||||
pHalGdmaAdapter->ChSar = pHalGdmaBlock[0].SrcAddr;
|
||||
pHalGdmaAdapter->ChDar = pHalGdmaBlock[0].DstAddr;
|
||||
|
||||
HalGdmaMultiBlockSetting(pHalGdmaObj, pHalGdmaBlock);
|
||||
HalGdmaOn((pHalGdmaAdapter));
|
||||
HalGdmaChIsrEn((pHalGdmaAdapter));
|
||||
HalGdmaChBlockSeting((pHalGdmaAdapter));
|
||||
HalGdmaLLPMemAlign(pHalGdmaObj, pHalGdmaBlock);
|
||||
HalGdmaChEn((pHalGdmaAdapter));
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
BOOL HalGdmaMemCpyInit(PHAL_GDMA_OBJ pHalGdmaObj)
|
||||
{
|
||||
HAL_GDMA_CHNL *pgdma_chnl;
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
PIRQ_HANDLE pGdmaIrqHandle;
|
||||
IRQ_HANDLE IrqHandle;
|
||||
|
||||
pgdma_chnl = HalGdmaChnlAlloc(NULL); // get a whatever GDMA channel
|
||||
if (NULL == pgdma_chnl) {
|
||||
DBG_GDMA_ERR("%s: Cannot allocate a GDMA Channel\n", __FUNCTION__);
|
||||
return _FALSE;
|
||||
}
|
||||
|
||||
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
|
||||
pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
|
||||
|
||||
DBG_GDMA_INFO("%s: Use GDMA%d CH%d\n", __FUNCTION__, pgdma_chnl->GdmaIndx, pgdma_chnl->GdmaChnl);
|
||||
#if 0
|
||||
if (pgdma_chnl->GdmaIndx == 0) {
|
||||
ACTCK_GDMA0_CCTRL(ON);
|
||||
GDMA0_FCTRL(ON);
|
||||
}
|
||||
else if (pgdma_chnl->GdmaIndx == 1) {
|
||||
ACTCK_GDMA1_CCTRL(ON);
|
||||
GDMA1_FCTRL(ON);
|
||||
}
|
||||
#endif
|
||||
_memset((void *)pHalGdmaAdapter, 0, sizeof(HAL_GDMA_ADAPTER));
|
||||
|
||||
// pHalGdmaAdapter->GdmaCtl.TtFc = TTFCMemToMem;
|
||||
pHalGdmaAdapter->GdmaCtl.Done = 1;
|
||||
// pHalGdmaAdapter->MuliBlockCunt = 0;
|
||||
// pHalGdmaAdapter->MaxMuliBlock = 1;
|
||||
pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl;
|
||||
pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx;
|
||||
pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl;
|
||||
pHalGdmaAdapter->GdmaIsrType = (TransferType|ErrType);
|
||||
pHalGdmaAdapter->IsrCtrl = ENABLE;
|
||||
pHalGdmaAdapter->GdmaOnOff = ON;
|
||||
|
||||
pHalGdmaAdapter->GdmaCtl.IntEn = 1;
|
||||
// pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight;
|
||||
// pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
|
||||
// pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes;
|
||||
// pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes;
|
||||
// pHalGdmaAdapter->GdmaCtl.Dinc = IncType;
|
||||
// pHalGdmaAdapter->GdmaCtl.Sinc = IncType;
|
||||
|
||||
pGdmaIrqHandle->IrqNum = pgdma_chnl->IrqNum;
|
||||
pGdmaIrqHandle->Priority = 10;
|
||||
|
||||
IrqHandle.IrqFun = (IRQ_FUN) HalGdmaMemIrqHandler;
|
||||
IrqHandle.Data = (u32) pHalGdmaObj;
|
||||
IrqHandle.IrqNum = pGdmaIrqHandle->IrqNum;
|
||||
IrqHandle.Priority = pGdmaIrqHandle->Priority;
|
||||
|
||||
InterruptRegister(&IrqHandle);
|
||||
InterruptEn(&IrqHandle);
|
||||
pHalGdmaObj->Busy = 0;
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
VOID HalGdmaMemCpyDeInit(PHAL_GDMA_OBJ pHalGdmaObj)
|
||||
{
|
||||
HAL_GDMA_CHNL GdmaChnl;
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
PIRQ_HANDLE pGdmaIrqHandle;
|
||||
|
||||
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
|
||||
pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
|
||||
|
||||
GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
|
||||
GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
|
||||
GdmaChnl.IrqNum = pGdmaIrqHandle->IrqNum;
|
||||
HalGdmaChnlFree(&GdmaChnl);
|
||||
}
|
||||
|
||||
// If multi-task using the same GDMA Object, then it needs a mutex to protect this procedure
|
||||
VOID* HalGdmaMemCpy(PHAL_GDMA_OBJ pHalGdmaObj, void* pDest, void* pSrc, u32 len)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
|
||||
if (pHalGdmaObj->Busy) {
|
||||
DBG_GDMA_ERR("%s: ==> GDMA is Busy\r\n", __FUNCTION__);
|
||||
return 0;
|
||||
}
|
||||
pHalGdmaObj->Busy = 1;
|
||||
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
|
||||
|
||||
DBG_GDMA_INFO("%s: ==> Src=0x%x Dst=0x%x Len=%d\r\n", __FUNCTION__, pSrc, pDest, len);
|
||||
if ((((u32)pSrc & 0x03)==0) &&
|
||||
(((u32)pDest & 0x03)==0) &&
|
||||
((len & 0x03)== 0)) {
|
||||
// 4-bytes aligned, move 4 bytes each transfer
|
||||
pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight;
|
||||
pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes;
|
||||
pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
|
||||
pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes;
|
||||
pHalGdmaAdapter->GdmaCtl.BlockSize = len >> 2;
|
||||
}
|
||||
else {
|
||||
pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight;
|
||||
pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte;
|
||||
pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
|
||||
pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte;
|
||||
pHalGdmaAdapter->GdmaCtl.BlockSize = len;
|
||||
}
|
||||
|
||||
pHalGdmaAdapter->ChSar = (u32)pSrc;
|
||||
pHalGdmaAdapter->ChDar = (u32)pDest;
|
||||
pHalGdmaAdapter->PacketLen = len;
|
||||
|
||||
HalGdmaOn((pHalGdmaAdapter));
|
||||
HalGdmaChIsrEn((pHalGdmaAdapter));
|
||||
HalGdmaChSeting((pHalGdmaAdapter));
|
||||
HalGdmaChEn((pHalGdmaAdapter));
|
||||
|
||||
return (pDest);
|
||||
}
|
||||
145
lib/fwlib/src/hal_gpio.c
Normal file
145
lib/fwlib/src/hal_gpio.c
Normal file
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
#include "rtl8195a.h"
|
||||
|
||||
#ifdef CONFIG_GPIO_EN
|
||||
|
||||
HAL_GPIO_DATA_SECTION HAL_GPIO_ADAPTER gHAL_Gpio_Adapter;
|
||||
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
|
||||
|
||||
extern VOID GPIO_PullCtrl_8195a(u32 chip_pin, u8 pull_type);
|
||||
|
||||
/**
|
||||
* @brief To get the GPIO IP Pin name for the given chip pin name
|
||||
*
|
||||
* @param chip_pin: The chip pin name.
|
||||
*
|
||||
* @retval The gotten GPIO IP pin name
|
||||
*/
|
||||
HAL_GPIO_TEXT_SECTION u32
|
||||
HAL_GPIO_GetPinName(
|
||||
u32 chip_pin
|
||||
)
|
||||
{
|
||||
return HAL_GPIO_GetIPPinName_8195a((u32)chip_pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the GPIO pad Pull type
|
||||
*
|
||||
* @param pin: The pin for pull type control.
|
||||
* @param mode: the pull type for the pin.
|
||||
* @return None
|
||||
*/
|
||||
VOID
|
||||
HAL_GPIO_PullCtrl(
|
||||
u32 pin,
|
||||
u32 mode
|
||||
)
|
||||
{
|
||||
u8 pull_type;
|
||||
|
||||
DBG_GPIO_INFO("%s: pin=0x%x mode=%d\n ", __FUNCTION__, (u32)pin, (u32)mode);
|
||||
|
||||
switch (mode) {
|
||||
case hal_PullNone:
|
||||
pull_type = DIN_PULL_NONE;
|
||||
break;
|
||||
|
||||
case hal_PullDown:
|
||||
pull_type = DIN_PULL_LOW;
|
||||
break;
|
||||
|
||||
case hal_PullUp:
|
||||
pull_type = DIN_PULL_HIGH;
|
||||
break;
|
||||
|
||||
case hal_OpenDrain:
|
||||
default:
|
||||
pull_type = DIN_PULL_NONE;
|
||||
break;
|
||||
}
|
||||
|
||||
// HAL_GPIO_PullCtrl_8195a (pin, pull_type);
|
||||
GPIO_PullCtrl_8195a (pin, pull_type);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes a GPIO Pin by the GPIO_Pin parameters.
|
||||
*
|
||||
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
|
||||
*
|
||||
* @retval HAL_Status
|
||||
*/
|
||||
HAL_GPIO_TEXT_SECTION VOID
|
||||
HAL_GPIO_Init(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
)
|
||||
{
|
||||
if (_pHAL_Gpio_Adapter == NULL) {
|
||||
_pHAL_Gpio_Adapter = &gHAL_Gpio_Adapter;
|
||||
DBG_GPIO_INFO("%s: Initial GPIO Adapter\n ", __FUNCTION__);
|
||||
}
|
||||
|
||||
HAL_GPIO_Init_8195a(GPIO_Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes a GPIO Pin as a interrupt signal
|
||||
*
|
||||
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
|
||||
*
|
||||
* @retval HAL_Status
|
||||
*/
|
||||
VOID
|
||||
HAL_GPIO_Irq_Init(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
)
|
||||
{
|
||||
if (_pHAL_Gpio_Adapter == NULL) {
|
||||
_pHAL_Gpio_Adapter = &gHAL_Gpio_Adapter;
|
||||
DBG_GPIO_INFO("%s: Initial GPIO Adapter\n ", __FUNCTION__);
|
||||
}
|
||||
|
||||
if (_pHAL_Gpio_Adapter->IrqHandle.IrqFun == NULL) {
|
||||
_pHAL_Gpio_Adapter->IrqHandle.IrqFun = HAL_GPIO_MbedIrqHandler_8195a;
|
||||
_pHAL_Gpio_Adapter->IrqHandle.Priority = 8;
|
||||
HAL_GPIO_RegIrq_8195a(&_pHAL_Gpio_Adapter->IrqHandle);
|
||||
InterruptEn(&_pHAL_Gpio_Adapter->IrqHandle);
|
||||
DBG_GPIO_INFO("%s: Initial GPIO IRQ Adapter\n ", __FUNCTION__);
|
||||
}
|
||||
|
||||
DBG_GPIO_INFO("%s: GPIO(name=0x%x)(mode=%d)\n ", __FUNCTION__, GPIO_Pin->pin_name,
|
||||
GPIO_Pin->pin_mode);
|
||||
HAL_GPIO_MaskIrq_8195a(GPIO_Pin);
|
||||
HAL_GPIO_Init_8195a(GPIO_Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UnInitial GPIO Adapter
|
||||
*
|
||||
*
|
||||
* @retval HAL_Status
|
||||
*/
|
||||
VOID
|
||||
HAL_GPIO_IP_DeInit(
|
||||
VOID
|
||||
)
|
||||
{
|
||||
if (_pHAL_Gpio_Adapter != NULL) {
|
||||
InterruptDis(&_pHAL_Gpio_Adapter->IrqHandle);
|
||||
HAL_GPIO_UnRegIrq_8195a(&_pHAL_Gpio_Adapter->IrqHandle);
|
||||
_pHAL_Gpio_Adapter = NULL;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // CONFIG_GPIO_EN
|
||||
2694
lib/fwlib/src/hal_i2c.c
Normal file
2694
lib/fwlib/src/hal_i2c.c
Normal file
File diff suppressed because it is too large
Load diff
535
lib/fwlib/src/hal_i2s.c
Normal file
535
lib/fwlib/src/hal_i2s.c
Normal file
|
|
@ -0,0 +1,535 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "hal_i2s.h"
|
||||
#include "rand.h"
|
||||
#include "rtl_utility.h"
|
||||
|
||||
|
||||
//1 need to be modified
|
||||
|
||||
|
||||
/*======================================================
|
||||
Local used variables
|
||||
*/
|
||||
SRAM_BF_DATA_SECTION
|
||||
HAL_I2S_OP HalI2SOpSAL={0};
|
||||
|
||||
|
||||
VOID
|
||||
I2SISRHandle(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_ADAPTER pI2SAdp = (PHAL_I2S_ADAPTER) Data;
|
||||
PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL;
|
||||
PHAL_I2S_INIT_DAT pI2SCfg = pI2SAdp->pInitDat;
|
||||
u32 I2STxIsr, I2SRxIsr;
|
||||
u8 I2SPageNum = pI2SCfg->I2SPageNum+1;
|
||||
// u32 I2SPageSize = (pI2SAdp->I2SPageSize+1)<<2;
|
||||
u32 i;
|
||||
u32 pbuf;
|
||||
|
||||
I2STxIsr = pHalI2SOP->HalI2SReadReg(pI2SCfg, REG_I2S_TX_STATUS_INT);
|
||||
I2SRxIsr = pHalI2SOP->HalI2SReadReg(pI2SCfg, REG_I2S_RX_STATUS_INT);
|
||||
|
||||
pI2SCfg->I2STxIntrClr = I2STxIsr;
|
||||
pI2SCfg->I2SRxIntrClr = I2SRxIsr;
|
||||
pHalI2SOP->HalI2SClrIntr(pI2SCfg);
|
||||
|
||||
for (i=0 ; i<I2SPageNum ; i++) { // page 0, 1, 2, 3
|
||||
if (I2STxIsr & (1<<pI2SCfg->I2SHWTxIdx)) {
|
||||
// pbuf = ((u32)(pI2SCfg->I2STxData)) + (I2SPageSize*pI2SCfg->I2SHWTxIdx);
|
||||
pbuf = (u32)pI2SAdp->TxPageList[pI2SCfg->I2SHWTxIdx];
|
||||
pI2SAdp->UserCB.TxCCB(pI2SAdp->UserCB.TxCBId, (char*)pbuf);
|
||||
I2STxIsr &= ~(1<<pI2SCfg->I2SHWTxIdx);
|
||||
pI2SCfg->I2SHWTxIdx += 1;
|
||||
if (pI2SCfg->I2SHWTxIdx == I2SPageNum) {
|
||||
pI2SCfg->I2SHWTxIdx = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (I2SRxIsr & (1<<pI2SCfg->I2SHWRxIdx)) {
|
||||
// pbuf = ((u32)(pI2SCfg->I2SRxData)) + (I2SPageSize*pI2SCfg->I2SHWRxIdx);
|
||||
pbuf = (u32)pI2SAdp->RxPageList[pI2SCfg->I2SHWRxIdx];
|
||||
pI2SAdp->UserCB.RxCCB(pI2SAdp->UserCB.RxCBId, (char*)pbuf);
|
||||
I2SRxIsr &= ~(1<<pI2SCfg->I2SHWRxIdx);
|
||||
pI2SCfg->I2SHWRxIdx += 1;
|
||||
if (pI2SCfg->I2SHWRxIdx == I2SPageNum) {
|
||||
pI2SCfg->I2SHWRxIdx = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static HAL_Status
|
||||
RtkI2SIrqInit(
|
||||
IN PHAL_I2S_ADAPTER pI2SAdapter
|
||||
)
|
||||
{
|
||||
PIRQ_HANDLE pIrqHandle;
|
||||
|
||||
if (pI2SAdapter->DevNum > I2S_MAX_ID) {
|
||||
DBG_I2S_ERR("RtkI2SIrqInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
pIrqHandle = &pI2SAdapter->IrqHandle;
|
||||
|
||||
switch (pI2SAdapter->DevNum){
|
||||
case I2S0_SEL:
|
||||
pIrqHandle->IrqNum = I2S0_PCM0_IRQ;
|
||||
break;
|
||||
|
||||
case I2S1_SEL:
|
||||
pIrqHandle->IrqNum = I2S1_PCM1_IRQ;
|
||||
break;
|
||||
|
||||
default:
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
pIrqHandle->Data = (u32) (pI2SAdapter);
|
||||
pIrqHandle->IrqFun = (IRQ_FUN) I2SISRHandle;
|
||||
pIrqHandle->Priority = 3;
|
||||
InterruptRegister(pIrqHandle);
|
||||
InterruptEn(pIrqHandle);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
static HAL_Status
|
||||
RtkI2SIrqDeInit(
|
||||
IN PHAL_I2S_ADAPTER pI2SAdapter
|
||||
)
|
||||
{
|
||||
if (pI2SAdapter->DevNum > I2S_MAX_ID) {
|
||||
DBG_I2S_ERR("RtkI2SIrqDeInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
InterruptDis(&pI2SAdapter->IrqHandle);
|
||||
InterruptUnRegister(&pI2SAdapter->IrqHandle);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
static HAL_Status
|
||||
RtkI2SPinMuxInit(
|
||||
IN PHAL_I2S_ADAPTER pI2SAdapter
|
||||
)
|
||||
{
|
||||
u32 I2Stemp;
|
||||
|
||||
if (pI2SAdapter->DevNum > I2S_MAX_ID) {
|
||||
DBG_I2S_ERR("RtkI2SPinMuxInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
// enable system pll
|
||||
I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) | (1<<9) | (1<<10);
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);
|
||||
|
||||
switch (pI2SAdapter->DevNum){
|
||||
case I2S0_SEL:
|
||||
ACTCK_I2S_CCTRL(ON);
|
||||
SLPCK_I2S_CCTRL(ON);
|
||||
LXBUS_FCTRL(ON); // enable lx bus for i2s
|
||||
|
||||
/*I2S0 Pin Mux Setting*/
|
||||
PinCtrl(I2S0, pI2SAdapter->PinMux, ON);
|
||||
if (pI2SAdapter->PinMux == I2S_S0) {
|
||||
DBG_I2S_WARN(ANSI_COLOR_MAGENTA"I2S0 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
|
||||
}
|
||||
I2S0_MCK_CTRL(ON);
|
||||
I2S0_PIN_CTRL(ON);
|
||||
I2S0_FCTRL(ON);
|
||||
|
||||
break;
|
||||
case I2S1_SEL:
|
||||
ACTCK_I2S_CCTRL(ON);
|
||||
SLPCK_I2S_CCTRL(ON);
|
||||
LXBUS_FCTRL(ON); // enable lx bus for i2s
|
||||
|
||||
/*I2S1 Pin Mux Setting*/
|
||||
PinCtrl(I2S1, pI2SAdapter->PinMux, ON);
|
||||
if (pI2SAdapter->PinMux == I2S_S2) {
|
||||
DBG_I2S_WARN(ANSI_COLOR_MAGENTA"I2S1 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
|
||||
}
|
||||
I2S1_MCK_CTRL(ON);
|
||||
I2S1_PIN_CTRL(ON);
|
||||
I2S0_FCTRL(ON); //i2s 1 is control by bit 24 BIT_PERI_I2S0_EN
|
||||
I2S1_FCTRL(ON);
|
||||
break;
|
||||
default:
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
static HAL_Status
|
||||
RtkI2SPinMuxDeInit(
|
||||
IN PHAL_I2S_ADAPTER pI2SAdapter
|
||||
)
|
||||
{
|
||||
if (pI2SAdapter->DevNum > I2S_MAX_ID) {
|
||||
DBG_I2S_ERR("RtkI2SPinMuxDeInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
switch (pI2SAdapter->DevNum){
|
||||
case I2S0_SEL:
|
||||
/*I2S0 Pin Mux Setting*/
|
||||
//ACTCK_I2C0_CCTRL(OFF);
|
||||
PinCtrl(I2S0, pI2SAdapter->PinMux, OFF);
|
||||
I2S0_MCK_CTRL(OFF);
|
||||
I2S0_PIN_CTRL(OFF);
|
||||
//I2S0_FCTRL(OFF);
|
||||
|
||||
break;
|
||||
case I2S1_SEL:
|
||||
/*I2S1 Pin Mux Setting*/
|
||||
//ACTCK_I2C1_CCTRL(OFF);
|
||||
PinCtrl(I2S1, pI2SAdapter->PinMux, OFF);
|
||||
I2S1_MCK_CTRL(OFF);
|
||||
I2S1_PIN_CTRL(OFF);
|
||||
//I2S1_FCTRL(OFF);
|
||||
break;
|
||||
default:
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
HAL_Status
|
||||
RtkI2SInit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
|
||||
PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL;
|
||||
PHAL_I2S_INIT_DAT pI2SCfg;
|
||||
|
||||
if (pI2SAdapter == 0) {
|
||||
DBG_I2S_ERR("RtkI2SInit: Null Pointer\r\n");
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
if (pI2SAdapter->DevNum > I2S_MAX_ID) {
|
||||
DBG_I2S_ERR("RtkI2SInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
pI2SCfg = pI2SAdapter->pInitDat;
|
||||
|
||||
/*I2S Initialize HAL Operations*/
|
||||
HalI2SOpInit(pHalI2SOP);
|
||||
|
||||
/*I2S Interrupt Initialization*/
|
||||
RtkI2SIrqInit(pI2SAdapter);
|
||||
|
||||
/*I2S Pin Mux Initialization*/
|
||||
RtkI2SPinMuxInit(pI2SAdapter);
|
||||
|
||||
/*I2S Load User Setting*/
|
||||
pI2SCfg->I2SIdx = pI2SAdapter->DevNum;
|
||||
|
||||
/*I2S HAL Initialization*/
|
||||
pHalI2SOP->HalI2SInit(pI2SCfg);
|
||||
|
||||
/*I2S Device Status Update*/
|
||||
pI2SAdapter->DevSts = I2S_STS_INITIALIZED;
|
||||
|
||||
/*I2S Enable Module*/
|
||||
pI2SCfg->I2SEn = I2S_ENABLE;
|
||||
pHalI2SOP->HalI2SEnable(pI2SCfg);
|
||||
|
||||
/*I2S Device Status Update*/
|
||||
pI2SAdapter->DevSts = I2S_STS_IDLE;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
RtkI2SDeInit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
|
||||
PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL;
|
||||
PHAL_I2S_INIT_DAT pI2SCfg;
|
||||
u32 I2Stemp;
|
||||
|
||||
if (pI2SAdapter == 0) {
|
||||
DBG_I2S_ERR("RtkI2SDeInit: Null Pointer\r\n");
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
pI2SCfg = pI2SAdapter->pInitDat;
|
||||
|
||||
/*I2S Disable Module*/
|
||||
pI2SCfg->I2SEn = I2S_DISABLE;
|
||||
pHalI2SOP->HalI2SEnable(pI2SCfg);
|
||||
HalI2SClearAllOwnBit((VOID*)pI2SCfg);
|
||||
|
||||
/*I2C HAL DeInitialization*/
|
||||
//pHalI2SOP->HalI2SDeInit(pI2SCfg);
|
||||
|
||||
/*I2S Interrupt DeInitialization*/
|
||||
RtkI2SIrqDeInit(pI2SAdapter);
|
||||
|
||||
/*I2S Pin Mux DeInitialization*/
|
||||
RtkI2SPinMuxDeInit(pI2SAdapter);
|
||||
|
||||
/*I2S HAL DeInitialization*/
|
||||
pHalI2SOP->HalI2SDeInit(pI2SCfg);
|
||||
|
||||
/*I2S CLK Source Close*/
|
||||
I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) & (~((1<<9) | (1<<10)));
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);
|
||||
|
||||
/*I2S Device Status Update*/
|
||||
pI2SAdapter->DevSts = I2S_STS_UNINITIAL;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
RtkI2SEnable(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
|
||||
PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL;
|
||||
PHAL_I2S_INIT_DAT pI2SCfg;
|
||||
u32 I2Stemp;
|
||||
|
||||
// Enable IP Clock
|
||||
I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) | (1<<9) | (1<<10);
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);
|
||||
ACTCK_I2S_CCTRL(ON);
|
||||
SLPCK_I2S_CCTRL(ON);
|
||||
|
||||
pI2SCfg = pI2SAdapter->pInitDat;
|
||||
pI2SCfg->I2SEn = I2S_ENABLE;
|
||||
pHalI2SOP->HalI2SEnable(pI2SCfg);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
RtkI2SDisable(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
|
||||
PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL;
|
||||
PHAL_I2S_INIT_DAT pI2SCfg;
|
||||
u32 I2Stemp;
|
||||
|
||||
pI2SCfg = pI2SAdapter->pInitDat;
|
||||
pI2SCfg->I2SEn = I2S_DISABLE;
|
||||
pHalI2SOP->HalI2SEnable(pI2SCfg);
|
||||
|
||||
// Gate IP Clock
|
||||
ACTCK_I2S_CCTRL(OFF);
|
||||
SLPCK_I2S_CCTRL(OFF);
|
||||
|
||||
// Close I2S bus clock(WS,SCLK,MCLK). If needs that clock, mark this.
|
||||
I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) & (~((1<<9) | (1<<10)));
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
RtkI2SIoCtrl(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
RtkI2SPowerCtrl(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
RtkI2SLoadDefault(
|
||||
IN VOID *Adapter,
|
||||
IN VOID *Setting
|
||||
)
|
||||
{
|
||||
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Adapter;
|
||||
PHAL_I2S_INIT_DAT pI2SCfg = pI2SAdapter->pInitDat;
|
||||
PHAL_I2S_DEF_SETTING pLoadSetting = (PHAL_I2S_DEF_SETTING)Setting;
|
||||
|
||||
if (pI2SAdapter == 0) {
|
||||
DBG_I2S_ERR("RtkI2SLoadDefault: Null Pointer\r\n");
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
if (pI2SAdapter->pInitDat == NULL) {
|
||||
DBG_I2S_ERR("RtkI2SLoadDefault: pInitDat is NULL!\r\n", pI2SAdapter->DevNum);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
pI2SAdapter->DevSts = pLoadSetting->DevSts;
|
||||
pI2SAdapter->ErrType = 0;
|
||||
pI2SAdapter->TimeOut = 0;
|
||||
|
||||
pI2SCfg->I2SIdx = pI2SAdapter->DevNum;
|
||||
pI2SCfg->I2SEn = I2S_DISABLE;
|
||||
pI2SCfg->I2SMaster = pLoadSetting->I2SMaster;
|
||||
pI2SCfg->I2SWordLen = pLoadSetting->I2SWordLen;
|
||||
pI2SCfg->I2SChNum = pLoadSetting->I2SChNum;
|
||||
pI2SCfg->I2SPageNum = pLoadSetting->I2SPageNum;
|
||||
pI2SCfg->I2SPageSize = pLoadSetting->I2SPageSize;
|
||||
pI2SCfg->I2SRate = pLoadSetting->I2SRate;
|
||||
pI2SCfg->I2STRxAct = pLoadSetting->I2STRxAct;
|
||||
pI2SCfg->I2STxIntrMSK = pLoadSetting->I2STxIntrMSK;
|
||||
pI2SCfg->I2SRxIntrMSK = pLoadSetting->I2SRxIntrMSK;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
VOID HalI2SOpInit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_OP pHalI2SOp = (PHAL_I2S_OP) Data;
|
||||
|
||||
pHalI2SOp->HalI2SInit = HalI2SInitRtl8195a_Patch;
|
||||
pHalI2SOp->HalI2SDeInit = HalI2SDeInitRtl8195a;
|
||||
pHalI2SOp->HalI2STx = HalI2STxRtl8195a;
|
||||
pHalI2SOp->HalI2SRx = HalI2SRxRtl8195a;
|
||||
pHalI2SOp->HalI2SEnable = HalI2SEnableRtl8195a;
|
||||
pHalI2SOp->HalI2SIntrCtrl = HalI2SIntrCtrlRtl8195a;
|
||||
pHalI2SOp->HalI2SReadReg = HalI2SReadRegRtl8195a;
|
||||
pHalI2SOp->HalI2SSetRate = HalI2SSetRateRtl8195a;
|
||||
pHalI2SOp->HalI2SSetWordLen = HalI2SSetWordLenRtl8195a;
|
||||
pHalI2SOp->HalI2SSetChNum = HalI2SSetChNumRtl8195a;
|
||||
pHalI2SOp->HalI2SSetPageNum = HalI2SSetPageNumRtl8195a;
|
||||
pHalI2SOp->HalI2SSetPageSize = HalI2SSetPageSizeRtl8195a;
|
||||
pHalI2SOp->HalI2SClrIntr = HalI2SClrIntrRtl8195a;
|
||||
pHalI2SOp->HalI2SClrAllIntr = HalI2SClrAllIntrRtl8195a;
|
||||
pHalI2SOp->HalI2SDMACtrl = HalI2SDMACtrlRtl8195a;
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
HalI2SInit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
HAL_Status ret;
|
||||
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
|
||||
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
REG_POWER_STATE I2sPwrState;
|
||||
#endif
|
||||
|
||||
ret = RtkI2SInit(Data);
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
if(ret == HAL_OK) {
|
||||
// To register a new peripheral device power state
|
||||
I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum;
|
||||
I2sPwrState.PwrState = ACT;
|
||||
RegPowerState(I2sPwrState);
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
HalI2SDeInit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
REG_POWER_STATE I2sPwrState;
|
||||
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
|
||||
u8 HwState;
|
||||
|
||||
I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum;
|
||||
QueryRegPwrState(I2sPwrState.FuncIdx, &(I2sPwrState.PwrState), &HwState);
|
||||
|
||||
// if the power state isn't ACT, then switch the power state back to ACT first
|
||||
if ((I2sPwrState.PwrState != ACT) && (I2sPwrState.PwrState != INACT)) {
|
||||
HalI2SEnable(Data);
|
||||
QueryRegPwrState(I2sPwrState.FuncIdx, &(I2sPwrState.PwrState), &HwState);
|
||||
}
|
||||
|
||||
if (I2sPwrState.PwrState == ACT) {
|
||||
I2sPwrState.PwrState = INACT;
|
||||
RegPowerState(I2sPwrState);
|
||||
}
|
||||
#endif
|
||||
|
||||
RtkI2SDeInit(Data);
|
||||
|
||||
}
|
||||
|
||||
|
||||
HAL_Status
|
||||
HalI2SDisable(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
HAL_Status ret;
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
REG_POWER_STATE I2sPwrState;
|
||||
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
|
||||
#endif
|
||||
|
||||
ret = RtkI2SDisable(Data);
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
if (ret == HAL_OK) {
|
||||
I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum;
|
||||
I2sPwrState.PwrState = SLPCG;
|
||||
RegPowerState(I2sPwrState);
|
||||
}
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
HalI2SEnable(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
HAL_Status ret;
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
REG_POWER_STATE I2sPwrState;
|
||||
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
|
||||
#endif
|
||||
|
||||
ret = RtkI2SEnable(Data);
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
if (ret == HAL_OK) {
|
||||
I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum;
|
||||
I2sPwrState.PwrState = ACT;
|
||||
RegPowerState(I2sPwrState);
|
||||
}
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
42
lib/fwlib/src/hal_mii.c
Normal file
42
lib/fwlib/src/hal_mii.c
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "hal_mii.h"
|
||||
|
||||
VOID
|
||||
HalMiiOpInit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_MII_OP pHalMiiOp = (PHAL_MII_OP) Data;
|
||||
|
||||
pHalMiiOp->HalMiiGmacInit = HalMiiGmacInitRtl8195a;
|
||||
pHalMiiOp->HalMiiInit = HalMiiInitRtl8195a;
|
||||
pHalMiiOp->HalMiiGmacReset = HalMiiGmacResetRtl8195a;
|
||||
pHalMiiOp->HalMiiGmacEnablePhyMode = HalMiiGmacEnablePhyModeRtl8195a;
|
||||
pHalMiiOp->HalMiiGmacXmit = HalMiiGmacXmitRtl8195a;
|
||||
pHalMiiOp->HalMiiGmacCleanTxRing = HalMiiGmacCleanTxRingRtl8195a;
|
||||
pHalMiiOp->HalMiiGmacFillTxInfo = HalMiiGmacFillTxInfoRtl8195a;
|
||||
pHalMiiOp->HalMiiGmacFillRxInfo = HalMiiGmacFillRxInfoRtl8195a;
|
||||
pHalMiiOp->HalMiiGmacTx = HalMiiGmacTxRtl8195a;
|
||||
pHalMiiOp->HalMiiGmacRx = HalMiiGmacRxRtl8195a;
|
||||
pHalMiiOp->HalMiiGmacSetDefaultEthIoCmd = HalMiiGmacSetDefaultEthIoCmdRtl8195a;
|
||||
pHalMiiOp->HalMiiGmacInitIrq = HalMiiGmacInitIrqRtl8195a;
|
||||
pHalMiiOp->HalMiiGmacGetInterruptStatus = HalMiiGmacGetInterruptStatusRtl8195a;
|
||||
pHalMiiOp->HalMiiGmacClearInterruptStatus = HalMiiGmacClearInterruptStatusRtl8195a;
|
||||
#if 0
|
||||
pHalMiiOp-> = Rtl8195a;
|
||||
pHalMiiOp-> = Rtl8195a;
|
||||
pHalMiiOp-> = Rtl8195a;
|
||||
pHalMiiOp-> = Rtl8195a;
|
||||
pHalMiiOp-> = Rtl8195a;
|
||||
#endif
|
||||
}
|
||||
|
||||
20
lib/fwlib/src/hal_nfc.c
Normal file
20
lib/fwlib/src/hal_nfc.c
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "hal_nfc.h"
|
||||
|
||||
VOID HalNFCOpInit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
28
lib/fwlib/src/hal_pcm.c
Normal file
28
lib/fwlib/src/hal_pcm.c
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "hal_pcm.h"
|
||||
|
||||
VOID HalPcmOpInit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_PCM_OP pHalPcmOp = (PHAL_PCM_OP) Data;
|
||||
|
||||
pHalPcmOp->HalPcmOnOff = HalPcmOnOffRtl8195a;
|
||||
pHalPcmOp->HalPcmInit = HalPcmInitRtl8195a;
|
||||
pHalPcmOp->HalPcmSetting = HalPcmSettingRtl8195a;
|
||||
pHalPcmOp->HalPcmEn = HalPcmEnRtl8195a;
|
||||
pHalPcmOp->HalPcmIsrEnAndDis= HalPcmIsrEnAndDisRtl8195a;
|
||||
pHalPcmOp->HalPcmDumpReg= HalPcmDumpRegRtl8195a;
|
||||
pHalPcmOp->HalPcm= HalPcmRtl8195a;
|
||||
}
|
||||
|
||||
|
||||
131
lib/fwlib/src/hal_pwm.c
Normal file
131
lib/fwlib/src/hal_pwm.c
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
|
||||
#ifdef CONFIG_PWM_EN
|
||||
#include "hal_pwm.h"
|
||||
#include "hal_timer.h"
|
||||
|
||||
HAL_PWM_ADAPTER PWMPin[MAX_PWM_CTRL_PIN];
|
||||
const u8 PWMTimerIdx[MAX_PWM_CTRL_PIN]= {3,4,5,6}; // the G-timer ID used for PWM pin 0~3
|
||||
|
||||
/**
|
||||
* @brief Initializes and enable a PWM control pin.
|
||||
*
|
||||
* @param pwm_id: the PWM pin index
|
||||
* @param sel: pin mux selection
|
||||
*
|
||||
* @retval HAL_Status
|
||||
*/
|
||||
HAL_Status
|
||||
HAL_Pwm_Init(
|
||||
u32 pwm_id,
|
||||
u32 sel
|
||||
)
|
||||
{
|
||||
HAL_PWM_ADAPTER *pPwmAdapt;
|
||||
u32 timer_id;
|
||||
|
||||
DBG_PWM_INFO("%s: Init PWM for PWM %d, Sel %d\n", __FUNCTION__, pwm_id, sel);
|
||||
|
||||
if ((pwm_id >= MAX_PWM_CTRL_PIN) || (sel > 3)) {
|
||||
DBG_PWM_ERR ("HAL_Pwm_Init: Invalid PWM index(%d), sel(%d)\n", pwm_id, sel);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
pPwmAdapt = &PWMPin[pwm_id];
|
||||
pPwmAdapt->pwm_id = pwm_id;
|
||||
pPwmAdapt->sel = sel;
|
||||
timer_id = PWMTimerIdx[pwm_id];
|
||||
pPwmAdapt->gtimer_id = timer_id;
|
||||
|
||||
return HAL_Pwm_Init_8195a (pPwmAdapt);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable a PWM control pin.
|
||||
*
|
||||
* @param pwm_id: the PWM pin index
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void
|
||||
HAL_Pwm_Enable(
|
||||
u32 pwm_id
|
||||
)
|
||||
{
|
||||
HAL_PWM_ADAPTER *pPwmAdapt;
|
||||
|
||||
if (pwm_id >= MAX_PWM_CTRL_PIN) {
|
||||
DBG_PWM_ERR ("HAL_Pwm_Enable: Invalid PWM index(%d)\n", pwm_id);
|
||||
return;
|
||||
}
|
||||
pPwmAdapt = &PWMPin[pwm_id];
|
||||
|
||||
HAL_Pwm_Enable_8195a(pPwmAdapt);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable a PWM control pin.
|
||||
*
|
||||
* @param pwm_id: the PWM pin index
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void
|
||||
HAL_Pwm_Disable(
|
||||
u32 pwm_id
|
||||
)
|
||||
{
|
||||
HAL_PWM_ADAPTER *pPwmAdapt;
|
||||
|
||||
if (pwm_id >= MAX_PWM_CTRL_PIN) {
|
||||
DBG_PWM_ERR ("HAL_Pwm_Disable: Invalid PWM index(%d)\n", pwm_id);
|
||||
return;
|
||||
}
|
||||
pPwmAdapt = &PWMPin[pwm_id];
|
||||
|
||||
HAL_Pwm_Disable_8195a(pPwmAdapt);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the duty ratio of the PWM pin.
|
||||
*
|
||||
* @param pwm_id: the PWM pin index
|
||||
* @param period: the period time, in micro-second.
|
||||
* @param pulse_width: the pulse width time, in micro-second.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void
|
||||
HAL_Pwm_SetDuty(
|
||||
u32 pwm_id,
|
||||
u32 period,
|
||||
u32 pulse_width
|
||||
)
|
||||
{
|
||||
HAL_PWM_ADAPTER *pPwmAdapt;
|
||||
|
||||
if (pwm_id >= MAX_PWM_CTRL_PIN) {
|
||||
DBG_PWM_ERR ("HAL_Pwm_SetDuty: Invalid PWM index(%d)\n", pwm_id);
|
||||
return;
|
||||
}
|
||||
|
||||
// DBG_PWM_INFO("%s: Period%d Pulse%d\n", __FUNCTION__, period, pulse_width);
|
||||
pPwmAdapt = &PWMPin[pwm_id];
|
||||
|
||||
HAL_Pwm_SetDuty_8195a(pPwmAdapt, period, pulse_width);
|
||||
}
|
||||
|
||||
|
||||
#endif // end of "#ifdef CONFIG_PWM_EN"
|
||||
971
lib/fwlib/src/hal_sdr_controller.c
Normal file
971
lib/fwlib/src/hal_sdr_controller.c
Normal file
|
|
@ -0,0 +1,971 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
#include "rtl8195a.h"
|
||||
#include "hal_sdr_controller.h"
|
||||
#include "rtl8195a_sdr.h"
|
||||
#if 0
|
||||
#define HAL_SDR_WRITE32(addr, value32) HAL_WRITE32(SDR_CTRL_BASE, addr, value32)
|
||||
#define HAL_SDR_WRITE16(addr, value16) HAL_WRITE16(SDR_CTRL_BASE, addr, value16)
|
||||
#define HAL_SDR_WRITE8(addr, value8) HAL_WRITE8(SDR_CTRL_BASE, addr, value8)
|
||||
#define HAL_SDR_READ32(addr) HAL_READ32(SDR_CTRL_BASE, addr)
|
||||
#define HAL_SDR_READ16(addr) HAL_READ16(SDR_CTRL_BASE, addr)
|
||||
#define HAL_SDR_READ8(addr) HAL_READ8(SDR_CTRL_BASE, addr)
|
||||
|
||||
#define HAL_SDRAM_WRITE32(addr, value32) HAL_WRITE32(SDR_SDRAM_BASE, addr, value32)
|
||||
#define HAL_SDRAM_WRITE16(addr, value16) HAL_WRITE16(SDR_SDRAM_BASE, addr, value16)
|
||||
#define HAL_SDRAM_WRITE8(addr, value8) HAL_WRITE8(SDR_SDRAM_BASE, addr, value8)
|
||||
#define HAL_SDRAM_READ32(addr) HAL_READ32(SDR_SDRAM_BASE, addr)
|
||||
#define HAL_SDRAM_READ16(addr) HAL_READ16(SDR_SDRAM_BASE, addr)
|
||||
#define HAL_SDRAM_READ8(addr) HAL_READ8(SDR_SDRAM_BASE, addr)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
HAL_CUT_B_RAM_DATA_SECTION
|
||||
DRAM_INFO SdrDramDev = {
|
||||
DRAM_INFO_TYPE,
|
||||
DRAM_INFO_COL_ADDR_WTH,
|
||||
DRAM_INFO_BANK_SZ,
|
||||
DRAM_INFO_DQ_WTH
|
||||
};
|
||||
|
||||
|
||||
HAL_CUT_B_RAM_DATA_SECTION
|
||||
DRAM_MODE_REG_INFO SdrDramModeReg = {
|
||||
BST_LEN_4,
|
||||
SENQUENTIAL,
|
||||
0x3, // Mode0Cas: 3
|
||||
0x0, // Mode0Wr
|
||||
0, // Mode1DllEnN
|
||||
0, // Mode1AllLat
|
||||
0 // Mode2Cwl
|
||||
};
|
||||
|
||||
HAL_CUT_B_RAM_DATA_SECTION
|
||||
DRAM_TIMING_INFO SdrDramTiming = {
|
||||
DRAM_TIMING_TRFC, // TrfcPs;
|
||||
DRAM_TIMING_TREFI, // TrefiPs;
|
||||
DRAM_TIMING_TWRMAXTCK, // WrMaxTck;
|
||||
DRAM_TIMING_TRCD, // TrcdPs;
|
||||
DRAM_TIMING_TRP, // TrpPs;
|
||||
DRAM_TIMING_TRAS, // TrasPs;
|
||||
DRAM_TIMING_TRRD, // TrrdTck;
|
||||
DRAM_TIMING_TWR, // TwrPs;
|
||||
DRAM_TIMING_TWTR, // TwtrTck;
|
||||
//13090, // TrtpPs;
|
||||
DRAM_TIMING_TMRD, // TmrdTck;
|
||||
DRAM_TIMING_TRTP, // TrtpTck;
|
||||
DRAM_TIMING_TCCD, // TccdTck;
|
||||
DRAM_TIMING_TRC // TrcPs;
|
||||
};
|
||||
|
||||
HAL_CUT_B_RAM_DATA_SECTION
|
||||
DRAM_DEVICE_INFO SdrDramInfo = {
|
||||
&SdrDramDev,
|
||||
&SdrDramModeReg,
|
||||
&SdrDramTiming,
|
||||
DRAM_TIMING_TCK,
|
||||
DFI_RATIO_1
|
||||
};
|
||||
|
||||
|
||||
#define FPGA
|
||||
#define FPGA_TEMP
|
||||
#define SDR_CLK_DLY_CTRL 0x40000300
|
||||
#define MIN_RD_PIPE 0x0
|
||||
#define MAX_RD_PIPE 0x7
|
||||
|
||||
#define SUPPORT_DRAM_KED
|
||||
|
||||
|
||||
#ifdef FPGA
|
||||
#ifdef FPGA_TEMP
|
||||
#define MAX_TAP_DLY 0xC
|
||||
#else
|
||||
#define MAX_TAP_DLY 0x7F
|
||||
#define SPEC_MAX_TAP 0xFF
|
||||
#endif
|
||||
#else
|
||||
#define MAX_TAP_DLY 99 // 0~99
|
||||
#define SPEC_MAX_TAP 99
|
||||
#define WINDOW_COMBIN // combine window [0~a] and [b~99] (for asic mode)
|
||||
#endif
|
||||
|
||||
#define TAP_DLY 0x1
|
||||
#define REC_NUM 512
|
||||
|
||||
|
||||
u32 SdrControllerInit(VOID);
|
||||
VOID DramInit(DRAM_DEVICE_INFO *);
|
||||
s32 MemTest(u32 loop_cnt);
|
||||
u32 SdrCalibration(VOID);
|
||||
u32 Sdr_Rand2(VOID);
|
||||
|
||||
//3 Note: stack overfloat if the arrary is declared in the task
|
||||
HAL_CUT_B_RAM_DATA_SECTION
|
||||
u32 AvaWds[2][REC_NUM];
|
||||
|
||||
HAL_CUT_B_RAM_DATA_SECTION
|
||||
unsigned int rand_x = 123456789;
|
||||
|
||||
#ifdef CONFIG_SDR_EN
|
||||
|
||||
#ifdef CONFIG_SDR_VERIFY
|
||||
enum{
|
||||
LLT,
|
||||
TXRPT,
|
||||
RXBUFF,
|
||||
TXBUFF,
|
||||
};
|
||||
#define REPORT_OFFSET 0x8000
|
||||
#define RAMASK_OFFSET 0x8800
|
||||
#define LLT_H_ADDR 0x650
|
||||
#define TXREPORT_H_ADDR 0x660
|
||||
#define RXBUFF_H_ADDR 0x670
|
||||
#define TXBUFF_H_ADDR 0x680
|
||||
|
||||
#define REG_PKTBUF_DBG_CTRL_8723B 0x0140
|
||||
|
||||
int
|
||||
rt_rpt_h_addr(u8 rpt)
|
||||
{
|
||||
u32 r_val, offset;
|
||||
|
||||
if (rpt == LLT){
|
||||
offset = LLT_H_ADDR;
|
||||
}
|
||||
else if (rpt == TXRPT){
|
||||
offset = TXREPORT_H_ADDR;
|
||||
}
|
||||
else if (rpt == RXBUFF){
|
||||
offset = RXBUFF_H_ADDR;
|
||||
}
|
||||
else if (rpt == TXBUFF){
|
||||
offset = TXBUFF_H_ADDR;
|
||||
}
|
||||
else {
|
||||
}
|
||||
|
||||
r_val = ((HAL_READ32(WIFI_REG_BASE, REG_PKTBUF_DBG_CTRL_8723B)&0xFFFFF000)|offset);
|
||||
HAL_WRITE32(WIFI_REG_BASE, REG_PKTBUF_DBG_CTRL_8723B, r_val);
|
||||
}
|
||||
|
||||
|
||||
|
||||
int
|
||||
rt_txrpt_read32(u8 macid, u8 offset)
|
||||
{
|
||||
u32 r_val;
|
||||
|
||||
rt_rpt_h_addr(TXRPT);
|
||||
r_val = HAL_READ32(WIFI_REG_BASE, (REPORT_OFFSET + macid*4 + offset));
|
||||
|
||||
return r_val;
|
||||
}
|
||||
|
||||
int
|
||||
rt_txrpt_read16(u8 macid, u8 offset)
|
||||
{
|
||||
u16 r_val;
|
||||
|
||||
rt_rpt_h_addr(TXRPT);
|
||||
r_val = HAL_READ16(WIFI_REG_BASE, (REPORT_OFFSET + macid*8 + offset));
|
||||
|
||||
return r_val;
|
||||
}
|
||||
|
||||
int
|
||||
rt_txrpt_read8(u8 macid, u8 offset)
|
||||
{
|
||||
u8 r_val;
|
||||
|
||||
rt_rpt_h_addr(TXRPT);
|
||||
r_val = HAL_READ8(WIFI_REG_BASE, (REPORT_OFFSET + macid*16 + offset));
|
||||
|
||||
return r_val;
|
||||
}
|
||||
|
||||
int
|
||||
rt_txrpt_read_1b(u8 macid, u8 offset, u8 bit_offset)
|
||||
{
|
||||
u8 r_val = ((rt_txrpt_read8(macid, offset) & BIT(bit_offset))?1:0);
|
||||
|
||||
return r_val;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
rt_txrpt_write32(u8 macid, u8 offset, u32 val)
|
||||
{
|
||||
rt_rpt_h_addr(TXRPT);
|
||||
HAL_WRITE32(WIFI_REG_BASE, (REPORT_OFFSET + macid*4 + offset), val);
|
||||
}
|
||||
|
||||
int
|
||||
rt_txrpt_write16(u8 macid, u8 offset, u16 val)
|
||||
{
|
||||
rt_rpt_h_addr(TXRPT);
|
||||
HAL_WRITE16(WIFI_REG_BASE, (REPORT_OFFSET + macid*8 + offset), val);
|
||||
}
|
||||
|
||||
int
|
||||
rt_txrpt_write8(u8 macid, u8 offset, u8 val)
|
||||
{
|
||||
rt_rpt_h_addr(TXRPT);
|
||||
DBG_8195A("Write addr %x %x\n", (REPORT_OFFSET + macid*16 + offset), val);
|
||||
HAL_WRITE8(WIFI_REG_BASE, (REPORT_OFFSET + macid*16 + offset), val);
|
||||
}
|
||||
|
||||
int
|
||||
rt_txrpt_write_1b(u8 macid, u8 offset, u8 bit_offset, u8 val)
|
||||
{
|
||||
u8 r_val = rt_txrpt_read8(macid, offset);
|
||||
|
||||
if (val){
|
||||
r_val |= BIT(bit_offset);
|
||||
}
|
||||
else {
|
||||
r_val &= (~BIT(bit_offset));
|
||||
}
|
||||
|
||||
HAL_WRITE8(WIFI_REG_BASE, (REPORT_OFFSET + macid*16 + offset), r_val);
|
||||
}
|
||||
|
||||
|
||||
u8
|
||||
ReadTxrptsdr8(
|
||||
IN u8 Macid,
|
||||
IN u8 Offset)
|
||||
{
|
||||
u8 r_val;
|
||||
|
||||
r_val = rt_txrpt_read8(Macid, Offset);
|
||||
return r_val;
|
||||
}
|
||||
|
||||
VOID
|
||||
WriteTxrptsdr8(
|
||||
IN u8 Macid,
|
||||
IN u8 Offset,
|
||||
IN u8 Val)
|
||||
{
|
||||
rt_txrpt_write8(Macid, Offset, Val);
|
||||
}
|
||||
|
||||
VOID
|
||||
SdrTestApp(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
u32 *Cmd =(u32*)Data;
|
||||
u32 Loop, LoopIndex, Value32, Addr, Loop1, LoopIndex1;
|
||||
|
||||
switch (Cmd[0]) {
|
||||
case 1:
|
||||
DBG_8195A("Initial SDR\n");
|
||||
|
||||
//1 "SdrControllerInit" is located in Image1, so we shouldn't call it in Image2
|
||||
if (!SdrControllerInit()) {
|
||||
DBG_8195A("SDR Calibartion Fail!!!!\n");
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
Loop = Cmd[1];
|
||||
Loop1 = Cmd[2];
|
||||
DBG_8195A("Verify SDR: Loop = 0x%08x Loop1 = 0x%08x\n",Loop, Loop1);
|
||||
|
||||
for (LoopIndex1=0; LoopIndex1 < Loop1; LoopIndex1++) {
|
||||
|
||||
for (LoopIndex=0; LoopIndex < Loop; LoopIndex++) {
|
||||
Value32 = Rand2();
|
||||
Addr = Rand2();
|
||||
Addr &= 0x1FFFFF;
|
||||
Addr &= (~0x3);
|
||||
|
||||
if (!(LoopIndex & 0xFFFFF)) {
|
||||
DBG_8195A("Alive: LOOP = 0x%08x, LOOP = 0x%08x\n",LoopIndex1, LoopIndex);
|
||||
}
|
||||
|
||||
// DBG_8195A("Value: 0x%x; Addr: 0x%x\n", Value32, Addr+SDR_SDRAM_BASE);
|
||||
HAL_SDRAM_WRITE32(Addr, Value32);
|
||||
|
||||
if (Value32 != HAL_SDRAM_READ32(Addr)) {
|
||||
DBG_8195A("Loop:%d; Addr: 0x%08x => CheckData error: W: 0x%08x /R:0x%x\n"
|
||||
,LoopIndex
|
||||
,Addr
|
||||
,Value32
|
||||
,HAL_SDRAM_READ32(Addr));
|
||||
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO2, HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSTBY_INFO2)+1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
DBG_8195A("Verify SDR Success\n");
|
||||
break;
|
||||
|
||||
case 3:
|
||||
DBG_8195A("WL read RPT MACID %x\n", Cmd[1]);
|
||||
{
|
||||
u8 i =0;
|
||||
for(i=0;i<16;i++) {
|
||||
DBG_8195A("WL RPT offset %d = %x\n", i, ReadTxrptsdr8(Cmd[1],i));
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
DBG_8195A("WL write RPT MACID %x\n", Cmd[1]);
|
||||
{
|
||||
u8 i =0;
|
||||
for(i=0;i<16;i++) {
|
||||
WriteTxrptsdr8(Cmd[1],i,Cmd[2]);
|
||||
//DBG_8195A("WL RPT offset %d = %x\n", i, ReadTxrptsdr8(Cmd[1],i));
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
HAL_SDRC_TEXT_SECTION
|
||||
VOID
|
||||
SdrCtrlInit(
|
||||
VOID
|
||||
){
|
||||
HAL_WRITE32(0x40000000, 0x40,
|
||||
((HAL_READ32(0x40000000, 0x40)&0xfffff)|0xe00000));
|
||||
LDO25M_CTRL(ON);
|
||||
}
|
||||
|
||||
HAL_SDRC_TEXT_SECTION
|
||||
u32
|
||||
SdrControllerInit(
|
||||
VOID
|
||||
)
|
||||
{
|
||||
DBG_8195A("SDR Controller Init\n");
|
||||
|
||||
HAL_WRITE32(0x40000000, 0x40,
|
||||
((HAL_READ32(0x40000000, 0x40)&0xfffff)|0x300000));
|
||||
|
||||
SRAM_MUX_CFG(0x2);
|
||||
|
||||
SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE);
|
||||
|
||||
HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4,0);
|
||||
|
||||
ACTCK_SDR_CCTRL(ON);
|
||||
|
||||
SLPCK_SDR_CCTRL(ON);
|
||||
|
||||
PinCtrl(SDR, 0, ON);
|
||||
|
||||
HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4,0);
|
||||
|
||||
MEM_CTRL_FCTRL(ON);
|
||||
|
||||
HalDelayUs(3000);
|
||||
|
||||
// sdr initialization
|
||||
DramInit(&SdrDramInfo);
|
||||
|
||||
// sdr calibration
|
||||
if(!SdrCalibration()) {
|
||||
return 0;
|
||||
}
|
||||
else {
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
HAL_SDRC_TEXT_SECTION
|
||||
VOID
|
||||
DramInit (
|
||||
IN DRAM_DEVICE_INFO *DramInfo
|
||||
)
|
||||
{
|
||||
u32 CsBstLen = 0; // 0:bst_4, 1:bst_8
|
||||
u32 CasWr = 0;//, CasWrT; // cas write latency
|
||||
u32 CasRd = 0, CasRdT = 0, CrlSrt = 0; // cas read latency
|
||||
u32 AddLat;
|
||||
u32 DramEmr2 = 0, DramMr0 = 0;
|
||||
u32 CrTwr, DramMaxWr, DramWr;
|
||||
u32 CrTrtw = 0, CrTrtwT = 0;
|
||||
u32 DrmaPeriod;
|
||||
DRAM_TYPE DdrType;
|
||||
DRAM_DQ_WIDTH DqWidth;
|
||||
DRAM_COLADDR_WTH Page;
|
||||
u32 DfiRate;
|
||||
volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
|
||||
ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
|
||||
ms_ctrl_0_map = ms_ctrl_0_map;
|
||||
|
||||
DfiRate = 1 << (u32) (DramInfo->DfiRate);
|
||||
DrmaPeriod = (DramInfo->DdrPeriodPs)*(DfiRate); // according DFI_RATE to setting
|
||||
|
||||
// In PHY, write latency == 3
|
||||
DramMaxWr= (DramInfo->Timing->WrMaxTck)/(DfiRate) +1;
|
||||
DramWr = ((DramInfo->Timing->TwrPs) / DrmaPeriod)+1;
|
||||
CrTwr = ((DramInfo->Timing->TwrPs) / DrmaPeriod) + 3;
|
||||
|
||||
if (CrTwr < DramMaxWr) {
|
||||
CrTwr = CrTwr;
|
||||
}
|
||||
else {
|
||||
CrTwr = DramMaxWr;
|
||||
}
|
||||
|
||||
if ((DramInfo->Dev->DeviceType) == DRAM_DDR_2) {
|
||||
DdrType = DRAM_DDR_2;
|
||||
if (DramInfo->ModeReg->BstLen == BST_LEN_4) {
|
||||
CsBstLen = 0; //bst_4
|
||||
CrTrtwT = 2+2; //4/2+2
|
||||
DramMr0 = 0x2;
|
||||
}
|
||||
else { // BST_LEN_8
|
||||
CsBstLen = 1; // bst_8
|
||||
CrTrtwT = 4+2; // 8/2+2
|
||||
DramMr0 = 0x3;
|
||||
}
|
||||
CasRd = DramInfo->ModeReg->Mode0Cas;
|
||||
AddLat = DramInfo->ModeReg ->Mode1AllLat;
|
||||
CasWr = CasRd + AddLat -1;
|
||||
DramEmr2 = 0;
|
||||
|
||||
DramMr0 =(((DramWr%6)-1) << (PCTL_MR_OP_BFO+1)) | // write_recovery
|
||||
(0 << PCTL_MR_OP_BFO ) | // dll
|
||||
(DramInfo->ModeReg->Mode0Cas << PCTL_MR_CAS_BFO ) |
|
||||
(DramInfo->ModeReg->BstType << PCTL_MR_BT_BFO ) |
|
||||
DramMr0;
|
||||
}
|
||||
else if ((DramInfo->Dev->DeviceType) == DRAM_DDR_3) {
|
||||
DdrType = DRAM_DDR_3;
|
||||
if (DramInfo->ModeReg->BstLen == BST_LEN_4) {
|
||||
CsBstLen = 0; //bst_4
|
||||
DramMr0 = 0x2;
|
||||
}
|
||||
else { // BST_LEN_8
|
||||
CsBstLen = 1; // bst_8
|
||||
DramMr0 = 0x0;
|
||||
}
|
||||
|
||||
CrlSrt = (DramInfo->ModeReg->Mode0Cas >> 1);
|
||||
if (((DramInfo->ModeReg->Mode0Cas) & 0x1) ) {
|
||||
CasRdT = CrlSrt+ 12;
|
||||
}
|
||||
else {
|
||||
CasRdT = CrlSrt+ 4;
|
||||
}
|
||||
|
||||
if (DramInfo->ModeReg->Mode1AllLat == 1) { // CL-1
|
||||
AddLat = CasRd -1;
|
||||
}
|
||||
else if (DramInfo->ModeReg->Mode1AllLat == 2){ // CL-2
|
||||
AddLat = CasRd -2;
|
||||
}
|
||||
else {
|
||||
AddLat = 0;
|
||||
}
|
||||
|
||||
CasRd = CasRdT + AddLat;
|
||||
|
||||
CasWr = DramInfo->ModeReg->Mode2Cwl + 5 + AddLat;
|
||||
|
||||
DramEmr2 = DramInfo->ModeReg->Mode2Cwl << 3;
|
||||
|
||||
if (DramWr == 16) {
|
||||
DramWr = 0;
|
||||
}
|
||||
else if (DramWr <= 9) { // 5< wr <= 9
|
||||
DramWr = DramWr - 4;
|
||||
}
|
||||
else {
|
||||
DramWr = (DramWr + 1) / 2;
|
||||
}
|
||||
|
||||
DramMr0 =(DramWr << (PCTL_MR_OP_BFO+1) ) | // write_recovery
|
||||
(0 << PCTL_MR_OP_BFO ) | // dll
|
||||
((DramInfo->ModeReg->Mode0Cas >>1 ) << PCTL_MR_CAS_BFO ) |
|
||||
(DramInfo->ModeReg->BstType << PCTL_MR_BT_BFO ) |
|
||||
((DramInfo->ModeReg->Mode0Cas & 0x1) << 2 ) |
|
||||
DramMr0;
|
||||
|
||||
CrTrtwT = (CasRdT + 6) - CasWr;
|
||||
|
||||
} // ddr2/ddr3
|
||||
else if ((DramInfo->Dev->DeviceType) == DRAM_SDR) {
|
||||
DdrType = DRAM_SDR;
|
||||
if (DramInfo->ModeReg->BstLen == BST_LEN_4) {
|
||||
DramMr0 = 2; // bst_4
|
||||
CsBstLen = 0; //bst_4
|
||||
CasRd = 0x2;
|
||||
}
|
||||
else { // BST_LEN_8
|
||||
DramMr0 = 3; // bst_8
|
||||
CsBstLen = 1; // bst_8
|
||||
CasRd = 0x3;
|
||||
}
|
||||
|
||||
CasWr = 0;
|
||||
|
||||
DramMr0 =(CasRd << PCTL_MR_CAS_BFO) |
|
||||
(DramInfo->ModeReg->BstType << PCTL_MR_BT_BFO ) |
|
||||
DramMr0;
|
||||
|
||||
CrTrtwT = 0; // tic: CasRd + rd_rtw + rd_pipe
|
||||
} // SDR
|
||||
|
||||
|
||||
// countting tRTW
|
||||
if ((CrTrtwT & 0x1)) {
|
||||
CrTrtw = (CrTrtwT+1) /(DfiRate);
|
||||
}
|
||||
else {
|
||||
CrTrtw = CrTrtwT /(DfiRate);
|
||||
}
|
||||
|
||||
DqWidth = (DramInfo->Dev->DqWidth);
|
||||
Page = DramInfo->Dev->ColAddrWth +1; // DQ16 -> memory:byte_unit *2
|
||||
if (DqWidth == DRAM_DQ_32) { // paralle dq_16 => Page + 1
|
||||
Page = Page +1;
|
||||
}
|
||||
#if 1
|
||||
|
||||
// WRAP_MISC setting
|
||||
HAL_SDR_WRITE32(REG_SDR_MISC,(
|
||||
(Page << WRAP_MISC_PAGE_SIZE_BFO) |
|
||||
(DramInfo->Dev->Bank << WRAP_MISC_BANK_SIZE_BFO) |
|
||||
(CsBstLen << WRAP_MISC_BST_SIZE_BFO ) |
|
||||
(DqWidth << WRAP_MISC_DDR_PARAL_BFO)
|
||||
));
|
||||
// PCTL setting
|
||||
HAL_SDR_WRITE32(REG_SDR_DCR,(
|
||||
(0x2 << PCTL_DCR_DFI_RATE_BFO) |
|
||||
(DqWidth << PCTL_DCR_DQ32_BFO ) |
|
||||
(DdrType << PCTL_DCR_DDR3_BFO )
|
||||
));
|
||||
|
||||
HAL_SDR_WRITE32(REG_SDR_IOCR,(
|
||||
((CasRd -4)/(DfiRate) << PCTL_IOCR_TPHY_RD_EN_BFO ) |
|
||||
(0 << PCTL_IOCR_TPHY_WL_BFO ) |
|
||||
(((CasWr -3)/(DfiRate)) << PCTL_IOCR_TPHY_WD_BFO ) |
|
||||
(0 << PCTL_IOCR_RD_PIPE_BFO )
|
||||
));
|
||||
|
||||
if ((DramInfo->Dev->DeviceType) != SDR) { // DDR2/3
|
||||
HAL_SDR_WRITE32(REG_SDR_EMR2,DramEmr2);
|
||||
HAL_SDR_WRITE32(REG_SDR_EMR1,(
|
||||
(1 << 2 ) | //RTT
|
||||
(1 << 1 ) | //D.I.C
|
||||
(DramInfo->ModeReg->Mode1DllEnN )
|
||||
));
|
||||
} // DDR2/3
|
||||
|
||||
HAL_SDR_WRITE32(REG_SDR_MR,DramMr0);
|
||||
|
||||
HAL_SDR_WRITE32(REG_SDR_DRR, (
|
||||
(0 << PCTL_DRR_REF_DIS_BFO) |
|
||||
(9 << PCTL_DRR_REF_NUM_BFO) |
|
||||
((((DramInfo->Timing->TrefiPs)/DrmaPeriod)+1) << PCTL_DRR_TREF_BFO ) |
|
||||
((((DramInfo->Timing->TrfcPs)/DrmaPeriod)+1) << PCTL_DRR_TRFC_BFO )
|
||||
));
|
||||
|
||||
HAL_SDR_WRITE32(REG_SDR_TPR0,(
|
||||
((((DramInfo->Timing->TrtpTck)/DfiRate)+1) << PCTL_TPR0_TRTP_BFO) |
|
||||
(CrTwr << PCTL_TPR0_TWR_BFO ) |
|
||||
((((DramInfo->Timing->TrasPs)/DrmaPeriod)+1) << PCTL_TPR0_TRAS_BFO) |
|
||||
((((DramInfo->Timing->TrpPs)/DrmaPeriod)+1) << PCTL_TPR0_TRP_BFO )
|
||||
));
|
||||
|
||||
HAL_SDR_WRITE32(REG_SDR_TPR1, (
|
||||
(CrTrtw << PCTL_TPR1_TRTW_BFO) |
|
||||
((((DramInfo->Timing->TwtrTck)/DfiRate)+3) << PCTL_TPR1_TWTR_BFO) |
|
||||
((((DramInfo->Timing->TccdTck)/DfiRate)+1) << PCTL_TPR1_TCCD_BFO) |
|
||||
((((DramInfo->Timing->TrcdPs)/DrmaPeriod)+1) << PCTL_TPR1_TRCD_BFO) |
|
||||
((((DramInfo->Timing->TrcPs)/DrmaPeriod)+1) << PCTL_TPR1_TRC_BFO ) |
|
||||
(((DramInfo->Timing->TrrdTck/DfiRate)+1) << PCTL_TPR1_TRRD_BFO)
|
||||
));
|
||||
|
||||
HAL_SDR_WRITE32(REG_SDR_TPR2, (
|
||||
(DramInfo->Timing->TmrdTck << PCTL_TPR2_TMRD_BFO ) |
|
||||
(0 << PCTL_TPR2_INIT_NS_EN_BFO ) |
|
||||
(2 << PCTL_TPR2_INIT_REF_NUM_BFO)
|
||||
));
|
||||
|
||||
// set all_mode _idle
|
||||
HAL_SDR_WRITE32(REG_SDR_CSR,0x700);
|
||||
|
||||
// start to init
|
||||
HAL_SDR_WRITE32(REG_SDR_CCR,0x01);
|
||||
while ((HAL_SDR_READ32(REG_SDR_CCR)& 0x1) == 0x0);
|
||||
|
||||
// enter mem_mode
|
||||
HAL_SDR_WRITE32(REG_SDR_CSR,0x600);
|
||||
#else
|
||||
// WRAP_MISC setting
|
||||
ms_ctrl_0_map->misc = //0x12;
|
||||
(
|
||||
(Page << WRAP_MISC_PAGE_SIZE_BFO) |
|
||||
(DramInfo->Dev->Bank << WRAP_MISC_BANK_SIZE_BFO) |
|
||||
(CsBstLen << WRAP_MISC_BST_SIZE_BFO ) |
|
||||
(DqWidth << WRAP_MISC_DDR_PARAL_BFO)
|
||||
);
|
||||
// PCTL setting
|
||||
ms_ctrl_0_map->dcr = //0x208;
|
||||
(
|
||||
(0x2 << PCTL_DCR_DFI_RATE_BFO) |
|
||||
(DqWidth << PCTL_DCR_DQ32_BFO ) |
|
||||
(DdrType << PCTL_DCR_DDR3_BFO )
|
||||
);
|
||||
|
||||
ms_ctrl_0_map->iocr = (
|
||||
((CasRd -4)/(DfiRate) << PCTL_IOCR_TPHY_RD_EN_BFO ) |
|
||||
(0 << PCTL_IOCR_TPHY_WL_BFO ) |
|
||||
(((CasWr -3)/(DfiRate)) << PCTL_IOCR_TPHY_WD_BFO ) |
|
||||
(0 << PCTL_IOCR_RD_PIPE_BFO )
|
||||
);
|
||||
|
||||
if ((DramInfo->Dev->DeviceType) != SDR) { // DDR2/3
|
||||
ms_ctrl_0_map->emr2 = DramEmr2;
|
||||
|
||||
ms_ctrl_0_map->emr1 = (
|
||||
(1 << 2 ) | //RTT
|
||||
(1 << 1 ) | //D.I.C
|
||||
(DramInfo->ModeReg->Mode1DllEnN )
|
||||
);
|
||||
} // DDR2/3
|
||||
|
||||
ms_ctrl_0_map->mr = DramMr0;
|
||||
|
||||
ms_ctrl_0_map->drr = (
|
||||
(0 << PCTL_DRR_REF_DIS_BFO) |
|
||||
(9 << PCTL_DRR_REF_NUM_BFO) |
|
||||
((((DramInfo->Timing->TrefiPs)/DrmaPeriod)+1)<< PCTL_DRR_TREF_BFO ) |
|
||||
((((DramInfo->Timing->TrfcPs)/DrmaPeriod)+1) << PCTL_DRR_TRFC_BFO )
|
||||
);
|
||||
|
||||
ms_ctrl_0_map->tpr0= (
|
||||
((((DramInfo->Timing->TrtpTck)/DfiRate)+1) << PCTL_TPR0_TRTP_BFO) |
|
||||
(CrTwr << PCTL_TPR0_TWR_BFO ) |
|
||||
((((DramInfo->Timing->TrasPs)/DrmaPeriod)+1) << PCTL_TPR0_TRAS_BFO) |
|
||||
((((DramInfo->Timing->TrpPs)/DrmaPeriod)+1) << PCTL_TPR0_TRP_BFO )
|
||||
);
|
||||
|
||||
ms_ctrl_0_map->tpr1= (
|
||||
(CrTrtw << PCTL_TPR1_TRTW_BFO) |
|
||||
((((DramInfo->Timing->TwtrTck)/DfiRate)+3) << PCTL_TPR1_TWTR_BFO) |
|
||||
((((DramInfo->Timing->TccdTck)/DfiRate)+1) << PCTL_TPR1_TCCD_BFO) |
|
||||
((((DramInfo->Timing->TrcdPs)/DrmaPeriod)+1) << PCTL_TPR1_TRCD_BFO) |
|
||||
((((DramInfo->Timing->TrcPs)/DrmaPeriod)+1) << PCTL_TPR1_TRC_BFO ) |
|
||||
(((DramInfo->Timing->TrrdTck/DfiRate)+1) << PCTL_TPR1_TRRD_BFO)
|
||||
);
|
||||
|
||||
ms_ctrl_0_map->tpr2= (
|
||||
(DramInfo->Timing->TmrdTck << PCTL_TPR2_TMRD_BFO ) |
|
||||
(0 << PCTL_TPR2_INIT_NS_EN_BFO ) |
|
||||
(2 << PCTL_TPR2_INIT_REF_NUM_BFO)
|
||||
);
|
||||
// set all_mode _idle
|
||||
ms_ctrl_0_map->csr = 0x700;
|
||||
|
||||
// start to init
|
||||
ms_ctrl_0_map->ccr = 0x1;
|
||||
while (((ms_ctrl_0_map->ccr)& 0x1) == 0x0);
|
||||
|
||||
// enter mem_mode
|
||||
ms_ctrl_0_map->csr= 0x600;
|
||||
#endif
|
||||
} // DramInit
|
||||
|
||||
//3
|
||||
extern void *
|
||||
_memset( void *s, int c, SIZE_T n );
|
||||
|
||||
HAL_SDRC_TEXT_SECTION
|
||||
u32
|
||||
SdrCalibration(
|
||||
VOID
|
||||
)
|
||||
{
|
||||
#ifdef FPGA
|
||||
#ifdef FPGA_TEMP
|
||||
// u32 Value32;
|
||||
#endif
|
||||
#else
|
||||
// u32 Value32;
|
||||
#endif
|
||||
u32 RdPipe = 0, TapCnt = 0, Pass = 0, AvaWdsCnt = 0;
|
||||
u32 RdPipeCounter, RecNum[2], RecRdPipe[2];//, AvaWds[2][REC_NUM];
|
||||
BOOL RdPipeFlag, PassFlag = 0, Result;
|
||||
|
||||
Result = _FALSE;
|
||||
|
||||
#ifdef SUPPORT_DRAM_KED
|
||||
// read calibration data from system data 0x5d~0x6c
|
||||
SPIC_INIT_PARA SpicInitPara;
|
||||
u32 valid;
|
||||
union { u8 b[4]; u32 l;} value;
|
||||
u32 CpuType = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70)) >> 4);
|
||||
|
||||
valid = RdPipe = TapCnt = 0xFFFFFFFF;
|
||||
value.l = HAL_READ32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType);
|
||||
if((value.b[0]^value.b[1])==0xFF)
|
||||
valid = value.b[0];
|
||||
//DiagPrintf("dump1 %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
|
||||
value.l = HAL_READ32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType+4);
|
||||
if((value.b[0]^value.b[1])==0xFF)
|
||||
RdPipe = value.b[0];
|
||||
if((value.b[2]^value.b[3])==0xFF)
|
||||
TapCnt = value.b[2];
|
||||
//DiagPrintf("dump2 %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
|
||||
|
||||
if((valid==1)&&(RdPipe!=0xFFFFFFFF)&&(TapCnt!=0xFFFFFFFF)){
|
||||
// wait DRAM settle down
|
||||
HalDelayUs(10);
|
||||
// load previous dram Ked data
|
||||
HAL_SDR_WRITE32(REG_SDR_IOCR, ((HAL_SDR_READ32(REG_SDR_IOCR) & 0xff) | (RdPipe << PCTL_IOCR_RD_PIPE_BFO)));
|
||||
SDR_DDL_FCTRL(TapCnt);
|
||||
if(MemTest(3))
|
||||
return _TRUE;
|
||||
}
|
||||
#endif
|
||||
|
||||
_memset((u8*)AvaWds, 0, sizeof(u32)*REC_NUM*2);
|
||||
|
||||
volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
|
||||
ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
|
||||
ms_ctrl_0_map = ms_ctrl_0_map;
|
||||
PassFlag = PassFlag;
|
||||
RdPipeCounter =0;
|
||||
|
||||
// DBG_8195A("%d\n",__LINE__);
|
||||
|
||||
for(RdPipe=MIN_RD_PIPE; RdPipe<=MAX_RD_PIPE; RdPipe++) {
|
||||
// ms_ctrl_0_map->iocr = (ms_ctrl_0_map->iocr & 0xff) | (RdPipe << PCTL_IOCR_RD_PIPE_BFO);
|
||||
HAL_SDR_WRITE32(REG_SDR_IOCR, ((HAL_SDR_READ32(REG_SDR_IOCR) & 0xff) | (RdPipe << PCTL_IOCR_RD_PIPE_BFO)));
|
||||
|
||||
DBG_SDR_INFO("IOCR: 0x%x; Write: 0x%x\n",HAL_SDR_READ32(REG_SDR_IOCR), (RdPipe << PCTL_IOCR_RD_PIPE_BFO));
|
||||
// DBG_8195A("IOCR: 0x%x; Write: 0x%x\n",ms_ctrl_0_map->iocr, (RdPipe << PCTL_IOCR_RD_PIPE_BFO));
|
||||
|
||||
RdPipeFlag = _FALSE;
|
||||
PassFlag = _FALSE;
|
||||
AvaWdsCnt = 0;
|
||||
|
||||
for(TapCnt=0; TapCnt < (MAX_TAP_DLY+1); TapCnt++) {
|
||||
// Modify clk delay
|
||||
#ifdef FPGA
|
||||
#ifdef FPGA_TEMP
|
||||
SDR_DDL_FCTRL(TapCnt);
|
||||
// Value32 = (RD_DATA(SDR_CLK_DLY_CTRL) & 0xFF00FFFF);
|
||||
// Value32 = (Value32 | (TapCnt << 16));
|
||||
// WR_DATA(SDR_CLK_DLY_CTRL, Value32);
|
||||
#else
|
||||
HAL_SDR_WRITE32(REG_SDR_DLY0, TapCnt);
|
||||
// ms_ctrl_0_map->phy_dly0 = TapCnt;
|
||||
#endif
|
||||
DBG_SDR_INFO("DLY: 0x%x; Write: 0x%x\n",HAL_PERI_ON_READ32(REG_PESOC_MEM_CTRL), TapCnt);
|
||||
#else
|
||||
SDR_DDL_FCTRL(TapCnt);
|
||||
// Value32 = (RD_DATA(SDR_CLK_DLY_CTRL) & 0xFF00FFFF);
|
||||
// Value32 = (Value32 | (TapCnt << 16));
|
||||
// WR_DATA(SDR_CLK_DLY_CTRL, Value32);
|
||||
#endif
|
||||
|
||||
Pass = MemTest(10000);
|
||||
PassFlag = _FALSE;
|
||||
|
||||
if(Pass==_TRUE) { // PASS
|
||||
|
||||
if (!RdPipeFlag) {
|
||||
DBG_SDR_INFO("%d Time Pass\n", RdPipeCounter);
|
||||
RdPipeCounter++;
|
||||
RdPipeFlag = _TRUE;
|
||||
RecRdPipe[RdPipeCounter - 1] = RdPipe;
|
||||
}
|
||||
|
||||
AvaWds[RdPipeCounter-1][AvaWdsCnt] = TapCnt;
|
||||
AvaWdsCnt++;
|
||||
|
||||
RecNum[RdPipeCounter-1] = AvaWdsCnt;
|
||||
|
||||
if((TapCnt+TAP_DLY)>=MAX_TAP_DLY) {
|
||||
break;
|
||||
}
|
||||
|
||||
PassFlag = _TRUE;
|
||||
|
||||
DBG_SDR_INFO("Verify Pass => RdPipe:%d; TapCnt: %d\n", RdPipe, TapCnt);
|
||||
|
||||
}
|
||||
else { // FAIL
|
||||
// if(PassFlag==_TRUE) {
|
||||
// break;
|
||||
// }
|
||||
// else {
|
||||
if (RdPipeCounter > 0) {
|
||||
RdPipeCounter++;
|
||||
if (RdPipeCounter < 3) {
|
||||
RecNum[RdPipeCounter-1] = 0;
|
||||
RecRdPipe[RdPipeCounter - 1] = RdPipe;
|
||||
}
|
||||
break;
|
||||
}
|
||||
// }
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (RdPipeCounter > 2) {
|
||||
u8 BestRangeIndex, BestIndex;
|
||||
|
||||
#ifdef CONFIG_SDR_VERIFY //to reduce log
|
||||
u32 i;
|
||||
DBG_SDR_INFO("Avaliable RdPipe 0\n");
|
||||
|
||||
for (i=0;i<256;i++) {
|
||||
DBG_SDR_INFO("%d\n", AvaWds[0][i]);
|
||||
}
|
||||
DBG_SDR_INFO("Avaliable RdPipe 1\n");
|
||||
for (i=0;i<256;i++) {
|
||||
DBG_SDR_INFO("%d\n", AvaWds[1][i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
DBG_SDR_INFO("Rec 0 => total counter %d; RdPipe:%d;\n", RecNum[0], RecRdPipe[0]);
|
||||
DBG_SDR_INFO("Rec 1 => total counter %d; RdPipe:%d;\n", RecNum[1], RecRdPipe[1]);
|
||||
|
||||
BestRangeIndex = (RecNum[0] > RecNum[1]) ? 0 : 1;
|
||||
|
||||
BestIndex = RecNum[BestRangeIndex]>>1;
|
||||
|
||||
DBG_SDR_INFO("The Finial RdPipe: %d; TpCnt: 0x%x\n", RecRdPipe[BestRangeIndex], AvaWds[BestRangeIndex][BestIndex]);
|
||||
|
||||
// set RdPipe and tap_dly
|
||||
// ms_ctrl_0_map->iocr = (ms_ctrl_0_map->iocr & 0xff) | (RecRdPipe[BestRangeIndex] << PCTL_IOCR_RD_PIPE_BFO);
|
||||
HAL_SDR_WRITE32(REG_SDR_IOCR, ((HAL_SDR_READ32(REG_SDR_IOCR) & 0xff) | (RecRdPipe[BestRangeIndex] << PCTL_IOCR_RD_PIPE_BFO)));
|
||||
|
||||
#ifdef FPGA
|
||||
#ifdef FPGA_TEMP
|
||||
SDR_DDL_FCTRL(AvaWds[BestRangeIndex][BestIndex]);
|
||||
|
||||
// Value32 = (RD_DATA(SDR_CLK_DLY_CTRL) & 0xFF00FFFF);
|
||||
// Value32 = Value32 | (AvaWds[BestRangeIndex][BestIndex] << 16);
|
||||
// WR_DATA(SDR_CLK_DLY_CTRL, Value32);
|
||||
#else
|
||||
HAL_SDR_WRITE32(REG_SDR_DLY0, AvaWds[BestRangeIndex][BestIndex]);
|
||||
// ms_ctrl_0_map->phy_dly0 = AvaWds[BestRangeIndex][BestIndex];
|
||||
#endif
|
||||
#else
|
||||
SDR_DDL_FCTRL(AvaWds[BestRangeIndex][BestIndex]);
|
||||
// Value32 = (RD_DATA(SDR_CLK_DLY_CTRL) & 0xFF00FFFF);
|
||||
// Value32 = Value32 | (AvaWds[BestRangeIndex][BestIndex] << 16);
|
||||
// WR_DATA(SDR_CLK_DLY_CTRL, Value32);
|
||||
#endif
|
||||
#ifdef SUPPORT_DRAM_KED
|
||||
RdPipe = RecRdPipe[BestRangeIndex];
|
||||
TapCnt = AvaWds[BestRangeIndex][BestIndex];
|
||||
|
||||
value.b[0] = (u8)RdPipe;
|
||||
value.b[1] = ~value.b[0];
|
||||
value.b[2] = (u8)TapCnt;
|
||||
value.b[3] = ~value.b[2];
|
||||
//DiagPrintf("dump1w %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
|
||||
HAL_WRITE32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType+4, value.l);
|
||||
SpicWaitWipDoneRefinedRtl8195A(SpicInitPara);
|
||||
|
||||
valid = 1;
|
||||
value.b[0] = (u8)valid;
|
||||
value.b[1] = ~value.b[0];
|
||||
value.b[2] = 0xFF;
|
||||
value.b[3] = 0xFF;
|
||||
//DiagPrintf("dump1w %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
|
||||
HAL_WRITE32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType, value.l);
|
||||
SpicWaitWipDoneRefinedRtl8195A(SpicInitPara);
|
||||
#endif
|
||||
Result = _TRUE;
|
||||
break;
|
||||
}
|
||||
|
||||
if (RdPipeCounter == 0) {
|
||||
|
||||
DBG_SDR_INFO("NOT Find RdPipe\n");
|
||||
}
|
||||
}
|
||||
|
||||
return Result;
|
||||
} // SdrCalibration
|
||||
|
||||
|
||||
|
||||
|
||||
HAL_SDRC_TEXT_SECTION
|
||||
VOID
|
||||
ChangeRandSeed(
|
||||
IN u32 Seed
|
||||
)
|
||||
{
|
||||
rand_x = Seed;
|
||||
}
|
||||
|
||||
HAL_SDRC_TEXT_SECTION
|
||||
u32
|
||||
Sdr_Rand2(
|
||||
VOID
|
||||
)
|
||||
{
|
||||
HAL_RAM_DATA_SECTION static unsigned int y = 362436;
|
||||
|
||||
HAL_RAM_DATA_SECTION static unsigned int z = 521288629;
|
||||
|
||||
HAL_RAM_DATA_SECTION static unsigned int c = 7654321;
|
||||
|
||||
unsigned long long t, a= 698769069;
|
||||
|
||||
rand_x = 69069 * rand_x + 12345;
|
||||
y ^= (y << 13); y ^= (y >> 17); y ^= (y << 5);
|
||||
t = a * z + c; c = (t >> 32); z = t;
|
||||
|
||||
return rand_x + y + z;
|
||||
}
|
||||
|
||||
HAL_SDRC_TEXT_SECTION
|
||||
s32
|
||||
MemTest(
|
||||
u32 LoopCnt
|
||||
)
|
||||
{
|
||||
u32 LoopIndex = 0;
|
||||
u32 Value32, Addr;
|
||||
for (LoopIndex = 0; LoopIndex<LoopCnt; LoopIndex++) {
|
||||
Value32 = Sdr_Rand2();
|
||||
Addr = Sdr_Rand2();
|
||||
Addr &= 0x1FFFFF;
|
||||
Addr &= (~0x3);
|
||||
|
||||
HAL_SDRAM_WRITE32(Addr, Value32);
|
||||
|
||||
if (HAL_SDRAM_READ32(Addr) != Value32) {
|
||||
DBG_8195A("Test %d: No match addr 0x%x => 0x%x != 0x%x\n",LoopIndex,
|
||||
Addr, Value32, HAL_SDRAM_READ32(Addr));
|
||||
return _FALSE;
|
||||
}
|
||||
else {
|
||||
// HAL_SDRAM_WRITE32(Addr, 0);
|
||||
}
|
||||
}
|
||||
return _TRUE;
|
||||
|
||||
} // MemTest
|
||||
|
||||
#endif // end of "#ifdef CONFIG_SDR_EN"
|
||||
3449
lib/fwlib/src/hal_soc_ps_monitor.c
Normal file
3449
lib/fwlib/src/hal_soc_ps_monitor.c
Normal file
File diff suppressed because it is too large
Load diff
377
lib/fwlib/src/hal_ssi.c
Normal file
377
lib/fwlib/src/hal_ssi.c
Normal file
|
|
@ -0,0 +1,377 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "hal_ssi.h"
|
||||
|
||||
const HAL_GDMA_CHNL Ssi2_TX_GDMA_Chnl_Option[] = {
|
||||
{0,4,GDMA0_CHANNEL4_IRQ,0},
|
||||
{0,5,GDMA0_CHANNEL5_IRQ,0},
|
||||
{0,3,GDMA0_CHANNEL3_IRQ,0},
|
||||
{0,0,GDMA0_CHANNEL0_IRQ,0},
|
||||
{0,1,GDMA0_CHANNEL1_IRQ,0},
|
||||
{0,2,GDMA0_CHANNEL2_IRQ,0},
|
||||
|
||||
{0xff,0,0,0} // end
|
||||
};
|
||||
|
||||
const HAL_GDMA_CHNL Ssi2_RX_GDMA_Chnl_Option[] = {
|
||||
{1,4,GDMA1_CHANNEL4_IRQ,0},
|
||||
{1,5,GDMA1_CHANNEL5_IRQ,0},
|
||||
{1,3,GDMA1_CHANNEL3_IRQ,0},
|
||||
{1,0,GDMA1_CHANNEL0_IRQ,0},
|
||||
{1,1,GDMA1_CHANNEL1_IRQ,0},
|
||||
{1,2,GDMA1_CHANNEL2_IRQ,0},
|
||||
|
||||
{0xff,0,0,0} // end
|
||||
};
|
||||
|
||||
//TODO: Load default Setting: It should be loaded from external setting file.
|
||||
const DW_SSI_DEFAULT_SETTING SpiDefaultSetting =
|
||||
{
|
||||
.RxCompCallback = NULL,
|
||||
.RxCompCbPara = NULL,
|
||||
.RxData = NULL,
|
||||
.TxCompCallback = NULL,
|
||||
.TxCompCbPara = NULL,
|
||||
.TxData = NULL,
|
||||
.DmaRxDataLevel = 7, // RX FIFO stored bytes > (DMARDLR(7) + 1) then trigger DMA transfer
|
||||
.DmaTxDataLevel = 48, // TX FIFO free space > (FIFO_SPACE(64)-DMATDLR(48)) then trigger DMA transfer
|
||||
.InterruptPriority = 0x20,
|
||||
.RxLength = 0,
|
||||
.RxLengthRemainder = 0,
|
||||
.RxThresholdLevel = 7, // if number of entries in th RX FIFO >= (RxThresholdLevel+1), RX interrupt asserted
|
||||
.TxLength = 0,
|
||||
.TxThresholdLevel = 8, // if number of entries in th TX FIFO <= TxThresholdLevel, TX interrupt asserted
|
||||
.SlaveSelectEnable = 0,
|
||||
.ClockDivider = SSI_CLK_SPI0_2/1000000, // SCLK=1M
|
||||
.DataFrameNumber = 0,
|
||||
.ControlFrameSize = CFS_1_BIT,
|
||||
.DataFrameFormat = FRF_MOTOROLA_SPI,
|
||||
.DataFrameSize = DFS_8_BITS,
|
||||
.DmaControl = 0, // default DMA is disable
|
||||
.InterruptMask = 0x0,
|
||||
.MicrowireDirection = MW_DIRECTION_MASTER_TO_SLAVE,
|
||||
.MicrowireHandshaking = MW_HANDSHAKE_DISABLE,
|
||||
.MicrowireTransferMode = MW_TMOD_NONSEQUENTIAL,
|
||||
.SclkPhase = SCPH_TOGGLES_AT_START,
|
||||
.SclkPolarity = SCPOL_INACTIVE_IS_HIGH,
|
||||
.SlaveOutputEnable = SLV_TXD_ENABLE, // Slave
|
||||
.TransferMode = TMOD_TR,
|
||||
.TransferMechanism = SSI_DTM_INTERRUPT
|
||||
};
|
||||
|
||||
extern HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor);
|
||||
extern HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor);
|
||||
extern HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor);
|
||||
extern HAL_Status HalSsiDeInitRtl8195a(VOID * Adapter);
|
||||
extern HAL_Status HalSsiClockOffRtl8195a(VOID * Adapter);
|
||||
extern HAL_Status HalSsiClockOnRtl8195a(VOID * Adapter);
|
||||
extern HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length);
|
||||
extern HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
|
||||
extern VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate);
|
||||
#ifdef CONFIG_GDMA_EN
|
||||
extern VOID HalSsiDmaInitRtl8195a(VOID *Adapter);
|
||||
#endif
|
||||
|
||||
VOID HalSsiOpInit(VOID *Adaptor)
|
||||
{
|
||||
PHAL_SSI_OP pHalSsiOp = (PHAL_SSI_OP) Adaptor;
|
||||
|
||||
// pHalSsiOp->HalSsiPinmuxEnable = HalSsiPinmuxEnableRtl8195a;
|
||||
pHalSsiOp->HalSsiPinmuxEnable = HalSsiPinmuxEnableRtl8195a_Patch;
|
||||
pHalSsiOp->HalSsiPinmuxDisable = HalSsiPinmuxDisableRtl8195a;
|
||||
pHalSsiOp->HalSsiEnable = HalSsiEnableRtl8195a;
|
||||
pHalSsiOp->HalSsiDisable = HalSsiDisableRtl8195a;
|
||||
// pHalSsiOp->HalSsiInit = HalSsiInitRtl8195a;
|
||||
pHalSsiOp->HalSsiInit = HalSsiInitRtl8195a_Patch;
|
||||
pHalSsiOp->HalSsiSetSclkPolarity = HalSsiSetSclkPolarityRtl8195a;
|
||||
pHalSsiOp->HalSsiSetSclkPhase = HalSsiSetSclkPhaseRtl8195a;
|
||||
pHalSsiOp->HalSsiWrite = HalSsiWriteRtl8195a;
|
||||
pHalSsiOp->HalSsiRead = HalSsiReadRtl8195a;
|
||||
pHalSsiOp->HalSsiGetRxFifoLevel = HalSsiGetRxFifoLevelRtl8195a;
|
||||
pHalSsiOp->HalSsiGetTxFifoLevel = HalSsiGetTxFifoLevelRtl8195a;
|
||||
pHalSsiOp->HalSsiGetStatus = HalSsiGetStatusRtl8195a;
|
||||
pHalSsiOp->HalSsiGetInterruptStatus = HalSsiGetInterruptStatusRtl8195a;
|
||||
pHalSsiOp->HalSsiLoadSetting = HalSsiLoadSettingRtl8195a;
|
||||
pHalSsiOp->HalSsiSetInterruptMask = HalSsiSetInterruptMaskRtl8195a;
|
||||
pHalSsiOp->HalSsiGetInterruptMask = HalSsiGetInterruptMaskRtl8195a;
|
||||
pHalSsiOp->HalSsiSetDeviceRole = HalSsiSetDeviceRoleRtl8195a;
|
||||
pHalSsiOp->HalSsiWriteable = HalSsiWriteableRtl8195a;
|
||||
pHalSsiOp->HalSsiReadable = HalSsiReadableRtl8195a;
|
||||
pHalSsiOp->HalSsiBusy = HalSsiBusyRtl8195a;
|
||||
pHalSsiOp->HalSsiInterruptEnable = HalSsiInterruptEnableRtl8195a;
|
||||
pHalSsiOp->HalSsiInterruptDisable = HalSsiInterruptDisableRtl8195a;
|
||||
// pHalSsiOp->HalSsiReadInterrupt = HalSsiReadInterruptRtl8195a;
|
||||
pHalSsiOp->HalSsiReadInterrupt = HalSsiIntReadRtl8195a;
|
||||
pHalSsiOp->HalSsiSetRxFifoThresholdLevel = HalSsiSetRxFifoThresholdLevelRtl8195a;
|
||||
pHalSsiOp->HalSsiSetTxFifoThresholdLevel = HalSsiSetTxFifoThresholdLevelRtl8195a;
|
||||
// pHalSsiOp->HalSsiWriteInterrupt = HalSsiWriteInterruptRtl8195a;
|
||||
pHalSsiOp->HalSsiWriteInterrupt = HalSsiIntWriteRtl8195a;
|
||||
pHalSsiOp->HalSsiGetRawInterruptStatus = HalSsiGetRawInterruptStatusRtl8195a;
|
||||
pHalSsiOp->HalSsiGetSlaveEnableRegister = HalSsiGetSlaveEnableRegisterRtl8195a;
|
||||
pHalSsiOp->HalSsiSetSlaveEnableRegister = HalSsiSetSlaveEnableRegisterRtl8195a;
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_GDMA_EN
|
||||
|
||||
HAL_Status
|
||||
HalSsiTxGdmaInit(
|
||||
IN PHAL_SSI_OP pHalSsiOp,
|
||||
IN PHAL_SSI_ADAPTOR pHalSsiAdapter
|
||||
)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
PSSI_DMA_CONFIG pDmaConfig;
|
||||
HAL_GDMA_CHNL *pgdma_chnl;
|
||||
PHAL_GDMA_OP pHalGdmaOp;
|
||||
|
||||
if ((NULL == pHalSsiOp) || (NULL == pHalSsiAdapter)) {
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
pDmaConfig = &pHalSsiAdapter->DmaConfig;
|
||||
|
||||
// Load default setting
|
||||
HalSsiTxGdmaLoadDefRtl8195a((void*)pHalSsiAdapter);
|
||||
|
||||
// Start to patch the default setting
|
||||
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter;
|
||||
if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) {
|
||||
// The default GDMA Channel is not available, try others
|
||||
if (pHalSsiAdapter->Index == 2) {
|
||||
// SSI2 TX Only can use GDMA 0
|
||||
pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Ssi2_TX_GDMA_Chnl_Option);
|
||||
}
|
||||
else {
|
||||
pgdma_chnl = HalGdmaChnlAlloc(NULL);
|
||||
}
|
||||
|
||||
if (pgdma_chnl == NULL) {
|
||||
// No Available DMA channel
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else {
|
||||
pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx;
|
||||
pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl;
|
||||
pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl;
|
||||
pDmaConfig->TxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum;
|
||||
}
|
||||
}
|
||||
|
||||
DBG_SSI_INFO("HalSsiTxGdmaInit: GdmaIndex=%d ChNum=%d \r\n", pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum);
|
||||
pHalGdmaOp = (PHAL_GDMA_OP)pDmaConfig->pHalGdmaOp;
|
||||
pHalGdmaOp->HalGdmaOnOff((VOID*)(pHalGdmaAdapter));
|
||||
pHalGdmaOp->HalGdmaChIsrEnAndDis((VOID*)(pHalGdmaAdapter));
|
||||
|
||||
HalSsiDmaInit(pHalSsiAdapter);
|
||||
InterruptRegister(&pDmaConfig->TxGdmaIrqHandle);
|
||||
InterruptEn(&pDmaConfig->TxGdmaIrqHandle);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
VOID
|
||||
HalSsiTxGdmaDeInit(
|
||||
IN PHAL_SSI_ADAPTOR pHalSsiAdapter
|
||||
)
|
||||
{
|
||||
PSSI_DMA_CONFIG pDmaConfig;
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
HAL_GDMA_CHNL GdmaChnl;
|
||||
|
||||
if (NULL == pHalSsiAdapter) {
|
||||
return;
|
||||
}
|
||||
|
||||
pDmaConfig = &pHalSsiAdapter->DmaConfig;
|
||||
|
||||
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pTxHalGdmaAdapter;
|
||||
GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
|
||||
GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
|
||||
GdmaChnl.IrqNum = pDmaConfig->TxGdmaIrqHandle.IrqNum;
|
||||
HalGdmaChnlFree(&GdmaChnl);
|
||||
}
|
||||
|
||||
|
||||
HAL_Status
|
||||
HalSsiRxGdmaInit(
|
||||
IN PHAL_SSI_OP pHalSsiOp,
|
||||
IN PHAL_SSI_ADAPTOR pHalSsiAdapter
|
||||
)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
PSSI_DMA_CONFIG pDmaConfig;
|
||||
HAL_GDMA_CHNL *pgdma_chnl;
|
||||
PHAL_GDMA_OP pHalGdmaOp;
|
||||
|
||||
if ((NULL == pHalSsiOp) || (NULL == pHalSsiAdapter)) {
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
pDmaConfig = &pHalSsiAdapter->DmaConfig;
|
||||
// Load default setting
|
||||
HalSsiRxGdmaLoadDefRtl8195a((void*)pHalSsiAdapter);
|
||||
|
||||
// Start to patch the default setting
|
||||
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter;
|
||||
if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) {
|
||||
// The default GDMA Channel is not available, try others
|
||||
if (pHalSsiAdapter->Index == 2) {
|
||||
// SSI2 RX Only can use GDMA 1
|
||||
pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Ssi2_RX_GDMA_Chnl_Option);
|
||||
}
|
||||
else {
|
||||
pgdma_chnl = HalGdmaChnlAlloc(NULL);
|
||||
}
|
||||
|
||||
if (pgdma_chnl == NULL) {
|
||||
// No Available DMA channel
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else {
|
||||
pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx;
|
||||
pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl;
|
||||
pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl;
|
||||
pDmaConfig->RxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum;
|
||||
}
|
||||
}
|
||||
|
||||
DBG_SSI_INFO("HalSsiRxGdmaInit: GdmaIndex=%d ChNum=%d \r\n", pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum);
|
||||
pHalGdmaOp = (PHAL_GDMA_OP)pDmaConfig->pHalGdmaOp;
|
||||
pHalGdmaOp->HalGdmaOnOff((VOID*)(pHalGdmaAdapter));
|
||||
pHalGdmaOp->HalGdmaChIsrEnAndDis((VOID*)(pHalGdmaAdapter));
|
||||
|
||||
HalSsiDmaInit(pHalSsiAdapter);
|
||||
InterruptRegister(&pDmaConfig->RxGdmaIrqHandle);
|
||||
InterruptEn(&pDmaConfig->RxGdmaIrqHandle);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
VOID
|
||||
HalSsiRxGdmaDeInit(
|
||||
IN PHAL_SSI_ADAPTOR pHalSsiAdapter
|
||||
)
|
||||
{
|
||||
PSSI_DMA_CONFIG pDmaConfig;
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
HAL_GDMA_CHNL GdmaChnl;
|
||||
|
||||
if (NULL == pHalSsiAdapter) {
|
||||
return;
|
||||
}
|
||||
|
||||
pDmaConfig = &pHalSsiAdapter->DmaConfig;
|
||||
|
||||
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pDmaConfig->pRxHalGdmaAdapter;
|
||||
GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
|
||||
GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
|
||||
GdmaChnl.IrqNum = pDmaConfig->RxGdmaIrqHandle.IrqNum;
|
||||
HalGdmaChnlFree(&GdmaChnl);
|
||||
}
|
||||
|
||||
#endif // end of "#ifdef CONFIG_GDMA_EN"
|
||||
|
||||
HAL_Status
|
||||
HalSsiInit(VOID *Data)
|
||||
{
|
||||
HAL_Status ret;
|
||||
PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
REG_POWER_STATE SsiPwrState;
|
||||
#endif
|
||||
ret = HalSsiInitRtl8195a_Patch(pHalSsiAdapter);
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
if(ret == HAL_OK) {
|
||||
// To register a new peripheral device power state
|
||||
SsiPwrState.FuncIdx = SPI0+ pHalSsiAdapter->Index;
|
||||
SsiPwrState.PwrState = ACT;
|
||||
RegPowerState(SsiPwrState);
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
HalSsiDeInit(VOID *Data)
|
||||
{
|
||||
HAL_Status ret;
|
||||
PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
REG_POWER_STATE SsiPwrState;
|
||||
u8 HardwareState;
|
||||
|
||||
SsiPwrState.FuncIdx= SPI0+ pHalSsiAdapter->Index;
|
||||
QueryRegPwrState(SsiPwrState.FuncIdx, &(SsiPwrState.PwrState), &HardwareState);
|
||||
|
||||
if(SsiPwrState.PwrState != HardwareState){
|
||||
DBG_SSI_ERR("Registered State is not the Hardware State");
|
||||
return HAL_ERR_UNKNOWN;
|
||||
}
|
||||
else{
|
||||
if((SsiPwrState.PwrState != INACT) && (SsiPwrState.PwrState !=ACT)){
|
||||
DBG_SSI_INFO("Return to ACT state before DeInit");
|
||||
HalSsiEnable(pHalSsiAdapter);
|
||||
QueryRegPwrState(SsiPwrState.FuncIdx, &(SsiPwrState.PwrState), &HardwareState);
|
||||
}
|
||||
if(SsiPwrState.PwrState == ACT){
|
||||
SsiPwrState.PwrState = INACT;
|
||||
RegPowerState(SsiPwrState);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
ret = HalSsiDeInitRtl8195a(pHalSsiAdapter);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
HAL_Status
|
||||
HalSsiEnable(VOID *Data)
|
||||
{
|
||||
HAL_Status ret;
|
||||
PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
REG_POWER_STATE SsiPwrState;
|
||||
#endif
|
||||
ret = HalSsiClockOnRtl8195a(pHalSsiAdapter);
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
if(ret == HAL_OK) {
|
||||
// To register a new peripheral device power state
|
||||
SsiPwrState.FuncIdx = SPI0+ pHalSsiAdapter->Index;
|
||||
SsiPwrState.PwrState = ACT;
|
||||
RegPowerState(SsiPwrState);
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
HalSsiDisable(VOID *Data)
|
||||
{
|
||||
HAL_Status ret;
|
||||
PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
REG_POWER_STATE SsiPwrState;
|
||||
#endif
|
||||
ret = HalSsiClockOffRtl8195a(pHalSsiAdapter);
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
if(ret == HAL_OK) {
|
||||
// To register a new peripheral device power state
|
||||
SsiPwrState.FuncIdx = SPI0+ pHalSsiAdapter->Index;
|
||||
SsiPwrState.PwrState = SLPCG;
|
||||
RegPowerState(SsiPwrState);
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
32
lib/fwlib/src/hal_timer.c
Normal file
32
lib/fwlib/src/hal_timer.c
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
|
||||
VOID
|
||||
HalTimerOpInit_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_TIMER_OP pHalTimerOp = (PHAL_TIMER_OP) Data;
|
||||
|
||||
pHalTimerOp->HalGetTimerId = HalGetTimerIdRtl8195a;
|
||||
pHalTimerOp->HalTimerInit = (BOOL (*)(void*))HalTimerInitRtl8195a_Patch;
|
||||
#ifdef CONFIG_CHIP_C_CUT
|
||||
pHalTimerOp->HalTimerReadCount = HalTimerReadCountRtl8195aV02;
|
||||
#else
|
||||
pHalTimerOp->HalTimerReadCount = HalTimerReadCountRtl8195a_Patch;
|
||||
#endif
|
||||
pHalTimerOp->HalTimerIrqClear = HalTimerIrqClearRtl8195a;
|
||||
pHalTimerOp->HalTimerDis = HalTimerDisRtl8195a_Patch;
|
||||
pHalTimerOp->HalTimerEn = HalTimerEnRtl8195a_Patch;
|
||||
pHalTimerOp->HalTimerDumpReg = HalTimerDumpRegRtl8195a;
|
||||
}
|
||||
|
||||
871
lib/fwlib/src/hal_uart.c
Normal file
871
lib/fwlib/src/hal_uart.c
Normal file
|
|
@ -0,0 +1,871 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "rtl8195a_uart.h"
|
||||
#include "hal_uart.h"
|
||||
#include "hal_gdma.h"
|
||||
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
// Pre-Defined Supported Baud Rate Table for CPU 166 MHz
|
||||
const u32 DEF_BAUDRATE_TABLE[] = {
|
||||
110, 300, 600, 1200,
|
||||
2400, 4800, 9600, 14400,
|
||||
19200, 28800, 38400, 57600,
|
||||
76800, 115200, 128000, 153600,
|
||||
230400, 380400, 460800, 500000,
|
||||
921600, 1000000, 1382400, 1444400,
|
||||
1500000, 1843200, 2000000, 2100000,
|
||||
2764800, 3000000, 3250000, 3692300,
|
||||
3750000, 4000000, 6000000,
|
||||
|
||||
56000, 256000,
|
||||
|
||||
// For UART to IR Carrier
|
||||
66000, 72000, 73400, 76000,
|
||||
80000, 112000,
|
||||
|
||||
// End of the table
|
||||
0xffffffff
|
||||
};
|
||||
|
||||
const u16 ovsr_adj_table_10bit[10] = {
|
||||
0x000, 0x020, 0x044, 0x124, 0x294, 0x2AA, 0x16B, 0x2DB, 0x3BB, 0x3EF
|
||||
};
|
||||
|
||||
const u16 ovsr_adj_table_9bit[9] = {
|
||||
0x000, 0x010, 0x044, 0x92, 0xAA, 0x155, 0x1B6, 0x1BB, 0x1EF
|
||||
};
|
||||
|
||||
const u16 ovsr_adj_table_8bit[8] = {
|
||||
0x000, 0x010, 0x044, 0x92, 0xAA, 0xB5, 0xBB, 0xEF
|
||||
};
|
||||
|
||||
#if 0 // Old format
|
||||
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
|
||||
|
||||
const u8 DEF_OVSR_166[] = {
|
||||
10, 10, 12, 14,
|
||||
10, 10, 10, 11,
|
||||
14, 11, 14, 11,
|
||||
14, 10, 11, 14,
|
||||
18, 17, 17, 18,
|
||||
17, 13, 19, 18,
|
||||
10, 11, 13, 19,
|
||||
14, 13, 12, 11,
|
||||
10, 10, 13,
|
||||
|
||||
20, 18,
|
||||
|
||||
// For UART to IR Carrier
|
||||
13, 13, 18, 15,
|
||||
20, 12,
|
||||
};
|
||||
|
||||
const u16 DEF_DIV_166[] = {
|
||||
74272, 27233, 11347, 4863,
|
||||
3404, 1702, 851, 516,
|
||||
304, 258, 152, 129,
|
||||
76, 71, 58, 38,
|
||||
19, 12, 10, 9,
|
||||
5, 6, 3, 3,
|
||||
5, 4, 3, 2,
|
||||
2, 2, 2, 2,
|
||||
2, 2, 1,
|
||||
|
||||
73, 17,
|
||||
|
||||
// For UART to IR Carrier
|
||||
97, 89, 63, 73,
|
||||
52, 62,
|
||||
};
|
||||
|
||||
|
||||
const u16 DEF_OVSR_ADJ_166[] = {
|
||||
0x000, 0x000, 0x000, 0x000,
|
||||
0x000, 0x000, 0x000, 0x000,
|
||||
0x000, 0x000, 0x000, 0x000,
|
||||
0x000, 0x000, 0x000, 0x000,
|
||||
0x2AA, 0x3BB, 0x1B6, 0x010,
|
||||
0x1B6, 0x2AA, 0x1B6, 0x2DB,
|
||||
0x3BB, 0x000, 0x2AA, 0x294,
|
||||
0x2DB, 0x2AA, 0x2AA, 0x000 ,
|
||||
0x3BB, 0x088, 0x2AA,
|
||||
|
||||
0x000, 0x2DB,
|
||||
|
||||
// For UART to IR Carrier
|
||||
0x000, 0x000, 0x000, 0x000,
|
||||
0x000, 0x000
|
||||
};
|
||||
#endif //#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
|
||||
|
||||
#ifdef CONFIG_CHIP_C_CUT
|
||||
|
||||
const u8 DEF_OVSR_166[] = {
|
||||
13, 12, 12, 12,
|
||||
18, 10, 10, 11,
|
||||
10, 11, 10, 20,
|
||||
20, 20, 20, 20,
|
||||
20, 18, 20, 12,
|
||||
15, 16, 20, 19,
|
||||
18, 15, 10, 13,
|
||||
15, 13, 12, 11,
|
||||
11, 10, 13,
|
||||
|
||||
16, 18,
|
||||
|
||||
// For UART to IR Carrier
|
||||
13, 13, 18, 15,
|
||||
20, 12,
|
||||
};
|
||||
|
||||
const u16 DEF_DIV_166[] = {
|
||||
58275, 23148, 11574, 5787,
|
||||
1929, 1736, 868, 526,
|
||||
434, 263, 217, 72,
|
||||
54, 36, 32, 27,
|
||||
18, 12, 9, 13,
|
||||
6, 5, 3, 3,
|
||||
3, 3, 4, 3,
|
||||
2, 2, 2, 2,
|
||||
2, 2, 1,
|
||||
|
||||
93, 18,
|
||||
|
||||
// For UART to IR Carrier
|
||||
97, 89, 63, 73,
|
||||
52, 62,
|
||||
};
|
||||
|
||||
const u16 DEF_OVSR_ADJ_166[] = {
|
||||
0x000, 0x000, 0x000, 0x000,
|
||||
0x000, 0x000, 0x000, 0x000,
|
||||
0x000, 0x000, 0x000, 0x010,
|
||||
0x010, 0x010, 0x124, 0x010,
|
||||
0x010, 0x088, 0x010, 0x2DB,
|
||||
0x000, 0x16B, 0x010, 0x088,
|
||||
0x2AA, 0x000, 0x294, 0x088,
|
||||
0x000, 0x3BB, 0x3BB, 0x088,
|
||||
0x010, 0x294, 0x3BB,
|
||||
|
||||
0x000, 0x010,
|
||||
|
||||
// For UART to IR Carrier
|
||||
0x000, 0x000, 0x000, 0x000,
|
||||
0x000, 0x000
|
||||
};
|
||||
|
||||
#endif // #ifdef CONFIG_CHIP_C_CUT
|
||||
#endif // end of #if 0 // Old format
|
||||
|
||||
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
|
||||
const u8 DEF_OVSR_B_CUT[] = {
|
||||
20, 20, 20, 20,
|
||||
20, 20, 15, 18,
|
||||
13, 15, 18, 13,
|
||||
18, 12, 11, 10,
|
||||
16, 15, 16, 18,
|
||||
11, 20, 19, 14,
|
||||
18, 11, 20, 19,
|
||||
14, 13, 12, 11,
|
||||
21, 20, 13,
|
||||
|
||||
18, 11,
|
||||
|
||||
// For UART to IR Carrier
|
||||
13, 13, 18, 15,
|
||||
20, 12
|
||||
|
||||
};
|
||||
|
||||
const u16 DEF_DIV_B_CUT[] = {
|
||||
37202, 13616, 6808, 3404,
|
||||
1702, 851, 567, 315,
|
||||
327, 189, 118, 109,
|
||||
59, 59, 58, 53,
|
||||
22, 14, 11, 9,
|
||||
8, 4, 3, 4,
|
||||
3, 4, 2, 2,
|
||||
2, 2, 2, 2,
|
||||
1, 1, 1,
|
||||
|
||||
81, 29,
|
||||
|
||||
// For UART to IR Carrier
|
||||
97, 89, 63, 73,
|
||||
52, 62
|
||||
};
|
||||
|
||||
const u8 DEF_OVSR_ADJ_BITS_B_CUT_10B[] = {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
1, 3, 1, 2,
|
||||
1, 4, 7, 1,
|
||||
2, 1, 4, 5,
|
||||
8, 6, 6, 1,
|
||||
8, 4, 6,
|
||||
|
||||
0, 0,
|
||||
|
||||
// For UART to IR Carrier
|
||||
0, 0, 0, 0,
|
||||
0, 0
|
||||
|
||||
};
|
||||
|
||||
const u8 DEF_OVSR_ADJ_BITS_B_CUT_9B[] = {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
1, 3, 1, 1,
|
||||
1, 4, 6, 1,
|
||||
1, 1, 4, 4,
|
||||
7, 6, 5, 1,
|
||||
7, 4, 6,
|
||||
|
||||
0, 0,
|
||||
|
||||
// For UART to IR Carrier
|
||||
0, 0, 0, 0,
|
||||
0, 0
|
||||
|
||||
};
|
||||
|
||||
const u8 DEF_OVSR_ADJ_BITS_B_CUT_8B[] = {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
1, 3, 1, 1,
|
||||
1, 4, 6, 1,
|
||||
1, 1, 4, 4,
|
||||
6, 5, 5, 1,
|
||||
6, 4, 5,
|
||||
|
||||
0, 0,
|
||||
|
||||
// For UART to IR Carrier
|
||||
0, 0, 0, 0,
|
||||
0, 0
|
||||
};
|
||||
|
||||
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
|
||||
|
||||
const u8 DEF_OVSR_C_CUT[] = {
|
||||
20, 20, 20, 20,
|
||||
20, 20, 20, 14,
|
||||
20, 12, 14, 19,
|
||||
19, 19, 13, 20,
|
||||
19, 18, 20, 15,
|
||||
18, 20, 20, 19,
|
||||
11, 15, 20, 13,
|
||||
15, 13, 12, 11,
|
||||
11, 20, 13,
|
||||
|
||||
16, 13,
|
||||
|
||||
// For UART to IR Carrier
|
||||
13, 13, 18, 15,
|
||||
20, 12
|
||||
};
|
||||
|
||||
const u16 DEF_DIV_C_CUT[] = {
|
||||
37878, 13888, 6944, 3472,
|
||||
1736, 868, 434, 413,
|
||||
217, 241, 155, 76,
|
||||
57, 38, 50, 27,
|
||||
19, 12, 9, 11,
|
||||
5, 4, 3, 3,
|
||||
5, 3, 2, 3,
|
||||
2, 2, 2, 2,
|
||||
2, 1, 1,
|
||||
|
||||
93, 25,
|
||||
|
||||
// For UART to IR Carrier
|
||||
97, 89, 63, 73,
|
||||
52, 62
|
||||
};
|
||||
|
||||
const u8 DEF_OVSR_ADJ_BITS_C_CUT_10B[] = {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 1,
|
||||
0, 3, 1, 2,
|
||||
1, 8, 1, 2,
|
||||
1, 1, 8, 2,
|
||||
1, 9, 8, 3,
|
||||
1, 8, 9,
|
||||
|
||||
0, 0,
|
||||
|
||||
// For UART to IR Carrier
|
||||
0, 0, 0, 0,
|
||||
0, 0
|
||||
|
||||
};
|
||||
|
||||
const u8 DEF_OVSR_ADJ_BITS_C_CUT_9B[] = {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 1,
|
||||
0, 2, 1, 1,
|
||||
1, 8, 1, 2,
|
||||
1, 1, 8, 2,
|
||||
1, 8, 8, 3,
|
||||
1, 8, 8,
|
||||
|
||||
0, 0,
|
||||
|
||||
// For UART to IR Carrier
|
||||
0, 0, 0, 0,
|
||||
0, 0
|
||||
|
||||
};
|
||||
|
||||
const u8 DEF_OVSR_ADJ_BITS_C_CUT_8B[] = {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 1,
|
||||
0, 2, 1, 1,
|
||||
1, 7, 1, 2,
|
||||
1, 1, 7, 2,
|
||||
1, 7, 7, 2,
|
||||
1, 7, 7,
|
||||
|
||||
0, 0,
|
||||
|
||||
// For UART to IR Carrier
|
||||
0, 0, 0, 0,
|
||||
0, 0
|
||||
};
|
||||
|
||||
#endif // #if !(CONFIG_CHIP_E_CUT)
|
||||
|
||||
extern u32 _UartIrqHandle(VOID *Data);
|
||||
|
||||
extern HAL_Status
|
||||
HalRuartInitRtl8195a_Patch(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
#if (CONFIG_CHIP_C_CUT)
|
||||
extern _LONG_CALL_ HAL_Status
|
||||
HalRuartInitRtl8195aV02(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
#endif
|
||||
|
||||
extern u8 HalRuartGetChipVerRtl8195a(VOID);
|
||||
|
||||
const HAL_GDMA_CHNL Uart2_TX_GDMA_Chnl_Option[] = {
|
||||
{0,0,GDMA0_CHANNEL0_IRQ,0},
|
||||
{0,1,GDMA0_CHANNEL1_IRQ,0},
|
||||
{0,2,GDMA0_CHANNEL2_IRQ,0},
|
||||
{0,3,GDMA0_CHANNEL3_IRQ,0},
|
||||
{0,4,GDMA0_CHANNEL4_IRQ,0},
|
||||
{0,5,GDMA0_CHANNEL5_IRQ,0},
|
||||
|
||||
{0xff,0,0,0} // end
|
||||
};
|
||||
|
||||
const HAL_GDMA_CHNL Uart2_RX_GDMA_Chnl_Option[] = {
|
||||
{1,0,GDMA1_CHANNEL0_IRQ,0},
|
||||
{1,1,GDMA1_CHANNEL1_IRQ,0},
|
||||
{1,2,GDMA1_CHANNEL2_IRQ,0},
|
||||
{1,3,GDMA1_CHANNEL3_IRQ,0},
|
||||
{1,4,GDMA1_CHANNEL4_IRQ,0},
|
||||
{1,5,GDMA1_CHANNEL5_IRQ,0},
|
||||
|
||||
{0xff,0,0,0} // end
|
||||
};
|
||||
|
||||
VOID
|
||||
HalRuartOpInit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_RUART_OP pHalRuartOp = (PHAL_RUART_OP) Data;
|
||||
|
||||
pHalRuartOp->HalRuartAdapterLoadDef = HalRuartAdapterLoadDefRtl8195a;
|
||||
pHalRuartOp->HalRuartTxGdmaLoadDef = HalRuartTxGdmaLoadDefRtl8195a;
|
||||
pHalRuartOp->HalRuartRxGdmaLoadDef = HalRuartRxGdmaLoadDefRtl8195a;
|
||||
pHalRuartOp->HalRuartResetRxFifo = HalRuartResetRxFifoRtl8195a;
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
pHalRuartOp->HalRuartInit = HalRuartInitRtl8195a_V04;
|
||||
#else
|
||||
pHalRuartOp->HalRuartInit = HalRuartInitRtl8195a_Patch; // Hardware Init ROM code patch
|
||||
#endif
|
||||
pHalRuartOp->HalRuartDeInit = HalRuartDeInitRtl8195a; // Hardware Init
|
||||
pHalRuartOp->HalRuartPutC = HalRuartPutCRtl8195a; // Send a byte
|
||||
pHalRuartOp->HalRuartSend = HalRuartSendRtl8195a; // Polling mode Tx
|
||||
pHalRuartOp->HalRuartIntSend = HalRuartIntSendRtl8195a; // Interrupt mode Tx
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
pHalRuartOp->HalRuartDmaSend = HalRuartDmaSendRtl8195a_V04; // DMA mode Tx
|
||||
pHalRuartOp->HalRuartStopSend = HalRuartStopSendRtl8195a_V04; // Stop non-blocking TX
|
||||
#else
|
||||
pHalRuartOp->HalRuartDmaSend = HalRuartDmaSendRtl8195a_Patch; // DMA mode Tx
|
||||
pHalRuartOp->HalRuartStopSend = HalRuartStopSendRtl8195a_Patch; // Stop non-blocking TX
|
||||
#endif
|
||||
pHalRuartOp->HalRuartGetC = HalRuartGetCRtl8195a; // get a byte
|
||||
pHalRuartOp->HalRuartRecv = HalRuartRecvRtl8195a; // Polling mode Rx
|
||||
pHalRuartOp->HalRuartIntRecv = HalRuartIntRecvRtl8195a; // Interrupt mode Rx
|
||||
pHalRuartOp->HalRuartDmaRecv = HalRuartDmaRecvRtl8195a; // DMA mode Rx
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
pHalRuartOp->HalRuartStopRecv = HalRuartStopRecvRtl8195a_V04; // Stop non-blocking Rx
|
||||
#else
|
||||
pHalRuartOp->HalRuartStopRecv = HalRuartStopRecvRtl8195a_Patch; // Stop non-blocking Rx
|
||||
#endif
|
||||
pHalRuartOp->HalRuartGetIMR = HalRuartGetIMRRtl8195a;
|
||||
pHalRuartOp->HalRuartSetIMR = HalRuartSetIMRRtl8195a;
|
||||
pHalRuartOp->HalRuartGetDebugValue = HalRuartGetDebugValueRtl8195a;
|
||||
pHalRuartOp->HalRuartDmaInit = HalRuartDmaInitRtl8195a;
|
||||
pHalRuartOp->HalRuartRTSCtrl = HalRuartRTSCtrlRtl8195a;
|
||||
pHalRuartOp->HalRuartRegIrq = HalRuartRegIrqRtl8195a;
|
||||
pHalRuartOp->HalRuartIntEnable = HalRuartIntEnableRtl8195a;
|
||||
pHalRuartOp->HalRuartIntDisable = HalRuartIntDisableRtl8195a;
|
||||
}
|
||||
|
||||
/**
|
||||
* Load UART HAL default setting
|
||||
*
|
||||
* Call this function to load the default setting for UART HAL adapter
|
||||
*
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
HalRuartAdapterInit(
|
||||
PRUART_ADAPTER pRuartAdapter,
|
||||
u8 UartIdx
|
||||
)
|
||||
{
|
||||
PHAL_RUART_OP pHalRuartOp;
|
||||
PHAL_RUART_ADAPTER pHalRuartAdapter;
|
||||
|
||||
if (NULL == pRuartAdapter) {
|
||||
return;
|
||||
}
|
||||
|
||||
pHalRuartOp = pRuartAdapter->pHalRuartOp;
|
||||
pHalRuartAdapter = pRuartAdapter->pHalRuartAdapter;
|
||||
|
||||
if ((NULL == pHalRuartOp) || (NULL == pHalRuartAdapter)) {
|
||||
return;
|
||||
}
|
||||
|
||||
// Load default setting
|
||||
if (pHalRuartOp->HalRuartAdapterLoadDef != NULL) {
|
||||
pHalRuartOp->HalRuartAdapterLoadDef (pHalRuartAdapter, UartIdx);
|
||||
pHalRuartAdapter->IrqHandle.Priority = 6;
|
||||
}
|
||||
else {
|
||||
// Initial your UART HAL adapter here
|
||||
}
|
||||
|
||||
// Start to modify the defualt setting
|
||||
pHalRuartAdapter->PinmuxSelect = RUART0_MUX_TO_GPIOC;
|
||||
pHalRuartAdapter->BaudRate = 38400;
|
||||
|
||||
// pHalRuartAdapter->IrqHandle.IrqFun = (IRQ_FUN)_UartIrqHandle;
|
||||
// pHalRuartAdapter->IrqHandle.Data = (void *)pHalRuartAdapter;
|
||||
|
||||
// Register IRQ
|
||||
InterruptRegister(&pHalRuartAdapter->IrqHandle);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Load UART HAL GDMA default setting
|
||||
*
|
||||
* Call this function to load the default setting for UART GDMA
|
||||
*
|
||||
*
|
||||
*/
|
||||
HAL_Status
|
||||
HalRuartTxGdmaInit(
|
||||
PHAL_RUART_OP pHalRuartOp,
|
||||
PHAL_RUART_ADAPTER pHalRuartAdapter,
|
||||
PUART_DMA_CONFIG pUartGdmaConfig
|
||||
)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
HAL_GDMA_CHNL *pgdma_chnl;
|
||||
|
||||
if ((NULL == pHalRuartOp) || (NULL == pHalRuartAdapter) || (NULL == pUartGdmaConfig)) {
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
// Load default setting
|
||||
if (pHalRuartOp->HalRuartTxGdmaLoadDef != NULL) {
|
||||
pHalRuartOp->HalRuartTxGdmaLoadDef (pHalRuartAdapter, pUartGdmaConfig);
|
||||
pUartGdmaConfig->TxGdmaIrqHandle.Priority = 6;
|
||||
}
|
||||
else {
|
||||
// Initial your GDMA setting here
|
||||
}
|
||||
|
||||
// Start to patch the default setting
|
||||
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter;
|
||||
if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) {
|
||||
// The default GDMA Channel is not available, try others
|
||||
if (pHalRuartAdapter->UartIndex == 2) {
|
||||
// UART2 TX Only can use GDMA 0
|
||||
pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Uart2_TX_GDMA_Chnl_Option);
|
||||
}
|
||||
else {
|
||||
pgdma_chnl = HalGdmaChnlAlloc(NULL);
|
||||
}
|
||||
|
||||
if (pgdma_chnl == NULL) {
|
||||
// No Available DMA channel
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else {
|
||||
pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx;
|
||||
pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl;
|
||||
pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl;
|
||||
pUartGdmaConfig->TxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum;
|
||||
}
|
||||
}
|
||||
|
||||
// User can assign a Interrupt Handler here
|
||||
// pUartGdmaConfig->TxGdmaIrqHandle.Data = pHalRuartAdapter;
|
||||
// pUartGdmaConfig->TxGdmaIrqHandle.IrqFun = (IRQ_FUN)_UartTxDmaIrqHandle
|
||||
// pUartGdmaConfig->TxGdmaIrqHandle.Priority = 0x20;
|
||||
|
||||
pHalRuartOp->HalRuartDmaInit (pHalRuartAdapter);
|
||||
InterruptRegister(&pUartGdmaConfig->TxGdmaIrqHandle);
|
||||
InterruptEn(&pUartGdmaConfig->TxGdmaIrqHandle);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
VOID
|
||||
HalRuartTxGdmaDeInit(
|
||||
PUART_DMA_CONFIG pUartGdmaConfig
|
||||
)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
HAL_GDMA_CHNL GdmaChnl;
|
||||
|
||||
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter;
|
||||
GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
|
||||
GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
|
||||
GdmaChnl.IrqNum = pUartGdmaConfig->TxGdmaIrqHandle.IrqNum;
|
||||
HalGdmaChnlFree(&GdmaChnl);
|
||||
}
|
||||
|
||||
/**
|
||||
* Load UART HAL GDMA default setting
|
||||
*
|
||||
* Call this function to load the default setting for UART GDMA
|
||||
*
|
||||
*
|
||||
*/
|
||||
HAL_Status
|
||||
HalRuartRxGdmaInit(
|
||||
PHAL_RUART_OP pHalRuartOp,
|
||||
PHAL_RUART_ADAPTER pHalRuartAdapter,
|
||||
PUART_DMA_CONFIG pUartGdmaConfig
|
||||
)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
HAL_GDMA_CHNL *pgdma_chnl;
|
||||
|
||||
if ((NULL == pHalRuartOp) || (NULL == pHalRuartAdapter) || (NULL == pUartGdmaConfig)) {
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
// Load default setting
|
||||
if (pHalRuartOp->HalRuartRxGdmaLoadDef != NULL) {
|
||||
pHalRuartOp->HalRuartRxGdmaLoadDef (pHalRuartAdapter, pUartGdmaConfig);
|
||||
pUartGdmaConfig->RxGdmaIrqHandle.Priority = 6;
|
||||
}
|
||||
else {
|
||||
// Initial your GDMA setting here
|
||||
}
|
||||
|
||||
// Start to patch the default setting
|
||||
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pRxHalGdmaAdapter;
|
||||
if (HalGdmaChnlRegister(pHalGdmaAdapter->GdmaIndex, pHalGdmaAdapter->ChNum) != HAL_OK) {
|
||||
// The default GDMA Channel is not available, try others
|
||||
if (pHalRuartAdapter->UartIndex == 2) {
|
||||
// UART2 RX Only can use GDMA 1
|
||||
pgdma_chnl = HalGdmaChnlAlloc((HAL_GDMA_CHNL*)Uart2_RX_GDMA_Chnl_Option);
|
||||
}
|
||||
else {
|
||||
pgdma_chnl = HalGdmaChnlAlloc(NULL);
|
||||
}
|
||||
|
||||
if (pgdma_chnl == NULL) {
|
||||
// No Available DMA channel
|
||||
return HAL_BUSY;
|
||||
}
|
||||
else {
|
||||
pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx;
|
||||
pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl;
|
||||
pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl;
|
||||
pUartGdmaConfig->RxGdmaIrqHandle.IrqNum = pgdma_chnl->IrqNum;
|
||||
}
|
||||
}
|
||||
|
||||
// pUartGdmaConfig->RxGdmaIrqHandle.Data = pHalRuartAdapter;
|
||||
// pUartGdmaConfig->RxGdmaIrqHandle.IrqFun = (IRQ_FUN)_UartTxDmaIrqHandle;
|
||||
// pUartGdmaConfig->RxGdmaIrqHandle.Priority = 0x20;
|
||||
|
||||
pHalRuartOp->HalRuartDmaInit (pHalRuartAdapter);
|
||||
InterruptRegister(&pUartGdmaConfig->RxGdmaIrqHandle);
|
||||
InterruptEn(&pUartGdmaConfig->RxGdmaIrqHandle);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
VOID
|
||||
HalRuartRxGdmaDeInit(
|
||||
PUART_DMA_CONFIG pUartGdmaConfig
|
||||
)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
HAL_GDMA_CHNL GdmaChnl;
|
||||
|
||||
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pRxHalGdmaAdapter;
|
||||
GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
|
||||
GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
|
||||
GdmaChnl.IrqNum = pUartGdmaConfig->RxGdmaIrqHandle.IrqNum;
|
||||
HalGdmaChnlFree(&GdmaChnl);
|
||||
}
|
||||
|
||||
/**
|
||||
* Hook a RX indication callback
|
||||
*
|
||||
* To hook a callback function which will be called when a got a RX byte
|
||||
*
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
HalRuartRxIndHook(
|
||||
PRUART_ADAPTER pRuartAdapter,
|
||||
VOID *pCallback,
|
||||
VOID *pPara
|
||||
)
|
||||
{
|
||||
PHAL_RUART_ADAPTER pHalRuartAdapter = pRuartAdapter->pHalRuartAdapter;
|
||||
|
||||
pHalRuartAdapter->RxDRCallback = (void (*)(void*))pCallback;
|
||||
pHalRuartAdapter->RxDRCbPara = pPara;
|
||||
|
||||
// enable RX data ready interrupt
|
||||
pHalRuartAdapter->Interrupts |= RUART_IER_ERBI | RUART_IER_ELSI;
|
||||
pRuartAdapter->pHalRuartOp->HalRuartSetIMR(pHalRuartAdapter);
|
||||
}
|
||||
|
||||
|
||||
HAL_Status
|
||||
HalRuartResetTxFifo(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
return (HalRuartResetTxFifoRtl8195a(Data));
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
HalRuartSetBaudRate(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
return HalRuartSetBaudRateRtl8195a_V04(Data);
|
||||
#else
|
||||
return HalRuartSetBaudRateRtl8195a(Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
HalRuartInit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
HAL_Status ret;
|
||||
PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data;
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
REG_POWER_STATE UartPwrState;
|
||||
#endif
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
pHalRuartAdapter->pDefaultBaudRateTbl = (uint32_t*)BAUDRATE_166_ROM_V04;
|
||||
pHalRuartAdapter->pDefaultOvsrRTbl = (uint8_t*)OVSR_166_ROM_V04;
|
||||
pHalRuartAdapter->pDefaultOvsrAdjTbl = (uint16_t*)OVSR_ADJ_166_ROM_V04;
|
||||
pHalRuartAdapter->pDefaultDivTbl = (uint16_t*)DIV_166_ROM_V04;
|
||||
ret = HalRuartInitRtl8195a_V04(Data);
|
||||
#else
|
||||
pHalRuartAdapter->pDefaultBaudRateTbl = (uint32_t*)DEF_BAUDRATE_TABLE;
|
||||
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
|
||||
u8 chip_ver;
|
||||
|
||||
chip_ver = HalRuartGetChipVerRtl8195a();
|
||||
if (chip_ver < 2) {
|
||||
pHalRuartAdapter->pDefaultOvsrRTbl = (uint8_t*)DEF_OVSR_B_CUT;
|
||||
pHalRuartAdapter->pDefaultDivTbl = (uint16_t*)DEF_DIV_B_CUT;
|
||||
pHalRuartAdapter->pDefOvsrAdjBitTbl_10 = (uint8_t*)DEF_OVSR_ADJ_BITS_B_CUT_10B;
|
||||
pHalRuartAdapter->pDefOvsrAdjBitTbl_9 = (uint8_t*)DEF_OVSR_ADJ_BITS_B_CUT_9B;
|
||||
pHalRuartAdapter->pDefOvsrAdjBitTbl_8 = (uint8_t*)DEF_OVSR_ADJ_BITS_B_CUT_8B;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
pHalRuartAdapter->pDefaultOvsrRTbl = (uint8_t*)DEF_OVSR_C_CUT;
|
||||
pHalRuartAdapter->pDefaultDivTbl = (uint16_t*)DEF_DIV_C_CUT;
|
||||
pHalRuartAdapter->pDefOvsrAdjBitTbl_10 = (uint8_t*)DEF_OVSR_ADJ_BITS_C_CUT_10B;
|
||||
pHalRuartAdapter->pDefOvsrAdjBitTbl_9 = (uint8_t*)DEF_OVSR_ADJ_BITS_C_CUT_9B;
|
||||
pHalRuartAdapter->pDefOvsrAdjBitTbl_8 = (uint8_t*)DEF_OVSR_ADJ_BITS_C_CUT_8B;
|
||||
}
|
||||
pHalRuartAdapter->pDefOvsrAdjTbl_10 = (uint16_t*)ovsr_adj_table_10bit;
|
||||
pHalRuartAdapter->pDefOvsrAdjTbl_9 = (uint16_t*)ovsr_adj_table_9bit;
|
||||
pHalRuartAdapter->pDefOvsrAdjTbl_8 = (uint16_t*)ovsr_adj_table_8bit;
|
||||
|
||||
ret = HalRuartInitRtl8195a_Patch(Data);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
if(ret == HAL_OK) {
|
||||
// To register a new peripheral device power state
|
||||
UartPwrState.FuncIdx = UART0 + pHalRuartAdapter->UartIndex;
|
||||
UartPwrState.PwrState = ACT;
|
||||
RegPowerState(UartPwrState);
|
||||
}
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
VOID
|
||||
HalRuartDeInit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
REG_POWER_STATE UartPwrState;
|
||||
PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data;
|
||||
u8 HwState;
|
||||
|
||||
UartPwrState.FuncIdx = UART0 + pHalRuartAdapter->UartIndex;
|
||||
QueryRegPwrState(UartPwrState.FuncIdx, &(UartPwrState.PwrState), &HwState);
|
||||
|
||||
// if the power state isn't ACT, then switch the power state back to ACT first
|
||||
if ((UartPwrState.PwrState != ACT) && (UartPwrState.PwrState != INACT)) {
|
||||
HalRuartEnable(Data);
|
||||
QueryRegPwrState(UartPwrState.FuncIdx, &(UartPwrState.PwrState), &HwState);
|
||||
}
|
||||
|
||||
if (UartPwrState.PwrState == ACT) {
|
||||
UartPwrState.PwrState = INACT;
|
||||
RegPowerState(UartPwrState);
|
||||
}
|
||||
#endif
|
||||
|
||||
HalRuartDeInitRtl8195a(Data);
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
HalRuartDisable(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
HAL_Status ret;
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
REG_POWER_STATE UartPwrState;
|
||||
PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data;
|
||||
#endif
|
||||
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
ret = HalRuartDisableRtl8195a_V04(Data);
|
||||
#else
|
||||
ret = HalRuartDisableRtl8195a(Data);
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
if (ret == HAL_OK) {
|
||||
UartPwrState.FuncIdx = UART0 + pHalRuartAdapter->UartIndex;
|
||||
UartPwrState.PwrState = SLPCG;
|
||||
RegPowerState(UartPwrState);
|
||||
}
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
HalRuartEnable(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
HAL_Status ret;
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
REG_POWER_STATE UartPwrState;
|
||||
PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data;
|
||||
#endif
|
||||
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
ret = HalRuartEnableRtl8195a_V04(Data);
|
||||
#else
|
||||
ret = HalRuartEnableRtl8195a(Data);
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
if (ret == HAL_OK) {
|
||||
UartPwrState.FuncIdx = UART0 + pHalRuartAdapter->UartIndex;
|
||||
UartPwrState.PwrState = ACT;
|
||||
RegPowerState(UartPwrState);
|
||||
}
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
HalRuartFlowCtrl(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
HAL_Status ret;
|
||||
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
ret = HalRuartFlowCtrlRtl8195a_V04((VOID *)Data);
|
||||
#else
|
||||
ret = HalRuartFlowCtrlRtl8195a((VOID *)Data);
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
VOID
|
||||
HalRuartEnterCritical(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
HalRuartEnterCriticalRtl8195a_V04(Data);
|
||||
#else
|
||||
HalRuartEnterCriticalRtl8195a(Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
HalRuartExitCritical(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
HalRuartExitCriticalRtl8195a_V04(Data);
|
||||
#else
|
||||
HalRuartExitCriticalRtl8195a(Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue