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pvvx 2016-09-13 12:31:00 +03:00
parent aa9624efbe
commit 56693eef0d
125 changed files with 45637 additions and 1 deletions
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1069
lib/cpu/cortex/cortex.c Normal file
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lib/cpu/cortex/cortex.h Normal file
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#ifndef _CORTEX_H_
#define _CORTEX_H_
#include <stdint.h>
typedef struct{
volatile uint32_t ISER[8];
uint32_t RESERVED1[24];
volatile uint32_t ICER[8];
uint32_t RESERVED2[24];
volatile uint32_t ISPR[8];
uint32_t RESERVED3[24];
volatile uint32_t ICPR[8];
uint32_t RESERVED4[24];
volatile uint32_t IABR[8];
uint32_t RESERVED5[56];
volatile uint32_t IPR[32];
}NVIC_TypeDef;
typedef struct{
uint32_t RESERVED1[2];
volatile uint32_t ACTLR;
uint32_t RESERVED2[829];
volatile const uint32_t CPUID;
volatile uint32_t ICSR;
volatile uint32_t VTOR;
volatile uint32_t AIRCR;
volatile uint32_t SCR;
volatile uint32_t CCR;
volatile uint32_t SHPR[3];
volatile uint32_t SHCSR;
volatile uint32_t CFSR;
volatile uint32_t HFSR;
volatile uint32_t DFSR;
volatile uint32_t MMFAR;
volatile uint32_t BFAR;
volatile uint32_t AFSR;
volatile const uint32_t PFR[2];
volatile const uint32_t DFR;
volatile const uint32_t AFR;
volatile const uint32_t MMFR[4];
volatile const uint32_t ISAR[5];
uint32_t RESERVED3[5];
volatile uint32_t CPACR;
}SCB_TypeDef;
#define NVIC ((NVIC_TypeDef *)0xE000E100)
#define SCB ((SCB_TypeDef *)0xE000E000)
// SCB_AIRCR
#define SCB_AIRCR_VECTRESET (((uint32_t)0x0001) << 0)
#define SCB_AIRCR_VECTCLRACTIVE (((uint32_t)0x0001) << 1)
#define SCB_AIRCR_SYSRESETREQ (((uint32_t)0x0001) << 2)
#define SCB_AIRCR_PRIGROUP (((uint32_t)0x0007) << 8)
#define SCB_AIRCR_VECTKEY (((uint32_t)0xFFFF) << 16)
#define SCB_AIRCR_VECTKEYSTAT (((uint32_t)0xFFFF) << 16)
// SCB_CPACR
#define SCB_CPACR_CP10 (((uint32_t)0x03) << 20)
#define SCB_CPACR_CP11 (((uint32_t)0x03) << 22)
#define cortex_interrupt_set_priority(i, p) (NVIC->IPR[(i) >> 2] = ((NVIC->IPR[(i) >> 2] & ~(((uint32_t)0xFF) << (((i) & 0x03) << 3))) | (((uint32_t)p) << (((i) & 0x03) << 3))))
#define cortex_interrupt_enable(i) (NVIC->ISER[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
#define cortex_interrupt_disable(i) (NVIC->ICER[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
#define cortex_interrupt_clear(i) (NVIC->ICPR[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
#define cortex_interrupts_disable() __asm__("cpsid f")
#define cortex_interrupts_enable() __asm__("cpsie f")
#define interrupts_disable() __asm__("cpsid f")
#define interrupts_enable() __asm__("cpsie f")
#define CORTEX_ISR(n) _CORTEX_ISR(n)
#define _CORTEX_ISR(n) void __attribute__((interrupt)) CORTEX_INTERRUPT_##n##_Handler()
void cortex_bootstrap(void *start) __attribute__ ((noreturn));
void cortex_reboot() __attribute__ ((noreturn));
#endif

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lib/cpu/cortex/cortex.ocd Normal file
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proc cortex_bootstrap {start} {
# disable interrupts
reg faultmask 0x01
set vectors ""
mem2array vectors 32 $start 2
reg sp $vectors(0)
reg pc $vectors(1)
resume
}
proc cortex_reboot {} {
mww 0xE000ED0C 0x05FA0007
}

737
lib/cpu/rtl8710/export-rom_v03.txt Normal file
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SECTIONS
{
__vectors_table = 0x0;
Reset_Handler = 0x101;
NMI_Handler = 0x109;
HardFault_Handler = 0x10d;
MemManage_Handler = 0x121;
BusFault_Handler = 0x125;
UsageFault_Handler = 0x129;
HalLogUartInit = 0x201;
HalSerialPutcRtl8195a = 0x2d9;
HalSerialGetcRtl8195a = 0x309;
HalSerialGetIsrEnRegRtl8195a = 0x329;
HalSerialSetIrqEnRegRtl8195a = 0x335;
HalCpuClkConfig = 0x341;
HalGetCpuClk = 0x355;
HalRomInfo = 0x39d;
HalGetRomInfo = 0x3b5;
HalResetVsr = 0x3c5;
HalDelayUs = 0x899;
HalNMIHandler = 0x8e1;
HalHardFaultHandler = 0x911;
HalMemManageHandler = 0xc09;
HalBusFaultHandler = 0xc39;
HalUsageFaultHandler = 0xc69;
HalUart0PinCtrlRtl8195A = 0xcfd;
HalUart1PinCtrlRtl8195A = 0xdc9;
HalUart2PinCtrlRtl8195A = 0xe9d;
HalSPI0PinCtrlRtl8195A = 0xf75;
HalSPI1PinCtrlRtl8195A = 0x1015;
HalSPI2PinCtrlRtl8195A = 0x10e5;
HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
HalI2C0PinCtrlRtl8195A = 0x1275;
HalI2C1PinCtrlRtl8195A = 0x1381;
HalI2C2PinCtrlRtl8195A = 0x1459;
HalI2C3PinCtrlRtl8195A = 0x1529;
HalI2S0PinCtrlRtl8195A = 0x1639;
HalI2S1PinCtrlRtl8195A = 0x176d;
HalPCM0PinCtrlRtl8195A = 0x1845;
HalPCM1PinCtrlRtl8195A = 0x1949;
HalSDIODPinCtrlRtl8195A = 0x1a1d;
HalSDIOHPinCtrlRtl8195A = 0x1a6d;
HalMIIPinCtrlRtl8195A = 0x1ab9;
HalWLLEDPinCtrlRtl8195A = 0x1b51;
HalWLANT0PinCtrlRtl8195A = 0x1c0d;
HalWLANT1PinCtrlRtl8195A = 0x1c61;
HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
HalNFCPinCtrlRtl8195A = 0x1d59;
HalPWM0PinCtrlRtl8195A = 0x1da9;
HalPWM1PinCtrlRtl8195A = 0x1ead;
HalPWM2PinCtrlRtl8195A = 0x1fb5;
HalPWM3PinCtrlRtl8195A = 0x20b1;
HalETE0PinCtrlRtl8195A = 0x21b9;
HalETE1PinCtrlRtl8195A = 0x22c1;
HalETE2PinCtrlRtl8195A = 0x23c9;
HalETE3PinCtrlRtl8195A = 0x24d1;
HalEGTIMPinCtrlRtl8195A = 0x25d9;
HalSPIFlashPinCtrlRtl8195A = 0x2679;
HalSDRPinCtrlRtl8195A = 0x2725;
HalJTAGPinCtrlRtl8195A = 0x280d;
HalTRACEPinCtrlRtl8195A = 0x2861;
HalLOGUartPinCtrlRtl8195A = 0x28b9;
HalLOGUartIRPinCtrlRtl8195A = 0x291d;
HalSICPinCtrlRtl8195A = 0x2981;
HalEEPROMPinCtrlRtl8195A = 0x29d9;
HalDEBUGPinCtrlRtl8195A = 0x2a31;
HalPinCtrlRtl8195A = 0x2b39;
SpicRxCmdRtl8195A = 0x2e5d;
SpicWaitBusyDoneRtl8195A = 0x2ea5;
SpicGetFlashStatusRtl8195A = 0x2eb5;
SpicWaitWipDoneRtl8195A = 0x2f55;
SpicTxCmdRtl8195A = 0x2f6d;
SpicSetFlashStatusRtl8195A = 0x2fc1;
SpicCmpDataForCalibrationRtl8195A = 0x3049;
SpicLoadInitParaFromClockRtl8195A = 0x3081;
SpicInitRtl8195A = 0x30e5;
SpicEraseFlashRtl8195A = 0x31bd;
SpiFlashApp = 0x3279;
HalPeripheralIntrHandle = 0x33b5;
HalSysOnIntrHandle = 0x3439;
HalWdgIntrHandle = 0x3485;
HalTimer0IntrHandle = 0x34d5;
HalTimer1IntrHandle = 0x3525;
HalI2C3IntrHandle = 0x3575;
HalTimer2To7IntrHandle = 0x35c5;
HalSpi0IntrHandle = 0x3615;
HalGpioIntrHandle = 0x3665;
HalUart0IntrHandle = 0x36b5;
HalSpiFlashIntrHandle = 0x3705;
HalUsbOtgIntrHandle = 0x3755;
HalSdioHostIntrHandle = 0x37a5;
HalI2s0OrPcm0IntrHandle = 0x37f5;
HalI2s1OrPcm1IntrHandle = 0x3845;
HalWlDmaIntrHandle = 0x3895;
HalWlProtocolIntrHandle = 0x38e5;
HalCryptoIntrHandle = 0x3935;
HalGmacIntrHandle = 0x3985;
HalGdma0Ch0IntrHandle = 0x39d5;
HalGdma0Ch1IntrHandle = 0x3a25;
HalGdma0Ch2IntrHandle = 0x3a75;
HalGdma0Ch3IntrHandle = 0x3ac5;
HalGdma0Ch4IntrHandle = 0x3b15;
HalGdma0Ch5IntrHandle = 0x3b65;
HalGdma1Ch0IntrHandle = 0x3bb5;
HalGdma1Ch1IntrHandle = 0x3c05;
HalGdma1Ch2IntrHandle = 0x3c55;
HalGdma1Ch3IntrHandle = 0x3ca5;
HalGdma1Ch4IntrHandle = 0x3cf5;
HalGdma1Ch5IntrHandle = 0x3d45;
HalSdioDeviceIntrHandle = 0x3d95;
VectorTableInitRtl8195A = 0x3de5;
VectorTableInitForOSRtl8195A = 0x4019;
VectorIrqRegisterRtl8195A = 0x4029;
VectorIrqUnRegisterRtl8195A = 0x4091;
VectorIrqEnRtl8195A = 0x40f1;
VectorIrqDisRtl8195A = 0x418d;
_UartRxDmaIrqHandle = 0x422d;
HalRuartPutCRtl8195a = 0x4281;
HalRuartGetCRtl8195a = 0x429d;
HalRuartRTSCtrlRtl8195a = 0x42bd;
HalRuartGetDebugValueRtl8195a = 0x42e1;
HalRuartGetIMRRtl8195a = 0x43e1;
HalRuartSetIMRRtl8195a = 0x442d;
_UartIrqHandle = 0x4465;
HalRuartDmaInitRtl8195a = 0x4681;
HalRuartIntDisableRtl8195a = 0x4845;
HalRuartDeInitRtl8195a = 0x4855;
HalRuartIntEnableRtl8195a = 0x4985;
_UartTxDmaIrqHandle = 0x4995;
HalRuartRegIrqRtl8195a = 0x49d1;
HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
RuartLock = 0x4cc9;
RuartUnLock = 0x4ced;
HalRuartIntSendRtl8195a = 0x4d09;
HalRuartDmaSendRtl8195a = 0x4e35;
HalRuartStopSendRtl8195a = 0x4f89;
HalRuartIntRecvRtl8195a = 0x504d;
HalRuartDmaRecvRtl8195a = 0x51ad;
HalRuartStopRecvRtl8195a = 0x52cd;
RuartIsTimeout = 0x5385;
HalRuartSendRtl8195a = 0x53b1;
HalRuartRecvRtl8195a = 0x5599;
RuartResetRxFifoRtl8195a = 0x5751;
HalRuartResetRxFifoRtl8195a = 0x5775;
HalRuartInitRtl8195a = 0x5829;
HalGdmaOnOffRtl8195a = 0x5df1;
HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
HalGdmaChEnRtl8195a = 0x5e51;
HalGdmaChDisRtl8195a = 0x5e6d;
HalGdamChInitRtl8195a = 0x5e91;
HalGdmaChSetingRtl8195a = 0x5ebd;
HalGdmaChIsrCleanRtl8195a = 0x6419;
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
HalEFUSEPowerSwitch8195AROM = 0x6561;
HALEFUSEOneByteReadROM = 0x65f9;
HALEFUSEOneByteWriteROM = 0x6699;
rtl_memcmpb_v1_00 = 0x681d;
rtl_random_v1_00 = 0x6861;
rtl_align_to_be32_v1_00 = 0x6881;
rtl_memsetw_v1_00 = 0x6899;
rtl_memsetb_v1_00 = 0x68ad;
rtl_memcpyw_v1_00 = 0x68bd;
rtl_memcpyb_v1_00 = 0x68dd;
rtl_memDump_v1_00 = 0x68f5;
rtl_AES_set_encrypt_key = 0x6901;
rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
rtl_cryptoEngine_init_v1_00 = 0x6ea9;
rtl_cryptoEngine_exit_v1_00 = 0x7055;
rtl_cryptoEngine_reset_v1_00 = 0x70b1;
rtl_cryptoEngine_v1_00 = 0x70ed;
rtl_crypto_cipher_init_v1_00 = 0x7c69;
rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
HalSsiPinmuxEnableRtl8195a = 0x7cd5;
HalSsiEnableRtl8195a = 0x7e45;
HalSsiDisableRtl8195a = 0x7ef9;
HalSsiLoadSettingRtl8195a = 0x7fad;
HalSsiSetInterruptMaskRtl8195a = 0x8521;
HalSsiGetInterruptMaskRtl8195a = 0x85c9;
HalSsiSetSclkPolarityRtl8195a = 0x863d;
HalSsiSetSclkPhaseRtl8195a = 0x8715;
HalSsiWriteRtl8195a = 0x87e9;
HalSsiSetDeviceRoleRtl8195a = 0x8861;
HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
HalSsiReadRtl8195a = 0x89b9;
HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
HalSsiGetStatusRtl8195a = 0x8b1d;
HalSsiWriteableRtl8195a = 0x8b91;
HalSsiReadableRtl8195a = 0x8c09;
HalSsiBusyRtl8195a = 0x8c81;
HalSsiReadInterruptRtl8195a = 0x8cf9;
HalSsiWriteInterruptRtl8195a = 0x8efd;
HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
HalSsiGetInterruptStatusRtl8195a = 0x90d9;
HalSsiInterruptEnableRtl8195a = 0x914d;
HalSsiInterruptDisableRtl8195a = 0x9299;
HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
HalSsiInitRtl8195a = 0x94d1;
_SsiReadInterrupt = 0x9ba5;
_SsiWriteInterrupt = 0x9db1;
_SsiIrqHandle = 0x9eb1;
HalI2CWrite32 = 0xa061;
HalI2CRead32 = 0xa09d;
HalI2CDeInit8195a = 0xa0dd;
HalI2CSendRtl8195a = 0xa1f1;
HalI2CReceiveRtl8195a = 0xa25d;
HalI2CEnableRtl8195a = 0xa271;
HalI2CIntrCtrl8195a = 0xa389;
HalI2CReadRegRtl8195a = 0xa3a1;
HalI2CWriteRegRtl8195a = 0xa3b1;
HalI2CSetCLKRtl8195a = 0xa3c5;
HalI2CMassSendRtl8195a = 0xa6e9;
HalI2CClrIntrRtl8195a = 0xa749;
HalI2CClrAllIntrRtl8195a = 0xa761;
HalI2CInit8195a = 0xa775;
HalI2CDMACtrl8195a = 0xaa31;
RtkI2CIoCtrl = 0xaa61;
RtkI2CPowerCtrl = 0xaa65;
HalI2COpInit = 0xaa69;
I2CIsTimeout = 0xac65;
I2CTXGDMAISRHandle = 0xb435;
I2CRXGDMAISRHandle = 0xb4c1;
RtkI2CIrqInit = 0xb54d;
RtkI2CIrqDeInit = 0xb611;
RtkI2CPinMuxInit = 0xb675;
RtkI2CPinMuxDeInit = 0xb7c9;
RtkI2CDMAInit = 0xb955;
RtkI2CInit = 0xbc95;
RtkI2CDMADeInit = 0xbdad;
RtkI2CDeInit = 0xbe4d;
RtkI2CSendUserAddr = 0xbee5;
RtkI2CSend = 0xc07d;
RtkI2CLoadDefault = 0xce51;
RtkSalI2COpInit = 0xcf21;
HalI2SWrite32 = 0xcf65;
HalI2SRead32 = 0xcf85;
HalI2SDeInitRtl8195a = 0xcfa9;
HalI2STxRtl8195a = 0xcfc9;
HalI2SRxRtl8195a = 0xd011;
HalI2SEnableRtl8195a = 0xd05d;
HalI2SIntrCtrlRtl8195a = 0xd0b1;
HalI2SReadRegRtl8195a = 0xd0d1;
HalI2SClrIntrRtl8195a = 0xd0dd;
HalI2SClrAllIntrRtl8195a = 0xd0fd;
HalI2SInitRtl8195a = 0xd11d;
GPIO_GetIPPinName_8195a = 0xd2e5;
GPIO_GetChipPinName_8195a = 0xd331;
GPIO_PullCtrl_8195a = 0xd39d;
GPIO_FuncOn_8195a = 0xd421;
GPIO_FuncOff_8195a = 0xd481;
GPIO_Int_Mask_8195a = 0xd4e9;
GPIO_Int_SetType_8195a = 0xd511;
HAL_GPIO_IrqHandler_8195a = 0xd5fd;
HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
HAL_GPIO_IntCtrl_8195a = 0xd6cd;
HAL_GPIO_Init_8195a = 0xd805;
HAL_GPIO_DeInit_8195a = 0xdac1;
HAL_GPIO_ReadPin_8195a = 0xdbd1;
HAL_GPIO_WritePin_8195a = 0xdc91;
HAL_GPIO_RegIrq_8195a = 0xddad;
HAL_GPIO_UnRegIrq_8195a = 0xddf5;
HAL_GPIO_UserRegIrq_8195a = 0xde15;
HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
HAL_GPIO_MaskIrq_8195a = 0xdfc1;
HAL_GPIO_UnMaskIrq_8195a = 0xe061;
HAL_GPIO_IntDebounce_8195a = 0xe101;
HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
HAL_GPIO_PullCtrl_8195a = 0xe1c9;
DumpForOneBytes = 0xe259;
CmdRomHelp = 0xe419;
CmdWriteWord = 0xe491;
CmdDumpHelfWord = 0xe505;
CmdDumpWord = 0xe5f1;
CmdDumpByte = 0xe6f5;
CmdSpiFlashTool = 0xe751;
GetRomCmdNum = 0xe7a9;
CmdWriteByte = 0xe7ad;
Isspace = 0xe7ed;
Strtoul = 0xe801;
ArrayInitialize = 0xe8b1;
GetArgc = 0xe8c9;
GetArgv = 0xe8f9;
UartLogCmdExecute = 0xe95d;
UartLogShowBackSpace = 0xe9fd;
UartLogRecallOldCmd = 0xea39;
UartLogHistoryCmd = 0xea71;
UartLogCmdChk = 0xeadd;
UartLogIrqHandle = 0xebf5;
RtlConsolInit = 0xecc5;
RtlConsolTaskRom = 0xed49;
RtlExitConsol = 0xed79;
RtlConsolRom = 0xedcd;
HalTimerOpInit = 0xee0d;
HalTimerIrq2To7Handle = 0xee59;
HalGetTimerIdRtl8195a = 0xef09;
HalTimerInitRtl8195a = 0xef3d;
HalTimerDisRtl8195a = 0xf069;
HalTimerEnRtl8195a = 0xf089;
HalTimerReadCountRtl8195a = 0xf0a9;
HalTimerIrqClearRtl8195a = 0xf0bd;
HalTimerDumpRegRtl8195a = 0xf0d1;
VSprintf = 0xf129;
DiagPrintf = 0xf39d;
DiagSPrintf = 0xf3b9;
DiagSnPrintf = 0xf3d1;
prvDiagPrintf = 0xf3ed;
prvDiagSPrintf = 0xf40d;
_memcmp = 0xf429;
_memcpy = 0xf465;
_memset = 0xf511;
Rand = 0xf585;
_strncpy = 0xf60d;
_strcpy = 0xf629;
prvStrCpy = 0xf639;
_strlen = 0xf651;
_strnlen = 0xf669;
prvStrLen = 0xf699;
_strcmp = 0xf6b1;
_strncmp = 0xf6d1;
prvStrCmp = 0xf719;
StrUpr = 0xf749;
prvAtoi = 0xf769;
prvStrStr = 0xf7bd;
_strsep = 0xf7d5;
skip_spaces = 0xf815;
skip_atoi = 0xf831;
_parse_integer_fixup_radix = 0xf869;
_parse_integer = 0xf8bd;
simple_strtoull = 0xf915;
simple_strtoll = 0xf945;
simple_strtoul = 0xf965;
simple_strtol = 0xf96d;
_vsscanf = 0xf985;
_sscanf = 0xff71;
div_u64 = 0xff91;
div_s64 = 0xff99;
div_u64_rem = 0xffa1;
div_s64_rem = 0xffb1;
_strpbrk = 0xffc1;
_strchr = 0xffed;
aes_set_key = 0x10005;
aes_encrypt = 0x103d1;
aes_decrypt = 0x114a5;
AES_WRAP = 0x125c9;
AES_UnWRAP = 0x12701;
crc32_get = 0x12861;
arc4_byte = 0x12895;
rt_arc4_init = 0x128bd;
rt_arc4_crypt = 0x12901;
rt_md5_init = 0x131c1;
rt_md5_append = 0x131f5;
rt_md5_final = 0x1327d;
rt_md5_hmac = 0x132d5;
rtw_get_bit_value_from_ieee_value = 0x13449;
rtw_is_cckrates_included = 0x13475;
rtw_is_cckratesonly_included = 0x134b5;
rtw_check_network_type = 0x134dd;
rtw_set_fixed_ie = 0x1350d;
rtw_set_ie = 0x1352d;
rtw_get_ie = 0x1355d;
rtw_set_supported_rate = 0x13591;
rtw_get_rateset_len = 0x13611;
rtw_get_wpa_ie = 0x1362d;
rtw_get_wpa2_ie = 0x136c9;
rtw_get_wpa_cipher_suite = 0x13701;
rtw_get_wpa2_cipher_suite = 0x13769;
rtw_parse_wpa_ie = 0x137d1;
rtw_parse_wpa2_ie = 0x138ad;
rtw_get_sec_ie = 0x13965;
rtw_get_wps_ie = 0x13a15;
rtw_get_wps_attr = 0x13a99;
rtw_get_wps_attr_content = 0x13b49;
rtw_ieee802_11_parse_elems = 0x13b91;
str_2char2num = 0x13d9d;
key_2char2num = 0x13db9;
convert_ip_addr = 0x13dd1;
rom_psk_PasswordHash = 0x13e9d;
rom_psk_CalcGTK = 0x13ed5;
rom_psk_CalcPTK = 0x13f69;
wep_80211_encrypt = 0x14295;
wep_80211_decrypt = 0x142f5;
tkip_micappendbyte = 0x14389;
rtw_secmicsetkey = 0x143d9;
rtw_secmicappend = 0x14419;
rtw_secgetmic = 0x14435;
rtw_seccalctkipmic = 0x1449d;
tkip_phase1 = 0x145a5;
tkip_phase2 = 0x14725;
tkip_80211_encrypt = 0x14941;
tkip_80211_decrypt = 0x149d5;
aes1_encrypt = 0x14a8d;
aesccmp_construct_mic_iv = 0x14c65;
aesccmp_construct_mic_header1 = 0x14ccd;
aesccmp_construct_mic_header2 = 0x14d21;
aesccmp_construct_ctr_preload = 0x14db5;
aes_80211_encrypt = 0x14e29;
aes_80211_decrypt = 0x151ad;
_sha1_process_message_block = 0x155b9;
_sha1_pad_message = 0x15749;
rt_sha1_init = 0x157e5;
rt_sha1_update = 0x15831;
rt_sha1_finish = 0x158a9;
rt_hmac_sha1 = 0x15909;
rom_aes_128_cbc_encrypt = 0x15a65;
rom_aes_128_cbc_decrypt = 0x15ae1;
rom_rijndaelKeySetupEnc = 0x15b5d;
rom_aes_decrypt_init = 0x15c39;
rom_aes_internal_decrypt = 0x15d15;
rom_aes_decrypt_deinit = 0x16071;
rom_aes_encrypt_init = 0x16085;
rom_aes_internal_encrypt = 0x1609d;
rom_aes_encrypt_deinit = 0x16451;
bignum_init = 0x17b35;
bignum_deinit = 0x17b61;
bignum_get_unsigned_bin_len = 0x17b81;
bignum_get_unsigned_bin = 0x17b85;
bignum_set_unsigned_bin = 0x17c21;
bignum_cmp = 0x17cd1;
bignum_cmp_d = 0x17cd5;
bignum_add = 0x17cfd;
bignum_sub = 0x17d0d;
bignum_mul = 0x17d1d;
bignum_exptmod = 0x17d2d;
WPS_realloc = 0x17d51;
os_zalloc = 0x17d99;
rom_hmac_sha256_vector = 0x17dc1;
rom_hmac_sha256 = 0x17ebd;
rom_sha256_vector = 0x18009;
phy_CalculateBitShift = 0x18221;
PHY_SetBBReg_8195A = 0x18239;
PHY_QueryBBReg_8195A = 0x18279;
ROM_odm_QueryRxPwrPercentage = 0x1829d;
ROM_odm_EVMdbToPercentage = 0x182bd;
ROM_odm_SignalScaleMapping_8195A = 0x182e5;
ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
ROM_odm_SetEDCCAThreshold = 0x18721;
ROM_odm_SetTRxMux = 0x18749;
ROM_odm_SetCrystalCap = 0x18771;
ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
ROM_ODM_CfoTrackingReset = 0x187e9;
ROM_odm_CfoTrackingFlow = 0x18811;
curve25519_donna = 0x1965d;
aes_test_alignment_detection = 0x1a391;
aes_mode_reset = 0x1a3ed;
aes_ecb_encrypt = 0x1a3f9;
aes_ecb_decrypt = 0x1a431;
aes_cbc_encrypt = 0x1a469;
aes_cbc_decrypt = 0x1a579;
aes_cfb_encrypt = 0x1a701;
aes_cfb_decrypt = 0x1a9e5;
aes_ofb_crypt = 0x1acc9;
aes_ctr_crypt = 0x1af7d;
aes_encrypt_key128 = 0x1b289;
aes_encrypt_key192 = 0x1b2a5;
aes_encrypt_key256 = 0x1b2c1;
aes_encrypt_key = 0x1b2e1;
aes_decrypt_key128 = 0x1b351;
aes_decrypt_key192 = 0x1b36d;
aes_decrypt_key256 = 0x1b389;
aes_decrypt_key = 0x1b3a9;
aes_init = 0x1b419;
CRYPTO_chacha_20 = 0x1b41d;
CRYPTO_poly1305_init = 0x1bc25;
CRYPTO_poly1305_update = 0x1bd09;
CRYPTO_poly1305_finish = 0x1bd8d;
rom_sha512_starts = 0x1ceb5;
rom_sha512_update = 0x1d009;
rom_sha512_finish = 0x1d011;
rom_sha512 = 0x1d261;
rom_sha512_hmac_starts = 0x1d299;
rom_sha512_hmac_update = 0x1d35d;
rom_sha512_hmac_finish = 0x1d365;
rom_sha512_hmac_reset = 0x1d3b5;
rom_sha512_hmac = 0x1d3d1;
rom_sha512_hkdf = 0x1d40d;
rom_ed25519_gen_keypair = 0x1d501;
rom_ed25519_gen_signature = 0x1d505;
rom_ed25519_verify_signature = 0x1d51d;
rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
rom_ed25519_crypto_sign_detached = 0x1d579;
rom_ed25519_crypto_sign_verify_detached = 0x1d655;
rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
rom_ed25519_ge_p3_tobytes = 0x207d5;
rom_ed25519_ge_scalarmult_base = 0x20821;
rom_ed25519_ge_tobytes = 0x209e1;
rom_ed25519_sc_muladd = 0x20a2d;
rom_ed25519_sc_reduce = 0x2603d;
rtl_memchr_v1_00 = 0x28a4d;
rtl_memcmp_v1_00 = 0x28ae1;
rtl_memcpy_v1_00 = 0x28b49;
__aeabi_memcpy = 0x28b49;
__aeabi_memcpy4 = 0x28b49;
rtl_memmove_v1_00 = 0x28bed;
rtl_memset_v1_00 = 0x28cb5;
__aeabi_memset = 0x28cb5;
rtl_strcat_v1_00 = 0x28d49;
rtl_strchr_v1_00 = 0x28d91;
rtl_strcmp_v1_00 = 0x28e55;
rtl_strcpy_v1_00 = 0x28ec9;
rtl_strlen_v1_00 = 0x28f15;
rtl_strncat_v1_00 = 0x28f69;
rtl_strncmp_v1_00 = 0x28fc5;
rtl_strncpy_v1_00 = 0x2907d;
rtl_strstr_v1_00 = 0x293cd;
rtl_strsep_v1_00 = 0x2960d;
rtl_strtok_v1_00 = 0x29619;
rtl__strtok_r_v1_00 = 0x2962d;
rtl_strtok_r_v1_00 = 0x29691;
rtl_close_v1_00 = 0x29699;
rtl_fstat_v1_00 = 0x296ad;
rtl_isatty_v1_00 = 0x296c1;
rtl_lseek_v1_00 = 0x296d5;
rtl_open_v1_00 = 0x296e9;
rtl_read_v1_00 = 0x296fd;
rtl_write_v1_00 = 0x29711;
rtl_sbrk_v1_00 = 0x29725;
rtl_ltoa_v1_00 = 0x297bd;
rtl_ultoa_v1_00 = 0x29855;
rtl_dtoi_v1_00 = 0x298c5;
rtl_dtoi64_v1_00 = 0x29945;
rtl_dtoui_v1_00 = 0x299dd;
rtl_ftol_v1_00 = 0x299e5;
rtl_itof_v1_00 = 0x29a51;
rtl_itod_v1_00 = 0x29ae9;
rtl_i64tod_v1_00 = 0x29b79;
rtl_uitod_v1_00 = 0x29c55;
rtl_ftod_v1_00 = 0x29d2d;
rtl_dtof_v1_00 = 0x29de9;
rtl_uitof_v1_00 = 0x29e89;
rtl_fadd_v1_00 = 0x29f65;
rtl_fsub_v1_00 = 0x2a261;
rtl_fmul_v1_00 = 0x2a559;
rtl_fdiv_v1_00 = 0x2a695;
rtl_dadd_v1_00 = 0x2a825;
rtl_dsub_v1_00 = 0x2aed9;
rtl_dmul_v1_00 = 0x2b555;
rtl_ddiv_v1_00 = 0x2b8ad;
rtl_dcmpeq_v1_00 = 0x2be4d;
rtl_dcmplt_v1_00 = 0x2bebd;
rtl_dcmpgt_v1_00 = 0x2bf51;
rtl_dcmple_v1_00 = 0x2c049;
rtl_fcmplt_v1_00 = 0x2c139;
rtl_fcmpgt_v1_00 = 0x2c195;
rtl_cos_f32_v1_00 = 0x2c229;
rtl_sin_f32_v1_00 = 0x2c435;
rtl_fabs_v1_00 = 0x2c639;
rtl_fabsf_v1_00 = 0x2c641;
rtl_dtoa_r_v1_00 = 0x2c77d;
__rom_mallocr_init_v1_00 = 0x2d7d1;
rtl_free_r_v1_00 = 0x2d841;
rtl_malloc_r_v1_00 = 0x2da31;
rtl_realloc_r_v1_00 = 0x2df55;
rtl_memalign_r_v1_00 = 0x2e331;
rtl_valloc_r_v1_00 = 0x2e421;
rtl_pvalloc_r_v1_00 = 0x2e42d;
rtl_calloc_r_v1_00 = 0x2e441;
rtl_cfree_r_v1_00 = 0x2e4a9;
rtl_Balloc_v1_00 = 0x2e515;
rtl_Bfree_v1_00 = 0x2e571;
rtl_i2b_v1_00 = 0x2e585;
rtl_multadd_v1_00 = 0x2e599;
rtl_mult_v1_00 = 0x2e629;
rtl_pow5mult_v1_00 = 0x2e769;
rtl_hi0bits_v1_00 = 0x2e809;
rtl_d2b_v1_00 = 0x2e845;
rtl_lshift_v1_00 = 0x2e901;
rtl_cmp_v1_00 = 0x2e9bd;
rtl_diff_v1_00 = 0x2ea01;
rtl_sread_v1_00 = 0x2eae9;
rtl_seofread_v1_00 = 0x2eb39;
rtl_swrite_v1_00 = 0x2eb3d;
rtl_sseek_v1_00 = 0x2ebc1;
rtl_sclose_v1_00 = 0x2ec11;
rtl_sbrk_r_v1_00 = 0x2ec41;
rtl_fflush_r_v1_00 = 0x2ef8d;
rtl_vfprintf_r_v1_00 = 0x2f661;
rtl_fpclassifyd = 0x30c15;
CpkClkTbl = 0x30c68;
ROM_IMG1_VALID_PATTEN = 0x30c80;
SpicCalibrationPattern = 0x30c88;
SpicInitCPUCLK = 0x30c98;
BAUDRATE = 0x30ca8;
OVSR = 0x30d1c;
DIV = 0x30d90;
OVSR_ADJ = 0x30e04;
__AES_rcon = 0x30e78;
__AES_Te4 = 0x30ea0;
I2CDmaChNo = 0x312a0;
_GPIO_PinMap_Chip2IP_8195a = 0x312b4;
_GPIO_PinMap_PullCtrl_8195a = 0x3136c;
_GPIO_SWPORT_DDR_TBL = 0x31594;
_GPIO_EXT_PORT_TBL = 0x31598;
_GPIO_SWPORT_DR_TBL = 0x3159c;
UartLogRomCmdTable = 0x316a0;
_HalRuartOp = 0x31700;
_HalGdmaOp = 0x31760;
RTW_WPA_OUI_TYPE = 0x3540c;
WPA_CIPHER_SUITE_NONE = 0x35410;
WPA_CIPHER_SUITE_WEP40 = 0x35414;
WPA_CIPHER_SUITE_TKIP = 0x35418;
WPA_CIPHER_SUITE_CCMP = 0x3541c;
WPA_CIPHER_SUITE_WEP104 = 0x35420;
RSN_CIPHER_SUITE_NONE = 0x35424;
RSN_CIPHER_SUITE_WEP40 = 0x35428;
RSN_CIPHER_SUITE_TKIP = 0x3542c;
RSN_CIPHER_SUITE_CCMP = 0x35430;
RSN_CIPHER_SUITE_WEP104 = 0x35434;
RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
RSN_VERSION_BSD = 0x3544c;
rom_wps_Te0 = 0x35988;
rom_wps_rcons = 0x35d88;
rom_wps_Td4s = 0x35d94;
rom_wps_Td0 = 0x35e94;
__rom_b_cut_end__ = 0x4467c;
__rom_c_cut_text_start__ = 0x4467c;
HalInitPlatformLogUartV02 = 0x4467d;
HalReInitPlatformLogUartV02 = 0x4471d;
HalInitPlatformTimerV02 = 0x44755;
HalShowBuildInfoV02 = 0x447cd;
SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
HalSpiInitV02 = 0x4488d;
HalBootFlowV02 = 0x44a29;
HalInitialROMCodeGlobalVarV02 = 0x44ae5;
HalResetVsrV02 = 0x44b41;
HalI2CSendRtl8195aV02 = 0x44ce1;
HalI2CSetCLKRtl8195aV02 = 0x44d59;
RtkI2CSendV02 = 0x4508d;
RtkI2CReceiveV02 = 0x459a1;
HalI2COpInitV02 = 0x461ed;
I2CISRHandleV02 = 0x463e9;
RtkSalI2COpInitV02 = 0x46be1;
SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
SpiFlashAppV02 = 0x46c85;
SpicInitRtl8195AV02 = 0x46dc5;
SpicEraseFlashRtl8195AV02 = 0x46ea1;
HalTimerIrq2To7HandleV02 = 0x46f5d;
HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
HalTimerInitRtl8195aV02 = 0x4706d;
HalTimerReadCountRtl8195aV02 = 0x471b5;
HalTimerReLoadRtl8195aV02 = 0x471d1;
HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
HalTimerDeInitRtl8195aV02 = 0x472c1;
HalTimerOpInitV02 = 0x472f9;
GPIO_LockV02 = 0x47345;
GPIO_UnLockV02 = 0x47379;
GPIO_Int_Clear_8195aV02 = 0x473a5;
HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
FindElementIndexV02 = 0x47541;
HalRuartInitRtl8195aV02 = 0x4756d;
DramInit_rom = 0x47619;
ChangeRandSeed_rom = 0x47979;
Sdr_Rand2_rom = 0x47985;
MemTest_rom = 0x479dd;
SdrCalibration_rom = 0x47a45;
SdrControllerInit_rom = 0x47d99;
SDIO_EnterCritical = 0x47e39;
SDIO_ExitCritical = 0x47e85;
SDIO_IRQ_Handler_Rom = 0x47ec5;
SDIO_Interrupt_Init_Rom = 0x47f31;
SDIO_Device_Init_Rom = 0x47f81;
SDIO_Interrupt_DeInit_Rom = 0x48215;
SDIO_Device_DeInit_Rom = 0x48255;
SDIO_Enable_Interrupt_Rom = 0x48281;
SDIO_Disable_Interrupt_Rom = 0x482a1;
SDIO_Clear_ISR_Rom = 0x482c1;
SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
SDIO_Free_Rx_Pkt_Rom = 0x48331;
SDIO_Recycle_Rx_BD_Rom = 0x48355;
SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
SDIO_RxTask_Rom = 0x4851d;
SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
SDIO_Process_RPWM_Rom = 0x485b5;
SDIO_Reset_Cmd_Rom = 0x485e9;
SDIO_Rx_Data_Transaction_Rom = 0x48611;
SDIO_Send_C2H_PktMsg_Rom = 0x48829;
SDIO_Register_Tx_Callback_Rom = 0x488f5;
SDIO_ReadMem_Rom = 0x488fd;
SDIO_WriteMem_Rom = 0x489a9;
SDIO_SetMem_Rom = 0x48a69;
SDIO_TX_Pkt_Handle_Rom = 0x48b29;
SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
SDIO_IRQ_Handler_BH_Rom = 0x48d95;
SDIO_TxTask_Rom = 0x48e9d;
SDIO_TaskUp_Rom = 0x48eed;
SDIO_Boot_Up = 0x48f55;
__rom_c_cut_text_end__ = 0x49070;
__rom_c_cut_rodata_start__ = 0x49070;
BAUDRATE_v02 = 0x49070;
OVSR_v02 = 0x490fc;
DIV_v02 = 0x49188;
OVSR_ADJ_v02 = 0x49214;
SdrDramInfo_rom = 0x492a0;
SdrDramTiming_rom = 0x492b4;
SdrDramModeReg_rom = 0x492e8;
SdrDramDev_rom = 0x49304;
__rom_c_cut_rodata_end__ = 0x49314;
NewVectorTable = 0x10000000;
UserIrqFunTable = 0x10000100;
UserIrqDataTable = 0x10000200;
__rom_bss_start__ = 0x10000300;
CfgSysDebugWarn = 0x10000300;
CfgSysDebugInfo = 0x10000304;
CfgSysDebugErr = 0x10000308;
ConfigDebugWarn = 0x1000030c;
ConfigDebugInfo = 0x10000310;
ConfigDebugErr = 0x10000314;
HalTimerOp = 0x10000318;
GPIOState = 0x10000334;
gTimerRecord = 0x1000034c;
SSI_DBG_CONFIG = 0x10000350;
_pHAL_Gpio_Adapter = 0x10000354;
Timer2To7VectorTable = 0x10000358;
pUartLogCtl = 0x10000384;
UartLogBuf = 0x10000388;
UartLogCtl = 0x10000408;
UartLogHistoryBuf = 0x10000430;
ArgvArray = 0x100006ac;
rom_wlan_ram_map = 0x100006d4;
FalseAlmCnt = 0x100006e0;
ROMInfo = 0x10000720;
DM_CfoTrack = 0x10000738;
rom_libgloss_ram_map = 0x10000760;
rtl_errno = 0x10000bc4;
_rtl_impure_ptr = 0x10001c60;
}

13
lib/cpu/rtl8710/rtl8710.h Normal file
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#ifndef _RTL8710_H_
#define _RTL8710_H_
#include "rtl8710_sys.h"
#include "rtl8710_int.h"
#include "rtl8710_peri_on.h"
#include "rtl8710_timer.h"
#include "rtl8710_gpio.h"
//#include "rtl8710_log_uart.h"
//#include "rtl8710_spi.h"
#endif

48
lib/cpu/rtl8710/rtl8710.ld Normal file
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MEMORY{
tcm (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64k
ram (rwx) : ORIGIN = 0x10000000, LENGTH = 448k
}
PROVIDE(STACK_TOP = 0x1FFF0000 + 64k);
SECTIONS{
__rom_bss_start__ = 0x10000300;
__rom_bss_end__ = 0x10000bc8;
.text : {
__text_beg__ = . ;
*(.vectors*) *(.header) *(.text) *(.text*) *(.rodata) *(.rodata*) *(.glue_7) *(.glue_7t) *(.eh_frame) *(.ARM.extab*) . = ALIGN(4); __text_end__ = . ;
} >ram
.data : {
. = ALIGN(4);
__data_beg__ = . ;
*(.ram_vectors) *(.data) *(.data*) *(.ram_func) . = ALIGN(4);
__data_end__ = . ;
} >ram
.bss : {
. = ALIGN(4);
__bss_beg__ = . ;
*(.bss) *(COMMON) . = ALIGN(4); __bss_end__ = . ;
} >ram
__exidx_start = .;
.ARM.exidx : {
___exidx_start = . ;
*(.ARM.exidx*) ;
___exidx_end = . ; } >ram
__exidx_end = .;
.ARM.extab : {
*(.ARM.extab*)
} >ram
. = ALIGN(4);
end = .;
PROVIDE (end = .);
}
INCLUDE "export-rom_v03.txt"

332
lib/cpu/rtl8710/rtl8710.ocd Normal file
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#
# OpenOCD script for RTL8710
# Copyright (C) 2016 Rebane, rebane@alkohol.ee
#
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME rtl8710
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x800
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x2ba01477
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x10001000 -work-area-size $_WORKAREASIZE -work-area-backup 0
# adapter_khz 500
adapter_nsrst_delay 100
if {![using_hla]} {
cortex_m reset_config sysresetreq
}
set rtl8710_flasher_firmware_ptr 0x10001000
set rtl8710_flasher_buffer 0x10008000
set rtl8710_flasher_buffer_size 262144
set rtl8710_flasher_sector_size 4096
array set rtl8710_flasher_code {
0 0xB671B57F 1 0x25FF4B58 2 0x6B196B1A 3 0x7040F042 4 0x69D96318 5 0xF4414E55
6 0x69D97480 7 0xF8D361DC 8 0xF8C32120 9 0xF8D35120 10 0xF8C31124 11 0x47B05124
12 0x47B04E4F 13 0x47984B4F 14 0x60104A4F 15 0x484F47B0 16 0x60012100 17 0x2C006804
18 0x4D4DD0FC 19 0xB93E682E 20 0x60264C49 21 0x47B04E46 22 0x47984B46 23 0xE7ED6020
24 0x2B01682B 25 0x4E42D109 26 0x4C4647B0 27 0x47A02006 28 0x47904A45 29 0x47A020C7
30 0x682AE00D 31 0xD10E2A02 32 0x47B04E3B 33 0x20064C3F 34 0x483F47A0 35 0x493F4780
36 0x68084D3F 37 0x47B047A8 38 0x47A02004 39 0x6828E7CE 40 0xD1132803 41 0x47A04C32
42 0x24004838 43 0x4E396805 44 0x68311960 45 0xD206428C 46 0x4B384A37 47 0x221018A1
48 0x34104798 49 0x4D2AE7F3 50 0xE7B847A8 51 0x29046829 52 0x2400D11B 53 0x6806482F
54 0xD2B042B4 55 0x47A84D24 56 0x20064E28 57 0x4B2847B0 58 0x49284798 59 0x680A4B2A
60 0x18A018E1 61 0xF44F4B2A 62 0x47987280 63 0x200447A8 64 0xF50447B0 65 0x47A87480
66 0x682CE7E4 67 0xD1232C05 68 0x47984B17 69 0x4D1F2400 70 0x4294682A 71 0x481BD28F
72 0x68012210 73 0x18604E1D 74 0x47B04669 75 0x1B19682B 76 0xBF282910 77 0x23002110
78 0xD011428B 79 0xF81D4A16 80 0x18A05003 81 0x42B55CC6 82 0x3301D101 83 0x4A15E7F4
84 0x60112101 85 0xE7726054 86 0x25014E12 87 0xE76E6035 88 0x47A84D03 89 0xE7D63410
90 0x40000200 91 0x100011BD 92 0x100013DD 93 0x10001289 94 0x1000800C 95 0x10008000
96 0x10008004 97 0x1000130D 98 0x100013ED 99 0x10008010 100 0x10001335 101 0x10008014
102 0x10008020 103 0x10001221 104 0x10001375 105 0x10008008 106 0x6A5A4B03 107 0xD0FB0512
108 0x0060F893 109 0xBF004770 110 0x40006000 111 0x6B194B17 112 0xF4416B1A 113 0x63187040
114 0x69186919 115 0x0110F041 116 0xF8D36119 117 0x220000C0 118 0x0106F020 119 0x00C0F8D3
120 0x10C0F8C3 121 0x00C0F8D3 122 0x0101F040 123 0x00C0F8D3 124 0x10C0F8C3 125 0x43BCF503
126 0x609A6899 127 0x20016AD9 128 0x691962DA 129 0x69596118 130 0x61592102 131 0x619A6999
132 0x61DA69D9 133 0x64DA6CD9 134 0xBF004770 135 0x40000200 136 0x460EB570 137 0xB34A4614
138 0xF3C04B15 139 0x681A4507 140 0x7240F44F 141 0x685A601A 142 0xF3C02103 143 0x2C102207
144 0x2410BF28 145 0x605CB2C0 146 0x1060F883 147 0x5060F883 148 0xF8832101 149 0xF8832060
150 0x689A0060 151 0x60992500 152 0x47984B08 153 0x35015570 154 0x42A2B2AA 155 0x4804D3F8
156 0xF0116A81 157 0xD1FA0301 158 0x60836881 159 0xBD704620 160 0x40006000 161 0x100011A9
162 0x4C10B5F8 163 0x68232003 164 0x7340F44F 165 0x68636023 166 0x60602101 167 0x68A3229F
168 0x60A14D0B 169 0x2060F884 170 0x460647A8 171 0x460747A8 172 0x040347A8 173 0x2707EA43
174 0x0006EA47 175 0x4B036AA1 176 0x0201F011 177 0x6899D1FA 178 0xBDF8609A 179 0x40006000
180 0x100011A9 181 0x4C0BB510 182 0x68232001 183 0x7340F44F 184 0x68636023 185 0x60602105
186 0x60A068A2 187 0xF8844A06 188 0x47901060 189 0x4B036AA1 190 0x0201F011 191 0x6899D1FA
192 0xBD10609A 193 0x40006000 194 0x100011A9 195 0x21014B08 196 0xF44F681A 197 0x601A7280
198 0x6099689A 199 0x0060F883 200 0x48036A9A 201 0x0101F012 202 0x6883D1FA 203 0x47706081
204 0x40006000 205 0x21014B0E 206 0xF44F681A 207 0x601A7280 208 0x2220689A 209 0xF8836099
210 0xF3C02060 211 0xF3C04107 212 0xB2C02207 213 0x1060F883 214 0x2060F883 215 0x0060F883
216 0x4A036A99 217 0x0001F011 218 0x6893D1FA 219 0x47706090 220 0x40006000 221 0xB36AB530
222 0x25014B17 223 0xF44F681C 224 0x601C7480 225 0x2402689C 226 0xF883609D 227 0xF3C04060
228 0xF3C04507 229 0xB2C02407 230 0x5060F883 231 0x7F80F5B2 232 0xF44FBF28 233 0xF8837280
234 0xF8834060 235 0x20000060 236 0x4C095C0D 237 0xF8843001 238 0xB2855060 239 0xD3F74295
240 0x07496A99 241 0x6AA0D5FC 242 0xF0104B03 243 0xD1FA0101 244 0x60996898 245 0xBD304610
246 0x40006000 247 0x4B02B508 248 0x07C04798 249 0xBD08D4FB 250 0x100012D5 251 0x4B04B508
252 0xF0004798 253 0xB2C10002 254 0xD0F82900 255 0xBF00BD08 256 0x100012D5
}
set rtl8710_flasher_command_read_id 0
set rtl8710_flasher_command_mass_erase 1
set rtl8710_flasher_command_sector_erase 2
set rtl8710_flasher_command_read 3
set rtl8710_flasher_command_write 4
set rtl8710_flasher_command_verify 5
set rtl8710_flasher_ready 0
set rtl8710_flasher_capacity 0
set rtl8710_flasher_auto_erase 0
set rtl8710_flasher_auto_verify 0
set rtl8710_flasher_auto_erase_sector 0xFFFFFFFF
proc rtl8710_flasher_init {} {
global rtl8710_flasher_firmware_ptr
global rtl8710_flasher_buffer
global rtl8710_flasher_capacity
global rtl8710_flasher_ready
global rtl8710_flasher_code
if {[expr {$rtl8710_flasher_ready == 0}]} {
echo "initializing RTL8710 flasher"
halt
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
array2mem rtl8710_flasher_code 32 $rtl8710_flasher_firmware_ptr [array size rtl8710_flasher_code]
reg faultmask 0x01
reg sp 0x20000000
reg pc $rtl8710_flasher_firmware_ptr
resume
rtl8710_flasher_wait
set id [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]]
set rtl8710_flasher_capacity [expr {2 ** [expr {($id >> 16) & 0xFF}]}]
set rtl8710_flasher_ready 1
echo "RTL8710 flasher initialized"
}
return ""
}
proc rtl8710_flasher_mrw {reg} {
set value ""
mem2array value 32 $reg 1
return $value(0)
}
proc rtl8710_flasher_wait {} {
global rtl8710_flasher_buffer
while {[rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x00}]]} { }
}
proc rtl8710_flasher_load_block {local_filename offset len} {
global rtl8710_flasher_buffer
load_image $local_filename [expr {$rtl8710_flasher_buffer + 0x20 - $offset}] bin [expr {$rtl8710_flasher_buffer + 0x20}] $len
}
proc rtl8710_flasher_read_block {offset len} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_read
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_read
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x14}] $len
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]]
if {[expr {$status > 0}]} {
error "read error, offset $offset"
}
}
proc rtl8710_flasher_write_block {offset len} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_write
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_write
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x14}] $len
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]]
if {[expr {$status > 0}]} {
error "write error, offset $offset"
}
}
proc rtl8710_flasher_verify_block {offset len} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_verify
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_verify
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x14}] $len
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]]
if {[expr {$status > 0}]} {
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]]
set status [expr {$status + $offset}]
error "verify error, offset $status"
}
}
proc rtl8710_flash_read_id {} {
global rtl8710_flasher_buffer
global rtl8710_flasher_capacity
global rtl8710_flasher_command_read_id
rtl8710_flasher_init
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_read_id
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set id [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]]
set manufacturer_id [format "0x%02X" [expr {$id & 0xFF}]]
set memory_type [format "0x%02X" [expr {($id >> 8) & 0xFF}]]
set memory_capacity [expr {2 ** [expr {($id >> 16) & 0xFF}]}]
echo "manufacturer ID: $manufacturer_id, memory type: $memory_type, memory capacity: $memory_capacity bytes"
}
proc rtl8710_flash_mass_erase {} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_mass_erase
rtl8710_flasher_init
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_mass_erase
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
}
proc rtl8710_flash_sector_erase {offset} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_sector_erase
rtl8710_flasher_init
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_sector_erase
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
}
proc rtl8710_flash_read {local_filename loc size} {
global rtl8710_flasher_buffer
global rtl8710_flasher_buffer_size
rtl8710_flasher_init
for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} {
set len [expr {$size - $offset}]
if {[expr {$len > $rtl8710_flasher_buffer_size}]} {
set len $rtl8710_flasher_buffer_size
}
set flash_offset [expr {$loc + $offset}]
echo "read offset $flash_offset"
rtl8710_flasher_read_block $flash_offset $len
dump_image /tmp/_rtl8710_flasher.bin [expr {$rtl8710_flasher_buffer + 0x20}] $len
exec dd conv=notrunc if=/tmp/_rtl8710_flasher.bin "of=$local_filename" bs=1 "seek=$offset"
echo "read $len bytes"
}
}
proc rtl8710_flash_write {local_filename loc} {
global rtl8710_flasher_buffer_size
global rtl8710_flasher_sector_size
global rtl8710_flasher_auto_erase
global rtl8710_flasher_auto_verify
global rtl8710_flasher_auto_erase_sector
rtl8710_flasher_init
set sector 0
set size [file size $local_filename]
for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} {
set len [expr {$size - $offset}]
if {[expr {$len > $rtl8710_flasher_buffer_size}]} {
set len $rtl8710_flasher_buffer_size
}
set flash_offset [expr {$loc + $offset}]
echo "write offset $flash_offset"
rtl8710_flasher_load_block $local_filename $offset $len
if {[expr {$rtl8710_flasher_auto_erase != 0}]} {
for {set i $flash_offset} {$i < [expr {$flash_offset + $len}]} {incr i} {
set sector [expr {$i / $rtl8710_flasher_sector_size}]
if {[expr {$rtl8710_flasher_auto_erase_sector != $sector}]} {
echo "erase sector $sector"
rtl8710_flash_sector_erase [expr {$sector * $rtl8710_flasher_sector_size}]
set rtl8710_flasher_auto_erase_sector $sector
}
}
}
rtl8710_flasher_write_block $flash_offset $len
echo "wrote $len bytes"
if {[expr {$rtl8710_flasher_auto_verify != 0}]} {
echo "verify offset $flash_offset"
rtl8710_flasher_verify_block $flash_offset $len
}
}
}
proc rtl8710_flash_verify {local_filename loc} {
global rtl8710_flasher_buffer_size
rtl8710_flasher_init
set size [file size $local_filename]
for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} {
set len [expr {$size - $offset}]
if {[expr {$len > $rtl8710_flasher_buffer_size}]} {
set len $rtl8710_flasher_buffer_size
}
set flash_offset [expr {$loc + $offset}]
echo "read offset $flash_offset"
rtl8710_flasher_load_block $local_filename $offset $len
echo "verify offset $flash_offset"
rtl8710_flasher_verify_block $flash_offset $len
}
}
proc rtl8710_flash_auto_erase {on} {
global rtl8710_flasher_auto_erase
if {[expr {$on != 0}]} {
set rtl8710_flasher_auto_erase 1
echo "auto erase on"
} else {
set rtl8710_flasher_auto_erase 0
echo "auto erase off"
}
}
proc rtl8710_flash_auto_verify {on} {
global rtl8710_flasher_auto_verify
if {[expr {$on != 0}]} {
set rtl8710_flasher_auto_verify 1
echo "auto verify on"
} else {
set rtl8710_flasher_auto_verify 0
echo "auto verify off"
}
}
proc rtl8710_reboot {} {
mww 0xE000ED0C 0x05FA0007
}

37
lib/cpu/rtl8710/rtl8710_gpio.h Normal file
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#ifndef _RTL8710_GPIO_H_
#define _RTL8710_GPIO_H_
#include <stdint.h>
typedef struct{
volatile uint32_t SWPORTA_DR;
volatile uint32_t SWPORTA_DDR;
volatile uint32_t SWPORTA_CTRL;
volatile uint32_t SWPORTB_DR;
volatile uint32_t SWPORTB_DDR;
volatile uint32_t SWPORTB_CTRL;
volatile uint32_t SWPORTC_DR;
volatile uint32_t SWPORTC_DDR;
volatile uint32_t SWPORTC_CTRL;
uint32_t RESERVED1[3];
volatile uint32_t INTEN;
volatile uint32_t INTMASK;
volatile uint32_t INTTYPE_LEVEL;
volatile uint32_t INT_POLARITY;
volatile uint32_t INTSTATUS;
volatile uint32_t RAW_INTSTATUS;
volatile uint32_t DEBOUNCE;
volatile uint32_t PORTA_EOI;
volatile uint32_t EXT_PORTA;
volatile uint32_t EXT_PORTB;
volatile uint32_t EXT_PORTC;
uint32_t RESERVED2[1];
volatile uint32_t LS_SYNC;
}__attribute__((packed)) GPIO_TypeDef;
#define GPIO ((GPIO_TypeDef *)0x40001000)
#define GPIO_PORTA_GC4 (((uint32_t)1) << 8)
#endif

53
lib/cpu/rtl8710/rtl8710_int.h Normal file
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#ifndef _RTL8710_INT_H_
#define _RTL8710_INT_H_
#define SYSTEM_ON_INT 0
#define WDG_INT 1
#define TIMER0_INT 2
#define TIMER1_INT 3
#define I2C3_INT 4
#define TIMER2_7_INT 5
#define SPI0_INT 6
#define GPIO_INT 7
#define UART0_INT 8
#define SPI_FLASH_INT 9
#define USB_OTG_INT 10
#define SDIO_HOST_INT 11
#define SDIO_DEVICE_INT 12
#define I2S0_PCM0_INT 13
#define I2S1_PCM1_INT 14
#define WL_DMA_INT 15
#define WL_PROTOCOL_INT 16
#define CRYPTO_INT 17
#define GMAC_INT 18
#define PERIPHERAL_INT 19
#define GDMA0_CHANNEL0_INT 20
#define GDMA0_CHANNEL1_INT 21
#define GDMA0_CHANNEL2_INT 22
#define GDMA0_CHANNEL3_INT 23
#define GDMA0_CHANNEL4_INT 24
#define GDMA0_CHANNEL5_INT 25
#define GDMA1_CHANNEL0_INT 26
#define GDMA1_CHANNEL1_INT 27
#define GDMA1_CHANNEL2_INT 28
#define GDMA1_CHANNEL3_INT 29
#define GDMA1_CHANNEL4_INT 30
#define GDMA1_CHANNEL5_INT 31
#define I2C0_INT 64
#define I2C1_INT 65
#define I2C2_INT 66
#define SPI1_INT 72
#define SPI2_INT 73
#define UART1_INT 80
#define UART2_INT 81
#define LOG_UART_INT 88
#define ADC_INT 89
#define DAC0_INT 91
#define DAC1_INT 92
#define LP_EXTENSION_INT 93
#define PTA_TRX_INT 95
#define RXI300_INT 96
#define NFC_INT 97
#endif

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lib/cpu/rtl8710/rtl8710_log_uart.h Normal file
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#ifndef _RTL8710_LOG_UART_H_
#define _RTL8710_LOG_UART_H_
#include <stdint.h>
typedef struct{
union{
volatile uint32_t RBR;
volatile uint32_t THR;
volatile uint32_t DLL;
volatile uint32_t RBR_THR_DLL;
};
union{
volatile uint32_t IER;
volatile uint32_t DLH;
volatile uint32_t IER_DLH;
};
union{
volatile uint32_t IIR;
volatile uint32_t FCR;
volatile uint32_t IIR_FCR;
};
volatile uint32_t LCR;
volatile uint32_t MCR;
volatile uint32_t LSR;
volatile uint32_t MSR;
uint32_t RESERVED1[24];
volatile uint32_t USR;
}__attribute__((packed)) LOG_UART_TypeDef;
#define LOG_UART ((LOG_UART_TypeDef *)0x40003000)
// LOG_UART_IER
#define LOG_UART_IER_ERBFI (((uint32_t)0x01) << 0)
#define LOG_UART_IER_ETBEI (((uint32_t)0x01) << 1)
#define LOG_UART_IER_ELSI (((uint32_t)0x01) << 2)
#define LOG_UART_IER_EDSSI (((uint32_t)0x01) << 3)
// LOG_UART_FCR
#define LOG_UART_FCR_FIFOE (((uint32_t)0x01) << 0)
#define LOG_UART_FCR_RFIFOR (((uint32_t)0x01) << 1)
#define LOG_UART_FCR_XFIFOR (((uint32_t)0x01) << 2)
#define LOG_UART_FCR_DMAM (((uint32_t)0x01) << 3)
#define LOG_UART_FCR_TET (((uint32_t)0x03) << 4)
#define LOG_UART_FCR_RT (((uint32_t)0x03) << 6)
// LOG_UART_LCR
#define LOG_UART_LCR_DLS (((uint32_t)0x03) << 0)
#define LOG_UART_LCR_STOP (((uint32_t)0x01) << 2)
#define LOG_UART_LCR_PEN (((uint32_t)0x01) << 3)
#define LOG_UART_LCR_EPS (((uint32_t)0x01) << 4)
#define LOG_UART_LCR_STICK_PAR (((uint32_t)0x01) << 5)
#define LOG_UART_LCR_BC (((uint32_t)0x01) << 6)
#define LOG_UART_LCR_DLAB (((uint32_t)0x01) << 7)
// LOG_UART_MCR
#define LOG_UART_MCR_DTR (((uint32_t)0x01) << 0)
#define LOG_UART_MCR_RTS (((uint32_t)0x01) << 1)
#define LOG_UART_MCR_OUT1 (((uint32_t)0x01) << 2)
#define LOG_UART_MCR_OUT2 (((uint32_t)0x01) << 3)
#define LOG_UART_MCR_LOOPBACK (((uint32_t)0x01) << 4)
#define LOG_UART_MCR_AFCE (((uint32_t)0x01) << 5)
// LOG_UART_LSR
#define LOG_UART_LSR_DR (((uint32_t)0x01) << 0)
#define LOG_UART_LSR_OE (((uint32_t)0x01) << 1)
#define LOG_UART_LSR_PE (((uint32_t)0x01) << 2)
#define LOG_UART_LSR_FE (((uint32_t)0x01) << 3)
#define LOG_UART_LSR_BI (((uint32_t)0x01) << 4)
#define LOG_UART_LSR_THRE (((uint32_t)0x01) << 5)
#define LOG_UART_LSR_TEMT (((uint32_t)0x01) << 6)
#define LOG_UART_LSR_RFE (((uint32_t)0x01) << 7)
#define LOG_UART_LSR_ADDR_RCVD (((uint32_t)0x01) << 8)
#endif

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lib/cpu/rtl8710/rtl8710_peri_on.h Normal file
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#ifndef _RTL8710_PERI_ON_H_
#define _RTL8710_PERI_ON_H_
#include <stdint.h>
typedef struct{
volatile uint32_t PEON_PWR_CTRL; // 0x0200
volatile uint32_t PON_ISO_CTRL; // 0x0204
uint32_t RESERVED1[2];
volatile uint32_t SOC_FUNC_EN; // 0x0210
volatile uint32_t SOC_HCI_COM_FUNC_EN; // 0x0214
volatile uint32_t SOC_PERI_FUNC0_EN; // 0x0218
volatile uint32_t SOC_PERI_FUNC1_EN; // 0x021C
volatile uint32_t SOC_PERI_DB_FUNC0_EN; // 0x0220
uint32_t RESERVED2[3];
volatile uint32_t PESOC_CLK_CTRL; // 0x0230
volatile uint32_t PESOC_PERI_CLK_CTRL0; // 0x0234
volatile uint32_t PESOC_PERI_CLK_CTRL1; // 0x0238
volatile uint32_t PESOC_CLK_CTRL3; // 0x023C
volatile uint32_t PESOC_HCI_CLK_CTRL0; // 0x0240
volatile uint32_t PESOC_COM_CLK_CTRL1; // 0x0244
volatile uint32_t PESOC_HW_ENG_CLK_CTRL; // 0x0248
uint32_t RESERVED3[1];
volatile uint32_t PESOC_CLK_SEL; // 0x0250
uint32_t RESERVED4[6];
volatile uint32_t SYS_ANACK_CAL_CTRL; // 0x026C
volatile uint32_t OSC32K_CTRL; // 0x0270
volatile uint32_t OSC32K_REG_CTRL0; // 0x0274
volatile uint32_t OSC32K_REG_CTRL1; // 0x0278
volatile uint32_t THERMAL_METER_CTRL; // 0x027C
volatile uint32_t UART_MUX_CTRL; // 0x0280
volatile uint32_t SPI_MUX_CTRL; // 0x0284
volatile uint32_t I2C_MUX_CTRL; // 0x0288
volatile uint32_t I2S_MUX_CTRL; // 0x028C
uint32_t RESERVED5[4];
volatile uint32_t HCI_PINMUX_CTRL; // 0x02A0
volatile uint32_t WL_PINMUX_CTRL; // 0x02A4
volatile uint32_t BT_PINMUX_CTRL; // 0x02A8
volatile uint32_t PWM_PINMUX_CTRL; // 0x02AC
uint32_t RESERVED6[4];
volatile uint32_t CPU_PERIPHERAL_CTRL; // 0x02C0
uint32_t RESERVED7[7];
volatile uint32_t HCI_CTRL_STATUS_0; // 0x02E0
volatile uint32_t HCI_CTRL_STATUS_1; // 0x02E4
uint32_t RESERVED8[6];
volatile uint32_t PESOC_MEM_CTRL; // 0x0300
volatile uint32_t PESOC_SOC_CTRL; // 0x0304
volatile uint32_t PESOC_PERI_CTRL; // 0x0308
uint32_t RESERVED9[5];
volatile uint32_t GPIO_SHTDN_CTRL; // 0x0320
volatile uint32_t GPIO_DRIVING_CTRL; // 0x0324
uint32_t RESERVED10[2];
volatile uint32_t GPIO_PULL_CTRL0; // 0x0330
volatile uint32_t GPIO_PULL_CTRL1; // 0x0334
volatile uint32_t GPIO_PULL_CTRL2; // 0x0338
volatile uint32_t GPIO_PULL_CTRL3; // 0x033C
volatile uint32_t GPIO_PULL_CTRL4; // 0x0340
volatile uint32_t GPIO_PULL_CTRL5; // 0x0344
volatile uint32_t GPIO_PULL_CTRL6; // 0x0348
uint32_t RESERVED11[5];
volatile uint32_t PERI_PWM0_CTRL; // 0x0360
volatile uint32_t PERI_PWM1_CTRL; // 0x0364
volatile uint32_t PERI_PWM2_CTRL; // 0x0368
volatile uint32_t PERI_PWM3_CTRL; // 0x036C
volatile uint32_t PERI_TIM_EVT_CTRL; // 0x0370
volatile uint32_t PERI_EGTIM_CTRL; // 0x0374
uint32_t RESERVED12[30];
volatile uint32_t PEON_CFG; // 0x03F0
volatile uint32_t PEON_STATUS; // 0x03F4
}__attribute__((packed)) PERI_ON_TypeDef;
#define PERI_ON ((PERI_ON_TypeDef *)0x40000200)
// PERI_ON_SOC_FUNC_EN
#define PERI_ON_SOC_FUNC_EN_FUN (((uint32_t)0x01) << 0)
#define PERI_ON_SOC_FUNC_EN_OCP (((uint32_t)0x01) << 1)
#define PERI_ON_SOC_FUNC_EN_LXBUS (((uint32_t)0x01) << 2)
#define PERI_ON_SOC_FUNC_EN_FLASH (((uint32_t)0x01) << 4)
#define PERI_ON_SOC_FUNC_EN_MEM_CTRL (((uint32_t)0x01) << 6)
#define PERI_ON_SOC_FUNC_EN_CPU (((uint32_t)0x01) << 8)
#define PERI_ON_SOC_FUNC_EN_LOG_UART (((uint32_t)0x01) << 12)
#define PERI_ON_SOC_FUNC_EN_GDMA0 (((uint32_t)0x01) << 13)
#define PERI_ON_SOC_FUNC_EN_GDMA1 (((uint32_t)0x01) << 14)
#define PERI_ON_SOC_FUNC_EN_GTIMER (((uint32_t)0x01) << 16)
#define PERI_ON_SOC_FUNC_EN_SECURITY_ENGINE (((uint32_t)0x01) << 20)
// PERI_ON_SOC_PERI_FUNC1_EN
#define PERI_ON_SOC_PERI_FUNC1_EN_ADC0 (((uint32_t)0x01) << 0)
#define PERI_ON_SOC_PERI_FUNC1_EN_DAC0 (((uint32_t)0x01) << 4)
#define PERI_ON_SOC_PERI_FUNC1_EN_DAC1 (((uint32_t)0x01) << 5)
#define PERI_ON_SOC_PERI_FUNC1_EN_GPIO (((uint32_t)0x01) << 8)
// PERI_ON_PESOC_CLK_CTRL
#define PERI_ON_CLK_CTRL_CKE_OCP (((uint32_t)0x01) << 0)
#define PERI_ON_CLK_CTRL_CKE_PLFM (((uint32_t)0x01) << 2)
#define PERI_ON_CLK_CTRL_ACTCK_TRACE_EN (((uint32_t)0x01) << 4)
#define PERI_ON_CLK_CTRL_SLPCK_TRACE_EN (((uint32_t)0x01) << 5)
#define PERI_ON_CLK_CTRL_ACTCK_VENDOR_REG_EN (((uint32_t)0x01) << 6)
#define PERI_ON_CLK_CTRL_SLPCK_VENDOR_REG_EN (((uint32_t)0x01) << 7)
#define PERI_ON_CLK_CTRL_ACTCK_FLASH_EN (((uint32_t)0x01) << 8)
#define PERI_ON_CLK_CTRL_SLPCK_FLASH_EN (((uint32_t)0x01) << 9)
#define PERI_ON_CLK_CTRL_ACTCK_SDR_EN (((uint32_t)0x01) << 10)
#define PERI_ON_CLK_CTRL_SLPCK_SDR_EN (((uint32_t)0x01) << 11)
#define PERI_ON_CLK_CTRL_ACTCK_LOG_UART_EN (((uint32_t)0x01) << 12)
#define PERI_ON_CLK_CTRL_SLPCK_LOG_UART_EN (((uint32_t)0x01) << 13)
#define PERI_ON_CLK_CTRL_ACTCK_TIMER_EN (((uint32_t)0x01) << 14)
#define PERI_ON_CLK_CTRL_SLPCK_TIMER_EN (((uint32_t)0x01) << 15)
#define PERI_ON_CLK_CTRL_ACTCK_GDMA0_EN (((uint32_t)0x01) << 16)
#define PERI_ON_CLK_CTRL_SLPCK_GDMA0_EN (((uint32_t)0x01) << 17)
#define PERI_ON_CLK_CTRL_ACTCK_GDMA1_EN (((uint32_t)0x01) << 18)
#define PERI_ON_CLK_CTRL_SLPCK_GDMA1_EN (((uint32_t)0x01) << 19)
#define PERI_ON_CLK_CTRL_ACTCK_GPIO_EN (((uint32_t)0x01) << 24)
#define PERI_ON_CLK_CTRL_SLPCK_GPIO_EN (((uint32_t)0x01) << 25)
#define PERI_ON_CLK_CTRL_ACTCK_BTCMD_EN (((uint32_t)0x01) << 28)
#define PERI_ON_CLK_CTRL_SLPCK_BTCMD_EN (((uint32_t)0x01) << 29)
// PERI_ON_CPU_PERIPHERAL_CTRL
#define PERI_ON_CPU_PERIPHERAL_CTRL_SPI_FLASH_PIN_EN (((uint32_t)0x01) << 0)
#define PERI_ON_CPU_PERIPHERAL_CTRL_SPI_FLASH_PIN_SEL (((uint32_t)0x03) << 1)
#define PERI_ON_CPU_PERIPHERAL_CTRL_SDR_PIN_EN (((uint32_t)0x01) << 4)
#define PERI_ON_CPU_PERIPHERAL_CTRL_SWD_PIN_EN (((uint32_t)0x01) << 16)
#define PERI_ON_CPU_PERIPHERAL_CTRL_TRACE_PIN_EN (((uint32_t)0x01) << 17)
#define PERI_ON_CPU_PERIPHERAL_CTRL_LOG_UART_PIN_EN (((uint32_t)0x01) << 20)
#define PERI_ON_CPU_PERIPHERAL_CTRL_LOG_UART_IR_EN (((uint32_t)0x01) << 21)
#define PERI_ON_CPU_PERIPHERAL_CTRL_LOG_UART_PIN_SEL (((uint32_t)0x03) << 22)
#endif

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#ifndef _RTL8710_SPI_H_
#define _RTL8710_SPI_H_
#include <stdint.h>
typedef struct{
volatile uint32_t CTRLR0;
volatile uint32_t CTRLR1;
volatile uint32_t SSIENR;
volatile uint32_t MWCR;
volatile uint32_t SER;
volatile uint32_t BAUDR;
volatile uint32_t TXFTLR;
volatile uint32_t RXFTLR;
volatile uint32_t TXFLR;
volatile uint32_t RXFLR;
volatile uint32_t SR;
volatile uint32_t IMR;
volatile uint32_t ISR;
volatile uint32_t RISR;
volatile uint32_t TXOICR;
volatile uint32_t RXOICR;
volatile uint32_t RXUICR;
volatile uint32_t MSTICR;
volatile uint32_t ICR;
volatile uint32_t DMACR;
volatile uint32_t DMATDLR;
volatile uint32_t DMARDLR;
volatile uint32_t IDR;
volatile uint32_t SSI_COMP_VERSION;
union{
struct{
union{
volatile uint8_t DR;
volatile uint8_t DR8;
};
uint8_t RESERVED1[3];
}__attribute__((packed));
struct{
volatile uint16_t DR16;
uint16_t RESERVED2[1];
}__attribute__((packed));
volatile uint32_t DR32;
};
uint32_t RESERVED3[31];
volatile uint32_t READ_FAST_SINGLE;
volatile uint32_t READ_DUAL_DATA;
volatile uint32_t READ_DUAL_ADDR_DATA;
volatile uint32_t READ_QUAD_DATA;
union{
volatile uint32_t READ_QUAD_ADDR_DATA;
volatile uint32_t RX_SAMPLE_DLY;
};
volatile uint32_t WRITE_SIGNLE;
volatile uint32_t WRITE_DUAL_DATA;
volatile uint32_t WRITE_DUAL_ADDR_DATA;
volatile uint32_t WRITE_QUAD_DATA;
volatile uint32_t WRITE_QUAD_ADDR_DATA;
volatile uint32_t WRITE_ENABLE;
volatile uint32_t READ_STATUS;
volatile uint32_t CTRLR2;
volatile uint32_t FBAUDR;
volatile uint32_t ADDR_LENGTH;
volatile uint32_t AUTO_LENGTH;
volatile uint32_t VALID_CMD;
volatile uint32_t FLASE_SIZE;
volatile uint32_t FLUSH_FIFO;
}__attribute__((packed)) SPI_TypeDef;
#define SPI_FLASH ((SPI_TypeDef *)0x40006000)
// SPI_CTRLR0
#define SPI_CTRLR0_FRF (((uint32_t)0x03) << 4)
#define SPI_CTRLR0_SCPH (((uint32_t)0x01) << 6)
#define SPI_CTRLR0_SCPOL (((uint32_t)0x01) << 7)
#define SPI_CTRLR0_TMOD (((uint32_t)0x03) << 8)
#define SPI_CTRLR0_SLV_OE (((uint32_t)0x01) << 10)
#define SPI_CTRLR0_SRL (((uint32_t)0x01) << 11)
#define SPI_CTRLR0_CFS (((uint32_t)0x0F) << 12)
#define SPI_CTRLR0_ADDR_CH (((uint32_t)0x03) << 16)
#define SPI_CTRLR0_DATA_CH (((uint32_t)0x03) << 18)
#define SPI_CTRLR0_CMD_CH (((uint32_t)0x03) << 20)
#define SPI_CTRLR0_FAST_RD (((uint32_t)0x01) << 22)
#define SPI_CTRLR0_SHIFT_CK_MTIMES (((uint32_t)0x1F) << 23)
// SPI_SER
#define SPI_SER_SS0 (((uint32_t)0x01) << 0)
#define SPI_SER_SS1 (((uint32_t)0x01) << 1)
#define SPI_SER_SS2 (((uint32_t)0x01) << 2)
// SPI_SR
#define SPI_SR_SSI (((uint32_t)0x01) << 0)
#define SPI_SR_TFNF (((uint32_t)0x01) << 1)
#define SPI_SR_TFE (((uint32_t)0x01) << 2)
#define SPI_SR_RFNE (((uint32_t)0x01) << 3)
#define SPI_SR_RFF (((uint32_t)0x01) << 4)
#define SPI_SR_TXE (((uint32_t)0x01) << 5)
#endif

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#ifndef _RTL8710_SYS_H_
#define _RTL8710_SYS_H_
#include <stdint.h>
// ~/programming/rtl8710/doc/registers/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h
typedef struct{
volatile uint16_t PWR_CTRL; // 0x0000
volatile uint16_t ISO_CTRL; // 0x0002
uint32_t RESERVED1[1];
volatile uint32_t FUNC_EN; // 0x0008
uint32_t RESERVED2[1];
volatile uint32_t CLK_CTRL0; // 0x0010
volatile uint32_t CLK_CTRL1; // 0x0014
uint32_t RESERVED3[2];
volatile uint32_t EFUSE_SYSCFG0; // 0x0020
volatile uint32_t EFUSE_SYSCFG1; // 0x0024
volatile uint32_t EFUSE_SYSCFG2; // 0x0028
volatile uint32_t EFUSE_SYSCFG3; // 0x002C
volatile uint32_t EFUSE_SYSCFG4; // 0x0030
volatile uint32_t EFUSE_SYSCFG5; // 0x0034
volatile uint32_t EFUSE_SYSCFG6; // 0x0038
volatile uint32_t EFUSE_SYSCFG7; // 0x003C
volatile uint32_t REGU_CTRL0; // 0x0040
uint32_t RESERVED4[1];
volatile uint32_t SWR_CTRL0; // 0x0048
volatile uint32_t SWR_CTRL1; // 0x004C
uint32_t RESERVED5[4];
volatile uint32_t XTAL_CTRL0; // 0x0060
volatile uint32_t XTAL_CTRL1; // 0x0064
uint32_t RESERVED6[2];
volatile uint32_t SYSPLL_CTRL0; // 0x0070
volatile uint32_t SYSPLL_CTRL1; // 0x0074
volatile uint32_t SYSPLL_CTRL2; // 0x0078
uint32_t RESERVED7[5];
volatile uint32_t ANA_TIM_CTRL; // 0x0090
volatile uint32_t DSLP_TIM_CTRL; // 0x0094
volatile uint32_t DSLP_TIM_CAL_CTRL; // 0x0098
uint32_t RESERVED8[1];
volatile uint32_t DEBUG_CTRL; // 0x00A0
volatile uint32_t PINMUX_CTRL; // 0x00A4
volatile uint32_t GPIO_DSTBY_WAKE_CTRL0; // 0x00A8
volatile uint32_t GPIO_DSTBY_WAKE_CTRL1; // 0x00AC
uint32_t RESERVED9[3];
volatile uint32_t DEBUG_REG; // 0x00BC
uint32_t RESERVED10[8];
volatile uint32_t EEPROM_CTRL0; // 0x00E0
volatile uint32_t EEPROM_CTRL1; // 0x00E4
volatile uint32_t EFUSE_CTRL; // 0x00E8
volatile uint32_t EFUSE_TEST; // 0x00EC
volatile uint32_t DSTBY_INFO0; // 0x00F0
volatile uint32_t DSTBY_INFO1; // 0x00F4
volatile uint32_t DSTBY_INFO2; // 0x00F8
volatile uint32_t DSTBY_INFO3; // 0x00FC
volatile uint32_t SLP_WAKE_EVENT_MSK0; // 0x0100
volatile uint32_t SLP_WAKE_EVENT_MSK1; // 0x0104
volatile uint32_t SLP_WAKE_EVENT_STATUS0; // 0x0108
volatile uint32_t SLP_WAKE_EVENT_STATUS1; // 0x010C
volatile uint32_t SNF_WAKE_EVENT_MSK0; // 0x0110
volatile uint32_t SNF_WAKE_EVENT_STATUS; // 0x0114
volatile uint32_t PWRMGT_CTRL; // 0x0118
uint32_t RESERVED11[1];
volatile uint32_t PWRMGT_OPTION; // 0x0120
volatile uint32_t PWRMGT_OPTION_EXT; // 0x0124
uint32_t RESERVED12[2];
volatile uint32_t DSLP_WEVENT; // 0x0130
volatile uint32_t PERI_MONITOR; // 0x0134
uint32_t RESERVED13[46];
volatile uint32_t SYSTEM_CFG0; // 0x01F0
volatile uint32_t SYSTEM_CFG1; // 0x01F4
volatile uint32_t SYSTEM_CFG2; // 0x01F8
}__attribute__((packed)) SYS_TypeDef;
#define SYS ((SYS_TypeDef *)0x40000000)
// SYS_PWR_CTRL
#define SYS_PWR_CTRL_PEON_EN (((uint16_t)0x01) << 0)
#define SYS_PWR_CTRL_RET_MEM_EN (((uint16_t)0x01) << 1)
#define SYS_PWR_CTRL_SOC_EN (((uint16_t)0x01) << 2)
// SYS_ISO_CTRL
#define SYS_ISO_CTRL_PEON (((uint16_t)0x01) << 0)
#define SYS_ISO_CTRL_RET_MEM (((uint16_t)0x01) << 1)
#define SYS_ISO_CTRL_SOC (((uint16_t)0x01) << 2)
#define SYS_ISO_CTRL_SYSPLL (((uint16_t)0x01) << 7)
// SYS_FUNC_EN
#define SYS_FUNC_EN_FEN_EELDR (((uint32_t)0x01) << 0)
#define SYS_FUNC_EN_SOC_SYSPEON_EN (((uint32_t)0x01) << 4)
#define SYS_FUNC_EN_FEN_SIC (((uint32_t)0x01) << 24)
#define SYS_FUNC_EN_FEN_SIC_MST (((uint32_t)0x01) << 25)
#define SYS_FUNC_EN_PWRON_TRAP_SHTDN_N (((uint32_t)0x01) << 30)
#define SYS_FUNC_EN_AMACRO_EN (((uint32_t)0x01) << 31)
// SYS_CLK_CTRL0
#define SYS_CLK_CTRL0_CK_SYSREG_EN (((uint32_t)0x01) << 0)
#define SYS_CLK_CTRL0_CK_EELDR_EN (((uint32_t)0x01) << 1)
#define SYS_CLK_CTRL0_SOC_OCP_IOBUS_CK_EN (((uint32_t)0x01) << 2)
// SYS_CLK_CTRL1
#define SYS_CLK_CTRL1_PESOC_EELDR_CK_SEL (((uint32_t)0x01) << 0)
#define SYS_CLK_CTRL1_PESOC_OCP_CPU_CK_SEL (((uint32_t)0x07) << 4)
#endif

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#ifndef _RTL8710_TIMER_H_
#define _RTL8710_TIMER_H_
#include <stdint.h>
typedef struct{
volatile uint32_t TIM0_LOAD_COUNT;
volatile uint32_t TIM0_CURRENT_VALUE;
volatile uint32_t TIM0_CONTROL;
volatile uint32_t TIM0_EOI;
volatile uint32_t TIM0_IS;
volatile uint32_t TIM1_LOAD_COUNT;
volatile uint32_t TIM1_CURRENT_VALUE;
volatile uint32_t TIM1_CONTROL;
volatile uint32_t TIM1_EOI;
volatile uint32_t TIM1_IS;
uint32_t RESERVED1[30];
volatile uint32_t TIMS_IS;
volatile uint32_t TIMS_EOI;
volatile uint32_t TIMS_RAW_IS;
volatile uint32_t TIMS_COMP_VERSION;
volatile uint32_t TIM0_LOAD_COUNT2;
volatile uint32_t TIM1_LOAD_COUNT2;
}__attribute__((packed)) TIMER_TypeDef;
#define TIMER ((TIMER_TypeDef *)0x40002000)
// TIMER_CONTROL
#define TIMER_CONTROL_ENABLE (((uint32_t)0x01) << 0)
#define TIMER_CONTROL_MODE (((uint32_t)0x01) << 1)
#define TIMER_CONTROL_IM (((uint32_t)0x01) << 2)
#define TIMER_CONTROL_PWM (((uint32_t)0x01) << 3)
#endif