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pvvx 2016-09-13 12:31:00 +03:00
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commit 56693eef0d
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164
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org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning
org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>()}
org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning
org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},paramNot\=>false}
org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning
org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},else\=>false,afterelse\=>false}
org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error
org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning
org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true}
org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning
org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true}
org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning
org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>("@(\#)","$Id")}
org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error
org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}

29
.settings/org.eclipse.cdt.core.prefs Normal file
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@ -0,0 +1,29 @@
eclipse.preferences.version=1
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/MINGW_HOME/delimiter=;
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/MINGW_HOME/operation=replace
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/MINGW_HOME/value=C\:\\MinGW
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/OOCD_HOME/delimiter=;
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/OOCD_HOME/operation=append
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/OOCD_HOME/value=D\:\\MCU\\OpenOCD\\bin
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/PATH/delimiter=;
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/PATH/operation=replace
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/PATH/value=${MINGW_HOME}\\mingw64\\bin;${MSYS_HOME}\\bin;${OOCD_HOME};${TL_PATH};C\:\\Eclipse;D\:\\MentorGraphics\\Sourcery_CodeBench_Lite_for_MIPS_ELF\\bin;D\:\\MCU\\STMicroelectronics\\st_toolset\\asm;C\:\\Windows;C\:\\Windows\\system32
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/SYSTEMROOT/delimiter=;
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/SYSTEMROOT/operation=append
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/SYSTEMROOT/value=C\:\\Windows
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/TL_PATH/delimiter=;
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/TL_PATH/operation=append
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/TL_PATH/value=D\:\\MCU\\GNU Tools ARM Embedded\\5.2 2015q4\\bin
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/append=true
environment/project/cdt.managedbuild.config.gnu.mingw.exe.debug.2135385807/appendContributed=false
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/OOCD_HOME/delimiter=;
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/OOCD_HOME/operation=append
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/OOCD_HOME/value=D\:\\MCU\\OpenOCD\\bin
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/PATH/delimiter=;
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/PATH/operation=replace
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/PATH/value=${MINGW_HOME}\\bin;${MSYS_HOME}\\bin;${OOCD_HOME}C\:/Program Files (x86)/Java/jre1.8.0_101/bin/client;C\:/Program Files (x86)/Java/jre1.8.0_101/bin;C\:/Program Files (x86)/Java/jre1.8.0_101/lib/i386;C\:\\MinGW\\mingw64\\bin;C\:\\MinGW\\msys\\1.0\\bin;C\:\\MinGW\\bin;D\:\\MCU\\STMicroelectronics\\st_toolset\\asm;C\:\\Python27;C\:\\Utils\\FarUtils;C\:\\Utils\\FarUtils\\HIEW810;C\:\\Windows;C\:\\Windows\\system32;C\:\\Windows\\System32\\Wbem;C\:\\Windows\\System32\\WindowsPowerShell\\v1.0;D\:\\MCU\\Microchip\\xc32\\v1.42\\bin;D\:\\MCU\\Microchip\\mplabc30\\v3.31\\bin;D\:\\MCU\\Microchip\\MPLAB C32 Suite\\bin;D\:\\MCU\\Microchip\\mplabc32\\v1.12\\bin;D\:\\MCU\\Microchip\\mcc18\\mpasm;D\:\\MCU\\Microchip\\mcc18\\bin;D\:\\WRK\\TortoiseGit\\bin;C\:\\Utils\\TortoiseSVN\\binC\:\\Program Files (x86)\\Git\\cmd;C\:\\Program Files (x86)\\Borland\\Delphi7\\Bin;C\:\\Program Files (x86)\\Borland\\Delphi7\\Projects\\Bpl\\;C\:\\Program Files (x86)\\Common Files\\Microsoft Shared\\Windows Live;C\:\\Program Files (x86)\\ATI Technologies\\ATI.ACE\\Core-Static;C\:\\Program Files (x86)\\Common Files\\Acronis\\SnapAPI;C\:\\Program Files (x86)\\Windows Live\\Shared;C\:\\Program Files (x86)\\IVI Foundation\\VISA\\WinNT\\Bin;C\:\\Program Files (x86)\\Windows Kits\\8.1\\Windows Performance Toolkit;C\:\\Program Files (x86)\\Microsoft SDKs\\TypeScript\\1.0;C\:\\Program Files (x86)\\IVI Foundation\\VISA\\WinNT\\Bin;C\:\\Program Files\\Microsoft SQL Server\\110\\Tools\\Binn;C\:\\Program Files\\Common Files\\Microsoft Shared\\Windows Live;C\:\\Program Files\\Microsoft SQL Server\\120\\Tools\\Binn;C\:\\Program Files\\Microsoft DNX\\Dnvm;C\:\\Program Files\\IVI Foundation\\VISA\\Win64\\Bin;D\:\\Automation\\Samcoon\\SKWorkshop\\Marco\\HMI\\bin;D\:\\Automation\\Samcoon\\SKWorkshop\\Marco\\X86\\bin;D\:\\Automation\\Samcoon\\SK035AE\\SKWorkshop\\Marco\\HMI\\bin;D\:\\Automation\\Samcoon\\SK035AE\\SKWorkshop\\Marco\\X86\\bin;C\:\\Users\\PVV\\.dnx\\bin;C\:\\ProgramData\\chocolatey\\bin;C\:\\ProgramData\\Oracle\\Java\\javapath;C\:\\Program Files (x86)\\QuickTime\\QTSystem;C\:\\Program Files\\nodejs;D\:\\MCU\\GNU Tools ARM Embedded\\5.2 2015q4\\bin;D\:\\MentorGraphics\\Sourcery_CodeBench_Lite_for_MIPS_ELF\\bin;D\:\\MCU\\OpenOCD\\bin;C\:\\Eclipse
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/TL_PATH/delimiter=;
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/TL_PATH/operation=append
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/TL_PATH/value=D\:\\MCU\\GNU Tools ARM Embedded\\5.2 2015q4\\bin
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/append=true
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/appendContributed=true

36
LICENSE Normal file
View file

@ -0,0 +1,36 @@
THE BEER-WARE LICENSE
As long as you retain this notice you can do whatever you want
with this stuff. If we meet some day, and you think this stuff
is worth it, you can buy me a beer in return.
Rebane, rebane@alkohol.ee
-----------------------------------------------------------------------
This is free and unencumbered software released into the public domain.
Anyone is free to copy, modify, publish, use, compile, sell, or
distribute this software, either in source code form or as a compiled
binary, for any purpose, commercial or non-commercial, and by any
means.
In jurisdictions that recognize copyright laws, the author or authors
of this software dedicate any and all copyright interest in the
software to the public domain. We make this dedication for the benefit
of the public at large and to the detriment of our heirs and
successors. We intend this dedication to be an overt act of
relinquishment in perpetuity of all present and future rights to this
software under copyright law.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
For more information, please refer to <http://unlicense.org/>

62
Makefile Normal file
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@ -0,0 +1,62 @@
LIBDIR = lib
FILENAME_PREFIX = test
ADDRESS = 0x10001000
#FLASHER = stlink-v2-1
#FLASHER = stlink-v2
FLASHER = Jlink
# stlink-v2-1
ifeq ($(FLASHER), Jlink)
# Jlink FLASHER_SPEED ..4000 kHz
FLASHER_SPEED = 3500
else
ifeq ($(FLASHER),stlink-v2)
# stlink-v2 FLASHER_SPEED ..1800 kHz
FLASHER_SPEED = 1800
else
# ? FLASHER_SPEED ..500 kHz ?
FLASHER_SPEED = 500
endif
endif
CC_PARAMS = -Wall -g -Os -mlittle-endian -mlong-calls -mthumb -mcpu=cortex-m3 -mfloat-abi=soft -mthumb-interwork -ffunction-sections -ffreestanding -fsingle-precision-constant -fshort-wchar -fno-short-enums -Ddouble=float -Wstrict-aliasing=0 -Wl,-T,$(LIBDIR)/cpu/rtl8710/rtl8710.ld -L$(LIBDIR)/cpu/rtl8710 -nostartfiles -nostdlib -u cortex_vectors -Wl,--gc-sections
BASE_PARAMS = -DCORTEX_INTERRUPT_MAX=32 -I$(LIBDIR) -I$(LIBDIR)/cpu/rtl8710 -I$(LIBDIR)/cpu/cortex -I$(LIBDIR)/fwlib -Wl,--section-start=.text=$(ADDRESS)
#$(LIBDIR)/cpu/cortex/cortex.c
LIBC_PARAMS = -I$(LIBDIR)/libc $(LIBDIR)/libc/libc.c -DLIBC_PRINTF
FIRMWARE_PARAMS = main.c
CC = arm-none-eabi-gcc
all: firmware
firmware:
$(CC) $(CC_PARAMS) $(BASE_PARAMS) $(LIBC_PARAMS) $(FIRMWARE_PARAMS) -lgcc -o $(FILENAME_PREFIX).elf
arm-none-eabi-objdump -S $(FILENAME_PREFIX).elf >$(FILENAME_PREFIX).asm
arm-none-eabi-strip $(FILENAME_PREFIX).elf
arm-none-eabi-objcopy -O binary $(FILENAME_PREFIX).elf $(FILENAME_PREFIX).bin
chmod 755 $(FILENAME_PREFIX).bin
$(CC) $(CC_PARAMS) -DSeg1StartAddr=$(ADDRESS) -DBinFileName="\"$(FILENAME_PREFIX).bin\"" rtl8710_flash_boot.S -o flash.elf
arm-none-eabi-objcopy -O binary flash.elf flash.bin
chmod 755 flash.bin
size:
arm-none-eabi-size -A -x $(FILENAME_PREFIX).elf
clean:
rm -rf $(FILENAME_PREFIX).bin $(FILENAME_PREFIX).elf $(FILENAME_PREFIX).asm flash.bin flash.elf
test:
openocd -f interface/$(FLASHER).cfg -c "adapter_khz $(FLASHER_SPEED)" -f $(LIBDIR)/cpu/rtl8710/rtl8710.ocd -f $(LIBDIR)/cpu/cortex/cortex.ocd -c "init" -c "reset halt" -c "load_image $(FILENAME_PREFIX).bin $(ADDRESS) bin" -c "cortex_bootstrap $(ADDRESS)" -c "shutdown"
flash:
openocd -f interface/$(FLASHER).cfg -c "adapter_khz $(FLASHER_SPEED)" -f $(LIBDIR)/cpu/rtl8710/rtl8710.ocd -c "init" -c "reset halt" -c "rtl8710_flash_auto_erase 1" -c "rtl8710_flash_auto_verify 1" -c "rtl8710_flash_write flash.bin 0" -c "rtl8710_reboot" -c "reset run" -c shutdown
reset:
openocd -f interface/$(FLASHER).cfg -c "adapter_khz $(FLASHER_SPEED)" -f $(LIBDIR)/cpu/rtl8710/rtl8710.ocd -c "init" -c "reset halt" -c "rtl8710_reboot" -c shutdown

25
README.md
View file

@ -1 +1,24 @@
# RTL00_HelloWorld
# RTL-00 Test Hello World
RTL8710 OpenOCD J-Link/STlink
## pins:
* UART RX: GB0
* UART TX: GB1
* LED: GC4
* SWDIO: GE3
* SWCLK: GE4
## building:
```
make
```
## testing in ram:
```
make test
```
## flashing:
```
make flash
```
## reset:
```
make reset
```

501
lib/basic_types.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __BASIC_TYPES_H__
#define __BASIC_TYPES_H__
//#define PLATFORM_FREERTOS
#include <stdint.h>
#define PLATFORM_LITTLE_ENDIAN 0
#define PLATFORM_BIG_ENDIAN 1
#define SYSTEM_ENDIAN PLATFORM_LITTLE_ENDIAN
#define SUCCESS 0
#define FAIL (-1)
#undef _SUCCESS
#define _SUCCESS 1
#undef _FAIL
#define _FAIL 0
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE (!FALSE)
#endif
#define _TRUE TRUE
#define _FALSE FALSE
#ifndef NULL
#define NULL 0
#endif
#ifdef __GNUC__
#define __weak __attribute__((weak))
#define likely(x) __builtin_expect ((x), 1)
#define unlikely(x) __builtin_expect ((x), 0)
#endif
typedef unsigned int uint;
typedef signed int sint;
#ifdef __ICCARM__
typedef signed long long __int64_t;
typedef unsigned long long __uint64_t;
#endif
#define s8 int8_t
#define u8 uint8_t
#define s16 int16_t
#define u16 uint16_t
#define s32 int32_t
#define u32 uint32_t
#define s64 int64_t
#define u64 uint64_t
#ifdef CONFIG_MBED_ENABLED
typedef unsigned int BOOL;
#else
#ifndef BOOL
typedef unsigned char BOOL;
#endif
#ifndef bool
#ifndef __cplusplus
typedef unsigned char bool;
#endif
#endif
#endif
#define UCHAR uint8_t
#define USHORT uint16_t
#define UINT uint32_t
#define ULONG uint32_t
typedef struct { volatile int counter; } atomic_t;
typedef enum _RTK_STATUS_ {
_EXIT_SUCCESS = 0,
_EXIT_FAILURE = 1
}RTK_STATUS, *PRTK_STATUS;
#define IN
#define OUT
#define VOID void
#define INOUT
#define NDIS_OID uint
#define NDIS_STATUS uint
#ifndef PVOID
typedef void * PVOID;
#endif
typedef u32 dma_addr_t;
typedef void (*proc_t)(void*);
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef __kernel_size_t SIZE_T;
typedef __kernel_ssize_t SSIZE_T;
#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field)
#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T))
#define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1)
#define SIZE_PTR SIZE_T
#define SSIZE_PTR SSIZE_T
#ifndef ON
#define ON 1
#endif
#ifndef OFF
#define OFF 0
#endif
#ifndef ENABLE
#define ENABLE 1
#endif
#ifndef DISABLE
#define DISABLE 0
#endif
#define BIT0 0x0001
#define BIT1 0x0002
#define BIT2 0x0004
#define BIT3 0x0008
#define BIT4 0x0010
#define BIT5 0x0020
#define BIT6 0x0040
#define BIT7 0x0080
#define BIT8 0x0100
#define BIT9 0x0200
#define BIT10 0x0400
#define BIT11 0x0800
#define BIT12 0x1000
#define BIT13 0x2000
#define BIT14 0x4000
#define BIT15 0x8000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define BIT_(__n) (1<<(__n))
#ifndef BIT
#define BIT(__n) (1<<(__n))
#endif
#if defined (__ICCARM__)
#define STRINGIFY(s) #s
#define SECTION(_name) _Pragma( STRINGIFY(location=_name))
#define ALIGNMTO(_bound) _Pragma( STRINGIFY(data_alignment=##_bound##))
#define _PACKED_ __packed
#define _LONG_CALL_
#define _LONG_CALL_ROM_
#define _WEAK __weak
#else
#define SECTION(_name) __attribute__ ((__section__(_name)))
#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound)))
#define _PACKED_ __attribute__ ((packed))
#define _LONG_CALL_ __attribute__ ((long_call))
#define _LONG_CALL_ROM_ _LONG_CALL_
#define _WEAK __attribute__ ((weak))
#endif
//port from fw by thomas
// TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness
#define SWAP32(x) ((u32)( \
(((u32)(x) & (u32)0x000000ff) << 24) | \
(((u32)(x) & (u32)0x0000ff00) << 8) | \
(((u32)(x) & (u32)0x00ff0000) >> 8) | \
(((u32)(x) & (u32)0xff000000) >> 24)))
#define WAP16(x) ((u16)( \
(((u16)(x) & (u16)0x00ff) << 8) | \
(((u16)(x) & (u16)0xff00) >> 8)))
#if SYSTEM_ENDIAN == PLATFORM_LITTLE_ENDIAN
#ifndef rtk_le16_to_cpu
#define rtk_cpu_to_le32(x) ((u32)(x))
#define rtk_le32_to_cpu(x) ((u32)(x))
#define rtk_cpu_to_le16(x) ((u16)(x))
#define rtk_le16_to_cpu(x) ((u16)(x))
#define rtk_cpu_to_be32(x) SWAP32((x))
#define rtk_be32_to_cpu(x) SWAP32((x))
#define rtk_cpu_to_be16(x) WAP16((x))
#define rtk_be16_to_cpu(x) WAP16((x))
#endif
#elif SYSTEM_ENDIAN == PLATFORM_BIG_ENDIAN
#ifndef rtk_le16_to_cpu
#define rtk_cpu_to_le32(x) SWAP32((x))
#define rtk_le32_to_cpu(x) SWAP32((x))
#define rtk_cpu_to_le16(x) WAP16((x))
#define rtk_le16_to_cpu(x) WAP16((x))
#define rtk_cpu_to_be32(x) ((__u32)(x))
#define rtk_be32_to_cpu(x) ((__u32)(x))
#define rtk_cpu_to_be16(x) ((__u16)(x))
#define rtk_be16_to_cpu(x) ((__u16)(x))
#endif
#endif
/*
* Call endian free function when
* 1. Read/write packet content.
* 2. Before write integer to IO.
* 3. After read integer from IO.
*/
//
// Byte Swapping routine.
//
#define EF1Byte (u8)
#define EF2Byte le16_to_cpu
#define EF4Byte le32_to_cpu
//
// Read LE format data from memory
//
#define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr)))
#define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr)))
#define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr)))
//
// Write LE data to memory
//
#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val)
#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val)
#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val)
//
// Example:
// BIT_LEN_MASK_32(0) => 0x00000000
// BIT_LEN_MASK_32(1) => 0x00000001
// BIT_LEN_MASK_32(2) => 0x00000003
// BIT_LEN_MASK_32(32) => 0xFFFFFFFF
//
#define BIT_LEN_MASK_32(__BitLen) \
(0xFFFFFFFF >> (32 - (__BitLen)))
//
// Example:
// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
//
#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \
(BIT_LEN_MASK_32(__BitLen) << (__BitOffset))
//
// Description:
// Return 4-byte value in host byte ordering from
// 4-byte pointer in litten-endian system.
//
#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
(EF4Byte(*((u32 *)(__pStart))))
//
// Description:
// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to
// 4-byte value in host byte ordering.
//
#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_32(__BitLen) \
)
//
// Description:
// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering
// and return the result in 4-byte value in host byte ordering.
//
#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
& \
( ~ BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \
)
//
// Description:
// Set subfield of little-endian 4-byte value to specified value.
//
#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u32 *)(__pStart)) = \
EF4Byte( \
LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \
);
#define BIT_LEN_MASK_16(__BitLen) \
(0xFFFF >> (16 - (__BitLen)))
#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \
(BIT_LEN_MASK_16(__BitLen) << (__BitOffset))
#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
(EF2Byte(*((u16 *)(__pStart))))
#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_16(__BitLen) \
)
#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
& \
( ~ BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \
)
#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u16 *)(__pStart)) = \
EF2Byte( \
LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \
);
#define BIT_LEN_MASK_8(__BitLen) \
(0xFF >> (8 - (__BitLen)))
#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \
(BIT_LEN_MASK_8(__BitLen) << (__BitOffset))
#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
(EF1Byte(*((u8 *)(__pStart))))
#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_8(__BitLen) \
)
#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
& \
( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \
)
#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u8 *)(__pStart)) = \
EF1Byte( \
LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \
);
//pclint
#define LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \
( \
LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
)
//pclint
#define SET_BITS_TO_LE_1BYTE_8BIT(__pStart, __BitOffset, __BitLen, __Value) \
{ \
*((pu1Byte)(__pStart)) = \
EF1Byte( \
LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \
| \
((u1Byte)__Value) \
); \
}
// Get the N-bytes aligment offset from the current length
#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))
typedef unsigned char BOOLEAN,*PBOOLEAN;
#define TEST_FLAG(__Flag,__testFlag) (((__Flag) & (__testFlag)) != 0)
#define SET_FLAG(__Flag, __setFlag) ((__Flag) |= __setFlag)
#define CLEAR_FLAG(__Flag, __clearFlag) ((__Flag) &= ~(__clearFlag))
#define CLEAR_FLAGS(__Flag) ((__Flag) = 0)
#define TEST_FLAGS(__Flag, __testFlags) (((__Flag) & (__testFlags)) == (__testFlags))
/* Define compilor specific symbol */
//
// inline function
//
#if defined ( __ICCARM__ )
#define __inline__ inline
#define __inline inline
#define __inline_definition //In dialect C99, inline means that a function's definition is provided
//only for inlining, and that there is another definition
//(without inline) somewhere else in the program.
//That means that this program is incomplete, because if
//add isn't inlined (for example, when compiling without optimization),
//then main will have an unresolved reference to that other definition.
// Do not inline function is the function body is defined .c file and this
// function will be called somewhere else, otherwise there is compile error
#elif defined ( __CC_ARM )
#define __inline__ __inline //__linine__ is not supported in keil compilor, use __inline instead
#define inline __inline
#define __inline_definition // for dialect C99
#elif defined ( __GNUC__ )
#define __inline__ inline
#define __inline inline
#define __inline_definition inline
#endif
//
// pack
//
#if defined (__ICCARM__)
#define RTW_PACK_STRUCT_BEGIN _Pragma( STRINGIFY(pack(1)))
#define RTW_PACK_STRUCT_STRUCT
#define RTW_PACK_STRUCT_END _Pragma( STRINGIFY(pack()))
//#define RTW_PACK_STRUCT_USE_INCLUDES
#elif defined (__CC_ARM)
#define RTW_PACK_STRUCT_BEGIN __packed
#define RTW_PACK_STRUCT_STRUCT
#define RTW_PACK_STRUCT_END
#elif defined (__GNUC__)
#define RTW_PACK_STRUCT_BEGIN
#define RTW_PACK_STRUCT_STRUCT __attribute__ ((__packed__))
#define RTW_PACK_STRUCT_END
#elif defined(PLATFORM_WINDOWS)
#define RTW_PACK_STRUCT_BEGIN
#define RTW_PACK_STRUCT_STRUCT
#define RTW_PACK_STRUCT_END
#define RTW_PACK_STRUCT_USE_INCLUDES
#endif
// for standard library
#ifdef __ICCARM__
#define __extension__ /* Ignore */
#define __restrict /* Ignore */
#endif
typedef struct _RAM_START_FUNCTION_ {
VOID (*RamStartFun) (VOID);
}RAM_START_FUNCTION, *PRAM_START_FUNCTION;
typedef struct _RAM_FUNCTION_START_TABLE_ {
VOID (*RamStartFun) (VOID);
VOID (*RamWakeupFun) (VOID);
VOID (*RamPatchFun0) (VOID);
VOID (*RamPatchFun1) (VOID);
VOID (*RamPatchFun2) (VOID);
}RAM_FUNCTION_START_TABLE, *PRAM_FUNCTION_START_TABLE;
#endif// __BASIC_TYPES_H__

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#ifndef _CORTEX_H_
#define _CORTEX_H_
#include <stdint.h>
typedef struct{
volatile uint32_t ISER[8];
uint32_t RESERVED1[24];
volatile uint32_t ICER[8];
uint32_t RESERVED2[24];
volatile uint32_t ISPR[8];
uint32_t RESERVED3[24];
volatile uint32_t ICPR[8];
uint32_t RESERVED4[24];
volatile uint32_t IABR[8];
uint32_t RESERVED5[56];
volatile uint32_t IPR[32];
}NVIC_TypeDef;
typedef struct{
uint32_t RESERVED1[2];
volatile uint32_t ACTLR;
uint32_t RESERVED2[829];
volatile const uint32_t CPUID;
volatile uint32_t ICSR;
volatile uint32_t VTOR;
volatile uint32_t AIRCR;
volatile uint32_t SCR;
volatile uint32_t CCR;
volatile uint32_t SHPR[3];
volatile uint32_t SHCSR;
volatile uint32_t CFSR;
volatile uint32_t HFSR;
volatile uint32_t DFSR;
volatile uint32_t MMFAR;
volatile uint32_t BFAR;
volatile uint32_t AFSR;
volatile const uint32_t PFR[2];
volatile const uint32_t DFR;
volatile const uint32_t AFR;
volatile const uint32_t MMFR[4];
volatile const uint32_t ISAR[5];
uint32_t RESERVED3[5];
volatile uint32_t CPACR;
}SCB_TypeDef;
#define NVIC ((NVIC_TypeDef *)0xE000E100)
#define SCB ((SCB_TypeDef *)0xE000E000)
// SCB_AIRCR
#define SCB_AIRCR_VECTRESET (((uint32_t)0x0001) << 0)
#define SCB_AIRCR_VECTCLRACTIVE (((uint32_t)0x0001) << 1)
#define SCB_AIRCR_SYSRESETREQ (((uint32_t)0x0001) << 2)
#define SCB_AIRCR_PRIGROUP (((uint32_t)0x0007) << 8)
#define SCB_AIRCR_VECTKEY (((uint32_t)0xFFFF) << 16)
#define SCB_AIRCR_VECTKEYSTAT (((uint32_t)0xFFFF) << 16)
// SCB_CPACR
#define SCB_CPACR_CP10 (((uint32_t)0x03) << 20)
#define SCB_CPACR_CP11 (((uint32_t)0x03) << 22)
#define cortex_interrupt_set_priority(i, p) (NVIC->IPR[(i) >> 2] = ((NVIC->IPR[(i) >> 2] & ~(((uint32_t)0xFF) << (((i) & 0x03) << 3))) | (((uint32_t)p) << (((i) & 0x03) << 3))))
#define cortex_interrupt_enable(i) (NVIC->ISER[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
#define cortex_interrupt_disable(i) (NVIC->ICER[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
#define cortex_interrupt_clear(i) (NVIC->ICPR[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
#define cortex_interrupts_disable() __asm__("cpsid f")
#define cortex_interrupts_enable() __asm__("cpsie f")
#define interrupts_disable() __asm__("cpsid f")
#define interrupts_enable() __asm__("cpsie f")
#define CORTEX_ISR(n) _CORTEX_ISR(n)
#define _CORTEX_ISR(n) void __attribute__((interrupt)) CORTEX_INTERRUPT_##n##_Handler()
void cortex_bootstrap(void *start) __attribute__ ((noreturn));
void cortex_reboot() __attribute__ ((noreturn));
#endif

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proc cortex_bootstrap {start} {
# disable interrupts
reg faultmask 0x01
set vectors ""
mem2array vectors 32 $start 2
reg sp $vectors(0)
reg pc $vectors(1)
resume
}
proc cortex_reboot {} {
mww 0xE000ED0C 0x05FA0007
}

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SECTIONS
{
__vectors_table = 0x0;
Reset_Handler = 0x101;
NMI_Handler = 0x109;
HardFault_Handler = 0x10d;
MemManage_Handler = 0x121;
BusFault_Handler = 0x125;
UsageFault_Handler = 0x129;
HalLogUartInit = 0x201;
HalSerialPutcRtl8195a = 0x2d9;
HalSerialGetcRtl8195a = 0x309;
HalSerialGetIsrEnRegRtl8195a = 0x329;
HalSerialSetIrqEnRegRtl8195a = 0x335;
HalCpuClkConfig = 0x341;
HalGetCpuClk = 0x355;
HalRomInfo = 0x39d;
HalGetRomInfo = 0x3b5;
HalResetVsr = 0x3c5;
HalDelayUs = 0x899;
HalNMIHandler = 0x8e1;
HalHardFaultHandler = 0x911;
HalMemManageHandler = 0xc09;
HalBusFaultHandler = 0xc39;
HalUsageFaultHandler = 0xc69;
HalUart0PinCtrlRtl8195A = 0xcfd;
HalUart1PinCtrlRtl8195A = 0xdc9;
HalUart2PinCtrlRtl8195A = 0xe9d;
HalSPI0PinCtrlRtl8195A = 0xf75;
HalSPI1PinCtrlRtl8195A = 0x1015;
HalSPI2PinCtrlRtl8195A = 0x10e5;
HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
HalI2C0PinCtrlRtl8195A = 0x1275;
HalI2C1PinCtrlRtl8195A = 0x1381;
HalI2C2PinCtrlRtl8195A = 0x1459;
HalI2C3PinCtrlRtl8195A = 0x1529;
HalI2S0PinCtrlRtl8195A = 0x1639;
HalI2S1PinCtrlRtl8195A = 0x176d;
HalPCM0PinCtrlRtl8195A = 0x1845;
HalPCM1PinCtrlRtl8195A = 0x1949;
HalSDIODPinCtrlRtl8195A = 0x1a1d;
HalSDIOHPinCtrlRtl8195A = 0x1a6d;
HalMIIPinCtrlRtl8195A = 0x1ab9;
HalWLLEDPinCtrlRtl8195A = 0x1b51;
HalWLANT0PinCtrlRtl8195A = 0x1c0d;
HalWLANT1PinCtrlRtl8195A = 0x1c61;
HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
HalNFCPinCtrlRtl8195A = 0x1d59;
HalPWM0PinCtrlRtl8195A = 0x1da9;
HalPWM1PinCtrlRtl8195A = 0x1ead;
HalPWM2PinCtrlRtl8195A = 0x1fb5;
HalPWM3PinCtrlRtl8195A = 0x20b1;
HalETE0PinCtrlRtl8195A = 0x21b9;
HalETE1PinCtrlRtl8195A = 0x22c1;
HalETE2PinCtrlRtl8195A = 0x23c9;
HalETE3PinCtrlRtl8195A = 0x24d1;
HalEGTIMPinCtrlRtl8195A = 0x25d9;
HalSPIFlashPinCtrlRtl8195A = 0x2679;
HalSDRPinCtrlRtl8195A = 0x2725;
HalJTAGPinCtrlRtl8195A = 0x280d;
HalTRACEPinCtrlRtl8195A = 0x2861;
HalLOGUartPinCtrlRtl8195A = 0x28b9;
HalLOGUartIRPinCtrlRtl8195A = 0x291d;
HalSICPinCtrlRtl8195A = 0x2981;
HalEEPROMPinCtrlRtl8195A = 0x29d9;
HalDEBUGPinCtrlRtl8195A = 0x2a31;
HalPinCtrlRtl8195A = 0x2b39;
SpicRxCmdRtl8195A = 0x2e5d;
SpicWaitBusyDoneRtl8195A = 0x2ea5;
SpicGetFlashStatusRtl8195A = 0x2eb5;
SpicWaitWipDoneRtl8195A = 0x2f55;
SpicTxCmdRtl8195A = 0x2f6d;
SpicSetFlashStatusRtl8195A = 0x2fc1;
SpicCmpDataForCalibrationRtl8195A = 0x3049;
SpicLoadInitParaFromClockRtl8195A = 0x3081;
SpicInitRtl8195A = 0x30e5;
SpicEraseFlashRtl8195A = 0x31bd;
SpiFlashApp = 0x3279;
HalPeripheralIntrHandle = 0x33b5;
HalSysOnIntrHandle = 0x3439;
HalWdgIntrHandle = 0x3485;
HalTimer0IntrHandle = 0x34d5;
HalTimer1IntrHandle = 0x3525;
HalI2C3IntrHandle = 0x3575;
HalTimer2To7IntrHandle = 0x35c5;
HalSpi0IntrHandle = 0x3615;
HalGpioIntrHandle = 0x3665;
HalUart0IntrHandle = 0x36b5;
HalSpiFlashIntrHandle = 0x3705;
HalUsbOtgIntrHandle = 0x3755;
HalSdioHostIntrHandle = 0x37a5;
HalI2s0OrPcm0IntrHandle = 0x37f5;
HalI2s1OrPcm1IntrHandle = 0x3845;
HalWlDmaIntrHandle = 0x3895;
HalWlProtocolIntrHandle = 0x38e5;
HalCryptoIntrHandle = 0x3935;
HalGmacIntrHandle = 0x3985;
HalGdma0Ch0IntrHandle = 0x39d5;
HalGdma0Ch1IntrHandle = 0x3a25;
HalGdma0Ch2IntrHandle = 0x3a75;
HalGdma0Ch3IntrHandle = 0x3ac5;
HalGdma0Ch4IntrHandle = 0x3b15;
HalGdma0Ch5IntrHandle = 0x3b65;
HalGdma1Ch0IntrHandle = 0x3bb5;
HalGdma1Ch1IntrHandle = 0x3c05;
HalGdma1Ch2IntrHandle = 0x3c55;
HalGdma1Ch3IntrHandle = 0x3ca5;
HalGdma1Ch4IntrHandle = 0x3cf5;
HalGdma1Ch5IntrHandle = 0x3d45;
HalSdioDeviceIntrHandle = 0x3d95;
VectorTableInitRtl8195A = 0x3de5;
VectorTableInitForOSRtl8195A = 0x4019;
VectorIrqRegisterRtl8195A = 0x4029;
VectorIrqUnRegisterRtl8195A = 0x4091;
VectorIrqEnRtl8195A = 0x40f1;
VectorIrqDisRtl8195A = 0x418d;
_UartRxDmaIrqHandle = 0x422d;
HalRuartPutCRtl8195a = 0x4281;
HalRuartGetCRtl8195a = 0x429d;
HalRuartRTSCtrlRtl8195a = 0x42bd;
HalRuartGetDebugValueRtl8195a = 0x42e1;
HalRuartGetIMRRtl8195a = 0x43e1;
HalRuartSetIMRRtl8195a = 0x442d;
_UartIrqHandle = 0x4465;
HalRuartDmaInitRtl8195a = 0x4681;
HalRuartIntDisableRtl8195a = 0x4845;
HalRuartDeInitRtl8195a = 0x4855;
HalRuartIntEnableRtl8195a = 0x4985;
_UartTxDmaIrqHandle = 0x4995;
HalRuartRegIrqRtl8195a = 0x49d1;
HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
RuartLock = 0x4cc9;
RuartUnLock = 0x4ced;
HalRuartIntSendRtl8195a = 0x4d09;
HalRuartDmaSendRtl8195a = 0x4e35;
HalRuartStopSendRtl8195a = 0x4f89;
HalRuartIntRecvRtl8195a = 0x504d;
HalRuartDmaRecvRtl8195a = 0x51ad;
HalRuartStopRecvRtl8195a = 0x52cd;
RuartIsTimeout = 0x5385;
HalRuartSendRtl8195a = 0x53b1;
HalRuartRecvRtl8195a = 0x5599;
RuartResetRxFifoRtl8195a = 0x5751;
HalRuartResetRxFifoRtl8195a = 0x5775;
HalRuartInitRtl8195a = 0x5829;
HalGdmaOnOffRtl8195a = 0x5df1;
HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
HalGdmaChEnRtl8195a = 0x5e51;
HalGdmaChDisRtl8195a = 0x5e6d;
HalGdamChInitRtl8195a = 0x5e91;
HalGdmaChSetingRtl8195a = 0x5ebd;
HalGdmaChIsrCleanRtl8195a = 0x6419;
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
HalEFUSEPowerSwitch8195AROM = 0x6561;
HALEFUSEOneByteReadROM = 0x65f9;
HALEFUSEOneByteWriteROM = 0x6699;
rtl_memcmpb_v1_00 = 0x681d;
rtl_random_v1_00 = 0x6861;
rtl_align_to_be32_v1_00 = 0x6881;
rtl_memsetw_v1_00 = 0x6899;
rtl_memsetb_v1_00 = 0x68ad;
rtl_memcpyw_v1_00 = 0x68bd;
rtl_memcpyb_v1_00 = 0x68dd;
rtl_memDump_v1_00 = 0x68f5;
rtl_AES_set_encrypt_key = 0x6901;
rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
rtl_cryptoEngine_init_v1_00 = 0x6ea9;
rtl_cryptoEngine_exit_v1_00 = 0x7055;
rtl_cryptoEngine_reset_v1_00 = 0x70b1;
rtl_cryptoEngine_v1_00 = 0x70ed;
rtl_crypto_cipher_init_v1_00 = 0x7c69;
rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
HalSsiPinmuxEnableRtl8195a = 0x7cd5;
HalSsiEnableRtl8195a = 0x7e45;
HalSsiDisableRtl8195a = 0x7ef9;
HalSsiLoadSettingRtl8195a = 0x7fad;
HalSsiSetInterruptMaskRtl8195a = 0x8521;
HalSsiGetInterruptMaskRtl8195a = 0x85c9;
HalSsiSetSclkPolarityRtl8195a = 0x863d;
HalSsiSetSclkPhaseRtl8195a = 0x8715;
HalSsiWriteRtl8195a = 0x87e9;
HalSsiSetDeviceRoleRtl8195a = 0x8861;
HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
HalSsiReadRtl8195a = 0x89b9;
HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
HalSsiGetStatusRtl8195a = 0x8b1d;
HalSsiWriteableRtl8195a = 0x8b91;
HalSsiReadableRtl8195a = 0x8c09;
HalSsiBusyRtl8195a = 0x8c81;
HalSsiReadInterruptRtl8195a = 0x8cf9;
HalSsiWriteInterruptRtl8195a = 0x8efd;
HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
HalSsiGetInterruptStatusRtl8195a = 0x90d9;
HalSsiInterruptEnableRtl8195a = 0x914d;
HalSsiInterruptDisableRtl8195a = 0x9299;
HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
HalSsiInitRtl8195a = 0x94d1;
_SsiReadInterrupt = 0x9ba5;
_SsiWriteInterrupt = 0x9db1;
_SsiIrqHandle = 0x9eb1;
HalI2CWrite32 = 0xa061;
HalI2CRead32 = 0xa09d;
HalI2CDeInit8195a = 0xa0dd;
HalI2CSendRtl8195a = 0xa1f1;
HalI2CReceiveRtl8195a = 0xa25d;
HalI2CEnableRtl8195a = 0xa271;
HalI2CIntrCtrl8195a = 0xa389;
HalI2CReadRegRtl8195a = 0xa3a1;
HalI2CWriteRegRtl8195a = 0xa3b1;
HalI2CSetCLKRtl8195a = 0xa3c5;
HalI2CMassSendRtl8195a = 0xa6e9;
HalI2CClrIntrRtl8195a = 0xa749;
HalI2CClrAllIntrRtl8195a = 0xa761;
HalI2CInit8195a = 0xa775;
HalI2CDMACtrl8195a = 0xaa31;
RtkI2CIoCtrl = 0xaa61;
RtkI2CPowerCtrl = 0xaa65;
HalI2COpInit = 0xaa69;
I2CIsTimeout = 0xac65;
I2CTXGDMAISRHandle = 0xb435;
I2CRXGDMAISRHandle = 0xb4c1;
RtkI2CIrqInit = 0xb54d;
RtkI2CIrqDeInit = 0xb611;
RtkI2CPinMuxInit = 0xb675;
RtkI2CPinMuxDeInit = 0xb7c9;
RtkI2CDMAInit = 0xb955;
RtkI2CInit = 0xbc95;
RtkI2CDMADeInit = 0xbdad;
RtkI2CDeInit = 0xbe4d;
RtkI2CSendUserAddr = 0xbee5;
RtkI2CSend = 0xc07d;
RtkI2CLoadDefault = 0xce51;
RtkSalI2COpInit = 0xcf21;
HalI2SWrite32 = 0xcf65;
HalI2SRead32 = 0xcf85;
HalI2SDeInitRtl8195a = 0xcfa9;
HalI2STxRtl8195a = 0xcfc9;
HalI2SRxRtl8195a = 0xd011;
HalI2SEnableRtl8195a = 0xd05d;
HalI2SIntrCtrlRtl8195a = 0xd0b1;
HalI2SReadRegRtl8195a = 0xd0d1;
HalI2SClrIntrRtl8195a = 0xd0dd;
HalI2SClrAllIntrRtl8195a = 0xd0fd;
HalI2SInitRtl8195a = 0xd11d;
GPIO_GetIPPinName_8195a = 0xd2e5;
GPIO_GetChipPinName_8195a = 0xd331;
GPIO_PullCtrl_8195a = 0xd39d;
GPIO_FuncOn_8195a = 0xd421;
GPIO_FuncOff_8195a = 0xd481;
GPIO_Int_Mask_8195a = 0xd4e9;
GPIO_Int_SetType_8195a = 0xd511;
HAL_GPIO_IrqHandler_8195a = 0xd5fd;
HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
HAL_GPIO_IntCtrl_8195a = 0xd6cd;
HAL_GPIO_Init_8195a = 0xd805;
HAL_GPIO_DeInit_8195a = 0xdac1;
HAL_GPIO_ReadPin_8195a = 0xdbd1;
HAL_GPIO_WritePin_8195a = 0xdc91;
HAL_GPIO_RegIrq_8195a = 0xddad;
HAL_GPIO_UnRegIrq_8195a = 0xddf5;
HAL_GPIO_UserRegIrq_8195a = 0xde15;
HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
HAL_GPIO_MaskIrq_8195a = 0xdfc1;
HAL_GPIO_UnMaskIrq_8195a = 0xe061;
HAL_GPIO_IntDebounce_8195a = 0xe101;
HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
HAL_GPIO_PullCtrl_8195a = 0xe1c9;
DumpForOneBytes = 0xe259;
CmdRomHelp = 0xe419;
CmdWriteWord = 0xe491;
CmdDumpHelfWord = 0xe505;
CmdDumpWord = 0xe5f1;
CmdDumpByte = 0xe6f5;
CmdSpiFlashTool = 0xe751;
GetRomCmdNum = 0xe7a9;
CmdWriteByte = 0xe7ad;
Isspace = 0xe7ed;
Strtoul = 0xe801;
ArrayInitialize = 0xe8b1;
GetArgc = 0xe8c9;
GetArgv = 0xe8f9;
UartLogCmdExecute = 0xe95d;
UartLogShowBackSpace = 0xe9fd;
UartLogRecallOldCmd = 0xea39;
UartLogHistoryCmd = 0xea71;
UartLogCmdChk = 0xeadd;
UartLogIrqHandle = 0xebf5;
RtlConsolInit = 0xecc5;
RtlConsolTaskRom = 0xed49;
RtlExitConsol = 0xed79;
RtlConsolRom = 0xedcd;
HalTimerOpInit = 0xee0d;
HalTimerIrq2To7Handle = 0xee59;
HalGetTimerIdRtl8195a = 0xef09;
HalTimerInitRtl8195a = 0xef3d;
HalTimerDisRtl8195a = 0xf069;
HalTimerEnRtl8195a = 0xf089;
HalTimerReadCountRtl8195a = 0xf0a9;
HalTimerIrqClearRtl8195a = 0xf0bd;
HalTimerDumpRegRtl8195a = 0xf0d1;
VSprintf = 0xf129;
DiagPrintf = 0xf39d;
DiagSPrintf = 0xf3b9;
DiagSnPrintf = 0xf3d1;
prvDiagPrintf = 0xf3ed;
prvDiagSPrintf = 0xf40d;
_memcmp = 0xf429;
_memcpy = 0xf465;
_memset = 0xf511;
Rand = 0xf585;
_strncpy = 0xf60d;
_strcpy = 0xf629;
prvStrCpy = 0xf639;
_strlen = 0xf651;
_strnlen = 0xf669;
prvStrLen = 0xf699;
_strcmp = 0xf6b1;
_strncmp = 0xf6d1;
prvStrCmp = 0xf719;
StrUpr = 0xf749;
prvAtoi = 0xf769;
prvStrStr = 0xf7bd;
_strsep = 0xf7d5;
skip_spaces = 0xf815;
skip_atoi = 0xf831;
_parse_integer_fixup_radix = 0xf869;
_parse_integer = 0xf8bd;
simple_strtoull = 0xf915;
simple_strtoll = 0xf945;
simple_strtoul = 0xf965;
simple_strtol = 0xf96d;
_vsscanf = 0xf985;
_sscanf = 0xff71;
div_u64 = 0xff91;
div_s64 = 0xff99;
div_u64_rem = 0xffa1;
div_s64_rem = 0xffb1;
_strpbrk = 0xffc1;
_strchr = 0xffed;
aes_set_key = 0x10005;
aes_encrypt = 0x103d1;
aes_decrypt = 0x114a5;
AES_WRAP = 0x125c9;
AES_UnWRAP = 0x12701;
crc32_get = 0x12861;
arc4_byte = 0x12895;
rt_arc4_init = 0x128bd;
rt_arc4_crypt = 0x12901;
rt_md5_init = 0x131c1;
rt_md5_append = 0x131f5;
rt_md5_final = 0x1327d;
rt_md5_hmac = 0x132d5;
rtw_get_bit_value_from_ieee_value = 0x13449;
rtw_is_cckrates_included = 0x13475;
rtw_is_cckratesonly_included = 0x134b5;
rtw_check_network_type = 0x134dd;
rtw_set_fixed_ie = 0x1350d;
rtw_set_ie = 0x1352d;
rtw_get_ie = 0x1355d;
rtw_set_supported_rate = 0x13591;
rtw_get_rateset_len = 0x13611;
rtw_get_wpa_ie = 0x1362d;
rtw_get_wpa2_ie = 0x136c9;
rtw_get_wpa_cipher_suite = 0x13701;
rtw_get_wpa2_cipher_suite = 0x13769;
rtw_parse_wpa_ie = 0x137d1;
rtw_parse_wpa2_ie = 0x138ad;
rtw_get_sec_ie = 0x13965;
rtw_get_wps_ie = 0x13a15;
rtw_get_wps_attr = 0x13a99;
rtw_get_wps_attr_content = 0x13b49;
rtw_ieee802_11_parse_elems = 0x13b91;
str_2char2num = 0x13d9d;
key_2char2num = 0x13db9;
convert_ip_addr = 0x13dd1;
rom_psk_PasswordHash = 0x13e9d;
rom_psk_CalcGTK = 0x13ed5;
rom_psk_CalcPTK = 0x13f69;
wep_80211_encrypt = 0x14295;
wep_80211_decrypt = 0x142f5;
tkip_micappendbyte = 0x14389;
rtw_secmicsetkey = 0x143d9;
rtw_secmicappend = 0x14419;
rtw_secgetmic = 0x14435;
rtw_seccalctkipmic = 0x1449d;
tkip_phase1 = 0x145a5;
tkip_phase2 = 0x14725;
tkip_80211_encrypt = 0x14941;
tkip_80211_decrypt = 0x149d5;
aes1_encrypt = 0x14a8d;
aesccmp_construct_mic_iv = 0x14c65;
aesccmp_construct_mic_header1 = 0x14ccd;
aesccmp_construct_mic_header2 = 0x14d21;
aesccmp_construct_ctr_preload = 0x14db5;
aes_80211_encrypt = 0x14e29;
aes_80211_decrypt = 0x151ad;
_sha1_process_message_block = 0x155b9;
_sha1_pad_message = 0x15749;
rt_sha1_init = 0x157e5;
rt_sha1_update = 0x15831;
rt_sha1_finish = 0x158a9;
rt_hmac_sha1 = 0x15909;
rom_aes_128_cbc_encrypt = 0x15a65;
rom_aes_128_cbc_decrypt = 0x15ae1;
rom_rijndaelKeySetupEnc = 0x15b5d;
rom_aes_decrypt_init = 0x15c39;
rom_aes_internal_decrypt = 0x15d15;
rom_aes_decrypt_deinit = 0x16071;
rom_aes_encrypt_init = 0x16085;
rom_aes_internal_encrypt = 0x1609d;
rom_aes_encrypt_deinit = 0x16451;
bignum_init = 0x17b35;
bignum_deinit = 0x17b61;
bignum_get_unsigned_bin_len = 0x17b81;
bignum_get_unsigned_bin = 0x17b85;
bignum_set_unsigned_bin = 0x17c21;
bignum_cmp = 0x17cd1;
bignum_cmp_d = 0x17cd5;
bignum_add = 0x17cfd;
bignum_sub = 0x17d0d;
bignum_mul = 0x17d1d;
bignum_exptmod = 0x17d2d;
WPS_realloc = 0x17d51;
os_zalloc = 0x17d99;
rom_hmac_sha256_vector = 0x17dc1;
rom_hmac_sha256 = 0x17ebd;
rom_sha256_vector = 0x18009;
phy_CalculateBitShift = 0x18221;
PHY_SetBBReg_8195A = 0x18239;
PHY_QueryBBReg_8195A = 0x18279;
ROM_odm_QueryRxPwrPercentage = 0x1829d;
ROM_odm_EVMdbToPercentage = 0x182bd;
ROM_odm_SignalScaleMapping_8195A = 0x182e5;
ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
ROM_odm_SetEDCCAThreshold = 0x18721;
ROM_odm_SetTRxMux = 0x18749;
ROM_odm_SetCrystalCap = 0x18771;
ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
ROM_ODM_CfoTrackingReset = 0x187e9;
ROM_odm_CfoTrackingFlow = 0x18811;
curve25519_donna = 0x1965d;
aes_test_alignment_detection = 0x1a391;
aes_mode_reset = 0x1a3ed;
aes_ecb_encrypt = 0x1a3f9;
aes_ecb_decrypt = 0x1a431;
aes_cbc_encrypt = 0x1a469;
aes_cbc_decrypt = 0x1a579;
aes_cfb_encrypt = 0x1a701;
aes_cfb_decrypt = 0x1a9e5;
aes_ofb_crypt = 0x1acc9;
aes_ctr_crypt = 0x1af7d;
aes_encrypt_key128 = 0x1b289;
aes_encrypt_key192 = 0x1b2a5;
aes_encrypt_key256 = 0x1b2c1;
aes_encrypt_key = 0x1b2e1;
aes_decrypt_key128 = 0x1b351;
aes_decrypt_key192 = 0x1b36d;
aes_decrypt_key256 = 0x1b389;
aes_decrypt_key = 0x1b3a9;
aes_init = 0x1b419;
CRYPTO_chacha_20 = 0x1b41d;
CRYPTO_poly1305_init = 0x1bc25;
CRYPTO_poly1305_update = 0x1bd09;
CRYPTO_poly1305_finish = 0x1bd8d;
rom_sha512_starts = 0x1ceb5;
rom_sha512_update = 0x1d009;
rom_sha512_finish = 0x1d011;
rom_sha512 = 0x1d261;
rom_sha512_hmac_starts = 0x1d299;
rom_sha512_hmac_update = 0x1d35d;
rom_sha512_hmac_finish = 0x1d365;
rom_sha512_hmac_reset = 0x1d3b5;
rom_sha512_hmac = 0x1d3d1;
rom_sha512_hkdf = 0x1d40d;
rom_ed25519_gen_keypair = 0x1d501;
rom_ed25519_gen_signature = 0x1d505;
rom_ed25519_verify_signature = 0x1d51d;
rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
rom_ed25519_crypto_sign_detached = 0x1d579;
rom_ed25519_crypto_sign_verify_detached = 0x1d655;
rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
rom_ed25519_ge_p3_tobytes = 0x207d5;
rom_ed25519_ge_scalarmult_base = 0x20821;
rom_ed25519_ge_tobytes = 0x209e1;
rom_ed25519_sc_muladd = 0x20a2d;
rom_ed25519_sc_reduce = 0x2603d;
rtl_memchr_v1_00 = 0x28a4d;
rtl_memcmp_v1_00 = 0x28ae1;
rtl_memcpy_v1_00 = 0x28b49;
__aeabi_memcpy = 0x28b49;
__aeabi_memcpy4 = 0x28b49;
rtl_memmove_v1_00 = 0x28bed;
rtl_memset_v1_00 = 0x28cb5;
__aeabi_memset = 0x28cb5;
rtl_strcat_v1_00 = 0x28d49;
rtl_strchr_v1_00 = 0x28d91;
rtl_strcmp_v1_00 = 0x28e55;
rtl_strcpy_v1_00 = 0x28ec9;
rtl_strlen_v1_00 = 0x28f15;
rtl_strncat_v1_00 = 0x28f69;
rtl_strncmp_v1_00 = 0x28fc5;
rtl_strncpy_v1_00 = 0x2907d;
rtl_strstr_v1_00 = 0x293cd;
rtl_strsep_v1_00 = 0x2960d;
rtl_strtok_v1_00 = 0x29619;
rtl__strtok_r_v1_00 = 0x2962d;
rtl_strtok_r_v1_00 = 0x29691;
rtl_close_v1_00 = 0x29699;
rtl_fstat_v1_00 = 0x296ad;
rtl_isatty_v1_00 = 0x296c1;
rtl_lseek_v1_00 = 0x296d5;
rtl_open_v1_00 = 0x296e9;
rtl_read_v1_00 = 0x296fd;
rtl_write_v1_00 = 0x29711;
rtl_sbrk_v1_00 = 0x29725;
rtl_ltoa_v1_00 = 0x297bd;
rtl_ultoa_v1_00 = 0x29855;
rtl_dtoi_v1_00 = 0x298c5;
rtl_dtoi64_v1_00 = 0x29945;
rtl_dtoui_v1_00 = 0x299dd;
rtl_ftol_v1_00 = 0x299e5;
rtl_itof_v1_00 = 0x29a51;
rtl_itod_v1_00 = 0x29ae9;
rtl_i64tod_v1_00 = 0x29b79;
rtl_uitod_v1_00 = 0x29c55;
rtl_ftod_v1_00 = 0x29d2d;
rtl_dtof_v1_00 = 0x29de9;
rtl_uitof_v1_00 = 0x29e89;
rtl_fadd_v1_00 = 0x29f65;
rtl_fsub_v1_00 = 0x2a261;
rtl_fmul_v1_00 = 0x2a559;
rtl_fdiv_v1_00 = 0x2a695;
rtl_dadd_v1_00 = 0x2a825;
rtl_dsub_v1_00 = 0x2aed9;
rtl_dmul_v1_00 = 0x2b555;
rtl_ddiv_v1_00 = 0x2b8ad;
rtl_dcmpeq_v1_00 = 0x2be4d;
rtl_dcmplt_v1_00 = 0x2bebd;
rtl_dcmpgt_v1_00 = 0x2bf51;
rtl_dcmple_v1_00 = 0x2c049;
rtl_fcmplt_v1_00 = 0x2c139;
rtl_fcmpgt_v1_00 = 0x2c195;
rtl_cos_f32_v1_00 = 0x2c229;
rtl_sin_f32_v1_00 = 0x2c435;
rtl_fabs_v1_00 = 0x2c639;
rtl_fabsf_v1_00 = 0x2c641;
rtl_dtoa_r_v1_00 = 0x2c77d;
__rom_mallocr_init_v1_00 = 0x2d7d1;
rtl_free_r_v1_00 = 0x2d841;
rtl_malloc_r_v1_00 = 0x2da31;
rtl_realloc_r_v1_00 = 0x2df55;
rtl_memalign_r_v1_00 = 0x2e331;
rtl_valloc_r_v1_00 = 0x2e421;
rtl_pvalloc_r_v1_00 = 0x2e42d;
rtl_calloc_r_v1_00 = 0x2e441;
rtl_cfree_r_v1_00 = 0x2e4a9;
rtl_Balloc_v1_00 = 0x2e515;
rtl_Bfree_v1_00 = 0x2e571;
rtl_i2b_v1_00 = 0x2e585;
rtl_multadd_v1_00 = 0x2e599;
rtl_mult_v1_00 = 0x2e629;
rtl_pow5mult_v1_00 = 0x2e769;
rtl_hi0bits_v1_00 = 0x2e809;
rtl_d2b_v1_00 = 0x2e845;
rtl_lshift_v1_00 = 0x2e901;
rtl_cmp_v1_00 = 0x2e9bd;
rtl_diff_v1_00 = 0x2ea01;
rtl_sread_v1_00 = 0x2eae9;
rtl_seofread_v1_00 = 0x2eb39;
rtl_swrite_v1_00 = 0x2eb3d;
rtl_sseek_v1_00 = 0x2ebc1;
rtl_sclose_v1_00 = 0x2ec11;
rtl_sbrk_r_v1_00 = 0x2ec41;
rtl_fflush_r_v1_00 = 0x2ef8d;
rtl_vfprintf_r_v1_00 = 0x2f661;
rtl_fpclassifyd = 0x30c15;
CpkClkTbl = 0x30c68;
ROM_IMG1_VALID_PATTEN = 0x30c80;
SpicCalibrationPattern = 0x30c88;
SpicInitCPUCLK = 0x30c98;
BAUDRATE = 0x30ca8;
OVSR = 0x30d1c;
DIV = 0x30d90;
OVSR_ADJ = 0x30e04;
__AES_rcon = 0x30e78;
__AES_Te4 = 0x30ea0;
I2CDmaChNo = 0x312a0;
_GPIO_PinMap_Chip2IP_8195a = 0x312b4;
_GPIO_PinMap_PullCtrl_8195a = 0x3136c;
_GPIO_SWPORT_DDR_TBL = 0x31594;
_GPIO_EXT_PORT_TBL = 0x31598;
_GPIO_SWPORT_DR_TBL = 0x3159c;
UartLogRomCmdTable = 0x316a0;
_HalRuartOp = 0x31700;
_HalGdmaOp = 0x31760;
RTW_WPA_OUI_TYPE = 0x3540c;
WPA_CIPHER_SUITE_NONE = 0x35410;
WPA_CIPHER_SUITE_WEP40 = 0x35414;
WPA_CIPHER_SUITE_TKIP = 0x35418;
WPA_CIPHER_SUITE_CCMP = 0x3541c;
WPA_CIPHER_SUITE_WEP104 = 0x35420;
RSN_CIPHER_SUITE_NONE = 0x35424;
RSN_CIPHER_SUITE_WEP40 = 0x35428;
RSN_CIPHER_SUITE_TKIP = 0x3542c;
RSN_CIPHER_SUITE_CCMP = 0x35430;
RSN_CIPHER_SUITE_WEP104 = 0x35434;
RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
RSN_VERSION_BSD = 0x3544c;
rom_wps_Te0 = 0x35988;
rom_wps_rcons = 0x35d88;
rom_wps_Td4s = 0x35d94;
rom_wps_Td0 = 0x35e94;
__rom_b_cut_end__ = 0x4467c;
__rom_c_cut_text_start__ = 0x4467c;
HalInitPlatformLogUartV02 = 0x4467d;
HalReInitPlatformLogUartV02 = 0x4471d;
HalInitPlatformTimerV02 = 0x44755;
HalShowBuildInfoV02 = 0x447cd;
SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
HalSpiInitV02 = 0x4488d;
HalBootFlowV02 = 0x44a29;
HalInitialROMCodeGlobalVarV02 = 0x44ae5;
HalResetVsrV02 = 0x44b41;
HalI2CSendRtl8195aV02 = 0x44ce1;
HalI2CSetCLKRtl8195aV02 = 0x44d59;
RtkI2CSendV02 = 0x4508d;
RtkI2CReceiveV02 = 0x459a1;
HalI2COpInitV02 = 0x461ed;
I2CISRHandleV02 = 0x463e9;
RtkSalI2COpInitV02 = 0x46be1;
SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
SpiFlashAppV02 = 0x46c85;
SpicInitRtl8195AV02 = 0x46dc5;
SpicEraseFlashRtl8195AV02 = 0x46ea1;
HalTimerIrq2To7HandleV02 = 0x46f5d;
HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
HalTimerInitRtl8195aV02 = 0x4706d;
HalTimerReadCountRtl8195aV02 = 0x471b5;
HalTimerReLoadRtl8195aV02 = 0x471d1;
HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
HalTimerDeInitRtl8195aV02 = 0x472c1;
HalTimerOpInitV02 = 0x472f9;
GPIO_LockV02 = 0x47345;
GPIO_UnLockV02 = 0x47379;
GPIO_Int_Clear_8195aV02 = 0x473a5;
HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
FindElementIndexV02 = 0x47541;
HalRuartInitRtl8195aV02 = 0x4756d;
DramInit_rom = 0x47619;
ChangeRandSeed_rom = 0x47979;
Sdr_Rand2_rom = 0x47985;
MemTest_rom = 0x479dd;
SdrCalibration_rom = 0x47a45;
SdrControllerInit_rom = 0x47d99;
SDIO_EnterCritical = 0x47e39;
SDIO_ExitCritical = 0x47e85;
SDIO_IRQ_Handler_Rom = 0x47ec5;
SDIO_Interrupt_Init_Rom = 0x47f31;
SDIO_Device_Init_Rom = 0x47f81;
SDIO_Interrupt_DeInit_Rom = 0x48215;
SDIO_Device_DeInit_Rom = 0x48255;
SDIO_Enable_Interrupt_Rom = 0x48281;
SDIO_Disable_Interrupt_Rom = 0x482a1;
SDIO_Clear_ISR_Rom = 0x482c1;
SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
SDIO_Free_Rx_Pkt_Rom = 0x48331;
SDIO_Recycle_Rx_BD_Rom = 0x48355;
SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
SDIO_RxTask_Rom = 0x4851d;
SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
SDIO_Process_RPWM_Rom = 0x485b5;
SDIO_Reset_Cmd_Rom = 0x485e9;
SDIO_Rx_Data_Transaction_Rom = 0x48611;
SDIO_Send_C2H_PktMsg_Rom = 0x48829;
SDIO_Register_Tx_Callback_Rom = 0x488f5;
SDIO_ReadMem_Rom = 0x488fd;
SDIO_WriteMem_Rom = 0x489a9;
SDIO_SetMem_Rom = 0x48a69;
SDIO_TX_Pkt_Handle_Rom = 0x48b29;
SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
SDIO_IRQ_Handler_BH_Rom = 0x48d95;
SDIO_TxTask_Rom = 0x48e9d;
SDIO_TaskUp_Rom = 0x48eed;
SDIO_Boot_Up = 0x48f55;
__rom_c_cut_text_end__ = 0x49070;
__rom_c_cut_rodata_start__ = 0x49070;
BAUDRATE_v02 = 0x49070;
OVSR_v02 = 0x490fc;
DIV_v02 = 0x49188;
OVSR_ADJ_v02 = 0x49214;
SdrDramInfo_rom = 0x492a0;
SdrDramTiming_rom = 0x492b4;
SdrDramModeReg_rom = 0x492e8;
SdrDramDev_rom = 0x49304;
__rom_c_cut_rodata_end__ = 0x49314;
NewVectorTable = 0x10000000;
UserIrqFunTable = 0x10000100;
UserIrqDataTable = 0x10000200;
__rom_bss_start__ = 0x10000300;
CfgSysDebugWarn = 0x10000300;
CfgSysDebugInfo = 0x10000304;
CfgSysDebugErr = 0x10000308;
ConfigDebugWarn = 0x1000030c;
ConfigDebugInfo = 0x10000310;
ConfigDebugErr = 0x10000314;
HalTimerOp = 0x10000318;
GPIOState = 0x10000334;
gTimerRecord = 0x1000034c;
SSI_DBG_CONFIG = 0x10000350;
_pHAL_Gpio_Adapter = 0x10000354;
Timer2To7VectorTable = 0x10000358;
pUartLogCtl = 0x10000384;
UartLogBuf = 0x10000388;
UartLogCtl = 0x10000408;
UartLogHistoryBuf = 0x10000430;
ArgvArray = 0x100006ac;
rom_wlan_ram_map = 0x100006d4;
FalseAlmCnt = 0x100006e0;
ROMInfo = 0x10000720;
DM_CfoTrack = 0x10000738;
rom_libgloss_ram_map = 0x10000760;
rtl_errno = 0x10000bc4;
_rtl_impure_ptr = 0x10001c60;
}

13
lib/cpu/rtl8710/rtl8710.h Normal file
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#ifndef _RTL8710_H_
#define _RTL8710_H_
#include "rtl8710_sys.h"
#include "rtl8710_int.h"
#include "rtl8710_peri_on.h"
#include "rtl8710_timer.h"
#include "rtl8710_gpio.h"
//#include "rtl8710_log_uart.h"
//#include "rtl8710_spi.h"
#endif

48
lib/cpu/rtl8710/rtl8710.ld Normal file
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MEMORY{
tcm (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64k
ram (rwx) : ORIGIN = 0x10000000, LENGTH = 448k
}
PROVIDE(STACK_TOP = 0x1FFF0000 + 64k);
SECTIONS{
__rom_bss_start__ = 0x10000300;
__rom_bss_end__ = 0x10000bc8;
.text : {
__text_beg__ = . ;
*(.vectors*) *(.header) *(.text) *(.text*) *(.rodata) *(.rodata*) *(.glue_7) *(.glue_7t) *(.eh_frame) *(.ARM.extab*) . = ALIGN(4); __text_end__ = . ;
} >ram
.data : {
. = ALIGN(4);
__data_beg__ = . ;
*(.ram_vectors) *(.data) *(.data*) *(.ram_func) . = ALIGN(4);
__data_end__ = . ;
} >ram
.bss : {
. = ALIGN(4);
__bss_beg__ = . ;
*(.bss) *(COMMON) . = ALIGN(4); __bss_end__ = . ;
} >ram
__exidx_start = .;
.ARM.exidx : {
___exidx_start = . ;
*(.ARM.exidx*) ;
___exidx_end = . ; } >ram
__exidx_end = .;
.ARM.extab : {
*(.ARM.extab*)
} >ram
. = ALIGN(4);
end = .;
PROVIDE (end = .);
}
INCLUDE "export-rom_v03.txt"

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lib/cpu/rtl8710/rtl8710.ocd Normal file
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#
# OpenOCD script for RTL8710
# Copyright (C) 2016 Rebane, rebane@alkohol.ee
#
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME rtl8710
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x800
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x2ba01477
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x10001000 -work-area-size $_WORKAREASIZE -work-area-backup 0
# adapter_khz 500
adapter_nsrst_delay 100
if {![using_hla]} {
cortex_m reset_config sysresetreq
}
set rtl8710_flasher_firmware_ptr 0x10001000
set rtl8710_flasher_buffer 0x10008000
set rtl8710_flasher_buffer_size 262144
set rtl8710_flasher_sector_size 4096
array set rtl8710_flasher_code {
0 0xB671B57F 1 0x25FF4B58 2 0x6B196B1A 3 0x7040F042 4 0x69D96318 5 0xF4414E55
6 0x69D97480 7 0xF8D361DC 8 0xF8C32120 9 0xF8D35120 10 0xF8C31124 11 0x47B05124
12 0x47B04E4F 13 0x47984B4F 14 0x60104A4F 15 0x484F47B0 16 0x60012100 17 0x2C006804
18 0x4D4DD0FC 19 0xB93E682E 20 0x60264C49 21 0x47B04E46 22 0x47984B46 23 0xE7ED6020
24 0x2B01682B 25 0x4E42D109 26 0x4C4647B0 27 0x47A02006 28 0x47904A45 29 0x47A020C7
30 0x682AE00D 31 0xD10E2A02 32 0x47B04E3B 33 0x20064C3F 34 0x483F47A0 35 0x493F4780
36 0x68084D3F 37 0x47B047A8 38 0x47A02004 39 0x6828E7CE 40 0xD1132803 41 0x47A04C32
42 0x24004838 43 0x4E396805 44 0x68311960 45 0xD206428C 46 0x4B384A37 47 0x221018A1
48 0x34104798 49 0x4D2AE7F3 50 0xE7B847A8 51 0x29046829 52 0x2400D11B 53 0x6806482F
54 0xD2B042B4 55 0x47A84D24 56 0x20064E28 57 0x4B2847B0 58 0x49284798 59 0x680A4B2A
60 0x18A018E1 61 0xF44F4B2A 62 0x47987280 63 0x200447A8 64 0xF50447B0 65 0x47A87480
66 0x682CE7E4 67 0xD1232C05 68 0x47984B17 69 0x4D1F2400 70 0x4294682A 71 0x481BD28F
72 0x68012210 73 0x18604E1D 74 0x47B04669 75 0x1B19682B 76 0xBF282910 77 0x23002110
78 0xD011428B 79 0xF81D4A16 80 0x18A05003 81 0x42B55CC6 82 0x3301D101 83 0x4A15E7F4
84 0x60112101 85 0xE7726054 86 0x25014E12 87 0xE76E6035 88 0x47A84D03 89 0xE7D63410
90 0x40000200 91 0x100011BD 92 0x100013DD 93 0x10001289 94 0x1000800C 95 0x10008000
96 0x10008004 97 0x1000130D 98 0x100013ED 99 0x10008010 100 0x10001335 101 0x10008014
102 0x10008020 103 0x10001221 104 0x10001375 105 0x10008008 106 0x6A5A4B03 107 0xD0FB0512
108 0x0060F893 109 0xBF004770 110 0x40006000 111 0x6B194B17 112 0xF4416B1A 113 0x63187040
114 0x69186919 115 0x0110F041 116 0xF8D36119 117 0x220000C0 118 0x0106F020 119 0x00C0F8D3
120 0x10C0F8C3 121 0x00C0F8D3 122 0x0101F040 123 0x00C0F8D3 124 0x10C0F8C3 125 0x43BCF503
126 0x609A6899 127 0x20016AD9 128 0x691962DA 129 0x69596118 130 0x61592102 131 0x619A6999
132 0x61DA69D9 133 0x64DA6CD9 134 0xBF004770 135 0x40000200 136 0x460EB570 137 0xB34A4614
138 0xF3C04B15 139 0x681A4507 140 0x7240F44F 141 0x685A601A 142 0xF3C02103 143 0x2C102207
144 0x2410BF28 145 0x605CB2C0 146 0x1060F883 147 0x5060F883 148 0xF8832101 149 0xF8832060
150 0x689A0060 151 0x60992500 152 0x47984B08 153 0x35015570 154 0x42A2B2AA 155 0x4804D3F8
156 0xF0116A81 157 0xD1FA0301 158 0x60836881 159 0xBD704620 160 0x40006000 161 0x100011A9
162 0x4C10B5F8 163 0x68232003 164 0x7340F44F 165 0x68636023 166 0x60602101 167 0x68A3229F
168 0x60A14D0B 169 0x2060F884 170 0x460647A8 171 0x460747A8 172 0x040347A8 173 0x2707EA43
174 0x0006EA47 175 0x4B036AA1 176 0x0201F011 177 0x6899D1FA 178 0xBDF8609A 179 0x40006000
180 0x100011A9 181 0x4C0BB510 182 0x68232001 183 0x7340F44F 184 0x68636023 185 0x60602105
186 0x60A068A2 187 0xF8844A06 188 0x47901060 189 0x4B036AA1 190 0x0201F011 191 0x6899D1FA
192 0xBD10609A 193 0x40006000 194 0x100011A9 195 0x21014B08 196 0xF44F681A 197 0x601A7280
198 0x6099689A 199 0x0060F883 200 0x48036A9A 201 0x0101F012 202 0x6883D1FA 203 0x47706081
204 0x40006000 205 0x21014B0E 206 0xF44F681A 207 0x601A7280 208 0x2220689A 209 0xF8836099
210 0xF3C02060 211 0xF3C04107 212 0xB2C02207 213 0x1060F883 214 0x2060F883 215 0x0060F883
216 0x4A036A99 217 0x0001F011 218 0x6893D1FA 219 0x47706090 220 0x40006000 221 0xB36AB530
222 0x25014B17 223 0xF44F681C 224 0x601C7480 225 0x2402689C 226 0xF883609D 227 0xF3C04060
228 0xF3C04507 229 0xB2C02407 230 0x5060F883 231 0x7F80F5B2 232 0xF44FBF28 233 0xF8837280
234 0xF8834060 235 0x20000060 236 0x4C095C0D 237 0xF8843001 238 0xB2855060 239 0xD3F74295
240 0x07496A99 241 0x6AA0D5FC 242 0xF0104B03 243 0xD1FA0101 244 0x60996898 245 0xBD304610
246 0x40006000 247 0x4B02B508 248 0x07C04798 249 0xBD08D4FB 250 0x100012D5 251 0x4B04B508
252 0xF0004798 253 0xB2C10002 254 0xD0F82900 255 0xBF00BD08 256 0x100012D5
}
set rtl8710_flasher_command_read_id 0
set rtl8710_flasher_command_mass_erase 1
set rtl8710_flasher_command_sector_erase 2
set rtl8710_flasher_command_read 3
set rtl8710_flasher_command_write 4
set rtl8710_flasher_command_verify 5
set rtl8710_flasher_ready 0
set rtl8710_flasher_capacity 0
set rtl8710_flasher_auto_erase 0
set rtl8710_flasher_auto_verify 0
set rtl8710_flasher_auto_erase_sector 0xFFFFFFFF
proc rtl8710_flasher_init {} {
global rtl8710_flasher_firmware_ptr
global rtl8710_flasher_buffer
global rtl8710_flasher_capacity
global rtl8710_flasher_ready
global rtl8710_flasher_code
if {[expr {$rtl8710_flasher_ready == 0}]} {
echo "initializing RTL8710 flasher"
halt
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
array2mem rtl8710_flasher_code 32 $rtl8710_flasher_firmware_ptr [array size rtl8710_flasher_code]
reg faultmask 0x01
reg sp 0x20000000
reg pc $rtl8710_flasher_firmware_ptr
resume
rtl8710_flasher_wait
set id [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]]
set rtl8710_flasher_capacity [expr {2 ** [expr {($id >> 16) & 0xFF}]}]
set rtl8710_flasher_ready 1
echo "RTL8710 flasher initialized"
}
return ""
}
proc rtl8710_flasher_mrw {reg} {
set value ""
mem2array value 32 $reg 1
return $value(0)
}
proc rtl8710_flasher_wait {} {
global rtl8710_flasher_buffer
while {[rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x00}]]} { }
}
proc rtl8710_flasher_load_block {local_filename offset len} {
global rtl8710_flasher_buffer
load_image $local_filename [expr {$rtl8710_flasher_buffer + 0x20 - $offset}] bin [expr {$rtl8710_flasher_buffer + 0x20}] $len
}
proc rtl8710_flasher_read_block {offset len} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_read
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_read
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x14}] $len
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]]
if {[expr {$status > 0}]} {
error "read error, offset $offset"
}
}
proc rtl8710_flasher_write_block {offset len} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_write
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_write
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x14}] $len
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]]
if {[expr {$status > 0}]} {
error "write error, offset $offset"
}
}
proc rtl8710_flasher_verify_block {offset len} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_verify
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_verify
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x14}] $len
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]]
if {[expr {$status > 0}]} {
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]]
set status [expr {$status + $offset}]
error "verify error, offset $status"
}
}
proc rtl8710_flash_read_id {} {
global rtl8710_flasher_buffer
global rtl8710_flasher_capacity
global rtl8710_flasher_command_read_id
rtl8710_flasher_init
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_read_id
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set id [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]]
set manufacturer_id [format "0x%02X" [expr {$id & 0xFF}]]
set memory_type [format "0x%02X" [expr {($id >> 8) & 0xFF}]]
set memory_capacity [expr {2 ** [expr {($id >> 16) & 0xFF}]}]
echo "manufacturer ID: $manufacturer_id, memory type: $memory_type, memory capacity: $memory_capacity bytes"
}
proc rtl8710_flash_mass_erase {} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_mass_erase
rtl8710_flasher_init
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_mass_erase
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
}
proc rtl8710_flash_sector_erase {offset} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_sector_erase
rtl8710_flasher_init
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_sector_erase
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
}
proc rtl8710_flash_read {local_filename loc size} {
global rtl8710_flasher_buffer
global rtl8710_flasher_buffer_size
rtl8710_flasher_init
for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} {
set len [expr {$size - $offset}]
if {[expr {$len > $rtl8710_flasher_buffer_size}]} {
set len $rtl8710_flasher_buffer_size
}
set flash_offset [expr {$loc + $offset}]
echo "read offset $flash_offset"
rtl8710_flasher_read_block $flash_offset $len
dump_image /tmp/_rtl8710_flasher.bin [expr {$rtl8710_flasher_buffer + 0x20}] $len
exec dd conv=notrunc if=/tmp/_rtl8710_flasher.bin "of=$local_filename" bs=1 "seek=$offset"
echo "read $len bytes"
}
}
proc rtl8710_flash_write {local_filename loc} {
global rtl8710_flasher_buffer_size
global rtl8710_flasher_sector_size
global rtl8710_flasher_auto_erase
global rtl8710_flasher_auto_verify
global rtl8710_flasher_auto_erase_sector
rtl8710_flasher_init
set sector 0
set size [file size $local_filename]
for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} {
set len [expr {$size - $offset}]
if {[expr {$len > $rtl8710_flasher_buffer_size}]} {
set len $rtl8710_flasher_buffer_size
}
set flash_offset [expr {$loc + $offset}]
echo "write offset $flash_offset"
rtl8710_flasher_load_block $local_filename $offset $len
if {[expr {$rtl8710_flasher_auto_erase != 0}]} {
for {set i $flash_offset} {$i < [expr {$flash_offset + $len}]} {incr i} {
set sector [expr {$i / $rtl8710_flasher_sector_size}]
if {[expr {$rtl8710_flasher_auto_erase_sector != $sector}]} {
echo "erase sector $sector"
rtl8710_flash_sector_erase [expr {$sector * $rtl8710_flasher_sector_size}]
set rtl8710_flasher_auto_erase_sector $sector
}
}
}
rtl8710_flasher_write_block $flash_offset $len
echo "wrote $len bytes"
if {[expr {$rtl8710_flasher_auto_verify != 0}]} {
echo "verify offset $flash_offset"
rtl8710_flasher_verify_block $flash_offset $len
}
}
}
proc rtl8710_flash_verify {local_filename loc} {
global rtl8710_flasher_buffer_size
rtl8710_flasher_init
set size [file size $local_filename]
for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} {
set len [expr {$size - $offset}]
if {[expr {$len > $rtl8710_flasher_buffer_size}]} {
set len $rtl8710_flasher_buffer_size
}
set flash_offset [expr {$loc + $offset}]
echo "read offset $flash_offset"
rtl8710_flasher_load_block $local_filename $offset $len
echo "verify offset $flash_offset"
rtl8710_flasher_verify_block $flash_offset $len
}
}
proc rtl8710_flash_auto_erase {on} {
global rtl8710_flasher_auto_erase
if {[expr {$on != 0}]} {
set rtl8710_flasher_auto_erase 1
echo "auto erase on"
} else {
set rtl8710_flasher_auto_erase 0
echo "auto erase off"
}
}
proc rtl8710_flash_auto_verify {on} {
global rtl8710_flasher_auto_verify
if {[expr {$on != 0}]} {
set rtl8710_flasher_auto_verify 1
echo "auto verify on"
} else {
set rtl8710_flasher_auto_verify 0
echo "auto verify off"
}
}
proc rtl8710_reboot {} {
mww 0xE000ED0C 0x05FA0007
}

37
lib/cpu/rtl8710/rtl8710_gpio.h Normal file
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#ifndef _RTL8710_GPIO_H_
#define _RTL8710_GPIO_H_
#include <stdint.h>
typedef struct{
volatile uint32_t SWPORTA_DR;
volatile uint32_t SWPORTA_DDR;
volatile uint32_t SWPORTA_CTRL;
volatile uint32_t SWPORTB_DR;
volatile uint32_t SWPORTB_DDR;
volatile uint32_t SWPORTB_CTRL;
volatile uint32_t SWPORTC_DR;
volatile uint32_t SWPORTC_DDR;
volatile uint32_t SWPORTC_CTRL;
uint32_t RESERVED1[3];
volatile uint32_t INTEN;
volatile uint32_t INTMASK;
volatile uint32_t INTTYPE_LEVEL;
volatile uint32_t INT_POLARITY;
volatile uint32_t INTSTATUS;
volatile uint32_t RAW_INTSTATUS;
volatile uint32_t DEBOUNCE;
volatile uint32_t PORTA_EOI;
volatile uint32_t EXT_PORTA;
volatile uint32_t EXT_PORTB;
volatile uint32_t EXT_PORTC;
uint32_t RESERVED2[1];
volatile uint32_t LS_SYNC;
}__attribute__((packed)) GPIO_TypeDef;
#define GPIO ((GPIO_TypeDef *)0x40001000)
#define GPIO_PORTA_GC4 (((uint32_t)1) << 8)
#endif

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lib/cpu/rtl8710/rtl8710_int.h Normal file
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#ifndef _RTL8710_INT_H_
#define _RTL8710_INT_H_
#define SYSTEM_ON_INT 0
#define WDG_INT 1
#define TIMER0_INT 2
#define TIMER1_INT 3
#define I2C3_INT 4
#define TIMER2_7_INT 5
#define SPI0_INT 6
#define GPIO_INT 7
#define UART0_INT 8
#define SPI_FLASH_INT 9
#define USB_OTG_INT 10
#define SDIO_HOST_INT 11
#define SDIO_DEVICE_INT 12
#define I2S0_PCM0_INT 13
#define I2S1_PCM1_INT 14
#define WL_DMA_INT 15
#define WL_PROTOCOL_INT 16
#define CRYPTO_INT 17
#define GMAC_INT 18
#define PERIPHERAL_INT 19
#define GDMA0_CHANNEL0_INT 20
#define GDMA0_CHANNEL1_INT 21
#define GDMA0_CHANNEL2_INT 22
#define GDMA0_CHANNEL3_INT 23
#define GDMA0_CHANNEL4_INT 24
#define GDMA0_CHANNEL5_INT 25
#define GDMA1_CHANNEL0_INT 26
#define GDMA1_CHANNEL1_INT 27
#define GDMA1_CHANNEL2_INT 28
#define GDMA1_CHANNEL3_INT 29
#define GDMA1_CHANNEL4_INT 30
#define GDMA1_CHANNEL5_INT 31
#define I2C0_INT 64
#define I2C1_INT 65
#define I2C2_INT 66
#define SPI1_INT 72
#define SPI2_INT 73
#define UART1_INT 80
#define UART2_INT 81
#define LOG_UART_INT 88
#define ADC_INT 89
#define DAC0_INT 91
#define DAC1_INT 92
#define LP_EXTENSION_INT 93
#define PTA_TRX_INT 95
#define RXI300_INT 96
#define NFC_INT 97
#endif

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lib/cpu/rtl8710/rtl8710_log_uart.h Normal file
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#ifndef _RTL8710_LOG_UART_H_
#define _RTL8710_LOG_UART_H_
#include <stdint.h>
typedef struct{
union{
volatile uint32_t RBR;
volatile uint32_t THR;
volatile uint32_t DLL;
volatile uint32_t RBR_THR_DLL;
};
union{
volatile uint32_t IER;
volatile uint32_t DLH;
volatile uint32_t IER_DLH;
};
union{
volatile uint32_t IIR;
volatile uint32_t FCR;
volatile uint32_t IIR_FCR;
};
volatile uint32_t LCR;
volatile uint32_t MCR;
volatile uint32_t LSR;
volatile uint32_t MSR;
uint32_t RESERVED1[24];
volatile uint32_t USR;
}__attribute__((packed)) LOG_UART_TypeDef;
#define LOG_UART ((LOG_UART_TypeDef *)0x40003000)
// LOG_UART_IER
#define LOG_UART_IER_ERBFI (((uint32_t)0x01) << 0)
#define LOG_UART_IER_ETBEI (((uint32_t)0x01) << 1)
#define LOG_UART_IER_ELSI (((uint32_t)0x01) << 2)
#define LOG_UART_IER_EDSSI (((uint32_t)0x01) << 3)
// LOG_UART_FCR
#define LOG_UART_FCR_FIFOE (((uint32_t)0x01) << 0)
#define LOG_UART_FCR_RFIFOR (((uint32_t)0x01) << 1)
#define LOG_UART_FCR_XFIFOR (((uint32_t)0x01) << 2)
#define LOG_UART_FCR_DMAM (((uint32_t)0x01) << 3)
#define LOG_UART_FCR_TET (((uint32_t)0x03) << 4)
#define LOG_UART_FCR_RT (((uint32_t)0x03) << 6)
// LOG_UART_LCR
#define LOG_UART_LCR_DLS (((uint32_t)0x03) << 0)
#define LOG_UART_LCR_STOP (((uint32_t)0x01) << 2)
#define LOG_UART_LCR_PEN (((uint32_t)0x01) << 3)
#define LOG_UART_LCR_EPS (((uint32_t)0x01) << 4)
#define LOG_UART_LCR_STICK_PAR (((uint32_t)0x01) << 5)
#define LOG_UART_LCR_BC (((uint32_t)0x01) << 6)
#define LOG_UART_LCR_DLAB (((uint32_t)0x01) << 7)
// LOG_UART_MCR
#define LOG_UART_MCR_DTR (((uint32_t)0x01) << 0)
#define LOG_UART_MCR_RTS (((uint32_t)0x01) << 1)
#define LOG_UART_MCR_OUT1 (((uint32_t)0x01) << 2)
#define LOG_UART_MCR_OUT2 (((uint32_t)0x01) << 3)
#define LOG_UART_MCR_LOOPBACK (((uint32_t)0x01) << 4)
#define LOG_UART_MCR_AFCE (((uint32_t)0x01) << 5)
// LOG_UART_LSR
#define LOG_UART_LSR_DR (((uint32_t)0x01) << 0)
#define LOG_UART_LSR_OE (((uint32_t)0x01) << 1)
#define LOG_UART_LSR_PE (((uint32_t)0x01) << 2)
#define LOG_UART_LSR_FE (((uint32_t)0x01) << 3)
#define LOG_UART_LSR_BI (((uint32_t)0x01) << 4)
#define LOG_UART_LSR_THRE (((uint32_t)0x01) << 5)
#define LOG_UART_LSR_TEMT (((uint32_t)0x01) << 6)
#define LOG_UART_LSR_RFE (((uint32_t)0x01) << 7)
#define LOG_UART_LSR_ADDR_RCVD (((uint32_t)0x01) << 8)
#endif

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#ifndef _RTL8710_PERI_ON_H_
#define _RTL8710_PERI_ON_H_
#include <stdint.h>
typedef struct{
volatile uint32_t PEON_PWR_CTRL; // 0x0200
volatile uint32_t PON_ISO_CTRL; // 0x0204
uint32_t RESERVED1[2];
volatile uint32_t SOC_FUNC_EN; // 0x0210
volatile uint32_t SOC_HCI_COM_FUNC_EN; // 0x0214
volatile uint32_t SOC_PERI_FUNC0_EN; // 0x0218
volatile uint32_t SOC_PERI_FUNC1_EN; // 0x021C
volatile uint32_t SOC_PERI_DB_FUNC0_EN; // 0x0220
uint32_t RESERVED2[3];
volatile uint32_t PESOC_CLK_CTRL; // 0x0230
volatile uint32_t PESOC_PERI_CLK_CTRL0; // 0x0234
volatile uint32_t PESOC_PERI_CLK_CTRL1; // 0x0238
volatile uint32_t PESOC_CLK_CTRL3; // 0x023C
volatile uint32_t PESOC_HCI_CLK_CTRL0; // 0x0240
volatile uint32_t PESOC_COM_CLK_CTRL1; // 0x0244
volatile uint32_t PESOC_HW_ENG_CLK_CTRL; // 0x0248
uint32_t RESERVED3[1];
volatile uint32_t PESOC_CLK_SEL; // 0x0250
uint32_t RESERVED4[6];
volatile uint32_t SYS_ANACK_CAL_CTRL; // 0x026C
volatile uint32_t OSC32K_CTRL; // 0x0270
volatile uint32_t OSC32K_REG_CTRL0; // 0x0274
volatile uint32_t OSC32K_REG_CTRL1; // 0x0278
volatile uint32_t THERMAL_METER_CTRL; // 0x027C
volatile uint32_t UART_MUX_CTRL; // 0x0280
volatile uint32_t SPI_MUX_CTRL; // 0x0284
volatile uint32_t I2C_MUX_CTRL; // 0x0288
volatile uint32_t I2S_MUX_CTRL; // 0x028C
uint32_t RESERVED5[4];
volatile uint32_t HCI_PINMUX_CTRL; // 0x02A0
volatile uint32_t WL_PINMUX_CTRL; // 0x02A4
volatile uint32_t BT_PINMUX_CTRL; // 0x02A8
volatile uint32_t PWM_PINMUX_CTRL; // 0x02AC
uint32_t RESERVED6[4];
volatile uint32_t CPU_PERIPHERAL_CTRL; // 0x02C0
uint32_t RESERVED7[7];
volatile uint32_t HCI_CTRL_STATUS_0; // 0x02E0
volatile uint32_t HCI_CTRL_STATUS_1; // 0x02E4
uint32_t RESERVED8[6];
volatile uint32_t PESOC_MEM_CTRL; // 0x0300
volatile uint32_t PESOC_SOC_CTRL; // 0x0304
volatile uint32_t PESOC_PERI_CTRL; // 0x0308
uint32_t RESERVED9[5];
volatile uint32_t GPIO_SHTDN_CTRL; // 0x0320
volatile uint32_t GPIO_DRIVING_CTRL; // 0x0324
uint32_t RESERVED10[2];
volatile uint32_t GPIO_PULL_CTRL0; // 0x0330
volatile uint32_t GPIO_PULL_CTRL1; // 0x0334
volatile uint32_t GPIO_PULL_CTRL2; // 0x0338
volatile uint32_t GPIO_PULL_CTRL3; // 0x033C
volatile uint32_t GPIO_PULL_CTRL4; // 0x0340
volatile uint32_t GPIO_PULL_CTRL5; // 0x0344
volatile uint32_t GPIO_PULL_CTRL6; // 0x0348
uint32_t RESERVED11[5];
volatile uint32_t PERI_PWM0_CTRL; // 0x0360
volatile uint32_t PERI_PWM1_CTRL; // 0x0364
volatile uint32_t PERI_PWM2_CTRL; // 0x0368
volatile uint32_t PERI_PWM3_CTRL; // 0x036C
volatile uint32_t PERI_TIM_EVT_CTRL; // 0x0370
volatile uint32_t PERI_EGTIM_CTRL; // 0x0374
uint32_t RESERVED12[30];
volatile uint32_t PEON_CFG; // 0x03F0
volatile uint32_t PEON_STATUS; // 0x03F4
}__attribute__((packed)) PERI_ON_TypeDef;
#define PERI_ON ((PERI_ON_TypeDef *)0x40000200)
// PERI_ON_SOC_FUNC_EN
#define PERI_ON_SOC_FUNC_EN_FUN (((uint32_t)0x01) << 0)
#define PERI_ON_SOC_FUNC_EN_OCP (((uint32_t)0x01) << 1)
#define PERI_ON_SOC_FUNC_EN_LXBUS (((uint32_t)0x01) << 2)
#define PERI_ON_SOC_FUNC_EN_FLASH (((uint32_t)0x01) << 4)
#define PERI_ON_SOC_FUNC_EN_MEM_CTRL (((uint32_t)0x01) << 6)
#define PERI_ON_SOC_FUNC_EN_CPU (((uint32_t)0x01) << 8)
#define PERI_ON_SOC_FUNC_EN_LOG_UART (((uint32_t)0x01) << 12)
#define PERI_ON_SOC_FUNC_EN_GDMA0 (((uint32_t)0x01) << 13)
#define PERI_ON_SOC_FUNC_EN_GDMA1 (((uint32_t)0x01) << 14)
#define PERI_ON_SOC_FUNC_EN_GTIMER (((uint32_t)0x01) << 16)
#define PERI_ON_SOC_FUNC_EN_SECURITY_ENGINE (((uint32_t)0x01) << 20)
// PERI_ON_SOC_PERI_FUNC1_EN
#define PERI_ON_SOC_PERI_FUNC1_EN_ADC0 (((uint32_t)0x01) << 0)
#define PERI_ON_SOC_PERI_FUNC1_EN_DAC0 (((uint32_t)0x01) << 4)
#define PERI_ON_SOC_PERI_FUNC1_EN_DAC1 (((uint32_t)0x01) << 5)
#define PERI_ON_SOC_PERI_FUNC1_EN_GPIO (((uint32_t)0x01) << 8)
// PERI_ON_PESOC_CLK_CTRL
#define PERI_ON_CLK_CTRL_CKE_OCP (((uint32_t)0x01) << 0)
#define PERI_ON_CLK_CTRL_CKE_PLFM (((uint32_t)0x01) << 2)
#define PERI_ON_CLK_CTRL_ACTCK_TRACE_EN (((uint32_t)0x01) << 4)
#define PERI_ON_CLK_CTRL_SLPCK_TRACE_EN (((uint32_t)0x01) << 5)
#define PERI_ON_CLK_CTRL_ACTCK_VENDOR_REG_EN (((uint32_t)0x01) << 6)
#define PERI_ON_CLK_CTRL_SLPCK_VENDOR_REG_EN (((uint32_t)0x01) << 7)
#define PERI_ON_CLK_CTRL_ACTCK_FLASH_EN (((uint32_t)0x01) << 8)
#define PERI_ON_CLK_CTRL_SLPCK_FLASH_EN (((uint32_t)0x01) << 9)
#define PERI_ON_CLK_CTRL_ACTCK_SDR_EN (((uint32_t)0x01) << 10)
#define PERI_ON_CLK_CTRL_SLPCK_SDR_EN (((uint32_t)0x01) << 11)
#define PERI_ON_CLK_CTRL_ACTCK_LOG_UART_EN (((uint32_t)0x01) << 12)
#define PERI_ON_CLK_CTRL_SLPCK_LOG_UART_EN (((uint32_t)0x01) << 13)
#define PERI_ON_CLK_CTRL_ACTCK_TIMER_EN (((uint32_t)0x01) << 14)
#define PERI_ON_CLK_CTRL_SLPCK_TIMER_EN (((uint32_t)0x01) << 15)
#define PERI_ON_CLK_CTRL_ACTCK_GDMA0_EN (((uint32_t)0x01) << 16)
#define PERI_ON_CLK_CTRL_SLPCK_GDMA0_EN (((uint32_t)0x01) << 17)
#define PERI_ON_CLK_CTRL_ACTCK_GDMA1_EN (((uint32_t)0x01) << 18)
#define PERI_ON_CLK_CTRL_SLPCK_GDMA1_EN (((uint32_t)0x01) << 19)
#define PERI_ON_CLK_CTRL_ACTCK_GPIO_EN (((uint32_t)0x01) << 24)
#define PERI_ON_CLK_CTRL_SLPCK_GPIO_EN (((uint32_t)0x01) << 25)
#define PERI_ON_CLK_CTRL_ACTCK_BTCMD_EN (((uint32_t)0x01) << 28)
#define PERI_ON_CLK_CTRL_SLPCK_BTCMD_EN (((uint32_t)0x01) << 29)
// PERI_ON_CPU_PERIPHERAL_CTRL
#define PERI_ON_CPU_PERIPHERAL_CTRL_SPI_FLASH_PIN_EN (((uint32_t)0x01) << 0)
#define PERI_ON_CPU_PERIPHERAL_CTRL_SPI_FLASH_PIN_SEL (((uint32_t)0x03) << 1)
#define PERI_ON_CPU_PERIPHERAL_CTRL_SDR_PIN_EN (((uint32_t)0x01) << 4)
#define PERI_ON_CPU_PERIPHERAL_CTRL_SWD_PIN_EN (((uint32_t)0x01) << 16)
#define PERI_ON_CPU_PERIPHERAL_CTRL_TRACE_PIN_EN (((uint32_t)0x01) << 17)
#define PERI_ON_CPU_PERIPHERAL_CTRL_LOG_UART_PIN_EN (((uint32_t)0x01) << 20)
#define PERI_ON_CPU_PERIPHERAL_CTRL_LOG_UART_IR_EN (((uint32_t)0x01) << 21)
#define PERI_ON_CPU_PERIPHERAL_CTRL_LOG_UART_PIN_SEL (((uint32_t)0x03) << 22)
#endif

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#ifndef _RTL8710_SPI_H_
#define _RTL8710_SPI_H_
#include <stdint.h>
typedef struct{
volatile uint32_t CTRLR0;
volatile uint32_t CTRLR1;
volatile uint32_t SSIENR;
volatile uint32_t MWCR;
volatile uint32_t SER;
volatile uint32_t BAUDR;
volatile uint32_t TXFTLR;
volatile uint32_t RXFTLR;
volatile uint32_t TXFLR;
volatile uint32_t RXFLR;
volatile uint32_t SR;
volatile uint32_t IMR;
volatile uint32_t ISR;
volatile uint32_t RISR;
volatile uint32_t TXOICR;
volatile uint32_t RXOICR;
volatile uint32_t RXUICR;
volatile uint32_t MSTICR;
volatile uint32_t ICR;
volatile uint32_t DMACR;
volatile uint32_t DMATDLR;
volatile uint32_t DMARDLR;
volatile uint32_t IDR;
volatile uint32_t SSI_COMP_VERSION;
union{
struct{
union{
volatile uint8_t DR;
volatile uint8_t DR8;
};
uint8_t RESERVED1[3];
}__attribute__((packed));
struct{
volatile uint16_t DR16;
uint16_t RESERVED2[1];
}__attribute__((packed));
volatile uint32_t DR32;
};
uint32_t RESERVED3[31];
volatile uint32_t READ_FAST_SINGLE;
volatile uint32_t READ_DUAL_DATA;
volatile uint32_t READ_DUAL_ADDR_DATA;
volatile uint32_t READ_QUAD_DATA;
union{
volatile uint32_t READ_QUAD_ADDR_DATA;
volatile uint32_t RX_SAMPLE_DLY;
};
volatile uint32_t WRITE_SIGNLE;
volatile uint32_t WRITE_DUAL_DATA;
volatile uint32_t WRITE_DUAL_ADDR_DATA;
volatile uint32_t WRITE_QUAD_DATA;
volatile uint32_t WRITE_QUAD_ADDR_DATA;
volatile uint32_t WRITE_ENABLE;
volatile uint32_t READ_STATUS;
volatile uint32_t CTRLR2;
volatile uint32_t FBAUDR;
volatile uint32_t ADDR_LENGTH;
volatile uint32_t AUTO_LENGTH;
volatile uint32_t VALID_CMD;
volatile uint32_t FLASE_SIZE;
volatile uint32_t FLUSH_FIFO;
}__attribute__((packed)) SPI_TypeDef;
#define SPI_FLASH ((SPI_TypeDef *)0x40006000)
// SPI_CTRLR0
#define SPI_CTRLR0_FRF (((uint32_t)0x03) << 4)
#define SPI_CTRLR0_SCPH (((uint32_t)0x01) << 6)
#define SPI_CTRLR0_SCPOL (((uint32_t)0x01) << 7)
#define SPI_CTRLR0_TMOD (((uint32_t)0x03) << 8)
#define SPI_CTRLR0_SLV_OE (((uint32_t)0x01) << 10)
#define SPI_CTRLR0_SRL (((uint32_t)0x01) << 11)
#define SPI_CTRLR0_CFS (((uint32_t)0x0F) << 12)
#define SPI_CTRLR0_ADDR_CH (((uint32_t)0x03) << 16)
#define SPI_CTRLR0_DATA_CH (((uint32_t)0x03) << 18)
#define SPI_CTRLR0_CMD_CH (((uint32_t)0x03) << 20)
#define SPI_CTRLR0_FAST_RD (((uint32_t)0x01) << 22)
#define SPI_CTRLR0_SHIFT_CK_MTIMES (((uint32_t)0x1F) << 23)
// SPI_SER
#define SPI_SER_SS0 (((uint32_t)0x01) << 0)
#define SPI_SER_SS1 (((uint32_t)0x01) << 1)
#define SPI_SER_SS2 (((uint32_t)0x01) << 2)
// SPI_SR
#define SPI_SR_SSI (((uint32_t)0x01) << 0)
#define SPI_SR_TFNF (((uint32_t)0x01) << 1)
#define SPI_SR_TFE (((uint32_t)0x01) << 2)
#define SPI_SR_RFNE (((uint32_t)0x01) << 3)
#define SPI_SR_RFF (((uint32_t)0x01) << 4)
#define SPI_SR_TXE (((uint32_t)0x01) << 5)
#endif

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#ifndef _RTL8710_SYS_H_
#define _RTL8710_SYS_H_
#include <stdint.h>
// ~/programming/rtl8710/doc/registers/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h
typedef struct{
volatile uint16_t PWR_CTRL; // 0x0000
volatile uint16_t ISO_CTRL; // 0x0002
uint32_t RESERVED1[1];
volatile uint32_t FUNC_EN; // 0x0008
uint32_t RESERVED2[1];
volatile uint32_t CLK_CTRL0; // 0x0010
volatile uint32_t CLK_CTRL1; // 0x0014
uint32_t RESERVED3[2];
volatile uint32_t EFUSE_SYSCFG0; // 0x0020
volatile uint32_t EFUSE_SYSCFG1; // 0x0024
volatile uint32_t EFUSE_SYSCFG2; // 0x0028
volatile uint32_t EFUSE_SYSCFG3; // 0x002C
volatile uint32_t EFUSE_SYSCFG4; // 0x0030
volatile uint32_t EFUSE_SYSCFG5; // 0x0034
volatile uint32_t EFUSE_SYSCFG6; // 0x0038
volatile uint32_t EFUSE_SYSCFG7; // 0x003C
volatile uint32_t REGU_CTRL0; // 0x0040
uint32_t RESERVED4[1];
volatile uint32_t SWR_CTRL0; // 0x0048
volatile uint32_t SWR_CTRL1; // 0x004C
uint32_t RESERVED5[4];
volatile uint32_t XTAL_CTRL0; // 0x0060
volatile uint32_t XTAL_CTRL1; // 0x0064
uint32_t RESERVED6[2];
volatile uint32_t SYSPLL_CTRL0; // 0x0070
volatile uint32_t SYSPLL_CTRL1; // 0x0074
volatile uint32_t SYSPLL_CTRL2; // 0x0078
uint32_t RESERVED7[5];
volatile uint32_t ANA_TIM_CTRL; // 0x0090
volatile uint32_t DSLP_TIM_CTRL; // 0x0094
volatile uint32_t DSLP_TIM_CAL_CTRL; // 0x0098
uint32_t RESERVED8[1];
volatile uint32_t DEBUG_CTRL; // 0x00A0
volatile uint32_t PINMUX_CTRL; // 0x00A4
volatile uint32_t GPIO_DSTBY_WAKE_CTRL0; // 0x00A8
volatile uint32_t GPIO_DSTBY_WAKE_CTRL1; // 0x00AC
uint32_t RESERVED9[3];
volatile uint32_t DEBUG_REG; // 0x00BC
uint32_t RESERVED10[8];
volatile uint32_t EEPROM_CTRL0; // 0x00E0
volatile uint32_t EEPROM_CTRL1; // 0x00E4
volatile uint32_t EFUSE_CTRL; // 0x00E8
volatile uint32_t EFUSE_TEST; // 0x00EC
volatile uint32_t DSTBY_INFO0; // 0x00F0
volatile uint32_t DSTBY_INFO1; // 0x00F4
volatile uint32_t DSTBY_INFO2; // 0x00F8
volatile uint32_t DSTBY_INFO3; // 0x00FC
volatile uint32_t SLP_WAKE_EVENT_MSK0; // 0x0100
volatile uint32_t SLP_WAKE_EVENT_MSK1; // 0x0104
volatile uint32_t SLP_WAKE_EVENT_STATUS0; // 0x0108
volatile uint32_t SLP_WAKE_EVENT_STATUS1; // 0x010C
volatile uint32_t SNF_WAKE_EVENT_MSK0; // 0x0110
volatile uint32_t SNF_WAKE_EVENT_STATUS; // 0x0114
volatile uint32_t PWRMGT_CTRL; // 0x0118
uint32_t RESERVED11[1];
volatile uint32_t PWRMGT_OPTION; // 0x0120
volatile uint32_t PWRMGT_OPTION_EXT; // 0x0124
uint32_t RESERVED12[2];
volatile uint32_t DSLP_WEVENT; // 0x0130
volatile uint32_t PERI_MONITOR; // 0x0134
uint32_t RESERVED13[46];
volatile uint32_t SYSTEM_CFG0; // 0x01F0
volatile uint32_t SYSTEM_CFG1; // 0x01F4
volatile uint32_t SYSTEM_CFG2; // 0x01F8
}__attribute__((packed)) SYS_TypeDef;
#define SYS ((SYS_TypeDef *)0x40000000)
// SYS_PWR_CTRL
#define SYS_PWR_CTRL_PEON_EN (((uint16_t)0x01) << 0)
#define SYS_PWR_CTRL_RET_MEM_EN (((uint16_t)0x01) << 1)
#define SYS_PWR_CTRL_SOC_EN (((uint16_t)0x01) << 2)
// SYS_ISO_CTRL
#define SYS_ISO_CTRL_PEON (((uint16_t)0x01) << 0)
#define SYS_ISO_CTRL_RET_MEM (((uint16_t)0x01) << 1)
#define SYS_ISO_CTRL_SOC (((uint16_t)0x01) << 2)
#define SYS_ISO_CTRL_SYSPLL (((uint16_t)0x01) << 7)
// SYS_FUNC_EN
#define SYS_FUNC_EN_FEN_EELDR (((uint32_t)0x01) << 0)
#define SYS_FUNC_EN_SOC_SYSPEON_EN (((uint32_t)0x01) << 4)
#define SYS_FUNC_EN_FEN_SIC (((uint32_t)0x01) << 24)
#define SYS_FUNC_EN_FEN_SIC_MST (((uint32_t)0x01) << 25)
#define SYS_FUNC_EN_PWRON_TRAP_SHTDN_N (((uint32_t)0x01) << 30)
#define SYS_FUNC_EN_AMACRO_EN (((uint32_t)0x01) << 31)
// SYS_CLK_CTRL0
#define SYS_CLK_CTRL0_CK_SYSREG_EN (((uint32_t)0x01) << 0)
#define SYS_CLK_CTRL0_CK_EELDR_EN (((uint32_t)0x01) << 1)
#define SYS_CLK_CTRL0_SOC_OCP_IOBUS_CK_EN (((uint32_t)0x01) << 2)
// SYS_CLK_CTRL1
#define SYS_CLK_CTRL1_PESOC_EELDR_CK_SEL (((uint32_t)0x01) << 0)
#define SYS_CLK_CTRL1_PESOC_OCP_CPU_CK_SEL (((uint32_t)0x07) << 4)
#endif

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#ifndef _RTL8710_TIMER_H_
#define _RTL8710_TIMER_H_
#include <stdint.h>
typedef struct{
volatile uint32_t TIM0_LOAD_COUNT;
volatile uint32_t TIM0_CURRENT_VALUE;
volatile uint32_t TIM0_CONTROL;
volatile uint32_t TIM0_EOI;
volatile uint32_t TIM0_IS;
volatile uint32_t TIM1_LOAD_COUNT;
volatile uint32_t TIM1_CURRENT_VALUE;
volatile uint32_t TIM1_CONTROL;
volatile uint32_t TIM1_EOI;
volatile uint32_t TIM1_IS;
uint32_t RESERVED1[30];
volatile uint32_t TIMS_IS;
volatile uint32_t TIMS_EOI;
volatile uint32_t TIMS_RAW_IS;
volatile uint32_t TIMS_COMP_VERSION;
volatile uint32_t TIM0_LOAD_COUNT2;
volatile uint32_t TIM1_LOAD_COUNT2;
}__attribute__((packed)) TIMER_TypeDef;
#define TIMER ((TIMER_TypeDef *)0x40002000)
// TIMER_CONTROL
#define TIMER_CONTROL_ENABLE (((uint32_t)0x01) << 0)
#define TIMER_CONTROL_MODE (((uint32_t)0x01) << 1)
#define TIMER_CONTROL_IM (((uint32_t)0x01) << 2)
#define TIMER_CONTROL_PWM (((uint32_t)0x01) << 3)
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_ADC_H_
#define _HAL_ADC_H_
#include "rtl8195a.h"
#include "rtl8195a_adc.h"
#include "hal_gdma.h"
//================ ADC Configuration =========================
#define ADC_INTR_OP_TYPE 1
#define ADC_DMA_OP_TYPE 1
// ADC SAL management macros
#define SAL_ADC_USER_CB_NUM (sizeof(SAL_ADC_USER_CB) / sizeof(PSAL_ADC_USERCB_ADPT))
// ADC used module.
// Please set the ADC module flag to 1 to enable the related
#define ADC0_USED 1
#define ADC1_USED 1
#define ADC2_USED 1
#define ADC3_USED 1
//================ Debug MSG Definition =======================
#define ADC_PREFIX "RTL8195A[adc]: "
#define ADC_PREFIX_LVL " [ADC_DBG]: "
typedef enum _ADC_DBG_LVL_ {
HAL_ADC_LVL = 0x01,
SAL_ADC_LVL = 0x02,
VERI_ADC_LVL = 0x04,
}ADC_DBG_LVL,*PADC_DBG_LVL;
#ifdef CONFIG_DEBUG_LOG
#ifdef CONFIG_DEBUG_LOG_ADC_HAL
#define DBG_8195A_ADC(...) do{ \
_DbgDump("\r"ADC_PREFIX __VA_ARGS__);\
}while(0)
#define ADCDBGLVL 0xFF
#define DBG_8195A_ADC_LVL(LVL,...) do{\
if (LVL&ADCDBGLVL){\
_DbgDump("\r"ADC_PREFIX_LVL __VA_ARGS__);\
}\
}while(0)
#else
#define DBG_ADC_LOG_PERD 100
#define DBG_8195A_ADC(...)
#define DBG_8195A_ADC_LVL(...)
#endif
#endif
//================ ADC HAL Related Enumeration ==================
// ADC Module Selection
typedef enum _ADC_MODULE_SEL_ {
ADC0_SEL = 0x0,
ADC1_SEL = 0x1,
ADC2_SEL = 0x2,
ADC3_SEL = 0x3,
}ADC_MODULE_SEL,*PADC_MODULE_SEL;
// ADC module status
typedef enum _ADC_MODULE_STATUS_ {
ADC_DISABLE = 0x0,
ADC_ENABLE = 0x1,
}ADC_MODULE_STATUS, *PADC_MODULE_STATUS;
// ADC Data Endian
typedef enum _ADC_DATA_ENDIAN_ {
ADC_DATA_ENDIAN_LITTLE = 0x0,
ADC_DATA_ENDIAN_BIG = 0x1,
}ADC_DATA_ENDIAN,*PADC_DATA_ENDIAN;
// ADC Debug Select
typedef enum _ADC_DEBUG_SEL_ {
ADC_DBG_SEL_DISABLE = 0x0,
ADC_DBG_SEL_ENABLE = 0x1,
}ADC_DEBUG_SEL,*PADC_DEBUG_SEL;
typedef enum _ADC_COMPARE_SET_ {
ADC_COMP_SMALLER_THAN = 0x0,
ADC_COMP_GREATER_THAN = 0x1,
}ADC_COMPARE_SET, *PADC_COMPARE_SET;
// ADC feature status
typedef enum _ADC_FEATURE_STATUS_{
ADC_FEATURE_DISABLED = 0,
ADC_FEATURE_ENABLED = 1,
}ADC_FEATURE_STATUS,*PADC_FEATURE_STATUS;
// ADC operation type
typedef enum _ADC_OP_TYPE_ {
ADC_RDREG_TYPE = 0x0,
ADC_DMA_TYPE = 0x1,
ADC_INTR_TYPE = 0x2,
}ADC_OP_TYPE, *PADC_OP_TYPE;
// ADC device status
typedef enum _ADC_DEVICE_STATUS_ {
ADC_STS_UNINITIAL = 0x00,
ADC_STS_INITIALIZED = 0x01,
ADC_STS_IDLE = 0x02,
ADC_STS_TX_READY = 0x03,
ADC_STS_TX_ING = 0x04,
ADC_STS_RX_READY = 0x05,
ADC_STS_RX_ING = 0x06,
ADC_STS_ERROR = 0x07,
ADC_STS_FULL = 0x08,
}ADC_DEVICE_STATUS, *PADC_DEVICE_STATUS;
// ADC error type
typedef enum _ADC_ERR_TYPE_ {
ADC_ERR_FIFO_RD_ERROR = 0x40, //ADC FIFO read error
}ADC_ERR_TYPE, *PADC_ERR_TYPE;
// ADC initial status
typedef enum _ADC_INITAIL_STATUS_ {
ADC0_INITED = 0x1,
ADC1_INITED = 0x2,
ADC2_INITED = 0x4,
ADC3_INITED = 0x8,
}ADC_INITAIL_STATUS, *PADC_INITAIL_STATUS;
//================ ADC HAL Data Structure ======================
// ADC HAL initial data structure
typedef struct _HAL_ADC_INIT_DAT_ {
u8 ADCIdx; //ADC index used
u8 ADCEn; //ADC module enable
u8 ADCEndian; //ADC endian selection,
//but actually it's for 32-bit ADC data swap control
//1'b0: no swap,
//1'b1: swap the upper 16-bit and the lower 16-bit
u8 ADCBurstSz; //ADC DMA operation threshold
u8 ADCCompOnly; //ADC compare mode only enable (without FIFO enable)
u8 ADCOneShotEn; //ADC one-shot mode enable
u8 ADCOverWREn; //ADC overwrite mode enable
u8 ADCOneShotTD; //ADC one shot mode threshold
u16 ADCCompCtrl; //ADC compare mode control,
//1'b0:less than the compare threshold
//1'b1:greater than the compare threshod
u16 ADCCompTD; //ADC compare mode threshold
u8 ADCDataRate; //ADC down sample data rate,
u8 ADCAudioEn; //ADC audio mode enable
u8 ADCEnManul; //ADC enable manually
u8 ADCDbgSel;
u32 RSVD0;
u32 *ADCData; //ADC data pointer
u32 ADCPWCtrl; //ADC0 power control
u32 ADCIntrMSK; //ADC Interrupt Mask
u32 ADCAnaParAd3; //ADC analog parameter 3
u32 ADCInInput; //ADC Input is internal?
}HAL_ADC_INIT_DAT,*PHAL_ADC_INIT_DAT;
// ADC HAL Operations
typedef struct _HAL_ADC_OP_ {
RTK_STATUS (*HalADCInit) (VOID *Data); //HAL ADC initialization
RTK_STATUS (*HalADCDeInit) (VOID *Data); //HAL ADC de-initialization
RTK_STATUS (*HalADCEnable) (VOID *Data); //HAL ADC de-initialization
u32 (*HalADCReceive) (VOID *Data); //HAL ADC receive
RTK_STATUS (*HalADCIntrCtrl) (VOID *Data); //HAL ADC interrupt control
u32 (*HalADCReadReg) (VOID *Data, u8 ADCReg);//HAL ADC read register
}HAL_ADC_OP, *PHAL_ADC_OP;
// ADC user callback adapter
typedef struct _SAL_ADC_USERCB_ADPT_ {
VOID (*USERCB) (VOID *Data);
u32 USERData;
}SAL_ADC_USERCB_ADPT, *PSAL_ADC_USERCB_ADPT;
// ADC user callback structure
typedef struct _SAL_ADC_USER_CB_ {
PSAL_ADC_USERCB_ADPT pTXCB; //ADC Transmit Callback
PSAL_ADC_USERCB_ADPT pTXCCB; //ADC Transmit Complete Callback
PSAL_ADC_USERCB_ADPT pRXCB; //ADC Receive Callback
PSAL_ADC_USERCB_ADPT pRXCCB; //ADC Receive Complete Callback
PSAL_ADC_USERCB_ADPT pRDREQCB; //ADC Read Request Callback
PSAL_ADC_USERCB_ADPT pERRCB; //ADC Error Callback
PSAL_ADC_USERCB_ADPT pDMATXCB; //ADC DMA Transmit Callback
PSAL_ADC_USERCB_ADPT pDMATXCCB; //ADC DMA Transmit Complete Callback
PSAL_ADC_USERCB_ADPT pDMARXCB; //ADC DMA Receive Callback
PSAL_ADC_USERCB_ADPT pDMARXCCB; //ADC DMA Receive Complete Callback
}SAL_ADC_USER_CB, *PSAL_ADC_USER_CB;
// ADC Transmit Buffer
typedef struct _SAL_ADC_TRANSFER_BUF_ {
u32 DataLen; //ADC Transmfer Length
u32 *pDataBuf; //ADC Transfer Buffer Pointer
u32 RSVD; //
}SAL_ADC_TRANSFER_BUF,*PSAL_ADC_TRANSFER_BUF;
typedef struct _SAL_ADC_DMA_USER_DEF_ {
u8 TxDatSrcWdth;
u8 TxDatDstWdth;
u8 TxDatSrcBstSz;
u8 TxDatDstBstSz;
u8 TxChNo;
u8 LlpCtrl;
u16 RSVD0;
u32 MaxMultiBlk;
u32 pLlix;
u32 pBlockSizeList;
}SAL_ADC_DMA_USER_DEF, *PSAL_ADC_DMA_USER_DEF;
// Software API Level ADC Handler
typedef struct _SAL_ADC_HND_ {
u8 DevNum; //ADC device number
u8 PinMux; //ADC pin mux seletion
u8 OpType; //ADC operation type selection
volatile u8 DevSts; //ADC device status
u32 ADCExd; //ADC extended options:
//bit 0: example
//bit 31~bit 1: Reserved
u32 ErrType; //
u32 TimeOut; //ADC IO Timeout count
PHAL_ADC_INIT_DAT pInitDat; //Pointer to ADC initial data struct
PSAL_ADC_TRANSFER_BUF pRXBuf; //Pointer to ADC TX buffer
PSAL_ADC_USER_CB pUserCB; //Pointer to ADC User Callback
}SAL_ADC_HND, *PSAL_ADC_HND;
// ADC SAL handle private
typedef struct _SAL_ADC_HND_PRIV_ {
VOID **ppSalADCHnd; //Pointer to SAL_ADC_HND pointer
SAL_ADC_HND SalADCHndPriv; //Private SAL_ADC_HND
}SAL_ADC_HND_PRIV, *PSAL_ADC_HND_PRIV;
//ADC SAL management adapter
typedef struct _SAL_ADC_MNGT_ADPT_ {
PSAL_ADC_HND_PRIV pSalHndPriv; //Pointer to SAL_ADC_HND
PHAL_ADC_INIT_DAT pHalInitDat; //Pointer to HAL ADC initial data( HAL_ADC_INIT_DAT )
PHAL_ADC_OP pHalOp; //Pointer to HAL ADC operation( HAL_ADC_OP )
VOID (*pHalOpInit)(VOID*);//Pointer to HAL ADC initialize function
PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
VOID (*pSalIrqFunc)(VOID*); //Used for SAL ADC interrupt function
PSAL_ADC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA config
PHAL_GDMA_ADAPTER pHalGdmaAdp;
PHAL_GDMA_OP pHalGdmaOp;
PIRQ_HANDLE pIrqGdmaHnd;
VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL DAC initialize function
PSAL_ADC_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_ADC_USER_CB )
VOID (*pSalDMAIrqFunc)(VOID*); //Used for SAL DAC interrupt function
}SAL_ADC_MNGT_ADPT, *PSAL_ADC_MNGT_ADPT;
//================ ADC HAL Function Prototype ===================
// ADC HAL inline function
// For checking I2C input index valid or not
static inline RTK_STATUS
RtkADCIdxChk(
IN u8 ADCIdx
)
{
#if !ADC0_USED
if (ADCIdx == ADC0_SEL)
return _EXIT_FAILURE;
#endif
#if !ADC1_USED
if (ADCIdx == ADC1_SEL)
return _EXIT_FAILURE;
#endif
#if !ADC2_USED
if (ADCIdx == ADC2_SEL)
return _EXIT_FAILURE;
#endif
#if !ADC3_USED
if (ADCIdx == ADC3_SEL)
return _EXIT_FAILURE;
#endif
return _EXIT_SUCCESS;
}
VOID HalADCOpInit(IN VOID *Data);
PSAL_ADC_HND RtkADCGetSalHnd(IN u8 DACIdx);
RTK_STATUS RtkADCFreeSalHnd(IN PSAL_ADC_HND pSalADCHND);
RTK_STATUS RtkADCLoadDefault(IN VOID *Data);
RTK_STATUS RtkADCInit(IN VOID *Data);
RTK_STATUS RtkADCDeInit(IN VOID *Data);
//RTK_STATUS RtkADCReceive(IN VOID *Data);
u32 RtkADCReceive(IN VOID *Data);
u32 RtkADCReceiveBuf(IN VOID *Data,IN u32 *pBuf);
PSAL_ADC_MNGT_ADPT RtkADCGetMngtAdpt(IN u8 ADCIdx);
RTK_STATUS RtkADCFreeMngtAdpt(IN PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt);
VOID ADCISRHandle(IN VOID *Data);
VOID ADCGDMAISRHandle(IN VOID *Data);
HAL_Status RtkADCDisablePS(IN VOID *Data);
HAL_Status RtkADCEnablePS(IN VOID *Data);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_API_H_
#define _HAL_API_H_
#include "basic_types.h"
#include "hal_irqn.h"
#define HAL_READ32(base, addr) \
rtk_le32_to_cpu(*((volatile u32*)(base + addr)))
#define HAL_WRITE32(base, addr, value32) \
((*((volatile u32*)(base + addr))) = rtk_cpu_to_le32(value32))
#define HAL_READ16(base, addr) \
rtk_le16_to_cpu(*((volatile u16*)(base + addr)))
#define HAL_WRITE16(base, addr, value) \
((*((volatile u16*)(base + addr))) = rtk_cpu_to_le16(value))
#define HAL_READ8(base, addr) \
(*((volatile u8*)(base + addr)))
#define HAL_WRITE8(base, addr, value) \
((*((volatile u8*)(base + addr))) = value)
#if 0
// These "extern _LONG_CALL_" function declaration are for RAM code building only
// For ROM code building, thses code should be marked off
extern _LONG_CALL_ u8
HalPinCtrlRtl8195A(
IN u32 Function,
IN u32 PinLocation,
IN BOOL Operation
);
extern _LONG_CALL_ VOID
HalSerialPutcRtl8195a(
IN u8 c
);
extern _LONG_CALL_ u8
HalSerialGetcRtl8195a(
IN BOOL PullMode
);
extern _LONG_CALL_ u32
HalSerialGetIsrEnRegRtl8195a(VOID);
extern _LONG_CALL_ VOID
HalSerialSetIrqEnRegRtl8195a (
IN u32 SetValue
);
extern _LONG_CALL_ VOID
VectorTableInitForOSRtl8195A(
IN VOID *PortSVC,
IN VOID *PortPendSVH,
IN VOID *PortSysTick
);
extern _LONG_CALL_ BOOL
VectorIrqRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ BOOL
VectorIrqUnRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ VOID
VectorIrqEnRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ VOID
VectorIrqDisRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
#endif
extern BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);
extern VOID InitWDGIRQ(VOID);
#define PinCtrl HalPinCtrlRtl8195A
#define DiagPutChar HalSerialPutcRtl8195a
#define DiagGetChar HalSerialGetcRtl8195a
#define DiagGetIsrEnReg HalSerialGetIsrEnRegRtl8195a
#define DiagSetIsrEnReg HalSerialSetIrqEnRegRtl8195a
#define InterruptForOSInit VectorTableInitForOSRtl8195A
#define InterruptRegister VectorIrqRegisterRtl8195A
#define InterruptUnRegister VectorIrqUnRegisterRtl8195A
#define InterruptEn VectorIrqEnRtl8195A
#define InterruptDis VectorIrqDisRtl8195A
#define SpicFlashInit SpicFlashInitRtl8195A
#define Calibration32k En32KCalibration
#define WDGInit InitWDGIRQ
typedef enum _HAL_Status
{
HAL_OK = 0x00,
HAL_BUSY = 0x01,
HAL_TIMEOUT = 0x02,
HAL_ERR_PARA = 0x03, // error with invaild parameters
HAL_ERR_MEM = 0x04, // error with memory allocation failed
HAL_ERR_HW = 0x05, // error with hardware error
HAL_ERR_UNKNOWN = 0xee // unknown error
} HAL_Status;
#endif //_HAL_API_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_COMMON_H_
#define _HAL_COMMON_H_
//================= Function Prototype START ===================
HAL_Status HalCommonInit(void);
//================= Function Prototype END ===================
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef __HAL_CRYPTO_H__
#define __HAL_CRYPTO_H__
#include "hal_api.h"
#include "basic_types.h"
#define CRYPTO_MAX_MSG_LENGTH 16000
#define CRYPTO_MD5_DIGEST_LENGTH 16
#define CRYPTO_SHA1_DIGEST_LENGTH 20
#define CRYPTO_SHA2_DIGEST_LENGTH 32
typedef enum _SHA2_TYPE_ {
SHA2_NONE = 0,
SHA2_224 = 224/8,
SHA2_256 = 256/8,
SHA2_384 = 384/8,
SHA2_512 = 512/8
} SHA2_TYPE;
#define _ERRNO_CRYPTO_DESC_NUM_SET_OutRange -2
#define _ERRNO_CRYPTO_BURST_NUM_SET_OutRange -3
#define _ERRNO_CRYPTO_NULL_POINTER -4
#define _ERRNO_CRYPTO_ENGINE_NOT_INIT -5
#define _ERRNO_CRYPTO_ADDR_NOT_4Byte_Aligned -6
#define _ERRNO_CRYPTO_KEY_OutRange -7
#define _ERRNO_CRYPTO_MSG_OutRange -8
#define _ERRNO_CRYPTO_IV_OutRange -9
#define _ERRNO_CRYPTO_AUTH_TYPE_NOT_MATCH -10
#define _ERRNO_CRYPTO_CIPHER_TYPE_NOT_MATCH -11
#define _ERRNO_CRYPTO_KEY_IV_LEN_DIFF -12
//
// External API Functions
//
// Crypto Engine
extern int rtl_cryptoEngine_init(void);
extern void rtl_cryptoEngine_info(void);
//
// Authentication
//
// md5
extern int rtl_crypto_md5(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
extern int rtl_crypto_md5_init(void);
extern int rtl_crypto_md5_process(IN const u8* message, const IN u32 msglen, OUT u8* pDigest);
// sha1
extern int rtl_crypto_sha1(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
extern int rtl_crypto_sha1_init(void);
extern int rtl_crypto_sha1_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
// sha2
extern int rtl_crypto_sha2(IN const SHA2_TYPE sha2type,
IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
extern int rtl_crypto_sha2_init(IN const SHA2_TYPE sha2type);
extern int rtl_crypto_sha2_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
// HMAC-md5
extern int rtl_crypto_hmac_md5(IN const u8* message, IN const u32 msglen,
IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
extern int rtl_crypto_hmac_md5_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_hmac_md5_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
// HMAC-sha1
extern int rtl_crypto_hmac_sha1(IN const u8* message, IN const u32 msglen,
IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
extern int rtl_crypto_hmac_sha1_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_hmac_sha1_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
// HMAC-sha2
extern int rtl_crypto_hmac_sha2(IN const SHA2_TYPE sha2type, IN const u8* message, IN const u32 msglen,
IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
extern int rtl_crypto_hmac_sha2_init(IN const SHA2_TYPE sha2type, IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_hmac_sha2_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
//
// Cipher Functions
//
// AES - CBC
extern int rtl_crypto_aes_cbc_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_aes_cbc_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_aes_cbc_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// AES - ECB
extern int rtl_crypto_aes_ecb_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_aes_ecb_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_aes_ecb_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// AES - CTR
extern int rtl_crypto_aes_ctr_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_aes_ctr_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_aes_ctr_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// 3DES - CBC
extern int rtl_crypto_3des_cbc_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_3des_cbc_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_3des_cbc_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// 3DES - ECB
extern int rtl_crypto_3des_ecb_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_3des_ecb_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_3des_ecb_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// DES - CBC
extern int rtl_crypto_des_cbc_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_des_cbc_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_des_cbc_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// DES - ECB
extern int rtl_crypto_des_ecb_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_des_ecb_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_des_ecb_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
//
// C functions in ROM
//
extern int rtl_memcmpb(const u8 *dst, const u8 *src, int bytes);
extern int rtl_memcpyb(u8 *dst, const u8 *src, int bytes);
#endif /* __HAL_CRYPTO_H__ */

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//======================================================
// Routines to access hardware
//
// Copyright (c) 2013 Realtek Semiconductor Corp.
//
// This module is a confidential and proprietary property of RealTek and
// possession or use of this module requires written permission of RealTek.
//======================================================
#ifndef _HAL_DAC_H_
#define _HAL_DAC_H_
#include "rtl8195a.h"
#include "rtl8195a_dac.h"
#include "hal_api.h"
#include "hal_gdma.h"
//================ DAC Configuration =========================
#define DAC_INTR_OP_TYPE 1
#define DAC_DMA_OP_TYPE 1
// DAC SAL management macros
#define SAL_DAC_USER_CB_NUM (sizeof(SAL_DAC_USER_CB) / sizeof(PSAL_DAC_USERCB_ADPT))
// DAC SAL used module.
// Please set the DAC module flag to 1 to enable the related DAC module functions.
#define DAC0_USED 1
#define DAC1_USED 1
//================ Debug MSG Definition =======================
#define DAC_PREFIX "RTL8195A[dac]: "
#define DAC_PREFIX_LVL " [DAC_DBG]: "
typedef enum _DAC_DBG_LVL_ {
HAL_DAC_LVL = 0x00,
SAL_DAC_LVL = 0x02,
VERI_DAC_LVL = 0x04,
}DAC_DBG_LVL,*PDAC_DBG_LVL;
#ifdef CONFIG_DEBUG_LOG
#ifdef CONFIG_DEBUG_LOG_DAC_HAL
#define DBG_8195A_DAC(...) do{ \
_DbgDump("\r"DAC_PREFIX __VA_ARGS__);\
}while(0)
#define DACDBGLVL 0xFF
#define DBG_8195A_DAC_LVL(LVL,...) do{\
if (LVL&DACDBGLVL){\
_DbgDump("\r"DAC_PREFIX_LVL __VA_ARGS__);\
}\
}while(0)
#else
#define DBG_DAC_LOG_PERD 100
#define DBG_8195A_DAC(...)
#define DBG_8195A_DAC_LVL(...)
#endif
#endif
//================ DAC HAL Related Enumeration ==================
// DAC Module Selection
typedef enum _DAC_MODULE_SEL_ {
DAC0_SEL = 0x0,
DAC1_SEL = 0x1,
}DAC_MODULE_SEL,*PDAC_MODULE_SEL;
// DAC module status
typedef enum _DAC_MODULE_STATUS_ {
DAC_DISABLE = 0x0,
DAC_ENABLE = 0x1,
}DAC_MODULE_STATUS, *PDAC_MODULE_STATUS;
// DAC Data Rate
typedef enum _DAC_DATA_RATE_ {
DAC_DATA_RATE_10K = 0x0,
DAC_DATA_RATE_250K = 0x1,
}DAC_DATA_RATE,*PDAC_DATA_RATE;
// DAC Data Endian
typedef enum _DAC_DATA_ENDIAN_ {
DAC_DATA_ENDIAN_LITTLE = 0x0,
DAC_DATA_ENDIAN_BIG = 0x1,
}DAC_DATA_ENDIAN,*PDAC_DATA_ENDIAN;
// DAC Debug Select
typedef enum _DAC_DEBUG_SEL_ {
DAC_DBG_SEL_DISABLE = 0x0,
DAC_DBG_SEL_ENABLE = 0x1,
}DAC_DEBUG_SEL,*PDAC_DEBUG_SEL;
// DAC Dsc Debug Select
typedef enum _DAC_DSC_DEBUG_SEL_ {
DAC_DSC_DBG_SEL_DISABLE = 0x0,
DAC_DSC_DBG_SEL_ENABLE = 0x1,
}DAC_DSC_DEBUG_SEL,*PDAC_DSC_DEBUG_SEL;
// DAC Bypass Dsc Debug Select
typedef enum _DAC_BYPASS_DSC_SEL_ {
DAC_BYPASS_DSC_SEL_DISABLE = 0x0,
DAC_BYPASS_DSC_SEL_ENABLE = 0x1,
}DAC_BYPASS_DSC_SEL,*PDAC_BYPASS_DSC_SEL;
// DAC feature status
typedef enum _DAC_FEATURE_STATUS_{
DAC_FEATURE_DISABLED = 0,
DAC_FEATURE_ENABLED = 1,
}DAC_FEATURE_STATUS,*PDAC_FEATURE_STATUS;
// DAC operation type
typedef enum _DAC_OP_TYPE_ {
DAC_POLL_TYPE = 0x0,
DAC_DMA_TYPE = 0x1,
DAC_INTR_TYPE = 0x2,
}DAC_OP_TYPE, *PDAC_OP_TYPE;
// DAC device status
typedef enum _DAC_Device_STATUS_ {
DAC_STS_UNINITIAL = 0x00,
DAC_STS_INITIALIZED = 0x01,
DAC_STS_IDLE = 0x02,
DAC_STS_TX_READY = 0x03,
DAC_STS_TX_ING = 0x04,
DAC_STS_RX_READY = 0x05,
DAC_STS_RX_ING = 0x06,
DAC_STS_ERROR = 0x07,
}DAC_Device_STATUS, *PDAC_Device_STATUS;
//DAC device error type
typedef enum _DAC_ERR_TYPE_ {
DAC_ERR_FIFO_OVER = 0x04, //DAC FIFO overflow.
DAC_ERR_FIFO_STOP = 0x08, //DAC FIFO is completely empty, and it will be stopped automatically.
DAC_ERR_FIFO_WRFAIL = 0x10, //When DAC is NOT enabled, a write operation attempts to access DAC register.
DAC_ERR_FIFO_DSC_OVER0 = 0x20,
DAC_ERR_FIFO_DSC_OVER1 = 0x40,
}DAC_ERR_TYPE, *PDAC_ERR_TYPE;
// DAC data input method
typedef enum _DAC_INPUT_TYPE_{
DAC_INPUT_SINGLE_WR = 0x1, //DAC input by using single register write
DAC_INPUT_DMA_ONEBLK = 0x2, //DAC input by using single DMA block
DAC_INPUT_DMA_LLP = 0x3, //DAC input by using DMA linked list mode
}DAC_INPUT_TYPE,*PDAC_INPUT_TYPE;
//======================================================
// DAC HAL initial data structure
typedef struct _HAL_DAC_INIT_DAT_ {
u8 DACIdx; //DAC index used
u8 DACEn; //DAC module enable
u8 DACDataRate; //DAC data rate, 1'b0:10KHz, 1'b1:250KHz
u8 DACEndian; //DAC endian selection,
//but actually it's for 32-bit DAC data swap control
//1'b0: no swap,
//1'b1: swap the upper 16-bit and the lower 16-bit
u8 DACFilterSet; //DAC filter settle
u8 DACBurstSz; //DAC burst size
u8 DACDbgSel; //DAC debug sel
u8 DACDscDbgSel; //DAC debug dsc sel
u8 DACBPDsc; //DAC bypass delta sigma for loopback
u8 DACDeltaSig; //DAC bypass value of delta sigma
u16 RSVD1;
u32 *DACData; //DAC data pointer
u32 DACPWCtrl; //DAC0 and DAC1 power control
u32 DACAnaCtrl0; //DAC anapar_da control 0
u32 DACAnaCtrl1; //DAC anapar_da control 1
u32 DACIntrMSK; //DAC Interrupt Mask
}HAL_DAC_INIT_DAT,*PHAL_DAC_INIT_DAT;
// DAC HAL Operations
typedef struct _HAL_DAC_OP_ {
RTK_STATUS (*HalDACInit) (VOID *Data); //HAL DAC initialization
RTK_STATUS (*HalDACDeInit) (VOID *Data); //HAL DAC de-initialization
RTK_STATUS (*HalDACEnable) (VOID *Data); //HAL DAC de-initialization
u8 (*HalDACSend) (VOID *Data); //HAL DAC receive
RTK_STATUS (*HalDACIntrCtrl) (VOID *Data); //HAL DAC interrupt control
u32 (*HalDACReadReg) (VOID *Data, u8 DACReg);//HAL DAC read register
}HAL_DAC_OP, *PHAL_DAC_OP;
// DAC user callback adapter
typedef struct _SAL_DAC_USERCB_ADPT_ {
VOID (*USERCB) (VOID *Data);
u32 USERData;
}SAL_DAC_USERCB_ADPT, *PSAL_DAC_USERCB_ADPT;
// DAC user callback structure
typedef struct _SAL_DAC_USER_CB_ {
PSAL_DAC_USERCB_ADPT pTXCB; //DAC Transmit Callback
PSAL_DAC_USERCB_ADPT pTXCCB; //DAC Transmit Complete Callback
PSAL_DAC_USERCB_ADPT pRXCB; //DAC Receive Callback
PSAL_DAC_USERCB_ADPT pRXCCB; //DAC Receive Complete Callback
PSAL_DAC_USERCB_ADPT pRDREQCB; //DAC Read Request Callback
PSAL_DAC_USERCB_ADPT pERRCB; //DAC Error Callback
PSAL_DAC_USERCB_ADPT pDMATXCB; //DAC DMA Transmit Callback
PSAL_DAC_USERCB_ADPT pDMATXCCB; //DAC DMA Transmit Complete Callback
PSAL_DAC_USERCB_ADPT pDMARXCB; //DAC DMA Receive Callback
PSAL_DAC_USERCB_ADPT pDMARXCCB; //DAC DMA Receive Complete Callback
}SAL_DAC_USER_CB, *PSAL_DAC_USER_CB;
// DAC Transmit Buffer
typedef struct _SAL_DAC_TRANSFER_BUF_ {
u32 DataLen; //DAC Transmfer Length
u32 *pDataBuf; //DAC Transfer Buffer Pointer
u32 RSVD; //
}SAL_DAC_TRANSFER_BUF,*PSAL_DAC_TRANSFER_BUF;
typedef struct _SAL_DAC_DMA_USER_DEF_ {
u8 TxDatSrcWdth;
u8 TxDatDstWdth;
u8 TxDatSrcBstSz;
u8 TxDatDstBstSz;
u8 TxChNo;
u8 LlpCtrl;
u16 RSVD0;
u32 MaxMultiBlk;
u32 pLlix;
u32 pBlockSizeList;
}SAL_DAC_DMA_USER_DEF, *PSAL_DAC_DMA_USER_DEF;
// Software API Level DAC Handler
typedef struct _SAL_DAC_HND_ {
u8 DevNum; //DAC device number
u8 PinMux; //DAC pin mux seletion
u8 OpType; //DAC operation type selection
volatile u8 DevSts; //DAC device status
u8 DACInType; //DAC input type
u8 RSVD0;
u16 RSVD1;
u32 DACExd; //DAC extended options:
//bit 0: example
//bit 31~bit 1: Reserved
u32 ErrType; //
u32 TimeOut; //DAC IO Timeout count
PHAL_DAC_INIT_DAT pInitDat; //Pointer to DAC initial data struct
PSAL_DAC_TRANSFER_BUF pTXBuf; //Pointer to DAC TX buffer
PSAL_DAC_USER_CB pUserCB; //Pointer to DAC User Callback
PSAL_DAC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA Config
}SAL_DAC_HND, *PSAL_DAC_HND;
// DAC SAL handle private
typedef struct _SAL_DAC_HND_PRIV_ {
VOID **ppSalDACHnd; //Pointer to SAL_DAC_HND pointer
SAL_DAC_HND SalDACHndPriv; //Private SAL_DAC_HND
}SAL_DAC_HND_PRIV, *PSAL_DAC_HND_PRIV;
//DAC SAL management adapter
typedef struct _SAL_DAC_MNGT_ADPT_ {
PSAL_DAC_HND_PRIV pSalHndPriv; //Pointer to SAL_DAC_HND
PHAL_DAC_INIT_DAT pHalInitDat; //Pointer to HAL DAC initial data( HAL_I2C_INIT_DAT )
PHAL_DAC_OP pHalOp; //Pointer to HAL DAC operation( HAL_DAC_OP )
VOID (*pHalOpInit)(VOID*); //Pointer to HAL DAC initialize function
PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
PSAL_DAC_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_DAC_USER_CB )
VOID (*pSalIrqFunc)(VOID*); //Used for SAL DAC interrupt function
PSAL_DAC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA config
PHAL_GDMA_ADAPTER pHalGdmaAdp;
PHAL_GDMA_OP pHalGdmaOp;
VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL DAC initialize function
PIRQ_HANDLE pIrqGdmaHnd;
VOID (*pSalDMAIrqFunc)(VOID*); //Used for SAL DAC interrupt function
}SAL_DAC_MNGT_ADPT, *PSAL_DAC_MNGT_ADPT;
//================ DAC HAL Function Prototype ===================
// DAC HAL inline function
// For checking DAC input index valid or not
static inline RTK_STATUS
RtkDACIdxChk(
IN u8 DACIdx
)
{
#if !DAC0_USED
if (DACIdx == DAC0_SEL)
return _EXIT_FAILURE;
#endif
#if !DAC1_USED
if (DACIdx == DAC1_SEL)
return _EXIT_FAILURE;
#endif
return _EXIT_SUCCESS;
}
VOID HalDACOpInit(IN VOID *Data);
RTK_STATUS RtkDACLoadDefault(IN VOID *Data);
RTK_STATUS RtkDACInit(IN VOID *Data);
RTK_STATUS RtkDACDeInit(IN VOID *Data);
RTK_STATUS RtkDACSend(IN VOID *Data);
PSAL_DAC_HND RtkDACGetSalHnd(IN u8 DACIdx);
RTK_STATUS RtkDACFreeSalHnd(IN PSAL_DAC_HND pSalDACHND);
PSAL_DAC_MNGT_ADPT RtkDACGetMngtAdpt(IN u8 DACIdx);
RTK_STATUS RtkDACFreeMngtAdpt(IN PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_DIAG_H_
#define _HAL_DIAG_H_
//Register offset
#define UART_REV_BUF_OFF 0x00
#define UART_TRAN_HOLD_OFF 0x00
#define UART_DLH_OFF 0x04
#define UART_DLL_OFF 0x00
#define UART_INTERRUPT_EN_REG_OFF 0x04
#define UART_INTERRUPT_IDEN_REG_OFF 0x08
#define UART_FIFO_CTL_REG_OFF 0x08
#define UART_LINE_CTL_REG_OFF 0x0c
#define UART_MODEM_CTL_REG_OFF 0x10
#define UART_LINE_STATUS_REG_OFF 0x14
#define UART_MODEM_STATUS_REG_OFF 0x18
#define UART_FIFO_ACCESS_REG_OFF 0x70
#define UART_STATUS_REG_OFF 0x7c
#define UART_TFL_OFF 0x80
#define UART_RFL_OFF 0x84
//Buad rate
#define UART_BAUD_RATE_2400 2400
#define UART_BAUD_RATE_4800 4800
#define UART_BAUD_RATE_9600 9600
#define UART_BAUD_RATE_19200 19200
#define UART_BAUD_RATE_38400 38400
#define UART_BAUD_RATE_57600 57600
#define UART_BAUD_RATE_115200 115200
#define UART_BAUD_RATE_921600 921600
#define UART_BAUD_RATE_1152000 1152000
#define UART_PARITY_ENABLE 0x08
#define UART_PARITY_DISABLE 0
#define UART_DATA_LEN_5BIT 0x0
#define UART_DATA_LEN_6BIT 0x1
#define UART_DATA_LEN_7BIT 0x2
#define UART_DATA_LEN_8BIT 0x3
#define UART_STOP_1BIT 0x0
#define UART_STOP_2BIT 0x4
#define HAL_UART_READ32(addr) HAL_READ32(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE32(addr, value) HAL_WRITE32(LOG_UART_REG_BASE, addr, value)
#define HAL_UART_READ16(addr) HAL_READ16(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE16(addr, value) HAL_WRITE16(LOG_UART_REG_BASE, addr, value)
#define HAL_UART_READ8(addr) HAL_READ8(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE8(addr, value) HAL_WRITE8(LOG_UART_REG_BASE, addr, value)
typedef struct _LOG_UART_ADAPTER_ {
u32 BaudRate;
u32 FIFOControl;
u32 IntEnReg;
u8 Parity;
u8 Stop;
u8 DataLength;
}LOG_UART_ADAPTER, *PLOG_UART_ADAPTER;
typedef struct _COMMAND_TABLE_ {
const u8* cmd;
u16 ArgvCnt;
u32 (*func)(u16 argc, u8* argv[]);
const u8* msg;
}COMMAND_TABLE, *PCOMMAND_TABLE;
//VOID
//HalLogUartHandle(void);
extern _LONG_CALL_ROM_ u32
HalLogUartInit(
IN LOG_UART_ADAPTER UartAdapter
);
extern _LONG_CALL_ROM_ VOID
HalSerialPutcRtl8195a(
IN u8 c
);
extern _LONG_CALL_ROM_ u8
HalSerialGetcRtl8195a(
IN BOOL PullMode
);
extern _LONG_CALL_ROM_ u32
HalSerialGetIsrEnRegRtl8195a(VOID);
extern _LONG_CALL_ROM_ VOID
HalSerialSetIrqEnRegRtl8195a (
IN u32 SetValue
);
#endif//_HAL_DIAG_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_EFUSE_H_
#define _HAL_EFUSE_H_
_LONG_CALL_ROM_ extern VOID HalEFUSEPowerSwitch8195AROM(IN u8 bWrite, IN u8 PwrState, IN u8 L25OutVoltage);
_LONG_CALL_ extern u32 HALEFUSEOneByteReadROM(IN u32 CtrlSetting, IN u16 Addr, OUT u8 *Data, IN u8 L25OutVoltage);
_LONG_CALL_ extern u32 HALEFUSEOneByteWriteROM(IN u32 CtrlSetting, IN u16 Addr, IN u8 Data, IN u8 L25OutVoltage);
#define EFUSERead8 HALEFUSEOneByteReadROM
#define EFUSEWrite8 HALEFUSEOneByteWriteROM
#define L25EOUTVOLTAGE 7
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_GDMA_H_
#define _HAL_GDMA_H_
#include "rtl8195a_gdma.h"
typedef struct _GDMA_CH_LLI_ELE_ {
u32 Sarx;
u32 Darx;
u32 Llpx;
u32 CtlxLow;
u32 CtlxUp;
u32 Temp;
}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
#if 1
#if 0
typedef struct _GDMA_CH_LLI_ {
PGDMA_CH_LLI_ELE pLliEle;
PGDMA_CH_LLI pNextLli;
}GDMA_CH_LLI, *PGDMA_CH_LLI;
typedef struct _BLOCK_SIZE_LIST_ {
u32 BlockSize;
PBLOCK_SIZE_LIST pNextBlockSiz;
}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST;
#else
struct GDMA_CH_LLI {
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pNextLli;
};
struct BLOCK_SIZE_LIST {
u32 BlockSize;
struct BLOCK_SIZE_LIST *pNextBlockSiz;
};
#endif
#endif
typedef struct _HAL_GDMA_ADAPTER_ {
u32 ChSar;
u32 ChDar;
GDMA_CHANNEL_NUM ChEn;
GDMA_CTL_REG GdmaCtl;
GDMA_CFG_REG GdmaCfg;
u32 PacketLen;
u32 BlockLen;
u32 MuliBlockCunt;
u32 MaxMuliBlock;
struct GDMA_CH_LLI *pLlix;
struct BLOCK_SIZE_LIST *pBlockSizeList;
PGDMA_CH_LLI_ELE pLli;
u32 NextPlli;
u8 TestItem;
u8 ChNum;
u8 GdmaIndex;
u8 IsrCtrl:1;
u8 GdmaOnOff:1;
u8 Llpctrl:1;
u8 Lli0:1;
u8 Rsvd4to7:4;
u8 GdmaIsrType;
}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER;
typedef struct _HAL_GDMA_CHNL_ {
u8 GdmaIndx;
u8 GdmaChnl;
u8 IrqNum;
u8 Reserved;
}HAL_GDMA_CHNL, *PHAL_GDMA_CHNL;
typedef struct _HAL_GDMA_BLOCK_ {
u32 SrcAddr;
u32 DstAddr;
u32 BlockLength;
u32 SrcOffset;
u32 DstOffset;
}HAL_GDMA_BLOCK, *PHAL_GDMA_BLOCK;
typedef struct _HAL_GDMA_OP_ {
VOID (*HalGdmaOnOff)(VOID *Data);
BOOL (*HalGdamChInit)(VOID *Data);
BOOL (*HalGdmaChSeting)(VOID *Data);
BOOL (*HalGdmaChBlockSeting)(VOID *Data);
VOID (*HalGdmaChDis)(VOID *Data);
VOID (*HalGdmaChEn)(VOID *Data);
VOID (*HalGdmaChIsrEnAndDis) (VOID *Data);
u8 (*HalGdmaChIsrClean)(VOID *Data);
VOID (*HalGdmaChCleanAutoSrc)(VOID *Data);
VOID (*HalGdmaChCleanAutoDst)(VOID *Data);
}HAL_GDMA_OP, *PHAL_GDMA_OP;
typedef struct _HAL_GDMA_OBJ_ {
HAL_GDMA_ADAPTER HalGdmaAdapter;
IRQ_HANDLE GdmaIrqHandle;
volatile GDMA_CH_LLI_ELE GdmaChLli[16];
struct GDMA_CH_LLI Lli[16];
struct BLOCK_SIZE_LIST BlockSizeList[16];
u8 Busy; // is transfering
u8 BlockNum;
} HAL_GDMA_OBJ, *PHAL_GDMA_OBJ;
VOID HalGdmaOpInit(IN VOID *Data);
VOID HalGdmaOn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaOff(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChInit(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChBlockSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChIsrEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChIsrDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
u8 HalGdmaChIsrClean(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChCleanAutoSrc(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChCleanAutoDst(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
extern HAL_Status HalGdmaChnlRegister (u8 GdmaIdx, u8 ChnlNum);
extern VOID HalGdmaChnlUnRegister (u8 GdmaIdx, u8 ChnlNum);
extern PHAL_GDMA_CHNL HalGdmaChnlAlloc (HAL_GDMA_CHNL *pChnlOption);
extern VOID HalGdmaChnlFree (HAL_GDMA_CHNL *pChnl);
extern BOOL HalGdmaMemCpyInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern VOID HalGdmaMemCpyDeInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern VOID* HalGdmaMemCpy(PHAL_GDMA_OBJ pHalGdmaObj, void* pDest, void* pSrc, u32 len);
extern VOID HalGdmaMemAggr(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock);
extern BOOL HalGdmaMemCpyAggrInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern const HAL_GDMA_OP _HalGdmaOp;
extern const HAL_GDMA_CHNL GDMA_Chnl_Option[];
extern const HAL_GDMA_CHNL GDMA_Multi_Block_Chnl_Option[];
extern const u16 HalGdmaChnlEn[6];
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_GPIO_H_
#define _HAL_GPIO_H_
#define HAL_GPIO_PIN_INT_MODE 0x80
typedef enum {
_PORT_A = 0,
_PORT_B = 1,
_PORT_C = 2,
_PORT_D = 3,
_PORT_E = 4,
_PORT_F = 5,
_PORT_G = 6,
_PORT_H = 7,
_PORT_I = 8,
_PORT_J = 9,
_PORT_K = 10,
_PORT_MAX
} HAL_GPIO_PORT_NAME;
typedef enum {
_PA_0 = (_PORT_A<<4|0),
_PA_1 = (_PORT_A<<4|1),
_PA_2 = (_PORT_A<<4|2),
_PA_3 = (_PORT_A<<4|3),
_PA_4 = (_PORT_A<<4|4),
_PA_5 = (_PORT_A<<4|5),
_PA_6 = (_PORT_A<<4|6),
_PA_7 = (_PORT_A<<4|7),
_PB_0 = (_PORT_B<<4|0),
_PB_1 = (_PORT_B<<4|1),
_PB_2 = (_PORT_B<<4|2),
_PB_3 = (_PORT_B<<4|3),
_PB_4 = (_PORT_B<<4|4),
_PB_5 = (_PORT_B<<4|5),
_PB_6 = (_PORT_B<<4|6),
_PB_7 = (_PORT_B<<4|7),
_PC_0 = (_PORT_C<<4|0),
_PC_1 = (_PORT_C<<4|1),
_PC_2 = (_PORT_C<<4|2),
_PC_3 = (_PORT_C<<4|3),
_PC_4 = (_PORT_C<<4|4),
_PC_5 = (_PORT_C<<4|5),
_PC_6 = (_PORT_C<<4|6),
_PC_7 = (_PORT_C<<4|7),
_PC_8 = (_PORT_C<<4|8),
_PC_9 = (_PORT_C<<4|9),
_PD_0 = (_PORT_D<<4|0),
_PD_1 = (_PORT_D<<4|1),
_PD_2 = (_PORT_D<<4|2),
_PD_3 = (_PORT_D<<4|3),
_PD_4 = (_PORT_D<<4|4),
_PD_5 = (_PORT_D<<4|5),
_PD_6 = (_PORT_D<<4|6),
_PD_7 = (_PORT_D<<4|7),
_PD_8 = (_PORT_D<<4|8),
_PD_9 = (_PORT_D<<4|9),
_PE_0 = (_PORT_E<<4|0),
_PE_1 = (_PORT_E<<4|1),
_PE_2 = (_PORT_E<<4|2),
_PE_3 = (_PORT_E<<4|3),
_PE_4 = (_PORT_E<<4|4),
_PE_5 = (_PORT_E<<4|5),
_PE_6 = (_PORT_E<<4|6),
_PE_7 = (_PORT_E<<4|7),
_PE_8 = (_PORT_E<<4|8),
_PE_9 = (_PORT_E<<4|9),
_PE_A = (_PORT_E<<4|10),
_PF_0 = (_PORT_F<<4|0),
_PF_1 = (_PORT_F<<4|1),
_PF_2 = (_PORT_F<<4|2),
_PF_3 = (_PORT_F<<4|3),
_PF_4 = (_PORT_F<<4|4),
_PF_5 = (_PORT_F<<4|5),
// _PF_6 = (_PORT_F<<4|6),
// _PF_7 = (_PORT_F<<4|7),
_PG_0 = (_PORT_G<<4|0),
_PG_1 = (_PORT_G<<4|1),
_PG_2 = (_PORT_G<<4|2),
_PG_3 = (_PORT_G<<4|3),
_PG_4 = (_PORT_G<<4|4),
_PG_5 = (_PORT_G<<4|5),
_PG_6 = (_PORT_G<<4|6),
_PG_7 = (_PORT_G<<4|7),
_PH_0 = (_PORT_H<<4|0),
_PH_1 = (_PORT_H<<4|1),
_PH_2 = (_PORT_H<<4|2),
_PH_3 = (_PORT_H<<4|3),
_PH_4 = (_PORT_H<<4|4),
_PH_5 = (_PORT_H<<4|5),
_PH_6 = (_PORT_H<<4|6),
_PH_7 = (_PORT_H<<4|7),
_PI_0 = (_PORT_I<<4|0),
_PI_1 = (_PORT_I<<4|1),
_PI_2 = (_PORT_I<<4|2),
_PI_3 = (_PORT_I<<4|3),
_PI_4 = (_PORT_I<<4|4),
_PI_5 = (_PORT_I<<4|5),
_PI_6 = (_PORT_I<<4|6),
_PI_7 = (_PORT_I<<4|7),
_PJ_0 = (_PORT_J<<4|0),
_PJ_1 = (_PORT_J<<4|1),
_PJ_2 = (_PORT_J<<4|2),
_PJ_3 = (_PORT_J<<4|3),
_PJ_4 = (_PORT_J<<4|4),
_PJ_5 = (_PORT_J<<4|5),
_PJ_6 = (_PORT_J<<4|6),
// _PJ_7 = (_PORT_J<<4|7),
_PK_0 = (_PORT_K<<4|0),
_PK_1 = (_PORT_K<<4|1),
_PK_2 = (_PORT_K<<4|2),
_PK_3 = (_PORT_K<<4|3),
_PK_4 = (_PORT_K<<4|4),
_PK_5 = (_PORT_K<<4|5),
_PK_6 = (_PORT_K<<4|6),
// _PK_7 = (_PORT_K<<4|7),
// Not connected
_PIN_NC = (int)0xFFFFFFFF
} HAL_PIN_NAME;
typedef enum
{
GPIO_PIN_LOW = 0,
GPIO_PIN_HIGH = 1,
GPIO_PIN_ERR = 2 // read Pin error
} HAL_GPIO_PIN_STATE;
typedef enum {
DIN_PULL_NONE = 0, //floating or high impedance ?
DIN_PULL_LOW = 1,
DIN_PULL_HIGH = 2,
DOUT_PUSH_PULL = 3,
DOUT_OPEN_DRAIN = 4,
INT_LOW = (5|HAL_GPIO_PIN_INT_MODE), // Interrupt Low level trigger
INT_HIGH = (6|HAL_GPIO_PIN_INT_MODE), // Interrupt High level trigger
INT_FALLING = (7|HAL_GPIO_PIN_INT_MODE), // Interrupt Falling edge trigger
INT_RISING = (8|HAL_GPIO_PIN_INT_MODE) // Interrupt Rising edge trigger
} HAL_GPIO_PIN_MODE;
enum {
GPIO_PORT_A = 0,
GPIO_PORT_B = 1,
GPIO_PORT_C = 2,
GPIO_PORT_D = 3
};
typedef enum {
hal_PullNone = 0,
hal_PullUp = 1,
hal_PullDown = 2,
hal_OpenDrain = 3,
hal_PullDefault = hal_PullNone
} HAL_PinMode;
typedef struct _HAL_GPIO_PORT_ {
u32 out_data; // to write the GPIO port
u32 in_data; // to read the GPIO port
u32 dir; // config each pin direction
}HAL_GPIO_PORT, *PHAL_GPIO_PORT;
#define HAL_GPIO_PIN_NAME(port,pin) (((port)<<5)|(pin))
#define HAL_GPIO_GET_PORT_BY_NAME(x) ((x>>5) & 0x03)
#define HAL_GPIO_GET_PIN_BY_NAME(x) (x & 0x1f)
typedef struct _HAL_GPIO_PIN_ {
HAL_GPIO_PIN_MODE pin_mode;
u32 pin_name; // Pin: [7:5]: port number, [4:0]: pin number
}HAL_GPIO_PIN, *PHAL_GPIO_PIN;
typedef struct _HAL_GPIO_OP_ {
#if defined(__ICCARM__)
void* dummy;
#endif
}HAL_GPIO_OP, *PHAL_GPIO_OP;
typedef void (*GPIO_IRQ_FUN)(VOID *Data, u32 Id);
typedef void (*GPIO_USER_IRQ_FUN)(u32 Id);
typedef struct _HAL_GPIO_ADAPTER_ {
IRQ_HANDLE IrqHandle; // GPIO HAL IRQ Handle
GPIO_USER_IRQ_FUN UserIrqHandler; // GPIO IRQ Handler
GPIO_IRQ_FUN PortA_IrqHandler[32]; // The interrupt handler triggered by Port A[x]
VOID *PortA_IrqData[32];
VOID (*EnterCritical)(void);
VOID (*ExitCritical)(void);
u32 Local_Gpio_Dir[3]; // to record direction setting: 0- IN, 1- Out
u8 Gpio_Func_En; // Is GPIO HW function enabled ?
u8 Locked;
}HAL_GPIO_ADAPTER, *PHAL_GPIO_ADAPTER;
u32
HAL_GPIO_GetPinName(
u32 chip_pin
);
VOID
HAL_GPIO_PullCtrl(
u32 pin,
u32 mode
);
VOID
HAL_GPIO_Init(
HAL_GPIO_PIN *GPIO_Pin
);
VOID
HAL_GPIO_Irq_Init(
HAL_GPIO_PIN *GPIO_Pin
);
#endif // end of "#define _HAL_GPIO_H_"

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_I2C_H_ //#ifndef _HAL_I2C_H_
#define _HAL_I2C_H_
#include "rtl8195a_i2c.h"
#include "hal_gdma.h"
//================= I2C CONFIGURATION START ==================
// I2C SAL User Configuration Flags
// I2C SAL operation types
#define I2C_POLL_OP_TYPE 1
#define I2C_INTR_OP_TYPE 1
#define I2C_DMA_OP_TYPE 1
// I2C supports user register address
#define I2C_USER_REG_ADDR 1 //I2C User specific register address by using
//the first I2C data as the register
//address
// I2C SAL used module. Please set the I2C module flag to 1 to enable the related
// I2C module functions.
#define I2C0_USED 1
#define I2C1_USED 1
#define I2C2_USED 1
#define I2C3_USED 1
//================= I2C CONFIGURATION END ===================
//================= I2C HAL START ==========================
// I2C debug output
#define I2C_PREFIX "RTL8195A[i2c]: "
#define I2C_PREFIX_LVL " [i2c_DBG]: "
typedef enum _I2C_DBG_LVL_ {
HAL_I2C_LVL = 0x01,
SAL_I2C_LVL = 0x02,
VERI_I2C_LVL = 0x03,
}I2C_DBG_LVL,*PI2C_DBG_LVL;
#ifdef CONFIG_DEBUG_LOG
#ifdef CONFIG_DEBUG_LOG_I2C_HAL
#define DBG_I2C_LOG_PERD 100
#define I2CDBGLVL 0xFF
#define DBG_8195A_I2C(...) do{ \
_DbgDump("\r"I2C_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_I2C_LVL(LVL,...) do{\
if (LVL&I2CDBGLVL){\
_DbgDump("\r"I2C_PREFIX_LVL __VA_ARGS__);\
}\
}while(0)
#else
#define DBG_I2C_LOG_PERD 100
#define DBG_8195A_I2C(...)
#define DBG_8195A_I2C_LVL(...)
#endif
#else
#define DBG_I2C_LOG_PERD 100
#define DBG_8195A_I2C(...)
#define DBG_8195A_I2C_LVL(...)
#endif
//======================================================
// I2C HAL related enumeration
// I2C Module Selection
typedef enum _I2C_MODULE_SEL_ {
I2C0_SEL = 0x0,
I2C1_SEL = 0x1,
I2C2_SEL = 0x2,
I2C3_SEL = 0x3,
}I2C_MODULE_SEL,*PI2C_MODULE_SEL;
// I2C HAL initial data structure
typedef struct _HAL_I2C_INIT_DAT_ {
u8 I2CIdx; //I2C index used
u8 I2CEn; //I2C module enable
u8 I2CMaster; //Master or Slave mode
u8 I2CAddrMod; //I2C addressing mode(7-bit, 10-bit)
u8 I2CSpdMod; //I2C speed mode(Standard, Fast, High)
u8 I2CSetup; //I2C SDA setup time
u8 I2CRXTL; //I2C RX FIFO Threshold
u8 I2CTXTL; //I2C TX FIFO Threshold
u8 I2CBusLd; //I2C bus load (pf) for high speed mode
u8 I2CReSTR; //I2C restart support
u8 I2CGC; //I2C general support
u8 I2CStartB; //I2C start byte support
u8 I2CSlvNoAck; //I2C slave no ack support
u8 I2CDMACtrl; //I2C DMA feature support
u8 I2CCmd; //I2C Command
u8 I2CDataLen; //I2C Data Length
u8 I2CSlvAckGC; //I2C slave acks to General Call
u8 I2CStop; //I2C issues STOP bit or not
u16 RSVD0;
u8 *I2CRWData; //I2C Read/Write data pointer
u16 I2CIntrMSK; //I2C Interrupt Mask
u16 I2CIntrClr; //I2C Interrupt register to clear
u16 I2CAckAddr; //I2C target address in I2C Master mode,
//ack address in I2C Slave mode
u16 I2CSdaHd; //I2C SDA hold time
u32 I2CClk; //I2C bus clock (in kHz)
u8 I2CTxDMARqLv; //I2C TX DMA Empty Level
u8 I2CRxDMARqLv; //I2C RX DMA Full Level
u16 RSVD1; //Reserved
}HAL_I2C_INIT_DAT,*PHAL_I2C_INIT_DAT;
// I2C HAL Operations
typedef struct _HAL_I2C_OP_ {
HAL_Status (*HalI2CInit) (VOID *Data); //HAL I2C initialization
HAL_Status (*HalI2CDeInit) (VOID *Data); //HAL I2C de-initialization
HAL_Status (*HalI2CSend) (VOID *Data); //HAL I2C send
u8 (*HalI2CReceive) (VOID *Data); //HAL I2C receive
HAL_Status (*HalI2CEnable) (VOID *Data); //HAL I2C enable module
HAL_Status (*HalI2CIntrCtrl) (VOID *Data); //HAL I2C interrupt control
u32 (*HalI2CReadReg) (VOID *Data, u8 I2CReg);//HAL I2C read register
HAL_Status (*HalI2CWriteReg) (VOID *Data, u8 I2CReg, u32 RegVal);//HAL I2C write register
HAL_Status (*HalI2CSetCLK) (VOID *Data); //HAL I2C set bus clock
HAL_Status (*HalI2CMassSend) (VOID *Data); //HAL I2C mass send
HAL_Status (*HalI2CClrIntr) (VOID *Data); //HAL I2C clear interrupts
HAL_Status (*HalI2CClrAllIntr) (VOID *Data); //HAL I2C clear all interrupts
HAL_Status (*HalI2CDMACtrl) (VOID *Data); //HAL I2C DMA control
}HAL_I2C_OP, *PHAL_I2C_OP;
//================= I2C HAL END ===========================
//================= I2C SAL START ==========================
//I2C SAL Macros
//======================================================
// I2C SAL related enumerations
// I2C Extend Features
typedef enum _I2C_EXD_SUPPORT_{
I2C_EXD_RESTART = 0x1, //BIT_0, RESTART bit
I2C_EXD_GENCALL = 0x2, //BIT_1, Master generates General Call. All "send" operations generate General Call addresss
I2C_EXD_STARTB = 0x4, //BIT_2, Using START BYTE, instead of START Bit
I2C_EXD_SLVNOACK = 0x8, //BIT_3, Slave no ack to master
I2C_EXD_BUS400PF = 0x10, //BIT_4, I2C bus loading is 400pf
I2C_EXD_SLVACKGC = 0x20, //BIT_5, Slave acks to a General Call
I2C_EXD_USER_REG = 0x40, //BIT_6, Using User Register Address
I2C_EXD_USER_TWOB = 0x80, //BIT_7, User Register Address is 2-byte
I2C_EXD_MTR_ADDR_RTY= 0x100, //BIT_8, Master retries to send start condition and Slave address when the slave doesn't ack
// the address.
I2C_EXD_MTR_ADDR_UPD= 0x200, //BIT_9, Master dynamically updates slave address
I2C_EXD_MTR_HOLD_BUS= 0x400, //BIT_10, Master doesn't generate STOP when the FIFO is empty. This would make Master hold
// the bus.
}I2C_EXD_SUPPORT,*PI2C_EXD_SUPPORT;
// I2C operation type
typedef enum _I2C_OP_TYPE_ {
I2C_POLL_TYPE = 0x0,
I2C_DMA_TYPE = 0x1,
I2C_INTR_TYPE = 0x2,
}I2C_OP_TYPE, *PI2C_OP_TYPE;
// I2C pinmux selection
typedef enum _I2C_PINMUX_ {
I2C_PIN_S0 = 0x0,
I2C_PIN_S1 = 0x1,
I2C_PIN_S2 = 0x2,
I2C_PIN_S3 = 0x3, //Only valid for I2C0 and I2C3
}I2C_PINMUX, *PI2C_PINMUX;
// I2C module status
typedef enum _I2C_MODULE_STATUS_ {
I2C_DISABLE = 0x0,
I2C_ENABLE = 0x1,
}I2C_MODULE_STATUS, *PI2C_MODULE_STATUS;
// I2C device status
typedef enum _I2C_Device_STATUS_ {
I2C_STS_UNINITIAL = 0x00,
I2C_STS_INITIALIZED = 0x01,
I2C_STS_IDLE = 0x02,
I2C_STS_TX_READY = 0x03,
I2C_STS_TX_ING = 0x04,
I2C_STS_RX_READY = 0x05,
I2C_STS_RX_ING = 0x06,
I2C_STS_ERROR = 0x10,
I2C_STS_TIMEOUT = 0x11,
}I2C_Device_STATUS, *PI2C_Device_STATUS;
// I2C feature status
typedef enum _I2C_FEATURE_STATUS_{
I2C_FEATURE_DISABLED = 0,
I2C_FEATURE_ENABLED = 1,
}I2C_FEATURE_STATUS,*PI2C_FEATURE_STATUS;
// I2C device mode
typedef enum _I2C_DEV_MODE_ {
I2C_SLAVE_MODE = 0x0,
I2C_MASTER_MODE = 0x1,
}I2C_DEV_MODE, *PI2C_DEV_MODE;
// I2C Bus Transmit/Receive
typedef enum _I2C_DIRECTION_ {
I2C_ONLY_TX = 0x1,
I2C_ONLY_RX = 0x2,
I2C_TXRX = 0x3,
}I2C_DIRECTION, *PI2C_DIRECTION;
//I2C DMA module number
typedef enum _I2C_DMA_MODULE_SEL_ {
I2C_DMA_MODULE_0 = 0x0,
I2C_DMA_MODULE_1 = 0x1
}I2C_DMA_MODULE_SEL, *PI2C_DMA_MODULE_SEL;
// I2C0 DMA peripheral number
typedef enum _I2C0_DMA_PERI_NUM_ {
I2C0_DMA_TX_NUM = 0x8,
I2C0_DMA_RX_NUM = 0x9,
}I2C0_DMA_PERI_NUM,*PI2C0_DMA_PERI_NUM;
// I2C1 DMA peripheral number
typedef enum _I2C1_DMA_PERI_NUM_ {
I2C1_DMA_TX_NUM = 0xA,
I2C1_DMA_RX_NUM = 0xB,
}I2C1_DMA_PERI_NUM,*PI2C1_DMA_PERI_NUM;
// I2C0 DMA module used
typedef enum _I2C0_DMA_MODULE_ {
I2C0_DMA0 = 0x0,
I2C0_DMA1 = 0x1,
}I2C0_DMA_MODULE,*PI2C0_DMA_MODULE;
// I2C0 DMA module used
typedef enum _I2C1_DMA_MODULE_ {
I2C1_DMA0 = 0x0,
I2C1_DMA1 = 0x1,
}I2C1_DMA_MODULE,*PI2C1_DMA_MODULE;
// I2C command type
typedef enum _I2C_COMMAND_TYPE_ {
I2C_WRITE_CMD = 0x0,
I2C_READ_CMD = 0x1,
}I2C_COMMAND_TYPE,*PI2C_COMMAND_TYPE;
// I2C STOP BIT
typedef enum _I2C_STOP_TYPE_ {
I2C_STOP_DIS = 0x0,
I2C_STOP_EN = 0x1,
}I2C_STOP_TYPE, *PI2C_STOP_TYPE;
// I2C error type
typedef enum _I2C_ERR_TYPE_ {
I2C_ERR_RX_UNDER = 0x01, //I2C RX FIFO Underflow
I2C_ERR_RX_OVER = 0x02, //I2C RX FIFO Overflow
I2C_ERR_TX_OVER = 0x04, //I2C TX FIFO Overflow
I2C_ERR_TX_ABRT = 0x08, //I2C TX terminated
I2C_ERR_SLV_TX_NACK = 0x10, //I2C slave transmission terminated by master NACK,
//but there are data in slave TX FIFO
I2C_ERR_USER_REG_TO = 0x20,
I2C_ERR_RX_CMD_TO = 0x21,
I2C_ERR_RX_FF_TO = 0x22,
I2C_ERR_TX_CMD_TO = 0x23,
I2C_ERR_TX_FF_TO = 0x24,
I2C_ERR_TX_ADD_TO = 0x25,
I2C_ERR_RX_ADD_TO = 0x26,
}I2C_ERR_TYPE, *PI2C_ERR_TYPE;
// I2C Time Out type
typedef enum _I2C_TIMEOUT_TYPE_ {
I2C_TIMEOOUT_DISABLE = 0x00,
I2C_TIMEOOUT_ENDLESS = 0xFFFFFFFF,
}I2C_TIMEOUT_TYPE, *PI2C_TIMEOUT_TYPE;
//======================================================
// SAL I2C related data structures
// I2C user callback adapter
typedef struct _SAL_I2C_USERCB_ADPT_ {
VOID (*USERCB) (VOID *Data);
u32 USERData;
}SAL_I2C_USERCB_ADPT, *PSAL_I2C_USERCB_ADPT;
// I2C user callback structure
typedef struct _SAL_I2C_USER_CB_ {
PSAL_I2C_USERCB_ADPT pTXCB; //I2C Transmit Callback
PSAL_I2C_USERCB_ADPT pTXCCB; //I2C Transmit Complete Callback
PSAL_I2C_USERCB_ADPT pRXCB; //I2C Receive Callback
PSAL_I2C_USERCB_ADPT pRXCCB; //I2C Receive Complete Callback
PSAL_I2C_USERCB_ADPT pRDREQCB; //I2C Read Request Callback
PSAL_I2C_USERCB_ADPT pERRCB; //I2C Error Callback
PSAL_I2C_USERCB_ADPT pDMATXCB; //I2C DMA Transmit Callback
PSAL_I2C_USERCB_ADPT pDMATXCCB; //I2C DMA Transmit Complete Callback
PSAL_I2C_USERCB_ADPT pDMARXCB; //I2C DMA Receive Callback
PSAL_I2C_USERCB_ADPT pDMARXCCB; //I2C DMA Receive Complete Callback
PSAL_I2C_USERCB_ADPT pGENCALLCB; //I2C General Call Callback
}SAL_I2C_USER_CB, *PSAL_I2C_USER_CB;
// I2C Transmit Buffer
typedef struct _SAL_I2C_TRANSFER_BUF_ {
u16 DataLen; //I2C Transmfer Length
u16 TargetAddr; //I2C Target Address. It's only valid in Master Mode.
u32 RegAddr; //I2C Register Address. It's only valid in Master Mode.
u32 RSVD; //
u8 *pDataBuf; //I2C Transfer Buffer Pointer
}SAL_I2C_TRANSFER_BUF,*PSAL_I2C_TRANSFER_BUF;
typedef struct _SAL_I2C_DMA_USER_DEF_ {
u8 TxDatSrcWdth;
u8 TxDatDstWdth;
u8 TxDatSrcBstSz;
u8 TxDatDstBstSz;
u8 TxChNo;
u8 RSVD0;
u16 RSVD1;
u8 RxDatSrcWdth;
u8 RxDatDstWdth;
u8 RxDatSrcBstSz;
u8 RxDatDstBstSz;
u8 RxChNo;
u8 RSVD2;
u16 RSVD3;
}SAL_I2C_DMA_USER_DEF, *PSAL_I2C_DMA_USER_DEF;
// RTK I2C OP
typedef struct _RTK_I2C_OP_ {
HAL_Status (*Init) (VOID *Data);
HAL_Status (*DeInit) (VOID *Data);
HAL_Status (*Send) (VOID *Data);
HAL_Status (*Receive) (VOID *Data);
HAL_Status (*IoCtrl) (VOID *Data);
HAL_Status (*PowerCtrl) (VOID *Data);
}RTK_I2C_OP, *PRTK_I2C_OP;
// Software API Level I2C Handler
typedef struct _SAL_I2C_HND_ {
u8 DevNum; //I2C device number
u8 PinMux; //I2C pin mux seletion
u8 OpType; //I2C operation type selection
volatile u8 DevSts; //I2C device status
u8 I2CMaster; //I2C Master or Slave mode
u8 I2CAddrMod; //I2C 7-bit or 10-bit mode
u8 I2CSpdMod; //I2C SS/ FS/ HS speed mode
u8 I2CAckAddr; //I2C target address in Master
//mode or ack address in Slave
//mode
u16 I2CClk; //I2C bus clock
u8 MasterRead; //I2C Master Read Supported,
//An Address will be sent before
//read data back.
u8 I2CDmaSel; //I2C DMA module select
// 0 for DMA0,
// 1 for DMA1
u8 I2CTxDMARqLv; //I2C TX DMA Empty Level
u8 I2CRxDMARqLv; //I2C RX DMA Full Level
u16 RSVD0; //Reserved
u32 AddRtyTimeOut; //I2C TimeOut Value for master send address retry
//(Originally Reserved.)
u32 I2CExd; //I2C extended options:
//bit 0: I2C RESTART supported,
// 0 for NOT supported,
// 1 for supported
//bit 1: I2C General Call supported
// 0 for NOT supported,
// 1 for supported
//bit 2: I2C START Byte supported
// 0 for NOT supported,
// 1 for supported
//bit 3: I2C Slave-No-Ack
// supported
// 0 for NOT supported,
// 1 for supported
//bit 4: I2C bus loading,
// 0 for 100pf,
// 1 for 400pf
//bit 5: I2C slave ack to General
// Call
//bit 6: I2C User register address
//bit 7: I2C 2-Byte User register
// address
//bit 8: I2C slave address no ack retry,
// It's only for Master mode,
// when slave doesn't ack the
// address
//bit 31~bit 8: Reserved
u32 ErrType; //
u32 TimeOut; //I2C IO Timeout count, in ms
PHAL_I2C_INIT_DAT pInitDat; //Pointer to I2C initial data struct
PSAL_I2C_TRANSFER_BUF pTXBuf; //Pointer to I2C TX buffer
PSAL_I2C_TRANSFER_BUF pRXBuf; //Pointer to I2C RX buffer
PSAL_I2C_USER_CB pUserCB; //Pointer to I2C User Callback
PSAL_I2C_DMA_USER_DEF pDMAConf; //Pointer to I2C User Define DMA config
}SAL_I2C_HND, *PSAL_I2C_HND;
//======================================================
// I2C SAL Function Prototypes
// For checking I2C input index valid or not
static inline HAL_Status
RtkI2CIdxChk(
IN u8 I2CIdx
)
{
if (I2CIdx > I2C3_SEL)
return HAL_ERR_UNKNOWN;
return HAL_OK;
}
#if 0
//For checking I2C operation type valid or not
static inline HAL_Status
RtkI2COpTypeChk(
IN VOID *Data
)
{
PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data;
if (pSalI2CHND->OpType == I2C_POLL_TYPE)
return HAL_ERR_UNKNOWN;
if (pSalI2CHND->OpType == I2C_DMA_TYPE)
return HAL_ERR_UNKNOWN;
if (pSalI2CHND->OpType == I2C_INTR_TYPE)
return HAL_ERR_UNKNOWN;
pSalI2CHND = pSalI2CHND;
return HAL_OK;
}
#endif
//For checking I2C DMA available or not
static inline HAL_Status
RtkI2CDMAChk(
IN VOID *Data
)
{
PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data;
if (pSalI2CHND->OpType == I2C_DMA_TYPE) {
if (pSalI2CHND->DevNum >= I2C2_SEL)
return HAL_ERR_UNKNOWN;
}
else {
return HAL_ERR_UNKNOWN;
}
return HAL_OK;
}
//For checking I2C DMA available or not
static inline HAL_Status
RtkI2CDMAInitChk(
IN VOID *Data
)
{
PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data;
if (pSalI2CHND->OpType != I2C_DMA_TYPE) {
return HAL_ERR_UNKNOWN;
}
else {
return HAL_OK;
}
}
//======================================================
//SAL I2C management function prototype
_LONG_CALL_ROM_ HAL_Status RtkI2CLoadDefault(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CInit(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CDeInit(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CSend(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CReceive(IN VOID *Data);
_LONG_CALL_ROM_ VOID RtkSalI2COpInit(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CSendUserAddr(IN VOID *Data,IN u8 MtrWr);
_LONG_CALL_ROM_ HAL_Status RtkI2CIoCtrl(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CPowerCtrl(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CInitForPS(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CDeInitForPS(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CDisablePS(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CEnablePS(IN VOID *Data);
//================= I2C SAL END ===========================
//================= I2C SAL MANAGEMENT START =================
// I2C SAL management macros
#define SAL_USER_CB_NUM (sizeof(SAL_I2C_USER_CB) / sizeof(PSAL_I2C_USERCB_ADPT))
//======================================================
// I2C SAL management data structures
// I2C SAL handle private
typedef struct _SAL_I2C_HND_PRIV_ {
VOID **ppSalI2CHnd; //Pointer to SAL_I2C_HND pointer
SAL_I2C_HND SalI2CHndPriv; //Private SAL_I2C_HND
}SAL_I2C_HND_PRIV, *PSAL_I2C_HND_PRIV;
//I2C SAL management adapter
typedef struct _SAL_I2C_MNGT_ADPT_ {
PSAL_I2C_HND_PRIV pSalHndPriv; //Pointer to SAL_I2C_HND
PHAL_I2C_INIT_DAT pHalInitDat; //Pointer to HAL I2C initial data( HAL_I2C_INIT_DAT )
PHAL_I2C_OP pHalOp; //Pointer to HAL I2C operation( HAL_I2C_OP )
VOID (*pHalOpInit)(VOID*); //Pointer to HAL I2C initialize function
PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
PSAL_I2C_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_I2C_USER_CB )
volatile u32 MstRDCmdCnt; //Used for Master Read command count
volatile u32 InnerTimeOut; //Used for SAL internal timeout count
VOID (*pSalIrqFunc)(VOID*); //Used for SAL I2C interrupt function
PSAL_I2C_DMA_USER_DEF pDMAConf; //Pointer to I2C User Define DMA config
PHAL_GDMA_ADAPTER pHalTxGdmaAdp; //Pointer to HAL_GDMA_ADAPTER
PHAL_GDMA_ADAPTER pHalRxGdmaAdp; //Pointer to HAL_GDMA_ADAPTER
PHAL_GDMA_OP pHalGdmaOp; //Pointer to HAL_GDMA_OP
VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL I2C initialize function
PIRQ_HANDLE pIrqTxGdmaHnd; //Pointer to IRQ handler for Tx GDMA
PIRQ_HANDLE pIrqRxGdmaHnd; //Pointer to IRQ handler for Rx GDMA
VOID (*pSalDMATxIrqFunc)(VOID*); //Used for SAL I2C interrupt function
VOID (*pSalDMARxIrqFunc)(VOID*); //Used for SAL I2C interrupt function
u32 RSVD; //Reserved
}SAL_I2C_MNGT_ADPT, *PSAL_I2C_MNGT_ADPT;
//======================================================
//SAL I2C management function prototype
PSAL_I2C_MNGT_ADPT RtkI2CGetMngtAdpt(IN u8 I2CIdx);
HAL_Status RtkI2CFreeMngtAdpt(IN PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt);
PSAL_I2C_HND RtkI2CGetSalHnd(IN u8 I2CIdx);
HAL_Status RtkI2CFreeSalHnd(IN PSAL_I2C_HND pSalI2CHND);
u32 RtkSalI2CSts(IN VOID *Data);
extern _LONG_CALL_ VOID I2CISRHandle(IN VOID *Data);
extern _LONG_CALL_ VOID I2CTXGDMAISRHandle(IN VOID *Data);
extern _LONG_CALL_ VOID I2CRXGDMAISRHandle(IN VOID *Data);
extern HAL_Status I2CIsTimeout (IN u32 StartCount, IN u32 TimeoutCnt);
extern HAL_TIMER_OP HalTimerOp;
//======================================================
// Function Prototypes
_LONG_CALL_ VOID HalI2COpInit(IN VOID *Data);
//================= I2C SAL MANAGEMENT END ==================
//================= Rtl8195a I2C V02 function prototype ============
_LONG_CALL_ VOID HalI2COpInitV02(IN VOID *Data);
_LONG_CALL_ VOID I2CISRHandleV02(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CSendV02(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CReceiveV02(IN VOID *Data);
_LONG_CALL_ VOID RtkSalI2COpInitV02(IN VOID *Data);
//================= Rtl8195a I2C V02 function prototype END==========
//======================================================
//SAL I2C patch function prototype
HAL_Status RtkI2CSend_Patch(IN VOID *Data);
HAL_Status RtkI2CReceive_Patch(IN VOID *Data);
VOID HalI2COpInit_Patch(IN VOID *Data);
VOID I2CISRHandle_Patch(IN VOID *Data);
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
#define RtkI2CSend RtkI2CSend_Patch
#define RtkI2CReceive RtkI2CReceive_Patch
#endif
HAL_Status RtkI2CSend_Patch(IN VOID *Data);
HAL_Status RtkI2CReceive_Patch(IN VOID *Data);
//================= I2C SAL END ===========================
#endif //#ifndef _HAL_I2C_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_I2S_H_
#define _HAL_I2S_H_
#include "rtl8195a_i2s.h"
/* User Define Flags */
#define I2S_MAX_ID 1 // valid I2S index 0 ~ I2S_MAX_ID
/**********************************************************************/
/* I2S HAL initial data structure */
typedef struct _HAL_I2S_INIT_DAT_ {
u8 I2SIdx; /*I2S index used*/
u8 I2SEn; /*I2S module enable tx/rx/tx+rx*/
u8 I2SMaster; /*I2S Master or Slave mode*/
u8 I2SWordLen; /*I2S Word length 16 or 24bits*/
u8 I2SChNum; /*I2S Channel number mono or stereo*/
u8 I2SPageNum; /*I2S Page Number 2~4*/
u16 I2SPageSize; /*I2S page Size 1~4096 word*/
u8 *I2STxData; /*I2S Tx data pointer*/
u8 *I2SRxData; /*I2S Rx data pointer*/
u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/
u32 I2STxIntrClr; /*I2S Tx Interrupt register to clear */
u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/
u32 I2SRxIntrClr; /*I2S Rx Interrupt register to clear*/
u16 I2STxIdx; /*I2S TX page index */
u16 I2SRxIdx; /*I2S RX page index */
u16 I2SHWTxIdx; /*I2S HW TX page index */
u16 I2SHWRxIdx; /*I2S HW RX page index */
u16 I2SRate; /*I2S sample rate*/
u8 I2STRxAct; /*I2S tx rx act*/
}HAL_I2S_INIT_DAT, *PHAL_I2S_INIT_DAT;
/**********************************************************************/
/* I2S Data Structures */
/* I2S Module Selection */
typedef enum _I2S_MODULE_SEL_ {
I2S0_SEL = 0x0,
I2S1_SEL = 0x1,
}I2S_MODULE_SEL,*PI2S_MODULE_SEL;
/*
typedef struct _HAL_I2S_ADAPTER_ {
u32 Enable:1;
I2S_CTL_REG I2sCtl;
I2S_SETTING_REG I2sSetting;
u32 abc;
u8 I2sIndex;
}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER;
*/
/* I2S HAL Operations */
typedef struct _HAL_I2S_OP_ {
RTK_STATUS (*HalI2SInit) (VOID *Data);
RTK_STATUS (*HalI2SDeInit) (VOID *Data);
RTK_STATUS (*HalI2STx) (VOID *Data, u8 *pBuff);
RTK_STATUS (*HalI2SRx) (VOID *Data, u8 *pBuff);
RTK_STATUS (*HalI2SEnable) (VOID *Data);
RTK_STATUS (*HalI2SIntrCtrl) (VOID *Data);
u32 (*HalI2SReadReg) (VOID *Data, u8 I2SReg);
RTK_STATUS (*HalI2SSetRate) (VOID *Data);
RTK_STATUS (*HalI2SSetWordLen) (VOID *Data);
RTK_STATUS (*HalI2SSetChNum) (VOID *Data);
RTK_STATUS (*HalI2SSetPageNum) (VOID *Data);
RTK_STATUS (*HalI2SSetPageSize) (VOID *Data);
RTK_STATUS (*HalI2SClrIntr) (VOID *Data);
RTK_STATUS (*HalI2SClrAllIntr) (VOID *Data);
RTK_STATUS (*HalI2SDMACtrl) (VOID *Data);
/*
VOID (*HalI2sOnOff)(VOID *Data);
BOOL (*HalI2sInit)(VOID *Data);
BOOL (*HalI2sSetting)(VOID *Data);
BOOL (*HalI2sEn)(VOID *Data);
BOOL (*HalI2sIsrEnAndDis) (VOID *Data);
BOOL (*HalI2sDumpReg)(VOID *Data);
BOOL (*HalI2s)(VOID *Data);
*/
}HAL_I2S_OP, *PHAL_I2S_OP;
/**********************************************************************/
/* I2S Pinmux Selection */
#if 0
typedef enum _I2S0_PINMUX_ {
I2S0_TO_S0 = 0x0,
I2S0_TO_S1 = 0x1,
I2S0_TO_S2 = 0x2,
}I2S0_PINMUX, *PI2S0_PINMUX;
typedef enum _I2S1_PINMUX_ {
I2S1_TO_S0 = 0x0,
I2S1_TO_S1 = 0x1,
}I2S1_PINMUX, *PI2S1_PINMUX;
#endif
typedef enum _I2S_PINMUX_ {
I2S_S0 = 0,
I2S_S1 = 1,
I2S_S2 = 2,
I2S_S3 = 3
}I2S_PINMUX, *PI2S_PINMUX;
/* I2S Module Status */
typedef enum _I2S_MODULE_STATUS_ {
I2S_DISABLE = 0x0,
I2S_ENABLE = 0x1,
}I2S_MODULE_STATUS, *PI2S_MODULE_STATUS;
/* I2S Device Status */
typedef enum _I2S_Device_STATUS_ {
I2S_STS_UNINITIAL = 0x00,
I2S_STS_INITIALIZED = 0x01,
I2S_STS_IDLE = 0x02,
I2S_STS_TX_READY = 0x03,
I2S_STS_TX_ING = 0x04,
I2S_STS_RX_READY = 0x05,
I2S_STS_RX_ING = 0x06,
I2S_STS_TRX_READY = 0x07,
I2S_STS_TRX_ING = 0x08,
I2S_STS_ERROR = 0x09,
}I2S_Device_STATUS, *PI2S_Device_STATUS;
/* I2S Feature Status */
typedef enum _I2S_FEATURE_STATUS_{
I2S_FEATURE_DISABLED = 0,
I2S_FEATURE_ENABLED = 1,
}I2S_FEATURE_STATUS,*PI2S_FEATURE_STATUS;
/* I2S Device Mode */
typedef enum _I2S_DEV_MODE_ {
I2S_MASTER_MODE = 0x0,
I2S_SLAVE_MODE = 0x1
}I2S_DEV_MODE, *PI2S_DEV_MODE;
/* I2S Word Length */
typedef enum _I2S_WORD_LEN_ {
I2S_WL_16 = 0x0,
I2S_WL_24 = 0x1,
}I2S_WORD_LEN, *PI2S_WORD_LEN;
/* I2S Bus Transmit/Receive */
typedef enum _I2S_DIRECTION_ {
I2S_ONLY_RX = 0x0,
I2S_ONLY_TX = 0x1,
I2S_TXRX = 0x2
}I2S_DIRECTION, *PI2S_DIRECTION;
/* I2S Channel number */
typedef enum _I2S_CH_NUM_ {
I2S_CH_STEREO = 0x0,
I2S_CH_RSVD = 0x1,
I2S_CH_MONO = 0x2
}I2S_CH_NUM, *PI2S_CH_NUM;
/* I2S Page number */
typedef enum _I2S_PAGE_NUM_ {
I2S_1PAGE = 0x0,
I2S_2PAGE = 0x1,
I2S_3PAGE = 0x2,
I2S_4PAGE = 0x3
}I2S_PAGE_NUM, *PI2S_PAGE_NUM;
/* I2S Sample rate*/
typedef enum _I2S_SAMPLE_RATE_ {
I2S_SR_8KHZ = 0x00, // /12
I2S_SR_16KHZ = 0x01, // /6
I2S_SR_24KHZ = 0x02, // /4
I2S_SR_32KHZ = 0x03, // /3
I2S_SR_48KHZ = 0x05, // /2
I2S_SR_96KHZ = 0x06, // x1, base 96kHz
I2S_SR_7p35KHZ = 0x10,
I2S_SR_11p02KHZ = 0x11,
I2S_SR_22p05KHZ = 0x12,
I2S_SR_29p4KHZ = 0x13,
I2S_SR_44p1KHZ = 0x15,
I2S_SR_88p2KHZ = 0x16 // x1, base 88200Hz
}I2S_SAMPLE_RATE, *PI2S_SAMPLE_RATE;
/* I2S TX interrupt mask/status */
typedef enum _I2S_TX_IMR_ {
I2S_TX_INT_PAGE0_OK = (1<<0),
I2S_TX_INT_PAGE1_OK = (1<<1),
I2S_TX_INT_PAGE2_OK = (1<<2),
I2S_TX_INT_PAGE3_OK = (1<<3),
I2S_TX_INT_FULL = (1<<4),
I2S_TX_INT_EMPTY = (1<<5)
} I2S_TX_IMR, *PI2S_TX_IMR;
/* I2S RX interrupt mask/status */
typedef enum _I2S_RX_IMR_ {
I2S_RX_INT_PAGE0_OK = (1<<0),
I2S_RX_INT_PAGE1_OK = (1<<1),
I2S_RX_INT_PAGE2_OK = (1<<2),
I2S_RX_INT_PAGE3_OK = (1<<3),
I2S_RX_INT_EMPTY = (1<<4),
I2S_RX_INT_FULL = (1<<5)
} I2S_RX_IMR, *PI2S_RX_IMR;
/* I2S User Callbacks */
typedef struct _SAL_I2S_USER_CB_{
VOID (*TXCB) (VOID *Data);
VOID (*TXCCB) (VOID *Data);
VOID (*RXCB) (VOID *Data);
VOID (*RXCCB) (VOID *Data);
VOID (*RDREQCB) (VOID *Data);
VOID (*ERRCB) (VOID *Data);
VOID (*GENCALLCB) (VOID *Data);
}SAL_I2S_USER_CB,*PSAL_I2S_USER_CB;
typedef struct _I2S_USER_CB_{
VOID (*TxCCB)(uint32_t id, char *pbuf);
u32 TxCBId;
VOID (*RxCCB)(uint32_t id, char *pbuf);
u32 RxCBId;
}I2S_USER_CB,*PI2S_USER_CB;
/* Software API Level I2S Handler */
typedef struct _HAL_I2S_ADAPTER_{
u8 DevNum; //I2S device number
u8 PinMux; //I2S pin mux seletion
u8 RSVD0; //Reserved
volatile u8 DevSts; //I2S device status
u32 RSVD2; //Reserved
u32 I2SExd; //I2S extended options:
//bit 0: I2C RESTART supported,
// 0 for NOT supported,
// 1 for supported
//bit 1: I2C General Call supported
// 0 for NOT supported,
// 1 for supported
//bit 2: I2C START Byte supported
// 0 for NOT supported,
// 1 for supported
//bit 3: I2C Slave-No-Ack
// supported
// 0 for NOT supported,
// 1 for supported
//bit 4: I2C bus loading,
// 0 for 100pf,
// 1 for 400pf
//bit 5: I2C slave ack to General
// Call
//bit 6: I2C User register address
//bit 7: I2C 2-Byte User register
// address
//bit 31~bit 8: Reserved
u32 ErrType; //
u32 TimeOut; //I2S IO Timeout count
PHAL_I2S_INIT_DAT pInitDat; //Pointer to I2S initial data struct
I2S_USER_CB UserCB; //Pointer to I2S User Callback
IRQ_HANDLE IrqHandle; // Irq Handler
u32* TxPageList[4]; // The Tx DAM buffer: pointer of each page
u32* RxPageList[4]; // The Tx DAM buffer: pointer of each page
}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER;
typedef struct _HAL_I2S_DEF_SETTING_{
u8 I2SMaster; // Master or Slave mode
u8 DevSts; //I2S device status
u8 I2SChNum; //I2S Channel number mono or stereo
u8 I2SPageNum; //I2S Page number 2~4
u8 I2STRxAct; //I2S tx rx act, tx only or rx only or tx+rx
u8 I2SWordLen; //I2S Word length 16bit or 24bit
u16 I2SPageSize; //I2S Page size 1~4096 word
u16 I2SRate; //I2S sample rate 8k ~ 96khz
u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/
u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/
}HAL_I2S_DEF_SETTING, *PHAL_I2S_DEF_SETTING;
/**********************************************************************/
HAL_Status
RtkI2SLoadDefault(IN VOID *Adapter, IN VOID *Setting);
HAL_Status
RtkI2SInit(IN VOID *Data);
HAL_Status
RtkI2SDeInit(IN VOID *Data);
HAL_Status
RtkI2SEnable(IN VOID *Data);
HAL_Status
RtkI2SDisable(IN VOID *Data);
extern HAL_Status
HalI2SInit( IN VOID *Data);
extern VOID
HalI2SDeInit( IN VOID *Data);
extern HAL_Status
HalI2SDisable( IN VOID *Data);
extern HAL_Status
HalI2SEnable( IN VOID *Data);
/**********************************************************************/
VOID I2S0ISRHandle(VOID *Data);
VOID I2S1ISRHandle(VOID *Data);
/**********************************************************************/
VOID HalI2SOpInit(
IN VOID *Data
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_IRQN_H_
#define _HAL_IRQN_H_
#define PERIPHERAL_IRQ_BASE_NUM 64
typedef enum _IRQn_Type_ {
#if 0
/****** Cortex-M3 Processor Exceptions Numbers ********/
NON_MASKABLE_INT_IRQ = -14,
HARD_FAULT_IRQ = -13,
MEM_MANAGE_FAULT_IRQ = -12,
BUS_FAULT_IRQ = -11,
USAGE_FAULT_IRQ = -10,
SVCALL_IRQ = -5,
DEBUG_MONITOR_IRQ = -4,
PENDSVC_IRQ = -2,
SYSTICK_IRQ = -1,
#else
/****** Cortex-M3 Processor Exceptions Numbers ********/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
#endif
/****** RTL8195A Specific Interrupt Numbers ************/
SYSTEM_ON_IRQ = 0,
WDG_IRQ = 1,
TIMER0_IRQ = 2,
TIMER1_IRQ = 3,
I2C3_IRQ = 4,
TIMER2_7_IRQ = 5,
SPI0_IRQ = 6,
GPIO_IRQ = 7,
UART0_IRQ = 8,
SPI_FLASH_IRQ = 9,
USB_OTG_IRQ = 10,
SDIO_HOST_IRQ = 11,
SDIO_DEVICE_IRQ = 12,
I2S0_PCM0_IRQ = 13,
I2S1_PCM1_IRQ = 14,
WL_DMA_IRQ = 15,
WL_PROTOCOL_IRQ = 16,
CRYPTO_IRQ = 17,
GMAC_IRQ = 18,
PERIPHERAL_IRQ = 19,
GDMA0_CHANNEL0_IRQ = 20,
GDMA0_CHANNEL1_IRQ = 21,
GDMA0_CHANNEL2_IRQ = 22,
GDMA0_CHANNEL3_IRQ = 23,
GDMA0_CHANNEL4_IRQ = 24,
GDMA0_CHANNEL5_IRQ = 25,
GDMA1_CHANNEL0_IRQ = 26,
GDMA1_CHANNEL1_IRQ = 27,
GDMA1_CHANNEL2_IRQ = 28,
GDMA1_CHANNEL3_IRQ = 29,
GDMA1_CHANNEL4_IRQ = 30,
GDMA1_CHANNEL5_IRQ = 31,
/****** RTL8195A Peripheral Interrupt Numbers ************/
I2C0_IRQ = 64,// 0 + 64,
I2C1_IRQ = 65,// 1 + 64,
I2C2_IRQ = 66,// 2 + 64,
SPI1_IRQ = 72,// 8 + 64,
SPI2_IRQ = 73,// 9 + 64,
UART1_IRQ = 80,// 16 + 64,
UART2_IRQ = 81,// 17 + 64,
UART_LOG_IRQ = 88,// 24 + 64,
ADC_IRQ = 89,// 25 + 64,
DAC0_IRQ = 91,// 27 + 64,
DAC1_IRQ = 92,// 28 + 64,
//RXI300_IRQ = 93// 29 + 64
LP_EXTENSION_IRQ = 93,// 29+64
PTA_TRX_IRQ = 95,// 31+64
RXI300_IRQ = 96,// 0+32 + 64
NFC_IRQ = 97// 1+32+64
} IRQn_Type, *PIRQn_Type;
typedef VOID (*HAL_VECTOR_FUN) (VOID);
typedef enum _VECTOR_TABLE_TYPE_{
DEDECATED_VECTRO_TABLE,
PERIPHERAL_VECTOR_TABLE
}VECTOR_TABLE_TYPE, *PVECTOR_TABLE_TYPE;
typedef u32 (*IRQ_FUN)(VOID *Data);
typedef struct _IRQ_HANDLE_ {
IRQ_FUN IrqFun;
IRQn_Type IrqNum;
u32 Data;
u32 Priority;
}IRQ_HANDLE, *PIRQ_HANDLE;
#endif //_HAL_IRQN_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_MII_H_
#define _HAL_MII_H_
#include "rtl8195a_mii.h"
/**
* LOG Configurations
*/
#define NOLOG
#define LOG_TAG "NoTag"
#define LOG_INFO_HEADER "I"
#define LOG_DEBUG_HEADER "D"
#define LOG_ERROR_HEADER "E"
#define LOG_TEST_HEADER "T"
#define IDENT_TWO_SPACE " "
#define IDENT_FOUR_SPACE " "
#define LOG_INFO(...) do {\
DiagPrintf("\r"LOG_INFO_HEADER"/"LOG_TAG": " __VA_ARGS__);\
}while(0)
#define LOG_DEBUG(...) do {\
DiagPrintf("\r"LOG_DEBUG_HEADER"/"LOG_TAG": " __VA_ARGS__);\
}while(0)
#define LOG_ERROR(...) do {\
DiagPrintf("\r"LOG_ERROR_HEADER"/"LOG_TAG": " __VA_ARGS__);\
}while(0)
#ifdef NOLOG
#define LOGI
#define LOGD
#define LOGE
#define LOGI2
#define LOGD2
#define LOGE2
#define LOGI4
#define LOGD4
#define LOGE4
#else
#define LOGI LOG_INFO
#define LOGD LOG_DEBUG
#define LOGE LOG_ERROR
#define LOGI2(...) LOG_INFO(IDENT_TWO_SPACE __VA_ARGS__)
#define LOGD2(...) LOG_DEBUG(IDENT_TWO_SPACE __VA_ARGS__)
#define LOGE2(...) LOG_ERROR(IDENT_TWO_SPACE __VA_ARGS__)
#define LOGI4(...) LOG_INFO(IDENT_FOUR_SPACE __VA_ARGS__)
#define LOGD4(...) LOG_DEBUG(IDENT_FOUR_SPACE __VA_ARGS__)
#define LOGE4(...) LOG_ERROR(IDENT_FOUR_SPACE __VA_ARGS__)
#endif
#define ANSI_COLOR_GREEN "\x1b[32m"
#define ANSI_COLOR_CYAN "\x1b[36m"
#define ANSI_COLOR_YELLOW "\x1b[33m"
#define ANSI_COLOR_MAGENTA "\x1b[35m"
#define ANSI_COLOR_RED "\x1b[31m"
#define ANSI_COLOR_BLUE "\x1b[34m"
#define ANSI_COLOR_RESET "\x1b[0m"
#define DBG_ENTRANCE LOGI(ANSI_COLOR_GREEN "=> %s() <%s>\n" ANSI_COLOR_RESET, \
__func__, __FILE__)
// GMAC MII Configurations
#ifdef LOG_TAG
#undef LOG_TAG
#define LOG_TAG "MII"
#endif
typedef struct _HAL_MII_ADAPTER_ {
u32 InterruptMask;
PPHY_MODE_INFO pPhyModeInfo;
}HAL_MII_ADAPTER, *PHAL_MII_ADAPTER;
typedef struct _HAL_MII_OP_ {
BOOL (*HalMiiGmacInit)(VOID *Data);
BOOL (*HalMiiInit)(VOID *Data);
BOOL (*HalMiiGmacReset)(VOID *Data);
BOOL (*HalMiiGmacEnablePhyMode)(VOID *Data);
u32 (*HalMiiGmacXmit)(VOID *Data);
VOID (*HalMiiGmacCleanTxRing)(VOID *Data);
VOID (*HalMiiGmacFillTxInfo)(VOID *Data);
VOID (*HalMiiGmacFillRxInfo)(VOID *Data);
VOID (*HalMiiGmacTx)(VOID *Data);
VOID (*HalMiiGmacRx)(VOID *Data);
VOID (*HalMiiGmacSetDefaultEthIoCmd)(VOID *Data);
VOID (*HalMiiGmacInitIrq)(VOID *Data);
u32 (*HalMiiGmacGetInterruptStatus)(VOID);
VOID (*HalMiiGmacClearInterruptStatus)(u32 IsrStatus);
}HAL_MII_OP, *PHAL_MII_OP;
VOID HalMiiOpInit(IN VOID *Data);
typedef struct _MII_ADAPTER_ {
PHAL_MII_OP pHalMiiOp;
PHAL_MII_ADAPTER pHalMiiAdapter;
PTX_INFO pTx_Info;
PRX_INFO pRx_Info;
VOID* TxBuffer;
VOID* RxBuffer;
}MII_ADAPTER, *PMII_ADAPTER;
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _MISC_H_
#define _MISC_H_
#include <basic_types.h>
#ifdef CONFIG_TIMER_MODULE
extern _LONG_CALL_ u32 HalDelayUs(u32 us);
#endif
extern _LONG_CALL_ u32 HalGetCpuClk(VOID);
extern _LONG_CALL_ u8 HalGetRomInfo(VOID);
extern _LONG_CALL_ void *_memset( void *s, int c, SIZE_T n );
extern _LONG_CALL_ void *_memcpy( void *s1, const void *s2, SIZE_T n );
extern _LONG_CALL_ int _memcmp( const void *av, const void *bv, SIZE_T len );
//extern _LONG_CALL_ SIZE_T _strlen(const char *s);
extern _LONG_CALL_ int _strcmp(const char *cs, const char *ct);
#endif //_MISC_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_NFC_H_
#define _HAL_NFC_H_
#include "rtl8195a_nfc.h"
VOID HalNFCOpInit(
IN VOID *Data
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PCM_H_
#define _HAL_PCM_H_
#include "rtl8195a_pcm.h"
/*
typedef struct _GDMA_CH_LLI_ELE_ {
u32 Sarx;
u32 Darx;
u32 Llpx;
u32 CtlxLow;
u32 CtlxUp;
u32 Temp;
}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
#if 1
#if 0
typedef struct _GDMA_CH_LLI_ {
PGDMA_CH_LLI_ELE pLliEle;
PGDMA_CH_LLI pNextLli;
}GDMA_CH_LLI, *PGDMA_CH_LLI;
typedef struct _BLOCK_SIZE_LIST_ {
u32 BlockSize;
PBLOCK_SIZE_LIST pNextBlockSiz;
}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST;
#else
struct GDMA_CH_LLI {
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pNextLli;
};
struct BLOCK_SIZE_LIST {
u32 BlockSize;
struct BLOCK_SIZE_LIST *pNextBlockSiz;
};
#endif
#endif
typedef struct _HAL_GDMA_ADAPTER_ {
u32 ChSar;
u32 ChDar;
GDMA_CHANNEL_NUM ChEn;
GDMA_CTL_REG GdmaCtl;
GDMA_CFG_REG GdmaCfg;
u32 PacketLen;
u32 BlockLen;
u32 MuliBlockCunt;
u32 MaxMuliBlock;
struct GDMA_CH_LLI *pLlix;
struct BLOCK_SIZE_LIST *pBlockSizeList;
PGDMA_CH_LLI_ELE pLli;
u32 NextPlli;
u8 TestItem;
u8 ChNum;
u8 GdmaIndex;
u8 IsrCtrl:1;
u8 GdmaOnOff:1;
u8 Llpctrl:1;
u8 Lli0:1;
u8 Rsvd4to7:4;
u8 GdmaIsrType;
}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER;
*/
typedef struct _HAL_PCM_ADAPTER_ {
u32 Enable:1;
PCM_CTL_REG PcmCtl;
PCM_CHCNR03_REG PcmChCNR03;
PCM_TSR03_REG PcmTSR03;
PCM_BSIZE03_REG PcmBSize03;
u32 abc;
u8 PcmIndex;
u8 PcmCh;
}HAL_PCM_ADAPTER, *PHAL_PCM_ADAPTER;
typedef struct _HAL_PCM_OP_ {
VOID (*HalPcmOnOff)(VOID *Data);
BOOL (*HalPcmInit)(VOID *Data);
BOOL (*HalPcmSetting)(VOID *Data);
BOOL (*HalPcmEn)(VOID *Data);
BOOL (*HalPcmIsrEnAndDis) (VOID *Data);
BOOL (*HalPcmDumpReg)(VOID *Data);
BOOL (*HalPcm)(VOID *Data);
}HAL_PCM_OP, *PHAL_PCM_OP;
VOID HalPcmOpInit(
IN VOID *Data
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PERI_ON_H_
#define _HAL_PERI_ON_H_
#define MASK_ALLON 0xFFFFFFFF
#define HAL_PERI_ON_READ32(addr) HAL_READ32(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE32(addr, value) HAL_WRITE32(PERI_ON_BASE, addr, value)
#define HAL_PERI_ON_READ16(addr) HAL_READ16(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE16(addr, value) HAL_WRITE16(PERI_ON_BASE, addr, value)
#define HAL_PERI_ON_READ8(addr) HAL_READ8(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE8(addr, value) HAL_WRITE8(PERI_ON_BASE, addr, value)
#define HAL_PERL_ON_FUNC_CTRL(addr,value,ctrl) \
HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~value))|((MASK_ALLON - ctrl + 1) & value)))
#define HAL_PERL_ON_PIN_SEL(addr,mask,value) \
HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~mask)) | value))
//40 REG_SYS_REGU_CTRL0
#define LDO25M_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_REGU_CTRL0, BIT_SYS_REGU_LDO25M_EN, ctrl)
//A0 SYS_DEBUG_CTRL
#define DEBUG_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_DEBUG_CTRL, BIT_SYS_DBG_PIN_EN, ctrl)
//A4 SYS_PINMUX_CTRL
#define SIC_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_SIC_PIN_EN, ctrl)
#define EEPROM_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_EEPROM_PIN_EN, ctrl)
//210 SOV_FUNC_EN
#define LXBUS_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LXBUS_EN, ctrl)
#define FLASH_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI_FLASH_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_FLASH_EN, ctrl);}
#define MEM_CTRL_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDR_SDRAM_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_MEM_CTRL_EN, ctrl);}
#define LOC_UART_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(LOG_UART_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LOG_UART_EN, ctrl);}
#define GDMA0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GDMA0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA0_EN, ctrl);}
#define GDMA1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GDMA1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA1_EN, ctrl);}
#define GTIMER_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(TIMER_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GTIMER_EN, ctrl);}
#define SECURITY_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(CRYPTO_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_SECURITY_ENGINE_EN, ctrl);}
//214 SOC_HCI_COM_FUNC_EN
#define SDIOD_ON_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_DEVICE_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN, ctrl);}
#define SDIOD_OFF_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_DEVICE_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN, ctrl);}
#define SDIOH_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_HOST_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN, ctrl);}
#define SDIO_ON_RST_MASK(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_RST_MUX, ctrl)
#define OTG_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(USB_OTG_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_EN, ctrl);}
#define OTG_RST_MASK(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_RST_MUX, ctrl)
#define MII_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(MII_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_MII_EN, ctrl);}
#define MII_MUX_SEL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SM_SEL, ctrl)
#define WL_MACON_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(WIFI_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_WL_MACON_EN, ctrl);}
//218 SOC_PERI_FUNC0_EN
#define UART0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART0_EN, ctrl);}
#define UART1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART1_EN, ctrl);}
#define UART2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART2_EN, ctrl);}
#define SPI0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI0_EN, ctrl);}
#define SPI1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI1_EN, ctrl);}
#define SPI2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI2_EN, ctrl);}
#define I2C0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C0_EN, ctrl);}
#define I2C1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C1_EN, ctrl);}
#define I2C2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C2_EN, ctrl);}
#define I2C3_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C3_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C3_EN, ctrl);}
#define I2S0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2S0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S0_EN, ctrl);}
#define I2S1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2S1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S1_EN, ctrl);}
#define PCM0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(PCM0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM0_EN, ctrl);}
#define PCM1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(PCM1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM1_EN, ctrl);}
//21C SOC_PERI_FUNC1_EN
#define ADC0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(ADC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_ADC0_EN, ctrl);}
#define DAC0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(DAC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC0_EN, ctrl);}
#define DAC1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(DAC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC1_EN, ctrl);}
#define GPIO_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GPIO_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_GPIO_EN, ctrl);}
//220 SOC_PERI_BD_FUNC0_EN
#define UART0_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART0_BD_EN, ctrl);}
#define UART1_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART1_BD_EN, ctrl);}
#define UART2_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART2_BD_EN, ctrl);}
//230 PESOC_CLK_CTRL
#define ACTCK_CPU_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_CKE_PLFM, ctrl)
#define ACTCK_TRACE_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TRACE_EN, ctrl)
#define SLPCK_TRACE_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TRACE_EN, ctrl)
#define ACTCK_VENDOR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_VENDOR_REG_EN, ctrl)
#define SLPCK_VENDOR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_VENDOR_REG_EN, ctrl)
#define ACTCK_FLASH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_FLASH_EN, ctrl)
#define SLPCK_FLASH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_FLASH_EN, ctrl)
#define ACTCK_SDR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_SDR_EN, ctrl)
#define SLPCK_SDR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_SDR_EN, ctrl)
#define ACTCK_LOG_UART_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_LOG_UART_EN, ctrl)
#define SLPCK_LOG_UART_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_LOG_UART_EN, ctrl)
#define ACTCK_TIMER_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TIMER_EN, ctrl)
#define SLPCK_TIMER_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TIMER_EN, ctrl)
#define ACTCK_GDMA0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA0_EN, ctrl)
#define SLPCK_GDMA0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA0_EN, ctrl)
#define ACTCK_GDMA1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA1_EN, ctrl)
#define SLPCK_GDMA1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA1_EN, ctrl)
#define ACTCK_GPIO_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GPIO_EN, ctrl)
#define SLPCK_GPIO_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GPIO_EN, ctrl)
#define ACTCK_BTCMD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_BTCMD_EN, ctrl)
#define SLPCK_BTCMD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_BTCMD_EN, ctrl)
//234 PESOC_PERI_CLK_CTRL0
#define ACTCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART0_EN, ctrl)
#define SLPCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART0_EN, ctrl)
#define ACTCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART1_EN, ctrl)
#define SLPCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART1_EN, ctrl)
#define ACTCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART2_EN, ctrl)
#define SLPCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART2_EN, ctrl)
#define ACTCK_SPI0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI0_EN, ctrl)
#define SLPCK_SPI0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI0_EN, ctrl)
#define ACTCK_SPI1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI1_EN, ctrl)
#define SLPCK_SPI1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI1_EN, ctrl)
#define ACTCK_SPI2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI2_EN, ctrl)
#define SLPCK_SPI2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI2_EN, ctrl)
//238 PESOC_PERI_CLK_CTRL1
#define ACTCK_I2C0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C0_EN, ctrl)
#define SLPCK_I2C0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C0_EN, ctrl)
#define ACTCK_I2C1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C1_EN, ctrl)
#define SLPCK_I2C1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C1_EN, ctrl)
#define ACTCK_I2C2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C2_EN, ctrl)
#define SLPCK_I2C2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C2_EN, ctrl)
#define ACTCK_I2C3_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C3_EN, ctrl)
#define SLPCK_I2C3_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C3_EN, ctrl)
#define ACTCK_I2S_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2S_EN, ctrl)
#define SLPCK_I2S_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2S_EN, ctrl)
#define ACTCK_PCM_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_PCM_EN, ctrl)
#define SLPCK_PCM_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_PCM_EN, ctrl)
#define ACTCK_ADC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_ADC_EN, ctrl)
#define SLPCK_ADC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_ADC_EN, ctrl)
#define ACTCK_DAC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_DAC_EN, ctrl)
#define SLPCK_DAC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_DAC_EN, ctrl)
//240 PESOC_HCI_CLK_CTRL0
#define ACTCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_DEV_EN, ctrl)
#define SLPCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_DEV_EN, ctrl)
#define ACTCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_HST_EN, ctrl)
#define SLPCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_HST_EN, ctrl)
#define ACTCK_OTG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_OTG_EN, ctrl)
#define SLPCK_OTG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_OTG_EN, ctrl)
#define ACTCK_MII_MPHY_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_MII_MPHY_EN, ctrl)
#define SLPCK_MII_MPHY_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_MII_MPHY_EN, ctrl)
//244 PESOC_COM_CLK_CTRL1
#define ACTCK_WL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_WL_EN, ctrl)
#define SLPCK_WL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_WL_EN, ctrl)
#define ACTCK_SEC_ENG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_SECURITY_ENG_EN, ctrl)
#define SLPCK_SEC_ENG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_SECURITY_ENG_EN, ctrl)
#define ACTCK_NFC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_NFC_EN, ctrl)
#define SLPCK_NFC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_NFC_EN, ctrl)
#define NFC_CAL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_NFC_CAL_EN, ctrl)
//250 REG_PERI_CLK_SEL
#define TRACE_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_TRACE_CK_SEL << BIT_SHIFT_PESOC_TRACE_CK_SEL), BIT_PESOC_TRACE_CK_SEL(num))
#define FLASH_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_FLASH_CK_SEL << BIT_SHIFT_PESOC_FLASH_CK_SEL), BIT_PESOC_FLASH_CK_SEL(num))
#define SDR_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_SDR_CK_SEL << BIT_SHIFT_PESOC_SDR_CK_SEL), BIT_PESOC_SDR_CK_SEL(num))
#define I2C_SCLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_PERI_SCLK_SEL << BIT_SHIFT_PESOC_PERI_SCLK_SEL), BIT_PESOC_PERI_SCLK_SEL(num))
//270 REG_OSC32K_CTRL
#define OSC32K_CKGEN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_OSC32K_CTRL, BIT_32K_POW_CKGEN_EN, ctrl)
//280 REG_UART_MUX_CTRL
#define UART0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART0_PIN_EN, ctrl)
#define UART0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART0_PIN_SEL << BIT_SHIFT_UART0_PIN_SEL), BIT_UART0_PIN_SEL(num))
#define UART1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART1_PIN_EN, ctrl)
#define UART1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART1_PIN_SEL << BIT_SHIFT_UART1_PIN_SEL), BIT_UART1_PIN_SEL(num))
#define UART2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART2_PIN_EN, ctrl)
#define UART2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART2_PIN_SEL << BIT_SHIFT_UART2_PIN_SEL), BIT_UART2_PIN_SEL(num))
//284 REG_SPI_MUX_CTRL
#define SPI0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_PIN_EN, ctrl)
#define SPI0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI0_PIN_SEL << BIT_SHIFT_SPI0_PIN_SEL), BIT_SPI0_PIN_SEL(num))
#define SPI1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI1_PIN_EN, ctrl)
#define SPI1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI1_PIN_SEL << BIT_SHIFT_SPI1_PIN_SEL), BIT_SPI1_PIN_SEL(num))
#define SPI2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI2_PIN_EN, ctrl)
#define SPI2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI2_PIN_SEL << BIT_SHIFT_SPI2_PIN_SEL), BIT_SPI2_PIN_SEL(num))
#define SPI0_MULTI_CS_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_MULTI_CS_EN, ctrl)
//288 REG_I2C_MUX_CTRL
#define I2C0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C0_PIN_EN, ctrl)
#define I2C0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C0_PIN_SEL << BIT_SHIFT_I2C0_PIN_SEL), BIT_I2C0_PIN_SEL(num))
#define I2C1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C1_PIN_EN, ctrl)
#define I2C1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C1_PIN_SEL << BIT_SHIFT_I2C1_PIN_SEL), BIT_I2C1_PIN_SEL(num))
#define I2C2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C2_PIN_EN, ctrl)
#define I2C2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C2_PIN_SEL << BIT_SHIFT_I2C2_PIN_SEL), BIT_I2C2_PIN_SEL(num))
#define I2C3_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C3_PIN_EN, ctrl)
#define I2C3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C3_PIN_SEL << BIT_SHIFT_I2C3_PIN_SEL), BIT_I2C3_PIN_SEL(num))
//28C REG_I2S_MUX_CTRL
#define I2S0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_PIN_EN, ctrl)
#define I2S0_MCK_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_MCK_EN, ctrl)
#define I2S0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S0_PIN_SEL << BIT_SHIFT_I2S0_PIN_SEL), BIT_I2S0_PIN_SEL(num))
#define I2S1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_PIN_EN, ctrl)
#define I2S1_MCK_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_MCK_EN, ctrl)
#define I2S1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S1_PIN_SEL << BIT_SHIFT_I2S1_PIN_SEL), BIT_I2S1_PIN_SEL(num))
#define PCM0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM0_PIN_EN, ctrl)
#define PCM0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM0_PIN_SEL << BIT_SHIFT_PCM0_PIN_SEL), BIT_PCM0_PIN_SEL(num))
#define PCM1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM1_PIN_EN, ctrl)
#define PCM1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM1_PIN_SEL << BIT_SHIFT_PCM1_PIN_SEL), BIT_PCM1_PIN_SEL(num))
//2A0 HCI_PINMUX_CTRL
#define SDIOD_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN, ctrl)
#define SDIOH_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN, ctrl)
#define MII_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN, ctrl)
//2A4 WL_PINMUX_CTRL
#define LED_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_LED_PIN_EN, ctrl)
#define LED_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_WL_PINMUX_CTRL, (BIT_MASK_WL_LED_PIN_SEL << BIT_SHIFT_WL_LED_PIN_SEL), BIT_WL_LED_PIN_SEL(num))
#define ANT0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT0_PIN_EN, ctrl)
#define ANT1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT1_PIN_EN, ctrl)
#define BTCOEX_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCOEX_PIN_EN, ctrl)
#define BTCMD_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCMD_PIN_EN, ctrl)
#define NFC_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_NFC_PIN_EN, ctrl)
//2AC PWM_PINMUX_CTRL
#define PWM0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM0_PIN_EN, ctrl)
#define PWM0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM0_PIN_SEL << BIT_SHIFT_PWM0_PIN_SEL), BIT_PWM0_PIN_SEL(num))
#define PWM1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM1_PIN_EN, ctrl)
#define PWM1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM1_PIN_SEL << BIT_SHIFT_PWM1_PIN_SEL), BIT_PWM1_PIN_SEL(num))
#define PWM2_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM2_PIN_EN, ctrl)
#define PWM2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM2_PIN_SEL << BIT_SHIFT_PWM2_PIN_SEL), BIT_PWM2_PIN_SEL(num))
#define PWM3_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM3_PIN_EN, ctrl)
#define PWM3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM3_PIN_SEL << BIT_SHIFT_PWM3_PIN_SEL), BIT_PWM3_PIN_SEL(num))
#define ETE0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE0_PIN_EN, ctrl)
#define ETE0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE0_PIN_SEL << BIT_SHIFT_ETE0_PIN_SEL), BIT_ETE0_PIN_SEL(num))
#define ETE1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE1_PIN_EN, ctrl)
#define ETE1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE1_PIN_SEL << BIT_SHIFT_ETE1_PIN_SEL), BIT_ETE1_PIN_SEL(num))
#define ETE2_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE2_PIN_EN, ctrl)
#define ETE2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE2_PIN_SEL << BIT_SHIFT_ETE2_PIN_SEL), BIT_ETE2_PIN_SEL(num))
#define ETE3_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE3_PIN_EN, ctrl)
#define ETE3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE3_PIN_SEL << BIT_SHIFT_ETE3_PIN_SEL), BIT_ETE3_PIN_SEL(num))
//2C0 CPU_PERIPHERAL_CTRL
#define SPI_FLASH_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SPI_FLSH_PIN_EN, ctrl)
#define SPI_FLASH_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_CPU_PERIPHERAL_CTRL, (BIT_MASK_SPI_FLSH_PIN_SEL << BIT_SHIFT_SPI_FLSH_PIN_SEL), BIT_SPI_FLSH_PIN_SEL(num))
#define SDR_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SDR_PIN_EN, ctrl)
#define TRACE_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_TRACE_PIN_EN, ctrl)
#define LOG_UART_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_PIN_EN, ctrl)
#define LOG_UART_IR_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_IR_EN, ctrl)
//300 REG_PESOC_MEM_CTRL
#define SDR_DDL_FCTRL(ctrl) HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_SDR_DDL_CTRL << BIT_SHIFT_PESOC_SDR_DDL_CTRL), BIT_PESOC_SDR_DDL_CTRL(ctrl))
#define FLASH_DDL_FCTRL(ctrl) HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_FLASH_DDL_CTRL << BIT_SHIFT_PESOC_FLASH_DDL_CTRL), BIT_PESOC_FLASH_DDL_CTRL(ctrl))
//304 REG_PESOC_SOC_CTRL
#define SRAM_MUX_CFG(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_SRAM_MUX_CFG << BIT_SHIFT_PESOC_SRAM_MUX_CFG), BIT_PESOC_SRAM_MUX_CFG(num))
#define LX_WL_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_WL_SWAP_SEL, ctrl)
#define LX_MST_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_MST_SWAP_SEL, ctrl)
#define LX_SLV_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_SLV_SWAP_SEL, ctrl)
#define MII_LX_WRAPPER_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_WRAPPER_EN, ctrl)
#define MII_LX_MST_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_MST_SWAP_SEL, ctrl)
#define MII_LX_SLV_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_SLV_SWAP_SEL, ctrl)
#define GDMA_CFG(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_GDMA_CFG << BIT_SHIFT_PESOC_GDMA_CFG), BIT_PESOC_GDMA_CFG(num))
//308 PESOC_PERI_CTRL
#define SPI_RN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CTRL, BIT_SOC_FUNC_SPI_RN, ctrl)
//320 GPIO_SHTDN_CTRL
#define GPIO_GPA_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPA_SHTDN_N, ctrl)
#define GPIO_GPB_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPB_SHTDN_N, ctrl)
#define GPIO_GPC_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPC_SHTDN_N, ctrl)
#define GPIO_GPD_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPD_SHTDN_N, ctrl)
#define GPIO_GPE_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPE_SHTDN_N, ctrl)
#define GPIO_GPF_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPF_SHTDN_N, ctrl)
#define GPIO_GPG_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPG_SHTDN_N, ctrl)
#define GPIO_GPH_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPH_SHTDN_N, ctrl)
#define GPIO_GPI_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPI_SHTDN_N, ctrl)
#define GPIO_GPJ_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPJ_SHTDN_N, ctrl)
#define GPIO_GPK_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPK_SHTDN_N, ctrl)
//374
#define EGTIM_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PERI_EGTIM_CTRL, BIT_PERI_EGTIM_EN, ctrl)
#define EGTIM_RSIG_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_REF_SIG_SEL << BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL), BIT_PERI_EGTIM_REF_SIG_SEL(num))
#define EGTIME_PIN_G0_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP0_OPT_SEL(num))
#define EGTIME_PIN_G1_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP1_OPT_SEL(num))
#define EGTIME_PIN_G2_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP2_OPT_SEL(num))
#endif //_HAL_PERI_ON_H_

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#ifndef _HAL_PINMUX_
#define _HAL_PINMUX_
//Function Index
#define UART0 0
#define UART1 1
#define UART2 2
#define SPI0 8
#define SPI1 9
#define SPI2 10
#define SPI0_MCS 15
#define I2C0 16
#define I2C1 17
#define I2C2 18
#define I2C3 19
#define I2S0 24
#define I2S1 25
#define PCM0 28
#define PCM1 29
#define ADC0 32
#define DAC0 36
#define DAC1 37
#define SDIOD 64
#define SDIOH 65
#define USBOTG 66
#define MII 88
#define WL_LED 96
#define WL_ANT0 104
#define WL_ANT1 105
#define WL_BTCOEX 108
#define WL_BTCMD 109
#define NFC 112
#define PWM0 160
#define PWM1 161
#define PWM2 162
#define PWM3 163
#define ETE0 164
#define ETE1 165
#define ETE2 166
#define ETE3 167
#define EGTIM 168
#define SPI_FLASH 196
#define SDR 200
#define JTAG 216
#define TRACE 217
#define LOG_UART 220
#define LOG_UART_IR 221
#define SIC 224
#define EEPROM 225
#define DEBUG 226
//Location Index(Pin Mux Selection)
#define S0 0
#define S1 1
#define S2 2
#define S3 3
_LONG_CALL_ u8
HalPinCtrlRtl8195A(
IN u32 Function,
IN u32 PinLocation,
IN BOOL Operation);
#endif //_HAL_PINMUX_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PLATFORM_
#define _HAL_PLATFORM_
#define ROMVERSION 0x03
#define ROMINFORMATION (ROMVERSION)
#define SYSTEM_CLK PLATFORM_CLOCK
#define SDR_SDRAM_BASE 0x30000000
#define SYSTEM_CTRL_BASE 0x40000000
#define PERI_ON_BASE 0x40000000
#define VENDOR_REG_BASE 0x40002800
#define SPI_FLASH_BASE 0x98000000
#define SDR_CTRL_BASE 0x40005000
#define PERIPHERAL_IRQ_STATUS 0x04
#define PERIPHERAL_IRQ_MODE 0x08
#define PERIPHERAL_IRQ_EN 0x0C
#define LP_PERI_EXT_IRQ_STATUS 0x24
#define LP_PERI_EXT_IRQ_MODE 0x28
#define LP_PERI_EXT_IRQ_EN 0x2C
#define PERIPHERAL_IRQ_ALL_LEVEL 0
#define TIMER_CLK 32*1000
//3 Peripheral IP Base Address
#define GPIO_REG_BASE 0x40001000
#define TIMER_REG_BASE 0x40002000
#define NFC_INTERFACE_BASE 0x40002400
#define LOG_UART_REG_BASE 0x40003000
#define I2C2_REG_BASE 0x40003400
#define I2C3_REG_BASE 0x40003800
#define SPI_FLASH_CTRL_BASE 0x40006000
#define ADC_REG_BASE 0x40010000
#define DAC_REG_BASE 0x40011000
#define UART0_REG_BASE 0x40040000
#define UART1_REG_BASE 0x40040400
#define UART2_REG_BASE 0x40040800
#define SPI0_REG_BASE 0x40042000
#define SPI1_REG_BASE 0x40042400
#define SPI2_REG_BASE 0x40042800
#define I2C0_REG_BASE 0x40044000
#define I2C1_REG_BASE 0x40044400
#define SDIO_DEVICE_REG_BASE 0x40050000
#define MII_REG_BASE 0x40050000
#define SDIO_HOST_REG_BASE 0x40058000
#define GDMA0_REG_BASE 0x40060000
#define GDMA1_REG_BASE 0x40061000
#define I2S0_REG_BASE 0x40062000
#define I2S1_REG_BASE 0x40063000
#define PCM0_REG_BASE 0x40064000
#define PCM1_REG_BASE 0x40065000
#define CRYPTO_REG_BASE 0x40070000
#define WIFI_REG_BASE 0x40080000
#define USB_OTG_REG_BASE 0x400C0000
#define GDMA1_REG_OFF 0x1000
#define I2S1_REG_OFF 0x1000
#define PCM1_REG_OFF 0x1000
#define SSI_REG_OFF 0x400
#define RUART_REG_OFF 0x400
#define CPU_CLK_TYPE_NO 6
enum _BOOT_TYPE_ {
BOOT_FROM_FLASH = 0,
BOOT_FROM_SDIO = 1,
BOOT_FROM_USB = 2,
BOOT_FROM_RSVD = 3,
};
enum _EFUSE_CPU_CLK_ {
#if 1
CLK_200M = 0,
CLK_100M = 1,
CLK_50M = 2,
CLK_25M = 3,
CLK_12_5M = 4,
CLK_4M = 5,
#else
CLK_25M = 0,
CLK_200M = 1,
CLK_100M = 2,
CLK_50M = 3,
CLK_12_5M = 4,
CLK_4M = 5,
#endif
};
#endif //_HAL_PLATFORM_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PWM_H_
#define _HAL_PWM_H_
#define MAX_PWM_CTRL_PIN 4
// the minimum tick time for G-timer is 61 us (clock source = 32768Hz, reload value=1 and reload takes extra 1T)
//#define GTIMER_TICK_US 31 // micro-second, 1000000/32768 ~= 30.5
#define MIN_GTIMER_TIMEOUT 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
#define PWM_GTIMER_TICK_TIME 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
typedef struct _HAL_PWM_ADAPTER_ {
u8 pwm_id; // the PWM ID, 0~3
u8 sel; // PWM Pin selection, 0~3
u8 gtimer_id; // using G-Timer ID, there are 7 G-timer, but we prefer to use timer 3~6
u8 enable; // is enabled
// u32 timer_value; // the G-Timer auto-reload value, source clock is 32768Hz, reload will takes extra 1 tick. To set the time of a tick of PWM
u32 tick_time; // the tick time for the G-timer
u32 period; // the period of a PWM control cycle, in PWM tick
u32 pulsewidth; // the pulse width in a period of a PWM control cycle, in PWM tick. To control the ratio
// float duty_ratio; // the dyty ratio = pulswidth/period
}HAL_PWM_ADAPTER, *PHAL_PWM_ADAPTER;
extern HAL_Status
HAL_Pwm_Init(
u32 pwm_id,
u32 sel
);
extern void
HAL_Pwm_Enable(
u32 pwm_id
);
extern void
HAL_Pwm_Disable(
u32 pwm_id
);
extern void
HAL_Pwm_SetDuty(
u32 pwm_id,
u32 period,
u32 pulse_width
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SDIO_H_
#define _HAL_SDIO_H_
#include "rtl8195a_sdio.h"
#if !SDIO_BOOT_DRIVER
#include "mailbox.h"
#endif
#define PURE_SDIO_INIC 0 // is a pure SDIO iNIC device or a SDIO iNIC + peripheral device
#if SDIO_BOOT_DRIVER
typedef struct _HAL_SDIO_ADAPTER_ {
u8 *pTXBDAddr; /* The TX_BD start address */
PSDIO_TX_BD pTXBDAddrAligned; /* The TX_BD start address, it must be 4-bytes aligned */
PSDIO_TX_BD_HANDLE pTXBDHdl; /* point to the allocated memory for TX_BD Handle array */
u16 TXBDWPtr; /* The SDIO TX(Host->Device) BD local write index, different with HW maintained write Index. */
u16 TXBDRPtr; /* The SDIO TX(Host->Device) BD read index */
u16 TXBDRPtrReg; /* The SDIO TX(Host->Device) BD read index has been write to HW register */
u16 reserve1;
u8 *pRXBDAddr; /* The RX_BD start address */
PSDIO_RX_BD pRXBDAddrAligned; /* The RX_BD start address, it must be 8-bytes aligned */
PSDIO_RX_BD_HANDLE pRXBDHdl; /* point to the allocated memory for RX_BD Handle array */
u16 RXBDWPtr; /* The SDIO RX(Device->Host) BD write index */
u16 RXBDRPtr; /* The SDIO RX(Device->Host) BD local read index, different with HW maintained Read Index. */
u16 IntMask; /* The Interrupt Mask */
u16 IntStatus; /* The Interrupt Status */
u32 Events; /* The Event to the SDIO Task */
u32 EventSema; /* Semaphore for SDIO events, use to wakeup the SDIO task */
u8 CCPWM; /* the value write to register CCPWM, which will sync to Host HCPWM */
u8 reserve2;
u16 CCPWM2; /* the value write to register CCPWM2, which will sync to Host HCPWM2 */
s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize); /* to hook the WLan driver TX callback function to handle a Packet TX */
VOID *pTxCb_Adapter; /* a pointer will be used to call the TX Callback function,
which is from the TX CallBack function register */
s8 (*pTxCallback_Backup)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize); // Use to back up the registered TX Callback function, for MP/Normal mode switch
VOID *pTxCb_Adapter_Backup; // Backup the pTxCb_Adapter, for MP/Normal mode switch
_LIST FreeTxPktList; /* The list to queue free Tx packets handler */
_LIST RxPktList; /* The list to queue RX packets */
_LIST FreeRxPktList; /* The list to queue free Rx packets handler */
SDIO_TX_PACKET *pTxPktHandler; /* to store allocated TX Packet handler memory address */
SDIO_RX_PACKET *pRxPktHandler; /* to store allocated RX Packet handler memory address */
u32 RxInQCnt; /* The packet count for Rx In Queue */
u32 MemAllocCnt; // Memory allocated count, for debug only
u32 MAllocFailedCnt; // MemAlloc Failed count, for debugging
// VOID *pHalOp; /* point to HAL operation function table */
} HAL_SDIO_ADAPTER, *PHAL_SDIO_ADAPTER;
extern BOOL SDIO_Device_Init_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev
);
extern VOID SDIO_Device_DeInit_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev
);
extern VOID SDIO_Send_C2H_IOMsg_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 *C2HMsg
);
extern u8 SDIO_Send_C2H_PktMsg_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u8 *C2HMsg,
IN u16 MsgLen
);
extern VOID SDIO_Register_Tx_Callback_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize),
IN VOID *pAdapter
);
extern s8 SDIO_Rx_Callback_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN VOID *pData,
IN u16 Offset,
IN u16 Length,
IN u8 CmdType
);
#else // else of "#if SDIO_BOOT_DRIVER"
typedef struct _HAL_SDIO_ADAPTER_ {
// u8 *pTxBuff; /* point to the SDIO TX Buffer */
// u8 *pTxBuffAligned; /* point to the SDIO TX Buffer with 4-bytes aligned */
// u32 TXFifoRPtr; /* The SDIO TX(Host->Device) FIFO buffer read pointer */
u8 *pTXBDAddr; /* The TX_BD start address */
PSDIO_TX_BD pTXBDAddrAligned; /* The TX_BD start address, it must be 4-bytes aligned */
PSDIO_TX_BD_HANDLE pTXBDHdl; /* point to the allocated memory for TX_BD Handle array */
u16 TXBDWPtr; /* The SDIO TX(Host->Device) BD local write index, different with HW maintained write Index. */
u16 TXBDRPtr; /* The SDIO TX(Host->Device) BD read index */
u16 TXBDRPtrReg; /* The SDIO TX(Host->Device) BD read index has been write to HW register */
u8 *pRXBDAddr; /* The RX_BD start address */
PSDIO_RX_BD pRXBDAddrAligned; /* The RX_BD start address, it must be 8-bytes aligned */
PSDIO_RX_BD_HANDLE pRXBDHdl; /* point to the allocated memory for RX_BD Handle array */
u16 RXBDWPtr; /* The SDIO RX(Device->Host) BD write index */
u16 RXBDRPtr; /* The SDIO RX(Device->Host) BD local read index, different with HW maintained Read Index. */
u16 IntMask; /* The Interrupt Mask */
u16 IntStatus; /* The Interrupt Status */
u32 Events; /* The Event to the SDIO Task */
u8 CCPWM; /* the value write to register CCPWM, which will sync to Host HCPWM */
u8 reserve1;
u16 CCPWM2; /* the value write to register CCPWM2, which will sync to Host HCPWM2 */
u8 CRPWM; /* sync from Host HRPWM */
u8 reserve2;
u16 CRPWM2; /* sync from Host HRPWM2 */
#if !TASK_SCHEDULER_DISABLED
_Sema TxSema; /* Semaphore for SDIO TX, use to wakeup the SDIO TX task */
_Sema RxSema; /* Semaphore for SDIO RX, use to wakeup the SDIO RX task */
#else
u32 EventSema; /* Semaphore for SDIO events, use to wakeup the SDIO task */
#endif
s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize); /* to hook the WLan driver TX callback function to handle a Packet TX */
VOID *pTxCb_Adapter; /* a pointer will be used to call the TX Callback function,
which is from the TX CallBack function register */
s8 (*pTxCallback_Backup)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize); // Use to back up the registered TX Callback function, for MP/Normal mode switch
VOID *pTxCb_Adapter_Backup; // Backup the pTxCb_Adapter, for MP/Normal mode switch
#if (CONFIG_INIC_EN == 0)
_LIST FreeTxPktList; /* The list to queue free Tx packets handler */
SDIO_TX_PACKET *pTxPktHandler; /* to store allocated TX Packet handler memory address */
#endif
_LIST RxPktList; /* The list to queue RX packets */
_LIST FreeRxPktList; /* The list to queue free Rx packets handler */
// _LIST RecyclePktList; /* The list to queue packets handler to be recycled */
SDIO_RX_PACKET *pRxPktHandler; /* to store allocated RX Packet handler memory address */
_Mutex RxMutex; /* The Mutex to protect RxPktList */
u32 RxInQCnt; /* The packet count for Rx In Queue */
#if SDIO_DEBUG
_Mutex StatisticMutex; /* The Mutex to protect Statistic data */
u32 MemAllocCnt; // Memory allocated count, for debug only
u32 MAllocFailedCnt; // MemAlloc Failed count, for debugging
#endif
VOID *pHalOp; /* point to HAL operation function table */
RTL_MAILBOX *pMBox; /* the Mail box for other driver module can send message to SDIO driver */
#ifdef PLATFORM_FREERTOS
xTaskHandle xSDIOTxTaskHandle; /* The handle of the SDIO Task for TX, can be used to delte the task */
xTaskHandle xSDIORxTaskHandle; /* The handle of the SDIO Task speical for RX, can be used to delte the task */
#endif
u8 RxFifoBusy; /* is the RX BD fetch hardware busy */
#if SDIO_MP_MODE
#if !TASK_SCHEDULER_DISABLED
u32 MP_Events; /* The Event to the SDIO Task */
_Sema MP_EventSema; /* Semaphore for SDIO events, use to wakeup the SDIO task */
RTL_MAILBOX *pMP_MBox; /* the Mail box for communication with other driver module */
#ifdef PLATFORM_FREERTOS
xTaskHandle MP_TaskHandle; /* The handle of the MP loopback Task, can be used to delte the task */
#endif // end of "#ifdef PLATFORM_FREERTOS"
#endif // end of "#if !TASK_SCHEDULER_DISABLED"
// for MP mode
RTL_TIMER *pPeriodTimer; /* a timer to calculate throughput periodically */
u8 MP_ModeEn; /* is in MP mode */
u8 MP_LoopBackEn; /* is loop-back enabled */
u8 MP_ContinueTx; /* is continue TX test enabled */
u8 MP_ContinueRx; /* is continue RX test enabled */
u8 MP_ContinueRxMode; /* continue RX test mode: static RX Buf, Dyna-Allocate RX Buf, Pre-Allocate RX Buf */
u8 MP_CRxInfinite; /* is non-stop SDIO RX, no packet count limit */
u16 MP_CRxSize; /* SDIO RX test packet size */
u8 *pMP_CRxBuf; // the buffer for continye RX test
u32 MP_CRxPktCnt; /* SDIO RX test packet count */
u32 MP_CRxPktPendingCnt; /* SDIO RX test packet pening count */
u32 MP_TxPktCnt; /* SDIO TX packet count */
u32 MP_RxPktCnt; /* SDIO RX packet count */
u32 MP_TxByteCnt; /* SDIO TX Byte count */
u32 MP_RxByteCnt; /* SDIO RX Byte count */
u32 MP_TxDropCnt; /* SDIO TX Drop packet count */
u32 MP_RxDropCnt; /* SDIO RX Drop packet count */
u32 MP_TxPktCntInPeriod; /* SDIO TX packet count in a period */
u32 MP_RxPktCntInPeriod; /* SDIO RX packet count in a period */
u32 MP_TxByteCntInPeriod; /* SDIO TX Byte count in a period */
u32 MP_RxByteCntInPeriod; /* SDIO RX Byte count in a period */
u32 MP_TxAvgTPWin[SDIO_AVG_TP_WIN_SIZE]; /* a window of SDIO TX byte count history, for average throughput calculation */
u32 MP_RxAvgTPWin[SDIO_AVG_TP_WIN_SIZE]; /* a window of SDIO RX byte count history, for average throughput calculation */
u32 MP_TxAvgTPWinSum; /* The sum of all byte-count in the window */
u32 MP_RxAvgTPWinSum; /* The sum of all byte-count in the window */
u8 OldestTxAvgWinIdx; /* the index of the oldest TX byte count log */
u8 TxAvgWinCnt; /* the number of log in the Window */
u8 OldestRxAvgWinIdx; /* the index of the oldest RX byte count log */
u8 RxAvgWinCnt; /* the number of log in the Window */
_LIST MP_RxPktList; /* The list to queue RX packets, for MP loopback test */
#endif // end of '#if SDIO_MP_MODE'
} HAL_SDIO_ADAPTER, *PHAL_SDIO_ADAPTER;
#endif // end of "#else of "#if SDIO_BOOT_DRIVER""
typedef struct _HAL_SDIO_OP_ {
BOOL (*HalSdioDevInit)(PHAL_SDIO_ADAPTER pSDIODev);
VOID (*HalSdioDevDeInit)(PHAL_SDIO_ADAPTER pSDIODev);
VOID (*HalSdioSendC2HIOMsg)(PHAL_SDIO_ADAPTER pSDIODev, u32 *C2HMsg);
u8 (*HalSdioSendC2HPktMsg)(PHAL_SDIO_ADAPTER pSDIODev, u8 *C2HMsg, u16 MsgLen);
VOID (*HalSdioRegTxCallback)(PHAL_SDIO_ADAPTER pSDIODev,s8 (*CallbackFun)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize), VOID *pAdapter);
s8 (*HalSdioRxCallback)(PHAL_SDIO_ADAPTER pSDIODev, VOID *pData, u16 Offset, u16 PktSize, u8 CmdType);
#if SDIO_MP_MODE
VOID (*HalSdioDevMPApp)(PHAL_SDIO_ADAPTER pSDIODev, u16 argc, u8 *argv[]);
#endif
}HAL_SDIO_OP, *PHAL_SDIO_OP;
extern BOOL SDIO_Device_Init(
IN PHAL_SDIO_ADAPTER pSDIODev
);
extern VOID SDIO_Device_DeInit(
IN PHAL_SDIO_ADAPTER pSDIODev
);
extern VOID SDIO_Send_C2H_IOMsg(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 *C2HMsg
);
extern u8 SDIO_Send_C2H_PktMsg(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u8 *C2HMsg,
IN u16 MsgLen
);
extern VOID SDIO_Register_Tx_Callback(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize),
IN VOID *pAdapter
);
extern s8 SDIO_Rx_Callback(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN VOID *pData,
IN u16 Offset,
IN u16 Length,
IN u8 CmdType
);
#if SDIO_MP_MODE
extern VOID SDIO_DeviceMPApp(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u16 argc,
IN u8 *argv[]
);
#endif
extern PHAL_SDIO_ADAPTER pgSDIODev;
extern VOID HalSdioInit(VOID);
extern VOID HalSdioDeInit(VOID);
#endif // #ifndef _HAL_SDIO_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SDR_CONTROLLER_H_
#define _HAL_SDR_CONTROLLER_H_
typedef enum _DRAM_TYPE_ {
DRAM_DDR_1 = 1,
DRAM_DDR_2 = 2,
DRAM_DDR_3 = 3,
DRAM_DDR_4 = 4,
DRAM_SDR = 8
}DRAM_TYPE;
typedef enum _DRAM_COLADDR_WTH_ {
DRAM_COLADDR_8B = 0,
DRAM_COLADDR_9B = 1,
DRAM_COLADDR_10B = 2,
DRAM_COLADDR_11B = 3,
DRAM_COLADDR_12B = 4,
DRAM_COLADDR_13B = 5,
DRAM_COLADDR_14B = 6,
DRAM_COLADDR_15B = 7,
DRAM_COLADDR_16B = 8
}DRAM_COLADDR_WTH;
typedef enum _DRAM_BANK_SIZE_ {
DRAM_BANK_2 = 0,
DRAM_BANK_4 = 1,
DRAM_BANK_8 = 2
}DRAM_BANK_SIZE;
typedef enum _DRAM_DQ_WIDTH_ {
DRAM_DQ_16 = 0,
DRAM_DQ_32 = 1,
DRAM_HALF_DQ32 = 2
}DRAM_DQ_WIDTH;
typedef enum _MODE0_BST_LEN_ {
BST_LEN_4 = 0,
BST_LEN_FLY = 1,
BST_LEN_8 = 2
}MODE0_BST_LEN;
typedef enum _MODE0_BST_TYPE_ {
SENQUENTIAL = 0,
INTERLEAVE = 1
}MODE0_BST_TYPE;
typedef enum _DFI_RATIO_TYPE_ {
DFI_RATIO_1 = 0, // DFI= 1:1, or SDR
DFI_RATIO_2 = 1,
DFI_RATIO_4 = 2
}DFI_RATIO_TYPE;
typedef struct _DRAM_INFO_ {
DRAM_TYPE DeviceType;
DRAM_COLADDR_WTH ColAddrWth;
DRAM_BANK_SIZE Bank;
DRAM_DQ_WIDTH DqWidth;
}DRAM_INFO;
typedef struct _DRAM_MODE_REG_INFO_ {
MODE0_BST_LEN BstLen;
MODE0_BST_TYPE BstType;
//enum mode0_cas rd_cas;
u32 Mode0Cas;
u32 Mode0Wr;
u32 Mode1DllEnN;
u32 Mode1AllLat;
u32 Mode2Cwl;
}DRAM_MODE_REG_INFO;
typedef struct _DRAM_TIMING_INFO_ {
u32 TrfcPs;
u32 TrefiPs;
u32 WrMaxTck;
u32 TrcdPs;
u32 TrpPs;
u32 TrasPs;
u32 TrrdTck;
u32 TwrPs;
u32 TwtrTck;
//u32 TrtpPs;
u32 TmrdTck;
u32 TrtpTck;
u32 TccdTck;
u32 TrcPs;
}DRAM_TIMING_INFO;
typedef struct _DRAM_DEVICE_INFO_ {
DRAM_INFO *Dev;
DRAM_MODE_REG_INFO *ModeReg;
DRAM_TIMING_INFO *Timing;
u32 DdrPeriodPs;
DFI_RATIO_TYPE *DfiRate;
}DRAM_DEVICE_INFO;
//======================================================
//DRAM Info
#ifdef CONFIG_FPGA
#define DRAM_INFO_TYPE DRAM_SDR
#define DRAM_INFO_COL_ADDR_WTH DRAM_COLADDR_9B
#define DRAM_INFO_BANK_SZ DRAM_BANK_4
#define DRAM_INFO_DQ_WTH DRAM_DQ_16
#else
#define DRAM_INFO_TYPE DRAM_SDR
#define DRAM_INFO_COL_ADDR_WTH DRAM_COLADDR_8B
#define DRAM_INFO_BANK_SZ DRAM_BANK_2
#define DRAM_INFO_DQ_WTH DRAM_DQ_16
#endif
//======================================================
//DRAM Timing
#ifdef CONFIG_SDR_100MHZ
#define DRAM_TIMING_TCK 10000 //ps
#endif
#ifdef CONFIG_SDR_50MHZ
#define DRAM_TIMING_TCK 20000 //ps
#endif
#ifdef CONFIG_SDR_25MHZ
#define DRAM_TIMING_TCK 40000 //ps
#endif
#ifdef CONFIG_SDR_12_5MHZ
#define DRAM_TIMING_TCK 80000 //ps
#endif
#if 1
#define DRAM_TIMING_TREF 64000 //us
#define DRAM_ROW_NUM 8192 //depends on row bit number
#define DRAM_TIMING_TRFC 60000 //ps
#define DRAM_TIMING_TREFI ((u32)((DRAM_TIMING_TREF*1000)/DRAM_ROW_NUM)*1000) //ps
#define DRAM_TIMING_TWRMAXTCK 2 //tck
#define DRAM_TIMING_TRCD 15000 //ps
#define DRAM_TIMING_TRP 15000 //ps
#define DRAM_TIMING_TRAS 42000 //ps
#define DRAM_TIMING_TRRD 2 //tck
#define DRAM_TIMING_TWR ((u32)(DRAM_TIMING_TCK*2))
#define DRAM_TIMING_TWTR 0 //tck
#define DRAM_TIMING_TMRD 2 //tck
#define DRAM_TIMING_TRTP 0 //tck
#define DRAM_TIMING_TCCD 1 //tck
#define DRAM_TIMING_TRC 60000 //ps
#else
#define DRAM_TIMING_TREF 66000 //us
#define DRAM_ROW_NUM 8192 //depends on row bit number
#define DRAM_TIMING_TRFC 66000 //ps
#define DRAM_TIMING_TREFI 63999800
#define DRAM_TIMING_TWRMAXTCK 2 //tck
#define DRAM_TIMING_TRCD 15000 //ps
#define DRAM_TIMING_TRP 15000 //ps
#define DRAM_TIMING_TRAS 37000 //ps
#define DRAM_TIMING_TRRD 2 //tck
#define DRAM_TIMING_TWR 7000
#define DRAM_TIMING_TWTR 0 //tck
#define DRAM_TIMING_TMRD 2 //tck
#define DRAM_TIMING_TRTP 0 //tck
#define DRAM_TIMING_TCCD 1 //tck
#define DRAM_TIMING_TRC 60000 //ps
#endif
#define HAL_SDR_WRITE32(addr, value32) HAL_WRITE32(SDR_CTRL_BASE, addr, value32)
#define HAL_SDR_WRITE16(addr, value16) HAL_WRITE16(SDR_CTRL_BASE, addr, value16)
#define HAL_SDR_WRITE8(addr, value8) HAL_WRITE8(SDR_CTRL_BASE, addr, value8)
#define HAL_SDR_READ32(addr) HAL_READ32(SDR_CTRL_BASE, addr)
#define HAL_SDR_READ16(addr) HAL_READ16(SDR_CTRL_BASE, addr)
#define HAL_SDR_READ8(addr) HAL_READ8(SDR_CTRL_BASE, addr)
#define HAL_SDRAM_WRITE32(addr, value32) HAL_WRITE32(SDR_SDRAM_BASE, addr, value32)
#define HAL_SDRAM_WRITE16(addr, value16) HAL_WRITE16(SDR_SDRAM_BASE, addr, value16)
#define HAL_SDRAM_WRITE8(addr, value8) HAL_WRITE8(SDR_SDRAM_BASE, addr, value8)
#define HAL_SDRAM_READ32(addr) HAL_READ32(SDR_SDRAM_BASE, addr)
#define HAL_SDRAM_READ16(addr) HAL_READ16(SDR_SDRAM_BASE, addr)
#define HAL_SDRAM_READ8(addr) HAL_READ8(SDR_SDRAM_BASE, addr)
#endif // end of "#ifndef _HAL_SDR_CONTROLLER_H_"

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lib/fwlib/hal_soc_ps_monitor.h Normal file
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#ifndef _HAL_SOCPWR_
#define _HAL_SOCPWR_
#define MAX_BACKUP_SIZE 129
#define MAXFUNC 10
#define FSTREG 0xFF
#define REG_VDR_ANACK_CAL_CTRL 0xA0
#define PS_MASK 0xFFFFFFFF
//pwr state
#define HWACT 0
#define HWCG 1
#define HWINACT 2
#define UNDEF 3
#define ALLMET 0xff
//SLP
#define SLP_STIMER BIT0
#define SLP_GTIMER BIT1
#define SLP_GPIO BIT2
#define SLP_WL BIT3
#define SLP_NFC BIT4
#define SLP_SDIO BIT5
#define SLP_USB BIT6
#define SLP_TIMER33 BIT7
//DSTBY
#define DSTBY_STIMER BIT0
#define DSTBY_NFC BIT1
#define DSTBY_TIMER33 BIT2
#define DSTBY_GPIO BIT3
//DS wake event
#define DS_TIMER33 BIT0
#define DS_GPIO BIT1
enum power_state_idx{
ACT = 0,
WFE = 1,
WFI = 2,
SNOOZE = 3,
SLPCG = 4,
SLPPG = 5,
DSTBY = 6,
DSLP = 7,
INACT = 8,
MAXSTATE = 9
};
enum clk_idx{
ANACK = 0,
A33CK = 1,
};
typedef struct _power_state_{
u8 FuncIdx;
u8 PowerState;
}POWER_STATE, *pPOWER_STATE;
typedef struct _reg_power_state_{
u8 FuncIdx;
u8 PwrState;
}REG_POWER_STATE, *pPREG_POWER_STATE;
#if 0
typedef struct _power_state_{
u8 FuncIdx;
u8 PowerState;
u32 ReqDuration;
u32 RegCount;
u32 RemainDuration;
}POWER_STATE, *pPOWER_STATE;
typedef struct _reg_power_state_{
u8 FuncIdx;
u8 PwrState;
u32 ReqDuration;
//u8 StateIdx;
}REG_POWER_STATE, *pPREG_POWER_STATE;
#endif
typedef struct _power_mgn_{
u8 ActFuncCount;
POWER_STATE PwrState[MAXFUNC];
u8 CurrentState;
u8 SDREn;
u32 MSPbackup[MAX_BACKUP_SIZE];
u32 CPURegbackup[25];
u32 CPUPSP;
u32 WakeEventFlag;
BOOL SleepFlag;
//u32 CPUReg[13];
//u32 MSBackUp[128];
}Power_Mgn, *pPower_Mgn;
typedef struct _SYS_ADAPTER_ {
u8 function;
}SYS_ADAPTER, *PSYS_ADAPTER;
extern Power_Mgn PwrAdapter;
u8 ChangeSoCPwrState(
IN u8 RequestState,
IN u32 ReqCount
);
VOID PrintCPU(VOID);
void WakeFromSLPPG(void);
VOID SOCPSTestApp(VOID *Data);
__inline static VOID
CPURegBackUp(
VOID
)
{
#if defined (__ICCARM__)
// TODO: IAR has different way using assembly
#elif defined (__GNUC__)
//backup cpu reg
#if 0
asm volatile
(
"PUSH {PSR, PC, LR, R12,R3,R2,R1,R0}\n"
);
#endif
#if 0
asm volatile
(
"PUSH {r0,r1,r2,r3,r4}\n"
);
#endif
asm volatile
(
"MOV %0, r0\n"
:"=r"(PwrAdapter.CPURegbackup[0])
::"memory"
);
asm volatile
(
"MOV %0, r1\n"
:"=r"(PwrAdapter.CPURegbackup[1])
::"memory"
);
asm volatile
(
"MOV %0, r2\n"
:"=r"(PwrAdapter.CPURegbackup[2])
::"memory"
);
asm volatile
(
"MOV %0, r3\n"
:"=r"(PwrAdapter.CPURegbackup[3])
::"memory"
);
asm volatile
(
"MOV %0, r4\n"
:"=r"(PwrAdapter.CPURegbackup[4])
::"memory"
);
asm volatile
(
"MOV %0, r5\n"
:"=r"(PwrAdapter.CPURegbackup[5])
::"memory"
);
asm volatile
(
"MOV %0, r6\n"
:"=r"(PwrAdapter.CPURegbackup[6])
::"memory"
);
asm volatile
(
"MOV %0, r7\n"
:"=r"(PwrAdapter.CPURegbackup[7])
::"memory"
);
asm volatile
(
"MOV %0, r8\n"
:"=r"(PwrAdapter.CPURegbackup[8])
::"memory"
);
asm volatile
(
"MOV %0, r9\n"
:"=r"(PwrAdapter.CPURegbackup[9])
::"memory"
);
asm volatile
(
"MOV %0, r10\n"
:"=r"(PwrAdapter.CPURegbackup[10])
::"memory"
);
asm volatile
(
"MOV %0, r11\n"
:"=r"(PwrAdapter.CPURegbackup[11])
::"memory"
);
asm volatile
(
"MOV %0, r12\n"
:"=r"(PwrAdapter.CPURegbackup[12])
::"memory"
);
asm volatile
(
"MOV %0, r13\n"
:"=r"(PwrAdapter.CPURegbackup[13])
::"memory"
);
asm volatile
(
//"MOV %0, r14\n"
"LDR %0, =SLPPG_WAKEUP_POINT\n"
"ADD %0, #1\n"
:"=r"(PwrAdapter.CPURegbackup[14])
::"memory"
);
asm volatile
(
"LDR %0, =SLPPG_WAKEUP_POINT\n"
"ADD %0, #1\n"
:"=r"(PwrAdapter.CPURegbackup[15])
::"memory"
);
asm volatile
(
"MRS %0, PSR\n"
:"=r"(PwrAdapter.CPURegbackup[16])
::"memory"
);
#if 1
asm volatile
(
"mov %0, r13\n"
"MOV %1, PC\n"
"MRS %2, CONTROL\n"
"MRS %3, PSP\n"
"MRS %4, MSP\n"
:"=r"(PwrAdapter.CPURegbackup[24]),"=r"(PwrAdapter.CPURegbackup[23]),"=r"(PwrAdapter.CPURegbackup[22]),"=r"(PwrAdapter.CPURegbackup[21]),"=r"(PwrAdapter.CPURegbackup[20])
::"memory"
);
#endif
#ifdef CONFIG_SOC_PS_VERIFY
PrintCPU();
#endif //#ifdef CONFIG_SOC_PS_VERIFY
#endif //#elif defined (__GNUC__)
}
VOID RegPowerState(REG_POWER_STATE RegPwrState);
#endif //_HAL_SOCPWR_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SPIFLASH__
#define _HAL_SPIFLASH__
//======================================================
// Header files
#define SPIC_CALIBRATION_IN_NVM 1 // if store the SPIC calibration data in the NVM
#ifndef CONFIG_IMAGE_SEPARATE // Store SPIC Calibration only for seprated image
#undef SPIC_CALIBRATION_IN_NVM
#define SPIC_CALIBRATION_IN_NVM 0
#endif
//======================================================
// Definition
#define HAL_SPI_WRITE32(addr, value32) HAL_WRITE32(SPI_FLASH_CTRL_BASE, addr, value32)
#define HAL_SPI_WRITE16(addr, value16) HAL_WRITE16(SPI_FLASH_CTRL_BASE, addr, value16)
#define HAL_SPI_WRITE8(addr, value8) HAL_WRITE8(SPI_FLASH_CTRL_BASE, addr, value8)
#define HAL_SPI_READ32(addr) HAL_READ32(SPI_FLASH_CTRL_BASE, addr)
#define HAL_SPI_READ16(addr) HAL_READ16(SPI_FLASH_CTRL_BASE, addr)
#define HAL_SPI_READ8(addr) HAL_READ8(SPI_FLASH_CTRL_BASE, addr)
typedef struct _SPIC_PARA_MODE_ {
u8 Valid:1; // valid
u8 CpuClk:3; // CPU clock
u8 BitMode:2; // Bit mode
u8 Reserved:2; // reserved
} SPIC_PARA_MODE, *PSPIC_PARA_MODE;
typedef struct _SPIC_INIT_PARA_ {
u8 BaudRate;
u8 RdDummyCyle;
u8 DelayLine;
union {
u8 Rsvd;
u8 Valid;
SPIC_PARA_MODE Mode;
};
#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
u8 id[3];
u8 flashtype;
#endif
}SPIC_INIT_PARA, *PSPIC_INIT_PARA;
enum _SPIC_BIT_MODE_ {
SpicOneBitMode = 0,
SpicDualBitMode = 1,
SpicQuadBitMode = 2,
};
//======================================================
// Flash type used
#define FLASH_OTHERS 0
#define FLASH_MXIC 1
#define FLASH_WINBOND 2
#define FLASH_MICRON 3
#define FLASH_MXIC_MX25L4006E 1
#define FLASH_MXIC_MX25L8073E 0
// The below parts are based on the flash characteristics
//====== Flash Command Definition ======
#if FLASH_MXIC_MX25L4006E
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52)
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#elif FLASH_MXIC_MX25L8073E
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0x52 //Block Erase
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
#define FLASH_CMD_4PP 0x38 //quad page program
#define FLASH_CMD_FF 0xFF //Release Read Enhanced
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
#else
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0x52 //Block Erase
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
#define FLASH_CMD_4PP 0x38 //quad page program
#define FLASH_CMD_FF 0xFF //Release Read Enhanced
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
#endif //#if FLASH_MXIC_MX25L4006E
// ============================
// ===== Flash Parameter Definition =====
#if FLASH_MXIC_MX25L4006E
#define FLASH_RD_2IO_EN 0
#define FLASH_RD_2O_EN 1
#define FLASH_RD_4IO_EN 0
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 0
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 0
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x08
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_I)
#define FLASH_VLD_QUAD_CMDS (0)
#elif FLASH_MXIC_MX25L8073E //This flash model is just for prototype, if you want to use it,
//the code MUST be rechecked according to the flash spec.
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 0
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x08
#define FLASH_DM_CYCLE_2IO 0x04
#define FLASH_DM_CYCLE_4O 0x08
#define FLASH_DM_CYCLE_4IO 0x04
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
#else
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 0
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x08
#define FLASH_DM_CYCLE_2IO 0x04
#define FLASH_DM_CYCLE_4O 0x08
#define FLASH_DM_CYCLE_4IO 0x04
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
#endif
#if 0
//======================================================
// Function prototype
BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);
_LONG_CALL_
extern VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara);
// spi-flash controller initialization
_LONG_CALL_
extern VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode);
// wait sr[0] = 0, wait transmission done
_LONG_CALL_
extern VOID SpicWaitBusyDoneRtl8195A(VOID);
// wait spi-flash status register[0] = 0
//_LONG_CALL_
//extern VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara);
#endif
//======================================================
// ROM Function prototype
_LONG_CALL_ VOID SpiFlashAppV02(IN VOID *Data);
_LONG_CALL_ROM_ VOID SpicInitRtl8195AV02(IN u8 InitBaudRate,IN u8 SpicBitMode);
_LONG_CALL_ROM_ VOID SpicEraseFlashRtl8195AV02(VOID);
_LONG_CALL_ROM_ VOID SpicLoadInitParaFromClockRtl8195AV02(IN u8 CpuClkMode,IN u8 BaudRate,IN PSPIC_INIT_PARA pSpicInitPara);
VOID SpicBlockEraseFlashRtl8195A(IN u32 Address);
VOID SpicSectorEraseFlashRtl8195A(IN u32 Address);
VOID SpicDieEraseFlashRtl8195A(IN u32 Address);
VOID SpicWriteProtectFlashRtl8195A(IN u32 Protect);
VOID SpicWaitWipDoneRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicWaitOperationDoneRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicRxCmdRefinedRtl8195A(IN u8 cmd,IN SPIC_INIT_PARA SpicInitPara);
u8 SpicGetFlashStatusRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicInitRefinedRtl8195A(IN u8 InitBaudRate,IN u8 SpicBitMode);
u32 SpicWaitWipRtl8195A(VOID);
u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk);
VOID SpicDisableRtl8195A(VOID);
VOID SpicDeepPowerDownFlashRtl8195A(VOID);
VOID SpicUserProgramRtl8195A(IN u8 * data, IN SPIC_INIT_PARA SpicInitPara, IN u32 addr, IN u32 * LengthInfo);
#if SPIC_CALIBRATION_IN_NVM
VOID SpicNVMCalLoad(u8 BitMode, u8 CpuClk);
VOID SpicNVMCalLoadAll(void);
VOID SpicNVMCalStore(u8 BitMode, u8 CpuClk);
#endif // #if SPIC_CALIBRATION_IN_NVM
#endif //_HAL_SPIFLASH__

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SSI_H_
#define _HAL_SSI_H_
#include "rtl8195a_ssi.h"
/**
* LOG Configurations
*/
extern u32 SSI_DBG_CONFIG;
extern uint8_t SPI0_IS_AS_SLAVE;
#define SSI_DBG_ENTRANCE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENTRANCE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE ANSI_COLOR_GREEN __VA_ARGS__ ANSI_COLOR_RESET); \
}while(0)
#define SSI_DBG_INIT(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INIT_V(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_V)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INIT_VV(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_VV)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_PINMUX(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_PINMUX)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_ENDIS(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENDIS)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_V(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_V)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_HNDLR(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_HNDLR)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_READ(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_READ)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_WRITE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_WRITE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_STATUS(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_STATUS)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_FIFO(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_FIFO)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_READ(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_READ)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_WRITE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_WRITE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_SLV_CTRL(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_SLV_CTRL)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
typedef enum _SSI_DBG_TYPE_LIST_ {
DBG_TYPE_ENTRANCE = 1 << 0,
DBG_TYPE_INIT = 1 << 1,
DBG_TYPE_INIT_V = 1 << 2,
DBG_TYPE_INIT_VV = 1 << 3,
DBG_TYPE_PINMUX = 1 << 4,
DBG_TYPE_ENDIS = 1 << 5,
DBG_TYPE_INT = 1 << 6,
DBG_TYPE_INT_V = 1 << 7,
DBG_TYPE_INT_HNDLR = 1 << 8,
DBG_TYPE_INT_READ = 1 << 9,
DBG_TYPE_INT_WRITE = 1 << 10,
DBG_TYPE_STATUS = 1 << 11,
DBG_TYPE_FIFO = 1 << 12,
DBG_TYPE_READ = 1 << 13,
DBG_TYPE_WRITE = 1 << 14,
DBG_TYPE_SLV_CTRL = 1 << 15
} SSI_DBG_TYPE_LIST, *PSSI_DBG_TYPE_LIST;
typedef struct _SSI_DMA_CONFIG_ {
VOID *pHalGdmaOp;
VOID *pTxHalGdmaAdapter;
VOID *pRxHalGdmaAdapter;
u8 RxDmaBurstSize;
u8 TxDmaBurstSize;
u8 RxDmaEnable;
u8 TxDmaEnable;
IRQ_HANDLE RxGdmaIrqHandle;
IRQ_HANDLE TxGdmaIrqHandle;
}SSI_DMA_CONFIG, *PSSI_DMA_CONFIG;
/**
* DesignWare SSI Configurations
*/
typedef struct _HAL_SSI_ADAPTOR_ {
SSI_DMA_CONFIG DmaConfig;
IRQ_HANDLE IrqHandle;
//
VOID (*RxCompCallback)(VOID *Para);
VOID *RxCompCbPara;
VOID *RxData;
VOID (*TxCompCallback)(VOID *Para);
VOID *TxCompCbPara;
VOID *TxData;
u32 DmaRxDataLevel;
u32 DmaTxDataLevel;
u32 InterruptPriority;
u32 RxLength;
u32 RxLengthRemainder;
u32 RxThresholdLevel;
u32 TxLength;
u32 TxThresholdLevel;
u32 SlaveSelectEnable;
//
u16 ClockDivider;
u16 DataFrameNumber;
//
u8 ControlFrameSize;
u8 DataFrameFormat;
u8 DataFrameSize;
u8 DmaControl;
u8 Index;
u8 InterruptMask;
u8 MicrowireDirection;
u8 MicrowireHandshaking;
u8 MicrowireTransferMode;
u8 PinmuxSelect;
u8 Role;
u8 SclkPhase;
u8 SclkPolarity;
u8 SlaveOutputEnable;
u8 TransferMode;
u8 TransferMechanism;
// Extend
u32 Reserved1;
u8 DefaultRxThresholdLevel;
}HAL_SSI_ADAPTOR, *PHAL_SSI_ADAPTOR;
typedef struct _HAL_SSI_OP_{
HAL_Status (*HalSsiPinmuxEnable)(VOID *Adaptor);
HAL_Status (*HalSsiPinmuxDisable)(VOID *Adaptor);
HAL_Status (*HalSsiEnable)(VOID *Adaptor);
HAL_Status (*HalSsiDisable)(VOID *Adaptor);
HAL_Status (*HalSsiInit)(VOID *Adaptor);
HAL_Status (*HalSsiSetSclkPolarity)(VOID *Adaptor);
HAL_Status (*HalSsiSetSclkPhase)(VOID *Adaptor);
HAL_Status (*HalSsiWrite)(VOID *Adaptor, u32 value);
HAL_Status (*HalSsiLoadSetting)(VOID *Adaptor, VOID *Setting);
HAL_Status (*HalSsiSetInterruptMask)(VOID *Adaptor);
HAL_Status (*HalSsiSetDeviceRole)(VOID *Adaptor, u32 Role);
HAL_Status (*HalSsiInterruptEnable)(VOID *Adaptor);
HAL_Status (*HalSsiInterruptDisable)(VOID *Adaptor);
HAL_Status (*HalSsiReadInterrupt)(VOID *Adaptor, VOID *RxData, u32 Length);
HAL_Status (*HalSsiSetRxFifoThresholdLevel)(VOID *Adaptor);
HAL_Status (*HalSsiSetTxFifoThresholdLevel)(VOID *Adaptor);
HAL_Status (*HalSsiWriteInterrupt)(VOID *Adaptor, u8 *TxData, u32 Length);
HAL_Status (*HalSsiSetSlaveEnableRegister)(VOID *Adaptor, u32 SlaveIndex);
u32 (*HalSsiBusy)(VOID *Adaptor);
u32 (*HalSsiReadable)(VOID *Adaptor);
u32 (*HalSsiWriteable)(VOID *Adaptor);
u32 (*HalSsiGetInterruptMask)(VOID *Adaptor);
u32 (*HalSsiGetRxFifoLevel)(VOID *Adaptor);
u32 (*HalSsiGetTxFifoLevel)(VOID *Adaptor);
u32 (*HalSsiGetStatus)(VOID *Adaptor);
u32 (*HalSsiGetInterruptStatus)(VOID *Adaptor);
u32 (*HalSsiRead)(VOID *Adaptor);
u32 (*HalSsiGetRawInterruptStatus)(VOID *Adaptor);
u32 (*HalSsiGetSlaveEnableRegister)(VOID *Adaptor);
}HAL_SSI_OP, *PHAL_SSI_OP;
typedef struct _DW_SSI_DEFAULT_SETTING_ {
VOID (*RxCompCallback)(VOID *Para);
VOID *RxCompCbPara;
VOID *RxData;
VOID (*TxCompCallback)(VOID *Para);
VOID *TxCompCbPara;
VOID *TxData;
u32 DmaRxDataLevel;
u32 DmaTxDataLevel;
u32 InterruptPriority;
u32 RxLength;
u32 RxLengthRemainder;
u32 RxThresholdLevel;
u32 TxLength;
u32 TxThresholdLevel;
u32 SlaveSelectEnable;
//
u16 ClockDivider;
u16 DataFrameNumber;
//
u8 ControlFrameSize;
u8 DataFrameFormat;
u8 DataFrameSize;
u8 DmaControl;
//u8 Index;
u8 InterruptMask;
u8 MicrowireDirection;
u8 MicrowireHandshaking;
u8 MicrowireTransferMode;
//u8 PinmuxSelect;
//u8 Role;
u8 SclkPhase;
u8 SclkPolarity;
u8 SlaveOutputEnable;
u8 TransferMode;
u8 TransferMechanism;
} DW_SSI_DEFAULT_SETTING, *PDW_SSI_DEFAULT_SETTING;
struct spi_s {
HAL_SSI_ADAPTOR spi_adp;
HAL_SSI_OP spi_op;
u32 irq_handler;
u32 irq_id;
u32 dma_en;
u32 state;
u8 sclk;
#ifdef CONFIG_GDMA_EN
HAL_GDMA_ADAPTER spi_gdma_adp_tx;
HAL_GDMA_ADAPTER spi_gdma_adp_rx;
#endif
};
VOID HalSsiOpInit(VOID *Adaptor);
static __inline__ VOID HalSsiSetSclk(
IN PHAL_SSI_ADAPTOR pHalSsiAdapter,
IN u32 ClkRate)
{
HalSsiSetSclkRtl8195a((VOID*)pHalSsiAdapter, ClkRate);
}
HAL_Status HalSsiInit(VOID * Data);
HAL_Status HalSsiDeInit(VOID * Data);
HAL_Status HalSsiEnable(VOID * Data);
HAL_Status HalSsiDisable(VOID * Data);
#ifdef CONFIG_GDMA_EN
HAL_Status HalSsiTxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
VOID HalSsiTxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
HAL_Status HalSsiRxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
VOID HalSsiRxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
static __inline__ VOID
HalSsiDmaInit(
IN PHAL_SSI_ADAPTOR pHalSsiAdapter
)
{
HalSsiDmaInitRtl8195a((void *)pHalSsiAdapter);
}
static __inline__ HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length)
{
return (HalSsiDmaSendRtl8195a(Adapter, pTxData, Length));
}
static __inline__ HAL_Status HalSsiDmaRecv(VOID *Adapter, u8 *pRxData, u32 Length)
{
return (HalSsiDmaRecvRtl8195a(Adapter, pRxData, Length));
}
#endif // end of "#ifdef CONFIG_GDMA_EN"
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_TIMER_H_
#define _HAL_TIMER_H_
#include "basic_types.h"
#include "hal_platform.h"
#include "hal_irqn.h"
#include "rtl8195a/rtl8195a_timer.h"
#define GTIMER_CLK_HZ (32768)
#define GTIMER_TICK_US (1000000/GTIMER_CLK_HZ)
typedef enum _TIMER_MODE_ {
FREE_RUN_MODE = 0,
USER_DEFINED = 1
}TIMER_MODE, *PTIMER_MODE;
typedef struct _TIMER_ADAPTER_ {
u32 TimerLoadValueUs;
u32 TimerIrqPriority;
TIMER_MODE TimerMode;
IRQ_HANDLE IrqHandle;
u8 TimerId;
u8 IrqDis;
}TIMER_ADAPTER, *PTIMER_ADAPTER;
typedef struct _HAL_TIMER_OP_ {
u32 (*HalGetTimerId)(u32 *TimerId);
BOOL (*HalTimerInit)(VOID *Data);
u32 (*HalTimerReadCount)(u32 TimerId);
VOID (*HalTimerIrqClear)(u32 TimerId);
VOID (*HalTimerDis)(u32 TimerId);
VOID (*HalTimerEn)(u32 TimerId);
VOID (*HalTimerDumpReg)(u32 TimerId);
}HAL_TIMER_OP, *PHAL_TIMER_OP;
VOID HalTimerOpInit_Patch(
IN VOID *Data
);
//======================================================
// ROM Function prototype
_LONG_CALL_ VOID HalTimerOpInitV02(IN VOID *Data);
//#define HalTimerOpInit HalTimerOpInit_Patch
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_UART_H_
#define _HAL_UART_H_
#include "rtl8195a_uart.h"
/**
* RUART Configurations
*/
#define UART_WAIT_FOREVER 0xffffffff
typedef struct _UART_DMA_CONFIG_ {
u8 TxDmaEnable;
u8 RxDmaEnable;
u8 TxDmaBurstSize;
u8 RxDmaBurstSize;
VOID *pHalGdmaOp;
VOID *pTxHalGdmaAdapter;
VOID *pRxHalGdmaAdapter;
IRQ_HANDLE TxGdmaIrqHandle;
IRQ_HANDLE RxGdmaIrqHandle;
}UART_DMA_CONFIG, *PUART_DMA_CONFIG;
typedef struct _HAL_RUART_ADAPTER_ {
u32 BaudRate;
u32 FlowControl;
u32 FifoControl;
u32 Interrupts;
u32 TxCount; // how many byte to TX
u32 RxCount; // how many bytes to RX
u8 *pTxBuf;
u8 *pRxBuf;
HAL_UART_State State; // UART state
u8 Status; // Transfer Status
u8 Locked; // is UART locked for operation
u8 UartIndex;
u8 WordLen; // word length select: 0 -> 7 bits, 1 -> 8 bits
u8 StopBit; // word length select: 0 -> 1 stop bit, 1 -> 2 stop bit
u8 Parity; // parity check enable
u8 ParityType; // parity check type
u8 StickParity;
u8 ModemStatus; // the modem status
u8 DmaEnable;
u8 TestCaseNumber;
u8 PinmuxSelect;
BOOL PullMode;
IRQ_HANDLE IrqHandle;
PUART_DMA_CONFIG DmaConfig;
VOID (*ModemStatusInd)(VOID *pAdapter); // modem status indication interrupt handler
VOID (*TxTDCallback)(VOID *pAdapter); // User Tx Done callback function
VOID (*RxDRCallback)(VOID *pAdapter); // User Rx Data ready callback function
VOID (*TxCompCallback)(VOID *para); // User Tx complete callback function
VOID (*RxCompCallback)(VOID *para); // User Rx complete callback function
VOID *TxTDCbPara; // the pointer agrument for TxTDCallback
VOID *RxDRCbPara; // the pointer agrument for RxDRCallback
VOID *TxCompCbPara; // the pointer argument for TxCompCbPara
VOID *RxCompCbPara; // the pointer argument for RxCompCallback
VOID (*EnterCritical)(void);
VOID (*ExitCritical)(void);
//1 New member only can be added below: members above must be fixed for ROM code
u32 *pDefaultBaudRateTbl; // point to the table of pre-defined baud rate
u8 *pDefaultOvsrRTbl; // point to the table of OVSR for pre-defined baud rate
u16 *pDefaultDivTbl; // point to the table of DIV for pre-defined baud rate
u8 *pDefOvsrAdjBitTbl_10; // point to the table of OVSR-Adj bits for 10 bits
u8 *pDefOvsrAdjBitTbl_9; // point to the table of OVSR-Adj bits for 9 bits
u8 *pDefOvsrAdjBitTbl_8; // point to the table of OVSR-Adj bits for 8 bits
u16 *pDefOvsrAdjTbl_10; // point to the table of OVSR-Adj for pre-defined baud rate
u16 *pDefOvsrAdjTbl_9; // point to the table of OVSR-Adj for pre-defined baud rate
u16 *pDefOvsrAdjTbl_8; // point to the table of OVSR-Adj for pre-defined baud rate
u32 BaudRateUsing; // Current using Baud-Rate
#if CONFIG_CHIP_E_CUT
u8 TxState;
u8 RxState;
u32 TxInitSize; // how many byte to TX at atart
u32 RxInitSize; // how many bytes to RX at start
VOID (*RuartEnterCritical)(VOID *para); // enter critical: disable UART interrupt
VOID (*RuartExitCritical)(VOID *para); // exit critical: re-enable UART interrupt
VOID (*TaskYield)(VOID *para); // User Task Yield: do a context switch while waitting
VOID *TaskYieldPara; // the agrument (pointer) for TaskYield
#endif // #if CONFIG_CHIP_E_CUT
}HAL_RUART_ADAPTER, *PHAL_RUART_ADAPTER;
typedef struct _HAL_RUART_OP_ {
VOID (*HalRuartAdapterLoadDef)(VOID *pAdp, u8 UartIdx); // Load UART adapter default setting
VOID (*HalRuartTxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load TX GDMA default setting
VOID (*HalRuartRxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load RX GDMA default setting
HAL_Status (*HalRuartResetRxFifo)(VOID *Data);
HAL_Status (*HalRuartInit)(VOID *Data);
VOID (*HalRuartDeInit)(VOID *Data);
HAL_Status (*HalRuartPutC)(VOID *Data, u8 TxData);
u32 (*HalRuartSend)(VOID *Data, u8 *pTxData, u32 Length, u32 Timeout);
HAL_Status (*HalRuartIntSend)(VOID *Data, u8 *pTxData, u32 Length);
HAL_Status (*HalRuartDmaSend)(VOID *Data, u8 *pTxData, u32 Length);
HAL_Status (*HalRuartStopSend)(VOID *Data);
HAL_Status (*HalRuartGetC)(VOID *Data, u8 *pRxByte);
u32 (*HalRuartRecv)(VOID *Data, u8 *pRxData, u32 Length, u32 Timeout);
HAL_Status (*HalRuartIntRecv)(VOID *Data, u8 *pRxData, u32 Length);
HAL_Status (*HalRuartDmaRecv)(VOID *Data, u8 *pRxData, u32 Length);
HAL_Status (*HalRuartStopRecv)(VOID *Data);
u8 (*HalRuartGetIMR)(VOID *Data);
VOID (*HalRuartSetIMR)(VOID *Data);
u32 (*HalRuartGetDebugValue)(VOID *Data, u32 DbgSel);
VOID (*HalRuartDmaInit)(VOID *Data);
VOID (*HalRuartRTSCtrl)(VOID *Data, BOOLEAN RtsCtrl);
VOID (*HalRuartRegIrq)(VOID *Data);
VOID (*HalRuartIntEnable)(VOID *Data);
VOID (*HalRuartIntDisable)(VOID *Data);
}HAL_RUART_OP, *PHAL_RUART_OP;
typedef struct _RUART_DATA_ {
PHAL_RUART_ADAPTER pHalRuartAdapter;
BOOL PullMode;
u8 BinaryData;
u8 SendBuffer;
u8 RecvBuffer;
}RUART_DATA, *PRUART_DATA;
typedef struct _RUART_ADAPTER_ {
PHAL_RUART_OP pHalRuartOp;
PHAL_RUART_ADAPTER pHalRuartAdapter;
PUART_DMA_CONFIG pHalRuartDmaCfg;
}RUART_ADAPTER, *PRUART_ADAPTER;
extern VOID
HalRuartOpInit(
IN VOID *Data
);
extern HAL_Status
HalRuartTxGdmaInit(
PHAL_RUART_OP pHalRuartOp,
PHAL_RUART_ADAPTER pHalRuartAdapter,
PUART_DMA_CONFIG pUartGdmaConfig
);
extern VOID
HalRuartTxGdmaDeInit(
PUART_DMA_CONFIG pUartGdmaConfig
);
extern HAL_Status
HalRuartRxGdmaInit(
PHAL_RUART_OP pHalRuartOp,
PHAL_RUART_ADAPTER pHalRuartAdapter,
PUART_DMA_CONFIG pUartGdmaConfig
);
extern VOID
HalRuartRxGdmaDeInit(
PUART_DMA_CONFIG pUartGdmaConfig
);
extern HAL_Status
HalRuartResetTxFifo(
VOID *Data
);
extern HAL_Status
HalRuartSetBaudRate(
IN VOID *Data
);
extern HAL_Status
HalRuartInit(
IN VOID *Data
);
extern VOID
HalRuartDeInit(
IN VOID *Data
);
extern HAL_Status
HalRuartDisable(
IN VOID *Data
);
extern HAL_Status
HalRuartEnable(
IN VOID *Data
);
HAL_Status
HalRuartFlowCtrl(
IN VOID *Data
);
extern const HAL_RUART_OP _HalRuartOp;
extern HAL_Status RuartLock (PHAL_RUART_ADAPTER pHalRuartAdapter);
extern VOID RuartUnLock (PHAL_RUART_ADAPTER pHalRuartAdapter);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_USB_H_
#define _HAL_USB_H_
#include "rtl8195a_usb.h"
#endif //_HAL_USB_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_UTIL_H_
#define _HAL_UTIL_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* Simple doubly linked list implementation.
*
* Some of the internal functions ("__xxx") are useful when
* manipulating whole lists rather than single entries, as
* sometimes we already know the next/prev entries and we can
* generate better code by using them directly rather than
* using the generic single-entry routines.
*/
struct LIST_HEADER {
struct LIST_HEADER *Next, *Prev;
};
typedef struct LIST_HEADER _LIST;
//#define RTL_LIST_HEAD_INIT(name) { &(name), &(name) }
#define RTL_INIT_LIST_HEAD(ptr) do { \
(ptr)->Next = (ptr); (ptr)->Prev = (ptr); \
} while (0)
/*
* Insert a new entry between two known consecutive entries.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static __inline__ VOID
__List_Add(
IN struct LIST_HEADER * New,
IN struct LIST_HEADER * Prev,
IN struct LIST_HEADER * Next
)
{
Next->Prev = New;
New->Next = Next;
New->Prev = Prev;
Prev->Next = New;
}
/*
* Delete a list entry by making the prev/next entries
* point to each other.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static __inline__ VOID
__List_Del(
IN struct LIST_HEADER * Prev,
IN struct LIST_HEADER * Next
)
{
Next->Prev = Prev;
Prev->Next = Next;
}
/**
* ListDel - deletes entry from list.
* @entry: the element to delete from the list.
* Note: list_empty on entry does not return true after this, the entry is in an undefined state.
*/
static __inline__ VOID
ListDel(
IN struct LIST_HEADER *Entry
)
{
__List_Del(Entry->Prev, Entry->Next);
}
/**
* ListDelInit - deletes entry from list and reinitialize it.
* @entry: the element to delete from the list.
*/
static __inline__ VOID
ListDelInit(
IN struct LIST_HEADER *Entry
)
{
__List_Del(Entry->Prev, Entry->Next);
RTL_INIT_LIST_HEAD(Entry);
}
/**
* ListEmpty - tests whether a list is empty
* @head: the list to test.
*/
static __inline__ u32
ListEmpty(
IN struct LIST_HEADER *Head
)
{
return Head->Next == Head;
}
/**
* ListSplice - join two lists
* @list: the new list to add.
* @head: the place to add it in the first list.
*/
static __inline__ VOID
ListSplice(
IN struct LIST_HEADER *List,
IN struct LIST_HEADER *Head
)
{
struct LIST_HEADER *First = List->Next;
if (First != List) {
struct LIST_HEADER *Last = List->Prev;
struct LIST_HEADER *At = Head->Next;
First->Prev = Head;
Head->Next = First;
Last->Next = At;
At->Prev = Last;
}
}
static __inline__ VOID
ListAdd(
IN struct LIST_HEADER *New,
IN struct LIST_HEADER *head
)
{
__List_Add(New, head, head->Next);
}
static __inline__ VOID
ListAddTail(
IN struct LIST_HEADER *New,
IN struct LIST_HEADER *head
)
{
__List_Add(New, head->Prev, head);
}
static __inline VOID
RtlInitListhead(
IN _LIST *list
)
{
RTL_INIT_LIST_HEAD(list);
}
/*
For the following list_xxx operations,
caller must guarantee the atomic context.
Otherwise, there will be racing condition.
*/
static __inline u32
RtlIsListEmpty(
IN _LIST *phead
)
{
if (ListEmpty(phead))
return _TRUE;
else
return _FALSE;
}
static __inline VOID
RtlListInsertHead(
IN _LIST *plist,
IN _LIST *phead
)
{
ListAdd(plist, phead);
}
static __inline VOID
RtlListInsertTail(
IN _LIST *plist,
IN _LIST *phead
)
{
ListAddTail(plist, phead);
}
static __inline _LIST
*RtlListGetNext(
IN _LIST *plist
)
{
return plist->Next;
}
static __inline VOID
RtlListDelete(
IN _LIST *plist
)
{
ListDelInit(plist);
}
#define RTL_LIST_CONTAINOR(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
#ifndef CONTAINER_OF
#define CONTAINER_OF(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
#endif
/*
#define list_entry(ptr, type, member) \
CONTAINER_OF(ptr, type, member)
#define list_first_entry(ptr, type, member) \
list_entry((ptr)->Next, type, member)
#define list_next_entry(pos, member, type) \
list_entry((pos)->member.Next, type, member)
#define list_for_each_entry(pos, head, member, type) \
for (pos = list_first_entry(head, type, member); \
&pos->member != (head); \
pos = list_next_entry(pos, member, type))
#define list_for_each(pos, head) \
for (pos = (head)->Next; pos != (head); pos = pos->Next)
*/
#ifndef BIT
#define BIT(x) ( 1 << (x))
#endif
#ifdef __cplusplus
}
#endif
#endif //_HAL_UTIL_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_VECTOR_TABLE_H_
#define _HAL_VECTOR_TABLE_H_
extern _LONG_CALL_ROM_ VOID
VectorTableInitRtl8195A(
IN u32 StackP
);
extern _LONG_CALL_ROM_ VOID
VectorTableInitForOSRtl8195A(
IN VOID *PortSVC,
IN VOID *PortPendSVH,
IN VOID *PortSysTick
);
extern _LONG_CALL_ROM_ BOOL
VectorIrqRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ BOOL
VectorIrqUnRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
VectorIrqEnRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
VectorIrqDisRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
HalPeripheralIntrHandle(VOID);
#endif //_HAL_VECTOR_TABLE_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_8195A_H_
#define _HAL_8195A_H_
#include "platform_autoconf.h"
#include "basic_types.h"
#include "section_config.h"
#include "rtl8195a_sys_on.h"
#include "rtl8195a_peri_on.h"
#include "hal_platform.h"
#include "hal_pinmux.h"
#include "hal_api.h"
#include "hal_peri_on.h"
#include "hal_misc.h"
#include "hal_irqn.h"
#include "hal_vector_table.h"
#include "hal_diag.h"
#include "hal_spi_flash.h"
#include "hal_timer.h"
#include "hal_util.h"
#include "hal_efuse.h"
#include "hal_soc_ps_monitor.h"
#include "diag.h"
#include "hal_common.h"
#include "hal_soc_ps_monitor.h"
/* ----------------------------------------------------------------------------
-- Cortex M3 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
* @{
*/
#define __CM3_REV 0x0200 /**< Core revision r0p0 */
#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 1 /**< Vendor specific implementation of SysTickConfig is defined */
#include "core_cm3.h"
#ifdef CONFIG_TIMER_EN
#include "hal_timer.h"
#endif
#ifdef CONFIG_GDMA_EN
#include "hal_gdma.h"
#include "rtl8195a_gdma.h"
#endif
#ifdef CONFIG_GPIO_EN
#include "hal_gpio.h"
#include "rtl8195a_gpio.h"
#endif
#ifdef CONFIG_SPI_COM_EN
#include "hal_ssi.h"
#include "rtl8195a_ssi.h"
#endif
#ifdef CONFIG_UART_EN
#include "hal_uart.h"
#include "rtl8195a_uart.h"
#endif
#ifdef CONFIG_I2C_EN
#include "hal_i2c.h"
#include "rtl8195a_i2c.h"
#endif
#ifdef CONFIG_PCM_EN
#include "hal_pcm.h"
#include "rtl8195a_pcm.h"
#endif
#ifdef CONFIG_PWM_EN
#include "hal_pwm.h"
#include "rtl8195a_pwm.h"
#endif
#ifdef CONFIG_I2S_EN
#include "hal_i2s.h"
#include "rtl8195a_i2s.h"
#endif
#ifdef CONFIG_DAC_EN
#include "hal_dac.h"
#include "rtl8195a_dac.h"
#endif
#include "hal_adc.h"
#include "rtl8195a_adc.h"
#ifdef CONFIG_SDR_EN
#endif
#ifdef CONFIG_SPIC_EN
#endif
#ifdef CONFIG_SDIO_DEVICE_EN
#include "hal_sdio.h"
#endif
#ifdef CONFIG_NFC_EN
#include "hal_nfc.h"
#include "rtl8195a_nfc.h"
#endif
#ifdef CONFIG_WDG
#include "rtl8195a_wdt.h"
#endif
#ifdef CONFIG_USB_EN
#include "hal_usb.h"
#include "rtl8195a_usb.h"
#endif
// firmware information, located at the header of Image2
#define FW_VERSION (0x0100)
#define FW_SUBVERSION (0x0001)
#define FW_CHIP_ID (0x8195)
#define FW_CHIP_VER (0x01)
#define FW_BUS_TYPE (0x01) // the iNIC firmware type: USB/SDIO
#define FW_INFO_RSV1 (0x00) // the firmware information reserved
#define FW_INFO_RSV2 (0x00) // the firmware information reserved
#define FW_INFO_RSV3 (0x00) // the firmware information reserved
#define FW_INFO_RSV4 (0x00) // the firmware information reserved
#define FLASH_RESERVED_DATA_BASE 0x8000 // reserve 32K for Image1
#define FLASH_SYSTEM_DATA_ADDR 0x9000 // reserve 32K+4K for Image1 + Reserved data
// Flash Map for Calibration data
#define FLASH_CAL_DATA_BASE 0xA000
#define FLASH_CAL_DATA_ADDR(_offset) (FLASH_CAL_DATA_BASE + _offset)
#define FLASH_CAL_DATA_SIZE 0x1000
#define FLASH_SECTOR_SIZE 0x1000
// SPIC Calibration Data
#define FLASH_SPIC_PARA_OFFSET 0x80
#define FLASH_SPIC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SPIC_PARA_OFFSET)
// SDRC Calibration Data
#define FLASH_SDRC_PARA_OFFSET 0x180
#define FLASH_SDRC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SDRC_PARA_OFFSET)
// ADC Calibration Data
#define FLASH_ADC_PARA_OFFSET 0x200
#define FLASH_ADC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_ADC_PARA_OFFSET)
#endif //_HAL_8195A_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_ADC_H_
#define _RTL8195A_ADC_H_
//================ Register Bit Field ==========================
//2 REG_ADC_FIFO_READ
#define BIT_SHIFT_ADC_FIFO_RO 0
#define BIT_MASK_ADC_FIFO_RO 0xffffffffL
#define BIT_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
#define BIT_CTRL_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
#define BIT_GET_ADC_FIFO_RO(x) (((x) >> BIT_SHIFT_ADC_FIFO_RO) & BIT_MASK_ADC_FIFO_RO)
//2 REG_ADC_CONTROL
#define BIT_SHIFT_ADC_DBG_SEL 24
#define BIT_MASK_ADC_DBG_SEL 0x7
#define BIT_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
#define BIT_CTRL_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
#define BIT_GET_ADC_DBG_SEL(x) (((x) >> BIT_SHIFT_ADC_DBG_SEL) & BIT_MASK_ADC_DBG_SEL)
#define BIT_SHIFT_ADC_THRESHOLD 16
#define BIT_MASK_ADC_THRESHOLD 0x3f
#define BIT_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
#define BIT_CTRL_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
#define BIT_GET_ADC_THRESHOLD(x) (((x) >> BIT_SHIFT_ADC_THRESHOLD) & BIT_MASK_ADC_THRESHOLD)
#define BIT_SHIFT_ADC_BURST_SIZE 8
#define BIT_MASK_ADC_BURST_SIZE 0x1f
#define BIT_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
#define BIT_CTRL_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
#define BIT_GET_ADC_BURST_SIZE(x) (((x) >> BIT_SHIFT_ADC_BURST_SIZE) & BIT_MASK_ADC_BURST_SIZE)
#define BIT_ADC_ENDIAN BIT(3)
#define BIT_SHIFT_ADC_ENDIAN 3
#define BIT_MASK_ADC_ENDIAN 0x1
#define BIT_CTRL_ADC_ENDIAN(x) (((x) & BIT_MASK_ADC_ENDIAN) << BIT_SHIFT_ADC_ENDIAN)
#define BIT_ADC_OVERWRITE BIT(2)
#define BIT_SHIFT_ADC_OVERWRITE 2
#define BIT_MASK_ADC_OVERWRITE 0x1
#define BIT_CTRL_ADC_OVERWRITE(x) (((x) & BIT_MASK_ADC_OVERWRITE) << BIT_SHIFT_ADC_OVERWRITE)
#define BIT_ADC_ONESHOT BIT(1)
#define BIT_SHIFT_ADC_ONESHOT 1
#define BIT_MASK_ADC_ONESHOT 0x1
#define BIT_CTRL_ADC_ONESHOT(x) (((x) & BIT_MASK_ADC_ONESHOT) << BIT_SHIFT_ADC_ONESHOT)
#define BIT_ADC_COMP_ONLY BIT(0)
#define BIT_SHIFT_ADC_COMP_ONLY 0
#define BIT_MASK_ADC_COMP_ONLY 0x1
#define BIT_CTRL_ADC_COMP_ONLY(x) (((x) & BIT_MASK_ADC_COMP_ONLY) << BIT_SHIFT_ADC_COMP_ONLY)
//2 REG_ADC_INTR_EN
#define BIT_ADC_AWAKE_CPU_EN BIT(7)
#define BIT_SHIFT_ADC_AWAKE_CPU_EN 7
#define BIT_MASK_ADC_AWAKE_CPU_EN 0x1
#define BIT_CTRL_ADC_AWAKE_CPU_EN(x) (((x) & BIT_MASK_ADC_AWAKE_CPU_EN) << BIT_SHIFT_ADC_AWAKE_CPU_EN)
#define BIT_ADC_FIFO_RD_ERROR_EN BIT(6)
#define BIT_SHIFT_ADC_FIFO_RD_ERROR_EN 6
#define BIT_MASK_ADC_FIFO_RD_ERROR_EN 0x1
#define BIT_CTRL_ADC_FIFO_RD_ERROR_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_EN) << BIT_SHIFT_ADC_FIFO_RD_ERROR_EN)
#define BIT_ADC_FIFO_RD_REQ_EN BIT(5)
#define BIT_SHIFT_ADC_FIFO_RD_REQ_EN 5
#define BIT_MASK_ADC_FIFO_RD_REQ_EN 0x1
#define BIT_CTRL_ADC_FIFO_RD_REQ_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_EN) << BIT_SHIFT_ADC_FIFO_RD_REQ_EN)
#define BIT_ADC_FIFO_FULL_EN BIT(4)
#define BIT_SHIFT_ADC_FIFO_FULL_EN 4
#define BIT_MASK_ADC_FIFO_FULL_EN 0x1
#define BIT_CTRL_ADC_FIFO_FULL_EN(x) (((x) & BIT_MASK_ADC_FIFO_FULL_EN) << BIT_SHIFT_ADC_FIFO_FULL_EN)
#define BIT_ADC_COMP_3_EN BIT(3)
#define BIT_SHIFT_ADC_COMP_3_EN 3
#define BIT_MASK_ADC_COMP_3_EN 0x1
#define BIT_CTRL_ADC_COMP_3_EN(x) (((x) & BIT_MASK_ADC_COMP_3_EN) << BIT_SHIFT_ADC_COMP_3_EN)
#define BIT_ADC_COMP_2_EN BIT(2)
#define BIT_SHIFT_ADC_COMP_2_EN 2
#define BIT_MASK_ADC_COMP_2_EN 0x1
#define BIT_CTRL_ADC_COMP_2_EN(x) (((x) & BIT_MASK_ADC_COMP_2_EN) << BIT_SHIFT_ADC_COMP_2_EN)
#define BIT_ADC_COMP_1_EN BIT(1)
#define BIT_SHIFT_ADC_COMP_1_EN 1
#define BIT_MASK_ADC_COMP_1_EN 0x1
#define BIT_CTRL_ADC_COMP_1_EN(x) (((x) & BIT_MASK_ADC_COMP_1_EN) << BIT_SHIFT_ADC_COMP_1_EN)
#define BIT_ADC_COMP_0_EN BIT(0)
#define BIT_SHIFT_ADC_COMP_0_EN 0
#define BIT_MASK_ADC_COMP_0_EN 0x1
#define BIT_CTRL_ADC_COMP_0_EN(x) (((x) & BIT_MASK_ADC_COMP_0_EN) << BIT_SHIFT_ADC_COMP_0_EN)
//2 REG_ADC_INTR_STS
#define BIT_ADC_FIFO_THRESHOLD BIT(7)
#define BIT_SHIFT_ADC_FIFO_THRESHOLD 7
#define BIT_MASK_ADC_FIFO_THRESHOLD 0x1
#define BIT_CTRL_ADC_FIFO_THRESHOLD(x) (((x) & BIT_MASK_ADC_FIFO_THRESHOLD) << BIT_SHIFT_ADC_FIFO_THRESHOLD)
#define BIT_ADC_FIFO_RD_ERROR_ST BIT(6)
#define BIT_SHIFT_ADC_FIFO_RD_ERROR_ST 6
#define BIT_MASK_ADC_FIFO_RD_ERROR_ST 0x1
#define BIT_CTRL_ADC_FIFO_RD_ERROR_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_ST) << BIT_SHIFT_ADC_FIFO_RD_ERROR_ST)
#define BIT_ADC_FIFO_RD_REQ_ST BIT(5)
#define BIT_SHIFT_ADC_FIFO_RD_REQ_ST 5
#define BIT_MASK_ADC_FIFO_RD_REQ_ST 0x1
#define BIT_CTRL_ADC_FIFO_RD_REQ_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_ST) << BIT_SHIFT_ADC_FIFO_RD_REQ_ST)
#define BIT_ADC_FIFO_FULL_ST BIT(4)
#define BIT_SHIFT_ADC_FIFO_FULL_ST 4
#define BIT_MASK_ADC_FIFO_FULL_ST 0x1
#define BIT_CTRL_ADC_FIFO_FULL_ST(x) (((x) & BIT_MASK_ADC_FIFO_FULL_ST) << BIT_SHIFT_ADC_FIFO_FULL_ST)
#define BIT_ADC_COMP_3_ST BIT(3)
#define BIT_SHIFT_ADC_COMP_3_ST 3
#define BIT_MASK_ADC_COMP_3_ST 0x1
#define BIT_CTRL_ADC_COMP_3_ST(x) (((x) & BIT_MASK_ADC_COMP_3_ST) << BIT_SHIFT_ADC_COMP_3_ST)
#define BIT_ADC_COMP_2_ST BIT(2)
#define BIT_SHIFT_ADC_COMP_2_ST 2
#define BIT_MASK_ADC_COMP_2_ST 0x1
#define BIT_CTRL_ADC_COMP_2_ST(x) (((x) & BIT_MASK_ADC_COMP_2_ST) << BIT_SHIFT_ADC_COMP_2_ST)
#define BIT_ADC_COMP_1_ST BIT(1)
#define BIT_SHIFT_ADC_COMP_1_ST 1
#define BIT_MASK_ADC_COMP_1_ST 0x1
#define BIT_CTRL_ADC_COMP_1_ST(x) (((x) & BIT_MASK_ADC_COMP_1_ST) << BIT_SHIFT_ADC_COMP_1_ST)
#define BIT_ADC_COMP_0_ST BIT(0)
#define BIT_SHIFT_ADC_COMP_0_ST 0
#define BIT_MASK_ADC_COMP_0_ST 0x1
#define BIT_CTRL_ADC_COMP_0_ST(x) (((x) & BIT_MASK_ADC_COMP_0_ST) << BIT_SHIFT_ADC_COMP_0_ST)
//2 REG_ADC_COMP_VALUE_L
#define BIT_SHIFT_ADC_COMP_TH_1 16
#define BIT_MASK_ADC_COMP_TH_1 0xffff
#define BIT_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
#define BIT_CTRL_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
#define BIT_GET_ADC_COMP_TH_1(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_1) & BIT_MASK_ADC_COMP_TH_1)
#define BIT_SHIFT_ADC_COMP_TH_0 0
#define BIT_MASK_ADC_COMP_TH_0 0xffff
#define BIT_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
#define BIT_CTRL_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
#define BIT_GET_ADC_COMP_TH_0(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_0) & BIT_MASK_ADC_COMP_TH_0)
//2 REG_ADC_COMP_VALUE_H
#define BIT_SHIFT_ADC_COMP_TH_3 16
#define BIT_MASK_ADC_COMP_TH_3 0xffff
#define BIT_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
#define BIT_CTRL_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
#define BIT_GET_ADC_COMP_TH_3(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_3) & BIT_MASK_ADC_COMP_TH_3)
#define BIT_SHIFT_ADC_COMP_TH_2 0
#define BIT_MASK_ADC_COMP_TH_2 0xffff
#define BIT_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
#define BIT_CTRL_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
#define BIT_GET_ADC_COMP_TH_2(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_2) & BIT_MASK_ADC_COMP_TH_2)
//2 REG_ADC_COMP_SET
#define BIT_SHIFT_ADC_GREATER_THAN 0
#define BIT_MASK_ADC_GREATER_THAN 0xf
#define BIT_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
#define BIT_CTRL_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
#define BIT_GET_ADC_GREATER_THAN(x) (((x) >> BIT_SHIFT_ADC_GREATER_THAN) & BIT_MASK_ADC_GREATER_THAN)
//2 REG_ADC_POWER
#define BIT_SHIFT_ADC_PWR_CUT_CNTR 16
#define BIT_MASK_ADC_PWR_CUT_CNTR 0xff
#define BIT_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
#define BIT_CTRL_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
#define BIT_GET_ADC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_ADC_PWR_CUT_CNTR) & BIT_MASK_ADC_PWR_CUT_CNTR)
#define BIT_ADC_FIFO_ON_ST BIT(11)
#define BIT_SHIFT_ADC_FIFO_ON_ST 11
#define BIT_MASK_ADC_FIFO_ON_ST 0x1
#define BIT_CTRL_ADC_FIFO_ON_ST(x) (((x) & BIT_MASK_ADC_FIFO_ON_ST) << BIT_SHIFT_ADC_FIFO_ON_ST)
#define BIT_ADC_ISO_ON_ST BIT(10)
#define BIT_SHIFT_ADC_ISO_ON_ST 10
#define BIT_MASK_ADC_ISO_ON_ST 0x1
#define BIT_CTRL_ADC_ISO_ON_ST(x) (((x) & BIT_MASK_ADC_ISO_ON_ST) << BIT_SHIFT_ADC_ISO_ON_ST)
#define BIT_ADC_PWR33_ON_ST BIT(9)
#define BIT_SHIFT_ADC_PWR33_ON_ST 9
#define BIT_MASK_ADC_PWR33_ON_ST 0x1
#define BIT_CTRL_ADC_PWR33_ON_ST(x) (((x) & BIT_MASK_ADC_PWR33_ON_ST) << BIT_SHIFT_ADC_PWR33_ON_ST)
#define BIT_ADC_PWR12_ON_ST BIT(8)
#define BIT_SHIFT_ADC_PWR12_ON_ST 8
#define BIT_MASK_ADC_PWR12_ON_ST 0x1
#define BIT_CTRL_ADC_PWR12_ON_ST(x) (((x) & BIT_MASK_ADC_PWR12_ON_ST) << BIT_SHIFT_ADC_PWR12_ON_ST)
#define BIT_ADC_ISO_MANUAL BIT(3)
#define BIT_SHIFT_ADC_ISO_MANUAL 3
#define BIT_MASK_ADC_ISO_MANUAL 0x1
#define BIT_CTRL_ADC_ISO_MANUAL(x) (((x) & BIT_MASK_ADC_ISO_MANUAL) << BIT_SHIFT_ADC_ISO_MANUAL)
#define BIT_ADC_PWR33_MANUAL BIT(2)
#define BIT_SHIFT_ADC_PWR33_MANUAL 2
#define BIT_MASK_ADC_PWR33_MANUAL 0x1
#define BIT_CTRL_ADC_PWR33_MANUAL(x) (((x) & BIT_MASK_ADC_PWR33_MANUAL) << BIT_SHIFT_ADC_PWR33_MANUAL)
#define BIT_ADC_PWR12_MANUAL BIT(1)
#define BIT_SHIFT_ADC_PWR12_MANUAL 1
#define BIT_MASK_ADC_PWR12_MANUAL 0x1
#define BIT_CTRL_ADC_PWR12_MANUAL(x) (((x) & BIT_MASK_ADC_PWR12_MANUAL) << BIT_SHIFT_ADC_PWR12_MANUAL)
#define BIT_ADC_PWR_AUTO BIT(0)
#define BIT_SHIFT_ADC_PWR_AUTO 0
#define BIT_MASK_ADC_PWR_AUTO 0x1
#define BIT_CTRL_ADC_PWR_AUTO(x) (((x) & BIT_MASK_ADC_PWR_AUTO) << BIT_SHIFT_ADC_PWR_AUTO)
//2 REG_ADC_ANAPAR_AD0
#define BIT_SHIFT_ADC_ANAPAR_AD0 2
#define BIT_MASK_ADC_ANAPAR_AD0 0x3fffffff
#define BIT_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
#define BIT_CTRL_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
#define BIT_GET_ADC_ANAPAR_AD0(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD0) & BIT_MASK_ADC_ANAPAR_AD0)
#define BIT_ADC_AUDIO_EN BIT(1)
#define BIT_SHIFT_ADC_AUDIO_EN 1
#define BIT_MASK_ADC_AUDIO_EN 0x1
#define BIT_CTRL_ADC_AUDIO_EN(x) (((x) & BIT_MASK_ADC_AUDIO_EN) << BIT_SHIFT_ADC_AUDIO_EN)
#define BIT_ADC_EN_MANUAL BIT(0)
#define BIT_SHIFT_ADC_EN_MANUAL 0
#define BIT_MASK_ADC_EN_MANUAL 0x1
#define BIT_CTRL_ADC_EN_MANUAL(x) (((x) & BIT_MASK_ADC_EN_MANUAL) << BIT_SHIFT_ADC_EN_MANUAL)
//2 REG_ADC_ANAPAR_AD1
#define BIT_SHIFT_ADC_ANAPAR_AD1 0
#define BIT_MASK_ADC_ANAPAR_AD1 0xffffffffL
#define BIT_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
#define BIT_CTRL_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
#define BIT_GET_ADC_ANAPAR_AD1(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD1) & BIT_MASK_ADC_ANAPAR_AD1)
//2 REG_ADC_ANAPAR_AD2
#define BIT_SHIFT_ADC_ANAPAR_AD2 0
#define BIT_MASK_ADC_ANAPAR_AD2 0xffffffffL
#define BIT_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
#define BIT_CTRL_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
#define BIT_GET_ADC_ANAPAR_AD2(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD2) & BIT_MASK_ADC_ANAPAR_AD2)
//2 REG_ADC_ANAPAR_AD3
#define BIT_SHIFT_ADC_ANAPAR_AD3 0
#define BIT_MASK_ADC_ANAPAR_AD3 0xffffffffL
#define BIT_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
#define BIT_CTRL_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
#define BIT_GET_ADC_ANAPAR_AD3(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD3) & BIT_MASK_ADC_ANAPAR_AD3)
//2 REG_ADC_ANAPAR_AD4
#define BIT_SHIFT_ADC_ANAPAR_AD4 0
#define BIT_MASK_ADC_ANAPAR_AD4 0xffffffffL
#define BIT_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
#define BIT_CTRL_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
#define BIT_GET_ADC_ANAPAR_AD4(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD4) & BIT_MASK_ADC_ANAPAR_AD4)
//2 REG_ADC_ANAPAR_AD5
#define BIT_SHIFT_ADC_ANAPAR_AD5 0
#define BIT_MASK_ADC_ANAPAR_AD5 0xffffffffL
#define BIT_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
#define BIT_CTRL_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
#define BIT_GET_ADC_ANAPAR_AD5(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD5) & BIT_MASK_ADC_ANAPAR_AD5)
//2 REG_ADC_CALI_DATA
#define BIT_SHIFT_ADC_CALI_DATA_6 16
#define BIT_MASK_ADC_CALI_DATA_6 0xffff
#define BIT_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
#define BIT_CTRL_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
#define BIT_GET_ADC_CALI_DATA_6(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_6) & BIT_MASK_ADC_CALI_DATA_6)
#define BIT_SHIFT_ADC_CALI_DATA_0 0
#define BIT_MASK_ADC_CALI_DATA_0 0xffff
#define BIT_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
#define BIT_CTRL_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
#define BIT_GET_ADC_CALI_DATA_0(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_0) & BIT_MASK_ADC_CALI_DATA_0)
//================ Register Reg Field =========================
#define REG_ADC_FIFO_READ 0x0000
#define REG_ADC_CONTROL 0x0004
#define REG_ADC_INTR_EN 0x0008
#define REG_ADC_INTR_STS 0x000C
#define REG_ADC_COMP_VALUE_L 0x0010
#define REG_ADC_COMP_VALUE_H 0x0014
#define REG_ADC_COMP_SET 0x0018
#define REG_ADC_POWER 0x001C
#define REG_ADC_ANAPAR_AD0 0x0020
#define REG_ADC_ANAPAR_AD1 0x0024
#define REG_ADC_ANAPAR_AD2 0x0028
#define REG_ADC_ANAPAR_AD3 0x002C
#define REG_ADC_ANAPAR_AD4 0x0030
#define REG_ADC_ANAPAR_AD5 0x0034
#define REG_ADC_CALI_DATA 0x0038
//================ ADC HAL related enumeration ==================
//================ ADC Function Prototypes =====================
#define HAL_ADC_WRITE32(addr, value) HAL_WRITE32(ADC_REG_BASE,addr,value)
#define HAL_ADC_READ32(addr) HAL_READ32(ADC_REG_BASE,addr)
RTK_STATUS HalADCInit8195a(IN VOID *Data);
RTK_STATUS HalADCDeInit8195a(IN VOID *Data);
RTK_STATUS HalADCEnableRtl8195a(IN VOID *Data);
RTK_STATUS HalADCIntrCtrl8195a(IN VOID *Data);
u32 HalADCReceiveRtl8195a(IN VOID *Data);
u32 HalADCReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg);
#endif

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lib/fwlib/rtl8195a/rtl8195a_dac.h Normal file
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#ifndef _RTL8195A_DAC_H_
#define _RTL8195A_DAC_H_
//================ Register Bit Field ==========================
//2 REG_DAC0_FIFO_WR
#define BIT_SHIFT_DAC0_FIFO_WO 0
#define BIT_MASK_DAC0_FIFO_WO 0xffffffffL
#define BIT_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
#define BIT_CTRL_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
#define BIT_GET_DAC0_FIFO_WO(x) (((x) >> BIT_SHIFT_DAC0_FIFO_WO) & BIT_MASK_DAC0_FIFO_WO)
//2 REG_DAC_CTRL
#define BIT_SHIFT_DAC_DELTA_SIGMA 25
#define BIT_MASK_DAC_DELTA_SIGMA 0x7
#define BIT_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
#define BIT_CTRL_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
#define BIT_GET_DAC_DELTA_SIGMA(x) (((x) >> BIT_SHIFT_DAC_DELTA_SIGMA) & BIT_MASK_DAC_DELTA_SIGMA)
#define BIT_DAC_BYPASS_DSC BIT(24)
#define BIT_SHIFT_DAC_BYPASS_DSC 24
#define BIT_MASK_DAC_BYPASS_DSC 0x1
#define BIT_CTRL_DAC_BYPASS_DSC(x) (((x) & BIT_MASK_DAC_BYPASS_DSC) << BIT_SHIFT_DAC_BYPASS_DSC)
#define BIT_SHIFT_DAC_DSC_DBG_SEL 19
#define BIT_MASK_DAC_DSC_DBG_SEL 0x3
#define BIT_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
#define BIT_CTRL_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
#define BIT_GET_DAC_DSC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DSC_DBG_SEL) & BIT_MASK_DAC_DSC_DBG_SEL)
#define BIT_SHIFT_DAC_DBG_SEL 16
#define BIT_MASK_DAC_DBG_SEL 0x7
#define BIT_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
#define BIT_CTRL_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
#define BIT_GET_DAC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DBG_SEL) & BIT_MASK_DAC_DBG_SEL)
#define BIT_SHIFT_DAC_BURST_SIZE 8
#define BIT_MASK_DAC_BURST_SIZE 0xf
#define BIT_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
#define BIT_CTRL_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
#define BIT_GET_DAC_BURST_SIZE(x) (((x) >> BIT_SHIFT_DAC_BURST_SIZE) & BIT_MASK_DAC_BURST_SIZE)
#define BIT_DAC_FILTER_SETTLE BIT(4)
#define BIT_SHIFT_DAC_FILTER_SETTLE 4
#define BIT_MASK_DAC_FILTER_SETTLE 0x1
#define BIT_CTRL_DAC_FILTER_SETTLE(x) (((x) & BIT_MASK_DAC_FILTER_SETTLE) << BIT_SHIFT_DAC_FILTER_SETTLE)
#define BIT_DAC_OV_OPTION BIT(3)
#define BIT_SHIFT_DAC_OV_OPTION 3
#define BIT_MASK_DAC_OV_OPTION 0x1
#define BIT_CTRL_DAC_OV_OPTION(x) (((x) & BIT_MASK_DAC_OV_OPTION) << BIT_SHIFT_DAC_OV_OPTION)
#define BIT_DAC_ENDIAN BIT(2)
#define BIT_SHIFT_DAC_ENDIAN 2
#define BIT_MASK_DAC_ENDIAN 0x1
#define BIT_CTRL_DAC_ENDIAN(x) (((x) & BIT_MASK_DAC_ENDIAN) << BIT_SHIFT_DAC_ENDIAN)
#define BIT_DAC_SPEED BIT(1)
#define BIT_SHIFT_DAC_SPEED 1
#define BIT_MASK_DAC_SPEED 0x1
#define BIT_CTRL_DAC_SPEED(x) (((x) & BIT_MASK_DAC_SPEED) << BIT_SHIFT_DAC_SPEED)
#define BIT_DAC_FIFO_EN BIT(0)
#define BIT_SHIFT_DAC_FIFO_EN 0
#define BIT_MASK_DAC_FIFO_EN 0x1
#define BIT_CTRL_DAC_FIFO_EN(x) (((x) & BIT_MASK_DAC_FIFO_EN) << BIT_SHIFT_DAC_FIFO_EN)
//2 REG_DAC_INTR_CTRL
#define BIT_DAC_DSC_OVERFLOW1_EN BIT(6)
#define BIT_SHIFT_DAC_DSC_OVERFLOW1_EN 6
#define BIT_MASK_DAC_DSC_OVERFLOW1_EN 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW1_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW1_EN)
#define BIT_DAC_DSC_OVERFLOW0_EN BIT(5)
#define BIT_SHIFT_DAC_DSC_OVERFLOW0_EN 5
#define BIT_MASK_DAC_DSC_OVERFLOW0_EN 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW0_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW0_EN)
#define BIT_DAC__WRITE_ERROR_EN BIT(4)
#define BIT_SHIFT_DAC__WRITE_ERROR_EN 4
#define BIT_MASK_DAC__WRITE_ERROR_EN 0x1
#define BIT_CTRL_DAC__WRITE_ERROR_EN(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_EN) << BIT_SHIFT_DAC__WRITE_ERROR_EN)
#define BIT_DAC_FIFO_STOP_EN BIT(3)
#define BIT_SHIFT_DAC_FIFO_STOP_EN 3
#define BIT_MASK_DAC_FIFO_STOP_EN 0x1
#define BIT_CTRL_DAC_FIFO_STOP_EN(x) (((x) & BIT_MASK_DAC_FIFO_STOP_EN) << BIT_SHIFT_DAC_FIFO_STOP_EN)
#define BIT_DAC_FIFO_OVERFLOW_EN BIT(2)
#define BIT_SHIFT_DAC_FIFO_OVERFLOW_EN 2
#define BIT_MASK_DAC_FIFO_OVERFLOW_EN 0x1
#define BIT_CTRL_DAC_FIFO_OVERFLOW_EN(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_EN) << BIT_SHIFT_DAC_FIFO_OVERFLOW_EN)
#define BIT_DAC_FIFO_WR_REQ_EN BIT(1)
#define BIT_SHIFT_DAC_FIFO_WR_REQ_EN 1
#define BIT_MASK_DAC_FIFO_WR_REQ_EN 0x1
#define BIT_CTRL_DAC_FIFO_WR_REQ_EN(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_EN) << BIT_SHIFT_DAC_FIFO_WR_REQ_EN)
#define BIT_DAC_FIFO_FULL_EN BIT(0)
#define BIT_SHIFT_DAC_FIFO_FULL_EN 0
#define BIT_MASK_DAC_FIFO_FULL_EN 0x1
#define BIT_CTRL_DAC_FIFO_FULL_EN(x) (((x) & BIT_MASK_DAC_FIFO_FULL_EN) << BIT_SHIFT_DAC_FIFO_FULL_EN)
//2 REG_DAC_INTR_STS
#define BIT_DAC_DSC_OVERFLOW1_ST BIT(6)
#define BIT_SHIFT_DAC_DSC_OVERFLOW1_ST 6
#define BIT_MASK_DAC_DSC_OVERFLOW1_ST 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW1_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW1_ST)
#define BIT_DAC_DSC_OVERFLOW0_ST BIT(5)
#define BIT_SHIFT_DAC_DSC_OVERFLOW0_ST 5
#define BIT_MASK_DAC_DSC_OVERFLOW0_ST 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW0_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW0_ST)
#define BIT_DAC__WRITE_ERROR_ST BIT(4)
#define BIT_SHIFT_DAC__WRITE_ERROR_ST 4
#define BIT_MASK_DAC__WRITE_ERROR_ST 0x1
#define BIT_CTRL_DAC__WRITE_ERROR_ST(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_ST) << BIT_SHIFT_DAC__WRITE_ERROR_ST)
#define BIT_DAC_FIFO_STOP_ST BIT(3)
#define BIT_SHIFT_DAC_FIFO_STOP_ST 3
#define BIT_MASK_DAC_FIFO_STOP_ST 0x1
#define BIT_CTRL_DAC_FIFO_STOP_ST(x) (((x) & BIT_MASK_DAC_FIFO_STOP_ST) << BIT_SHIFT_DAC_FIFO_STOP_ST)
#define BIT_DAC_FIFO_OVERFLOW_ST BIT(2)
#define BIT_SHIFT_DAC_FIFO_OVERFLOW_ST 2
#define BIT_MASK_DAC_FIFO_OVERFLOW_ST 0x1
#define BIT_CTRL_DAC_FIFO_OVERFLOW_ST(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_ST) << BIT_SHIFT_DAC_FIFO_OVERFLOW_ST)
#define BIT_DAC_FIFO_WR_REQ_ST BIT(1)
#define BIT_SHIFT_DAC_FIFO_WR_REQ_ST 1
#define BIT_MASK_DAC_FIFO_WR_REQ_ST 0x1
#define BIT_CTRL_DAC_FIFO_WR_REQ_ST(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_ST) << BIT_SHIFT_DAC_FIFO_WR_REQ_ST)
#define BIT_DAC_FIFO_FULL_ST BIT(0)
#define BIT_SHIFT_DAC_FIFO_FULL_ST 0
#define BIT_MASK_DAC_FIFO_FULL_ST 0x1
#define BIT_CTRL_DAC_FIFO_FULL_ST(x) (((x) & BIT_MASK_DAC_FIFO_FULL_ST) << BIT_SHIFT_DAC_FIFO_FULL_ST)
//2 REG_DAC_PWR_CTRL
#define BIT_SHIFT_DAC_PWR_CUT_CNTR 16
#define BIT_MASK_DAC_PWR_CUT_CNTR 0xff
#define BIT_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
#define BIT_CTRL_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
#define BIT_GET_DAC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_DAC_PWR_CUT_CNTR) & BIT_MASK_DAC_PWR_CUT_CNTR)
#define BIT_ST_DAC_FIFO_ON BIT(11)
#define BIT_SHIFT_ST_DAC_FIFO_ON 11
#define BIT_MASK_ST_DAC_FIFO_ON 0x1
#define BIT_CTRL_ST_DAC_FIFO_ON(x) (((x) & BIT_MASK_ST_DAC_FIFO_ON) << BIT_SHIFT_ST_DAC_FIFO_ON)
#define BIT_ST_DAC_ISO_ON BIT(10)
#define BIT_SHIFT_ST_DAC_ISO_ON 10
#define BIT_MASK_ST_DAC_ISO_ON 0x1
#define BIT_CTRL_ST_DAC_ISO_ON(x) (((x) & BIT_MASK_ST_DAC_ISO_ON) << BIT_SHIFT_ST_DAC_ISO_ON)
#define BIT_ST_DAC_PWR33_ON BIT(9)
#define BIT_SHIFT_ST_DAC_PWR33_ON 9
#define BIT_MASK_ST_DAC_PWR33_ON 0x1
#define BIT_CTRL_ST_DAC_PWR33_ON(x) (((x) & BIT_MASK_ST_DAC_PWR33_ON) << BIT_SHIFT_ST_DAC_PWR33_ON)
#define BIT_ST_DAC_PWR12_ON BIT(8)
#define BIT_SHIFT_ST_DAC_PWR12_ON 8
#define BIT_MASK_ST_DAC_PWR12_ON 0x1
#define BIT_CTRL_ST_DAC_PWR12_ON(x) (((x) & BIT_MASK_ST_DAC_PWR12_ON) << BIT_SHIFT_ST_DAC_PWR12_ON)
#define BIT_DAC_ISO_MANU BIT(3)
#define BIT_SHIFT_DAC_ISO_MANU 3
#define BIT_MASK_DAC_ISO_MANU 0x1
#define BIT_CTRL_DAC_ISO_MANU(x) (((x) & BIT_MASK_DAC_ISO_MANU) << BIT_SHIFT_DAC_ISO_MANU)
#define BIT_DAC_PWR33_MANU BIT(2)
#define BIT_SHIFT_DAC_PWR33_MANU 2
#define BIT_MASK_DAC_PWR33_MANU 0x1
#define BIT_CTRL_DAC_PWR33_MANU(x) (((x) & BIT_MASK_DAC_PWR33_MANU) << BIT_SHIFT_DAC_PWR33_MANU)
#define BIT_DAC_PWR12_MANU BIT(1)
#define BIT_SHIFT_DAC_PWR12_MANU 1
#define BIT_MASK_DAC_PWR12_MANU 0x1
#define BIT_CTRL_DAC_PWR12_MANU(x) (((x) & BIT_MASK_DAC_PWR12_MANU) << BIT_SHIFT_DAC_PWR12_MANU)
#define BIT_DAC_PWR_AUTO BIT(0)
#define BIT_SHIFT_DAC_PWR_AUTO 0
#define BIT_MASK_DAC_PWR_AUTO 0x1
#define BIT_CTRL_DAC_PWR_AUTO(x) (((x) & BIT_MASK_DAC_PWR_AUTO) << BIT_SHIFT_DAC_PWR_AUTO)
//2 REG_DAC_ANAPAR_DA0
#define BIT_SHIFT_PWR_ALL_CNTR 12
#define BIT_MASK_PWR_ALL_CNTR 0xfffff
#define BIT_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
#define BIT_CTRL_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
#define BIT_GET_PWR_ALL_CNTR(x) (((x) >> BIT_SHIFT_PWR_ALL_CNTR) & BIT_MASK_PWR_ALL_CNTR)
#define BIT_SHIFT_PWR_FUP_CNTR 0
#define BIT_MASK_PWR_FUP_CNTR 0xfff
#define BIT_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
#define BIT_CTRL_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
#define BIT_GET_PWR_FUP_CNTR(x) (((x) >> BIT_SHIFT_PWR_FUP_CNTR) & BIT_MASK_PWR_FUP_CNTR)
//2 REG_DAC_ANAPAR_DA1
#define BIT_FUP_EN BIT(31)
#define BIT_SHIFT_FUP_EN 31
#define BIT_MASK_FUP_EN 0x1
#define BIT_CTRL_FUP_EN(x) (((x) & BIT_MASK_FUP_EN) << BIT_SHIFT_FUP_EN)
#define BIT_SHIFT_ANAPAR_DA 8
#define BIT_MASK_ANAPAR_DA 0x7fffff
#define BIT_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
#define BIT_CTRL_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
#define BIT_GET_ANAPAR_DA(x) (((x) >> BIT_SHIFT_ANAPAR_DA) & BIT_MASK_ANAPAR_DA)
#define BIT_D_POW_DACVREF BIT(7)
#define BIT_SHIFT_D_POW_DACVREF 7
#define BIT_MASK_D_POW_DACVREF 0x1
#define BIT_CTRL_D_POW_DACVREF(x) (((x) & BIT_MASK_D_POW_DACVREF) << BIT_SHIFT_D_POW_DACVREF)
#define BIT_D_POW_VREF2 BIT(6)
#define BIT_SHIFT_D_POW_VREF2 6
#define BIT_MASK_D_POW_VREF2 0x1
#define BIT_CTRL_D_POW_VREF2(x) (((x) & BIT_MASK_D_POW_VREF2) << BIT_SHIFT_D_POW_VREF2)
#define BIT_D_POW_MBIAS BIT(5)
#define BIT_SHIFT_D_POW_MBIAS 5
#define BIT_MASK_D_POW_MBIAS 0x1
#define BIT_CTRL_D_POW_MBIAS(x) (((x) & BIT_MASK_D_POW_MBIAS) << BIT_SHIFT_D_POW_MBIAS)
#define BIT_D_POW_DIV4 BIT(4)
#define BIT_SHIFT_D_POW_DIV4 4
#define BIT_MASK_D_POW_DIV4 0x1
#define BIT_CTRL_D_POW_DIV4(x) (((x) & BIT_MASK_D_POW_DIV4) << BIT_SHIFT_D_POW_DIV4)
#define BIT_D_POW_DF1SE_R BIT(3)
#define BIT_SHIFT_D_POW_DF1SE_R 3
#define BIT_MASK_D_POW_DF1SE_R 0x1
#define BIT_CTRL_D_POW_DF1SE_R(x) (((x) & BIT_MASK_D_POW_DF1SE_R) << BIT_SHIFT_D_POW_DF1SE_R)
#define BIT_D_POW_DF2SE_L BIT(2)
#define BIT_SHIFT_D_POW_DF2SE_L 2
#define BIT_MASK_D_POW_DF2SE_L 0x1
#define BIT_CTRL_D_POW_DF2SE_L(x) (((x) & BIT_MASK_D_POW_DF2SE_L) << BIT_SHIFT_D_POW_DF2SE_L)
#define BIT_D_POW_DAC_R BIT(1)
#define BIT_SHIFT_D_POW_DAC_R 1
#define BIT_MASK_D_POW_DAC_R 0x1
#define BIT_CTRL_D_POW_DAC_R(x) (((x) & BIT_MASK_D_POW_DAC_R) << BIT_SHIFT_D_POW_DAC_R)
#define BIT_D_POW_DAC_L BIT(0)
#define BIT_SHIFT_D_POW_DAC_L 0
#define BIT_MASK_D_POW_DAC_L 0x1
#define BIT_CTRL_D_POW_DAC_L(x) (((x) & BIT_MASK_D_POW_DAC_L) << BIT_SHIFT_D_POW_DAC_L)
//================ Register Reg Field =========================
#define REG_DAC0_FIFO_WR 0x0000
#define REG_DAC_CTRL 0x0004
#define REG_DAC_INTR_CTRL 0x0008
#define REG_DAC_INTR_STS 0x000C
#define REG_DAC_PWR_CTRL 0x0010
#define REG_DAC_ANAPAR_DA0 0x0014
#define REG_DAC_ANAPAR_DA1 0x0018
//================ DAC HAL related enumeration ==================
//================ DAC HAL Macro ===========================
#define HAL_DAC_WRITE32(dacidx, addr, value) HAL_WRITE32(DAC_REG_BASE+dacidx*0x800 \
,addr,value)
#define HAL_DAC_READ32(dacidx, addr) HAL_READ32(DAC_REG_BASE+dacidx*0x800,addr)
//================ DAC Function Prototypes =====================
RTK_STATUS HalDACInit8195a(IN VOID *Data);
RTK_STATUS HalDACDeInit8195a(IN VOID *Data);
RTK_STATUS HalDACEnableRtl8195a(IN VOID *Data);
RTK_STATUS HalDACIntrCtrl8195a(IN VOID *Data);
u8 HalDACSendRtl8195a(IN VOID *Data);
u32 HalDACReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg);
#endif

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lib/fwlib/rtl8195a/rtl8195a_gdma.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_GDMA_H_
#define _RTL8195A_GDMA_H_
// Define GDMA Handshake interface with peripheral, 0 -> GDMA0, 1-> GDMA1
// Set this Hnadshake interface map to register REG_PESOC_SOC_CTRL
#define GDMA_HANDSHAKE_UART0_TX 0
#define GDMA_HANDSHAKE_UART0_RX 1
#define GDMA_HANDSHAKE_UART1_TX 2
#define GDMA_HANDSHAKE_UART1_RX 3
#define GDMA_HANDSHAKE_UART2_TX 14 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_UART2_RX 14 // Only on GDMA 1, hardware fixed
#define GDMA_HANDSHAKE_SSI0_TX 4
#define GDMA_HANDSHAKE_SSI0_RX 5
#define GDMA_HANDSHAKE_SSI1_TX 6
#define GDMA_HANDSHAKE_SSI1_RX 7
#define GDMA_HANDSHAKE_SSI2_TX 15 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_SSI2_RX 15 // Only on GDMA 1, hardware fixed
#define GDMA_HANDSHAKE_I2C0_TX 8
#define GDMA_HANDSHAKE_I2C0_RX 9
#define GDMA_HANDSHAKE_I2C1_TX 10
#define GDMA_HANDSHAKE_I2C1_RX 11
#define GDMA_HANDSHAKE_ADC 12
#define GDMA_HANDSHAKE_DAC0 13 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_DAC1 13 // Only on GDMA 1, hardware fixed
#define HAL_GDMAX_READ32(GdmaIndex, addr) \
HAL_READ32(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE32(GdmaIndex, addr, value) \
HAL_WRITE32((GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF)), addr, value)
#define HAL_GDMAX_READ16(GdmaIndex, addr) \
HAL_READ16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE16(GdmaIndex, addr, value) \
HAL_WRITE16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
#define HAL_GDMAX_READ8(GdmaIndex, addr) \
HAL_READ8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE8(GdmaIndex, addr, value) \
HAL_WRITE8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
#define GDMA_CH_MAX 0x06
#define REG_GDMA_CH_OFF 0x058
#define REG_GDMA_CH_SAR 0x000
#define REG_GDMA_CH_DAR 0x008
#define REG_GDMA_CH_LLP 0x010
#define REG_GDMA_CH_CTL 0x018
#define REG_GDMA_CH_SSTAT 0x020
#define REG_GDMA_CH_DSTAT 0x028
#define REG_GDMA_CH_SSTATAR 0x030
#define REG_GDMA_CH_DSTATAR 0x038
#define REG_GDMA_CH_CFG 0x040
#define REG_GDMA_CH_SGR 0x048
#define REG_GDMA_CH_DSR 0x050
//3 Interrupt Registers
#define REG_GDMA_RAW_INT_BASE 0x2C0
#define REG_GDMA_RAW_INT_TFR 0x2C0
#define REG_GDMA_RAW_INT_BLOCK 0x2c8
#define REG_GDMA_RAW_INT_SRC_TRAN 0x2D0
#define REG_GDMA_RAW_INT_DST_TRAN 0x2D8
#define REG_GDMA_RAW_INT_ERR 0x2E0
#define REG_GDMA_STATUS_INT_BASE 0x2E8
#define REG_GDMA_STATUS_INT_TFR 0x2E8
#define REG_GDMA_STATUS_INT_BLOCK 0x2F0
#define REG_GDMA_STATUS_INT_SRC_TRAN 0x2F8
#define REG_GDMA_STATUS_INT_DST_TRAN 0x300
#define REG_GDMA_STATUS_INT_ERR 0x308
#define REG_GDMA_MASK_INT_BASE 0x310
#define REG_GDMA_MASK_INT_TFR 0x310
#define REG_GDMA_MASK_INT_BLOCK 0x318
#define REG_GDMA_MASK_INT_SRC_TRAN 0x320
#define REG_GDMA_MASK_INT_DST_TRAN 0x328
#define REG_GDMA_MASK_INT_INT_ERR 0x330
#define REG_GDMA_CLEAR_INT_BASE 0x338
#define REG_GDMA_CLEAR_INT_TFR 0x338
#define REG_GDMA_CLEAR_INT_BLOCK 0x340
#define REG_GDMA_CLEAR_INT_SRC_TRAN 0x348
#define REG_GDMA_CLEAR_INT_DST_TRAN 0x350
#define REG_GDMA_CLEAR_INT_ERR 0x358
#define REG_GDMA_STATUS_INT 0x360
//3 Software handshaking Registers
#define REG_GDMA_REQ_SRC 0x368
#define REG_GDMA_REQ_DST 0x370
#define REG_GDMA_REQ_SGL_REQ 0x378
#define REG_GDMA_REQ_DST_REQ 0x380
#define REG_GDMA_REQ_LST_SRC 0x388
#define REG_GDMA_REQ_LST_DST 0x390
//3 Miscellaneous Registers
#define REG_GDMA_DMAC_CFG 0x398
#define REG_GDMA_CH_EN 0x3A0
#define REG_GDMA_DMA_ID 0x3A8
#define REG_GDMA_DMA_TEST 0x3B0
#define REG_GDMA_DMA_COM_PARAMS6 0x3C8
#define REG_GDMA_DMA_COM_PARAMS5 0x3D0
#define REG_GDMA_DMA_COM_PARAMS4 0x3D8
#define REG_GDMA_DMA_COM_PARAMS3 0x3E0
#define REG_GDMA_DMA_COM_PARAMS2 0x3E8
#define REG_GDMA_DMA_COM_PARAMS1 0x3F0
#define REG_GDMA_DMA_COM_PARAMS0 0x3F8
//3 CTL Register Bit Control
#define BIT_SHIFT_CTLX_LO_INT_EN 0
#define BIT_MASK_CTLX_LO_INT_EN 0x1
#define BIT_CTLX_LO_INT_EN(x)(((x) & BIT_MASK_CTLX_LO_INT_EN) << BIT_SHIFT_CTLX_LO_INT_EN)
#define BIT_INVC_CTLX_LO_INT_EN (~(BIT_MASK_CTLX_LO_INT_EN << BIT_SHIFT_CTLX_LO_INT_EN))
#define BIT_SHIFT_CTLX_LO_DST_TR_WIDTH 1
#define BIT_MASK_CTLX_LO_DST_TR_WIDTH 0x7
#define BIT_CTLX_LO_DST_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_DST_TR_WIDTH) << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH)
#define BIT_INVC_CTLX_LO_DST_TR_WIDTH (~(BIT_MASK_CTLX_LO_DST_TR_WIDTH << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH))
#define BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH 4
#define BIT_MASK_CTLX_LO_SRC_TR_WIDTH 0x7
#define BIT_CTLX_LO_SRC_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_SRC_TR_WIDTH) << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH)
#define BIT_INVC_CTLX_LO_SRC_TR_WIDTH (~(BIT_MASK_CTLX_LO_SRC_TR_WIDTH << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH))
#define BIT_SHIFT_CTLX_LO_DINC 7
#define BIT_MASK_CTLX_LO_DINC 0x3
#define BIT_CTLX_LO_DINC(x)(((x) & BIT_MASK_CTLX_LO_DINC) << BIT_SHIFT_CTLX_LO_DINC)
#define BIT_INVC_CTLX_LO_DINC (~(BIT_MASK_CTLX_LO_DINC << BIT_SHIFT_CTLX_LO_DINC))
#define BIT_SHIFT_CTLX_LO_SINC 9
#define BIT_MASK_CTLX_LO_SINC 0x3
#define BIT_CTLX_LO_SINC(x)(((x) & BIT_MASK_CTLX_LO_SINC) << BIT_SHIFT_CTLX_LO_SINC)
#define BIT_INVC_CTLX_LO_SINC (~(BIT_MASK_CTLX_LO_SINC << BIT_SHIFT_CTLX_LO_SINC))
#define BIT_SHIFT_CTLX_LO_DEST_MSIZE 11
#define BIT_MASK_CTLX_LO_DEST_MSIZE 0x7
#define BIT_CTLX_LO_DEST_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_DEST_MSIZE) << BIT_SHIFT_CTLX_LO_DEST_MSIZE)
#define BIT_INVC_CTLX_LO_DEST_MSIZE (~(BIT_MASK_CTLX_LO_DEST_MSIZE << BIT_SHIFT_CTLX_LO_DEST_MSIZE))
#define BIT_SHIFT_CTLX_LO_SRC_MSIZE 14
#define BIT_MASK_CTLX_LO_SRC_MSIZE 0x7
#define BIT_CTLX_LO_SRC_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_SRC_MSIZE) << BIT_SHIFT_CTLX_LO_SRC_MSIZE)
#define BIT_INVC_CTLX_LO_SRC_MSIZE (~(BIT_MASK_CTLX_LO_SRC_MSIZE << BIT_SHIFT_CTLX_LO_SRC_MSIZE))
#define BIT_SHIFT_CTLX_LO_SRC_GATHER_EN 17
#define BIT_MASK_CTLX_LO_SRC_GATHER_EN 0x1
#define BIT_CTLX_LO_SRC_GATHER_EN(x)(((x) & BIT_MASK_CTLX_LO_SRC_GATHER_EN) << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN)
#define BIT_INVC_CTLX_LO_SRC_GATHER_EN (~(BIT_MASK_CTLX_LO_SRC_GATHER_EN << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN))
#define BIT_SHIFT_CTLX_LO_DST_SCATTER_EN 18
#define BIT_MASK_CTLX_LO_DST_SCATTER_EN 0x1
#define BIT_CTLX_LO_DST_SCATTER_EN(x)(((x) & BIT_MASK_CTLX_LO_DST_SCATTER_EN) << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN)
#define BIT_INVC_CTLX_LO_DST_SCATTER_EN (~(BIT_MASK_CTLX_LO_DST_SCATTER_EN << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN))
#define BIT_SHIFT_CTLX_LO_TT_FC 20
#define BIT_MASK_CTLX_LO_TT_FC 0x7
#define BIT_CTLX_LO_TT_FC(x)(((x) & BIT_MASK_CTLX_LO_TT_FC) << BIT_SHIFT_CTLX_LO_TT_FC)
#define BIT_INVC_CTLX_LO_TT_FC (~(BIT_MASK_CTLX_LO_TT_FC << BIT_SHIFT_CTLX_LO_TT_FC))
#define BIT_SHIFT_CTLX_LO_DMS 23
#define BIT_MASK_CTLX_LO_DMS 0x3
#define BIT_CTLX_LO_DMS(x)(((x) & BIT_MASK_CTLX_LO_DMS) << BIT_MASK_CTLX_LO_DMS)
#define BIT_INVC_CTLX_LO_DMS (~(BIT_MASK_CTLX_LO_DMS << BIT_SHIFT_CTLX_LO_DMS))
#define BIT_SHIFT_CTLX_LO_SMS 25
#define BIT_MASK_CTLX_LO_SMS 0x3
#define BIT_CTLX_LO_SMS(x)(((x) & BIT_MASK_CTLX_LO_SMS) << BIT_SHIFT_CTLX_LO_SMS)
#define BIT_INVC_CTLX_LO_SMS (~(BIT_MASK_CTLX_LO_SMS << BIT_SHIFT_CTLX_LO_SMS))
#define BIT_SHIFT_CTLX_LO_LLP_DST_EN 27
#define BIT_MASK_CTLX_LO_LLP_DST_EN 0x1
#define BIT_CTLX_LO_LLP_DST_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_DST_EN) << BIT_SHIFT_CTLX_LO_LLP_DST_EN)
#define BIT_INVC_CTLX_LO_LLP_DST_EN (~(BIT_MASK_CTLX_LO_LLP_DST_EN << BIT_SHIFT_CTLX_LO_LLP_DST_EN))
#define BIT_SHIFT_CTLX_LO_LLP_SRC_EN 28
#define BIT_MASK_CTLX_LO_LLP_SRC_EN 0x1
#define BIT_CTLX_LO_LLP_SRC_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_SRC_EN) << BIT_SHIFT_CTLX_LO_LLP_SRC_EN)
#define BIT_INVC_CTLX_LO_LLP_SRC_EN (~(BIT_MASK_CTLX_LO_LLP_SRC_EN << BIT_SHIFT_CTLX_LO_LLP_SRC_EN))
#define BIT_SHIFT_CTLX_UP_BLOCK_BS 0
#define BIT_MASK_CTLX_UP_BLOCK_BS 0xFFF
#define BIT_CTLX_UP_BLOCK_BS(x)(((x) & BIT_MASK_CTLX_UP_BLOCK_BS) << BIT_SHIFT_CTLX_UP_BLOCK_BS)
#define BIT_INVC_CTLX_UP_BLOCK_BS (~(BIT_MASK_CTLX_UP_BLOCK_BS << BIT_SHIFT_CTLX_UP_BLOCK_BS))
#define BIT_SHIFT_CTLX_UP_DONE 12
#define BIT_MASK_CTLX_UP_DONE 0x1
#define BIT_CTLX_UP_DONE(x)(((x) & BIT_MASK_CTLX_UP_DONE) << BIT_SHIFT_CTLX_UP_DONE)
#define BIT_INVC_CTLX_UP_DONE (~(BIT_MASK_CTLX_UP_DONE << BIT_SHIFT_CTLX_UP_DONE))
//3 CFG Register Bit Control
#define BIT_SHIFT_CFGX_LO_CH_PRIOR 5
#define BIT_MASK_CFGX_LO_CH_PRIOR 0x7
#define BIT_CFGX_LO_CH_PRIOR(x)(((x) & BIT_MASK_CFGX_LO_CH_PRIOR) << BIT_SHIFT_CFGX_LO_CH_PRIOR)
#define BIT_INVC_CFGX_LO_CH_PRIOR (~(BIT_MASK_CFGX_LO_CH_PRIOR << BIT_SHIFT_CFGX_LO_CH_PRIOR))
#define BIT_SHIFT_CFGX_LO_CH_SUSP 8
#define BIT_MASK_CFGX_LO_CH_SUSP 0x1
#define BIT_CFGX_LO_CH_SUSP(x)(((x) & BIT_MASK_CFGX_LO_CH_SUSP) << BIT_SHIFT_CFGX_LO_CH_SUSP)
#define BIT_INVC_CFGX_LO_CH_SUSP (~(BIT_MASK_CFGX_LO_CH_SUSP << BIT_SHIFT_CFGX_LO_CH_SUSP))
#define BIT_SHIFT_CFGX_LO_FIFO_EMPTY 9
#define BIT_MASK_CFGX_LO_FIFO_EMPTY 0x1
#define BIT_CFGX_LO_FIFO_EMPTY(x)(((x) & BIT_MASK_CFGX_LO_FIFO_EMPTY) << BIT_SHIFT_CFGX_LO_FIFO_EMPTY)
#define BIT_INVC_CFGX_LO_FIFO_EMPTY (~(BIT_MASK_CFGX_LO_FIFO_EMPTY << BIT_SHIFT_CFGX_LO_FIFO_EMPTY))
#define BIT_SHIFT_CFGX_LO_HS_SEL_DST 10
#define BIT_MASK_CFGX_LO_HS_SEL_DST 0x1
#define BIT_CFGX_LO_HS_SEL_DST(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_DST) << BIT_SHIFT_CFGX_LO_HS_SEL_DST)
#define BIT_INVC_CFGX_LO_HS_SEL_DST (~(BIT_MASK_CFGX_LO_HS_SEL_DST << BIT_SHIFT_CFGX_LO_HS_SEL_DST))
#define BIT_SHIFT_CFGX_LO_HS_SEL_SRC 11
#define BIT_MASK_CFGX_LO_HS_SEL_SRC 0x1
#define BIT_CFGX_LO_HS_SEL_SRC(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_SRC) << BIT_SHIFT_CFGX_LO_HS_SEL_SRC)
#define BIT_INVC_CFGX_LO_HS_SEL_SRC (~(BIT_MASK_CFGX_LO_HS_SEL_SRC << BIT_SHIFT_CFGX_LO_HS_SEL_SRC))
#define BIT_SHIFT_CFGX_LO_LOCK_CH_L 12
#define BIT_MASK_CFGX_LO_LOCK_CH_L 0x3
#define BIT_CFGX_LO_LOCK_CH_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH_L) << BIT_SHIFT_CFGX_LO_LOCK_CH_L)
#define BIT_INVC_CFGX_LO_LOCK_CH_L (~(BIT_MASK_CFGX_LO_LOCK_CH_L << BIT_SHIFT_CFGX_LO_LOCK_CH_L))
#define BIT_SHIFT_CFGX_LO_LOCK_B_L 14
#define BIT_MASK_CFGX_LO_LOCK_B_L 0x3
#define BIT_CFGX_LO_LOCK_B_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B_L) << BIT_SHIFT_CFGX_LO_LOCK_B_L)
#define BIT_INVC_CFGX_LO_LOCK_B_L (~(BIT_MASK_CFGX_LO_LOCK_B_L << BIT_SHIFT_CFGX_LO_LOCK_B_L))
#define BIT_SHIFT_CFGX_LO_LOCK_CH 16
#define BIT_MASK_CFGX_LO_LOCK_CH 0x1
#define BIT_CFGX_LO_LOCK_CH(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH) << BIT_SHIFT_CFGX_LO_LOCK_CH)
#define BIT_INVC_CFGX_LO_LOCK_CH (~(BIT_MASK_CFGX_LO_LOCK_CH << BIT_SHIFT_CFGX_LO_LOCK_CH))
#define BIT_SHIFT_CFGX_LO_LOCK_B 17
#define BIT_MASK_CFGX_LO_LOCK_B 0x1
#define BIT_CFGX_LO_LOCK_B(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B) << BIT_SHIFT_CFGX_LO_LOCK_B)
#define BIT_INVC_CFGX_LO_LOCK_B (~(BIT_MASK_CFGX_LO_LOCK_B << BIT_SHIFT_CFGX_LO_LOCK_B))
#define BIT_SHIFT_CFGX_LO_DST_HS_POL 18
#define BIT_MASK_CFGX_LO_DST_HS_POL 0x1
#define BIT_CFGX_LO_DST_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_DST_HS_POL) << BIT_SHIFT_CFGX_LO_DST_HS_POL)
#define BIT_INVC_CFGX_LO_DST_HS_POL (~(BIT_MASK_CFGX_LO_DST_HS_POL << BIT_SHIFT_CFGX_LO_DST_HS_POL))
#define BIT_SHIFT_CFGX_LO_SRC_HS_POL 19
#define BIT_MASK_CFGX_LO_SRC_HS_POL 0x1
#define BIT_CFGX_LO_SRC_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_SRC_HS_POL) << BIT_SHIFT_CFGX_LO_SRC_HS_POL)
#define BIT_INVC_CFGX_LO_SRC_HS_POL (~(BIT_MASK_CFGX_LO_SRC_HS_POL << BIT_SHIFT_CFGX_LO_SRC_HS_POL))
#define BIT_SHIFT_CFGX_LO_MAX_ABRST 20
#define BIT_MASK_CFGX_LO_MAX_ABRST 0x3FF
#define BIT_CFGX_LO_MAX_ABRST(x)(((x) & BIT_MASK_CFGX_LO_MAX_ABRST) << BIT_SHIFT_CFGX_LO_MAX_ABRST)
#define BIT_INVC_CFGX_LO_MAX_ABRST (~(BIT_MASK_CFGX_LO_MAX_ABRST << BIT_SHIFT_CFGX_LO_MAX_ABRST))
#define BIT_SHIFT_CFGX_LO_RELOAD_SRC 30
#define BIT_MASK_CFGX_LO_RELOAD_SRC 0x1
#define BIT_CFGX_LO_RELOAD_SRC(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_SRC) << BIT_SHIFT_CFGX_LO_RELOAD_SRC)
#define BIT_INVC_CFGX_LO_RELOAD_SRC (~(BIT_MASK_CFGX_LO_RELOAD_SRC << BIT_SHIFT_CFGX_LO_RELOAD_SRC))
#define BIT_SHIFT_CFGX_LO_RELOAD_DST 31
#define BIT_MASK_CFGX_LO_RELOAD_DST 0x1
#define BIT_CFGX_LO_RELOAD_DST(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_DST) << BIT_SHIFT_CFGX_LO_RELOAD_DST)
#define BIT_INVC_CFGX_LO_RELOAD_DST (~(BIT_MASK_CFGX_LO_RELOAD_DST << BIT_SHIFT_CFGX_LO_RELOAD_DST))
#define BIT_SHIFT_CFGX_UP_FCMODE 0
#define BIT_MASK_CFGX_UP_FCMODE 0x1
#define BIT_CFGX_UP_FCMODE(x)(((x) & BIT_MASK_CFGX_UP_FCMODE) << BIT_SHIFT_CFGX_UP_FCMODE)
#define BIT_INVC_CFGX_UP_FCMODE (~(BIT_MASK_CFGX_UP_FCMODE << BIT_SHIFT_CFGX_UP_FCMODE))
#define BIT_SHIFT_CFGX_UP_FIFO_MODE 1
#define BIT_MASK_CFGX_UP_FIFO_MODE 0x1
#define BIT_CFGX_UP_FIFO_MODE(x)(((x) & BIT_MASK_CFGX_UP_FIFO_MODE) << BIT_SHIFT_CFGX_UP_FIFO_MODE)
#define BIT_INVC_CFGX_UP_FIFO_MODE (~(BIT_MASK_CFGX_UP_FIFO_MODE << BIT_SHIFT_CFGX_UP_FIFO_MODE))
#define BIT_SHIFT_CFGX_UP_PROTCTL 2
#define BIT_MASK_CFGX_UP_PROTCTL 0x7
#define BIT_CFGX_UP_PROTCTL(x)(((x) & BIT_MASK_CFGX_UP_PROTCTL) << BIT_SHIFT_CFGX_UP_PROTCTL)
#define BIT_INVC_CFGX_UP_PROTCTL (~(BIT_MASK_CFGX_UP_PROTCTL << BIT_SHIFT_CFGX_UP_PROTCTL))
#define BIT_SHIFT_CFGX_UP_DS_UPD_EN 5
#define BIT_MASK_CFGX_UP_DS_UPD_EN 0x1
#define BIT_CFGX_UP_DS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_DS_UPD_EN) << BIT_SHIFT_CFGX_UP_DS_UPD_EN)
#define BIT_INVC_CFGX_UP_DS_UPD_EN (~(BIT_MASK_CFGX_UP_DS_UPD_EN << BIT_SHIFT_CFGX_UP_DS_UPD_EN))
#define BIT_SHIFT_CFGX_UP_SS_UPD_EN 6
#define BIT_MASK_CFGX_UP_SS_UPD_EN 0x1
#define BIT_CFGX_UP_SS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_SS_UPD_EN) << BIT_SHIFT_CFGX_UP_SS_UPD_EN)
#define BIT_INVC_CFGX_UP_SS_UPD_EN (~(BIT_MASK_CFGX_UP_SS_UPD_EN << BIT_SHIFT_CFGX_UP_SS_UPD_EN))
#define BIT_SHIFT_CFGX_UP_SRC_PER 7
#define BIT_MASK_CFGX_UP_SRC_PER 0xF
#define BIT_CFGX_UP_SRC_PER(x)(((x) & BIT_MASK_CFGX_UP_SRC_PER) << BIT_SHIFT_CFGX_UP_SRC_PER)
#define BIT_INVC_CFGX_UP_SRC_PER (~(BIT_MASK_CFGX_UP_SRC_PER << BIT_SHIFT_CFGX_UP_SRC_PER))
#define BIT_SHIFT_CFGX_UP_DEST_PER 11
#define BIT_MASK_CFGX_UP_DEST_PER 0xF
#define BIT_CFGX_UP_DEST_PER(x)(((x) & BIT_MASK_CFGX_UP_DEST_PER) << BIT_SHIFT_CFGX_UP_DEST_PER)
#define BIT_INVC_CFGX_UP_DEST_PER (~(BIT_MASK_CFGX_UP_DEST_PER << BIT_SHIFT_CFGX_UP_DEST_PER))
typedef enum _GDMA_CHANNEL_NUM_ {
GdmaNoCh = 0x0000,
GdmaCh0 = 0x0101,
GdmaCh1 = 0x0202,
GdmaCh2 = 0x0404,
GdmaCh3 = 0x0808,
GdmaCh4 = 0x1010,
GdmaCh5 = 0x2020,
GdmaCh6 = 0x4040,
GdmaCh7 = 0x8080,
GdmaAllCh = 0xffff
}GDMA_CHANNEL_NUM, *PGDMA_CHANNEL_NUM;
//3 CTL register struct
typedef enum _GDMA_CTL_TT_FC_TYPE_ {
TTFCMemToMem = 0x00,
TTFCMemToPeri = 0x01,
TTFCPeriToMem = 0x02
}GDMA_CTL_TT_FC_TYPE, *PGDMA_CTL_TT_FC_TYPE;
//Max type = Bus Width
typedef enum _GDMA_CTL_TR_WIDTH_ {
TrWidthOneByte = 0x00,
TrWidthTwoBytes = 0x01,
TrWidthFourBytes = 0x02
}GDMA_CTL_TR_WIDTH, *PGDMA_CTL_TR_WIDTH;
typedef enum _GDMA_CTL_MSIZE_ {
MsizeOne = 0x00,
MsizeFour = 0x01,
MsizeEight = 0x02
}GDMA_CTL_MSIZE, *PGDMA_CTL_MSIZE;
typedef enum _GDMA_INC_TYPE_ {
IncType = 0x00,
DecType = 0x01,
NoChange = 0x02
}GDMA_INC_TYPE, *PGDMA_INC_TYPE;
typedef struct _GDMA_CTL_REG_ {
GDMA_CTL_TT_FC_TYPE TtFc;
GDMA_CTL_TR_WIDTH DstTrWidth;
GDMA_CTL_TR_WIDTH SrcTrWidth;
GDMA_INC_TYPE Dinc;
GDMA_INC_TYPE Sinc;
GDMA_CTL_MSIZE DestMsize;
GDMA_CTL_MSIZE SrcMsize;
u8 IntEn :1; // Bit 0
u8 SrcGatherEn :1; // Bit 1
u8 DstScatterEn :1; // Bit 2
u8 LlpDstEn :1; // Bit 3
u8 LlpSrcEn :1; // Bit 4
u8 Done :1; // Bit 5
u8 Rsvd6To7 :2; //Bit 6 -7
u16 BlockSize;
}GDMA_CTL_REG, *PGDMA_CTL_REG;
//3 CFG Register Structure
typedef enum _GDMA_CH_PRIORITY_ {
Prior0 = 0,
Prior1 = 1,
Prior2 = 2,
Prior3 = 3,
Prior4 = 4,
Prior5 = 5,
Prior6 = 6,
Prior7 = 7
}GDMA_CH_PRIORITY, *PGDMA_CH_PRIORITY;
typedef enum _GDMA_LOCK_LEVEL_ {
OverComplDmaTransfer = 0x00,
OverComplDmaBlockTransfer = 0x01,
OverComplDmaTransation = 0x02
}GDMA_LOCK_LEVEL, *PGDMA_LOCK_LEVEL;
typedef struct _GDMA_CFG_REG_ {
GDMA_CH_PRIORITY ChPrior;
GDMA_LOCK_LEVEL LockBL;
GDMA_LOCK_LEVEL LockChL;
u16 MaxAbrst;
u8 SrcPer;
u8 DestPer;
u16 ChSusp :1; //Bit 0
u16 FifoEmpty :1; //Bit 1
u16 HsSelDst :1; //Bit 2
u16 HsSelSrc :1; //Bit 3
u16 LockCh :1; //Bit 4
u16 LockB :1; //Bit 5
u16 DstHsPol :1; //Bit 6
u16 SrcHsPol :1; //Bit 7
u16 ReloadSrc :1; //Bit 8
u16 ReloadDst :1; //Bit 9
u16 FifoMode :1; //Bit 10
u16 DsUpdEn :1; //Bit 11
u16 SsUpdEn :1; //Bit 12
u16 Rsvd13To15 :3;
}GDMA_CFG_REG, *PGDMA_CFG_REG;
typedef enum _GDMA_ISR_TYPE_ {
TransferType = 0x1,
BlockType = 0x2,
SrcTransferType = 0x4,
DstTransferType = 0x8,
ErrType = 0x10
}GDMA_ISR_TYPE, *PGDMA_ISR_TYPE;
VOID
HalGdmaOnOffRtl8195a (
IN VOID *Data
);
BOOL
HalGdamChInitRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaChSetingRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaChBlockSetingRtl8195a(
IN VOID *Data
);
VOID
HalGdmaChDisRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChEnRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChIsrEnAndDisRtl8195a (
IN VOID *Data
);
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChCleanAutoSrcRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChCleanAutoDstRtl8195a (
IN VOID *Data
);
u32
HalGdmaQueryDArRtl8195a(
IN VOID *Data
);
u32
HalGdmaQuerySArRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaQueryChEnRtl8195a (
IN VOID *Data
);
#ifdef CONFIG_CHIP_E_CUT
_LONG_CALL_ BOOL
HalGdmaChBlockSetingRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ u32
HalGdmaQueryDArRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ u32
HalGdmaQuerySArRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ BOOL
HalGdmaQueryChEnRtl8195a_V04 (
IN VOID *Data
);
#endif // #ifdef CONFIG_CHIP_E_CUT
#endif

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lib/fwlib/rtl8195a/rtl8195a_gpio.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_GPIO_H_
#define _RTL8195A_GPIO_H_
#include "hal_api.h"
#include "hal_gpio.h"
#define GPIO_PORTA_DR 0x00 // data register
#define GPIO_PORTA_DDR 0x04 // data direction
#define GPIO_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software
#define GPIO_PORTB_DR 0x0c // data register
#define GPIO_PORTB_DDR 0x10 // data direction
#define GPIO_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software
#define GPIO_PORTC_DR 0x18 // data register
#define GPIO_PORTC_DDR 0x1c // data direction
#define GPIO_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software
//1 Only the PORTA can be configured to generate interrupts
#define GPIO_INT_EN 0x30 // Interrupt enable register
#define GPIO_INT_MASK 0x34 // Interrupt mask
#define GPIO_INT_TYPE 0x38 // Interrupt type(level/edge) register
#define GPIO_INT_POLARITY 0x3C // Interrupt polarity(Active low/high) register
#define GPIO_INT_STATUS 0x40 // Interrupt status
#define GPIO_INT_RAWSTATUS 0x44 // Interrupt status without mask
#define GPIO_DEBOUNCE 0x48 // Interrupt signal debounce
#define GPIO_PORTA_EOI 0x4c // Clear interrupt
#define GPIO_EXT_PORTA 0x50 // GPIO IN read or OUT read back
#define GPIO_EXT_PORTB 0x54 // GPIO IN read or OUT read back
#define GPIO_EXT_PORTC 0x58 // GPIO IN read or OUT read back
#define GPIO_INT_SYNC 0x60 // Is level-sensitive interrupt being sync sith PCLK
enum {
HAL_GPIO_HIGHZ = 0,
HAL_GPIO_PULL_LOW = 1,
HAL_GPIO_PULL_HIGH = 2
};
//======================================================
// ROM Function prototype
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
static __inline HAL_Status
GPIO_Lock (
VOID
)
{
HAL_Status Status;
if (_pHAL_Gpio_Adapter->EnterCritical) {
_pHAL_Gpio_Adapter->EnterCritical();
}
if(_pHAL_Gpio_Adapter->Locked) {
Status = HAL_BUSY;
}
else {
_pHAL_Gpio_Adapter->Locked = 1;
Status = HAL_OK;
}
if (_pHAL_Gpio_Adapter->ExitCritical) {
_pHAL_Gpio_Adapter->ExitCritical();
}
return Status;
}
static __inline VOID
GPIO_UnLock (
VOID
)
{
if (_pHAL_Gpio_Adapter->EnterCritical) {
_pHAL_Gpio_Adapter->EnterCritical();
}
_pHAL_Gpio_Adapter->Locked = 0;
if (_pHAL_Gpio_Adapter->ExitCritical) {
_pHAL_Gpio_Adapter->ExitCritical();
}
}
_LONG_CALL_ extern u32
HAL_GPIO_IrqHandler_8195a(
IN VOID *pData
);
_LONG_CALL_ extern u32
HAL_GPIO_MbedIrqHandler_8195a(
IN VOID *pData
);
_LONG_CALL_ HAL_Status
HAL_GPIO_IntCtrl_8195a(
HAL_GPIO_PIN *GPIO_Pin,
u32 En
);
_LONG_CALL_ HAL_Status
HAL_GPIO_Init_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_DeInit_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_GPIO_PIN_STATE
HAL_GPIO_ReadPin_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_WritePin_8195a(
HAL_GPIO_PIN *GPIO_Pin,
HAL_GPIO_PIN_STATE Pin_State
);
_LONG_CALL_ HAL_Status
HAL_GPIO_RegIrq_8195a(
IN PIRQ_HANDLE pIrqHandle
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UnRegIrq_8195a(
IN PIRQ_HANDLE pIrqHandle
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UserRegIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin,
VOID *IrqHandler,
VOID *IrqData
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UserUnRegIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_MaskIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UnMaskIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_IntDebounce_8195a(
HAL_GPIO_PIN *GPIO_Pin,
u8 Enable
);
_LONG_CALL_ u32
HAL_GPIO_GetIPPinName_8195a(
u32 chip_pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_PullCtrl_8195a(
u32 chip_pin,
u8 pull_type
);
_LONG_CALL_ u32
GPIO_GetChipPinName_8195a(
u32 port,
u32 pin
);
_LONG_CALL_ VOID
GPIO_PullCtrl_8195a(
u32 chip_pin,
u8 pull_type
);
_LONG_CALL_ VOID
GPIO_Int_SetType_8195a(
u8 pin_num,
u8 int_mode
);
_LONG_CALL_ HAL_Status HAL_GPIO_IntCtrl_8195aV02(HAL_GPIO_PIN *GPIO_Pin, u32 En);
_LONG_CALL_ u32 GPIO_Int_Clear_8195aV02(u32 irq_clr);
HAL_Status
HAL_GPIO_ClearISR_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
/********** HAL In-Line Functions **********/
/**
* @brief De-Initializes a GPIO Pin, reset it as default setting.
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval HAL_Status
*/
static __inline VOID
HAL_GPIO_DeInit(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_DeInit_8195a(GPIO_Pin);
}
/**
* @brief Reads the specified input port pin.
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval The input port pin current status(High or Low).
*/
static __inline s32
HAL_GPIO_ReadPin(
HAL_GPIO_PIN *GPIO_Pin
)
{
return (s32)HAL_GPIO_ReadPin_8195a(GPIO_Pin);
}
/**
* @brief Write the specified output port pin.
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @param Pin_State: The state going to be set to the assigned GPIO pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_WritePin(
HAL_GPIO_PIN *GPIO_Pin,
u32 Value
)
{
HAL_GPIO_WritePin_8195a(GPIO_Pin, (HAL_GPIO_PIN_STATE)Value);
}
/**
* @brief To register a user interrupt handler for a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @param IrqHandler: The IRQ handler to be assigned to the specified pin
*
* @param IrqData: The pointer will be pass the the IRQ handler
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UserRegIrq(
HAL_GPIO_PIN *GPIO_Pin,
VOID *IrqHandler,
VOID *IrqData
)
{
HAL_GPIO_UserRegIrq_8195a(GPIO_Pin, IrqHandler, IrqData);
}
/**
* @brief To un-register a user interrupt handler for a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UserUnRegIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_UserUnRegIrq_8195a(GPIO_Pin);
}
/**
* @brief Enable/Disable GPIO interrupt
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
*
* @param En: Enable (1) or Disable (0)
*
* @retval HAL_Status
*/
static __inline VOID
HAL_GPIO_IntCtrl(
HAL_GPIO_PIN *GPIO_Pin,
u32 En
)
{
HAL_GPIO_IntCtrl_8195a(GPIO_Pin, En);
}
/**
* @brief Mask the interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_MaskIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_MaskIrq_8195a(GPIO_Pin);
}
/**
* @brief UnMask the interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UnMaskIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_ClearISR_8195a(GPIO_Pin);
HAL_GPIO_UnMaskIrq_8195a(GPIO_Pin);
}
#endif // end of "#define _RTL8195A_GPIO_H_"

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_I2C_H_
#define _RTL8195A_I2C_H_
#include "hal_api.h"
//================ Register Bit Field ==================
//2 REG_DW_I2C_IC_CON
#define BIT_IC_CON_IC_SLAVE_DISABLE BIT(6)
#define BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE 6
#define BIT_MASK_IC_CON_IC_SLAVE_DISABLE 0x1
#define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(x) (((x) & BIT_MASK_IC_CON_IC_SLAVE_DISABLE) << BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE)
#define BIT_IC_CON_IC_RESTART_EN BIT(5)
#define BIT_SHIFT_IC_CON_IC_RESTART_EN 5
#define BIT_MASK_IC_CON_IC_RESTART_EN 0x1
#define BIT_CTRL_IC_CON_IC_RESTART_EN(x) (((x) & BIT_MASK_IC_CON_IC_RESTART_EN) << BIT_SHIFT_IC_CON_IC_RESTART_EN)
#define BIT_IC_CON_IC_10BITADDR_MASTER BIT(4)
#define BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER 4
#define BIT_MASK_IC_CON_IC_10BITADDR_MASTER 0x1
#define BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER)
#define BIT_IC_CON_IC_10BITADDR_SLAVE BIT(3)
#define BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE 3
#define BIT_MASK_IC_CON_IC_10BITADDR_SLAVE 0x1
#define BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_SLAVE) << BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE)
#define BIT_SHIFT_IC_CON_SPEED 1
#define BIT_MASK_IC_CON_SPEED 0x3
#define BIT_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
#define BIT_CTRL_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
#define BIT_GET_IC_CON_SPEED(x) (((x) >> BIT_SHIFT_IC_CON_SPEED) & BIT_MASK_IC_CON_SPEED)
#define BIT_IC_CON_MASTER_MODE BIT(0)
#define BIT_SHIFT_IC_CON_MASTER_MODE 0
#define BIT_MASK_IC_CON_MASTER_MODE 0x1
#define BIT_CTRL_IC_CON_MASTER_MODE(x) (((x) & BIT_MASK_IC_CON_MASTER_MODE) << BIT_SHIFT_IC_CON_MASTER_MODE)
//2 REG_DW_I2C_IC_TAR
#define BIT_IC_TAR_IC_10BITADDR_MASTER BIT(12)
#define BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER 12
#define BIT_MASK_IC_TAR_IC_10BITADDR_MASTER 0x1
#define BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_TAR_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER)
#define BIT_IC_TAR_SPECIAL BIT(11)
#define BIT_SHIFT_IC_TAR_SPECIAL 11
#define BIT_MASK_IC_TAR_SPECIAL 0x1
#define BIT_CTRL_IC_TAR_SPECIAL(x) (((x) & BIT_MASK_IC_TAR_SPECIAL) << BIT_SHIFT_IC_TAR_SPECIAL)
#define BIT_IC_TAR_GC_OR_START BIT(10)
#define BIT_SHIFT_IC_TAR_GC_OR_START 10
#define BIT_MASK_IC_TAR_GC_OR_START 0x1
#define BIT_CTRL_IC_TAR_GC_OR_START(x) (((x) & BIT_MASK_IC_TAR_GC_OR_START) << BIT_SHIFT_IC_TAR_GC_OR_START)
#define BIT_SHIFT_IC_TAR 0
#define BIT_MASK_IC_TAR 0x3ff
#define BIT_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
#define BIT_CTRL_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
#define BIT_GET_IC_TAR(x) (((x) >> BIT_SHIFT_IC_TAR) & BIT_MASK_IC_TAR)
//2 REG_DW_I2C_IC_SAR
#define BIT_SHIFT_IC_SAR 0
#define BIT_MASK_IC_SAR 0x3ff
#define BIT_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
#define BIT_CTRL_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
#define BIT_GET_IC_SAR(x) (((x) >> BIT_SHIFT_IC_SAR) & BIT_MASK_IC_SAR)
//2 REG_DW_I2C_IC_HS_MADDR
#define BIT_SHIFT_IC_HS_MADDR 0
#define BIT_MASK_IC_HS_MADDR 0x7
#define BIT_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
#define BIT_CTRL_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
#define BIT_GET_IC_HS_MADDR(x) (((x) >> BIT_SHIFT_IC_HS_MADDR) & BIT_MASK_IC_HS_MADDR)
//2 REG_DW_I2C_IC_DATA_CMD
#define BIT_IC_DATA_CMD_RESTART BIT(10)
#define BIT_SHIFT_IC_DATA_CMD_RESTART 10
#define BIT_MASK_IC_DATA_CMD_RESTART 0x1
#define BIT_CTRL_IC_DATA_CMD_RESTART(x) (((x) & BIT_MASK_IC_DATA_CMD_RESTART) << BIT_SHIFT_IC_DATA_CMD_RESTART)
#define BIT_IC_DATA_CMD_STOP BIT(9)
#define BIT_SHIFT_IC_DATA_CMD_STOP 9
#define BIT_MASK_IC_DATA_CMD_STOP 0x1
#define BIT_CTRL_IC_DATA_CMD_STOP(x) (((x) & BIT_MASK_IC_DATA_CMD_STOP) << BIT_SHIFT_IC_DATA_CMD_STOP)
#define BIT_IC_DATA_CMD_CMD BIT(8)
#define BIT_SHIFT_IC_DATA_CMD_CMD 8
#define BIT_MASK_IC_DATA_CMD_CMD 0x1
#define BIT_CTRL_IC_DATA_CMD_CMD(x) (((x) & BIT_MASK_IC_DATA_CMD_CMD) << BIT_SHIFT_IC_DATA_CMD_CMD)
#define BIT_SHIFT_IC_DATA_CMD_DAT 0
#define BIT_MASK_IC_DATA_CMD_DAT 0xff
#define BIT_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
#define BIT_CTRL_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
#define BIT_GET_IC_DATA_CMD_DAT(x) (((x) >> BIT_SHIFT_IC_DATA_CMD_DAT) & BIT_MASK_IC_DATA_CMD_DAT)
//2 REG_DW_I2C_IC_SS_SCL_HCNT
#define BIT_SHIFT_IC_SS_SCL_HCNT 0
#define BIT_MASK_IC_SS_SCL_HCNT 0xffff
#define BIT_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
#define BIT_CTRL_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
#define BIT_GET_IC_SS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_HCNT) & BIT_MASK_IC_SS_SCL_HCNT)
//2 REG_DW_I2C_IC_SS_SCL_LCNT
#define BIT_SHIFT_IC_SS_SCL_LCNT 0
#define BIT_MASK_IC_SS_SCL_LCNT 0xffff
#define BIT_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
#define BIT_CTRL_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
#define BIT_GET_IC_SS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_LCNT) & BIT_MASK_IC_SS_SCL_LCNT)
//2 REG_DW_I2C_IC_FS_SCL_HCNT
#define BIT_SHIFT_IC_FS_SCL_HCNT 0
#define BIT_MASK_IC_FS_SCL_HCNT 0xffff
#define BIT_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
#define BIT_CTRL_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
#define BIT_GET_IC_FS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_HCNT) & BIT_MASK_IC_FS_SCL_HCNT)
//2 REG_DW_I2C_IC_FS_SCL_LCNT
#define BIT_SHIFT_IC_FS_SCL_LCNT 0
#define BIT_MASK_IC_FS_SCL_LCNT 0xffff
#define BIT_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
#define BIT_CTRL_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
#define BIT_GET_IC_FS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_LCNT) & BIT_MASK_IC_FS_SCL_LCNT)
//2 REG_DW_I2C_IC_HS_SCL_HCNT
#define BIT_SHIFT_IC_HS_SCL_HCNT 0
#define BIT_MASK_IC_HS_SCL_HCNT 0xffff
#define BIT_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
#define BIT_CTRL_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
#define BIT_GET_IC_HS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_HCNT) & BIT_MASK_IC_HS_SCL_HCNT)
//2 REG_DW_I2C_IC_HS_SCL_LCNT
#define BIT_SHIFT_IC_HS_SCL_LCNT 0
#define BIT_MASK_IC_HS_SCL_LCNT 0xffff
#define BIT_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
#define BIT_CTRL_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
#define BIT_GET_IC_HS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_LCNT) & BIT_MASK_IC_HS_SCL_LCNT)
//2 REG_DW_I2C_IC_INTR_STAT
#define BIT_IC_INTR_STAT_R_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL 11
#define BIT_MASK_IC_INTR_STAT_R_GEN_CALL 0x1
#define BIT_CTRL_IC_INTR_STAT_R_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_GEN_CALL) << BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL)
#define BIT_IC_INTR_STAT_R_START_DET BIT(10)
#define BIT_SHIFT_IC_INTR_STAT_R_START_DET 10
#define BIT_MASK_IC_INTR_STAT_R_START_DET 0x1
#define BIT_CTRL_IC_INTR_STAT_R_START_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_START_DET) << BIT_SHIFT_IC_INTR_STAT_R_START_DET)
#define BIT_IC_INTR_STAT_R_STOP_DET BIT(9)
#define BIT_SHIFT_IC_INTR_STAT_R_STOP_DET 9
#define BIT_MASK_IC_INTR_STAT_R_STOP_DET 0x1
#define BIT_CTRL_IC_INTR_STAT_R_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_STOP_DET) << BIT_SHIFT_IC_INTR_STAT_R_STOP_DET)
#define BIT_IC_INTR_STAT_R_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY 8
#define BIT_MASK_IC_INTR_STAT_R_ACTIVITY 0x1
#define BIT_CTRL_IC_INTR_STAT_R_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_ACTIVITY) << BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY)
#define BIT_IC_INTR_STAT_R_RX_DONE BIT(7)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_DONE 7
#define BIT_MASK_IC_INTR_STAT_R_RX_DONE 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_DONE) << BIT_SHIFT_IC_INTR_STAT_R_RX_DONE)
#define BIT_IC_INTR_STAT_R_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT 6
#define BIT_MASK_IC_INTR_STAT_R_TX_ABRT 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_ABRT) << BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT)
#define BIT_IC_INTR_STAT_R_RD_REQ BIT(5)
#define BIT_SHIFT_IC_INTR_STAT_R_RD_REQ 5
#define BIT_MASK_IC_INTR_STAT_R_RD_REQ 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RD_REQ) << BIT_SHIFT_IC_INTR_STAT_R_RD_REQ)
#define BIT_IC_INTR_STAT_R_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY 4
#define BIT_MASK_IC_INTR_STAT_R_TX_EMPTY 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_EMPTY) << BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY)
#define BIT_IC_INTR_STAT_R_TX_OVER BIT(3)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_OVER 3
#define BIT_MASK_IC_INTR_STAT_R_TX_OVER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_TX_OVER)
#define BIT_IC_INTR_STAT_R_RX_FULL BIT(2)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_FULL 2
#define BIT_MASK_IC_INTR_STAT_R_RX_FULL 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_FULL) << BIT_SHIFT_IC_INTR_STAT_R_RX_FULL)
#define BIT_IC_INTR_STAT_R_RX_OVER BIT(1)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_OVER 1
#define BIT_MASK_IC_INTR_STAT_R_RX_OVER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_RX_OVER)
#define BIT_IC_INTR_STAT_R_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER 0
#define BIT_MASK_IC_INTR_STAT_R_RX_UNDER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_UNDER) << BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER)
//2 REG_DW_I2C_IC_INTR_MASK
#define BIT_IC_INTR_MASK_M_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL 11
#define BIT_MASK_IC_INTR_MASK_M_GEN_CALL 0x1
#define BIT_CTRL_IC_INTR_MASK_M_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_GEN_CALL) << BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL)
#define BIT_IC_INTR_MASK_M_START_DET BIT(10)
#define BIT_SHIFT_IC_INTR_MASK_M_START_DET 10
#define BIT_MASK_IC_INTR_MASK_M_START_DET 0x1
#define BIT_CTRL_IC_INTR_MASK_M_START_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_START_DET) << BIT_SHIFT_IC_INTR_MASK_M_START_DET)
#define BIT_IC_INTR_MASK_M_STOP_DET BIT(9)
#define BIT_SHIFT_IC_INTR_MASK_M_STOP_DET 9
#define BIT_MASK_IC_INTR_MASK_M_STOP_DET 0x1
#define BIT_CTRL_IC_INTR_MASK_M_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_STOP_DET) << BIT_SHIFT_IC_INTR_MASK_M_STOP_DET)
#define BIT_IC_INTR_MASK_M_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY 8
#define BIT_MASK_IC_INTR_MASK_M_ACTIVITY 0x1
#define BIT_CTRL_IC_INTR_MASK_M_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_ACTIVITY) << BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY)
#define BIT_IC_INTR_MASK_M_RX_DONE BIT(7)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_DONE 7
#define BIT_MASK_IC_INTR_MASK_M_RX_DONE 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_DONE) << BIT_SHIFT_IC_INTR_MASK_M_RX_DONE)
#define BIT_IC_INTR_MASK_M_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT 6
#define BIT_MASK_IC_INTR_MASK_M_TX_ABRT 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_ABRT) << BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT)
#define BIT_IC_INTR_MASK_M_RD_REQ BIT(5)
#define BIT_SHIFT_IC_INTR_MASK_M_RD_REQ 5
#define BIT_MASK_IC_INTR_MASK_M_RD_REQ 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RD_REQ) << BIT_SHIFT_IC_INTR_MASK_M_RD_REQ)
#define BIT_IC_INTR_MASK_M_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY 4
#define BIT_MASK_IC_INTR_MASK_M_TX_EMPTY 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_EMPTY) << BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY)
#define BIT_IC_INTR_MASK_M_TX_OVER BIT(3)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_OVER 3
#define BIT_MASK_IC_INTR_MASK_M_TX_OVER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_TX_OVER)
#define BIT_IC_INTR_MASK_M_RX_FULL BIT(2)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_FULL 2
#define BIT_MASK_IC_INTR_MASK_M_RX_FULL 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_FULL) << BIT_SHIFT_IC_INTR_MASK_M_RX_FULL)
#define BIT_IC_INTR_MASK_M_RX_OVER BIT(1)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_OVER 1
#define BIT_MASK_IC_INTR_MASK_M_RX_OVER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_RX_OVER)
#define BIT_IC_INTR_MASK_M_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER 0
#define BIT_MASK_IC_INTR_MASK_M_RX_UNDER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_UNDER) << BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER)
//2 REG_DW_I2C_IC_RAW_INTR_STAT
#define BIT_IC_RAW_INTR_STAT_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL 11
#define BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_GEN_CALL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL) << BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL)
#define BIT_IC_RAW_INTR_STAT_START_DET BIT(10)
#define BIT_SHIFT_IC_RAW_INTR_STAT_START_DET 10
#define BIT_MASK_IC_RAW_INTR_STAT_START_DET 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_START_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_START_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_START_DET)
#define BIT_IC_RAW_INTR_STAT_STOP_DET BIT(9)
#define BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET 9
#define BIT_MASK_IC_RAW_INTR_STAT_STOP_DET 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_STOP_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_STOP_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET)
#define BIT_IC_RAW_INTR_STAT_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY 8
#define BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_ACTIVITY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY) << BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY)
#define BIT_IC_RAW_INTR_STAT_RX_DONE BIT(7)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE 7
#define BIT_MASK_IC_RAW_INTR_STAT_RX_DONE 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_DONE(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_DONE) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE)
#define BIT_IC_RAW_INTR_STAT_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT 6
#define BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_ABRT(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT)
#define BIT_IC_RAW_INTR_STAT_RD_REQ BIT(5)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ 5
#define BIT_MASK_IC_RAW_INTR_STAT_RD_REQ 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RD_REQ(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RD_REQ) << BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ)
#define BIT_IC_RAW_INTR_STAT_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY 4
#define BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_EMPTY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY)
#define BIT_IC_RAW_INTR_STAT_TX_OVER BIT(3)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER 3
#define BIT_MASK_IC_RAW_INTR_STAT_TX_OVER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER)
#define BIT_IC_RAW_INTR_STAT_RX_FULL BIT(2)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL 2
#define BIT_MASK_IC_RAW_INTR_STAT_RX_FULL 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_FULL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_FULL) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL)
#define BIT_IC_RAW_INTR_STAT_RX_OVER BIT(1)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER 1
#define BIT_MASK_IC_RAW_INTR_STAT_RX_OVER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER)
#define BIT_IC_RAW_INTR_STAT_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER 0
#define BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_UNDER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER)
//2 REG_DW_I2C_IC_RX_TL
#define BIT_SHIFT_IC_RX_TL 0
#define BIT_MASK_IC_RX_TL 0xff
#define BIT_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
#define BIT_CTRL_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
#define BIT_GET_IC_RX_TL(x) (((x) >> BIT_SHIFT_IC_RX_TL) & BIT_MASK_IC_RX_TL)
//2 REG_DW_I2C_IC_TX_TL
#define BIT_SHIFT_IC_TX_TL 0
#define BIT_MASK_IC_TX_TL 0xff
#define BIT_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
#define BIT_CTRL_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
#define BIT_GET_IC_TX_TL(x) (((x) >> BIT_SHIFT_IC_TX_TL) & BIT_MASK_IC_TX_TL)
//2 REG_DW_I2C_IC_CLR_INTR
#define BIT_IC_CLR_INTR BIT(0)
#define BIT_SHIFT_IC_CLR_INTR 0
#define BIT_MASK_IC_CLR_INTR 0x1
#define BIT_CTRL_IC_CLR_INTR(x) (((x) & BIT_MASK_IC_CLR_INTR) << BIT_SHIFT_IC_CLR_INTR)
//2 REG_DW_I2C_IC_CLR_RX_UNDER
#define BIT_IC_CLR_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_CLR_RX_UNDER 0
#define BIT_MASK_IC_CLR_RX_UNDER 0x1
#define BIT_CTRL_IC_CLR_RX_UNDER(x) (((x) & BIT_MASK_IC_CLR_RX_UNDER) << BIT_SHIFT_IC_CLR_RX_UNDER)
//2 REG_DW_I2C_IC_CLR_RX_OVER
#define BIT_IC_CLR_RX_OVER BIT(0)
#define BIT_SHIFT_IC_CLR_RX_OVER 0
#define BIT_MASK_IC_CLR_RX_OVER 0x1
#define BIT_CTRL_IC_CLR_RX_OVER(x) (((x) & BIT_MASK_IC_CLR_RX_OVER) << BIT_SHIFT_IC_CLR_RX_OVER)
//2 REG_DW_I2C_IC_CLR_TX_OVER
#define BIT_IC_CLR_TX_OVER BIT(0)
#define BIT_SHIFT_IC_CLR_TX_OVER 0
#define BIT_MASK_IC_CLR_TX_OVER 0x1
#define BIT_CTRL_IC_CLR_TX_OVER(x) (((x) & BIT_MASK_IC_CLR_TX_OVER) << BIT_SHIFT_IC_CLR_TX_OVER)
//2 REG_DW_I2C_IC_CLR_RD_REQ
#define BIT_IC_CLR_RD_REQ BIT(0)
#define BIT_SHIFT_IC_CLR_RD_REQ 0
#define BIT_MASK_IC_CLR_RD_REQ 0x1
#define BIT_CTRL_IC_CLR_RD_REQ(x) (((x) & BIT_MASK_IC_CLR_RD_REQ) << BIT_SHIFT_IC_CLR_RD_REQ)
//2 REG_DW_I2C_IC_CLR_TX_ABRT
#define BIT_CLR_RD_REQ BIT(0)
#define BIT_SHIFT_CLR_RD_REQ 0
#define BIT_MASK_CLR_RD_REQ 0x1
#define BIT_CTRL_CLR_RD_REQ(x) (((x) & BIT_MASK_CLR_RD_REQ) << BIT_SHIFT_CLR_RD_REQ)
//2 REG_DW_I2C_IC_CLR_RX_DONE
#define BIT_IC_CLR_RX_DONE BIT(0)
#define BIT_SHIFT_IC_CLR_RX_DONE 0
#define BIT_MASK_IC_CLR_RX_DONE 0x1
#define BIT_CTRL_IC_CLR_RX_DONE(x) (((x) & BIT_MASK_IC_CLR_RX_DONE) << BIT_SHIFT_IC_CLR_RX_DONE)
//2 REG_DW_I2C_IC_CLR_ACTIVITY
#define BIT_IC_CLR_ACTIVITY BIT(0)
#define BIT_SHIFT_IC_CLR_ACTIVITY 0
#define BIT_MASK_IC_CLR_ACTIVITY 0x1
#define BIT_CTRL_IC_CLR_ACTIVITY(x) (((x) & BIT_MASK_IC_CLR_ACTIVITY) << BIT_SHIFT_IC_CLR_ACTIVITY)
//2 REG_DW_I2C_IC_CLR_STOP_DET
#define BIT_IC_CLR_STOP_DET BIT(0)
#define BIT_SHIFT_IC_CLR_STOP_DET 0
#define BIT_MASK_IC_CLR_STOP_DET 0x1
#define BIT_CTRL_IC_CLR_STOP_DET(x) (((x) & BIT_MASK_IC_CLR_STOP_DET) << BIT_SHIFT_IC_CLR_STOP_DET)
//2 REG_DW_I2C_IC_CLR_START_DET
#define BIT_IC_CLR_START_DET BIT(0)
#define BIT_SHIFT_IC_CLR_START_DET 0
#define BIT_MASK_IC_CLR_START_DET 0x1
#define BIT_CTRL_IC_CLR_START_DET(x) (((x) & BIT_MASK_IC_CLR_START_DET) << BIT_SHIFT_IC_CLR_START_DET)
//2 REG_DW_I2C_IC_CLR_GEN_CALL
#define BIT_IC_CLR_GEN_CALL BIT(0)
#define BIT_SHIFT_IC_CLR_GEN_CALL 0
#define BIT_MASK_IC_CLR_GEN_CALL 0x1
#define BIT_CTRL_IC_CLR_GEN_CALL(x) (((x) & BIT_MASK_IC_CLR_GEN_CALL) << BIT_SHIFT_IC_CLR_GEN_CALL)
//2 REG_DW_I2C_IC_ENABLE
#define BIT_IC_ENABLE BIT(0)
#define BIT_SHIFT_IC_ENABLE 0
#define BIT_MASK_IC_ENABLE 0x1
#define BIT_CTRL_IC_ENABLE(x) (((x) & BIT_MASK_IC_ENABLE) << BIT_SHIFT_IC_ENABLE)
//2 REG_DW_I2C_IC_STATUS
#define BIT_IC_STATUS_SLV_ACTIVITY BIT(6)
#define BIT_SHIFT_IC_STATUS_SLV_ACTIVITY 6
#define BIT_MASK_IC_STATUS_SLV_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_SLV_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_SLV_ACTIVITY) << BIT_SHIFT_IC_STATUS_SLV_ACTIVITY)
#define BIT_IC_STATUS_MST_ACTIVITY BIT(5)
#define BIT_SHIFT_IC_STATUS_MST_ACTIVITY 5
#define BIT_MASK_IC_STATUS_MST_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_MST_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_MST_ACTIVITY) << BIT_SHIFT_IC_STATUS_MST_ACTIVITY)
#define BIT_IC_STATUS_RFF BIT(4)
#define BIT_SHIFT_IC_STATUS_RFF 4
#define BIT_MASK_IC_STATUS_RFF 0x1
#define BIT_CTRL_IC_STATUS_RFF(x) (((x) & BIT_MASK_IC_STATUS_RFF) << BIT_SHIFT_IC_STATUS_RFF)
#define BIT_IC_STATUS_RFNE BIT(3)
#define BIT_SHIFT_IC_STATUS_RFNE 3
#define BIT_MASK_IC_STATUS_RFNE 0x1
#define BIT_CTRL_IC_STATUS_RFNE(x) (((x) & BIT_MASK_IC_STATUS_RFNE) << BIT_SHIFT_IC_STATUS_RFNE)
#define BIT_IC_STATUS_TFE BIT(2)
#define BIT_SHIFT_IC_STATUS_TFE 2
#define BIT_MASK_IC_STATUS_TFE 0x1
#define BIT_CTRL_IC_STATUS_TFE(x) (((x) & BIT_MASK_IC_STATUS_TFE) << BIT_SHIFT_IC_STATUS_TFE)
#define BIT_IC_STATUS_TFNF BIT(1)
#define BIT_SHIFT_IC_STATUS_TFNF 1
#define BIT_MASK_IC_STATUS_TFNF 0x1
#define BIT_CTRL_IC_STATUS_TFNF(x) (((x) & BIT_MASK_IC_STATUS_TFNF) << BIT_SHIFT_IC_STATUS_TFNF)
#define BIT_IC_STATUS_ACTIVITY BIT(0)
#define BIT_SHIFT_IC_STATUS_ACTIVITY 0
#define BIT_MASK_IC_STATUS_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_ACTIVITY) << BIT_SHIFT_IC_STATUS_ACTIVITY)
//2 REG_DW_I2C_IC_TXFLR
#define BIT_SHIFT_IC_TXFLR 0
#define BIT_MASK_IC_TXFLR 0x3f
#define BIT_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
#define BIT_CTRL_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
#define BIT_GET_IC_TXFLR(x) (((x) >> BIT_SHIFT_IC_TXFLR) & BIT_MASK_IC_TXFLR)
//2 REG_DW_I2C_IC_RXFLR
#define BIT_SHIFT_IC_RXFLR 0
#define BIT_MASK_IC_RXFLR 0x1f
#define BIT_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
#define BIT_CTRL_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
#define BIT_GET_IC_RXFLR(x) (((x) >> BIT_SHIFT_IC_RXFLR) & BIT_MASK_IC_RXFLR)
//2 REG_DW_I2C_IC_SDA_HOLD
#define BIT_SHIFT_IC_SDA_HOLD 0
#define BIT_MASK_IC_SDA_HOLD 0xffff
#define BIT_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
#define BIT_CTRL_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
#define BIT_GET_IC_SDA_HOLD(x) (((x) >> BIT_SHIFT_IC_SDA_HOLD) & BIT_MASK_IC_SDA_HOLD)
//2 REG_DW_I2C_IC_TX_ABRT_SOURCE
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX BIT(15)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 15
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST BIT(14)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 14
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO BIT(13)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 13
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO)
#define BIT_IC_TX_ABRT_SOURCE_ARB_LOST BIT(12)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST 12
#define BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ARB_LOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS BIT(11)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 11
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT BIT(10)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 10
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT BIT(9)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 9
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT BIT(8)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 8
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET BIT(7)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 7
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET BIT(6)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 6
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ BIT(5)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 5
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK BIT(4)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 4
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK BIT(3)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 3
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK BIT(2)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 2
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK BIT(1)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 1
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK BIT(0)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK)
//2 REG_DW_I2C_IC_SLV_DATA_NACK_ONLY
#define BIT_IC_SLV_DATA_NACK_ONLY BIT(0)
#define BIT_SHIFT_IC_SLV_DATA_NACK_ONLY 0
#define BIT_MASK_IC_SLV_DATA_NACK_ONLY 0x1
#define BIT_CTRL_IC_SLV_DATA_NACK_ONLY(x) (((x) & BIT_MASK_IC_SLV_DATA_NACK_ONLY) << BIT_SHIFT_IC_SLV_DATA_NACK_ONLY)
//2 REG_DW_I2C_IC_DMA_CR
#define BIT_IC_DMA_CR_TDMAE BIT(1)
#define BIT_SHIFT_IC_DMA_CR_TDMAE 1
#define BIT_MASK_IC_DMA_CR_TDMAE 0x1
#define BIT_CTRL_IC_DMA_CR_TDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_TDMAE) << BIT_SHIFT_IC_DMA_CR_TDMAE)
#define BIT_IC_DMA_CR_RDMAE BIT(0)
#define BIT_SHIFT_IC_DMA_CR_RDMAE 0
#define BIT_MASK_IC_DMA_CR_RDMAE 0x1
#define BIT_CTRL_IC_DMA_CR_RDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_RDMAE) << BIT_SHIFT_IC_DMA_CR_RDMAE)
//2 REG_DW_I2C_IC_DMA_TDLR
#define BIT_SHIFT_IC_DMA_TDLR_DMATDL 0
#define BIT_MASK_IC_DMA_TDLR_DMATDL 0x1f
#define BIT_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
#define BIT_CTRL_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
#define BIT_GET_IC_DMA_TDLR_DMATDL(x) (((x) >> BIT_SHIFT_IC_DMA_TDLR_DMATDL) & BIT_MASK_IC_DMA_TDLR_DMATDL)
//2 REG_DW_I2C_IC_DMA_RDLR
#define BIT_SHIFT_IC_DMA_RDLR_DMARDL 0
#define BIT_MASK_IC_DMA_RDLR_DMARDL 0xf
#define BIT_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
#define BIT_CTRL_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
#define BIT_GET_IC_DMA_RDLR_DMARDL(x) (((x) >> BIT_SHIFT_IC_DMA_RDLR_DMARDL) & BIT_MASK_IC_DMA_RDLR_DMARDL)
//2 REG_DW_I2C_IC_SDA_SETUP
#define BIT_SHIFT_IC_SDA_SETUP 0
#define BIT_MASK_IC_SDA_SETUP 0xff
#define BIT_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
#define BIT_CTRL_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
#define BIT_GET_IC_SDA_SETUP(x) (((x) >> BIT_SHIFT_IC_SDA_SETUP) & BIT_MASK_IC_SDA_SETUP)
//2 REG_DW_I2C_IC_ACK_GENERAL_CALL
#define BIT_IC_ACK_GENERAL_CALL BIT(0)
#define BIT_SHIFT_IC_ACK_GENERAL_CALL 0
#define BIT_MASK_IC_ACK_GENERAL_CALL 0x1
#define BIT_CTRL_IC_ACK_GENERAL_CALL(x) (((x) & BIT_MASK_IC_ACK_GENERAL_CALL) << BIT_SHIFT_IC_ACK_GENERAL_CALL)
//2 REG_DW_I2C_IC_ENABLE_STATUS
#define BIT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST BIT(2)
#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 2
#define BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_SLV_RX_DATA_LOST(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST)
#define BIT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY BIT(1)
#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 1
#define BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY)
#define BIT_IC_ENABLE_STATUS_IC_EN BIT(0)
#define BIT_SHIFT_IC_ENABLE_STATUS_IC_EN 0
#define BIT_MASK_IC_ENABLE_STATUS_IC_EN 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_IC_EN(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_IC_EN) << BIT_SHIFT_IC_ENABLE_STATUS_IC_EN)
//2 REG_DW_I2C_IC_COMP_PARAM_1
#define BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 16
#define BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 0xff
#define BIT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_CTRL_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_GET_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 8
#define BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 0xff
#define BIT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_CTRL_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_GET_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS BIT(7)
#define BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 7
#define BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS) << BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS)
#define BIT_IC_COMP_PARAM_1_HAS_DMA BIT(6)
#define BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA 6
#define BIT_MASK_IC_COMP_PARAM_1_HAS_DMA 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_HAS_DMA(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HAS_DMA) << BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA)
#define BIT_IC_COMP_PARAM_1_INTR_IO BIT(5)
#define BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO 5
#define BIT_MASK_IC_COMP_PARAM_1_INTR_IO 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_INTR_IO(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_INTR_IO) << BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO)
#define BIT_IC_COMP_PARAM_1_HC_COUNT_VALUES BIT(4)
#define BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES 4
#define BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_HC_COUNT_VALUES(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES) << BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES)
#define BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE 2
#define BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE 0x3
#define BIT_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_CTRL_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_GET_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH 0
#define BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH 0x3
#define BIT_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
#define BIT_CTRL_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
#define BIT_GET_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH)
//2 REG_DW_I2C_IC_COMP_VERSION
#define BIT_SHIFT_IC_COMP_VERSION 0
#define BIT_MASK_IC_COMP_VERSION 0xffffffffL
#define BIT_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
#define BIT_CTRL_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
#define BIT_GET_IC_COMP_VERSION(x) (((x) >> BIT_SHIFT_IC_COMP_VERSION) & BIT_MASK_IC_COMP_VERSION)
//2 REG_DW_I2C_IC_COMP_TYPE
#define BIT_SHIFT_IC_COMP_TYPE 0
#define BIT_MASK_IC_COMP_TYPE 0xffffffffL
#define BIT_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
#define BIT_CTRL_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
#define BIT_GET_IC_COMP_TYPE(x) (((x) >> BIT_SHIFT_IC_COMP_TYPE) & BIT_MASK_IC_COMP_TYPE)
//======================== Register Address Definition ========================
#define REG_DW_I2C_IC_CON 0x0000
#define REG_DW_I2C_IC_TAR 0x0004
#define REG_DW_I2C_IC_SAR 0x0008
#define REG_DW_I2C_IC_HS_MADDR 0x000C
#define REG_DW_I2C_IC_DATA_CMD 0x0010
#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014
#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018
#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C
#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020
#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024
#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028
#define REG_DW_I2C_IC_INTR_STAT 0x002C
#define REG_DW_I2C_IC_INTR_MASK 0x0030
#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034
#define REG_DW_I2C_IC_RX_TL 0x0038
#define REG_DW_I2C_IC_TX_TL 0x003C
#define REG_DW_I2C_IC_CLR_INTR 0x0040
#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044
#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048
#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C
#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050
#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054
#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058
#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C
#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060
#define REG_DW_I2C_IC_CLR_START_DET 0x0064
#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068
#define REG_DW_I2C_IC_ENABLE 0x006C
#define REG_DW_I2C_IC_STATUS 0x0070
#define REG_DW_I2C_IC_TXFLR 0x0074
#define REG_DW_I2C_IC_RXFLR 0x0078
#define REG_DW_I2C_IC_SDA_HOLD 0x007C
#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080
#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084
#define REG_DW_I2C_IC_DMA_CR 0x0088
#define REG_DW_I2C_IC_DMA_TDLR 0x008C
#define REG_DW_I2C_IC_DMA_RDLR 0x0090
#define REG_DW_I2C_IC_SDA_SETUP 0x0094
#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098
#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C
#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4
#define REG_DW_I2C_IC_COMP_VERSION 0x00F8
#define REG_DW_I2C_IC_COMP_TYPE 0x00FC
//======================================================
// I2C related enumeration
// I2C Address Mode
typedef enum _I2C_ADDR_MODE_ {
I2C_ADDR_7BIT = 0,
I2C_ADDR_10BIT = 1,
}I2C_ADDR_MODE,*PI2C_ADDR_MODE;
// I2C Speed Mode
typedef enum _I2C_SPD_MODE_ {
I2C_SS_MODE = 1,
I2C_FS_MODE = 2,
I2C_HS_MODE = 3,
}I2C_SPD_MODE,*PI2C_SPD_MODE;
//I2C Timing Parameters
#define I2C_SS_MIN_SCL_HTIME 4000 //the unit is ns.
#define I2C_SS_MIN_SCL_LTIME 4700 //the unit is ns.
#define I2C_FS_MIN_SCL_HTIME 600 //the unit is ns.
#define I2C_FS_MIN_SCL_LTIME 1300 //the unit is ns.
#define I2C_HS_MIN_SCL_HTIME_100 60 //the unit is ns, with bus loading = 100pf
#define I2C_HS_MIN_SCL_LTIME_100 120 //the unit is ns., with bus loading = 100pf
#define I2C_HS_MIN_SCL_HTIME_400 160 //the unit is ns, with bus loading = 400pf
#define I2C_HS_MIN_SCL_LTIME_400 320 //the unit is ns., with bus loading = 400pf
//======================================================
//I2C Essential functions and macros
_LONG_CALL_ROM_ VOID HalI2CWrite32(IN u8 I2CIdx, IN u8 I2CReg, IN u32 I2CVal);
_LONG_CALL_ROM_ u32 HalI2CRead32(IN u8 I2CIdx, IN u8 I2CReg);
#define HAL_I2C_WRITE32(I2CIdx, addr, value) HalI2CWrite32(I2CIdx,addr,value)
#define HAL_I2C_READ32(I2CIdx, addr) HalI2CRead32(I2CIdx,addr)
// Rtl8195a I2C function prototypes
_LONG_CALL_ HAL_Status HalI2CEnableRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CInit8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CDeInit8195a(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CSendRtl8195a(IN VOID *Data);
_LONG_CALL_ u8 HalI2CReceiveRtl8195a(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status HalI2CIntrCtrl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CClrIntrRtl8195a(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status HalI2CClrAllIntrRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CDMACtrl8195a(IN VOID *Data);
_LONG_CALL_ u32 HalI2CReadRegRtl8195a(IN VOID *Data, IN u8 I2CReg);
_LONG_CALL_ HAL_Status HalI2CWriteRegRtl8195a(IN VOID *Data, IN u8 I2CReg, IN u32 RegVal);
//Rtl8195a I2C V02 function prototype
_LONG_CALL_ HAL_Status HalI2CSendRtl8195aV02(IN VOID *Data);
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data);
#elif defined(CONFIG_CHIP_E_CUT)
_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data);
#endif
//Rtl8195a I2C V02 function prototype END
HAL_Status HalI2CInit8195a_Patch(IN VOID *Data);
HAL_Status HalI2CSendRtl8195a_Patch(IN VOID *Data);
HAL_Status HalI2CSetCLKRtl8195a_Patch(IN VOID *Data);
#endif

617
lib/fwlib/rtl8195a/rtl8195a_i2s.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_I2S_H_
#define _RTL8195A_I2S_H_
//=============== Register Bit Field Definition ====================
// REG_I2S_CONTROL
#define BIT_CTLX_I2S_EN BIT(0)
#define BIT_SHIFT_CTLX_I2S_EN 0
#define BIT_MASK_CTLX_I2S_EN 0x1
#define BIT_CTRL_CTLX_I2S_EN(x) (((x) & BIT_MASK_CTLX_I2S_EN) << BIT_SHIFT_CTLX_I2S_EN)
#define BIT_SHIFT_CTLX_I2S_TRX_ACT 1
#define BIT_MASK_CTLX_I2S_TRX_ACT 0x3
#define BIT_CTRL_CTLX_I2S_TRX_ACT(x) (((x) & BIT_MASK_CTLX_I2S_TRX_ACT) << BIT_SHIFT_CTLX_I2S_TRX_ACT)
#define BIT_GET_CTLX_I2S_TRX_ACT(x) (((x) >> BIT_SHIFT_CTLX_I2S_TRX_ACT) & BIT_MASK_CTLX_I2S_TRX_ACT)
#define BIT_SHIFT_CTLX_I2S_CH_NUM 3
#define BIT_MASK_CTLX_I2S_CH_NUM 0x3
#define BIT_CTRL_CTLX_I2S_CH_NUM(x) (((x) & BIT_MASK_CTLX_I2S_CH_NUM) << BIT_SHIFT_CTLX_I2S_CH_NUM)
#define BIT_GET_CTLX_I2S_CH_NUM(x) (((x) >> BIT_SHIFT_CTLX_I2S_CH_NUM) & BIT_MASK_CTLX_I2S_CH_NUM)
#define BIT_CTLX_I2S_WL BIT(6)
#define BIT_SHIFT_CTLX_I2S_WL 6
#define BIT_MASK_CTLX_I2S_WL 0x1
#define BIT_CTRL_CTLX_I2S_WL(x) (((x) & BIT_MASK_CTLX_I2S_WL) << BIT_SHIFT_CTLX_I2S_WL)
#define BIT_CTLX_I2S_LRSWAP BIT(10)
#define BIT_SHIFT_CTLX_I2S_LRSWAP 10
#define BIT_MASK_CTLX_I2S_LRSWAP 0x1
#define BIT_CTRL_CTLX_I2S_LRSWAP(x) (((x) & BIT_MASK_CTLX_I2S_LRSWAP) << BIT_SHIFT_CTLX_I2S_LRSWAP)
#define BIT_CTLX_I2S_SCK_INV BIT(11)
#define BIT_SHIFT_CTLX_I2S_SCK_INV 11
#define BIT_MASK_CTLX_I2S_SCK_INV 0x1
#define BIT_CTRL_CTLX_I2S_SCK_INV(x) (((x) & BIT_MASK_CTLX_I2S_SCK_INV) << BIT_SHIFT_CTLX_I2S_SCK_INV)
#define BIT_CTLX_I2S_ENDIAN_SWAP BIT(12)
#define BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP 12
#define BIT_MASK_CTLX_I2S_ENDIAN_SWAP 0x1
#define BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_I2S_ENDIAN_SWAP) << BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP)
#define BIT_CTLX_I2S_SLAVE_MODE BIT(29)
#define BIT_SHIFT_CTLX_I2S_SLAVE_MODE 29
#define BIT_MASK_CTLX_I2S_SLAVE_MODE 0x1
#define BIT_CTRL_CTLX_I2S_SLAVE_MODE(x) (((x) & BIT_MASK_CTLX_I2S_SLAVE_MODE) << BIT_SHIFT_CTLX_I2S_SLAVE_MODE)
#define BIT_CTLX_I2S_CLK_SRC BIT(30)
#define BIT_SHIFT_CTLX_I2S_CLK_SRC 30
#define BIT_MASK_CTLX_I2S_CLK_SRC 0x1
#define BIT_CTRL_CTLX_I2S_CLK_SRC(x) (((x) & BIT_MASK_CTLX_I2S_CLK_SRC) << BIT_SHIFT_CTLX_I2S_CLK_SRC)
#define BIT_CTLX_I2S_SW_RSTN BIT(31)
#define BIT_SHIFT_CTLX_I2S_SW_RSTN 31
#define BIT_MASK_CTLX_I2S_SW_RSTN 0x1
#define BIT_CTRL_CTLX_I2S_SW_RSTN(x) (((x) & BIT_MASK_CTLX_I2S_SW_RSTN) << BIT_SHIFT_CTLX_I2S_SW_RSTN)
// REG_I2S_SETTING
#define BIT_SHIFT_SETTING_I2S_PAGE_SZ 0
#define BIT_MASK_SETTING_I2S_PAGE_SZ 0xFFF
#define BIT_CTRL_SETTING_I2S_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_SZ) << BIT_SHIFT_SETTING_I2S_PAGE_SZ)
#define BIT_GET_SETTING_I2S_PAGE_SZ(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_SZ) & BIT_MASK_SETTING_I2S_PAGE_SZ)
#define BIT_SHIFT_SETTING_I2S_PAGE_NUM 12
#define BIT_MASK_SETTING_I2S_PAGE_NUM 0x3
#define BIT_CTRL_SETTING_I2S_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_NUM) << BIT_SHIFT_SETTING_I2S_PAGE_NUM)
#define BIT_GET_SETTING_I2S_PAGE_NUM(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_NUM) & BIT_MASK_SETTING_I2S_PAGE_NUM)
#define BIT_SHIFT_SETTING_I2S_SAMPLE_RATE 14
#define BIT_MASK_SETTING_I2S_SAMPLE_RATE 0x7
#define BIT_CTRL_SETTING_I2S_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_I2S_SAMPLE_RATE) << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE)
#define BIT_GET_SETTING_I2S_SAMPLE_RATE(x) (((x) >> BIT_SHIFT_SETTING_I2S_SAMPLE_RATE) & BIT_MASK_SETTING_I2S_SAMPLE_RATE)
// i2s trx page own bit
#define BIT_PAGE_I2S_OWN_BIT BIT(31)
#define BIT_SHIFT_PAGE_I2S_OWN_BIT 31
#define BIT_MASK_PAGE_I2S_OWN_BIT 0x1
#define BIT_CTRL_PAGE_I2S_OWN_BIT(x) (((x) & BIT_MASK_PAGE_I2S_OWN_BIT) << BIT_SHIFT_PAGE_I2S_OWN_BIT)
//=============== Register Address Definition ====================
#define REG_I2S_PAGE_OWN_OFF 0x004
#define REG_I2S_CTL 0x000
#define REG_I2S_TX_PAGE_PTR 0x004
#define REG_I2S_RX_PAGE_PTR 0x008
#define REG_I2S_SETTING 0x00C
#define REG_I2S_TX_MASK_INT 0x010
#define REG_I2S_TX_STATUS_INT 0x014
#define REG_I2S_RX_MASK_INT 0x018
#define REG_I2S_RX_STATUS_INT 0x01c
#define REG_I2S_TX_PAGE0_OWN 0x020
#define REG_I2S_TX_PAGE1_OWN 0x024
#define REG_I2S_TX_PAGE2_OWN 0x028
#define REG_I2S_TX_PAGE3_OWN 0x02C
#define REG_I2S_RX_PAGE0_OWN 0x030
#define REG_I2S_RX_PAGE1_OWN 0x034
#define REG_I2S_RX_PAGE2_OWN 0x038
#define REG_I2S_RX_PAGE3_OWN 0x03C
/*I2S Essential Functions and Macros*/
VOID
HalI2SWrite32(
IN u8 I2SIdx,
IN u8 I2SReg,
IN u32 I2SVal
);
u32
HalI2SRead32(
IN u8 I2SIdx,
IN u8 I2SReg
);
/*
#define HAL_I2SX_READ32(I2sIndex, addr) \
HAL_READ32(I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF), addr)
#define HAL_I2SX_WRITE32(I2sIndex, addr, value) \
HAL_WRITE32((I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF)), addr, value)
*/
#define HAL_I2S_WRITE32(I2SIdx, addr, value) HalI2SWrite32(I2SIdx,addr,value)
#define HAL_I2S_READ32(I2SIdx, addr) HalI2SRead32(I2SIdx,addr)
/* I2S debug output*/
#define I2S_PREFIX "RTL8195A[i2s]: "
#define I2S_PREFIX_LVL " [i2s_DBG]: "
typedef enum _I2S_DBG_LVL_ {
HAL_I2S_LVL = 0x01,
SAL_I2S_LVL = 0x02,
VERI_I2S_LVL = 0x03,
}I2S_DBG_LVL,*PI2S_DBG_LVL;
#ifdef CONFIG_DEBUG_LOG
#ifdef CONFIG_DEBUG_LOG_I2S_HAL
#define DBG_8195A_I2S(...) do{ \
_DbgDump("\r"I2S_PREFIX __VA_ARGS__);\
}while(0)
#define I2SDBGLVL 0xFF
#define DBG_8195A_I2S_LVL(LVL,...) do{\
if (LVL&I2SDBGLVL){\
_DbgDump("\r"I2S_PREFIX_LVL __VA_ARGS__);\
}\
}while(0)
#else
#define DBG_I2S_LOG_PERD 100
#define DBG_8195A_I2S(...)
#define DBG_8195A_I2S_LVL(...)
#endif
#else
#define DBG_I2S_LOG_PERD 100
#define DBG_8195A_I2S(...)
#define DBG_8195A_I2S_LVL(...)
#endif
/*
#define REG_I2S_PAGE_OWN_OFF 0x004
#define REG_I2S_CTL 0x000
#define REG_I2S_TX_PAGE_PTR 0x004
#define REG_I2S_RX_PAGE_PTR 0x008
#define REG_I2S_SETTING 0x00C
#define REG_I2S_TX_MASK_INT 0x010
#define REG_I2S_TX_STATUS_INT 0x014
#define REG_I2S_RX_MASK_INT 0x018
#define REG_I2S_RX_STATUS_INT 0x01c
#define REG_I2S_TX_PAGE0_OWN 0x020
#define REG_I2S_TX_PAGE1_OWN 0x024
#define REG_I2S_TX_PAGE2_OWN 0x028
#define REG_I2S_TX_PAGE3_OWN 0x02C
#define REG_I2S_RX_PAGE0_OWN 0x030
#define REG_I2S_RX_PAGE1_OWN 0x034
#define REG_I2S_RX_PAGE2_OWN 0x038
#define REG_I2S_RX_PAGE3_OWN 0x03C
*/
/* template
#define BIT_SHIFT_CTLX_ 7
#define BIT_MASK_CTLX_ 0x1
#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_)
#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_))
*//*
#define BIT_SHIFT_CTLX_IIS_EN 0
#define BIT_MASK_CTLX_IIS_EN 0x1
#define BIT_CTLX_IIS_EN(x) (((x) & BIT_MASK_CTLX_IIS_EN) << BIT_SHIFT_CTLX_IIS_EN)
#define BIT_INV_CTLX_IIS_EN (~(BIT_MASK_CTLX_IIS_EN << BIT_SHIFT_CTLX_IIS_EN))
#define BIT_SHIFT_CTLX_TRX 1
#define BIT_MASK_CTLX_TRX 0x3
#define BIT_CTLX_TRX(x) (((x) & BIT_MASK_CTLX_TRX) << BIT_SHIFT_CTLX_TRX)
#define BIT_INV_CTLX_TRX (~(BIT_MASK_CTLX_TRX << BIT_SHIFT_CTLX_TRX))
#define BIT_SHIFT_CTLX_CH_NUM 3
#define BIT_MASK_CTLX_CH_NUM 0x3
#define BIT_CTLX_CH_NUM(x) (((x) & BIT_MASK_CTLX_CH_NUM) << BIT_SHIFT_CTLX_CH_NUM)
#define BIT_INV_CTLX_CH_NUM (~(BIT_MASK_CTLX_CH_NUM << BIT_SHIFT_CTLX_CH_NUM))
#define BIT_SHIFT_CTLX_EDGE_SW 5
#define BIT_MASK_CTLX_EDGE_SW 0x1
#define BIT_CTLX_EDGE_SW(x) (((x) & BIT_MASK_CTLX_EDGE_SW) << BIT_SHIFT_CTLX_EDGE_SW)
#define BIT_INV_CTLX_EDGE_SW (~(BIT_MASK_CTLX_EDGE_SW << BIT_SHIFT_CTLX_EDGE_SW))
#define BIT_SHIFT_CTLX_WL 6
#define BIT_MASK_CTLX_WL 0x1
#define BIT_CTLX_WL(x) (((x) & BIT_MASK_CTLX_WL) << BIT_SHIFT_CTLX_WL)
#define BIT_INV_CTLX_WL (~(BIT_MASK_CTLX_WL << BIT_SHIFT_CTLX_WL))
#define BIT_SHIFT_CTLX_LOOP_BACK 7
#define BIT_MASK_CTLX_LOOP_BACK 0x1
#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK)
#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK))
#define BIT_SHIFT_CTLX_FORMAT 8
#define BIT_MASK_CTLX_FORMAT 0x3
#define BIT_CTLX_FORMAT(x) (((x) & BIT_MASK_CTLX_FORMAT) << BIT_SHIFT_CTLX_FORMAT)
#define BIT_INV_CTLX_FORMAT (~(BIT_MASK_CTLX_FORMAT << BIT_SHIFT_CTLX_FORMAT))
#define BIT_SHIFT_CTLX_LRSWAP 10
#define BIT_MASK_CTLX_LRSWAP 0x1
#define BIT_CTLX_LRSWAP(x) (((x) & BIT_MASK_CTLX_LRSWAP) << BIT_SHIFT_CTLX_LRSWAP)
#define BIT_INV_CTLX_LRSWAP (~(BIT_MASK_CTLX_LRSWAP << BIT_SHIFT_CTLX_LRSWAP))
#define BIT_SHIFT_CTLX_SCK_INV 11
#define BIT_MASK_CTLX_SCK_INV 0x1
#define BIT_CTLX_SCK_INV(x) (((x) & BIT_MASK_CTLX_SCK_INV) << BIT_SHIFT_CTLX_SCK_INV)
#define BIT_INV_CTLX_SCK_INV (~(BIT_MASK_CTLX_SCK_INV << BIT_SHIFT_CTLX_SCK_INV))
#define BIT_SHIFT_CTLX_ENDIAN_SWAP 12
#define BIT_MASK_CTLX_ENDIAN_SWAP 0x1
#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP)
#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP))
#define BIT_SHIFT_CTLX_DEBUG_SWITCH 15
#define BIT_MASK_CTLX_DEBUG_SWITCH 0x3
#define BIT_CTLX_DEBUG_SWITCH(x) (((x) & BIT_MASK_CTLX_DEBUG_SWITCH) << BIT_SHIFT_CTLX_DEBUG_SWITCH)
#define BIT_INV_CTLX_DEBUG_SWITCH (~(BIT_MASK_CTLX_DEBUG_SWITCH << BIT_SHIFT_CTLX_DEBUG_SWITCH))
#define BIT_SHIFT_CTLX_SLAVE_SEL 29
#define BIT_MASK_CTLX_SLAVE_SEL 0x1
#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL)
#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL))
#define BIT_SHIFT_CTLX_CLK_SRC 30
#define BIT_MASK_CTLX_CLK_SRC 0x1
#define BIT_CTLX_CLK_SRC(x) (((x) & BIT_MASK_CTLX_CLK_SRC) << BIT_SHIFT_CTLX_CLK_SRC)
#define BIT_INV_CTLX_CLK_SRC (~(BIT_MASK_CTLX_CLK_SRC << BIT_SHIFT_CTLX_CLK_SRC))
#define BIT_SHIFT_CTLX_SW_RSTN 31
#define BIT_MASK_CTLX_SW_RSTN 0x1
#define BIT_CTLX_SW_RSTN(x) (((x) & BIT_MASK_CTLX_SW_RSTN) << BIT_SHIFT_CTLX_SW_RSTN)
#define BIT_INV_CTLX_SW_RSTN (~(BIT_MASK_CTLX_SW_RSTN << BIT_SHIFT_CTLX_SW_RSTN))
#define BIT_SHIFT_SETTING_PAGE_SZ 0
#define BIT_MASK_SETTING_PAGE_SZ 0xFFF
#define BIT_SETTING_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_PAGE_SZ) << BIT_SHIFT_SETTING_PAGE_SZ)
#define BIT_INV_SETTING_PAGE_SZ (~(BIT_MASK_SETTING_PAGE_SZ << BIT_SHIFT_SETTING_PAGE_SZ))
#define BIT_SHIFT_SETTING_PAGE_NUM 12
#define BIT_MASK_SETTING_PAGE_NUM 0x3
#define BIT_SETTING_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_PAGE_NUM) << BIT_SHIFT_SETTING_PAGE_NUM)
#define BIT_INV_SETTING_PAGE_NUM (~(BIT_MASK_SETTING_PAGE_NUM << BIT_SHIFT_SETTING_PAGE_NUM))
#define BIT_SHIFT_SETTING_SAMPLE_RATE 14
#define BIT_MASK_SETTING_SAMPLE_RATE 0x7
#define BIT_SETTING_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_SAMPLE_RATE) << BIT_SHIFT_SETTING_SAMPLE_RATE)
#define BIT_INV_SETTING_SAMPLE_RATE (~(BIT_MASK_SETTING_SAMPLE_RATE << BIT_SHIFT_SETTING_SAMPLE_RATE))
*/
typedef enum _I2S_CTL_FORMAT {
FormatI2s = 0x00,
FormatLeftJustified = 0x01,
FormatRightJustified = 0x02
}I2S_CTL_FORMAT, *PI2S_CTL_FORMAT;
typedef enum _I2S_CTL_CHNUM {
ChannelStereo = 0x00,
Channel5p1 = 0x01,
ChannelMono = 0x02
}I2S_CTL_CHNUM, *PI2S_CTL_CHNUM;
typedef enum _I2S_CTL_TRX_ACT {
RxOnly = 0x00,
TxOnly = 0x01,
TXRX = 0x02
}I2S_CTL_TRX_ACT, *PI2S_CTL_TRX_ACT;
/*
typedef struct _I2S_CTL_REG_ {
I2S_CTL_FORMAT Format;
I2S_CTL_CHNUM ChNum;
I2S_CTL_TRX_ACT TrxAct;
u32 I2s_En :1; // Bit 0
u32 Rsvd1to4 :4; // Bit 1-4 is TrxAct, ChNum
u32 EdgeSw :1; // Bit 5 Edge switch
u32 WordLength :1; // Bit 6
u32 LoopBack :1; // Bit 7
u32 Rsvd8to9 :2; // Bit 8-9 is Format
u32 DacLrSwap :1; // Bit 10
u32 SckInv :1; // Bit 11
u32 EndianSwap :1; // Bit 12
u32 Rsvd13to14 :2; // Bit 11-14
u32 DebugSwitch :2; // Bit 15-16
u32 Rsvd17to28 :12; // Bit 17-28
u32 SlaveMode :1; // Bit 29
u32 SR44p1KHz :1; // Bit 30
u32 SwRstn :1; // Bit 31
} I2S_CTL_REG, *PI2S_CTL_REG;
*/
typedef enum _I2S_SETTING_PAGE_NUM {
I2s1Page = 0x00,
I2s2Page = 0x01,
I2s3Page = 0x02,
I2s4Page = 0x03
}I2S_SETTING_PAGE_NUM, *PI2S_SETTING_PAGE_NUM;
//sampling rate
typedef enum _I2S_SETTING_SR {
I2sSR8K = 0x00,
I2sSR16K = 0x01,
I2sSR24K = 0x02,
I2sSR32K = 0x03,
I2sSR48K = 0x05,
I2sSR44p1K = 0x15,
I2sSR96K = 0x06,
I2sSR88p2K = 0x16
}I2S_SETTING_SR, *PI2S_SETTING_SR;
/*
typedef struct _I2S_SETTING_REG_ {
I2S_SETTING_PAGE_NUM PageNum;
I2S_SETTING_SR SampleRate;
u32 PageSize:12; // Bit 0-11
}I2S_SETTING_REG, *PI2S_SETTING_REG;
typedef enum _I2S_TX_ISR {
I2sTxP0OK = 0x01,
I2sTxP1OK = 0x02,
I2sTxP2OK = 0x04,
I2sTxP3OK = 0x08,
I2sTxPageUn = 0x10,
I2sTxFifoEmpty = 0x20
}I2S_TX_ISR, *PI2S_TX_ISR;
typedef enum _I2S_RX_ISR {
I2sRxP0OK = 0x01,
I2sRxP1OK = 0x02,
I2sRxP2OK = 0x04,
I2sRxP3OK = 0x08,
I2sRxPageUn = 0x10,
I2sRxFifoFull = 0x20
}I2S_RX_ISR, *PI2S_RX_ISR;
*/
/* Hal I2S function prototype*/
RTK_STATUS
HalI2SInitRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SInitRtl8195a_Patch(
IN VOID *Data
);
RTK_STATUS
HalI2SDeInitRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2STxRtl8195a(
IN VOID *Data,
IN u8 *pBuff
);
RTK_STATUS
HalI2SRxRtl8195a(
IN VOID *Data,
OUT u8 *pBuff
);
RTK_STATUS
HalI2SEnableRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SIntrCtrlRtl8195a(
IN VOID *Data
);
u32
HalI2SReadRegRtl8195a(
IN VOID *Data,
IN u8 I2SReg
);
RTK_STATUS
HalI2SSetRateRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetWordLenRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetChNumRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetPageNumRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetPageSizeRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetDirectionRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetDMABufRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SClrIntrRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SClrAllIntrRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SDMACtrlRtl8195a(
IN VOID *Data
);
u8
HalI2SGetTxPageRtl8195a(
IN VOID *Data
);
u8
HalI2SGetRxPageRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SPageSendRtl8195a(
IN VOID *Data,
IN u8 PageIdx
);
#if 0
RTK_STATUS
HalI2SPageRecvRtl8195a(
IN VOID *Data,
IN u8 PageIdx
);
#else
RTK_STATUS
HalI2SPageRecvRtl8195a(
IN VOID *Data
);
#endif
RTK_STATUS
HalI2SClearAllOwnBitRtl8195a(
IN VOID *Data
);
// HAL functions Wrapper
static __inline VOID
HalI2SSetRate(
IN VOID *Data
)
{
HalI2SSetRateRtl8195a(Data);
}
static __inline VOID
HalI2SSetWordLen(
IN VOID *Data
)
{
HalI2SSetWordLenRtl8195a(Data);
}
static __inline VOID
HalI2SSetChNum(
IN VOID *Data
)
{
HalI2SSetChNumRtl8195a(Data);
}
static __inline VOID
HalI2SSetPageNum(
IN VOID *Data
)
{
HalI2SSetPageNumRtl8195a(Data);
}
static __inline VOID
HalI2SSetPageSize(
IN VOID *Data
)
{
HalI2SSetPageSizeRtl8195a(Data);
}
static __inline VOID
HalI2SSetDirection(
IN VOID *Data
)
{
HalI2SSetDirectionRtl8195a(Data);
}
static __inline VOID
HalI2SSetDMABuf(
IN VOID *Data
)
{
HalI2SSetDMABufRtl8195a(Data);
}
static __inline u8
HalI2SGetTxPage(
IN VOID *Data
)
{
return HalI2SGetTxPageRtl8195a(Data);
}
static __inline u8
HalI2SGetRxPage(
IN VOID *Data
)
{
return HalI2SGetRxPageRtl8195a(Data);
}
static __inline VOID
HalI2SPageSend(
IN VOID *Data,
IN u8 PageIdx
)
{
HalI2SPageSendRtl8195a(Data, PageIdx);
}
#if 0
static __inline VOID
HalI2SPageRecv(
IN VOID *Data,
IN u8 PageIdx
)
{
HalI2SPageRecvRtl8195a(Data, PageIdx);
}
#else
static __inline VOID
HalI2SPageRecv(
IN VOID *Data
)
{
HalI2SPageRecvRtl8195a(Data);
}
#endif
static __inline VOID
HalI2SClearAllOwnBit(
IN VOID *Data
)
{
HalI2SClearAllOwnBitRtl8195a(Data);
}
#endif /* _RTL8195A_I2S_H_ */

674
lib/fwlib/rtl8195a/rtl8195a_mii.h Normal file
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@ -0,0 +1,674 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_MII_H_
#define _RTL8195A_MII_H_
#include "basic_types.h"
#include "hal_api.h"
#define ETHERNET_REG_BASE 0x40050000
#define ETHERNET_MODULE_BASE ETHERNET_REG_BASE + 0x0000
#define CPU_INTERFACE_BASE ETHERNET_REG_BASE + 0x1300
/* Ethernet Module registers */
#define REG_RTL_MII_IDR0 0x0000 // Table 2 IDR0 (Offset 0000h-0003h, R/W)
#define REG_RTL_MII_IDR4 0x0004 // Table 3 IDR4 (Offset 0004h-0007h, R/W)
#define REG_RTL_MII_MAR0 0x0008 // Table 4 MAR0 (Offset 0008h-000bh, R/W)
#define REG_RTL_MII_MAR4 0x000C // Table 5 MAR4 (Offset 000ch-000fh, R/W)
#define REG_RTL_MII_CR 0x0038 // Table 21 Command Register (COM_REG, Offset 0038-003Bh, R/W)
#define REG_RTL_MII_IMRISR 0x003C // Table 22 + Table 23
#define REG_RTL_MII_TCR 0x0040 // Table 24 Transmit Configuration Register (TC_REG, Offset 0040h-0043h, R/W)
#define REG_RTL_MII_RCR 0x0044 // Table 25 Receive Configuration Register (RC_REG, Offset 0044h-0047h, R/W)
#define REG_RTL_MII_CTCR 0x0048 // Table 26 CPU Tag Control Register (CPUTAG_REG, Offset 0048h-004bh, R/W)
#define REG_RTL_MII_CONFIG 0x004C // Table 27 Configuration Register (CONFIG_REG, Offset 004ch-004fh, R/W)
#define REG_RTL_MII_CTCR1 0x0050 // Table 28 CPUTAG1 Register (CPUTAG1_REG, Offset 0050h-0053h, R/W)
#define REG_RTL_MII_MSR 0x0058 // Table 29 Media Status Register (MS_reg: Offset 0058h – 005bh, R/W)
#define REG_RTL_MII_MIIAR 0x005C // Table 30 MII Access Register (MIIA_REG, Offset 005c-005fh, R/W)
#define REG_RTL_MII_VR 0x0064 // Table 32 VLAN Register (VLAN_REG, Offset 0064-0067h, R/W)
#define REG_RTL_MII_IMR0 0x00D0 // Table 50 IMR0_REG (IMR0_REG, Offset D0h-D3h)
#define REG_RTL_MII_IMR1 0x00D4 // Table 51 IMR1_REG (IMR1_REG, Offset d4h-d7h)
#define REG_RTL_MII_ISR1 0x00D8 // Table 52 ISR1 Register (ISR1_REG, Offset D8h-DBh)
#define REG_RTL_MII_INTR 0x00DC // Table 53 Interrupt routing register (INTR_REG, Offset DCh-DFh)
#define REG_RTL_MII_CCR 0x00E4 // Table xx Clock Control Register (CLKCTL_REG, Offset E4h-E7h)
/* CPU Interface registers */
#define REG_RTL_MII_TXFDP1 0x1300 // Table 55 TxFDP1 register (TXFDP1_REG, offset 1300h-1303h)
#define REG_RTL_MII_TXCDO1 0x1304 // Table 56 TxCDO1 register (TXCDO1_REG, offset 1304h-1305h)
#define REG_RTL_MII_TXFDP2 0x1310 // Table 57 TxFDP2 register (TXFDP2_REG, offset 1310h-1313h)
#define REG_RTL_MII_TXCDO2 0x1314 // Table 58 TxCDO2 register (TXCDO2_REG, offset 1314h-1315h)
#define REG_RTL_MII_TXFDP3 0x1320 // Table 59 TxFDP3 register (TXFDP3_REG, offset 1320h-1323h)
#define REG_RTL_MII_TXCDO3 0x1324 // Table 60 TxCDO3 register (TXCDO3_REG, offset 1324h-1325h)
#define REG_RTL_MII_TXFDP4 0x1330 // Table 61 TxFDP4 register (TXFDP4_REG, offset 1330h-1333h)
#define REG_RTL_MII_TXCDO4 0x1334 // Table 62 TxCDO4 register (TXCDO4_REG, offset 1334h-1335h)
#define REG_RTL_MII_TXFDP5 0x1340 // Table 63 TxFDP5 register (TXFDP5_REG, offset 1340h-1343h)
#define REG_RTL_MII_TXCDO5 0x1344 // Table 64 TxCDO5 register (TXCDO5_REG, offset 1344h-1345h)
#define REG_RTL_MII_RXFDP2 0x1390 // Table 66 RxFDP2 register (RXFDP#_REG, offset 1390h-1393h)
#define REG_RTL_MII_RXFDP1 0x13F0 // Table 71 RxFDP1 register (RXFDP1_REG, offset 13F0h-13F3h)
#define REG_RTL_MII_RXRS1 0x13F6 // Table 73 Rx Ring Size1 register (RX_RS1_REG, offset 13F6h-13F7h)
#define REG_RTL_MII_RX_PSE1 0x142C // Table 77 Rx_Pse_Des_Thres_1_h (RX_PSE1_REG, Offset 142ch)
#define REG_RTL_MII_ETNRXCPU1 0x1430 // Table 79 EhtrntRxCPU_Des_Num1 (ETNRXCPU1_REG, Offset 1430h-1433h)
#define REG_RTL_MII_IOCMD 0x1434 // Table 80 Ethernet_IO_CMD (ETN_IO_CMD_REG, Offset 1434h-1437h)
#define REG_RTL_MII_IOCMD1 0x1438 // Table 81 Ethernet_IO_CMD1 (IO_CMD1_REG: Offset 1438h-143bh)
#define HAL_MII_READ32(addr) \
HAL_READ32(ETHERNET_REG_BASE, addr)
#define HAL_MII_WRITE32(addr, value) \
HAL_WRITE32(ETHERNET_REG_BASE, addr, value)
#define HAL_MII_READ16(addr) \
HAL_READ16(ETHERNET_REG_BASE, addr)
#define HAL_MII_WRITE16(addr, value) \
HAL_WRITE16(ETHERNET_REG_BASE, addr, value)
#define HAL_MII_READ8(addr) \
HAL_READ8(ETHERNET_REG_BASE, addr)
#define HAL_MII_WRITE8(addr, value) \
HAL_WRITE8(ETHERNET_REG_BASE, addr, value)
#define CMD_CONFIG 0x00081000
//2014-04-29 yclin (disable [27] r_en_precise_dma)
// #define CMD1_CONFIG 0x39000000
#define CMD1_CONFIG 0x31000000
// #define MAX_RX_DESC_SIZE 6
#define MAX_RX_DESC_SIZE 1
#define MAX_TX_DESC_SIZE 5
// 0058h
#define BIT_SHIFT_MSR_FORCE_SPEED_SELECT 16
#define BIT_MASK_MSR_FORCE_SPEED_SELECT 0x3
#define BIT_MSR_FORCE_SPEED_SELECT(x)(((x) & BIT_MASK_MSR_FORCE_SPEED_SELECT) << BIT_SHIFT_MSR_FORCE_SPEED_SELECT)
#define BIT_INVC_MSR_FORCE_SPEED_SELECT (~(BIT_MASK_MSR_FORCE_SPEED_SELECT << BIT_SHIFT_MSR_FORCE_SPEED_SELECT))
#define BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE 10
#define BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE 0x1
#define BIT_MSR_FORCE_SPEED_MODE_ENABLE(x)(((x) & BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE) << BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE)
#define BIT_INVC_MSR_FORCE_SPEED_MODE_ENABLE (~(BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE << BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE))
// 1434h
#define BIT_SHIFT_IOCMD_RXENABLE 5
#define BIT_MASK_IOCMD_RXENABLE 0x1
#define BIT_IOCMD_RXENABLE(x)(((x) & BIT_MASK_IOCMD_RXENABLE) << BIT_SHIFT_IOCMD_RXENABLE)
#define BIT_INVC_IOCMD_RXENABLE (~(BIT_MASK_IOCMD_RXENABLE << BIT_SHIFT_IOCMD_RXENABLE))
#define BIT_SHIFT_IOCMD_TXENABLE 4
#define BIT_MASK_IOCMD_TXENABLE 0x1
#define BIT_IOCMD_TXENABLE(x)(((x) & BIT_MASK_IOCMD_TXENABLE) << BIT_SHIFT_IOCMD_TXENABLE)
#define BIT_INVC_IOCMD_TXENABLE (~(BIT_MASK_IOCMD_TXENABLE << BIT_SHIFT_IOCMD_TXENABLE))
#define BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE 0
#define BIT_MASK_IOCMD_FIRST_DMATX_ENABLE 0x1
#define BIT_IOCMD_FIRST_DMATX_ENABLE(x)(((x) & BIT_MASK_IOCMD_FIRST_DMATX_ENABLE) << BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE)
#define BIT_INVC_IOCMD_FIRST_DMATX_ENABLE (~(BIT_MASK_IOCMD_FIRST_DMATX_ENABLE << BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE))
// 1438h
#define BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE 16
#define BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE 0x1
#define BIT_IOCMD1_FIRST_DMARX_ENABLE(x)(((x) & BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE) << BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE)
#define BIT_INVC_IOCMD1_FIRST_DMARX_ENABLE (~(BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE << BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE))
/**
* 1.4.1.7 Tx command descriptor used in RL6266
* 5 dobule words
*/
typedef struct _TX_INFO_ {
union {
struct {
u32 own:1; //31
u32 eor:1; //30
u32 fs:1; //29
u32 ls:1; //28
u32 ipcs:1; //27
u32 l4cs:1; //26
u32 keep:1; //25
u32 blu:1; //24
u32 crc:1; //23
u32 vsel:1; //22
u32 dislrn:1; //21
u32 cputag_ipcs:1; //20
u32 cputag_l4cs:1; //19
u32 cputag_psel:1; //18
u32 rsvd:1; //17
u32 data_length:17; //0~16
} bit;
u32 dw; //double word
} opts1;
u32 addr;
union {
struct {
u32 cputag:1; //31
u32 aspri:1; //30
u32 cputag_pri:3; //27~29
u32 tx_vlan_action:2; //25~26
u32 tx_pppoe_action:2; //23~24
u32 tx_pppoe_idx:3; //20~22
u32 efid:1; //19
u32 enhance_fid:3; //16~18
u32 vidl:8; // 8~15
u32 prio:3; // 5~7
u32 cfi:1; // 4
u32 vidh:4; // 0~3
} bit;
u32 dw; //double word
} opts2;
union {
struct {
u32 extspa:3; //29~31
u32 tx_portmask:6; //23~28
u32 tx_dst_stream_id:7; //16~22
u32 rsvd:14; // 2~15
u32 l34keep:1; // 1
u32 ptp:1; // 0
} bit;
u32 dw; //double word
} opts3;
union {
struct {
u32 lgsen:1; //31
u32 lgmss:11; //20~30
u32 rsvd:20; // 0~19
} bit;
u32 dw; //double word
} opts4;
} TX_INFO, *PTX_INFO;
typedef struct _RX_INFO_ {
union{
struct{
u32 own:1; //31
u32 eor:1; //30
u32 fs:1; //29
u32 ls:1; //28
u32 crcerr:1; //27
u32 ipv4csf:1; //26
u32 l4csf:1; //25
u32 rcdf:1; //24
u32 ipfrag:1; //23
u32 pppoetag:1; //22
u32 rwt:1; //21
u32 pkttype:4; //20-17
u32 l3routing:1; //16
u32 origformat:1; //15
u32 pctrl:1; //14
#ifdef CONFIG_RG_JUMBO_FRAME
u32 data_length:14; //13~0
#else
u32 rsvd:2; //13~12
u32 data_length:12; //11~0
#endif
}bit;
u32 dw; //double word
}opts1;
u32 addr;
union{
struct{
u32 cputag:1; //31
u32 ptp_in_cpu_tag_exist:1; //30
u32 svlan_tag_exist:1; //29
u32 rsvd_2:2; //27~28
u32 pon_stream_id:7; //20~26
u32 rsvd_1:3; //17~19
u32 ctagva:1; //16
u32 cvlan_tag:16; //15~0
}bit;
u32 dw; //double word
}opts2;
union{
struct{
u32 src_port_num:5; //27~31
u32 dst_port_mask:6; //21~26
u32 reason:8; //13~20
u32 internal_priority:3; //10~12
u32 ext_port_ttl_1:5; //5~9
u32 rsvd:5; //4~0
}bit;
u32 dw; //double word
}opts3;
} RX_INFO, *PRX_INFO;
/**
* GMAC_STATUS_REGS
*/
// TX/RX Descriptor Common
#define BIT_SHIFT_GMAC_DESCOWN 31
#define BIT_MASK_GMAC_DESCOWN 0x1
#define BIT_GMAC_DESCOWN(x)(((x) & BIT_MASK_GMAC_DESCOWN) << BIT_SHIFT_GMAC_DESCOWN)
#define BIT_INVC_GMAC_DESCOWN (~(BIT_MASK_GMAC_DESCOWN << BIT_SHIFT_GMAC_DESCOWN))
#define BIT_SHIFT_GMAC_RINGEND 30
#define BIT_MASK_GMAC_RINGEND 0x1
#define BIT_GMAC_RINGEND(x)(((x) & BIT_MASK_GMAC_RINGEND) << BIT_SHIFT_GMAC_RINGEND)
#define BIT_INVC_GMAC_RINGEND (~(BIT_MASK_GMAC_RINGEND << BIT_SHIFT_GMAC_RINGEND))
#define BIT_SHIFT_GMAC_FIRSTFRAG 29
#define BIT_MASK_GMAC_FIRSTFRAG 0x1
#define BIT_GMAC_FIRSTFRAG(x)(((x) & BIT_MASK_GMAC_FIRSTFRAG) << BIT_SHIFT_GMAC_FIRSTFRAG)
#define BIT_INVC_GMAC_FIRSTFRAG (~(BIT_MASK_GMAC_FIRSTFRAG << BIT_SHIFT_GMAC_FIRSTFRAG))
#define BIT_SHIFT_GMAC_LASTFRAG 28
#define BIT_MASK_GMAC_LASTFRAG 0x1
#define BIT_GMAC_LASTFRAG(x)(((x) & BIT_MASK_GMAC_LASTFRAG) << BIT_SHIFT_GMAC_LASTFRAG)
#define BIT_INVC_GMAC_LASTFRAG (~(BIT_MASK_GMAC_LASTFRAG << BIT_SHIFT_GMAC_LASTFRAG))
// TX Descriptor opts1
#define BIT_SHIFT_GMAC_IPCS 27
#define BIT_MASK_GMAC_IPCS 0x1
#define BIT_GMAC_IPCS(x)(((x) & BIT_MASK_GMAC_IPCS) << BIT_SHIFT_GMAC_IPCS)
#define BIT_INVC_GMAC_IPCS (~(BIT_MASK_GMAC_IPCS << BIT_SHIFT_GMAC_IPCS))
#define BIT_SHIFT_GMAC_L4CS 26
#define BIT_MASK_GMAC_L4CS 0x1
#define BIT_GMAC_L4CS(x)(((x) & BIT_MASK_GMAC_L4CS) << BIT_SHIFT_GMAC_L4CS)
#define BIT_INVC_GMAC_L4CS (~(BIT_MASK_GMAC_L4CS << BIT_SHIFT_GMAC_L4CS))
#define BIT_SHIFT_GMAC_KEEP 25
#define BIT_MASK_GMAC_KEEP 0x1
#define BIT_GMAC_KEEP(x)(((x) & BIT_MASK_GMAC_KEEP) << BIT_SHIFT_GMAC_KEEP)
#define BIT_INVC_GMAC_KEEP (~(BIT_MASK_GMAC_KEEP << BIT_SHIFT_GMAC_KEEP))
#define BIT_SHIFT_GMAC_BLU 24
#define BIT_MASK_GMAC_BLU 0x1
#define BIT_GMAC_BLU(x)(((x) & BIT_MASK_GMAC_BLU) << BIT_SHIFT_GMAC_BLU)
#define BIT_INVC_GMAC_BLU (~(BIT_MASK_GMAC_BLU << BIT_SHIFT_GMAC_BLU))
#define BIT_SHIFT_GMAC_TXCRC 23
#define BIT_MASK_GMAC_TXCRC 0x1
#define BIT_GMAC_TXCRC(x)(((x) & BIT_MASK_GMAC_TXCRC) << BIT_SHIFT_GMAC_TXCRC)
#define BIT_INVC_GMAC_TXCRC (~(BIT_MASK_GMAC_TXCRC << BIT_SHIFT_GMAC_TXCRC))
#define BIT_SHIFT_GMAC_VSEL 22
#define BIT_MASK_GMAC_VSEL 0x1
#define BIT_GMAC_VSEL(x)(((x) & BIT_MASK_GMAC_VSEL) << BIT_SHIFT_GMAC_VSEL)
#define BIT_INVC_GMAC_VSEL (~(BIT_MASK_GMAC_VSEL << BIT_SHIFT_GMAC_VSEL))
#define BIT_SHIFT_GMAC_DISLRN 21
#define BIT_MASK_GMAC_DISLRN 0x1
#define BIT_GMAC_DISLRN(x)(((x) & BIT_MASK_GMAC_DISLRN) << BIT_SHIFT_GMAC_DISLRN)
#define BIT_INVC_GMAC_DISLRN (~(BIT_MASK_GMAC_DISLRN << BIT_SHIFT_GMAC_DISLRN))
#define BIT_SHIFT_GMAC_CPUTAG_IPCS 20
#define BIT_MASK_GMAC_CPUTAG_IPCS 0x1
#define BIT_GMAC_CPUTAG_IPCS(x)(((x) & BIT_MASK_GMAC_CPUTAG_IPCS) << BIT_SHIFT_GMAC_CPUTAG_IPCS)
#define BIT_INVC_GMAC_CPUTAG_IPCS (~(BIT_MASK_GMAC_CPUTAG_IPCS << BIT_SHIFT_GMAC_CPUTAG_IPCS))
#define BIT_SHIFT_GMAC_CPUTAG_L4CS 19
#define BIT_MASK_GMAC_CPUTAG_L4CS 0x1
#define BIT_GMAC_CPUTAG_L4CS(x)(((x) & BIT_MASK_GMAC_CPUTAG_L4CS) << BIT_SHIFT_GMAC_CPUTAG_L4CS)
#define BIT_INVC_GMAC_CPUTAG_L4CS (~(BIT_MASK_GMAC_CPUTAG_L4CS << BIT_SHIFT_GMAC_CPUTAG_L4CS))
#define BIT_SHIFT_GMAC_CPUTAG_PSEL 18
#define BIT_MASK_GMAC_CPUTAG_PSEL 0x1
#define BIT_GMAC_CPUTAG_PSEL(x)(((x) & BIT_MASK_GMAC_CPUTAG_PSEL) << BIT_SHIFT_GMAC_CPUTAG_PSEL)
#define BIT_INVC_GMAC_CPUTAG_PSEL (~(BIT_MASK_GMAC_CPUTAG_PSEL << BIT_SHIFT_GMAC_CPUTAG_PSEL))
#if 0
enum RE8670_STATUS_REGS
{
/*TX/RX share */
DescOwn = (1 << 31), /* Descriptor is owned by NIC */
RingEnd = (1 << 30), /* End of descriptor ring */
FirstFrag = (1 << 29), /* First segment of a packet */
LastFrag = (1 << 28), /* Final segment of a packet */
/*Tx descriptor opt1*/
IPCS = (1 << 27),
L4CS = (1 << 26),
KEEP = (1 << 25),
BLU = (1 << 24),
TxCRC = (1 << 23),
VSEL = (1 << 22),
DisLrn = (1 << 21),
CPUTag_ipcs = (1 << 20),
CPUTag_l4cs = (1 << 19),
/*Tx descriptor opt2*/
CPUTag = (1 << 31),
aspri = (1 << 30),
CPRI = (1 << 27),
TxVLAN_int = (0 << 25), //intact
TxVLAN_ins = (1 << 25), //insert
TxVLAN_rm = (2 << 25), //remove
TxVLAN_re = (3 << 25), //remark
//TxPPPoEAct = (1 << 23),
TxPPPoEAct = 23,
//TxPPPoEIdx = (1 << 20),
TxPPPoEIdx = 20,
Efid = (1 << 19),
//Enhan_Fid = (1 << 16),
Enhan_Fid = 16,
/*Tx descriptor opt3*/
SrcExtPort = 29,
TxDesPortM = 23,
TxDesStrID = 16,
TxDesVCM = 0,
/*Tx descriptor opt4*/
/*Rx descriptor opt1*/
CRCErr = (1 << 27),
IPV4CSF = (1 << 26),
L4CSF = (1 << 25),
RCDF = (1 << 24),
IP_FRAG = (1 << 23),
PPPoE_tag = (1 << 22),
RWT = (1 << 21),
PktType = (1 << 17),
RxProtoIP = 1,
RxProtoPPTP = 2,
RxProtoICMP = 3,
RxProtoIGMP = 4,
RxProtoTCP = 5,
RxProtoUDP = 6,
RxProtoIPv6 = 7,
RxProtoICMPv6 = 8,
RxProtoTCPv6 = 9,
RxProtoUDPv6 = 10,
L3route = (1 << 16),
OrigFormat = (1 << 15),
PCTRL = (1 << 14),
/*Rx descriptor opt2*/
PTPinCPU = (1 << 30),
SVlanTag = (1 << 29),
/*Rx descriptor opt3*/
SrcPort = (1 << 27),
DesPortM = (1 << 21),
Reason = (1 << 13),
IntPriority = (1 << 10),
ExtPortTTL = (1 << 5),
};
enum _DescStatusBit {
DescOwn = (1 << 31), /* Descriptor is owned by NIC */
RingEnd = (1 << 30), /* End of descriptor ring */
FirstFrag = (1 << 29), /* First segment of a packet */
LastFrag = (1 << 28), /* Final segment of a packet */
/* Tx private */
LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
MSSShift = 16, /* MSS value position */
MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
IPCS = (1 << 18), /* Calculate IP checksum */
UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
TxVlanTag = (1 << 17), /* Add VLAN tag */
/* Rx private */
PID1 = (1 << 18), /* Protocol ID bit 1/2 */
PID0 = (1 << 17), /* Protocol ID bit 2/2 */
#define RxProtoUDP (PID1)
#define RxProtoTCP (PID0)
#define RxProtoIP (PID1 | PID0)
#define RxProtoMask RxProtoIP
IPFail = (1 << 16), /* IP checksum failed */
UDPFail = (1 << 15), /* UDP/IP checksum failed */
TCPFail = (1 << 14), /* TCP/IP checksum failed */
RxVlanTag = (1 << 16), /* VLAN tag available */
};
#endif
typedef struct _PHY_MODE_INFO_ {
u8 PhyAddress;
u8 PhyMode;
u8 PhyInterface;
} PHY_MODE_INFO, *PPHY_MODE_INFO;
typedef enum _PHY_MODE_SWITCH_ {
PHY_MODE_DISABLE = 0,
PHY_MODE_ENABLE = 1
} PHY_MODE_SWITCH, *PPHY_MODE_SWITCH;
typedef enum _PHY_INTERFACE_SELECT_ {
PHY_INTERFACE_ONE_WORKS = 0,
PHY_INTERFACE_ZERO_WORKS = 1
} PHY_INTERFACE_SELECT, *PPHY_INTERFACE_SELECT;
typedef enum _GMAC_MSR_FORCE_SPEED_ {
FORCE_SPD_100M = 0,
FORCE_SPD_10M = 1,
FORCE_SPD_GIGA = 2,
NO_FORCE_SPD = 3
}GMAC_MSR_FORCE_SPEED, *PGMAC_MSR_FORCE_SPEED;
// typedef enum _GMAC_INTERRUPT_MASK_ {
// GMAC_IMR_ROK = BIT0,
// GMAC_IMR_CNT_WRAP = BIT1,
// GMAC_IMR_RER_RUNT = BIT2,
// // BIT3 Reserved
// GMAC_IMR_RER_OVF = BIT4,
// GMAC_IMR_RDU = BIT5,
// GMAC_IMR_TOK_TI = BIT6,
// GMAC_IMR_TER = BIT7,
// GMAC_IMR_LINKCHG = BIT8,
// GMAC_IMR_TDU = BIT9,
// GMAC_IMR_SWINT = BIT10,
// GMAC_IMR_RDU2 = BIT11,
// GMAC_IMR_RDU3 = BIT12,
// GMAC_IMR_RDU4 = BIT13,
// GMAC_IMR_RDU5 = BIT14,
// GMAC_IMR_RDU6 = BIT15,
// } GMAC_INTERRUPT_MASK, *PGMAC_INTERRUPT_MASK;
typedef enum _GMAC_INTERRUPT_MASK_ {
GMAC_IMR_ROK = BIT16,
GMAC_IMR_CNT_WRAP = BIT17,
GMAC_IMR_RER_RUNT = BIT18,
// BIT19 Reserved
GMAC_IMR_RER_OVF = BIT20,
GMAC_IMR_RDU = BIT21,
GMAC_IMR_TOK_TI = BIT22,
GMAC_IMR_TER = BIT23,
GMAC_IMR_LINKCHG = BIT24,
GMAC_IMR_TDU = BIT25,
GMAC_IMR_SWINT = BIT26,
GMAC_IMR_RDU2 = BIT27,
GMAC_IMR_RDU3 = BIT28,
GMAC_IMR_RDU4 = BIT29,
GMAC_IMR_RDU5 = BIT30,
GMAC_IMR_RDU6 = BIT31,
} GMAC_INTERRUPT_MASK, *PGMAC_INTERRUPT_MASK;
typedef enum _GMAC_INTERRUPT_STATUS_ {
GMAC_ISR_ROK = BIT0,
GMAC_ISR_CNT_WRAP = BIT1,
GMAC_ISR_RER_RUNT = BIT2,
// BIT3 Reserved
GMAC_ISR_RER_OVF = BIT4,
GMAC_ISR_RDU = BIT5,
GMAC_ISR_TOK_TI = BIT6,
GMAC_ISR_TER = BIT7,
GMAC_ISR_LINKCHG = BIT8,
GMAC_ISR_TDU = BIT9,
GMAC_ISR_SWINT = BIT10,
GMAC_ISR_RDU2 = BIT11,
GMAC_ISR_RDU3 = BIT12,
GMAC_ISR_RDU4 = BIT13,
GMAC_ISR_RDU5 = BIT14,
GMAC_ISR_RDU6 = BIT15,
} GMAC_INTERRUPT_STATUS, *PGMAC_INTERRUPT_STATUS;
typedef enum _GMAC_TX_VLAN_ACTION_ {
INTACT = 0,
INSERT_VLAN_HDR = 1,
REMOVE_VLAN_HDR = 2,
REMARKING_VID = 3
}GMAC_TX_VLAN_ACTION, *PGMAC_TX_VLAN_ACTION;
typedef enum _GMAC_RX_PACKET_TYPE_ {
TYPE_ETHERNET = 0,
TYPE_IPV4 = 1,
TYPE_IPV4_PPTP = 2,
TYPE_IPV4_ICMP = 3,
TYPE_IPV4_IGMP = 4,
TYPE_IPV4_TCP = 5,
TYPE_IPV4_UDP = 6,
TYPE_IPV6 = 7,
TYPE_ICMPV6 = 8,
TYPE_IPV6_TCP = 9,
TYPE_IPV6_UDP = 10
}GMAC_RX_PACKET_TYPE, *PGMAC_RX_PACKET_TYPE;
/*
// Memory Map of DW_apb_ssi
#define REG_DW_SSI_CTRLR0 0x00 // 16 bits
#define REG_DW_SSI_CTRLR1 0x04 // 16 bits
#define REG_DW_SSI_SSIENR 0x08 // 1 bit
#define REG_DW_SSI_RX_SAMPLE_DLY 0xF0 // 8 bits
#define REG_DW_SSI_RSVD_0 0xF4 // 32 bits
#define REG_DW_SSI_RSVD_1 0xF8 // 32 bits
#define REG_DW_SSI_RSVD_2 0xFC // 32 bits
// CTRLR0 0x00 // 16 bits, 6.2.1
// DFS Reset Value: 0x7
#define BIT_SHIFT_CTRLR0_DFS 0
#define BIT_MASK_CTRLR0_DFS 0xF
#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS)
#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS))
#define BIT_SHIFT_CTRLR0_FRF 4
#define BIT_MASK_CTRLR0_FRF 0x3
#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF)
#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF))
#define BIT_SHIFT_CTRLR0_SCPH 6
#define BIT_MASK_CTRLR0_SCPH 0x1
#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH)
#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH))
// CTRLR1 0x04 // 16 bits
#define BIT_SHIFT_CTRLR1_NDF 0
#define BIT_MASK_CTRLR1_NDF 0xFFFF
#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF)
#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF))
// TXFLTR 0x18 // Variable Length
#define BIT_SHIFT_TXFTLR_TFT 0
#define BIT_MASK_TXFTLR_TFT 0x3F // (TX_ABW-1):0
#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT)
#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT))
// TXFLR 0x20 // see [READ ONLY]
#define BIT_MASK_TXFLR_TXTFL 0x7F // (TX_ABW):0
// RXFLR 0x24 // see [READ ONLY]
#define BIT_MASK_RXFLR_RXTFL 0x7F // (RX_ABW):0
// SR 0x28 // 7 bits [READ ONLY]
#define BIT_SR_BUSY BIT0
#define BIT_SR_TFNF BIT1
#define BIT_SR_TFE BIT2
#define BIT_SR_RFNE BIT3
#define BIT_SR_RFF BIT4
#define BIT_SR_TXE BIT5
#define BIT_SR_DCOL BIT6
#define BIT_IMR_TXEIM BIT0
#define BIT_IMR_TXOIM BIT1
#define BIT_IMR_RXUIM BIT2
#define BIT_IMR_RXOIM BIT3
#define BIT_IMR_RXFIM BIT4
#define BIT_IMR_MSTIM BIT5
// ISR 0x30 // 6 bits [READ ONLY]
#define BIT_ISR_TXEIS BIT0
#define BIT_ISR_TXOIS BIT1
#define BIT_ISR_RXUIS BIT2
#define BIT_ISR_RXOIS BIT3
#define BIT_ISR_RXFIS BIT4
#define BIT_ISR_MSTIS BIT5
*/
BOOL
HalMiiGmacInitRtl8195a(
IN VOID *Data
);
BOOL
HalMiiInitRtl8195a(
IN VOID *Data
);
BOOL
HalMiiGmacResetRtl8195a(
IN VOID *Data
);
BOOL
HalMiiGmacEnablePhyModeRtl8195a(
IN VOID *Data
);
u32
HalMiiGmacXmitRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacCleanTxRingRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacFillTxInfoRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacFillRxInfoRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacTxRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacRxRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacSetDefaultEthIoCmdRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacInitIrqRtl8195a(
IN VOID *Data
);
u32
HalMiiGmacGetInterruptStatusRtl8195a(
VOID
);
VOID
HalMiiGmacClearInterruptStatusRtl8195a(
u32 IsrStatus
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_NFC_H_
#define _RTL8195A_NFC_H_
#include "hal_api.h"
//#include "osdep_api.h"
#ifdef CONFIG_NFC_VERIFY
#include "../test/nfc/rtl8195a_nfc_test.h"
#endif
#if CONFIG_NFC_NORMAL
//===================== Register Bit Field Definition =====================
// TODO:
//===================== Register Address Definition =====================
//TODO:
//#include "osdep_api.h"
#define N2A_Q_LENGTH 10
#define N2ARLENGTH 4
//#define NFCTAGLENGTH 36 // maximum 36*4=144 bytes
#define NFCTAG_BASE 0x7F000
#define NFCTAG_PAGESIZE 256
#define NFCTAG_MAXPAGEIDX 16//(4*(1024/NFCTAG_PAGESIZE))
#define A2NWCLENGTH 4
#define FLASHAPPLENGTH 31
#define FLASHAPP_BASE 0x7E000
#define FLASH_PAGESIZE 128
#define FLASH_MAXPAGEIDX 32//(4*(1024/FLASH_PAGESIZE))
typedef struct _A2N_CATCH_W_ {
//u8 Vaild;
u8 A2NCatchRPage;
u32 A2NCatchWData[A2NWCLENGTH];
}A2N_CATCH_W_QUEUE, *PA2N_CATCH_W_QUEUE;
typedef struct _A2N_MAILBOX_Q_ {
u8 Length;
u8 Response;
u32 Content[A2NWCLENGTH+1];
}A2N_MAILBOX_Q,*PA2N_MAILBOX_Q;
typedef struct _N2A_CATCH_R_ {
u8 Vaild;
u8 N2ACatchRPage;
u32 N2ACatchRData[N2ARLENGTH];
}N2A_CATCH_R_QUEUE, *PN2A_CATCH_R_QUEUE;
typedef struct _N2A_R_ {
u8 Vaild;
u8 N2ARPage;
}N2A_R_QUEUE, *PN2A_R_QUEUE;
typedef struct _N2A_W_ {
u8 Vaild;
u8 N2AWPage;
u32 N2AWData;
}N2A_W_QUEUE, *PN2A_W_QUEUE;
typedef struct _NFC_ADAPTER_ {
u8 Function;
u32 NFCIsr;
u8 N2ABoxOpen;
u8 A2NSeq;
//u8 NFCTagFlashWIdx;
//u8 NFCTagFlashRIdx;
// u32 NFCTag[NFCTAGLENGTH];
#if !TASK_SCHEDULER_DISABLED
void * VeriSema;
#else
u32 VeriSema;
#endif
#ifdef PLATFORM_FREERTOS
void * NFCTask;
#else
u32 NFCTask;
#endif
#ifdef CONFIG_NFC_VERIFY
//N2A Write Tag
u8 N2AWQRIdx;
u8 N2AWQWIdx;
N2A_W_QUEUE N2AWQ[N2A_Q_LENGTH];
//N2A Read Tag
u8 N2ARQRIdx;
u8 N2ARQWIdx;
N2A_R_QUEUE N2ARQ[N2A_Q_LENGTH];
//N2A Read Catch
u8 N2ARCRIdx;
u8 N2ARCWIdx;
N2A_CATCH_R_QUEUE N2ACatchR[N2A_Q_LENGTH];
#endif
//A2N Write Catch
//u8 A2NWCRIdx;
//u8 A2NWCWIdx;
//A2N_CATCH_W_QUEUE A2NCatchW[N2A_Q_LENGTH];
//A2N Write mailbox queue
u8 A2NWMailBox;
u8 A2NWQRIdx;
u8 A2NWQWIdx;
A2N_MAILBOX_Q A2NMAILQ[N2A_Q_LENGTH];
u8 TaskStop;
void *nfc_obj;
}NFC_ADAPTER, *PNFC_ADAPTER;
typedef enum _N2A_CMD_ {
TAG_READ = 0,
TAG_WRITE = 1,
CATCH_READ_DATA = 2,
NFC_R_PRESENT = 4,
N2A_MAILBOX_STATE = 5,
EXT_CLK_REQ = 6,
MAX_N2ACMD
} N2A_CMD, *PN2A_CMD;
typedef enum _A2N_CMD_ {
TAG_READ_DATA = 0,
CATCH_READ = 2,
CATCH_WRITE = 3,
A2N_MAILBOX_STATE = 4,
CONFIRM_N2A_BOX_STATE = 5,
EXT_CLK_RSP = 6,
MAX_A2NCMD
} A2N_CMD, *PA2N_CMD;
// Callback event defination
typedef enum _NFC_HAL_EVENT_ {
NFC_HAL_READER_PRESENT = (1<<0),
NFC_HAL_READ = (1<<1),
NFC_HAL_WRITE = (1<<2),
NFC_HAL_ERR = (1<<3),
NFC_HAL_CACHE_RD = (1<<4)
}NFC_CB_EVENT, *PNFC_CB_EVENT;
VOID A2NWriteCatch(IN VOID *pNFCAdapte, IN u8 N2AWPage,
IN u8 Length, IN u32 *WData);
VOID A2NReadCatch(IN VOID *pNFCAdapte, IN u8 A2NRPage);
VOID HalNFCDmemInit(IN u32 *pTagData, IN u32 TagLen);
VOID HalNFCInit(PNFC_ADAPTER pNFCAdp);
VOID HalNFCDeinit(PNFC_ADAPTER pNFCAdp);
VOID HalNFCFwDownload(VOID);
#endif //CONFIG_NFC_NORMAL
#endif // #ifndef _RTL8195A_NFC_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_PCM_H_
#define _RTL8195A_PCM_H_
#include "basic_types.h"
#include "hal_api.h"
#define HAL_PCMX_READ32(PcmIndex, addr) \
HAL_READ32(PCM0_REG_BASE+ (PcmIndex*PCM1_REG_OFF), addr)
#define HAL_PCMX_WRITE32(PcmIndex, addr, value) \
HAL_WRITE32((PCM0_REG_BASE+ (PcmIndex*PCM1_REG_OFF)), addr, value)
#define REG_PCM_TRXBSA_OFF 0x004
#define REG_PCM_CTL 0x000
#define REG_PCM_CHCNR03 0x004
#define REG_PCM_TSR03 0x008
#define REG_PCM_BSIZE03 0x00C
#define REG_PCM_CH0TXBSA 0x010
#define REG_PCM_CH1TXBSA 0x014
#define REG_PCM_CH2TXBSA 0x018
#define REG_PCM_CH3TXBSA 0x01c
#define REG_PCM_CH0RXBSA 0x020
#define REG_PCM_CH1RXBSA 0x024
#define REG_PCM_CH2RXBSA 0x028
#define REG_PCM_CH3RXBSA 0x02c
#define REG_PCM_IMR03 0x030
#define REG_PCM_ISR03 0x034
#define REG_PCM_CHCNR47 0x038
#define REG_PCM_TSR47 0x03c
#define REG_PCM_BSIZE47 0x040
#define REG_PCM_CH4TXBSA 0x044
#define REG_PCM_CH5TXBSA 0x048
#define REG_PCM_CH6TXBSA 0x04c
#define REG_PCM_CH7TXBSA 0x050
#define REG_PCM_CH4RXBSA 0x054
#define REG_PCM_CH5RXBSA 0x058
#define REG_PCM_CH6RXBSA 0x05c
#define REG_PCM_CH7RXBSA 0x060
#define REG_PCM_IMR47 0x064
#define REG_PCM_ISR47 0x068
#define REG_PCM_CHCNR811 0x06c
#define REG_PCM_TSR811 0x070
#define REG_PCM_BSIZE811 0x074
#define REG_PCM_CH8TXBSA 0x078
#define REG_PCM_CH9TXBSA 0x07c
#define REG_PCM_CH10TXBSA 0x080
#define REG_PCM_CH11TXBSA 0x084
#define REG_PCM_CH8RXBSA 0x088
#define REG_PCM_CH9RXBSA 0x08c
#define REG_PCM_CH10RXBSA 0x090
#define REG_PCM_CH11RXBSA 0x094
#define REG_PCM_IMR811 0x098
#define REG_PCM_ISR811 0x09c
#define REG_PCM_CHCNR1215 0x0a0
#define REG_PCM_TSR1215 0x0a4
#define REG_PCM_BSIZE1215 0x0a8
#define REG_PCM_CH12TXBSA 0x0ac
#define REG_PCM_CH13TXBSA 0x0b0
#define REG_PCM_CH14TXBSA 0x0b4
#define REG_PCM_CH15TXBSA 0x0b8
#define REG_PCM_CH12RXBSA 0x0bc
#define REG_PCM_CH13RXBSA 0x0c0
#define REG_PCM_CH14RXBSA 0x0c4
#define REG_PCM_CH15RXBSA 0x0c8
#define REG_PCM_IMR1215 0x0cc
#define REG_PCM_ISR1215 0x0d0
#define REG_PCM_INTMAP 0x0d4
#define REG_PCM_WTSR03 0x0d8
#define REG_PCM_WTSR47 0x0dc
#define REG_PCM_RX_BUFOW 0x0e0
/* template
#define BIT_SHIFT_CTLX_ 7
#define BIT_MASK_CTLX_ 0x1
#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_)
#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_))
*/
#define BIT_SHIFT_CTLX_SLAVE_SEL 8
#define BIT_MASK_CTLX_SLAVE_SEL 0x1
#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL)
#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL))
#define BIT_SHIFT_CTLX_FSINV 9
#define BIT_MASK_CTLX_FSINV 0x1
#define BIT_CTLX_FSINV(x) (((x) & BIT_MASK_CTLX_FSINV) << BIT_SHIFT_CTLX_FSINV)
#define BIT_INV_CTLX_FSINV (~(BIT_MASK_CTLX_FSINV << BIT_SHIFT_CTLX_FSINV))
#define BIT_SHIFT_CTLX_PCM_EN 12
#define BIT_MASK_CTLX_PCM_EN 0x1
#define BIT_CTLX_PCM_EN(x) (((x) & BIT_MASK_CTLX_PCM_EN) << BIT_SHIFT_CTLX_PCM_EN)
#define BIT_INV_CTLX_PCM_EN (~(BIT_MASK_CTLX_PCM_EN << BIT_SHIFT_CTLX_PCM_EN))
#define BIT_SHIFT_CTLX_LINEARMODE 13
#define BIT_MASK_CTLX_LINEARMODE 0x1
#define BIT_CTLX_LINEARMODE(x) (((x) & BIT_MASK_CTLX_LINEARMODE) << BIT_SHIFT_CTLX_LINEARMODE)
#define BIT_INV_CTLX_LINEARMODE (~(BIT_MASK_CTLX_LINEARMODE << BIT_SHIFT_CTLX_LINEARMODE))
#define BIT_SHIFT_CTLX_LOOP_BACK 14
#define BIT_MASK_CTLX_LOOP_BACK 0x1
#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK)
#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK))
#define BIT_SHIFT_CTLX_ENDIAN_SWAP 17
#define BIT_MASK_CTLX_ENDIAN_SWAP 0x1
#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP)
#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP))
#define BIT_SHIFT_CHCNR03_CH0RE 24
#define BIT_MASK_CHCNR03_CH0RE 0x1
#define BIT_CHCNR03_CH0RE(x) (((x) & BIT_MASK_CHCNR03_CH0RE) << BIT_SHIFT_CHCNR03_CH0RE)
#define BIT_INV_CHCNR03_CH0RE (~(BIT_MASK_CHCNR03_CH0RE << BIT_SHIFT_CHCNR03_CH0RE))
#define BIT_SHIFT_CHCNR03_CH0TE 25
#define BIT_MASK_CHCNR03_CH0TE 0x1
#define BIT_CHCNR03_CH0TE(x) (((x) & BIT_MASK_CHCNR03_CH0TE) << BIT_SHIFT_CHCNR03_CH0TE)
#define BIT_INV_CHCNR03_CH0TE (~(BIT_MASK_CHCNR03_CH0TE << BIT_SHIFT_CHCNR03_CH0TE))
#define BIT_SHIFT_CHCNR03_CH1RE 16
#define BIT_MASK_CHCNR03_CH1RE 0x1
#define BIT_CHCNR03_CH1RE(x) (((x) & BIT_MASK_CHCNR03_CH1RE) << BIT_SHIFT_CHCNR03_CH1RE)
#define BIT_INV_CHCNR03_CH1RE (~(BIT_MASK_CHCNR03_CH1RE << BIT_SHIFT_CHCNR03_CH1RE))
#define BIT_SHIFT_CHCNR03_CH1TE 17
#define BIT_MASK_CHCNR03_CH1TE 0x1
#define BIT_CHCNR03_CH1TE(x) (((x) & BIT_MASK_CHCNR03_CH1TE) << BIT_SHIFT_CHCNR03_CH1TE)
#define BIT_INV_CHCNR03_CH1TE (~(BIT_MASK_CHCNR03_CH1TE << BIT_SHIFT_CHCNR03_CH1TE))
#define BIT_SHIFT_CHCNR03_CH2RE 8
#define BIT_MASK_CHCNR03_CH2RE 0x1
#define BIT_CHCNR03_CH2RE(x) (((x) & BIT_MASK_CHCNR03_CH2RE) << BIT_SHIFT_CHCNR03_CH2RE)
#define BIT_INV_CHCNR03_CH2RE (~(BIT_MASK_CHCNR03_CH2RE << BIT_SHIFT_CHCNR03_CH2RE))
#define BIT_SHIFT_CHCNR03_CH2TE 9
#define BIT_MASK_CHCNR03_CH2TE 0x1
#define BIT_CHCNR03_CH2TE(x) (((x) & BIT_MASK_CHCNR03_CH2TE) << BIT_SHIFT_CHCNR03_CH2TE)
#define BIT_INV_CHCNR03_CH2TE (~(BIT_MASK_CHCNR03_CH2TE << BIT_SHIFT_CHCNR03_CH2TE))
#define BIT_SHIFT_CHCNR03_CH3RE 0
#define BIT_MASK_CHCNR03_CH3RE 0x1
#define BIT_CHCNR03_CH3RE(x) (((x) & BIT_MASK_CHCNR03_CH3RE) << BIT_SHIFT_CHCNR03_CH3RE)
#define BIT_INV_CHCNR03_CH3RE (~(BIT_MASK_CHCNR03_CH3RE << BIT_SHIFT_CHCNR03_CH3RE))
#define BIT_SHIFT_CHCNR03_CH3TE 1
#define BIT_MASK_CHCNR03_CH3TE 0x1
#define BIT_CHCNR03_CH3TE(x) (((x) & BIT_MASK_CHCNR03_CH3TE) << BIT_SHIFT_CHCNR03_CH3TE)
#define BIT_INV_CHCNR03_CH3TE (~(BIT_MASK_CHCNR03_CH3TE << BIT_SHIFT_CHCNR03_CH3TE))
#define BIT_SHIFT_CHCNR03_CH0MUA 26
#define BIT_MASK_CHCNR03_CH0MUA 0x1
#define BIT_CHCNR03_CH0MUA(x) (((x) & BIT_MASK_CHCNR03_CH0MUA) << BIT_SHIFT_CHCNR03_CH0MUA)
#define BIT_INV_CHCNR03_CH0MUA (~(BIT_MASK_CHCNR03_CH0MUA << BIT_SHIFT_CHCNR03_CH0MUA))
#define BIT_SHIFT_CHCNR03_CH0BAND 27
#define BIT_MASK_CHCNR03_CH0BAND 0x1
#define BIT_CHCNR03_CH0BAND(x) (((x) & BIT_MASK_CHCNR03_CH0BAND) << BIT_SHIFT_CHCNR03_CH0BAND)
#define BIT_INV_CHCNR03_CH0BAND (~(BIT_MASK_CHCNR03_CH0BAND << BIT_SHIFT_CHCNR03_CH0BAND))
#define BIT_SHIFT_TSR03_CH0TSA 24
#define BIT_MASK_TSR03_CH0TSA 0x1F
#define BIT_TSR03_CH0TSA(x) (((x) & BIT_MASK_TSR03_CH0TSA) << BIT_SHIFT_TSR03_CH0TSA)
#define BIT_INV_TSR03_CH0TSA (~(BIT_MASK_TSR03_CH0TSA << BIT_SHIFT_TSR03_CH0TSA))
#define BIT_SHIFT_BSIZE03_CH0BSIZE 24
#define BIT_MASK_BSIZE03_CH0BSIZE 0xFF
#define BIT_BSIZE03_CH0BSIZE(x) (((x) & BIT_MASK_BSIZE03_CH0BSIZE) << BIT_SHIFT_BSIZE03_CH0BSIZE)
#define BIT_INV_BSIZE03_CH0BSIZE (~(BIT_MASK_BSIZE03_CH0BSIZE << BIT_SHIFT_BSIZE03_CH0BSIZE))
typedef struct _PCM_CTL_REG_ {
u32 FCNT :8; // Bit 0-7
u32 SlaveMode :1; // Bit 8
u32 FsInv :1; // Bit 9
u32 Rsvd10to11 :1; // Bit 10-11
u32 Pcm_En :1; // Bit 12
u32 LinearMode :1; // Bit 13
u32 LoopBack :1; // Bit 14
u32 Rsvd15to16 :2; // Bit 15-16
u32 EndianSwap :1; // Bit 17
u32 Rsvd18to31 :14; // Bit 18-31
} PCM_CTL_REG, *PPCM_CTL_REG;
typedef struct _PCM_CHCNR03_REG_ {
u32 CH3RE :1; // Bit 0
u32 CH3TE :1; // Bit 1
u32 CH3MuA :1; // Bit 2
u32 CH3Band :1; // Bit 3
u32 CH3SlicSel:4; // Bit 4-7
u32 CH2RE :1; // Bit 8
u32 CH2TE :1; // Bit 9
u32 CH2MuA :1; // Bit 10
u32 CH2Band :1; // Bit 11
u32 CH2SlicSel:4; // Bit 12-15
u32 CH1RE :1; // Bit 16
u32 CH1TE :1; // Bit 17
u32 CH1MuA :1; // Bit 18
u32 CH1Band :1; // Bit 19
u32 CH1SlicSel:4; // Bit 20-23
u32 CH0RE :1; // Bit 24
u32 CH0TE :1; // Bit 25
u32 CH0MuA :1; // Bit 26
u32 CH0Band :1; // Bit 27
u32 CH0SlicSel:4; // Bit 28-31
}PCM_CHCNR03_REG, *PPCM_CHCNR03_REG;
typedef struct _PCM_TSR03_REG_ {
u32 CH3TSA :5; // Bit 0-4
u32 Rsvd5to7 :3; // Bit 5-7
u32 CH2TSA :5; // Bit 8-12
u32 Rsvd13to15:3; // Bit 13-15
u32 CH1TSA :5; // Bit 16-20
u32 Rsvd21to23:3; // Bit 21-23
u32 CH0TSA :5; // Bit 24-28
u32 Rsvd29to31:3; // Bit 29-31
}PCM_TSR03_REG, *PPCM_TSR03_REG;
typedef struct _PCM_BSIZE03_REG_ {
u32 CH3BSize :8; // Bit 0-7
u32 CH2BSize :8; // Bit 8-15
u32 CH1BSize :8; // Bit 16-23
u32 CH0BSize :8; // Bit 24-31
}PCM_BSIZE03_REG, *PPCM_BSIZE03_REG;
typedef struct _PCM_ISR03_REG_ {
u32 CH3RXP1UA :1; // Bit 0
u32 CH3RXP0UA :1; // Bit 1
u32 CH3TXP1UA :1; // Bit 2
u32 CH3TXP0UA :1; // Bit 3
u32 CH3RXP1IP :1; // Bit 4
u32 CH3RXP0IP :1; // Bit 5
u32 CH3TXP1IP :1; // Bit 6
u32 CH3TXP0IP :1; // Bit 7
u32 CH2RXP1UA :1; // Bit 8
u32 CH2RXP0UA :1; // Bit 9
u32 CH2TXP1UA :1; // Bit 10
u32 CH2TXP0UA :1; // Bit 11
u32 CH2RXP1IP :1; // Bit 12
u32 CH2RXP0IP :1; // Bit 13
u32 CH2TXP1IP :1; // Bit 14
u32 CH2TXP0IP :1; // Bit 15
u32 CH1RXP1UA :1; // Bit 16
u32 CH1RXP0UA :1; // Bit 17
u32 CH1TXP1UA :1; // Bit 18
u32 CH1TXP0UA :1; // Bit 19
u32 CH1RXP1IP :1; // Bit 20
u32 CH1RXP0IP :1; // Bit 21
u32 CH1TXP1IP :1; // Bit 22
u32 CH1TXP0IP :1; // Bit 23
u32 CH0RXP1UA :1; // Bit 24
u32 CH0RXP0UA :1; // Bit 25
u32 CH0TXP1UA :1; // Bit 26
u32 CH0TXP0UA :1; // Bit 27
u32 CH0RXP1IP :1; // Bit 28
u32 CH0RXP0IP :1; // Bit 29
u32 CH0TXP1IP :1; // Bit 30
u32 CH0TXP0IP :1; // Bit 31
}PCM_ISR03_REG, *PPCM_ISR03_REG;
typedef enum _PCM_ISR015 {
PcmCh3P1RBU = 0x00000001, //ch0-3
PcmCh3P0RBU = 0x00000002,
PcmCh3P1TBU = 0x00000004,
PcmCh3P0TBU = 0x00000008,
PcmCh3P1ROK = 0x00000010,
PcmCh3P0ROK = 0x00000020,
PcmCh3P1TOK = 0x00000040,
PcmCh3P0TOK = 0x00000080,
PcmCh2P1RBU = 0x00000100,
PcmCh2P0RBU = 0x00000200,
PcmCh2P1TBU = 0x00000400,
PcmCh2P0TBU = 0x00000800,
PcmCh2P1ROK = 0x00001000,
PcmCh2P0ROK = 0x00002000,
PcmCh2P1TOK = 0x00004000,
PcmCh2P0TOK = 0x00008000,
PcmCh1P1RBU = 0x00010000,
PcmCh1P0RBU = 0x00020000,
PcmCh1P1TBU = 0x00040000,
PcmCh1P0TBU = 0x00080000,
PcmCh1P1ROK = 0x00100000,
PcmCh1P0ROK = 0x00200000,
PcmCh1P1TOK = 0x00400000,
PcmCh1P0TOK = 0x00800000,
PcmCh0P1RBU = 0x01000000,
PcmCh0P0RBU = 0x02000000,
PcmCh0P1TBU = 0x04000000,
PcmCh0P0TBU = 0x08000000,
PcmCh0P1ROK = 0x10000000,
PcmCh0P0ROK = 0x20000000,
PcmCh0P1TOK = 0x40000000,
PcmCh0P0TOK = 0x80000000,
PcmCh7P1RBU = 0x00000001, //ch4-7
PcmCh7P0RBU = 0x00000002,
PcmCh7P1TBU = 0x00000004,
PcmCh7P0TBU = 0x00000008,
PcmCh7P1ROK = 0x00000010,
PcmCh7P0ROK = 0x00000020,
PcmCh7P1TOK = 0x00000040,
PcmCh7P0TOK = 0x00000080,
PcmCh6P1RBU = 0x00000100,
PcmCh6P0RBU = 0x00000200,
PcmCh6P1TBU = 0x00000400,
PcmCh6P0TBU = 0x00000800,
PcmCh6P1ROK = 0x00001000,
PcmCh6P0ROK = 0x00002000,
PcmCh6P1TOK = 0x00004000,
PcmCh6P0TOK = 0x00008000,
PcmCh5P1RBU = 0x00010000,
PcmCh5P0RBU = 0x00020000,
PcmCh5P1TBU = 0x00040000,
PcmCh5P0TBU = 0x00080000,
PcmCh5P1ROK = 0x00100000,
PcmCh5P0ROK = 0x00200000,
PcmCh5P1TOK = 0x00400000,
PcmCh5P0TOK = 0x00800000,
PcmCh4P1RBU = 0x01000000,
PcmCh4P0RBU = 0x02000000,
PcmCh4P1TBU = 0x04000000,
PcmCh4P0TBU = 0x08000000,
PcmCh4P1ROK = 0x10000000,
PcmCh4P0ROK = 0x20000000,
PcmCh4P1TOK = 0x40000000,
PcmCh4P0TOK = 0x80000000,
PcmCh11P1RBU = 0x00000001, //ch8-11
PcmCh11P0RBU = 0x00000002,
PcmCh11P1TBU = 0x00000004,
PcmCh11P0TBU = 0x00000008,
PcmCh11P1ROK = 0x00000010,
PcmCh11P0ROK = 0x00000020,
PcmCh11P1TOK = 0x00000040,
PcmCh11P0TOK = 0x00000080,
PcmCh10P1RBU = 0x00000100,
PcmCh10P0RBU = 0x00000200,
PcmCh10P1TBU = 0x00000400,
PcmCh10P0TBU = 0x00000800,
PcmCh10P1ROK = 0x00001000,
PcmCh10P0ROK = 0x00002000,
PcmCh10P1TOK = 0x00004000,
PcmCh10P0TOK = 0x00008000,
PcmCh9P1RBU = 0x00010000,
PcmCh9P0RBU = 0x00020000,
PcmCh9P1TBU = 0x00040000,
PcmCh9P0TBU = 0x00080000,
PcmCh9P1ROK = 0x00100000,
PcmCh9P0ROK = 0x00200000,
PcmCh9P1TOK = 0x00400000,
PcmCh9P0TOK = 0x00800000,
PcmCh8P1RBU = 0x01000000,
PcmCh8P0RBU = 0x02000000,
PcmCh8P1TBU = 0x04000000,
PcmCh8P0TBU = 0x08000000,
PcmCh8P1ROK = 0x10000000,
PcmCh8P0ROK = 0x20000000,
PcmCh8P1TOK = 0x40000000,
PcmCh8P0TOK = 0x80000000,
PcmCh15P1RBU = 0x00000001, //ch12-15
PcmCh15P0RBU = 0x00000002,
PcmCh15P1TBU = 0x00000004,
PcmCh15P0TBU = 0x00000008,
PcmCh15P1ROK = 0x00000010,
PcmCh15P0ROK = 0x00000020,
PcmCh15P1TOK = 0x00000040,
PcmCh15P0TOK = 0x00000080,
PcmCh14P1RBU = 0x00000100,
PcmCh14P0RBU = 0x00000200,
PcmCh14P1TBU = 0x00000400,
PcmCh14P0TBU = 0x00000800,
PcmCh14P1ROK = 0x00001000,
PcmCh14P0ROK = 0x00002000,
PcmCh14P1TOK = 0x00004000,
PcmCh14P0TOK = 0x00008000,
PcmCh13P1RBU = 0x00010000,
PcmCh13P0RBU = 0x00020000,
PcmCh13P1TBU = 0x00040000,
PcmCh13P0TBU = 0x00080000,
PcmCh13P1ROK = 0x00100000,
PcmCh13P0ROK = 0x00200000,
PcmCh13P1TOK = 0x00400000,
PcmCh13P0TOK = 0x00800000,
PcmCh12P1RBU = 0x01000000,
PcmCh12P0RBU = 0x02000000,
PcmCh12P1TBU = 0x04000000,
PcmCh12P0TBU = 0x08000000,
PcmCh12P1ROK = 0x10000000,
PcmCh12P0ROK = 0x20000000,
PcmCh12P1TOK = 0x40000000,
PcmCh12P0TOK = 0x80000000
}PCM_ISR015, *PPCM_ISR015;
VOID
HalPcmOnOffRtl8195a(
IN VOID *Data
);
BOOL
HalPcmInitRtl8195a(
IN VOID *Data
);
BOOL
HalPcmSettingRtl8195a(
IN VOID *Data
);
BOOL
HalPcmEnRtl8195a(
IN VOID *Data
);
BOOL
HalPcmIsrEnAndDisRtl8195a(
IN VOID *Data
);
BOOL
HalPcmDumpRegRtl8195a(
IN VOID *Data
);
BOOL
HalPcmRtl8195a(
IN VOID *Data
);
#endif /* _RTL8195A_PCM_H_ */

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_PWM_H_
#define _RTL8195A_PWM_H_
extern void
HAL_Pwm_SetDuty_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern HAL_Status
HAL_Pwm_Init_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Enable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Disable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_SDIO_HOST_H_
#define _RTL8195A_SDIO_HOST_H_
#include "hal_api.h"
#include "osdep_api.h"
#ifdef CONFIG_SDIO_HOST_VERIFY
#define HAL_MMC_HOST_READ32(addr) HAL_READ32(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE32(addr, value) HAL_WRITE32(SDIO_HOST_REG_BASE, addr, value)
#define HAL_MMC_HOST_READ16(addr) HAL_READ16(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE16(addr, value) HAL_WRITE16(SDIO_HOST_REG_BASE, addr, value)
#define HAL_MMC_HOST_READ8(addr) HAL_READ8(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE8(addr, value) HAL_WRITE8(SDIO_HOST_REG_BASE, addr, value)
/* RTL8195A Register */
// REG_SOC_HCI_COM_FUNC_EN (0x214)
#define SD_DEVICE_IP_ON_BLK BIT0
#define SD_DEVICE_IP_OFF_BLK BIT1
#define SD_HOST_IP_BLK BIT2
// REG_PESOC_HCI_CLK_CTRL0 (0x240)
#define SD_HOST_CLKEN_IN_CPU_RUN_MODE BIT2
// REG_HCI_PINMUX_CTRL (0x2A0)
#define SD_DEVICE_MODE_PINMUX_EN BIT0
#define SD_HOST_MODE_PINMUX_EN BIT1
// 0x40059000
#define SD_HOST_CARD_DETECT_CIRCUIT BIT10
/* SD Host Register */
#define REG_SDMA_SYS_ADDR_ARG 0x00 // 4byte
#define REG_BLOCK_SIZE 0x04 // 2byte
#define REG_BLOCK_COUNT 0x06 // 2byte
#define REG_ARGUMENT1 0x08 // 4byte
#define REG_TRANSFER_MODE 0x0C // 2byte
#define REG_COMMAND 0x0E // 2byte
#define REG_RESPONSE0 0x10 // 4byte
#define REG_RESPONSE2 0x14 // 4byte
#define REG_RESPONSE4 0x18 // 4byte
#define REG_RESPONSE6 0x1C // 4byte
#define REG_BUFFER_DATA_PORT 0x20 // 4byte
#define REG_PRESENT_STATE 0x24 // 4byte
#define REG_HOST_CONTROL1 0x28 // 1byte
#define REG_POWER_CONTROL 0x29 // 1byte
#define REG_BLOCK_GAP_CONTROL 0x2A // 1byte
#define REG_WAKEUP_CONTROL 0x2B // 1byte
#define REG_CLOCK_CONTROL 0x2C // 2byte
#define REG_TIMEOUT_CONTROL 0x2E // 1byte
#define REG_SW_RESET 0x2F // 1byte
#define REG_NORMAL_INT_STATUS 0x30 // 2byte
#define REG_ERROR_INT_STATUS 0x32 // 2byte
#define REG_NORMAL_INT_STATUS_ENABLE 0x34 // 2byte
#define REG_ERROR_INT_STATUS_ENABLE 0x36 // 2byte
#define REG_NORMAL_INT_SIGNAL_ENABLE 0x38 // 2byte
#define REG_ERROR_INT_SIGNAL_ENABLE 0x3A // 2byte
#define REG_CAPABILITIES 0x40 // 8byte
#define REG_ADMA_ADDRESS 0x58 // 8byte
// Transfer Mode (0x0C)
#define BIT_DMA_EN BIT0
#define BIT_BLK_CNT_EN BIT1
#define BIT_AUTO_CMD12_EN BIT2
#define BIT_AUTO_CMD23_EN BIT3
#define BIT_READ_TRANS BIT4
#define BIT_MULTI_BLK BIT5
// Present State (0x24)
#define BIT_CMD_INHIBIT_CMD BIT0
#define BIT_CMD_INHIBIT_DAT BIT1
#define BIT_CARD_INSERTED BIT16
#define BIT_WRITE_PROTECT_SWITCH_PIN BIT19
// Power Control (0x29)
#define BIT_POWER_33 0xE
#define BIT_POWER_30 0xC
#define BIT_POWER_18 0xA
// Clock Control (0x2C)
#define BIT_INTERNAL_CLK_EN BIT0
#define BIT_INTERNAL_CLK_STABLE BIT1
#define BIT_SD_CLK_EN BIT2
// Software Reset (0x2F)
#define BIT_SW_RESET_ALL BIT0
#define BIT_SW_RESET_CMD_LINE BIT1
#define BIT_SW_RESET_DAT_LINE BIT2
// Norma Interrupt Status (0x30)
#define BIT_COMMAND_COMPLETE BIT0
#define BIT_TRANSFER_COMPLETE BIT1
#define BIT_BLOCK_GAP_EVENT BIT2
#define BIT_DMA_INT BIT3
#define BIT_BUFFER_WRITE_RDY BIT4
#define BIT_BUFFER_READ_RDY BIT5
#define BIT_CARD_INSERTION BIT6
#define BIT_CARD_REMOVAL BIT7
#define BIT_CARD_INT BIT8
#define BIT_ERROR_INT BIT15
// Error Interrupt Status (0x32)
#define BIT_DATA_TIME_OUT_ERROR BIT4
#define BIT_DATA_CRC_ERROR BIT5
#define BIT_ADMA_ERROR BIT9
// Capabilities (0x40)
#define BIT_VDD_33 BIT24
#define BIT_VDD_30 BIT25
#define BIT_VDD_18 BIT26
#define ENABLE 1
#define DISABLE 0
#define ADMA_DESC_NUM 50
#define BUFFER_UNIT_SIZE 512
typedef enum _MMC_HOST_TEST_FUNC_ {
MMC_HOST_TEST_HW_INIT, // 0
MMC_HOST_TEST_CARD_INIT, // 1
MMC_HOST_TEST_SEND_CMD, // 2
MMC_HOST_TEST_DEBUG, // 3
MMC_HOST_TEST_SW_RESET, // 4
MMC_HOST_TEST_READ_SINGLE, // 5
MMC_HOST_TEST_WRITE_SINGLE, // 6
MMC_HOST_TEST_READ_MULTI, // 7
MMC_HOST_TEST_WRITE_MULTI, // 8
MMC_HOST_TEST_SINGLE_LONGRUN, // 9
MMC_HOST_TEST_MULTI_LONGRUN, // 10
MMC_HOST_TEST_CARD_DETECTION, // 11
MMC_HOST_TEST_WRITE_PROTECT, // 12
MMC_HOST_TEST_REGISTER_RW // 13
}MMC_HOST_TEST_FUNC;
typedef enum _RESPONSE_TYPE_ {
No_Response, // 00b
Response_136, // 01b
Response_48, // 10b
Response_48_Busy // 11b
}RESPONSE_TYPE;
typedef enum _COMMAND_TYPE_ {
Normal, // 00b
Suspend, // 01b
Resume, // 10b
Abort // 11b
}COMMAND_TYPE;
typedef enum _DATA_PRESENT_ {
No_Data_Present, // 00b
Data_Present, // 01b
}DATA_PRESENT;
typedef enum _SUPPLY_VOLTAGE_ {
MMC_VDD_27_28 = BIT15,
MMC_VDD_28_29 = BIT16,
MMC_VDD_29_30 = BIT17,
MMC_VDD_30_31 = BIT18,
MMC_VDD_31_32 = BIT19,
MMC_VDD_32_33 = BIT20,
MMC_VDD_33_34 = BIT21,
MMC_VDD_34_35 = BIT22,
MMC_VDD_35_36 = BIT23,
}SUPPLY_VOLTAGE;
typedef enum _COMMAND_INDEX_ {
GO_IDLE_STATE = 0,
ALL_SEND_CID = 2,
SEND_RELATIVE_ADDR = 3,
SET_BUS_WIDTH = 6,
SELECT_CARD = 7,
SEND_IF_COND = 8,
SEND_CSD = 9,
STOP_TRANSMISSION = 12,
SEND_STATUS = 13,
READ_SINGLE_BLOCK = 17,
READ_MULTIPLE_BLOCK = 18,
WRITE_BLOCK = 24,
WRITE_MULTIPLE_BLOCK = 25,
SD_SEND_OP_COND = 41,
APP_CMD = 55,
}COMMAND_INDEX;
typedef enum _TRANSFER_CONFIG_ {
Read_Data = 0,
Write_Data = 1,
Single_Block = 0,
Multiple_Block = 1,
}TRANSFER_CONFIG;
typedef enum _ERROR_STATUS_ {
General_Error, // 0
CRC_Error, // 1
TIME_OUT_ERROR, // 2
CRC_Error_NeedCMD12, // 3
Transfer_OK // 4
}ERROR_STATUS;
typedef enum _CARD_CURRENT_STATE_ {
IDLE_STATE,
READY_STATE,
IDENT_STATE,
STBY_STATE,
TRAN_STATE,
DATA_STATE,
RCV_STATE,
PRG_STATE,
DIS_STATE,
UNKNOWN_STATE
}CARD_CURRENT_STATE;
typedef struct _COMMAND_FORMAT_
{
u16 Resp_Type:2;
u16 Rsvd0:1;
u16 CMD_CRC_Chk:1;
u16 CMD_Idx_Chk:1;
u16 Data_Present:1;
u16 CMD_Type:2;
u16 CMD_Idx:6;
u16 Rsvd1:2;
}COMMAND_FORMAT, *PCOMMAND_FPRMAT;
typedef struct _MMC_COMMAND
{
COMMAND_FORMAT Cmd_Format;
u32 Arg;
}MMC_COMMAND;
typedef struct _MMC_HOST_
{
u32 OCR_Avail;
u32 Resp[4];
u32 CID[4];
u32 RCA;
}MMC_HOST, *PMMC_HOST;
typedef struct _ADMA_ATTR_
{
u16 Valid:1;
u16 End:1;
u16 Int:1;
u16 Rsvd1:1;
u16 Act1:1;
u16 Act2:1;
u16 Rsvd2:10;
}ADMA_ATTR, *PADMA_ATTR;
// 24 bytes
typedef struct _ADMA_DESC_TABLE_
{
// 1st buffer desc
ADMA_ATTR Attribute1;
u16 Length1;
u32 Address1;
// 2nd buffer desc
ADMA_ATTR Attribute2;
u16 Length2;
u32 Address2;
// 3rd buffer desc
ADMA_ATTR Attribute3;
u16 Length3;
u32 Address3;
}ADMA_DESC_TABLE, *PADMA_DESC_TABLE;
// 1024 bytes
typedef struct _ADMA_BUFFER_
{
u8 Data1[512]; /* 1st buffer */
u8 Data2[512]; /* 2nd buffer */
}ADMA_BUFFER, *PADMA_BUFFER;
VOID
SdHostTestApp(
IN u8 *argv[]
);
#endif // end of "#ifdef CONFIG_SDIO_HOST_VERIFY"
#endif /* #ifndef _RTL8195A_SDIO_HOST_H_ */

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#ifndef _RTL8195A_SDR_H
#define _RTL8195A_SDR_H
#define MS_0_CTRL_BASE BSP_MS_I_DRAMC_0_BASE
#define MS_0_CTRL_PHY_BASE (BSP_MS_I_DRAMC_0_BASE)
#define MS_0_WRAP_BASE (MS_0_CTRL_BASE + 0x200)
#define MS_1_CTRL_BASE BSP_MS_I_DRAMC_1_BASE
#define MS_1_CTRL_PHY_BASE (BSP_MS_I_DRAMC_1_BASE)
#define MS_1_WRAP_BASE (MS_1_CTRL_BASE + 0x200)
#define MS_PCTL_CCR_OFFSET 0x000
#define MS_PCTL_DCR_OFFSET 0x004
#define MS_PCTL_IOCR_OFFSET 0x008
#define MS_PCTL_CSR_OFFSET 0x00c
#define MS_PCTL_DRR_OFFSET 0x010
#define MS_PCTL_TPR0_OFFSET 0x014
#define MS_PCTL_TPR1_OFFSET 0x018
#define MS_PCTL_TPR2_OFFSET 0x01c
#define MS_PCTL_MR_OFFSET 0x020
#define MS_PCTL_EMR1_OFFSET 0x024
#define MS_PCTL_EMR2_OFFSET 0x028
#define MS_PCTL_EMR3_OFFSET 0x02c
#define MS_PCTL_CSR2_OFFSET 0x030
#define MS_PCTL_SRST_OFFSET 0x034
#define MS_PCTL_DTR2_OFFSET 0x038
#define MS_PCTL_DTR3_OFFSET 0x03c
#define MS_PCTL_GDLLCR_OFFSET 0x040
#define MS_PCTL_DLLCR0_OFFSET 0x044
#define MS_PCTL_DLLCR1_OFFSET 0x048
#define MS_PCTL_DLLCR2_OFFSET 0x04c
#define MS_PCTL_DLLCR3_OFFSET 0x050
#define MS_PCTL_DLLCR4_OFFSET 0x054
#define MS_PCTL_DLLCR5_OFFSET 0x058
#define MS_PCTL_DLLCR6_OFFSET 0x05c
#define MS_PCTL_DLLCR7_OFFSET 0x060
#define MS_PCTL_DLLCR8_OFFSET 0x064
#define MS_PCTL_DQTR0_OFFSET 0x068
#define MS_PCTL_DQTR1_OFFSET 0x06c
#define MS_PCTL_DQTR2_OFFSET 0x070
#define MS_PCTL_DQTR3_OFFSET 0x074
#define MS_PCTL_DQTR4_OFFSET 0x078
#define MS_PCTL_DQTR5_OFFSET 0x07c
#define MS_PCTL_DQTR6_OFFSET 0x080
#define MS_PCTL_DQTR7_OFFSET 0x084
#define MS_PCTL_DQSTR_OFFSET 0x088
#define MS_PCTL_DQSBTR_OFFSET 0x08c
#define MS_PCTL_ODTCR_OFFSET 0x090
#define MS_PCTL_DTR0_OFFSET 0x094
#define MS_PCTL_DTR1_OFFSET 0x098
#define MS_PCTL_DTAR_OFFSET 0x09c
#define MS_PCTL_ZQCR0_OFFSET 0x0a0
#define MS_PCTL_ZQCR1_OFFSET 0x0a4
#define MS_PCTL_ZQSR_OFFSET 0x0a8
#define MS_PCTL_RSLR0_OFFSET 0x0ac
#define MS_PCTL_RSLR1_OFFSET 0x0b0
#define MS_PCTL_RSLR2_OFFSET 0x0b4
#define MS_PCTL_RSLR3_OFFSET 0x0b8
#define MS_PCTL_RDGR0_OFFSET 0x0bc
#define MS_PCTL_RDGR1_OFFSET 0x0c0
#define MS_PCTL_RDGR2_OFFSET 0x0c4
#define MS_PCTL_RDGR3_OFFSET 0x0c8
#define MS_PCTL_MXSL_OFFSET 0x0cc
#define MS_PCTL_BCR_OFFSET 0x0d0
#define MS_PCTL_BALR0_OFFSET 0x0d4
#define MS_PCTL_BALR1_OFFSET 0x0d8
#define MS_PCTL_BDR0_OFFSET 0x0dc
#define MS_PCTL_BDR1_OFFSET 0x0e0
#define MS_PCTL_BBR_OFFSET 0x0e4
#define MS_PCTL_BSR_OFFSET 0x0e8
#define MS_PCTL_BYR_OFFSET 0x0ec
#define MS_PCTL_BFA_OFFSET 0x0f0
#define MS_PCTL_IDR_OFFSET 0x0f8
#define MS_PCTL_ERR_OFFSET 0x0fc
#define MS_WRAP_SCR_OFFSET 0x224
#define MS_WRAP_QCR_OFFSET 0x230
#define MS_WRAP_PCR_OFFSET 0x234
#define MS_WRAP_QTR0_OFFSET 0x240
#define MS_WRAP_QTR1_OFFSET 0x244
#define MS_WRAP_QTR2_OFFSET 0x248
#define MS_WRAP_QTR3_OFFSET 0x24c
#define MS_WRAP_QTR4_OFFSET 0x250
#define MS_WRAP_QTR5_OFFSET 0x254
#define MS_WRAP_QTR6_OFFSET 0x258
#define MS_WRAP_QTR7_OFFSET 0x25c
#define MS_WRAP_QTR8_OFFSET 0x260
#define MS_WRAP_QTR9_OFFSET 0x264
#define MS_WRAP_QTR10_OFFSET 0x268
#define MS_WRAP_QTR11_OFFSET 0x26c
#define MS_WRAP_QTR12_OFFSET 0x270
#define MS_WRAP_QTR13_OFFSET 0x274
#define MS_WRAP_QTR14_OFFSET 0x278
#define MS_WRAP_QTR15_OFFSET 0x27c
#define MS_PHY_DLY0 0x100
#define MS_PHY_DLY1_RST 0x104
#define MS_PHY_DLY_CLK 0x108
#define MS_PHY_DLY_ST 0x10c
#define MS_PHY_DLY_NUM 0x100
#define PCTL_CCR_INIT_BFO 0
#define PCTL_CCR_INIT_BFW 1
#define PCTL_CCR_DTT_BFO 1
#define PCTL_CCR_DTT_BFW 1
#define PCTL_CCR_BTT_BFO 2
#define PCTL_CCR_BTT_BFW 1
#define PCTL_CCR_DPIT_BFO 3
#define PCTL_CCR_DPIT_BFW 1
#define PCTL_CCR_FLUSH_FIFO_BFO 8
#define PCTL_CCR_FLUSH_FIFO_BFW 1
#define PCTL_DCR_DDR3_BFO 0
#define PCTL_DCR_DDR3_BFW 1
#define PCTL_DCR_SDR_BFO 1
#define PCTL_DCR_SDR_BFW 1
#define PCTL_DCR_DQ32_BFO 4
#define PCTL_DCR_DQ32_BFW 1
#define PCTL_DCR_DFI_RATE_BFO 8
#define PCTL_DCR_DFI_RATE_BFW 3
#define PCTL_IOCR_RD_PIPE_BFO 8
#define PCTL_IOCR_RD_PIPE_BFW 4
#define PCTL_IOCR_TPHY_WD_BFO 12
#define PCTL_IOCR_TPHY_WD_BFW 5
#define PCTL_IOCR_TPHY_WL_BFO 17
#define PCTL_IOCR_TPHY_WL_BFW 3
#define PCTL_IOCR_TPHY_RD_EN_BFO 20
#define PCTL_IOCR_TPHY_RD_EN_BFW 5
#define PCTL_CSR_MEM_IDLE_BFO 8
#define PCTL_CSR_MEM_IDLE_BFW 1
#define PCTL_CSR_DT_IDLE_BFO 9
#define PCTL_CSR_DT_IDLE_BFW 1
#define PCTL_CSR_BIST_IDLE_BFO 10
#define PCTL_CSR_BIST_IDLE_BFW 1
#define PCTL_CSR_DT_FAIL_BFO 11
#define PCTL_CSR_DT_FAIL_BFW 1
#define PCTL_CSR_BT_FAIL_BFO 12
#define PCTL_CSR_BT_FAIL_BFW 1
#define PCTL_DRR_TRFC_BFO 0
#define PCTL_DRR_TRFC_BFW 7
#define PCTL_DRR_TREF_BFO 8
#define PCTL_DRR_TREF_BFW 24
#define PCTL_DRR_REF_NUM_BFO 24
#define PCTL_DRR_REF_NUM_BFW 4
#define PCTL_DRR_REF_DIS_BFO 28
#define PCTL_DRR_REF_DIS_BFW 1
#define PCTL_TPR0_TRP_BFO 0
#define PCTL_TPR0_TRP_BFW 4
#define PCTL_TPR0_TRAS_BFO 4
#define PCTL_TPR0_TRAS_BFW 5
#define PCTL_TPR0_TWR_BFO 9
#define PCTL_TPR0_TWR_BFW 4
#define PCTL_TPR0_TRTP_BFO 13
#define PCTL_TPR0_TRTP_BFW 3
#define PCTL_TPR1_TRRD_BFO 0
#define PCTL_TPR1_TRRD_BFW 4
#define PCTL_TPR1_TRC_BFO 4
#define PCTL_TPR1_TRC_BFW 6
#define PCTL_TPR1_TRCD_BFO 10
#define PCTL_TPR1_TRCD_BFW 4
#define PCTL_TPR1_TCCD_BFO 14
#define PCTL_TPR1_TCCD_BFW 3
#define PCTL_TPR1_TWTR_BFO 17
#define PCTL_TPR1_TWTR_BFW 3
#define PCTL_TPR1_TRTW_BFO 20
#define PCTL_TPR1_TRTW_BFW 4
#define PCTL_TPR2_INIT_REF_NUM_BFO 0
#define PCTL_TPR2_INIT_REF_NUM_BFW 4
#define PCTL_TPR2_INIT_NS_EN_BFO 4
#define PCTL_TPR2_INIT_NS_EN_BFW 1
#define PCTL_TPR2_TMRD_BFO 5
#define PCTL_TPR2_TMRD_BFW 2
#define PCTL_MR_BL_BFO 0
#define PCTL_MR_BL_BFW 3
#define PCTL_MR_BT_BFO 3
#define PCTL_MR_BT_BFW 1
#define PCTL_MR_CAS_BFO 4
#define PCTL_MR_CAS_BFW 3
#define PCTL_MR_OP_BFO 8
#define PCTL_MR_OP_BFW 12
#define PCTL_EMR1_ADDLAT_BFO 3
#define PCTL_EMR1_ADDLAT_BFW 3
#define PCTL_CMD_DPIN_RSTN_BFO 0
#define PCTL_CMD_DPIN_RSTN_BFW 1
#define PCTL_CMD_DPIN_CKE_BFO 1
#define PCTL_CMD_DPIN_CKE_BFW 1
#define PCTL_CMD_DPIN_ODT_BFO 2
#define PCTL_CMD_DPIN_ODT_BFW 1
#define PCTL_BCR_STOP_BFO 0
#define PCTL_BCR_STOP_BFW 1
#define PCTL_BCR_CMP_BFO 1
#define PCTL_BCR_CMP_BFW 1
#define PCTL_BCR_LOOP_BFO 2
#define PCTL_BCR_LOOP_BFW 1
#define PCTL_BCR_DIS_MASK_BFO 3
#define PCTL_BCR_DIS_MASK_BFW 1
#define PCTL_BCR_AT_STOP_BFO 4
#define PCTL_BCR_AT_STOP_BFW 1
#define PCTL_BCR_FLUSH_CMD_BFO 8
#define PCTL_BCR_FLUSH_CMD_BFW 1
#define PCTL_BCR_FLUSH_WD_BFO 9
#define PCTL_BCR_FLUSH_WD_BFW 1
#define PCTL_BCR_FLUSH_RGD_BFO 10
#define PCTL_BCR_FLUSH_RGD_BFW 1
#define PCTL_BCR_FLUSH_RD_BFO 11
#define PCTL_BCR_FLUSH_RD_BFW 1
#define PCTL_BCR_FLUSH_RD_EXPC_BFO 16
#define PCTL_BCR_FLUSH_RD_EXPC_BFW 14
#define PCTL_BST_ERR_FST_TH_BFO 0
#define PCTL_BST_ERR_FST_TH_BFW 12
#define PCTL_BST_ERR_CNT_BFO 16
#define PCTL_BST_ERR_CNT_BFW 14
#define PCTL_BSRAM0_CMD_LEVEL_BFO 0
#define PCTL_BSRAM0_CMD_LEVEL_BFW 12
#define PCTL_BSRAM0_WD_LEVEL_BFO 16
#define PCTL_BSRAM0_WD_LEVEL_BFW 14
#define PCTL_BSRAM1_RG_LEVEL_BFO 0
#define PCTL_BSRAM1_RG_LEVEL_BFW 14
#define PCTL_BSRAM1_RD_LEVEL_BFO 16
#define PCTL_BSRAM1_RD_LEVEL_BFW 14
#define WRAP_MISC_PAGE_SIZE_BFO 0
#define WRAP_MISC_PAGE_SIZE_BFW 4
#define WRAP_MISC_BANK_SIZE_BFO 4
#define WRAP_MISC_BANK_SIZE_BFW 2
#define WRAP_MISC_BST_SIZE_BFO 6
#define WRAP_MISC_BST_SIZE_BFW 2
#define WRAP_MISC_DDR_PARAL_BFO 8
#define WRAP_MISC_DDR_PARAL_BFW 1
struct ms_rxi310_portmap {
volatile unsigned int ccr; /* 0x000 */
volatile unsigned int dcr; /* 0x004 */
volatile unsigned int iocr; /* 0x008 */
volatile unsigned int csr; /* 0x00c */
volatile unsigned int drr; /* 0x010 */
volatile unsigned int tpr0; /* 0x014 */
volatile unsigned int tpr1; /* 0x018 */
volatile unsigned int tpr2; /* 0x01c */
volatile unsigned int mr; /* 0x020 */
volatile unsigned int emr1; /* 0x024 */
volatile unsigned int emr2; /* 0x028 */
volatile unsigned int emr3; /* 0x02c */
volatile unsigned int cdpin; /* 0x030 */
volatile unsigned int tdpin; /* 0x034 */
volatile unsigned int dtr2; /* 0x038 */
volatile unsigned int dtr3; /* 0x03c */
volatile unsigned int gdllcr; /* 0x040 */
volatile unsigned int dllcr0; /* 0x044 */
volatile unsigned int dllcr1; /* 0x048 */
volatile unsigned int dllcr2; /* 0x04c */
volatile unsigned int dllcr3; /* 0x050 */
volatile unsigned int dllcr4; /* 0x054 */
volatile unsigned int dllcr5; /* 0x058 */
volatile unsigned int dllcr6; /* 0x05c */
volatile unsigned int dllcr7; /* 0x060 */
volatile unsigned int dllcr8; /* 0x064 */
volatile unsigned int dqtr0; /* 0x068 */
volatile unsigned int dqtr1; /* 0x06c */
volatile unsigned int dqtr2; /* 0x070 */
volatile unsigned int dqtr3; /* 0x074 */
volatile unsigned int dqtr4; /* 0x078 */
volatile unsigned int dqtr5; /* 0x07c */
volatile unsigned int dqtr6; /* 0x080 */
volatile unsigned int dqtr7; /* 0x084 */
volatile unsigned int dqstr; /* 0x088 */
volatile unsigned int dqsbtr; /* 0x08c */
volatile unsigned int odtcr; /* 0x090 */
volatile unsigned int dtr0; /* 0x094 */
volatile unsigned int dtr1; /* 0x098 */
volatile unsigned int dtar; /* 0x09c */
volatile unsigned int zqcr0; /* 0x0a0 */
volatile unsigned int zqcr1; /* 0x0a4 */
volatile unsigned int zqsr; /* 0x0a8 */
volatile unsigned int rslr0; /* 0x0ac */
volatile unsigned int rslr1; /* 0x0b0 */
volatile unsigned int rslr2; /* 0x0b4 */
volatile unsigned int rslr3; /* 0x0b8 */
volatile unsigned int rdgr0; /* 0x0bc */
volatile unsigned int rdgr1; /* 0x0c0 */
volatile unsigned int rdgr2; /* 0x0c4 */
volatile unsigned int rdgr3; /* 0x0c8 */
volatile unsigned int mxsl; /* 0x0cc */
volatile unsigned int bcr; /* 0x0d0 */
volatile unsigned int bst; /* 0x0d4 */
volatile unsigned int bsram0; /* 0x0d8 */
volatile unsigned int bsram1; /* 0x0dc */
volatile unsigned int bdr1; /* 0x0e0 */
volatile unsigned int bbr; /* 0x0e4 */
volatile unsigned int bsr; /* 0x0e8 */
volatile unsigned int byr; /* 0x0ec */
volatile unsigned int bfa; /* 0x0f0 */
volatile unsigned int pctl_svn; /* 0x0f4 */
volatile unsigned int pctl_idr; /* 0x0f8 */
volatile unsigned int err; /* 0x0fc */
// SDR_PHY CONTROL REGISTER
volatile unsigned int phy_dly0; /* 0x100 */
volatile unsigned int phy_dly1_rst; /* 0x104 */
volatile unsigned int phy_dly_clk; /* 0x108 */
volatile unsigned int phy_dly_st; /* 0x10c */
volatile unsigned int phy_dly_num; /* 0x110 */
volatile unsigned int reserved0[68];
// WRAP CONTROL REGISTER
volatile unsigned int misc; /* 0x224 */
volatile unsigned int cq_ver; /* 0x228 */
volatile unsigned int cq_mon; /* 0x22c */
volatile unsigned int wq_ver; /* 0x230 */
volatile unsigned int wq_mon; /* 0x234 */
volatile unsigned int rq_ver; /* 0x240 */
volatile unsigned int rq_mon; /* 0x244 */
volatile unsigned int reserved1[22];
volatile unsigned int wwrap_idr; /* 0x2a0 */
volatile unsigned int wrap_svn; /* 0x2a4 */
}; //ms_rxi310_portmap
#define QFIFO_CMD_BANK_BFO (35 - QFIFO_CMD_WRRD_BFO) // [38:35]
#define QFIFO_CMD_BANK_BFW 4
#define QFIFO_CMD_PAGE_BFO (20 - QFIFO_CMD_WRRD_BFO) // [34:20]
#define QFIFO_CMD_PAGE_BFW 15
#define QFIFO_CMD_COLU_BFO (7 - QFIFO_CMD_WRRD_BFO) // [19: 7]
#define QFIFO_CMD_COLU_BFW 13 // [19: 7]
#define QFIFO_BST_LEN_BFO (3 - QFIFO_CMD_WRRD_BFO) // [6:3]
#define QFIFO_BST_LEN_BFW 4 // [6:3]
#define QFIFO_CMD_WRRD_BFO 2 // [2], remove bit[1:0]
#define QFIFO_CMD_WRRD_BFW 1 // [2], remove bit[1:0]
//====================================================//
#define REG_SDR_CCR 0x00
#define REG_SDR_DCR 0x04
#define REG_SDR_IOCR 0x08
#define REG_SDR_CSR 0x0C
#define REG_SDR_DRR 0x10
#define REG_SDR_TPR0 0x14
#define REG_SDR_TPR1 0x18
#define REG_SDR_TPR2 0x1C
#define REG_SDR_MR 0x20
#define REG_SDR_EMR1 0x24
#define REG_SDR_EMR2 0x28
#define REG_SDR_EMR3 0x2C
#define REG_SDR_CMD_DPIN 0x30
#define REG_SDR_TIE_DPIN 0x34
#define REG_SDR_BCR 0xD0
#define REG_SDR_BST 0xD4
#define REG_SDR_BSRAM0 0xD8
#define REG_SDR_BSRAM1 0xDC
#define REG_SDR_PCTL_SVN_ID 0xF4
#define REG_SDR_PCTL_IDR 0xF8
#define REG_SDR_DLY0 0x100
#define REG_SDR_DLY1 0x104
#define REG_SDR_DCM_RST 0x104
#define REG_SDR_DLY_CLK_PHA 0x108
#define REG_SDR_DLY_ST 0x10C
#define REG_SDR_MISC 0x224
#define REG_SDR_OCP_WRAP_IDR 0x2A0
#define REG_SDR_OCP_WRAP_VERSION 0x2A4
#endif // end of "#ifndef _RTL8195A_SDR_H"

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lib/fwlib/rtl8195a/rtl8195a_spi_flash.h Normal file
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#ifndef _RTL8195A_SPI_FLASH_H
#define _RTL8195A_SPI_FLASH_H
#define CPU_OPT_WIDTH 0x1F
//2 REG_NOT_VALID
//2 REG_SPIC_CTRLR0
#define BIT_SHIFT_CK_MTIMES 23
#define BIT_MASK_CK_MTIMES 0x1f
#define BIT_CK_MTIMES(x) (((x) & BIT_MASK_CK_MTIMES) << BIT_SHIFT_CK_MTIMES)
#define BIT_CTRL_CK_MTIMES(x) (((x) & BIT_MASK_CK_MTIMES) << BIT_SHIFT_CK_MTIMES)
#define BIT_GET_CK_MTIMES(x) (((x) >> BIT_SHIFT_CK_MTIMES) & BIT_MASK_CK_MTIMES)
#define BIT_FAST_RD BIT(22)
#define BIT_SHIFT_FAST_RD 22
#define BIT_MASK_FAST_RD 0x1
#define BIT_CTRL_FAST_RD(x) (((x) & BIT_MASK_FAST_RD) << BIT_SHIFT_FAST_RD)
#define BIT_SHIFT_CMD_CH 20
#define BIT_MASK_CMD_CH 0x3
#define BIT_CMD_CH(x) (((x) & BIT_MASK_CMD_CH) << BIT_SHIFT_CMD_CH)
#define BIT_CTRL_CMD_CH(x) (((x) & BIT_MASK_CMD_CH) << BIT_SHIFT_CMD_CH)
#define BIT_GET_CMD_CH(x) (((x) >> BIT_SHIFT_CMD_CH) & BIT_MASK_CMD_CH)
#define BIT_SHIFT_DATA_CH 18
#define BIT_MASK_DATA_CH 0x3
#define BIT_DATA_CH(x) (((x) & BIT_MASK_DATA_CH) << BIT_SHIFT_DATA_CH)
#define BIT_CTRL_DATA_CH(x) (((x) & BIT_MASK_DATA_CH) << BIT_SHIFT_DATA_CH)
#define BIT_GET_DATA_CH(x) (((x) >> BIT_SHIFT_DATA_CH) & BIT_MASK_DATA_CH)
#define BIT_SHIFT_ADDR_CH 16
#define BIT_MASK_ADDR_CH 0x3
#define BIT_ADDR_CH(x) (((x) & BIT_MASK_ADDR_CH) << BIT_SHIFT_ADDR_CH)
#define BIT_CTRL_ADDR_CH(x) (((x) & BIT_MASK_ADDR_CH) << BIT_SHIFT_ADDR_CH)
#define BIT_GET_ADDR_CH(x) (((x) >> BIT_SHIFT_ADDR_CH) & BIT_MASK_ADDR_CH)
#define BIT_SHIFT_TMOD 8
#define BIT_MASK_TMOD 0x3
#define BIT_TMOD(x) (((x) & BIT_MASK_TMOD) << BIT_SHIFT_TMOD)
#define BIT_CTRL_TMOD(x) (((x) & BIT_MASK_TMOD) << BIT_SHIFT_TMOD)
#define BIT_GET_TMOD(x) (((x) >> BIT_SHIFT_TMOD) & BIT_MASK_TMOD)
#define BIT_SCPOL BIT(7)
#define BIT_SHIFT_SCPOL 7
#define BIT_MASK_SCPOL 0x1
#define BIT_CTRL_SCPOL(x) (((x) & BIT_MASK_SCPOL) << BIT_SHIFT_SCPOL)
#define BIT_SCPH BIT(6)
#define BIT_SHIFT_SCPH 6
#define BIT_MASK_SCPH 0x1
#define BIT_CTRL_SCPH(x) (((x) & BIT_MASK_SCPH) << BIT_SHIFT_SCPH)
//2 REG_SPIC_CTRLR1
#define BIT_SHIFT_NDF 0
#define BIT_MASK_NDF 0xfff
#define BIT_NDF(x) (((x) & BIT_MASK_NDF) << BIT_SHIFT_NDF)
#define BIT_CTRL_NDF(x) (((x) & BIT_MASK_NDF) << BIT_SHIFT_NDF)
#define BIT_GET_NDF(x) (((x) >> BIT_SHIFT_NDF) & BIT_MASK_NDF)
//2 REG_SPIC_SSIENR
#define BIT_ATCK_CMD BIT(1)
#define BIT_SHIFT_ATCK_CMD 1
#define BIT_MASK_ATCK_CMD 0x1
#define BIT_CTRL_ATCK_CMD(x) (((x) & BIT_MASK_ATCK_CMD) << BIT_SHIFT_ATCK_CMD)
#define BIT_SPIC_EN BIT(0)
#define BIT_SHIFT_SPIC_EN 0
#define BIT_MASK_SPIC_EN 0x1
#define BIT_CTRL_SPIC_EN(x) (((x) & BIT_MASK_SPIC_EN) << BIT_SHIFT_SPIC_EN)
//2 REG_SPIC_MWCR
//2 REG_SPIC_SER
#define BIT_SER BIT(0)
#define BIT_SHIFT_SER 0
#define BIT_MASK_SER 0x1
#define BIT_CTRL_SER(x) (((x) & BIT_MASK_SER) << BIT_SHIFT_SER)
//2 REG_SPIC_BAUDR
#define BIT_SHIFT_SCKDV 0
#define BIT_MASK_SCKDV 0xffff
#define BIT_SCKDV(x) (((x) & BIT_MASK_SCKDV) << BIT_SHIFT_SCKDV)
#define BIT_CTRL_SCKDV(x) (((x) & BIT_MASK_SCKDV) << BIT_SHIFT_SCKDV)
#define BIT_GET_SCKDV(x) (((x) >> BIT_SHIFT_SCKDV) & BIT_MASK_SCKDV)
//2 REG_SPIC_TXFTLR
#define BIT_SHIFT_TFT 0
#define BIT_MASK_TFT 0x1f
#define BIT_TFT(x) (((x) & BIT_MASK_TFT) << BIT_SHIFT_TFT)
#define BIT_CTRL_TFT(x) (((x) & BIT_MASK_TFT) << BIT_SHIFT_TFT)
#define BIT_GET_TFT(x) (((x) >> BIT_SHIFT_TFT) & BIT_MASK_TFT)
//2 REG_SPIC_RXFTLR
#define BIT_SHIFT_RFT 0
#define BIT_MASK_RFT 0x1f
#define BIT_RFT(x) (((x) & BIT_MASK_RFT) << BIT_SHIFT_RFT)
#define BIT_CTRL_RFT(x) (((x) & BIT_MASK_RFT) << BIT_SHIFT_RFT)
#define BIT_GET_RFT(x) (((x) >> BIT_SHIFT_RFT) & BIT_MASK_RFT)
//2 REG_SPIC_TXFLR
#define BIT_SHIFT_TXFL 0
#define BIT_MASK_TXFL 0x3f
#define BIT_TXFL(x) (((x) & BIT_MASK_TXFL) << BIT_SHIFT_TXFL)
#define BIT_CTRL_TXFL(x) (((x) & BIT_MASK_TXFL) << BIT_SHIFT_TXFL)
#define BIT_GET_TXFL(x) (((x) >> BIT_SHIFT_TXFL) & BIT_MASK_TXFL)
//2 REG_SPIC_RXFLR
#define BIT_SHIFT_RXFL 0
#define BIT_MASK_RXFL 0x3f
#define BIT_RXFL(x) (((x) & BIT_MASK_RXFL) << BIT_SHIFT_RXFL)
#define BIT_CTRL_RXFL(x) (((x) & BIT_MASK_RXFL) << BIT_SHIFT_RXFL)
#define BIT_GET_RXFL(x) (((x) >> BIT_SHIFT_RXFL) & BIT_MASK_RXFL)
//2 REG_SPIC_SR
#define BIT_TXE BIT(5)
#define BIT_SHIFT_TXE 5
#define BIT_MASK_TXE 0x1
#define BIT_CTRL_TXE(x) (((x) & BIT_MASK_TXE) << BIT_SHIFT_TXE)
#define BIT_RFF BIT(4)
#define BIT_SHIFT_RFF 4
#define BIT_MASK_RFF 0x1
#define BIT_CTRL_RFF(x) (((x) & BIT_MASK_RFF) << BIT_SHIFT_RFF)
#define BIT_RFNE BIT(3)
#define BIT_SHIFT_RFNE 3
#define BIT_MASK_RFNE 0x1
#define BIT_CTRL_RFNE(x) (((x) & BIT_MASK_RFNE) << BIT_SHIFT_RFNE)
#define BIT_TFE BIT(2)
#define BIT_SHIFT_TFE 2
#define BIT_MASK_TFE 0x1
#define BIT_CTRL_TFE(x) (((x) & BIT_MASK_TFE) << BIT_SHIFT_TFE)
#define BIT_TFNF BIT(1)
#define BIT_SHIFT_TFNF 1
#define BIT_MASK_TFNF 0x1
#define BIT_CTRL_TFNF(x) (((x) & BIT_MASK_TFNF) << BIT_SHIFT_TFNF)
#define BIT_BUSY BIT(0)
#define BIT_SHIFT_BUSY 0
#define BIT_MASK_BUSY 0x1
#define BIT_CTRL_BUSY(x) (((x) & BIT_MASK_BUSY) << BIT_SHIFT_BUSY)
//2 REG_SPIC_IMR
#define BIT_TXSIM BIT(9)
#define BIT_SHIFT_TXSIM 9
#define BIT_MASK_TXSIM 0x1
#define BIT_CTRL_TXSIM(x) (((x) & BIT_MASK_TXSIM) << BIT_SHIFT_TXSIM)
#define BIT_ACEIM BIT(8)
#define BIT_SHIFT_ACEIM 8
#define BIT_MASK_ACEIM 0x1
#define BIT_CTRL_ACEIM(x) (((x) & BIT_MASK_ACEIM) << BIT_SHIFT_ACEIM)
#define BIT_BYEIM BIT(7)
#define BIT_SHIFT_BYEIM 7
#define BIT_MASK_BYEIM 0x1
#define BIT_CTRL_BYEIM(x) (((x) & BIT_MASK_BYEIM) << BIT_SHIFT_BYEIM)
#define BIT_WBEIM BIT(6)
#define BIT_SHIFT_WBEIM 6
#define BIT_MASK_WBEIM 0x1
#define BIT_CTRL_WBEIM(x) (((x) & BIT_MASK_WBEIM) << BIT_SHIFT_WBEIM)
#define BIT_FSEIM BIT(5)
#define BIT_SHIFT_FSEIM 5
#define BIT_MASK_FSEIM 0x1
#define BIT_CTRL_FSEIM(x) (((x) & BIT_MASK_FSEIM) << BIT_SHIFT_FSEIM)
#define BIT_RXFIM BIT(4)
#define BIT_SHIFT_RXFIM 4
#define BIT_MASK_RXFIM 0x1
#define BIT_CTRL_RXFIM(x) (((x) & BIT_MASK_RXFIM) << BIT_SHIFT_RXFIM)
#define BIT_RXOIM BIT(3)
#define BIT_SHIFT_RXOIM 3
#define BIT_MASK_RXOIM 0x1
#define BIT_CTRL_RXOIM(x) (((x) & BIT_MASK_RXOIM) << BIT_SHIFT_RXOIM)
#define BIT_RXUIM BIT(2)
#define BIT_SHIFT_RXUIM 2
#define BIT_MASK_RXUIM 0x1
#define BIT_CTRL_RXUIM(x) (((x) & BIT_MASK_RXUIM) << BIT_SHIFT_RXUIM)
#define BIT_TXOIM BIT(1)
#define BIT_SHIFT_TXOIM 1
#define BIT_MASK_TXOIM 0x1
#define BIT_CTRL_TXOIM(x) (((x) & BIT_MASK_TXOIM) << BIT_SHIFT_TXOIM)
#define BIT_TXEIM BIT(0)
#define BIT_SHIFT_TXEIM 0
#define BIT_MASK_TXEIM 0x1
#define BIT_CTRL_TXEIM(x) (((x) & BIT_MASK_TXEIM) << BIT_SHIFT_TXEIM)
//2 REG_SPIC_ISR
#define BIT_TXSIS BIT(9)
#define BIT_SHIFT_TXSIS 9
#define BIT_MASK_TXSIS 0x1
#define BIT_CTRL_TXSIS(x) (((x) & BIT_MASK_TXSIS) << BIT_SHIFT_TXSIS)
#define BIT_ACEIS BIT(8)
#define BIT_SHIFT_ACEIS 8
#define BIT_MASK_ACEIS 0x1
#define BIT_CTRL_ACEIS(x) (((x) & BIT_MASK_ACEIS) << BIT_SHIFT_ACEIS)
#define BIT_BYEIS BIT(7)
#define BIT_SHIFT_BYEIS 7
#define BIT_MASK_BYEIS 0x1
#define BIT_CTRL_BYEIS(x) (((x) & BIT_MASK_BYEIS) << BIT_SHIFT_BYEIS)
#define BIT_WBEIS BIT(6)
#define BIT_SHIFT_WBEIS 6
#define BIT_MASK_WBEIS 0x1
#define BIT_CTRL_WBEIS(x) (((x) & BIT_MASK_WBEIS) << BIT_SHIFT_WBEIS)
#define BIT_FSEIS BIT(5)
#define BIT_SHIFT_FSEIS 5
#define BIT_MASK_FSEIS 0x1
#define BIT_CTRL_FSEIS(x) (((x) & BIT_MASK_FSEIS) << BIT_SHIFT_FSEIS)
#define BIT_RXFIS BIT(4)
#define BIT_SHIFT_RXFIS 4
#define BIT_MASK_RXFIS 0x1
#define BIT_CTRL_RXFIS(x) (((x) & BIT_MASK_RXFIS) << BIT_SHIFT_RXFIS)
#define BIT_RXOIS BIT(3)
#define BIT_SHIFT_RXOIS 3
#define BIT_MASK_RXOIS 0x1
#define BIT_CTRL_RXOIS(x) (((x) & BIT_MASK_RXOIS) << BIT_SHIFT_RXOIS)
#define BIT_RXUIS BIT(2)
#define BIT_SHIFT_RXUIS 2
#define BIT_MASK_RXUIS 0x1
#define BIT_CTRL_RXUIS(x) (((x) & BIT_MASK_RXUIS) << BIT_SHIFT_RXUIS)
#define BIT_TXOIS BIT(1)
#define BIT_SHIFT_TXOIS 1
#define BIT_MASK_TXOIS 0x1
#define BIT_CTRL_TXOIS(x) (((x) & BIT_MASK_TXOIS) << BIT_SHIFT_TXOIS)
#define BIT_TXEIS BIT(0)
#define BIT_SHIFT_TXEIS 0
#define BIT_MASK_TXEIS 0x1
#define BIT_CTRL_TXEIS(x) (((x) & BIT_MASK_TXEIS) << BIT_SHIFT_TXEIS)
//2 REG_SPIC_RISR
#define BIT_ACEIR BIT(8)
#define BIT_SHIFT_ACEIR 8
#define BIT_MASK_ACEIR 0x1
#define BIT_CTRL_ACEIR(x) (((x) & BIT_MASK_ACEIR) << BIT_SHIFT_ACEIR)
#define BIT_BYEIR BIT(7)
#define BIT_SHIFT_BYEIR 7
#define BIT_MASK_BYEIR 0x1
#define BIT_CTRL_BYEIR(x) (((x) & BIT_MASK_BYEIR) << BIT_SHIFT_BYEIR)
#define BIT_WBEIR BIT(6)
#define BIT_SHIFT_WBEIR 6
#define BIT_MASK_WBEIR 0x1
#define BIT_CTRL_WBEIR(x) (((x) & BIT_MASK_WBEIR) << BIT_SHIFT_WBEIR)
#define BIT_FSEIR BIT(5)
#define BIT_SHIFT_FSEIR 5
#define BIT_MASK_FSEIR 0x1
#define BIT_CTRL_FSEIR(x) (((x) & BIT_MASK_FSEIR) << BIT_SHIFT_FSEIR)
#define BIT_RXFIR BIT(4)
#define BIT_SHIFT_RXFIR 4
#define BIT_MASK_RXFIR 0x1
#define BIT_CTRL_RXFIR(x) (((x) & BIT_MASK_RXFIR) << BIT_SHIFT_RXFIR)
#define BIT_RXOIR BIT(3)
#define BIT_SHIFT_RXOIR 3
#define BIT_MASK_RXOIR 0x1
#define BIT_CTRL_RXOIR(x) (((x) & BIT_MASK_RXOIR) << BIT_SHIFT_RXOIR)
#define BIT_RXUIR BIT(2)
#define BIT_SHIFT_RXUIR 2
#define BIT_MASK_RXUIR 0x1
#define BIT_CTRL_RXUIR(x) (((x) & BIT_MASK_RXUIR) << BIT_SHIFT_RXUIR)
#define BIT_TXOIR BIT(1)
#define BIT_SHIFT_TXOIR 1
#define BIT_MASK_TXOIR 0x1
#define BIT_CTRL_TXOIR(x) (((x) & BIT_MASK_TXOIR) << BIT_SHIFT_TXOIR)
#define BIT_TXEIR BIT(0)
#define BIT_SHIFT_TXEIR 0
#define BIT_MASK_TXEIR 0x1
#define BIT_CTRL_TXEIR(x) (((x) & BIT_MASK_TXEIR) << BIT_SHIFT_TXEIR)
//2 REG_SPIC_TXOICR
#define BIT_TXOICR BIT(0)
#define BIT_SHIFT_TXOICR 0
#define BIT_MASK_TXOICR 0x1
#define BIT_CTRL_TXOICR(x) (((x) & BIT_MASK_TXOICR) << BIT_SHIFT_TXOICR)
//2 REG_SPIC_RXOICR
#define BIT_RXOCIR BIT(0)
#define BIT_SHIFT_RXOCIR 0
#define BIT_MASK_RXOCIR 0x1
#define BIT_CTRL_RXOCIR(x) (((x) & BIT_MASK_RXOCIR) << BIT_SHIFT_RXOCIR)
//2 REG_SPC_RXUICR
#define BIT_RXUICR BIT(0)
#define BIT_SHIFT_RXUICR 0
#define BIT_MASK_RXUICR 0x1
#define BIT_CTRL_RXUICR(x) (((x) & BIT_MASK_RXUICR) << BIT_SHIFT_RXUICR)
//2 REG_SPIC_MSTICR
#define BIT_MSTICR BIT(0)
#define BIT_SHIFT_MSTICR 0
#define BIT_MASK_MSTICR 0x1
#define BIT_CTRL_MSTICR(x) (((x) & BIT_MASK_MSTICR) << BIT_SHIFT_MSTICR)
//2 REG_SPIC_ICR
#define BIT_SHIFT_ICR 0
#define BIT_MASK_ICR 0xff
#define BIT_ICR(x) (((x) & BIT_MASK_ICR) << BIT_SHIFT_ICR)
#define BIT_CTRL_ICR(x) (((x) & BIT_MASK_ICR) << BIT_SHIFT_ICR)
#define BIT_GET_ICR(x) (((x) >> BIT_SHIFT_ICR) & BIT_MASK_ICR)
//2 REG_SPIC_DMACR
//2 REG_SPIC_DMATDLR0
//2 REG_SPIC_DMATDLR1
//2 REG_SPIC_IDR
#define BIT_SHIFT_IDCODE 0
#define BIT_MASK_IDCODE 0xffffffffL
#define BIT_IDCODE(x) (((x) & BIT_MASK_IDCODE) << BIT_SHIFT_IDCODE)
#define BIT_CTRL_IDCODE(x) (((x) & BIT_MASK_IDCODE) << BIT_SHIFT_IDCODE)
#define BIT_GET_IDCODE(x) (((x) >> BIT_SHIFT_IDCODE) & BIT_MASK_IDCODE)
//2 REG_SPIC_VERSION
#define BIT_SHIFT_SPIC_VERSION 0
#define BIT_MASK_SPIC_VERSION 0xffffffffL
#define BIT_SPIC_VERSION(x) (((x) & BIT_MASK_SPIC_VERSION) << BIT_SHIFT_SPIC_VERSION)
#define BIT_CTRL_SPIC_VERSION(x) (((x) & BIT_MASK_SPIC_VERSION) << BIT_SHIFT_SPIC_VERSION)
#define BIT_GET_SPIC_VERSION(x) (((x) >> BIT_SHIFT_SPIC_VERSION) & BIT_MASK_SPIC_VERSION)
//2 REG_SPIC_DR0
#define BIT_SHIFT_DR0 0
#define BIT_MASK_DR0 0xffffffffL
#define BIT_DR0(x) (((x) & BIT_MASK_DR0) << BIT_SHIFT_DR0)
#define BIT_CTRL_DR0(x) (((x) & BIT_MASK_DR0) << BIT_SHIFT_DR0)
#define BIT_GET_DR0(x) (((x) >> BIT_SHIFT_DR0) & BIT_MASK_DR0)
//2 REG_SPIC_DR1
#define BIT_SHIFT_DR1 0
#define BIT_MASK_DR1 0xffffffffL
#define BIT_DR1(x) (((x) & BIT_MASK_DR1) << BIT_SHIFT_DR1)
#define BIT_CTRL_DR1(x) (((x) & BIT_MASK_DR1) << BIT_SHIFT_DR1)
#define BIT_GET_DR1(x) (((x) >> BIT_SHIFT_DR1) & BIT_MASK_DR1)
//2 REG_SPIC_DR2
#define BIT_SHIFT_DR2 0
#define BIT_MASK_DR2 0xffffffffL
#define BIT_DR2(x) (((x) & BIT_MASK_DR2) << BIT_SHIFT_DR2)
#define BIT_CTRL_DR2(x) (((x) & BIT_MASK_DR2) << BIT_SHIFT_DR2)
#define BIT_GET_DR2(x) (((x) >> BIT_SHIFT_DR2) & BIT_MASK_DR2)
//2 REG_SPIC_DR3
#define BIT_SHIFT_DR3 0
#define BIT_MASK_DR3 0xffffffffL
#define BIT_DR3(x) (((x) & BIT_MASK_DR3) << BIT_SHIFT_DR3)
#define BIT_CTRL_DR3(x) (((x) & BIT_MASK_DR3) << BIT_SHIFT_DR3)
#define BIT_GET_DR3(x) (((x) >> BIT_SHIFT_DR3) & BIT_MASK_DR3)
//2 REG_SPIC_DR4
#define BIT_SHIFT_DR4 0
#define BIT_MASK_DR4 0xffffffffL
#define BIT_DR4(x) (((x) & BIT_MASK_DR4) << BIT_SHIFT_DR4)
#define BIT_CTRL_DR4(x) (((x) & BIT_MASK_DR4) << BIT_SHIFT_DR4)
#define BIT_GET_DR4(x) (((x) >> BIT_SHIFT_DR4) & BIT_MASK_DR4)
//2 REG_SPIC_DR5
#define BIT_SHIFT_DR5 0
#define BIT_MASK_DR5 0xffffffffL
#define BIT_DR5(x) (((x) & BIT_MASK_DR5) << BIT_SHIFT_DR5)
#define BIT_CTRL_DR5(x) (((x) & BIT_MASK_DR5) << BIT_SHIFT_DR5)
#define BIT_GET_DR5(x) (((x) >> BIT_SHIFT_DR5) & BIT_MASK_DR5)
//2 REG_SPIC_DR6
#define BIT_SHIFT_DR6 0
#define BIT_MASK_DR6 0xffffffffL
#define BIT_DR6(x) (((x) & BIT_MASK_DR6) << BIT_SHIFT_DR6)
#define BIT_CTRL_DR6(x) (((x) & BIT_MASK_DR6) << BIT_SHIFT_DR6)
#define BIT_GET_DR6(x) (((x) >> BIT_SHIFT_DR6) & BIT_MASK_DR6)
//2 REG_SPIC_DR7
#define BIT_SHIFT_DR7 0
#define BIT_MASK_DR7 0xffffffffL
#define BIT_DR7(x) (((x) & BIT_MASK_DR7) << BIT_SHIFT_DR7)
#define BIT_CTRL_DR7(x) (((x) & BIT_MASK_DR7) << BIT_SHIFT_DR7)
#define BIT_GET_DR7(x) (((x) >> BIT_SHIFT_DR7) & BIT_MASK_DR7)
//2 REG_SPIC_DR8
#define BIT_SHIFT_DR8 0
#define BIT_MASK_DR8 0xffffffffL
#define BIT_DR8(x) (((x) & BIT_MASK_DR8) << BIT_SHIFT_DR8)
#define BIT_CTRL_DR8(x) (((x) & BIT_MASK_DR8) << BIT_SHIFT_DR8)
#define BIT_GET_DR8(x) (((x) >> BIT_SHIFT_DR8) & BIT_MASK_DR8)
//2 REG_SPIC_DR9
#define BIT_SHIFT_DR9 0
#define BIT_MASK_DR9 0xffffffffL
#define BIT_DR9(x) (((x) & BIT_MASK_DR9) << BIT_SHIFT_DR9)
#define BIT_CTRL_DR9(x) (((x) & BIT_MASK_DR9) << BIT_SHIFT_DR9)
#define BIT_GET_DR9(x) (((x) >> BIT_SHIFT_DR9) & BIT_MASK_DR9)
//2 REG_SPIC_DR10
#define BIT_SHIFT_DR10 0
#define BIT_MASK_DR10 0xffffffffL
#define BIT_DR10(x) (((x) & BIT_MASK_DR10) << BIT_SHIFT_DR10)
#define BIT_CTRL_DR10(x) (((x) & BIT_MASK_DR10) << BIT_SHIFT_DR10)
#define BIT_GET_DR10(x) (((x) >> BIT_SHIFT_DR10) & BIT_MASK_DR10)
//2 REG_SPIC_DR11
#define BIT_SHIFT_DR11 0
#define BIT_MASK_DR11 0xffffffffL
#define BIT_DR11(x) (((x) & BIT_MASK_DR11) << BIT_SHIFT_DR11)
#define BIT_CTRL_DR11(x) (((x) & BIT_MASK_DR11) << BIT_SHIFT_DR11)
#define BIT_GET_DR11(x) (((x) >> BIT_SHIFT_DR11) & BIT_MASK_DR11)
//2 REG_SPIC_DR12
#define BIT_SHIFT_DR12 0
#define BIT_MASK_DR12 0xffffffffL
#define BIT_DR12(x) (((x) & BIT_MASK_DR12) << BIT_SHIFT_DR12)
#define BIT_CTRL_DR12(x) (((x) & BIT_MASK_DR12) << BIT_SHIFT_DR12)
#define BIT_GET_DR12(x) (((x) >> BIT_SHIFT_DR12) & BIT_MASK_DR12)
//2 REG_SPIC_DR13
#define BIT_SHIFT_DR13 0
#define BIT_MASK_DR13 0xffffffffL
#define BIT_DR13(x) (((x) & BIT_MASK_DR13) << BIT_SHIFT_DR13)
#define BIT_CTRL_DR13(x) (((x) & BIT_MASK_DR13) << BIT_SHIFT_DR13)
#define BIT_GET_DR13(x) (((x) >> BIT_SHIFT_DR13) & BIT_MASK_DR13)
//2 REG_SPIC_DR14
#define BIT_SHIFT_DR14 0
#define BIT_MASK_DR14 0xffffffffL
#define BIT_DR14(x) (((x) & BIT_MASK_DR14) << BIT_SHIFT_DR14)
#define BIT_CTRL_DR14(x) (((x) & BIT_MASK_DR14) << BIT_SHIFT_DR14)
#define BIT_GET_DR14(x) (((x) >> BIT_SHIFT_DR14) & BIT_MASK_DR14)
//2 REG_SPIC_DR15
#define BIT_SHIFT_DR15 0
#define BIT_MASK_DR15 0xffffffffL
#define BIT_DR15(x) (((x) & BIT_MASK_DR15) << BIT_SHIFT_DR15)
#define BIT_CTRL_DR15(x) (((x) & BIT_MASK_DR15) << BIT_SHIFT_DR15)
#define BIT_GET_DR15(x) (((x) >> BIT_SHIFT_DR15) & BIT_MASK_DR15)
//2 REG_SPIC_DR16
#define BIT_SHIFT_DR16 0
#define BIT_MASK_DR16 0xffffffffL
#define BIT_DR16(x) (((x) & BIT_MASK_DR16) << BIT_SHIFT_DR16)
#define BIT_CTRL_DR16(x) (((x) & BIT_MASK_DR16) << BIT_SHIFT_DR16)
#define BIT_GET_DR16(x) (((x) >> BIT_SHIFT_DR16) & BIT_MASK_DR16)
//2 REG_SPIC_DR17
#define BIT_SHIFT_DR17 0
#define BIT_MASK_DR17 0xffffffffL
#define BIT_DR17(x) (((x) & BIT_MASK_DR17) << BIT_SHIFT_DR17)
#define BIT_CTRL_DR17(x) (((x) & BIT_MASK_DR17) << BIT_SHIFT_DR17)
#define BIT_GET_DR17(x) (((x) >> BIT_SHIFT_DR17) & BIT_MASK_DR17)
//2 REG_SPIC_DR18
#define BIT_SHIFT_DR18 0
#define BIT_MASK_DR18 0xffffffffL
#define BIT_DR18(x) (((x) & BIT_MASK_DR18) << BIT_SHIFT_DR18)
#define BIT_CTRL_DR18(x) (((x) & BIT_MASK_DR18) << BIT_SHIFT_DR18)
#define BIT_GET_DR18(x) (((x) >> BIT_SHIFT_DR18) & BIT_MASK_DR18)
//2 REG_SPIC_DR19
#define BIT_SHIFT_DR19 0
#define BIT_MASK_DR19 0xffffffffL
#define BIT_DR19(x) (((x) & BIT_MASK_DR19) << BIT_SHIFT_DR19)
#define BIT_CTRL_DR19(x) (((x) & BIT_MASK_DR19) << BIT_SHIFT_DR19)
#define BIT_GET_DR19(x) (((x) >> BIT_SHIFT_DR19) & BIT_MASK_DR19)
//2 REG_SPIC_DR20
#define BIT_SHIFT_DR20 0
#define BIT_MASK_DR20 0xffffffffL
#define BIT_DR20(x) (((x) & BIT_MASK_DR20) << BIT_SHIFT_DR20)
#define BIT_CTRL_DR20(x) (((x) & BIT_MASK_DR20) << BIT_SHIFT_DR20)
#define BIT_GET_DR20(x) (((x) >> BIT_SHIFT_DR20) & BIT_MASK_DR20)
//2 REG_SPIC_DR21
#define BIT_SHIFT_DR21 0
#define BIT_MASK_DR21 0xffffffffL
#define BIT_DR21(x) (((x) & BIT_MASK_DR21) << BIT_SHIFT_DR21)
#define BIT_CTRL_DR21(x) (((x) & BIT_MASK_DR21) << BIT_SHIFT_DR21)
#define BIT_GET_DR21(x) (((x) >> BIT_SHIFT_DR21) & BIT_MASK_DR21)
//2 REG_SPIC_DR22
#define BIT_SHIFT_DR22 0
#define BIT_MASK_DR22 0xffffffffL
#define BIT_DR22(x) (((x) & BIT_MASK_DR22) << BIT_SHIFT_DR22)
#define BIT_CTRL_DR22(x) (((x) & BIT_MASK_DR22) << BIT_SHIFT_DR22)
#define BIT_GET_DR22(x) (((x) >> BIT_SHIFT_DR22) & BIT_MASK_DR22)
//2 REG_SPIC_DR23
#define BIT_SHIFT_DR23 0
#define BIT_MASK_DR23 0xffffffffL
#define BIT_DR23(x) (((x) & BIT_MASK_DR23) << BIT_SHIFT_DR23)
#define BIT_CTRL_DR23(x) (((x) & BIT_MASK_DR23) << BIT_SHIFT_DR23)
#define BIT_GET_DR23(x) (((x) >> BIT_SHIFT_DR23) & BIT_MASK_DR23)
//2 REG_SPIC_DR24
#define BIT_SHIFT_DR24 0
#define BIT_MASK_DR24 0xffffffffL
#define BIT_DR24(x) (((x) & BIT_MASK_DR24) << BIT_SHIFT_DR24)
#define BIT_CTRL_DR24(x) (((x) & BIT_MASK_DR24) << BIT_SHIFT_DR24)
#define BIT_GET_DR24(x) (((x) >> BIT_SHIFT_DR24) & BIT_MASK_DR24)
//2 REG_SPIC_DR25
#define BIT_SHIFT_DR25 0
#define BIT_MASK_DR25 0xffffffffL
#define BIT_DR25(x) (((x) & BIT_MASK_DR25) << BIT_SHIFT_DR25)
#define BIT_CTRL_DR25(x) (((x) & BIT_MASK_DR25) << BIT_SHIFT_DR25)
#define BIT_GET_DR25(x) (((x) >> BIT_SHIFT_DR25) & BIT_MASK_DR25)
//2 REG_SPIC_DR26
#define BIT_SHIFT_DR26 0
#define BIT_MASK_DR26 0xffffffffL
#define BIT_DR26(x) (((x) & BIT_MASK_DR26) << BIT_SHIFT_DR26)
#define BIT_CTRL_DR26(x) (((x) & BIT_MASK_DR26) << BIT_SHIFT_DR26)
#define BIT_GET_DR26(x) (((x) >> BIT_SHIFT_DR26) & BIT_MASK_DR26)
//2 REG_SPIC_DR27
#define BIT_SHIFT_DR27 0
#define BIT_MASK_DR27 0xffffffffL
#define BIT_DR27(x) (((x) & BIT_MASK_DR27) << BIT_SHIFT_DR27)
#define BIT_CTRL_DR27(x) (((x) & BIT_MASK_DR27) << BIT_SHIFT_DR27)
#define BIT_GET_DR27(x) (((x) >> BIT_SHIFT_DR27) & BIT_MASK_DR27)
//2 REG_SPIC_DR28
#define BIT_SHIFT_DR28 0
#define BIT_MASK_DR28 0xffffffffL
#define BIT_DR28(x) (((x) & BIT_MASK_DR28) << BIT_SHIFT_DR28)
#define BIT_CTRL_DR28(x) (((x) & BIT_MASK_DR28) << BIT_SHIFT_DR28)
#define BIT_GET_DR28(x) (((x) >> BIT_SHIFT_DR28) & BIT_MASK_DR28)
//2 REG_SPIC_DR29
#define BIT_SHIFT_DR29 0
#define BIT_MASK_DR29 0xffffffffL
#define BIT_DR29(x) (((x) & BIT_MASK_DR29) << BIT_SHIFT_DR29)
#define BIT_CTRL_DR29(x) (((x) & BIT_MASK_DR29) << BIT_SHIFT_DR29)
#define BIT_GET_DR29(x) (((x) >> BIT_SHIFT_DR29) & BIT_MASK_DR29)
//2 REG_SPIC_DR30
#define BIT_SHIFT_DR30 0
#define BIT_MASK_DR30 0xffffffffL
#define BIT_DR30(x) (((x) & BIT_MASK_DR30) << BIT_SHIFT_DR30)
#define BIT_CTRL_DR30(x) (((x) & BIT_MASK_DR30) << BIT_SHIFT_DR30)
#define BIT_GET_DR30(x) (((x) >> BIT_SHIFT_DR30) & BIT_MASK_DR30)
//2 REG_SPIC_DR31
#define BIT_SHIFT_DR31 0
#define BIT_MASK_DR31 0xffffffffL
#define BIT_DR31(x) (((x) & BIT_MASK_DR31) << BIT_SHIFT_DR31)
#define BIT_CTRL_DR31(x) (((x) & BIT_MASK_DR31) << BIT_SHIFT_DR31)
#define BIT_GET_DR31(x) (((x) >> BIT_SHIFT_DR31) & BIT_MASK_DR31)
//2 REG_SPIC_READ_FAST_SINGLE
#define BIT_SHIFT_FRD_CMD 0
#define BIT_MASK_FRD_CMD 0xff
#define BIT_FRD_CMD(x) (((x) & BIT_MASK_FRD_CMD) << BIT_SHIFT_FRD_CMD)
#define BIT_CTRL_FRD_CMD(x) (((x) & BIT_MASK_FRD_CMD) << BIT_SHIFT_FRD_CMD)
#define BIT_GET_FRD_CMD(x) (((x) >> BIT_SHIFT_FRD_CMD) & BIT_MASK_FRD_CMD)
//2 REG_SPIC_READ_DUAL_DATA
#define BIT_SHIFT_RD_DUAL_O_CMD 0
#define BIT_MASK_RD_DUAL_O_CMD 0xff
#define BIT_RD_DUAL_O_CMD(x) (((x) & BIT_MASK_RD_DUAL_O_CMD) << BIT_SHIFT_RD_DUAL_O_CMD)
#define BIT_CTRL_RD_DUAL_O_CMD(x) (((x) & BIT_MASK_RD_DUAL_O_CMD) << BIT_SHIFT_RD_DUAL_O_CMD)
#define BIT_GET_RD_DUAL_O_CMD(x) (((x) >> BIT_SHIFT_RD_DUAL_O_CMD) & BIT_MASK_RD_DUAL_O_CMD)
//2 REG_SPIC_READ_DUAL_ADDR_DATA
#define BIT_SHIFT_RD_DUAL_IO_CMD 0
#define BIT_MASK_RD_DUAL_IO_CMD 0xff
#define BIT_RD_DUAL_IO_CMD(x) (((x) & BIT_MASK_RD_DUAL_IO_CMD) << BIT_SHIFT_RD_DUAL_IO_CMD)
#define BIT_CTRL_RD_DUAL_IO_CMD(x) (((x) & BIT_MASK_RD_DUAL_IO_CMD) << BIT_SHIFT_RD_DUAL_IO_CMD)
#define BIT_GET_RD_DUAL_IO_CMD(x) (((x) >> BIT_SHIFT_RD_DUAL_IO_CMD) & BIT_MASK_RD_DUAL_IO_CMD)
//2 REG_SPIC_READ_QUAD_DATA
#define BIT_SHIFT_RD_QUAD_O_CMD 0
#define BIT_MASK_RD_QUAD_O_CMD 0xff
#define BIT_RD_QUAD_O_CMD(x) (((x) & BIT_MASK_RD_QUAD_O_CMD) << BIT_SHIFT_RD_QUAD_O_CMD)
#define BIT_CTRL_RD_QUAD_O_CMD(x) (((x) & BIT_MASK_RD_QUAD_O_CMD) << BIT_SHIFT_RD_QUAD_O_CMD)
#define BIT_GET_RD_QUAD_O_CMD(x) (((x) >> BIT_SHIFT_RD_QUAD_O_CMD) & BIT_MASK_RD_QUAD_O_CMD)
//2 REG_SPIC_READ_QUAD_ADDR_DATA
#define BIT_SHIFT_RD_QUAD_IO_CMD 0
#define BIT_MASK_RD_QUAD_IO_CMD 0xff
#define BIT_RD_QUAD_IO_CMD(x) (((x) & BIT_MASK_RD_QUAD_IO_CMD) << BIT_SHIFT_RD_QUAD_IO_CMD)
#define BIT_CTRL_RD_QUAD_IO_CMD(x) (((x) & BIT_MASK_RD_QUAD_IO_CMD) << BIT_SHIFT_RD_QUAD_IO_CMD)
#define BIT_GET_RD_QUAD_IO_CMD(x) (((x) >> BIT_SHIFT_RD_QUAD_IO_CMD) & BIT_MASK_RD_QUAD_IO_CMD)
//2 REG_SPIC_WRITE_SIGNLE
#define BIT_SHIFT_WR_CMD 0
#define BIT_MASK_WR_CMD 0xff
#define BIT_WR_CMD(x) (((x) & BIT_MASK_WR_CMD) << BIT_SHIFT_WR_CMD)
#define BIT_CTRL_WR_CMD(x) (((x) & BIT_MASK_WR_CMD) << BIT_SHIFT_WR_CMD)
#define BIT_GET_WR_CMD(x) (((x) >> BIT_SHIFT_WR_CMD) & BIT_MASK_WR_CMD)
//2 REG_SPIC_WRITE_DUAL_DATA
#define BIT_SHIFT_WR_DUAL_I_CMD 0
#define BIT_MASK_WR_DUAL_I_CMD 0xff
#define BIT_WR_DUAL_I_CMD(x) (((x) & BIT_MASK_WR_DUAL_I_CMD) << BIT_SHIFT_WR_DUAL_I_CMD)
#define BIT_CTRL_WR_DUAL_I_CMD(x) (((x) & BIT_MASK_WR_DUAL_I_CMD) << BIT_SHIFT_WR_DUAL_I_CMD)
#define BIT_GET_WR_DUAL_I_CMD(x) (((x) >> BIT_SHIFT_WR_DUAL_I_CMD) & BIT_MASK_WR_DUAL_I_CMD)
//2 REG_SPIC_WRITE_DUAL_ADDR_DATA
#define BIT_SHIFT_WR_DUAL_II_CMD 0
#define BIT_MASK_WR_DUAL_II_CMD 0xff
#define BIT_WR_DUAL_II_CMD(x) (((x) & BIT_MASK_WR_DUAL_II_CMD) << BIT_SHIFT_WR_DUAL_II_CMD)
#define BIT_CTRL_WR_DUAL_II_CMD(x) (((x) & BIT_MASK_WR_DUAL_II_CMD) << BIT_SHIFT_WR_DUAL_II_CMD)
#define BIT_GET_WR_DUAL_II_CMD(x) (((x) >> BIT_SHIFT_WR_DUAL_II_CMD) & BIT_MASK_WR_DUAL_II_CMD)
//2 REG_SPIC_WRITE_QUAD_DATA
#define BIT_SHIFT_WR_QUAD_I_CMD 0
#define BIT_MASK_WR_QUAD_I_CMD 0xff
#define BIT_WR_QUAD_I_CMD(x) (((x) & BIT_MASK_WR_QUAD_I_CMD) << BIT_SHIFT_WR_QUAD_I_CMD)
#define BIT_CTRL_WR_QUAD_I_CMD(x) (((x) & BIT_MASK_WR_QUAD_I_CMD) << BIT_SHIFT_WR_QUAD_I_CMD)
#define BIT_GET_WR_QUAD_I_CMD(x) (((x) >> BIT_SHIFT_WR_QUAD_I_CMD) & BIT_MASK_WR_QUAD_I_CMD)
//2 REG_SPIC_WRITE_QUAD_ADDR_DATA
#define BIT_SHIFT_WR_QUAD_II_CMD 0
#define BIT_MASK_WR_QUAD_II_CMD 0xff
#define BIT_WR_QUAD_II_CMD(x) (((x) & BIT_MASK_WR_QUAD_II_CMD) << BIT_SHIFT_WR_QUAD_II_CMD)
#define BIT_CTRL_WR_QUAD_II_CMD(x) (((x) & BIT_MASK_WR_QUAD_II_CMD) << BIT_SHIFT_WR_QUAD_II_CMD)
#define BIT_GET_WR_QUAD_II_CMD(x) (((x) >> BIT_SHIFT_WR_QUAD_II_CMD) & BIT_MASK_WR_QUAD_II_CMD)
//2 REG_SPIC_WRITE_ENABLE
#define BIT_SHIFT_WR_EN_CMD 0
#define BIT_MASK_WR_EN_CMD 0xff
#define BIT_WR_EN_CMD(x) (((x) & BIT_MASK_WR_EN_CMD) << BIT_SHIFT_WR_EN_CMD)
#define BIT_CTRL_WR_EN_CMD(x) (((x) & BIT_MASK_WR_EN_CMD) << BIT_SHIFT_WR_EN_CMD)
#define BIT_GET_WR_EN_CMD(x) (((x) >> BIT_SHIFT_WR_EN_CMD) & BIT_MASK_WR_EN_CMD)
//2 REG_SPIC_READ_STATUS
#define BIT_SHIFT_RD_ST_CMD 0
#define BIT_MASK_RD_ST_CMD 0xff
#define BIT_RD_ST_CMD(x) (((x) & BIT_MASK_RD_ST_CMD) << BIT_SHIFT_RD_ST_CMD)
#define BIT_CTRL_RD_ST_CMD(x) (((x) & BIT_MASK_RD_ST_CMD) << BIT_SHIFT_RD_ST_CMD)
#define BIT_GET_RD_ST_CMD(x) (((x) >> BIT_SHIFT_RD_ST_CMD) & BIT_MASK_RD_ST_CMD)
//2 REG_SPIC_CTRLR2
#define BIT_SHIFT_FIFO_ENTRY 4
#define BIT_MASK_FIFO_ENTRY 0xf
#define BIT_FIFO_ENTRY(x) (((x) & BIT_MASK_FIFO_ENTRY) << BIT_SHIFT_FIFO_ENTRY)
#define BIT_CTRL_FIFO_ENTRY(x) (((x) & BIT_MASK_FIFO_ENTRY) << BIT_SHIFT_FIFO_ENTRY)
#define BIT_GET_FIFO_ENTRY(x) (((x) >> BIT_SHIFT_FIFO_ENTRY) & BIT_MASK_FIFO_ENTRY)
#define BIT_WR_SEQ BIT(3)
#define BIT_SHIFT_WR_SEQ 3
#define BIT_MASK_WR_SEQ 0x1
#define BIT_CTRL_WR_SEQ(x) (((x) & BIT_MASK_WR_SEQ) << BIT_SHIFT_WR_SEQ)
#define BIT_WPN_DNUM BIT(2)
#define BIT_SHIFT_WPN_DNUM 2
#define BIT_MASK_WPN_DNUM 0x1
#define BIT_CTRL_WPN_DNUM(x) (((x) & BIT_MASK_WPN_DNUM) << BIT_SHIFT_WPN_DNUM)
#define BIT_WPN_SET BIT(1)
#define BIT_SHIFT_WPN_SET 1
#define BIT_MASK_WPN_SET 0x1
#define BIT_CTRL_WPN_SET(x) (((x) & BIT_MASK_WPN_SET) << BIT_SHIFT_WPN_SET)
#define BIT_SO_DUM BIT(0)
#define BIT_SHIFT_SO_DUM 0
#define BIT_MASK_SO_DUM 0x1
#define BIT_CTRL_SO_DUM(x) (((x) & BIT_MASK_SO_DUM) << BIT_SHIFT_SO_DUM)
//2 REG_SPIC_FBAUDR
#define BIT_SHIFT_FSCKDV 0
#define BIT_MASK_FSCKDV 0xfff
#define BIT_FSCKDV(x) (((x) & BIT_MASK_FSCKDV) << BIT_SHIFT_FSCKDV)
#define BIT_CTRL_FSCKDV(x) (((x) & BIT_MASK_FSCKDV) << BIT_SHIFT_FSCKDV)
#define BIT_GET_FSCKDV(x) (((x) >> BIT_SHIFT_FSCKDV) & BIT_MASK_FSCKDV)
//2 REG_SPIC_ADDR_LENGTH
#define BIT_SHIFT_ADDR_PHASE_LENGTH 0
#define BIT_MASK_ADDR_PHASE_LENGTH 0x3
#define BIT_ADDR_PHASE_LENGTH(x) (((x) & BIT_MASK_ADDR_PHASE_LENGTH) << BIT_SHIFT_ADDR_PHASE_LENGTH)
#define BIT_CTRL_ADDR_PHASE_LENGTH(x) (((x) & BIT_MASK_ADDR_PHASE_LENGTH) << BIT_SHIFT_ADDR_PHASE_LENGTH)
#define BIT_GET_ADDR_PHASE_LENGTH(x) (((x) >> BIT_SHIFT_ADDR_PHASE_LENGTH) & BIT_MASK_ADDR_PHASE_LENGTH)
//2 REG_SPIC_AUTO_LENGTH
#define BIT_SHIFT_CS_H_WR_DUM_LEN 28
#define BIT_MASK_CS_H_WR_DUM_LEN 0xf
#define BIT_CS_H_WR_DUM_LEN(x) (((x) & BIT_MASK_CS_H_WR_DUM_LEN) << BIT_SHIFT_CS_H_WR_DUM_LEN)
#define BIT_CTRL_CS_H_WR_DUM_LEN(x) (((x) & BIT_MASK_CS_H_WR_DUM_LEN) << BIT_SHIFT_CS_H_WR_DUM_LEN)
#define BIT_GET_CS_H_WR_DUM_LEN(x) (((x) >> BIT_SHIFT_CS_H_WR_DUM_LEN) & BIT_MASK_CS_H_WR_DUM_LEN)
#define BIT_SHIFT_CS_H_RD_DUM_LEN 26
#define BIT_MASK_CS_H_RD_DUM_LEN 0x3
#define BIT_CS_H_RD_DUM_LEN(x) (((x) & BIT_MASK_CS_H_RD_DUM_LEN) << BIT_SHIFT_CS_H_RD_DUM_LEN)
#define BIT_CTRL_CS_H_RD_DUM_LEN(x) (((x) & BIT_MASK_CS_H_RD_DUM_LEN) << BIT_SHIFT_CS_H_RD_DUM_LEN)
#define BIT_GET_CS_H_RD_DUM_LEN(x) (((x) >> BIT_SHIFT_CS_H_RD_DUM_LEN) & BIT_MASK_CS_H_RD_DUM_LEN)
#define BIT_SHIFT_AUTO_DUM_LEN 18
#define BIT_MASK_AUTO_DUM_LEN 0xff
#define BIT_AUTO_DUM_LEN(x) (((x) & BIT_MASK_AUTO_DUM_LEN) << BIT_SHIFT_AUTO_DUM_LEN)
#define BIT_CTRL_AUTO_DUM_LEN(x) (((x) & BIT_MASK_AUTO_DUM_LEN) << BIT_SHIFT_AUTO_DUM_LEN)
#define BIT_GET_AUTO_DUM_LEN(x) (((x) >> BIT_SHIFT_AUTO_DUM_LEN) & BIT_MASK_AUTO_DUM_LEN)
#define BIT_SHIFT_AUTO_ADDR__LENGTH 16
#define BIT_MASK_AUTO_ADDR__LENGTH 0x3
#define BIT_AUTO_ADDR__LENGTH(x) (((x) & BIT_MASK_AUTO_ADDR__LENGTH) << BIT_SHIFT_AUTO_ADDR__LENGTH)
#define BIT_CTRL_AUTO_ADDR__LENGTH(x) (((x) & BIT_MASK_AUTO_ADDR__LENGTH) << BIT_SHIFT_AUTO_ADDR__LENGTH)
#define BIT_GET_AUTO_ADDR__LENGTH(x) (((x) >> BIT_SHIFT_AUTO_ADDR__LENGTH) & BIT_MASK_AUTO_ADDR__LENGTH)
#define BIT_SHIFT_RD_DUMMY_LENGTH 0
#define BIT_MASK_RD_DUMMY_LENGTH 0xffff
#define BIT_RD_DUMMY_LENGTH(x) (((x) & BIT_MASK_RD_DUMMY_LENGTH) << BIT_SHIFT_RD_DUMMY_LENGTH)
#define BIT_CTRL_RD_DUMMY_LENGTH(x) (((x) & BIT_MASK_RD_DUMMY_LENGTH) << BIT_SHIFT_RD_DUMMY_LENGTH)
#define BIT_GET_RD_DUMMY_LENGTH(x) (((x) >> BIT_SHIFT_RD_DUMMY_LENGTH) & BIT_MASK_RD_DUMMY_LENGTH)
//2 REG_SPIC_VALID_CMD
#define BIT_WR_BLOCKING BIT(9)
#define BIT_SHIFT_WR_BLOCKING 9
#define BIT_MASK_WR_BLOCKING 0x1
#define BIT_CTRL_WR_BLOCKING(x) (((x) & BIT_MASK_WR_BLOCKING) << BIT_SHIFT_WR_BLOCKING)
#define BIT_WR_QUAD_II BIT(8)
#define BIT_SHIFT_WR_QUAD_II 8
#define BIT_MASK_WR_QUAD_II 0x1
#define BIT_CTRL_WR_QUAD_II(x) (((x) & BIT_MASK_WR_QUAD_II) << BIT_SHIFT_WR_QUAD_II)
#define BIT_WR_QUAD_I BIT(7)
#define BIT_SHIFT_WR_QUAD_I 7
#define BIT_MASK_WR_QUAD_I 0x1
#define BIT_CTRL_WR_QUAD_I(x) (((x) & BIT_MASK_WR_QUAD_I) << BIT_SHIFT_WR_QUAD_I)
#define BIT_WR_DUAL_II BIT(6)
#define BIT_SHIFT_WR_DUAL_II 6
#define BIT_MASK_WR_DUAL_II 0x1
#define BIT_CTRL_WR_DUAL_II(x) (((x) & BIT_MASK_WR_DUAL_II) << BIT_SHIFT_WR_DUAL_II)
#define BIT_WR_DUAL_I BIT(5)
#define BIT_SHIFT_WR_DUAL_I 5
#define BIT_MASK_WR_DUAL_I 0x1
#define BIT_CTRL_WR_DUAL_I(x) (((x) & BIT_MASK_WR_DUAL_I) << BIT_SHIFT_WR_DUAL_I)
#define BIT_RD_QUAD_IO BIT(4)
#define BIT_SHIFT_RD_QUAD_IO 4
#define BIT_MASK_RD_QUAD_IO 0x1
#define BIT_CTRL_RD_QUAD_IO(x) (((x) & BIT_MASK_RD_QUAD_IO) << BIT_SHIFT_RD_QUAD_IO)
#define BIT_RD_QUAD_O BIT(3)
#define BIT_SHIFT_RD_QUAD_O 3
#define BIT_MASK_RD_QUAD_O 0x1
#define BIT_CTRL_RD_QUAD_O(x) (((x) & BIT_MASK_RD_QUAD_O) << BIT_SHIFT_RD_QUAD_O)
#define BIT_RD_DUAL_IO BIT(2)
#define BIT_SHIFT_RD_DUAL_IO 2
#define BIT_MASK_RD_DUAL_IO 0x1
#define BIT_CTRL_RD_DUAL_IO(x) (((x) & BIT_MASK_RD_DUAL_IO) << BIT_SHIFT_RD_DUAL_IO)
#define BIT_RD_DUAL_I BIT(1)
#define BIT_SHIFT_RD_DUAL_I 1
#define BIT_MASK_RD_DUAL_I 0x1
#define BIT_CTRL_RD_DUAL_I(x) (((x) & BIT_MASK_RD_DUAL_I) << BIT_SHIFT_RD_DUAL_I)
#define BIT_FRD_SINGEL BIT(0)
#define BIT_SHIFT_FRD_SINGEL 0
#define BIT_MASK_FRD_SINGEL 0x1
#define BIT_CTRL_FRD_SINGEL(x) (((x) & BIT_MASK_FRD_SINGEL) << BIT_SHIFT_FRD_SINGEL)
//2 REG_SPIC_FLASE_SIZE
#define BIT_SHIFT_FLASE_SIZE 0
#define BIT_MASK_FLASE_SIZE 0xf
#define BIT_FLASE_SIZE(x) (((x) & BIT_MASK_FLASE_SIZE) << BIT_SHIFT_FLASE_SIZE)
#define BIT_CTRL_FLASE_SIZE(x) (((x) & BIT_MASK_FLASE_SIZE) << BIT_SHIFT_FLASE_SIZE)
#define BIT_GET_FLASE_SIZE(x) (((x) >> BIT_SHIFT_FLASE_SIZE) & BIT_MASK_FLASE_SIZE)
//2 REG_SPIC_FLUSH_FIFO
#define BIT_FLUSH_FIFO BIT(0)
#define BIT_SHIFT_FLUSH_FIFO 0
#define BIT_MASK_FLUSH_FIFO 0x1
#define BIT_CTRL_FLUSH_FIFO(x) (((x) & BIT_MASK_FLUSH_FIFO) << BIT_SHIFT_FLUSH_FIFO)
//=================== Register Address Definition ============================//
#define REG_SPIC_CTRLR0 0x0000//O
#define REG_SPIC_CTRLR1 0x0004//O
#define REG_SPIC_SSIENR 0x0008//O
#define REG_SPIC_MWCR 0x000C
#define REG_SPIC_SER 0x0010//O
#define REG_SPIC_BAUDR 0x0014//O
#define REG_SPIC_TXFTLR 0x0018
#define REG_SPIC_RXFTLR 0x001C//O
#define REG_SPIC_TXFLR 0x0020//O
#define REG_SPIC_RXFLR 0x0024
#define REG_SPIC_SR 0x0028
#define REG_SPIC_IMR 0x002C//O
#define REG_SPIC_ISR 0x0030
#define REG_SPIC_RISR 0x0034
#define REG_SPIC_TXOICR 0x0038
#define REG_SPIC_RXOICR 0x003C
#define REG_SPC_RXUICR 0x0040
#define REG_SPIC_MSTICR 0x0044
#define REG_SPIC_ICR 0x0048
#define REG_SPIC_DMACR 0x004C
#define REG_SPIC_DMATDLR0 0x0050
#define REG_SPIC_DMATDLR1 0x0054
#define REG_SPIC_IDR 0x0058
#define REG_SPIC_VERSION 0x005C
#define REG_SPIC_DR0 0x0060
#define REG_SPIC_DR1 0x0064
#define REG_SPIC_DR2 0x0068
#define REG_SPIC_DR3 0x006C
#define REG_SPIC_DR4 0x0070
#define REG_SPIC_DR5 0x0074
#define REG_SPIC_DR6 0x0078
#define REG_SPIC_DR7 0x007C
#define REG_SPIC_DR8 0x0080
#define REG_SPIC_DR9 0x0084
#define REG_SPIC_DR10 0x0088
#define REG_SPIC_DR11 0x008C
#define REG_SPIC_DR12 0x0090
#define REG_SPIC_DR13 0x0094
#define REG_SPIC_DR14 0x0098
#define REG_SPIC_DR15 0x009C
#define REG_SPIC_DR16 0x00A0
#define REG_SPIC_DR17 0x00A4
#define REG_SPIC_DR18 0x00A8
#define REG_SPIC_DR19 0x00AC
#define REG_SPIC_DR20 0x00B0
#define REG_SPIC_DR21 0x00B4
#define REG_SPIC_DR22 0x00B8
#define REG_SPIC_DR23 0x00BC
#define REG_SPIC_DR24 0x00C0
#define REG_SPIC_DR25 0x00C4
#define REG_SPIC_DR26 0x00C8
#define REG_SPIC_DR27 0x00CC
#define REG_SPIC_DR28 0x00D0
#define REG_SPIC_DR29 0x00D4
#define REG_SPIC_DR30 0x00D8
#define REG_SPIC_DR31 0x00DC
#define REG_SPIC_READ_FAST_SINGLE 0x00E0//O
#define REG_SPIC_READ_DUAL_DATA 0x00E4//O
#define REG_SPIC_READ_DUAL_ADDR_DATA 0x00E8//O
#define REG_SPIC_READ_QUAD_DATA 0x00EC//O
#define REG_SPIC_READ_QUAD_ADDR_DATA 0x00F0//O
#define REG_SPIC_WRITE_SIGNLE 0x00F4//O
#define REG_SPIC_WRITE_DUAL_DATA 0x00F8//O
#define REG_SPIC_WRITE_DUAL_ADDR_DATA 0x00FC//O
#define REG_SPIC_WRITE_QUAD_DATA 0x0100//O
#define REG_SPIC_WRITE_QUAD_ADDR_DATA 0x0104//O
#define REG_SPIC_WRITE_ENABLE 0x0108//O
#define REG_SPIC_READ_STATUS 0x010C//O
#define REG_SPIC_CTRLR2 0x0110//O
#define REG_SPIC_FBAUDR 0x0114//O
#define REG_SPIC_ADDR_LENGTH 0x0118//O
#define REG_SPIC_AUTO_LENGTH 0x011C//O
#define REG_SPIC_VALID_CMD 0x0120//O
#define REG_SPIC_FLASE_SIZE 0x0124//O
#define REG_SPIC_FLUSH_FIFO 0x0128//O
#endif // end of "#ifndef _RTL8195A_SPI_FLASH_H"

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lib/fwlib/rtl8195a/rtl8195a_ssi.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_SSI_H_
#define _RTL8195A_SSI_H_
#define SSI_DUMMY_DATA 0x00 // for master mode, we need to push a Dummy data to TX FIFO for read
#define SSI_CLK_SPI1 (PLATFORM_CLOCK/2)
#define SSI_CLK_SPI0_2 (PLATFORM_CLOCK/4)
/* Parameters of DW_apb_ssi for RTL8195A */
#define SSI_TX_FIFO_DEPTH 64
#define TX_ABW 6 // 1-8, log2(SSI_TX_FIFO_DEPTH)
#define SSI_RX_FIFO_DEPTH 64
#define RX_ABW 6 // 1-8, log2(SSI_RX_FIFO_DEPTH)
#define SSI0_REG_BASE 0x40042000
#define SSI1_REG_BASE 0x40042400
#define SSI2_REG_BASE 0x40042800
/* Memory Map of DW_apb_ssi */
#define REG_DW_SSI_CTRLR0 0x00 // 16 bits
#define REG_DW_SSI_CTRLR1 0x04 // 16 bits
#define REG_DW_SSI_SSIENR 0x08 // 1 bit
#define REG_DW_SSI_MWCR 0x0C // 3 bits
#define REG_DW_SSI_SER 0x10 //
#define REG_DW_SSI_BAUDR 0x14 // 16 bits
#define REG_DW_SSI_TXFTLR 0x18 // TX_ABW
#define REG_DW_SSI_RXFTLR 0x1C // RX_ABW
#define REG_DW_SSI_TXFLR 0x20 //
#define REG_DW_SSI_RXFLR 0x24 //
#define REG_DW_SSI_SR 0x28 // 7 bits
#define REG_DW_SSI_IMR 0x2C //
#define REG_DW_SSI_ISR 0x30 // 6 bits
#define REG_DW_SSI_RISR 0x34 // 6 bits
#define REG_DW_SSI_TXOICR 0x38 // 1 bits
#define REG_DW_SSI_RXOICR 0x3C // 1 bits
#define REG_DW_SSI_RXUICR 0x40 // 1 bits
#define REG_DW_SSI_MSTICR 0x44 // 1 bits
#define REG_DW_SSI_ICR 0x48 // 1 bits
#define REG_DW_SSI_DMACR 0x4C // 2 bits
#define REG_DW_SSI_DMATDLR 0x50 // TX_ABW
#define REG_DW_SSI_DMARDLR 0x54 // RX_ABW
#define REG_DW_SSI_IDR 0x58 // 32 bits
#define REG_DW_SSI_COMP_VERSION 0x5C // 32 bits
#define REG_DW_SSI_DR 0x60 // 16 bits 0x60-0xEC
#define REG_DW_SSI_RX_SAMPLE_DLY 0xF0 // 8 bits
#define REG_DW_SSI_RSVD_0 0xF4 // 32 bits
#define REG_DW_SSI_RSVD_1 0xF8 // 32 bits
#define REG_DW_SSI_RSVD_2 0xFC // 32 bits
// CTRLR0 0x00 // 16 bits, 6.2.1
// DFS Reset Value: 0x7
#define BIT_SHIFT_CTRLR0_DFS 0
#define BIT_MASK_CTRLR0_DFS 0xF
#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS)
#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS))
#define BIT_SHIFT_CTRLR0_FRF 4
#define BIT_MASK_CTRLR0_FRF 0x3
#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF)
#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF))
#define BIT_SHIFT_CTRLR0_SCPH 6
#define BIT_MASK_CTRLR0_SCPH 0x1
#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH)
#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH))
#define BIT_SHIFT_CTRLR0_SCPOL 7
#define BIT_MASK_CTRLR0_SCPOL 0x1
#define BIT_CTRLR0_SCPOL(x)(((x) & BIT_MASK_CTRLR0_SCPOL) << BIT_SHIFT_CTRLR0_SCPOL)
#define BIT_INVC_CTRLR0_SCPOL (~(BIT_MASK_CTRLR0_SCPOL << BIT_SHIFT_CTRLR0_SCPOL))
#define BIT_SHIFT_CTRLR0_TMOD 8
#define BIT_MASK_CTRLR0_TMOD 0x3
#define BIT_CTRLR0_TMOD(x)(((x) & BIT_MASK_CTRLR0_TMOD) << BIT_SHIFT_CTRLR0_TMOD)
#define BIT_INVC_CTRLR0_TMOD (~(BIT_MASK_CTRLR0_TMOD << BIT_SHIFT_CTRLR0_TMOD))
#define BIT_SHIFT_CTRLR0_SLV_OE 10
#define BIT_MASK_CTRLR0_SLV_OE 0x1
#define BIT_CTRLR0_SLV_OE(x)(((x) & BIT_MASK_CTRLR0_SLV_OE) << BIT_SHIFT_CTRLR0_SLV_OE)
#define BIT_INVC_CTRLR0_SLV_OE (~(BIT_MASK_CTRLR0_SLV_OE << BIT_SHIFT_CTRLR0_SLV_OE))
#define BIT_SHIFT_CTRLR0_SRL 11
#define BIT_MASK_CTRLR0_SRL 0x1
#define BIT_CTRLR0_SRL(x)(((x) & BIT_MASK_CTRLR0_SRL) << BIT_SHIFT_CTRLR0_SRL)
#define BIT_INVC_CTRLR0_SRL (~(BIT_MASK_CTRLR0_SRL << BIT_SHIFT_CTRLR0_SRL))
#define BIT_SHIFT_CTRLR0_CFS 12
#define BIT_MASK_CTRLR0_CFS 0xF
#define BIT_CTRLR0_CFS(x)(((x) & BIT_MASK_CTRLR0_CFS) << BIT_SHIFT_CTRLR0_CFS)
#define BIT_INVC_CTRLR0_CFS (~(BIT_MASK_CTRLR0_CFS << BIT_SHIFT_CTRLR0_CFS))
// CTRLR1 0x04 // 16 bits
#define BIT_SHIFT_CTRLR1_NDF 0
#define BIT_MASK_CTRLR1_NDF 0xFFFF
#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF)
#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF))
// SSIENR 0x08 // 1 bit
#define BIT_SHIFT_SSIENR_SSI_EN 0
#define BIT_MASK_SSIENR_SSI_EN 0x1
#define BIT_SSIENR_SSI_EN(x)(((x) & BIT_MASK_SSIENR_SSI_EN) << BIT_SHIFT_SSIENR_SSI_EN)
#define BIT_INVC_SSIENR_SSI_EN (~(BIT_MASK_SSIENR_SSI_EN << BIT_SHIFT_SSIENR_SSI_EN))
// MWCR 0x0c // 3 bits
#define BIT_SHIFT_MWCR_MWMOD 0
#define BIT_MASK_MWCR_MWMOD 0x1
#define BIT_MWCR_MWMOD(x)(((x) & BIT_MASK_MWCR_MWMOD) << BIT_SHIFT_MWCR_MWMOD)
#define BIT_INVC_MWCR_MWMOD (~(BIT_MASK_MWCR_MWMOD << BIT_SHIFT_MWCR_MWMOD))
#define BIT_SHIFT_MWCR_MDD 1
#define BIT_MASK_MWCR_MDD 0x1
#define BIT_MWCR_MDD(x)(((x) & BIT_MASK_MWCR_MDD) << BIT_SHIFT_MWCR_MDD)
#define BIT_INVC_MWCR_MDD (~(BIT_MASK_MWCR_MDD << BIT_SHIFT_MWCR_MDD))
#define BIT_SHIFT_MWCR_MHS 2
#define BIT_MASK_MWCR_MHS 0x1
#define BIT_MWCR_MHS(x)(((x) & BIT_MASK_MWCR_MHS) << BIT_SHIFT_MWCR_MHS)
#define BIT_INVC_MWCR_MHS (~(BIT_MASK_MWCR_MHS << BIT_SHIFT_MWCR_MHS))
// SER 0x10 // Variable Length
#define BIT_SHIFT_SER_SER 0
#define BIT_MASK_SER_SER 0xFF
#define BIT_SER_SER(x)(((x) & BIT_MASK_SER_SER) << BIT_SHIFT_SER_SER)
#define BIT_INVC_SER_SER (~(BIT_MASK_SER_SER << BIT_SHIFT_SER_SER))
// BAUDR 0x14 // 16 bits
#define BIT_SHIFT_BAUDR_SCKDV 0
#define BIT_MASK_BAUDR_SCKDV 0xFFFF
#define BIT_BAUDR_SCKDV(x)(((x) & BIT_MASK_BAUDR_SCKDV) << BIT_SHIFT_BAUDR_SCKDV)
#define BIT_INVC_BAUDR_SCKDV (~(BIT_MASK_BAUDR_SCKDV << BIT_SHIFT_BAUDR_SCKDV))
// TXFLTR 0x18 // Variable Length
#define BIT_SHIFT_TXFTLR_TFT 0
#define BIT_MASK_TXFTLR_TFT 0x3F // (TX_ABW-1):0
#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT)
#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT))
// RXFLTR 0x1c // Variable Length
#define BIT_SHIFT_RXFTLR_RFT 0
#define BIT_MASK_RXFTLR_RFT 0x3F // (RX_ABW-1):0
#define BIT_RXFTLR_RFT(x)(((x) & BIT_MASK_RXFTLR_RFT) << BIT_SHIFT_RXFTLR_RFT)
#define BIT_INVC_RXFTLR_RFT (~(BIT_MASK_RXFTLR_RFT << BIT_SHIFT_RXFTLR_RFT))
// TXFLR 0x20 // see [READ ONLY]
#define BIT_MASK_TXFLR_TXTFL 0x7F // (TX_ABW):0
// RXFLR 0x24 // see [READ ONLY]
#define BIT_MASK_RXFLR_RXTFL 0x7F // (RX_ABW):0
// SR 0x28 // 7 bits [READ ONLY]
#define BIT_SR_BUSY BIT0
#define BIT_SR_TFNF BIT1
#define BIT_SR_TFE BIT2
#define BIT_SR_RFNE BIT3
#define BIT_SR_RFF BIT4
#define BIT_SR_TXE BIT5
#define BIT_SR_DCOL BIT6
// IMR 0x2c // see
#define BIT_SHIFT_IMR_TXEIM 0
#define BIT_MASK_IMR_TXEIM 0x1
// #define BIT_IMR_TXEIM(x)(((x) & BIT_MASK_IMR_TXEIM) << BIT_SHIFT_IMR_TXEIM)
#define BIT_INVC_IMR_TXEIM (~(BIT_MASK_IMR_TXEIM << BIT_SHIFT_IMR_TXEIM))
#define BIT_SHIFT_IMR_TXOIM 1
#define BIT_MASK_IMR_TXOIM 0x1
// #define BIT_IMR_TXOIM(x)(((x) & BIT_MASK_IMR_TXOIM) << BIT_SHIFT_IMR_TXOIM)
#define BIT_INVC_IMR_TXOIM (~(BIT_MASK_IMR_TXOIM << BIT_SHIFT_IMR_TXOIM))
#define BIT_SHIFT_IMR_RXUIM 2
#define BIT_MASK_IMR_RXUIM 0x1
// #define BIT_IMR_RXUIM(x)(((x) & BIT_MASK_IMR_RXUIM) << BIT_SHIFT_IMR_RXUIM)
#define BIT_INVC_IMR_RXUIM (~(BIT_MASK_IMR_RXUIM << BIT_SHIFT_IMR_RXUIM))
#define BIT_SHIFT_IMR_RXOIM 3
#define BIT_MASK_IMR_RXOIM 0x1
// #define BIT_IMR_RXOIM(x)(((x) & BIT_MASK_IMR_RXOIM) << BIT_SHIFT_IMR_RXOIM)
#define BIT_INVC_IMR_RXOIM (~(BIT_MASK_IMR_RXOIM << BIT_SHIFT_IMR_RXOIM))
#define BIT_SHIFT_IMR_RXFIM 4
#define BIT_MASK_IMR_RXFIM 0x1
// #define BIT_IMR_RXFIM(x)(((x) & BIT_MASK_IMR_RXFIM) << BIT_SHIFT_IMR_RXFIM)
#define BIT_INVC_IMR_RXFIM (~(BIT_MASK_IMR_RXFIM << BIT_SHIFT_IMR_RXFIM))
#define BIT_SHIFT_IMR_MSTIM 5
#define BIT_MASK_IMR_MSTIM 0x1
// #define BIT_IMR_MSTIM(x)(((x) & BIT_MASK_IMR_MSTIM) << BIT_SHIFT_IMR_MSTIM)
#define BIT_INVC_IMR_MSTIM (~(BIT_MASK_IMR_MSTIM << BIT_SHIFT_IMR_MSTIM))
#define BIT_IMR_TXEIM BIT0
#define BIT_IMR_TXOIM BIT1
#define BIT_IMR_RXUIM BIT2
#define BIT_IMR_RXOIM BIT3
#define BIT_IMR_RXFIM BIT4
#define BIT_IMR_MSTIM BIT5
// ISR 0x30 // 6 bits [READ ONLY]
#define BIT_ISR_TXEIS BIT0
#define BIT_ISR_TXOIS BIT1
#define BIT_ISR_RXUIS BIT2
#define BIT_ISR_RXOIS BIT3
#define BIT_ISR_RXFIS BIT4
#define BIT_ISR_MSTIS BIT5
// RISR 0x34 // 6 bits [READ ONLY]
#define BIT_RISR_TXEIR BIT0
#define BIT_RISR_TXOIR BIT1
#define BIT_RISR_RXUIR BIT2
#define BIT_RISR_RXOIR BIT3
#define BIT_RISR_RXFIR BIT4
#define BIT_RISR_MSTIR BIT5
// TXOICR 0x38 // 1 bits [READ ONLY]
// RXOICR 0x3c // 1 bits [READ ONLY]
// RXUICR 0x40 // 1 bits [READ ONLY]
// MSTICR 0x44 // 1 bits [READ ONLY]
// ICR 0x48 // 1 bits [READ ONLY]
// DMACR 0x4c // 2 bits
#define BIT_SHIFT_DMACR_RDMAE 0
#define BIT_MASK_DMACR_RDMAE 0x1
#define BIT_DMACR_RDMAE(x)(((x) & BIT_MASK_DMACR_RDMAE) << BIT_SHIFT_DMACR_RDMAE)
#define BIT_INVC_DMACR_RDMAE (~(BIT_MASK_DMACR_RDMAE << BIT_SHIFT_DMACR_RDMAE))
#define BIT_SHIFT_DMACR_TDMAE 1
#define BIT_MASK_DMACR_TDMAE 0x1
#define BIT_DMACR_TDMAE(x)(((x) & BIT_MASK_DMACR_TDMAE) << BIT_SHIFT_DMACR_TDMAE)
#define BIT_INVC_DMACR_TDMAE (~(BIT_MASK_DMACR_TDMAE << BIT_SHIFT_DMACR_TDMAE))
// DMATDLR 0x50
#define BIT_SHIFT_DMATDLR_DMATDL 0
#define BIT_MASK_DMATDLR_DMATDL 0x3F // (TX_ABW-1):0
#define BIT_DMATDLR_DMATDL(x)(((x) & BIT_MASK_DMATDLR_DMATDL) << BIT_SHIFT_DMATDLR_DMATDL)
#define BIT_INVC_DMATDLR_DMATDL (~(BIT_MASK_DMATDLR_DMATDL << BIT_SHIFT_DMATDLR_DMATDL))
// DMARDLR 0x54
#define BIT_SHIFT_DMARDLR_DMARDL 0
#define BIT_MASK_DMARDLR_DMARDL 0x3F // (RX_ABW-1):0
#define BIT_DMARDLR_DMARDL(x)(((x) & BIT_MASK_DMARDLR_DMARDL) << BIT_SHIFT_DMARDLR_DMARDL)
#define BIT_INVC_DMARDLR_DMARDL (~(BIT_MASK_DMARDLR_DMARDL << BIT_SHIFT_DMARDLR_DMARDL))
// IDR 0x58 // 32 bits [READ ONLY]
// COMP_VERSION 0x5c // 32 bits [READ ONLY]
// DR 0x60 // 16 bits 0x60-0xEC
#define BIT_SHIFT_DR_DR 0
#define BIT_MASK_DR_DR 0xFFFF
#define BIT_DR_DR(x)(((x) & BIT_MASK_DR_DR) << BIT_SHIFT_DR_DR)
#define BIT_INVC_DR_DR (~(BIT_MASK_DR_DR << BIT_SHIFT_DR_DR))
// RX_SAMPLE_DLY 0xF0 // 8 bits
#define BIT_SHIFT_RX_SAMPLE_DLY_RSD 0
#define BIT_MASK_RX_SAMPLE_DLY_RSD 0xFFFF
#define BIT_RX_SAMPLE_DLY_RSD(x)(((x) & BIT_MASK_RX_SAMPLE_DLY_RSD) << BIT_SHIFT_RX_SAMPLE_DLY_RSD)
#define BIT_INVC_RX_SAMPLE_DLY_RSD (~(BIT_MASK_RX_SAMPLE_DLY_RSD << BIT_SHIFT_RX_SAMPLE_DLY_RSD))
// RSVD_0 0xF4 // 32 bits
// RSVD_1 0xF8 // 32 bits
// RSVD_2 0xFC // 32 bits
// SSI0 Pinmux
#define BIT_SHIFT_SSI0_PIN_EN 0
#define BIT_MASK_SSI0_PIN_EN 0x1
#define BIT_SSI0_PIN_EN(x)(((x) & BIT_MASK_SSI0_PIN_EN) << BIT_SHIFT_SSI0_PIN_EN)
#define BIT_INVC_SSI0_PIN_EN (~(BIT_MASK_SSI0_PIN_EN << BIT_SHIFT_SSI0_PIN_EN))
#define BIT_SHIFT_SSI0_PIN_SEL 1
#define BIT_MASK_SSI0_PIN_SEL 0x7
#define BIT_SSI0_PIN_SEL(x)(((x) & BIT_MASK_SSI0_PIN_SEL) << BIT_SHIFT_SSI0_PIN_SEL)
#define BIT_INVC_SSI0_PIN_SEL (~(BIT_MASK_SSI0_PIN_SEL << BIT_SHIFT_SSI0_PIN_SEL))
// SSI1 Pinmux
#define BIT_SHIFT_SSI1_PIN_EN 4
#define BIT_MASK_SSI1_PIN_EN 0x1
#define BIT_SSI1_PIN_EN(x)(((x) & BIT_MASK_SSI1_PIN_EN) << BIT_SHIFT_SSI1_PIN_EN)
#define BIT_INVC_SSI1_PIN_EN (~(BIT_MASK_SSI1_PIN_EN << BIT_SHIFT_SSI1_PIN_EN))
#define BIT_SHIFT_SSI1_PIN_SEL 5
#define BIT_MASK_SSI1_PIN_SEL 0x7
#define BIT_SSI1_PIN_SEL(x)(((x) & BIT_MASK_SSI1_PIN_SEL) << BIT_SHIFT_SSI1_PIN_SEL)
#define BIT_INVC_SSI1_PIN_SEL (~(BIT_MASK_SSI1_PIN_SEL << BIT_SHIFT_SSI1_PIN_SEL))
// SSI2 Pinmux
#define BIT_SHIFT_SSI2_PIN_EN 8
#define BIT_MASK_SSI2_PIN_EN 0x1
#define BIT_SSI2_PIN_EN(x)(((x) & BIT_MASK_SSI2_PIN_EN) << BIT_SHIFT_SSI2_PIN_EN)
#define BIT_INVC_SSI2_PIN_EN (~(BIT_MASK_SSI2_PIN_EN << BIT_SHIFT_SSI2_PIN_EN))
#define BIT_SHIFT_SSI2_PIN_SEL 9
#define BIT_MASK_SSI2_PIN_SEL 0x7
#define BIT_SSI2_PIN_SEL(x)(((x) & BIT_MASK_SSI2_PIN_SEL) << BIT_SHIFT_SSI2_PIN_SEL)
#define BIT_INVC_SSI2_PIN_SEL (~(BIT_MASK_SSI2_PIN_SEL << BIT_SHIFT_SSI2_PIN_SEL))
// SSI0 Multiple Chip Selection (Pinmux Select is controlled by BIT_SSI0_PIN_SEL)
#define BIT_SHIFT_SSI0_MULTI_CS_EN 28
#define BIT_MASK_SSI0_MULTI_CS_EN 0x1
#define BIT_SSI0_MULTI_CS_EN(x)(((x) & BIT_MASK_SSI0_MULTI_CS_EN) << BIT_SHIFT_SSI0_MULTI_CS_EN)
#define BIT_INVC_SSI0_MULTI_CS_EN (~(BIT_MASK_SSI0_MULTI_CS_EN << BIT_SHIFT_SSI0_MULTI_CS_EN))
#define HAL_SSI_READ32(SsiIndex, addr) \
HAL_READ32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE32(SsiIndex, addr, value) \
HAL_WRITE32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
#define HAL_SSI_READ16(SsiIndex, addr) \
HAL_READ16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE16(SsiIndex, addr, value) \
HAL_WRITE16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
#define HAL_SSI_READ8(SsiIndex, addr) \
HAL_READ8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE8(SsiIndex, addr, value) \
HAL_WRITE8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
// SSI Pinmux Select
typedef enum _SSI0_PINMUX_SELECT_ {
SSI0_MUX_TO_GPIOE = S0,
SSI0_MUX_TO_GPIOC = S1
}SSI0_PINMUX_SELECT, *PSSI0_PINMUX_SELECT;
typedef enum _SSI1_PINMUX_SELECT_ {
SSI1_MUX_TO_GPIOA = S0,
SSI1_MUX_TO_GPIOB = S1,
SSI1_MUX_TO_GPIOD = S2
}SSI1_PINMUX_SELECT, *PSSI1_PINMUX_SELECT;
typedef enum _SSI2_PINMUX_SELECT_ {
SSI2_MUX_TO_GPIOG = S0,
SSI2_MUX_TO_GPIOE = S1,
SSI2_MUX_TO_GPIOD = S2
}SSI2_PINMUX_SELECT, *PSSI2_PINMUX_SELECT;
typedef enum _SSI0_MULTI_CS_PINMUX_SELECT_ {
SSI0_CS_MUX_TO_GPIOE = S0,
SSI0_CS_MUX_TO_GPIOC = S1
}SSI0_MULTI_CS_PINMUX_SELECT, *PSSI0_MULTI_CS_PINMUX_SELECT;
typedef enum _SSI_CTRLR0_TMOD_ {
TMOD_TR = 0,
TMOD_TO = 1,
TMOD_RO = 2,
TMOD_EEPROM_R = 3
}SSI_CTRLR0_TMOD, *PSSI_CTRLR0_TMOD;
typedef enum _SSI_CTRLR0_SCPOL_ {
SCPOL_INACTIVE_IS_LOW = 0,
SCPOL_INACTIVE_IS_HIGH = 1
}SSI_CTRLR0_SCPOL, *PSSI_CTRLR0_SCPOL;
typedef enum _SSI_CTRLR0_SCPH_ {
SCPH_TOGGLES_IN_MIDDLE = 0,
SCPH_TOGGLES_AT_START = 1
}SSI_CTRLR0_SCPH, *PSSI_CTRLR0_SCPH;
typedef enum _SSI_CTRLR0_DFS_ {
DFS_4_BITS = 3,
DFS_5_BITS = 4,
DFS_6_BITS = 5,
DFS_7_BITS = 6,
DFS_8_BITS = 7,
DFS_9_BITS = 8,
DFS_10_BITS = 9,
DFS_11_BITS = 10,
DFS_12_BITS = 11,
DFS_13_BITS = 12,
DFS_14_BITS = 13,
DFS_15_BITS = 14,
DFS_16_BITS = 15,
}SSI_CTRLR0_DFS, *PSSI_CTRLR0_DFS;
typedef enum _SSI_CTRLR0_CFS_ {
CFS_1_BIT = 0,
CFS_2_BITS = 1,
CFS_3_BITS = 2,
CFS_4_BITS = 3,
CFS_5_BITS = 4,
CFS_6_BITS = 5,
CFS_7_BITS = 6,
CFS_8_BITS = 7,
CFS_9_BITS = 8,
CFS_10_BITS = 9,
CFS_11_BITS = 10,
CFS_12_BITS = 11,
CFS_13_BITS = 12,
CFS_14_BITS = 13,
CFS_15_BITS = 14,
CFS_16_BITS = 15
}SSI_CTRLR0_CFS, *PSSI_CTRLR0_CFS;
typedef enum _SSI_CTRLR0_SLV_OE_ {
SLV_TXD_ENABLE = 0,
SLV_TXD_DISABLE = 1
}SSI_CTRLR0_SLV_OE, *PSSI_CTRLR0_SLV_OE;
typedef enum _SSI_ROLE_SELECT_ {
SSI_SLAVE = 0,
SSI_MASTER = 1
}SSI_ROLE_SELECT, *PSSI_ROLE_SELECT;
typedef enum _SSI_FRAME_FORMAT_ {
FRF_MOTOROLA_SPI = 0,
FRF_TI_SSP = 1,
FRF_NS_MICROWIRE = 2,
FRF_RSVD = 3
}SSI_FRAME_FORMAT, *PSSI_FRAME_FORMAT;
typedef enum _SSI_DMACR_ENABLE_ {
SSI_NODMA = 0,
SSI_RXDMA_ENABLE = 1,
SSI_TXDMA_ENABLE = 2,
SSI_TRDMA_ENABLE = 3
}SSI_DMACR_ENABLE, *PSSI_DMACR_ENABLE;
typedef enum _SSI_MWCR_HANDSHAKE_ {
MW_HANDSHAKE_DISABLE = 0,
MW_HANDSHAKE_ENABLE = 1
}SSI_MWCR_HANDSHAKE, *PSSI_MWCR_HANDSHAKE;
typedef enum _SSI_MWCR_DIRECTION_ {
MW_DIRECTION_SLAVE_TO_MASTER = 0,
MW_DIRECTION_MASTER_TO_SLAVE = 1
}SSI_MWCR_DIRECTION, *PSSI_MWCR_DIRECTION;
typedef enum _SSI_MWCR_TMOD_ {
MW_TMOD_NONSEQUENTIAL = 0,
MW_TMOD_SEQUENTIAL = 1
}SSI_MWCR_TMOD, *PSSI_MWCR_TMOD;
typedef enum _SSI_DATA_TRANSFER_MECHANISM_ {
SSI_DTM_BASIC,
SSI_DTM_INTERRUPT,
SSI_DTM_DMA
}SSI_DATA_TRANSFER_MECHANISM, *PSSI_DATA_TRANSFER_MECHANISM;
_LONG_CALL_ HAL_Status HalSsiPinmuxEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiDisableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiInitRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetSclkPolarityRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetSclkPhaseRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiWriteRtl8195a(VOID *Adaptor, u32 value);
_LONG_CALL_ HAL_Status HalSsiLoadSettingRtl8195a(VOID *Adaptor, VOID *Setting);
_LONG_CALL_ HAL_Status HalSsiSetInterruptMaskRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetDeviceRoleRtl8195a(VOID *Adaptor, u32 Role);
_LONG_CALL_ HAL_Status HalSsiInterruptEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiInterruptDisableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiReadInterruptRtl8195a(VOID *Adaptor, VOID *RxData, u32 Length);
_LONG_CALL_ HAL_Status HalSsiSetRxFifoThresholdLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetTxFifoThresholdLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiWriteInterruptRtl8195a(VOID *Adaptor, VOID *TxData, u32 Length);
_LONG_CALL_ HAL_Status HalSsiSetSlaveEnableRegisterRtl8195a(VOID *Adaptor, u32 SlaveIndex);
_LONG_CALL_ u32 HalSsiBusyRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiWriteableRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiReadableRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetInterruptMaskRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetRxFifoLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetTxFifoLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetInterruptStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiReadRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetRawInterruptStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetSlaveEnableRegisterRtl8195a(VOID *Adaptor);
_LONG_CALL_ VOID _SsiReadInterrupt(VOID *Adaptor);
_LONG_CALL_ VOID _SsiWriteInterrupt(VOID *Adaptor);
_LONG_CALL_ u32 _SsiIrqHandle(VOID *Adaptor);
// ROM code patch
VOID _SsiReadInterruptRtl8195a(VOID *Adapter);
VOID _SsiWriteInterruptRtl8195a(VOID *Adapter);
HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor);
HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor);
HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor);
HAL_Status HalSsiDeInitRtl8195a(VOID * Adapter);
HAL_Status HalSsiClockOffRtl8195a(VOID * Adapter);
HAL_Status HalSsiClockOnRtl8195a(VOID * Adapter);
VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate);
HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length);
HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
#ifdef CONFIG_GDMA_EN
VOID HalSsiTxGdmaLoadDefRtl8195a(VOID *Adapter);
VOID HalSsiRxGdmaLoadDefRtl8195a(VOID *Adapter);
VOID HalSsiDmaInitRtl8195a(VOID *Adapter);
HAL_Status HalSsiDmaSendRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
HAL_Status HalSsiDmaRecvRtl8195a(VOID *Adapter, u8 *pRxData, u32 Length);
#endif // end of "#ifdef CONFIG_GDMA_EN"
#endif

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lib/fwlib/rtl8195a/rtl8195a_sys_on.h Normal file
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lib/fwlib/rtl8195a/rtl8195a_timer.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_TIMER_H_
#define _RTL8195A_TIMER_H_
#define TIMER_TICK_US 31
#define TIMER_LOAD_COUNT_OFF 0x00
#define TIMER_CURRENT_VAL_OFF 0x04
#define TIMER_CTL_REG_OFF 0x08
#define TIMER_EOI_OFF 0x0c
#define TIMER_INT_STATUS_OFF 0x10
#define TIMER_INTERVAL 0x14
#define TIMERS_INT_STATUS_OFF 0xa0
#define TIMERS_EOI_OFF 0xa4
#define TIMERS_RAW_INT_STATUS_OFF 0xa8
#define TIMERS_COMP_VER_OFF 0xac
#define MAX_TIMER_VECTOR_TABLE_NUM 6
#define HAL_TIMER_READ32(addr) (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE32(addr, value) ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ16(addr) (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE16(addr, value) ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ8(addr) (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE8(addr, value) ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value)
_LONG_CALL_ u32
HalGetTimerIdRtl8195a(
IN u32 *TimerID
);
_LONG_CALL_ BOOL
HalTimerInitRtl8195a(
IN VOID *Data
);
_LONG_CALL_ u32
HalTimerReadCountRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerIrqClearRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDisRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerEnRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDumpRegRtl8195a(
IN u32 TimerId
);
// ROM Code patch
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
);
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
);
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
);
#ifdef CONFIG_CHIP_C_CUT
__weak _LONG_CALL_
VOID
HalTimerIrq2To7HandleV02(
IN VOID *Data
);
__weak _LONG_CALL_
HAL_Status
HalTimerIrqRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
HAL_Status
HalTimerInitRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
u32
HalTimerReadCountRtl8195aV02(
IN u32 TimerId
);
__weak _LONG_CALL_
VOID
HalTimerReLoadRtl8195aV02(
IN u32 TimerId,
IN u32 LoadUs
);
__weak _LONG_CALL_
HAL_Status
HalTimerIrqUnRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
VOID
HalTimerDeInitRtl8195aV02(
IN VOID *Data
);
#endif // end of "#ifdef CONFIG_CHIP_C_CUT"
// HAL functions wrapper
static __inline HAL_Status
HalTimerInit(
IN VOID *Data
)
{
return (HalTimerInitRtl8195a_Patch(Data));
}
static __inline VOID
HalTimerEnable(
IN u32 TimerId
)
{
HalTimerIrqEnRtl8195a(TimerId);
HalTimerEnRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerDisable(
IN u32 TimerId
)
{
HalTimerDisRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerReLoad(
IN u32 TimerId,
IN u32 LoadUs
)
{
HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs);
}
#ifndef CONFIG_CHIP_C_CUT
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195a_Patch(Data);
}
#else
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195aV02(Data);
}
#endif // end of "#ifndef CONFIG_CHIP_C_CUT"
#endif //_RTL8195A_TIMER_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_UART_H_
#define _RTL8195A_UART_H_
#define MAX_UART_INDEX 2
#define RUART_DLL_OFF 0x00
#define RUART_DLM_OFF 0x04 //RW, DLAB = 1
#define RUART_INTERRUPT_EN_REG_OFF 0x04
#define RUART_IER_ERBI 0x01 //BIT0, Enable Received Data Available Interrupt (rx trigger)
#define RUART_IER_ETBEI (1<<1) //BIT1, Enable Transmitter FIFO Empty Interrupt (tx fifo empty)
#define RUART_IER_ELSI (1<<2) //BIT2, Enable Receiver Line Status Interrupt (receiver line status)
#define RUART_IER_EDSSI (1<<3) //BIT3, Enable Modem Status Interrupt (modem status transition)
#define RUART_INT_ID_REG_OFF 0x08 //[R]
#define RUART_IIR_INT_PEND 0x01
#define RUART_IIR_INT_ID (0x07<<1) //011(3), 010(2), 110(6), 001(1), 000(0)
#define RUART_FIFO_CTL_REG_OFF 0x08 //[W]
#define RUART_FIFO_CTL_REG_CLEAR_RXFIFO (1<<1) //BIT1, 0x02, Write 1 clear
#define RUART_FIFO_CTL_REG_CLEAR_TXFIFO (1<<2) //BIT2, 0x04, Write 1 clear
#define RUART_FIFO_CTL_REG_DMA_ENABLE 0x08 //BIT3
#define FIFO_CTL_DEFAULT_WITH_FIFO_DMA 0xC9
#define FIFO_CTL_DEFAULT_WITH_FIFO 0xC1
#define RUART_MODEM_CTL_REG_OFF 0x10
#define RUART_MCR_RTS BIT1
#define RUART_MCL_AUTOFLOW_ENABLE (1<<5) //BIT5, 0x20
#define RUART_LINE_CTL_REG_OFF 0x0C
#define RUART_LINE_CTL_REG_DLAB_ENABLE (1<<7) //BIT7, 0x80
#define RUART_LINE_STATUS_REG_OFF 0x14
#define RUART_LINE_STATUS_REG_DR 0x01 //BIT0, Data Ready indicator
#define RUART_LINE_STATUS_ERR_OVERRUN (1<<1) //BIT1, Over Run
#define RUART_LINE_STATUS_ERR_PARITY (1<<2) //BIT2, Parity error
#define RUART_LINE_STATUS_ERR_FRAMING (1<<3) //BIT3, Framing error
#define RUART_LINE_STATUS_ERR_BREAK (1<<4) //BIT4, Break interrupt error
#define RUART_LINE_STATUS_REG_THRE (1<<5) //BIT5, 0x20, Transmit Holding Register Empty Interrupt enable
#define RUART_LINE_STATUS_REG_TEMT (1<<6) //BIT6, 0x40, Transmitter Empty indicator(bit)
#define RUART_LINE_STATUS_ERR_RXFIFO (1<<7) //BIT7, RX FIFO error
#define RUART_LINE_STATUS_ERR (RUART_LINE_STATUS_ERR_OVERRUN|RUART_LINE_STATUS_ERR_PARITY| \
RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \
RUART_LINE_STATUS_ERR_RXFIFO) //Line status error
#define RUART_MODEM_STATUS_REG_OFF 0x18 //Modem Status Register
#define RUART_SCRATCH_PAD_REG_OFF 0x1C //Scratch Pad Register
#define RUART_SP_REG_RXBREAK_INT_STATUS (1<<7) //BIT7, 0x80, Write 1 clear
#define RUART_SP_REG_DBG_SEL (0x0F<<8) //[11:8], Debug port selection
#define RUART_SP_REG_XFACTOR_ADJ (0x7FF<<16) //[26:16]
#define RUART_STS_REG_OFF 0x20
#define RUART_STS_REG_RESET_RCV (1<<3) //BIT3, 0x08, Reset Uart Receiver
#define RUART_STS_REG_XFACTOR 0xF<<4
#define RUART_REV_BUF_REG_OFF 0x24 //Receiver Buffer Register
#define RUART_TRAN_HOLD_REG_OFF 0x24 //Transmitter Holding Register
#define RUART_MISC_CTL_REG_OFF 0x28
#define RUART_TXDMA_BURSTSIZE_MASK 0xF8 //7:3
#define RUART_RXDMA_BURSTSIZE_MASK 0x1F00 //12:8
#define RUART_DEBUG_REG_OFF 0x3C
// RUART_LINE_CTL_REG_OFF (0x0C)
#define BIT_SHIFT_LCR_WLS 0 // word length select: 0: 7 bits, 1: 8bits
#define BIT_MASK_LCR_WLS_8BITS 0x1
#define BIT_LCR_WLS(x)(((x) & BIT_MASK_LCR_WLS_8BITS) << BIT_SHIFT_LCR_WLS)
#define BIT_CLR_LCR_WLS (~(BIT_MASK_LCR_WLS_8BITS << BIT_SHIFT_LCR_WLS))
#define BIT_SHIFT_LCR_STB 2 // Stop bit select: 0: no stop bit, 1: 1 stop bit
#define BIT_MASK_LCR_STB_EN 0x1
#define BIT_LCR_STB_EN(x)(((x) & BIT_MASK_LCR_STB_EN) << BIT_SHIFT_LCR_STB)
#define BIT_INVC_LCR_STB_EN (~(BIT_MASK_LCR_STB_EN << BIT_SHIFT_LCR_STB))
#define BIT_SHIFT_LCR_PARITY_EN 3
#define BIT_MASK_LCR_PARITY_EN 0x1
#define BIT_LCR_PARITY_EN(x)(((x) & BIT_MASK_LCR_PARITY_EN) << BIT_SHIFT_LCR_PARITY_EN)
#define BIT_INVC_LCR_PARITY_EN (~(BIT_MASK_LCR_PARITY_EN << BIT_SHIFT_LCR_PARITY_EN))
#define BIT_SHIFT_LCR_PARITY_TYPE 4
#define BIT_MASK_LCR_PARITY_TYPE 0x1
#define BIT_LCR_PARITY_TYPE(x)(((x) & BIT_MASK_LCR_PARITY_TYPE) << BIT_SHIFT_LCR_PARITY_TYPE)
#define BIT_INVC_LCR_PARITY_TYPE (~(BIT_MASK_LCR_PARITY_TYPE << BIT_SHIFT_LCR_PARITY_TYPE))
#define BIT_SHIFT_LCR_STICK_PARITY_EN 5
#define BIT_MASK_LCR_STICK_PARITY_EN 0x1
#define BIT_LCR_STICK_PARITY_EN(x)(((x) & BIT_MASK_LCR_STICK_PARITY_EN) << BIT_SHIFT_LCR_STICK_PARITY_EN)
#define BIT_INVC_LCR_STICK_PARITY_EN (~(BIT_MASK_LCR_STICK_PARITY_EN << BIT_SHIFT_LCR_STICK_PARITY_EN))
#define BIT_SHIFT_LCR_BREAK_CTRL 6
#define BIT_MASK_LCR_BREAK_CTRL 0x1
#define BIT_UART_LCR_BREAK_CTRL ((BIT_MASK_LCR_BREAK_CTRL) << BIT_SHIFT_LCR_BREAK_CTRL)
#define RUART_BAUD_RATE_2400 2400
#define RUART_BAUD_RATE_4800 4800
#define RUART_BAUD_RATE_9600 9600
#define RUART_BAUD_RATE_19200 19200
#define RUART_BAUD_RATE_38400 38400
#define RUART_BAUD_RATE_57600 57600
#define RUART_BAUD_RATE_115200 115200
#define RUART_BAUD_RATE_921600 921600
#define RUART_BAUD_RATE_1152000 1152000
#define HAL_RUART_READ32(UartIndex, addr) \
HAL_READ32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE32(UartIndex, addr, value) \
HAL_WRITE32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
#define HAL_RUART_READ16(UartIndex, addr) \
HAL_READ16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE16(UartIndex, addr, value) \
HAL_WRITE16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
#define HAL_RUART_READ8(UartIndex, addr) \
HAL_READ8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE8(UartIndex, addr, value) \
HAL_WRITE8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
#define UART_OVSR_POOL_MIN 1000
#define UART_OVSR_POOL_MAX 2090
#define DIVISOR_RESOLUTION 10
#define JITTER_LIMIT 100
#define UART_SCLK (200000000*5/12)
typedef struct _RUART_SPEED_SETTING_ {
u32 BaudRate;
u32 Ovsr;
u32 Div;
u16 Ovsr_adj;
u8 Ovsr_adj_max_bits; // 9: No parity, 10: with Parity
u8 Ovsr_adj_bits;
u16 *Ovsr_adj_map;
u32 max_err; // 10 ~ 100: 30
u32 Ovsr_min; // 10 ~ 20: 1000
u32 Ovsr_max; // 10 ~ 20: 2000
u32 divisor_resolution; // 1 ~ 20: 10
u32 jitter_lim; // 50 ~ 100: 100
u32 sclk; // 83.33333 MHz
}RUART_SPEED_SETTING, *PRUART_SPEED_SETTING;
typedef enum _UART_RXFIFO_TRIGGER_LEVEL_ {
OneByte = 0x00,
FourBytes = 0x01,
EightBytes = 0x10,
FourteenBytes = 0x11
}UART_RXFIFO_TRIGGER_LEVEL, *PUART_RXFIFO_TRIGGER_LEVEL;
typedef enum _RUART0_PINMUX_SELECT_ {
RUART0_MUX_TO_GPIOC = S0,
RUART0_MUX_TO_GPIOE = S1,
RUART0_MUX_TO_GPIOA = S2
}RUART0_PINMUX_SELECT, *PRUART0_PINMUX_SELECT;
typedef enum _RUART1_PINMUX_SELECT_ {
RUART1_MUX_TO_GPIOD = S0,
RUART1_MUX_TO_GPIOE = S1,
RUART1_MUX_TO_GPIOB = S2
}RUART1_PINMUX_SELECT, *PRUART1_PINMUX_SELECT;
typedef enum _RUART2_PINMUX_SELECT_ {
RUART2_MUX_TO_GPIOA = S0,
RUART2_MUX_TO_GPIOC = S1,
RUART2_MUX_TO_GPIOD = S2
}RUART2_PINMUX_SELECT, *PRUART2_PINMUX_SELECT;
typedef enum _RUART_FLOW_CONTROL_ {
AUTOFLOW_DISABLE = 0,
AUTOFLOW_ENABLE = 1
}RUART_FLOW_CONTROL, *PRUART_FLOW_CONTROL;
typedef enum _RUART_WORD_LEN_SEL_ {
RUART_WLS_7BITS = 0,
RUART_WLS_8BITS = 1
}RUART_WORD_LEN_SEL, *PRUART_WORD_LEN_SEL;
typedef enum _RUART_STOP_BITS_ {
RUART_STOP_BIT_1 = 0,
RUART_STOP_BIT_2 = 1
}RUART_STOP_BITS, *PRUART_STOP_BITS;
typedef enum _RUART_PARITY_CONTROL_ {
RUART_PARITY_DISABLE = 0,
RUART_PARITY_ENABLE = 1
}RUART_PARITY_CONTROL, *PRUART_PARITY_CONTROL;
typedef enum _RUART_PARITY_TYPE_ {
RUART_ODD_PARITY = 0,
RUART_EVEN_PARITY = 1
}RUART_PARITY_TYPE, *PRUART_PARITY_TYPE;
typedef enum _RUART_STICK_PARITY_CONTROL_ {
RUART_STICK_PARITY_DISABLE = 0,
RUART_STICK_PARITY_ENABLE = 1
}RUART_STICK_PARITY_CONTROL, *PRUART_STICK_PARITY_CONTROL;
typedef enum _UART_INT_ID_ {
ModemStatus = 0,
TxFifoEmpty = 1,
ReceiverDataAvailable = 2,
ReceivLineStatus = 3,
TimeoutIndication = 6
}UART_INT_ID, *PUART_INT_ID;
typedef enum _HAL_UART_State_
{
HAL_UART_STATE_NULL = 0x00, // UART hardware not been initial yet
HAL_UART_STATE_READY = 0x10, // UART is initialed, ready to use
HAL_UART_STATE_BUSY = 0x20, // UART hardware is busy on configuration
HAL_UART_STATE_BUSY_TX = 0x21, // UART is buzy on TX
HAL_UART_STATE_BUSY_RX = 0x22, // UART is busy on RX
HAL_UART_STATE_BUSY_TX_RX = 0x23, // UART is busy on TX an RX
HAL_UART_STATE_TIMEOUT = 0x30, // Transfer timeout
HAL_UART_STATE_ERROR = 0x40 // UART Error
}HAL_UART_State, *PHAL_UART_State;
typedef enum _HAL_UART_Status_
{
HAL_UART_STATUS_OK = 0x00, // Transfer OK
HAL_UART_STATUS_TIMEOUT = 0x01, // Transfer Timeout
HAL_UART_STATUS_ERR_OVERRUN = 0x02, // RX Over run
HAL_UART_STATUS_ERR_PARITY = 0x04, // Parity error
HAL_UART_STATUS_ERR_FRAM = 0x08, // Framing Error
HAL_UART_STATUS_ERR_BREAK = 0x10, // Break Interrupt
HAL_UART_STATUS_ERR_PARA = 0x20, // Parameter error
HAL_UART_STATUS_ERR_RXFIFO = 0x80, // RX FIFO error
}HAL_UART_Status, *PHAL_UART_Status;
u32
HalRuartGetDebugValueRtl8195a(
IN VOID* Data,
IN u32 DbgSel
);
#if 0
u32
FindElementIndex(
u32 Element,
u32* Array
);
#endif
VOID
RuartResetRxFifoRtl8195a(
IN u8 UartIndex
);
#if 0
VOID
RuartBusDomainEnableRtl8195a(
IN u8 UartIndex
);
#endif
HAL_Status
HalRuartResetRxFifoRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartInitRtl8195a(
IN VOID *Data
);
VOID
HalRuartDeInitRtl8195a(
IN VOID *Data ///< RUART Adapter
);
HAL_Status
HalRuartPutCRtl8195a(
IN VOID *Data,
IN u8 TxData
);
u32
HalRuartSendRtl8195a(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length,
IN u32 Timeout
);
HAL_Status
HalRuartIntSendRtl8195a(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
HAL_Status
HalRuartDmaSendRtl8195a(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
HAL_Status
HalRuartStopSendRtl8195a(
IN VOID *Data // PHAL_RUART_ADAPTER
);
HAL_Status
HalRuartGetCRtl8195a(
IN VOID *Data,
OUT u8 *pRxByte
);
u32
HalRuartRecvRtl8195a(
IN VOID *Data,
IN u8 *pRxData,
IN u32 Length,
IN u32 Timeout
);
HAL_Status
HalRuartIntRecvRtl8195a(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
HAL_Status
HalRuartDmaRecvRtl8195a(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
HAL_Status
HalRuartStopRecvRtl8195a(
IN VOID *Data // PHAL_RUART_ADAPTER
);
u8
HalRuartGetIMRRtl8195a(
IN VOID *Data
);
_LONG_CALL_ VOID
HalRuartSetIMRRtl8195a(
IN VOID *Data
);
VOID
HalRuartDmaInitRtl8195a(
IN VOID *Data
);
VOID
HalRuartRTSCtrlRtl8195a(
IN VOID *Data,
IN BOOLEAN RtsCtrl
);
VOID
HalRuartRegIrqRtl8195a(
IN VOID *Data
);
VOID
HalRuartIntEnableRtl8195a(
IN VOID *Data
);
VOID
HalRuartIntDisableRtl8195a(
IN VOID *Data
);
VOID
HalRuartAdapterLoadDefRtl8195a(
IN VOID *pAdp,
IN u8 UartIdx
);
VOID
HalRuartTxGdmaLoadDefRtl8195a(
IN VOID *pAdp,
IN VOID *pCfg
);
VOID
HalRuartRxGdmaLoadDefRtl8195a(
IN VOID *pAdp,
IN VOID *pCfg
);
_LONG_CALL_ HAL_Status HalRuartIntSendRtl8195aV02(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
_LONG_CALL_ HAL_Status
HalRuartIntRecvRtl8195aV02(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
_LONG_CALL_ s32
FindElementIndex_v02(
u32 Element, ///< RUART Baudrate
u32* Array, ///< Pre-defined Baudrate Array
u32 ElementNo
);
_LONG_CALL_ HAL_Status HalRuartInitRtl8195a_v02(IN VOID *Data);
// New added function 2015/04/20
HAL_Status
HalRuartResetTxFifoRtl8195a(
IN VOID *Data ///< RUART Adapter
);
HAL_Status
HalRuartSetBaudRateRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartEnableRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartDisableRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartFlowCtrlRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartDmaSendRtl8195a_Patch(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length
);
HAL_Status
RuartIsTimeout (
u32 StartCount,
u32 TimeoutCnt
);
HAL_Status
HalRuartStopRecvRtl8195a_Patch(
IN VOID *Data
);
HAL_Status
HalRuartStopSendRtl8195a_Patch(
IN VOID *Data
);
VOID
HalRuartEnterCriticalRtl8195a(
IN VOID *Data
);
VOID
HalRuartExitCriticalRtl8195a(
IN VOID *Data
);
#if CONFIG_CHIP_E_CUT
_LONG_CALL_ HAL_Status
HalRuartSetBaudRateRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartInitRtl8195a_V04(
IN VOID *Data ///< RUART Adapter
);
_LONG_CALL_ HAL_Status
HalRuartEnableRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartDisableRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartFlowCtrlRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartDmaSendRtl8195a_V04(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length
);
_LONG_CALL_ HAL_Status
HalRuartStopRecvRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartStopSendRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ VOID
HalRuartEnterCriticalRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ VOID
HalRuartExitCriticalRtl8195a_V04(
IN VOID *Data
);
#endif // #if CONFIG_CHIP_E_CUT
#endif

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lib/fwlib/rtl8195a/rtl8195a_wdt.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2014 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_WDT_H_
#define _RTL8195A_WDT_H_
#define WDGTIMERELY (10*1024) //us
typedef struct _WDG_REG_ {
u16 WdgScalar;
u8 WdgEnByte;
u8 WdgClear:1;
u8 WdgCunLimit:4;
u8 Rsvd:1;
u8 WdgMode:1;
u8 WdgToISR:1;
}WDG_REG, *PWDG_REG;
typedef struct _WDG_ADAPTER_ {
WDG_REG Ctrl;
IRQ_HANDLE IrqHandle;
TIMER_ADAPTER WdgGTimer;
VOID (*UserCallback)(u32 callback_id); // User callback function
u32 callback_id;
}WDG_ADAPTER, *PWDG_ADAPTER;
typedef enum _WDG_CNTLMT_ {
CNT1H = 0,
CNT3H = 1,
CNT7H = 2,
CNTFH = 3,
CNT1FH = 4,
CNT3FH = 5,
CNT7FH = 6,
CNTFFH = 7,
CNT1FFH = 8,
CNT3FFH = 9,
CNT7FFH = 10,
CNTFFFH = 11
}WDG_CNTLMT, *PWDG_CNTLMT;
typedef enum _WDG_MODE_ {
INT_MODE = 0,
RESET_MODE = 1
}WDG_MODE, *PWDG_MODE;
extern VOID
WDGInitial(
IN u32 Period
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGStop(
VOID
);
extern VOID
WDGRefresh(
VOID
);
extern VOID
WDGIrqCallBackReg(
IN VOID *CallBack,
IN u32 Id
);
#endif //_RTL8195A_WDT_H_

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lib/fwlib/rtl8195a/src/rtl8195a_adc.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "platform_autoconf.h"
#include "diag.h"
#include "rtl8195a_adc.h"
#include "hal_adc.h"
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCInit8195a(
IN VOID *Data
)
{
PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
u32 AdcTempDat;
u8 AdcTempIdx = pHalAdcInitData->ADCIdx;
/* Enable ADC power cut */
/*
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
AdcTempDat |= BIT_ADC_PWR_AUTO;
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
*/
/* ADC Control register set-up*/
AdcTempDat = 0;
AdcTempDat |= (BIT_CTRL_ADC_COMP_ONLY(pHalAdcInitData->ADCCompOnly) |
BIT_CTRL_ADC_ONESHOT(pHalAdcInitData->ADCOneShotEn) |
BIT_CTRL_ADC_OVERWRITE(pHalAdcInitData->ADCOverWREn) |
BIT_CTRL_ADC_ENDIAN(pHalAdcInitData->ADCEndian) |
BIT_CTRL_ADC_BURST_SIZE(pHalAdcInitData->ADCBurstSz) |
BIT_CTRL_ADC_THRESHOLD(pHalAdcInitData->ADCOneShotTD) |
BIT_CTRL_ADC_DBG_SEL(pHalAdcInitData->ADCDbgSel));
HAL_ADC_WRITE32(REG_ADC_CONTROL,AdcTempDat);
DBG_8195A_ADC_LVL(HAL_ADC_LVL,"REG_ADC_CONTROL:%x\n", HAL_ADC_READ32(REG_ADC_CONTROL));
/* ADC compare value and compare method setting*/
switch (AdcTempIdx) {
case ADC0_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_L);
AdcTempDat &= ~(BIT_ADC_COMP_TH_0(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_0(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat);
break;
case ADC1_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_L);
AdcTempDat &= ~(BIT_ADC_COMP_TH_1(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_1(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat);
break;
case ADC2_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_H);
AdcTempDat &= ~(BIT_ADC_COMP_TH_2(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_2(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat);
break;
case ADC3_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_H);
AdcTempDat &= ~(BIT_ADC_COMP_TH_3(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_3(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat);
break;
default:
return _EXIT_FAILURE;
}
/* ADC compare mode setting */
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_SET);
AdcTempDat &= (~(0x01 << pHalAdcInitData->ADCIdx));
AdcTempDat |= (BIT_CTRL_ADC_COMP_0_EN(pHalAdcInitData->ADCCompCtrl) <<
pHalAdcInitData->ADCIdx);
HAL_ADC_WRITE32(REG_ADC_COMP_SET, AdcTempDat);
/* ADC audio mode set-up */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
AdcTempDat &= ~(BIT_ADC_AUDIO_EN);
AdcTempDat |= BIT_CTRL_ADC_AUDIO_EN(pHalAdcInitData->ADCAudioEn);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
/* ADC enable manually setting */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
AdcTempDat &= ~(BIT_ADC_EN_MANUAL);
AdcTempDat |= BIT_CTRL_ADC_EN_MANUAL(pHalAdcInitData->ADCEnManul);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
/* ADC analog parameter 0 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("AD0:%x\n", AdcTempDat);
//AdcTempDat |= (BIT0);
if (pHalAdcInitData->ADCInInput == 1){
AdcTempDat &= (~BIT14);
}
else {
AdcTempDat |= (BIT14);
}
AdcTempDat &= (~(BIT3|BIT2));
/* Adjust VCM for C-Cut*/
#ifdef CONFIG_CHIP_C_CUT
AdcTempDat |= (BIT22);
#endif
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("AD0:%x\n", AdcTempDat);
/* ADC analog parameter 1 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
AdcTempDat &= (~BIT1);
AdcTempDat |= (BIT2|BIT0);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
DBG_ADC_INFO("AD1:%x\n", AdcTempDat);
/* ADC analog parameter 2 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD2);
DBG_ADC_INFO("AD2:%x\n", AdcTempDat);
AdcTempDat = 0x67884400;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD2, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD2);
DBG_ADC_INFO("AD2:%x\n", AdcTempDat);
/* ADC analog parameter 3 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD3);
DBG_ADC_INFO("AD3:%x\n", AdcTempDat);
AdcTempDat = 0x77780039;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD3, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD3);
DBG_ADC_INFO("AD3:%x\n", AdcTempDat);
/* ADC analog parameter 4 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD4);
DBG_ADC_INFO("AD4:%x\n", AdcTempDat);
AdcTempDat = 0x0004d501;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD4, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD4);
DBG_ADC_INFO("AD4:%x\n", AdcTempDat);
/* ADC analog parameter 5 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD5);
DBG_ADC_INFO("AD5:%x\n", AdcTempDat);
AdcTempDat = 0x1E010800;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD5, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD5);
DBG_ADC_INFO("AD5:%x\n", AdcTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCDeInit8195a(
IN VOID *Data
)
{
u32 AdcTempDat;
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
AdcTempDat &= ~(BIT_ADC_PWR_AUTO);
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCEnableRtl8195a(
IN VOID *Data
){
PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
u32 AdcTempDat;
DBG_ADC_INFO("HalADCEnableRtl8195a\n");
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
AdcTempDat &= (~BIT_ADC_PWR_AUTO);
AdcTempDat |= 0x02;
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
AdcTempDat |= 0x04;
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
AdcTempDat &= (~0x08);
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_POWER);
DBG_ADC_INFO("HalADCEnableRtl8195a, power reg:%x\n",AdcTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCIntrCtrl8195a(
IN VOID *Data
){
PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
HAL_ADC_WRITE32(REG_ADC_INTR_EN, pHalAdcInitData->ADCIntrMSK);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CReceiveRtl8195a
//
// Description:
// Directly read one data byte a I2C data fifo.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The first data fifo content.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
u32
HalADCReceiveRtl8195a(
IN VOID *Data
){
u32 AdcTempDat;
AdcTempDat = HAL_ADC_READ32(REG_ADC_FIFO_READ);
return (AdcTempDat);
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CReadRegRtl8195a
//
// Description:
// Directly read a I2C register according to the register offset.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
// [in] I2CReg -
// The I2C register offset.
//
// Return:
// The register content in u32 format.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
u32
HalADCReadRegRtl8195a(
IN VOID *Data,
IN u8 I2CReg
){
u32 AdcTempDat;
AdcTempDat = HAL_ADC_READ32(I2CReg);
return (AdcTempDat);
}

269
lib/fwlib/rtl8195a/src/rtl8195a_dac.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_dac.h"
#include "hal_dac.h"
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalDACInit8195a
//
// Description:
// To initialize DAC module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The DAC parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-15.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACInit8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
u32 DacTempDat;
u8 DacTempIdx = pHalDacInitData->DACIdx;
/* Enable DAC power cut */
DacTempDat = HAL_DAC_READ32(0, REG_DAC_PWR_CTRL);
DacTempDat |= BIT_DAC_PWR_AUTO;
HAL_DAC_WRITE32(0, REG_DAC_PWR_CTRL, DacTempDat);
/* Disable DAC module first */
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, 0);
/* Setup DAC module */
DacTempDat = 0;
DacTempDat |= (BIT_CTRL_DAC_SPEED(pHalDacInitData->DACDataRate) |
BIT_CTRL_DAC_ENDIAN(pHalDacInitData->DACEndian) |
BIT_CTRL_DAC_FILTER_SETTLE(pHalDacInitData->DACFilterSet) |
BIT_CTRL_DAC_BURST_SIZE(pHalDacInitData->DACBurstSz) |
BIT_CTRL_DAC_DBG_SEL(pHalDacInitData->DACDbgSel) |
BIT_CTRL_DAC_DSC_DBG_SEL(pHalDacInitData->DACDscDbgSel) |
BIT_CTRL_DAC_BYPASS_DSC(pHalDacInitData->DACBPDsc) |
BIT_CTRL_DAC_DELTA_SIGMA(pHalDacInitData->DACDeltaSig));
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACDeInit8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
u32 DacTempDat;
DacTempDat = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_CTRL);
DacTempDat &= (~BIT_DAC_FIFO_EN);
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_CTRL ,DacTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACEnableRtl8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
u32 DacTempDat;
u8 DacTempIdx = pHalDacInitData->DACIdx;
DacTempDat = HAL_DAC_READ32(DacTempIdx, REG_DAC_CTRL);
DacTempDat &= (~BIT_DAC_FIFO_EN);
DacTempDat |= BIT_CTRL_DAC_FIFO_EN(pHalDacInitData->DACEn);
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACIntrCtrl8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_INTR_CTRL, pHalDacInitData->DACIntrMSK);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CReceiveRtl8195a
//
// Description:
// Directly read one data byte a I2C data fifo.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The first data fifo content.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
u8
HalDACSendRtl8195a(
IN VOID *Data
){
return (0);
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalDACReadRegRtl8195a
//
// Description:
//
//
// Arguments:
// [in] VOID *Data -
// The DAC parameter data struct.
// [in] I2CReg -
// The DAC register offset.
//
// Return:
// The DAC register content in u32 format.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-15.
//
//---------------------------------------------------------------------------------------------------
u32
HalDACReadRegRtl8195a(
IN VOID *Data,
IN u8 I2CReg
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
//DBG_8195A_DAC("dac read reg idx:%x\n",pHalDacInitData->DACIdx);
//DBG_8195A_DAC("dac read reg offset:%x\n",I2CReg);
return (u32)HAL_DAC_READ32(pHalDacInitData->DACIdx, I2CReg);
}

291
lib/fwlib/rtl8195a/src/rtl8195a_gdma.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_gdma.h"
#include "hal_gdma.h"
#ifndef CONFIG_CHIP_E_CUT
BOOL
HalGdmaChBlockSetingRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pGdmaChLli;
struct BLOCK_SIZE_LIST *pGdmaChBkLi;
u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock;
u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 ChEn = pHalGdmaAdapter->ChEn;
u8 GdmaChIsrBitmap = (ChEn & 0xFF);
u8 PendingIsrIndex;
pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
//4 1) Check chanel is avaliable
if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
//4 Disable Channel
DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
HalGdmaChDisRtl8195a(Data);
}
//4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran, Error
for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) {
u32 PendRaw, PendStstus;
PendRaw = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8));
PendStstus = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8));
if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) {
//4 Clear Pending Isr
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8),
(PendStstus & (GdmaChIsrBitmap))
);
}
}
//4 Fill in SARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChSar)
);
//4 Fill in DARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChDar)
);
//4 3) Process CTLx
CtlxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF));
//4 Clear Config low register bits
CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN &
BIT_INVC_CTLX_LO_DST_TR_WIDTH &
BIT_INVC_CTLX_LO_SRC_TR_WIDTH &
BIT_INVC_CTLX_LO_DINC &
BIT_INVC_CTLX_LO_SINC &
BIT_INVC_CTLX_LO_DEST_MSIZE &
BIT_INVC_CTLX_LO_SRC_MSIZE &
BIT_INVC_CTLX_LO_TT_FC &
BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
CtlxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4));
//4 Clear Config upper register bits
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS &
BIT_INVC_CTLX_UP_DONE);
CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) |
BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) |
BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) |
BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) |
BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) |
BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) |
BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) |
BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) |
BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) |
CtlxLow;
CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) |
BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) |
CtlxUp;
//4 Fill in CTLx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF),
CtlxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4),
CtlxUp
);
//4 4) Program CFGx
CfgxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF));
CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR &
BIT_INVC_CFGX_LO_CH_SUSP &
BIT_INVC_CFGX_LO_HS_SEL_DST &
BIT_INVC_CFGX_LO_HS_SEL_SRC &
BIT_INVC_CFGX_LO_LOCK_CH_L &
BIT_INVC_CFGX_LO_LOCK_B_L &
BIT_INVC_CFGX_LO_LOCK_CH &
BIT_INVC_CFGX_LO_LOCK_B &
BIT_INVC_CFGX_LO_RELOAD_SRC &
BIT_INVC_CFGX_LO_RELOAD_DST);
CfgxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4));
CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE &
BIT_INVC_CFGX_UP_DS_UPD_EN &
BIT_INVC_CFGX_UP_SS_UPD_EN &
BIT_INVC_CFGX_UP_SRC_PER &
BIT_INVC_CFGX_UP_DEST_PER);
CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) |
BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) |
BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) |
BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) |
BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) |
BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) |
BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) |
BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) |
BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) |
BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) |
CfgxLow;
CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) |
BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) |
BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) |
BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) |
BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) |
CfgxUp;
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4),
CfgxUp
);
//4 Check 4 Bytes Alignment
if ((u32)(pLliEle) & 0x3) {
DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!!!!\n",
pHalGdmaAdapter->pLli);
return _FALSE;
}
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF),
pLliEle
);
//4 Update the first llp0
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)pGdmaChLli->pLliEle;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
while (MultiBlockCount > 1) {
MultiBlockCount--;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pLliEle = pGdmaChLli->pLliEle;
if (NULL == pLliEle) {
DBG_GDMA_ERR("pLliEle Null Point!!!!!\n");
return _FALSE;
}
//4 Clear the last element llp enable bit
if (1 == MultiBlockCount) {
if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 1){
CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
}
}
//4 Update block size for transfer
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
//4 Update tje Lli and Block size list point to next llp
pGdmaChLli = pGdmaChLli->pNextLli;
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
//4 Updatethe Llpx context
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle);
}
return _TRUE;
}
u32
HalGdmaQueryDArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
u32
HalGdmaQuerySArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
BOOL
HalGdmaQueryChEnRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
if (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN) & (pHalGdmaAdapter->ChEn)) {
return 1;
} else {
return 0;
}
}
#endif

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lib/fwlib/rtl8195a/src/rtl8195a_gpio.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "hal_gpio.h"
#include "rtl8195a_gpio.h"
#include "gpio_irq_api.h"
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
/**
* @brief Clear the pending interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
HAL_Status
HAL_GPIO_ClearISR_8195a(
HAL_GPIO_PIN *GPIO_Pin
)
{
u8 port_num;
u8 pin_num;
HAL_GPIO_PIN_MODE pin_mode;
port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
pin_mode = GPIO_Pin->pin_mode;
if ((pin_mode & HAL_GPIO_PIN_INT_MODE)==0 || (port_num != GPIO_PORT_A)) {
DBG_GPIO_WARN("HAL_GPIO_ClearISR_8195a: This pin(%x:%x) is'nt an interrupt pin\n", GPIO_Pin->pin_name, GPIO_Pin->pin_mode);
return HAL_ERR_PARA;
}
if (GPIO_Lock() != HAL_OK) {
return HAL_BUSY;
}
// Clear pending interrupt before unmask it
HAL_WRITE32(GPIO_REG_BASE, GPIO_PORTA_EOI, (1<<pin_num));
GPIO_UnLock();
return HAL_OK;
}

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
/* Used only for A~C Version */
#ifndef CONFIG_CHIP_E_CUT
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CSendRtl8195a
//
// Description:
// Send one byte to the I2C internal fifo, it will generate START and STOP bit
// automatically.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// _EXIT_SUCCESS if the sending succeeded.
// _EXIT_FAILURE if the sending failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
HAL_Status
HalI2CSendRtl8195a_Patch(
IN VOID *Data
){
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
u8 I2CIdx = pHalI2CInitData->I2CIdx;
u8 *pDat = pHalI2CInitData->I2CRWData;
u8 I2CCmd = pHalI2CInitData->I2CCmd;
u8 I2CStop = pHalI2CInitData->I2CStop;
u8 I2CReSTR= pHalI2CInitData->I2CReSTR;
DBG_I2C_INFO("HalI2CSendRtl8195a\n");
DBG_I2C_INFO("I2C Index: %x\n",I2CIdx);
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DATA_CMD,
*(pDat) |
BIT_CTRL_IC_DATA_CMD_RESTART(I2CReSTR)|
BIT_CTRL_IC_DATA_CMD_CMD(I2CCmd) |
BIT_CTRL_IC_DATA_CMD_STOP(I2CStop));
return (HAL_OK);
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
HAL_Status
HalI2CInit8195a_Patch(
IN VOID *Data
)
{
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
u8 Master;
u8 I2CIdx;
u8 SpdMd;
u8 AddrMd;
u8 ReSTR;
u8 StartByte;
u8 Specical;
u8 GC;
u16 I2CAckAddr;
u16 SdaHd;
u8 SdaSetup;
u8 RXTL;
u8 TXTL;
u8 SlvNoAck;
u32 INTRMsk;
u8 TxDMARqLv;
u8 RxDMARqLv;
/* Get the I2C parameters*/
I2CIdx = pHalI2CInitData->I2CIdx;
SpdMd = pHalI2CInitData->I2CSpdMod;
AddrMd = pHalI2CInitData->I2CAddrMod;
I2CAckAddr = pHalI2CInitData->I2CAckAddr;
Master = pHalI2CInitData->I2CMaster;
SdaHd = pHalI2CInitData->I2CSdaHd;
SdaSetup = pHalI2CInitData->I2CSetup;
ReSTR = pHalI2CInitData->I2CReSTR;
GC = pHalI2CInitData->I2CGC;
StartByte = pHalI2CInitData->I2CStartB;
SlvNoAck = pHalI2CInitData->I2CSlvNoAck;
RXTL = pHalI2CInitData->I2CRXTL;
TXTL = pHalI2CInitData->I2CTXTL;
TxDMARqLv = pHalI2CInitData->I2CTxDMARqLv;
RxDMARqLv = pHalI2CInitData->I2CRxDMARqLv;
/* Disable the IC first */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_ENABLE,BIT_CTRL_IC_ENABLE(0));
/* Master case*/
if (Master) {
/*RESTART MUST be set in these condition in Master mode.
But it might be NOT compatible in old slaves.*/
if ((AddrMd == I2C_ADDR_10BIT) || (SpdMd == I2C_HS_MODE))
ReSTR = 1;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_CON,
(BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(1) |
BIT_CTRL_IC_CON_IC_RESTART_EN(ReSTR) |
BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(AddrMd) |
BIT_CTRL_IC_CON_SPEED(SpdMd) |
BIT_CTRL_IC_CON_MASTER_MODE(Master)));
DBG_I2C_INFO("Init master, IC_CON%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_CON, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_CON));
/* To set target addr.*/
Specical = 0;
if ((GC!=0) || (StartByte!=0))
Specical = 1;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_TAR,
(BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(AddrMd) |
BIT_CTRL_IC_TAR_SPECIAL(Specical) |
BIT_CTRL_IC_TAR_GC_OR_START(StartByte) |
BIT_CTRL_IC_TAR(I2CAckAddr)));
/* To Set I2C clock*/
HalI2CSetCLKRtl8195a_Patch(pHalI2CInitData);
DBG_I2C_INFO("Init master, IC_TAR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_TAR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_TAR));
} /*if (Master)*/
else {
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_CON,
BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(AddrMd) |
BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(Master) |
BIT_CTRL_IC_CON_SPEED(SpdMd)|
BIT_CTRL_IC_CON_MASTER_MODE(Master));
DBG_I2C_INFO("Init slave, IC_CON%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_CON, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_CON));
/* To set slave addr. */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SAR,BIT_CTRL_IC_SAR(I2CAckAddr));
DBG_I2C_INFO("Init slave, IC_SAR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_SAR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SAR));
/* To set slave no ack */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SLV_DATA_NACK_ONLY,BIT_CTRL_IC_SLV_DATA_NACK_ONLY(SlvNoAck));
/* Set ack general call. */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_ACK_GENERAL_CALL,BIT_CTRL_IC_ACK_GENERAL_CALL(pHalI2CInitData->I2CSlvAckGC));
DBG_I2C_INFO("Init slave, I2C_IC_ACK_GC%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_ACK_GENERAL_CALL, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_ACK_GENERAL_CALL));
/* to set SDA hold time */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(SdaHd));
//4
/* to set SDA setup time */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_SETUP,BIT_CTRL_IC_SDA_SETUP(SdaSetup));
}
/* To set TX_Empty Level */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_TX_TL,TXTL);
/* To set RX_Full Level */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_RX_TL,RXTL);
/* To set TX/RX FIFO level */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DMA_TDLR,TxDMARqLv);
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DMA_RDLR,RxDMARqLv);
DBG_I2C_INFO("Init i2c dev, I2C_IC_DMA_TDLR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_DMA_TDLR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_DMA_TDLR));
DBG_I2C_INFO("Init i2c dev, I2C_IC_DMA_RDLR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_DMA_RDLR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_DMA_RDLR));
/*I2C Clear all interrupts first*/
HalI2CClrAllIntrRtl8195a(pHalI2CInitData);
/*I2C Disable all interrupts first*/
INTRMsk = pHalI2CInitData->I2CIntrMSK;
pHalI2CInitData->I2CIntrMSK = 0;
HalI2CIntrCtrl8195a(pHalI2CInitData);
pHalI2CInitData->I2CIntrMSK = INTRMsk;
return HAL_OK;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CSetCLKRtl8195a
//
// Description:
// To set I2C bus clock rate.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
HAL_Status
HalI2CSetCLKRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
u8 SpdMd = pHalI2CInitData->I2CSpdMod;
u32 I2CClk = pHalI2CInitData->I2CClk;
u8 I2CIdx = pHalI2CInitData->I2CIdx;
u32 ICHLcnt;
u32 ICHtime;
u32 ICLtime;
/* Get the IC-Clk setting first for the following process*/
#ifdef CONFIG_FPGA
u32 IcClk = SYSTEM_CLK/1000000;
#else
u32 IcClk;
u32 ClkSELTmp = 0;
u32 CpuClkTmp = 0;
#if defined(CONFIG_CHIP_A_CUT)
CpuClkTmp = StartupHalGetCpuClk();
#elif (defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT))
CpuClkTmp = HalGetCpuClk();
#endif
DBG_I2C_INFO("%s, CPU Clk:%x\n",__func__, CpuClkTmp);
ClkSELTmp = HAL_READ32(PERI_ON_BASE, REG_PESOC_CLK_SEL);
ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3)));
HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp);
IcClk = (CpuClkTmp/1000000)>>1;
#if 0
if ((I2CClk > 0) && (I2CClk <= 400)) {
ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3)));
HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp);
IcClk = ClkSELTmp/1000000; /*actually it's 12.5MHz*/
}
else {
ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3)));
HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp);
IcClk = 100;
}
#endif
#endif
switch (SpdMd)
{
case I2C_SS_MODE:
{
ICHtime = ((1000000/I2CClk)*I2C_SS_MIN_SCL_HTIME)/(I2C_SS_MIN_SCL_HTIME+I2C_SS_MIN_SCL_LTIME);
ICLtime = ((1000000/I2CClk)*I2C_SS_MIN_SCL_LTIME)/(I2C_SS_MIN_SCL_HTIME+I2C_SS_MIN_SCL_LTIME);
ICHLcnt = (ICHtime * IcClk)/1000;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT,ICHLcnt);
DBG_I2C_INFO("IC_SS_SCL_HCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_SS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT));
ICHLcnt = (ICLtime * IcClk)/1000;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT,ICHLcnt);
DBG_I2C_INFO("IC_SS_SCL_LCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_SS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT));
break;
}
case I2C_FS_MODE:
{
ICHtime = ((1000000/I2CClk)*I2C_FS_MIN_SCL_HTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
ICLtime = ((1000000/I2CClk)*I2C_FS_MIN_SCL_LTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
ICHLcnt = (ICHtime * IcClk)/1000;
if (ICHLcnt>4)/*this part is according to the fine-tune result*/
ICHLcnt -= 4;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT,ICHLcnt);
DBG_I2C_INFO("IC_FS_SCL_HCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_FS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT));
ICHLcnt = (ICLtime * IcClk)/1000;
if (ICHLcnt>3)/*this part is according to the fine-tune result*/
ICHLcnt -= 3;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT,ICHLcnt);
DBG_I2C_INFO("IC_FS_SCL_LCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_FS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT));
break;
}
case I2C_HS_MODE:
{
ICHLcnt = 400;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT,ICHLcnt);
ICHLcnt = 470;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT,ICHLcnt);
ICHLcnt = 60;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT,ICHLcnt);
ICHLcnt = 130;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT,ICHLcnt);
ICHtime = ((1000000/I2CClk)*I2C_HS_MIN_SCL_HTIME_100)/(I2C_HS_MIN_SCL_HTIME_100+I2C_HS_MIN_SCL_LTIME_100);
ICLtime = ((1000000/I2CClk)*I2C_HS_MIN_SCL_LTIME_100)/(I2C_HS_MIN_SCL_HTIME_100+I2C_HS_MIN_SCL_LTIME_100);
DBG_I2C_INFO("ICHtime:%x\n",ICHtime);
DBG_I2C_INFO("ICLtime:%x\n",ICLtime);
ICHLcnt = (ICHtime * IcClk)/1000;
if (ICHLcnt>8)/*this part is according to the fine-tune result*/
ICHLcnt -= 3;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_HS_SCL_HCNT,ICHLcnt);
DBG_I2C_INFO("IC_HS_SCL_HCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_HS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_HS_SCL_HCNT));
ICHLcnt = (ICLtime * IcClk)/1000;
if (ICHLcnt>6)/*this part is according to the fine-tune result*/
ICHLcnt -= 6;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_HS_SCL_LCNT,ICHLcnt);
DBG_I2C_INFO("IC_HS_SCL_LCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_HS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_HS_SCL_LCNT));
break;
}
default:
break;
}
return HAL_OK;
}
#endif

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lib/fwlib/rtl8195a/src/rtl8195a_i2s.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_i2s.h"
#include "hal_i2s.h"
extern void *
_memset( void *s, int c, SIZE_T n );
RTK_STATUS
HalI2SInitRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
//u8 I2SEn;
u8 I2SMaster;
u8 I2SWordLen;
u8 I2SChNum;
u8 I2SPageNum;
u16 I2SPageSize;
u16 I2SRate;
u32 I2STxIntrMSK;
u32 I2SRxIntrMSK;
u8 I2STRxAct;
u8 *I2STxData;
u8 *I2SRxData;
u32 Tmp;
I2SIdx = pHalI2SInitData->I2SIdx;
//I2SEn = pHalI2SInitData->I2SEn;
I2SMaster = pHalI2SInitData->I2SMaster;
I2SWordLen = pHalI2SInitData->I2SWordLen;
I2SChNum = pHalI2SInitData->I2SChNum;
I2SPageNum = pHalI2SInitData->I2SPageNum;
I2SPageSize = pHalI2SInitData->I2SPageSize;
I2SRate = pHalI2SInitData->I2SRate;
I2STRxAct = pHalI2SInitData->I2STRxAct;
I2STxData = pHalI2SInitData->I2STxData;
I2SRxData = pHalI2SInitData->I2SRxData;
/* Disable the I2S first, and reset to default */
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
BIT_CTRL_CTLX_I2S_SW_RSTN(1));
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
BIT_CTRL_CTLX_I2S_SW_RSTN(0));
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
BIT_CTRL_CTLX_I2S_SW_RSTN(1));
Tmp = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
Tmp |= BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(1);
if (I2SRate&0x10)
{
Tmp |= BIT_CTRL_CTLX_I2S_CLK_SRC(1);
}
Tmp |= (BIT_CTRL_CTLX_I2S_WL(I2SWordLen) | BIT_CTRL_CTLX_I2S_CH_NUM(I2SChNum) |
BIT_CTRL_CTLX_I2S_SLAVE_MODE(I2SMaster) | BIT_CTRL_CTLX_I2S_TRX_ACT(I2STRxAct));
/* set 44.1khz clock source, word length, channel number, master or slave, trx act */
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, Tmp);
Tmp = BIT_CTRL_SETTING_I2S_PAGE_SZ(I2SPageSize) | BIT_CTRL_SETTING_I2S_PAGE_NUM(I2SPageNum) |
BIT_CTRL_SETTING_I2S_SAMPLE_RATE(I2SRate);
/* set page size, page number, sample rate */
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, Tmp);
/* need tx rx buffer? need rx page own bit */
if (I2STxData != NULL) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (u32)I2STxData);
}
if (I2SRxData != NULL) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (u32)I2SRxData);
}
pHalI2SInitData->I2STxIdx = 0;
pHalI2SInitData->I2SRxIdx = 0;
pHalI2SInitData->I2SHWTxIdx = 0;
pHalI2SInitData->I2SHWRxIdx = 0;
/* I2S Clear all interrupts first */
HalI2SClrAllIntrRtl8195a(pHalI2SInitData);
/* I2S Disable all interrupts first */
I2STxIntrMSK = pHalI2SInitData->I2STxIntrMSK;
I2SRxIntrMSK = pHalI2SInitData->I2SRxIntrMSK;
pHalI2SInitData->I2STxIntrMSK = 0;
pHalI2SInitData->I2SRxIntrMSK = 0;
HalI2SIntrCtrlRtl8195a(pHalI2SInitData);
pHalI2SInitData->I2STxIntrMSK = I2STxIntrMSK;
pHalI2SInitData->I2SRxIntrMSK = I2SRxIntrMSK;
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetRateRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_CLK_SRC << BIT_SHIFT_CTLX_I2S_CLK_SRC);
if (pHalI2SInitData->I2SRate&0x10)
{
reg_value |= BIT_CTRL_CTLX_I2S_CLK_SRC(1);
}
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_SAMPLE_RATE << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE);
reg_value |= BIT_CTRL_SETTING_I2S_SAMPLE_RATE(pHalI2SInitData->I2SRate);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetWordLenRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_WL << BIT_SHIFT_CTLX_I2S_WL);
reg_value |= BIT_CTRL_CTLX_I2S_WL(pHalI2SInitData->I2SWordLen);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetChNumRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_CH_NUM << BIT_SHIFT_CTLX_I2S_CH_NUM);
reg_value |= BIT_CTRL_CTLX_I2S_CH_NUM(pHalI2SInitData->I2SChNum);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetPageNumRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetPageSizeRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetDirectionRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_TRX_ACT << BIT_SHIFT_CTLX_I2S_TRX_ACT);
reg_value |= BIT_CTRL_CTLX_I2S_TRX_ACT(pHalI2SInitData->I2STRxAct);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetDMABufRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
u32 page_num;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
page_num = pHalI2SInitData->I2SPageNum + 1;
if (pHalI2SInitData->I2STxData) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2STxData);
pHalI2SInitData->I2STxIntrMSK = (1<<page_num) - 1;
} else {
pHalI2SInitData->I2STxIntrMSK = 0;
}
if (pHalI2SInitData->I2SRxData) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2SRxData);
pHalI2SInitData->I2SRxIntrMSK = (1<<page_num) - 1;
} else {
pHalI2SInitData->I2SRxIntrMSK = 0;
}
// According to the page number to modify the ISR mask
HalI2SIntrCtrlRtl8195a(pHalI2SInitData);
return _EXIT_SUCCESS;
}
u8
HalI2SGetTxPageRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u16 I2STxIdx = pHalI2SInitData->I2STxIdx;
u32 reg;
I2SIdx = pHalI2SInitData->I2SIdx;
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(I2STxIdx<<2));
if ((reg & (1<<31)) == 0) {
return I2STxIdx;
} else {
return 0xFF;
}
}
u8
HalI2SGetRxPageRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx;
u32 reg;
I2SIdx = pHalI2SInitData->I2SIdx;
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2));
if ((reg & (1<<31)) == 0) {
return I2SRxIdx;
} else {
return 0xFF;
}
}
RTK_STATUS
HalI2SPageSendRtl8195a(
IN VOID *Data,
IN u8 PageIdx
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u16 I2STxIdx = pHalI2SInitData->I2STxIdx;
u8 I2SPageNum = pHalI2SInitData->I2SPageNum;
u8 I2SIdx;
if (I2STxIdx != PageIdx) {
DBG_I2S_ERR("HalI2SPageSendRtl8195a: UnExpected Page Index. TxPage=%d, Expected:%d\r\n",
PageIdx, I2STxIdx);
}
I2SIdx = pHalI2SInitData->I2SIdx;
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN+4*PageIdx, 1<<31);
I2STxIdx = PageIdx+1;
if (I2STxIdx > I2SPageNum) {
I2STxIdx = 0;
}
pHalI2SInitData->I2STxIdx = I2STxIdx;
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SPageRecvRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx;
u8 I2SPageNum = pHalI2SInitData->I2SPageNum;
u32 reg;
u8 I2SIdx;
I2SIdx = pHalI2SInitData->I2SIdx;
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2));
if ((reg & (1<<31)) != 0) {
DBG_I2S_ERR("HalI2SPageRecvRtl8195a: No Idle Rx Page\r\n");
return _EXIT_FAILURE;
}
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx<<2), 1<<31);
I2SRxIdx += 1;
if (I2SRxIdx > I2SPageNum) {
I2SRxIdx = 0;
}
pHalI2SInitData->I2SRxIdx = I2SRxIdx;
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SClearAllOwnBitRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 i;
I2SIdx = pHalI2SInitData->I2SIdx;
for (i=0;i<4;i++) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(i<<2), 0);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(i<<2), 0);
}
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SDMACtrlRtl8195a(
IN VOID *Data
)
{
return _EXIT_SUCCESS;
}

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lib/fwlib/rtl8195a/src/rtl8195a_mii.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_mii.h"
#include "hal_mii.h"
VOID MiiIrqHandle (IN VOID *Data);
VOID MiiIrqHandle (IN VOID *Data) {
u32 RegValue = HalMiiGmacGetInterruptStatusRtl8195a();
#ifdef CONFIG_MII_VERIFY
extern volatile u8 isRxOK;
extern volatile u8 isTxOK;
extern volatile u8 RxIntCnt;
// DBG_8195A("ISR = 0x%08X\n", RegValue);
if(RegValue & GMAC_ISR_ROK) {
HalMiiGmacClearInterruptStatusRtl8195a(0x00410001);
isRxOK = 1;
RxIntCnt++;
}
if(RegValue & GMAC_ISR_TOK_TI) {
HalMiiGmacClearInterruptStatusRtl8195a(0x00410040);
isTxOK = 1;
}
#else
#endif
}
VOID
ConfigDebugPort_E4(u32 DebugSelect) {
u32 RegValue;
RegValue = HAL_MII_READ32(REG_RTL_MII_CCR);
RegValue |= DebugSelect << 2;
HAL_MII_WRITE32(REG_RTL_MII_CCR, RegValue);
}
/**
* MII Initialize.
*
* MII Initialize.
*
* Initialization Steps:
* I. Rtl8195A Board Configurations:
* 1. MII Function Enable & AHB mux
*
* @return runtime status value.
*/
BOOL
HalMiiGmacInitRtl8195a(
IN VOID *Data
)
{
u32 RegValue;
/* 1. enable MII Pinmux & disable SDIO Host/Device mode Pinmux */
RegValue = HAL_READ32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL);
RegValue |= BIT24;
RegValue &= ~(BIT0 | BIT1); // Important!
HAL_WRITE32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL, RegValue);
/* 2. enable MII IP block (214, 12) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN);
RegValue |= BIT12;
HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, RegValue);
/* 3. Lexra2AHB Function Enable (304, 11) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_SOC_CTRL);
RegValue |= BIT11;
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_SOC_CTRL, RegValue);
/* 4. enable MII bus clock (240, 24|25) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0);
RegValue |= (BIT24 | BIT25);
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0, RegValue);
/* 5. */
RegValue = HAL_READ32(SYSTEM_CTRL_BASE, 0x74) & 0xFFFFC7FF;
HAL_WRITE32(SYSTEM_CTRL_BASE, 0x74, (RegValue | 0x00003000));
/* 6. AHB mux: select MII (214, 13) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN);
RegValue |= BIT13;
HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, RegValue);
/* 7. Vendor Register Clock Enable (230, 6|7) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_CLK_CTRL);
RegValue |= (BIT6 | BIT7);
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_CLK_CTRL, RegValue);
/* 8. Enable GMAC Lexra Timeout (090, 16|17|18) */
RegValue = HAL_READ32(VENDOR_REG_BASE, 0x0090);
RegValue |= (BIT16 | BIT17 | BIT18);
HAL_WRITE32(VENDOR_REG_BASE, 0x0090, RegValue);
/* 9. Endian Swap Control (304, 12|13) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_SOC_CTRL);
RegValue |= (BIT12 | BIT13);
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_SOC_CTRL, RegValue);
return _TRUE;
}
BOOL
HalMiiInitRtl8195a(
IN VOID *Data
)
{
return _TRUE;
}
BOOL
HalMiiGmacResetRtl8195a(
IN VOID *Data
)
{
HAL_MII_WRITE32(REG_RTL_MII_CR, (HAL_MII_READ32(REG_RTL_MII_CR) | BIT0));
return _TRUE;
}
BOOL
HalMiiGmacEnablePhyModeRtl8195a(
IN VOID *Data
)
{
return _TRUE;
}
u32
HalMiiGmacXmitRtl8195a(
IN VOID *Data
)
{
return 0;
}
VOID
HalMiiGmacCleanTxRingRtl8195a(
IN VOID *Data
)
{
}
VOID
HalMiiGmacFillTxInfoRtl8195a(
IN VOID *Data
)
{
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
PTX_INFO pTx_Info = pMiiAdapter->pTx_Info;
VOID* TxBuffer = pMiiAdapter->TxBuffer;
pTx_Info->opts1.dw = 0xBC8001FE;
/* pTx_Info->opts1.dw = 0xBC800080; // size: 128 */
pTx_Info->addr = (u32)TxBuffer;
pTx_Info->opts2.dw = 0x0400279F;
pTx_Info->opts3.dw = 0x00000000;
/* pTx_Info->opts4.dw = 0x57800000; */
pTx_Info->opts4.dw = 0x1FE00000;
HAL_MII_WRITE32(REG_RTL_MII_TXFDP1, pTx_Info);
}
VOID
HalMiiGmacFillRxInfoRtl8195a(
IN VOID *Data
)
{
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
PRX_INFO pRx_Info = pMiiAdapter->pRx_Info;
VOID* RxBuffer = pMiiAdapter->RxBuffer;
/* pRx_Info->opts1.dw = 0x80000200; //Data Length: 4095(FFF), 512(200) */
pRx_Info->opts1.dw = 0x800001FC; //Data Length: 4095(FFF), 512(200)
/* pRx_Info->opts1.dw = 0x8000007F; */
pRx_Info->addr = (u32)RxBuffer;
pRx_Info->opts2.dw = 0x00000000;
pRx_Info->opts3.dw = 0x00000000;
HAL_MII_WRITE32(REG_RTL_MII_RXFDP1, pRx_Info);
}
VOID
HalMiiGmacTxRtl8195a(
IN VOID *Data
)
{
u32 RegValue;
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
RegValue |= BIT_IOCMD_TXENABLE(1);
HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue);
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
RegValue |= BIT_IOCMD_FIRST_DMATX_ENABLE(1);
HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue);
}
VOID
HalMiiGmacRxRtl8195a(
IN VOID *Data
)
{
u32 RegValue;
RegValue = HAL_MII_READ32(REG_RTL_MII_TCR);
HAL_MII_WRITE32(REG_RTL_MII_TCR, 0x00000D00); // loopback R2T mode
RegValue = HAL_MII_READ32(REG_RTL_MII_RCR);
HAL_MII_WRITE32(REG_RTL_MII_RCR, 0x0000007F);
RegValue = HAL_MII_READ32(REG_RTL_MII_ETNRXCPU1);
HAL_MII_WRITE32(REG_RTL_MII_ETNRXCPU1, 0x1F0A0F00);
RegValue = HAL_MII_READ32(REG_RTL_MII_RX_PSE1);
HAL_MII_WRITE32(REG_RTL_MII_RX_PSE1, 0x00000022);
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1);
RegValue |= BIT_IOCMD1_FIRST_DMARX_ENABLE(1);
HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, RegValue);
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
RegValue |= BIT_IOCMD_RXENABLE(1);
HAL_MII_WRITE32(REG_RTL_MII_IOCMD, RegValue);
}
VOID
HalMiiGmacSetDefaultEthIoCmdRtl8195a(
IN VOID *Data
)
{
u32 RegValue;
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD);
HAL_MII_WRITE32(REG_RTL_MII_IOCMD, CMD_CONFIG);
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1);
HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, CMD1_CONFIG);
//2014-04-29 yclin (disable 0x40051438[27] r_en_precise_dma) {
RegValue = HAL_MII_READ32(REG_RTL_MII_IOCMD1);
RegValue = RegValue & 0xF7FFFFFF;
HAL_MII_WRITE32(REG_RTL_MII_IOCMD1, RegValue);
// }
}
VOID
HalMiiGmacInitIrqRtl8195a(
IN VOID *Data
)
{
IRQ_HANDLE MiiIrqHandle_Master;
PMII_ADAPTER pMiiAdapter = (PMII_ADAPTER) Data;
MiiIrqHandle_Master.Data = (u32) (pMiiAdapter);
MiiIrqHandle_Master.IrqNum = GMAC_IRQ;
MiiIrqHandle_Master.IrqFun = (IRQ_FUN) MiiIrqHandle;
MiiIrqHandle_Master.Priority = 0;
InterruptRegister(&MiiIrqHandle_Master);
InterruptEn(&MiiIrqHandle_Master);
}
u32
HalMiiGmacGetInterruptStatusRtl8195a(
VOID
)
{
u32 RegValue;
RegValue = HAL_MII_READ32(REG_RTL_MII_IMRISR);
return RegValue;
}
VOID
HalMiiGmacClearInterruptStatusRtl8195a(
u32 IsrStatus
)
{
HAL_MII_WRITE32(REG_RTL_MII_IMRISR, IsrStatus);
}

1921
lib/fwlib/rtl8195a/src/rtl8195a_nfc.c Normal file
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360
lib/fwlib/rtl8195a/src/rtl8195a_pcm.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "platform_autoconf.h"
#include "diag.h"
#include "rtl8195a_pcm.h"
#include "hal_pcm.h"
extern void *
_memset( void *s, int c, SIZE_T n );
VOID
HalPcmOnOffRtl8195a (
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
//todo on off pcm
}
//default sampling rate 8khz, linear, 10ms frame size, time slot 0 , tx+rx
// master mode, enable endian swap
// Question: need local tx/rx page?
BOOL
HalPcmInitRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
_memset((void *)pHalPcmAdapter, 0, sizeof(HAL_PCM_ADAPTER));
//4 1) Initial PcmChCNR03 Register
pHalPcmAdapter->PcmChCNR03.CH0MuA = 0;
pHalPcmAdapter->PcmChCNR03.CH0Band = 0;
//4 1) Initial PcmTSR03 Register
pHalPcmAdapter->PcmTSR03.CH0TSA = 0;
//4 1) Initial PcmBSize03 Register
pHalPcmAdapter->PcmBSize03.CH0BSize = 39; // 40word= 8khz*0.01s*1ch*2byte/4byte
//4 2) Initial Ctl Register
pHalPcmAdapter->PcmCtl.Pcm_En = 1;
pHalPcmAdapter->PcmCtl.SlaveMode = 0;
pHalPcmAdapter->PcmCtl.FsInv = 0;
pHalPcmAdapter->PcmCtl.LinearMode = 0;
pHalPcmAdapter->PcmCtl.LoopBack = 0;
pHalPcmAdapter->PcmCtl.EndianSwap = 1;
return _TRUE;
}
BOOL
HalPcmSettingRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegCtl, RegChCNR03, RegTSR03, RegBSize03;
u32 Isr03;
PcmCh=0;
//4 1) Check Pcm index is avaliable
if (HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03) & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
//4 2) Check if there are the pending isr
Isr03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_ISR03);
Isr03 &= 0xff000000;
//4 Clear Pending Isr
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_ISR03, Isr03);
//}
//4 3) Process RegCtl
RegCtl = HAL_PCMX_READ32(PcmIndex, REG_PCM_CTL);
//4 Clear Ctl register bits
RegCtl &= ( BIT_INV_CTLX_SLAVE_SEL &
BIT_INV_CTLX_FSINV &
BIT_INV_CTLX_PCM_EN &
BIT_INV_CTLX_LINEARMODE &
BIT_INV_CTLX_LOOP_BACK &
BIT_INV_CTLX_ENDIAN_SWAP);
RegCtl = BIT_CTLX_SLAVE_SEL(pHalPcmAdapter->PcmCtl.SlaveMode) |
BIT_CTLX_FSINV(pHalPcmAdapter->PcmCtl.FsInv) |
BIT_CTLX_PCM_EN(pHalPcmAdapter->PcmCtl.Pcm_En) |
BIT_CTLX_LINEARMODE(pHalPcmAdapter->PcmCtl.LinearMode) |
BIT_CTLX_LOOP_BACK(pHalPcmAdapter->PcmCtl.LoopBack) |
BIT_CTLX_ENDIAN_SWAP(pHalPcmAdapter->PcmCtl.EndianSwap) |
RegCtl;
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CTL, RegCtl);
//4 4) Program ChCNR03 Register
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
RegChCNR03 &= (BIT_INV_CHCNR03_CH0RE &
BIT_INV_CHCNR03_CH0TE &
BIT_INV_CHCNR03_CH0MUA &
BIT_INV_CHCNR03_CH0BAND);
RegChCNR03 = BIT_CHCNR03_CH0RE(pHalPcmAdapter->PcmChCNR03.CH0RE) |
BIT_CHCNR03_CH0TE(pHalPcmAdapter->PcmChCNR03.CH0TE) |
BIT_CHCNR03_CH0MUA(pHalPcmAdapter->PcmChCNR03.CH0MuA) |
BIT_CHCNR03_CH0BAND(pHalPcmAdapter->PcmChCNR03.CH0Band) |
RegChCNR03;
DBG_8195A_DMA("RegChCNR03 data:0x%x\n", RegChCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03);
// time slot
RegTSR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_TSR03);
RegTSR03 &= (BIT_INV_TSR03_CH0TSA);
RegTSR03 = BIT_TSR03_CH0TSA(pHalPcmAdapter->PcmTSR03.CH0TSA) |
RegTSR03;
DBG_8195A_DMA("RegTSR03 data:0x%x\n", RegTSR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_TSR03, RegTSR03);
// buffer size
RegBSize03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_BSIZE03);
RegBSize03 &= (BIT_INV_BSIZE03_CH0BSIZE);
RegBSize03 = BIT_BSIZE03_CH0BSIZE(pHalPcmAdapter->PcmBSize03.CH0BSize) |
RegBSize03;
DBG_8195A_DMA("RegBSize03 data:0x%x\n", RegBSize03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_BSIZE03, RegBSize03);
return _TRUE;
}
BOOL
HalPcmEnRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 1;
//4 1) Check Pcm index is avaliable
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
if (RegChCNR03 & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03|BIT24|BIT25);
pHalPcmAdapter->PcmChCNR03.CH0RE = 1;
pHalPcmAdapter->PcmChCNR03.CH0TE = 1;
return _TRUE;
}
BOOL
HalPcmDisRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 0;
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03&(~(BIT24|BIT25)));
pHalPcmAdapter->PcmChCNR03.CH0RE = 0;
pHalPcmAdapter->PcmChCNR03.CH0TE = 0;
return _TRUE;
}
BOOL
HalPcmIsrEnAndDisRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrMask, Addr, IsrCtrl;
u8 IsrTypeIndex = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
Addr = (REG_GDMA_MASK_INT_BASE + IsrTypeIndex*8);
IsrMask = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, Addr);
IsrCtrl = ((pHalGdmaAdapter->IsrCtrl)?(pHalGdmaAdapter->ChEn | IsrMask):
((~pHalGdmaAdapter->ChEn) & IsrMask));
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
Addr,
IsrCtrl
);
}
}
*/
return _TRUE;
}
BOOL
HalPcmDumpRegRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)|
(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
BOOL
HalPcmRtl8195a (
IN VOID *Data
)
{
/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)&
~(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
/*
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrStatus;
u8 IsrTypeIndex = 0, IsrActBitMap = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
IsrStatus = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_RAW_INT_BASE + IsrTypeIndex*8));
// DBG_8195A_DMA("Isr Type %d: Isr Status 0x%x\n", IsrTypeIndex, IsrStatus);
IsrStatus = (IsrStatus & (pHalGdmaAdapter->ChEn & 0xFF));
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE+ (IsrTypeIndex*8)),
(IsrStatus)// & (pHalGdmaAdapter->ChEn & 0xFF))
);
IsrActBitMap |= BIT_(IsrTypeIndex);
}
}
return IsrActBitMap;
}
VOID
HalGdmaChCleanAutoSrcRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_SRC;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
VOID
HalGdmaChCleanAutoDstRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_DST;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
*/

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "hal_peri_on.h"
#ifdef CONFIG_PWM_EN
#include "rtl8195a_pwm.h"
#include "hal_pwm.h"
extern HAL_PWM_ADAPTER PWMPin[];
extern HAL_TIMER_OP HalTimerOp;
/**
* @brief Configure a G-Timer to generate a tick with certain time.
*
* @param pwm_id: the PWM pin index
* @param tick_time: the time (micro-second) of a tick
*
* @retval None
*/
void
Pwm_SetTimerTick_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 tick_time
)
{
TIMER_ADAPTER TimerAdapter;
if (tick_time <= MIN_GTIMER_TIMEOUT) {
tick_time = MIN_GTIMER_TIMEOUT;
}
else {
tick_time = (((tick_time-1)/TIMER_TICK_US)+1) * TIMER_TICK_US;
}
// Initial a G-Timer for the PWM pin
if (pPwmAdapt->tick_time != tick_time) {
TimerAdapter.IrqDis = 1; // Disable Irq
TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) NULL;
TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ;
TimerAdapter.IrqHandle.Priority = 0;
TimerAdapter.IrqHandle.Data = (u32)NULL;
TimerAdapter.TimerId = pPwmAdapt->gtimer_id;
TimerAdapter.TimerIrqPriority = 0;
TimerAdapter.TimerLoadValueUs = tick_time-1;
TimerAdapter.TimerMode = 1; // auto-reload with user defined value
HalTimerOp.HalTimerInit((VOID*) &TimerAdapter);
pPwmAdapt->tick_time = tick_time;
DBG_PWM_INFO("%s: Timer_Id=%d Count=%d\n", __FUNCTION__, pPwmAdapt->gtimer_id, tick_time);
}
}
/**
* @brief Set the duty ratio of the PWM pin.
*
* @param pwm_id: the PWM pin index
* @param period: the period time, in micro-second.
* @param pulse_width: the pulse width time, in micro-second.
*
* @retval None
*/
void
HAL_Pwm_SetDuty_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
)
{
u32 RegAddr;
u32 RegValue;
u32 period_tick;
u32 pulsewidth_tick;
u32 tick_time;
u8 timer_id;
u8 pwm_id;
pwm_id = pPwmAdapt->pwm_id;
// Adjust the tick time to a proper value
if (period < (MIN_GTIMER_TIMEOUT*2)) {
DBG_PWM_ERR ("HAL_Pwm_SetDuty_8195a: Invalid PWM period(%d), too short!!\n", period);
tick_time = MIN_GTIMER_TIMEOUT;
period = MIN_GTIMER_TIMEOUT*2;
}
else {
tick_time = period / 0x3fc;
if (tick_time < MIN_GTIMER_TIMEOUT) {
tick_time = MIN_GTIMER_TIMEOUT;
}
}
Pwm_SetTimerTick_8195a(pPwmAdapt, tick_time);
tick_time = pPwmAdapt->tick_time;
#if 0
// Check if current tick time needs adjustment
if ((pPwmAdapt->tick_time << 12) <= period) {
// need a longger tick time
}
else if ((pPwmAdapt->tick_time >> 2) >= period) {
// need a shorter tick time
}
#endif
period_tick = period/tick_time;
if (period_tick == 0) {
period_tick = 1;
}
if (pulse_width >= period) {
// pulse_width = period-1;
pulse_width = period;
}
pulsewidth_tick = pulse_width/tick_time;
if (pulsewidth_tick == 0) {
// pulsewidth_tick = 1;
}
timer_id = pPwmAdapt->gtimer_id;
pPwmAdapt->period = period_tick & 0x3ff;
pPwmAdapt->pulsewidth = pulsewidth_tick & 0x3ff;
RegAddr = REG_PERI_PWM0_CTRL + (pwm_id*4);
RegValue = BIT31 | (timer_id<<24) | (pulsewidth_tick<<12) | period_tick;
HAL_WRITE32(PERI_ON_BASE, RegAddr, RegValue);
}
/**
* @brief Initializes and enable a PWM control pin.
*
* @param pwm_id: the PWM pin index
* @param sel: pin mux selection
* @param timer_id: the G-timer index assigned to this PWM
*
* @retval HAL_Status
*/
HAL_Status
HAL_Pwm_Init_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
)
{
u32 pwm_id;
u32 pin_sel;
pwm_id = pPwmAdapt->pwm_id;
pin_sel = pPwmAdapt->sel;
// Initial a G-Timer for the PWM pin
Pwm_SetTimerTick_8195a(pPwmAdapt, MIN_GTIMER_TIMEOUT);
// Set default duty ration
HAL_Pwm_SetDuty_8195a(pPwmAdapt, 20000, 10000);
// Configure the Pin Mux
PinCtrl((PWM0+pwm_id), pin_sel, 1);
return HAL_OK;
}
/**
* @brief Enable a PWM control pin.
*
* @param pwm_id: the PWM pin index
*
* @retval None
*/
void
HAL_Pwm_Enable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
)
{
u32 pwm_id;
pwm_id = pPwmAdapt->pwm_id;
// Configure the Pin Mux
if (!pPwmAdapt->enable) {
PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 1);
HalTimerOp.HalTimerEn(pPwmAdapt->gtimer_id);
pPwmAdapt->enable = 1;
}
}
/**
* @brief Disable a PWM control pin.
*
* @param pwm_id: the PWM pin index
*
* @retval None
*/
void
HAL_Pwm_Disable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
)
{
u32 pwm_id;
pwm_id = pPwmAdapt->pwm_id;
// Configure the Pin Mux
if (pPwmAdapt->enable) {
PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 0);
HalTimerOp.HalTimerDis(pPwmAdapt->gtimer_id);
pPwmAdapt->enable = 0;
}
}
#endif //CONFIG_PWM_EN

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_timer.h"
extern u32 gTimerRecord;
extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM];
#ifdef CONFIG_CHIP_A_CUT
HAL_RAM_BSS_SECTION u32 gTimerRecord;
#endif
#ifdef CONFIG_CHIP_C_CUT
extern u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#else
u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#endif
VOID
HalTimerIrq2To7Handle_Patch(
IN VOID *Data
)
{
u32 TimerIrqStatus = 0, CheckIndex;
IRQ_FUN pHandler;
TimerIrqStatus = HAL_TIMER_READ32(TIMERS_INT_STATUS_OFF);
DBG_TIMER_INFO("%s:TimerIrqStatus: 0x%x\n",__FUNCTION__, TimerIrqStatus);
for (CheckIndex = 2; CheckIndex<8; CheckIndex++) {
//3 Check IRQ status bit and Timer X IRQ enable bit
if ((TimerIrqStatus & BIT_(CheckIndex)) &&
(HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_CTL_REG_OFF) & BIT0)) {
//3 Execute Timer callback function
pHandler = Timer2To7VectorTable[CheckIndex-2];
if (pHandler != NULL) {
pHandler((void*)Timer2To7HandlerData[CheckIndex-2]);
}
//3 Clear Timer ISR
HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_EOI_OFF);
}
}
}
HAL_Status
HalTimerIrqRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
IRQ_HANDLE TimerIrqHandle;
//IRQ_FUN BackUpIrqFun = NULL;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s: No Support Timer ID %d!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
TimerIrqHandle.IrqNum = TIMER2_7_IRQ;
TimerIrqHandle.IrqFun = (IRQ_FUN) HalTimerIrq2To7Handle_Patch;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] =
(IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
Timer2To7HandlerData[pHalTimerAdap->TimerId-2] =
(uint32_t) pHalTimerAdap->IrqHandle.Data;
}
else {
TimerIrqHandle.IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
TimerIrqHandle.IrqFun = (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
}
TimerIrqHandle.Data = (u32)pHalTimerAdap;
InterruptRegister(&TimerIrqHandle);
}
return HAL_OK;
}
#ifndef CONFIG_CHIP_C_CUT
// Patch for A/B Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
u32 ControlReg;
if ((gTimerRecord & (1<<pHalTimerAdap->TimerId)) != 0) {
DBG_TIMER_ERR ("%s:Error! Timer %d is occupied!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_BUSY;
}
//4 1) Config Timer Setting
ControlReg = ((u32)pHalTimerAdap->TimerMode<<1)|((u32)pHalTimerAdap->IrqDis<<2);
/*
set TimerControlReg
0: Timer enable (0,disable; 1,enable)
1: Timer Mode (0, free-running mode; 1, user-defined count mode)
2: Timer Interrupt Mask (0, not masked; 1,masked)
*/
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
ControlReg);
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
else {
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_LOAD_COUNT_OFF),
0xFFFFFFFF);
}
//4 2) Setting Timer IRQ
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
//4 2.1) Initial TimerIRQHandle
ret = HalTimerIrqRegisterRtl8195a_Patch(pHalTimerAdap);
if (HAL_OK != ret) {
DBG_TIMER_ERR ("%s: Timer %d Register IRQ Err!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return ret;
}
//4 2.2) Enable TimerIRQ for Platform
InterruptEn((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
}
else {
DBG_TIMER_ERR ("%s: Timer %d ISR Handler is NULL!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
}
//4 4) Enable Timer
// HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
// (ControlReg|0x1));
gTimerRecord |= (1<<pHalTimerAdap->TimerId);
return ret;
}
#else
// Patch for C Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
ret = HalTimerInitRtl8195aV02(Data);
// Patch the Rom code to load the correct count value
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
return ret;
}
#endif
HAL_Status
HalTimerIrqUnRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
PIRQ_HANDLE pTimerIrqHandle;
u32 i;
pTimerIrqHandle = &pHalTimerAdap->IrqHandle;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s:Error: No Support Timer ID!\n", __FUNCTION__);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
pTimerIrqHandle->IrqNum = TIMER2_7_IRQ;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = NULL;
for (i=0;i<MAX_TIMER_VECTOR_TABLE_NUM;i++) {
if (Timer2To7VectorTable[i] != NULL) {
break;
}
}
if (i == MAX_TIMER_VECTOR_TABLE_NUM) {
// All timer UnRegister Interrupt
InterruptDis((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
InterruptUnRegister(pTimerIrqHandle);
}
}
else {
pTimerIrqHandle->IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
InterruptUnRegister(pTimerIrqHandle);
}
}
return HAL_OK;
}
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
u32 timer_id;
timer_id = pHalTimerAdap->TimerId;
HalTimerDisRtl8195a (timer_id);
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
HalTimerIrqUnRegisterRtl8195a_Patch(pHalTimerAdap);
}
}
gTimerRecord &= ~(1<<pHalTimerAdap->TimerId);
}
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
)
{
u32 LoadCount = 0;
u32 ms125; // how many 125ms
u32 remain_us;
ms125 = LoadUs/125000;
remain_us = LoadUs - (ms125*125000);
LoadCount = ms125 * (GTIMER_CLK_HZ/8);
LoadCount += (remain_us*GTIMER_CLK_HZ)/1000000;
if (LoadCount == 0) {
LoadCount = 1;
}
// DBG_TIMER_INFO("%s: Load Count=0x%x\r\n", __FUNCTION__, LoadCount);
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_LOAD_COUNT_OFF),
LoadCount);
}
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
)
{
u32 TimerCountOld;
u32 TimerCountNew;
u32 TimerRDCnt;
TimerRDCnt = 0;
TimerCountOld = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
while(1) {
TimerCountNew = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
if (TimerCountOld == TimerCountNew) {
return (u32)TimerCountOld;
}
else {
TimerRDCnt++;
TimerCountOld = TimerCountNew;
if (TimerRDCnt >= 2){
return (u32)TimerCountOld;
}
}
}
}
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~(BIT2)));
}
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT2));
}
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT0));
}
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
)
{
// Disable Timer will alos disable the IRQ, so need to re-enable the IRQ when re-enable the timer
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~BIT0));
}

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_USB_H_
#define _RTL8195A_USB_H_
// common command for USB
#define USB_CMD_TX_ETH 0x83 // request to TX a 802.3 packet
#define USB_CMD_TX_WLN 0x81 // request to TX a 802.11 packet
#define USB_CMD_H2C 0x11 // H2C(host to device) command packet
#define USB_CMD_MEMRD 0x51 // request to read a block of memory data
#define USB_CMD_MEMWR 0x53 // request to write a block of memory
#define USB_CMD_MEMST 0x55 // request to set a block of memory with a value
#define USB_CMD_STARTUP 0x61 // request to jump to the start up function
#define USB_CMD_RX_ETH 0x82 // indicate a RX 802.3 packet
#define USB_CMD_RX_WLN 0x80 // indicate a RX 802.11 packet
#define USB_CMD_C2H 0x10 // C2H(device to host) command packet
#define USB_CMD_MEMRD_RSP 0x50 // response to memory block read command
#define USB_CMD_MEMWR_RSP 0x52 // response to memory write command
#define USB_CMD_MEMST_RSP 0x54 // response to memory set command
#define USB_CMD_STARTED 0x60 // indicate the program has jumped to the given function
// TODO: This data structer just for test, we should modify it for the normal driver
typedef struct _USB_TX_DESC{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 rsvd0:24;
#else
u32 rsvd0:24;
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 rsvd1;
// u4Byte 3
u32 rsvd2;
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} USB_TX_DESC, *PUSB_TX_DESC;
#define SIZE_USB_TX_DESC sizeof(USB_TX_DESC)
// TODO: This data structer just for test, we should modify it for the normal driver
typedef struct _USB_RX_DESC{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:6; // bit[29:24]
u32 icv:1; // bit[30], ICV error
u32 crc:1; // bit[31], CRC error
#else
u32 crc:1; // bit[31], CRC error
u32 icv:1; // bit[30], ICV error
u32 rsvd0:6; // bit[29:24]
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 pkt_len:16; // bit[15:0], the packet size
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
#else
u32 rsvd1:24; // bit[31:8]
u32 type:8; // bit[7:0], the type of this packet
#endif
// u4Byte 2
u32 rsvd2;
// u4Byte 3
u32 rsvd3;
// u4Byte 4
u32 rsvd4;
// u4Byte 5
u32 rsvd5;
} USB_RX_DESC, *PUSB_RX_DESC;
#define SIZE_USB_RX_DESC sizeof(USB_RX_DESC)
#endif // #ifndef _RTL8195A_USB_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#ifdef CONFIG_TIMER_MODULE
VOID
En32KCalibration(
VOID
)
{
u32 Rtemp;
u32 Ttemp = 0;
//DiagPrintf("32K clock source calibration\n");
//set parameter
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
//offset 1 = 0x1500
Rtemp = 0x811500;
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
HalDelayUs(40);
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
//offset 2 = 0x01c0
Rtemp = 0x8201c0;
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
HalDelayUs(40);
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
//offset 4 = 0x0100
Rtemp = 0x840100;
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
HalDelayUs(40);
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
//offset 0 = 0xf980
Rtemp = 0x80f980;
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
HalDelayUs(40);
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
while(1) {
//Polling LOCK
Rtemp = 0x110000;
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, Rtemp);
//DiagPrintf("Polling lock\n");
HalDelayUs(40);
Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL1);
if ((Rtemp & 0x3000) != 0x0){
//DiagPrintf("32.768 Calibration Success\n", Ttemp);
break;
}
else {
Ttemp++;
HalDelayUs(30);
//DiagPrintf("Check lock: %d\n", Ttemp);
//DiagPrintf("0x278: %x\n", Rtemp);
if (Ttemp > 100000) { /*Delay 100ms*/
DiagPrintf("32K Calibration Fail!!\n", Ttemp);
break;
}
}
}
}
#if CONFIG_WDG
WDG_ADAPTER WDGAdapter;
extern HAL_TIMER_OP HalTimerOp;
#ifdef CONFIG_WDG_NORMAL
VOID
WDGInitial(
IN u32 Period
)
{
u8 CountId;
u16 DivFactor;
u32 CountTemp;
u32 CountProcess = 0;
u32 DivFacProcess = 0;
u32 PeriodProcess = 100*Period;
u32 MinPeriodTemp = 0xFFFFFFFF;
u32 PeriodTemp = 0;
u32 *Reg = (u32*)&(WDGAdapter.Ctrl);
DBG_8195A(" Period = 0x%08x\n", Period);
for (CountId = 0; CountId < 12; CountId++) {
CountTemp = ((0x00000001 << (CountId+1))-1);
DivFactor = (u16)((PeriodProcess)/(CountTemp*3));
if (DivFactor > 0) {
PeriodTemp = 3*(DivFactor+1)*CountTemp;
if (PeriodProcess < PeriodTemp) {
if (MinPeriodTemp > PeriodTemp) {
MinPeriodTemp = PeriodTemp;
CountProcess = CountId;
DivFacProcess = DivFactor;
}
}
}
}
DBG_8195A("WdgScalar = 0x%08x\n", DivFacProcess);
DBG_8195A("WdgCunLimit = 0x%08x\n", CountProcess);
WDGAdapter.Ctrl.WdgScalar = DivFacProcess;
WDGAdapter.Ctrl.WdgEnByte = 0;
WDGAdapter.Ctrl.WdgClear = 1;
WDGAdapter.Ctrl.WdgCunLimit = CountProcess;
WDGAdapter.Ctrl.WdgMode = RESET_MODE;
WDGAdapter.Ctrl.WdgToISR = 0;
HAL_WRITE32(VENDOR_REG_BASE, 0, (*Reg));
}
VOID
WDGIrqHandle
(
IN VOID *Data
)
{
u32 temp;
WDG_REG *CtrlReg;
if (NULL != WDGAdapter.UserCallback) {
WDGAdapter.UserCallback(WDGAdapter.callback_id);
}
// Clear ISR
temp = HAL_READ32(VENDOR_REG_BASE, 0);
CtrlReg = (WDG_REG*)&temp;
CtrlReg->WdgToISR = 1; // write 1 clear
HAL_WRITE32(VENDOR_REG_BASE, 0, (temp));
}
VOID
WDGIrqInitial(
VOID
)
{
u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
WDGAdapter.IrqHandle.Data = (u32)&WDGAdapter;
WDGAdapter.IrqHandle.IrqFun = (IRQ_FUN)WDGIrqHandle;
WDGAdapter.IrqHandle.IrqNum = WDG_IRQ;
WDGAdapter.IrqHandle.Priority = 0;
InterruptRegister(&(WDGAdapter.IrqHandle));
InterruptEn(&(WDGAdapter.IrqHandle));
WDGAdapter.Ctrl.WdgToISR = 1; // clear ISR first
WDGAdapter.Ctrl.WdgMode = INT_MODE;
HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
WDGAdapter.Ctrl.WdgToISR = 0;
}
VOID
WDGStart(
VOID
)
{
u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
WDGAdapter.Ctrl.WdgEnByte = 0xA5;
HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
}
VOID
WDGStop(
VOID
)
{
u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
WDGAdapter.Ctrl.WdgEnByte = 0;
HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
}
VOID
WDGRefresh(
VOID
)
{
u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
WDGAdapter.Ctrl.WdgClear = 1;
HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
}
VOID
WDGIrqCallBackReg(
IN VOID *CallBack,
IN u32 Id
)
{
WDGAdapter.UserCallback = (VOID (*)(u32))CallBack;
WDGAdapter.callback_id = Id;
}
#endif
#ifdef CONFIG_WDG_TEST
VOID
WDGIrqHandle
(
IN VOID *Data
)
{
}
VOID
WDGGtimerHandle
(
IN VOID *Data
)
{
u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
WDGAdapter.Ctrl.WdgClear = 1;
DBG_8195A("reset WDG\n");
if (HAL_READ32(SYSTEM_CTRL_BASE,REG_SYS_DSTBY_INFO2) == 0) {
HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
}
}
VOID
InitWDGIRQ(VOID)
{
u32 *Temp = (u32*)&(WDGAdapter.Ctrl);
WDGAdapter.Ctrl.WdgScalar = 0x96;
WDGAdapter.Ctrl.WdgEnByte = 0xA5;
WDGAdapter.Ctrl.WdgClear = 1;
WDGAdapter.Ctrl.WdgCunLimit = CNTFFFH;
WDGAdapter.Ctrl.WdgMode = RESET_MODE;
WDGAdapter.Ctrl.WdgToISR = 0;
if (WDGAdapter.Ctrl.WdgMode == INT_MODE) {
WDGAdapter.IrqHandle.Data = NULL;
WDGAdapter.IrqHandle.IrqFun = (IRQ_FUN)WDGIrqHandle;
WDGAdapter.IrqHandle.IrqNum = WDG_IRQ;
WDGAdapter.IrqHandle.Priority = 0;
InterruptRegister(&(WDGAdapter.IrqHandle));
InterruptEn(&(WDGAdapter.IrqHandle));
}
else {
WDGAdapter.WdgGTimer.TimerIrqPriority = 0;
WDGAdapter.WdgGTimer.TimerMode = USER_DEFINED;
WDGAdapter.WdgGTimer.IrqDis = OFF;
WDGAdapter.WdgGTimer.TimerId = 2;//
WDGAdapter.WdgGTimer.IrqHandle.IrqFun = (IRQ_FUN)WDGGtimerHandle;
WDGAdapter.WdgGTimer.IrqHandle.IrqNum = TIMER2_7_IRQ;
WDGAdapter.WdgGTimer.IrqHandle.Priority = 0;
WDGAdapter.WdgGTimer.IrqHandle.Data = NULL;
if ((WDGAdapter.Ctrl.WdgCunLimit == CNTFFFH)&&(WDGAdapter.Ctrl.WdgScalar >= 0x8429)){
WDGAdapter.WdgGTimer.TimerLoadValueUs = 0xFFFFFFFF - WDGTIMERELY;
}
else {
WDGAdapter.WdgGTimer.TimerLoadValueUs = (BIT0 << (WDGAdapter.Ctrl.WdgCunLimit+1))
*WDGAdapter.Ctrl.WdgScalar*TIMER_TICK_US - WDGTIMERELY;
}
HalTimerOp.HalTimerInit((VOID*) &(WDGAdapter.WdgGTimer));
}
//fill reg
HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));
}
//WDG
VOID HalWdgInit(
VOID
)
{
}
#endif //CONFIG_WDG_TEST
#endif //CONFIG_WDG
#endif //#ifdef CONFIG_TIMER_MODULE

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "hal_common.h"
extern HAL_TIMER_OP HalTimerOp;
HAL_Status
HalCommonInit(void){
#ifdef CONFIG_TIMER_MODULE
HalTimerOpInit_Patch((VOID*)(&HalTimerOp));
#endif
return HAL_OK;
}

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "hal_gdma.h"
#define MAX_GDMA_INDX 1
#define MAX_GDMA_CHNL 6
static u8 HalGdmaReg[MAX_GDMA_INDX+1];
const HAL_GDMA_CHNL GDMA_Chnl_Option[] = {
{0,0,GDMA0_CHANNEL0_IRQ,0},
{1,0,GDMA1_CHANNEL0_IRQ,0},
{0,1,GDMA0_CHANNEL1_IRQ,0},
{1,1,GDMA1_CHANNEL1_IRQ,0},
{0,2,GDMA0_CHANNEL2_IRQ,0},
{1,2,GDMA1_CHANNEL2_IRQ,0},
{0,3,GDMA0_CHANNEL3_IRQ,0},
{1,3,GDMA1_CHANNEL3_IRQ,0},
{0,4,GDMA0_CHANNEL4_IRQ,0},
{1,4,GDMA1_CHANNEL4_IRQ,0},
{0,5,GDMA0_CHANNEL5_IRQ,0},
{1,5,GDMA1_CHANNEL5_IRQ,0},
{0xff,0,0,0} // end
};
const HAL_GDMA_CHNL GDMA_Multi_Block_Chnl_Option[] = {
{0,4,GDMA0_CHANNEL4_IRQ,0},
{1,4,GDMA1_CHANNEL4_IRQ,0},
{0,5,GDMA0_CHANNEL5_IRQ,0},
{1,5,GDMA1_CHANNEL5_IRQ,0},
{0xff,0,0,0} // end
};
const u16 HalGdmaChnlEn[6] = {
GdmaCh0, GdmaCh1, GdmaCh2, GdmaCh3,
GdmaCh4, GdmaCh5
};
VOID HalGdmaOpInit(
IN VOID *Data
)
{
PHAL_GDMA_OP pHalGdmaOp = (PHAL_GDMA_OP) Data;
pHalGdmaOp->HalGdmaOnOff = HalGdmaOnOffRtl8195a;
pHalGdmaOp->HalGdamChInit = HalGdamChInitRtl8195a;
pHalGdmaOp->HalGdmaChDis = HalGdmaChDisRtl8195a;
pHalGdmaOp->HalGdmaChEn = HalGdmaChEnRtl8195a;
pHalGdmaOp->HalGdmaChSeting = HalGdmaChSetingRtl8195a;
#ifndef CONFIG_CHIP_E_CUT
pHalGdmaOp->HalGdmaChBlockSeting = HalGdmaChBlockSetingRtl8195a;
#else
pHalGdmaOp->HalGdmaChBlockSeting = HalGdmaChBlockSetingRtl8195a_V04;
#endif
pHalGdmaOp->HalGdmaChIsrEnAndDis = HalGdmaChIsrEnAndDisRtl8195a;
pHalGdmaOp->HalGdmaChIsrClean = HalGdmaChIsrCleanRtl8195a;
pHalGdmaOp->HalGdmaChCleanAutoSrc = HalGdmaChCleanAutoSrcRtl8195a;
pHalGdmaOp->HalGdmaChCleanAutoDst = HalGdmaChCleanAutoDstRtl8195a;
}
VOID HalGdmaOn(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
{
pHalGdmaAdapter->GdmaOnOff = ON;
HalGdmaOnOffRtl8195a((VOID*)pHalGdmaAdapter);
}
VOID HalGdmaOff(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
{
pHalGdmaAdapter->GdmaOnOff = OFF;
HalGdmaOnOffRtl8195a((VOID*)pHalGdmaAdapter);
}
BOOL HalGdmaChInit(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
{
return (HalGdamChInitRtl8195a((VOID*)pHalGdmaAdapter));
}
VOID HalGdmaChDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
{
HalGdmaChDisRtl8195a((VOID*)pHalGdmaAdapter);
}
VOID HalGdmaChEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
{
HalGdmaChEnRtl8195a((VOID*)pHalGdmaAdapter);
}
BOOL HalGdmaChSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
{
return (HalGdmaChSetingRtl8195a((VOID*)pHalGdmaAdapter));
}
BOOL HalGdmaChBlockSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
{
#ifndef CONFIG_CHIP_E_CUT
return (HalGdmaChBlockSetingRtl8195a((VOID*)pHalGdmaAdapter));
#else
return (HalGdmaChBlockSetingRtl8195a_V04((VOID*)pHalGdmaAdapter));
#endif
}
VOID HalGdmaChIsrEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
{
pHalGdmaAdapter->IsrCtrl = ENABLE;
HalGdmaChIsrEnAndDisRtl8195a((VOID*)pHalGdmaAdapter);
}
VOID HalGdmaChIsrDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
{
pHalGdmaAdapter->IsrCtrl = DISABLE;
HalGdmaChIsrEnAndDisRtl8195a((VOID*)pHalGdmaAdapter);
}
u8 HalGdmaChIsrClean(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
{
return (HalGdmaChIsrCleanRtl8195a((VOID*)pHalGdmaAdapter));
}
VOID HalGdmaChCleanAutoSrc(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
{
HalGdmaChCleanAutoSrcRtl8195a((VOID*)pHalGdmaAdapter);
}
VOID HalGdmaChCleanAutoDst(PHAL_GDMA_ADAPTER pHalGdmaAdapter)
{
HalGdmaChCleanAutoDstRtl8195a((VOID*)pHalGdmaAdapter);
}
HAL_Status HalGdmaChnlRegister (u8 GdmaIdx, u8 ChnlNum)
{
u32 mask;
if ((GdmaIdx > MAX_GDMA_INDX) || (ChnlNum > MAX_GDMA_CHNL)) {
// Invalid GDMA Index or Channel Number
return HAL_ERR_PARA;
}
mask = 1 << ChnlNum;
if ((HalGdmaReg[GdmaIdx] & mask) != 0) {
return HAL_BUSY;
}
else {
#if 1
if (HalGdmaReg[GdmaIdx] == 0) {
if (GdmaIdx == 0) {
ACTCK_GDMA0_CCTRL(ON);
GDMA0_FCTRL(ON);
}
else {
ACTCK_GDMA1_CCTRL(ON);
GDMA1_FCTRL(ON);
}
}
#endif
HalGdmaReg[GdmaIdx] |= mask;
return HAL_OK;
}
}
VOID HalGdmaChnlUnRegister (u8 GdmaIdx, u8 ChnlNum)
{
u32 mask;
if ((GdmaIdx > MAX_GDMA_INDX) || (ChnlNum > MAX_GDMA_CHNL)) {
// Invalid GDMA Index or Channel Number
return;
}
mask = 1 << ChnlNum;
HalGdmaReg[GdmaIdx] &= ~mask;
#if 1
if (HalGdmaReg[GdmaIdx] == 0) {
if (GdmaIdx == 0) {
ACTCK_GDMA0_CCTRL(OFF);
GDMA0_FCTRL(OFF);
}
else {
ACTCK_GDMA1_CCTRL(OFF);
GDMA1_FCTRL(OFF);
}
}
#endif
}
PHAL_GDMA_CHNL HalGdmaChnlAlloc (HAL_GDMA_CHNL *pChnlOption)
{
HAL_GDMA_CHNL *pgdma_chnl;
pgdma_chnl = pChnlOption;
if (pChnlOption == NULL) {
// Use default GDMA Channel Option table
pgdma_chnl = (HAL_GDMA_CHNL*)&GDMA_Chnl_Option[0];
}
else{
pgdma_chnl = (HAL_GDMA_CHNL*) pgdma_chnl;
}
while (pgdma_chnl->GdmaIndx <= MAX_GDMA_INDX) {
if (HalGdmaChnlRegister(pgdma_chnl->GdmaIndx, pgdma_chnl->GdmaChnl) == HAL_OK) {
// This GDMA Channel is available
break;
}
pgdma_chnl += 1;
}
if (pgdma_chnl->GdmaIndx > MAX_GDMA_INDX) {
pgdma_chnl = NULL;
}
return pgdma_chnl;
}
VOID HalGdmaChnlFree (HAL_GDMA_CHNL *pChnl)
{
IRQ_HANDLE IrqHandle;
IrqHandle.IrqNum = pChnl->IrqNum;
InterruptDis(&IrqHandle);
InterruptUnRegister(&IrqHandle);
HalGdmaChnlUnRegister(pChnl->GdmaIndx, pChnl->GdmaChnl);
}
VOID HalGdmaMemIrqHandler(VOID *pData)
{
PHAL_GDMA_OBJ pHalGdmaObj=(PHAL_GDMA_OBJ)pData;
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
PIRQ_HANDLE pGdmaIrqHandle;
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
// Clean Auto Reload Bit
HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter);
// Clear Pending ISR
HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
HalGdmaChDis((VOID*)(pHalGdmaAdapter));
pHalGdmaObj->Busy = 0;
if (pGdmaIrqHandle->IrqFun != NULL) {
pGdmaIrqHandle->IrqFun((VOID*)pGdmaIrqHandle->Data);
}
}
BOOL HalGdmaMemCpyAggrInit(PHAL_GDMA_OBJ pHalGdmaObj)
{
HAL_GDMA_CHNL *pgdma_chnl;
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
PIRQ_HANDLE pGdmaIrqHandle;
IRQ_HANDLE IrqHandle;
pgdma_chnl = HalGdmaChnlAlloc((PHAL_GDMA_CHNL) &GDMA_Multi_Block_Chnl_Option[0]); // get a whatever GDMA channel
if (NULL == pgdma_chnl) {
DBG_GDMA_ERR("%s: Cannot allocate a GDMA Channel\n", __FUNCTION__);
return _FALSE;
}
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
DBG_GDMA_INFO("%s: Use GDMA%d CH%d\n", __FUNCTION__, pgdma_chnl->GdmaIndx, pgdma_chnl->GdmaChnl);
_memset((void *)pHalGdmaAdapter, 0, sizeof(HAL_GDMA_ADAPTER));
pHalGdmaAdapter->GdmaCtl.TtFc = TTFCMemToMem;
pHalGdmaAdapter->GdmaCtl.Done = 1;
pHalGdmaAdapter->MuliBlockCunt = 0;
pHalGdmaAdapter->MaxMuliBlock = 1;
pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl;
pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx;
pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl;
pHalGdmaAdapter->GdmaIsrType = (TransferType|ErrType);
pHalGdmaAdapter->IsrCtrl = ENABLE;
pHalGdmaAdapter->GdmaOnOff = ON;
pHalGdmaAdapter->GdmaCtl.IntEn = 1;
pHalGdmaAdapter->Rsvd4to7 = 1;
pHalGdmaAdapter->Llpctrl = 1;
pGdmaIrqHandle->IrqNum = pgdma_chnl->IrqNum;
pGdmaIrqHandle->Priority = 0x10;
IrqHandle.IrqFun = (IRQ_FUN) HalGdmaMemIrqHandler;
IrqHandle.Data = (u32) pHalGdmaObj;
IrqHandle.IrqNum = pGdmaIrqHandle->IrqNum;
IrqHandle.Priority = pGdmaIrqHandle->Priority;
InterruptRegister(&IrqHandle);
InterruptEn(&IrqHandle);
pHalGdmaObj->Busy = 0;
return _TRUE;
}
VOID HalGdmaMultiBlockSetting(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
u8 BlockNumber;
u8 BlockIndex;
u8 FourBytesAlign;
BlockNumber = pHalGdmaObj->BlockNum;
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
pHalGdmaAdapter->GdmaCtl.LlpSrcEn = 1;
pHalGdmaAdapter->GdmaCtl.LlpDstEn = 1;
if(((pHalGdmaBlock[0].SrcAddr & 0x03) == 0) &&((pHalGdmaBlock[0].DstAddr & 0x03) == 0)
&& ((pHalGdmaBlock[0].BlockLength & 0X03) == 0)){
pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight;
pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes;
pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes;
FourBytesAlign = 1;
}
else{
pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight;
pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte;
pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte;
FourBytesAlign = 0;
}
for(BlockIndex = 0; BlockIndex < BlockNumber; BlockIndex++){
pHalGdmaObj->GdmaChLli[BlockIndex].Sarx = pHalGdmaBlock[BlockIndex].SrcAddr;
pHalGdmaObj->GdmaChLli[BlockIndex].Darx = pHalGdmaBlock[BlockIndex].DstAddr;
pHalGdmaObj->BlockSizeList[BlockIndex].pNextBlockSiz = &pHalGdmaObj->BlockSizeList[BlockIndex + 1];
if(FourBytesAlign){
pHalGdmaObj->BlockSizeList[BlockIndex].BlockSize = pHalGdmaBlock[BlockIndex].BlockLength >> 2;
}
else{
pHalGdmaObj->BlockSizeList[BlockIndex].BlockSize = pHalGdmaBlock[BlockIndex].BlockLength;
}
pHalGdmaObj->Lli[BlockIndex].pLliEle = (GDMA_CH_LLI_ELE*) &pHalGdmaObj->GdmaChLli[BlockIndex];
pHalGdmaObj->Lli[BlockIndex].pNextLli = &pHalGdmaObj->Lli[BlockIndex + 1];
if(BlockIndex == BlockNumber - 1){
pHalGdmaObj->BlockSizeList[BlockIndex].pNextBlockSiz = NULL;
pHalGdmaObj->Lli[BlockIndex].pNextLli = NULL;
}
//DBG_GDMA_INFO("Lli[%d].pLiEle = %x\r\n", BlockIndex,Lli[BlockIndex].pLliEle);
//DBG_GDMA_INFO("Lli[%d].pNextLli = %x\r\n", BlockIndex,Lli[BlockIndex].pNextLli);
}
pHalGdmaAdapter->pBlockSizeList = (struct BLOCK_SIZE_LIST*) &pHalGdmaObj->BlockSizeList;
pHalGdmaAdapter->pLlix = (struct GDMA_CH_LLI*) &pHalGdmaObj->Lli;
//DBG_GDMA_INFO("pHalGdmaAdapter->pBlockSizeList = %x\r\n", pHalGdmaAdapter->pBlockSizeList);
//DBG_GDMA_INFO("pHalGdmaAdapter->pLlix = %x\r\n", pHalGdmaAdapter->pLlix );
}
VOID HalGdmaLLPMemAlign(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pGdmaChLli;
struct BLOCK_SIZE_LIST *pGdmaChBkLi;
u32 CtlxLow;
u32 CtlxUp;
u8 BlockNumber;
u8 BlockIndex;
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
BlockNumber = pHalGdmaObj->BlockNum;
pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
//4 Move to the second block to configure Memory Alginment setting
pLliEle->Llpx = (u32) pGdmaChLli->pLliEle;
pGdmaChBkLi = pGdmaChBkLi ->pNextBlockSiz;
for(BlockIndex = 1; BlockIndex < BlockNumber; BlockIndex++){
pLliEle = pGdmaChLli->pLliEle;
CtlxLow = pLliEle->CtlxLow;
CtlxLow &= (BIT_INVC_CTLX_LO_DST_TR_WIDTH & BIT_INVC_CTLX_LO_SRC_TR_WIDTH);
CtlxUp = pLliEle->CtlxUp;
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
if(((pHalGdmaBlock[BlockIndex].SrcAddr & 0x03) == 0) &&((pHalGdmaBlock[BlockIndex].DstAddr & 0x03) == 0)
&& ((pHalGdmaBlock[BlockIndex].BlockLength & 0X03) == 0)){
pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes;
pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes;
pGdmaChBkLi->BlockSize = pHalGdmaBlock[BlockIndex].BlockLength>> 2;
}
else{
pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte;
pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte;
pGdmaChBkLi->BlockSize = pHalGdmaBlock[BlockIndex].BlockLength;
}
CtlxLow |= (BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth));
CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
pGdmaChLli = pGdmaChLli->pNextLli;
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle);
}
}
VOID HalGdmaMemAggr(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
u8 BlockNumber;
BlockNumber = pHalGdmaObj->BlockNum;
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
if (pHalGdmaObj->Busy) {
DBG_GDMA_ERR("%s: ==> GDMA is Busy\r\n", __FUNCTION__);
return;
}
pHalGdmaObj->Busy = 1;
pHalGdmaAdapter->MaxMuliBlock = BlockNumber;
pHalGdmaAdapter->ChSar = pHalGdmaBlock[0].SrcAddr;
pHalGdmaAdapter->ChDar = pHalGdmaBlock[0].DstAddr;
HalGdmaMultiBlockSetting(pHalGdmaObj, pHalGdmaBlock);
HalGdmaOn((pHalGdmaAdapter));
HalGdmaChIsrEn((pHalGdmaAdapter));
HalGdmaChBlockSeting((pHalGdmaAdapter));
HalGdmaLLPMemAlign(pHalGdmaObj, pHalGdmaBlock);
HalGdmaChEn((pHalGdmaAdapter));
}
BOOL HalGdmaMemCpyInit(PHAL_GDMA_OBJ pHalGdmaObj)
{
HAL_GDMA_CHNL *pgdma_chnl;
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
PIRQ_HANDLE pGdmaIrqHandle;
IRQ_HANDLE IrqHandle;
pgdma_chnl = HalGdmaChnlAlloc(NULL); // get a whatever GDMA channel
if (NULL == pgdma_chnl) {
DBG_GDMA_ERR("%s: Cannot allocate a GDMA Channel\n", __FUNCTION__);
return _FALSE;
}
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
DBG_GDMA_INFO("%s: Use GDMA%d CH%d\n", __FUNCTION__, pgdma_chnl->GdmaIndx, pgdma_chnl->GdmaChnl);
#if 0
if (pgdma_chnl->GdmaIndx == 0) {
ACTCK_GDMA0_CCTRL(ON);
GDMA0_FCTRL(ON);
}
else if (pgdma_chnl->GdmaIndx == 1) {
ACTCK_GDMA1_CCTRL(ON);
GDMA1_FCTRL(ON);
}
#endif
_memset((void *)pHalGdmaAdapter, 0, sizeof(HAL_GDMA_ADAPTER));
// pHalGdmaAdapter->GdmaCtl.TtFc = TTFCMemToMem;
pHalGdmaAdapter->GdmaCtl.Done = 1;
// pHalGdmaAdapter->MuliBlockCunt = 0;
// pHalGdmaAdapter->MaxMuliBlock = 1;
pHalGdmaAdapter->ChNum = pgdma_chnl->GdmaChnl;
pHalGdmaAdapter->GdmaIndex = pgdma_chnl->GdmaIndx;
pHalGdmaAdapter->ChEn = 0x0101 << pgdma_chnl->GdmaChnl;
pHalGdmaAdapter->GdmaIsrType = (TransferType|ErrType);
pHalGdmaAdapter->IsrCtrl = ENABLE;
pHalGdmaAdapter->GdmaOnOff = ON;
pHalGdmaAdapter->GdmaCtl.IntEn = 1;
// pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight;
// pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
// pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes;
// pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes;
// pHalGdmaAdapter->GdmaCtl.Dinc = IncType;
// pHalGdmaAdapter->GdmaCtl.Sinc = IncType;
pGdmaIrqHandle->IrqNum = pgdma_chnl->IrqNum;
pGdmaIrqHandle->Priority = 10;
IrqHandle.IrqFun = (IRQ_FUN) HalGdmaMemIrqHandler;
IrqHandle.Data = (u32) pHalGdmaObj;
IrqHandle.IrqNum = pGdmaIrqHandle->IrqNum;
IrqHandle.Priority = pGdmaIrqHandle->Priority;
InterruptRegister(&IrqHandle);
InterruptEn(&IrqHandle);
pHalGdmaObj->Busy = 0;
return _TRUE;
}
VOID HalGdmaMemCpyDeInit(PHAL_GDMA_OBJ pHalGdmaObj)
{
HAL_GDMA_CHNL GdmaChnl;
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
PIRQ_HANDLE pGdmaIrqHandle;
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
pGdmaIrqHandle = &(pHalGdmaObj->GdmaIrqHandle);
GdmaChnl.GdmaIndx = pHalGdmaAdapter->GdmaIndex;
GdmaChnl.GdmaChnl = pHalGdmaAdapter->ChNum;
GdmaChnl.IrqNum = pGdmaIrqHandle->IrqNum;
HalGdmaChnlFree(&GdmaChnl);
}
// If multi-task using the same GDMA Object, then it needs a mutex to protect this procedure
VOID* HalGdmaMemCpy(PHAL_GDMA_OBJ pHalGdmaObj, void* pDest, void* pSrc, u32 len)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
if (pHalGdmaObj->Busy) {
DBG_GDMA_ERR("%s: ==> GDMA is Busy\r\n", __FUNCTION__);
return 0;
}
pHalGdmaObj->Busy = 1;
pHalGdmaAdapter = &(pHalGdmaObj->HalGdmaAdapter);
DBG_GDMA_INFO("%s: ==> Src=0x%x Dst=0x%x Len=%d\r\n", __FUNCTION__, pSrc, pDest, len);
if ((((u32)pSrc & 0x03)==0) &&
(((u32)pDest & 0x03)==0) &&
((len & 0x03)== 0)) {
// 4-bytes aligned, move 4 bytes each transfer
pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight;
pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthFourBytes;
pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthFourBytes;
pHalGdmaAdapter->GdmaCtl.BlockSize = len >> 2;
}
else {
pHalGdmaAdapter->GdmaCtl.SrcMsize = MsizeEight;
pHalGdmaAdapter->GdmaCtl.SrcTrWidth = TrWidthOneByte;
pHalGdmaAdapter->GdmaCtl.DestMsize = MsizeEight;
pHalGdmaAdapter->GdmaCtl.DstTrWidth = TrWidthOneByte;
pHalGdmaAdapter->GdmaCtl.BlockSize = len;
}
pHalGdmaAdapter->ChSar = (u32)pSrc;
pHalGdmaAdapter->ChDar = (u32)pDest;
pHalGdmaAdapter->PacketLen = len;
HalGdmaOn((pHalGdmaAdapter));
HalGdmaChIsrEn((pHalGdmaAdapter));
HalGdmaChSeting((pHalGdmaAdapter));
HalGdmaChEn((pHalGdmaAdapter));
return (pDest);
}

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#ifdef CONFIG_GPIO_EN
HAL_GPIO_DATA_SECTION HAL_GPIO_ADAPTER gHAL_Gpio_Adapter;
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
extern VOID GPIO_PullCtrl_8195a(u32 chip_pin, u8 pull_type);
/**
* @brief To get the GPIO IP Pin name for the given chip pin name
*
* @param chip_pin: The chip pin name.
*
* @retval The gotten GPIO IP pin name
*/
HAL_GPIO_TEXT_SECTION u32
HAL_GPIO_GetPinName(
u32 chip_pin
)
{
return HAL_GPIO_GetIPPinName_8195a((u32)chip_pin);
}
/**
* @brief Set the GPIO pad Pull type
*
* @param pin: The pin for pull type control.
* @param mode: the pull type for the pin.
* @return None
*/
VOID
HAL_GPIO_PullCtrl(
u32 pin,
u32 mode
)
{
u8 pull_type;
DBG_GPIO_INFO("%s: pin=0x%x mode=%d\n ", __FUNCTION__, (u32)pin, (u32)mode);
switch (mode) {
case hal_PullNone:
pull_type = DIN_PULL_NONE;
break;
case hal_PullDown:
pull_type = DIN_PULL_LOW;
break;
case hal_PullUp:
pull_type = DIN_PULL_HIGH;
break;
case hal_OpenDrain:
default:
pull_type = DIN_PULL_NONE;
break;
}
// HAL_GPIO_PullCtrl_8195a (pin, pull_type);
GPIO_PullCtrl_8195a (pin, pull_type);
}
/**
* @brief Initializes a GPIO Pin by the GPIO_Pin parameters.
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
*
* @retval HAL_Status
*/
HAL_GPIO_TEXT_SECTION VOID
HAL_GPIO_Init(
HAL_GPIO_PIN *GPIO_Pin
)
{
if (_pHAL_Gpio_Adapter == NULL) {
_pHAL_Gpio_Adapter = &gHAL_Gpio_Adapter;
DBG_GPIO_INFO("%s: Initial GPIO Adapter\n ", __FUNCTION__);
}
HAL_GPIO_Init_8195a(GPIO_Pin);
}
/**
* @brief Initializes a GPIO Pin as a interrupt signal
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
*
* @retval HAL_Status
*/
VOID
HAL_GPIO_Irq_Init(
HAL_GPIO_PIN *GPIO_Pin
)
{
if (_pHAL_Gpio_Adapter == NULL) {
_pHAL_Gpio_Adapter = &gHAL_Gpio_Adapter;
DBG_GPIO_INFO("%s: Initial GPIO Adapter\n ", __FUNCTION__);
}
if (_pHAL_Gpio_Adapter->IrqHandle.IrqFun == NULL) {
_pHAL_Gpio_Adapter->IrqHandle.IrqFun = HAL_GPIO_MbedIrqHandler_8195a;
_pHAL_Gpio_Adapter->IrqHandle.Priority = 8;
HAL_GPIO_RegIrq_8195a(&_pHAL_Gpio_Adapter->IrqHandle);
InterruptEn(&_pHAL_Gpio_Adapter->IrqHandle);
DBG_GPIO_INFO("%s: Initial GPIO IRQ Adapter\n ", __FUNCTION__);
}
DBG_GPIO_INFO("%s: GPIO(name=0x%x)(mode=%d)\n ", __FUNCTION__, GPIO_Pin->pin_name,
GPIO_Pin->pin_mode);
HAL_GPIO_MaskIrq_8195a(GPIO_Pin);
HAL_GPIO_Init_8195a(GPIO_Pin);
}
/**
* @brief UnInitial GPIO Adapter
*
*
* @retval HAL_Status
*/
VOID
HAL_GPIO_IP_DeInit(
VOID
)
{
if (_pHAL_Gpio_Adapter != NULL) {
InterruptDis(&_pHAL_Gpio_Adapter->IrqHandle);
HAL_GPIO_UnRegIrq_8195a(&_pHAL_Gpio_Adapter->IrqHandle);
_pHAL_Gpio_Adapter = NULL;
}
}
#endif // CONFIG_GPIO_EN

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "hal_i2s.h"
#include "rand.h"
#include "rtl_utility.h"
//1 need to be modified
/*======================================================
Local used variables
*/
SRAM_BF_DATA_SECTION
HAL_I2S_OP HalI2SOpSAL={0};
VOID
I2SISRHandle(
IN VOID *Data
)
{
PHAL_I2S_ADAPTER pI2SAdp = (PHAL_I2S_ADAPTER) Data;
PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL;
PHAL_I2S_INIT_DAT pI2SCfg = pI2SAdp->pInitDat;
u32 I2STxIsr, I2SRxIsr;
u8 I2SPageNum = pI2SCfg->I2SPageNum+1;
// u32 I2SPageSize = (pI2SAdp->I2SPageSize+1)<<2;
u32 i;
u32 pbuf;
I2STxIsr = pHalI2SOP->HalI2SReadReg(pI2SCfg, REG_I2S_TX_STATUS_INT);
I2SRxIsr = pHalI2SOP->HalI2SReadReg(pI2SCfg, REG_I2S_RX_STATUS_INT);
pI2SCfg->I2STxIntrClr = I2STxIsr;
pI2SCfg->I2SRxIntrClr = I2SRxIsr;
pHalI2SOP->HalI2SClrIntr(pI2SCfg);
for (i=0 ; i<I2SPageNum ; i++) { // page 0, 1, 2, 3
if (I2STxIsr & (1<<pI2SCfg->I2SHWTxIdx)) {
// pbuf = ((u32)(pI2SCfg->I2STxData)) + (I2SPageSize*pI2SCfg->I2SHWTxIdx);
pbuf = (u32)pI2SAdp->TxPageList[pI2SCfg->I2SHWTxIdx];
pI2SAdp->UserCB.TxCCB(pI2SAdp->UserCB.TxCBId, (char*)pbuf);
I2STxIsr &= ~(1<<pI2SCfg->I2SHWTxIdx);
pI2SCfg->I2SHWTxIdx += 1;
if (pI2SCfg->I2SHWTxIdx == I2SPageNum) {
pI2SCfg->I2SHWTxIdx = 0;
}
}
if (I2SRxIsr & (1<<pI2SCfg->I2SHWRxIdx)) {
// pbuf = ((u32)(pI2SCfg->I2SRxData)) + (I2SPageSize*pI2SCfg->I2SHWRxIdx);
pbuf = (u32)pI2SAdp->RxPageList[pI2SCfg->I2SHWRxIdx];
pI2SAdp->UserCB.RxCCB(pI2SAdp->UserCB.RxCBId, (char*)pbuf);
I2SRxIsr &= ~(1<<pI2SCfg->I2SHWRxIdx);
pI2SCfg->I2SHWRxIdx += 1;
if (pI2SCfg->I2SHWRxIdx == I2SPageNum) {
pI2SCfg->I2SHWRxIdx = 0;
}
}
}
}
static HAL_Status
RtkI2SIrqInit(
IN PHAL_I2S_ADAPTER pI2SAdapter
)
{
PIRQ_HANDLE pIrqHandle;
if (pI2SAdapter->DevNum > I2S_MAX_ID) {
DBG_I2S_ERR("RtkI2SIrqInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
return HAL_ERR_PARA;
}
pIrqHandle = &pI2SAdapter->IrqHandle;
switch (pI2SAdapter->DevNum){
case I2S0_SEL:
pIrqHandle->IrqNum = I2S0_PCM0_IRQ;
break;
case I2S1_SEL:
pIrqHandle->IrqNum = I2S1_PCM1_IRQ;
break;
default:
return HAL_ERR_PARA;
}
pIrqHandle->Data = (u32) (pI2SAdapter);
pIrqHandle->IrqFun = (IRQ_FUN) I2SISRHandle;
pIrqHandle->Priority = 3;
InterruptRegister(pIrqHandle);
InterruptEn(pIrqHandle);
return HAL_OK;
}
static HAL_Status
RtkI2SIrqDeInit(
IN PHAL_I2S_ADAPTER pI2SAdapter
)
{
if (pI2SAdapter->DevNum > I2S_MAX_ID) {
DBG_I2S_ERR("RtkI2SIrqDeInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
return HAL_ERR_PARA;
}
InterruptDis(&pI2SAdapter->IrqHandle);
InterruptUnRegister(&pI2SAdapter->IrqHandle);
return HAL_OK;
}
static HAL_Status
RtkI2SPinMuxInit(
IN PHAL_I2S_ADAPTER pI2SAdapter
)
{
u32 I2Stemp;
if (pI2SAdapter->DevNum > I2S_MAX_ID) {
DBG_I2S_ERR("RtkI2SPinMuxInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
return HAL_ERR_PARA;
}
// enable system pll
I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) | (1<<9) | (1<<10);
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);
switch (pI2SAdapter->DevNum){
case I2S0_SEL:
ACTCK_I2S_CCTRL(ON);
SLPCK_I2S_CCTRL(ON);
LXBUS_FCTRL(ON); // enable lx bus for i2s
/*I2S0 Pin Mux Setting*/
PinCtrl(I2S0, pI2SAdapter->PinMux, ON);
if (pI2SAdapter->PinMux == I2S_S0) {
DBG_I2S_WARN(ANSI_COLOR_MAGENTA"I2S0 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
}
I2S0_MCK_CTRL(ON);
I2S0_PIN_CTRL(ON);
I2S0_FCTRL(ON);
break;
case I2S1_SEL:
ACTCK_I2S_CCTRL(ON);
SLPCK_I2S_CCTRL(ON);
LXBUS_FCTRL(ON); // enable lx bus for i2s
/*I2S1 Pin Mux Setting*/
PinCtrl(I2S1, pI2SAdapter->PinMux, ON);
if (pI2SAdapter->PinMux == I2S_S2) {
DBG_I2S_WARN(ANSI_COLOR_MAGENTA"I2S1 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
}
I2S1_MCK_CTRL(ON);
I2S1_PIN_CTRL(ON);
I2S0_FCTRL(ON); //i2s 1 is control by bit 24 BIT_PERI_I2S0_EN
I2S1_FCTRL(ON);
break;
default:
return HAL_ERR_PARA;
}
return HAL_OK;
}
static HAL_Status
RtkI2SPinMuxDeInit(
IN PHAL_I2S_ADAPTER pI2SAdapter
)
{
if (pI2SAdapter->DevNum > I2S_MAX_ID) {
DBG_I2S_ERR("RtkI2SPinMuxDeInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
return HAL_ERR_PARA;
}
switch (pI2SAdapter->DevNum){
case I2S0_SEL:
/*I2S0 Pin Mux Setting*/
//ACTCK_I2C0_CCTRL(OFF);
PinCtrl(I2S0, pI2SAdapter->PinMux, OFF);
I2S0_MCK_CTRL(OFF);
I2S0_PIN_CTRL(OFF);
//I2S0_FCTRL(OFF);
break;
case I2S1_SEL:
/*I2S1 Pin Mux Setting*/
//ACTCK_I2C1_CCTRL(OFF);
PinCtrl(I2S1, pI2SAdapter->PinMux, OFF);
I2S1_MCK_CTRL(OFF);
I2S1_PIN_CTRL(OFF);
//I2S1_FCTRL(OFF);
break;
default:
return HAL_ERR_PARA;
}
return HAL_OK;
}
HAL_Status
RtkI2SInit(
IN VOID *Data
)
{
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL;
PHAL_I2S_INIT_DAT pI2SCfg;
if (pI2SAdapter == 0) {
DBG_I2S_ERR("RtkI2SInit: Null Pointer\r\n");
return HAL_ERR_PARA;
}
if (pI2SAdapter->DevNum > I2S_MAX_ID) {
DBG_I2S_ERR("RtkI2SInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
return HAL_ERR_PARA;
}
pI2SCfg = pI2SAdapter->pInitDat;
/*I2S Initialize HAL Operations*/
HalI2SOpInit(pHalI2SOP);
/*I2S Interrupt Initialization*/
RtkI2SIrqInit(pI2SAdapter);
/*I2S Pin Mux Initialization*/
RtkI2SPinMuxInit(pI2SAdapter);
/*I2S Load User Setting*/
pI2SCfg->I2SIdx = pI2SAdapter->DevNum;
/*I2S HAL Initialization*/
pHalI2SOP->HalI2SInit(pI2SCfg);
/*I2S Device Status Update*/
pI2SAdapter->DevSts = I2S_STS_INITIALIZED;
/*I2S Enable Module*/
pI2SCfg->I2SEn = I2S_ENABLE;
pHalI2SOP->HalI2SEnable(pI2SCfg);
/*I2S Device Status Update*/
pI2SAdapter->DevSts = I2S_STS_IDLE;
return HAL_OK;
}
HAL_Status
RtkI2SDeInit(
IN VOID *Data
)
{
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL;
PHAL_I2S_INIT_DAT pI2SCfg;
u32 I2Stemp;
if (pI2SAdapter == 0) {
DBG_I2S_ERR("RtkI2SDeInit: Null Pointer\r\n");
return HAL_ERR_PARA;
}
pI2SCfg = pI2SAdapter->pInitDat;
/*I2S Disable Module*/
pI2SCfg->I2SEn = I2S_DISABLE;
pHalI2SOP->HalI2SEnable(pI2SCfg);
HalI2SClearAllOwnBit((VOID*)pI2SCfg);
/*I2C HAL DeInitialization*/
//pHalI2SOP->HalI2SDeInit(pI2SCfg);
/*I2S Interrupt DeInitialization*/
RtkI2SIrqDeInit(pI2SAdapter);
/*I2S Pin Mux DeInitialization*/
RtkI2SPinMuxDeInit(pI2SAdapter);
/*I2S HAL DeInitialization*/
pHalI2SOP->HalI2SDeInit(pI2SCfg);
/*I2S CLK Source Close*/
I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) & (~((1<<9) | (1<<10)));
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);
/*I2S Device Status Update*/
pI2SAdapter->DevSts = I2S_STS_UNINITIAL;
return HAL_OK;
}
HAL_Status
RtkI2SEnable(
IN VOID *Data
)
{
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL;
PHAL_I2S_INIT_DAT pI2SCfg;
u32 I2Stemp;
// Enable IP Clock
I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) | (1<<9) | (1<<10);
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);
ACTCK_I2S_CCTRL(ON);
SLPCK_I2S_CCTRL(ON);
pI2SCfg = pI2SAdapter->pInitDat;
pI2SCfg->I2SEn = I2S_ENABLE;
pHalI2SOP->HalI2SEnable(pI2SCfg);
return HAL_OK;
}
HAL_Status
RtkI2SDisable(
IN VOID *Data
)
{
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL;
PHAL_I2S_INIT_DAT pI2SCfg;
u32 I2Stemp;
pI2SCfg = pI2SAdapter->pInitDat;
pI2SCfg->I2SEn = I2S_DISABLE;
pHalI2SOP->HalI2SEnable(pI2SCfg);
// Gate IP Clock
ACTCK_I2S_CCTRL(OFF);
SLPCK_I2S_CCTRL(OFF);
// Close I2S bus clock(WS,SCLK,MCLK). If needs that clock, mark this.
I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) & (~((1<<9) | (1<<10)));
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);
return HAL_OK;
}
RTK_STATUS
RtkI2SIoCtrl(
IN VOID *Data
)
{
return _EXIT_SUCCESS;
}
RTK_STATUS
RtkI2SPowerCtrl(
IN VOID *Data
)
{
return _EXIT_SUCCESS;
}
HAL_Status
RtkI2SLoadDefault(
IN VOID *Adapter,
IN VOID *Setting
)
{
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Adapter;
PHAL_I2S_INIT_DAT pI2SCfg = pI2SAdapter->pInitDat;
PHAL_I2S_DEF_SETTING pLoadSetting = (PHAL_I2S_DEF_SETTING)Setting;
if (pI2SAdapter == 0) {
DBG_I2S_ERR("RtkI2SLoadDefault: Null Pointer\r\n");
return HAL_ERR_PARA;
}
if (pI2SAdapter->pInitDat == NULL) {
DBG_I2S_ERR("RtkI2SLoadDefault: pInitDat is NULL!\r\n", pI2SAdapter->DevNum);
return HAL_ERR_PARA;
}
pI2SAdapter->DevSts = pLoadSetting->DevSts;
pI2SAdapter->ErrType = 0;
pI2SAdapter->TimeOut = 0;
pI2SCfg->I2SIdx = pI2SAdapter->DevNum;
pI2SCfg->I2SEn = I2S_DISABLE;
pI2SCfg->I2SMaster = pLoadSetting->I2SMaster;
pI2SCfg->I2SWordLen = pLoadSetting->I2SWordLen;
pI2SCfg->I2SChNum = pLoadSetting->I2SChNum;
pI2SCfg->I2SPageNum = pLoadSetting->I2SPageNum;
pI2SCfg->I2SPageSize = pLoadSetting->I2SPageSize;
pI2SCfg->I2SRate = pLoadSetting->I2SRate;
pI2SCfg->I2STRxAct = pLoadSetting->I2STRxAct;
pI2SCfg->I2STxIntrMSK = pLoadSetting->I2STxIntrMSK;
pI2SCfg->I2SRxIntrMSK = pLoadSetting->I2SRxIntrMSK;
return HAL_OK;
}
VOID HalI2SOpInit(
IN VOID *Data
)
{
PHAL_I2S_OP pHalI2SOp = (PHAL_I2S_OP) Data;
pHalI2SOp->HalI2SInit = HalI2SInitRtl8195a_Patch;
pHalI2SOp->HalI2SDeInit = HalI2SDeInitRtl8195a;
pHalI2SOp->HalI2STx = HalI2STxRtl8195a;
pHalI2SOp->HalI2SRx = HalI2SRxRtl8195a;
pHalI2SOp->HalI2SEnable = HalI2SEnableRtl8195a;
pHalI2SOp->HalI2SIntrCtrl = HalI2SIntrCtrlRtl8195a;
pHalI2SOp->HalI2SReadReg = HalI2SReadRegRtl8195a;
pHalI2SOp->HalI2SSetRate = HalI2SSetRateRtl8195a;
pHalI2SOp->HalI2SSetWordLen = HalI2SSetWordLenRtl8195a;
pHalI2SOp->HalI2SSetChNum = HalI2SSetChNumRtl8195a;
pHalI2SOp->HalI2SSetPageNum = HalI2SSetPageNumRtl8195a;
pHalI2SOp->HalI2SSetPageSize = HalI2SSetPageSizeRtl8195a;
pHalI2SOp->HalI2SClrIntr = HalI2SClrIntrRtl8195a;
pHalI2SOp->HalI2SClrAllIntr = HalI2SClrAllIntrRtl8195a;
pHalI2SOp->HalI2SDMACtrl = HalI2SDMACtrlRtl8195a;
}
HAL_Status
HalI2SInit(
IN VOID *Data
)
{
HAL_Status ret;
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
#ifdef CONFIG_SOC_PS_MODULE
REG_POWER_STATE I2sPwrState;
#endif
ret = RtkI2SInit(Data);
#ifdef CONFIG_SOC_PS_MODULE
if(ret == HAL_OK) {
// To register a new peripheral device power state
I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum;
I2sPwrState.PwrState = ACT;
RegPowerState(I2sPwrState);
}
#endif
return ret;
}
VOID
HalI2SDeInit(
IN VOID *Data
)
{
#ifdef CONFIG_SOC_PS_MODULE
REG_POWER_STATE I2sPwrState;
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
u8 HwState;
I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum;
QueryRegPwrState(I2sPwrState.FuncIdx, &(I2sPwrState.PwrState), &HwState);
// if the power state isn't ACT, then switch the power state back to ACT first
if ((I2sPwrState.PwrState != ACT) && (I2sPwrState.PwrState != INACT)) {
HalI2SEnable(Data);
QueryRegPwrState(I2sPwrState.FuncIdx, &(I2sPwrState.PwrState), &HwState);
}
if (I2sPwrState.PwrState == ACT) {
I2sPwrState.PwrState = INACT;
RegPowerState(I2sPwrState);
}
#endif
RtkI2SDeInit(Data);
}
HAL_Status
HalI2SDisable(
IN VOID *Data
)
{
HAL_Status ret;
#ifdef CONFIG_SOC_PS_MODULE
REG_POWER_STATE I2sPwrState;
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
#endif
ret = RtkI2SDisable(Data);
#ifdef CONFIG_SOC_PS_MODULE
if (ret == HAL_OK) {
I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum;
I2sPwrState.PwrState = SLPCG;
RegPowerState(I2sPwrState);
}
#endif
return ret;
}
HAL_Status
HalI2SEnable(
IN VOID *Data
)
{
HAL_Status ret;
#ifdef CONFIG_SOC_PS_MODULE
REG_POWER_STATE I2sPwrState;
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
#endif
ret = RtkI2SEnable(Data);
#ifdef CONFIG_SOC_PS_MODULE
if (ret == HAL_OK) {
I2sPwrState.FuncIdx = I2S0 + pI2SAdapter->DevNum;
I2sPwrState.PwrState = ACT;
RegPowerState(I2sPwrState);
}
#endif
return ret;
}

42
lib/fwlib/src/hal_mii.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "hal_mii.h"
VOID
HalMiiOpInit(
IN VOID *Data
)
{
PHAL_MII_OP pHalMiiOp = (PHAL_MII_OP) Data;
pHalMiiOp->HalMiiGmacInit = HalMiiGmacInitRtl8195a;
pHalMiiOp->HalMiiInit = HalMiiInitRtl8195a;
pHalMiiOp->HalMiiGmacReset = HalMiiGmacResetRtl8195a;
pHalMiiOp->HalMiiGmacEnablePhyMode = HalMiiGmacEnablePhyModeRtl8195a;
pHalMiiOp->HalMiiGmacXmit = HalMiiGmacXmitRtl8195a;
pHalMiiOp->HalMiiGmacCleanTxRing = HalMiiGmacCleanTxRingRtl8195a;
pHalMiiOp->HalMiiGmacFillTxInfo = HalMiiGmacFillTxInfoRtl8195a;
pHalMiiOp->HalMiiGmacFillRxInfo = HalMiiGmacFillRxInfoRtl8195a;
pHalMiiOp->HalMiiGmacTx = HalMiiGmacTxRtl8195a;
pHalMiiOp->HalMiiGmacRx = HalMiiGmacRxRtl8195a;
pHalMiiOp->HalMiiGmacSetDefaultEthIoCmd = HalMiiGmacSetDefaultEthIoCmdRtl8195a;
pHalMiiOp->HalMiiGmacInitIrq = HalMiiGmacInitIrqRtl8195a;
pHalMiiOp->HalMiiGmacGetInterruptStatus = HalMiiGmacGetInterruptStatusRtl8195a;
pHalMiiOp->HalMiiGmacClearInterruptStatus = HalMiiGmacClearInterruptStatusRtl8195a;
#if 0
pHalMiiOp-> = Rtl8195a;
pHalMiiOp-> = Rtl8195a;
pHalMiiOp-> = Rtl8195a;
pHalMiiOp-> = Rtl8195a;
pHalMiiOp-> = Rtl8195a;
#endif
}

20
lib/fwlib/src/hal_nfc.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "hal_nfc.h"
VOID HalNFCOpInit(
IN VOID *Data
)
{
}

28
lib/fwlib/src/hal_pcm.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "hal_pcm.h"
VOID HalPcmOpInit(
IN VOID *Data
)
{
PHAL_PCM_OP pHalPcmOp = (PHAL_PCM_OP) Data;
pHalPcmOp->HalPcmOnOff = HalPcmOnOffRtl8195a;
pHalPcmOp->HalPcmInit = HalPcmInitRtl8195a;
pHalPcmOp->HalPcmSetting = HalPcmSettingRtl8195a;
pHalPcmOp->HalPcmEn = HalPcmEnRtl8195a;
pHalPcmOp->HalPcmIsrEnAndDis= HalPcmIsrEnAndDisRtl8195a;
pHalPcmOp->HalPcmDumpReg= HalPcmDumpRegRtl8195a;
pHalPcmOp->HalPcm= HalPcmRtl8195a;
}

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