mirror of
https://github.com/pvvx/RTL00MP3.git
synced 2025-07-31 12:41:06 +00:00
update
This commit is contained in:
pvvx
parent
b075b615b6
commit
8c8b03208e
28 changed files with 2887 additions and 2556 deletions
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@ -1,5 +1,5 @@
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/*
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* BootLoader Ver 0.2
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* BootLoader Ver 0.3 (18/10/2017)
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* Created on: 12/02/2017
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* Author: pvvx
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*/
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@ -8,6 +8,7 @@
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#include "rtl_bios_data.h"
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#include "diag.h"
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#include "rtl8195a/rtl8195a_sys_on.h"
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#include "rtl8195a/rtl8195a_sdr.h"
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#include "hal_spi_flash.h"
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@ -30,7 +31,7 @@
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#define DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE (DEFAULT_BOOT_CLK_CPU-6)
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#endif
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#endif // DEFAULT_BOOT_CLK_CPU
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#define FIX_SDR_CALIBRATION // for speed and low used SRAM
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#define BOOT_RAM_TEXT_SECTION // __attribute__((section(".boot.text")))
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//-------------------------------------------------------------------------
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@ -65,7 +66,6 @@ extern _LONG_CALL_ VOID HalInitPlatformLogUartV02(VOID);
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extern _LONG_CALL_ VOID HalInitPlatformTimerV02(VOID);
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//extern _LONG_CALL_ VOID DramInit_rom(IN DRAM_DEVICE_INFO *DramInfo);
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//extern _LONG_CALL_ u32 SdrCalibration_rom(VOID);
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extern _LONG_CALL_ int SdrControllerInit_rom(PDRAM_DEVICE_INFO pDramInfo);
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extern _LONG_CALL_ u32 SpicCmpDataForCalibrationRtl8195A(void); // compare read_data and golden_data
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//extern _LONG_CALL_ VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara); // wait spi-flash status register[0] = 0
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//extern _LONG_CALL_ VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara);
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@ -100,14 +100,14 @@ LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() {
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CfgSysDebugErr = -1;
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ConfigDebugWarn = -1;
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// ConfigDebugInfo = 0;
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ConfigDebugErr = -1;
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ConfigDebugErr = -1; // ~_DBG_SDR_;
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#elif CONFIG_DEBUG_LOG > 0
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// CfgSysDebugWarn = 0;
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// CfgSysDebugInfo = 0;
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CfgSysDebugErr = -1;
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// ConfigDebugWarn = 0;
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// ConfigDebugInfo = 0;
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ConfigDebugErr = -1;
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ConfigDebugErr = -1; // ~_DBG_SDR_;
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#else
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// CfgSysDebugWarn = 0;
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// CfgSysDebugInfo = 0;
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@ -125,15 +125,6 @@ LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) {
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HalPinCtrlRtl8195A(JTAG, 0, 1);
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}
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/* GetChipId() */
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LOCAL uint8 INFRA_START_SECTION _Get_ChipId() {
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uint8 ChipId = CHIP_ID_8710AF;
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if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
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&ChipId, L25EOUTVOLTAGE) != 1)
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DBG_8195A("Get Chip ID Failed\r");
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return ChipId;
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}
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/*
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* 16 bytes FIFO ... 16*11/38400 = 0.004583 sec
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* (0.005/5)*166666666 = 166666.666 Tcpu
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@ -281,11 +272,130 @@ LOCAL int BOOT_RAM_TEXT_SECTION InitSpic(uint8 SpicBitMode) {
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}
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ACTCK_FLASH_CCTRL(1);
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SLPCK_FLASH_CCTRL(1);
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HalPinCtrlRtl8195A(SPI_FLASH, 0, 1);
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HalPinCtrlRtl8195A(SPI_FLASH, 0, ON);
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InitSpicFlashType(&spic_table_flash);
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return SetSpicBitMode(SpicBitMode);
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}
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#ifdef CONFIG_SDR_EN
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/* GetChipId() */
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LOCAL uint8 INFRA_START_SECTION _Get_ChipId() {
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uint8 ChipId = CHIP_ID_8710AF;
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if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
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&ChipId, L25EOUTVOLTAGE) != 1)
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DBG_8195A("Get Chip ID Failed\r");
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return ChipId;
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}
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LOCAL void INFRA_START_SECTION sdr_preinit(void) {
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HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
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((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); // ROM: BIT_SYS_REGU_LDO25M_ADJ(0x0e)? HAL RAM BIT_SYS_REGU_LDO25M_ADJ(0x03)
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LDO25M_CTRL(ON);
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SRAM_MUX_CFG(0x2);
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SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE); // REG_PESOC_CLK_SEL
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HalPinCtrlRtl8195A(SDR, 0, ON); // SDR_PIN_FCTRL(ON);
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ACTCK_SDR_CCTRL(ON);
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SLPCK_SDR_CCTRL(ON);
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HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4, 0);
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MEM_CTRL_FCTRL(ON);
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// HalDelayUs(1000);
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}
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#ifndef FIX_SDR_CALIBRATION
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extern _LONG_CALL_ int SdrCalibration_rom(void);
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extern _LONG_CALL_ unsigned int Rand(void);
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extern _LONG_CALL_ int SdrControllerInit_rom(PDRAM_DEVICE_INFO pDramInfo);
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LOCAL int INFRA_START_SECTION sdr_test(u32 LoopCnt) {
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u32 LoopIndex = 0;
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u32 Value32, Addr;
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for (LoopIndex = 0; LoopIndex < LoopCnt; LoopIndex++) {
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Value32 = Rand();
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Addr = Rand();
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Addr &= 0x1FFFFF;
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Addr &= (~0x3);
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HAL_SDRAM_WRITE32(Addr, Value32);
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if (HAL_SDRAM_READ32(Addr) != Value32)
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return 0;
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}
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return 1;
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}
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#endif
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LOCAL int INFRA_START_SECTION sdr_init_from_flash(void) {
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#define RdPipe 0
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#if DEFAULT_BOOT_CLK_CPU < 6
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#define TapCnt 0x11
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#elif DEFAULT_BOOT_CLK_CPU == 7
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#define TapCnt 0x23
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#else
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#define TapCnt 0x19
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#endif
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// set all_mode _idle
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HAL_SDR_WRITE32(REG_SDR_CSR, 0x700);
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// WRAP_MISC setting
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HAL_SDR_WRITE32(REG_SDR_MISC, 0x00000001);
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// PCTL setting
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HAL_SDR_WRITE32(REG_SDR_DCR, 0x00000008);
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HAL_SDR_WRITE32(REG_SDR_IOCR, RdPipe << PCTL_IOCR_RD_PIPE_BFO);
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HAL_SDR_WRITE32(REG_SDR_EMR2, 0x00000000);
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HAL_SDR_WRITE32(REG_SDR_EMR1, 0x00000006);
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HAL_SDR_WRITE32(REG_SDR_MR, 0x00000022);
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HAL_SDR_WRITE32(REG_SDR_DRR, 0x09030e07);
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HAL_SDR_WRITE32(REG_SDR_TPR0, 0x00002652);
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HAL_SDR_WRITE32(REG_SDR_TPR1, 0x00068873);
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HAL_SDR_WRITE32(REG_SDR_TPR2, 0x00000042);
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// start to init
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HAL_SDR_WRITE32(REG_SDR_CCR, 0x01);
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DBG_8195A("SDR calibration: %02x-%02x\n", RdPipe, TapCnt);
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while ((HAL_SDR_READ32(REG_SDR_CCR) & 0x1) == 0x0);
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// enter mem_mode
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HAL_SDR_WRITE32(REG_SDR_CSR, 0x600);
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#ifdef FIX_SDR_CALIBRATION
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SDR_DDL_FCTRL(TapCnt); // SDR_DDL_FCTRL(0x11);
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return 1;
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#else
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union { u8 b[8]; u16 s[4]; u32 l[2]; u64 d;} value;
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// read calibration data from system data FLASH_SDRC_PARA_BASE
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u32 reg = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1);
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u32 faddr = SPI_FLASH_BASE + FLASH_SDRC_PARA_BASE + ((reg & 0x70) >> 1) + ((reg & BIT17) >> 11) ; // step 8 in FLASH_SDRC_PARA_BASE[64 + 64 bytes]
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value.d = *((volatile u64 *)faddr);
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DBG_8195A("SDR flash calibration [%08x] %02x-%02x-%02x\n", faddr, value.b[0], value.b[4], value.b[6]);
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if(value.s[0] == 0xFE01 && (value.b[4]^value.b[5]) == 0xFF && (value.b[6]^value.b[7]) == 0xFF) {
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HAL_SDR_WRITE32(REG_SDR_IOCR, (HAL_SDR_READ32(REG_SDR_IOCR) & 0xff) | ((u32)value.b[4] << PCTL_IOCR_RD_PIPE_BFO));
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SDR_DDL_FCTRL((u32)value.b[6]);
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if(sdr_test(7))
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return 1; // ok
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else
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DBG_8195A("Not valid SDR calibration in flash!\n");
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} else
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DBG_8195A("Error SDR calibration in flash!\n");
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if(SdrCalibration_rom()) { // Внимание: дает завышенный TapCnt !
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// DBG_8195A("SDR calibration: %02x-%02x-%02x\n", value.b[0], value.b[4], value.b[6]);
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value.s[0] = 0xFE01;
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value.b[4] = HAL_SDR_READ32(REG_SDR_IOCR) >> PCTL_IOCR_RD_PIPE_BFO;
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value.b[5] = value.b[4] ^ 0xFF;
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value.b[6] = HAL_PERI_ON_READ32(REG_PESOC_MEM_CTRL) >> BIT_SHIFT_PESOC_SDR_DDL_CTRL;
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value.b[7] = value.b[6] ^ 0xFF;
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// DBG_8195A("%08x: %02x-%02x-%02x)\n", faddr, value.b[0], value.b[4], value.b[6]);
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if((*((volatile u16 *)(faddr)) & value.s[0]) == value.s[0]
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&& (*((volatile u32 *)(faddr + 4)) & value.l[1]) == value.l[1]) {
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*((volatile u32 *)(faddr + 4)) = value.l[1];
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DBG_8195A("Write new calibration [%08x] %02x-%02x-%02x\n", faddr, value.b[0], value.b[4], value.b[6]);
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HalDelayUs(1000);
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*((volatile u16 *)(faddr)) = value.s[0];
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} else {
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DBG_8195A("Work recalibration: %02x-%02x-%02x!\n", value.b[0], value.b[4], value.b[6]);
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}
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return 2; // recalibration - ok
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} else
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DBG_8195A("SDR recalibration fail!\n");
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return 0;
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#endif // FIX_SDR_CALIBRATION
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}
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#endif // CONFIG_SDR_EN
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/* SYSPlatformInit */
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LOCAL void INFRA_START_SECTION SYSPlatformInit(void) {
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@ -562,35 +672,36 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
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else
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DBG_8195A("\r===== Enter SRAM-Boot %d ====\n", flg);
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#if CONFIG_DEBUG_LOG > 1
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DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(),
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DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\n", HalGetCpuClk(),
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HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
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#endif
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#ifdef CONFIG_SDR_EN
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uint8 ChipId = _Get_ChipId();
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if (ChipId < CHIP_ID_8195AM) {
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#endif
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//----- SDRAM Off
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SDR_PIN_FCTRL(OFF);
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LDO25M_CTRL(OFF);
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init
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#ifdef CONFIG_SDR_EN
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init or None
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} else {
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//----- SDRAM On
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LDO25M_CTRL(ON);
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HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
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(HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x0e));
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SDR_PIN_FCTRL(ON);
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sdr_preinit();
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};
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#endif
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if (!InitSpic(SpicDualBitMode)) {
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DBG_8195A("Spic Init Error!\n");
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DBG_8195A("Spic Init fail!\n");
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RtlConsolRam();
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};
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if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // Flag SDRAM Init?
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// extern DRAM_DEVICE_INFO SdrDramInfo_rom; // 50 MHz
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if (!SdrControllerInit_rom(&SdrDramInfo)) { // 100 MHz
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DBG_8195A("SDR Controller Init fail!\n");
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#ifdef CONFIG_SDR_EN
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if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // Flag SDRAM No ReInit?
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if(!sdr_init_from_flash()) {
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DBG_8195A("SDR Init fail!\n");
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RtlConsolRam();
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}
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#if 0 // Test SDRAM
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#ifdef USE_SDRAM_TEST // Test SDRAM
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else {
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uint32 *ptr = SDR_SDRAM_BASE;
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uint32 *ptr = (uint32 *)SDR_SDRAM_BASE;
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uint32 tt = 0x55AA55AA;
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for (int i = 0; i < 512 * 1024; i++) {
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ptr[i] = tt++;
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@ -601,23 +712,26 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
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DBG_8195A("SDR err %p %p != %p!\n", &ptr[i], ptr[i], tt);
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RtlConsolRam();
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}
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// ptr[i] = 0;
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tt++;
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};
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DBG_8195A("SDR tst end\n");
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DBG_8195A("SDR test ok\n");
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};
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#endif // Test SDRAM
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#ifdef CONFIG_SDR_EN
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// Тест и ожидание загрузки Jlink-ом sdram.bin (~7 sec)
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if(flg && *((uint32 *)0x1FFF0000) == 0x12345678) {
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*((volatile uint32 *)0x1FFF0000) = 0x87654321;
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uint32 tt = 0x03ffffff; // ~7 sec
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DBG_8195A("Waiting for SDRAM to load...\n");
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// __asm__ __volatile__ ("cpsid f\n");
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while(*((volatile uint32 *)0x1FFF0000) == 0x87654321 && tt--);
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// __asm__ __volatile__ ("cpsie f\n");
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if(*((volatile uint32 *)0x1FFF0000) == 1)
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DBG_8195A("SDRAM load ok\n");
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}
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#endif // test
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM No ReInit
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};
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#endif // CONFIG_SDR_EN
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if (!flg)
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loadUserImges(IsForceLoadDefaultImg2() + 1);
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@ -1,5 +1,5 @@
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/*
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* StartUp SDK
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* StartUp USDK v0.2 (19/10/2017)
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* Created on: 02/03/2017
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* Author: pvvx
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*/
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@ -41,6 +41,7 @@ void SDIO_Device_Off(void);
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//void VectorTableOverrideRtl8195A(u32 StackP);
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void SYSPlatformInit(void);
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#define FIX_SDR_CALIBRATION // for speed :)
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//-------------------------------------------------------------------------
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// Data declarations
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extern u8 __bss_start__, __bss_end__;
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@ -49,7 +50,63 @@ extern const unsigned char cus_sig[32]; // images name
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IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 =
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{ InfraStart + 1 };
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#ifdef CONFIG_SDR_EN
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#ifdef FIX_SDR_CALIBRATION // for speed :)
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#include "rtl8195a/rtl8195a_sdr.h"
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LOCAL void sdr_init(void) {
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HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
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((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); // ROM: BIT_SYS_REGU_LDO25M_ADJ(0x0e)? HAL RAM BIT_SYS_REGU_LDO25M_ADJ(0x03)
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LDO25M_CTRL(ON);
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SRAM_MUX_CFG(0x2);
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SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE); // REG_PESOC_CLK_SEL
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HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4, 0);
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ACTCK_SDR_CCTRL(ON);
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SLPCK_SDR_CCTRL(ON);
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HalPinCtrlRtl8195A(SDR, 0, ON); // SDR_PIN_FCTRL(ON);
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MEM_CTRL_FCTRL(ON);
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// HalDelayUs(1000);
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// read calibration data from system data FLASH_SDRC_PARA_BASE
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union { u8 b[8]; u16 s[4]; u32 l[2]; u64 d;} value;
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u32 faddr = SPI_FLASH_BASE + FLASH_SDRC_PARA_BASE + CPU_CLOCK_SEL_VALUE*8 + CPU_CLOCK_SEL_DIV5_3*8*8; // step 8 in FLASH_SDRC_PARA_BASE[64 + 64 bytes]
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value.d = *((volatile u64 *)faddr);
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if(value.s[0] == 0xFE01 && (value.b[4]^value.b[5]) == 0xFF && (value.b[6]^value.b[7]) == 0xFF) {
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DBG_8195A("SDR flash calibration [%08x]: %02x-%02x ", faddr, value.b[4], value.b[6]);
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} else {
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value.b[4] = 0; // TapCnt
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#if CONFIG_CPU_CLK < 6
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value.b[6] = 0x11; // RdPipe
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#elif CONFIG_CPU_CLK == 7
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value.b[6] = 0x23; // RdPipe
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#else
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value.b[6] = 0x19; // RdPipe
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#endif
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DBG_8195A("Use fix SDR calibration: %02x-%02x ", value.b[4], value.b[6]);
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}
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// set all_mode _idle
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HAL_SDR_WRITE32(REG_SDR_CSR, 0x700);
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// WRAP_MISC setting
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HAL_SDR_WRITE32(REG_SDR_MISC, 0x00000001);
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// PCTL setting
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HAL_SDR_WRITE32(REG_SDR_DCR, 0x00000008);
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HAL_SDR_WRITE32(REG_SDR_IOCR, (u32)value.b[4] << PCTL_IOCR_RD_PIPE_BFO);
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HAL_SDR_WRITE32(REG_SDR_EMR2, 0x00000000);
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HAL_SDR_WRITE32(REG_SDR_EMR1, 0x00000006);
|
||||
HAL_SDR_WRITE32(REG_SDR_MR, 0x00000022);
|
||||
HAL_SDR_WRITE32(REG_SDR_DRR, 0x09030e07);
|
||||
HAL_SDR_WRITE32(REG_SDR_TPR0, 0x00002652);
|
||||
HAL_SDR_WRITE32(REG_SDR_TPR1, 0x00068873);
|
||||
HAL_SDR_WRITE32(REG_SDR_TPR2, 0x00000042);
|
||||
// start to init
|
||||
HAL_SDR_WRITE32(REG_SDR_CCR, 0x01);
|
||||
while ((HAL_SDR_READ32(REG_SDR_CCR) & 0x1) == 0x0)
|
||||
DBG_8195A(".");
|
||||
// enter mem_mode
|
||||
HAL_SDR_WRITE32(REG_SDR_CSR, 0x600);
|
||||
SDR_DDL_FCTRL((u32)value.b[6]);
|
||||
DBG_8195A(" ok\n");
|
||||
}
|
||||
#endif // FIX_SDR_CALIBRATION
|
||||
#endif // CONFIG_SDR_EN
|
||||
/*
|
||||
//----- HalNMIHandler_Patch
|
||||
void HalNMIHandler_Patch(void) {
|
||||
|
|
@ -167,30 +224,36 @@ extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
|
|||
};
|
||||
*/
|
||||
// SpicFlashInitRtl8195A(SpicDualBitMode); // SpicReadIDRtl8195A(); SpicDualBitMode
|
||||
#ifdef CONFIG_SDR_EN
|
||||
//---- SDRAM
|
||||
uint8 ChipId = HalGetChipId();
|
||||
if (ChipId >= CHIP_ID_8195AM) {
|
||||
#ifdef CONFIG_SDR_EN
|
||||
if((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена?
|
||||
if((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // SDR not init?
|
||||
#ifdef FIX_SDR_CALIBRATION // for speed :)
|
||||
sdr_init();
|
||||
#else // not FIX_SDR_CALIBRATION
|
||||
SdrCtrlInit();
|
||||
if(SdrControllerInit()) {
|
||||
if(!SdrControllerInit()) {
|
||||
DBG_8195A("SDR Controller Init fail!\n");
|
||||
};
|
||||
#endif // FIX_SDR_CALIBRATION
|
||||
};
|
||||
#endif
|
||||
// clear SDRAM bss
|
||||
extern uint8 __sdram_bss_start__[];
|
||||
extern uint8 __sdram_bss_end__[];
|
||||
if((uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__ > 0)
|
||||
memset(__sdram_bss_start__, 0, (uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__);
|
||||
}
|
||||
else
|
||||
else // if (ChipId < CHIP_ID_8195AM)
|
||||
{
|
||||
//----- SDRAM Off
|
||||
SDR_PIN_FCTRL(OFF);
|
||||
LDO25M_CTRL(OFF);
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off
|
||||
};
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init or None
|
||||
#else
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (~BIT(21))); // Flag SDRAM Not Init
|
||||
#endif // CONFIG_SDR_EN
|
||||
//----- Close Flash
|
||||
SPI_FLASH_PIN_FCTRL(OFF);
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
//2 REG_NOT_VALID
|
||||
|
||||
//2 REG_SOC_FUNC_EN
|
||||
// BIT(21) SDRAM
|
||||
// BIT(21) if 1 -> SDRAM No ReInit
|
||||
#define BIT_SOC_SECURITY_ENGINE_EN BIT(20)
|
||||
#define BIT_SOC_GTIMER_EN BIT(16)
|
||||
#define BIT_SOC_GDMA1_EN BIT(14)
|
||||
|
|
|
|||
|
|
@ -432,6 +432,7 @@ VOID
|
|||
else {
|
||||
return 1;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1056,19 +1057,19 @@ MemTest(
|
|||
{
|
||||
u32 LoopIndex = 0;
|
||||
u32 Value32, Addr;
|
||||
for (LoopIndex = 0; LoopIndex<LoopCnt; LoopIndex++) {
|
||||
for (LoopIndex = 0; LoopIndex < LoopCnt; LoopIndex++) {
|
||||
// Value32 = Sdr_Rand2();
|
||||
// Addr = Sdr_Rand2();
|
||||
Value32 = Rand();
|
||||
Addr = Rand();
|
||||
Addr &= 0x1FFFFF;
|
||||
Addr &= (~0x3);
|
||||
|
||||
HAL_SDRAM_WRITE32(Addr, Value32);
|
||||
Addr = Rand() & 0x1FFFFC;
|
||||
|
||||
if (HAL_SDRAM_READ32(Addr) != Value32) {
|
||||
DBG_8195A("Test %d: No match addr 0x%x => 0x%x != 0x%x\n",LoopIndex,
|
||||
Addr, Value32, HAL_SDRAM_READ32(Addr));
|
||||
HAL_SDRAM_WRITE32(Addr, Value32);
|
||||
u32 x = HAL_SDRAM_READ32(Addr);
|
||||
// DBG_8195A("[%p] %p %p\n", Addr, Value32, x);
|
||||
|
||||
if (x != Value32) {
|
||||
DBG_8195A("Test %d: No match addr 0x%x => 0x%x != 0x%x\n", LoopIndex,
|
||||
Addr, Value32, x);
|
||||
return _FALSE;
|
||||
}
|
||||
else {
|
||||
|
|
|
|||
|
|
@ -177,6 +177,7 @@ SECTIONS
|
|||
LONG(0)
|
||||
UartLogRamCmdTable = .;
|
||||
KEEP(*(SORT(.mon.tab*)))
|
||||
KEEP(*(SORT(.sdram.mon.tab*)))
|
||||
UartLogRamCmdTable_end = .;
|
||||
LONG(0)
|
||||
} > BD_RAM
|
||||
|
|
|
|||
|
|
@ -121,6 +121,35 @@ SECTIONS
|
|||
KEEP(*(.image2.validate.rodata*))
|
||||
KEEP(*(.custom.validate.rodata*))
|
||||
} > BD_RAM
|
||||
|
||||
.sdr_text :
|
||||
{
|
||||
__sdram_data_start__ = .;
|
||||
INCLUDE "sdram_obj.txt"
|
||||
*(.sdram.text*)
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_rodata :
|
||||
{
|
||||
*(.sdram.rodata*)
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_data :
|
||||
{
|
||||
*(.sdram.data*)
|
||||
__sdram_data_end__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_bss :
|
||||
{
|
||||
__sdram_bss_start__ = .;
|
||||
*(.uvc.ram.bss)
|
||||
*(.sdram.bss*)
|
||||
INCLUDE "sdram_bss.txt"
|
||||
__sdram_bss_end__ = .;
|
||||
. = ALIGN(8);
|
||||
__sdram_heap_start__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.ram_image2.text :
|
||||
{
|
||||
|
|
@ -226,32 +255,6 @@ SECTIONS
|
|||
} > BD_RAM
|
||||
__ram_heap2_end__ = 0x10070000;
|
||||
|
||||
.sdr_text :
|
||||
{
|
||||
__sdram_data_start__ = .;
|
||||
*(.sdram.text*)
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_rodata :
|
||||
{
|
||||
*(.sdram.rodata*)
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_data :
|
||||
{
|
||||
*(.sdram.data*)
|
||||
__sdram_data_end__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_bss :
|
||||
{
|
||||
__sdram_bss_start__ = .;
|
||||
*(.uvc.ram.bss)
|
||||
*(.sdram.bss*)
|
||||
__sdram_bss_end__ = .;
|
||||
. = ALIGN(8);
|
||||
__sdram_heap_start__ = .;
|
||||
} > SDRAM_RAM
|
||||
__sdram_heap_end__ = 0x30200000;
|
||||
|
||||
.boot.head :
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue