diff --git a/.cproject b/.cproject
index 4556cc5..6790fff 100644
--- a/.cproject
+++ b/.cproject
@@ -830,6 +830,45 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -920,45 +959,14 @@
true
false
+
+ mingw32-make.exe
+ -s
+ runsdram
+ true
+ true
+ true
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Makefile b/Makefile
index ac92758..5158de2 100644
--- a/Makefile
+++ b/Makefile
@@ -5,7 +5,7 @@ mp: ram_all_mp
.PHONY: ram_all
ram_all:
- @$(MAKE) -f $(SDK_PATH)sdkbuild.mk
+ @$(MAKE) -f $(SDK_PATH)sdkbuild.mk
@$(MAKE) -f $(SDK_PATH)flasher.mk genbin1 genbin23
.PHONY: ram_all_mp
@@ -20,20 +20,42 @@ clean:
clean_all:
@$(MAKE) -f $(SDK_PATH)sdkbuild.mk clean_all
-.PHONY: flashburn runram reset test readfullflash flashwebfs
+.PHONY: flashburn runram reset test readfullflash flashwebfs flashboot
+flashboot:
+ @$(MAKE) -f $(SDK_PATH)flasher.mk flashboot
+
flashburn:
+ #JLinkGDB-WrFlash.bat
@$(MAKE) -f $(SDK_PATH)flasher.mk flashburn
flash_OTA:
@$(MAKE) -f $(SDK_PATH)flasher.mk flash_OTA
+
+webfs:
+ @$(MAKE) -f webfs.mk
+flashwebfs:
+ @$(MAKE) -f webfs.mk
+ @$(MAKE) -f $(SDK_PATH)flasher.mk flashwebfs
+ #JLinkGDB-WrWebFs.bat
runram:
+ #JLink-RunRAM.bat
@$(MAKE) --f $(SDK_PATH)flasher.mk runram
+runsdram:
+ #JLink-RunRAM.bat
+ @$(MAKE) --f $(SDK_PATH)flasher.mk runsdram
+
reset:
+ #JLink-Reset.bat
@$(MAKE) -f $(SDK_PATH)flasher.mk reset
+test:
+ JLink-RTL00ConsoleROM.bat
+ #@make -f flasher.mk test
+
readfullflash:
+ #JLink-RdFullFlash.bat
@$(MAKE) -f $(SDK_PATH)flasher.mk readfullflash
diff --git a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h
index 52870d2..f795cc7 100644
--- a/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h
+++ b/RTL00_SDKV35a/component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h
@@ -32,6 +32,7 @@
#include
#ifdef PLATFORM_FREERTOS
#include "freertos_service.h"
+#include "osdep_service.h"
#elif defined(PLATFORM_CMSIS_RTOS)
#include "rtx_service.h"
#endif
diff --git a/RTL00_SDKV35a/component/common/video/v4l2/inc/v4l2-dev.h b/RTL00_SDKV35a/component/common/video/v4l2/inc/v4l2-dev.h
index aaf74a8..aef8d6d 100644
--- a/RTL00_SDKV35a/component/common/video/v4l2/inc/v4l2-dev.h
+++ b/RTL00_SDKV35a/component/common/video/v4l2/inc/v4l2-dev.h
@@ -135,14 +135,14 @@ struct video_device
/* device info */
char name[32];
int vfl_type; /* device type,usally assign the define VFL_TYPE_XXX value */
- int vfl_dir; /* receiver, transmitter or m2m,usally assign the define VFL_DIR_XXX value */
+ int vfl_dir; /* +72(dec) receiver, transmitter or m2m,usally assign the define VFL_DIR_XXX value */
/* 'minor' is set to -1 if the registration failed */
int minor;
u16 num; /* record the registered video device node number */
/* use bitops to set/clear/test flags,usally assign the define VFL_FL_XXX value */
unsigned long flags;
/* attribute to differentiate multiple indices on one physical device */
- int index;
+ int index; // +88(dec)
/* V4L2 file handles */
//spinlock_t fh_lock; /* Lock for all v4l2_fhs */
diff --git a/RTL00_SDKV35a/component/os/freertos/freertos_v9.0.0/Source/portable/MemMang/heap_5.c b/RTL00_SDKV35a/component/os/freertos/freertos_v9.0.0/Source/portable/MemMang/heap_5.c
index b2e9f57..476955b 100644
--- a/RTL00_SDKV35a/component/os/freertos/freertos_v9.0.0/Source/portable/MemMang/heap_5.c
+++ b/RTL00_SDKV35a/component/os/freertos/freertos_v9.0.0/Source/portable/MemMang/heap_5.c
@@ -173,7 +173,7 @@ static size_t xMinimumEverFreeBytesRemaining = 0;
#include "section_config.h"
SRAM_HEAP_SECTION
#endif
-unsigned char ucHeap[configTOTAL_HEAP_SIZE];
+unsigned char ucHeap[16384]; //configTOTAL_HEAP_SIZE
//extern void * __sdram_bss_end__;
//extern void * __ram_heap1_start__, __ram_heap1_end__, __ram_heap2_start__, __sdram_data_start__;
diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c
index 2199afc..5200357 100644
--- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c
+++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c
@@ -1,5 +1,5 @@
/*
- * BootLoader Ver 0.2
+ * BootLoader Ver 0.3 (18/10/2017)
* Created on: 12/02/2017
* Author: pvvx
*/
@@ -8,6 +8,7 @@
#include "rtl_bios_data.h"
#include "diag.h"
#include "rtl8195a/rtl8195a_sys_on.h"
+#include "rtl8195a/rtl8195a_sdr.h"
#include "hal_spi_flash.h"
@@ -30,7 +31,7 @@
#define DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE (DEFAULT_BOOT_CLK_CPU-6)
#endif
#endif // DEFAULT_BOOT_CLK_CPU
-
+#define FIX_SDR_CALIBRATION // for speed and low used SRAM
#define BOOT_RAM_TEXT_SECTION // __attribute__((section(".boot.text")))
//-------------------------------------------------------------------------
@@ -65,7 +66,6 @@ extern _LONG_CALL_ VOID HalInitPlatformLogUartV02(VOID);
extern _LONG_CALL_ VOID HalInitPlatformTimerV02(VOID);
//extern _LONG_CALL_ VOID DramInit_rom(IN DRAM_DEVICE_INFO *DramInfo);
//extern _LONG_CALL_ u32 SdrCalibration_rom(VOID);
-extern _LONG_CALL_ int SdrControllerInit_rom(PDRAM_DEVICE_INFO pDramInfo);
extern _LONG_CALL_ u32 SpicCmpDataForCalibrationRtl8195A(void); // compare read_data and golden_data
//extern _LONG_CALL_ VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara); // wait spi-flash status register[0] = 0
//extern _LONG_CALL_ VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara);
@@ -100,14 +100,14 @@ LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() {
CfgSysDebugErr = -1;
ConfigDebugWarn = -1;
// ConfigDebugInfo = 0;
- ConfigDebugErr = -1;
+ ConfigDebugErr = -1; // ~_DBG_SDR_;
#elif CONFIG_DEBUG_LOG > 0
// CfgSysDebugWarn = 0;
// CfgSysDebugInfo = 0;
CfgSysDebugErr = -1;
// ConfigDebugWarn = 0;
// ConfigDebugInfo = 0;
- ConfigDebugErr = -1;
+ ConfigDebugErr = -1; // ~_DBG_SDR_;
#else
// CfgSysDebugWarn = 0;
// CfgSysDebugInfo = 0;
@@ -125,15 +125,6 @@ LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) {
HalPinCtrlRtl8195A(JTAG, 0, 1);
}
-/* GetChipId() */
-LOCAL uint8 INFRA_START_SECTION _Get_ChipId() {
- uint8 ChipId = CHIP_ID_8710AF;
- if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
- &ChipId, L25EOUTVOLTAGE) != 1)
- DBG_8195A("Get Chip ID Failed\r");
- return ChipId;
-}
-
/*
* 16 bytes FIFO ... 16*11/38400 = 0.004583 sec
* (0.005/5)*166666666 = 166666.666 Tcpu
@@ -281,11 +272,130 @@ LOCAL int BOOT_RAM_TEXT_SECTION InitSpic(uint8 SpicBitMode) {
}
ACTCK_FLASH_CCTRL(1);
SLPCK_FLASH_CCTRL(1);
- HalPinCtrlRtl8195A(SPI_FLASH, 0, 1);
+ HalPinCtrlRtl8195A(SPI_FLASH, 0, ON);
InitSpicFlashType(&spic_table_flash);
return SetSpicBitMode(SpicBitMode);
}
+#ifdef CONFIG_SDR_EN
+
+/* GetChipId() */
+LOCAL uint8 INFRA_START_SECTION _Get_ChipId() {
+ uint8 ChipId = CHIP_ID_8710AF;
+ if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
+ &ChipId, L25EOUTVOLTAGE) != 1)
+ DBG_8195A("Get Chip ID Failed\r");
+ return ChipId;
+}
+
+LOCAL void INFRA_START_SECTION sdr_preinit(void) {
+
+ HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
+ ((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); // ROM: BIT_SYS_REGU_LDO25M_ADJ(0x0e)? HAL RAM BIT_SYS_REGU_LDO25M_ADJ(0x03)
+ LDO25M_CTRL(ON);
+ SRAM_MUX_CFG(0x2);
+ SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE); // REG_PESOC_CLK_SEL
+ HalPinCtrlRtl8195A(SDR, 0, ON); // SDR_PIN_FCTRL(ON);
+ ACTCK_SDR_CCTRL(ON);
+ SLPCK_SDR_CCTRL(ON);
+ HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4, 0);
+ MEM_CTRL_FCTRL(ON);
+// HalDelayUs(1000);
+}
+
+#ifndef FIX_SDR_CALIBRATION
+extern _LONG_CALL_ int SdrCalibration_rom(void);
+extern _LONG_CALL_ unsigned int Rand(void);
+extern _LONG_CALL_ int SdrControllerInit_rom(PDRAM_DEVICE_INFO pDramInfo);
+
+LOCAL int INFRA_START_SECTION sdr_test(u32 LoopCnt) {
+ u32 LoopIndex = 0;
+ u32 Value32, Addr;
+ for (LoopIndex = 0; LoopIndex < LoopCnt; LoopIndex++) {
+ Value32 = Rand();
+ Addr = Rand();
+ Addr &= 0x1FFFFF;
+ Addr &= (~0x3);
+ HAL_SDRAM_WRITE32(Addr, Value32);
+ if (HAL_SDRAM_READ32(Addr) != Value32)
+ return 0;
+ }
+ return 1;
+}
+#endif
+
+LOCAL int INFRA_START_SECTION sdr_init_from_flash(void) {
+#define RdPipe 0
+#if DEFAULT_BOOT_CLK_CPU < 6
+#define TapCnt 0x11
+ #elif DEFAULT_BOOT_CLK_CPU == 7
+#define TapCnt 0x23
+ #else
+#define TapCnt 0x19
+ #endif
+ // set all_mode _idle
+ HAL_SDR_WRITE32(REG_SDR_CSR, 0x700);
+ // WRAP_MISC setting
+ HAL_SDR_WRITE32(REG_SDR_MISC, 0x00000001);
+ // PCTL setting
+ HAL_SDR_WRITE32(REG_SDR_DCR, 0x00000008);
+ HAL_SDR_WRITE32(REG_SDR_IOCR, RdPipe << PCTL_IOCR_RD_PIPE_BFO);
+ HAL_SDR_WRITE32(REG_SDR_EMR2, 0x00000000);
+ HAL_SDR_WRITE32(REG_SDR_EMR1, 0x00000006);
+ HAL_SDR_WRITE32(REG_SDR_MR, 0x00000022);
+ HAL_SDR_WRITE32(REG_SDR_DRR, 0x09030e07);
+ HAL_SDR_WRITE32(REG_SDR_TPR0, 0x00002652);
+ HAL_SDR_WRITE32(REG_SDR_TPR1, 0x00068873);
+ HAL_SDR_WRITE32(REG_SDR_TPR2, 0x00000042);
+ // start to init
+ HAL_SDR_WRITE32(REG_SDR_CCR, 0x01);
+ DBG_8195A("SDR calibration: %02x-%02x\n", RdPipe, TapCnt);
+ while ((HAL_SDR_READ32(REG_SDR_CCR) & 0x1) == 0x0);
+ // enter mem_mode
+ HAL_SDR_WRITE32(REG_SDR_CSR, 0x600);
+#ifdef FIX_SDR_CALIBRATION
+ SDR_DDL_FCTRL(TapCnt); // SDR_DDL_FCTRL(0x11);
+ return 1;
+#else
+ union { u8 b[8]; u16 s[4]; u32 l[2]; u64 d;} value;
+ // read calibration data from system data FLASH_SDRC_PARA_BASE
+ u32 reg = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1);
+ u32 faddr = SPI_FLASH_BASE + FLASH_SDRC_PARA_BASE + ((reg & 0x70) >> 1) + ((reg & BIT17) >> 11) ; // step 8 in FLASH_SDRC_PARA_BASE[64 + 64 bytes]
+ value.d = *((volatile u64 *)faddr);
+ DBG_8195A("SDR flash calibration [%08x] %02x-%02x-%02x\n", faddr, value.b[0], value.b[4], value.b[6]);
+ if(value.s[0] == 0xFE01 && (value.b[4]^value.b[5]) == 0xFF && (value.b[6]^value.b[7]) == 0xFF) {
+ HAL_SDR_WRITE32(REG_SDR_IOCR, (HAL_SDR_READ32(REG_SDR_IOCR) & 0xff) | ((u32)value.b[4] << PCTL_IOCR_RD_PIPE_BFO));
+ SDR_DDL_FCTRL((u32)value.b[6]);
+ if(sdr_test(7))
+ return 1; // ok
+ else
+ DBG_8195A("Not valid SDR calibration in flash!\n");
+ } else
+ DBG_8195A("Error SDR calibration in flash!\n");
+ if(SdrCalibration_rom()) { // Внимание: дает завышенный TapCnt !
+// DBG_8195A("SDR calibration: %02x-%02x-%02x\n", value.b[0], value.b[4], value.b[6]);
+ value.s[0] = 0xFE01;
+ value.b[4] = HAL_SDR_READ32(REG_SDR_IOCR) >> PCTL_IOCR_RD_PIPE_BFO;
+ value.b[5] = value.b[4] ^ 0xFF;
+ value.b[6] = HAL_PERI_ON_READ32(REG_PESOC_MEM_CTRL) >> BIT_SHIFT_PESOC_SDR_DDL_CTRL;
+ value.b[7] = value.b[6] ^ 0xFF;
+ // DBG_8195A("%08x: %02x-%02x-%02x)\n", faddr, value.b[0], value.b[4], value.b[6]);
+ if((*((volatile u16 *)(faddr)) & value.s[0]) == value.s[0]
+ && (*((volatile u32 *)(faddr + 4)) & value.l[1]) == value.l[1]) {
+ *((volatile u32 *)(faddr + 4)) = value.l[1];
+ DBG_8195A("Write new calibration [%08x] %02x-%02x-%02x\n", faddr, value.b[0], value.b[4], value.b[6]);
+ HalDelayUs(1000);
+ *((volatile u16 *)(faddr)) = value.s[0];
+ } else {
+ DBG_8195A("Work recalibration: %02x-%02x-%02x!\n", value.b[0], value.b[4], value.b[6]);
+ }
+ return 2; // recalibration - ok
+ } else
+ DBG_8195A("SDR recalibration fail!\n");
+ return 0;
+#endif // FIX_SDR_CALIBRATION
+}
+#endif // CONFIG_SDR_EN
/* SYSPlatformInit */
LOCAL void INFRA_START_SECTION SYSPlatformInit(void) {
@@ -562,35 +672,36 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
else
DBG_8195A("\r===== Enter SRAM-Boot %d ====\n", flg);
#if CONFIG_DEBUG_LOG > 1
- DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(),
+ DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\n", HalGetCpuClk(),
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
#endif
+#ifdef CONFIG_SDR_EN
uint8 ChipId = _Get_ChipId();
if (ChipId < CHIP_ID_8195AM) {
+#endif
//----- SDRAM Off
SDR_PIN_FCTRL(OFF);
LDO25M_CTRL(OFF);
- HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init
+#ifdef CONFIG_SDR_EN
+ HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init or None
} else {
//----- SDRAM On
- LDO25M_CTRL(ON);
- HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
- (HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x0e));
- SDR_PIN_FCTRL(ON);
+ sdr_preinit();
};
+#endif
if (!InitSpic(SpicDualBitMode)) {
- DBG_8195A("Spic Init Error!\n");
+ DBG_8195A("Spic Init fail!\n");
RtlConsolRam();
};
- if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // Flag SDRAM Init?
-// extern DRAM_DEVICE_INFO SdrDramInfo_rom; // 50 MHz
- if (!SdrControllerInit_rom(&SdrDramInfo)) { // 100 MHz
- DBG_8195A("SDR Controller Init fail!\n");
+#ifdef CONFIG_SDR_EN
+ if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // Flag SDRAM No ReInit?
+ if(!sdr_init_from_flash()) {
+ DBG_8195A("SDR Init fail!\n");
RtlConsolRam();
}
-#if 0 // Test SDRAM
+#ifdef USE_SDRAM_TEST // Test SDRAM
else {
- uint32 *ptr = SDR_SDRAM_BASE;
+ uint32 *ptr = (uint32 *)SDR_SDRAM_BASE;
uint32 tt = 0x55AA55AA;
for (int i = 0; i < 512 * 1024; i++) {
ptr[i] = tt++;
@@ -601,23 +712,26 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
DBG_8195A("SDR err %p %p != %p!\n", &ptr[i], ptr[i], tt);
RtlConsolRam();
}
+// ptr[i] = 0;
tt++;
};
- DBG_8195A("SDR tst end\n");
+ DBG_8195A("SDR test ok\n");
};
#endif // Test SDRAM
-#ifdef CONFIG_SDR_EN
// Тест и ожидание загрузки Jlink-ом sdram.bin (~7 sec)
if(flg && *((uint32 *)0x1FFF0000) == 0x12345678) {
*((volatile uint32 *)0x1FFF0000) = 0x87654321;
uint32 tt = 0x03ffffff; // ~7 sec
DBG_8195A("Waiting for SDRAM to load...\n");
+// __asm__ __volatile__ ("cpsid f\n");
while(*((volatile uint32 *)0x1FFF0000) == 0x87654321 && tt--);
+// __asm__ __volatile__ ("cpsie f\n");
+ if(*((volatile uint32 *)0x1FFF0000) == 1)
+ DBG_8195A("SDRAM load ok\n");
}
-#endif // test
- HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init
+ HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM No ReInit
};
-
+#endif // CONFIG_SDR_EN
if (!flg)
loadUserImges(IsForceLoadDefaultImg2() + 1);
diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c
index c09b301..13621a3 100644
--- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c
+++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c
@@ -1,5 +1,5 @@
/*
- * StartUp SDK
+ * StartUp USDK v0.2 (19/10/2017)
* Created on: 02/03/2017
* Author: pvvx
*/
@@ -41,6 +41,7 @@ void SDIO_Device_Off(void);
//void VectorTableOverrideRtl8195A(u32 StackP);
void SYSPlatformInit(void);
+#define FIX_SDR_CALIBRATION // for speed :)
//-------------------------------------------------------------------------
// Data declarations
extern u8 __bss_start__, __bss_end__;
@@ -49,7 +50,63 @@ extern const unsigned char cus_sig[32]; // images name
IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 =
{ InfraStart + 1 };
-
+#ifdef CONFIG_SDR_EN
+#ifdef FIX_SDR_CALIBRATION // for speed :)
+#include "rtl8195a/rtl8195a_sdr.h"
+LOCAL void sdr_init(void) {
+ HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
+ ((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); // ROM: BIT_SYS_REGU_LDO25M_ADJ(0x0e)? HAL RAM BIT_SYS_REGU_LDO25M_ADJ(0x03)
+ LDO25M_CTRL(ON);
+ SRAM_MUX_CFG(0x2);
+ SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE); // REG_PESOC_CLK_SEL
+ HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4, 0);
+ ACTCK_SDR_CCTRL(ON);
+ SLPCK_SDR_CCTRL(ON);
+ HalPinCtrlRtl8195A(SDR, 0, ON); // SDR_PIN_FCTRL(ON);
+ MEM_CTRL_FCTRL(ON);
+// HalDelayUs(1000);
+ // read calibration data from system data FLASH_SDRC_PARA_BASE
+ union { u8 b[8]; u16 s[4]; u32 l[2]; u64 d;} value;
+ u32 faddr = SPI_FLASH_BASE + FLASH_SDRC_PARA_BASE + CPU_CLOCK_SEL_VALUE*8 + CPU_CLOCK_SEL_DIV5_3*8*8; // step 8 in FLASH_SDRC_PARA_BASE[64 + 64 bytes]
+ value.d = *((volatile u64 *)faddr);
+ if(value.s[0] == 0xFE01 && (value.b[4]^value.b[5]) == 0xFF && (value.b[6]^value.b[7]) == 0xFF) {
+ DBG_8195A("SDR flash calibration [%08x]: %02x-%02x ", faddr, value.b[4], value.b[6]);
+ } else {
+ value.b[4] = 0; // TapCnt
+#if CONFIG_CPU_CLK < 6
+ value.b[6] = 0x11; // RdPipe
+#elif CONFIG_CPU_CLK == 7
+ value.b[6] = 0x23; // RdPipe
+#else
+ value.b[6] = 0x19; // RdPipe
+#endif
+ DBG_8195A("Use fix SDR calibration: %02x-%02x ", value.b[4], value.b[6]);
+ }
+ // set all_mode _idle
+ HAL_SDR_WRITE32(REG_SDR_CSR, 0x700);
+ // WRAP_MISC setting
+ HAL_SDR_WRITE32(REG_SDR_MISC, 0x00000001);
+ // PCTL setting
+ HAL_SDR_WRITE32(REG_SDR_DCR, 0x00000008);
+ HAL_SDR_WRITE32(REG_SDR_IOCR, (u32)value.b[4] << PCTL_IOCR_RD_PIPE_BFO);
+ HAL_SDR_WRITE32(REG_SDR_EMR2, 0x00000000);
+ HAL_SDR_WRITE32(REG_SDR_EMR1, 0x00000006);
+ HAL_SDR_WRITE32(REG_SDR_MR, 0x00000022);
+ HAL_SDR_WRITE32(REG_SDR_DRR, 0x09030e07);
+ HAL_SDR_WRITE32(REG_SDR_TPR0, 0x00002652);
+ HAL_SDR_WRITE32(REG_SDR_TPR1, 0x00068873);
+ HAL_SDR_WRITE32(REG_SDR_TPR2, 0x00000042);
+ // start to init
+ HAL_SDR_WRITE32(REG_SDR_CCR, 0x01);
+ while ((HAL_SDR_READ32(REG_SDR_CCR) & 0x1) == 0x0)
+ DBG_8195A(".");
+ // enter mem_mode
+ HAL_SDR_WRITE32(REG_SDR_CSR, 0x600);
+ SDR_DDL_FCTRL((u32)value.b[6]);
+ DBG_8195A(" ok\n");
+}
+#endif // FIX_SDR_CALIBRATION
+#endif // CONFIG_SDR_EN
/*
//----- HalNMIHandler_Patch
void HalNMIHandler_Patch(void) {
@@ -167,30 +224,36 @@ extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
};
*/
// SpicFlashInitRtl8195A(SpicDualBitMode); // SpicReadIDRtl8195A(); SpicDualBitMode
+#ifdef CONFIG_SDR_EN
//---- SDRAM
uint8 ChipId = HalGetChipId();
if (ChipId >= CHIP_ID_8195AM) {
-#ifdef CONFIG_SDR_EN
- if((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена?
+ if((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // SDR not init?
+ #ifdef FIX_SDR_CALIBRATION // for speed :)
+ sdr_init();
+ #else // not FIX_SDR_CALIBRATION
SdrCtrlInit();
- if(SdrControllerInit()) {
+ if(!SdrControllerInit()) {
DBG_8195A("SDR Controller Init fail!\n");
};
+ #endif // FIX_SDR_CALIBRATION
};
-#endif
// clear SDRAM bss
extern uint8 __sdram_bss_start__[];
extern uint8 __sdram_bss_end__[];
if((uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__ > 0)
memset(__sdram_bss_start__, 0, (uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__);
}
- else
+ else // if (ChipId < CHIP_ID_8195AM)
{
//----- SDRAM Off
SDR_PIN_FCTRL(OFF);
LDO25M_CTRL(OFF);
- HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off
};
+ HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init or None
+#else
+ HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (~BIT(21))); // Flag SDRAM Not Init
+#endif // CONFIG_SDR_EN
//----- Close Flash
SPI_FLASH_PIN_FCTRL(OFF);
diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h
index ac2ad51..57cd065 100644
--- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h
+++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h
@@ -24,7 +24,7 @@
//2 REG_NOT_VALID
//2 REG_SOC_FUNC_EN
-// BIT(21) SDRAM
+// BIT(21) if 1 -> SDRAM No ReInit
#define BIT_SOC_SECURITY_ENGINE_EN BIT(20)
#define BIT_SOC_GTIMER_EN BIT(16)
#define BIT_SOC_GDMA1_EN BIT(14)
diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c
index 1051f1d..a9ffdc8 100644
--- a/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c
+++ b/RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c
@@ -432,6 +432,7 @@ VOID
else {
return 1;
}
+ return 1;
}
@@ -1056,19 +1057,19 @@ MemTest(
{
u32 LoopIndex = 0;
u32 Value32, Addr;
- for (LoopIndex = 0; LoopIndex 0x%x != 0x%x\n",LoopIndex,
- Addr, Value32, HAL_SDRAM_READ32(Addr));
+ HAL_SDRAM_WRITE32(Addr, Value32);
+ u32 x = HAL_SDRAM_READ32(Addr);
+// DBG_8195A("[%p] %p %p\n", Addr, Value32, x);
+
+ if (x != Value32) {
+ DBG_8195A("Test %d: No match addr 0x%x => 0x%x != 0x%x\n", LoopIndex,
+ Addr, Value32, x);
return _FALSE;
}
else {
diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld
index b23a7ed..ee6e374 100644
--- a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld
+++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld
@@ -177,6 +177,7 @@ SECTIONS
LONG(0)
UartLogRamCmdTable = .;
KEEP(*(SORT(.mon.tab*)))
+ KEEP(*(SORT(.sdram.mon.tab*)))
UartLogRamCmdTable_end = .;
LONG(0)
} > BD_RAM
diff --git a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img3.ld b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img3.ld
index 31d2c9e..4b39069 100644
--- a/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img3.ld
+++ b/RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img3.ld
@@ -121,6 +121,35 @@ SECTIONS
KEEP(*(.image2.validate.rodata*))
KEEP(*(.custom.validate.rodata*))
} > BD_RAM
+
+ .sdr_text :
+ {
+ __sdram_data_start__ = .;
+ INCLUDE "sdram_obj.txt"
+ *(.sdram.text*)
+ } > SDRAM_RAM
+
+ .sdr_rodata :
+ {
+ *(.sdram.rodata*)
+ } > SDRAM_RAM
+
+ .sdr_data :
+ {
+ *(.sdram.data*)
+ __sdram_data_end__ = .;
+ } > SDRAM_RAM
+
+ .sdr_bss :
+ {
+ __sdram_bss_start__ = .;
+ *(.uvc.ram.bss)
+ *(.sdram.bss*)
+ INCLUDE "sdram_bss.txt"
+ __sdram_bss_end__ = .;
+ . = ALIGN(8);
+ __sdram_heap_start__ = .;
+ } > SDRAM_RAM
.ram_image2.text :
{
@@ -226,32 +255,6 @@ SECTIONS
} > BD_RAM
__ram_heap2_end__ = 0x10070000;
- .sdr_text :
- {
- __sdram_data_start__ = .;
- *(.sdram.text*)
- } > SDRAM_RAM
-
- .sdr_rodata :
- {
- *(.sdram.rodata*)
- } > SDRAM_RAM
-
- .sdr_data :
- {
- *(.sdram.data*)
- __sdram_data_end__ = .;
- } > SDRAM_RAM
-
- .sdr_bss :
- {
- __sdram_bss_start__ = .;
- *(.uvc.ram.bss)
- *(.sdram.bss*)
- __sdram_bss_end__ = .;
- . = ALIGN(8);
- __sdram_heap_start__ = .;
- } > SDRAM_RAM
__sdram_heap_end__ = 0x30200000;
.boot.head :
diff --git a/RTL00_SDKV35a/flasher.mk b/RTL00_SDKV35a/flasher.mk
index c58c047..93a1b3e 100644
--- a/RTL00_SDKV35a/flasher.mk
+++ b/RTL00_SDKV35a/flasher.mk
@@ -90,7 +90,7 @@ mp: OTA_IMAGE = $(BIN_DIR)/ota_mp.bin
TST_IMAGE = $(BIN_DIR)/ram_2.bin
-.PHONY: genbin1 genbin23 flashburn reset test readfullflash flashwebfs flash_OTA
+.PHONY: genbin1 genbin23 flashburn reset test readfullflash flashwebfs flash_OTA falshboot runsdram
.NOTPARALLEL: all mp genbin1 genbin23 flashburn reset test readfullflash _endgenbin flashwebfs flash_OTA
all: $(ELFFILE) $(OTA_IMAGE) $(FLASH_IMAGE) _endgenbin
@@ -113,11 +113,13 @@ reset:
@$(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed 1000 $(FLASHER_PATH)RTL_Reset.JLinkScript
runram:
- @$(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed 1000 $(FLASHER_PATH)RTL_RunRAM.JLinkScript
+ $(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed 1000 $(FLASHER_PATH)RTL_RunRAM.JLinkScript
+
+runsdram:
+ $(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed 1000 $(FLASHER_PATH)RTL_RunRAM_SDR.JLinkScript
readfullflash:
@$(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed 1000 $(FLASHER_PATH)RTL_FFlash.JLinkScript
-
flashburn:
@echo define call1>$(FLASHER_PATH)flash_file.jlink
@@ -145,6 +147,18 @@ flashwebfs:
@$(GDB) -x $(FLASHER_PATH)gdb_wrfile.jlink
#@taskkill /F /IM $(JLINK_GDBSRV)
+flashboot:
+ @echo define call1>$(FLASHER_PATH)file_info.jlink
+ @echo set '$$'ImageSize = $(shell printf '0x%X\n' $$(stat --printf="%s" $(RAM1P_IMAGE)))>>$(FLASHER_PATH)file_info.jlink
+ @echo set '$$'ImageAddr = 0x00000>>$(FLASHER_PATH)file_info.jlink
+ @echo end>>$(FLASHER_PATH)file_info.jlink
+ @echo define call2>>$(FLASHER_PATH)file_info.jlink
+ @echo FlasherWrite $(RAM1P_IMAGE) '$$'ImageAddr '$$'ImageSize>>$(FLASHER_PATH)file_info.jlink
+ @echo end>>$(FLASHER_PATH)file_info.jlink
+ @cmd /K start $(JLINK_PATH)$(JLINK_GDBSRV) -device Cortex-M3 -if SWD -ir -endian little -speed 1000
+ @$(GDB) -x $(FLASHER_PATH)gdb_wrfile.jlink
+
+
flashespfs:
@echo define call1>$(FLASHER_PATH)file_info.jlink
@echo set '$$'ImageSize = $(shell printf '0x%X\n' $$(stat --printf="%s" $(BIN_DIR)/webpages.espfs))>>$(FLASHER_PATH)file_info.jlink
@@ -184,6 +198,12 @@ flashwebfs:
-c "rtl8710_flash_write $(BIN_DIR)/WEBFiles.bin 0xd0000" \
-c "rtl8710_reboot" -c "reset run" -c shutdown
+flashboot:
+ @$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \
+ -c "rtl8710_flash_auto_erase 1" -c "rtl8710_flash_auto_verify 1" \
+ -c "rtl8710_flash_write $(RAM1P_IMAGE) 0" \
+ -c "rtl8710_reboot" -c "reset run" -c shutdown
+
flashespfs:
@$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \
-c "rtl8710_flash_auto_erase 1" -c "rtl8710_flash_auto_verify 1" \
@@ -194,7 +214,7 @@ reset:
# @$(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed $(FLASHER_SPEED) flasher/RTLreset.JLinkScript
@$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \
-c "rtl8710_reboot" -c shutdown
-
+
runram:
# @$(JLINK_PATH)$(JLINK_GDB) -device Cortex-M3 -if SWD -ir -endian little -speed $(FLASHER_SPEED)
# @$(GDB) -x flasher/gdb_run_ram.jlink
diff --git a/RTL00_SDKV35a/flasher/RTL_RunRAM.JLinkScript b/RTL00_SDKV35a/flasher/RTL_RunRAM.JLinkScript
index 5991456..f8b665b 100644
--- a/RTL00_SDKV35a/flasher/RTL_RunRAM.JLinkScript
+++ b/RTL00_SDKV35a/flasher/RTL_RunRAM.JLinkScript
@@ -7,6 +7,6 @@ r
loadbin build/bin/ram_1.r.bin 0x10000bc8
loadbin build/bin/ram_2.bin 0x10006000
r
-w4 0x40000210,0x20111157
+w4 0x40000210,0x20011113
g
q
\ No newline at end of file
diff --git a/RTL00_SDKV35a/flasher/gdb_flasher.jlink b/RTL00_SDKV35a/flasher/gdb_flasher.jlink
index f3aa851..d6f2c97 100644
--- a/RTL00_SDKV35a/flasher/gdb_flasher.jlink
+++ b/RTL00_SDKV35a/flasher/gdb_flasher.jlink
@@ -38,37 +38,38 @@ set mem inaccessible-by-default off
# Setup GDB FOR FASTER DOWNLOADS
set remote memory-write-packet-size 8192
set remote memory-write-packet-size fixed
+set $SPI_FLASH_BASE = 0x98000000
end
#############
# Boot_Flash
define SetBootFlash
printf "SetBoot = Flash:\n"
-monitor long 0x40000210 = 0x211157
+monitor long 0x40000210 = 0x00011113
end
# Boot RAM start_addr0() Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 )
define SetBootCall0
printf "SetBoot = Call0:\n"
-monitor long 0x40000210 = 0x80111157
+monitor long 0x40000210 = 0x80011113
end
# Boot RAM start_addr1() Run if ( v40000210 & 0x20000000 )
define SetBootCall1
printf "SetBoot = Call1:\n"
-monitor long 0x40000210 = 0x20111157
+monitor long 0x40000210 = 0x20011113
end
# Boot RAM start_addr2() Run if ( v40000210 & 0x10000000 )
define SetBootCall2
printf "SetBoot = Call2:\n"
-monitor long 0x40000210 = 0x10111157
+monitor long 0x40000210 = 0x10011113
end
# Boot RAM start_addr3() Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
define SetBootCall3
printf "SetBoot = Call3:\n"
-monitor long 0x40000210 = 0x8111157
+monitor long 0x40000210 = 0x8011113
end
# Boot RAM start_addr4() Init console, Run if ( v40000210 & 0x4000000 )
define SetBootCall4
printf "SetBoot = Call4:\n"
-monitor long 0x40000210 = 0x4111157
+monitor long 0x40000210 = 0x4011113
end
# CPU CLK 166 MHz?
define SetClk166MHz
@@ -89,8 +90,7 @@ monitor long 0x40000304 = 0x1FC00002
monitor long 0x40000250 = 0x400
monitor long 0x40000340 = 0x0
monitor long 0x40000230 = 0xdcc4
-monitor long 0x40000210 = 0x11117
-monitor long 0x40000210 = 0x11157
+monitor long 0x40000210 = 0x11113
monitor long 0x400002c0 = 0x110011
monitor long 0x40000320 = 0xffffffff
end
@@ -125,7 +125,6 @@ monitor long 0x40006018 = 0
monitor long 0x4000601C = 0
#disable DMA
monitor long 0x4000604C = 0
-set $SPI_FLASH_BASE = 0x98000000
end
###################
# SetFirwareSize #
@@ -154,7 +153,26 @@ if $Image1Size != 0 && $Image1Size < 0x1000000
printf "Image2Size = %d\n", $Image2Size
printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
set $FirmwareSize = $Image2Addr + $Image2Size
- printf "FirmwareSize = %d\n", $FirmwareSize
+ set $Image3Addr = $FirmwareSize
+ set $parms1 = $rambuffer - $FirmwareSize
+ set $parms3 = $Image3Addr + 0x08
+ restore $arg0 binary $parms1 $Image3Addr $parms3
+ set $Image3Size = {int}($rambuffer)
+ set $Image3LoadAddr = {int}($rambuffer+0x4)
+ if $Image3Size != 0xFFFFFFFF && $Image3Size != 0
+ set $Image3Size = $Image3Size + 16
+ printf "Image3Size = %d\n", $Image3Size
+ printf "Image3LoadAddr = 0x%08x\n", $Image3LoadAddr
+ set $FirmwareSize = $Image3Addr + $Image3Size
+ printf "FirmwareSize = %d\n", $FirmwareSize
+ else
+ set $Image3Size = 0
+ if $Image3LoadAddr == 0x30000000
+ set $FirmwareSize = $FirmwareSize + 8
+ end
+ printf "Image3 - None\n"
+ printf "FirmwareSize = %d\n", $FirmwareSize
+ end
else
set $Image2Size = 0
printf "Image2 - None\n"
@@ -164,7 +182,9 @@ if $Image1Size != 0 && $Image1Size < 0x1000000
else
set $Image1Size = 0
set $Image2Size = 0
+ set $Image3Size = 0
set $Image2Addr = 0
+ set $Image3Addr = 0
set $FirmwareSize = 0
printf "Image not format Firmware!\n"
end
@@ -173,6 +193,10 @@ end
# Flash Images Info #
#####################
define FlashImagesInfo
+set $Image2Size = 0
+set $Image3Size = 0
+set $Image2Addr = 0
+set $Image3Addr = 0
printf "Flash Info:\n"
set $Image1Size = {int}($SPI_FLASH_BASE + 0x10) + 32
set $Image1LoadAddr = {int}($SPI_FLASH_BASE + 0x14)
@@ -181,16 +205,26 @@ printf "Image1 - None\n"
else
set $Image2FlashAddr = {short}($SPI_FLASH_BASE + 0x18) * 1024
if $Image2FlashAddr == 0
-$Image2FlashAddr = $Image1Size
+set $Image2FlashAddr = $Image1Size
end
set $Image2Size = {int}($Image2FlashAddr + $SPI_FLASH_BASE)
set $Image2LoadAddr = {int}($Image2FlashAddr + $SPI_FLASH_BASE + 0x4)
printf "Image1Size = %d\n", $Image1Size
printf "Image1LoadAddr = 0x%08x\n", $Image1LoadAddr
printf "Image2FlashAddr = 0x%08x\n", $Image2FlashAddr
-if $Image2Size != 0xFFFFFFFF
+if $Image2Size != 0xFFFFFFFF && $Image2Size != 0
printf "Image2Size = %d\n", $Image2Size
printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
+set $Image3FlashAddr = $Image2FlashAddr + $Image2Size + 0x10
+set $Image3Size = {int}($Image3FlashAddr + $SPI_FLASH_BASE)
+set $Image3LoadAddr = {int}($Image3FlashAddr + $SPI_FLASH_BASE + 0x4)
+if $Image3Size != 0xFFFFFFFF && $Image3Size !=0
+printf "Image3FlashAddr = 0x%08x\n", $Image3FlashAddr
+printf "Image3Size = %d\n", $Image3Size
+printf "Image3LoadAddr = 0x%08x\n", $Image3LoadAddr
+else
+printf "Image3 - None\n"
+end
else
printf "Image2 - None\n"
end
diff --git a/RTL00_SDKV35a/flasher/gdb_wrflash.jlink b/RTL00_SDKV35a/flasher/gdb_wrflash.jlink
index 4a4af92..0bceeb0 100644
--- a/RTL00_SDKV35a/flasher/gdb_wrflash.jlink
+++ b/RTL00_SDKV35a/flasher/gdb_wrflash.jlink
@@ -7,7 +7,6 @@ set $rtl8710_flasher_auto_erase = 1
set $rtl8710_flasher_auto_verify = 1
set $rtl8710_flasher_firmware_ptr = 0x10001000
set $rtl8710_flasher_buffer = 0x10008000
-#262144
set $rtl8710_flasher_buffer_size = 421888
set $rtl8710_flasher_sector_size = 4096
set $rtl8710_flasher_auto_erase_sector = 0xFFFFFFFF
@@ -37,12 +36,11 @@ if $rtl8710_flasher_capacity == 0
monitor go
FlasherWait
set $id = {int}($rtl8710_flasher_buffer + 0x0C)
+ set $rtl8710_flasher_capacity = 1 << (($id >> 16) & 0x0ff)
if ($id == 0x1420c2)
- set $rtl8710_flasher_capacity = 1 << (($id >> 16) & 0x0ff)
printf "Flash ID = 0x%08x : MX25L8006E (%d kbytes)\n", $id, $rtl8710_flasher_capacity>>10
else
- set $rtl8710_flasher_capacity = 1024*1024)
- error "Flash ID = 0x%08x : ?\n", $id
+ printf "Flash ID = 0x%08x : (%d kbytes)\n", $id, $rtl8710_flasher_capacity>>10
end
printf "RTL8710 flasher initialized\n"
else
@@ -108,9 +106,9 @@ while $offset < $size
end
set $flash_offset = $arg1 + $offset
printf "write offset 0x%08x\n", $flash_offset
- set $parms1 = $rtl8710_flasher_buffer + 0x20 - $offset - $arg1
- set $parms2 = $offset + $arg1
- set $parms3 = $offset + $len + $arg1
+ set $parms1 = $rtl8710_flasher_buffer + 0x20 - $flash_offset
+ set $parms2 = $flash_offset
+ set $parms3 = $flash_offset + $len
restore $arg0 binary $parms1 $parms2 $parms3
if $rtl8710_flasher_auto_erase != 0
set $count_i = $flash_offset
@@ -153,8 +151,13 @@ if $Image1Size != 0
printf "Write Image1 size %d to Flash addr 0x00000000:\n", $Image1Size
#FlasherWrite $wr_flile 0 $Image1Size
call2
- if $Image2Size != 0 && $Image2Addr >= $Image1Size
- printf "Write Image2 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
+ if $Image2Size != 0 && $Image2Addr >= $Image1Size
+ if $Image3Size != 0 && $Image3Addr > $Image2Size
+ set $Image2Size = $Image2Size + $Image3Size
+ printf "Write Image2&3 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
+ else
+ printf "Write Image2 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
+ end
#FlasherWrite $wr_flile $Image2Addr $Image2Size
call3
end
diff --git a/RTL00_SDKV35a/sdkset.mk b/RTL00_SDKV35a/sdkset.mk
index edd8123..0a82017 100644
--- a/RTL00_SDKV35a/sdkset.mk
+++ b/RTL00_SDKV35a/sdkset.mk
@@ -48,7 +48,12 @@ endif
# m c nosys gcc
PATHLIBS = sdk/component/soc/realtek/8195a/misc/bsp/lib/common/gcc
+ifdef USE_SDRAM
+CFLAGS += -DUSE_SDRAM=1
+LDFILE ?= rlx8195A-symbol-v04-img3.ld
+else
LDFILE ?= rlx8195A-symbol-v04-img2.ld
+endif
BOOTS = sdk/component/soc/realtek/8195a/misc/bsp/image
# Include folder list
@@ -138,8 +143,8 @@ SRC_C += sdk/component/common/api/wifi/wifi_simple_config.c
SRC_C += sdk/component/common/api/wifi/wifi_util.c
SRC_C += sdk/component/common/api/lwip_netconf.c
ifdef USE_WIFI_API
-SRC_C += sdk/component/common/api/wifi_api.c
-SRC_C += sdk/component/common/api/wifi_api_scan.c
+DRAM_C += sdk/component/common/api/wifi_api.c
+DRAM_C += sdk/component/common/api/wifi_api_scan.c
endif
#network - lwip
@@ -179,9 +184,9 @@ SRC_C += sdk/component/common/network/lwip/$(LWIPDIR)/src/netif/etharp.c
SRC_C += sdk/component/common/network/lwip/$(LWIPDIR)/port/realtek/freertos/ethernetif.c
SRC_C += sdk/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c
SRC_C += sdk/component/common/network/lwip/$(LWIPDIR)/port/realtek/freertos/sys_arch.c
-SRC_C += sdk/component/common/network/dhcp/dhcps.c
-SRC_C += sdk/component/common/network/sntp/sntp.c
-SRC_C += sdk/component/common/network/netbios/netbios.c
+DRAM_C += sdk/component/common/network/dhcp/dhcps.c
+DRAM_C += sdk/component/common/network/sntp/sntp.c
+DRAM_C += sdk/component/common/network/netbios/netbios.c
#network - mdns
#SRC_C += sdk/component/common/network/mDNS/mDNSPlatform.c
@@ -406,18 +411,18 @@ ADD_SRC_C =
# -------------------------------------------------------------------
ifdef USE_AT
INCLUDES += sdk/component/common/utilities
-ADD_SRC_C += sdk/component/common/api/network/src/wlan_network.c
-ADD_SRC_C += sdk/component/common/api/wifi_interactive_mode.c
-ADD_SRC_C += sdk/component/common/api/network/src/ping_test.c
-ADD_SRC_C += sdk/component/common/utilities/webserver.c
-ADD_SRC_C += sdk/component/common/utilities/tcptest.c
-ADD_SRC_C += sdk/component/common/utilities/update.c
+DRAM_C += sdk/component/common/api/network/src/wlan_network.c
+DRAM_C += sdk/component/common/api/wifi_interactive_mode.c
+DRAM_C += sdk/component/common/api/network/src/ping_test.c
+DRAM_C += sdk/component/common/utilities/webserver.c
+DRAM_C += sdk/component/common/utilities/tcptest.c
+DRAM_C += sdk/component/common/utilities/update.c
INCLUDES += sdk/component/common/example
INCLUDES += sdk/component/common/example/wlan_fast_connect
-ADD_SRC_C += sdk/component/common/example/wlan_fast_connect/example_wlan_fast_connect.c
-ADD_SRC_C += sdk/component/common/example/uart_atcmd/example_uart_atcmd.c
-ADD_SRC_C += sdk/component/common/example/example_entry.c
-ADD_SRC_C += sdk/component/common/application/xmodem/uart_fw_update.c
+DRAM_C += sdk/component/common/example/wlan_fast_connect/example_wlan_fast_connect.c
+DRAM_C += sdk/component/common/example/uart_atcmd/example_uart_atcmd.c
+DRAM_C += sdk/component/common/example/example_entry.c
+DRAM_C += sdk/component/common/application/xmodem/uart_fw_update.c
endif
#application
#INCLUDES += sdk/component/common/application/apple/WACServer/External/Curve25519
diff --git a/build/bin/ota.bin b/build/bin/ota.bin
index a951306..23fd19b 100644
Binary files a/build/bin/ota.bin and b/build/bin/ota.bin differ
diff --git a/build/bin/ram_1.p.bin b/build/bin/ram_1.p.bin
index 9bfdcd5..5d0d745 100644
Binary files a/build/bin/ram_1.p.bin and b/build/bin/ram_1.p.bin differ
diff --git a/build/bin/ram_2.bin b/build/bin/ram_2.bin
index a121397..bc2aec9 100644
Binary files a/build/bin/ram_2.bin and b/build/bin/ram_2.bin differ
diff --git a/build/bin/ram_2.ns.bin b/build/bin/ram_2.ns.bin
index 9846a71..6b86165 100644
Binary files a/build/bin/ram_2.ns.bin and b/build/bin/ram_2.ns.bin differ
diff --git a/build/bin/ram_2.p.bin b/build/bin/ram_2.p.bin
index ad689bb..a2cffef 100644
Binary files a/build/bin/ram_2.p.bin and b/build/bin/ram_2.p.bin differ
diff --git a/build/bin/ram_all.bin b/build/bin/ram_all.bin
index d5289cf..6c631e3 100644
Binary files a/build/bin/ram_all.bin and b/build/bin/ram_all.bin differ
diff --git a/build/obj/build.nmap b/build/obj/build.nmap
index 53253b0..361a7b3 100644
--- a/build/obj/build.nmap
+++ b/build/obj/build.nmap
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-10027bb8 T rtw_tkip_encrypt
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-10028648 T Set_MSR
-1002866c T set_opmode
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-10028acc T HTOnAssocRsp
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-10028ebc T update_basic_rate
-10028eea T update_supported_rate
-10028f14 T update_MCS_rate
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-10028f4e T get_highest_rate_idx
-10028f68 T Update_RA_Entry
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-10028f78 T update_tx_basic_rate
-10028fd0 T check_assoc_AP
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-10029122 T update_capinfo
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-1002a494 T rtw_xmit
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-1002ad40 T rtl8195a_reset_desc_ring
-1002add6 T InitLxDmaRtl8195a
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-1002b144 T EnableDMA8195a
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-1002b1ac T DisableDMA8195a
-1002b1b8 T DisableInterrupt8195a
-1002b1d0 T UpdateInterruptMask8195a
-1002b232 T CheckRxTgRtl8195a
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-1002b29c T rtl8195a_recv_tasklet
-1002b5b0 T rtl8195a_tx_int_handler
-1002b5dc T InterruptHandle8195a
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-1002b934 t check_nic_enough_desc.isra.4
-1002b984 T rtl8195ab_init_xmit_priv
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-1002b99a T GetDmaTxbdIdx
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-1002b9da T rtl8195a_dequeue_xmitbuf
-1002b9fe T SetTxbdForLxDMARtl8195ab
-1002ba7e T UpdateTxbdHostIndex
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-1002bcc8 T rtw_dequeue_xframe
-1002bd5c T rtw_xmitframe_coalesce
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-1002c2c4 T UpdateHalRAMask8195A
-1002c45c T HalLittleWifiMCUThreadRtl8195a
-1002c4b0 T HalCheckInReqStateThreadRtl8195a
-1002c4fc T HalTDMAChangeStateThreadRtl8195a
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-1002c998 T rtl8195a_stop_thread
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-1002cb2c T GetHalODMVar8195A
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-1002d1be T _InitBurstPktLen_8195AB
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-1002d2f4 T Hal_GetChnlGroup8195A
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-1002d674 T Hal_EfuseParseEEPROMVer_8195A
-1002d68a T Hal_EfuseParsePackageType_8195A
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-1002d73a T Hal_EfuseParseXtal_8195A
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-1002d7ca T BWMapping_8195A
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-1002e9d4 T GetHalDefVar8195A
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-1002f5f4 T InitGTimer1ms
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-1002f688 T ChangeTransmiteRate
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-1002f7a4 T IssueRsvdPagePacketSetting
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-1002fb8c T PS_S2ToS0State
-1002fba8 T PS_S3ToS2orS0State
-1002fbd8 T PS_S0ToS1ToS2State
-1002fc34 T PS_S1ToS0orS2State
-1002fc64 T PS_S2ToS4State
-1002fcb0 T PS_S0ToS6State
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-10030c42 T ISR_RxUCMD0
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-100317cc T PHY_GetRateValuesOfTxPowerByRate
-10031964 T PHY_StoreTxPowerByRateNew
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-10031a18 T PHY_StoreTxPowerByRate
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-10031afc T PHY_GetRateIndexOfTxPowerByRate
-10031b10 T PHY_GetTxPowerByRate
-10031b70 T phy_StoreTxPowerByRateBase
-10031bbc T PHY_SetTxPowerByRate
-10031bf8 T phy_ConvertTxPowerByRateInDbmToRelativeValues
-10031cf8 T PHY_TxPowerByRateConfiguration
-10031d0a T PHY_SetTxPowerIndexByRateArray
-10031d48 T PHY_SetTxPowerIndexByRateSection
-10031dac T PHY_SetTxPowerLevelByPath
-10031de2 T phy_GetWorldWideLimit
-10031e0e T PHY_GetTxPowerLimit
-10031f38 T PHY_ConvertTxPowerLimitToPowerIndex
-10032088 T PHY_InitTxPowerLimit
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-1003214c T PHY_GetTxPowerIndex
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-10032188 T rtw_hal_read_chip_version
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-100321f6 T rtw_hal_init
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-10032268 T rtw_hal_get_def_var
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-100322b8 T rtw_hal_disable_interrupt
-100322da T rtw_hal_inirp_init
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-100322fe T rtw_hal_irp_reset
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-1003231e T rtw_hal_mgnt_xmit
-10032330 T rtw_hal_init_xmit_priv
-10032342 T rtw_hal_free_xmit_priv
-10032350 T rtw_hal_update_ra_mask
-1003237e T rtw_hal_add_ra_tid
-1003238c T rtw_hal_clone_data
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-100323ea T rtw_hal_write_bbreg
-10032416 T rtw_hal_read_rfreg
-10032428 T rtw_hal_write_rfreg
-1003243c T rtw_hal_interrupt_handler
-1003244e T rtw_hal_set_bwmode
-1003245c T rtw_hal_set_chan
-1003246a T rtw_hal_set_chnl_bw
-10032480 T rtw_hal_dm_watchdog
-10032496 T rtw_hal_macid_sleep
-100324b6 T rtw_hal_macid_wakeup
-100324d6 T decide_chip_type_by_device_id
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-10032642 T rtw_os_indicate_connect
-10032646 T rtw_os_indicate_scan_done
-1003264a T rtw_reset_securitypriv
-1003273e T rtw_os_indicate_disconnect
-10032788 T rtw_init_netdev
-100328d8 T rtw_drv_if2_init
-10032ae0 T rtw_drv_if2_stop
-10032b36 T rtw_drv_if2_free
-10032b84 T _netdev_open
-10032ca0 T _netdev_if2_open
-10032d5c T netdev_if2_open
-10032d84 T netdev_open
-10032dac T rtw_drv_probe
-10032f2c T rtw_dev_remove
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+1003c9a8 t __rtw_set_ie_veneer
+1003c9b0 t __tkip_80211_decrypt_veneer
+1003c9b8 t __rt_arc4_crypt_veneer
+1003c9c0 t __ROM_odm_EVMdbToPercentage_veneer
+1003c9c8 t __CmdWriteWord_veneer
+1003c9d0 t __aes_80211_decrypt_veneer
+1003c9d8 t __ROM_odm_QueryRxPwrPercentage_veneer
+1003c9e0 t __rtw_get_sec_ie_veneer
+1003c9e8 t __ROM_ODM_CfoTrackingReset_veneer
+1003c9f0 t __HalI2SWrite32_veneer
+1003c9f8 t __AES_UnWRAP_veneer
+1003ca00 t __HalI2SIntrCtrlRtl8195a_veneer
+1003ca08 t __rtw_ieee802_11_parse_elems_veneer
+1003ca10 t __key_2char2num_veneer
+1003ca18 t __CmdDumpWord_veneer
+1003ca20 t __rtw_parse_wpa2_ie_veneer
+1003ca28 t __rt_hmac_sha1_veneer
+1003ca30 t __rtw_set_fixed_ie_veneer
+1003ca38 t __rtw_get_bit_value_from_ieee_value_veneer
+1003ca40 t __rtw_set_supported_rate_veneer
+1003ca48 t __ROM_odm_SetCrystalCap_veneer
+1003ca50 t __aes_80211_encrypt_veneer
+1003ca58 t __wep_80211_encrypt_veneer
+1003ca60 t __tkip_80211_encrypt_veneer
+1003ca68 t __SpicWaitBusyDoneRtl8195A_veneer
+1003ca70 t __phy_CalculateBitShift_veneer
+1003ca78 t __rtw_get_rateset_len_veneer
+1003ca80 t __rt_arc4_init_veneer
+1003ca88 t __rtw_seccalctkipmic_veneer
+1003ca90 t __PHY_SetBBReg_8195A_veneer
+1003ca98 t __rom_psk_CalcPTK_veneer
+1003caa0 t __ROM_odm_CfoTrackingFlow_veneer
+1003caa8 t __rtw_get_wpa_ie_veneer
+1003cab0 t __rtw_get_wpa2_ie_veneer
+1003cab8 t __rtw_get_wps_ie_veneer
+1003cac0 t __rtw_get_wps_attr_content_veneer
+1003cac8 t __rtw_parse_wpa_ie_veneer
+1003cad0 t __rtw_get_ie_veneer
+1003cad8 t __PHY_QueryBBReg_8195A_veneer
+1003cb15 d __FUNCTION__.15285
+1003ce80 d bitrate_table
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+100451e0 d scale.7419
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+1004545e d sfb_8000_long
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+100455e0 d window_s
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+1004780c d hufftabB
+1004784c D mad_huff_pair_table
+100479cc D mad_huff_quad_table
+100479d4 d crc_table
+10047bd4 d D
+10048454 D mad_timer_zero
+1004878f d __func__.19887
+1004896e d __FUNCTION__.18776
+10048a00 d err_to_errno_table
+10048a48 D ip_addr_any
+10048a4c D ip_addr_broadcast
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+10048b08 D tcp_persist_backoff
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+10048b3c D ethbroadcast
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+10048c71 d CSWTCH.235
+10048cfe d __FUNCTION__.12591
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+10048d2e d __FUNCTION__.12625
+10048d4d d __FUNCTION__.12642
+10048d60 d __FUNCTION__.12653
+10048d7b d __FUNCTION__.12786
+10048d91 d __FUNCTION__.12790
+10048e24 D osdep_service
+10048f48 d __FUNCTION__.7330
+10048fd1 D GPIO_InPinMode
+10048fd5 D GPIO_SWPORT_DR_TBL
+10048fd8 d __func__.9082
+1004903c d I2SDefaultSetting
+10049050 d PinMap_I2S_CLK
+100490b0 d PinMap_I2S_RX
+100490f8 d PinMap_I2S_TX
+10049158 d PinMap_I2S_WS
+100491b8 d __FUNCTION__.9120
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+10049633 d __FUNCTION__.8789
+10049655 d __FUNCTION__.8796
+10049670 d __FUNCTION__.8803
+1004973d d __func__.8808
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+1004977a d __func__.8830
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+10049b99 d __func__.8686
+10049bac d __func__.8825
+10049bc5 d __func__.8631
+10049bf8 d __FUNCTION__.17777
+10049c18 D wlancmds
+10049e10 D rtw_cmd_callback
+1004a09c d RTW_ChannelPlan2G
+1004a114 D WPS_OUI
+1004a118 D RSN_TKIP_CIPHER
+1004a11c D MCS_rate_1R
+1004a12c D P2P_OUI
+1004a158 D WMM_INFO_OUI
+1004a15e D RTW_WPA_OUI
+1004a162 D WMM_PARA_OUI
+1004a168 d RTW_ChannelPlanMap
+1004a180 D null_addr
+1004a186 D WMM_OUI
+1004a18c d wlanevents
+1004a24c D zero_bssid
+1004a289 d __FUNCTION__.17681
+1004a29f D SNAP_ETH_TYPE_APPLETALK_AARP
+1004a2a1 d __FUNCTION__.17495
+1004a2b4 D SNAP_ETH_TYPE_IPX
+1004a2b6 D rtw_bridge_tunnel_header
+1004a2dd D rtw_rfc1042_header
+1004a2fb d CSWTCH.36
+1004a307 D ARTHEROS_OUI1
+1004a30a D ARTHEROS_OUI2
+1004a30d D REALTEK_OUI
+1004a310 D RALINK_OUI
+1004a313 D MARVELL_OUI
+1004a316 D CISCO_OUI
+1004a319 d rtw_basic_rate_cck
+1004a31d D BROADCOM_OUI1
+1004a320 D BROADCOM_OUI2
+1004a323 D REALTEK_96B_IE
+1004a329 d rtw_basic_rate_mix
+1004a330 d rtw_basic_rate_ofdm
+1004a333 D AIRGOCAP_OUI
+1004a347 d CSWTCH.66
+1004a360 d CSWTCH.48
+1004a3a2 d CSWTCH.28
+1004a3b4 D efuse_map_mask
+1004a3c4 D flash_map_mask
+1004a460 d __func__.21107
+1004a7a6 d CSWTCH.15
+1004a82a d CSWTCH.17
+1004a899 d CSWTCH.14
+1004a92e d __FUNCTION__.21257
+1004a940 d rtw_private_args
+1004ad8d d __FUNCTION__.21057
+1004ada0 d __FUNCTION__.21294
+1004adb1 d __FUNCTION__.21241
+1004adc0 d __FUNCTION__.21126
+1004add0 d iw_priv_type_size
+1004aeae d __FUNCTION__.17334
+1004aec4 d __FUNCTION__.17736
+1004aed4 d __FUNCTION__.17760
+1004aee7 d __FUNCTION__.17712
+1004aef6 d __FUNCTION__.17649
+1004af04 d __FUNCTION__.17661
+1004b2db d __FUNCTION__.17827
+1004b2f4 d __FUNCTION__.17654
+1004b2ff d __FUNCTION__.17615
+1004b30e d __FUNCTION__.17811
+1004b320 d __FUNCTION__.17765
+1004b32e d __FUNCTION__.17724
+1004b33f d __FUNCTION__.17637
+1004c6e0 D CCKFCCTable_Ch14_8195A
+1004c6f0 D CCKFCCTable_8195A
+1004c700 D OFDMSwingTable_New
+1004c7ac D CCKCETable_8195A
+1004c7c2 d CSWTCH.39
+1004c7d7 d __func__.20571
+1004c7f8 D hci_ops
+1004c81d V Array_MP_8195A_TXPWR_LMT
+1004cd8f d __func__.20444
+1004d0fb d dhcp_magic_cookie
+1004d0ff d dhcp_option_interface_mtu
+1004d101 d dhcp_option_lease_time_one_day
+1004d584 D xHeapRegions
+1004d5a4 D UartLogRamCmdTable
+1004d5a4 D console_commands_main
+1004d5b4 D console_commands
+1004d5d4 D console_cmd_wifi_api
+1004d644 D console_commands_at
+1004d6b4 D UartLogRamCmdTable_end
+1004d6b8 D __data_start__
+1004d6b8 D oversampling
+1004d6bc D SystemCoreClock
+1004d6c0 D error_flag
+1004d6c4 d iss.7965
+1004d6c8 d tcp_port
+1004d6ca d udp_port
+1004d6cc D lwip_host_name
+1004d6ec d uxCriticalNesting
+1004d6f0 d seed.12758
+1004d6f4 d last_wakelock_state
+1004d714 d wakelock
+1004d718 d wakeup_event
+1004d71c D mlme_sta_tbl
+1004d78c d PMKID_KDE_TYPE.17744
+1004d794 V nr_xmitbuff
+1004d798 V nr_xmitframe
+1004d79c d P802_1H_OUI
+1004d79f D rtw_adaptivity_mode
+1004d7a0 D g_user_ap_sta_num
+1004d7a4 d rtw_private_handler
+1004d7e8 V max_local_skb_num
+1004d7ec V max_skb_buf_num
+1004d7f0 D rom_e_rtw_msgp_str_
+1004d9cc D ARFB_table
+1004da0b D TRYING_NECESSARY_idx
+1004da1f D DROPING_NECESSARY
+1004da33 D PER_RATE_UP
+1004da47 D PER_RATE_DOWN
+1004da5c V Array_MP_8195A_PHY_REG_PG
+1004daec D Array_MP_8195A_AGC_TAB
+1004dcfc D Array_MP_8195A_PHY_REG
+1004e374 D rtl8195A_card_disable_flow
+1004e414 D rtl8195A_card_enable_flow
+1004e4b4 D Array_MP_8195A_MAC_REG
+1004e7bc D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_TFBGA96_8195A
+1004e7dc D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_TFBGA96_8195A
+1004e7fc D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_QFN48_8195A
+1004e81a D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_QFN56_8195A
+1004e838 D gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_QFN48_8195A
+1004e856 D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN56_8195A
+1004e874 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_TFBGA96_8195A
+1004e894 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_QFN56_8195A
+1004e8b2 D gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_QFN48_8195A
+1004e8d0 D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_QFN56_8195A
+1004e8f0 D Array_MP_8195A_RadioA
+1004eeb8 D gDeltaSwingTableXtal_MP_P_TxXtalTrack_8195A
+1004eed6 D gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_TFBGA96_8195A
+1004eef6 D gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_QFN48_8195A
+1004ef14 D feep_tab
+1004ef54 D tab_code_rtw_secyrity
+1004ef7c D tab_txt_rtw_secyrity
+1004efa4 D wifi_ap_cfg
+1004f00c D wifi_ap_dhcp
+1004f01c D wifi_cfg
+1004f023 D wifi_st_cfg
+1004f094 D wifi_st_dhcp
+1004f0a4 D wlan_ap_name
+1004f0aa D wlan_ap_netifn
+1004f0ab D wlan_st_name
+1004f0b1 d dhcp_recorded_xid
+1004f0b5 d dhcp_server_state_machine
+1004f0b6 D __data_end__
+1004f0b6 D __ram_image2_text_end__
+1004f0c0 D .ram.bss$$Base
+1004f0c0 D __bss_start__
+1004f0c0 d skbdata_list
+1004f0c8 V skb_data_pool
+100524c8 D HalI2SOpSAL
+10052504 d bufUnderrunCt
+10052508 D mp3_serv
+1005258c d oldRate
+10052590 D readBuf
+10052594 d sampCnt
+10052598 d sampCntAdd
+10052599 d sampDelCnt
+1005259a D tskmad_enable
+1005259b D tskreader_enable
+1005259c D pbuf_fifo
+100525a0 D I2sTxSema
+100525a4 D pi2s
+100525ac d join_user_data
+100525b0 D rtw_join_status
+100525b4 D scan_result_handler_ptr
+100525c8 D wifi_mode
+100525cc d event_callback_list
+1005274c D paff_array
+100527c4 D lwip_init_done
+100527c8 D xnetif
+10052840 D h_errno
+10052844 d s_aliases.7583
+10052848 d s_hostent.7582
+1005285c d s_hostent_addr.7584
+10052860 d s_phostent_addr.7585
+10052868 d select_cb_ctr
+1005286c d select_cb_list
+10052870 d sockets
+10052930 d mbox
+10052934 d tcpip_init_done
+10052938 d tcpip_init_done_arg
+1005293c d allrouters
+10052940 d allsystems
+10052944 d igmp_group_list
+10052948 D current_header
+1005294c D current_iphdr_dest
+10052950 D current_iphdr_src
+10052954 D current_netif
+10052958 d ip_id
+1005295a d str.6845
+1005296a d ip_reass_pbufcount
+1005296c d reassdatagrams
+10052970 D dhcp_rx_options_given
+1005297c D dhcp_rx_options_val
+100529a4 d xid.7865
+100529a8 d dns_payload
+100529ac d dns_payload_buffer
+10052bb0 d dns_pcb
+10052bb4 d dns_seqno
+10052bb8 d dns_servers
+10052bc0 d dns_table
+10053020 d next_timeout
+10053024 d tcpip_tcp_timer_active
+10053028 D netif_default
+1005302c D netif_list
+10053030 d netif_num
+10053031 D pbuf_free_ooseq_pending
+10053034 d raw_pcbs
+10053038 D tcp_active_pcbs
+1005303c D tcp_active_pcbs_changed
+10053040 D tcp_bound_pcbs
+10053044 D tcp_listen_pcbs
+10053048 D tcp_ticks
+1005304c d tcp_timer
+1005304d d tcp_timer_ctr
+10053050 D tcp_tmp_pcb
+10053054 D tcp_tw_pcbs
+10053058 d ackno
+1005305c d flags
+10053060 d inseg
+10053074 d recv_data
+10053078 d recv_flags
+1005307c d seqno
+10053080 D tcp_input_pcb
+10053084 d tcphdr
+10053088 d tcplen
+1005308c D udp_pcbs
+10053090 d arp_table
+10053158 d etharp_cached_entry
+1005315c D lwip_tickless_used
+10053160 d s_nextthread
+10053164 d s_timeoutlist
+10053194 d ext_free
+10053198 D ext_lower
+1005319c D ext_upper
+100531a0 d pxEnd
+100531a4 d xFreeBytesRemaining
+100531a8 d xMinimumEverFreeBytesRemaining
+100531ac d xStart
+100531b4 d ulStoppedTimerCompensation
+100531b8 d ulTimerCountsForOneTick
+100531bc d xMaximumPossibleSuppressedTicks
+100531c0 D pxCurrentTCB
+100531c4 d pxDelayedTaskList
+100531c8 d pxOverflowDelayedTaskList
+100531cc d pxReadyTasksLists
+100532a8 d ulTaskSwitchedInTime
+100532ac d uxCurrentNumberOfTasks
+100532b0 d uxDeletedTasksWaitingCleanUp
+100532b4 d uxPendedTicks
+100532b8 d uxSchedulerSuspended
+100532bc d uxTaskNumber
+100532c0 d uxTopReadyPriority
+100532c4 d xDelayedTaskList1
+100532d8 d xDelayedTaskList2
+100532ec d xIdleTaskHandle
+100532f0 d xNextTaskUnblockTime
+100532f4 d xNumOfOverflows
+100532f8 d xPendingReadyList
+1005330c d xSchedulerRunning
+10053310 d xSuspendedTaskList
+10053324 d xTasksWaitingTermination
+10053338 d xTickCount
+1005333c d xYieldPending
+10053340 d pxCurrentTimerList
+10053344 d pxOverflowTimerList
+10053348 d xActiveTimerList1
+1005335c d xActiveTimerList2
+10053370 d xLastTime.5386
+10053374 d xTimerQueue
+10053378 d xTimerTaskHandle
+1005337c d device_mutex
+10053388 d mutex_init
+1005338c d uxSavedInterruptStatus
+10053390 D min_free_heap_size
+10053394 d g_heap_inited
+10053398 D g_tcm_heap
+1005339c d tcm_lock
+100533a0 D flashobj
+100533ac D fspic_isinit
+100533b0 D WDGAdapter
+100533ec D gHAL_Gpio_Adapter
+10053518 d hold_wakelock_time
+10053598 d last_acquire_wakelock_time
+10053618 D missing_tick
+1005361c D post_sleep_callback
+1005369c D pre_sleep_callback
+1005371c D reserve_pll
+10053720 d sys_sleep_time
+10053724 D Timer2To7HandlerData
+1005373c D PwrAdapter
+100539c8 D SYSAdapte
+100539c9 D libc_has_init
+100539ca D print_off
+100539cc d rheap_end
+100539e0 d g_rtl_cipherEngine
+10053ee0 d init_status.9288
+10053ee4 D auto_reconnect_running
+10053ee8 D p_wlan_autoreconnect_hdl
+10053eec D mac_monitor_callback
+10053ef0 D mf_list_head
+10053ef4 d pscan_retry_cnt.21430
+10053ef8 D promisc_callback_all
+10053efc D promisc_sema
+10053f00 D promisc_callback
+10053f04 D psk_essid
+10053f4c D psk_passphrase
+10053fce D psk_passphrase64
+1005400f D wpa_global_PSK
+1005405f d RFC1042_OUI
+10054064 d rx_ring_pool
+10056144 d stop_report_count.20629
+10056145 D bCheckStateTIMER
+10056148 d WifiMcuCmdBitMap.20974
+1005614c D p_wlan_init_done_callback
+10056150 D rtw_power_percentage_idx
+10056154 D p_wlan_uart_adapter_callback
+10056158 D rtw_adaptivity_en
+1005615c D p_wlan_mgmt_filter
+10056160 D rtw_initmac
+10056164 D rtw_adaptivity_th_l2h_ini
+10056168 d drvpriv
+1005617c D skbbuf_used_num
+10056180 V skb_pool
+10056338 D skbdata_used_num
+1005633c d wrapper_skbbuf_list
+10056344 D max_skbdata_used_num
+10056348 D max_skbbuf_used_num
+1005634c d skb_fail_count
+10056350 D timer_table
+10056358 D rltk_wlan_info
+10056388 d timer_used_num
+1005638c D max_timer_used_num
+10056390 D Noisy_State
+10056394 D pExportWlanIrqSemaphore
+10056398 D gDeltaSwingTableXtal_MP_N_TxXtalTrack_8195A
+100563b8 D wifi_autoreconnect
+100563c0 D wifi_run_mode
+100563c1 D wifi_st_status
+100563c2 D wlan_st_netifn
+100563c4 D web_scan_handler_ptr
+100563d0 d bound_client_ethernet_address
+100563e0 d client_request_ip
+100563e4 d dhcp_client_ethernet_address
+100563f4 d dhcp_message_repository
+100563f8 d dhcp_message_total_options_lenth
+100563fc d dhcps_allocated_client_address
+10056400 D dhcps_ip4addr_pool_end
+10056401 D dhcps_ip4addr_pool_start
+10056404 d dhcps_ip_table_semaphore
+10056408 d dhcps_local_address
+1005640c d dhcps_local_gateway
+10056410 d dhcps_local_mask
+10056414 d dhcps_netif
+10056418 d dhcps_network_id
+1005641c d dhcps_pcb
+10056420 d dhcps_send_broadcast_address
+10056424 d dhcps_subnet_broadcast
+10056428 d ip_table
+10056448 ? __ram_heap2_start__
+10056448 D .ram.bss$$Limit
+10056448 D __bss_end__
10070000 A __ram_heap2_end__
1fff0000 D __ram_tcm_start__
1fff0000 D __tcm_heap_start__
diff --git a/flasher/RTL_RunRAM.JLinkScript b/flasher/RTL_RunRAM.JLinkScript
index 7632f1e..f8b665b 100644
--- a/flasher/RTL_RunRAM.JLinkScript
+++ b/flasher/RTL_RunRAM.JLinkScript
@@ -7,6 +7,6 @@ r
loadbin build/bin/ram_1.r.bin 0x10000bc8
loadbin build/bin/ram_2.bin 0x10006000
r
-w4 0x40000210,0x20111113
+w4 0x40000210,0x20011113
g
q
\ No newline at end of file
diff --git a/flasher/gdb_flasher.jlink b/flasher/gdb_flasher.jlink
index 2eb169c..d6f2c97 100644
--- a/flasher/gdb_flasher.jlink
+++ b/flasher/gdb_flasher.jlink
@@ -38,37 +38,38 @@ set mem inaccessible-by-default off
# Setup GDB FOR FASTER DOWNLOADS
set remote memory-write-packet-size 8192
set remote memory-write-packet-size fixed
+set $SPI_FLASH_BASE = 0x98000000
end
#############
# Boot_Flash
define SetBootFlash
printf "SetBoot = Flash:\n"
-monitor long 0x40000210 = 0x211157
+monitor long 0x40000210 = 0x00011113
end
# Boot RAM start_addr0() Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 )
define SetBootCall0
printf "SetBoot = Call0:\n"
-monitor long 0x40000210 = 0x80011117
+monitor long 0x40000210 = 0x80011113
end
# Boot RAM start_addr1() Run if ( v40000210 & 0x20000000 )
define SetBootCall1
printf "SetBoot = Call1:\n"
-monitor long 0x40000210 = 0x20011117
+monitor long 0x40000210 = 0x20011113
end
# Boot RAM start_addr2() Run if ( v40000210 & 0x10000000 )
define SetBootCall2
printf "SetBoot = Call2:\n"
-monitor long 0x40000210 = 0x10011117
+monitor long 0x40000210 = 0x10011113
end
# Boot RAM start_addr3() Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
define SetBootCall3
printf "SetBoot = Call3:\n"
-monitor long 0x40000210 = 0x8011117
+monitor long 0x40000210 = 0x8011113
end
# Boot RAM start_addr4() Init console, Run if ( v40000210 & 0x4000000 )
define SetBootCall4
printf "SetBoot = Call4:\n"
-monitor long 0x40000210 = 0x4011117
+monitor long 0x40000210 = 0x4011113
end
# CPU CLK 166 MHz?
define SetClk166MHz
@@ -89,8 +90,7 @@ monitor long 0x40000304 = 0x1FC00002
monitor long 0x40000250 = 0x400
monitor long 0x40000340 = 0x0
monitor long 0x40000230 = 0xdcc4
-monitor long 0x40000210 = 0x11117
-monitor long 0x40000210 = 0x11157
+monitor long 0x40000210 = 0x11113
monitor long 0x400002c0 = 0x110011
monitor long 0x40000320 = 0xffffffff
end
@@ -125,7 +125,6 @@ monitor long 0x40006018 = 0
monitor long 0x4000601C = 0
#disable DMA
monitor long 0x4000604C = 0
-set $SPI_FLASH_BASE = 0x98000000
end
###################
# SetFirwareSize #
@@ -154,7 +153,26 @@ if $Image1Size != 0 && $Image1Size < 0x1000000
printf "Image2Size = %d\n", $Image2Size
printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
set $FirmwareSize = $Image2Addr + $Image2Size
- printf "FirmwareSize = %d\n", $FirmwareSize
+ set $Image3Addr = $FirmwareSize
+ set $parms1 = $rambuffer - $FirmwareSize
+ set $parms3 = $Image3Addr + 0x08
+ restore $arg0 binary $parms1 $Image3Addr $parms3
+ set $Image3Size = {int}($rambuffer)
+ set $Image3LoadAddr = {int}($rambuffer+0x4)
+ if $Image3Size != 0xFFFFFFFF && $Image3Size != 0
+ set $Image3Size = $Image3Size + 16
+ printf "Image3Size = %d\n", $Image3Size
+ printf "Image3LoadAddr = 0x%08x\n", $Image3LoadAddr
+ set $FirmwareSize = $Image3Addr + $Image3Size
+ printf "FirmwareSize = %d\n", $FirmwareSize
+ else
+ set $Image3Size = 0
+ if $Image3LoadAddr == 0x30000000
+ set $FirmwareSize = $FirmwareSize + 8
+ end
+ printf "Image3 - None\n"
+ printf "FirmwareSize = %d\n", $FirmwareSize
+ end
else
set $Image2Size = 0
printf "Image2 - None\n"
@@ -164,7 +182,9 @@ if $Image1Size != 0 && $Image1Size < 0x1000000
else
set $Image1Size = 0
set $Image2Size = 0
+ set $Image3Size = 0
set $Image2Addr = 0
+ set $Image3Addr = 0
set $FirmwareSize = 0
printf "Image not format Firmware!\n"
end
@@ -173,6 +193,10 @@ end
# Flash Images Info #
#####################
define FlashImagesInfo
+set $Image2Size = 0
+set $Image3Size = 0
+set $Image2Addr = 0
+set $Image3Addr = 0
printf "Flash Info:\n"
set $Image1Size = {int}($SPI_FLASH_BASE + 0x10) + 32
set $Image1LoadAddr = {int}($SPI_FLASH_BASE + 0x14)
@@ -181,16 +205,26 @@ printf "Image1 - None\n"
else
set $Image2FlashAddr = {short}($SPI_FLASH_BASE + 0x18) * 1024
if $Image2FlashAddr == 0
-$Image2FlashAddr = $Image1Size
+set $Image2FlashAddr = $Image1Size
end
set $Image2Size = {int}($Image2FlashAddr + $SPI_FLASH_BASE)
set $Image2LoadAddr = {int}($Image2FlashAddr + $SPI_FLASH_BASE + 0x4)
printf "Image1Size = %d\n", $Image1Size
printf "Image1LoadAddr = 0x%08x\n", $Image1LoadAddr
printf "Image2FlashAddr = 0x%08x\n", $Image2FlashAddr
-if $Image2Size != 0xFFFFFFFF
+if $Image2Size != 0xFFFFFFFF && $Image2Size != 0
printf "Image2Size = %d\n", $Image2Size
printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
+set $Image3FlashAddr = $Image2FlashAddr + $Image2Size + 0x10
+set $Image3Size = {int}($Image3FlashAddr + $SPI_FLASH_BASE)
+set $Image3LoadAddr = {int}($Image3FlashAddr + $SPI_FLASH_BASE + 0x4)
+if $Image3Size != 0xFFFFFFFF && $Image3Size !=0
+printf "Image3FlashAddr = 0x%08x\n", $Image3FlashAddr
+printf "Image3Size = %d\n", $Image3Size
+printf "Image3LoadAddr = 0x%08x\n", $Image3LoadAddr
+else
+printf "Image3 - None\n"
+end
else
printf "Image2 - None\n"
end
diff --git a/flasher/gdb_wrflash.jlink b/flasher/gdb_wrflash.jlink
index 6d37642..0bceeb0 100644
--- a/flasher/gdb_wrflash.jlink
+++ b/flasher/gdb_wrflash.jlink
@@ -151,8 +151,13 @@ if $Image1Size != 0
printf "Write Image1 size %d to Flash addr 0x00000000:\n", $Image1Size
#FlasherWrite $wr_flile 0 $Image1Size
call2
- if $Image2Size != 0 && $Image2Addr >= $Image1Size
- printf "Write Image2 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
+ if $Image2Size != 0 && $Image2Addr >= $Image1Size
+ if $Image3Size != 0 && $Image3Addr > $Image2Size
+ set $Image2Size = $Image2Size + $Image3Size
+ printf "Write Image2&3 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
+ else
+ printf "Write Image2 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
+ end
#FlasherWrite $wr_flile $Image2Addr $Image2Size
call3
end
diff --git a/project.mk b/project.mk
index 7600a76..bad3745 100644
--- a/project.mk
+++ b/project.mk
@@ -1,6 +1,7 @@
#=============================================
# SDK CONFIG
#=============================================
+#USE_SDRAM = 1
#USE_AT = 1
#USE_FATFS = 1
#USE_SDIOH = 1
@@ -27,8 +28,8 @@ CFLAGS += -DLOGUART_STACK_SIZE=1024
#user main
ADD_SRC_C += project/src/user/main.c
# components
-ADD_SRC_C += project/src/user/wifi_console.c
-ADD_SRC_C += project/src/user/atcmd_user.c
+DRAM_C += project/src/user/wifi_console.c
+DRAM_C += project/src/user/atcmd_user.c
ADD_SRC_C += project/src/user/spiram_fifo.c
#lib mad
diff --git a/project/inc/platform_autoconf.h b/project/inc/platform_autoconf.h
index 3be5470..ea70e11 100644
--- a/project/inc/platform_autoconf.h
+++ b/project/inc/platform_autoconf.h
@@ -145,7 +145,7 @@
#define CONFIG_EFUSE_NORMAL 1
#undef CONFIG_EFUSE_TEST
#define CONFIG_EFUSE_MODULE 1
-#ifdef RTL8711AM
+#if defined(RTL8711AM) || defined(USE_SDRAM)
#define CONFIG_SDR_EN 1
#endif
#define CONFIG_SDR_NORMAL 1