mirror of
https://github.com/pvvx/RTL00MP3.git
synced 2026-07-07 20:15:41 +00:00
update
This commit is contained in:
pvvx
parent
b075b615b6
commit
8c8b03208e
28 changed files with 2887 additions and 2556 deletions
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@ -32,6 +32,7 @@
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#include <skbuff.h>
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#ifdef PLATFORM_FREERTOS
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#include "freertos_service.h"
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#include "osdep_service.h"
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#elif defined(PLATFORM_CMSIS_RTOS)
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#include "rtx_service.h"
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#endif
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@ -135,14 +135,14 @@ struct video_device
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/* device info */
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char name[32];
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int vfl_type; /* device type,usally assign the define VFL_TYPE_XXX value */
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int vfl_dir; /* receiver, transmitter or m2m,usally assign the define VFL_DIR_XXX value */
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int vfl_dir; /* +72(dec) receiver, transmitter or m2m,usally assign the define VFL_DIR_XXX value */
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/* 'minor' is set to -1 if the registration failed */
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int minor;
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u16 num; /* record the registered video device node number */
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/* use bitops to set/clear/test flags,usally assign the define VFL_FL_XXX value */
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unsigned long flags;
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/* attribute to differentiate multiple indices on one physical device */
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int index;
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int index; // +88(dec)
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/* V4L2 file handles */
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//spinlock_t fh_lock; /* Lock for all v4l2_fhs */
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@ -173,7 +173,7 @@ static size_t xMinimumEverFreeBytesRemaining = 0;
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#include "section_config.h"
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SRAM_HEAP_SECTION
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#endif
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unsigned char ucHeap[configTOTAL_HEAP_SIZE];
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unsigned char ucHeap[16384]; //configTOTAL_HEAP_SIZE
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//extern void * __sdram_bss_end__;
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//extern void * __ram_heap1_start__, __ram_heap1_end__, __ram_heap2_start__, __sdram_data_start__;
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@ -1,5 +1,5 @@
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/*
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* BootLoader Ver 0.2
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* BootLoader Ver 0.3 (18/10/2017)
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* Created on: 12/02/2017
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* Author: pvvx
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*/
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@ -8,6 +8,7 @@
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#include "rtl_bios_data.h"
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#include "diag.h"
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#include "rtl8195a/rtl8195a_sys_on.h"
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#include "rtl8195a/rtl8195a_sdr.h"
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#include "hal_spi_flash.h"
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@ -30,7 +31,7 @@
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#define DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE (DEFAULT_BOOT_CLK_CPU-6)
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#endif
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#endif // DEFAULT_BOOT_CLK_CPU
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#define FIX_SDR_CALIBRATION // for speed and low used SRAM
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#define BOOT_RAM_TEXT_SECTION // __attribute__((section(".boot.text")))
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//-------------------------------------------------------------------------
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@ -65,7 +66,6 @@ extern _LONG_CALL_ VOID HalInitPlatformLogUartV02(VOID);
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extern _LONG_CALL_ VOID HalInitPlatformTimerV02(VOID);
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//extern _LONG_CALL_ VOID DramInit_rom(IN DRAM_DEVICE_INFO *DramInfo);
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//extern _LONG_CALL_ u32 SdrCalibration_rom(VOID);
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extern _LONG_CALL_ int SdrControllerInit_rom(PDRAM_DEVICE_INFO pDramInfo);
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extern _LONG_CALL_ u32 SpicCmpDataForCalibrationRtl8195A(void); // compare read_data and golden_data
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//extern _LONG_CALL_ VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara); // wait spi-flash status register[0] = 0
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//extern _LONG_CALL_ VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara);
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@ -100,14 +100,14 @@ LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() {
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CfgSysDebugErr = -1;
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ConfigDebugWarn = -1;
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// ConfigDebugInfo = 0;
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ConfigDebugErr = -1;
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ConfigDebugErr = -1; // ~_DBG_SDR_;
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#elif CONFIG_DEBUG_LOG > 0
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// CfgSysDebugWarn = 0;
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// CfgSysDebugInfo = 0;
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CfgSysDebugErr = -1;
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// ConfigDebugWarn = 0;
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// ConfigDebugInfo = 0;
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ConfigDebugErr = -1;
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ConfigDebugErr = -1; // ~_DBG_SDR_;
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#else
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// CfgSysDebugWarn = 0;
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// CfgSysDebugInfo = 0;
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@ -125,15 +125,6 @@ LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) {
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HalPinCtrlRtl8195A(JTAG, 0, 1);
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}
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/* GetChipId() */
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LOCAL uint8 INFRA_START_SECTION _Get_ChipId() {
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uint8 ChipId = CHIP_ID_8710AF;
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if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
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&ChipId, L25EOUTVOLTAGE) != 1)
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DBG_8195A("Get Chip ID Failed\r");
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return ChipId;
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}
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/*
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* 16 bytes FIFO ... 16*11/38400 = 0.004583 sec
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* (0.005/5)*166666666 = 166666.666 Tcpu
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@ -281,11 +272,130 @@ LOCAL int BOOT_RAM_TEXT_SECTION InitSpic(uint8 SpicBitMode) {
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}
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ACTCK_FLASH_CCTRL(1);
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SLPCK_FLASH_CCTRL(1);
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HalPinCtrlRtl8195A(SPI_FLASH, 0, 1);
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HalPinCtrlRtl8195A(SPI_FLASH, 0, ON);
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InitSpicFlashType(&spic_table_flash);
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return SetSpicBitMode(SpicBitMode);
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}
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#ifdef CONFIG_SDR_EN
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/* GetChipId() */
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LOCAL uint8 INFRA_START_SECTION _Get_ChipId() {
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uint8 ChipId = CHIP_ID_8710AF;
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if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
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&ChipId, L25EOUTVOLTAGE) != 1)
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DBG_8195A("Get Chip ID Failed\r");
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return ChipId;
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}
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LOCAL void INFRA_START_SECTION sdr_preinit(void) {
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HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
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((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); // ROM: BIT_SYS_REGU_LDO25M_ADJ(0x0e)? HAL RAM BIT_SYS_REGU_LDO25M_ADJ(0x03)
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LDO25M_CTRL(ON);
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SRAM_MUX_CFG(0x2);
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SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE); // REG_PESOC_CLK_SEL
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HalPinCtrlRtl8195A(SDR, 0, ON); // SDR_PIN_FCTRL(ON);
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ACTCK_SDR_CCTRL(ON);
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SLPCK_SDR_CCTRL(ON);
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HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4, 0);
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MEM_CTRL_FCTRL(ON);
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// HalDelayUs(1000);
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}
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#ifndef FIX_SDR_CALIBRATION
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extern _LONG_CALL_ int SdrCalibration_rom(void);
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extern _LONG_CALL_ unsigned int Rand(void);
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extern _LONG_CALL_ int SdrControllerInit_rom(PDRAM_DEVICE_INFO pDramInfo);
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LOCAL int INFRA_START_SECTION sdr_test(u32 LoopCnt) {
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u32 LoopIndex = 0;
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u32 Value32, Addr;
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for (LoopIndex = 0; LoopIndex < LoopCnt; LoopIndex++) {
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Value32 = Rand();
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Addr = Rand();
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Addr &= 0x1FFFFF;
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Addr &= (~0x3);
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HAL_SDRAM_WRITE32(Addr, Value32);
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if (HAL_SDRAM_READ32(Addr) != Value32)
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return 0;
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}
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return 1;
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}
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#endif
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LOCAL int INFRA_START_SECTION sdr_init_from_flash(void) {
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#define RdPipe 0
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#if DEFAULT_BOOT_CLK_CPU < 6
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#define TapCnt 0x11
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#elif DEFAULT_BOOT_CLK_CPU == 7
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#define TapCnt 0x23
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#else
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#define TapCnt 0x19
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#endif
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// set all_mode _idle
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HAL_SDR_WRITE32(REG_SDR_CSR, 0x700);
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// WRAP_MISC setting
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HAL_SDR_WRITE32(REG_SDR_MISC, 0x00000001);
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// PCTL setting
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HAL_SDR_WRITE32(REG_SDR_DCR, 0x00000008);
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HAL_SDR_WRITE32(REG_SDR_IOCR, RdPipe << PCTL_IOCR_RD_PIPE_BFO);
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HAL_SDR_WRITE32(REG_SDR_EMR2, 0x00000000);
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HAL_SDR_WRITE32(REG_SDR_EMR1, 0x00000006);
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HAL_SDR_WRITE32(REG_SDR_MR, 0x00000022);
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HAL_SDR_WRITE32(REG_SDR_DRR, 0x09030e07);
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HAL_SDR_WRITE32(REG_SDR_TPR0, 0x00002652);
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HAL_SDR_WRITE32(REG_SDR_TPR1, 0x00068873);
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HAL_SDR_WRITE32(REG_SDR_TPR2, 0x00000042);
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// start to init
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HAL_SDR_WRITE32(REG_SDR_CCR, 0x01);
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DBG_8195A("SDR calibration: %02x-%02x\n", RdPipe, TapCnt);
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while ((HAL_SDR_READ32(REG_SDR_CCR) & 0x1) == 0x0);
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// enter mem_mode
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HAL_SDR_WRITE32(REG_SDR_CSR, 0x600);
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#ifdef FIX_SDR_CALIBRATION
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SDR_DDL_FCTRL(TapCnt); // SDR_DDL_FCTRL(0x11);
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return 1;
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#else
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union { u8 b[8]; u16 s[4]; u32 l[2]; u64 d;} value;
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// read calibration data from system data FLASH_SDRC_PARA_BASE
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u32 reg = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1);
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u32 faddr = SPI_FLASH_BASE + FLASH_SDRC_PARA_BASE + ((reg & 0x70) >> 1) + ((reg & BIT17) >> 11) ; // step 8 in FLASH_SDRC_PARA_BASE[64 + 64 bytes]
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value.d = *((volatile u64 *)faddr);
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DBG_8195A("SDR flash calibration [%08x] %02x-%02x-%02x\n", faddr, value.b[0], value.b[4], value.b[6]);
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if(value.s[0] == 0xFE01 && (value.b[4]^value.b[5]) == 0xFF && (value.b[6]^value.b[7]) == 0xFF) {
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HAL_SDR_WRITE32(REG_SDR_IOCR, (HAL_SDR_READ32(REG_SDR_IOCR) & 0xff) | ((u32)value.b[4] << PCTL_IOCR_RD_PIPE_BFO));
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SDR_DDL_FCTRL((u32)value.b[6]);
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if(sdr_test(7))
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return 1; // ok
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else
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DBG_8195A("Not valid SDR calibration in flash!\n");
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} else
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DBG_8195A("Error SDR calibration in flash!\n");
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if(SdrCalibration_rom()) { // Внимание: дает завышенный TapCnt !
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// DBG_8195A("SDR calibration: %02x-%02x-%02x\n", value.b[0], value.b[4], value.b[6]);
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value.s[0] = 0xFE01;
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value.b[4] = HAL_SDR_READ32(REG_SDR_IOCR) >> PCTL_IOCR_RD_PIPE_BFO;
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value.b[5] = value.b[4] ^ 0xFF;
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value.b[6] = HAL_PERI_ON_READ32(REG_PESOC_MEM_CTRL) >> BIT_SHIFT_PESOC_SDR_DDL_CTRL;
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value.b[7] = value.b[6] ^ 0xFF;
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// DBG_8195A("%08x: %02x-%02x-%02x)\n", faddr, value.b[0], value.b[4], value.b[6]);
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if((*((volatile u16 *)(faddr)) & value.s[0]) == value.s[0]
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&& (*((volatile u32 *)(faddr + 4)) & value.l[1]) == value.l[1]) {
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*((volatile u32 *)(faddr + 4)) = value.l[1];
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DBG_8195A("Write new calibration [%08x] %02x-%02x-%02x\n", faddr, value.b[0], value.b[4], value.b[6]);
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HalDelayUs(1000);
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*((volatile u16 *)(faddr)) = value.s[0];
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} else {
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DBG_8195A("Work recalibration: %02x-%02x-%02x!\n", value.b[0], value.b[4], value.b[6]);
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}
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return 2; // recalibration - ok
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} else
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DBG_8195A("SDR recalibration fail!\n");
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return 0;
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#endif // FIX_SDR_CALIBRATION
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}
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#endif // CONFIG_SDR_EN
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/* SYSPlatformInit */
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LOCAL void INFRA_START_SECTION SYSPlatformInit(void) {
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@ -562,35 +672,36 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
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else
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DBG_8195A("\r===== Enter SRAM-Boot %d ====\n", flg);
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#if CONFIG_DEBUG_LOG > 1
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DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(),
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DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\n", HalGetCpuClk(),
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HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
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#endif
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#ifdef CONFIG_SDR_EN
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uint8 ChipId = _Get_ChipId();
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if (ChipId < CHIP_ID_8195AM) {
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#endif
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//----- SDRAM Off
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SDR_PIN_FCTRL(OFF);
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LDO25M_CTRL(OFF);
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init
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#ifdef CONFIG_SDR_EN
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init or None
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} else {
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//----- SDRAM On
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LDO25M_CTRL(ON);
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HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
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(HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x0e));
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SDR_PIN_FCTRL(ON);
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sdr_preinit();
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};
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#endif
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if (!InitSpic(SpicDualBitMode)) {
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DBG_8195A("Spic Init Error!\n");
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DBG_8195A("Spic Init fail!\n");
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RtlConsolRam();
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};
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if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // Flag SDRAM Init?
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// extern DRAM_DEVICE_INFO SdrDramInfo_rom; // 50 MHz
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if (!SdrControllerInit_rom(&SdrDramInfo)) { // 100 MHz
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DBG_8195A("SDR Controller Init fail!\n");
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#ifdef CONFIG_SDR_EN
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if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // Flag SDRAM No ReInit?
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if(!sdr_init_from_flash()) {
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DBG_8195A("SDR Init fail!\n");
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RtlConsolRam();
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}
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#if 0 // Test SDRAM
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#ifdef USE_SDRAM_TEST // Test SDRAM
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else {
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uint32 *ptr = SDR_SDRAM_BASE;
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uint32 *ptr = (uint32 *)SDR_SDRAM_BASE;
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uint32 tt = 0x55AA55AA;
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for (int i = 0; i < 512 * 1024; i++) {
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ptr[i] = tt++;
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@ -601,23 +712,26 @@ LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
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DBG_8195A("SDR err %p %p != %p!\n", &ptr[i], ptr[i], tt);
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RtlConsolRam();
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}
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// ptr[i] = 0;
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tt++;
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};
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DBG_8195A("SDR tst end\n");
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DBG_8195A("SDR test ok\n");
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};
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#endif // Test SDRAM
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#ifdef CONFIG_SDR_EN
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// Тест и ожидание загрузки Jlink-ом sdram.bin (~7 sec)
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if(flg && *((uint32 *)0x1FFF0000) == 0x12345678) {
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*((volatile uint32 *)0x1FFF0000) = 0x87654321;
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uint32 tt = 0x03ffffff; // ~7 sec
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DBG_8195A("Waiting for SDRAM to load...\n");
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// __asm__ __volatile__ ("cpsid f\n");
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while(*((volatile uint32 *)0x1FFF0000) == 0x87654321 && tt--);
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// __asm__ __volatile__ ("cpsie f\n");
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if(*((volatile uint32 *)0x1FFF0000) == 1)
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DBG_8195A("SDRAM load ok\n");
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}
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#endif // test
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM No ReInit
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};
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#endif // CONFIG_SDR_EN
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if (!flg)
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loadUserImges(IsForceLoadDefaultImg2() + 1);
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@ -1,5 +1,5 @@
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/*
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* StartUp SDK
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* StartUp USDK v0.2 (19/10/2017)
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* Created on: 02/03/2017
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* Author: pvvx
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*/
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@ -41,6 +41,7 @@ void SDIO_Device_Off(void);
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//void VectorTableOverrideRtl8195A(u32 StackP);
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void SYSPlatformInit(void);
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#define FIX_SDR_CALIBRATION // for speed :)
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//-------------------------------------------------------------------------
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// Data declarations
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extern u8 __bss_start__, __bss_end__;
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@ -49,7 +50,63 @@ extern const unsigned char cus_sig[32]; // images name
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IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 =
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{ InfraStart + 1 };
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#ifdef CONFIG_SDR_EN
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#ifdef FIX_SDR_CALIBRATION // for speed :)
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#include "rtl8195a/rtl8195a_sdr.h"
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LOCAL void sdr_init(void) {
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HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
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((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); // ROM: BIT_SYS_REGU_LDO25M_ADJ(0x0e)? HAL RAM BIT_SYS_REGU_LDO25M_ADJ(0x03)
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LDO25M_CTRL(ON);
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SRAM_MUX_CFG(0x2);
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SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE); // REG_PESOC_CLK_SEL
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HAL_PERI_ON_WRITE32(REG_GPIO_PULL_CTRL4, 0);
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ACTCK_SDR_CCTRL(ON);
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SLPCK_SDR_CCTRL(ON);
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||||
HalPinCtrlRtl8195A(SDR, 0, ON); // SDR_PIN_FCTRL(ON);
|
||||
MEM_CTRL_FCTRL(ON);
|
||||
// HalDelayUs(1000);
|
||||
// read calibration data from system data FLASH_SDRC_PARA_BASE
|
||||
union { u8 b[8]; u16 s[4]; u32 l[2]; u64 d;} value;
|
||||
u32 faddr = SPI_FLASH_BASE + FLASH_SDRC_PARA_BASE + CPU_CLOCK_SEL_VALUE*8 + CPU_CLOCK_SEL_DIV5_3*8*8; // step 8 in FLASH_SDRC_PARA_BASE[64 + 64 bytes]
|
||||
value.d = *((volatile u64 *)faddr);
|
||||
if(value.s[0] == 0xFE01 && (value.b[4]^value.b[5]) == 0xFF && (value.b[6]^value.b[7]) == 0xFF) {
|
||||
DBG_8195A("SDR flash calibration [%08x]: %02x-%02x ", faddr, value.b[4], value.b[6]);
|
||||
} else {
|
||||
value.b[4] = 0; // TapCnt
|
||||
#if CONFIG_CPU_CLK < 6
|
||||
value.b[6] = 0x11; // RdPipe
|
||||
#elif CONFIG_CPU_CLK == 7
|
||||
value.b[6] = 0x23; // RdPipe
|
||||
#else
|
||||
value.b[6] = 0x19; // RdPipe
|
||||
#endif
|
||||
DBG_8195A("Use fix SDR calibration: %02x-%02x ", value.b[4], value.b[6]);
|
||||
}
|
||||
// set all_mode _idle
|
||||
HAL_SDR_WRITE32(REG_SDR_CSR, 0x700);
|
||||
// WRAP_MISC setting
|
||||
HAL_SDR_WRITE32(REG_SDR_MISC, 0x00000001);
|
||||
// PCTL setting
|
||||
HAL_SDR_WRITE32(REG_SDR_DCR, 0x00000008);
|
||||
HAL_SDR_WRITE32(REG_SDR_IOCR, (u32)value.b[4] << PCTL_IOCR_RD_PIPE_BFO);
|
||||
HAL_SDR_WRITE32(REG_SDR_EMR2, 0x00000000);
|
||||
HAL_SDR_WRITE32(REG_SDR_EMR1, 0x00000006);
|
||||
HAL_SDR_WRITE32(REG_SDR_MR, 0x00000022);
|
||||
HAL_SDR_WRITE32(REG_SDR_DRR, 0x09030e07);
|
||||
HAL_SDR_WRITE32(REG_SDR_TPR0, 0x00002652);
|
||||
HAL_SDR_WRITE32(REG_SDR_TPR1, 0x00068873);
|
||||
HAL_SDR_WRITE32(REG_SDR_TPR2, 0x00000042);
|
||||
// start to init
|
||||
HAL_SDR_WRITE32(REG_SDR_CCR, 0x01);
|
||||
while ((HAL_SDR_READ32(REG_SDR_CCR) & 0x1) == 0x0)
|
||||
DBG_8195A(".");
|
||||
// enter mem_mode
|
||||
HAL_SDR_WRITE32(REG_SDR_CSR, 0x600);
|
||||
SDR_DDL_FCTRL((u32)value.b[6]);
|
||||
DBG_8195A(" ok\n");
|
||||
}
|
||||
#endif // FIX_SDR_CALIBRATION
|
||||
#endif // CONFIG_SDR_EN
|
||||
/*
|
||||
//----- HalNMIHandler_Patch
|
||||
void HalNMIHandler_Patch(void) {
|
||||
|
|
@ -167,30 +224,36 @@ extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
|
|||
};
|
||||
*/
|
||||
// SpicFlashInitRtl8195A(SpicDualBitMode); // SpicReadIDRtl8195A(); SpicDualBitMode
|
||||
#ifdef CONFIG_SDR_EN
|
||||
//---- SDRAM
|
||||
uint8 ChipId = HalGetChipId();
|
||||
if (ChipId >= CHIP_ID_8195AM) {
|
||||
#ifdef CONFIG_SDR_EN
|
||||
if((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена?
|
||||
if((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // SDR not init?
|
||||
#ifdef FIX_SDR_CALIBRATION // for speed :)
|
||||
sdr_init();
|
||||
#else // not FIX_SDR_CALIBRATION
|
||||
SdrCtrlInit();
|
||||
if(SdrControllerInit()) {
|
||||
if(!SdrControllerInit()) {
|
||||
DBG_8195A("SDR Controller Init fail!\n");
|
||||
};
|
||||
#endif // FIX_SDR_CALIBRATION
|
||||
};
|
||||
#endif
|
||||
// clear SDRAM bss
|
||||
extern uint8 __sdram_bss_start__[];
|
||||
extern uint8 __sdram_bss_end__[];
|
||||
if((uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__ > 0)
|
||||
memset(__sdram_bss_start__, 0, (uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__);
|
||||
}
|
||||
else
|
||||
else // if (ChipId < CHIP_ID_8195AM)
|
||||
{
|
||||
//----- SDRAM Off
|
||||
SDR_PIN_FCTRL(OFF);
|
||||
LDO25M_CTRL(OFF);
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off
|
||||
};
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init or None
|
||||
#else
|
||||
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (~BIT(21))); // Flag SDRAM Not Init
|
||||
#endif // CONFIG_SDR_EN
|
||||
//----- Close Flash
|
||||
SPI_FLASH_PIN_FCTRL(OFF);
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
//2 REG_NOT_VALID
|
||||
|
||||
//2 REG_SOC_FUNC_EN
|
||||
// BIT(21) SDRAM
|
||||
// BIT(21) if 1 -> SDRAM No ReInit
|
||||
#define BIT_SOC_SECURITY_ENGINE_EN BIT(20)
|
||||
#define BIT_SOC_GTIMER_EN BIT(16)
|
||||
#define BIT_SOC_GDMA1_EN BIT(14)
|
||||
|
|
|
|||
|
|
@ -432,6 +432,7 @@ VOID
|
|||
else {
|
||||
return 1;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1056,19 +1057,19 @@ MemTest(
|
|||
{
|
||||
u32 LoopIndex = 0;
|
||||
u32 Value32, Addr;
|
||||
for (LoopIndex = 0; LoopIndex<LoopCnt; LoopIndex++) {
|
||||
for (LoopIndex = 0; LoopIndex < LoopCnt; LoopIndex++) {
|
||||
// Value32 = Sdr_Rand2();
|
||||
// Addr = Sdr_Rand2();
|
||||
Value32 = Rand();
|
||||
Addr = Rand();
|
||||
Addr &= 0x1FFFFF;
|
||||
Addr &= (~0x3);
|
||||
|
||||
HAL_SDRAM_WRITE32(Addr, Value32);
|
||||
Addr = Rand() & 0x1FFFFC;
|
||||
|
||||
if (HAL_SDRAM_READ32(Addr) != Value32) {
|
||||
DBG_8195A("Test %d: No match addr 0x%x => 0x%x != 0x%x\n",LoopIndex,
|
||||
Addr, Value32, HAL_SDRAM_READ32(Addr));
|
||||
HAL_SDRAM_WRITE32(Addr, Value32);
|
||||
u32 x = HAL_SDRAM_READ32(Addr);
|
||||
// DBG_8195A("[%p] %p %p\n", Addr, Value32, x);
|
||||
|
||||
if (x != Value32) {
|
||||
DBG_8195A("Test %d: No match addr 0x%x => 0x%x != 0x%x\n", LoopIndex,
|
||||
Addr, Value32, x);
|
||||
return _FALSE;
|
||||
}
|
||||
else {
|
||||
|
|
|
|||
|
|
@ -177,6 +177,7 @@ SECTIONS
|
|||
LONG(0)
|
||||
UartLogRamCmdTable = .;
|
||||
KEEP(*(SORT(.mon.tab*)))
|
||||
KEEP(*(SORT(.sdram.mon.tab*)))
|
||||
UartLogRamCmdTable_end = .;
|
||||
LONG(0)
|
||||
} > BD_RAM
|
||||
|
|
|
|||
|
|
@ -121,6 +121,35 @@ SECTIONS
|
|||
KEEP(*(.image2.validate.rodata*))
|
||||
KEEP(*(.custom.validate.rodata*))
|
||||
} > BD_RAM
|
||||
|
||||
.sdr_text :
|
||||
{
|
||||
__sdram_data_start__ = .;
|
||||
INCLUDE "sdram_obj.txt"
|
||||
*(.sdram.text*)
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_rodata :
|
||||
{
|
||||
*(.sdram.rodata*)
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_data :
|
||||
{
|
||||
*(.sdram.data*)
|
||||
__sdram_data_end__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_bss :
|
||||
{
|
||||
__sdram_bss_start__ = .;
|
||||
*(.uvc.ram.bss)
|
||||
*(.sdram.bss*)
|
||||
INCLUDE "sdram_bss.txt"
|
||||
__sdram_bss_end__ = .;
|
||||
. = ALIGN(8);
|
||||
__sdram_heap_start__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.ram_image2.text :
|
||||
{
|
||||
|
|
@ -226,32 +255,6 @@ SECTIONS
|
|||
} > BD_RAM
|
||||
__ram_heap2_end__ = 0x10070000;
|
||||
|
||||
.sdr_text :
|
||||
{
|
||||
__sdram_data_start__ = .;
|
||||
*(.sdram.text*)
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_rodata :
|
||||
{
|
||||
*(.sdram.rodata*)
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_data :
|
||||
{
|
||||
*(.sdram.data*)
|
||||
__sdram_data_end__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_bss :
|
||||
{
|
||||
__sdram_bss_start__ = .;
|
||||
*(.uvc.ram.bss)
|
||||
*(.sdram.bss*)
|
||||
__sdram_bss_end__ = .;
|
||||
. = ALIGN(8);
|
||||
__sdram_heap_start__ = .;
|
||||
} > SDRAM_RAM
|
||||
__sdram_heap_end__ = 0x30200000;
|
||||
|
||||
.boot.head :
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@ mp: OTA_IMAGE = $(BIN_DIR)/ota_mp.bin
|
|||
|
||||
TST_IMAGE = $(BIN_DIR)/ram_2.bin
|
||||
|
||||
.PHONY: genbin1 genbin23 flashburn reset test readfullflash flashwebfs flash_OTA
|
||||
.PHONY: genbin1 genbin23 flashburn reset test readfullflash flashwebfs flash_OTA falshboot runsdram
|
||||
.NOTPARALLEL: all mp genbin1 genbin23 flashburn reset test readfullflash _endgenbin flashwebfs flash_OTA
|
||||
|
||||
all: $(ELFFILE) $(OTA_IMAGE) $(FLASH_IMAGE) _endgenbin
|
||||
|
|
@ -113,11 +113,13 @@ reset:
|
|||
@$(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed 1000 $(FLASHER_PATH)RTL_Reset.JLinkScript
|
||||
|
||||
runram:
|
||||
@$(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed 1000 $(FLASHER_PATH)RTL_RunRAM.JLinkScript
|
||||
$(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed 1000 $(FLASHER_PATH)RTL_RunRAM.JLinkScript
|
||||
|
||||
runsdram:
|
||||
$(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed 1000 $(FLASHER_PATH)RTL_RunRAM_SDR.JLinkScript
|
||||
|
||||
readfullflash:
|
||||
@$(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed 1000 $(FLASHER_PATH)RTL_FFlash.JLinkScript
|
||||
|
||||
|
||||
flashburn:
|
||||
@echo define call1>$(FLASHER_PATH)flash_file.jlink
|
||||
|
|
@ -145,6 +147,18 @@ flashwebfs:
|
|||
@$(GDB) -x $(FLASHER_PATH)gdb_wrfile.jlink
|
||||
#@taskkill /F /IM $(JLINK_GDBSRV)
|
||||
|
||||
flashboot:
|
||||
@echo define call1>$(FLASHER_PATH)file_info.jlink
|
||||
@echo set '$$'ImageSize = $(shell printf '0x%X\n' $$(stat --printf="%s" $(RAM1P_IMAGE)))>>$(FLASHER_PATH)file_info.jlink
|
||||
@echo set '$$'ImageAddr = 0x00000>>$(FLASHER_PATH)file_info.jlink
|
||||
@echo end>>$(FLASHER_PATH)file_info.jlink
|
||||
@echo define call2>>$(FLASHER_PATH)file_info.jlink
|
||||
@echo FlasherWrite $(RAM1P_IMAGE) '$$'ImageAddr '$$'ImageSize>>$(FLASHER_PATH)file_info.jlink
|
||||
@echo end>>$(FLASHER_PATH)file_info.jlink
|
||||
@cmd /K start $(JLINK_PATH)$(JLINK_GDBSRV) -device Cortex-M3 -if SWD -ir -endian little -speed 1000
|
||||
@$(GDB) -x $(FLASHER_PATH)gdb_wrfile.jlink
|
||||
|
||||
|
||||
flashespfs:
|
||||
@echo define call1>$(FLASHER_PATH)file_info.jlink
|
||||
@echo set '$$'ImageSize = $(shell printf '0x%X\n' $$(stat --printf="%s" $(BIN_DIR)/webpages.espfs))>>$(FLASHER_PATH)file_info.jlink
|
||||
|
|
@ -184,6 +198,12 @@ flashwebfs:
|
|||
-c "rtl8710_flash_write $(BIN_DIR)/WEBFiles.bin 0xd0000" \
|
||||
-c "rtl8710_reboot" -c "reset run" -c shutdown
|
||||
|
||||
flashboot:
|
||||
@$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \
|
||||
-c "rtl8710_flash_auto_erase 1" -c "rtl8710_flash_auto_verify 1" \
|
||||
-c "rtl8710_flash_write $(RAM1P_IMAGE) 0" \
|
||||
-c "rtl8710_reboot" -c "reset run" -c shutdown
|
||||
|
||||
flashespfs:
|
||||
@$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \
|
||||
-c "rtl8710_flash_auto_erase 1" -c "rtl8710_flash_auto_verify 1" \
|
||||
|
|
@ -194,7 +214,7 @@ reset:
|
|||
# @$(JLINK_PATH)$(JLINK_EXE) -Device CORTEX-M3 -If SWD -Speed $(FLASHER_SPEED) flasher/RTLreset.JLinkScript
|
||||
@$(OPENOCD) -f interface/$(FLASHER).cfg -c "transport select swd" -f $(FLASHER_PATH)rtl8710.ocd -c "init" -c "adapter_khz $(FLASHER_SPEED)" -c "reset halt" \
|
||||
-c "rtl8710_reboot" -c shutdown
|
||||
|
||||
|
||||
runram:
|
||||
# @$(JLINK_PATH)$(JLINK_GDB) -device Cortex-M3 -if SWD -ir -endian little -speed $(FLASHER_SPEED)
|
||||
# @$(GDB) -x flasher/gdb_run_ram.jlink
|
||||
|
|
|
|||
|
|
@ -7,6 +7,6 @@ r
|
|||
loadbin build/bin/ram_1.r.bin 0x10000bc8
|
||||
loadbin build/bin/ram_2.bin 0x10006000
|
||||
r
|
||||
w4 0x40000210,0x20111157
|
||||
w4 0x40000210,0x20011113
|
||||
g
|
||||
q
|
||||
|
|
@ -38,37 +38,38 @@ set mem inaccessible-by-default off
|
|||
# Setup GDB FOR FASTER DOWNLOADS
|
||||
set remote memory-write-packet-size 8192
|
||||
set remote memory-write-packet-size fixed
|
||||
set $SPI_FLASH_BASE = 0x98000000
|
||||
end
|
||||
#############
|
||||
# Boot_Flash
|
||||
define SetBootFlash
|
||||
printf "SetBoot = Flash:\n"
|
||||
monitor long 0x40000210 = 0x211157
|
||||
monitor long 0x40000210 = 0x00011113
|
||||
end
|
||||
# Boot RAM start_addr0() Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 )
|
||||
define SetBootCall0
|
||||
printf "SetBoot = Call0:\n"
|
||||
monitor long 0x40000210 = 0x80111157
|
||||
monitor long 0x40000210 = 0x80011113
|
||||
end
|
||||
# Boot RAM start_addr1() Run if ( v40000210 & 0x20000000 )
|
||||
define SetBootCall1
|
||||
printf "SetBoot = Call1:\n"
|
||||
monitor long 0x40000210 = 0x20111157
|
||||
monitor long 0x40000210 = 0x20011113
|
||||
end
|
||||
# Boot RAM start_addr2() Run if ( v40000210 & 0x10000000 )
|
||||
define SetBootCall2
|
||||
printf "SetBoot = Call2:\n"
|
||||
monitor long 0x40000210 = 0x10111157
|
||||
monitor long 0x40000210 = 0x10011113
|
||||
end
|
||||
# Boot RAM start_addr3() Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
|
||||
define SetBootCall3
|
||||
printf "SetBoot = Call3:\n"
|
||||
monitor long 0x40000210 = 0x8111157
|
||||
monitor long 0x40000210 = 0x8011113
|
||||
end
|
||||
# Boot RAM start_addr4() Init console, Run if ( v40000210 & 0x4000000 )
|
||||
define SetBootCall4
|
||||
printf "SetBoot = Call4:\n"
|
||||
monitor long 0x40000210 = 0x4111157
|
||||
monitor long 0x40000210 = 0x4011113
|
||||
end
|
||||
# CPU CLK 166 MHz?
|
||||
define SetClk166MHz
|
||||
|
|
@ -89,8 +90,7 @@ monitor long 0x40000304 = 0x1FC00002
|
|||
monitor long 0x40000250 = 0x400
|
||||
monitor long 0x40000340 = 0x0
|
||||
monitor long 0x40000230 = 0xdcc4
|
||||
monitor long 0x40000210 = 0x11117
|
||||
monitor long 0x40000210 = 0x11157
|
||||
monitor long 0x40000210 = 0x11113
|
||||
monitor long 0x400002c0 = 0x110011
|
||||
monitor long 0x40000320 = 0xffffffff
|
||||
end
|
||||
|
|
@ -125,7 +125,6 @@ monitor long 0x40006018 = 0
|
|||
monitor long 0x4000601C = 0
|
||||
#disable DMA
|
||||
monitor long 0x4000604C = 0
|
||||
set $SPI_FLASH_BASE = 0x98000000
|
||||
end
|
||||
###################
|
||||
# SetFirwareSize #
|
||||
|
|
@ -154,7 +153,26 @@ if $Image1Size != 0 && $Image1Size < 0x1000000
|
|||
printf "Image2Size = %d\n", $Image2Size
|
||||
printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
|
||||
set $FirmwareSize = $Image2Addr + $Image2Size
|
||||
printf "FirmwareSize = %d\n", $FirmwareSize
|
||||
set $Image3Addr = $FirmwareSize
|
||||
set $parms1 = $rambuffer - $FirmwareSize
|
||||
set $parms3 = $Image3Addr + 0x08
|
||||
restore $arg0 binary $parms1 $Image3Addr $parms3
|
||||
set $Image3Size = {int}($rambuffer)
|
||||
set $Image3LoadAddr = {int}($rambuffer+0x4)
|
||||
if $Image3Size != 0xFFFFFFFF && $Image3Size != 0
|
||||
set $Image3Size = $Image3Size + 16
|
||||
printf "Image3Size = %d\n", $Image3Size
|
||||
printf "Image3LoadAddr = 0x%08x\n", $Image3LoadAddr
|
||||
set $FirmwareSize = $Image3Addr + $Image3Size
|
||||
printf "FirmwareSize = %d\n", $FirmwareSize
|
||||
else
|
||||
set $Image3Size = 0
|
||||
if $Image3LoadAddr == 0x30000000
|
||||
set $FirmwareSize = $FirmwareSize + 8
|
||||
end
|
||||
printf "Image3 - None\n"
|
||||
printf "FirmwareSize = %d\n", $FirmwareSize
|
||||
end
|
||||
else
|
||||
set $Image2Size = 0
|
||||
printf "Image2 - None\n"
|
||||
|
|
@ -164,7 +182,9 @@ if $Image1Size != 0 && $Image1Size < 0x1000000
|
|||
else
|
||||
set $Image1Size = 0
|
||||
set $Image2Size = 0
|
||||
set $Image3Size = 0
|
||||
set $Image2Addr = 0
|
||||
set $Image3Addr = 0
|
||||
set $FirmwareSize = 0
|
||||
printf "Image not format Firmware!\n"
|
||||
end
|
||||
|
|
@ -173,6 +193,10 @@ end
|
|||
# Flash Images Info #
|
||||
#####################
|
||||
define FlashImagesInfo
|
||||
set $Image2Size = 0
|
||||
set $Image3Size = 0
|
||||
set $Image2Addr = 0
|
||||
set $Image3Addr = 0
|
||||
printf "Flash Info:\n"
|
||||
set $Image1Size = {int}($SPI_FLASH_BASE + 0x10) + 32
|
||||
set $Image1LoadAddr = {int}($SPI_FLASH_BASE + 0x14)
|
||||
|
|
@ -181,16 +205,26 @@ printf "Image1 - None\n"
|
|||
else
|
||||
set $Image2FlashAddr = {short}($SPI_FLASH_BASE + 0x18) * 1024
|
||||
if $Image2FlashAddr == 0
|
||||
$Image2FlashAddr = $Image1Size
|
||||
set $Image2FlashAddr = $Image1Size
|
||||
end
|
||||
set $Image2Size = {int}($Image2FlashAddr + $SPI_FLASH_BASE)
|
||||
set $Image2LoadAddr = {int}($Image2FlashAddr + $SPI_FLASH_BASE + 0x4)
|
||||
printf "Image1Size = %d\n", $Image1Size
|
||||
printf "Image1LoadAddr = 0x%08x\n", $Image1LoadAddr
|
||||
printf "Image2FlashAddr = 0x%08x\n", $Image2FlashAddr
|
||||
if $Image2Size != 0xFFFFFFFF
|
||||
if $Image2Size != 0xFFFFFFFF && $Image2Size != 0
|
||||
printf "Image2Size = %d\n", $Image2Size
|
||||
printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
|
||||
set $Image3FlashAddr = $Image2FlashAddr + $Image2Size + 0x10
|
||||
set $Image3Size = {int}($Image3FlashAddr + $SPI_FLASH_BASE)
|
||||
set $Image3LoadAddr = {int}($Image3FlashAddr + $SPI_FLASH_BASE + 0x4)
|
||||
if $Image3Size != 0xFFFFFFFF && $Image3Size !=0
|
||||
printf "Image3FlashAddr = 0x%08x\n", $Image3FlashAddr
|
||||
printf "Image3Size = %d\n", $Image3Size
|
||||
printf "Image3LoadAddr = 0x%08x\n", $Image3LoadAddr
|
||||
else
|
||||
printf "Image3 - None\n"
|
||||
end
|
||||
else
|
||||
printf "Image2 - None\n"
|
||||
end
|
||||
|
|
|
|||
|
|
@ -7,7 +7,6 @@ set $rtl8710_flasher_auto_erase = 1
|
|||
set $rtl8710_flasher_auto_verify = 1
|
||||
set $rtl8710_flasher_firmware_ptr = 0x10001000
|
||||
set $rtl8710_flasher_buffer = 0x10008000
|
||||
#262144
|
||||
set $rtl8710_flasher_buffer_size = 421888
|
||||
set $rtl8710_flasher_sector_size = 4096
|
||||
set $rtl8710_flasher_auto_erase_sector = 0xFFFFFFFF
|
||||
|
|
@ -37,12 +36,11 @@ if $rtl8710_flasher_capacity == 0
|
|||
monitor go
|
||||
FlasherWait
|
||||
set $id = {int}($rtl8710_flasher_buffer + 0x0C)
|
||||
set $rtl8710_flasher_capacity = 1 << (($id >> 16) & 0x0ff)
|
||||
if ($id == 0x1420c2)
|
||||
set $rtl8710_flasher_capacity = 1 << (($id >> 16) & 0x0ff)
|
||||
printf "Flash ID = 0x%08x : MX25L8006E (%d kbytes)\n", $id, $rtl8710_flasher_capacity>>10
|
||||
else
|
||||
set $rtl8710_flasher_capacity = 1024*1024)
|
||||
error "Flash ID = 0x%08x : ?\n", $id
|
||||
printf "Flash ID = 0x%08x : (%d kbytes)\n", $id, $rtl8710_flasher_capacity>>10
|
||||
end
|
||||
printf "RTL8710 flasher initialized\n"
|
||||
else
|
||||
|
|
@ -108,9 +106,9 @@ while $offset < $size
|
|||
end
|
||||
set $flash_offset = $arg1 + $offset
|
||||
printf "write offset 0x%08x\n", $flash_offset
|
||||
set $parms1 = $rtl8710_flasher_buffer + 0x20 - $offset - $arg1
|
||||
set $parms2 = $offset + $arg1
|
||||
set $parms3 = $offset + $len + $arg1
|
||||
set $parms1 = $rtl8710_flasher_buffer + 0x20 - $flash_offset
|
||||
set $parms2 = $flash_offset
|
||||
set $parms3 = $flash_offset + $len
|
||||
restore $arg0 binary $parms1 $parms2 $parms3
|
||||
if $rtl8710_flasher_auto_erase != 0
|
||||
set $count_i = $flash_offset
|
||||
|
|
@ -153,8 +151,13 @@ if $Image1Size != 0
|
|||
printf "Write Image1 size %d to Flash addr 0x00000000:\n", $Image1Size
|
||||
#FlasherWrite $wr_flile 0 $Image1Size
|
||||
call2
|
||||
if $Image2Size != 0 && $Image2Addr >= $Image1Size
|
||||
printf "Write Image2 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
|
||||
if $Image2Size != 0 && $Image2Addr >= $Image1Size
|
||||
if $Image3Size != 0 && $Image3Addr > $Image2Size
|
||||
set $Image2Size = $Image2Size + $Image3Size
|
||||
printf "Write Image2&3 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
|
||||
else
|
||||
printf "Write Image2 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
|
||||
end
|
||||
#FlasherWrite $wr_flile $Image2Addr $Image2Size
|
||||
call3
|
||||
end
|
||||
|
|
|
|||
|
|
@ -48,7 +48,12 @@ endif
|
|||
|
||||
# m c nosys gcc
|
||||
PATHLIBS = sdk/component/soc/realtek/8195a/misc/bsp/lib/common/gcc
|
||||
ifdef USE_SDRAM
|
||||
CFLAGS += -DUSE_SDRAM=1
|
||||
LDFILE ?= rlx8195A-symbol-v04-img3.ld
|
||||
else
|
||||
LDFILE ?= rlx8195A-symbol-v04-img2.ld
|
||||
endif
|
||||
BOOTS = sdk/component/soc/realtek/8195a/misc/bsp/image
|
||||
|
||||
# Include folder list
|
||||
|
|
@ -138,8 +143,8 @@ SRC_C += sdk/component/common/api/wifi/wifi_simple_config.c
|
|||
SRC_C += sdk/component/common/api/wifi/wifi_util.c
|
||||
SRC_C += sdk/component/common/api/lwip_netconf.c
|
||||
ifdef USE_WIFI_API
|
||||
SRC_C += sdk/component/common/api/wifi_api.c
|
||||
SRC_C += sdk/component/common/api/wifi_api_scan.c
|
||||
DRAM_C += sdk/component/common/api/wifi_api.c
|
||||
DRAM_C += sdk/component/common/api/wifi_api_scan.c
|
||||
endif
|
||||
|
||||
#network - lwip
|
||||
|
|
@ -179,9 +184,9 @@ SRC_C += sdk/component/common/network/lwip/$(LWIPDIR)/src/netif/etharp.c
|
|||
SRC_C += sdk/component/common/network/lwip/$(LWIPDIR)/port/realtek/freertos/ethernetif.c
|
||||
SRC_C += sdk/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c
|
||||
SRC_C += sdk/component/common/network/lwip/$(LWIPDIR)/port/realtek/freertos/sys_arch.c
|
||||
SRC_C += sdk/component/common/network/dhcp/dhcps.c
|
||||
SRC_C += sdk/component/common/network/sntp/sntp.c
|
||||
SRC_C += sdk/component/common/network/netbios/netbios.c
|
||||
DRAM_C += sdk/component/common/network/dhcp/dhcps.c
|
||||
DRAM_C += sdk/component/common/network/sntp/sntp.c
|
||||
DRAM_C += sdk/component/common/network/netbios/netbios.c
|
||||
|
||||
#network - mdns
|
||||
#SRC_C += sdk/component/common/network/mDNS/mDNSPlatform.c
|
||||
|
|
@ -406,18 +411,18 @@ ADD_SRC_C =
|
|||
# -------------------------------------------------------------------
|
||||
ifdef USE_AT
|
||||
INCLUDES += sdk/component/common/utilities
|
||||
ADD_SRC_C += sdk/component/common/api/network/src/wlan_network.c
|
||||
ADD_SRC_C += sdk/component/common/api/wifi_interactive_mode.c
|
||||
ADD_SRC_C += sdk/component/common/api/network/src/ping_test.c
|
||||
ADD_SRC_C += sdk/component/common/utilities/webserver.c
|
||||
ADD_SRC_C += sdk/component/common/utilities/tcptest.c
|
||||
ADD_SRC_C += sdk/component/common/utilities/update.c
|
||||
DRAM_C += sdk/component/common/api/network/src/wlan_network.c
|
||||
DRAM_C += sdk/component/common/api/wifi_interactive_mode.c
|
||||
DRAM_C += sdk/component/common/api/network/src/ping_test.c
|
||||
DRAM_C += sdk/component/common/utilities/webserver.c
|
||||
DRAM_C += sdk/component/common/utilities/tcptest.c
|
||||
DRAM_C += sdk/component/common/utilities/update.c
|
||||
INCLUDES += sdk/component/common/example
|
||||
INCLUDES += sdk/component/common/example/wlan_fast_connect
|
||||
ADD_SRC_C += sdk/component/common/example/wlan_fast_connect/example_wlan_fast_connect.c
|
||||
ADD_SRC_C += sdk/component/common/example/uart_atcmd/example_uart_atcmd.c
|
||||
ADD_SRC_C += sdk/component/common/example/example_entry.c
|
||||
ADD_SRC_C += sdk/component/common/application/xmodem/uart_fw_update.c
|
||||
DRAM_C += sdk/component/common/example/wlan_fast_connect/example_wlan_fast_connect.c
|
||||
DRAM_C += sdk/component/common/example/uart_atcmd/example_uart_atcmd.c
|
||||
DRAM_C += sdk/component/common/example/example_entry.c
|
||||
DRAM_C += sdk/component/common/application/xmodem/uart_fw_update.c
|
||||
endif
|
||||
#application
|
||||
#INCLUDES += sdk/component/common/application/apple/WACServer/External/Curve25519
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue