mirror of
https://github.com/pvvx/RTL00MP3.git
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update -Wall -Werror
This commit is contained in:
pvvx
parent
2c29a376ba
commit
7cb9553f73
102 changed files with 3686 additions and 3504 deletions
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@ -6,7 +6,8 @@ Module RTL00(RTL8710AF), [F11AMIM13](http://fn-link.en.made-in-china.com/product
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[PADI](https://www.pine64.org/?page_id=946) (RTL8710AF), [F10AFIM13-B1](http://en.ofeixin.com/products_detail/productId=65.html) (RTL8710AF), [TinyCon2005-A-BE](http://www.ralinwi.com/product.aspx?info_lb=54&flag=1) (RTL8711AF),<br>
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[WFM-400](http://www.rayson.com/rayson/en/?pros=product&pros=product&b_cat_id=A03&m_cat_id=A0304&s_cat_id=A030401&prod_id=P0113&level=3) (RTL8711AM), [WFM-410](http://www.rayson.com/rayson/en/?pros=product&pros=product&b_cat_id=A03&m_cat_id=A0304&s_cat_id=A030401&prod_id=P0114&level=3) (RTL8711AF), [WFM-250](http://www.rayson.com/rayson/en/?pros=product&pros=product&b_cat_id=A03&m_cat_id=A0304&s_cat_id=A030401&prod_id=P0112&level=3) (RTL8195AM),<br>
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[AW-CU238, AW-CU239](https://www.buyiot.net/pd-1) (RTL8711AM), [AW-CU245, AW-CU245, AW-CU245](https://www.buyiot.net/home-1) (RTL8711AM/RTL8195AM/RTL8711AF),<br>
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[WG6611](http://www.jorjin.com/product.php?id=98) (RTL8711AM), [RAK473](http://www.rakwireless.com/en/download/RAK473/Firmware%20Upgrade) (RTL8711AM), [RAK474, RAK476](http://www.rakwireless.com/en/download/RAK473/Firmware%20Upgrade) (RTL8711AF), ...<br>
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[WG6611](http://www.jorjin.com/product.php?id=98) (RTL8711AM), [RAK473](http://www.rakwireless.com/en/download/RAK473/Firmware%20Upgrade) (RTL8711AM), [RAK474, RAK476](http://www.rakwireless.com/en/download/RAK473/Firmware%20Upgrade) (RTL8711AF), [6110R-IF](http://en.ofeixin.com/products_detail/productId=65.html) (RTL8710AF),<br>
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[MJIOT-AMB-01](http://www.nb-iot-tech.com/mjiot-amb-01-en.html) (RTL8710AF), [MJIOT-AMB-02](http://www.nb-iot-tech.com/mjiot-amb-02-en.html) (RTL8195AM), ...<br>
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RTL00 module (RTL8710AF)<br>
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@ -184,7 +184,9 @@ uint8_t LwIP_DHCP(uint8_t idx, uint8_t dhcp_state) {
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struct ip_addr netmask;
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struct ip_addr gw;
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uint32_t IPaddress;
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#if CONFIG_DEBUG_LOG > 2
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uint8_t iptab[4];
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#endif
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uint8_t DHCP_state;
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int mscnt = 0;
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struct netif *pnetif = NULL;
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@ -228,12 +230,14 @@ uint8_t LwIP_DHCP(uint8_t idx, uint8_t dhcp_state) {
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/* Stop DHCP */
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// dhcp_stop(pnetif); /* can not stop, need to renew, Robbie*/
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#if CONFIG_DEBUG_LOG > 2
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iptab[0] = (uint8_t) (IPaddress >> 24);
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iptab[1] = (uint8_t) (IPaddress >> 16);
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iptab[2] = (uint8_t) (IPaddress >> 8);
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iptab[3] = (uint8_t) (IPaddress);
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info_printf("Interface %d IP address: %d.%d.%d.%d\n", idx, iptab[3],
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iptab[2], iptab[1], iptab[0]);
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#endif
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#if CONFIG_WLAN
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error_flag = RTW_NO_ERROR;
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#endif
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@ -251,6 +255,7 @@ uint8_t LwIP_DHCP(uint8_t idx, uint8_t dhcp_state) {
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IP4_ADDR(&netmask, NETMASK_ADDR0, NETMASK_ADDR1, NETMASK_ADDR2, NETMASK_ADDR3);
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IP4_ADDR(&gw, GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3);
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netif_set_addr(pnetif, &ipaddr, &netmask, &gw);
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#if CONFIG_DEBUG_LOG > 2
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iptab[0] = IP_ADDR3;
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iptab[1] = IP_ADDR2;
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@ -258,6 +263,7 @@ uint8_t LwIP_DHCP(uint8_t idx, uint8_t dhcp_state) {
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iptab[3] = IP_ADDR0;
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info_printf("Interface %d DHCP timeout\n", idx);
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info_printf("Static IP address: %d.%d.%d.%d\n", iptab[3], iptab[2], iptab[1], iptab[0]);
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#endif
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#if CONFIG_WLAN
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error_flag = RTW_DHCP_FAIL;
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#endif
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@ -9,22 +9,30 @@
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#define DATA_IRAM_ATTR
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#define ICACHE_RAM_ATTR
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#define os_printf(...) rtl_printf(__VA_ARGS__)
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#define os_printf_plus(...) rtl_printf(__VA_ARGS__)
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#define os_sprintf_fd(...) rtl_sprintf(__VA_ARGS__)
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#define ets_sprintf(...) rtl_sprintf(__VA_ARGS__)
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#ifndef os_malloc
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#define os_malloc pvPortMalloc
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#define os_zalloc pvPortZalloc
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#define os_calloc pvPortCalloc
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#define os_realloc pvPortRealloc
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#endif
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#undef os_free
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#define os_free vPortFree
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#define system_get_free_heap_size xPortGetFreeHeapSize
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#undef os_realloc
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#define os_realloc pvPortReAlloc
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#define os_printf rtl_printf
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#define os_printf_plus rtl_printf
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#define os_sprintf_fd rtl_sprintf
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#define ets_sprintf rtl_sprintf
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//#ifndef os_malloc
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#undef os_malloc
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extern void *pvPortMalloc(size_t xWantedSize);
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#define os_malloc pvPortMalloc
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#undef os_zalloc
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extern void *pvPortZalloc(size_t xWantedSize);
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#define os_zalloc pvPortZalloc
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//#undef os_calloc
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//#define os_calloc pvPortCalloc
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#undef os_realloc
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extern void *pvPortReAlloc(void *pv, size_t xWantedSize);
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#define os_realloc pvPortReAlloc
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#undef os_free
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extern void vPortFree(void *pv);
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#define os_free vPortFree
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//#endif
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extern size_t xPortGetFreeHeapSize(void);
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#define system_get_free_heap_size xPortGetFreeHeapSize
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#define os_bzero rtl_bzero
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#define os_delay_us wait_us // HalDelayUs
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@ -104,22 +112,28 @@ extern SpiFlashChip * flashchip; // in RAM-BIOS: 0x3fffc714
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#define spi_flash_read(faddr, pbuf, size) flash_stream_read(&flashobj, faddr, size, (uint8_t *)pbuf)
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#define spi_flash_erase_block(blk) flash_erase_block(&flashobj, (blk)<<16);
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#ifndef ip4_addr1
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#define ip4_addr1(ipaddr) (((u8_t*)(ipaddr))[0])
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#define ip4_addr2(ipaddr) (((u8_t*)(ipaddr))[1])
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#define ip4_addr3(ipaddr) (((u8_t*)(ipaddr))[2])
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#define ip4_addr4(ipaddr) (((u8_t*)(ipaddr))[3])
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#endif
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/* These are cast to u16_t, with the intent that they are often arguments
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* to printf using the U16_F format from cc.h. */
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#ifndef ip4_addr1_16
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#define ip4_addr1_16(ipaddr) ((u16_t)ip4_addr1(ipaddr))
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#define ip4_addr2_16(ipaddr) ((u16_t)ip4_addr2(ipaddr))
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#define ip4_addr3_16(ipaddr) ((u16_t)ip4_addr3(ipaddr))
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#define ip4_addr4_16(ipaddr) ((u16_t)ip4_addr4(ipaddr))
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#endif
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#undef IP2STR
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#define IP2STR(ipaddr) ip4_addr1_16(ipaddr), \
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ip4_addr2_16(ipaddr), \
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ip4_addr3_16(ipaddr), \
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ip4_addr4_16(ipaddr)
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#undef IPSTR
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#define IPSTR "%d.%d.%d.%d"
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#ifndef MAC2STR
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@ -95,11 +95,11 @@
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#define memset rtl_memset
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#define strcat rtl_strcat
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#define strchr rtl_strchr
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#define strcmp(s1, s2) rtl_strcmp((const char *)s1, (const char *)s2)
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#define strcmp rtl_strcmp
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#define strcpy rtl_strcpy
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#define strlen(str) rtl_strlen((const char *)str)
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#define strlen rtl_strlen
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#define strncat rtl_strncat
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#define strncmp(s1, s2, n) rtl_strncmp((const char *)s1, (const char *)s2, n)
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#define strncmp rtl_strncmp
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#define strncpy rtl_strncpy
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#define strstr rtl_strstr
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#define strsep rtl_strsep
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@ -157,13 +157,22 @@
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//
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// memory management
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//
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#ifndef CONFIG_MBED_ENABLED
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extern void *pvPortMalloc( size_t xWantedSize );
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extern void vPortFree( void *pv );
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#undef malloc
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extern void *pvPortMalloc(size_t xWantedSize);
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#define malloc pvPortMalloc
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#undef zalloc
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extern void *pvPortZalloc(size_t xWantedSize);
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#define zalloc pvPortZalloc
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#undef realloc
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extern void *pvPortReAlloc(void *pv, size_t xWantedSize);
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#define realloc pvPortReAlloc
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#undef free
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extern void vPortFree(void *pv);
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#define free vPortFree
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#endif
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#elif defined (CONFIG_PLATFORM_8711B)
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#if defined (__IARSTDLIB__)
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@ -16,6 +16,8 @@
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#endif
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#include <lwip_netconf.h>
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#include <osdep_service.h>
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#include "dhcp.h"
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#include "dhcp/dhcps.h"
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#if CONFIG_EXAMPLE_WLAN_FAST_CONNECT
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#include "wlan_fast_connect/example_wlan_fast_connect.h"
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@ -157,6 +159,9 @@ extern unsigned char dhcp_mode_sta;
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#include "freertos/wrapper.h"
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#include "skbuff.h"
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extern int is_promisc_enabled();
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extern int promisc_set(rtw_rcr_level_t enabled, void (*callback)(u8 *, unsigned int, void *), int len_used);
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//------------------------------------------------------------------------end-patch//
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static int wifi_connect_local(rtw_network_info_t *pWifi) {
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int ret = 0;
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@ -278,8 +283,8 @@ static void wifi_disconn_hdl(char* buf, int buf_len, int flags, void* userdata)
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else if (rtw_join_status == 0)
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error_flag = RTW_CONNECT_FAIL;
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else if (rtw_join_status == JOIN_COMPLETE | JOIN_SECURITY_COMPLETE
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| JOIN_ASSOCIATED | JOIN_AUTHENTICATED | JOIN_LINK_READY)
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else if (rtw_join_status == (JOIN_COMPLETE | JOIN_SECURITY_COMPLETE
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| JOIN_ASSOCIATED | JOIN_AUTHENTICATED | JOIN_LINK_READY))
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error_flag = RTW_WRONG_PASSWORD;
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}
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@ -368,6 +373,7 @@ void restore_wifi_info_to_flash() {
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#endif
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extern int wext_set_bssid(const char *ifname, const __u8 *bssid);
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//----------------------------------------------------------------------------//
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int wifi_connect(
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unsigned char bssid[ETH_ALEN],
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@ -380,7 +386,7 @@ int wifi_connect(
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int ssid_len = 0;
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int password_len = 0;
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int bssid_len = 6;
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// int bssid_len = 6;
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xSemaphoreHandle join_semaphore;
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rtw_result_t result = RTW_SUCCESS;
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u8 wep_hex = 0;
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@ -440,7 +446,7 @@ int wifi_connect(
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if (password_len == 10) {
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u32 g[5] = { 0 };
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unsigned int g[5] = { 0 };
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u8 i = 0;
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sscanf((const char*) password, "%02x%02x%02x%02x%02x", &g[0],
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&g[1], &g[2], &g[3], &g[4]);
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@ -450,7 +456,7 @@ int wifi_connect(
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password_len = 5;
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wep_hex = 1;
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} else if (password_len == 26) {
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u32 g[13] = { 0 };
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unsigned int g[13] = { 0 };
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u8 i = 0;
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sscanf((const char*) password, "%02x%02x%02x%02x%02x%02x%02x"
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"%02x%02x%02x%02x%02x%02x", &g[0], &g[1], &g[2], &g[3],
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@ -731,6 +737,8 @@ int wifi_get_ap_info(rtw_bss_info_t * ap_info, rtw_security_t* security) {
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return ret;
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}
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extern int wext_get_drv_ability(const char *ifname, uint32_t *ability);
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int wifi_get_drv_ability(uint32_t *ability) {
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return wext_get_drv_ability(WLAN0_NAME, ability);
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}
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@ -948,6 +956,8 @@ int wifi_get_last_error(void) {
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int wpas_wps_init(const char* ifname);
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#endif
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extern int set_hidden_ssid(const char *ifname, uint8_t value);
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int wifi_start_ap(char *ssid, rtw_security_t security_type, char *password, int channel, char ssid_hidden) {
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const char *ifname = WLAN0_NAME;
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int ssid_len = 0;
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@ -1543,10 +1553,8 @@ int wifi_restart_ap(unsigned char *ssid, rtw_security_t security_type,
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printf("AP: security_type=%d\n", setting.security_type);
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printf("AP: password=%s\n", (char* )setting.password);
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printf("AP: key_idx =%d\n", setting.key_idx);
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ret = wifi_connect((char*) setting.ssid, setting.security_type,
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(char*) setting.password, strlen((char* )setting.ssid),
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strlen((char* )setting.password), setting.key_idx,
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NULL);
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ret = wifi_connect(NULL, 0 , (char*) setting.ssid, setting.security_type,
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(char*) setting.password, setting.key_idx, NULL);
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if (ret == RTW_SUCCESS) {
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#if CONFIG_DHCP_CLIENT
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/* Start DHCPClient */
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@ -1726,6 +1734,9 @@ int wifi_remove_packet_filter(unsigned char filter_id) {
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#endif
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#ifdef CONFIG_AP_MODE
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extern int wext_enable_forwarding(const char *ifname);
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extern int wext_disable_forwarding(const char *ifname);
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int wifi_enable_forwarding(void) {
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return wext_enable_forwarding(WLAN0_NAME);
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}
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@ -1739,6 +1750,8 @@ int wifi_disable_forwarding(void) {
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* usage: wifi_set_ch_deauth(0) -> wlan0 wifi_connect -> wifi_set_ch_deauth(1)
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*/
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#ifdef CONFIG_CONCURRENT_MODE
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extern int wext_set_ch_deauth(const char *ifname, __u8 enable);
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int wifi_set_ch_deauth(__u8 enable) {
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return wext_set_ch_deauth(WLAN1_NAME, enable);
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}
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@ -102,7 +102,7 @@ void wifi_indication(WIFI_EVENT_INDICATE event, unsigned char *buf, int buf_len,
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// , and tries not to share the same stack with wlan driver if remaining stack space is
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// not available for the following operations.
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// ex: using semaphore to notice another thread.
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switch (event) {
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switch ((int)event) {
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case WIFI_EVENT_DISCONNECT:
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#if(WIFI_INDICATE_MSG>0)
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info_printf("%s(%d): Disconnection indication received\n", __func__, event);
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@ -19,9 +19,8 @@
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extern void _promisc_deinit(_adapter *padapter);
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extern int _promisc_recv_func(_adapter *padapter, recv_frame *rframe);
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extern int _promisc_set(rtw_rcr_level_t enabled, void (*callback)(unsigned char *, unsigned int, void *), unsigned char len_used);
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extern unsigned char is_promisc_enabled(void);
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extern int promisc_get_fixed_channel(void *fixed_bssid, unsigned char *ssid, int *ssid_length);
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extern unsigned char is_promisc_enabled(void);
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extern unsigned char _is_promisc_enabled(void);
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extern int _promisc_get_fixed_channel(void *fixed_bssid, unsigned char *ssid, int *ssid_length);
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#endif
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@ -111,7 +110,7 @@ static struct eth_buffer eth_buffer;
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#ifdef CONFIG_PROMISC
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#define MAX_PACKET_FILTER_INFO 5
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#define FILTER_ID_INIT_VALUE 10
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rtw_packet_filter_info_t paff_array[MAX_PACKET_FILTER_INFO]={0, 0, 0, 0, 0};
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rtw_packet_filter_info_t paff_array[MAX_PACKET_FILTER_INFO]; // ={0, 0, 0, 0, 0};
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static u8 packet_filter_enable_num = 0;
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void promisc_init_packet_filter()
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@ -209,7 +209,7 @@ int wext_get_passphrase(const char *ifname, __u8 *passphrase) {
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rtw_result_t ret = RTW_ERROR;
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if(pdev) {
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uint16 len[4];
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ret = rtw_wx_get_passphrase(pdev, 0, &len, passphrase);
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ret = rtw_wx_get_passphrase(pdev, 0,(union iwreq_data *) &len, passphrase);
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if(ret == RTW_SUCCESS) passphrase[len[2]] = '\0';
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debug_printf("pas[%d]-<%s>\n", len[2], passphrase);
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}
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@ -404,7 +404,6 @@ int wext_get_lps_dtim(const char *ifname, __u8 *lps_dtim) {
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int wext_set_tos_value(const char *ifname, __u8 *tos_value) {
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struct iwreq iwr;
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int ret = -1;
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__u8 para[sizeof("set_tos_value") + 4];
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int cmd_len = sizeof("set_tos_value");
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memset(&iwr, 0, sizeof(iwr));
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@ -562,6 +561,8 @@ int wext_get_mode(const char *ifname, int *mode) {
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#endif
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}
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|
||||
extern int rtw_wx_set_ap_essid(struct net_device *dev, struct iw_request_info *a, union iwreq_data *wrqu, char *extra);
|
||||
|
||||
int wext_set_ap_ssid(const char *ifname, const __u8 *ssid, __u16 ssid_len) {
|
||||
#ifdef USE_WIFI_ADAPTER
|
||||
struct net_device * pdev = rltk_wlan_info[0].dev;
|
||||
|
|
@ -572,7 +573,7 @@ int wext_set_ap_ssid(const char *ifname, const __u8 *ssid, __u16 ssid_len) {
|
|||
uint16 len[2];
|
||||
len[0] = ssid_len;
|
||||
len[1] = (ssid_len != 0);
|
||||
ret = rtw_wx_set_ap_essid(pdev, 0, &len, ssid);
|
||||
ret = rtw_wx_set_ap_essid(pdev, 0, (union iwreq_data *) &len, (char *)ssid);
|
||||
}
|
||||
return ret;
|
||||
#else
|
||||
|
|
@ -751,7 +752,7 @@ int wext_private_command_with_retval(const char *ifname, char *cmd,
|
|||
iwr.u.data.length = buf_size;
|
||||
iwr.u.data.flags = 0;
|
||||
ret = iw_ioctl(ifname, SIOCDEVPRIVATE, &iwr);
|
||||
if (ret >= 0 & ret_buf != NULL) {
|
||||
if (ret >= 0 && ret_buf != NULL) {
|
||||
if (ret_len > iwr.u.data.length)
|
||||
ret_len = iwr.u.data.length;
|
||||
memcpy(ret_buf, (char *) iwr.u.data.pointer, ret_len);
|
||||
|
|
@ -923,7 +924,6 @@ int wext_set_gen_ie(const char *ifname, char *buf, __u16 buf_len, __u16 flags) {
|
|||
int wext_set_autoreconnect(const char *ifname, __u8 mode, __u8 retyr_times,
|
||||
__u16 timeout) {
|
||||
struct iwreq iwr;
|
||||
int ret = 0;
|
||||
__u8 para[sizeof("SetAutoRecnt") + 4];
|
||||
int cmd_len = sizeof("SetAutoRecnt");
|
||||
memset(&iwr, 0, sizeof(iwr));
|
||||
|
|
@ -1017,7 +1017,7 @@ int wext_update_custom_ie(const char *ifname, void * cus_ie, int ie_index) {
|
|||
#endif
|
||||
} else {
|
||||
memset(&iwr, 0, sizeof(iwr));
|
||||
cmd_len = para = pvPortMalloc((4) * 2 + cmd_len); //size:addr len+cmd_len
|
||||
para = pvPortMalloc((4) * 2 + cmd_len); //size:addr len+cmd_len
|
||||
if (para != NULL) {
|
||||
//Cmd
|
||||
snprintf(para, cmd_len, "UpdateIE");
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@ STATION_CONFIG wifi_st_cfg = {
|
|||
.ssid = DEF_ST_SSID,
|
||||
.password = DEF_ST_PASSWORD,
|
||||
.bssid = DEF_ST_BSSID,
|
||||
.flg = DEF_ST_BSSID,
|
||||
.flg = DEF_ST_USE_BSSID,
|
||||
.security = DEF_ST_SECURITY,
|
||||
.autoreconnect = DEF_ST_AUTORECONNECT,
|
||||
.reconnect_pause = DEF_ST_RECONNECT_PAUSE,
|
||||
|
|
@ -204,8 +204,8 @@ LOCAL int wlan_init_done_callback(void) {
|
|||
//char wlan_st_name[] = WLAN0_NAME;
|
||||
char wlan_st_name[] = WLAN0_NAME;
|
||||
char wlan_ap_name[] = WLAN1_NAME;
|
||||
char wlan_st_netifn = 0;
|
||||
char wlan_ap_netifn = 1;
|
||||
unsigned char wlan_st_netifn = 0;
|
||||
unsigned char wlan_ap_netifn = 1;
|
||||
|
||||
|
||||
uint32 get_new_ip(void)
|
||||
|
|
@ -256,7 +256,7 @@ extern Rltk_wlan_t rltk_wlan_info[2]; // in wrapper.h
|
|||
};*/
|
||||
#define get_padapter(num) (*(_adapter **)((rltk_wlan_info[num].dev)->priv));
|
||||
|
||||
LOCAL rtw_result_t _wext_set_lps_dtim(int adapter_num, uint8 lps_dtim ) {
|
||||
rtw_result_t _wext_set_lps_dtim(int adapter_num, uint8 lps_dtim ) {
|
||||
_adapter * pad = get_padapter(adapter_num);
|
||||
rtw_result_t ret = RTW_ERROR;
|
||||
if(pad) {
|
||||
|
|
@ -265,7 +265,7 @@ LOCAL rtw_result_t _wext_set_lps_dtim(int adapter_num, uint8 lps_dtim ) {
|
|||
return ret;
|
||||
}
|
||||
|
||||
LOCAL rtw_result_t _wext_enable_powersave(int adapter_num, uint8 ips_mode, uint8 lps_mode) {
|
||||
rtw_result_t _wext_enable_powersave(int adapter_num, uint8 ips_mode, uint8 lps_mode) {
|
||||
_adapter * pad = get_padapter(adapter_num);
|
||||
rtw_result_t ret = RTW_ERROR;
|
||||
if(pad) {
|
||||
|
|
@ -278,7 +278,7 @@ LOCAL rtw_result_t _wext_enable_powersave(int adapter_num, uint8 ips_mode, uint8
|
|||
return ret;
|
||||
}
|
||||
|
||||
LOCAL int _wext_cmp_ssid(int adapter_num, uint8 *ssid)
|
||||
LOCAL int _wext_cmp_ssid(int adapter_num, unsigned char *ssid)
|
||||
{
|
||||
_adapter * pad = get_padapter(adapter_num);
|
||||
int ret = 0;
|
||||
|
|
@ -357,7 +357,7 @@ LOCAL rtw_result_t wifi_run_ap(void) {
|
|||
int timeout = wifi_test_timeout_ms / wifi_test_timeout_step_ms;
|
||||
while (1) {
|
||||
#if 1
|
||||
if (_wext_cmp_ssid(WLAN_AP_NETIF_NUM, &wifi_ap_cfg.ssid )) {
|
||||
if (_wext_cmp_ssid(WLAN_AP_NETIF_NUM, wifi_ap_cfg.ssid )) {
|
||||
#else
|
||||
char essid[33];
|
||||
if ((wext_get_ssid(wlan_ap_name, (unsigned char *) essid) > 0)
|
||||
|
|
@ -404,7 +404,7 @@ LOCAL rtw_result_t StartStDHCPClient(void)
|
|||
debug_printf("Start DHCPClient...\n");
|
||||
int ret = RTW_SUCCESS;
|
||||
struct netif * pnetif = &xnetif[WLAN_ST_NETIF_NUM];
|
||||
DHCP_CONFIG *p = (dhcp_cfg *)&wifi_st_dhcp;
|
||||
DHCP_CONFIG *p = (DHCP_CONFIG *)&wifi_st_dhcp;
|
||||
unsigned char mode = p->mode;
|
||||
if(mode == 2 && p->ip != IP4ADDR(255,255,255,255) && p->ip != IP4ADDR(0,0,0,0)) { // fixed ip
|
||||
netif_set_addr(pnetif, (ip_addr_t *)&p->ip, (ip_addr_t *)&p->mask, (ip_addr_t *)&p->gw);
|
||||
|
|
@ -597,8 +597,8 @@ LOCAL void _LwIP_Init(void)
|
|||
xnetif[idx].name[0] = 'r';
|
||||
xnetif[idx].name[1] = '0' + idx;
|
||||
}
|
||||
netif_add(&xnetif[WLAN_ST_NETIF_NUM], (struct netif *)&wifi_st_dhcp.ip, (struct netif *)&wifi_st_dhcp.mask, (struct netif *)&wifi_st_dhcp.gw, NULL, ðernetif_init, &tcpip_input);
|
||||
netif_add(&xnetif[WLAN_AP_NETIF_NUM], (struct netif *)&wifi_ap_dhcp.ip, (struct netif *)&wifi_ap_dhcp.mask, (struct netif *)&wifi_ap_dhcp.gw, NULL, ðernetif_init, &tcpip_input);
|
||||
netif_add(&xnetif[WLAN_ST_NETIF_NUM], (ip_addr_t *)&wifi_st_dhcp.ip, (ip_addr_t *)&wifi_st_dhcp.mask, (ip_addr_t *)&wifi_st_dhcp.gw, NULL, ðernetif_init, &tcpip_input);
|
||||
netif_add(&xnetif[WLAN_AP_NETIF_NUM], (ip_addr_t *)&wifi_ap_dhcp.ip, (ip_addr_t *)&wifi_ap_dhcp.mask, (ip_addr_t *)&wifi_ap_dhcp.gw, NULL, ðernetif_init, &tcpip_input);
|
||||
#if CONFIG_ETHERNET // && NET_IF_NUM > 2
|
||||
{
|
||||
struct ip_addr ipaddr;
|
||||
|
|
@ -623,6 +623,9 @@ LOCAL void _LwIP_Init(void)
|
|||
}
|
||||
}
|
||||
|
||||
extern int rltk_set_tx_power_percentage(rtw_tx_pwr_percentage_t power_percentage_idx);
|
||||
|
||||
|
||||
int wifi_run(rtw_mode_t mode) {
|
||||
int ret = 0;
|
||||
#if CONFIG_DEBUG_LOG > 4
|
||||
|
|
@ -663,8 +666,8 @@ int wifi_run(rtw_mode_t mode) {
|
|||
netbios_set_name(WLAN_ST_NETIF_NUM, lwip_host_name[0]);
|
||||
#endif
|
||||
#endif
|
||||
netif_set_addr(&xnetif[WLAN_ST_NETIF_NUM], &wifi_st_dhcp.ip,
|
||||
&wifi_st_dhcp.mask, &wifi_st_dhcp.gw);
|
||||
netif_set_addr(&xnetif[WLAN_ST_NETIF_NUM], (ip_addr_t *) &wifi_st_dhcp.ip,
|
||||
(ip_addr_t *) &wifi_st_dhcp.mask, (ip_addr_t *) &wifi_st_dhcp.gw);
|
||||
pnif = &xnetif[WLAN_AP_NETIF_NUM];
|
||||
#if LWIP_NETIF_HOSTNAME
|
||||
// @todo ethernetif_init()...
|
||||
|
|
@ -673,8 +676,8 @@ int wifi_run(rtw_mode_t mode) {
|
|||
netbios_set_name(WLAN_AP_NETIF_NUM, lwip_host_name[1]);
|
||||
#endif
|
||||
#endif
|
||||
netif_set_addr(&xnetif[WLAN_AP_NETIF_NUM], &wifi_ap_dhcp.ip,
|
||||
&wifi_ap_dhcp.mask, &wifi_ap_dhcp.gw);
|
||||
netif_set_addr(&xnetif[WLAN_AP_NETIF_NUM], (ip_addr_t *) &wifi_ap_dhcp.ip,
|
||||
(ip_addr_t *) &wifi_ap_dhcp.mask, (ip_addr_t *) &wifi_ap_dhcp.gw);
|
||||
|
||||
}
|
||||
switch(mode) {
|
||||
|
|
@ -856,3 +859,32 @@ void show_wifi_cfg(void) {
|
|||
printf("\tSave flags: %p\n", wifi_cfg.save_flg);
|
||||
}
|
||||
|
||||
#if SDK_VER_NUM >= 0x4000
|
||||
extern int wext_get_associated_client_list(const char *ifname, void * client_list_buffer, __u16 buffer_length);
|
||||
|
||||
int show_wifi_ap_clients(void) {
|
||||
if((wifi_mode == RTW_MODE_AP) || (wifi_mode == RTW_MODE_STA_AP)) {
|
||||
struct {
|
||||
int count;
|
||||
rtw_mac_t mac_list[AP_STA_NUM];
|
||||
} client_info;
|
||||
client_info.count = AP_STA_NUM;
|
||||
if(wext_get_associated_client_list(wlan_ap_name, &client_info, sizeof(client_info)) >= 0) {
|
||||
if(client_info.count) {
|
||||
printf("\tAP %u clients:\n", client_info.count);
|
||||
int client_idx = 0;
|
||||
while(client_idx++ < client_info.count) {
|
||||
unsigned char *pmac = client_info.mac_list[client_idx].octet;
|
||||
printf("\tsta[%u]: %02x:%02x:%02x:%02x:%02x:%02x\n", client_idx,
|
||||
pmac[0],pmac[1],pmac[2],pmac[3],pmac[4],pmac[5]);
|
||||
}
|
||||
} else {
|
||||
printf("\tAP clients none\n");
|
||||
}
|
||||
return client_info.count;
|
||||
};
|
||||
};
|
||||
printf("Get AP clients error!\n");
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -10,10 +10,12 @@
|
|||
#include "wifi_constants.h"
|
||||
#include "queue.h"
|
||||
|
||||
#ifndef ip4_addr1
|
||||
#define ip4_addr1(ipaddr) (((uint8_t*)(ipaddr))[0])
|
||||
#define ip4_addr2(ipaddr) (((uint8_t*)(ipaddr))[1])
|
||||
#define ip4_addr3(ipaddr) (((uint8_t*)(ipaddr))[2])
|
||||
#define ip4_addr4(ipaddr) (((uint8_t*)(ipaddr))[3])
|
||||
#endif
|
||||
|
||||
#define IPSTR "%d.%d.%d.%d"
|
||||
|
||||
|
|
@ -118,8 +120,8 @@ extern unsigned char wifi_mode; // rtw_mode_t
|
|||
extern unsigned char wifi_st_status; // WIFI_STA_ENUM
|
||||
extern char wlan_st_name[];
|
||||
extern char wlan_ap_name[];
|
||||
extern char wlan_st_netifn;
|
||||
extern char wlan_ap_netifn;
|
||||
extern unsigned char wlan_st_netifn;
|
||||
extern unsigned char wlan_ap_netifn;
|
||||
|
||||
/* WiFi Station & scan security */
|
||||
typedef enum {
|
||||
|
|
@ -152,6 +154,9 @@ void show_wifi_st_ip(void);
|
|||
void show_wifi_cfg(void);
|
||||
void show_wifi_st_cfg(void);
|
||||
void show_wifi_ap_cfg(void);
|
||||
#if SDK_VER_NUM >= 0x4000
|
||||
int show_wifi_ap_clients(void);
|
||||
#endif
|
||||
uint32 read_wifi_cfg(uint32 flg);
|
||||
uint32 write_wifi_cfg(uint32 flg);
|
||||
int wifi_run(rtw_mode_t mode);
|
||||
|
|
@ -185,4 +190,9 @@ rtw_result_t api_wifi_scan(api_scan_result_handler_t scan_result_cb);
|
|||
void wifi_close_scan(void);
|
||||
|
||||
|
||||
rtw_result_t _wext_set_lps_dtim(int adapter_num, uint8 lps_dtim);
|
||||
int _wext_get_lps_dtim(int adapter_num);
|
||||
rtw_result_t _wext_enable_powersave(int adapter_num, uint8 ips_mode, uint8 lps_mode);
|
||||
|
||||
|
||||
#endif // _WIFI_API_H_
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@ LOCAL void _wifi_scan_done_hdl(char* buf, int buf_len, int flags, void* userdata
|
|||
web_scan_handler_t * pwscn_rec = &web_scan_handler_ptr;
|
||||
if(pscan_rec->gscan_result_handler) {
|
||||
// сторонний вывод
|
||||
(*pscan_rec->gscan_result_handler)(pscan_rec);
|
||||
(*pscan_rec->gscan_result_handler)((rtw_scan_handler_result_t *) pscan_rec);
|
||||
}
|
||||
else {
|
||||
// оставить структуру pscan_rec->pap_details[i] для вывода в web scan на 5 сек
|
||||
|
|
@ -136,6 +136,7 @@ LOCAL int _wifi_scan_networks(rtw_scan_result_handler_t results_handler) {
|
|||
}
|
||||
|
||||
/* -------- wext_set_pscan_channels ----------------- */
|
||||
extern int iw_ioctl(const char * ifname, unsigned long request, struct iwreq * pwrq);
|
||||
|
||||
LOCAL int wext_set_pscan_channels(void) {
|
||||
struct iwreq iwr;
|
||||
|
|
@ -183,7 +184,7 @@ rtw_result_t api_wifi_scan(api_scan_result_handler_t scan_result_cb)
|
|||
// error_printf("Error xTimerStart\n");
|
||||
} else if(wext_set_pscan_channels() < 0) {
|
||||
// error_printf("ERROR: wifi set partial scan channel fail\n");
|
||||
} else if(_wifi_scan_networks(scan_result_cb) != RTW_SUCCESS) {
|
||||
} else if(_wifi_scan_networks((rtw_scan_result_handler_t) scan_result_cb) != RTW_SUCCESS) {
|
||||
// error_printf("ERROR: wifi scan failed\n");
|
||||
} else if(scan_result_cb) {
|
||||
int i = 300;
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ void sd_xfer_done_callback(void *obj) {
|
|||
}
|
||||
|
||||
void sd_xfer_err_callback(void *obj) {
|
||||
DBG_SDIO_ERR("sd_xfer_err_callback \r\n");
|
||||
DBG_SDIO_ERR("sd_xfer_err_callback\r\n");
|
||||
}
|
||||
|
||||
//----- SD_WaitReady
|
||||
|
|
|
|||
|
|
@ -259,7 +259,7 @@ s8 sdio_sd_setClock(SD_CLK_FREQUENCY SDCLK) {
|
|||
DBG_SDIO_ERR("Malloc ADMA2 table fail.\n");
|
||||
return -1;
|
||||
}
|
||||
DBG_SDIO_INFO("SD card set CLK %d Hz\n", PLATFORM_CLOCK/(4<<(8-SDCLK)));
|
||||
DBG_SDIO_INFO("SD card set CLK %d Hz\n", PLATFORM_CLOCK/(2 << (SD_CLK_41_6MHZ - SDCLK)));
|
||||
sta = HalSdioHostOp.HalSdioHostChangeSdClock(&SdioHostAdapter, SDCLK);
|
||||
rtw_mfree(padma, sizeof(ADMA2_DESC_FMT));
|
||||
if (sta)
|
||||
|
|
|
|||
|
|
@ -39,8 +39,8 @@
|
|||
// 0x0000h ~ 0x00FFh System Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
#define REG_SYS_ISO_CTRL 0x0000
|
||||
#define REG_SYS_FUNC_EN 0x0002
|
||||
#define REG_SYS_ISO_CTRL_ 0x0000
|
||||
#define REG_SYS_FUNC_EN_ 0x0002
|
||||
#define REG_APS_FSMCO 0x0004
|
||||
#define REG_SYS_CLKR 0x0008
|
||||
#define REG_9346CR 0x000A
|
||||
|
|
@ -515,7 +515,7 @@
|
|||
#define REG_BSSID1 0x0708
|
||||
|
||||
/* port0 & port1 enable */
|
||||
#define REG_PORT_CTRL 0x76D
|
||||
//#define REG_PORT_CTRL 0x76D
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
|
|
@ -872,7 +872,7 @@ Default: 00b.
|
|||
#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
|
||||
#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0
|
||||
#define IMR_RXFOVW BIT12 // Receive FIFO Overflow
|
||||
#define IMR_RDU BIT11 // Receive Descriptor Unavailable
|
||||
#define IMR_RDU_ BIT11 // Receive Descriptor Unavailable
|
||||
#define IMR_ATIMEND BIT10 // For 92C,ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt.
|
||||
#define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup
|
||||
#define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt
|
||||
|
|
|
|||
|
|
@ -133,14 +133,14 @@ void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len)
|
|||
|
||||
DBG_TRACE("%s is called", __FUNCTION__);
|
||||
|
||||
if (!rltk_wlan_check_isup(idx))
|
||||
return;
|
||||
|
||||
if(idx == -1){
|
||||
DBG_ERR("skb is NULL");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!rltk_wlan_check_isup(idx))
|
||||
return;
|
||||
|
||||
skb = rltk_wlan_get_recv_skb(idx);
|
||||
DBG_ASSERT(skb, "No pending rx skb");
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#ifndef _SDCARD_H_
|
||||
#define _SDCARD_H_
|
||||
#include "fatfs_ext/inc/ff_driver.h"
|
||||
#include "ff_driver.h"
|
||||
|
||||
extern ll_diskio_drv SD_disk_Driver;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -17,6 +17,8 @@
|
|||
#include "us_ticker_api.h"
|
||||
|
||||
#include "platform_autoconf.h"
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
#define WAIT_US_USE_CYCCNT
|
||||
|
||||
|
|
|
|||
|
|
@ -27,7 +27,9 @@ extern "C" {
|
|||
typedef enum {
|
||||
IRQ_NONE,
|
||||
IRQ_RISE,
|
||||
IRQ_FALL
|
||||
IRQ_FALL,
|
||||
IRQ_LOW,
|
||||
IRQ_HIGH
|
||||
} gpio_irq_event;
|
||||
|
||||
typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
|
||||
|
|
|
|||
|
|
@ -34,8 +34,8 @@ typedef void (*dma_irq_handler)(uint32_t id);
|
|||
void dma_memcpy_init(gdma_t *dma_obj, dma_irq_handler handler, uint32_t id);
|
||||
void dma_memcpy_deinit(gdma_t *dma_obj);
|
||||
void dma_memcpy(gdma_t *dma_obj, void *dst, void* src, uint32_t len);
|
||||
void dma_memcpy_aggr_init(gdma_t * dma_obj, dma_irq_handler handler, uint32_t id);
|
||||
void dma_memcpy_aggr(gdma_t * dma_obj, PHAL_GDMA_BLOCK block_info);
|
||||
void dma_memcpy_aggr_init(gdma_t *dma_obj, dma_irq_handler handler, uint32_t id);
|
||||
void dma_memcpy_aggr(gdma_t *dma_obj, PHAL_GDMA_BLOCK block_info);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,10 +24,12 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
typedef enum {
|
||||
IRQ_LOW = 3,
|
||||
IRQ_HIGH =4
|
||||
} gpio_irq_event_ex;
|
||||
*/
|
||||
|
||||
void gpio_irq_deinit(gpio_irq_t *obj);
|
||||
void gpio_irq_pull_ctrl(gpio_irq_t *obj, PinMode pull_type);
|
||||
|
|
|
|||
|
|
@ -118,13 +118,13 @@ void analogin_init (analogin_t *obj, PinName pin){
|
|||
}
|
||||
|
||||
float analogin_read(analogin_t *obj){
|
||||
float value;
|
||||
// float value;
|
||||
union {
|
||||
unsigned int ui[2];
|
||||
unsigned short us[4];
|
||||
} adata;
|
||||
PSAL_ADC_HND p = &((&(obj->SalADCMngtAdpt))->pSalHndPriv->SalADCHndPriv);
|
||||
RtkADCReceiveBuf(p, &adata.ui);
|
||||
RtkADCReceiveBuf(p, (u32 *) &adata.ui);
|
||||
return (float)(adata.us[p->DevNum]) / (float)(0xCE80);
|
||||
/*
|
||||
uint32_t AnaloginTmp[2] = {0,0};
|
||||
|
|
@ -161,7 +161,7 @@ uint16_t analogin_read_u16(analogin_t *obj){
|
|||
unsigned short us[4];
|
||||
} adata;
|
||||
PSAL_ADC_HND p = &((&(obj->SalADCMngtAdpt))->pSalHndPriv->SalADCHndPriv);
|
||||
RtkADCRxManualRotate(p, &adata.ui);
|
||||
RtkADCRxManualRotate(p, (u32 *) &adata.ui);
|
||||
return adata.us[p->DevNum];
|
||||
/*
|
||||
uint32_t AnaloginTmp[2] = {0,0};
|
||||
|
|
|
|||
|
|
@ -592,6 +592,8 @@ unsigned int flash_get_size(flash_t *obj) {
|
|||
/*
|
||||
* Read Flash OTP data
|
||||
*/
|
||||
extern void SpicTxCmdWithDataRtl8195A(u8 cmd, u8 DataPhaseLen, u8* pData, SPIC_INIT_PARA SpicInitPara);
|
||||
|
||||
int flash_otp_read(flash_t *obj, uint32_t address, uint32_t Length,
|
||||
uint8_t * data) {
|
||||
int ret = 1;
|
||||
|
|
|
|||
|
|
@ -350,7 +350,7 @@ LOCAL FLASH_EEP_ATTR unsigned int pack_cfg_fmem(fobj_head obj)
|
|||
#if 0
|
||||
copy_align4_to_align1((uint8 *)pbuf, rdaddr, len);
|
||||
#else
|
||||
SpicUserReadFourByteRtl8195A(len, rdaddr, (unsigned int *)pbuf, flashobj.SpicInitPara.Mode.BitMode);
|
||||
SpicUserReadFourByteRtl8195A(len, rdaddr, (u32 *)pbuf, flashobj.SpicInitPara.Mode.BitMode);
|
||||
#endif
|
||||
int i = 0;
|
||||
int size4b = len >> 2;
|
||||
|
|
@ -376,7 +376,7 @@ LOCAL signed short FLASH_EEP_ATTR _flash_write_cfg(void *ptr, unsigned short id,
|
|||
fobj_head fobj;
|
||||
fobj.n.id = id;
|
||||
fobj.n.size = size;
|
||||
bool retb = false;
|
||||
// bool retb = false;
|
||||
unsigned int faddr = get_addr_bscfg(false);
|
||||
|
||||
if(faddr >= FMEM_ERROR_MAX) {
|
||||
|
|
|
|||
|
|
@ -573,6 +573,7 @@ int i2c_enable_control(i2c_t *obj, int enable) {
|
|||
pSalI2CHND->pInitDat->I2CEn = enable;
|
||||
|
||||
pSalI2CMngtAdpt->pHalOp->HalI2CEnable(pSalI2CHND->pInitDat);
|
||||
return 1;
|
||||
}
|
||||
|
||||
#if DEVICE_I2CSLAVE
|
||||
|
|
@ -719,14 +720,14 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length) {
|
|||
* \return result
|
||||
*/
|
||||
int i2c_slave_set_for_rd_req(i2c_t *obj, int set) {
|
||||
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt = NULL;
|
||||
PSAL_I2C_HND pSalI2CHND = NULL;
|
||||
PHAL_I2C_INIT_DAT pHalI2CInitDat = NULL;
|
||||
PHAL_I2C_OP pHalI2COP = NULL;
|
||||
PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt;
|
||||
// PSAL_I2C_HND pSalI2CHND = NULL;
|
||||
PHAL_I2C_INIT_DAT pHalI2CInitDat;
|
||||
PHAL_I2C_OP pHalI2COP;
|
||||
u32 I2CLocalTemp;
|
||||
|
||||
pSalI2CMngtAdpt = &(obj->SalI2CMngtAdpt);
|
||||
pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
|
||||
// pSalI2CHND = &(pSalI2CMngtAdpt->pSalHndPriv->SalI2CHndPriv);
|
||||
pHalI2CInitDat = pSalI2CMngtAdpt->pHalInitDat;
|
||||
pHalI2COP = pSalI2CMngtAdpt->pHalOp;
|
||||
|
||||
|
|
@ -772,6 +773,7 @@ int i2c_slave_set_for_data_nak(i2c_t *obj, int set_nak) {
|
|||
//}
|
||||
|
||||
HAL_I2C_WRITE32(pSalI2CHND->DevNum, REG_DW_I2C_IC_SLV_DATA_NACK_ONLY, set_nak);
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif // CONFIG_I2C_SLAVE_EN
|
||||
|
|
|
|||
|
|
@ -253,7 +253,7 @@ void log_uart_irq_set(log_uart_t *obj, LOG_UART_INT_ID irq, uint32_t enable)
|
|||
|
||||
char log_uart_getc(log_uart_t *obj)
|
||||
{
|
||||
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
|
||||
// HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
|
||||
|
||||
while (!log_uart_readable(obj));
|
||||
return (char)(HAL_UART_READ32(UART_REV_BUF_OFF) & 0xFF);
|
||||
|
|
@ -261,7 +261,7 @@ char log_uart_getc(log_uart_t *obj)
|
|||
|
||||
void log_uart_putc(log_uart_t *obj, char c)
|
||||
{
|
||||
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
|
||||
// HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
|
||||
|
||||
while (!log_uart_writable(obj));
|
||||
HAL_UART_WRITE8(UART_TRAN_HOLD_OFF, c);
|
||||
|
|
@ -269,7 +269,7 @@ void log_uart_putc(log_uart_t *obj, char c)
|
|||
|
||||
int log_uart_readable(log_uart_t *obj)
|
||||
{
|
||||
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
|
||||
// HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
|
||||
volatile u8 line_status;
|
||||
|
||||
line_status = HAL_UART_READ8(UART_LINE_STATUS_REG_OFF);
|
||||
|
|
@ -283,7 +283,7 @@ int log_uart_readable(log_uart_t *obj)
|
|||
|
||||
int log_uart_writable(log_uart_t *obj)
|
||||
{
|
||||
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
|
||||
// HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
|
||||
volatile u8 line_status;
|
||||
|
||||
line_status = HAL_UART_READ8(UART_LINE_STATUS_REG_OFF);
|
||||
|
|
@ -321,7 +321,7 @@ void log_uart_clear_rx(log_uart_t *obj)
|
|||
|
||||
void log_uart_break_set(log_uart_t *obj)
|
||||
{
|
||||
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
|
||||
// HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
|
||||
u32 RegValue;
|
||||
|
||||
RegValue = HAL_UART_READ32(UART_LINE_CTL_REG_OFF);
|
||||
|
|
@ -331,7 +331,7 @@ void log_uart_break_set(log_uart_t *obj)
|
|||
|
||||
void log_uart_break_clear(log_uart_t *obj)
|
||||
{
|
||||
HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
|
||||
// HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(obj->log_hal_uart);
|
||||
u32 RegValue;
|
||||
|
||||
RegValue = HAL_UART_READ32(UART_LINE_CTL_REG_OFF);
|
||||
|
|
|
|||
|
|
@ -44,6 +44,8 @@ const PinMap PinMap_PWM[] = {
|
|||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
extern void * rtl_memset(void *m, int c, size_t n);
|
||||
|
||||
int pwmout_init(pwmout_t* obj, PinName pin)
|
||||
{
|
||||
uint32_t peripheral;
|
||||
|
|
|
|||
|
|
@ -536,12 +536,12 @@ int32_t serial_send_stream (serial_t *obj, char *ptxbuf, uint32_t len)
|
|||
|
||||
int32_t serial_recv_stream_dma (serial_t *obj, char *prxbuf, uint32_t len)
|
||||
{
|
||||
PHAL_RUART_OP pHalRuartOp;
|
||||
// PHAL_RUART_OP pHalRuartOp;
|
||||
PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp);
|
||||
u8 uart_idx = pHalRuartAdapter->UartIndex;
|
||||
int32_t ret;
|
||||
|
||||
pHalRuartOp = &(obj->hal_uart_op);
|
||||
// pHalRuartOp = &(obj->hal_uart_op);
|
||||
if ((serial_dma_en[uart_idx] & SERIAL_RX_DMA_EN)==0) {
|
||||
PUART_DMA_CONFIG pHalRuartDmaCfg;
|
||||
|
||||
|
|
@ -563,12 +563,12 @@ int32_t serial_recv_stream_dma (serial_t *obj, char *prxbuf, uint32_t len)
|
|||
|
||||
int32_t serial_send_stream_dma (serial_t *obj, char *ptxbuf, uint32_t len)
|
||||
{
|
||||
PHAL_RUART_OP pHalRuartOp;
|
||||
// PHAL_RUART_OP pHalRuartOp;
|
||||
PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp);
|
||||
u8 uart_idx = pHalRuartAdapter->UartIndex;
|
||||
int32_t ret;
|
||||
|
||||
pHalRuartOp = &(obj->hal_uart_op);
|
||||
// pHalRuartOp = &(obj->hal_uart_op);
|
||||
|
||||
if ((serial_dma_en[uart_idx] & SERIAL_TX_DMA_EN)==0) {
|
||||
PUART_DMA_CONFIG pHalRuartDmaCfg;
|
||||
|
|
|
|||
|
|
@ -58,13 +58,11 @@ void spi_init (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName sse
|
|||
|
||||
_memset((void*)obj, 0, sizeof(spi_t));
|
||||
obj->state = 0;
|
||||
uint32_t SystemClock = SystemGetCpuClk();
|
||||
uint32_t MaxSsiFreq = (SystemClock >> 2) >> 1;
|
||||
|
||||
/* SsiClockDivider doesn't support odd number */
|
||||
|
||||
DBG_SSI_INFO("SystemClock: %d\n", SystemClock);
|
||||
DBG_SSI_INFO("MaxSsiFreq : %d\n", MaxSsiFreq);
|
||||
DBG_SSI_INFO("SystemClock: %d\n", SystemGetCpuClk());
|
||||
DBG_SSI_INFO("MaxSsiFreq : %d\n", (SystemClock >> 2) >> 1);
|
||||
|
||||
ssi_mosi = pinmap_peripheral(mosi, PinMap_SSI_MOSI);
|
||||
ssi_miso = pinmap_peripheral(miso, PinMap_SSI_MISO);
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ extern void HalDeinitLogUart(void);
|
|||
|
||||
#ifdef CONFIG_SDR_EN
|
||||
//#if defined ( __ICCARM__ )
|
||||
extern u8 IsSdrPowerOn();
|
||||
extern u8 IsSdrPowerOn(void);
|
||||
//#endif
|
||||
#endif
|
||||
/**
|
||||
|
|
@ -204,11 +204,16 @@ void sys_reset(void)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_SDR_EN
|
||||
|
||||
extern u8 IsSdrPowerOn(void);
|
||||
|
||||
u8 sys_is_sdram_power_on(void)
|
||||
{
|
||||
return IsSdrPowerOn();
|
||||
}
|
||||
|
||||
extern void SdrPowerOff(void);
|
||||
|
||||
void sys_sdram_off(void)
|
||||
{
|
||||
if (IsSdrPowerOn()) {
|
||||
|
|
|
|||
|
|
@ -30,8 +30,8 @@
|
|||
#define DHCP_MESSAGE_HTYPE (1)
|
||||
#define DHCP_MESSAGE_HLEN (6)
|
||||
|
||||
#define DHCP_SERVER_PORT (67)
|
||||
#define DHCP_CLIENT_PORT (68)
|
||||
//#define DHCP_SERVER_PORT (67)
|
||||
//#define DHCP_CLIENT_PORT (68)
|
||||
|
||||
#define DHCP_MESSAGE_TYPE_DISCOVER (1)
|
||||
#define DHCP_MESSAGE_TYPE_OFFER (2)
|
||||
|
|
|
|||
|
|
@ -91,9 +91,12 @@ static void arp_timer(void *arg);
|
|||
|
||||
#if LWIP_NETIF_HOSTNAME
|
||||
char lwip_host_name[NET_IF_NUM][LWIP_NETIF_HOSTNAME_SIZE] = {
|
||||
DEF_HOSTNAME"0",
|
||||
DEF_HOSTNAME"1",
|
||||
DEF_HOSTNAME"2"
|
||||
{ DEF_HOSTNAME"0" },
|
||||
{ DEF_HOSTNAME"1" }
|
||||
#if NET_IF_NUM > 2
|
||||
,{ DEF_HOSTNAME "2" }
|
||||
#endif
|
||||
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
|
||||
#include "lwip/err.h"
|
||||
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
|
||||
static const char *err_strerr[] = {
|
||||
"Ok", /* ERR_OK 0 */
|
||||
|
|
|
|||
|
|
@ -105,7 +105,7 @@ struct lwip_select_cb {
|
|||
struct lwip_setgetsockopt_data {
|
||||
/** socket struct for which to change options */
|
||||
struct lwip_sock *sock;
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
/** socket index for which to change options */
|
||||
int s;
|
||||
#endif /* LWIP_DEBUG */
|
||||
|
|
@ -1641,7 +1641,7 @@ lwip_getsockopt(int s, int level, int optname, void *optval, socklen_t *optlen)
|
|||
|
||||
/* Now do the actual option processing */
|
||||
data.sock = sock;
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
data.s = s;
|
||||
#endif /* LWIP_DEBUG */
|
||||
data.level = level;
|
||||
|
|
@ -1662,7 +1662,7 @@ static void
|
|||
lwip_getsockopt_internal(void *arg)
|
||||
{
|
||||
struct lwip_sock *sock;
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
int s;
|
||||
#endif /* LWIP_DEBUG */
|
||||
int level, optname;
|
||||
|
|
@ -1673,7 +1673,7 @@ lwip_getsockopt_internal(void *arg)
|
|||
|
||||
data = (struct lwip_setgetsockopt_data*)arg;
|
||||
sock = data->sock;
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
s = data->s;
|
||||
#endif /* LWIP_DEBUG */
|
||||
level = data->level;
|
||||
|
|
@ -2059,7 +2059,7 @@ lwip_setsockopt(int s, int level, int optname, const void *optval, socklen_t opt
|
|||
|
||||
/* Now do the actual option processing */
|
||||
data.sock = sock;
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
data.s = s;
|
||||
#endif /* LWIP_DEBUG */
|
||||
data.level = level;
|
||||
|
|
@ -2080,7 +2080,7 @@ static void
|
|||
lwip_setsockopt_internal(void *arg)
|
||||
{
|
||||
struct lwip_sock *sock;
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
int s;
|
||||
#endif /* LWIP_DEBUG */
|
||||
int level, optname;
|
||||
|
|
@ -2091,7 +2091,7 @@ lwip_setsockopt_internal(void *arg)
|
|||
|
||||
data = (struct lwip_setgetsockopt_data*)arg;
|
||||
sock = data->sock;
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
s = data->s;
|
||||
#endif /* LWIP_DEBUG */
|
||||
level = data->level;
|
||||
|
|
|
|||
|
|
@ -308,7 +308,7 @@ err_t
|
|||
tcpip_apimsg(struct api_msg *apimsg)
|
||||
{
|
||||
struct tcpip_msg msg;
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
/* catch functions that don't set err */
|
||||
apimsg->msg.err = ERR_VAL;
|
||||
#endif
|
||||
|
|
@ -339,7 +339,7 @@ tcpip_apimsg(struct api_msg *apimsg)
|
|||
err_t
|
||||
tcpip_apimsg_lock(struct api_msg *apimsg)
|
||||
{
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
/* catch functions that don't set err */
|
||||
apimsg->msg.err = ERR_VAL;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1008,7 +1008,7 @@ dhcp_bind(struct netif *netif)
|
|||
|
||||
ip_addr_copy(gw_addr, dhcp->offered_gw_addr);
|
||||
/* gateway address not given? */
|
||||
if (ip_addr_isany(&gw_addr)) {
|
||||
if (gw_addr.addr == IPADDR_ANY) {
|
||||
/* copy network address */
|
||||
ip_addr_get_network(&gw_addr, &dhcp->offered_ip_addr, &sn_mask);
|
||||
/* use first host address on network as gateway */
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ void
|
|||
icmp_input(struct pbuf *p, struct netif *inp)
|
||||
{
|
||||
u8_t type;
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
u8_t code;
|
||||
#endif /* LWIP_DEBUG */
|
||||
struct icmp_echo_hdr *iecho;
|
||||
|
|
@ -96,7 +96,7 @@ icmp_input(struct pbuf *p, struct netif *inp)
|
|||
}
|
||||
|
||||
type = *((u8_t *)p->payload);
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
code = *(((u8_t *)p->payload)+1);
|
||||
#endif /* LWIP_DEBUG */
|
||||
switch (type) {
|
||||
|
|
|
|||
|
|
@ -161,7 +161,7 @@ igmp_init(void)
|
|||
IP4_ADDR(&allrouters, 224, 0, 0, 2);
|
||||
}
|
||||
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
/**
|
||||
* Dump global IGMP groups list
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -128,8 +128,9 @@ struct netif *
|
|||
ip_route(ip_addr_t *dest)
|
||||
{
|
||||
struct netif *netif;
|
||||
#if CONFIG_ETHERNET
|
||||
struct netif *last_netif = NULL;
|
||||
|
||||
#endif
|
||||
#ifdef LWIP_HOOK_IP4_ROUTE
|
||||
netif = LWIP_HOOK_IP4_ROUTE(dest);
|
||||
if (netif != NULL) {
|
||||
|
|
@ -498,7 +499,7 @@ ip_input(struct pbuf *p, struct netif *inp)
|
|||
/* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */
|
||||
#if IP_ACCEPT_LINK_LAYER_ADDRESSING
|
||||
/* DHCP servers need 0.0.0.0 to be allowed as source address (RFC 1.1.2.2: 3.2.1.3/a) */
|
||||
if (check_ip_src && !ip_addr_isany(¤t_iphdr_src))
|
||||
if (check_ip_src && current_iphdr_src.addr != IPADDR_ANY)
|
||||
#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
|
||||
{ if ((ip_addr_isbroadcast(¤t_iphdr_src, inp)) ||
|
||||
(ip_addr_ismulticast(¤t_iphdr_src))) {
|
||||
|
|
|
|||
|
|
@ -140,7 +140,7 @@ static const u16_t memp_num[MEMP_MAX] = {
|
|||
};
|
||||
|
||||
/** This array holds a textual description of each pool. */
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
static const char *memp_desc[MEMP_MAX] = {
|
||||
#define LWIP_MEMPOOL(name,num,size,desc) (desc),
|
||||
#include "lwip/memp_std.h"
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ struct stats_ lwip_stats;
|
|||
|
||||
void stats_init(void)
|
||||
{
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
#if MEMP_STATS
|
||||
const char * memp_names[] = {
|
||||
#define LWIP_MEMPOOL(name,num,size,desc) desc,
|
||||
|
|
|
|||
|
|
@ -187,7 +187,7 @@ etharp_free_entry(int i)
|
|||
}
|
||||
/* recycle entry for re-use */
|
||||
arp_table[i].state = ETHARP_STATE_EMPTY;
|
||||
#ifdef LWIP_DEBUG
|
||||
#if defined(LWIP_DEBUG) && (LWIP_DEBUG != 0)
|
||||
/* for debugging, clean out the complete entry */
|
||||
arp_table[i].ctime = 0;
|
||||
arp_table[i].netif = NULL;
|
||||
|
|
|
|||
|
|
@ -163,8 +163,7 @@ PACK_STRUCT_END
|
|||
# include "arch/epstruct.h"
|
||||
#endif
|
||||
|
||||
//#define toupper(CH) \
|
||||
// (((CH) >= 'a' && (CH) <= 'z') ? ((CH) - 'a' + 'A') : (CH))
|
||||
#define toupper(CH) (((CH) >= 'a' && (CH) <= 'z') ? ((CH) - 'a' + 'A') : (CH))
|
||||
|
||||
|
||||
/** NetBIOS decoding name */
|
||||
|
|
@ -226,7 +225,7 @@ netbios_recv(void *arg, struct udp_pcb *upcb, struct pbuf *p, ip_addr_t *addr,
|
|||
if (current_netif != NULL && current_netif->num < NET_IF_NUM) {
|
||||
uint32 ip = current_netif->ip_addr.addr;
|
||||
char *curbiosname = netbios_name[current_netif->num];
|
||||
if (curbiosname[0] != '\0' && ip != NULL
|
||||
if (curbiosname[0] != '\0' && ip != 0
|
||||
/* we only answer if we got a default interface */
|
||||
&& (((ip ^ addr->addr) & current_netif->netmask.addr) == 0)) { // запрет ответа другой подсети
|
||||
#if DEBUGSOO > 3
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
#ifndef __NETBIOS_H__
|
||||
#define __NETBIOS_H__
|
||||
|
||||
#include "autoconf.h"
|
||||
#include "lwip/opt.h"
|
||||
|
||||
/** default port number for "NetBIOS Name service */
|
||||
|
|
@ -9,9 +10,9 @@
|
|||
/** size of a NetBIOS name */
|
||||
#define NETBIOS_NAME_LEN 16
|
||||
|
||||
#ifndef NET_IF_NUM
|
||||
#define NET_IF_NUM 2
|
||||
#endif
|
||||
//#ifndef NET_IF_NUM
|
||||
//#define NET_IF_NUM 2
|
||||
//#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
|
|
|||
|
|
@ -159,7 +159,7 @@ void sntp_get_lasttime(long *sec, long *usec, unsigned int *tick)
|
|||
|
||||
time_t sntp_gen_system_time(int timezone)
|
||||
{
|
||||
struct tm current_tm;
|
||||
// struct tm current_tm;
|
||||
unsigned int update_tick;
|
||||
long update_sec, update_usec, current_sec = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -74,7 +74,7 @@ static int inHandlerMode (void)
|
|||
#if configSignalManagementSupport // the older FreeRTOS version didn't support Signal Management functions
|
||||
static void add_thread_signal_map (osThreadId thread_id, EventGroupHandle_t signals)
|
||||
{
|
||||
int dummy;
|
||||
int dummy = 0;
|
||||
// uint32_t i;
|
||||
ThreadSignalRec *prec_entity;
|
||||
|
||||
|
|
@ -135,7 +135,7 @@ static EventGroupHandle_t find_signal_by_thread (osThreadId thread_id)
|
|||
{
|
||||
EventGroupHandle_t signals_hdl=NULL;
|
||||
// uint32_t i;
|
||||
int dummy;
|
||||
int dummy = 0;
|
||||
ThreadSignalRec *prec_entity;
|
||||
|
||||
if (inHandlerMode()) {
|
||||
|
|
@ -185,7 +185,7 @@ static EventGroupHandle_t remove_thread_signal_map (osThreadId thread_id)
|
|||
{
|
||||
EventGroupHandle_t signals_hdl=NULL;
|
||||
// uint32_t i;
|
||||
int dummy;
|
||||
int dummy = 0;
|
||||
ThreadSignalRec *prec_entity;
|
||||
ThreadSignalRec *pprev_entity;
|
||||
|
||||
|
|
@ -989,7 +989,7 @@ osPoolId osPoolCreate (const osPoolDef_t *pool_def)
|
|||
/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
|
||||
void *osPoolAlloc (osPoolId pool_id)
|
||||
{
|
||||
int dummy;
|
||||
int dummy = 0;
|
||||
void *p = NULL;
|
||||
uint32_t i;
|
||||
uint32_t index;
|
||||
|
|
@ -1047,7 +1047,7 @@ void *osPoolCAlloc (osPoolId pool_id)
|
|||
/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
|
||||
osStatus osPoolFree (osPoolId pool_id, void *block)
|
||||
{
|
||||
int dummy;
|
||||
int dummy = 0;
|
||||
uint32_t index;
|
||||
|
||||
if (pool_id == NULL) {
|
||||
|
|
|
|||
|
|
@ -58,6 +58,7 @@ int freertos_ready_to_sleep() {
|
|||
return wakelock == 0;
|
||||
}
|
||||
|
||||
extern uint32_t osKernelSysTick (void);
|
||||
/*
|
||||
* It is called when freertos is going to sleep.
|
||||
* At this moment, all sleep conditons are satisfied. All freertos' sleep pre-processing are done.
|
||||
|
|
@ -65,7 +66,7 @@ int freertos_ready_to_sleep() {
|
|||
* @param expected_idle_time : The time that FreeRTOS expect to sleep.
|
||||
* If we set this value to 0 then FreeRTOS will do nothing in its sleep function.
|
||||
**/
|
||||
void freertos_pre_sleep_processing(unsigned int *expected_idle_time) {
|
||||
void freertos_pre_sleep_processing(uint32_t *expected_idle_time) {
|
||||
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
|
||||
|
|
@ -176,7 +177,7 @@ void freertos_pre_sleep_processing(unsigned int *expected_idle_time) {
|
|||
#endif
|
||||
}
|
||||
|
||||
void freertos_post_sleep_processing(unsigned int *expected_idle_time) {
|
||||
void freertos_post_sleep_processing(uint32_t *expected_idle_time) {
|
||||
#ifndef configSYSTICK_CLOCK_HZ
|
||||
*expected_idle_time = 1 + ( portNVIC_SYSTICK_CURRENT_VALUE_REG / ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) );
|
||||
#else
|
||||
|
|
@ -257,8 +258,12 @@ uint32_t get_wakelock_status() {
|
|||
}
|
||||
|
||||
#if (configGENERATE_RUN_TIME_STATS == 1)
|
||||
|
||||
extern int sprintf(char* str, const char* fmt, ...);
|
||||
extern size_t strlen(const char *str);
|
||||
|
||||
void get_wakelock_hold_stats( char *pcWriteBuffer ) {
|
||||
u32 i;
|
||||
int i;
|
||||
u32 current_timestamp = osKernelSysTick();
|
||||
|
||||
*pcWriteBuffer = 0x00;
|
||||
|
|
@ -269,15 +274,15 @@ void get_wakelock_hold_stats( char *pcWriteBuffer ) {
|
|||
|
||||
for (i=0; i<32; i++) {
|
||||
if (last_wakelock_state[i] == 1) {
|
||||
sprintf(pcWriteBuffer, "%x\t\t%d\r\n", i, hold_wakelock_time[i] + (current_timestamp - last_acquire_wakelock_time[i]));
|
||||
sprintf(pcWriteBuffer, "%x\t\t%u\r\n", i, (unsigned int)( hold_wakelock_time[i] + (current_timestamp - last_acquire_wakelock_time[i])));
|
||||
} else {
|
||||
if (hold_wakelock_time[i] > 0) {
|
||||
sprintf(pcWriteBuffer, "%x\t\t%d\r\n", i, hold_wakelock_time[i]);
|
||||
sprintf(pcWriteBuffer, "%x\t\t%u\r\n", i, (unsigned int)hold_wakelock_time[i]);
|
||||
}
|
||||
}
|
||||
pcWriteBuffer += strlen( pcWriteBuffer );
|
||||
}
|
||||
sprintf(pcWriteBuffer, "time passed: %d ms, system sleep %d ms\r\n", current_timestamp - base_sys_time, sys_sleep_time);
|
||||
sprintf(pcWriteBuffer, "time passed: %u ms, system sleep %u ms\r\n", (unsigned int)(current_timestamp - base_sys_time), (unsigned int)sys_sleep_time);
|
||||
}
|
||||
|
||||
void clean_wakelock_stat() {
|
||||
|
|
|
|||
|
|
@ -174,7 +174,7 @@ void cli(void);
|
|||
#endif
|
||||
#define HALT() do { cli(); for(;;);} while(0)
|
||||
|
||||
//#undef ASSERT
|
||||
#undef ASSERT
|
||||
#define ASSERT(x) do { \
|
||||
if((x) == 0) \
|
||||
printf("\n\rAssert(" #x ") failed on line %d in file %s", __LINE__, __FILE__); \
|
||||
|
|
|
|||
|
|
@ -162,7 +162,7 @@ typedef struct HeapRegion
|
|||
* terminated by a HeapRegions_t structure that has a size of 0. The region
|
||||
* with the lowest start address must appear first in the array.
|
||||
*/
|
||||
static void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
|
||||
//static void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
|
||||
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -689,6 +689,7 @@ __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
|
|||
#endif /* configASSERT_DEFINED */
|
||||
/*-----------------------------------------------------------*/
|
||||
#if configUSE_IDLE_HOOK
|
||||
extern void WDGRefresh(void);
|
||||
void vApplicationIdleHook( void )
|
||||
{
|
||||
/* Use the idle task to place the CPU into a low power mode. Greater power
|
||||
|
|
|
|||
|
|
@ -202,6 +202,7 @@ HeapRegion_t xHeapRegions[] =
|
|||
#endif
|
||||
#endif
|
||||
|
||||
static void vPortDefineHeapRegions(const HeapRegion_t * const pxHeapRegions);
|
||||
/*-----------------------------------------------------------*/
|
||||
/*
|
||||
Dump xBlock list
|
||||
|
|
@ -501,7 +502,7 @@ static void vPortDefineHeapRegions(const HeapRegion_t * const pxHeapRegions) {
|
|||
|
||||
uint8 chip_id = HalGetChipId();
|
||||
while (pxHeapRegion->xSizeInBytes > 0) {
|
||||
if (pxHeapRegion->pucStartAddress
|
||||
if ((uint32_t)pxHeapRegion->pucStartAddress
|
||||
> 0x20000000 && chip_id >= CHIP_ID_8711AN && chip_id <= CHIP_ID_8711AF) {
|
||||
// pxHeapRegion->pucStartAddress = 0;
|
||||
// pxHeapRegion->xSizeInBytes = 0;
|
||||
|
|
@ -584,6 +585,8 @@ static void vPortDefineHeapRegions(const HeapRegion_t * const pxHeapRegions) {
|
|||
|
||||
}
|
||||
|
||||
extern void * rtl_memcpy(void *dst0, const void *src0, size_t len0);
|
||||
|
||||
void* pvPortReAlloc(void *pv, size_t xWantedSize) {
|
||||
BlockLink_t *pxLink;
|
||||
|
||||
|
|
|
|||
|
|
@ -82,6 +82,7 @@ task.h is included from an application file. */
|
|||
#include "task.h"
|
||||
#include "timers.h"
|
||||
#include "StackMacros.h"
|
||||
#include "tcm_heap.h"
|
||||
|
||||
/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
|
||||
MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ static void device_mutex_init(RT_DEV_LOCK_E device)
|
|||
}
|
||||
|
||||
//======================================================
|
||||
#if 0 // unused-function
|
||||
static void device_mutex_free(RT_DEV_LOCK_E device)
|
||||
{
|
||||
if(DEVICE_MUTEX_IS_INIT(device)){
|
||||
|
|
@ -47,7 +48,7 @@ static void device_mutex_free(RT_DEV_LOCK_E device)
|
|||
rtw_exit_critical(&lock, &irqL);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
//======================================================
|
||||
void device_mutex_lock(RT_DEV_LOCK_E device)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -49,11 +49,12 @@
|
|||
|
||||
//#define RtlKmalloc(size, flag) pvPortMallocAligned(size, 0)
|
||||
#define RtlKmalloc(size, flag) pvPortMalloc(size)
|
||||
#define RtlKfree(pv) vPortFreeAligned(pv)
|
||||
#define RtlKfree(pv) vPortFree(pv)
|
||||
|
||||
|
||||
|
||||
#ifdef CONFIG_TIMER_MODULE
|
||||
extern _LONG_CALL_ unsigned int HalDelayUs(unsigned int us);
|
||||
#define __Delay(t) HalDelayUs(t)
|
||||
#else
|
||||
static __inline__ u32 __Delay(u32 us)
|
||||
|
|
@ -66,7 +67,7 @@ static __inline__ u32 __Delay(u32 us)
|
|||
#define Mdelay(t) __Delay(t*1000)
|
||||
#define Udelay(t) __Delay(t)
|
||||
|
||||
|
||||
#undef ASSERT
|
||||
#define ASSERT(_bool_) do { } while (0)
|
||||
|
||||
//#define panic_printk DiagPrintf
|
||||
|
|
|
|||
|
|
@ -57,10 +57,9 @@ void tcm_heap_dump(void)
|
|||
{
|
||||
#if CONFIG_DEBUG_LOG > 1
|
||||
if(!g_heap_inited) tcm_heap_init();
|
||||
MemChunk *chunk, *prev;
|
||||
MemChunk *chunk;
|
||||
struct Heap* h = &g_tcm_heap;
|
||||
int count = 0;
|
||||
int free_mem;
|
||||
|
||||
DBG_8195A("TCM Free Heap Memory List:\n");
|
||||
for (chunk = h->FreeList; chunk; chunk = chunk->next) {
|
||||
|
|
@ -68,6 +67,7 @@ void tcm_heap_dump(void)
|
|||
}
|
||||
|
||||
/*
|
||||
MemChunk *prev;
|
||||
for (prev = (MemChunk *)&h->FreeList, chunk = h->FreeList;
|
||||
chunk;
|
||||
prev = chunk, chunk = chunk->next)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
#ifndef _BITBAND_IO_H_
|
||||
#define _BITBAND_IO_H_
|
||||
|
||||
#include "PinNames.h"
|
||||
#include "hal_platform.h"
|
||||
#include "hal_api.h"
|
||||
#include "hal_gpio.h"
|
||||
|
|
@ -10,12 +11,34 @@
|
|||
#define BITBAND_SRAM_BASE 0x12000000
|
||||
#define BITBAND_SRAM(a,b) (BITBAND_SRAM_BASE + (a-BITBAND_SRAM_REF)*32 + (b*4)) // Convert SRAM address
|
||||
|
||||
#define BITBAND_ADDR(a,b) (0x02000000 + (a & 0xF0000000) + (a - (a & 0xF0000000)) * 32 + ((b) * 4)) // Convert address ?
|
||||
/*
|
||||
* in hal_platform.h
|
||||
#define BITBAND_REG_BASE 0x40001000
|
||||
*/
|
||||
|
||||
/*
|
||||
* in rtl8195a_gpio.h
|
||||
*
|
||||
#define BITBAND_PORTA_DR 0x00 // data register
|
||||
#define BITBAND_PORTA_DDR 0x04 // data direction
|
||||
#define BITBAND_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software
|
||||
|
||||
#define BITBAND_PORTB_DR 0x0c // data register
|
||||
#define BITBAND_PORTB_DDR 0x10 // data direction
|
||||
#define BITBAND_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software
|
||||
|
||||
#define BITBAND_PORTC_DR 0x18 // data register
|
||||
#define BITBAND_PORTC_DDR 0x1c // data direction
|
||||
#define BITBAND_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software
|
||||
|
||||
#define BITBAND_EXT_PORTA 0x50 // GPIO IN read or OUT read back
|
||||
#define BITBAND_EXT_PORTB 0x54 // GPIO IN read or OUT read back
|
||||
#define BITBAND_EXT_PORTC 0x58 // GPIO IN read or OUT read back
|
||||
*/
|
||||
|
||||
#define BITBAND_PERI_REF 0x40000000
|
||||
#define BITBAND_PERI_BASE 0x42000000
|
||||
#define BITBAND_PERI(a,b) (BITBAND_PERI_BASE + (a - BITBAND_PERI_REF) * 32 + ((b) * 4)) // Convert PERI address
|
||||
|
||||
#define BITBAND_PERI(a,b) (BITBAND_PERI_BASE + (a-BITBAND_PERI_REF)*32 + (b*4)) // Convert PERI address
|
||||
#define ucBITBAND_PERI(a,b) *((volatile unsigned char *)BITBAND_PERI(a,b))
|
||||
#define uiBITBAND_PERI(a,b) *((volatile unsigned int *)BITBAND_PERI(a,b))
|
||||
|
||||
|
|
@ -121,10 +144,10 @@
|
|||
#define BITBAND_K5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,25) //Port = 2, bit = 25, K5
|
||||
#define BITBAND_K6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,26) //Port = 2, bit = 26, K6
|
||||
|
||||
volatile u8 * BitBandAddr(void *addr, u8 bit);
|
||||
volatile u8 * BitBandPeriAddr(void *addr, u8 bit);
|
||||
volatile u8 * GetOutPinBitBandAddr(PinName pin);
|
||||
volatile u8 * GetInpPinBitBandAddr(PinName pin);
|
||||
volatile u8 * HardSetPin(PinName pin, PinDirection pdir, PinMode pmode, u8 val);
|
||||
volatile uint8_t * BitBandAddr(void *addr, uint8_t bit);
|
||||
volatile uint8_t * BitBandPeriAddr(void *addr, uint8_t bit);
|
||||
volatile uint8_t * GetOutPinBitBandAddr(PinName pin);
|
||||
volatile uint8_t * GetInPinBitBandAddr(PinName pin);
|
||||
volatile uint8_t * HardSetPin(PinName pin, HAL_GPIO_PIN_MODE pmode, uint8_t val);
|
||||
|
||||
#endif // _BITBAND_IO_H_
|
||||
|
|
|
|||
|
|
@ -74,9 +74,9 @@ typedef struct _LOG_UART_ADAPTER_ {
|
|||
typedef struct _COMMAND_TABLE_ {
|
||||
const u8* cmd;
|
||||
u16 ArgvCnt;
|
||||
u32 (*func)(u16 argc, u8* argv[]);
|
||||
void (*func)(int argc, char * argv[]); // u32 (*func)(u16 argc, u8* argv[]);
|
||||
const u8* msg;
|
||||
}COMMAND_TABLE, *PCOMMAND_TABLE;
|
||||
} COMMAND_TABLE, *PCOMMAND_TABLE;
|
||||
|
||||
//VOID
|
||||
//HalLogUartHandle(void);
|
||||
|
|
|
|||
|
|
@ -116,7 +116,7 @@ HAL_CUT_B_RAM_DATA_SECTION u32 rand_x = 123456789; // 10000be4
|
|||
0, \
|
||||
"", \
|
||||
0, \
|
||||
0x0437DC, \
|
||||
(void *)0x0437DC, \
|
||||
0, \
|
||||
_NULL, \
|
||||
_NULL, \
|
||||
|
|
|
|||
|
|
@ -257,12 +257,12 @@ LOCAL int BOOT_RAM_TEXT_SECTION SetSpicBitMode(uint8 BitMode) {
|
|||
}
|
||||
|
||||
void BOOT_RAM_TEXT_SECTION InitSpicFlashType(struct spic_table_flash_type *ptable_flash) {
|
||||
u8 * ptrb = &ptable_flash->cmd;
|
||||
volatile u32 * ptrreg = (volatile u32 *)(SPI_FLASH_CTRL_BASE + REG_SPIC_READ_FAST_SINGLE);// 0x400060E0
|
||||
uint8 * ptrb = (uint8 *)&ptable_flash->cmd;
|
||||
volatile uint32 * ptrreg = (volatile uint32 *)(SPI_FLASH_CTRL_BASE + REG_SPIC_READ_FAST_SINGLE);// 0x400060E0
|
||||
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); // Disable SPI_FLASH User Mode
|
||||
do {
|
||||
*ptrreg++ = *ptrb++;
|
||||
} while(ptrb < (u8 *)(&ptable_flash->fsize));
|
||||
} while(ptrb < (uint8 *)(&ptable_flash->fsize));
|
||||
ptrreg[0] = ptable_flash->contrl;
|
||||
ptrreg[1] = ptable_flash->validcmd[SpicOneBitMode];
|
||||
ptrreg[2] = ptable_flash->fsize;
|
||||
|
|
@ -387,6 +387,7 @@ typedef enum {
|
|||
SEG_ID_MAX
|
||||
} _SEG_ID;
|
||||
|
||||
#if CONFIG_DEBUG_LOG > 1
|
||||
LOCAL const char * const txt_tab_seg[] = {
|
||||
"UNK", // 0
|
||||
"SRAM", // 1
|
||||
|
|
@ -397,6 +398,7 @@ LOCAL const char * const txt_tab_seg[] = {
|
|||
"CPU", // 6
|
||||
"ROM" // 7
|
||||
};
|
||||
#endif
|
||||
|
||||
LOCAL const uint32 tab_seg_def[] = { 0x10000000, 0x10070000, 0x1fff0000,
|
||||
0x20000000, 0x30000000, 0x30200000, 0x40000000, 0x40800000, 0x98000000,
|
||||
|
|
@ -404,7 +406,7 @@ LOCAL const uint32 tab_seg_def[] = { 0x10000000, 0x10070000, 0x1fff0000,
|
|||
|
||||
LOCAL uint32 BOOT_RAM_TEXT_SECTION get_seg_id(uint32 addr, int32 size) {
|
||||
uint32 ret = SEG_ID_ERR;
|
||||
uint32 * ptr = &tab_seg_def;
|
||||
uint32 * ptr = (uint32 *) &tab_seg_def;
|
||||
if (size > 0) {
|
||||
do {
|
||||
ret++;
|
||||
|
|
@ -447,7 +449,7 @@ LOCAL uint32 BOOT_RAM_TEXT_SECTION load_segs(uint32 faddr, PIMG2HEAD hdr,
|
|||
segnum, faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr,
|
||||
hdr->seg.size);
|
||||
#endif
|
||||
fnextaddr += flashcpy(fnextaddr, hdr->seg.ldaddr, hdr->seg.size);
|
||||
fnextaddr += flashcpy(fnextaddr, (void *)hdr->seg.ldaddr, hdr->seg.size);
|
||||
} else if (seg_id) {
|
||||
#if CONFIG_DEBUG_LOG > 2
|
||||
DBG_8195A("Skip Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n", segnum,
|
||||
|
|
@ -457,7 +459,7 @@ LOCAL uint32 BOOT_RAM_TEXT_SECTION load_segs(uint32 faddr, PIMG2HEAD hdr,
|
|||
} else {
|
||||
break;
|
||||
}
|
||||
fnextaddr += flashcpy(fnextaddr, &hdr->seg, sizeof(IMGSEGHEAD));
|
||||
fnextaddr += flashcpy(fnextaddr, (void *) &hdr->seg, sizeof(IMGSEGHEAD));
|
||||
segnum++;
|
||||
}
|
||||
return fnextaddr;
|
||||
|
|
@ -476,7 +478,7 @@ LOCAL int BOOT_RAM_TEXT_SECTION loadUserImges(int imgnum) {
|
|||
faddr = (faddr + FLASH_SECTOR_SIZE - 1) & (~(FLASH_SECTOR_SIZE - 1));
|
||||
uint32 img_id = load_img2_head(faddr, &hdr);
|
||||
if ((img_id >> 8) > 4 || (uint8) img_id != 0) {
|
||||
faddr = load_segs(faddr + 0x10, &hdr.seg, imagenum == imgnum);
|
||||
faddr = load_segs(faddr + 0x10, &hdr, imagenum == imgnum);
|
||||
if (imagenum == imgnum) {
|
||||
// DBG_8195A("Image%d: %s\n", imgnum, hdr.name);
|
||||
break;
|
||||
|
|
@ -544,7 +546,7 @@ LOCAL void BOOT_RAM_TEXT_SECTION RtlConsolRam(void) {
|
|||
pUartLogCtl->pTmpLogBuf->UARTLogBuf[0] = '?';
|
||||
pUartLogCtl->pTmpLogBuf->BufCount = 1;
|
||||
pUartLogCtl->ExecuteCmd = 1;
|
||||
RtlConsolTaskRom(pUartLogCtl);
|
||||
RtlConsolTaskRom((void *)pUartLogCtl);
|
||||
}
|
||||
|
||||
/* Enter Image 1.5 */
|
||||
|
|
|
|||
|
|
@ -26,6 +26,15 @@ extern void xPortPendSVHandler(void);
|
|||
extern void xPortSysTickHandler(void);
|
||||
extern void vPortSVCHandler(void);
|
||||
extern void rtl_libc_init(void);
|
||||
extern _LONG_CALL_ void HalCpuClkConfig(unsigned char CpuType);
|
||||
extern void PSHalInitPlatformLogUart(void);
|
||||
extern _LONG_CALL_ void UartLogCmdExecute(PUART_LOG_CTL pUartLogCtlExe);
|
||||
extern void HalReInitPlatformTimer(void);
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
extern void En32KCalibration(void);
|
||||
extern void SdrCtrlInit(void);
|
||||
extern void InitSoCPM(void);
|
||||
extern u32 SdrControllerInit(void);
|
||||
//extern void ShowRamBuildInfo(void); // app_start.c: VOID ShowRamBuildInfo(VOID)
|
||||
//void HalNMIHandler_Patch(void);
|
||||
void SDIO_Device_Off(void);
|
||||
|
|
@ -97,7 +106,7 @@ __weak int main(void) {
|
|||
DiagPrintf("\r<RTL>");
|
||||
while (1) {
|
||||
while (pUartLogCtl->ExecuteCmd != 1);
|
||||
UartLogCmdExecute(pUartLogCtl);
|
||||
UartLogCmdExecute((PUART_LOG_CTL) pUartLogCtl);
|
||||
DiagPrintf("\r<RTL>");
|
||||
pUartLogCtl->ExecuteCmd = 0;
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -245,7 +245,6 @@ HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor)
|
|||
u32 IRQ_UNKNOWN = 999;
|
||||
u32 Ctrlr0Value = 0;
|
||||
u32 Ctrlr1Value = 0;
|
||||
u32 SerValue = 0;
|
||||
u32 BaudrValue = 0;
|
||||
u32 TxftlrValue = 0;
|
||||
u32 RxftlrValue = 0;
|
||||
|
|
@ -318,8 +317,7 @@ HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor)
|
|||
HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR1));
|
||||
}
|
||||
|
||||
SerValue = BIT_SER_SER(1 << (pHalSsiAdaptor->SlaveSelectEnable));
|
||||
SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_SER Value: %X\n", Index, SerValue);
|
||||
SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_SER Value: %X\n", Index, BIT_SER_SER(1 << (pHalSsiAdaptor->SlaveSelectEnable)));
|
||||
|
||||
//HAL_SSI_WRITE32(Index, REG_DW_SSI_SER, SerValue);
|
||||
HalSsiSetSlaveEnableRegisterRtl8195a(Adaptor, pHalSsiAdaptor->SlaveSelectEnable);
|
||||
|
|
@ -617,7 +615,6 @@ HAL_Status HalSsiSetFormatRtl8195a(VOID *Adaptor)
|
|||
u32 RxftlrValue = 0;
|
||||
u8 Index = pHalSsiAdaptor->Index;
|
||||
u8 Role = pHalSsiAdaptor->Role;
|
||||
u32 Spi_mode = 0;
|
||||
|
||||
if (Index > 2) {
|
||||
DBG_SSI_ERR("HalSsiSetFormatRtl8195a: Invalid SSI Idx %d\r\n", Index);
|
||||
|
|
@ -639,10 +636,9 @@ HAL_Status HalSsiSetFormatRtl8195a(VOID *Adaptor)
|
|||
|
||||
HAL_SSI_WRITE32(Index, REG_DW_SSI_CTRLR0, Ctrlr0Value);
|
||||
|
||||
Spi_mode = (HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0) >>6) & 0x3;
|
||||
SSI_DBG_INIT("[2] SSI%d REG_DW_SSI_CTRLR0(%X) = %X, SPI Mode = %X\n", Index,
|
||||
SSI0_REG_BASE + (SSI_REG_OFF * Index) + REG_DW_SSI_CTRLR0,
|
||||
HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0), Spi_mode);
|
||||
HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0), (HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0) >>6) & 0x3);
|
||||
//The tx threshold and rx threshold value will be reset after the spi changes its role
|
||||
/* REG_DW_SSI_TXFTLR */
|
||||
TxftlrValue = BIT_TXFTLR_TFT(pHalSsiAdaptor->TxThresholdLevel);
|
||||
|
|
@ -741,7 +737,7 @@ HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length)
|
|||
{
|
||||
PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter;
|
||||
u32 RxFifoThresholdLevel;
|
||||
u8 Index = pHalSsiAdapter->Index;
|
||||
// u8 Index = pHalSsiAdapter->Index;
|
||||
|
||||
DBG_SSI_INFO("HalSsiIntReadRtl8195a: Idx=%d, RxData=0x%x, Len=0x%x\r\n", Index, RxData, Length);
|
||||
// if (HalSsiBusyRtl8195a(Adapter)) {
|
||||
|
|
|
|||
|
|
@ -12,13 +12,14 @@
|
|||
#include "rtl8195a_uart.h"
|
||||
#include "hal_uart.h"
|
||||
#include "hal_gdma.h"
|
||||
#include "strproc.h"
|
||||
|
||||
u8
|
||||
HalRuartGetChipVerRtl8195a(VOID)
|
||||
{
|
||||
u8 chip_ver;
|
||||
|
||||
chip_ver = (HAL_READ32(SYSTEM_CTRL_BASE, 0x01F0) >> 4) & 0x0f;
|
||||
chip_ver = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSTEM_CFG0) >> 4) & 0x0f; // 0x400001F0 RTL8710AF = 0x41000220
|
||||
return chip_ver;
|
||||
}
|
||||
|
||||
|
|
@ -151,9 +152,8 @@ HalRuartGenBaudRateRtl8195a(
|
|||
u32 min_divisor=0;
|
||||
u32 min_err=0xffffffff;
|
||||
u32 uart_ovsr;
|
||||
u32 uart_ovsr_mod;
|
||||
u32 min_uart_ovsr; // ovsr with mini err
|
||||
u32 min_uart_ovsr_mod;
|
||||
u32 min_uart_ovsr = 0; // ovsr with mini err
|
||||
u32 min_uart_ovsr_mod = 0;
|
||||
u64 uart_clock;
|
||||
u32 divisor_temp;
|
||||
u32 max_jitter_temp;
|
||||
|
|
@ -200,7 +200,7 @@ HalRuartGenBaudRateRtl8195a(
|
|||
min_uart_ovsr = uart_ovsr/100;
|
||||
min_uart_ovsr_mod = uart_ovsr%100;
|
||||
} else if (err_temp == min_err) {
|
||||
uart_ovsr_mod = uart_ovsr%100;
|
||||
u32 uart_ovsr_mod = uart_ovsr%100;
|
||||
// we perfer OVSR bigger and adj bits smaller
|
||||
if (((uart_ovsr/100) >= min_uart_ovsr) && (uart_ovsr_mod < min_uart_ovsr_mod)) {
|
||||
min_err = err_temp;
|
||||
|
|
@ -369,7 +369,7 @@ HalRuartSetBaudRateRtl8195a(
|
|||
u8 chip_ver;
|
||||
|
||||
// get chip version
|
||||
chip_ver = HalRuartGetChipVerRtl8195a();
|
||||
chip_ver = HalRuartGetChipVerRtl8195a(); // RTL8710AF = 2
|
||||
#endif
|
||||
|
||||
if (pHalRuartAdapter->WordLen == RUART_WLS_8BITS) {
|
||||
|
|
@ -1248,7 +1248,7 @@ HalRuartMultiBlkDmaRecvRtl8195a(
|
|||
}
|
||||
|
||||
/**
|
||||
* Stop non-blocking UART RX
|
||||
* Stop non-blocking UART TX
|
||||
*
|
||||
*
|
||||
* @return VOID
|
||||
|
|
@ -1283,7 +1283,7 @@ HalRuartStopRecvRtl8195a_Patch(
|
|||
if (NULL != pUartGdmaConfig) {
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
PHAL_GDMA_OP pHalGdmaOp;
|
||||
u8 IsrTypeMap;
|
||||
|
||||
|
||||
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pRxHalGdmaAdapter;
|
||||
pHalGdmaOp = (PHAL_GDMA_OP)pUartGdmaConfig->pHalGdmaOp;
|
||||
|
|
@ -1293,7 +1293,8 @@ HalRuartStopRecvRtl8195a_Patch(
|
|||
// Clean Auto Reload Bit
|
||||
pHalGdmaOp->HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter);
|
||||
// Clear Pending ISR
|
||||
IsrTypeMap = pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
|
||||
// u8 IsrTypeMap =
|
||||
pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
|
||||
pHalGdmaOp->HalGdmaChDis((VOID*)(pHalGdmaAdapter));
|
||||
|
||||
DMA_Dar = HalGdmaQueryDArRtl8195a((VOID*)pHalGdmaAdapter);
|
||||
|
|
@ -1358,7 +1359,7 @@ HalRuartStopSendRtl8195a_Patch(
|
|||
if (NULL != pUartGdmaConfig) {
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
PHAL_GDMA_OP pHalGdmaOp;
|
||||
u8 IsrTypeMap;
|
||||
|
||||
|
||||
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter;
|
||||
pHalGdmaOp = (PHAL_GDMA_OP)pUartGdmaConfig->pHalGdmaOp;
|
||||
|
|
@ -1368,7 +1369,8 @@ HalRuartStopSendRtl8195a_Patch(
|
|||
// Clean Auto Reload Bit
|
||||
pHalGdmaOp->HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter);
|
||||
// Clear Pending ISR
|
||||
IsrTypeMap = pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
|
||||
// u8 IsrTypeMap =
|
||||
pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
|
||||
pHalGdmaOp->HalGdmaChDis((VOID*)(pHalGdmaAdapter));
|
||||
|
||||
DMA_Sar = HalGdmaQuerySArRtl8195a((VOID*)pHalGdmaAdapter);
|
||||
|
|
|
|||
|
|
@ -1,54 +1,68 @@
|
|||
|
||||
#include "PinNames.h"
|
||||
#include "bitband_io.h"
|
||||
//#include "rtl8195a_gpio.h"
|
||||
|
||||
volatile u8 * BitBandAddr(void *addr, u8 bit) {
|
||||
return (volatile u8 *)(BITBAND_ADDR((u32)addr, bit));
|
||||
#define BITBAND_ADDR(a,b) (0x02000000 + (a & 0xF0000000) + (a - (a & 0xF0000000)) * 32 + ((b) * 4)) // Convert address ?
|
||||
|
||||
volatile uint8_t * BitBandAddr(void *addr, uint8_t bit) {
|
||||
uint32_t ret = BITBAND_ADDR((u32)addr, bit);
|
||||
return (volatile uint8_t *) ret;
|
||||
}
|
||||
|
||||
volatile u8 * BitBandPeriAddr(void *addr, u8 bit) {
|
||||
return (volatile u8 *)(BITBAND_PERI((u32)addr, bit));
|
||||
volatile uint8_t * BitBandPeriAddr(void *addr, uint8_t bit) {
|
||||
return (volatile uint8_t *)(BITBAND_PERI((u32)addr, bit));
|
||||
}
|
||||
|
||||
volatile u8 * GetOutPinBitBandAddr(PinName pin) {
|
||||
u32 paddr = NULL;
|
||||
u32 ippin = HAL_GPIO_GetIPPinName_8195a(pin);
|
||||
if(ippin != 0xff) {
|
||||
volatile uint8_t * GetOutPinBitBandAddr(PinName pin) {
|
||||
volatile uint8_t * paddr = 0;
|
||||
uint32_t ippin = HAL_GPIO_GetIPPinName_8195a(pin);
|
||||
if(ippin < 0xff) {
|
||||
// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
|
||||
paddr = BitBandPeriAddr((void *)(GPIO_REG_BASE + GPIO_PORTB_DR * (ippin >> 5)), ippin & 0x1f);
|
||||
}
|
||||
return paddr;
|
||||
}
|
||||
|
||||
volatile u8 * GetInPinBitBandAddr(PinName pin) {
|
||||
volatile u8 * paddr = NULL;
|
||||
u32 ippin = HAL_GPIO_GetIPPinName_8195a(pin);
|
||||
if(ippin != 0xff) {
|
||||
volatile uint8_t * GetInPinBitBandAddr(PinName pin) {
|
||||
volatile uint8_t * paddr = NULL;
|
||||
uint32_t ippin = HAL_GPIO_GetIPPinName_8195a(pin);
|
||||
if(ippin < 0xff) {
|
||||
// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
|
||||
paddr = BitBandPeriAddr((void *)(GPIO_REG_BASE + GPIO_EXT_PORTA + (ippin >> 5) * 4), ippin & 0x1f);
|
||||
}
|
||||
return paddr;
|
||||
}
|
||||
|
||||
volatile u8 * HardSetPin(PinName pin, PinDirection pdir, PinMode pmode, u8 val)
|
||||
extern _LONG_CALL_ u32 GPIO_FuncOn_8195a(VOID);
|
||||
extern void wait_us(int us);
|
||||
|
||||
volatile uint8_t * HardSetPin(PinName pin, HAL_GPIO_PIN_MODE pmode, uint8_t val)
|
||||
{
|
||||
volatile u8 *paddr = NULL;
|
||||
u32 ippin = HAL_GPIO_GetIPPinName_8195a(pin);
|
||||
if(ippin != 0xff) {
|
||||
// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
|
||||
paddr = BitBandPeriAddr((void *)(GPIO_REG_BASE + GPIO_PORTB_DR * (ippin >> 5)), ippin & 0x1f);
|
||||
volatile uint8_t *paddr = NULL;
|
||||
uint32_t ippin = HAL_GPIO_GetIPPinName_8195a(pin);
|
||||
if(ippin < 0xff) {
|
||||
if(_pHAL_Gpio_Adapter == NULL) {
|
||||
extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
|
||||
_pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
|
||||
}
|
||||
if(paddr && _pHAL_Gpio_Adapter) {
|
||||
if (_pHAL_Gpio_Adapter->Gpio_Func_En == 0) GPIO_FuncOn_8195a();
|
||||
paddr[0] = val; // data register
|
||||
paddr[(GPIO_PORTB_DDR - GPIO_PORTB_DR) * 32] = pdir; // data direction
|
||||
#if 1 // if use HAL_Gpio_Adapter
|
||||
uint32 * p = &_pHAL_Gpio_Adapter->Local_Gpio_Dir[ippin >> 5];
|
||||
if(pdir) *p |= 1 << (ippin & 0x1f);
|
||||
else *p &= ~(1 << (ippin & 0x1f));
|
||||
if(_pHAL_Gpio_Adapter->Gpio_Func_En == 0) GPIO_FuncOn_8195a();
|
||||
wait_us(100);
|
||||
// delayMicroseconds(100);
|
||||
// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
|
||||
#if CONFIG_DEBUG_LOG > 3
|
||||
GpioFunctionChk(ippin, ENABLE);
|
||||
#endif
|
||||
paddr[(GPIO_PORTB_CTRL - GPIO_PORTB_DR) * 32] = 0; // data source control, we should keep it as default: data source from software
|
||||
HAL_GPIO_PullCtrl_8195a(pin, pmode); // set GPIO_PULL_CTRLx
|
||||
GPIO_PullCtrl_8195a(ippin, HAL_GPIO_HIGHZ); // Make the pin pull control default as High-Z
|
||||
paddr = BitBandPeriAddr((void *)(GPIO_REG_BASE + GPIO_PORTB_DR * (ippin >> 5)), ippin & 0x1f);
|
||||
*paddr = val; // data register
|
||||
HAL_GPIO_PIN gpio;
|
||||
gpio.pin_name = ippin;
|
||||
gpio.pin_mode = pmode;
|
||||
HAL_GPIO_Init_8195a(&gpio);
|
||||
*paddr = val; // data register
|
||||
// paddr[(GPIO_PORTB_DDR - GPIO_PORTB_DR) * 32] = pmode == DOUT_PUSH_PULL; // data direction
|
||||
// GPIO_PullCtrl_8195a(ippin, pmode); // set GPIO_PULL_CTRLx
|
||||
// paddr[(GPIO_PORTB_CTRL - GPIO_PORTB_DR) * 32] = 0; // data source control, we should keep it as default: data source from software
|
||||
}
|
||||
return paddr;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -533,16 +533,16 @@ ADCISRHandle(
|
|||
PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL;
|
||||
PHAL_ADC_INIT_DAT pHalADCInitDat = NULL;
|
||||
PHAL_ADC_OP pHalADCOP = NULL;
|
||||
PSAL_ADC_USER_CB pSalADCUserCB = NULL;
|
||||
u8 ADCIrqIdx;
|
||||
// PSAL_ADC_USER_CB pSalADCUserCB = NULL;
|
||||
// u8 ADCIrqIdx;
|
||||
|
||||
/* To get the SAL_I2C_MNGT_ADPT pointer, and parse the rest pointers */
|
||||
pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv);
|
||||
pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv);
|
||||
pHalADCInitDat = pSalADCMngtAdpt->pHalInitDat;
|
||||
pHalADCOP = pSalADCMngtAdpt->pHalOp;
|
||||
ADCIrqIdx = pHalADCInitDat->ADCIdx;
|
||||
pSalADCUserCB = pSalADCHND->pUserCB;
|
||||
// ADCIrqIdx = pHalADCInitDat->ADCIdx;
|
||||
// pSalADCUserCB = pSalADCHND->pUserCB;
|
||||
|
||||
DBG_8195A_ADC_LVL(HAL_ADC_LVL,"ADC INTR STS:%x\n",pHalADCOP->HalADCReadReg(pHalADCInitDat, REG_ADC_INTR_STS));
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ void HalReInitPlatformTimer(void)
|
|||
TimerAdapter.IrqDis = 1;
|
||||
TimerAdapter.TimerId = 1;
|
||||
HalTimerOpInit_Patch(&HalTimerOp);
|
||||
HAL_TIMER_OP x;
|
||||
// HAL_TIMER_OP x;
|
||||
HalTimerOp.HalTimerInit(&TimerAdapter);
|
||||
HalTimerOp.HalTimerEn(1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -150,11 +150,13 @@ unsigned int rand_x = 123456789;
|
|||
*/
|
||||
#ifdef CONFIG_SDR_EN
|
||||
|
||||
#ifndef __GNUC__
|
||||
//#pragma arm section code = ".hal.sdrc.text"
|
||||
#pragma arm section rodata = ".rodata.hal.sdrc"
|
||||
//, rwdata = ".hal.sdrc.data"
|
||||
//, zidata = ".hal.sdrc.bss"
|
||||
//#pragma arm section bss = ".hal.sdrc.bss"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDR_VERIFY
|
||||
enum{
|
||||
|
|
@ -448,13 +450,10 @@ DramInit (
|
|||
u32 CrTwr, DramMaxWr, DramWr;
|
||||
u32 CrTrtw = 0, CrTrtwT = 0;
|
||||
u32 DrmaPeriod;
|
||||
DRAM_TYPE DdrType;
|
||||
DRAM_TYPE DdrType = DRAM_SDR;
|
||||
DRAM_DQ_WIDTH DqWidth;
|
||||
DRAM_COLADDR_WTH Page;
|
||||
u32 DfiRate;
|
||||
volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
|
||||
ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
|
||||
// ms_ctrl_0_map = ms_ctrl_0_map;
|
||||
|
||||
DfiRate = 1 << (u32) (DramInfo->DfiRate);
|
||||
DrmaPeriod = (DramInfo->DdrPeriodPs)*(DfiRate); // according DFI_RATE to setting
|
||||
|
|
@ -658,6 +657,9 @@ DramInit (
|
|||
// enter mem_mode
|
||||
HAL_SDR_WRITE32(REG_SDR_CSR,0x600);
|
||||
#else
|
||||
volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
|
||||
ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
|
||||
// ms_ctrl_0_map = ms_ctrl_0_map;
|
||||
// WRAP_MISC setting
|
||||
ms_ctrl_0_map->misc = //0x12;
|
||||
(
|
||||
|
|
@ -753,7 +755,8 @@ SdrCalibration(
|
|||
DBG_8195A("%s()\n", __func__);
|
||||
u32 RdPipe = 0, TapCnt = 0, Pass = 0, AvaWdsCnt = 0;
|
||||
u32 RdPipeCounter, RecNum[2], RecRdPipe[2];//, AvaWds[2][REC_NUM];
|
||||
BOOL RdPipeFlag, PassFlag = 0, Result;
|
||||
BOOL RdPipeFlag, Result;
|
||||
// BOOL PassFlag = 0;
|
||||
u8 flashtype = 0;
|
||||
|
||||
flashtype = SpicInitParaAllClk[0][0].flashtype;
|
||||
|
|
@ -829,7 +832,7 @@ SdrCalibration(
|
|||
#endif
|
||||
|
||||
RdPipeFlag = _FALSE;
|
||||
PassFlag = _FALSE;
|
||||
// PassFlag = _FALSE;
|
||||
AvaWdsCnt = 0;
|
||||
|
||||
for(TapCnt=0; TapCnt < (MAX_TAP_DLY+1); TapCnt++) {
|
||||
|
|
@ -853,7 +856,7 @@ SdrCalibration(
|
|||
#endif
|
||||
|
||||
Pass = MemTest(10000);
|
||||
PassFlag = _FALSE;
|
||||
// PassFlag = _FALSE;
|
||||
|
||||
if(Pass==_TRUE) { // PASS
|
||||
|
||||
|
|
@ -876,7 +879,7 @@ SdrCalibration(
|
|||
break;
|
||||
}
|
||||
|
||||
PassFlag = _TRUE;
|
||||
// PassFlag = _TRUE;
|
||||
|
||||
DBG_SDR_INFO("Verify Pass => RdPipe:%d; TapCnt: %d\n", RdPipe, TapCnt);
|
||||
|
||||
|
|
@ -1044,7 +1047,7 @@ Sdr_Rand2(
|
|||
}
|
||||
|
||||
*/
|
||||
|
||||
extern __attribute__ ((long_call)) unsigned int Rand(void);
|
||||
HAL_SDRC_TEXT_SECTION
|
||||
s32
|
||||
MemTest(
|
||||
|
|
|
|||
|
|
@ -373,6 +373,7 @@ WakeFromSLPPG(
|
|||
);
|
||||
}
|
||||
|
||||
// Предел 8355 ms!
|
||||
VOID
|
||||
DurationScaleAndPeriodOP(
|
||||
IN u32 SDuration,
|
||||
|
|
@ -412,7 +413,7 @@ CLKCal(
|
|||
u32 Rtemp = 0;
|
||||
u32 RRTemp = 0;
|
||||
|
||||
u32 x = (HAL_READ32(PERI_ON_BASE,REG_SYS_CLK_CTRL1) >> BIT_SHIFT_PESOC_OCP_CPU_CK_SEL) & BIT_MASK_PESOC_OCP_CPU_CK_SEL;
|
||||
u32 x = (HAL_READ32(PERI_ON_BASE, REG_SYS_CLK_CTRL1) >> BIT_SHIFT_PESOC_OCP_CPU_CK_SEL) & BIT_MASK_PESOC_OCP_CPU_CK_SEL;
|
||||
|
||||
if( ClkSel ){
|
||||
//a33_ck
|
||||
|
|
@ -432,7 +433,8 @@ CLKCal(
|
|||
}
|
||||
else {
|
||||
//anack
|
||||
RRTemp = (((2133/Rtemp) >> x) - 1);
|
||||
//pvvx: eror RTL8710AF? RRTemp = (((2133/Rtemp) >> x) - 1);
|
||||
RRTemp = (2133/Rtemp) - 1;
|
||||
}
|
||||
if ( x == 5 )
|
||||
DiagPrintf("Using ana to cal is not allowed!\n");
|
||||
|
|
@ -516,7 +518,7 @@ SleepClkGatted(
|
|||
|
||||
//3 1.5 Enable low power mode
|
||||
// 1.5.1 0x4000_0118[2] = 1 => for sleep mode
|
||||
Rtemp = 0x00000004;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000004;
|
||||
Rtemp = BIT_SYSON_PM_CMD_SLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000004;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//3 1.6 Wait CHIP enter low power mode
|
||||
|
|
@ -535,7 +537,7 @@ VOID SleepPwrGatted(
|
|||
u32 Rtemp = 0;
|
||||
u32 ScaleTemp = 0;
|
||||
u32 PeriodTemp = 0;
|
||||
u32 CalTemp = 0;
|
||||
// u32 CalTemp = 0;
|
||||
|
||||
//Backup CPU CLK
|
||||
BackupCPUClk();
|
||||
|
|
@ -547,7 +549,7 @@ VOID SleepPwrGatted(
|
|||
//3 1.1 Set TU timer timescale
|
||||
//0x4000_0090[21:16] = 6'h1F
|
||||
//0x4000_0090[15] = 1'b0 => Disable timer
|
||||
CalTemp = (CLKCal(ANACK) << 16);
|
||||
// CalTemp = (CLKCal(ANACK) << 16);
|
||||
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL)
|
||||
& (~((BIT_MASK_SYS_DSTDY_TIM_SCAL << BIT_SHIFT_SYS_DSTDY_TIM_SCAL) | (BIT_MASK_SYS_ANACK_TU_TIME << BIT_SHIFT_SYS_ANACK_TU_TIME))))
|
||||
| ScaleTemp;
|
||||
|
|
@ -580,7 +582,7 @@ VOID SleepPwrGatted(
|
|||
|
||||
//3 1.5 Enable low power mode
|
||||
// 1.5.1 0x4000_0118[2] = 1 => for sleep mode
|
||||
Rtemp = 0x00000004;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000004;
|
||||
Rtemp = BIT_SYSON_PM_CMD_SLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000004;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//3 1.6 Wait CHIP enter low power mode
|
||||
|
|
@ -602,7 +604,7 @@ DStandby(
|
|||
u32 Rtemp = 0;
|
||||
u32 ScaleTemp = 0;
|
||||
u32 PeriodTemp = 0;
|
||||
u32 CalTemp = 0;
|
||||
// u32 CalTemp = 0;
|
||||
|
||||
//Backup CPU CLK
|
||||
BackupCPUClk();
|
||||
|
|
@ -615,7 +617,7 @@ DStandby(
|
|||
//3 1.1 Set TU timer timescale
|
||||
//0x4000_0090[21:16] = 6'h1F
|
||||
//0x4000_0090[15] = 1'b0 => Disable timer
|
||||
CalTemp = (CLKCal(ANACK) << 16);
|
||||
// CalTemp = (CLKCal(ANACK) << 16);
|
||||
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL)
|
||||
& (~((BIT_MASK_SYS_DSTDY_TIM_SCAL << BIT_SHIFT_SYS_DSTDY_TIM_SCAL) | (BIT_MASK_SYS_ANACK_TU_TIME << BIT_SHIFT_SYS_ANACK_TU_TIME))))
|
||||
| ScaleTemp;
|
||||
|
|
@ -648,7 +650,7 @@ DStandby(
|
|||
|
||||
//3 1.5 Enable low power mode
|
||||
// [0x4000_0118[1] = 1 => for deep standby mode]
|
||||
Rtemp = 0x00000002;
|
||||
Rtemp = BIT_SYSON_PM_CMD_DSTBY;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//3 1.6 Wait CHIP enter low power mode
|
||||
|
|
@ -673,8 +675,6 @@ DSleep(
|
|||
u32 UTemp = 0;
|
||||
u32 MaxTemp = 0;
|
||||
|
||||
u32 Reada335 = 0;
|
||||
|
||||
//2 Deep Sleep mode:
|
||||
//3 2.1 Set TU timer timescale
|
||||
|
||||
|
|
@ -724,16 +724,15 @@ DSleep(
|
|||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp);
|
||||
|
||||
HalDelayUs(1000);
|
||||
Reada335 = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CAL_CTRL);
|
||||
#if CONFIG_DEBUG_LOG > 3
|
||||
DiagPrintf("a33 timer : 0x%x\n", Reada335);
|
||||
DiagPrintf("a33 timer : 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CAL_CTRL));
|
||||
#endif
|
||||
|
||||
HalDelayUs(8000);
|
||||
|
||||
//3 2.2.3
|
||||
//2.3 Enable low power mode: 0x4000_0118[0] = 1'b1;
|
||||
Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
Rtemp = BIT_SYSON_PM_CMD_DSLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//2.4 Wait CHIP enter deep sleep mode
|
||||
|
|
@ -1418,6 +1417,9 @@ SetSYSTimer(
|
|||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp);
|
||||
}
|
||||
|
||||
/*
|
||||
* SDuration < 8355 ms!
|
||||
*/
|
||||
VOID
|
||||
SleepCG(
|
||||
IN u8 Option,
|
||||
|
|
@ -1446,7 +1448,8 @@ SleepCG(
|
|||
Rtemp = 0x74003B00; //0x74003900;
|
||||
}
|
||||
else {
|
||||
Rtemp = 0x74000900;
|
||||
Rtemp = 0x74000900; // BIT_SYSON_PMOPT_NORM_XTAL_EN | BIT_SYSON_PMOPT_NORM_SYSPLL_EN | BIT_SYSON_PMOPT_NORM_SYSCLK_SEL | BIT_SYSON_PMOPT_NORM_EN_PWM
|
||||
// | BIT_SYSON_PMOPT_SLP_LPLDO_SEL | BIT_SYSON_PMOPT_SLP_EN_SOC
|
||||
}
|
||||
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp);
|
||||
|
|
@ -1465,49 +1468,49 @@ SleepCG(
|
|||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp);
|
||||
|
||||
//Enable wake event
|
||||
WakeEvent |= BIT0;
|
||||
WakeEvent |= BIT0; // BIT_SYSON_WEVT_SYSTIM_MSK
|
||||
}
|
||||
|
||||
if (Option & SLP_GTIMER) {
|
||||
|
||||
//Enable wake event
|
||||
WakeEvent |= BIT1;
|
||||
WakeEvent |= BIT1; // BIT_SYSON_WEVT_GTIM_MSK
|
||||
}
|
||||
|
||||
if (Option & SLP_GPIO) {
|
||||
|
||||
//Enable wake event
|
||||
WakeEvent |= BIT4;
|
||||
WakeEvent |= BIT4; // BIT_SYSON_WEVT_GPIO_MSK
|
||||
}
|
||||
|
||||
if (Option & SLP_WL) {
|
||||
|
||||
//Enable wake event
|
||||
WakeEvent |= BIT8;
|
||||
WakeEvent |= BIT8; // BIT_SYSON_WEVT_WLAN_MSK
|
||||
}
|
||||
|
||||
if (Option & SLP_NFC) {
|
||||
|
||||
//Enable wake event
|
||||
WakeEvent |= BIT28;
|
||||
WakeEvent |= BIT28; // BIT_SYSON_WEVT_A33_MSK
|
||||
}
|
||||
|
||||
if (Option & SLP_SDIO) {
|
||||
|
||||
//Enable wake event
|
||||
WakeEvent |= BIT14;
|
||||
WakeEvent |= BIT14; // BIT_SYSON_WEVT_SDIO_MSK
|
||||
}
|
||||
|
||||
if (Option & SLP_USB) {
|
||||
|
||||
//Enable wake event
|
||||
//WakeEvent |= BIT16;
|
||||
//WakeEvent |= BIT16; // BIT_SYSON_WEVT_USB_MSK
|
||||
}
|
||||
|
||||
if (Option & SLP_TIMER33) {
|
||||
|
||||
//Enable wake event
|
||||
WakeEvent |= BIT28;
|
||||
WakeEvent |= BIT28; // BIT_SYSON_WEVT_A33_MSK
|
||||
}
|
||||
/*
|
||||
while(1) {
|
||||
|
|
@ -1533,7 +1536,7 @@ SleepCG(
|
|||
if (SDREn) SDRSleep();
|
||||
#endif
|
||||
|
||||
Rtemp = 0x00000004;
|
||||
Rtemp = BIT_SYSON_PM_CMD_SLP;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//3 Wait CHIP enter low power mode
|
||||
|
|
@ -1565,7 +1568,7 @@ SleepPG(
|
|||
|
||||
//3 2 Configure power state option:
|
||||
// 2.1 power mode option:
|
||||
Rtemp = 0x74000100;
|
||||
Rtemp = 0x74000100; // BIT_SYSON_PMOPT_SLP_LPLDO_SEL
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp);
|
||||
|
||||
// 2.2 sleep power mode option1
|
||||
|
|
@ -1648,7 +1651,7 @@ SleepPG(
|
|||
LDO25M_CTRL(OFF);
|
||||
#endif
|
||||
|
||||
Rtemp = 0x00000004;
|
||||
Rtemp = BIT_SYSON_PM_CMD_SLP;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//3 Wait CHIP enter low power mode
|
||||
|
|
@ -1701,7 +1704,7 @@ DeepStandby(
|
|||
|
||||
//3 2 Configure power state option:
|
||||
// 2.1 deep standby power mode option:
|
||||
Rtemp = 0x74000100;
|
||||
Rtemp = 0x74000100; // BIT_SYSON_PMOPT_SLP_LPLDO_SEL
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp);
|
||||
|
||||
// 2.2 sleep power mode option1
|
||||
|
|
@ -1737,19 +1740,19 @@ DeepStandby(
|
|||
|
||||
if (Option & DSTBY_GPIO){
|
||||
|
||||
if (GpioOption & BIT0) {
|
||||
if (GpioOption & BIT0) { // PA_5
|
||||
DSTBYGpioCtrl(BIT0, (GpioOption & BIT4));
|
||||
}
|
||||
|
||||
if (GpioOption & BIT1) {
|
||||
if (GpioOption & BIT1) { // PC_7
|
||||
DSTBYGpioCtrl(BIT1, (GpioOption & BIT5));
|
||||
}
|
||||
|
||||
if (GpioOption & BIT2) {
|
||||
if (GpioOption & BIT2) { // PD_5
|
||||
DSTBYGpioCtrl(BIT2, (GpioOption & BIT6));
|
||||
}
|
||||
|
||||
if (GpioOption & BIT3) {
|
||||
if (GpioOption & BIT3) { // PE_3
|
||||
DSTBYGpioCtrl(BIT3, (GpioOption & BIT7));
|
||||
}
|
||||
|
||||
|
|
@ -1773,10 +1776,10 @@ DeepStandby(
|
|||
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_GPIO_SHTDN_CTRL, 0x0);
|
||||
|
||||
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) & 0xBFFFFFFF);
|
||||
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) & (~BIT_SYS_PWRON_TRAP_SHTDN_N)); // 0xBFFFFFFF, ~BIT(30)
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN, Rtemp);
|
||||
|
||||
Rtemp = 0x00000002;
|
||||
Rtemp = BIT_SYSON_PM_CMD_DSTBY;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//3 Wait CHIP enter low power mode
|
||||
|
|
@ -1799,7 +1802,7 @@ DeepSleep(
|
|||
u32 UTemp = 0;
|
||||
u32 MaxTemp = 0;
|
||||
|
||||
//??? HAL_WRITE32(0x60008000, 0x80006180, PS_MASK);
|
||||
HAL_WRITE32(0x60008000, 0x80006180, PS_MASK);
|
||||
|
||||
//1.1.1 Enable REGU access interface 0x4000_0094[31] = 1
|
||||
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) | 0x80000000);
|
||||
|
|
@ -1885,7 +1888,7 @@ DeepSleep(
|
|||
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) & 0xBFFFFFFF);
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN, Rtemp);
|
||||
|
||||
Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
Rtemp = BIT_SYSON_PM_CMD_DSLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//2.4 Wait CHIP enter deep sleep mode
|
||||
|
|
@ -1916,7 +1919,7 @@ DSleep_GPIO(
|
|||
|
||||
//2.2.2
|
||||
//2.3 Enable low power mode: 0x4000_0118[0] = 1'b1;
|
||||
Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
Rtemp = BIT_SYSON_PM_CMD_DSLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//2.4 Wait CHIP enter deep sleep mode
|
||||
|
|
@ -1989,7 +1992,7 @@ DSleep_Timer(
|
|||
|
||||
//3 2.3
|
||||
//2.3 Enable low power mode: 0x4000_0118[0] = 1'b1;
|
||||
Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
Rtemp = BIT_SYSON_PM_CMD_DSLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//2.4 Wait CHIP enter deep sleep mode
|
||||
|
|
|
|||
|
|
@ -527,7 +527,7 @@ HalSsiInit(VOID *Data)
|
|||
{
|
||||
HAL_Status ret;
|
||||
PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
|
||||
u32 Function;
|
||||
u32 Function = SPI0;
|
||||
u8 PinmuxSelect;
|
||||
u8 Index;
|
||||
|
||||
|
|
|
|||
|
|
@ -1021,7 +1021,7 @@ HalRuartDmaSend(
|
|||
u32 BlockSize;
|
||||
HAL_Status ret;
|
||||
PUART_DMA_CONFIG pUartGdmaConfig;
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
// PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
|
||||
if (((Length & 0x03)==0) &&
|
||||
(((u32)(pTxBuf) & 0x03)==0)) {
|
||||
|
|
@ -1078,7 +1078,7 @@ HalRuartDmaRecv(
|
|||
// u32 BlockSize;
|
||||
HAL_Status ret;
|
||||
PUART_DMA_CONFIG pUartGdmaConfig;
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
// PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
|
||||
if (Length < 4096) {
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include "rtl8195a.h"
|
||||
#include "rtl_bios_data.h"
|
||||
#include "osdep_api.h"
|
||||
#include "osdep_service.h"
|
||||
#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1)
|
||||
#include "freertos_pmu.h"
|
||||
#else
|
||||
|
|
@ -44,7 +45,7 @@ IN u8 EchoFlag);
|
|||
//_LONG_CALL_ extern void UartLogCmdExecute(IN PUART_LOG_CTL pUartLogCtlExe);
|
||||
//======================================================
|
||||
extern PCOMMAND_TABLE UartLogRamCmdTable[];
|
||||
extern UartLogRamCmdTableSize;
|
||||
extern int UartLogRamCmdTableSize;
|
||||
//======================================================
|
||||
//<Function>: UartLogIrqHandleRam
|
||||
//<Usage >: To deal with Uart-Log RX IRQ
|
||||
|
|
@ -61,7 +62,7 @@ void UartLogIrqHandleRam(void * Data) {
|
|||
if (UartReceiveData == 0) {
|
||||
goto exit;
|
||||
}
|
||||
PUART_LOG_CTL p = pUartLogCtl;
|
||||
PUART_LOG_CTL p = (PUART_LOG_CTL) pUartLogCtl;
|
||||
//KB_ESC chk is for cmd history, it's a special case here.
|
||||
if (UartReceiveData == KB_ASCII_ESC) {
|
||||
// Esc detection is only valid in the first stage of boot sequence (few seconds)
|
||||
|
|
@ -102,7 +103,7 @@ void UartLogIrqHandleRam(void * Data) {
|
|||
if (p->pTmpLogBuf != NULL) {
|
||||
p->ExecuteCmd = _TRUE;
|
||||
if (p->TaskRdy) {
|
||||
RtlUpSemaFromISR((_Sema *) &pUartLogCtl->Sema);
|
||||
rtw_up_sema_from_isr((_Sema *) &pUartLogCtl->Sema);
|
||||
}
|
||||
} else {
|
||||
ArrayInitialize((u8 *) pUartLogCtl->pTmpLogBuf->UARTLogBuf,
|
||||
|
|
@ -130,7 +131,7 @@ int GetArgvRam(IN u8 *pstr, u8** argv) {
|
|||
int arvc = 0;
|
||||
// u8** argv = ArgvArray;
|
||||
u8* p = pstr;
|
||||
u8 t, n = ' ';
|
||||
u8 t = 0, n = ' ';
|
||||
int m = 0;
|
||||
while(*p != 0
|
||||
&& *p != '\r'
|
||||
|
|
@ -200,7 +201,7 @@ int GetArgvRam(IN u8 *pstr, u8** argv) {
|
|||
//<Notes >:
|
||||
//======================================================
|
||||
MON_RAM_TEXT_SECTION void RtlConsolTaskRam(void *Data) {
|
||||
PUART_LOG_CTL p = pUartLogCtl;
|
||||
PUART_LOG_CTL p = (PUART_LOG_CTL) pUartLogCtl;
|
||||
#ifdef USE_ROM_CONSOLE // show Help
|
||||
p->pTmpLogBuf->UARTLogBuf[0] = '?';
|
||||
p->pTmpLogBuf->BufCount = 1;
|
||||
|
|
@ -208,7 +209,7 @@ MON_RAM_TEXT_SECTION void RtlConsolTaskRam(void *Data) {
|
|||
#endif
|
||||
do {
|
||||
p->TaskRdy = _TRUE;
|
||||
RtlDownSema(&p->Sema);
|
||||
rtw_down_sema(&p->Sema);
|
||||
if (p->ExecuteCmd) {
|
||||
// UartLogCmdExecute(pUartLogCtl);
|
||||
int argc = GetArgvRam(p->pTmpLogBuf->UARTLogBuf, ArgvArray);
|
||||
|
|
@ -225,9 +226,9 @@ MON_RAM_TEXT_SECTION void RtlConsolTaskRam(void *Data) {
|
|||
flg = 0;
|
||||
if(pcmd->ArgvCnt < argc) {
|
||||
#ifdef USE_ROM_CONSOLE
|
||||
pcmd->func(argc-1, &ArgvArray[1]);
|
||||
pcmd->func(argc-1, (char **) &ArgvArray[1]);
|
||||
#else
|
||||
pcmd->func(argc, &ArgvArray);
|
||||
pcmd->func(argc, (char **) &ArgvArray);
|
||||
#endif
|
||||
} else {
|
||||
#ifdef USE_ROM_CONSOLE
|
||||
|
|
@ -291,7 +292,7 @@ MON_RAM_TEXT_SECTION void console_init(void) {
|
|||
#endif
|
||||
pUartLogCtl->RevdNo = UART_LOG_HISTORY_LEN;
|
||||
// Create a Semaphone
|
||||
RtlInitSema(&pUartLogCtl->Sema, 1);
|
||||
rtw_init_sema((_sema *)&pUartLogCtl->Sema, 1);
|
||||
// executing boot sequence
|
||||
pUartLogCtl->ExecuteCmd = _FALSE;
|
||||
pUartLogCtl->ExecuteEsc = _TRUE; //don't check Esc anymore
|
||||
|
|
@ -316,7 +317,7 @@ extern char str_rom_57ch3Dch0A[]; // "==========================================
|
|||
_WEAK void console_help(int argc, char *argv[]) { // Help
|
||||
DiagPrintf("CONSOLE COMMAND SET:\n");
|
||||
DiagPrintf(&str_rom_57ch3Dch0A[25]); // DiagPrintf("==============================\n");
|
||||
PCOMMAND_TABLE pcmdtab = UartLogRamCmdTable;
|
||||
PCOMMAND_TABLE pcmdtab = (PCOMMAND_TABLE) UartLogRamCmdTable;
|
||||
while(pcmdtab->cmd) {
|
||||
#ifdef USE_ROM_CONSOLE
|
||||
DiagPrintf(pcmdtab->msg);
|
||||
|
|
@ -327,7 +328,8 @@ _WEAK void console_help(int argc, char *argv[]) { // Help
|
|||
}
|
||||
DiagPrintf(&str_rom_57ch3Dch0A[25]); // DiagPrintf("==============================\n");
|
||||
}
|
||||
LOCAL void print_on(int argc, char *argv[])
|
||||
|
||||
void print_on(int argc, char *argv[])
|
||||
{
|
||||
print_off = argv[1][0]!='1';
|
||||
}
|
||||
|
|
|
|||
|
|
@ -105,6 +105,22 @@ extern _LONG_CALL_ double __rtl_dsub_v1_00(double a, double b);
|
|||
extern _LONG_CALL_ double __rtl_dmul_v1_00(double a, double b);
|
||||
extern _LONG_CALL_ double __rtl_ddiv_v1_00(double a, double b);
|
||||
|
||||
// --- ???
|
||||
extern _LONG_CALL_ float __rtl_dtof_v1_00(double d);
|
||||
extern _LONG_CALL_ int __rtl_dtoui_v1_00(double d);
|
||||
extern _LONG_CALL_ float __rtl_itof_v1_00(int val);
|
||||
extern _LONG_CALL_ char *__rtl_ltoa_v1_00(int value, char *string, int radix);
|
||||
extern _LONG_CALL_ char *__rtl_ultoa_v1_00(unsigned int value, char *string, int radix);
|
||||
extern _LONG_CALL_ int __rtl_ftol_v1_00(float f);
|
||||
extern _LONG_CALL_ int __rtl_ftod_v1_00(float f);
|
||||
extern _LONG_CALL_ float __rtl_fadd_v1_00(float a, float b);
|
||||
extern _LONG_CALL_ float __rtl_fsub_v1_00(float a, float b);
|
||||
extern _LONG_CALL_ float __rtl_fmul_v1_00(float a, float b);
|
||||
extern _LONG_CALL_ float __rtl_fdiv_v1_00(float a, float b);
|
||||
extern _LONG_CALL_ int __rtl_dcmple_v1_00(double a, double b);
|
||||
extern _LONG_CALL_ int __rtl_fcmplt_v1_00(float a, float b);
|
||||
extern _LONG_CALL_ int __rtl_fcmpgt_v1_00(float a, float b);
|
||||
// --- ???
|
||||
|
||||
//
|
||||
// mprec
|
||||
|
|
|
|||
|
|
@ -22,7 +22,9 @@
|
|||
#define strsep __rtl_strsep_v1_00
|
||||
#define strtok __rtl_strtok_v1_00
|
||||
|
||||
static char toupper(char ch) {
|
||||
extern int isdigit (int c);
|
||||
|
||||
static int toupper(int ch) {
|
||||
return ((ch >= 'a' && ch <= 'z') ? ch - 'a' + 'A' : ch);
|
||||
};
|
||||
|
||||
|
|
@ -371,7 +373,7 @@ llatob(u_quad_t *vp, char *p, int base)
|
|||
char *
|
||||
btoa(char *dst, u_int value, int base)
|
||||
{
|
||||
char buf[34], digit;
|
||||
char buf[34], digit = 0;
|
||||
int i, j, rem, neg;
|
||||
|
||||
if (value == 0) {
|
||||
|
|
@ -417,7 +419,7 @@ btoa(char *dst, u_int value, int base)
|
|||
char *
|
||||
llbtoa(char *dst, u_quad_t value, int base)
|
||||
{
|
||||
char buf[66], digit;
|
||||
char buf[66], digit = 0;
|
||||
int i, j, rem, neg;
|
||||
|
||||
if (value == 0) {
|
||||
|
|
@ -536,7 +538,7 @@ c_vsprintf (char *d, const char *s, va_list ap)
|
|||
const char *t;
|
||||
char *p, *dst, tmp[40];
|
||||
unsigned int n;
|
||||
int fmt, trunc, haddot, width, base, longlong;
|
||||
int fmt, trunc, haddot, width, base = 0, longlong;
|
||||
double dbl;
|
||||
#ifndef NEWFP
|
||||
EP ex;
|
||||
|
|
@ -1072,11 +1074,14 @@ int c_printf(const char *fmt, ...)
|
|||
|
||||
#endif // ENAC_FLOAT
|
||||
|
||||
extern _LONG_CALL_ROM_ void HalSerialPutcRtl8195a(char c);
|
||||
|
||||
int puts (const char *s)
|
||||
{
|
||||
while(*s) {
|
||||
HalSerialPutcRtl8195a(*s++);
|
||||
}
|
||||
return 0; // -1 -> EOF
|
||||
}
|
||||
|
||||
void vTaskDelete(void *);
|
||||
|
|
|
|||
|
|
@ -170,7 +170,6 @@ int rtl_vprintf(const char *fmt, va_list param) {
|
|||
int rtl_vsnprintf(char *str, size_t size, const char *fmt, va_list param) {
|
||||
int result;
|
||||
int w;
|
||||
int v11;
|
||||
FILE f;
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
|
|
|
|||
|
|
@ -122,6 +122,6 @@ void init_rom_libgloss_ram_map(void) {
|
|||
rom_libgloss_ram_map.libgloss_open = ram_libgloss_open;
|
||||
rom_libgloss_ram_map.libgloss_read = ram_libgloss_read;
|
||||
rom_libgloss_ram_map.libgloss_write = ram_libgloss_write;
|
||||
rom_libgloss_ram_map.libgloss_sbrk = ram_libgloss_sbrk;
|
||||
rom_libgloss_ram_map.libgloss_sbrk = (void*)ram_libgloss_sbrk;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -67,9 +67,12 @@ unsigned long long __aeabi_llsr(unsigned long long val, unsigned int shift);
|
|||
|
||||
extern struct _reent * _rtl_impure_ptr;
|
||||
|
||||
#if CHECK_LIBC_INIT
|
||||
extern char libc_has_init;
|
||||
#endif
|
||||
extern char print_off;
|
||||
|
||||
#undef snprintf
|
||||
//-------------------------------------------------------------------------
|
||||
// Function
|
||||
//----- snprintf()
|
||||
|
|
@ -107,7 +110,9 @@ int snprintf(char *str, size_t size, const char *fmt, ...) {
|
|||
return result;
|
||||
}
|
||||
|
||||
|
||||
#ifndef ENAC_FLOAT
|
||||
#undef sprintf
|
||||
//----- sprintf()
|
||||
int sprintf(char *str, const char *fmt, ...) {
|
||||
FILE f;
|
||||
|
|
@ -131,6 +136,7 @@ int sprintf(char *str, const char *fmt, ...) {
|
|||
return result;
|
||||
}
|
||||
|
||||
#undef printf
|
||||
//----- printf()
|
||||
int printf(const char *fmt, ...) {
|
||||
#if CHECK_LIBC_INIT
|
||||
|
|
@ -151,6 +157,7 @@ int printf(const char *fmt, ...) {
|
|||
else return 0;
|
||||
}
|
||||
|
||||
#undef vprintf
|
||||
//----- vprintf()
|
||||
int vprintf(const char * fmt, __VALIST param) {
|
||||
#if CHECK_LIBC_INIT
|
||||
|
|
@ -165,11 +172,11 @@ int vprintf(const char * fmt, __VALIST param) {
|
|||
}
|
||||
#endif // ENAC_FLOAT
|
||||
|
||||
#undef vsnprintf
|
||||
//----- vsnprintf()
|
||||
int vsnprintf(char *str, size_t size, const char *fmt, __VALIST param) {
|
||||
int result;
|
||||
int w;
|
||||
int v11;
|
||||
FILE f;
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
|
|
@ -199,6 +206,7 @@ int vsnprintf(char *str, size_t size, const char *fmt, __VALIST param) {
|
|||
return result;
|
||||
}
|
||||
|
||||
#undef vfprintf
|
||||
//----- vfprintf()
|
||||
int vfprintf(FILE *fp, const char *fmt0, va_list ap) {
|
||||
#if CHECK_LIBC_INIT
|
||||
|
|
@ -209,86 +217,103 @@ int vfprintf(FILE *fp, const char *fmt0, va_list ap) {
|
|||
return __rtl_vfprintf_r_v1_00(_rtl_impure_ptr, fp, fmt0, ap);
|
||||
}
|
||||
|
||||
#undef memchr
|
||||
//----- memchr()
|
||||
void * memchr(const void * src_void , int c , size_t length) {
|
||||
return __rtl_memchr_v1_00(src_void, c, length);
|
||||
}
|
||||
|
||||
#undef memcmp
|
||||
//----- memcmp()
|
||||
int memcmp(const void *m1, const void *m2, size_t n) {
|
||||
return __rtl_memcmp_v1_00(m1, m2, n);
|
||||
}
|
||||
|
||||
#undef memcpy
|
||||
//----- memcpy()
|
||||
void * memcpy(void *dst0, const void *src0, size_t len0) {
|
||||
return __rtl_memcpy_v1_00(dst0, src0, len0);
|
||||
}
|
||||
|
||||
#undef memmove
|
||||
//----- memmove()
|
||||
void * memmove(void *dst_void, const void *src_void, size_t length) {
|
||||
return __rtl_memmove_v1_00(dst_void, src_void, length);
|
||||
}
|
||||
|
||||
#undef memset
|
||||
//----- memset()
|
||||
void * memset(void *m, int c, size_t n) {
|
||||
return __rtl_memset_v1_00(m, c, n);
|
||||
}
|
||||
|
||||
#undef strcat
|
||||
//----- strcat()
|
||||
char * strcat(char *s1, const char *s2) {
|
||||
return (char *) __rtl_strcat_v1_00(s1, s2);
|
||||
}
|
||||
|
||||
#undef strchr
|
||||
//----- strchr()
|
||||
char * strchr(const char *s1, int i) {
|
||||
return (char *) __rtl_strchr_v1_00(s1, i);
|
||||
}
|
||||
|
||||
#undef strcmp
|
||||
//----- strcmp()
|
||||
int strcmp(const char *s1, const char *s2) {
|
||||
return __rtl_strcmp_v1_00(s1, s2);
|
||||
}
|
||||
|
||||
#undef strcpy
|
||||
//----- strcpy()
|
||||
char * strcpy(char *dst0, const char *src0) {
|
||||
return (char *) __rtl_strcpy_v1_00(dst0, src0);
|
||||
}
|
||||
|
||||
#undef strlen
|
||||
//----- strlen()
|
||||
size_t strlen(const char *str) {
|
||||
return __rtl_strlen_v1_00(str);
|
||||
}
|
||||
|
||||
#undef strncat
|
||||
//----- strncat()
|
||||
char * strncat(char *s1, const char *s2, size_t n) {
|
||||
return (char *) __rtl_strncat_v1_00(s1, s2, n);
|
||||
}
|
||||
|
||||
#undef strncmp
|
||||
//----- strncmp()
|
||||
int strncmp(const char *s1, const char *s2, size_t n) {
|
||||
return __rtl_strncmp_v1_00(s1, s2, n);
|
||||
}
|
||||
|
||||
#undef strncpy
|
||||
//----- strncpy()
|
||||
char * strncpy(char *dst0, const char *src0, size_t count) {
|
||||
return (char *) __rtl_strncpy_v1_00(dst0, src0, count);
|
||||
}
|
||||
|
||||
#undef strstr
|
||||
//----- strstr()
|
||||
char * strstr(const char *searchee, const char *lookfor) {
|
||||
return (char *) __rtl_strstr_v1_00(searchee, lookfor);
|
||||
}
|
||||
|
||||
#undef strsep
|
||||
//----- strsep()
|
||||
char * strsep(char **source_ptr, const char *delim) {
|
||||
return (char *) __rtl_strsep_v1_00(source_ptr, delim);
|
||||
}
|
||||
|
||||
#undef strtok
|
||||
//----- strtok()
|
||||
char * strtok(char *s, const char *delim) {
|
||||
return (char *) __rtl_strtok_v1_00(s, delim);
|
||||
}
|
||||
|
||||
extern _LONG_CALL_ROM_ int _vsscanf(const char *buf, const char *fmt, va_list args);
|
||||
#undef sscanf
|
||||
int sscanf(const char *buf, const char *fmt, ...) {
|
||||
va_list args;
|
||||
int i;
|
||||
|
|
@ -300,7 +325,7 @@ int sscanf(const char *buf, const char *fmt, ...) {
|
|||
return i;
|
||||
}
|
||||
|
||||
char toupper(char ch) {
|
||||
int toupper(int ch) {
|
||||
return ((ch >= 'a' && ch <= 'z') ? ch - 'a' + 'A' : ch);
|
||||
};
|
||||
|
||||
|
|
@ -366,7 +391,7 @@ void longjmp(__jmp_buf buf, long value)
|
|||
|
||||
extern __attribute__ ((long_call)) unsigned int Rand(void);
|
||||
|
||||
unsigned int rand(void)
|
||||
int rand(void)
|
||||
{
|
||||
return Rand();
|
||||
}
|
||||
|
|
@ -534,3 +559,8 @@ int __aeabi_fcmpgt(float a, float b)
|
|||
{
|
||||
return __rtl_fcmpgt_v1_00(a, b);
|
||||
}
|
||||
|
||||
extern _LONG_CALL_ void __aeabi_memset(void *dest, size_t n, int c); // { memset(dest, c, n); }
|
||||
|
||||
void __aeabi_memclr(void *dest, size_t n) { __aeabi_memset(dest, n, 0); }
|
||||
void __aeabi_memclr4(void *dest, size_t n) { __aeabi_memset(dest, n, 0); }
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
*/
|
||||
|
||||
#include "basic_types.h"
|
||||
#include "rt_lib_rom.h"
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Function declarations
|
||||
|
|
|
|||
|
|
@ -20,25 +20,28 @@ float rtl_sin_f32(float a);
|
|||
// int __rtl_cos_f32_v1_00();
|
||||
// int __rtl_sin_f32_v1_00();
|
||||
|
||||
|
||||
extern _LONG_CALL_ float __rtl_fabsf_v1_00(float a);
|
||||
//----- rtl_fabsf()
|
||||
float rtl_fabsf(float a)
|
||||
{
|
||||
return __rtl_fabsf_v1_00(a);
|
||||
}
|
||||
|
||||
extern _LONG_CALL_ int __rtl_fabs_v1_00(double a);
|
||||
//----- rtl_fabs()
|
||||
int rtl_fabs(double a)
|
||||
{
|
||||
return __rtl_fabs_v1_00(a);
|
||||
}
|
||||
|
||||
extern _LONG_CALL_ float __rtl_cos_f32_v1_00(float a);
|
||||
//----- rtl_cos_f32()
|
||||
float rtl_cos_f32(float a)
|
||||
{
|
||||
return __rtl_cos_f32_v1_00(a);
|
||||
}
|
||||
|
||||
extern _LONG_CALL_ float __rtl_sin_f32_v1_00(float a);
|
||||
//----- rtl_sin_f32()
|
||||
float rtl_sin_f32(float a)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -19,9 +19,11 @@
|
|||
# FLAGS
|
||||
# -------------------------------------------------------------------
|
||||
CFLAGS = -DM3 -DCONFIG_PLATFORM_8195A -DGCC_ARMCM3 -DARDUINO_SDK -DF_CPU=166666666L -DNDEBUG
|
||||
CFLAGS += -mcpu=cortex-m3 -mthumb -g2 -Os -std=gnu99 -Wall -Werror
|
||||
CFLAGS += -mcpu=cortex-m3 -mthumb -g2 -Os -std=gnu99
|
||||
CFLAGS += -fno-common -fmessage-length=0 -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-short-enums -fsigned-char
|
||||
CFLAGS += -w -Wno-pointer-sign
|
||||
CFLAGS += -Wall -Werror
|
||||
CFLAGS += -Wno-old-style-declaration -Wno-pointer-sign -Wno-strict-aliasing
|
||||
CFLAGS += -Wno-variadic-macros -Wno-empty-body
|
||||
ifdef USE_GCC_LIB
|
||||
LFLAGS = -mcpu=cortex-m3 -mthumb -g -Os -nostartfiles --specs=nano.specs
|
||||
else
|
||||
|
|
@ -39,6 +41,10 @@ else
|
|||
all: LIBS +=_platform_new _wlan _p2p _wps _websocket _sdcard _xmodem _mdns
|
||||
mp: LIBS +=_platform_new _wlan_mp _wps _p2p _websocket _sdcard _xmodem _mdns
|
||||
endif
|
||||
ifdef USE_UVC
|
||||
all: LIBS +=_rtsp _usbh
|
||||
mp: LIBS +=_rtsp _usbh
|
||||
endif
|
||||
# m c nosys gcc
|
||||
PATHLIBS = sdk/component/soc/realtek/8195a/misc/bsp/lib/common/gcc
|
||||
LDFILE = rlx8195A-symbol-v04-img2.ld
|
||||
|
|
@ -81,11 +87,14 @@ INCLUDES += sdk/component/common/drivers/wlan/realtek/src/hal/OUTSRC
|
|||
INCLUDES += sdk/component/common/drivers/sdio/realtek/sdio_host/inc
|
||||
INCLUDES += sdk/component/soc/realtek/8195a/fwlib/ram_lib/wlan/realtek/wlan_ram_map/rom
|
||||
INCLUDES += sdk/component/common/network/ssl/ssl_ram_map/rom
|
||||
#INCLUDES += sdk/component/common/media/codec
|
||||
#INCLUDES += sdk/component/common/drivers/usb_class/host/uvc/inc
|
||||
#INCLUDES += sdk/component/common/drivers/usb_class/device
|
||||
#INCLUDES += sdk/component/common/drivers/usb_class/device/class
|
||||
#INCLUDES += sdk/component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include
|
||||
ifdef USE_UVC
|
||||
INCLUDES += sdk/component/common/media/codec
|
||||
INCLUDES += sdk/component/common/video/v4l2/inc
|
||||
INCLUDES += sdk/component/common/drivers/usb_class/host/uvc/inc
|
||||
INCLUDES += sdk/component/common/drivers/usb_class/device
|
||||
INCLUDES += sdk/component/common/drivers/usb_class/device/class
|
||||
INCLUDES += sdk/component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include
|
||||
endif
|
||||
|
||||
# Source file list
|
||||
# -------------------------------------------------------------------
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
4718
build/obj/build.nmap
4718
build/obj/build.nmap
File diff suppressed because it is too large
Load diff
|
|
@ -85,18 +85,14 @@ extern uint32_t SystemCoreClock;
|
|||
* See http://www.freertos.org/a00110.html.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
#define configUSE_STACK_TCM_HEAP 1 // RTL871xAx/RTL8195Ax Stack priority used TCM HEAP
|
||||
#define configUSE_STACK_TCM_HEAP 5 // RTL871xAx/RTL8195Ax Stack priority used TCM HEAP
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_IDLE_HOOK 1
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configCPU_CLOCK_HZ ( SystemCoreClock )
|
||||
#define configTICK_RATE_HZ ( ( uint32_t ) 1000 )
|
||||
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 )
|
||||
#ifdef CONFIG_UVC
|
||||
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 110 * 1024 ) ) // use HEAP5
|
||||
#else
|
||||
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 90 * 1024 ) ) // use HEAP5
|
||||
#endif
|
||||
#define configMAX_TASK_NAME_LEN ( 10 )
|
||||
#define configUSE_TRACE_FACILITY 0
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
|
|
@ -112,10 +108,11 @@ extern uint32_t SystemCoreClock;
|
|||
|
||||
#define configUSE_COUNTING_SEMAPHORES 1
|
||||
#define configUSE_ALTERNATIVE_API 0
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 2
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 0
|
||||
#define configUSE_RECURSIVE_MUTEXES 1
|
||||
#define configQUEUE_REGISTRY_SIZE 0
|
||||
#define configGENERATE_RUN_TIME_STATS 1
|
||||
|
||||
#if configGENERATE_RUN_TIME_STATS
|
||||
#define configUSE_STATS_FORMATTING_FUNCTIONS 1
|
||||
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() //( ulHighFrequencyTimerTicks = 0UL )
|
||||
|
|
@ -137,8 +134,8 @@ extern uint32_t SystemCoreClock;
|
|||
|
||||
#if (__IASMARM__ != 1)
|
||||
|
||||
extern void freertos_pre_sleep_processing(unsigned int *expected_idle_time);
|
||||
extern void freertos_post_sleep_processing(unsigned int *expected_idle_time);
|
||||
extern void freertos_pre_sleep_processing(uint32_t *expected_idle_time);
|
||||
extern void freertos_post_sleep_processing(uint32_t *expected_idle_time);
|
||||
extern int freertos_ready_to_sleep();
|
||||
|
||||
/* Enable tickless power saving. */
|
||||
|
|
@ -210,4 +207,6 @@ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
|
|||
//#define RTK_MODE_TIMER
|
||||
|
||||
|
||||
#define INCLUDE_uxTaskGetStackHighWaterMark 1
|
||||
|
||||
#endif /* FREERTOS_CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -8,8 +8,8 @@
|
|||
#ifndef _INC_FEEP_CONFIG_H_
|
||||
#define _INC_FEEP_CONFIG_H_
|
||||
|
||||
#define FEEP_ID_WIFI_CFG 0x5730 // id:'0W', type: struct wlan_fast_reconnect
|
||||
#define FEEP_ID_WIFI_AP_CFG 0x5731 // id:'1W', type: struct rtw_wifi_config_t
|
||||
//#define FEEP_ID_WIFI_CFG 0x5730 // id:'0W', type: struct wlan_fast_reconnect
|
||||
//#define FEEP_ID_WIFI_AP_CFG 0x5731 // id:'1W', type: struct rtw_wifi_config_t
|
||||
#define FEEP_ID_UART_CFG 0x5530 // id:'0U', type: UART_LOG_CONF
|
||||
#define FEEP_ID_LWIP_CFG 0x4C30 // id:'0L', type: struct atcmd_lwip_conf
|
||||
#define FEEP_ID_DHCP_CFG 0x4430 // id:'0D', type: struct
|
||||
|
|
|
|||
|
|
@ -167,6 +167,7 @@ a lot of data that needs to be copied, this should be set high. */
|
|||
* LWIP_AUTOIP==1: Enable AUTOIP module.
|
||||
*/
|
||||
#define LWIP_AUTOIP 0 //Realtek modified (0->1)
|
||||
|
||||
/* ---------- DHCP options ---------- */
|
||||
/* Define LWIP_DHCP to 1 if you want DHCP configuration of
|
||||
interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
|
||||
|
|
@ -184,6 +185,7 @@ a lot of data that needs to be copied, this should be set high. */
|
|||
|
||||
/* Support Multicast */
|
||||
#define LWIP_IGMP 1
|
||||
|
||||
extern __attribute__ ((long_call)) unsigned int Rand(void);
|
||||
#define LWIP_RAND() Rand()
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,9 @@
|
|||
/* #undef EXPERIMENTAL */
|
||||
|
||||
/* Define to disable debugging assertions. */
|
||||
#ifndef NDEBUG
|
||||
#define NDEBUG
|
||||
#endif
|
||||
|
||||
/* Define to optimize for accuracy over speed. */
|
||||
/* #undef OPT_ACCURACY */
|
||||
|
|
|
|||
|
|
@ -74,8 +74,8 @@ struct mad_frame {
|
|||
mad_fixed_t (*overlap)[2][32][18]; /* Layer III block overlap data */
|
||||
};
|
||||
|
||||
# define MAD_NCHANNELS(header) ((header)->mode ? 2 : 1)
|
||||
# define MAD_NSBSAMPLES(header) \
|
||||
#define MAD_NCHANNELS(header) ((header)->mode ? 2 : 1)
|
||||
#define MAD_NSBSAMPLES(header) \
|
||||
((header)->layer == MAD_LAYER_I ? 12 : \
|
||||
(((header)->layer == MAD_LAYER_III && \
|
||||
((header)->flags & MAD_FLAG_LSF_EXT)) ? 18 : 36))
|
||||
|
|
|
|||
|
|
@ -718,7 +718,7 @@ struct mad_stream {
|
|||
enum mad_error error; /* error code (see above) */
|
||||
};
|
||||
|
||||
enum {
|
||||
enum _MAD_OPTION{
|
||||
MAD_OPTION_IGNORECRC = 0x0001, /* ignore CRC errors */
|
||||
MAD_OPTION_HALFSAMPLERATE = 0x0002 /* generate PCM at 1/2 sample rate */
|
||||
# if 0 /* not yet implemented */
|
||||
|
|
|
|||
|
|
@ -83,7 +83,7 @@ struct mad_stream {
|
|||
enum mad_error error; /* error code (see above) */
|
||||
};
|
||||
|
||||
enum {
|
||||
enum e_MAD_OPTION_{
|
||||
MAD_OPTION_IGNORECRC = 0x0001, /* ignore CRC errors */
|
||||
MAD_OPTION_HALFSAMPLERATE = 0x0002 /* generate PCM at 1/2 sample rate */
|
||||
# if 0 /* not yet implemented */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
*
|
||||
* Automatically generated by make menuconfig: don't edit
|
||||
*/
|
||||
#define AUTOCONF_INCLUDED
|
||||
|
||||
|
|
@ -12,10 +12,11 @@
|
|||
/*
|
||||
* Target Platform Selection
|
||||
*/
|
||||
#define CONFIG_WITHOUT_MONITOR 1
|
||||
#define CONFIG_USE_TCM_HEAP 1
|
||||
#define configUSE_STACK_TCM_HEAP 5 // min priority use tcm ?
|
||||
|
||||
#define CONFIG_WITHOUT_MONITOR 1
|
||||
|
||||
#undef CONFIG_RTL8195A
|
||||
#define CONFIG_RTL8195A 1
|
||||
#undef CONFIG_FPGA
|
||||
|
|
@ -134,8 +135,8 @@
|
|||
#define CONFIG_CRYPTO_NORMAL 1
|
||||
#undef CONFIG_CRYPTO_TEST
|
||||
#define CONFIG_CRYPTO_MODULE 1
|
||||
#define CONFIG_CRYPTO_STARTUP 0
|
||||
#define CONFIG_MII_EN 1
|
||||
#define CONFIG_CRYPTO_STARTUP 1
|
||||
#define CONFIG_MII_EN 0 //1
|
||||
#define CONFIG_PWM_EN 1
|
||||
#define CONFIG_PWM_NORMAL 1
|
||||
#undef CONFIG_PWM_TEST
|
||||
|
|
@ -155,7 +156,7 @@
|
|||
#undef CONFIG_SPIC_TEST
|
||||
#define CONFIG_SPIC_MODULE 1
|
||||
#define CONFIG_ADC_EN 1
|
||||
//#define CONFIG_DAC_EN 1
|
||||
#define CONFIG_DAC_EN 1
|
||||
#define CONFIG_NOR_FLASH 1
|
||||
#undef CONFIG_SPI_FLASH
|
||||
#undef CONFIG_NAND_FLASH
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#define __PLATFORM_OPTS_H__
|
||||
|
||||
/*For MP mode setting*/
|
||||
#define SUPPORT_MP_MODE 1
|
||||
#define SUPPORT_MP_MODE 0
|
||||
|
||||
/**
|
||||
* For AT cmd Log service configurations
|
||||
|
|
@ -39,7 +39,7 @@
|
|||
* For FreeRTOS tickless configurations
|
||||
*/
|
||||
#define FREERTOS_PMU_TICKLESS_PLL_RESERVED 0 // In sleep mode, 0: close PLL clock, 1: reserve PLL clock
|
||||
#define FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM 1 // In sleep mode, 1: suspend SDRAM, 0: no act
|
||||
#define FREERTOS_PMU_TICKLESS_SUSPEND_SDRAM 0 // In sleep mode, 1: suspend SDRAM, 0: no act
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
|
|
@ -53,6 +53,7 @@
|
|||
/**
|
||||
* For Wlan configurations
|
||||
*/
|
||||
|
||||
#define CONFIG_WLAN 1
|
||||
#if CONFIG_WLAN
|
||||
#define CONFIG_LWIP_LAYER 1
|
||||
|
|
@ -86,7 +87,7 @@
|
|||
#endif
|
||||
|
||||
/* For Simple Link */
|
||||
#define CONFIG_INCLUDE_SIMPLE_CONFIG 1
|
||||
#define CONFIG_INCLUDE_SIMPLE_CONFIG 0
|
||||
|
||||
/*For wowlan service settings*/
|
||||
#define CONFIG_WOWLAN_SERVICE 0
|
||||
|
|
@ -157,4 +158,15 @@
|
|||
#define USE_FLASH_EEP 1
|
||||
#define CONFIG_WLAN_CONNECT_CB 1
|
||||
|
||||
//#define CONFIG_FATFS_EN 1 // FatFs & SD
|
||||
#ifdef CONFIG_FATFS_EN
|
||||
// fatfs version
|
||||
#define FATFS_R_10C
|
||||
// fatfs disk interface
|
||||
#define FATFS_DISK_USB 0
|
||||
#define FATFS_DISK_SD 1
|
||||
#undef CONFIG_SDIO_HOST_EN
|
||||
#define CONFIG_SDIO_HOST_EN 1
|
||||
#endif
|
||||
|
||||
#endif //__PLATFORM_OPTS_H__
|
||||
|
|
|
|||
|
|
@ -1,114 +0,0 @@
|
|||
/*
|
||||
*
|
||||
*
|
||||
*/
|
||||
#ifndef _INCLUDE_ESP_COMP_H_
|
||||
#define _INCLUDE_ESP_COMP_H_
|
||||
|
||||
#include "platform_autoconf.h"
|
||||
|
||||
#define ICACHE_FLASH_ATTR
|
||||
#define ICACHE_RODATA_ATTR
|
||||
#define DATA_IRAM_ATTR
|
||||
|
||||
#define os_printf(...) rtl_printf(__VA_ARGS__)
|
||||
#define os_printf_plus(...) rtl_printf(__VA_ARGS__)
|
||||
#define os_sprintf_fd(...) rtl_sprintf(__VA_ARGS__)
|
||||
#define ets_sprintf(...) rtl_sprintf(__VA_ARGS__)
|
||||
/*
|
||||
#define os_malloc pvPortMalloc
|
||||
#define os_zalloc pvPortZalloc
|
||||
#define os_calloc pvPortCalloc
|
||||
#define os_realloc pvPortRealloc
|
||||
*/
|
||||
#undef os_free
|
||||
#define os_free vPortFree
|
||||
#define system_get_free_heap_size xPortGetFreeHeapSize
|
||||
#undef os_realloc
|
||||
#define os_realloc pvPortReAlloc
|
||||
|
||||
|
||||
#define os_bzero rtl_bzero
|
||||
#define os_delay_us wait_us // HalDelayUs
|
||||
//#define os_install_putc1 rtl_install_putc1
|
||||
//#define os_install_putc2 rtl_install_putc2
|
||||
//#define os_intr_lock rtl_intr_lock
|
||||
//#define os_intr_unlock rtl_intr_unlock
|
||||
//#define os_isr_attach rtl_isr_attach
|
||||
//#define os_isr_mask rtl_isr_mask
|
||||
//#define os_isr_unmask rtl_isr_unmask
|
||||
#define os_memcmp rtl_memcmp
|
||||
#define os_memcpy rtl_memcpy
|
||||
#define ets_memcpy rtl_memcpy
|
||||
#define os_memmove rtl_memmove
|
||||
#define os_memset rtl_memset
|
||||
#define os_putc rtl_putc
|
||||
//#define os_str2macaddr rtl_str2macaddr
|
||||
//#define os_strcat strcat
|
||||
#define os_strchr rtl_strchr
|
||||
#define os_strrchr rtl_strrchr
|
||||
#define os_strcmp rtl_strcmp
|
||||
#define os_strcpy rtl_strcpy
|
||||
#define os_strlen rtl_strlen
|
||||
#define os_strncmp rtl_strncmp
|
||||
#define os_strncpy rtl_strncpy
|
||||
#define os_strstr rtl_strstr
|
||||
#define os_random Rand
|
||||
//extern uint32 phy_get_rand(void);
|
||||
#define system_get_os_print() 1
|
||||
|
||||
#ifdef USE_US_TIMER
|
||||
#define os_timer_arm_us(a, b, c) rtl_timer_arm_new(a, b, c)
|
||||
#endif
|
||||
|
||||
|
||||
//#define os_timer_arm(a, b, c) rtl_timer_arm_new(a, b, c)
|
||||
//#define os_timer_disarm rtl_timer_disarm
|
||||
//#define os_timer_init rtl_timer_init
|
||||
//#define os_timer_setfn rtl_timer_setfn
|
||||
|
||||
//#define os_timer_done rtl_timer_done
|
||||
//#define os_timer_handler_isr rtl_timer_handler_isr
|
||||
|
||||
//#define os_update_cpu_frequency rtl_update_cpu_frequency
|
||||
|
||||
//#define os_sprintf ets_sprintf
|
||||
|
||||
#define spi_flash_real_size() (1<<(flashobj.SpicInitPara.id[2]-1))
|
||||
|
||||
|
||||
|
||||
#define ip4_addr1(ipaddr) (((u8_t*)(ipaddr))[0])
|
||||
#define ip4_addr2(ipaddr) (((u8_t*)(ipaddr))[1])
|
||||
#define ip4_addr3(ipaddr) (((u8_t*)(ipaddr))[2])
|
||||
#define ip4_addr4(ipaddr) (((u8_t*)(ipaddr))[3])
|
||||
/* These are cast to u16_t, with the intent that they are often arguments
|
||||
* to printf using the U16_F format from cc.h. */
|
||||
#define ip4_addr1_16(ipaddr) ((u16_t)ip4_addr1(ipaddr))
|
||||
#define ip4_addr2_16(ipaddr) ((u16_t)ip4_addr2(ipaddr))
|
||||
#define ip4_addr3_16(ipaddr) ((u16_t)ip4_addr3(ipaddr))
|
||||
#define ip4_addr4_16(ipaddr) ((u16_t)ip4_addr4(ipaddr))
|
||||
|
||||
#define IP2STR(ipaddr) ip4_addr1_16(ipaddr), \
|
||||
ip4_addr2_16(ipaddr), \
|
||||
ip4_addr3_16(ipaddr), \
|
||||
ip4_addr4_16(ipaddr)
|
||||
|
||||
#define IPSTR "%d.%d.%d.%d"
|
||||
|
||||
/* CONFIG_DEBUG_LOG:
|
||||
=0 Off all diag/debug msg,
|
||||
=1 Only errors,
|
||||
=2 errors + warning, (default)
|
||||
=3 errors + warning + info,
|
||||
=4 errors + warning + info + debug,
|
||||
=5 full */
|
||||
#if CONFIG_DEBUG_LOG > 3
|
||||
#define DEBUGSOO (CONFIG_DEBUG_LOG - 1)
|
||||
#elif CONFIG_DEBUG_LOG > 1
|
||||
#define DEBUGSOO 2
|
||||
#else
|
||||
#define DEBUGSOO CONFIG_DEBUG_LOG
|
||||
#endif
|
||||
|
||||
#endif // _INCLUDE_ESP_COMP_H_
|
||||
|
|
@ -5,9 +5,9 @@
|
|||
#ifndef _INC_RTL_LIBC_
|
||||
#define _INC_RTL_LIBC_
|
||||
|
||||
//#undef malloc
|
||||
#undef malloc
|
||||
#define malloc(size) pvPortMalloc(size)
|
||||
//#undef free
|
||||
#undef free
|
||||
#define free(pbuf) vPortFree(pbuf)
|
||||
|
||||
#define atoi(str) prvAtoi(str)
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
#define DEF_WIFI_COUNTRY RTW_COUNTRY_RU // Регион использования WiFi...
|
||||
#define DEF_WIFI_TX_PWR RTW_TX_PWR_PERCENTAGE_25 // RTW_TX_PWR_PERCENTAGE_75 // RTW_TX_PWR_PERCENTAGE_100
|
||||
#define DEF_WIFI_BGN RTW_NETWORK_BGN // rtw_network_mode_t
|
||||
#define DEF_WIFI_ADAPTIVITY RTW_ADAPTIVITY_NORMAL // RTW_ADAPTIVITY_DISABLE/RTW_ADAPTIVITY_NORMAL/RTW_ADAPTIVITY_CARRIER_SENSE
|
||||
#define DEF_WIFI_ADAPTIVITY RTW_ADAPTIVITY_DISABLE // RTW_ADAPTIVITY_NORMAL // RTW_ADAPTIVITY_DISABLE/RTW_ADAPTIVITY_NORMAL/RTW_ADAPTIVITY_CARRIER_SENSE
|
||||
|
||||
/* Опции загрузки конфигов по старту */
|
||||
//#define DEF_LOAD_CFG 0 // старт в назначенном режиме по умолчанию
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
RTW_SECURITY_WPA_TKIP_PSK - WPA Security
|
||||
RTW_SECURITY_WPA2_AES_PSK - WPA2 Security using AES cipher
|
||||
RTW_SECURITY_WPA2_MIXED_PSK - WPA2 Security using AES and/or TKIP ciphers */
|
||||
#define DEF_AP_SECURITY RTW_SECURITY_WPA2_AES_PSK // WEP security is NOT IMPLEMENTED. It is NOT SECURE!
|
||||
#define DEF_AP_SECURITY RTW_ENCRYPTION_WPA2_MIXED // WEP security is NOT IMPLEMENTED. It is NOT SECURE!
|
||||
#define DEF_AP_BEACON 100 // 100...6000 ms
|
||||
#define DEF_AP_CHANNEL 1 // 1..14
|
||||
#define DEF_AP_CHANNEL 1 // 1..14
|
||||
|
|
@ -47,7 +47,7 @@
|
|||
//==== Interface 1 - wlan1 = STA ==========
|
||||
#define DEF_ST_SSID "HOMEAP" // Имя SSID AP (роутера) для присоединения по умолчанию (первый старт)
|
||||
#define DEF_ST_PASSWORD "0123456789" // Пароль AP (роутера) для присоединения по умолчанию (первый старт)
|
||||
#define DEF_ST_SECURITY RTW_SECURITY_WPA_WPA2_MIXED // Тип Security
|
||||
#define DEF_ST_SECURITY RTW_ENCRYPTION_WPA2_MIXED // Тип Security
|
||||
#define DEF_ST_BSSID { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } // If bssid set is not ff.ff.ff.ff.ff.ff,
|
||||
#define DEF_ST_USE_BSSID 0 // station will connect to the router with both ssid[] and bssid[] matched.
|
||||
#define DEF_ST_CHANNEL 1 // 1..14
|
||||
|
|
|
|||
|
|
@ -32,6 +32,8 @@ speed.
|
|||
#include "osdep_api.h"
|
||||
#include "i2s_api.h"
|
||||
#include "driver/i2s_freertos.h"
|
||||
#include "rtl_lib.h"
|
||||
#include "rtl8195a/rtl_libc.h"
|
||||
|
||||
#define USE_RTL_I2S_API 0 // speed
|
||||
|
||||
|
|
@ -103,7 +105,7 @@ int i2sInit(int mask, int bufsize, int word_len) { // word_len = WL_16b or WL_24
|
|||
DBG_8195A("I2S%d: Not heap buffer %d bytes!\n", i, sizeof(i2s_t) + page_size * I2S_DMA_PAGE_NUM);
|
||||
return 0;
|
||||
}
|
||||
rtl_memset(pi2s_new, 0, sizeof(i2s_t));
|
||||
memset(pi2s_new, 0, sizeof(i2s_t));
|
||||
u8 * i2s_tx_buf = (u8 *) pvPortMalloc(page_size * I2S_DMA_PAGE_NUM);
|
||||
if (i2s_tx_buf == NULL) {
|
||||
vPortFree(pi2s_new);
|
||||
|
|
@ -135,12 +137,13 @@ int i2sInit(int mask, int bufsize, int word_len) { // word_len = WL_16b or WL_24
|
|||
else i2s_init(pi2s_obj, I2S1_SCLK_PIN, I2S1_WS_PIN, I2S1_SD_PIN);
|
||||
i2s_set_param(pi2s_obj, pi2s_obj->channel_num, pi2s_obj->sampling_rate, pi2s_obj->word_length);
|
||||
i2s_set_dma_buffer(pi2s_obj, i2s_tx_buf, NULL, I2S_DMA_PAGE_NUM, page_size);
|
||||
i2s_tx_irq_handler(pi2s_obj, i2s_test_tx_complete, (uint32_t)pi2s_obj);
|
||||
i2s_tx_irq_handler(pi2s_obj, (i2s_irq_handler)i2s_test_tx_complete, (uint32_t)pi2s_obj);
|
||||
// i2s_rx_irq_handler(pi2s_obj, (i == 0)? (i2s_irq_handler)i2s1_test_rx_complete : (i2s_irq_handler)i2s2_test_rx_complete, i); // TX only!
|
||||
i2s_enable(pi2s_obj);
|
||||
DBG_8195A("I2S%d: Alloc DMA buf %d bytes (%d x %d samples %d bits)\n", i, page_size * I2S_DMA_PAGE_NUM, I2S_DMA_PAGE_NUM, bufsize, (word_len == WL_16b)? 32 : 96);
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
//Set the I2S sample rate, in HZ
|
||||
|
|
@ -265,6 +268,7 @@ u32 i2sPushPWMSamples(u32 sample) {
|
|||
}
|
||||
}
|
||||
portEXIT_CRITICAL();
|
||||
return sample;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,16 +19,16 @@
|
|||
* $Id: synth.c,v 1.25 2004/01/23 09:41:33 rob Exp $
|
||||
*/
|
||||
|
||||
# ifdef HAVE_CONFIG_H
|
||||
# include "config.h"
|
||||
# endif
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
# include "global.h"
|
||||
#include "global.h"
|
||||
|
||||
# include "fixed.h"
|
||||
# include "frame.h"
|
||||
# include "synth.h"
|
||||
# include "string.h"
|
||||
#include "fixed.h"
|
||||
#include "frame.h"
|
||||
#include "synth.h"
|
||||
#include "string.h"
|
||||
|
||||
// #define SAVED_SAMPLE_BUFF_LEN 240000
|
||||
// unsigned int saved_idx = 0;
|
||||
|
|
@ -582,6 +582,7 @@ void synth_full(struct mad_synth *, struct mad_frame const *,
|
|||
* NAME: synth->full()
|
||||
* DESCRIPTION: perform full frequency PCM synthesis
|
||||
*/
|
||||
extern void render_sample_block(short int *short_sample_buff, int no_samples);
|
||||
static
|
||||
void synth_full(struct mad_synth *synth, struct mad_frame const *frame,
|
||||
unsigned int nch, unsigned int ns)
|
||||
|
|
@ -608,7 +609,7 @@ void synth_full(struct mad_synth *synth, struct mad_frame const *frame,
|
|||
|
||||
for (ch = 0; ch < nch; ++ch)
|
||||
{
|
||||
sbsample = &frame->sbsample[ch];
|
||||
sbsample = (void *)&frame->sbsample[ch];
|
||||
filter = &synth->filter[ch];
|
||||
pcm1 = short_sample_buff[ch];
|
||||
|
||||
|
|
@ -732,7 +733,7 @@ void synth_full(struct mad_synth *synth, struct mad_frame const *frame,
|
|||
|
||||
/* Render di un blocco */
|
||||
if(nch < 2) memcpy(short_sample_buff[1], short_sample_buff[0], sizeof(short_sample_buff[0]));
|
||||
render_sample_block(short_sample_buff, sizeof(short_sample_buff[0])/sizeof(short int));
|
||||
render_sample_block((short int *) short_sample_buff, sizeof(short_sample_buff[0])/sizeof(short int));
|
||||
|
||||
phase = (phase + 1) % 16;
|
||||
|
||||
|
|
@ -745,11 +746,12 @@ void synth_full(struct mad_synth *synth, struct mad_frame const *frame,
|
|||
* DESCRIPTION: perform half frequency PCM synthesis
|
||||
*/
|
||||
static
|
||||
void synth_half(struct mad_synth *synth, struct mad_frame const *frame,
|
||||
void synth_half(struct mad_synth *synth, struct mad_frame *frame,
|
||||
unsigned int nch, unsigned int ns)
|
||||
{
|
||||
unsigned int phase, ch, s, sb, pe, po;
|
||||
short int *pcm1, *pcm1v, *pcm2v;
|
||||
// short int *pcm1;
|
||||
short int *pcm1v, *pcm2v;
|
||||
mad_fixed_t (*filter)[2][2][16][8];
|
||||
mad_fixed_t (*sbsample)[36][32];
|
||||
register mad_fixed_t (*fe)[8], (*fx)[8], (*fo)[8];
|
||||
|
|
@ -772,7 +774,8 @@ void synth_half(struct mad_synth *synth, struct mad_frame const *frame,
|
|||
{
|
||||
sbsample = &frame->sbsample[ch];
|
||||
filter = &synth->filter[ch];
|
||||
pcm1 = pcm1v = short_sample_buff;
|
||||
// pcm1 =
|
||||
pcm1v = (short int *)short_sample_buff;
|
||||
|
||||
dct32((*sbsample)[s], phase >> 1,
|
||||
(*filter)[0][phase & 1], (*filter)[1][phase & 1]);
|
||||
|
|
@ -894,14 +897,15 @@ void synth_half(struct mad_synth *synth, struct mad_frame const *frame,
|
|||
|
||||
/* Render di un blocco */
|
||||
if(nch < 2) memcpy(short_sample_buff[1], short_sample_buff[0], sizeof(short_sample_buff[0]));
|
||||
render_sample_block(short_sample_buff, sizeof(short_sample_buff[0])/sizeof(short int));
|
||||
render_sample_block((short int *)short_sample_buff, sizeof(short_sample_buff[0])/sizeof(short int));
|
||||
|
||||
pcm1 = pcm1v + 8;
|
||||
// pcm1 = pcm1v + 8;
|
||||
phase = (phase + 1) % 16;
|
||||
|
||||
} /* for di blocco */
|
||||
}
|
||||
|
||||
extern void set_dac_sample_rate(int rate, int chls);
|
||||
/*
|
||||
* NAME: synth->frame()
|
||||
* DESCRIPTION: perform PCM synthesis of frame subband samples
|
||||
|
|
@ -925,7 +929,7 @@ void mad_synth_frame(struct mad_synth *synth, struct mad_frame const *frame)
|
|||
if (frame->options & MAD_OPTION_HALFSAMPLERATE) {
|
||||
synth->pcm.samplerate /= 2;
|
||||
synth->pcm.length /= 2;
|
||||
synth_frame = synth_half;
|
||||
synth_frame = (void *)synth_half;
|
||||
}
|
||||
set_dac_sample_rate(synth->pcm.samplerate, nch);
|
||||
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ LOCAL void fATST(int argc, char *argv[]) {
|
|||
#if 0 //CONFIG_DEBUG_LOG > 1
|
||||
dump_mem_block_list();
|
||||
tcm_heap_dump();
|
||||
#endif;
|
||||
#endif
|
||||
printf("\n");
|
||||
#if (configGENERATE_RUN_TIME_STATS == 1)
|
||||
char *cBuffer = pvPortMalloc(512);
|
||||
|
|
@ -132,7 +132,7 @@ void dump_bytes(uint32 addr, int size)
|
|||
while (size) {
|
||||
if (symbs_line > size) symbs_line = size;
|
||||
printf("%08X ", addr);
|
||||
copy_align4_to_align1(buf, addr, symbs_line);
|
||||
copy_align4_to_align1(buf, (void *)addr, symbs_line);
|
||||
print_hex_dump(buf, symbs_line, ' ');
|
||||
int i;
|
||||
for(i = 0 ; i < symbs_line ; i++) {
|
||||
|
|
@ -151,6 +151,7 @@ void dump_bytes(uint32 addr, int size)
|
|||
//------------------------------------------------------------------------------
|
||||
// Dump byte register
|
||||
//------------------------------------------------------------------------------
|
||||
extern _LONG_CALL_ u32 Strtoul(IN const u8 *nptr, IN u8 **endptr, IN u32 base);
|
||||
LOCAL void fATSB(int argc, char *argv[])
|
||||
{
|
||||
int size = 16;
|
||||
|
|
|
|||
|
|
@ -3,13 +3,16 @@
|
|||
* FileName: user_main.c
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include "platform_autoconf.h"
|
||||
#include "autoconf.h"
|
||||
#include "rtl8195a/rtl_common.h"
|
||||
#include "rtl8195a.h"
|
||||
#include "hal_log_uart.h"
|
||||
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
//#include "diag.h"
|
||||
#include "diag.h"
|
||||
#include "osdep_service.h"
|
||||
#include "device_lock.h"
|
||||
#include "semphr.h"
|
||||
|
|
@ -33,6 +36,7 @@
|
|||
#include "user/playerconfig.h"
|
||||
#include "user/atcmd_user.h"
|
||||
#include "main.h"
|
||||
#include "flash_eep.h"
|
||||
#include "wifi_api.h"
|
||||
#include "rtl8195a/rtl_libc.h"
|
||||
|
||||
|
|
@ -88,7 +92,7 @@ LOCAL int mp3_cfg_read(void)
|
|||
|
||||
// Called by the NXP modifications of libmad. It passes us (for the mono synth)
|
||||
// 32 16-bit samples.
|
||||
void render_sample_block(short *short_sample_buff, int no_samples) {
|
||||
void render_sample_block(short int *short_sample_buff, int no_samples) {
|
||||
int i;
|
||||
for (i = 0; i < no_samples; i++) {
|
||||
int x = oversampling;
|
||||
|
|
@ -122,6 +126,8 @@ void set_dac_sample_rate(int rate, int chls) {
|
|||
oversampling = i2sSetRate(-1, rate);
|
||||
}
|
||||
|
||||
extern int RamFifoLen(void);
|
||||
|
||||
static enum mad_flow input(struct mad_stream *stream) {
|
||||
int n, i;
|
||||
int rem; //, fifoLen;
|
||||
|
|
@ -203,9 +209,9 @@ LOCAL void tskmad(void *pvParameters) {
|
|||
sizeof(struct mad_stream) + sizeof(struct mad_frame) + sizeof(struct mad_synth) + READBUFSZ,
|
||||
mad_bufs);
|
||||
#endif
|
||||
struct mad_stream *stream = mad_bufs;
|
||||
struct mad_frame *frame = &mad_bufs[sizeof(struct mad_stream)];
|
||||
struct mad_synth *synth = &mad_bufs[sizeof(struct mad_stream)
|
||||
struct mad_stream *stream = (struct mad_stream *)mad_bufs;
|
||||
struct mad_frame *frame = (struct mad_frame *) &mad_bufs[sizeof(struct mad_stream)];
|
||||
struct mad_synth *synth = (struct mad_synth *) &mad_bufs[sizeof(struct mad_stream)
|
||||
+ sizeof(struct mad_frame)];
|
||||
readBuf = &mad_bufs[sizeof(struct mad_stream) + sizeof(struct mad_frame)
|
||||
+ sizeof(struct mad_synth)];
|
||||
|
|
@ -374,6 +380,8 @@ LOCAL int http_head_read(unsigned char *buf, int len, int ff) {
|
|||
return ret;
|
||||
}
|
||||
|
||||
extern void RamFifoClose(void);
|
||||
|
||||
//Reader task. This will try to read data from a TCP socket into the SPI fifo buffer.
|
||||
LOCAL void tskreader(void *pvParameters) {
|
||||
char wbuf[SOCK_READ_BUF];
|
||||
|
|
@ -503,6 +511,8 @@ void connect_start(void) {
|
|||
#endif
|
||||
}
|
||||
|
||||
extern int tcm_heap_freeSpace(void);
|
||||
extern void console_init(void);
|
||||
/* RAM/TCM/Heaps info */
|
||||
void ShowMemInfo(void)
|
||||
{
|
||||
|
|
@ -525,13 +535,15 @@ LOCAL void user_init_thrd(void) {
|
|||
vTaskDelete(NULL);
|
||||
}
|
||||
|
||||
extern void WDGStart(void);
|
||||
extern int rtl_cryptoEngine_init(void);
|
||||
|
||||
/**
|
||||
* @brief Main program.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void main(void)
|
||||
int main(void)
|
||||
{
|
||||
#if DEBUG_MAIN_LEVEL > 3
|
||||
ConfigDebugErr = -1;
|
||||
|
|
@ -560,7 +572,7 @@ void main(void)
|
|||
#endif
|
||||
|
||||
/* wlan & user_start intialization */
|
||||
xTaskCreate(user_init_thrd, "user_init", 1024, NULL, tskIDLE_PRIORITY + 0 + PRIORITIE_OFFSET, NULL);
|
||||
xTaskCreate((TaskFunction_t) user_init_thrd, "user_init", 1024, NULL, tskIDLE_PRIORITY + 0 + PRIORITIE_OFFSET, NULL);
|
||||
|
||||
/*Enable Schedule, Start Kernel*/
|
||||
#if defined(CONFIG_KERNEL) && !TASK_SCHEDULER_DISABLED
|
||||
|
|
@ -600,7 +612,7 @@ LOCAL void fATWS(int argc, char *argv[]){
|
|||
}
|
||||
else if(argv[1][0] == 'S') { // strcmp(argv[1], "save") == 0
|
||||
printf("%s: %s,%d\n", argv[0], mp3_serv.url, mp3_serv.port);
|
||||
if(flash_write_cfg(&mp3_serv, ID_FEEP_MP3, strlen(mp3_serv.port) + strlen(mp3_serv.url)))
|
||||
if(flash_write_cfg(&mp3_serv, ID_FEEP_MP3, sizeof(mp3_serv.port) + strlen((const char *)mp3_serv.url)))
|
||||
printf("ATWS: saved\n", mp3_serv.url, mp3_serv.port);
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
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Reference in a new issue