j3d1/RTL00MP3
1
0
Fork 0
mirror of https://github.com/pvvx/RTL00MP3.git synced 2026-07-12 14:35:39 +00:00
Code Issues Projects Releases Packages Wiki Activity

update -Wall -Werror

Browse source
This commit is contained in:
pvvx 2017-09-07 02:26:00 +03:00
parent 2c29a376ba
commit 7cb9553f73
102 changed files with 3686 additions and 3504 deletions
Download patch file Download diff file Expand all files Collapse all files

2
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_bios_data.c
View file

@ -116,7 +116,7 @@ HAL_CUT_B_RAM_DATA_SECTION u32 rand_x = 123456789; // 10000be4
0, \
"", \
0, \
0x0437DC, \
(void *)0x0437DC, \
0, \
_NULL, \
_NULL, \

18
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c
View file

@ -257,12 +257,12 @@ LOCAL int BOOT_RAM_TEXT_SECTION SetSpicBitMode(uint8 BitMode) {
}
void BOOT_RAM_TEXT_SECTION InitSpicFlashType(struct spic_table_flash_type *ptable_flash) {
u8 * ptrb = &ptable_flash->cmd;
volatile u32 * ptrreg = (volatile u32 *)(SPI_FLASH_CTRL_BASE + REG_SPIC_READ_FAST_SINGLE);// 0x400060E0
uint8 * ptrb = (uint8 *)&ptable_flash->cmd;
volatile uint32 * ptrreg = (volatile uint32 *)(SPI_FLASH_CTRL_BASE + REG_SPIC_READ_FAST_SINGLE);// 0x400060E0
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); // Disable SPI_FLASH User Mode
do {
*ptrreg++ = *ptrb++;
} while(ptrb < (u8 *)(&ptable_flash->fsize));
} while(ptrb < (uint8 *)(&ptable_flash->fsize));
ptrreg[0] = ptable_flash->contrl;
ptrreg[1] = ptable_flash->validcmd[SpicOneBitMode];
ptrreg[2] = ptable_flash->fsize;
@ -387,6 +387,7 @@ typedef enum {
SEG_ID_MAX
} _SEG_ID;
#if CONFIG_DEBUG_LOG > 1
LOCAL const char * const txt_tab_seg[] = {
"UNK", // 0
"SRAM", // 1
@ -397,6 +398,7 @@ LOCAL const char * const txt_tab_seg[] = {
"CPU", // 6
"ROM" // 7
};
#endif
LOCAL const uint32 tab_seg_def[] = { 0x10000000, 0x10070000, 0x1fff0000,
0x20000000, 0x30000000, 0x30200000, 0x40000000, 0x40800000, 0x98000000,
@ -404,7 +406,7 @@ LOCAL const uint32 tab_seg_def[] = { 0x10000000, 0x10070000, 0x1fff0000,
LOCAL uint32 BOOT_RAM_TEXT_SECTION get_seg_id(uint32 addr, int32 size) {
uint32 ret = SEG_ID_ERR;
uint32 * ptr = &tab_seg_def;
uint32 * ptr = (uint32 *) &tab_seg_def;
if (size > 0) {
do {
ret++;
@ -447,7 +449,7 @@ LOCAL uint32 BOOT_RAM_TEXT_SECTION load_segs(uint32 faddr, PIMG2HEAD hdr,
segnum, faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr,
hdr->seg.size);
#endif
fnextaddr += flashcpy(fnextaddr, hdr->seg.ldaddr, hdr->seg.size);
fnextaddr += flashcpy(fnextaddr, (void *)hdr->seg.ldaddr, hdr->seg.size);
} else if (seg_id) {
#if CONFIG_DEBUG_LOG > 2
DBG_8195A("Skip Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n", segnum,
@ -457,7 +459,7 @@ LOCAL uint32 BOOT_RAM_TEXT_SECTION load_segs(uint32 faddr, PIMG2HEAD hdr,
} else {
break;
}
fnextaddr += flashcpy(fnextaddr, &hdr->seg, sizeof(IMGSEGHEAD));
fnextaddr += flashcpy(fnextaddr, (void *) &hdr->seg, sizeof(IMGSEGHEAD));
segnum++;
}
return fnextaddr;
@ -476,7 +478,7 @@ LOCAL int BOOT_RAM_TEXT_SECTION loadUserImges(int imgnum) {
faddr = (faddr + FLASH_SECTOR_SIZE - 1) & (~(FLASH_SECTOR_SIZE - 1));
uint32 img_id = load_img2_head(faddr, &hdr);
if ((img_id >> 8) > 4 || (uint8) img_id != 0) {
faddr = load_segs(faddr + 0x10, &hdr.seg, imagenum == imgnum);
faddr = load_segs(faddr + 0x10, &hdr, imagenum == imgnum);
if (imagenum == imgnum) {
// DBG_8195A("Image%d: %s\n", imgnum, hdr.name);
break;
@ -544,7 +546,7 @@ LOCAL void BOOT_RAM_TEXT_SECTION RtlConsolRam(void) {
pUartLogCtl->pTmpLogBuf->UARTLogBuf[0] = '?';
pUartLogCtl->pTmpLogBuf->BufCount = 1;
pUartLogCtl->ExecuteCmd = 1;
RtlConsolTaskRom(pUartLogCtl);
RtlConsolTaskRom((void *)pUartLogCtl);
}
/* Enter Image 1.5 */

11
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c
View file

@ -26,6 +26,15 @@ extern void xPortPendSVHandler(void);
extern void xPortSysTickHandler(void);
extern void vPortSVCHandler(void);
extern void rtl_libc_init(void);
extern _LONG_CALL_ void HalCpuClkConfig(unsigned char CpuType);
extern void PSHalInitPlatformLogUart(void);
extern _LONG_CALL_ void UartLogCmdExecute(PUART_LOG_CTL pUartLogCtlExe);
extern void HalReInitPlatformTimer(void);
extern void SystemCoreClockUpdate (void);
extern void En32KCalibration(void);
extern void SdrCtrlInit(void);
extern void InitSoCPM(void);
extern u32 SdrControllerInit(void);
//extern void ShowRamBuildInfo(void); // app_start.c: VOID ShowRamBuildInfo(VOID)
//void HalNMIHandler_Patch(void);
void SDIO_Device_Off(void);
@ -97,7 +106,7 @@ __weak int main(void) {
DiagPrintf("\r<RTL>");
while (1) {
while (pUartLogCtl->ExecuteCmd != 1);
UartLogCmdExecute(pUartLogCtl);
UartLogCmdExecute((PUART_LOG_CTL) pUartLogCtl);
DiagPrintf("\r<RTL>");
pUartLogCtl->ExecuteCmd = 0;
}