mirror of
https://github.com/pvvx/RTL00MP3.git
synced 2025-07-31 12:41:06 +00:00
update -Wall -Werror
This commit is contained in:
pvvx
parent
2c29a376ba
commit
7cb9553f73
102 changed files with 3686 additions and 3504 deletions
|
|
@ -1,6 +1,7 @@
|
|||
#ifndef _BITBAND_IO_H_
|
||||
#define _BITBAND_IO_H_
|
||||
|
||||
#include "PinNames.h"
|
||||
#include "hal_platform.h"
|
||||
#include "hal_api.h"
|
||||
#include "hal_gpio.h"
|
||||
|
|
@ -10,12 +11,34 @@
|
|||
#define BITBAND_SRAM_BASE 0x12000000
|
||||
#define BITBAND_SRAM(a,b) (BITBAND_SRAM_BASE + (a-BITBAND_SRAM_REF)*32 + (b*4)) // Convert SRAM address
|
||||
|
||||
#define BITBAND_ADDR(a,b) (0x02000000 + (a & 0xF0000000) + (a - (a & 0xF0000000)) * 32 + ((b) * 4)) // Convert address ?
|
||||
/*
|
||||
* in hal_platform.h
|
||||
#define BITBAND_REG_BASE 0x40001000
|
||||
*/
|
||||
|
||||
/*
|
||||
* in rtl8195a_gpio.h
|
||||
*
|
||||
#define BITBAND_PORTA_DR 0x00 // data register
|
||||
#define BITBAND_PORTA_DDR 0x04 // data direction
|
||||
#define BITBAND_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software
|
||||
|
||||
#define BITBAND_PORTB_DR 0x0c // data register
|
||||
#define BITBAND_PORTB_DDR 0x10 // data direction
|
||||
#define BITBAND_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software
|
||||
|
||||
#define BITBAND_PORTC_DR 0x18 // data register
|
||||
#define BITBAND_PORTC_DDR 0x1c // data direction
|
||||
#define BITBAND_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software
|
||||
|
||||
#define BITBAND_EXT_PORTA 0x50 // GPIO IN read or OUT read back
|
||||
#define BITBAND_EXT_PORTB 0x54 // GPIO IN read or OUT read back
|
||||
#define BITBAND_EXT_PORTC 0x58 // GPIO IN read or OUT read back
|
||||
*/
|
||||
|
||||
#define BITBAND_PERI_REF 0x40000000
|
||||
#define BITBAND_PERI_BASE 0x42000000
|
||||
#define BITBAND_PERI(a,b) (BITBAND_PERI_BASE + (a - BITBAND_PERI_REF) * 32 + ((b) * 4)) // Convert PERI address
|
||||
|
||||
#define BITBAND_PERI(a,b) (BITBAND_PERI_BASE + (a-BITBAND_PERI_REF)*32 + (b*4)) // Convert PERI address
|
||||
#define ucBITBAND_PERI(a,b) *((volatile unsigned char *)BITBAND_PERI(a,b))
|
||||
#define uiBITBAND_PERI(a,b) *((volatile unsigned int *)BITBAND_PERI(a,b))
|
||||
|
||||
|
|
@ -121,10 +144,10 @@
|
|||
#define BITBAND_K5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,25) //Port = 2, bit = 25, K5
|
||||
#define BITBAND_K6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,26) //Port = 2, bit = 26, K6
|
||||
|
||||
volatile u8 * BitBandAddr(void *addr, u8 bit);
|
||||
volatile u8 * BitBandPeriAddr(void *addr, u8 bit);
|
||||
volatile u8 * GetOutPinBitBandAddr(PinName pin);
|
||||
volatile u8 * GetInpPinBitBandAddr(PinName pin);
|
||||
volatile u8 * HardSetPin(PinName pin, PinDirection pdir, PinMode pmode, u8 val);
|
||||
volatile uint8_t * BitBandAddr(void *addr, uint8_t bit);
|
||||
volatile uint8_t * BitBandPeriAddr(void *addr, uint8_t bit);
|
||||
volatile uint8_t * GetOutPinBitBandAddr(PinName pin);
|
||||
volatile uint8_t * GetInPinBitBandAddr(PinName pin);
|
||||
volatile uint8_t * HardSetPin(PinName pin, HAL_GPIO_PIN_MODE pmode, uint8_t val);
|
||||
|
||||
#endif // _BITBAND_IO_H_
|
||||
|
|
|
|||
|
|
@ -74,9 +74,9 @@ typedef struct _LOG_UART_ADAPTER_ {
|
|||
typedef struct _COMMAND_TABLE_ {
|
||||
const u8* cmd;
|
||||
u16 ArgvCnt;
|
||||
u32 (*func)(u16 argc, u8* argv[]);
|
||||
void (*func)(int argc, char * argv[]); // u32 (*func)(u16 argc, u8* argv[]);
|
||||
const u8* msg;
|
||||
}COMMAND_TABLE, *PCOMMAND_TABLE;
|
||||
} COMMAND_TABLE, *PCOMMAND_TABLE;
|
||||
|
||||
//VOID
|
||||
//HalLogUartHandle(void);
|
||||
|
|
|
|||
|
|
@ -116,7 +116,7 @@ HAL_CUT_B_RAM_DATA_SECTION u32 rand_x = 123456789; // 10000be4
|
|||
0, \
|
||||
"", \
|
||||
0, \
|
||||
0x0437DC, \
|
||||
(void *)0x0437DC, \
|
||||
0, \
|
||||
_NULL, \
|
||||
_NULL, \
|
||||
|
|
|
|||
|
|
@ -257,12 +257,12 @@ LOCAL int BOOT_RAM_TEXT_SECTION SetSpicBitMode(uint8 BitMode) {
|
|||
}
|
||||
|
||||
void BOOT_RAM_TEXT_SECTION InitSpicFlashType(struct spic_table_flash_type *ptable_flash) {
|
||||
u8 * ptrb = &ptable_flash->cmd;
|
||||
volatile u32 * ptrreg = (volatile u32 *)(SPI_FLASH_CTRL_BASE + REG_SPIC_READ_FAST_SINGLE);// 0x400060E0
|
||||
uint8 * ptrb = (uint8 *)&ptable_flash->cmd;
|
||||
volatile uint32 * ptrreg = (volatile uint32 *)(SPI_FLASH_CTRL_BASE + REG_SPIC_READ_FAST_SINGLE);// 0x400060E0
|
||||
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); // Disable SPI_FLASH User Mode
|
||||
do {
|
||||
*ptrreg++ = *ptrb++;
|
||||
} while(ptrb < (u8 *)(&ptable_flash->fsize));
|
||||
} while(ptrb < (uint8 *)(&ptable_flash->fsize));
|
||||
ptrreg[0] = ptable_flash->contrl;
|
||||
ptrreg[1] = ptable_flash->validcmd[SpicOneBitMode];
|
||||
ptrreg[2] = ptable_flash->fsize;
|
||||
|
|
@ -387,6 +387,7 @@ typedef enum {
|
|||
SEG_ID_MAX
|
||||
} _SEG_ID;
|
||||
|
||||
#if CONFIG_DEBUG_LOG > 1
|
||||
LOCAL const char * const txt_tab_seg[] = {
|
||||
"UNK", // 0
|
||||
"SRAM", // 1
|
||||
|
|
@ -397,6 +398,7 @@ LOCAL const char * const txt_tab_seg[] = {
|
|||
"CPU", // 6
|
||||
"ROM" // 7
|
||||
};
|
||||
#endif
|
||||
|
||||
LOCAL const uint32 tab_seg_def[] = { 0x10000000, 0x10070000, 0x1fff0000,
|
||||
0x20000000, 0x30000000, 0x30200000, 0x40000000, 0x40800000, 0x98000000,
|
||||
|
|
@ -404,7 +406,7 @@ LOCAL const uint32 tab_seg_def[] = { 0x10000000, 0x10070000, 0x1fff0000,
|
|||
|
||||
LOCAL uint32 BOOT_RAM_TEXT_SECTION get_seg_id(uint32 addr, int32 size) {
|
||||
uint32 ret = SEG_ID_ERR;
|
||||
uint32 * ptr = &tab_seg_def;
|
||||
uint32 * ptr = (uint32 *) &tab_seg_def;
|
||||
if (size > 0) {
|
||||
do {
|
||||
ret++;
|
||||
|
|
@ -447,7 +449,7 @@ LOCAL uint32 BOOT_RAM_TEXT_SECTION load_segs(uint32 faddr, PIMG2HEAD hdr,
|
|||
segnum, faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr,
|
||||
hdr->seg.size);
|
||||
#endif
|
||||
fnextaddr += flashcpy(fnextaddr, hdr->seg.ldaddr, hdr->seg.size);
|
||||
fnextaddr += flashcpy(fnextaddr, (void *)hdr->seg.ldaddr, hdr->seg.size);
|
||||
} else if (seg_id) {
|
||||
#if CONFIG_DEBUG_LOG > 2
|
||||
DBG_8195A("Skip Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n", segnum,
|
||||
|
|
@ -457,7 +459,7 @@ LOCAL uint32 BOOT_RAM_TEXT_SECTION load_segs(uint32 faddr, PIMG2HEAD hdr,
|
|||
} else {
|
||||
break;
|
||||
}
|
||||
fnextaddr += flashcpy(fnextaddr, &hdr->seg, sizeof(IMGSEGHEAD));
|
||||
fnextaddr += flashcpy(fnextaddr, (void *) &hdr->seg, sizeof(IMGSEGHEAD));
|
||||
segnum++;
|
||||
}
|
||||
return fnextaddr;
|
||||
|
|
@ -476,7 +478,7 @@ LOCAL int BOOT_RAM_TEXT_SECTION loadUserImges(int imgnum) {
|
|||
faddr = (faddr + FLASH_SECTOR_SIZE - 1) & (~(FLASH_SECTOR_SIZE - 1));
|
||||
uint32 img_id = load_img2_head(faddr, &hdr);
|
||||
if ((img_id >> 8) > 4 || (uint8) img_id != 0) {
|
||||
faddr = load_segs(faddr + 0x10, &hdr.seg, imagenum == imgnum);
|
||||
faddr = load_segs(faddr + 0x10, &hdr, imagenum == imgnum);
|
||||
if (imagenum == imgnum) {
|
||||
// DBG_8195A("Image%d: %s\n", imgnum, hdr.name);
|
||||
break;
|
||||
|
|
@ -544,7 +546,7 @@ LOCAL void BOOT_RAM_TEXT_SECTION RtlConsolRam(void) {
|
|||
pUartLogCtl->pTmpLogBuf->UARTLogBuf[0] = '?';
|
||||
pUartLogCtl->pTmpLogBuf->BufCount = 1;
|
||||
pUartLogCtl->ExecuteCmd = 1;
|
||||
RtlConsolTaskRom(pUartLogCtl);
|
||||
RtlConsolTaskRom((void *)pUartLogCtl);
|
||||
}
|
||||
|
||||
/* Enter Image 1.5 */
|
||||
|
|
|
|||
|
|
@ -26,6 +26,15 @@ extern void xPortPendSVHandler(void);
|
|||
extern void xPortSysTickHandler(void);
|
||||
extern void vPortSVCHandler(void);
|
||||
extern void rtl_libc_init(void);
|
||||
extern _LONG_CALL_ void HalCpuClkConfig(unsigned char CpuType);
|
||||
extern void PSHalInitPlatformLogUart(void);
|
||||
extern _LONG_CALL_ void UartLogCmdExecute(PUART_LOG_CTL pUartLogCtlExe);
|
||||
extern void HalReInitPlatformTimer(void);
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
extern void En32KCalibration(void);
|
||||
extern void SdrCtrlInit(void);
|
||||
extern void InitSoCPM(void);
|
||||
extern u32 SdrControllerInit(void);
|
||||
//extern void ShowRamBuildInfo(void); // app_start.c: VOID ShowRamBuildInfo(VOID)
|
||||
//void HalNMIHandler_Patch(void);
|
||||
void SDIO_Device_Off(void);
|
||||
|
|
@ -97,7 +106,7 @@ __weak int main(void) {
|
|||
DiagPrintf("\r<RTL>");
|
||||
while (1) {
|
||||
while (pUartLogCtl->ExecuteCmd != 1);
|
||||
UartLogCmdExecute(pUartLogCtl);
|
||||
UartLogCmdExecute((PUART_LOG_CTL) pUartLogCtl);
|
||||
DiagPrintf("\r<RTL>");
|
||||
pUartLogCtl->ExecuteCmd = 0;
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -245,7 +245,6 @@ HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor)
|
|||
u32 IRQ_UNKNOWN = 999;
|
||||
u32 Ctrlr0Value = 0;
|
||||
u32 Ctrlr1Value = 0;
|
||||
u32 SerValue = 0;
|
||||
u32 BaudrValue = 0;
|
||||
u32 TxftlrValue = 0;
|
||||
u32 RxftlrValue = 0;
|
||||
|
|
@ -318,8 +317,7 @@ HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor)
|
|||
HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR1));
|
||||
}
|
||||
|
||||
SerValue = BIT_SER_SER(1 << (pHalSsiAdaptor->SlaveSelectEnable));
|
||||
SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_SER Value: %X\n", Index, SerValue);
|
||||
SSI_DBG_INIT("[1] Set SSI%d REG_DW_SSI_SER Value: %X\n", Index, BIT_SER_SER(1 << (pHalSsiAdaptor->SlaveSelectEnable)));
|
||||
|
||||
//HAL_SSI_WRITE32(Index, REG_DW_SSI_SER, SerValue);
|
||||
HalSsiSetSlaveEnableRegisterRtl8195a(Adaptor, pHalSsiAdaptor->SlaveSelectEnable);
|
||||
|
|
@ -617,7 +615,6 @@ HAL_Status HalSsiSetFormatRtl8195a(VOID *Adaptor)
|
|||
u32 RxftlrValue = 0;
|
||||
u8 Index = pHalSsiAdaptor->Index;
|
||||
u8 Role = pHalSsiAdaptor->Role;
|
||||
u32 Spi_mode = 0;
|
||||
|
||||
if (Index > 2) {
|
||||
DBG_SSI_ERR("HalSsiSetFormatRtl8195a: Invalid SSI Idx %d\r\n", Index);
|
||||
|
|
@ -639,10 +636,9 @@ HAL_Status HalSsiSetFormatRtl8195a(VOID *Adaptor)
|
|||
|
||||
HAL_SSI_WRITE32(Index, REG_DW_SSI_CTRLR0, Ctrlr0Value);
|
||||
|
||||
Spi_mode = (HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0) >>6) & 0x3;
|
||||
SSI_DBG_INIT("[2] SSI%d REG_DW_SSI_CTRLR0(%X) = %X, SPI Mode = %X\n", Index,
|
||||
SSI0_REG_BASE + (SSI_REG_OFF * Index) + REG_DW_SSI_CTRLR0,
|
||||
HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0), Spi_mode);
|
||||
HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0), (HAL_SSI_READ32(Index, REG_DW_SSI_CTRLR0) >>6) & 0x3);
|
||||
//The tx threshold and rx threshold value will be reset after the spi changes its role
|
||||
/* REG_DW_SSI_TXFTLR */
|
||||
TxftlrValue = BIT_TXFTLR_TFT(pHalSsiAdaptor->TxThresholdLevel);
|
||||
|
|
@ -741,7 +737,7 @@ HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length)
|
|||
{
|
||||
PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Adapter;
|
||||
u32 RxFifoThresholdLevel;
|
||||
u8 Index = pHalSsiAdapter->Index;
|
||||
// u8 Index = pHalSsiAdapter->Index;
|
||||
|
||||
DBG_SSI_INFO("HalSsiIntReadRtl8195a: Idx=%d, RxData=0x%x, Len=0x%x\r\n", Index, RxData, Length);
|
||||
// if (HalSsiBusyRtl8195a(Adapter)) {
|
||||
|
|
|
|||
|
|
@ -12,13 +12,14 @@
|
|||
#include "rtl8195a_uart.h"
|
||||
#include "hal_uart.h"
|
||||
#include "hal_gdma.h"
|
||||
#include "strproc.h"
|
||||
|
||||
u8
|
||||
HalRuartGetChipVerRtl8195a(VOID)
|
||||
{
|
||||
u8 chip_ver;
|
||||
|
||||
chip_ver = (HAL_READ32(SYSTEM_CTRL_BASE, 0x01F0) >> 4) & 0x0f;
|
||||
chip_ver = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSTEM_CFG0) >> 4) & 0x0f; // 0x400001F0 RTL8710AF = 0x41000220
|
||||
return chip_ver;
|
||||
}
|
||||
|
||||
|
|
@ -151,9 +152,8 @@ HalRuartGenBaudRateRtl8195a(
|
|||
u32 min_divisor=0;
|
||||
u32 min_err=0xffffffff;
|
||||
u32 uart_ovsr;
|
||||
u32 uart_ovsr_mod;
|
||||
u32 min_uart_ovsr; // ovsr with mini err
|
||||
u32 min_uart_ovsr_mod;
|
||||
u32 min_uart_ovsr = 0; // ovsr with mini err
|
||||
u32 min_uart_ovsr_mod = 0;
|
||||
u64 uart_clock;
|
||||
u32 divisor_temp;
|
||||
u32 max_jitter_temp;
|
||||
|
|
@ -200,7 +200,7 @@ HalRuartGenBaudRateRtl8195a(
|
|||
min_uart_ovsr = uart_ovsr/100;
|
||||
min_uart_ovsr_mod = uart_ovsr%100;
|
||||
} else if (err_temp == min_err) {
|
||||
uart_ovsr_mod = uart_ovsr%100;
|
||||
u32 uart_ovsr_mod = uart_ovsr%100;
|
||||
// we perfer OVSR bigger and adj bits smaller
|
||||
if (((uart_ovsr/100) >= min_uart_ovsr) && (uart_ovsr_mod < min_uart_ovsr_mod)) {
|
||||
min_err = err_temp;
|
||||
|
|
@ -369,7 +369,7 @@ HalRuartSetBaudRateRtl8195a(
|
|||
u8 chip_ver;
|
||||
|
||||
// get chip version
|
||||
chip_ver = HalRuartGetChipVerRtl8195a();
|
||||
chip_ver = HalRuartGetChipVerRtl8195a(); // RTL8710AF = 2
|
||||
#endif
|
||||
|
||||
if (pHalRuartAdapter->WordLen == RUART_WLS_8BITS) {
|
||||
|
|
@ -1248,7 +1248,7 @@ HalRuartMultiBlkDmaRecvRtl8195a(
|
|||
}
|
||||
|
||||
/**
|
||||
* Stop non-blocking UART RX
|
||||
* Stop non-blocking UART TX
|
||||
*
|
||||
*
|
||||
* @return VOID
|
||||
|
|
@ -1283,7 +1283,7 @@ HalRuartStopRecvRtl8195a_Patch(
|
|||
if (NULL != pUartGdmaConfig) {
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
PHAL_GDMA_OP pHalGdmaOp;
|
||||
u8 IsrTypeMap;
|
||||
|
||||
|
||||
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pRxHalGdmaAdapter;
|
||||
pHalGdmaOp = (PHAL_GDMA_OP)pUartGdmaConfig->pHalGdmaOp;
|
||||
|
|
@ -1293,7 +1293,8 @@ HalRuartStopRecvRtl8195a_Patch(
|
|||
// Clean Auto Reload Bit
|
||||
pHalGdmaOp->HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter);
|
||||
// Clear Pending ISR
|
||||
IsrTypeMap = pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
|
||||
// u8 IsrTypeMap =
|
||||
pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
|
||||
pHalGdmaOp->HalGdmaChDis((VOID*)(pHalGdmaAdapter));
|
||||
|
||||
DMA_Dar = HalGdmaQueryDArRtl8195a((VOID*)pHalGdmaAdapter);
|
||||
|
|
@ -1358,7 +1359,7 @@ HalRuartStopSendRtl8195a_Patch(
|
|||
if (NULL != pUartGdmaConfig) {
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
PHAL_GDMA_OP pHalGdmaOp;
|
||||
u8 IsrTypeMap;
|
||||
|
||||
|
||||
pHalGdmaAdapter = (PHAL_GDMA_ADAPTER)pUartGdmaConfig->pTxHalGdmaAdapter;
|
||||
pHalGdmaOp = (PHAL_GDMA_OP)pUartGdmaConfig->pHalGdmaOp;
|
||||
|
|
@ -1368,7 +1369,8 @@ HalRuartStopSendRtl8195a_Patch(
|
|||
// Clean Auto Reload Bit
|
||||
pHalGdmaOp->HalGdmaChCleanAutoDst((VOID*)pHalGdmaAdapter);
|
||||
// Clear Pending ISR
|
||||
IsrTypeMap = pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
|
||||
// u8 IsrTypeMap =
|
||||
pHalGdmaOp->HalGdmaChIsrClean((VOID*)pHalGdmaAdapter);
|
||||
pHalGdmaOp->HalGdmaChDis((VOID*)(pHalGdmaAdapter));
|
||||
|
||||
DMA_Sar = HalGdmaQuerySArRtl8195a((VOID*)pHalGdmaAdapter);
|
||||
|
|
|
|||
|
|
@ -1,54 +1,68 @@
|
|||
|
||||
#include "PinNames.h"
|
||||
#include "bitband_io.h"
|
||||
//#include "rtl8195a_gpio.h"
|
||||
|
||||
volatile u8 * BitBandAddr(void *addr, u8 bit) {
|
||||
return (volatile u8 *)(BITBAND_ADDR((u32)addr, bit));
|
||||
#define BITBAND_ADDR(a,b) (0x02000000 + (a & 0xF0000000) + (a - (a & 0xF0000000)) * 32 + ((b) * 4)) // Convert address ?
|
||||
|
||||
volatile uint8_t * BitBandAddr(void *addr, uint8_t bit) {
|
||||
uint32_t ret = BITBAND_ADDR((u32)addr, bit);
|
||||
return (volatile uint8_t *) ret;
|
||||
}
|
||||
|
||||
volatile u8 * BitBandPeriAddr(void *addr, u8 bit) {
|
||||
return (volatile u8 *)(BITBAND_PERI((u32)addr, bit));
|
||||
volatile uint8_t * BitBandPeriAddr(void *addr, uint8_t bit) {
|
||||
return (volatile uint8_t *)(BITBAND_PERI((u32)addr, bit));
|
||||
}
|
||||
|
||||
volatile u8 * GetOutPinBitBandAddr(PinName pin) {
|
||||
u32 paddr = NULL;
|
||||
u32 ippin = HAL_GPIO_GetIPPinName_8195a(pin);
|
||||
if(ippin != 0xff) {
|
||||
volatile uint8_t * GetOutPinBitBandAddr(PinName pin) {
|
||||
volatile uint8_t * paddr = 0;
|
||||
uint32_t ippin = HAL_GPIO_GetIPPinName_8195a(pin);
|
||||
if(ippin < 0xff) {
|
||||
// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
|
||||
paddr = BitBandPeriAddr((void *)(GPIO_REG_BASE + GPIO_PORTB_DR * (ippin >> 5)), ippin & 0x1f);
|
||||
}
|
||||
return paddr;
|
||||
}
|
||||
|
||||
volatile u8 * GetInPinBitBandAddr(PinName pin) {
|
||||
volatile u8 * paddr = NULL;
|
||||
u32 ippin = HAL_GPIO_GetIPPinName_8195a(pin);
|
||||
if(ippin != 0xff) {
|
||||
volatile uint8_t * GetInPinBitBandAddr(PinName pin) {
|
||||
volatile uint8_t * paddr = NULL;
|
||||
uint32_t ippin = HAL_GPIO_GetIPPinName_8195a(pin);
|
||||
if(ippin < 0xff) {
|
||||
// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
|
||||
paddr = BitBandPeriAddr((void *)(GPIO_REG_BASE + GPIO_EXT_PORTA + (ippin >> 5) * 4), ippin & 0x1f);
|
||||
}
|
||||
return paddr;
|
||||
}
|
||||
|
||||
volatile u8 * HardSetPin(PinName pin, PinDirection pdir, PinMode pmode, u8 val)
|
||||
extern _LONG_CALL_ u32 GPIO_FuncOn_8195a(VOID);
|
||||
extern void wait_us(int us);
|
||||
|
||||
volatile uint8_t * HardSetPin(PinName pin, HAL_GPIO_PIN_MODE pmode, uint8_t val)
|
||||
{
|
||||
volatile u8 *paddr = NULL;
|
||||
u32 ippin = HAL_GPIO_GetIPPinName_8195a(pin);
|
||||
if(ippin != 0xff) {
|
||||
volatile uint8_t *paddr = NULL;
|
||||
uint32_t ippin = HAL_GPIO_GetIPPinName_8195a(pin);
|
||||
if(ippin < 0xff) {
|
||||
if(_pHAL_Gpio_Adapter == NULL) {
|
||||
extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
|
||||
_pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
|
||||
}
|
||||
if(_pHAL_Gpio_Adapter->Gpio_Func_En == 0) GPIO_FuncOn_8195a();
|
||||
wait_us(100);
|
||||
// delayMicroseconds(100);
|
||||
// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
|
||||
#if CONFIG_DEBUG_LOG > 3
|
||||
GpioFunctionChk(ippin, ENABLE);
|
||||
#endif
|
||||
GPIO_PullCtrl_8195a(ippin, HAL_GPIO_HIGHZ); // Make the pin pull control default as High-Z
|
||||
paddr = BitBandPeriAddr((void *)(GPIO_REG_BASE + GPIO_PORTB_DR * (ippin >> 5)), ippin & 0x1f);
|
||||
}
|
||||
if(paddr && _pHAL_Gpio_Adapter) {
|
||||
if (_pHAL_Gpio_Adapter->Gpio_Func_En == 0) GPIO_FuncOn_8195a();
|
||||
paddr[0] = val; // data register
|
||||
paddr[(GPIO_PORTB_DDR - GPIO_PORTB_DR) * 32] = pdir; // data direction
|
||||
#if 1 // if use HAL_Gpio_Adapter
|
||||
uint32 * p = &_pHAL_Gpio_Adapter->Local_Gpio_Dir[ippin >> 5];
|
||||
if(pdir) *p |= 1 << (ippin & 0x1f);
|
||||
else *p &= ~(1 << (ippin & 0x1f));
|
||||
#endif
|
||||
paddr[(GPIO_PORTB_CTRL - GPIO_PORTB_DR) * 32] = 0; // data source control, we should keep it as default: data source from software
|
||||
HAL_GPIO_PullCtrl_8195a(pin, pmode); // set GPIO_PULL_CTRLx
|
||||
*paddr = val; // data register
|
||||
HAL_GPIO_PIN gpio;
|
||||
gpio.pin_name = ippin;
|
||||
gpio.pin_mode = pmode;
|
||||
HAL_GPIO_Init_8195a(&gpio);
|
||||
*paddr = val; // data register
|
||||
// paddr[(GPIO_PORTB_DDR - GPIO_PORTB_DR) * 32] = pmode == DOUT_PUSH_PULL; // data direction
|
||||
// GPIO_PullCtrl_8195a(ippin, pmode); // set GPIO_PULL_CTRLx
|
||||
// paddr[(GPIO_PORTB_CTRL - GPIO_PORTB_DR) * 32] = 0; // data source control, we should keep it as default: data source from software
|
||||
}
|
||||
return paddr;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -533,16 +533,16 @@ ADCISRHandle(
|
|||
PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL;
|
||||
PHAL_ADC_INIT_DAT pHalADCInitDat = NULL;
|
||||
PHAL_ADC_OP pHalADCOP = NULL;
|
||||
PSAL_ADC_USER_CB pSalADCUserCB = NULL;
|
||||
u8 ADCIrqIdx;
|
||||
// PSAL_ADC_USER_CB pSalADCUserCB = NULL;
|
||||
// u8 ADCIrqIdx;
|
||||
|
||||
/* To get the SAL_I2C_MNGT_ADPT pointer, and parse the rest pointers */
|
||||
pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv);
|
||||
pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv);
|
||||
pHalADCInitDat = pSalADCMngtAdpt->pHalInitDat;
|
||||
pHalADCOP = pSalADCMngtAdpt->pHalOp;
|
||||
ADCIrqIdx = pHalADCInitDat->ADCIdx;
|
||||
pSalADCUserCB = pSalADCHND->pUserCB;
|
||||
// ADCIrqIdx = pHalADCInitDat->ADCIdx;
|
||||
// pSalADCUserCB = pSalADCHND->pUserCB;
|
||||
|
||||
DBG_8195A_ADC_LVL(HAL_ADC_LVL,"ADC INTR STS:%x\n",pHalADCOP->HalADCReadReg(pHalADCInitDat, REG_ADC_INTR_STS));
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ void HalReInitPlatformTimer(void)
|
|||
TimerAdapter.IrqDis = 1;
|
||||
TimerAdapter.TimerId = 1;
|
||||
HalTimerOpInit_Patch(&HalTimerOp);
|
||||
HAL_TIMER_OP x;
|
||||
// HAL_TIMER_OP x;
|
||||
HalTimerOp.HalTimerInit(&TimerAdapter);
|
||||
HalTimerOp.HalTimerEn(1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -150,11 +150,13 @@ unsigned int rand_x = 123456789;
|
|||
*/
|
||||
#ifdef CONFIG_SDR_EN
|
||||
|
||||
#ifndef __GNUC__
|
||||
//#pragma arm section code = ".hal.sdrc.text"
|
||||
#pragma arm section rodata = ".rodata.hal.sdrc"
|
||||
//, rwdata = ".hal.sdrc.data"
|
||||
//, zidata = ".hal.sdrc.bss"
|
||||
//#pragma arm section bss = ".hal.sdrc.bss"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDR_VERIFY
|
||||
enum{
|
||||
|
|
@ -448,13 +450,10 @@ DramInit (
|
|||
u32 CrTwr, DramMaxWr, DramWr;
|
||||
u32 CrTrtw = 0, CrTrtwT = 0;
|
||||
u32 DrmaPeriod;
|
||||
DRAM_TYPE DdrType;
|
||||
DRAM_TYPE DdrType = DRAM_SDR;
|
||||
DRAM_DQ_WIDTH DqWidth;
|
||||
DRAM_COLADDR_WTH Page;
|
||||
u32 DfiRate;
|
||||
volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
|
||||
ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
|
||||
// ms_ctrl_0_map = ms_ctrl_0_map;
|
||||
|
||||
DfiRate = 1 << (u32) (DramInfo->DfiRate);
|
||||
DrmaPeriod = (DramInfo->DdrPeriodPs)*(DfiRate); // according DFI_RATE to setting
|
||||
|
|
@ -658,6 +657,9 @@ DramInit (
|
|||
// enter mem_mode
|
||||
HAL_SDR_WRITE32(REG_SDR_CSR,0x600);
|
||||
#else
|
||||
volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
|
||||
ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
|
||||
// ms_ctrl_0_map = ms_ctrl_0_map;
|
||||
// WRAP_MISC setting
|
||||
ms_ctrl_0_map->misc = //0x12;
|
||||
(
|
||||
|
|
@ -753,7 +755,8 @@ SdrCalibration(
|
|||
DBG_8195A("%s()\n", __func__);
|
||||
u32 RdPipe = 0, TapCnt = 0, Pass = 0, AvaWdsCnt = 0;
|
||||
u32 RdPipeCounter, RecNum[2], RecRdPipe[2];//, AvaWds[2][REC_NUM];
|
||||
BOOL RdPipeFlag, PassFlag = 0, Result;
|
||||
BOOL RdPipeFlag, Result;
|
||||
// BOOL PassFlag = 0;
|
||||
u8 flashtype = 0;
|
||||
|
||||
flashtype = SpicInitParaAllClk[0][0].flashtype;
|
||||
|
|
@ -829,7 +832,7 @@ SdrCalibration(
|
|||
#endif
|
||||
|
||||
RdPipeFlag = _FALSE;
|
||||
PassFlag = _FALSE;
|
||||
// PassFlag = _FALSE;
|
||||
AvaWdsCnt = 0;
|
||||
|
||||
for(TapCnt=0; TapCnt < (MAX_TAP_DLY+1); TapCnt++) {
|
||||
|
|
@ -853,7 +856,7 @@ SdrCalibration(
|
|||
#endif
|
||||
|
||||
Pass = MemTest(10000);
|
||||
PassFlag = _FALSE;
|
||||
// PassFlag = _FALSE;
|
||||
|
||||
if(Pass==_TRUE) { // PASS
|
||||
|
||||
|
|
@ -876,7 +879,7 @@ SdrCalibration(
|
|||
break;
|
||||
}
|
||||
|
||||
PassFlag = _TRUE;
|
||||
// PassFlag = _TRUE;
|
||||
|
||||
DBG_SDR_INFO("Verify Pass => RdPipe:%d; TapCnt: %d\n", RdPipe, TapCnt);
|
||||
|
||||
|
|
@ -1044,7 +1047,7 @@ Sdr_Rand2(
|
|||
}
|
||||
|
||||
*/
|
||||
|
||||
extern __attribute__ ((long_call)) unsigned int Rand(void);
|
||||
HAL_SDRC_TEXT_SECTION
|
||||
s32
|
||||
MemTest(
|
||||
|
|
|
|||
|
|
@ -373,6 +373,7 @@ WakeFromSLPPG(
|
|||
);
|
||||
}
|
||||
|
||||
// Предел 8355 ms!
|
||||
VOID
|
||||
DurationScaleAndPeriodOP(
|
||||
IN u32 SDuration,
|
||||
|
|
@ -412,7 +413,7 @@ CLKCal(
|
|||
u32 Rtemp = 0;
|
||||
u32 RRTemp = 0;
|
||||
|
||||
u32 x = (HAL_READ32(PERI_ON_BASE,REG_SYS_CLK_CTRL1) >> BIT_SHIFT_PESOC_OCP_CPU_CK_SEL) & BIT_MASK_PESOC_OCP_CPU_CK_SEL;
|
||||
u32 x = (HAL_READ32(PERI_ON_BASE, REG_SYS_CLK_CTRL1) >> BIT_SHIFT_PESOC_OCP_CPU_CK_SEL) & BIT_MASK_PESOC_OCP_CPU_CK_SEL;
|
||||
|
||||
if( ClkSel ){
|
||||
//a33_ck
|
||||
|
|
@ -432,7 +433,8 @@ CLKCal(
|
|||
}
|
||||
else {
|
||||
//anack
|
||||
RRTemp = (((2133/Rtemp) >> x) - 1);
|
||||
//pvvx: eror RTL8710AF? RRTemp = (((2133/Rtemp) >> x) - 1);
|
||||
RRTemp = (2133/Rtemp) - 1;
|
||||
}
|
||||
if ( x == 5 )
|
||||
DiagPrintf("Using ana to cal is not allowed!\n");
|
||||
|
|
@ -516,7 +518,7 @@ SleepClkGatted(
|
|||
|
||||
//3 1.5 Enable low power mode
|
||||
// 1.5.1 0x4000_0118[2] = 1 => for sleep mode
|
||||
Rtemp = 0x00000004;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000004;
|
||||
Rtemp = BIT_SYSON_PM_CMD_SLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000004;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//3 1.6 Wait CHIP enter low power mode
|
||||
|
|
@ -535,7 +537,7 @@ VOID SleepPwrGatted(
|
|||
u32 Rtemp = 0;
|
||||
u32 ScaleTemp = 0;
|
||||
u32 PeriodTemp = 0;
|
||||
u32 CalTemp = 0;
|
||||
// u32 CalTemp = 0;
|
||||
|
||||
//Backup CPU CLK
|
||||
BackupCPUClk();
|
||||
|
|
@ -547,7 +549,7 @@ VOID SleepPwrGatted(
|
|||
//3 1.1 Set TU timer timescale
|
||||
//0x4000_0090[21:16] = 6'h1F
|
||||
//0x4000_0090[15] = 1'b0 => Disable timer
|
||||
CalTemp = (CLKCal(ANACK) << 16);
|
||||
// CalTemp = (CLKCal(ANACK) << 16);
|
||||
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL)
|
||||
& (~((BIT_MASK_SYS_DSTDY_TIM_SCAL << BIT_SHIFT_SYS_DSTDY_TIM_SCAL) | (BIT_MASK_SYS_ANACK_TU_TIME << BIT_SHIFT_SYS_ANACK_TU_TIME))))
|
||||
| ScaleTemp;
|
||||
|
|
@ -580,7 +582,7 @@ VOID SleepPwrGatted(
|
|||
|
||||
//3 1.5 Enable low power mode
|
||||
// 1.5.1 0x4000_0118[2] = 1 => for sleep mode
|
||||
Rtemp = 0x00000004;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000004;
|
||||
Rtemp = BIT_SYSON_PM_CMD_SLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000004;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//3 1.6 Wait CHIP enter low power mode
|
||||
|
|
@ -602,7 +604,7 @@ DStandby(
|
|||
u32 Rtemp = 0;
|
||||
u32 ScaleTemp = 0;
|
||||
u32 PeriodTemp = 0;
|
||||
u32 CalTemp = 0;
|
||||
// u32 CalTemp = 0;
|
||||
|
||||
//Backup CPU CLK
|
||||
BackupCPUClk();
|
||||
|
|
@ -615,7 +617,7 @@ DStandby(
|
|||
//3 1.1 Set TU timer timescale
|
||||
//0x4000_0090[21:16] = 6'h1F
|
||||
//0x4000_0090[15] = 1'b0 => Disable timer
|
||||
CalTemp = (CLKCal(ANACK) << 16);
|
||||
// CalTemp = (CLKCal(ANACK) << 16);
|
||||
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL)
|
||||
& (~((BIT_MASK_SYS_DSTDY_TIM_SCAL << BIT_SHIFT_SYS_DSTDY_TIM_SCAL) | (BIT_MASK_SYS_ANACK_TU_TIME << BIT_SHIFT_SYS_ANACK_TU_TIME))))
|
||||
| ScaleTemp;
|
||||
|
|
@ -648,7 +650,7 @@ DStandby(
|
|||
|
||||
//3 1.5 Enable low power mode
|
||||
// [0x4000_0118[1] = 1 => for deep standby mode]
|
||||
Rtemp = 0x00000002;
|
||||
Rtemp = BIT_SYSON_PM_CMD_DSTBY;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//3 1.6 Wait CHIP enter low power mode
|
||||
|
|
@ -672,8 +674,6 @@ DSleep(
|
|||
//u32 PeriodTemp = 0;
|
||||
u32 UTemp = 0;
|
||||
u32 MaxTemp = 0;
|
||||
|
||||
u32 Reada335 = 0;
|
||||
|
||||
//2 Deep Sleep mode:
|
||||
//3 2.1 Set TU timer timescale
|
||||
|
|
@ -724,16 +724,15 @@ DSleep(
|
|||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL, Rtemp);
|
||||
|
||||
HalDelayUs(1000);
|
||||
Reada335 = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CAL_CTRL);
|
||||
#if CONFIG_DEBUG_LOG > 3
|
||||
DiagPrintf("a33 timer : 0x%x\n", Reada335);
|
||||
DiagPrintf("a33 timer : 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CAL_CTRL));
|
||||
#endif
|
||||
|
||||
HalDelayUs(8000);
|
||||
|
||||
//3 2.2.3
|
||||
//2.3 Enable low power mode: 0x4000_0118[0] = 1'b1;
|
||||
Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
Rtemp = BIT_SYSON_PM_CMD_DSLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//2.4 Wait CHIP enter deep sleep mode
|
||||
|
|
@ -1418,6 +1417,9 @@ SetSYSTimer(
|
|||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp);
|
||||
}
|
||||
|
||||
/*
|
||||
* SDuration < 8355 ms!
|
||||
*/
|
||||
VOID
|
||||
SleepCG(
|
||||
IN u8 Option,
|
||||
|
|
@ -1446,7 +1448,8 @@ SleepCG(
|
|||
Rtemp = 0x74003B00; //0x74003900;
|
||||
}
|
||||
else {
|
||||
Rtemp = 0x74000900;
|
||||
Rtemp = 0x74000900; // BIT_SYSON_PMOPT_NORM_XTAL_EN | BIT_SYSON_PMOPT_NORM_SYSPLL_EN | BIT_SYSON_PMOPT_NORM_SYSCLK_SEL | BIT_SYSON_PMOPT_NORM_EN_PWM
|
||||
// | BIT_SYSON_PMOPT_SLP_LPLDO_SEL | BIT_SYSON_PMOPT_SLP_EN_SOC
|
||||
}
|
||||
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp);
|
||||
|
|
@ -1465,49 +1468,49 @@ SleepCG(
|
|||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp);
|
||||
|
||||
//Enable wake event
|
||||
WakeEvent |= BIT0;
|
||||
WakeEvent |= BIT0; // BIT_SYSON_WEVT_SYSTIM_MSK
|
||||
}
|
||||
|
||||
if (Option & SLP_GTIMER) {
|
||||
|
||||
//Enable wake event
|
||||
WakeEvent |= BIT1;
|
||||
WakeEvent |= BIT1; // BIT_SYSON_WEVT_GTIM_MSK
|
||||
}
|
||||
|
||||
if (Option & SLP_GPIO) {
|
||||
|
||||
//Enable wake event
|
||||
WakeEvent |= BIT4;
|
||||
WakeEvent |= BIT4; // BIT_SYSON_WEVT_GPIO_MSK
|
||||
}
|
||||
|
||||
if (Option & SLP_WL) {
|
||||
|
||||
//Enable wake event
|
||||
WakeEvent |= BIT8;
|
||||
WakeEvent |= BIT8; // BIT_SYSON_WEVT_WLAN_MSK
|
||||
}
|
||||
|
||||
if (Option & SLP_NFC) {
|
||||
|
||||
//Enable wake event
|
||||
WakeEvent |= BIT28;
|
||||
WakeEvent |= BIT28; // BIT_SYSON_WEVT_A33_MSK
|
||||
}
|
||||
|
||||
if (Option & SLP_SDIO) {
|
||||
|
||||
//Enable wake event
|
||||
WakeEvent |= BIT14;
|
||||
WakeEvent |= BIT14; // BIT_SYSON_WEVT_SDIO_MSK
|
||||
}
|
||||
|
||||
if (Option & SLP_USB) {
|
||||
|
||||
//Enable wake event
|
||||
//WakeEvent |= BIT16;
|
||||
//WakeEvent |= BIT16; // BIT_SYSON_WEVT_USB_MSK
|
||||
}
|
||||
|
||||
if (Option & SLP_TIMER33) {
|
||||
|
||||
//Enable wake event
|
||||
WakeEvent |= BIT28;
|
||||
WakeEvent |= BIT28; // BIT_SYSON_WEVT_A33_MSK
|
||||
}
|
||||
/*
|
||||
while(1) {
|
||||
|
|
@ -1533,7 +1536,7 @@ SleepCG(
|
|||
if (SDREn) SDRSleep();
|
||||
#endif
|
||||
|
||||
Rtemp = 0x00000004;
|
||||
Rtemp = BIT_SYSON_PM_CMD_SLP;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//3 Wait CHIP enter low power mode
|
||||
|
|
@ -1565,7 +1568,7 @@ SleepPG(
|
|||
|
||||
//3 2 Configure power state option:
|
||||
// 2.1 power mode option:
|
||||
Rtemp = 0x74000100;
|
||||
Rtemp = 0x74000100; // BIT_SYSON_PMOPT_SLP_LPLDO_SEL
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp);
|
||||
|
||||
// 2.2 sleep power mode option1
|
||||
|
|
@ -1648,7 +1651,7 @@ SleepPG(
|
|||
LDO25M_CTRL(OFF);
|
||||
#endif
|
||||
|
||||
Rtemp = 0x00000004;
|
||||
Rtemp = BIT_SYSON_PM_CMD_SLP;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//3 Wait CHIP enter low power mode
|
||||
|
|
@ -1701,7 +1704,7 @@ DeepStandby(
|
|||
|
||||
//3 2 Configure power state option:
|
||||
// 2.1 deep standby power mode option:
|
||||
Rtemp = 0x74000100;
|
||||
Rtemp = 0x74000100; // BIT_SYSON_PMOPT_SLP_LPLDO_SEL
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp);
|
||||
|
||||
// 2.2 sleep power mode option1
|
||||
|
|
@ -1737,19 +1740,19 @@ DeepStandby(
|
|||
|
||||
if (Option & DSTBY_GPIO){
|
||||
|
||||
if (GpioOption & BIT0) {
|
||||
if (GpioOption & BIT0) { // PA_5
|
||||
DSTBYGpioCtrl(BIT0, (GpioOption & BIT4));
|
||||
}
|
||||
|
||||
if (GpioOption & BIT1) {
|
||||
if (GpioOption & BIT1) { // PC_7
|
||||
DSTBYGpioCtrl(BIT1, (GpioOption & BIT5));
|
||||
}
|
||||
|
||||
if (GpioOption & BIT2) {
|
||||
if (GpioOption & BIT2) { // PD_5
|
||||
DSTBYGpioCtrl(BIT2, (GpioOption & BIT6));
|
||||
}
|
||||
|
||||
if (GpioOption & BIT3) {
|
||||
if (GpioOption & BIT3) { // PE_3
|
||||
DSTBYGpioCtrl(BIT3, (GpioOption & BIT7));
|
||||
}
|
||||
|
||||
|
|
@ -1773,10 +1776,10 @@ DeepStandby(
|
|||
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_GPIO_SHTDN_CTRL, 0x0);
|
||||
|
||||
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) & 0xBFFFFFFF);
|
||||
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) & (~BIT_SYS_PWRON_TRAP_SHTDN_N)); // 0xBFFFFFFF, ~BIT(30)
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN, Rtemp);
|
||||
|
||||
Rtemp = 0x00000002;
|
||||
Rtemp = BIT_SYSON_PM_CMD_DSTBY;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//3 Wait CHIP enter low power mode
|
||||
|
|
@ -1799,7 +1802,7 @@ DeepSleep(
|
|||
u32 UTemp = 0;
|
||||
u32 MaxTemp = 0;
|
||||
|
||||
//??? HAL_WRITE32(0x60008000, 0x80006180, PS_MASK);
|
||||
HAL_WRITE32(0x60008000, 0x80006180, PS_MASK);
|
||||
|
||||
//1.1.1 Enable REGU access interface 0x4000_0094[31] = 1
|
||||
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_DSLP_TIM_CTRL) | 0x80000000);
|
||||
|
|
@ -1885,7 +1888,7 @@ DeepSleep(
|
|||
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) & 0xBFFFFFFF);
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN, Rtemp);
|
||||
|
||||
Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
Rtemp = BIT_SYSON_PM_CMD_DSLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//2.4 Wait CHIP enter deep sleep mode
|
||||
|
|
@ -1916,7 +1919,7 @@ DSleep_GPIO(
|
|||
|
||||
//2.2.2
|
||||
//2.3 Enable low power mode: 0x4000_0118[0] = 1'b1;
|
||||
Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
Rtemp = BIT_SYSON_PM_CMD_DSLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//2.4 Wait CHIP enter deep sleep mode
|
||||
|
|
@ -1989,7 +1992,7 @@ DSleep_Timer(
|
|||
|
||||
//3 2.3
|
||||
//2.3 Enable low power mode: 0x4000_0118[0] = 1'b1;
|
||||
Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
Rtemp = BIT_SYSON_PM_CMD_DSLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
|
||||
|
||||
//2.4 Wait CHIP enter deep sleep mode
|
||||
|
|
|
|||
|
|
@ -527,7 +527,7 @@ HalSsiInit(VOID *Data)
|
|||
{
|
||||
HAL_Status ret;
|
||||
PHAL_SSI_ADAPTOR pHalSsiAdapter = (PHAL_SSI_ADAPTOR) Data;
|
||||
u32 Function;
|
||||
u32 Function = SPI0;
|
||||
u8 PinmuxSelect;
|
||||
u8 Index;
|
||||
|
||||
|
|
|
|||
|
|
@ -1021,7 +1021,7 @@ HalRuartDmaSend(
|
|||
u32 BlockSize;
|
||||
HAL_Status ret;
|
||||
PUART_DMA_CONFIG pUartGdmaConfig;
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
// PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
|
||||
if (((Length & 0x03)==0) &&
|
||||
(((u32)(pTxBuf) & 0x03)==0)) {
|
||||
|
|
@ -1078,7 +1078,7 @@ HalRuartDmaRecv(
|
|||
// u32 BlockSize;
|
||||
HAL_Status ret;
|
||||
PUART_DMA_CONFIG pUartGdmaConfig;
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
// PHAL_GDMA_ADAPTER pHalGdmaAdapter;
|
||||
|
||||
if (Length < 4096) {
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include "rtl8195a.h"
|
||||
#include "rtl_bios_data.h"
|
||||
#include "osdep_api.h"
|
||||
#include "osdep_service.h"
|
||||
#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1)
|
||||
#include "freertos_pmu.h"
|
||||
#else
|
||||
|
|
@ -44,7 +45,7 @@ IN u8 EchoFlag);
|
|||
//_LONG_CALL_ extern void UartLogCmdExecute(IN PUART_LOG_CTL pUartLogCtlExe);
|
||||
//======================================================
|
||||
extern PCOMMAND_TABLE UartLogRamCmdTable[];
|
||||
extern UartLogRamCmdTableSize;
|
||||
extern int UartLogRamCmdTableSize;
|
||||
//======================================================
|
||||
//<Function>: UartLogIrqHandleRam
|
||||
//<Usage >: To deal with Uart-Log RX IRQ
|
||||
|
|
@ -61,7 +62,7 @@ void UartLogIrqHandleRam(void * Data) {
|
|||
if (UartReceiveData == 0) {
|
||||
goto exit;
|
||||
}
|
||||
PUART_LOG_CTL p = pUartLogCtl;
|
||||
PUART_LOG_CTL p = (PUART_LOG_CTL) pUartLogCtl;
|
||||
//KB_ESC chk is for cmd history, it's a special case here.
|
||||
if (UartReceiveData == KB_ASCII_ESC) {
|
||||
// Esc detection is only valid in the first stage of boot sequence (few seconds)
|
||||
|
|
@ -102,7 +103,7 @@ void UartLogIrqHandleRam(void * Data) {
|
|||
if (p->pTmpLogBuf != NULL) {
|
||||
p->ExecuteCmd = _TRUE;
|
||||
if (p->TaskRdy) {
|
||||
RtlUpSemaFromISR((_Sema *) &pUartLogCtl->Sema);
|
||||
rtw_up_sema_from_isr((_Sema *) &pUartLogCtl->Sema);
|
||||
}
|
||||
} else {
|
||||
ArrayInitialize((u8 *) pUartLogCtl->pTmpLogBuf->UARTLogBuf,
|
||||
|
|
@ -130,7 +131,7 @@ int GetArgvRam(IN u8 *pstr, u8** argv) {
|
|||
int arvc = 0;
|
||||
// u8** argv = ArgvArray;
|
||||
u8* p = pstr;
|
||||
u8 t, n = ' ';
|
||||
u8 t = 0, n = ' ';
|
||||
int m = 0;
|
||||
while(*p != 0
|
||||
&& *p != '\r'
|
||||
|
|
@ -200,7 +201,7 @@ int GetArgvRam(IN u8 *pstr, u8** argv) {
|
|||
//<Notes >:
|
||||
//======================================================
|
||||
MON_RAM_TEXT_SECTION void RtlConsolTaskRam(void *Data) {
|
||||
PUART_LOG_CTL p = pUartLogCtl;
|
||||
PUART_LOG_CTL p = (PUART_LOG_CTL) pUartLogCtl;
|
||||
#ifdef USE_ROM_CONSOLE // show Help
|
||||
p->pTmpLogBuf->UARTLogBuf[0] = '?';
|
||||
p->pTmpLogBuf->BufCount = 1;
|
||||
|
|
@ -208,7 +209,7 @@ MON_RAM_TEXT_SECTION void RtlConsolTaskRam(void *Data) {
|
|||
#endif
|
||||
do {
|
||||
p->TaskRdy = _TRUE;
|
||||
RtlDownSema(&p->Sema);
|
||||
rtw_down_sema(&p->Sema);
|
||||
if (p->ExecuteCmd) {
|
||||
// UartLogCmdExecute(pUartLogCtl);
|
||||
int argc = GetArgvRam(p->pTmpLogBuf->UARTLogBuf, ArgvArray);
|
||||
|
|
@ -225,9 +226,9 @@ MON_RAM_TEXT_SECTION void RtlConsolTaskRam(void *Data) {
|
|||
flg = 0;
|
||||
if(pcmd->ArgvCnt < argc) {
|
||||
#ifdef USE_ROM_CONSOLE
|
||||
pcmd->func(argc-1, &ArgvArray[1]);
|
||||
pcmd->func(argc-1, (char **) &ArgvArray[1]);
|
||||
#else
|
||||
pcmd->func(argc, &ArgvArray);
|
||||
pcmd->func(argc, (char **) &ArgvArray);
|
||||
#endif
|
||||
} else {
|
||||
#ifdef USE_ROM_CONSOLE
|
||||
|
|
@ -291,7 +292,7 @@ MON_RAM_TEXT_SECTION void console_init(void) {
|
|||
#endif
|
||||
pUartLogCtl->RevdNo = UART_LOG_HISTORY_LEN;
|
||||
// Create a Semaphone
|
||||
RtlInitSema(&pUartLogCtl->Sema, 1);
|
||||
rtw_init_sema((_sema *)&pUartLogCtl->Sema, 1);
|
||||
// executing boot sequence
|
||||
pUartLogCtl->ExecuteCmd = _FALSE;
|
||||
pUartLogCtl->ExecuteEsc = _TRUE; //don't check Esc anymore
|
||||
|
|
@ -316,7 +317,7 @@ extern char str_rom_57ch3Dch0A[]; // "==========================================
|
|||
_WEAK void console_help(int argc, char *argv[]) { // Help
|
||||
DiagPrintf("CONSOLE COMMAND SET:\n");
|
||||
DiagPrintf(&str_rom_57ch3Dch0A[25]); // DiagPrintf("==============================\n");
|
||||
PCOMMAND_TABLE pcmdtab = UartLogRamCmdTable;
|
||||
PCOMMAND_TABLE pcmdtab = (PCOMMAND_TABLE) UartLogRamCmdTable;
|
||||
while(pcmdtab->cmd) {
|
||||
#ifdef USE_ROM_CONSOLE
|
||||
DiagPrintf(pcmdtab->msg);
|
||||
|
|
@ -327,7 +328,8 @@ _WEAK void console_help(int argc, char *argv[]) { // Help
|
|||
}
|
||||
DiagPrintf(&str_rom_57ch3Dch0A[25]); // DiagPrintf("==============================\n");
|
||||
}
|
||||
LOCAL void print_on(int argc, char *argv[])
|
||||
|
||||
void print_on(int argc, char *argv[])
|
||||
{
|
||||
print_off = argv[1][0]!='1';
|
||||
}
|
||||
|
|
|
|||
|
|
@ -105,6 +105,22 @@ extern _LONG_CALL_ double __rtl_dsub_v1_00(double a, double b);
|
|||
extern _LONG_CALL_ double __rtl_dmul_v1_00(double a, double b);
|
||||
extern _LONG_CALL_ double __rtl_ddiv_v1_00(double a, double b);
|
||||
|
||||
// --- ???
|
||||
extern _LONG_CALL_ float __rtl_dtof_v1_00(double d);
|
||||
extern _LONG_CALL_ int __rtl_dtoui_v1_00(double d);
|
||||
extern _LONG_CALL_ float __rtl_itof_v1_00(int val);
|
||||
extern _LONG_CALL_ char *__rtl_ltoa_v1_00(int value, char *string, int radix);
|
||||
extern _LONG_CALL_ char *__rtl_ultoa_v1_00(unsigned int value, char *string, int radix);
|
||||
extern _LONG_CALL_ int __rtl_ftol_v1_00(float f);
|
||||
extern _LONG_CALL_ int __rtl_ftod_v1_00(float f);
|
||||
extern _LONG_CALL_ float __rtl_fadd_v1_00(float a, float b);
|
||||
extern _LONG_CALL_ float __rtl_fsub_v1_00(float a, float b);
|
||||
extern _LONG_CALL_ float __rtl_fmul_v1_00(float a, float b);
|
||||
extern _LONG_CALL_ float __rtl_fdiv_v1_00(float a, float b);
|
||||
extern _LONG_CALL_ int __rtl_dcmple_v1_00(double a, double b);
|
||||
extern _LONG_CALL_ int __rtl_fcmplt_v1_00(float a, float b);
|
||||
extern _LONG_CALL_ int __rtl_fcmpgt_v1_00(float a, float b);
|
||||
// --- ???
|
||||
|
||||
//
|
||||
// mprec
|
||||
|
|
|
|||
|
|
@ -22,7 +22,9 @@
|
|||
#define strsep __rtl_strsep_v1_00
|
||||
#define strtok __rtl_strtok_v1_00
|
||||
|
||||
static char toupper(char ch) {
|
||||
extern int isdigit (int c);
|
||||
|
||||
static int toupper(int ch) {
|
||||
return ((ch >= 'a' && ch <= 'z') ? ch - 'a' + 'A' : ch);
|
||||
};
|
||||
|
||||
|
|
@ -371,7 +373,7 @@ llatob(u_quad_t *vp, char *p, int base)
|
|||
char *
|
||||
btoa(char *dst, u_int value, int base)
|
||||
{
|
||||
char buf[34], digit;
|
||||
char buf[34], digit = 0;
|
||||
int i, j, rem, neg;
|
||||
|
||||
if (value == 0) {
|
||||
|
|
@ -417,7 +419,7 @@ btoa(char *dst, u_int value, int base)
|
|||
char *
|
||||
llbtoa(char *dst, u_quad_t value, int base)
|
||||
{
|
||||
char buf[66], digit;
|
||||
char buf[66], digit = 0;
|
||||
int i, j, rem, neg;
|
||||
|
||||
if (value == 0) {
|
||||
|
|
@ -536,7 +538,7 @@ c_vsprintf (char *d, const char *s, va_list ap)
|
|||
const char *t;
|
||||
char *p, *dst, tmp[40];
|
||||
unsigned int n;
|
||||
int fmt, trunc, haddot, width, base, longlong;
|
||||
int fmt, trunc, haddot, width, base = 0, longlong;
|
||||
double dbl;
|
||||
#ifndef NEWFP
|
||||
EP ex;
|
||||
|
|
@ -1072,11 +1074,14 @@ int c_printf(const char *fmt, ...)
|
|||
|
||||
#endif // ENAC_FLOAT
|
||||
|
||||
extern _LONG_CALL_ROM_ void HalSerialPutcRtl8195a(char c);
|
||||
|
||||
int puts (const char *s)
|
||||
{
|
||||
while(*s) {
|
||||
HalSerialPutcRtl8195a(*s++);
|
||||
}
|
||||
return 0; // -1 -> EOF
|
||||
}
|
||||
|
||||
void vTaskDelete(void *);
|
||||
|
|
|
|||
|
|
@ -170,7 +170,6 @@ int rtl_vprintf(const char *fmt, va_list param) {
|
|||
int rtl_vsnprintf(char *str, size_t size, const char *fmt, va_list param) {
|
||||
int result;
|
||||
int w;
|
||||
int v11;
|
||||
FILE f;
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
|
|
|
|||
|
|
@ -122,6 +122,6 @@ void init_rom_libgloss_ram_map(void) {
|
|||
rom_libgloss_ram_map.libgloss_open = ram_libgloss_open;
|
||||
rom_libgloss_ram_map.libgloss_read = ram_libgloss_read;
|
||||
rom_libgloss_ram_map.libgloss_write = ram_libgloss_write;
|
||||
rom_libgloss_ram_map.libgloss_sbrk = ram_libgloss_sbrk;
|
||||
rom_libgloss_ram_map.libgloss_sbrk = (void*)ram_libgloss_sbrk;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -67,9 +67,12 @@ unsigned long long __aeabi_llsr(unsigned long long val, unsigned int shift);
|
|||
|
||||
extern struct _reent * _rtl_impure_ptr;
|
||||
|
||||
#if CHECK_LIBC_INIT
|
||||
extern char libc_has_init;
|
||||
#endif
|
||||
extern char print_off;
|
||||
|
||||
#undef snprintf
|
||||
//-------------------------------------------------------------------------
|
||||
// Function
|
||||
//----- snprintf()
|
||||
|
|
@ -107,7 +110,9 @@ int snprintf(char *str, size_t size, const char *fmt, ...) {
|
|||
return result;
|
||||
}
|
||||
|
||||
|
||||
#ifndef ENAC_FLOAT
|
||||
#undef sprintf
|
||||
//----- sprintf()
|
||||
int sprintf(char *str, const char *fmt, ...) {
|
||||
FILE f;
|
||||
|
|
@ -131,6 +136,7 @@ int sprintf(char *str, const char *fmt, ...) {
|
|||
return result;
|
||||
}
|
||||
|
||||
#undef printf
|
||||
//----- printf()
|
||||
int printf(const char *fmt, ...) {
|
||||
#if CHECK_LIBC_INIT
|
||||
|
|
@ -151,6 +157,7 @@ int printf(const char *fmt, ...) {
|
|||
else return 0;
|
||||
}
|
||||
|
||||
#undef vprintf
|
||||
//----- vprintf()
|
||||
int vprintf(const char * fmt, __VALIST param) {
|
||||
#if CHECK_LIBC_INIT
|
||||
|
|
@ -165,11 +172,11 @@ int vprintf(const char * fmt, __VALIST param) {
|
|||
}
|
||||
#endif // ENAC_FLOAT
|
||||
|
||||
#undef vsnprintf
|
||||
//----- vsnprintf()
|
||||
int vsnprintf(char *str, size_t size, const char *fmt, __VALIST param) {
|
||||
int result;
|
||||
int w;
|
||||
int v11;
|
||||
FILE f;
|
||||
#if CHECK_LIBC_INIT
|
||||
if (!libc_has_init) {
|
||||
|
|
@ -199,6 +206,7 @@ int vsnprintf(char *str, size_t size, const char *fmt, __VALIST param) {
|
|||
return result;
|
||||
}
|
||||
|
||||
#undef vfprintf
|
||||
//----- vfprintf()
|
||||
int vfprintf(FILE *fp, const char *fmt0, va_list ap) {
|
||||
#if CHECK_LIBC_INIT
|
||||
|
|
@ -209,86 +217,103 @@ int vfprintf(FILE *fp, const char *fmt0, va_list ap) {
|
|||
return __rtl_vfprintf_r_v1_00(_rtl_impure_ptr, fp, fmt0, ap);
|
||||
}
|
||||
|
||||
#undef memchr
|
||||
//----- memchr()
|
||||
void * memchr(const void * src_void , int c , size_t length) {
|
||||
return __rtl_memchr_v1_00(src_void, c, length);
|
||||
}
|
||||
|
||||
#undef memcmp
|
||||
//----- memcmp()
|
||||
int memcmp(const void *m1, const void *m2, size_t n) {
|
||||
return __rtl_memcmp_v1_00(m1, m2, n);
|
||||
}
|
||||
|
||||
#undef memcpy
|
||||
//----- memcpy()
|
||||
void * memcpy(void *dst0, const void *src0, size_t len0) {
|
||||
return __rtl_memcpy_v1_00(dst0, src0, len0);
|
||||
}
|
||||
|
||||
#undef memmove
|
||||
//----- memmove()
|
||||
void * memmove(void *dst_void, const void *src_void, size_t length) {
|
||||
return __rtl_memmove_v1_00(dst_void, src_void, length);
|
||||
}
|
||||
|
||||
#undef memset
|
||||
//----- memset()
|
||||
void * memset(void *m, int c, size_t n) {
|
||||
return __rtl_memset_v1_00(m, c, n);
|
||||
}
|
||||
|
||||
#undef strcat
|
||||
//----- strcat()
|
||||
char * strcat(char *s1, const char *s2) {
|
||||
return (char *) __rtl_strcat_v1_00(s1, s2);
|
||||
}
|
||||
|
||||
#undef strchr
|
||||
//----- strchr()
|
||||
char * strchr(const char *s1, int i) {
|
||||
return (char *) __rtl_strchr_v1_00(s1, i);
|
||||
}
|
||||
|
||||
#undef strcmp
|
||||
//----- strcmp()
|
||||
int strcmp(const char *s1, const char *s2) {
|
||||
return __rtl_strcmp_v1_00(s1, s2);
|
||||
}
|
||||
|
||||
#undef strcpy
|
||||
//----- strcpy()
|
||||
char * strcpy(char *dst0, const char *src0) {
|
||||
return (char *) __rtl_strcpy_v1_00(dst0, src0);
|
||||
}
|
||||
|
||||
#undef strlen
|
||||
//----- strlen()
|
||||
size_t strlen(const char *str) {
|
||||
return __rtl_strlen_v1_00(str);
|
||||
}
|
||||
|
||||
#undef strncat
|
||||
//----- strncat()
|
||||
char * strncat(char *s1, const char *s2, size_t n) {
|
||||
return (char *) __rtl_strncat_v1_00(s1, s2, n);
|
||||
}
|
||||
|
||||
#undef strncmp
|
||||
//----- strncmp()
|
||||
int strncmp(const char *s1, const char *s2, size_t n) {
|
||||
return __rtl_strncmp_v1_00(s1, s2, n);
|
||||
}
|
||||
|
||||
#undef strncpy
|
||||
//----- strncpy()
|
||||
char * strncpy(char *dst0, const char *src0, size_t count) {
|
||||
return (char *) __rtl_strncpy_v1_00(dst0, src0, count);
|
||||
}
|
||||
|
||||
#undef strstr
|
||||
//----- strstr()
|
||||
char * strstr(const char *searchee, const char *lookfor) {
|
||||
return (char *) __rtl_strstr_v1_00(searchee, lookfor);
|
||||
}
|
||||
|
||||
#undef strsep
|
||||
//----- strsep()
|
||||
char * strsep(char **source_ptr, const char *delim) {
|
||||
return (char *) __rtl_strsep_v1_00(source_ptr, delim);
|
||||
}
|
||||
|
||||
#undef strtok
|
||||
//----- strtok()
|
||||
char * strtok(char *s, const char *delim) {
|
||||
return (char *) __rtl_strtok_v1_00(s, delim);
|
||||
}
|
||||
|
||||
extern _LONG_CALL_ROM_ int _vsscanf(const char *buf, const char *fmt, va_list args);
|
||||
#undef sscanf
|
||||
int sscanf(const char *buf, const char *fmt, ...) {
|
||||
va_list args;
|
||||
int i;
|
||||
|
|
@ -300,7 +325,7 @@ int sscanf(const char *buf, const char *fmt, ...) {
|
|||
return i;
|
||||
}
|
||||
|
||||
char toupper(char ch) {
|
||||
int toupper(int ch) {
|
||||
return ((ch >= 'a' && ch <= 'z') ? ch - 'a' + 'A' : ch);
|
||||
};
|
||||
|
||||
|
|
@ -366,7 +391,7 @@ void longjmp(__jmp_buf buf, long value)
|
|||
|
||||
extern __attribute__ ((long_call)) unsigned int Rand(void);
|
||||
|
||||
unsigned int rand(void)
|
||||
int rand(void)
|
||||
{
|
||||
return Rand();
|
||||
}
|
||||
|
|
@ -534,3 +559,8 @@ int __aeabi_fcmpgt(float a, float b)
|
|||
{
|
||||
return __rtl_fcmpgt_v1_00(a, b);
|
||||
}
|
||||
|
||||
extern _LONG_CALL_ void __aeabi_memset(void *dest, size_t n, int c); // { memset(dest, c, n); }
|
||||
|
||||
void __aeabi_memclr(void *dest, size_t n) { __aeabi_memset(dest, n, 0); }
|
||||
void __aeabi_memclr4(void *dest, size_t n) { __aeabi_memset(dest, n, 0); }
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
*/
|
||||
|
||||
#include "basic_types.h"
|
||||
#include "rt_lib_rom.h"
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Function declarations
|
||||
|
|
|
|||
|
|
@ -20,25 +20,28 @@ float rtl_sin_f32(float a);
|
|||
// int __rtl_cos_f32_v1_00();
|
||||
// int __rtl_sin_f32_v1_00();
|
||||
|
||||
|
||||
extern _LONG_CALL_ float __rtl_fabsf_v1_00(float a);
|
||||
//----- rtl_fabsf()
|
||||
float rtl_fabsf(float a)
|
||||
{
|
||||
return __rtl_fabsf_v1_00(a);
|
||||
}
|
||||
|
||||
extern _LONG_CALL_ int __rtl_fabs_v1_00(double a);
|
||||
//----- rtl_fabs()
|
||||
int rtl_fabs(double a)
|
||||
{
|
||||
return __rtl_fabs_v1_00(a);
|
||||
}
|
||||
|
||||
extern _LONG_CALL_ float __rtl_cos_f32_v1_00(float a);
|
||||
//----- rtl_cos_f32()
|
||||
float rtl_cos_f32(float a)
|
||||
{
|
||||
return __rtl_cos_f32_v1_00(a);
|
||||
}
|
||||
|
||||
extern _LONG_CALL_ float __rtl_sin_f32_v1_00(float a);
|
||||
//----- rtl_sin_f32()
|
||||
float rtl_sin_f32(float a)
|
||||
{
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue