mirror of
https://github.com/jialexd/sdk-ameba-v4.0c_180328.git
synced 2024-11-23 14:34:18 +00:00
649 lines
24 KiB
C
Executable file
649 lines
24 KiB
C
Executable file
/**
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******************************************************************************
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* @file rtl8711b_ssi.h
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* @author
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* @version V1.0.0
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* @date 2016-05-17
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* @brief This file contains all the functions prototypes for the SPI firmware
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* library.
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******************************************************************************
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* @attention
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*
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* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
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******************************************************************************
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*/
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#ifndef _RTL8710B_SPI_H_
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#define _RTL8710B_SPI_H_
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/** @addtogroup AmebaZ_Periph_Driver
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* @{
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*/
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/** @defgroup SPI
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* @brief SPI driver modules
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* @{
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*/
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/** @addtogroup SPI
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* @verbatim
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*****************************************************************************************
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* Introduction
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*****************************************************************************************
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* SPI0:
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* - Support Motorola SPI interface
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* - Role: Slave
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* - Base Address: SPI0_DEV
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* - Bus Clk: 62.5MHz
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* - BaudRate: less than or equal to 31.25M
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* - Transfer mode:TRx
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* - Data Frame Size: 4-16 bits supported
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* - IRQ Number: SPI0_IRQ
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* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI0_TX
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* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI0_RX
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*
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* SPI1:
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* - Support Motorola SPI interface
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* - Role: Master
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* - Base Address: SPI1_DEV
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* - Bus Clk: 62.5MHz
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* - BaudRate: less than or equal to 31.25M
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* - Transfer mode:Tx,Rx,TRx,EEPROM Read
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* - Data Frame Size: 4-16 bits supported
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* - IRQ Number: SPI1_IRQ
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* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI1_TX
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* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI1_RX
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*
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*****************************************************************************************
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* PINMUX
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*****************************************************************************************
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* SPI0:
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* - S0: PA_1(Sclk)/PA_2(CS)/PA_3(MISO)/PA_4(MOSI).
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* - S1: PA_18(Sclk)/PA_19(CS)/PA_22(MISO)/PA_23(MOSI).
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* - S2: PB_0(Sclk)/PB_1(CS)/PB_2(MISO)/PB_3(MOSI).
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*
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* SPI1:
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* - S0: PA_1(Sclk)/PA_2(CS)/PA_3(MISO)/PA_4(MOSI).
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* - S1: PA_18(Sclk)/PA_19(CS)/PA_22(MISO)/PA_23(MOSI).
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* - S2: PB_0(Sclk)/PB_1(CS)/PB_2(MISO)/PB_3(MOSI).
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*
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*****************************************************************************************
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* How to use Normal SPI
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*****************************************************************************************
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* To use the SPI in DMA mode, the following steps are mandatory:
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*
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* 1. Enable peripheral clock using the following functions:
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* -RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE) for SPI0;
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* -RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, ENABLE) for SPI1;
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*
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* 2. Configure the SPIx pinmux:
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* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIS) for SPI0;
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* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIM) for SPI1;
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*
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* 3. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize,
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* Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using
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* SSI_StructInit() and change some parameters if needed
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*
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* 4. Init Hardware use step3 parameters:
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* SSI_Init(SPI_TypeDef *spi_dev, SSI_InitTypeDef *SSI_InitStruct)
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*
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* 5. Enable the SPI:
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* SSI_Cmd()
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*
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* 6. When using poll:
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* -Using SSI_Writeable() function to make sure that the transmit FIFO is not full,
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* then using SSI_WriteData() function to send data
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*
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* -Using SSI_Readable() function to make sure that the receive FIFO is not empty,
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* then using SSI_ReadData() function to receive data
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*
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* 7. Enable the NVIC and the corresponding interrupt using following function if you need
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* to use interrupt mode.
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* -SSI_INTConfig(): SPI IRQ Mask set
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* -InterruptRegister(): register the SPI irq handler
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* -InterruptEn(): Enable the NVIC interrupt and set irq priority
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*
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*
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* @note in SPI_Exported_Functions group, these functions below are about Interrupts
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* and flags management:
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* -SSI_GetIsr()
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* -SSI_GetRawIsr()
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* -SSI_INTConfig()
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* -SSI_SetRxFifoLevel()
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* -SSI_SetTxFifoLevel()
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* -SSI_SetIsrClean()
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*
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*
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*****************************************************************************************
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* How to use SPI in DMA mode
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*****************************************************************************************
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* To use the SPI in DMA mode, the following steps are mandatory:
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*
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* 1. Enable peripheral clock using the following functions:
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* -RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE) for SPI0;
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* -RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, ENABLE) for SPI1;
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*
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* 2. Configure the SPIx pinmux:
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* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIS) for SPI0;
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* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIM) for SPI1;
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*
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* 3. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize,
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* Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using
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* SSI_StructInit() and change some parameters if needed
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*
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* 4. Init Hardware use step3 parameters:
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* SSI_Init(SPI_TypeDef *spi_dev, SSI_InitTypeDef *SSI_InitStruct)
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*
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* 5. Enable the SPI:
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* SSI_Cmd()
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*
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* 6. GDMA related configurations(DMA burst size/source address/destination address/block size etc).
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*
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* 7. Active the SPI DMA TX/RX using SSI_SetDmaEnable() function.
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*
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* @note in SPI_Exported_Functions group, these functions below are about DMA:
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* -SSI_SetDmaEnable()
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* -SSI_SetDmaLevel()
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*
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*****************************************************************************************
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* @endverbatim
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*/
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/* Exported Types --------------------------------------------------------*/
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/** @defgroup SPI_Exported_Types SPI Exported Types
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* @{
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*/
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/**
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* @brief SPI Init structure definition
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*/
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typedef struct
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{
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u32 SPI_DmaRxDataLevel; /*!< Specifies the DMA receive data level.
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The dma_rx_req is generated when the number of valid data entries in the
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receive FIFO is equal to or above this field value+1,and RDMAE=1.
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@note For Amebaz, the value range of this parameter should be 0 to 63,because
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the depth of Rx FIFO is 64. */
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u32 SPI_DmaTxDataLevel; /*!< Specifies the DMA transmit data level.
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The dma_tx_req is generated when the number of valid data entries in the
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transmit FIFO is equal to or below this field value,and TDMAE=1.
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@note For Amebaz, the value range of this parameter should be 0 to 63,because
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the depth of Rx FIFO is 64. */
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u32 SPI_RxThresholdLevel; /*!< Specifies the receive FIFO threshold level.
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This Parameter controls the level of entries(or above) at which the receive FIFO controller
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triggers an interrupt.When the number of receive FIFO entries is greater than or equal to this
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value +1,the receive FIFO full interrupt is triggered.
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@note For Amebaz, the value range of this parameter should be 0 to 63,because the depth
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of Rx FIFO is 64. */
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u32 SPI_TxThresholdLevel; /*!< Specifies the transmit FIFO threshold level.
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This Parameter controls the level of entries (or below) at which the transmit FIFO controller
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triggers an interrupt.When the number of transmit FIFO entries is less than or equal to this
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value,the transmit FIFO empty interrupt is triggered.
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@note For Amebaz, the value range of this parameter should be 0 to 63,because of the depth
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of Rx FIFO is 64. */
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u32 SPI_SlaveSelectEnable; /*!< Set the slave select enable flag.
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This Parameter controls which slave to be selected by master,each bit in SER register
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corresponds to a slave select line(ss_x_n) from spi master.
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@note The default vlaue of this parameter is 0,and one slave is selected.if more slaves to be selected,
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you may use SW way to do this.And this parameter is used only when the device is master. */
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u32 SPI_ClockDivider; /*!< Specifies the SPI Baud Rate.
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The value of sclk_out equals to ssi_clk devides the value of this parameter
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@note The LSB for this field is always set to 0 and is unaffected by a write operation,which ensures
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an even value is held. */
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u32 SPI_DataFrameNumber; /*!< Specifies the number of data frames master wants to receive .
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When TMOD=10 or TMOD=11,Ctrl1 register uses this value to set the number of data frames to
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be continuous received.
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@note The value of this parameter should be set to the number of data frames that to be received
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minus one.And this parameter is used only when the device is master. */
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u32 SPI_DataFrameFormat; /*!< Selects which serial protocol transfers the data .
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This parameter can be a value of @ref SPI_Frame_Format_definitions. */
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u32 SPI_DataFrameSize; /*!< Selects the data frame length .
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This parameter can be a value of @ref SPI_Data_Frame_Size_definitions.
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@note Need to right-justify transmit data before writting into the transmit FIFO
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The transmit logic ignores the upper unused bits when transmitting the data. */
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u32 SPI_InterruptMask; /*!< Specifies which interrupt to be enable.
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Each bit in this parameter corresponds to a specific interrupt.*/
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u32 SPI_Role; /*!< Specifies the role of SPI device.
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This parameter can be a value of @ref SPI_ROLE_definitions. . */
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u32 SPI_SclkPhase; /*!< Specifies the serial clock phase.
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When SPI_SclkPhase = 0, data are captured on the first edge of the serial clock. When SPI_SclkPhase = 1,
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the serial clock starts toggling one cycle after the slave select line is activated, and data
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are captured on the second edge of the serial clock.
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This parameter can be a value of @ref SPI_SCPH_definitions.
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@note Valid when the frame format(FRF) is set to Motorola SPI. */
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u32 SPI_SclkPolarity; /*!< Specifies the serial clock polarity.
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When SPI_SclkPolarity = 0, the serial clock remains low when idle. When SPI_SclkPolarity = 1,
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the serial clock remains high when idle.
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This parameter can be a value of @ref SPI_SCPOL_definitions.
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@note Valid when the frame format(FRF) is set to Motorola SPI.*/
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u32 SPI_TransferMode; /*!< Selects the mode of transfer for serial communication.
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This parameter can be a value of @ref SPI_TMOD_definitions.
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@note This transfer mode is only valid when the DW_apb_ssi is configured as a master device.*/
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u32 SPI_MicrowireControlFrameSize; /*!< Selects the length of the control word for the Microwire frame format.
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This parameter can be a value of @ref SPI_MW_Control_Frame_Size_definitions. */
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u32 SPI_MicrowireDirection; /*!< Specifies of the data word when the Microwire serial protocol is used.
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This parameter can be a value of @ref SPI_MW_Direction_definitions. */
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u32 SPI_MicrowireHandshaking; /*!< Specifies Microwire Handshaking.
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This parameter can be a value of @ref SPI_MW_Handshake_Enable_definitions. */
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u32 SPI_MicrowireTransferMode; /*!< Specifies Microwire Transfer Mode.
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This parameter can be a value of @ref SPI_MW_TMOD_definitions. */
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}SSI_InitTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup SPI_Exported_Constants SPI Exported Constants
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* @{
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*/
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/** @defgroup SPI_TMOD_definitions
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* @{
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*/
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#define TMOD_TR (0)
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#define TMOD_TO (1)
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#define TMOD_RO (2)
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#define TMOD_EEPROM_R (3)
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/**
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* @}
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*/
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/** @defgroup SPI_SCPOL_definitions
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* @{
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*/
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#define SCPOL_INACTIVE_IS_LOW (0)
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#define SCPOL_INACTIVE_IS_HIGH (1)
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/**
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* @}
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*/
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/** @defgroup SPI_SCPH_definitions
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* @{
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*/
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#define SCPH_TOGGLES_IN_MIDDLE (0)
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#define SCPH_TOGGLES_AT_START (1)
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/**
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* @}
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*/
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/** @defgroup SPI_Data_Frame_Size_definitions
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* @{
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*/
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#define DFS_4_BITS (3)
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#define DFS_5_BITS (4)
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#define DFS_6_BITS (5)
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#define DFS_7_BITS (6)
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#define DFS_8_BITS (7)
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#define DFS_9_BITS (8)
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#define DFS_10_BITS (9)
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#define DFS_11_BITS (10)
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#define DFS_12_BITS (11)
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#define DFS_13_BITS (12)
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#define DFS_14_BITS (13)
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#define DFS_15_BITS (14)
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#define DFS_16_BITS (15)
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/**
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* @}
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*/
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/** @defgroup SPI_MW_Control_Frame_Size_definitions
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* @{
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*/
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#define CFS_1_BIT (0)
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#define CFS_2_BITS (1)
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#define CFS_3_BITS (2)
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#define CFS_4_BITS (3)
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#define CFS_5_BITS (4)
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#define CFS_6_BITS (5)
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#define CFS_7_BITS (6)
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#define CFS_8_BITS (7)
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#define CFS_9_BITS (8)
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#define CFS_10_BITS (9)
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#define CFS_11_BITS (10)
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#define CFS_12_BITS (11)
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#define CFS_13_BITS (12)
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#define CFS_14_BITS (13)
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#define CFS_15_BITS (14)
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#define CFS_16_BITS (15)
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/**
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* @}
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*/
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/** @defgroup SPI_ROLE_definitions
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* @{
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*/
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#define SSI_SLAVE (0)
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#define SSI_MASTER (1)
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/**
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* @}
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*/
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/** @defgroup SPI_Frame_Format_definitions
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* @{
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*/
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#define FRF_MOTOROLA_SPI (0)
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#define FRF_TI_SSP (1)
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#define FRF_NS_MICROWIRE (2)
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#define FRF_RSVD (3)
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/**
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* @}
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*/
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/** @defgroup SPI_DMA_Control_definitions
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* @{
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*/
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#define SSI_NODMA (0)
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#define SSI_RXDMA_ENABLE (1)
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#define SSI_TXDMA_ENABLE (2)
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#define SSI_TRDMA_ENABLE (3)
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/**
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* @}
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*/
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/** @defgroup SPI_MW_Handshake_Enable_definitions
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* @{
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*/
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#define MW_HANDSHAKE_DISABLE (0)
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#define MW_HANDSHAKE_ENABLE (1)
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/**
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* @}
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*/
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/** @defgroup SPI_MW_Direction_definitions
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* @{
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*/
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#define MW_DIRECTION_SLAVE_TO_MASTER (0)
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#define MW_DIRECTION_MASTER_TO_SLAVE (1)
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/**
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* @}
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*/
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/** @defgroup SPI_MW_TMOD_definitions
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* @{
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*/
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#define MW_TMOD_NONSEQUENTIAL (0)
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#define MW_TMOD_SEQUENTIAL (1)
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/**
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* @}
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*/
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/** @defgroup SPI_FIFO_depth_definitions
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* @{
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*/
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#define SSI_TX_FIFO_DEPTH (64)
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#define SSI_RX_FIFO_DEPTH (64)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup SPI_Exported_Functions SPI Exported Functions
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* @{
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*/
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/** @defgroup SPI_Exported_Normal_Functions SPI Exported Normal Functions
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* @{
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*/
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_LONG_CALL_ void SSI_Cmd(SPI_TypeDef *spi_dev, u32 NewStaus);
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_LONG_CALL_ void SSI_SetSclkPolarity(SPI_TypeDef *spi_dev, u32 SclkPolarity);
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_LONG_CALL_ void SSI_SetSclkPhase(SPI_TypeDef *spi_dev, u32 SclkPhase);
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_LONG_CALL_ void SSI_WriteData(SPI_TypeDef *spi_dev, u32 value);
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_LONG_CALL_ VOID SSI_INTConfig(SPI_TypeDef* spi_dev, u32 SSI_IT, u32 newState);
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_LONG_CALL_ void SSI_SetRxFifoLevel(SPI_TypeDef *spi_dev, u32 RxThresholdLevel);
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_LONG_CALL_ void SSI_SetTxFifoLevel(SPI_TypeDef *spi_dev, u32 TxThresholdLevel);
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_LONG_CALL_ void SSI_SetSlaveEnable(SPI_TypeDef *spi_dev, u32 SlaveIndex);
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_LONG_CALL_ u32 SSI_Busy(SPI_TypeDef *spi_dev);
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_LONG_CALL_ u32 SSI_Writeable(SPI_TypeDef *spi_dev);
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_LONG_CALL_ u32 SSI_Readable(SPI_TypeDef *spi_dev);
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_LONG_CALL_ u32 SSI_GetRxCount(SPI_TypeDef *spi_dev);
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_LONG_CALL_ u32 SSI_GetTxCount(SPI_TypeDef *spi_dev);
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_LONG_CALL_ u32 SSI_GetStatus(SPI_TypeDef *spi_dev);
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_LONG_CALL_ u32 SSI_GetIsr(SPI_TypeDef *spi_dev);
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_LONG_CALL_ u32 SSI_ReadData(SPI_TypeDef *spi_dev);
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_LONG_CALL_ u32 SSI_ReceiveData(SPI_TypeDef *spi_dev, void* RxData, u32 Length);
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_LONG_CALL_ u32 SSI_SendData(SPI_TypeDef *spi_dev, void* TxData, u32 Length, u32 Role);
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_LONG_CALL_ u32 SSI_GetRawIsr(SPI_TypeDef *spi_dev);
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_LONG_CALL_ u32 SSI_GetSlaveEnable(SPI_TypeDef *spi_dev);
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_LONG_CALL_ u32 SSI_GetDataFrameSize(SPI_TypeDef *spi_dev);
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_LONG_CALL_ void SSI_Init(SPI_TypeDef *spi_dev, SSI_InitTypeDef *SSI_InitStruct);
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_LONG_CALL_ void SSI_StructInit(SSI_InitTypeDef* SSI_InitStruct);
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_LONG_CALL_ void SSI_SetDataFrameSize(SPI_TypeDef *spi_dev, u32 DataFrameSize);
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_LONG_CALL_ void SSI_SetBaud(SPI_TypeDef *SPIx, u32 BaudRate, u32 IpClk);
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_LONG_CALL_ void SSI_SetIsrClean(SPI_TypeDef *spi_dev, u32 InterruptStatus);
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_LONG_CALL_ void SSI_SetReadLen(SPI_TypeDef *spi_dev, u32 DataFrameNumber);
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_LONG_CALL_ void SSI_PinmuxInit(u8 Index, u32 PinmuxSelect);
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_LONG_CALL_ void SSI_PinmuxDeInit(u8 Index, u32 PinmuxSelect);
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/**
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* @}
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*/
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/** @defgroup SPI_Exported_DMA_Functions SPI Exported DMA Functions
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* @{
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*/
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_LONG_CALL_ BOOL SSI_TXGDMA_Init(u32 Index, PGDMA_InitTypeDef GDMA_InitStruct, void *CallbackData,
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IRQ_FUN CallbackFunc, u8 *pTxData, u32 Length);
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_LONG_CALL_ BOOL SSI_RXGDMA_Init(u8 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData,
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IRQ_FUN CallbackFunc, u8 *pRxData, u32 Length);
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_LONG_CALL_ void SSI_SetDmaEnable(SPI_TypeDef *spi_dev, u32 newState, u32 Mask);
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_LONG_CALL_ void SSI_SetDmaLevel(SPI_TypeDef *spi_dev, u32 TxLeve, u32 RxLevel);
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/**
|
|
* @}
|
|
*/
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|
|
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/**
|
|
* @}
|
|
*/
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|
|
|
|
|
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/* Registers Definitions --------------------------------------------------------*/
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|
/**************************************************************************//**
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|
* @defgroup SPI_Register_Definitions SPI Register Definitions
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|
* @{
|
|
*****************************************************************************/
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|
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/**************************************************************************//**
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|
* @defgroup CTRLR0
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|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_CTRLR0_DFS ((u32)0x0000000F)
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|
#define BIT_CTRLR0_FRF ((u32)0x00000003 << 4)
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|
#define BIT_CTRLR0_SCPH ((u32)0x00000001 << 6)
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|
#define BIT_CTRLR0_SCPOL ((u32)0x00000001 << 7)
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|
#define BIT_CTRLR0_TMOD ((u32)0x00000003 << 8)
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|
#define BIT_CTRLR0_SLV_OE ((u32)0x00000001 << 10)
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|
#define BIT_CTRLR0_SRL ((u32)0x00000001 << 11)
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|
#define BIT_CTRLR0_CFS ((u32)0x0000000F << 12)
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|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup CTRLR1
|
|
* @{
|
|
*****************************************************************************/
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|
#define BIT_CTRLR1_NDF ((u32)0x0000FFFF)
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|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup SSIENR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_SSIENR_SSI_EN ((u32)0x00000001)
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup MWCR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_MWCR_MWMOD ((u32)0x00000001)
|
|
#define BIT_MWCR_MDD ((u32)0x00000001 << 1)
|
|
#define BIT_MWCR_MHS ((u32)0x00000001 << 2)
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup SER
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_SER_SER ((u32)0x0000FFFF)
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup BAUDR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_BAUDR_SCKDV ((u32)0x0000FFFF)
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup TXFLTR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_TXFTLR_TFT ((u32)0x0000003F)//(TX_ABW-1):0
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup RXFLTR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_RXFTLR_RFT ((u32)0x0000003F) // (RX_ABW-1):0
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup TXFLR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_MASK_TXFLR_TXTFL ((u32)0x0000007F) // (TX_ABW):0
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup RXFLR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_MASK_RXFLR_RXTFL ((u32)0x0000007F) // (RX_ABW):0
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup SR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_SR_BUSY ((u32)0x00000001)
|
|
#define BIT_SR_TFNF ((u32)0x00000001 << 1)
|
|
#define BIT_SR_TFE ((u32)0x00000001 << 2)
|
|
#define BIT_SR_RFNE ((u32)0x00000001 << 3)
|
|
#define BIT_SR_RFF ((u32)0x00000001 << 4)
|
|
#define BIT_SR_TXE ((u32)0x00000001 << 5)
|
|
#define BIT_SR_DCOL ((u32)0x00000001 << 6)
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup IMR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_IMR_TXEIM ((u32)0x00000001)
|
|
#define BIT_IMR_TXOIM ((u32)0x00000001 << 1)
|
|
#define BIT_IMR_RXUIM ((u32)0x00000001 << 2)
|
|
#define BIT_IMR_RXOIM ((u32)0x00000001 << 3)
|
|
#define BIT_IMR_RXFIM ((u32)0x00000001 << 4)
|
|
#define BIT_IMR_MSTIM ((u32)0x00000001 << 5)
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup ISR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_ISR_TXEIS ((u32)0x00000001)
|
|
#define BIT_ISR_TXOIS ((u32)0x00000001 << 1)
|
|
#define BIT_ISR_RXUIS ((u32)0x00000001 << 2)
|
|
#define BIT_ISR_RXOIS ((u32)0x00000001 << 3)
|
|
#define BIT_ISR_RXFIS ((u32)0x00000001 << 4)
|
|
#define BIT_ISR_MSTIS ((u32)0x00000001 << 5)
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup RISR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_RISR_TXEIR ((u32)0x00000001)
|
|
#define BIT_RISR_TXOIR ((u32)0x00000001 << 1)
|
|
#define BIT_RISR_RXUIR ((u32)0x00000001 << 2)
|
|
#define BIT_RISR_RXOIR ((u32)0x00000001 << 3)
|
|
#define BIT_RISR_RXFIR ((u32)0x00000001 << 4)
|
|
#define BIT_RISR_MSTIR ((u32)0x00000001 << 5)
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup DMACR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_SHIFT_DMACR_RDMAE ((u32)0x00000001)
|
|
#define BIT_SHIFT_DMACR_TDMAE ((u32)0x00000001 << 1)
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup DMATDLR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_DMATDLR_DMATDL ((u32)0x0000003F) // (TX_ABW-1):0
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup DMARDLR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_DMARDLR_DMARDL ((u32)0x0000003F )// (RX_ABW-1):0
|
|
/** @} */
|
|
|
|
/**************************************************************************//**
|
|
* @defgroup DR
|
|
* @{
|
|
*****************************************************************************/
|
|
#define BIT_DR_DR ((u32)0x0000FFFF)
|
|
/** @} */
|
|
/** @} */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Other Definitions --------------------------------------------------------*/
|
|
typedef struct
|
|
{
|
|
SPI_TypeDef* SPIx;
|
|
u32 Tx_HandshakeInterface;
|
|
u32 Rx_HandshakeInterface;
|
|
IRQn_Type IrqNum;
|
|
} SPI_DevTable;
|
|
|
|
extern const SPI_DevTable SPI_DEV_TABLE[2];
|
|
|
|
#endif //_RTL8710B_SPI_H_
|
|
|
|
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|