mirror of
https://github.com/jialexd/sdk-ameba-v4.0c_180328.git
synced 2024-11-23 14:34:18 +00:00
507 lines
15 KiB
C
Executable file
507 lines
15 KiB
C
Executable file
/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef __HAL_CRYPTO_RAM_H__
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#define __HAL_CRYPTO_RAM_H__
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// IPSecEngine
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#define CRYPTO_MAX_DESP 8
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#define CRYPTO_MAX_MSG_LENGTH 32000
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#define CRYPTO_MD5_DIGEST_LENGTH 16
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#define CRYPTO_SHA1_DIGEST_LENGTH 20
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#define CRYPTO_SHA2_DIGEST_LENGTH 32
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#define CRYPTO_MAX_DIGEST_LENGTH 32 // SHA256 Digest length : 32
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#define CRYPTO_MAX_KEY_LENGTH 32 // MAX is AES-256 : 32 byte, 3DES : 24 byte
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#define CRYPTO_PADSIZE 64
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#define CRYPTO_AUTH_PADDING 64
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typedef enum _SHA2_TYPE_ {
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SHA2_NONE = 0,
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SHA2_224 = 224/8,
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SHA2_256 = 256/8,
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SHA2_384 = 384/8,
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SHA2_512 = 512/8
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} SHA2_TYPE;
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/**************************************************************************
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* Definition for Parameters
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**************************************************************************/
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#define HAL_CRYPTO_WRITE32(addr, value32) HAL_WRITE32(CRYPTO_REG_BASE, (addr), (value32))
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#define HAL_CRYPTO_WRITE16(addr, value16) HAL_WRITE16(CRYPTO_REG_BASE, (addr), (value16))
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#define HAL_CRYPTO_WRITE8(addr, value8) HAL_WRITE8(CRYPTO_REG_BASE, (addr), (value8))
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#define HAL_CRYPTO_READ32(addr) HAL_READ32(CRYPTO_REG_BASE, (addr))
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#define HAL_CRYPTO_READ16(addr) HAL_READ16(CRYPTO_REG_BASE, (addr))
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#define HAL_CRYPTO_READ8(addr) HAL_READ8(CRYPTO_REG_BASE, (addr))
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#define REG_IPSSDAR (0x00) // IPSec Source Descriptor Starting Address Register
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#define REG_IPSDDAR (0x04) // IPSec Destination Descriptor Starting Address Register
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#define REG_IPSCSR (0x08) // IPSec Command/Status Register
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#define REG_IPSCSDD (0x10) // IPSec CheckSum of Decrypted Data
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#define REG_IPSCTR (0x0C) // IPSec Control Register
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/**************************************************************************
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* Type definition for AES KEY
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**************************************************************************/
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//
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// For AES key calculation
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//
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#define CIPHER_AES_MAXNR 14
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#define CIPHER_AES_BLOCK_SIZE 16
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enum _CIPHER_AES_KEYlEN
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{
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_CIPHER_AES_KEYLEN_NONE = 0,
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_CIPHER_AES_KEYLEN_128BIT = 1,
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_CIPHER_AES_KEYLEN_192BIT = 2,
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_CIPHER_AES_KEYLEN_256BIT = 3,
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};
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typedef struct {
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u32 rd_key[4 *(CIPHER_AES_MAXNR + 1)];
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int rounds;
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} RTL_SW_AES_KEY;
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/**************************************************************************
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* Data Structure for Descriptor
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**************************************************************************/
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#define _LITTLE_ENDIAN
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#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
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typedef struct __rtl_crypto_source_s
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{
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// offset 0 :
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u32 sbl:15;
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// u32 resv2:1;
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u32 isSHA2:1;
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u32 md5:1;
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u32 hmac:1;
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//u32 auth_type:3; // hmac:1 + md5:2
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u32 ctr:1;
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u32 cbc:1;
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u32 trides:1;
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u32 aeskl:2;
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u32 kam:3;
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u32 ms:2;
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u32 resv1:1;
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u32 fs:1;
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u32 eor:1;
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u32 own:1;
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// offset 1 :
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u32 enl:15;
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u32 resv4:1;
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u32 a2eo:8;
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u32 resv3:5;
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u32 sha2:3;
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// offset 2:
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u32 resv6:16;
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u32 apl:8;
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u32 resv5:8;
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// offset 3:
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u32 sdbp;
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}RTL_CRYPTO_SOURCE_T;
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typedef struct __rtl_crypto_dest_s
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{
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u32 dbl:15;
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u32 resv1:15;
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u32 eor:1;
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u32 own:1;
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u32 ddbp;
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u32 resv2;
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u32 icv[5+4]; // also set with IPSCTR's DDLEN
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} RTL_CRYPTO_DEST_T;
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#else // SYSTEM_ENDIAN -> BIG_ENDIAN
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typedef struct __rtl_crypto_source_s
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{
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u32 own:1;
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u32 eor:1;
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u32 fs:1;
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u32 resv1:1;
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u32 ms:2;
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u32 kam:3;
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u32 aeskl:2;
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u32 trides:1;
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u32 cbc:1;
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u32 ctr:1;
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u32 auth_type:3; // hmac:1 + md5:2
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// u32 resv2:1;
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u32 sbl:15;
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u32 resv3:8;
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u32 a2eo:8;
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u32 resv4:1;
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u32 enl:15;
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u32 resv5:8;
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u32 apl:8;
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u32 resv6:16;
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u32 sdbp;
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} RTL_CRYPTO_SOURCE_T;
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typedef struct __rtl_crypto_dest_s
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{
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u32 own:1;
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u32 eor:1;
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u32 resv1:15;
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u32 dbl:15;
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u32 ddbp;
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u32 resv2;
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u32 icv[5]; // changint with DDLEN
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} RTL_CRYPTO_DEST_T;
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#endif // SYSTEM_ENDIAN
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/**************************************************************************
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* Data Structure for Cipher Adapter
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**************************************************************************/
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typedef struct _HAL_CRYPTO_ADAPTER_
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{
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u8 isInit; // 0: not init, 1: init
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u8 dma_mode; // 2: 64 bytes;
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u8 sawb_mode; // 0: disable sawb, 1:enable sawb
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u8 desc_num; // total number of source/destination description
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u8 mode_select;
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u32 cipher_type;
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u8 des;
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u8 trides;
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u8 aes;
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u8 isDecrypt;
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u32 auth_type;
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u8 isHMAC;
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u8 isMD5;
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u8 isSHA1;
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u8 isSHA2;
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SHA2_TYPE sha2type;
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u32 lenAuthKey;
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const u8* pAuthKey;
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u8 authKey[CRYPTO_MAX_DIGEST_LENGTH];
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u32 digestlen;
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// AES calculation
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RTL_SW_AES_KEY aes_key;
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u32 lenCipherKey;
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const u8* pCipherKey;
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u32 a2eo, enl, apl;
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u8 decryptKey[CRYPTO_MAX_KEY_LENGTH];
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u8 pad_to_align_1[16]; //pad to make g_IOPAD align 32
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u8 g_IOPAD[CRYPTO_PADSIZE*2+32];
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u8 *ipad;
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u8 *opad;
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u8 pad_to_align_2[24]; //pad to make g_authPadding align 32
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u8 g_authPadding[CRYPTO_AUTH_PADDING*2+32];
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// Source Descriptor
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u8 idx_srcdesc;
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RTL_CRYPTO_SOURCE_T *g_ipssdar;
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RTL_CRYPTO_SOURCE_T g_src_buf[CRYPTO_MAX_DESP];
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// Destination Descriptor
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u8 idx_dstdesc;
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RTL_CRYPTO_DEST_T *g_ipsddar;
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RTL_CRYPTO_DEST_T g_dst_buf[CRYPTO_MAX_DESP];
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u8 pad_to_align_3[16]; //pad to make _HAL_CRYPTO_ADAPTER_ size 1280
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} HAL_CRYPTO_ADAPTER, *PHAL_CRYPTO_ADAPTER ;
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/**************************************************************************
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* Definition for value and type
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**************************************************************************/
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/* IPSec Command/Status Register */
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#define IPS_SDUEIP (1<<15) /* Source Descriptor Unavailable Error Interrupt Pending */
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#define IPS_SDLEIP (1<<14) /* Source Descriptor Length Error Interrupt Pending */
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#define IPS_DDUEIP (1<<13) /* Destination Descriptor Unavailable Error Interrupt Pending */
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#define IPS_DDOKIP (1<<12) /* Destination Descriptor OK Interrupt Pending */
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#define IPS_DABFIP (1<<11) /* Data Address Buffer Interrupt Pending */
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#define IPS_FIX_DMA_FAI (1<<3)
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#define IPS_RDMA_IDLE (1<<2)
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#define IPS_POLL (1<<1) /* Descriptor Polling. Set 1 to kick crypto engine to fetch source descriptor. */
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#define IPS_SRST (1<<0) /* Software reset, write 1 to reset */
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/* IPSec Control Register */
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#define IPS_CHKSUM_EN (1<<28) /* Enable check sum calculation of decryption data*/
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//#define IPS_DDLEN_72 (7<<24) /* Destination Descriptor Length : address offset to 72 : for SHA-512 */
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#define IPS_DDLEN_20 (3<<24) /* Destination Descriptor Length : Length is 20*DW : for SHA-1/MD5 */
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#define IPS_DDLEN_16 (2<<24) /* Destination Descriptor Length : Length is 16*DW : for SHA-1/MD5 */
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#define IPS_DDLEN_12 (1<<24) /* Destination Descriptor Length : Length is 12*DW : for SHA-1/MD5 */
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#define IPS_DDLEN_8 (0<<24) /* Destination Descriptor Length : Length is 8*DW : for SHA-1/MD5 */
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#define IPS_SDUEIE (1<<15) /* Source Descriptor Unavailable Error Interrupt Enable */
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#define IPS_SDLEIE (1<<14) /* Source Descriptor Length Error Interrupt Enable */
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#define IPS_DDUEIE (1<<13) /* Destination Descriptor Unavailable Error Interrupt Enable */
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#define IPS_DDOKIE (1<<12) /* Destination Descriptor OK Interrupt Enable */
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#define IPS_DABFIE (1<<11) /* Data Address Buffer Interrupt Enable */
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#define IPS_LXBIG (1<<9) /* Lx bus data endian*/
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#define IPS_LBKM (1<<8) /* Loopback mode enable */
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#define IPS_SAWB (1<<7) /* Source Address Write Back */
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#define IPS_CKE (1<<6) /* Clock enable */
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#define IPS_DMBS_MASK (0x7<<3) /* Mask for Destination DMA Maximum Burst Size */
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#define IPS_DMBS_16 (0x0<<3) /* 16 Bytes */
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#define IPS_DMBS_32 (0x1<<3) /* 32 Bytes */
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#define IPS_DMBS_64 (0x2<<3) /* 64 Bytes */
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#define IPS_DMBS_128 (0x3<<3) /* 128 Bytes */
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#define IPS_SMBS_MASK (0x7<<0) /* Mask for SourceDMA Maximum Burst Size */
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#define IPS_SMBS_16 (0x0<<0) /* 16 Bytes */
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#define IPS_SMBS_32 (0x1<<0) /* 32 Bytes */
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#define IPS_SMBS_64 (0x2<<0) /* 64 Bytes */
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#define IPS_SMBS_128 (0x3<<0) /* 128 Bytes */
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// MS(0:27-26) Mode Select
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#define _MS_TYPE_CRYPT (0)
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#define _MS_TYPE_AUTH (1)
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#define _MS_TYPE_AUTH_THEN_CRYPT (2)
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#define _MS_TYPE_CRYPT_THEN_AUTH (3)
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// modeCrypto
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#define _MD_NOCRYPTO ((u32)-1)
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#define _MD_CBC (u32)(0)
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#define _MD_ECB (u32)(2)
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#define _MD_CTR (u32)(3)
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#define _MASK_CRYPTOECRYPT (u32)(1<<7)
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#define _MASK_CRYPTOTHENAUTH (u32)(1<<6)
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#define _MASK_CRYPTOAES (u32)(1<<5)
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#define _MASK_CRYPTO3DESDES (u32)(1<<4)
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#define _MASK_CBCECBCTR ((u32)((1<<0)|(1<<1)))
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//#define _MASK_ECBCBC (1<<1)
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// modeAuth
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#define _MD_NOAUTH ((u32)-1)
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#define _MASK_AUTHSHA2 (1<<0)
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#define _MASK_AUTHSHA1MD5 (1<<1)
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#define _MASK_AUTHHMAC (1<<2)
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#define _MASK_AUTH_IOPAD_READY (1<<3)
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#define MAX_PKTLEN (1<<14)
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//Bit 0: 0:DES 1:3DES
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//Bit 1: 0:CBC 1:ECB
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//Bit 2: 0:Decrypt 1:Encrypt
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#define DECRYPT_CBC_DES 0x00
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#define DECRYPT_CBC_3DES 0x01
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#define DECRYPT_ECB_DES 0x02
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#define DECRYPT_ECB_3DES 0x03
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#define ENCRYPT_CBC_DES 0x04
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#define ENCRYPT_CBC_3DES 0x05
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#define ENCRYPT_ECB_DES 0x06
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#define ENCRYPT_ECB_3DES 0x07
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#define RTL8651_CRYPTO_NON_BLOCKING 0x08
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#define RTL8651_CRYPTO_GENERIC_DMA 0x10
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#define DECRYPT_CBC_AES 0x20
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#define DECRYPT_ECB_AES 0x22
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#define DECRYPT_CTR_AES 0x23
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#define ENCRYPT_CBC_AES 0x24
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#define ENCRYPT_ECB_AES 0x26
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#define ENCRYPT_CTR_AES 0x27
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//Bit 0: 0:MD5 1:SHA1
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//Bit 1: 0:Hash 1:HMAC
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#define HASH_MD5 0x00
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#define HASH_SHA1 0x01
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#define HMAC_MD5 0x02
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#define HMAC_SHA1 0x03
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#define REG32(reg) (*((volatile u32 *)(reg)))
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#define READ_MEM32(reg) REG32(reg)
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#define WRITE_MEM32(reg,val) REG32(reg)=(val)
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// address macro
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#define KUSEG 0x00000000
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#define KSEG0 0x80000000
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#define KSEG1 0xa0000000
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#define KSEG2 0xc0000000
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#define KSEG3 0xe0000000
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#define CPHYSADDR(a) ((int)(a) & 0x1fffffff)
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#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
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#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
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#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
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#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
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#define PHYSICAL_ADDRESS(x) (x)//CPHYSADDR(x)
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#define UNCACHED_ADDRESS(x) (x)//CKSEG1ADDR(x)
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#define CACHED_ADDRESS(x) (x)//CKSEG0ADDR(x)
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enum _MODE_SELECT
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{
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_MS_CRYPTO = 0,
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_MS_AUTH = 1,
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_MS_AUTH_THEN_DECRYPT = 2,
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_MS_ENCRYPT_THEN_AUTH = 3,
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};
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//
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// AUTH Type
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//
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#define AUTH_TYPE_NO_AUTH ((u32)-1)
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#define AUTH_TYPE_MASK_FUNC 0x3 // bit 0, bit 1
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#define AUTH_TYPE_MD5 0x2
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#define AUTH_TYPE_SHA1 0x0
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#define AUTH_TYPE_SHA2 0x1
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#define AUTH_TYPE_MASK_HMAC 0x4 // bit 2
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#define AUTH_TYPE_HMAC_MD5 (AUTH_TYPE_MD5 | AUTH_TYPE_MASK_HMAC)
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#define AUTH_TYPE_HMAC_SHA1 (AUTH_TYPE_SHA1 | AUTH_TYPE_MASK_HMAC)
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#define AUTH_TYPE_HMAC_SHA2 (AUTH_TYPE_SHA2 | AUTH_TYPE_MASK_HMAC)
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#define AUTH_TYPE_MASK_SHA2 0x30 // bit 3,4
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#define AUTH_TYPE_SHA2_224 0x10
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#define AUTH_TYPE_SHA2_256 0x20
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//
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// Cipher Type
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//
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#define CIPHER_TYPE_NO_CIPHER ((u32)-1)
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#define CIPHER_TYPE_DES_CBC 0x0
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#define CIPHER_TYPE_DES_ECB 0x2
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#define CIPHER_TYPE_3DES_CBC 0x10
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#define CIPHER_TYPE_3DES_ECB 0x12
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#define CIPHER_TYPE_AES_CBC 0x20
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#define CIPHER_TYPE_AES_ECB 0x22
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#define CIPHER_TYPE_AES_CTR 0x23
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#define CIPHER_TYPE_MODE_ENCRYPT 0x80
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#define CIPHER_TYPE_MASK_FUNC 0x30 // 0x00 : DES, 0x10: 3DES, 0x20: AES
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#define CIPHER_TYPE_FUNC_DES 0x00
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#define CIPHER_TYPE_FUNC_3DES 0x10
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#define CIPHER_TYPE_FUNC_AES 0x20
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#define CIPHER_TYPE_MASK_BLOCK 0x7 // 0x0 : CBC, 0x2: ECB, 0x3: CTR
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#define CIPHER_TYPE_BLOCK_CBC 0x0
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#define CIPHER_TYPE_BLOCK_ECB 0x2
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#define CIPHER_TYPE_BLOCK_CTR 0x3
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//
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// Data Structure
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//
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/**************************************************************************
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* Data Structure for IPSec Engine
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**************************************************************************/
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/*
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* ipsec engine supports scatter list: your data can be stored in several segments those are not continuous.
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* Each scatter points to one segment of data.
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*/
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typedef struct rtl_ipsecScatter_s {
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u32 len;
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void* ptr;
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} rtl_ipsecScatter_t;
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// static inline function / macros
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static inline
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u32 __rtl_cpu_to_be32(u32 val)
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{
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asm volatile(
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"rev %0, %0"
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: "=r" (val)
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: "0" (val));
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return val;
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}
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//
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// ROM global variables
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extern const u32 __AES_Te4[];
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extern const u32 __AES_rcon[];
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//
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// ROM Function mapping
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//
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#define __rtl_cryptoEngine_init CRYPTO_Init
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#define __rtl_cryptoEngine_exit CRYPTO_DeInit
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#define __rtl_cryptoEngine_reset CRYPTO_Reset
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#define __rtl_cryptoEngine_set_security_mode CRYPTO_SetSecurityMode
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#define __rtl_cryptoEngine CRYPTO_Process
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#define __rtl_crypto_cipher_init CRYPTO_CipherInit
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#define __rtl_crypto_cipher_encrypt CRYPTO_CipherEncrypt
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#define __rtl_crypto_cipher_decrypt CRYPTO_CipherDecrypt
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//
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// ROM functions
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//
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extern _LONG_CALL_ void CRYPTO_AlignToBe32(u32 *pData, int bytes4_num );
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extern _LONG_CALL_ void CRYPTO_MemDump(const u8 *start, u32 size, char * strHeader);
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extern _LONG_CALL_ int CRYPTO_Init(HAL_CRYPTO_ADAPTER *pIE);
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extern _LONG_CALL_ int CRYPTO_DeInit(HAL_CRYPTO_ADAPTER *pIE);
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extern _LONG_CALL_ int CRYPTO_Reset(HAL_CRYPTO_ADAPTER *pIE);
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extern _LONG_CALL_ int CRYPTO_SetSecurityMode(HAL_CRYPTO_ADAPTER *pIE,
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IN const u32 mode_select, IN const u32 cipher_type, IN const u32 auth_type,
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IN const void* pCipherKey, IN const u32 lenCipherKey,
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IN const void* pAuthKey, IN const u32 lenAuthKey);
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extern _LONG_CALL_ int CRYPTO_Process(HAL_CRYPTO_ADAPTER *pIE,
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IN const u8 *message, IN const u32 msglen,
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IN const u8 *pIv, IN const u32 ivlen,
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IN const u32 a2eo, OUT void *pResult);
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extern _LONG_CALL_ int CRYPTO_CipherInit(HAL_CRYPTO_ADAPTER *pIE,
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IN const u32 cipher_type,
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IN const u8* key, IN const u32 keylen);
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extern _LONG_CALL_ int CRYPTO_CipherEncrypt(HAL_CRYPTO_ADAPTER *pIE,
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IN const u32 cipher_type,
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IN const u8* message, IN const u32 msglen,
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IN const u8* piv, IN const u32 ivlen,
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OUT u8* pResult);
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extern _LONG_CALL_ int CRYPTO_CipherDecrypt(HAL_CRYPTO_ADAPTER *pIE,
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IN const u32 cipher_type, IN const u8* message, IN const u32 msglen,
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IN const u8* piv, IN const u32 ivlen,
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OUT u8* pResult );
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extern _LONG_CALL_ void CRYPTO_SetCheckSumEn(u32 checksum_en);
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extern _LONG_CALL_ void CRYPTO_GetCheckSumData(u32* pChecksum);
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#endif // __HAL_CRYPTO_RAM_H
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