mirror of
https://github.com/jialexd/sdk-ameba-v4.0c_180328.git
synced 2024-11-28 09:10:28 +00:00
276 lines
6.8 KiB
C
Executable file
276 lines
6.8 KiB
C
Executable file
/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#include "ameba_soc.h"
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#include "build_info.h"
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#include "strproc.h"
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#include "system_8195a.h"
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u32 random_seed = 0x0;
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#if defined ( __ICCARM__ )
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#pragma section=".ram_image2.bss"
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#pragma section=".ram_image2.skb.bss"
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#pragma section=".rom.bss"
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#pragma section=".ram.start.table"
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#pragma section=".ram_image1.bss"
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#pragma section=".image2.start.table1"
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#pragma section=".image2.start.table2"
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u8* __bss_start__;
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u8* __bss_end__;
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void __iar_data_init_app(void)
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{
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__bss_start__ = (u8*)__section_begin(".ram_image2.bss");
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__bss_end__ = (u8*)__section_end(".ram_image2.skb.bss");
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}
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#endif
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extern VOID SOCPS_WakeFromPG(VOID);
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#if defined ( __ICCARM__ )
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VOID
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HalHardFaultHandler_user_define(u32 HardDefaultArg)
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{
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}
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VOID
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HalHardFaultHandler_Patch_c(u32 HardDefaultArg)
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{
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HalHardFaultHandler_user_define(HardDefaultArg);
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INT_HardFault(HardDefaultArg);
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}
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VOID
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HalHardFaultHandler_Patch_asm(void)
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{
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asm("TST LR, #4\n"
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"ITE EQ\n"
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"MRSEQ R0, MSP\n"
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"MRSNE R0, PSP\n"
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"B HalHardFaultHandler_Patch_c");
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}
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#endif
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// Override original Interrupt Vector Table
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VOID BOOT_VectorTableOverride(u32 StackP)
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{
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// Override NMI Handler
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//4 Initial NMI
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//NewVectorTable[2] = (HAL_VECTOR_FUN)HalNMIHandler_Patch;
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#if 0//defined ( __ICCARM__ )
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//Redefine Hardfault Handler
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NewVectorTable[3] = (HAL_VECTOR_FUN)HalHardFaultHandler_Patch_asm;
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#endif
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}
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void BOOT_Reason(void)
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{
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u32 backup_reg0 = BKUP_Read(BKUP_REG0);
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DBG_8195A("boot reason: %x \n", backup_reg0);
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}
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extern u32 GlobalDebugEnable;
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VOID BOOT_InitDebugFlg(VOID)
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{
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SYSTEM_DATA *SysData = (SYSTEM_DATA *)(SPI_FLASH_BASE + FLASH_SYSTEM_DATA_ADDR);
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/* reset */
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ConfigDebugErr = 0;
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ConfigDebugWarn = 0;
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ConfigDebugInfo = 0;
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#if (defined(CONFIG_POST_SIM) || defined(CONFIG_CP))
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return;
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#endif
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/* to initial ROM code using global variable */
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#ifdef CONFIG_DEBUG_ERR_MSG
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ConfigDebugErr = 0xFFFFFFFF;//_DBG_MISC_;]
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#endif
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#ifdef CONFIG_DEBUG_WARN_MSG
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ConfigDebugWarn = 0xFFFFFFFF;
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#endif
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#ifdef CONFIG_DEBUG_INFO_MSG
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ConfigDebugInfo = 0xFFFFFFFF;
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#endif
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if (SysData->UlogDbgEn == 0x0) {
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ConfigDebugErr = 0;
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ConfigDebugWarn = 0;
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ConfigDebugInfo = 0;
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GlobalDebugEnable = 0;
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}
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}
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VOID BOOT_RTC_Init(VOID)
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{
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RTC_InitTypeDef RTC_InitStruct_temp;
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RTC_AlarmTypeDef RTC_AlarmStruct_temp;
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RTC_TimeTypeDef RTC_TimeStruct;
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/* for 32K more stable */
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NCO32K_Init(32768, XTAL_ClkGet(), 15, 2);
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RTC_ClokSource(0);
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RTC_StructInit(&RTC_InitStruct_temp);
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RTC_Init(&RTC_InitStruct_temp);
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/* 32760 need add need add 15 cycles (256Hz) every 4 min*/
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//RTC_SmoothCalibConfig(RTC_CalibSign_Positive, 15,
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// RTC_CalibPeriod_4MIN, RTC_Calib_Enable);
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/* set time when power on */
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RTC_GetTime(RTC_Format_BIN, &RTC_TimeStruct);
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if (RTC_TimeStruct.RTC_Seconds == 0 && RTC_TimeStruct.RTC_Minutes == 0) {
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RTC_TimeStructInit(&RTC_TimeStruct);
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RTC_SetTime(RTC_Format_BIN, &RTC_TimeStruct);
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}
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/* set alarm */
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RTC_AlarmStructInit(&RTC_AlarmStruct_temp);
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RTC_AlarmStruct_temp.RTC_AlarmTime.RTC_Days = 1;
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RTC_AlarmStruct_temp.RTC_AlarmTime.RTC_Hours = 1;
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RTC_AlarmStruct_temp.RTC_AlarmTime.RTC_Minutes = 1;
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RTC_AlarmStruct_temp.RTC_AlarmTime.RTC_Seconds = 30;
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RTC_AlarmStruct_temp.RTC_AlarmMask = RTC_AlarmMask_Hours | RTC_AlarmMask_Minutes;
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RTC_AlarmStruct_temp.RTC_Alarm2Mask = RTC_Alarm2Mask_Days;
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RTC_SetAlarm(RTC_Format_BIN, &RTC_AlarmStruct_temp);
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RTC_AlarmCmd(DISABLE);
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/* RTC interrupt hander is reserved for user */
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//InterruptRegister((IRQ_FUN)BOOT_RTC_Handler, RTC_IRQ, NULL, 4);
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//InterruptEn(RTC_IRQ, 4);
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}
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VOID BOOT_PlatformInit(VOID)
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{
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u32 Temp = 0;
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/* Set SPS lower voltage */
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//Temp = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_SYSCFG0)&0xf0ffffff)|0x6000000);
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//HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_EFUSE_SYSCFG0, Temp);
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/* Driving control of RF1 clock buffer, 11:large current, 00: small current */
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Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_XTAL_CTRL1);
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Temp &= ~(BIT_SYS_XTAL_DRV_RF1(3));
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Temp |= BIT_SYS_XTAL_DRV_RF1(1);
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HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_XTAL_CTRL1, Temp);
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}
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//3 Imgae 2
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VOID BOOT_Image2(VOID)
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{
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int ret = 0;
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u32 OSC8MCali = _SUCCESS;
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#ifdef CONFIG_FPGA
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MPU->RNR = 0; //0xE000ED00, 0x98 MPU Region RNRber Register
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MPU->RBAR = 0; //0xE000ED00, 0x9C MPU Region Base Address Register
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MPU->RASR = 0x6000027; //0xE000ED00, 0xA0 MPU Region Attribute and Size Register
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MPU->CTRL = 7; //0xE000ED00, 0x94 MPU Control Register
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#endif
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#if defined ( __ICCARM__ )
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__iar_data_init_app();
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#endif
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BOOT_InitDebugFlg();
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BOOT_VectorTableOverride(0x1003EFFC);
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/* set CPU clock if needed, default is 125MHz */
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//CPU_ClkSet((u8)(CPU_CLOCK_SEL_VALUE));
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//DelayUs(10);
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#if (defined(CONFIG_CP))
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CPTest_EnterImg2Ok();
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#endif
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DBG_8195A("===== Enter Image 2 ====\n");
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//3 0) Vendor Config function
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//4 Ram Bss Iitial
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u32 BssLen = (__bss_end__ - __bss_start__);
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_memset((void *) __bss_start__, 0, BssLen);
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SystemCoreClockUpdate();
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ret = boot_export_symbol.boot_system_init1();
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//BOOT_PlatformInit();
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OSC8M_CLOCK_GLB = 8388608;
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#if (!defined(CONFIG_FPGA) && !defined(CONFIG_POST_SIM))
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OSC8MCali = OSC8M_Calibration(DISABLE, OSC32K_CALI_32KCYC_064, OSC8M_8388608HZ);
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DelayUs(90);
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DelayUs(90);
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#endif //CONFIG_FPGA
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#ifdef CONFIG_CP
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CPTest_OSCCalibrationOk();
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#endif
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/* Workaround for the GPIOA_7 didn't pull high: it may cause the
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SDIO Device hardware be enabled automatically at power on and then
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GPIOA[7:0] will be used for SDIO device */
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#ifndef CONFIG_SDIO_DEVICE_EN
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// SDIO Pin Mux off
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SDIOD_PIN_FCTRL(OFF);
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#endif
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DBG_8195A("OSC8M: %d \n", OSC8M_Get());
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BOOT_Reason();
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BOOT_RTC_Init();
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#if (!defined(CONFIG_FPGA))
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if (SYSCFG0_BDOption() != SYSCFG_BD_QFN48_MCM_8MBFlash) {
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random_seed = Gen_RandomSeed();
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}
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#endif
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#if defined(CONFIG_WIFI_NORMAL) && defined(CONFIG_NETWORK)
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rtw_efuse_boot_write();
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#endif
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ret = boot_export_symbol.boot_system_init2();
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APP_Start();
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#if defined ( __ICCARM__ )
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// it is dummy code, but IAR linker need this
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__iar_data_init3();
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#endif
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}
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IMAGE2_VALID_PATTEN_SECTION
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const u8 RAM_IMG2_VALID_PATTEN[20] = {
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'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
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(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
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(FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff),
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(FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff),
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(FW_CHIP_VER),
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(FW_BUS_TYPE),
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(FW_INFO_RSV1),
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(FW_INFO_RSV2),
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(FW_INFO_RSV3),
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(FW_INFO_RSV4)
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};
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IMAGE2_ENTRY_SECTION
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RAM_START_FUNCTION gImage2EntryFun0 = {
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BOOT_Image2,
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SOCPS_WakeFromPG
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};
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