mirror of
https://github.com/jialexd/sdk-ameba-v4.0c_180328.git
synced 2024-11-28 09:10:28 +00:00
523 lines
24 KiB
C
Executable file
523 lines
24 KiB
C
Executable file
/**
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******************************************************************************
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* @file rtl8710b_pmc.h
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* @author
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* @version V1.0.0
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* @date 2016-05-17
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* @brief This file provides firmware functions to manage the following
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* functionalities of the soc power management circut:
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* - wakeup timer
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* - wakeup pin
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* - sleep option
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* - sleep mode
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******************************************************************************
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* @attention
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*
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* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
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******************************************************************************
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*/
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#ifndef _RTL8710B_PMC_H_
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#define _RTL8710B_PMC_H_
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/** @addtogroup AmebaZ_Platform
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* @{
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*/
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/** @defgroup PMC
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* @brief PMC driver modules
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* @{
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*/
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/** @addtogroup PMC
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* @verbatim
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*****************************************************************************************
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* Introduction
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*****************************************************************************************
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* we support following soc power save functions:
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* - sleep clock gating
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* - sleep power gating
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* - deep standby
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* - deep sleep
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*
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*****************************************************************************************
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* sleep power gating
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*****************************************************************************************
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* following functions can be used when power gating:
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* -UART0/UART1
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* -TIM4/TIM5
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* -RTC
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* -WIFI
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* -SDIO
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* -USB
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* -I2C0/I2C1
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* -ADC
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* -GPIO
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* -REGU timer
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* -normal wakepin
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* -ANA timer
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* following functions will be closed when power gating:
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* -UART2 LOGUART
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* -TIM0-TIM3
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* -SPIC flash
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*
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*****************************************************************************************
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* deep standby
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*****************************************************************************************
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* following functions can be used when deep standby:
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* -RTC
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* -REGU timer
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* -normal wakepin
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* -ANA timer
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*
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*****************************************************************************************
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* deep sleep
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*****************************************************************************************
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* following functions can be used when deep standby:
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* -REGU timer
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* -REGU wakepin
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*
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*****************************************************************************************
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* wakepin (A18/A5/A22/A23: mux normal wakepin and REGU wakepin)
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*****************************************************************************************
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* normal wakepin:
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* -SLP_CG
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* -SLP_PG
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* -STDBY
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* REGU wakepin:
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* -just used in DSLP (1.2V closed)
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* -just support high acive, so this pin should pull low on your board
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*
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*****************************************************************************************
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*****************************************************************************************
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* SLP & SNZ power option
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*****************************************************************************************
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* BIT_SYSON_PMOPT_SLP_EN_SWR & BIT_SYSON_PMOPT_SNZ_EN_SWR
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* -we have two 1.2V LDO
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* -BIG LDO: SWR mode or LDO mode (can config )
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* -LITTLE LDO: a little 1.2v LDO
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* -BIT_SYSON_PMOPT_SLP_EN_SWR
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* -ENABLE/DISABLE BIG LDO when SLP
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* BIT_SYSON_PMOPT_SNZ_EN_SWR
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* -ENABLE/DISABLE BIG LDO when SNZ, WIFI & ADC need open BIG LDO when SNZ
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*
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* BIT_SYSON_PMOPT_SLP_EN_PWM & BIT_SYSON_PMOPT_SNZ_EN_PWM
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* -BIT_SYSON_PMOPT_SLP_EN_PWM
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* -ENABLE/DISABLE LDO heavy loading current mode when SLP
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* -BIT_SYSON_PMOPT_SNZ_EN_PWM
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* -ENABLE/DISABLE heavy loading current mode when SNZ, WIFI & ADC need heavy loading when SNZ
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*
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* BIT_SYSON_PMOPT_SLP_XTAL_EN & BIT_SYSON_PMOPT_SNZ_XTAL_EN
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* -WIFI and SOC both need XTAL when work,
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* -but WIFI have individual option to control XTAL, so BIT_SYSON_PMOPT_SNZ_XTAL_EN not needed
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*
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* BIT_SYSON_PMOPT_SLP_SYSPLL_EN & BIT_SYSON_PMOPT_SNZ_SYSPLL_EN
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* -WIFI and SOC both have individual PLL, here is SOC 500M PLL
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* -So BIT_SYSON_PMOPT_SNZ_SYSPLL_EN not needed
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*
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* BIT_SYSON_SNFEVT_WIFI_MSK = 1 & BIT_SYSON_BYPASS_SNZ_SLP = 1
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* - after OS suspend, platform will enter SNZ and close CPU, then platform enter sleep mode when WIFI 32K
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* - BIT_SYSON_PMOPT_SNZ_EN_SOC should never open, or CPU will not close when platform will enter SNZ
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*
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* BIT_SYSON_SNFEVT_WIFI_MSK = 1 & BIT_SYSON_BYPASS_SNZ_SLP = 0 (not use this config)
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* - after OS suspend, platform will enter sleep mode & close CPU after WIFI 32K
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*****************************************************************************************
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* @endverbatim
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup PMC_Exported_Constants PMC Exported Constants
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* @{
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*/
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/** @defgroup PMC_WakePin_definitions
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* @{
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*/
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#define WAKEUP_BY_GPIO_NONE ((u32)(0x00000000))
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#define WAKEUP_BY_GPIO_WAKEUP0_LOW ((u32)(0x00000001)) //PA18
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#define WAKEUP_BY_GPIO_WAKEUP0_HIG ((u32)(0x00000101))
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#define WAKEUP_BY_GPIO_WAKEUP1_LOW ((u32)(0x00000001 << 1)) //PA5
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#define WAKEUP_BY_GPIO_WAKEUP1_HIG ((u32)(0x00000101 << 1))
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#define WAKEUP_BY_GPIO_WAKEUP2_LOW ((u32)(0x00000001 << 2)) //PA22
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#define WAKEUP_BY_GPIO_WAKEUP2_HIG ((u32)(0x00000101 << 2))
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#define WAKEUP_BY_GPIO_WAKEUP3_LOW ((u32)(0x00000001 << 3)) //PA23
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#define WAKEUP_BY_GPIO_WAKEUP3_HIG ((u32)(0x00000101 << 3))
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/**
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* @}
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*/
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/** @defgroup SOCPS_PS_Mode_definitions
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* @{
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*/
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#define SOCPS_MODE_DSLP ((u32)(0x00000001 << 0))
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#define SOCPS_MODE_DSTBY ((u32)(0x00000001 << 1))
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#define SOCPS_MODE_SLP ((u32)(0x00000001 << 2))
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/**
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* @}
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*/
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/** @defgroup SOCPS_PS_ANA_Clk_definitions
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* @{
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*/
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#define ANACK_250K ((u32)0x00000000)
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#define ANACK_4M ((u32)0x00000001)
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/**
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* @}
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*/
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/** @defgroup SOCPS_PS_Calibration_Clk_definitions
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* @{
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*/
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#define ANACK ((u32)0x00000000)
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#define A33CK ((u32)0x00000001)
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/**
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* @}
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*/
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/** @defgroup SOCPS_PS_Wakeup_Pin_definitions
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* @{
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*/
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#define WAKUP_0 ((u32)0x00000000)/*!< _PA_18 */
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#define WAKUP_1 ((u32)0x00000001)/*!< _PA_5 */
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#define WAKUP_2 ((u32)0x00000002)/*!< _PA_22 */
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#define WAKUP_3 ((u32)0x00000003)/*!< _PA_23 */
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/**
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* @}
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*/
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/** @defgroup SOCPS_PS_Wakeup_Pin_Mask_definitions
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* @{
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*/
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#define WAKUP_0_MASK ((u32)(0x00000001 << 0))/*!< _PA_18 */
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#define WAKUP_1_MASK ((u32)(0x00000001 << 1))/*!< _PA_5 */
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#define WAKUP_2_MASK ((u32)(0x00000001 << 2))/*!< _PA_22 */
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#define WAKUP_3_MASK ((u32)(0x00000001 << 3))/*!< _PA_23 */
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#define IS_WAKEPIN_MASK(MASK) (((MASK) & 0x0000000F) != 0)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup PMC_Exported_Functions PMC Exported Functions
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* @{
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*/
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_LONG_CALL_ void SOCPS_BackupCPUClk(void);
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_LONG_CALL_ void SOCPS_RestoreCPUClk(void);
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_LONG_CALL_ void SOCPS_BootFromPS(u32 NewStatus);
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_LONG_CALL_ void SOCPS_TrapPin(u32 NewStatus);
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_LONG_CALL_ void SOCPS_ANACKSel(u32 ANACLK);
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_LONG_CALL_ void SOCPS_SetWakeEvent(u32 Option, u32 NewStatus);
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_LONG_CALL_ void SOCPS_ClearWakeEvent(void);
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_LONG_CALL_ void SOCPS_WakePinsCtrl(u32 GpioOption);
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_LONG_CALL_ void SOCPS_WakePinCtrl(u32 Index, u32 Polarity);
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_LONG_CALL_ void SOCPS_SetANATimer(u32 SDuration, u32 NewStatus);
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_LONG_CALL_ void SOCPS_SetReguWakepin(void);
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_LONG_CALL_ void SOCPS_SetReguTimer(u32 SDuration, u32 CalibData);
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_LONG_CALL_ void SOCPS_PWRMode(u32 pwrmode, u32 snz_bypss);
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_LONG_CALL_ void SOCPS_PWROption(u32 pwrmgt_option);
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_LONG_CALL_ void SOCPS_PWROptionExt(u32 pwrmgt_option);
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_LONG_CALL_ void SOCPS_SNZMode(u32 SnzMask, u32 NewStatus);
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_LONG_CALL_ u32 SOCPS_CLKCal(u32 ClkSel);
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_LONG_CALL_ void SOCPS_DeepStandby(void);
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_LONG_CALL_ void SOCPS_DeepSleep(void);
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_LONG_CALL_ void SOCPS_SleepPG(void);
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_LONG_CALL_ void SOCPS_SetReguWakepins(u32 PinMask);
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_LONG_CALL_ void SOCPS_ReguTimerCmd(u32 NewStatus);
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_LONG_CALL_ void SOCPS_WakePinDebounce(u32 Index, u32 Status);
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_LONG_CALL_ void SOCPS_DeepStandby_RAM(void);
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_LONG_CALL_ void SOCPS_SleepPG_RAM(void);
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_LONG_CALL_ void SOCPS_DeepSleep_RAM(void);
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_LONG_CALL_ void SOCPS_FlashPin_PullUp_RAM(u32 NewStatus, u32 ChipIndex);
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void SOCPS_SetReguWakepins_RAM(u32 PinMask);
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void SOCPS_ReguTimerCmd_RAM(u32 NewStatus);
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void SOCPS_WakePinDebounce_RAM(u32 Index, u32 Status);
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void SOCPS_SetReguTimer_RAM(u32 SDuration, u32 CalibData);
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void SOCPS_SleepCG(void);
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int SOCPS_DsleepWakeReason(void);
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int SOCPS_DstandbyWakeReason(void);
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int SOCPS_DstandbyWakeReason_gpio(void);
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/**
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* @}
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*/
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/* Registers Definitions --------------------------------------------------------*/
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/**************************************************************************//**
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* @defgroup PMC_Register_Definitions PMC Register Definitions
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* @{
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*****************************************************************************/
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/**************************************************************************//**
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* @defgroup REG_SYS_ANA_TIM_CTRL
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* @{
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*****************************************************************************/
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#define BIT_SYS_ANACK_TU_TIME(x) (((x) & 0x0000003f) << 16)
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#define BIT_SYS_DSBYCNT_EN (0x00000001 << 15)
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#define BIT_SYS_DSTDY_TIM_SCAL(x) (((x) & 0x0000000f) << 8)
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#define BIT_SYS_DSTBY_TIM_PERIOD(x) (((x) & 0x000000ff) << 0)
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_DSLP_TIM_CTRL
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* @{
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*****************************************************************************/
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#define BIT_SYS_REGU_ASIF_EN(x) (((x) & 0x000000ff) << 24)
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#define BIT_SYS_REGU_ASIF_THP_DA(x) (((x) & 0x00000003) << 20)
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#define BIT_SYS_REGU_ASIF_TPD_CK(x) (((x) & 0x00000003) << 18)
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#define BIT_SYS_REGU_ASIF_TSP_DA(x) (((x) & 0x3) << 16)
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#define BIT_SYS_REGU_ASIF_POLL (0x00000001 << 15)
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#define BIT_SYS_REGU_ASIF_MODE (0x00000001 << 14)
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#define BIT_SYS_REGU_ASIF_WE (0x00000001 << 12)
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#define BIT_SYS_REGU_ASIF_AD(x) (((x) & 0x0000000f) << 8)
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#define BIT_SYS_REGU_ASIF_WD(x) (((x) & 0x000000ff) << 0)
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_DSLP_TIM_CAL_CTRL
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* @{
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*****************************************************************************/
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#define BIT_SYS_DSLP_TIM_EN (0x00000001 << 24)
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#define BIT_SYS_DSLP_TIM_PERIOD(x) (((x) & 0x7fffff) << 0)
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_GPIO_DSTBY_WAKE_CTRL0
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* @{
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*****************************************************************************/
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#define BIT_SYS_WAKEPIN3_WEVENT_STS (0x00000001 << 27)
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#define BIT_SYS_WAKEPIN2_WEVENT_STS (0x00000001 << 26)
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#define BIT_SYS_WAKEPIN1_WEVENT_STS (0x00000001 << 25)
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#define BIT_SYS_WAKEPIN0_WEVENT_STS (0x00000001 << 24)
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#define BIT_SYS_WAKEPIN3_PULL_CTRL_EN (0x00000001 << 19)
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#define BIT_SYS_WAKEPIN2_PULL_CTRL_EN (0x00000001 << 18)
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#define BIT_SYS_WAKEPIN1_PULL_CTRL_EN (0x00000001 << 17)
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#define BIT_SYS_WAKEPIN0_PULL_CTRL_EN (0x00000001 << 16)
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#define BIT_SYS_WAKEPIN3_WINT_MODE (0x00000001 << 11)
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#define BIT_SYS_WAKEPIN2_WINT_MODE (0x00000001 << 10)
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#define BIT_SYS_WAKEPIN1_WINT_MODE (0x00000001 << 9)
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#define BIT_SYS_WAKEPIN0_WINT_MODE (0x00000001 << 8)
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#define BIT_SYS_WAKEPIN3_PIN_EN (0x00000001 << 3)
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#define BIT_SYS_WAKEPIN2_PIN_EN (0x00000001 << 2)
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#define BIT_SYS_WAKEPIN1_PIN_EN (0x00000001 << 1)
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#define BIT_SYS_WAKEPIN0_PIN_EN (0x00000001 << 0)
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#define MARSK_WAKEPIN0_HIGH_WAKE (BIT_SYS_WAKEPIN0_PIN_EN | \
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BIT_SYS_WAKEPIN0_WINT_MODE | \
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BIT_SYS_WAKEPIN0_PULL_CTRL_EN | \
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BIT_SYS_WAKEPIN0_WEVENT_STS)
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#define MARSK_WAKEPIN0_LOW_WAKE (BIT_SYS_WAKEPIN0_PIN_EN | \
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BIT_SYS_WAKEPIN0_PULL_CTRL_EN | \
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BIT_SYS_WAKEPIN0_WEVENT_STS)
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_GPIO_DSTBY_WAKE_CTRL1
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* @{
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*****************************************************************************/
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#define BIT_SYS_BTCLKDET_MODE (0x00000001 << 27)
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#define BIT_SYS_BTCLKDET_DEBOUNCE_EN (0x00000001 << 26)
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#define BIT_SYS_BTCLKDET_TIM_SCAL (0x00000003 << 24)
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#define BIT_SYS_WAKEPIN3_SHTDN_N (0x00000001 << 19)
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#define BIT_SYS_WAKEPIN2_SHTDN_N (0x00000001 << 18)
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#define BIT_SYS_WAKEPIN1_SHTDN_N (0x00000001 << 17)
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#define BIT_SYS_WAKEPIN0_SHTDN_N (0x00000001 << 16)
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#define BIT_SYS_WINT_DEBOUNCE_TIM_SCAL(x) (((x) & 0x3) << 8)
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#define BIT_SYS_WAKEPIN3_WINT_DEBOUNCE_EN (0x00000001 << 3)
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#define BIT_SYS_WAKEPIN2_WINT_DEBOUNCE_EN (0x00000001 << 2)
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#define BIT_SYS_WAKEPIN1_WINT_DEBOUNCE_EN (0x00000001 << 1)
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#define BIT_SYS_WAKEPIN0_WINT_DEBOUNCE_EN (0x00000001 << 0)
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_SLP_WAKE_EVENT_MSK0
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* @{
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*****************************************************************************/
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#define BIT_SYSON_WEVT_BOR2_MSK (0x00000001 << 30) /*!< BOR2 wakeup */
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#define BIT_SYSON_WEVT_GPIO_DSTBY_MSK (0x00000001 << 29) /*!< 1: enable Wakepin Wakeup DSTBY event */
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#define BIT_SYSON_WEVT_A33_AND_A33GPIO_MSK (0x00000001 << 28) /*!< 1: enable REGU A33(deepsleep mode, A33 Timer & A33 wakepin) Wakeup event */
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#define BIT_SYSON_WEVT_ADC_MSK (0x00000001 << 26) /*!< 1: enable ADC Wakeup event */
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#define BIT_SYSON_WEVT_SDIO_MSK (0x00000001 << 14) /*!< 1: enable SDIO Wakeup event */
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#define BIT_SYSON_WEVT_RTC_MSK (0x00000001 << 13) /*!< 1: enable RTC Wakeup event */
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#define BIT_SYSON_WEVT_UART1_MSK (0x00000001 << 12) /*!< 1: enable UART1 Wakeup event */
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#define BIT_SYSON_WEVT_UART0_MSK (0x00000001 << 11) /*!< 1: enable UART0 Wakeup event */
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#define BIT_SYSON_WEVT_I2C1_MSK (0x00000001 << 10) /*!< 1: enable I2C1 Wakeup event */
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#define BIT_SYSON_WEVT_I2C0_MSK (0x00000001 << 9) /*!< 1: enable I2C0 Wakeup event */
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#define BIT_SYSON_WEVT_WLAN_MSK (0x00000001 << 8) /*!< 1: enable WLAN Wakeup event */
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#define BIT_SYSON_WEVT_I2C1_ADDRMATCH_MSK (0x00000001 << 7) /*!< 1:enable wakeup event of I2C1 RX address match */
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#define BIT_SYSON_WEVT_I2C0_ADDRMATCH_MSK (0x00000001 << 6) /*!< 1:enable wakeup event of I2C0 RX address match */
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#define BIT_SYSON_WEVT_USB_MSK (0x00000001 << 5) /*!< 1: enable wakeup event of usb resume from suspend mode */
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#define BIT_SYSON_WEVT_GPIO_MSK (0x00000001 << 4) /*!< 1: enable GPIO Wakeup event */
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#define BIT_SYSON_WEVT_CHIP_EN_MSK (0x00000001 << 3) /*!< 1: enable chip en wakeup event */
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#define BIT_SYSON_WEVT_OVER_CURRENT_MSK (0x00000001 << 2) /*!< 1: enable OCP wakeup event, REGU OVER_CURRENT */
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#define BIT_SYSON_WEVT_GTIM_MSK (0x00000001 << 1) /*!< 1: enable Gtimer 4/5 Wakeup SYSON event */
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#define BIT_SYSON_WEVT_SYSTIM_MSK (0x00000001 << 0) /*!< 1: enable SYS Timer(ANA Timer, deepstandby mode) Wakeup SYSON event */
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_SLP_WAKE_EVENT_STATUS0
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* @{
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*****************************************************************************/
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#define BIT_SYSON_WEVT_BOR2_STS (0x00000001 << 30)
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#define BIT_SYSON_WEVT_GPIO_DSTBY_STS (0x00000001 << 29)
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#define BIT_SYSON_WEVT_A33_STS (0x00000001 << 28)
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#define BIT_SYSON_WEVT_ADC_STS (0x00000001 << 26)
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#define BIT_SYSON_WEVT_SDIO_STS (0x00000001 << 14)
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#define BIT_SYSON_WEVT_RTC_STS (0x00000001 << 13)
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#define BIT_SYSON_WEVT_UART1_STS (0x00000001 << 12)
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#define BIT_SYSON_WEVT_UART0_STS (0x00000001 << 11)
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#define BIT_SYSON_WEVT_I2C1_STS (0x00000001 << 10)
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#define BIT_SYSON_WEVT_I2C0_STS (0x00000001 << 9)
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#define BIT_SYSON_WEVT_WLAN_STS (0x00000001 << 8)
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#define BIT_SYSON_WEVT_I2C1_ADDRMATCH_STS (0x00000001 << 7)
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#define BIT_SYSON_WEVT_I2C0_ADDRMATCH_STS (0x00000001 << 6)
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#define BIT_SYSON_WEVT_USB_STS (0x00000001 << 5)
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#define BIT_SYSON_WEVT_GPIO_STS (0x00000001 << 4)
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#define BIT_SYSON_WEVT_CHIP_EN_STS (0x00000001 << 3)
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#define BIT_SYSON_WEVT_OVER_CURRENT_STS (0x00000001 << 2)
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#define BIT_SYSON_WEVT_GTIM_STS (0x00000001 << 1)
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#define BIT_SYSON_WEVT_SYSTIM_STS (0x00000001 << 0)
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_SNF_WAKE_EVENT_MSK0
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* @{
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*****************************************************************************/
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#define BIT_SYSON_SNFEVT_WIFI_MSK (0x00000001 << 1) /*!< 1: enable wlan power on wakeup event interrupt; 0: Disable */
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#define BIT_SYSON_SNFEVT_ADC_MSK (0x00000001 << 0) /*!< 1: enable ADC Wakeup SYSON event from GTIM3 interrupt under oneshot mode ; 0: disable the event to wakeup system */
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_SNF_WAKE_EVENT_STATUS
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* @{
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*****************************************************************************/
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#define BIT_SYSON_SNFEVT_WIFI_STS (0x00000001 << 1) /*!< 1: indicate wlan power on wakeup status */
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#define BIT_SYSON_SNFEVT_ADC_STS (0x00000001 << 0) /*!< 1: indicate ADC wakeup event status */
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_PWRMGT_CTRL
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* @{
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*****************************************************************************/
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#define BIT_SYSON_PMCOPT_BKPOFIMK2 (0x00000001 << 18) /*!< Enable wakeup interrupt to break power off flow during power off stage2 */
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#define BIT_SYSON_PMCOPT_BKPOFIMK1 (0x00000001 << 17) /*!< Enable wakeup interrupt to break power off flow during power off stage1 */
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#define BIT_SYSON_PMCOPT_BKPOFIMK0 (0x00000001 << 16) /*!< Enable wakeup interrupt to break power off flow during power off stage0 */
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#define BIT_SYSON_BYPASS_SNZ_SLP (0x00000001 << 8) /*!< If WIFI WOWLAN open we should open it, or SOC will sleep when WIFI active */
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#define BIT_SYSON_PM_CMD_SLP (0x00000001 << 2) /*!< 1: command SYSON SM to enter sleep state, when PMC finishes the process, this bit will be auto clear to 0 */
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#define BIT_SYSON_PM_CMD_DSTBY (0x00000001 << 1) /*!< 1: command SYSON SM to enter deep standby state,when PMC finishes the process, this bit will be auto clear to 0 */
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#define BIT_SYSON_PM_CMD_DSLP (0x00000001 << 0) /*!< 1: command SYSON SM to enter deep sleep state,when PMC finishes the process, this bit will be auto clear to 0 */
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_PWRMGT_OPTION
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* @{
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*****************************************************************************/
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#define BIT_SYSON_PMOPT_NORM_SYSCLK_SEL (0x00000001 << 30) /*!< 1: select system PLL clock as CPU clock when enter into active mode; 0: select ANA clock */
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#define BIT_SYSON_PMOPT_NORM_SYSPLL_EN (0x00000001 << 29) /*!< 1: enable syspem PLL when enter into active mode; 0: disable SYSPLL */
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#define BIT_SYSON_PMOPT_NORM_XTAL_EN (0x00000001 << 28) /*!< 1: enable XTAL when enter into active mode; 0: disable XTAL */
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#define BIT_SYSON_PMOPT_NORM_EN_PWM (0x00000001 << 26) /*!< 1: power enable SWR/LDO output heavy loading current mode when enter into power mode */
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#define BIT_SYSON_PMOPT_SNZ_MEM2_EN (0x00000001 << 24) /*!< 1: enable MEM2 when enter into snooze mode */
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#define BIT_SYSON_PMOPT_SNZ_MEM1_EN (0x00000001 << 23) /*!< 1: enable MEM1 when enter into snooze mode */
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#define BIT_SYSON_PMOPT_SNZ_MEM0_EN (0x00000001 << 22) /*!< 1: enable MEM0 when enter into snooze mode */
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#define BIT_SYSON_PMOPT_SNZ_SYSPLL_EN (0x00000001 << 21) /*!< 1: enable syspem PLL when enter into snooze mode, wifi not use, adc use */
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#define BIT_SYSON_PMOPT_SNZ_XTAL_EN (0x00000001 << 20) /*!< 1: enable XTAL when enter into snooze mode, wifi not use, adc use */
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#define BIT_SYSON_PMOPT_SNZ_EN_SOC (0x00000001 << 19) /*!< 1: power enable SOC platform when enter into snooze mode */
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#define BIT_SYSON_PMOPT_SNZ_EN_PWM (0x00000001 << 18) /*!< 1: power enable SWR/LDO output heavy loading current mode when enter into snooze mode, wifi use it when close BIT_SYSON_PMOPT_SLP_EN_PWM*/
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#define BIT_SYSON_PMOPT_SNZ_EN_SWR (0x00000001 << 17) /*!< 1: power enable SWR/LDO 1.2V when enter into snooze mode, wifi use it when close BIT_SYSON_PMOPT_SLP_EN_SWR*/
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#define BIT_SYSON_PMOPT_SLP_MEM2_EN (0x00000001 << 16) /*!< 1: enable MEM2 when enter into sleep mode, 64k */
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#define BIT_SYSON_PMOPT_SLP_MEM1_EN (0x00000001 << 15) /*!< 1: enable MEM1 when enter into sleep mode, 64k */
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#define BIT_SYSON_PMOPT_SLP_MEM0_EN (0x00000001 << 14) /*!< 1: enable MEM0 when enter into sleep mode, 128k */
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#define BIT_SYSON_PMOPT_SLP_SYSPLL_EN (0x00000001 << 13) /*!< 1: enable syspem PLL when enter into sleep mode; 0: disable SYSPLL */
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#define BIT_SYSON_PMOPT_SLP_XTAL_EN (0x00000001 << 12) /*!< 1: enable XTAL when enter into sleep mode; 0: disable XTAL */
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#define BIT_SYSON_PMOPT_SLP_EN_SOC (0x00000001 << 11) /*!< 1: power enable SOC platform when enter into sleep mode; 0: power off SoC domain */
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#define BIT_SYSON_PMOPT_SLP_EN_PWM (0x00000001 << 10) /*!< 1: power enable SWR/LDO output heavy loading current mode when enter into sleep mode, wifi on can not */
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#define BIT_SYSON_PMOPT_SLP_EN_SWR (0x00000001 << 9) /*!< 1: power enable BIG 1.2V LDO (SWR/LDO can cfg) when enter into sleep mode, just keep little LDO; wifi on can not */
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#define BIT_SYSON_PMOPT_SLP_LPLDO_SEL (0x00000001 << 8) /*!< V12H LDO operation mode selection for sleep, 1: normal, 0: standby(low current mode), always-on power is here */
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#define BIT_SYSON_PMOPT_DSTBY_LPLDO_SEL (0x00000001 << 0) /*!< V12H LDO operation mode selection for deep standby, 1: normal, 0: standby */
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/* 0x74000100 */
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#define BIT_SYSON_PMOPT_MASK (BIT_SYSON_PMOPT_NORM_EN_PWM | \
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BIT_SYSON_PMOPT_NORM_XTAL_EN | \
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BIT_SYSON_PMOPT_NORM_SYSPLL_EN | \
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BIT_SYSON_PMOPT_NORM_SYSCLK_SEL | \
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BIT_SYSON_PMOPT_SNZ_EN_SWR | \
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BIT_SYSON_PMOPT_SNZ_EN_PWM | \
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BIT_SYSON_PMOPT_SNZ_MEM0_EN | \
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BIT_SYSON_PMOPT_SNZ_MEM1_EN | \
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BIT_SYSON_PMOPT_SNZ_MEM2_EN)
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_PWRMGT_OPTION_EXT
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* @{
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|
*****************************************************************************/
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#define BIT_SYSON_PMOPT_SLP_BYPS_WL (0x00000001 << 4) /*!< 1: CM4 can enter sleep mode with no regard of wlan's power state */
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#define BIT_SYSON_PMOPT_SLP_REDUCE_VOL (0x00000001 << 3) /*!< 1: decrease SWR/LDO 1.2V voltage level when enter into sleep mode(decrease digital power); */
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#define BIT_SYSON_PMOPT_SLP_ANACK_SEL (0x00000001 << 2) /*!< 1: set ANA clock to 4MHz when enter into power mode; */
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#define BIT_SYSON_PMOPT_SLP_ANACK_EN (0x00000001 << 1) /*!< 1: enable syson register clock when enter into sleep mode; */
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#define BIT_SYSON_PMOPT_SLP_SWR_ADJ (0x00000001 << 0) /*!< 1: decrease VD12H 1.2V voltage level when enter into sleep mode(decrease always on power, should better not use); */
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_DSLP_WEVENT
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|
* @{
|
|
*****************************************************************************/
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#define BIT_SYSON_DSLP_GPIO (0x00000001 << 2) /*!< REGU GPIO wake33 event */
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#define BIT_SYSON_DSLP_WTIMER33 (0x00000001 << 0) /*!< REGU Timer33 wake event */
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/** @} */
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/** @} */
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/**
|
|
* @}
|
|
*/
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|
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/**
|
|
* @}
|
|
*/
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|
|
/* Other Definitions --------------------------------------------------------*/
|
|
#define REG_VDR_ANACK_CAL_CTRL 0xA0
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|
#define NVIC_ICPR0_PS_MASK 0xFFFFFFFF
|
|
|
|
#ifdef CONFIG_CHIP_A_CUT
|
|
#define SOCPS_SET_REGUTIMER SOCPS_SetReguTimer_RAM
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|
#else
|
|
#define SOCPS_SET_REGUTIMER SOCPS_SetReguTimer
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#endif
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#endif //_RTL8710B_PMC_H_
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/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
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