mirror of
https://github.com/jialexd/sdk-ameba-v4.0c_180328.git
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427 lines
15 KiB
C
Executable file
427 lines
15 KiB
C
Executable file
/**
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******************************************************************************
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* @file rtl8711b_clk.h
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* @author
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* @version V1.0.0
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* @date 2016-05-17
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* @brief This file provides firmware functions to manage the following
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* functionalities of clock control:
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* - NCO32K clock
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* - NCO8M clock
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* - CPU clock
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* - XTAL clock get
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* - OSC32K clock
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* - EXT32K clock
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******************************************************************************
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* @attention
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*
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* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
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******************************************************************************
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*/
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#ifndef _RTL8710B_CLK_H_
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#define _RTL8710B_CLK_H_
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/** @addtogroup AmebaZ_Platform
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* @{
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*/
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/** @defgroup CLOCK
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* @brief CLOCK driver modules
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* @{
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*/
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/** @addtogroup CLOCK
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* @verbatim
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*****************************************************************************************
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* NCO32K
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*****************************************************************************************
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* -RTC clock in
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* -TIM0-TIM3 clock in
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* -WIFI 32K clock in
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*****************************************************************************************
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* OSC32K OSC8M
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*****************************************************************************************
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* -OSC32K is used to calibration OSC8M
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* -OSC8M is used for LP UART when SOC suspend and close XTAL
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*****************************************************************************************
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*****************************************************************************************
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* NCO8M
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*****************************************************************************************
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* -used for LP UART when SOC active
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* -Clock in is XTAL (40MHz)
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* -Clock out is 8MHz
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*
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*****************************************************************************************
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* CPU clock
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*****************************************************************************************
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* -CLK_125M: 125000000
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* -CLK_62_5M: 62500000
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* -CLK_31_25M: 31250000
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* -CLK_16_625M: 15625000
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* -CLK_XTAL: XTAL
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* -CLK_ANA_4M: 4000000
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*
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*****************************************************************************************
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* XTAL clock
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*****************************************************************************************
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* -Get XTAL clock from EFUSE setting:
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* -40000000
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* -25000000
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* -13000000
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* -19200000
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* -20000000
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* -26000000
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* -38400000
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* -17664000
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* -16000000
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* -14318000
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* -12000000
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* -52000000
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* -48000000
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* -26000000
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* -27000000
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* -24000000
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*****************************************************************************************
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* EXT32K
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*****************************************************************************************
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* -External 32K: 32K clock from external 32k source
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* -Internal 32K: 32K clock from internal 32K source: NCO32K
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*
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*****************************************************************************************
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* @endverbatim
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup CLK_Exported_Constants CLK Exported Constants
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* @{
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*/
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/** @defgroup CPU_CLK_definitions
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* @{
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*/
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#define CLK_125M 0
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#define CLK_62_5M 1
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#define CLK_31_25M 2
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#define CLK_16_625M 3
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#define CLK_XTAL 4
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#define CLK_ANA_4M 5
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/**
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* @}
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*/
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/** @defgroup OSC32K_CLK_definitions
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* @note just used by function OSC32K_Calibration or OSC8M_Calibration
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* @{
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*/
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#define OSC32K_CALI_32KCYC_004 0
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#define OSC32K_CALI_32KCYC_008 1
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#define OSC32K_CALI_32KCYC_016 2
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#define OSC32K_CALI_32KCYC_032 3
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#define OSC32K_CALI_32KCYC_064 4
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#define OSC32K_CALI_32KCYC_128 5
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#define OSC32K_CALI_32KCYC_256 6
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#define OSC32K_CALI_32KCYC_512 7
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/**
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* @}
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*/
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/** @defgroup OSC8M_CLK_definitions
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* @note just used by function OSC8M_Calibration
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* @{
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*/
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#define OSC8M_8388608HZ 0
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#define OSC8M_8192000HZ 1
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#define OSC8M_8000000HZ 2
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#define OSC8M_16777216HZ 3
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup NCO32K_CLK_Exported_Functions NCO32K_CLK Exported Functions
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* @{
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*/
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_LONG_CALL_ void NCO32K_Init(u32 clk_out, u32 clk_ref, u8 calibration_cycles, u8 calibration_thrs);
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/**
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* @}
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*/
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/** @defgroup EXT32K_CLK_Exported_Functions EXT32K_CLK Exported Functions
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* @{
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*/
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_LONG_CALL_ void EXT32K_Cmd(u32 NewStatus);
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/**
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* @}
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*/
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/** @defgroup NCO8M_CLK_Exported_Functions NCO8M_CLK Exported Functions
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* @{
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*/
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_LONG_CALL_ void NCO8M_Init(u32 clk_ref_M, u32 clk_out_M);
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_LONG_CALL_ void NCO8M_Cmd(u32 NewState);
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/**
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* @}
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*/
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/** @defgroup CPU_CLK_Exported_Functions CPU_CLK Exported Functions
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* @{
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*/
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_LONG_CALL_ u32 CPU_ClkGet(u8 Is_FPGA);
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_LONG_CALL_ void CPU_ClkSet(u8 CpuType);
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/**
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* @}
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*/
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/** @defgroup XTAL_CLK_Exported_Functions XTAL_CLK Exported Functions
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* @{
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*/
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_LONG_CALL_ u32 XTAL_ClkGet(void);
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/**
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* @}
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*/
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/** @defgroup OSC_CLK_Exported_Functions OSC_CLK Exported Functions
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* @{
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*/
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_LONG_CALL_ u32 OSC8M_Calibration(u32 LOG_EN, u32 CaliCycles, u32 TargetClock);
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_LONG_CALL_ void OSC32K_Calibration(u32 LOG_EN, u32 CaliCycles);
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_LONG_CALL_ void OSC32K_Cmd(u32 NewStatus);
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_LONG_CALL_ u32 OSC8M_Get(void);
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/**
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* @}
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*/
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/** @defgroup ISO_CTL_Exported_Functions ISO_CTL Exported Functions
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* @{
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*/
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_LONG_CALL_ void ISO_Set(u32 BitMask, u32 NewState);
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/**
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* @}
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*/
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/** @defgroup PLL_Exported_Functions PLL Exported Functions
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* @{
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*/
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_LONG_CALL_ void PLL0_Set(u32 BitMask, u32 NewState);
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_LONG_CALL_ void PLL1_Set(u32 BitMask, u32 NewState);
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_LONG_CALL_ void PLL2_Set(u32 BitMask, u32 NewState);
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_LONG_CALL_ void PLL3_Set(u32 BitMask, u32 NewState);
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/**
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* @}
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*/
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/** @defgroup XTAL_CTL_Exported_Functions XTAL_CTL Exported Functions
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* @{
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*/
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_LONG_CALL_ void XTAL0_Set(u32 BitMask, u32 NewState);
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_LONG_CALL_ void XTAL1_Set(u32 BitMask, u32 NewState);
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_LONG_CALL_ void XTAL2_Set(u32 BitMask, u32 NewState);
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/**
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* @}
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*/
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/* Registers Definitions --------------------------------------------------------*/
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/**************************************************************************//**
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* @defgroup CLK_Register_Definitions CLK Register Definitions
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* @{
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*****************************************************************************/
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/**************************************************************************//**
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* @defgroup NCO1_CLK_INFO
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* @{
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*****************************************************************************/
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#define NCO1_BIT_32K_CLK_OUT_RDY (0x00000001 << 24)
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/** @} */
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/**************************************************************************//**
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* @defgroup NCO1_CTRL
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* @{
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*****************************************************************************/
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#define NCO1_BIT_32K_CLK_EN (0x00000001 << 16)
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#define NCO1_BIT_REF_CLK_EN (0x00000001 << 17)
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#define NCO1_BIT_CALI_CYCLES (0x00F00000)
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#define NCO1_BIT_CALI_THRS (0x7F000000)
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/** @} */
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/**************************************************************************//**
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* @defgroup NCO8M
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* @{
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*****************************************************************************/
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#define NCO2_BIT_OUT_CLK_EN (0x00000001)
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_CLK_CTRL0
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* @{
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*****************************************************************************/
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#define BIT_SOC_OCP_IOBUS_CK_EN (0x00000001 << 2)
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#define BIT_SYSON_CK_EELDR_EN (0x00000001 << 1)
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#define BIT_SYSON_CK_SYSREG_EN (0x00000001 << 0)
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_CLK_CTRL1
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* @{
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*****************************************************************************/
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#define BIT_PESOC_EXT32K_CK_SEL (0x00000001 << 8)
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#define BIT_PESOC_OCP_CPU_CK_SEL (0x00000007 << 4)
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#define BIT_PESOC_EELDR_CK_SEL (0x00000001 << 0)
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_XTAL_CTRL0
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* @{
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*****************************************************************************/
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#define BIT_SYS_XTAL_XQSEL_RF (0x00000001 << 31)
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#define BIT_SYS_XTAL_GATED_OK0 (0x00000001 << 30)
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#define BIT_SYS_XTAL_SC_XO(x) (((x) & 0x0000003f) << 24)
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#define BIT_SYS_XTAL_SC_XI(x) (((x) & 0x0000003f) << 18)
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#define BIT_SYS_XTAL_GMN(x) (((x) & 0x0000001f) << 13)
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#define BIT_SYS_XTAL_GMP(x) (((x) & 0x0000001f) << 8)
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#define BIT_SYS_XTAL_GSPL_EN (0x00000001 << 4) /*!< 1: Gate PLL ref clock from XTAL ; 0: not gated */
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#define BIT_SYS_XTAL_EN (0x00000001 << 1)
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#define BIT_SYS_XTAL_BGMB_EN (0x00000001 << 0)
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_XTAL_CTRL1
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* @{
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*****************************************************************************/
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#define BIT_SYS_XTAL_DELAY_SYSPLL (0x00000001 << 25)
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#define BIT_SYS_XTAL_DELAY_USB (0x00000001 << 24)
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#define BIT_SYS_XTAL_DELAY_WLAFE (0x00000001 << 23)
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#define BIT_SYS_XTAL_EN_AAC_GM (0x00000001 << 21)
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#define BIT_SYS_XTAL_EN_AAC_PEAKDET (0x00000001 << 20)
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#define BIT_SYS_XTAL_AGPIO(x) (((x) & 0x00000001) << 17)
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#define BIT_SYS_XTAL_DRV_SYSPLL(x) (((x) & 0x00000003) << 15)
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#define BIT_SYS_XTAL_GATE_SYSPLL (0x00000001 << 14)
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#define BIT_SYS_XTAL_DRV_USB(x) (((x) & 0x00000003) << 12)
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#define BIT_SYS_XTAL_GATE_USB (0x00000001 << 11)
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#define BIT_SYS_XTAL_DRV_WLAFE(x) (((x) & 0x00000003) << 9)
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#define BIT_SYS_XTAL_GATE_WLAFE (0x00000001 << 8)
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#define BIT_SYS_XTAL_DRV_RF2(x) (((x) & 0x00000003) << 6)
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#define BIT_SYS_XTAL_GATE_RF2 (0x00000001 << 5)
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#define BIT_SYS_XTAL_DRV_RF1(x) (((x) & 0x00000003) << 3)
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#define BIT_SYS_XTAL_GATE_RF1 (0x00000001 << 2)
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#define BIT_SYS_XTAL_LDO(x) (((x) & 0x00000003) << 0)
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_SYSPLL_CTRL0
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* @{
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*****************************************************************************/
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#define BIT_SYS_SYSPLL_CKTST_EN (0x00000001 << 22)
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#define BIT_SYS_SYSPLL_MONCK_SEL(x) (((x) & 0x00000007) << 19)
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#define BIT_SYS_SYSPLL_CP_IOFFSET(x) (((x) & 0x0000001f) << 14)
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#define BIT_SYS_SYSPLL_FREF_EDGE (0x00000001 << 9)
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#define BIT_SYS_SYSPLL_EN (0x00000001 << 1)
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#define BIT_SYS_SYSPLL_LVPC_EN (0x00000001 << 0)
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_SYSPLL_CTRL1
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* @{
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*****************************************************************************/
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#define BIT_SYS_SYSPLL_CL200M_SEL (0x00000001 << 17) /*!< 1:200MHz, 0:166.666MHz */
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#define BIT_SYS_SYSPLL_CK500K_SEL (0x00000001 << 15) /*!< 1:external source 0:PLL */
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#define BIT_SYS_SYSPLL_CK200M_EN (0x00000001 << 14) /*!< 1: enable CK200M */
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#define BIT_SYS_SYSPLL_CKSDR_EN (0x00000001 << 13) /*!< 1: enable CK_SDRAM */
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#define BIT_SYS_SYSPLL_CKSDR_DIV (0x00000003 << 11) /*!< SDR PLL select: 00/01/10/11 no clock/25M/50M/100M */
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#define BIT_SYS_SYSPLL_CK24P576_EN (0x00000001 << 10) /*!< 1:enable CK24.576M PLL */
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#define BIT_SYS_SYSPLL_CK22P5792_EN (0x00000001 << 9) /*!< 1: enable CK22.5792M PLL */
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#define BIT_SYS_SYSPLL_CK83P33M_EN (0x00000001 << 8) /*!< 1: enable CK83.33M PLL */
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#define BIT_SYS_SYSPLL_CK_PS_EN (0x00000001 << 7) /*!< reg_ps_en Enable phase shift */
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#define BIT_SYS_SYSPLL_CK_PS_SEL (0x00000007 << 4) /*!< "decide clock phase when reg_ps_enb = 1000/001<30><31>/111: phase 0, 45<34><35>315 */
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_SYSPLL_CTRL2
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* @{
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*****************************************************************************/
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#define BIT_SYS_SYSPLL_CK_ADC_EN (0x00000001 << 25) /*!< Set ADC PLL EN */
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_SYS_SYSPLL_CTRL3
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* @{
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*****************************************************************************/
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#define BIT_DIV_SEL (0x000001FF << 6) /*!< The period of signal CK500M_SYNC/CK500M_PS_SYNC is: (r_DIV_SEL[8:0] + 2) cycles of 500MHz clock */
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#define BIT_PHASE_SEL (0x00000007 << 3) /*!< Phase selection for CK_500M_PS 0: 0, 1: 45, 2: 90, 3: 135, 4: 180, 5: 225, 6: 270, 7: 315 */
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#define BIT_EN_CK_500M_PS (0x00000001 << 2) /*!< 1: enable PLL 500M phase shift clock; 0: disable, Enable this bit when use FLASH_CalibrationPhase */
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#define BIT_EN_CK_500M (0x00000001 << 1) /*!< 1: enable PLL 500M clock; 0: disable, HW auto enable this bit */
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_OSC32K_CTRL
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* @{
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*****************************************************************************/
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#define BIT_SYS_OSC32K_POW_CKGEN (0x00000001 << 0) /*!< 1: enable OSC 32K clock generator; 0: turn off OSC 32K clock gen */
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#define BIT_SYS_OSC32K_OUT_SEL (0x00000001 << 1) /*!< 1: New Calibration Mode(REGUOUT=OSCIN=8M) 0: Original Calibration Mode (REGUOUT=OSCIN=32k) */
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#define BIT_SYS_OSC32K_RESISTOR_COM (0x00000003 << 2) /*!< Compensate resistor control */
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#define BIT_SYS_OSC32K_CKE_8M (0x00000001 << 4) /*!< 1: osc 8m clk is enabled */
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#define BIT_SYS_OSC32K_CKE_FREF (0x00000001 << 5) /*!< 1: referece 25M clk is enabled */
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#define BIT_32K_BIAS_CURRENT (0x0000FFFF << 16) /*! Bias current control */
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_OSC32K_REG_CTRL0
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* @{
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*****************************************************************************/
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#define BIT_32K_REG_INDIRT_CMD (0x00000001 << 23) /*!< 1: write command, 0: read command */
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#define BIT_32K_REG_INDIRT_ADDR (0x0000003F << 16)
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#define BIT_32K_REG_INDIRT_WDATA (0x0000FFFF << 0)
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/** @} */
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/**************************************************************************//**
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* @defgroup REG_OSC32K_REG_CTRL0
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* @{
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*****************************************************************************/
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#define BIT_32K_REG_INDIRT_RDATA (0x0000FFFF << 0) /*!< 32K OSC register indirect read data */
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/** @} */
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/** @} */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Other definations --------------------------------------------------------*/
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extern u32 NCO32K_Enable;
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extern u32 OSC8M_CLOCK_GLB;
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/**
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* @brief Configures NCO 32K monitor function
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* @param NewStatus: Disable/Enable
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* @note you should disable monitor when XTAL 40M close
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*/
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static inline void NCO32K_Monitor(u32 NewStatus)
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{
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if (NewStatus == ENABLE) {
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NCO32k->CTRL |= NCO1_BIT_REF_CLK_EN;
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} else {
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NCO32k->CTRL &= ~NCO1_BIT_REF_CLK_EN;
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}
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}
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#endif //_RTL8710B_CLK_H_
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/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
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