mirror of
https://github.com/jialexd/sdk-ameba-v4.0c_180328.git
synced 2025-07-31 12:41:05 +00:00
first add sdk
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jialexd
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3915 changed files with 1291882 additions and 0 deletions
651
component/common/example/spi_atcmd/example_spi_atcmd.c
Executable file
651
component/common/example/spi_atcmd/example_spi_atcmd.c
Executable file
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@ -0,0 +1,651 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2015 Realtek Corporation. All rights reserved.
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*
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*
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******************************************************************************/
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#include <platform_opts.h>
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#if CONFIG_EXAMPLE_SPI_ATCMD
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#include "FreeRTOS.h"
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#include "task.h"
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#include <platform/platform_stdlib.h>
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#include "semphr.h"
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#include "device.h"
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#include "osdep_api.h"
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#include "osdep_service.h"
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#include "device_lock.h"
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#include "spi_atcmd/example_spi_atcmd.h"
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#include "at_cmd/log_service.h"
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#include "at_cmd/atcmd_wifi.h"
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#include "at_cmd/atcmd_lwip.h"
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#include "flash_api.h"
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#include "spi_api.h"
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#include "spi_ex_api.h"
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#include "gpio_irq_api.h"
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#include "gpio_irq_ex_api.h"
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/**** SPI FUNCTIONS ****/
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spi_t spi_obj;
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gpio_t gpio_cs;
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#define SPI_RX_BUFFER_SIZE ATSTRING_LEN/2
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#define SPI_TX_BUFFER_SIZE ATSTRING_LEN/2
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uint16_t spi_chunk_buffer[ATSTRING_LEN/2];
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_Sema master_rx_done_sema;
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_Sema master_tx_done_sema;
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#define SPI_USE_STREAM (0)
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#define SPI_USE_DMA (1)
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/**** SLAVE HARDWARE READY ****/
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gpio_t gpio_hrdy;
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#define SPI_SLAVE_BUSY 0
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#define SPI_SLAVE_READY 1
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volatile int spi_slave_status = SPI_SLAVE_BUSY;
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_Sema spi_check_hrdy_sema;
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#define BLOCKING 1
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#define NONBLOCKING 0
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volatile int hrdy_pull_down_counter = 0;
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/**** SLAVE SYNC ****/
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gpio_irq_t gpio_sync;
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#define SPI_STATE_MISO 0
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#define SPI_STATE_MOSI 1
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int spi_state = SPI_STATE_MISO;
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/**** TASK THREAD ****/
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_Sema spi_check_trx_sema;
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/**** LOG SERVICE ****/
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char at_string[ATSTRING_LEN];
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extern char log_buf[LOG_SERVICE_BUFLEN];
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extern xSemaphoreHandle log_rx_interrupt_sema;
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#define LOG_TX_BUFFER_SIZE 48*1024
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char log_tx_buffer[LOG_TX_BUFFER_SIZE];
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uint32_t log_tx_idx = 0;
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uint32_t log_rx_idx = 0;
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/**** DATA FORMAT ****/
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#define PREAMBLE_COMMAND 0x6000
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#define PREAMBLE_DATA_READ 0x1000
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#define PREAMBLE_DATA_WRITE 0x0000
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#define COMMAND_DUMMY 0x0000
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#define COMMAND_BEGIN 0x0304
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#define COMMAND_END 0x0305
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#define COMMAND_READ_BEGIN 0x0012
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#define COMMAND_READ_RAW 0x0013
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#define COMMAND_WRITE_BEGIN 0x0014
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#define COMMAND_READ_WRITE_END 0x0015
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#define REGISTER_ADDR 0x2000
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void atcmd_update_partition_info(AT_PARTITION id, AT_PARTITION_OP ops, u8 *data, u16 len) {
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flash_t flash;
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int size, offset, i;
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u32 read_data;
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switch(id){
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case AT_PARTITION_SPI:
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size = SPI_CONF_DATA_SIZE;
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offset = SPI_CONF_DATA_OFFSET;
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break;
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case AT_PARTITION_WIFI:
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size = WIFI_CONF_DATA_SIZE;
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offset = WIFI_CONF_DATA_OFFSET;
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break;
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case AT_PARTITION_LWIP:
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size = LWIP_CONF_DATA_SIZE;
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offset = LWIP_CONF_DATA_OFFSET;
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break;
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case AT_PARTITION_ALL:
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size = 0x1000;
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offset = 0;
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break;
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default:
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printf("partition id is invalid!\r\n");
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return;
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}
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device_mutex_lock(RT_DEV_LOCK_FLASH);
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if(id == AT_PARTITION_ALL && ops == AT_PARTITION_ERASE){
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flash_erase_sector(&flash, SPI_SETTING_SECTOR);
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goto exit;
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}
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if(ops == AT_PARTITION_READ){
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flash_stream_read(&flash, SPI_SETTING_SECTOR+offset, len, data);
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goto exit;
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}
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//erase BACKUP_SECTOR
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flash_erase_sector(&flash, SPI_SETTING_BACKUP_SECTOR);
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if(ops == AT_PARTITION_WRITE){
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// backup new data
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flash_stream_write(&flash, SPI_SETTING_BACKUP_SECTOR+offset, len, data);
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}
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//backup front data to backup sector
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for(i = 0; i < offset; i += sizeof(read_data)){
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flash_read_word(&flash, SPI_SETTING_SECTOR + i, &read_data);
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flash_write_word(&flash, SPI_SETTING_BACKUP_SECTOR + i,read_data);
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}
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//backup rear data
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for(i = (offset + size); i < 0x1000; i += sizeof(read_data)){
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flash_read_word(&flash, SPI_SETTING_SECTOR + i, &read_data);
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flash_write_word(&flash, SPI_SETTING_BACKUP_SECTOR + i,read_data);
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}
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//erase UART_SETTING_SECTOR
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flash_erase_sector(&flash, SPI_SETTING_SECTOR);
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//retore data to UART_SETTING_SECTOR from UART_SETTING_BACKUP_SECTOR
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for(i = 0; i < 0x1000; i+= sizeof(read_data)){
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flash_read_word(&flash, SPI_SETTING_BACKUP_SECTOR + i, &read_data);
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flash_write_word(&flash, SPI_SETTING_SECTOR + i,read_data);
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}
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//erase BACKUP_SECTOR
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flash_erase_sector(&flash, SPI_SETTING_BACKUP_SECTOR);
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exit:
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device_mutex_unlock(RT_DEV_LOCK_FLASH);
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return;
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}
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/* AT cmd V2 API */
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void spi_at_send_string(char *str) {
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spi_at_send_buf(str, strlen(str));
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}
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/* AT cmd V2 API */
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void spi_at_send_buf(u8 *buf, u32 len) {
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int i;
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int spi_tx_tail_next;
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if( !len || (!buf) ){
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return;
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}
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if (buf == log_tx_buffer) {
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log_tx_idx = len;
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} else {
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for (i=0; i<len; i++) {
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if (log_tx_idx == LOG_TX_BUFFER_SIZE) {
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// overflow!
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break;
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}
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log_tx_buffer[log_tx_idx++] = buf[i];
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}
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}
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if (__get_IPSR() != 0) {
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RtlUpSema(&spi_check_trx_sema);
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} else {
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RtlUpSemaFromISR(&spi_check_trx_sema);
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}
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}
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/* IRQ handler called when SPI TX/RX finish */
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void master_trx_done_callback(void *pdata, SpiIrq event) {
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switch(event){
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case SpiRxIrq:
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RtlUpSemaFromISR(&master_rx_done_sema);
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//DBG_8195A("Master RX done!\n");
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break;
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case SpiTxIrq:
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//DBG_8195A("Master TX done!\n");
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break;
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default:
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DBG_8195A("unknown interrput evnent!\n");
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}
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}
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/* IRQ handler called when SPI TX finish */
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static void master_tx_done_callback(uint32_t id) {
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RtlUpSemaFromISR(&master_tx_done_sema);
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}
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/* IRQ handler as gpio hrdy hit rising edge */
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void slave_hrdy_change_callback(uint32_t id) {
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gpio_irq_disable(&gpio_hrdy);
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if (spi_slave_status == SPI_SLAVE_BUSY) {
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// Transition from LOW to HIGH. Change to listen IRQ_LOW
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spi_slave_status = SPI_SLAVE_READY;
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hrdy_pull_down_counter++;
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gpio_irq_set(&gpio_hrdy, IRQ_LOW, 1);
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gpio_irq_enable(&gpio_hrdy);
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} else {
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// Transition from HIGH to LOW. Change to listen IRQ_HIGH
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spi_slave_status = SPI_SLAVE_BUSY;
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gpio_irq_set(&gpio_hrdy, IRQ_HIGH, 1);
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gpio_irq_enable(&gpio_hrdy);
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}
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RtlUpSemaFromISR(&spi_check_hrdy_sema);
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}
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/* IRQ Handler as gpio sync state change */
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void slave_sync_chagne_callback(uint32_t id)
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{
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gpio_irq_disable(&gpio_sync);
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if (spi_state == SPI_STATE_MISO) {
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// Transition from LOW to HIGH. Change to listen IRQ_LOW
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spi_state = SPI_STATE_MOSI;
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gpio_irq_set(&gpio_sync, IRQ_LOW, 1);
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gpio_irq_enable(&gpio_sync);
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} else {
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// Transition from HIGH to LOW. Change to listen IRQ_HIGH
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spi_state = SPI_STATE_MISO;
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gpio_irq_set(&gpio_sync, IRQ_HIGH, 1);
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gpio_irq_enable(&gpio_sync);
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}
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RtlUpSemaFromISR(&spi_check_trx_sema);
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}
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void spi_atcmd_main(void)
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{
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wifi_disable_powersave();
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// read settings
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SPI_LOG_CONF spiconf;
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spiconf.bits = 16;
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spiconf.frequency = 20000000;
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spiconf.mode = (SPI_SCLK_IDLE_LOW|SPI_SCLK_TOGGLE_MIDDLE);
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// init spi
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spi_init(&spi_obj, SPI0_MOSI, SPI0_MISO, SPI0_SCLK, SPI0_CS);
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spi_frequency(&spi_obj, spiconf.frequency);
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spi_format(&spi_obj, spiconf.bits, spiconf.mode, 0);
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spi_bus_tx_done_irq_hook(&spi_obj, master_tx_done_callback, (uint32_t)&spi_obj);
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spi_irq_hook(&spi_obj, master_trx_done_callback, (uint32_t)&spi_obj);
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// init simulated spi cs
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gpio_init(&gpio_cs, GPIO_CS);
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gpio_dir(&gpio_cs, PIN_OUTPUT);
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gpio_mode(&gpio_cs, PullNone);
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gpio_write(&gpio_cs, 1);
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// init gpio for check if spi slave hw ready
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gpio_init(&gpio_hrdy, GPIO_HRDY);
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gpio_dir(&gpio_hrdy, PIN_INPUT);
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gpio_mode(&gpio_hrdy, PullDown);
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gpio_irq_init(&gpio_hrdy, GPIO_HRDY, slave_hrdy_change_callback, (uint32_t)&gpio_hrdy);
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gpio_irq_set(&gpio_hrdy, IRQ_HIGH, 1);
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gpio_irq_enable(&gpio_hrdy);
|
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|
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// init gpio for check if spi slave want to send data
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gpio_irq_init(&gpio_sync, GPIO_SYNC, slave_sync_chagne_callback,(uint32_t)&gpio_sync);
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gpio_irq_set(&gpio_sync, IRQ_HIGH, 1);
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gpio_irq_enable(&gpio_sync);
|
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|
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// init semaphore for check hardware ready
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RtlInitSema(&spi_check_hrdy_sema, 1);
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RtlDownSema(&spi_check_hrdy_sema);
|
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|
||||
// init semaphore that makes spi tx/rx thread to check something
|
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RtlInitSema(&spi_check_trx_sema, 1);
|
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RtlDownSema(&spi_check_trx_sema);
|
||||
|
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// init semaphore for master tx
|
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RtlInitSema(&master_tx_done_sema, 1);
|
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RtlDownSema(&master_tx_done_sema);
|
||||
|
||||
// init semaphore for master rx
|
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RtlInitSema(&master_rx_done_sema, 1);
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RtlDownSema(&master_rx_done_sema);
|
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}
|
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|
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int32_t spi_master_send(spi_t *obj, char *tx_buffer, uint32_t length) {
|
||||
hrdy_pull_down_counter = 0;
|
||||
spi_master_write_stream_dma(obj, tx_buffer, length);
|
||||
RtlDownSema(&master_tx_done_sema);
|
||||
|
||||
if (spi_slave_status == SPI_SLAVE_BUSY) {
|
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while (hrdy_pull_down_counter == 0);
|
||||
hrdy_pull_down_counter = 0;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t spi_master_recv(spi_t *obj, char *rx_buffer, uint32_t length) {
|
||||
hrdy_pull_down_counter = 0;
|
||||
spi_flush_rx_fifo(obj);
|
||||
spi_master_read_stream_dma(obj, rx_buffer, length);
|
||||
RtlDownSema(&master_rx_done_sema);
|
||||
RtlDownSema(&master_tx_done_sema);
|
||||
|
||||
if (spi_slave_status == SPI_SLAVE_BUSY) {
|
||||
while (hrdy_pull_down_counter == 0);
|
||||
hrdy_pull_down_counter = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void atcmd_check_special_case(char *buf) {
|
||||
int i;
|
||||
if (strlen(buf) > 4) {
|
||||
if (strncmp(buf, "ATPT", 4) == 0) {
|
||||
for (i=0; i<strlen(buf); i++) {
|
||||
if (buf[i] == ':') {
|
||||
buf[i] = '\0';
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void spi_trx_thread(void *param)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t rxlen, txlen;
|
||||
uint32_t recv_len, recv_remain, send_len;
|
||||
|
||||
uint16_t dummy, L_address, H_address, L_size, H_size;
|
||||
|
||||
int slave_ready = 0;
|
||||
do {
|
||||
slave_ready = gpio_read(&gpio_hrdy);
|
||||
rtw_msleep_os(1000);
|
||||
} while(slave_ready == 0);
|
||||
|
||||
while(1) {
|
||||
RtlDownSema(&spi_check_trx_sema);
|
||||
|
||||
if (spi_state == SPI_STATE_MOSI) {
|
||||
if (log_tx_idx > 0) {
|
||||
/* Slave hw is ready, and Master has something to send. */
|
||||
|
||||
// stage A, read target address
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_COMMAND;
|
||||
spi_chunk_buffer[txlen++] = COMMAND_BEGIN;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_chunk_buffer[0] = PREAMBLE_DATA_READ;
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, 1 * 2);
|
||||
spi_master_recv(&spi_obj, spi_chunk_buffer, 1 * 2);
|
||||
dummy = spi_chunk_buffer[0];
|
||||
spi_master_recv(&spi_obj, spi_chunk_buffer, 1 * 2);
|
||||
L_address = spi_chunk_buffer[0];
|
||||
spi_master_recv(&spi_obj, spi_chunk_buffer, 1 * 2);
|
||||
H_address = spi_chunk_buffer[0];
|
||||
spi_master_recv(&spi_obj, spi_chunk_buffer, 1 * 2);
|
||||
L_size = spi_chunk_buffer[0];
|
||||
spi_master_recv(&spi_obj, spi_chunk_buffer, 1 * 2);
|
||||
H_size = spi_chunk_buffer[0];
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
// stage B, write data
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_COMMAND;
|
||||
spi_chunk_buffer[txlen++] = COMMAND_WRITE_BEGIN;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
if (log_tx_idx % 2 != 0) {
|
||||
log_tx_buffer[log_tx_idx++] = 0;
|
||||
}
|
||||
send_len = log_tx_idx / 2;
|
||||
L_size = send_len & 0x0000FFFF;
|
||||
H_size = (send_len & 0xFFFF0000) >> 16;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
txlen = 1;
|
||||
spi_chunk_buffer[0] = PREAMBLE_DATA_WRITE;
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
spi_chunk_buffer[0] = L_address;
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
spi_chunk_buffer[0] = H_address;
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
spi_chunk_buffer[0] = L_size;
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
spi_chunk_buffer[0] = H_size;
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_DATA_WRITE;
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
txlen = log_tx_idx/2;
|
||||
spi_master_send(&spi_obj, log_tx_buffer, txlen * 2); // sending raw data
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
// stage C, write data end
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_COMMAND;
|
||||
spi_chunk_buffer[txlen++] = COMMAND_READ_WRITE_END;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
// stage final
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_COMMAND;
|
||||
spi_chunk_buffer[txlen++] = COMMAND_END;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
L_size = log_tx_idx & 0x0000FFFF;
|
||||
H_size = (log_tx_idx & 0xFFFF0000) >> 16;
|
||||
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_DATA_WRITE;
|
||||
spi_chunk_buffer[txlen++] = L_size;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_DATA_WRITE;
|
||||
spi_chunk_buffer[txlen++] = H_size;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
// finalize
|
||||
log_tx_idx = 0;
|
||||
}
|
||||
|
||||
} else if (spi_state == SPI_STATE_MISO) {
|
||||
/* Slave hw is ready, and Slave want to send something. */
|
||||
do {
|
||||
// stage A, read target address
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_COMMAND;
|
||||
spi_chunk_buffer[txlen++] = COMMAND_BEGIN;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_DATA_READ;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
spi_master_recv(&spi_obj, spi_chunk_buffer, 1 * 2);
|
||||
dummy = spi_chunk_buffer[0];
|
||||
spi_master_recv(&spi_obj, spi_chunk_buffer, 1 * 2);
|
||||
L_address = spi_chunk_buffer[0];
|
||||
spi_master_recv(&spi_obj, spi_chunk_buffer, 1 * 2);
|
||||
H_address = spi_chunk_buffer[0];
|
||||
spi_master_recv(&spi_obj, spi_chunk_buffer, 1 * 2);
|
||||
L_size = spi_chunk_buffer[0];
|
||||
spi_master_recv(&spi_obj, spi_chunk_buffer, 1 * 2);
|
||||
H_size = spi_chunk_buffer[0];
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
recv_len = ((H_size << 16) | L_size);
|
||||
|
||||
if (recv_len == 0) {
|
||||
break;
|
||||
}
|
||||
|
||||
// Stage B, confirm addr & len
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_COMMAND;
|
||||
spi_chunk_buffer[txlen++] = COMMAND_READ_BEGIN;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
txlen = 1;
|
||||
|
||||
spi_chunk_buffer[0] = PREAMBLE_DATA_WRITE;
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
spi_chunk_buffer[0] = L_address;
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
spi_chunk_buffer[0] = H_address;
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
spi_chunk_buffer[0] = L_size;
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
spi_chunk_buffer[0] = H_size;
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
// Stage C, begin to read
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_COMMAND;
|
||||
spi_chunk_buffer[txlen++] = COMMAND_READ_RAW;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_DATA_READ;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
spi_master_recv(&spi_obj, spi_chunk_buffer, 1 * 2); // recv dummy
|
||||
rxlen = recv_len;
|
||||
spi_master_recv(&spi_obj, log_buf, rxlen * 2);
|
||||
log_buf[rxlen*2]= '\0';
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
// Stage D, read end
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_COMMAND;
|
||||
spi_chunk_buffer[txlen++] = COMMAND_READ_WRITE_END;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
// stage final
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_COMMAND;
|
||||
spi_chunk_buffer[txlen++] = COMMAND_END;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
L_size = (recv_len) & 0x0000FFFF;
|
||||
H_size = ((recv_len) & 0xFFFF0000) >> 16;
|
||||
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_DATA_WRITE;
|
||||
spi_chunk_buffer[txlen++] = L_size;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
txlen = 0;
|
||||
spi_chunk_buffer[txlen++] = PREAMBLE_DATA_WRITE;
|
||||
spi_chunk_buffer[txlen++] = H_size;
|
||||
|
||||
gpio_write(&gpio_cs, 0);
|
||||
spi_master_send(&spi_obj, spi_chunk_buffer, txlen * 2);
|
||||
gpio_write(&gpio_cs, 1);
|
||||
|
||||
// finalize
|
||||
//printf("%s", log_buf);
|
||||
atcmd_check_special_case(log_buf);
|
||||
RtlUpSema(&log_rx_interrupt_sema);
|
||||
taskYIELD();
|
||||
} while (0);
|
||||
}
|
||||
}
|
||||
|
||||
vTaskDelete(NULL);
|
||||
}
|
||||
|
||||
static void spi_atcmd_thread(void *param)
|
||||
{
|
||||
p_wlan_init_done_callback = NULL;
|
||||
atcmd_wifi_restore_from_flash();
|
||||
atcmd_lwip_restore_from_flash();
|
||||
rtw_msleep_os(20);
|
||||
spi_atcmd_main();
|
||||
|
||||
// the rx_buffer of atcmd is to receive and sending out to log_tx
|
||||
atcmd_lwip_set_rx_buffer(log_tx_buffer, sizeof(log_tx_buffer));
|
||||
|
||||
at_set_debug_mask(0x0);
|
||||
|
||||
if(xTaskCreate(spi_trx_thread, ((const char*)"spi_trx_thread"), 4096, NULL, tskIDLE_PRIORITY+1 , NULL) != pdPASS)
|
||||
printf("\n\r%s xTaskCreate(spi_trx_thread) failed", __FUNCTION__);
|
||||
|
||||
vTaskDelete(NULL);
|
||||
}
|
||||
|
||||
int spi_atcmd_module_init(void){
|
||||
if(xTaskCreate(spi_atcmd_thread, ((const char*)"spi_atcmd_thread"), 1024, NULL, tskIDLE_PRIORITY+1 , NULL) != pdPASS)
|
||||
printf("\n\r%s xTaskCreate(spi_atcmd_thread) failed", __FUNCTION__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void example_spi_atcmd(void)
|
||||
{
|
||||
p_wlan_init_done_callback = spi_atcmd_module_init;
|
||||
return;
|
||||
}
|
||||
|
||||
#endif // #if CONFIG_EXAMPLE_SPI_ATCMD
|
||||
Loading…
Add table
Add a link
Reference in a new issue