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https://github.com/jialexd/sdk-ameba-v4.0c_180328.git
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149 lines
5 KiB
C
149 lines
5 KiB
C
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/**
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******************************************************************************
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* @file rtl8711b_rtc.h
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* @author
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* @version V1.0.0
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* @date 2016-05-17
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* @brief This file contains all the functions prototypes for the WDG firmware
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* library.
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******************************************************************************
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* @attention
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*
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* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
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******************************************************************************
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*/
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#ifndef _RTL8711B_WDG_H_
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#define _RTL8711B_WDG_H_
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/** @addtogroup AmebaZ_Periph_Driver
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* @{
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*/
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/** @defgroup WDG
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* @brief WDG driver modules
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* @{
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*/
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/** @addtogroup WDG
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* @verbatim
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*****************************************************************************************
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* Introduction
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*****************************************************************************************
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* WDG:
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* - Base Address: VENDOR_REG_BASE
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* - Timer clk: NCO 32k
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* - Generates MCU reset or NMI interrupt on expiry of a programmed time period,
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* unless the program refreshes the watchdog
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* - IRQ: WDG_IRQ & NMI
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*
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*****************************************************************************************
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* WDG Register
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*****************************************************************************************
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* [31] R/W1C Wdt_to Watch dog timer timeout. 1 cycle pulse
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* [30] R/W Wdt_mode 1: Reset system, 0: Interrupt CPU
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* [29] R/W RSVD
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* [28:25] R/W Cnt_limit 0: 0x001
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* 1: 0x003
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* 2: 0x007
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* 3: 0x00F
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* 4: 0x01F
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* 5: 0x03F
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* 6: 0x07F
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* 7: 0x0FF
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* 8: 0x1FF
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* 9: 0x3FF
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* 10: 0x7FF
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* 11~15: 0xFFF"
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* [24] W Wdt_clear Write 1 to clear timer
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* [32:16] R/W Wdt_en_byte Set 0xA5 to enable watch dog timer
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* [15:0] R/W BIT_VNDR_divfactor "Dividing factor.Watch dog timer is count with 32.768KHz/(divfactor+1).
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* Minimum dividing factor is 1."
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*
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*****************************************************************************************
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* How to use WGD
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*****************************************************************************************
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* To use WDG peripheral, the following steps are mandatory:
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*
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* 1. Get count ID and divisor factor according to WDG timeout period using
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* WDG_Scalar(WDG_TEST_TIMEOUT, &CountProcess, &DivFacProcess);
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*
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* 2. Configure WDG with the corresponding configuration.
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* WDG_Init(&WDG_InitStruct)
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*
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* 3. Activate the WDG peripheral:
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WDG_Cmd(ENABLE).
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*
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* @note In interrupt mode, call WDG_IrqInit() function after WDG_Init()
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*
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* @note WDG_Refresh() function is used to clear timer, if call this function before timeout period,
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* then MCU reset or NMI interrupt won't generate
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*
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*****************************************************************************************
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* @endverbatim
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup WDG_Exported_Types WDG Exported Types
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* @{
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*/
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/**
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* @brief WDG Init structure definition
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*/
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typedef struct
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{
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u32 CountProcess; /*!< WDG parameter get from WDG_Scalar, Specifies count id of WDG
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This parameter must be set to a value in the 0-11 range */
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u32 DivFacProcess; /*!< WDG parameter get from WDG_Scalar, Specifies WDG timeout count divisor factor
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This parameter must be set to a value in the 1-65535 range */
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} WDG_InitTypeDef;
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/**
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* @}
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*/
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/** @defgroup WDG_Exported_Functions WDG Exported Functions
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* @{
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*/
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_LONG_CALL_ void WDG_Scalar(u32 Period, u32 *pCountProcess, u32 *pDivFacProcess);
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_LONG_CALL_ void WDG_Init(WDG_InitTypeDef *WDG_InitStruct);
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_LONG_CALL_ void WDG_IrqInit(void *handler, u32 Id);
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_LONG_CALL_ void WDG_Cmd(u32 NewState);
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_LONG_CALL_ void WDG_Refresh(void);
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/**
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* @}
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*/
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/* Registers Definitions --------------------------------------------------------*/
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/**************************************************************************//**
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* @defgroup WDG_Register_Definitions WDG Register Definitions
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* @{
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*****************************************************************************/
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/**************************************************************************//**
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* @defgroup WDG_REG
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* @{
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*****************************************************************************/
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#define WDG_BIT_CLEAR ((u32)0x00000001 << 24)
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#define WDG_BIT_RST_MODE ((u32)0x00000001 << 30)
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#define WDG_BIT_ISR_CLEAR ((u32)0x00000001 << 31)
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/** @} */
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/** @} */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif //_RTL8711B_WDG_H_
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/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
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