mirror of
https://github.com/jialexd/sdk-ameba-v4.0c_180328.git
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235 lines
9.1 KiB
C
235 lines
9.1 KiB
C
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/**
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******************************************************************************
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* @file rtl8710b_sdio.h
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* @author
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* @version V1.0.0
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* @date 2016-05-17
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* @brief This file contains all the functions prototypes for the SDIO firmware
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* library.
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******************************************************************************
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* @attention
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*
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* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
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******************************************************************************
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*/
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#ifndef _RTL8710B_SDIO_H_
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#define _RTL8710B_SDIO_H_
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/** @addtogroup AmebaZ_Periph_Driver
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* @{
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*/
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/** @defgroup SDIO
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* @brief SDIO driver modules
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* @{
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*/
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/* Exported Types --------------------------------------------------------*/
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/** @defgroup SDIO_Exported_Types SDIO Exported Types
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* @{
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*/
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/**
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* @brief SDIO Init structure definition
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*/
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typedef struct {
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/* TXBD */
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u32 TXBD_BAR; /*!< Specifies TXBD base address */
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u32 TXBD_RING_SIZE; /*!< Specifies TXBD ring size, This parameter must be set to a value in the 0-0xFFFF range. */
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u32 TX_BUFFER_SIZE; /*!< Specifies TX buffer size, This parameter must be set to a value in the 0-0xFF range. */
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/* RXBD */
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u32 RXBD_BAR; /*!< Specifies RXBD base address */
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u32 RXBD_RING_SIZE; /*!< Specifies RXBD ring size, This parameter must be set to a value in the 0-0xFFFF range. */
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u32 RXBD_FREE_TH; /*!< the threshold of free RX BD count to trigger interrupt */
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} SDIO_InitTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup SDIO_Exported_Constants SDIO Exported Constants
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* @{
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*/
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/** @defgroup SDIO_MP_CMD_definitions The SDIO MP CMD definations
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* @{
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*/
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#define SDIO_MP_START 1
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#define SDIO_MP_STOP 2
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#define SDIO_MP_LOOPBACK 3
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#define SDIO_MP_STATUS 4
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#define SDIO_MP_READ_REG8 5
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#define SDIO_MP_READ_REG16 6
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#define SDIO_MP_READ_REG32 7
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#define SDIO_MP_WRITE_REG8 8
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#define SDIO_MP_WRITE_REG16 9
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#define SDIO_MP_WRITE_REG32 10
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#define SDIO_MP_WAKEUP 11 // wakeup the SDIO task manually, for debugging
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#define SDIO_MP_DUMP 12 // start/stop to dump the SDIO status periodically
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#define SDIO_MP_CTX 13 // setup continue TX test
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#define SDIO_MP_CRX 14 // setup continue RX test
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#define SDIO_MP_CRX_DA 15 // setup continue RX with dynamic allocate RX Buf test
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#define SDIO_MP_CRX_STOP 16 // setup continue RX test
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#define SDIO_MP_DBG_MSG 17 // Debug message On/Off
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/**
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* @}
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*/
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/** @defgroup SDIO_RPWM_definitions The SDIO RPWM definations
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* @{
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*/
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#define RPWM2_ACT_BIT (0x00000001 << 0) // Active
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#define RPWM2_SLEEP_BIT 0 // Sleep
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#define RPWM2_DSTANDBY_BIT (0x00000001 << 1) // Deep Standby
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#define RPWM2_PG_BIT 0 // Power Gated
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#define RPWM2_FBOOT_BIT (0x00000001 << 2) // fast reboot
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#define RPWM2_NBOOT_BIT 0 // normal reboot
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#define RPWM2_WKPIN_0_BIT (0x00000001 << 3) // enable GPIO wakeup pin 0
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#define RPWM2_WKPIN_1_BIT (0x00000001 << 4) // enable GPIO wakeup pin 1
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#define RPWM2_WKPIN_2_BIT (0x00000001 << 5) // enable GPIO wakeup pin 2
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#define RPWM2_WKPIN_3_BIT (0x00000001 << 6) // enable GPIO wakeup pin 3
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#define RPWM2_WKPIN_0_LV_BIT (0x00000001 << 7) // GPIO wakeup pin 0 wakeup level
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#define RPWM2_WKPIN_1_LV_BIT (0x00000001 << 8) // GPIO wakeup pin 1 wakeup level
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#define RPWM2_WKPIN_2_LV_BIT (0x00000001 << 9) // GPIO wakeup pin 2 wakeup level
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#define RPWM2_WKPIN_3_LV_BIT (0x00000001 << 10) // GPIO wakeup pin 3 wakeup level
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#define RPWM2_CG_BIT (0x00000001 << 11) // Clock Gated
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#define RPWM2_ACK_BIT (0x00000001 << 14) // Acknowledge
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#define RPWM2_TOGGLE_BIT (0x00000001 << 15) // Toggle bit
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/**
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* @}
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*/
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/** @defgroup SDIO_CPWM2_definitions The SDIO CPWM2 definations
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* @{
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*/
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#define CPWM2_ACT_BIT (0x00000001 << 0) // Active
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#define CPWM2_DSTANDBY_BIT (0x00000001 << 1) // Deep Standby
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#define CPWM2_FBOOT_BIT (0x00000001 << 2) // fast reboot
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#define CPWM2_INIC_FW_RDY_BIT (0x00000001 << 3) // is the iNIC FW(1) or Boot FW(0)
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#define CPWM2_TOGGLE_BIT (0x00000001 << 15) // Toggle bit
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/**
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* @}
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*/
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/** @defgroup SDIO_CPWM1_definitions The SDIO CPWM1 definations
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* @{
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*/
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#define CPWM1_TOGGLE_BIT (0x00000001 << 7) // Toggle bit
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/**
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* @}
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*/
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/** @defgroup SDIO_EVENT_definitions The SDIO EVENT definations
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* @{
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*/
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#define SDIO_EVENT_RX_PKT_RDY (0x00000001 << 1) // A new SDIO packet ready
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#define SDIO_EVENT_DUMP (0x00000001 << 3) // SDIO status dump periodically Enable
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#define SDIO_EVENT_EXIT (0x00000001 << 27) // Request to exit the SDIO task
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#define SDIO_EVENT_MP_STOPPED (0x00000001 << 28) // The SDIO task is stopped
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#define SDIO_EVENT_IRQ_STOPPED (0x00000001 << 29) // The SDIO task is stopped
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#define SDIO_EVENT_TX_STOPPED (0x00000001 << 30) // The SDIO task is stopped
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#define SDIO_EVENT_RX_STOPPED (0x00000001 << 31) // The SDIO task is stopped
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @defgroup SDIO_Exported_Functions SDIO Exported Functions
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* @{
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*/
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_LONG_CALL_ void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
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_LONG_CALL_ void SDIO_Init(SDIO_InitTypeDef* SDIOInit_Struct);
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_LONG_CALL_ void SDIO_INTClear(void);
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_LONG_CALL_ VOID SDIO_INTConfig(u16 IntMask, u32 NewState);
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_LONG_CALL_ u8 SDIO_RPWM1_Get(void);
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_LONG_CALL_ u16 SDIO_RPWM2_Get(void);
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_LONG_CALL_ void SDIO_CPWM1_Set(u8 Val);
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_LONG_CALL_ void SDIO_CPWM2_Set(u16 Val, u32 Newstate);
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_LONG_CALL_ u16 SDIO_RXBD_RPTR_Get(void);
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_LONG_CALL_ void SDIO_RXBD_WPTR_Set(u16 Val);
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_LONG_CALL_ u16 SDIO_TXBD_WPTR_Get(void);
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_LONG_CALL_ void SDIO_TXBD_RPTR_Set(u16 Val);
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_LONG_CALL_ void SDIO_DMA_Reset(void);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#define HAL_SDIO_READ32(addr) HAL_READ32(SDIO_DEVICE_REG_BASE, addr)
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#define HAL_SDIO_WRITE32(addr, value) HAL_WRITE32(SDIO_DEVICE_REG_BASE, addr, value)
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#define HAL_SDIO_READ16(addr) HAL_READ16(SDIO_DEVICE_REG_BASE, addr)
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#define HAL_SDIO_WRITE16(addr, value) HAL_WRITE16(SDIO_DEVICE_REG_BASE, addr, value)
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#define HAL_SDIO_READ8(addr) HAL_READ8(SDIO_DEVICE_REG_BASE, addr)
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#define HAL_SDIO_WRITE8(addr, value) HAL_WRITE8(SDIO_DEVICE_REG_BASE, addr, value)
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/* Registers Definitions --------------------------------------------------------*/
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#define REG_SPDIO_TXBD_ADDR 0xA0 // 4 Bytes
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#define REG_SPDIO_TXBD_SIZE 0xA4 // 4 Bytes
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#define REG_SPDIO_TXBD_WPTR 0xA8 // 2 Bytes
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#define REG_SPDIO_TXBD_RPTR 0xAC // 2 Bytes
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#define REG_SPDIO_RXBD_ADDR 0xB0 // 4 Bytes
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#define REG_SPDIO_RXBD_SIZE 0xB4 // 2 Bytes
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#define REG_SPDIO_RXBD_C2H_WPTR 0xB6 // 2 Bytes
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#define REG_SPDIO_RXBD_C2H_RPTR 0xB8 // 2 Bytes
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#define REG_SPDIO_HCI_RX_REQ 0xBA // 1 Byte
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#define REG_SPDIO_CPU_RST_DMA 0xBB // 1 Byte
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#define REG_SPDIO_RX_REQ_ADDR 0xBC // 2 Bytes
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#define REG_SPDIO_CPU_INT_MASK 0xC0 // 2 Bytes
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#define REG_SPDIO_CPU_INT_STAS 0xC2 // 2 Bytes
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#define REG_SPDIO_CCPWM 0xC4 // 1 Byts
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#define REG_SPDIO_CPU_IND 0xC5 // 1 Byte
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#define REG_SPDIO_CCPWM2 0xC6 // 2 Bytes
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#define REG_SPDIO_CPU_H2C_MSG 0xC8 // 4 Bytes
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#define REG_SPDIO_CPU_C2H_MSG 0xCC // 4 Bytes
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#define REG_SPDIO_CRPWM 0xD0 // 1 Bytes
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#define REG_SPDIO_CRPWM2 0xD2 // 2 Bytes
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#define REG_SPDIO_AHB_DMA_CTRL 0xD4 // 4 Bytes
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#define REG_SPDIO_RXBD_CNT 0xD8 // 4 Bytes
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#define REG_SPDIO_TX_BUF_UNIT_SZ 0xD9 // 1 Bytes
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#define REG_SPDIO_RX_BD_FREE_CNT 0xDA // 2 Bytes
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#define REG_SPDIO_CPU_H2C_MSG_EXT 0xDC // 4 Bytes
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#define REG_SPDIO_CPU_C2H_MSG_EXT 0xE0 // 4 Bytes
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/******************** Bits definition for REG_SPDIO_CPU_RST_DMA register *******************/
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#define BIT_CPU_RST_SDIO_DMA BIT(7)
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/******************** Bits definition for REG_SPDIO_CPU_INT_MASK/REG_SPDIO_CPU_INT_STAS register *******************/
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#define BIT_TXFIFO_H2C_OVF BIT(0)
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#define BIT_H2C_BUS_RES_FAIL BIT(1)
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#define BIT_H2C_DMA_OK BIT(2)
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#define BIT_C2H_DMA_OK BIT(3)
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#define BIT_H2C_MSG_INT BIT(4)
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#define BIT_RPWM1_INT BIT(5)
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#define BIT_RPWM2_INT BIT(6)
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#define BIT_SDIO_RST_CMD_INT BIT(7)
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#define BIT_RXBD_FLAG_ERR_INT BIT(8)
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#define BIT_RX_BD_AVAI_INT BIT(9)
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#define BIT_HOST_WAKE_CPU_INT BIT(10)
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#define SDIO_INIT_INT_MASK (BIT_H2C_DMA_OK | BIT_C2H_DMA_OK | \
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BIT_H2C_MSG_INT | BIT_RPWM1_INT | \
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BIT_RPWM2_INT |BIT_H2C_BUS_RES_FAIL | \
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BIT_RXBD_FLAG_ERR_INT)
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/******************** Bits definition for REG_SPDIO_CPU_IND register *******************/
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#define BIT_SYSTEM_TRX_RDY_IND BIT(0)
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/******************** Bits definition for REG_SPDIO_HCI_RX_REQ register *******************/
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#define BIT_HCI_RX_REQ BIT(0)
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#endif /* #ifndef _RTL8710B_SDIO_H_ */
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