mirror of
https://github.com/jialexd/sdk-ameba-v4.0c_180328.git
synced 2024-12-02 03:00:30 +00:00
179 lines
8.7 KiB
Text
179 lines
8.7 KiB
Text
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
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/*-Specials-*/
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//define symbol __ICFEDIT_intvec_start__ = 0x00000000;
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/**/
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/**/
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include "rom_symbol_v01_iar.icf";
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/****************************************
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* Memory Regions *
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****************************************/
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define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
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define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
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define symbol __ICFEDIT_region_ROMBSS_RAM_start__ = 0x10000000;
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define symbol __ICFEDIT_region_ROMBSS_RAM_end__ = 0x10001FFF;
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define symbol __ICFEDIT_region_BOOTLOADER_RAM_start__ = 0x10002000;
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define symbol __ICFEDIT_region_BOOTLOADER_RAM_end__ = 0x10004FFF;
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define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10005000;
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define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1003DFFF;
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define symbol __ICFEDIT_region_MSP_RAM_start__ = 0x1003E000;
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define symbol __ICFEDIT_region_MSP_RAM_end__ = 0x1003EFFF;
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define symbol __ICFEDIT_region_RDP_RAM_start__ = 0x1003F000;
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define symbol __ICFEDIT_region_RDP_RAM_end__ = 0x1003FFEF;
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define symbol __ICFEDIT_region_IMG2_TEMP_start__ = 0x10006000;
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define symbol __ICFEDIT_region_IMG2_TEMP_end__ = 0x1000BFFF;
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define symbol __ICFEDIT_region_XIP_BOOT_start__ = 0x08000000+0x20;
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define symbol __ICFEDIT_region_XIP_BOOT_end__ = 0x08003FFF;
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define symbol __ICFEDIT_region_XIP_OTA1_start__ = 0x0800B000+0x20;
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define symbol __ICFEDIT_region_XIP_OTA1_end__ = 0x080FFFFF;
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/****************************************
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* Sizes *
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****************************************/
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/*define symbol __ICFEDIT_size_cstack__ = 0x400;*/
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/*define symbol __ICFEDIT_size_heap__ = 0x800;*/
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
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define region ROM_BSS_region = mem:[from __ICFEDIT_region_ROMBSS_RAM_start__ to __ICFEDIT_region_ROMBSS_RAM_end__];
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define region BOOT_RAM_region = mem:[from __ICFEDIT_region_BOOTLOADER_RAM_start__ to __ICFEDIT_region_BOOTLOADER_RAM_end__];
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define region BD_RAM_region = mem:[from __ICFEDIT_region_BD_RAM_start__ to __ICFEDIT_region_BD_RAM_end__];
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define region IMG2_TEMP_region = mem:[from __ICFEDIT_region_IMG2_TEMP_start__ to __ICFEDIT_region_IMG2_TEMP_end__];
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define region XIP_BOOT_region = mem:[from __ICFEDIT_region_XIP_BOOT_start__ to __ICFEDIT_region_XIP_BOOT_end__];
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define region XIP_OTA1_region = mem:[from __ICFEDIT_region_XIP_OTA1_start__ to __ICFEDIT_region_XIP_OTA1_end__];
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define region RDP_RAM_region = mem:[from __ICFEDIT_region_RDP_RAM_start__ to __ICFEDIT_region_RDP_RAM_end__];
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/*define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };*/
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/*define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };*/
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//initialize by copy { readwrite };
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//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
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//do not initialize { section * };
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//place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors_table };
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//
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/****************************************
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* ROM Section config *
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****************************************/
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keep { section .rom.text };
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keep { section .rom.rodata };
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place at start of ROM_region { readonly, section .rom.text, section .rom.rodata };
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/****************************************
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* ROM BSS Section config *
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****************************************/
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keep { section .ram_vector_table1 };
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keep { section .ram_vector_table2 };
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keep { section .ram_vector_table3 };
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keep { section .hal.rom.bss* };
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keep { section .wlan_ram_map* };
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keep { section .libc.ram.bss* };
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keep { section .ssl_ram_map* };
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define block .hal.rom.bss with fixed order{ section .ram_vector_table1,
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section .ram_vector_table2,
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section .ram_vector_table3,
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section .hal.rom.bss*,
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section .wlan_ram_map*,
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section .libc.ram.bss*,
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section .ssl_ram_map*,
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};
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define block ROM_BSS with fixed order { block .hal.rom.bss};
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place at start of ROM_BSS_region { readwrite,
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block ROM_BSS,
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};
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/****************************************
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* BOOT RAM Section config *
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****************************************/
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keep { section .image1.entry.data* };
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keep { section .image1.validate.rodata* };
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define block .ram_image1.entry with fixed order{section .image1.entry.data*,
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section .image1.validate.rodata*,
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};
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keep { section .boot.ram.text* };
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keep { section .boot.rodata* };
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define block .ram_image1.text with fixed order{section .boot.ram.text*,
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section .boot.rodata*,
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};
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keep { section .boot.ram.data* };
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define block .ram_image1.data with fixed order{section .boot.ram.data*,
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};
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keep { section .boot.ram.bss* };
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define block .ram_image1.bss with fixed order{section .boot.ram.bss*,
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};
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define block IMAGE1 with fixed order { block .ram_image1.entry, block .ram_image1.text, block .ram_image1.data, block .ram_image1.bss};
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place at start of BOOT_RAM_region { readwrite,
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block IMAGE1,
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};
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/****************************************
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* BD RAM Section config *
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****************************************/
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keep { section .image2.entry.data* };
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keep { section .image2.validate.rodata* };
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define block .ram_image2.entry with fixed order{ section .image2.entry.data*,
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section .image2.validate.rodata*,
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};
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define block SHT$$PREINIT_ARRAY { preinit_array };
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define block __iar_tls$$INIT_ARRAY { init_array };
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define block SHT$$INIT_ARRAY { block __iar_tls$$INIT_ARRAY };
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define block CPP_INIT with fixed order { block SHT$$PREINIT_ARRAY,
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block SHT$$INIT_ARRAY };
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define block .ram.data with fixed order{ section .data*,
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section DATA,
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section .iar.init_table,
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section __DLIB_PERTHREAD,
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block CPP_INIT,
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section .mdns.data,
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section .mdns.text
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};
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define block .ram.text with fixed order{ section .image2.ram.text*,
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};
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define block IMAGE2 with fixed order { block .ram_image2.entry,
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block .ram.data,
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block .ram.text,
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};
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define block .ram_image2.bss with fixed order{ section .bss*,
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section COMMON,
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};
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define block .ram_image2.skb.bss with fixed order{ section .bdsram.data* };
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define block .ram_heap.data with fixed order{ section .bfsram.data* };
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place at start of BD_RAM_region { readwrite,
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block IMAGE2,
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block .ram_image2.bss,
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block .ram_image2.skb.bss,
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block .ram_heap.data,
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section .heap.stdlib,
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};
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/****************************************
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* XIP BOOT Section config *
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****************************************/
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keep { section .flashboot.text* };
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define block .xip_image1.text with fixed order{ section .flashboot.text* };
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define block Bootloader with fixed order { section LOADER };
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place at start of XIP_BOOT_region { block Bootloader,
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readwrite,
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block .xip_image1.text };
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/****************************************
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* XIP OTA1 Section config *
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****************************************/
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define block .xip_image2.text with fixed order{ section .img2_custom_signature*,
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section .text*,
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section .rodata,
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section .debug_trace,
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section CODE,
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section Veneer, // object startup.o,
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};
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place at start of XIP_OTA1_region { readwrite,
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block .xip_image2.text };
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/****************************************
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* RDP Section config *
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****************************************/
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keep { section .rdp.ram.text* };
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keep { section .rdp.ram.data* };
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define block .RDP_RAM with fixed order {
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section .rdp.ram.text*,
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section .rdp.ram.data* };
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place at start of RDP_RAM_region{
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readwrite,
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block .RDP_RAM };
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define exported symbol __ram_start_table_start__= 0x10002000; // use in rom
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define exported symbol __image1_validate_code__= 0x10002018; // needed by ram code
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define exported symbol __rom_top_4k_start_= 0x1003F000; // needed by ram code
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define exported symbol __flash_text_start__= 0x0800b020; // needed by ram code
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define exported symbol boot_export_symbol = 0x10002020;
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