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https://github.com/taubel/sdk-ameba-v4.0b-gcc.git
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161 lines
4.9 KiB
C
161 lines
4.9 KiB
C
/**************************************************************************//**
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* @file system_ARMCM3.c
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* @brief CMSIS Device System Source File for
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* ARMCM3 Device Series
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* @version V1.08
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* @date 23. November 2012
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*
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* @note
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*
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******************************************************************************/
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/* Copyright (c) 2011 - 2012 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#include "basic_types.h"
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#include "ameba_soc.h"
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/*----------------------------------------------------------------------------
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Define clocks
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*----------------------------------------------------------------------------*/
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#define __SYSTEM_CLOCK PLATFORM_CLOCK
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/*----------------------------------------------------------------------------
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Clock Variable definitions
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*----------------------------------------------------------------------------*/
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uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
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u32
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SystemGetCpuClk(void)
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{
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#ifdef CONFIG_FPGA
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return CPU_ClkGet(_TRUE);
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#else
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return CPU_ClkGet(_FALSE);
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#endif
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}
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/*----------------------------------------------------------------------------
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Clock functions
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*----------------------------------------------------------------------------*/
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void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
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{
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SystemCoreClock = SystemGetCpuClk();
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}
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System.
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*/
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void SystemInit (void)
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{
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// TODO: Hardware initial
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#ifdef UNALIGNED_SUPPORT_DISABLE
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SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
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#endif
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SystemCoreClockUpdate();
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}
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/**
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* @brief Generate random seed
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* @param none
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* @return value: random seed value
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*/
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u32 Gen_RandomSeed(VOID)
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{
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u32 adc_tmp, isr, AdcTempDat;
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u8 random_tmp, random[4];
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ADC_TypeDef *adc = ADC;
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int i, j;
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/* init ADC*/
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ADC_InitTypeDef AdcInitStruct;
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ADC_InitStruct(&AdcInitStruct);
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AdcInitStruct.ADC_BurstSz = 2;
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ADC_AnaparAd[1] = 0x41004;
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InterruptDis(ADC_IRQ);
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PLL2_Set(BIT_SYS_SYSPLL_CK_ADC_EN, ENABLE);
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RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
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ADC_Init(&AdcInitStruct);
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/* Clear ADC Status */
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ADC_INTClear();
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ADC_INTConfig(BIT_ADC_FIFO_FULL_EN|BIT_ADC_FIFO_RD_REQ_EN, ENABLE);
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ADC_Cmd(ENABLE);
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/* B CUT ADD patch for reset fail */
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AdcTempDat = adc->ANAPAR_AD1;
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AdcTempDat |= BIT(0);
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adc->ANAPAR_AD1 = AdcTempDat;
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for(i = 0; i < 4; i++){
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retry:
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random_tmp = 0;
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for (j = 0; j < 8; j++){
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while (1) {
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isr = ADC_GetISR();
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if (isr & (BIT_ADC_FIFO_FULL | BIT_ADC_FIFO_RD_REQ)) {
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adc_tmp = ADC_Read();
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ADC_Read();
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ADC_INTClear();
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ADC_INTConfig(BIT_ADC_FIFO_FULL_EN|BIT_ADC_FIFO_RD_REQ_EN, DISABLE);
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break;
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}
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}
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random_tmp |= ((adc_tmp & 0x1) << j);
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}
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if((random_tmp == 0x00) || (random_tmp == 0xff)){
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goto retry;
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}
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random[i] = random_tmp;
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}
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/* B CUT ADD patch for reset fail */
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AdcTempDat = adc->ANAPAR_AD1;
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AdcTempDat &= ~ BIT(0);
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adc->ANAPAR_AD1 = AdcTempDat;
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/* disable ADC*/
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ADC_Cmd(DISABLE);
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ADC_INTClear();
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PLL2_Set(BIT_SYS_SYSPLL_CK_ADC_EN, DISABLE);
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RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, DISABLE);
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return *(u32*)random;
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}
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