mirror of
https://github.com/taubel/sdk-ameba-v4.0b-gcc.git
synced 2026-07-01 00:55:38 +00:00
initial commit
This commit is contained in:
Tautvydas Belgeras
commit
60a7afcc83
2528 changed files with 1001987 additions and 0 deletions
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@ -0,0 +1,24 @@
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.PHONY: all copy clean
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#*****************************************************************************#
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# Source FILE LIST #
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#*****************************************************************************#
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CSRC = src inc
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#*****************************************************************************#
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# RULES TO GENERATE TARGETS #
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#*****************************************************************************#
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# Define the Rules to build the core targets
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all: copy
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copy:
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for cpf in $(CSRC); do \
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cp -rf $$cpf ../..; \
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done
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@ -0,0 +1,7 @@
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Example Description
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This example describes how to configure usoc to receive usb host data or send data.
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Behaviour:
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This example will print out interrupt information when usb device receive or send data.
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@ -0,0 +1,52 @@
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include $(MAKE_INCLUDE_GEN)
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#include ./Makefile.inc
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.PHONY: all clean
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CHIP = rtl8195a
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HALINCDIR = realtek/v3_0/include
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MODULE_IFLAGS += -I$(shell pwd -L)/../inc
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MODULE_IFLAGS += -I$(SWLIBDIR)/api
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MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
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MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
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MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
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MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
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GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
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#*****************************************************************************#
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# Source FILE LIST #
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#*****************************************************************************#
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CSRC += main.c
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#*****************************************************************************#
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# Object FILE LIST #
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#*****************************************************************************#
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OBJS = $(CSRC:.c=.o)
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#*****************************************************************************#
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# Object FILE LIST #
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#*****************************************************************************#
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#OBJS = monitor.o rtl_consol.o
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#*****************************************************************************#
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# RULES TO GENERATE TARGETS #
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#*****************************************************************************#
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# Define the Rules to build the core targets
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all: CORE_TARGETS COPY_RAM_OBJS
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#*****************************************************************************#
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# GENERATE OBJECT FILE
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#*****************************************************************************#
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CORE_TARGETS: $(OBJS)
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#*****************************************************************************#
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# GENERATE OBJECT FILE
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#*****************************************************************************#
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clean:
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rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#include "ameba_soc.h"
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#include "main.h"
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static USOC_TX_BD usocTXBD[USOC_TXBD_RING_SIZE];
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static USOC_RX_BD usocRXBD[USOC_RXBD_RING_SIZE];
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u8 HeaderPattern[58] = {0x59,0x05,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88,0x01,0x00,0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,
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0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x01,0x10,0x00,0x06,0x00,0x3f,0x05,0x00,0x04,0x00,0x00,0x01,0x00};
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void pkt_one_gen(u16 seqno, u16 pktlen, u8 seq)
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{
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int i;
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u32 rxbd_sw_idx = USOC_RXBD_SWIDX_Get(USOC_REG);
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u8 payload[USOC_RX_BUFFER_SIZE];
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for( i = 0; i < 58; i++)
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payload[i] = HeaderPattern[i];
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if(seq == 1) {
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for( i = 58; i < pktlen; i++) {
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payload[i] = (u8) i;
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}
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} else {
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for( i = 58; i < pktlen; i++) {
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payload[i] = 0x3E;
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}
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}
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if(usocRXBD[rxbd_sw_idx].status == RXBD_STAT_INIT) {
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usocRXBD[rxbd_sw_idx].address = (u32)payload;
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usocRXBD[rxbd_sw_idx].pktSize = pktlen;
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usocRXBD[rxbd_sw_idx].seqNum = seqno;
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usocRXBD[rxbd_sw_idx].status = RXBD_STAT_RDY;
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rxbd_sw_idx++;
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rxbd_sw_idx = rxbd_sw_idx%USOC_RXBD_RING_SIZE;
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}
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USOC_RXBD_SWIDX_Cfg(USOC_REG, rxbd_sw_idx);
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}
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void usoc_rxbd_irq_handle()
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{
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USOC_RX_BD* pRxbd = NULL;
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int i;
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/* change rxbd status when hw done */
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for( i = 0; i < USOC_RXBD_RING_SIZE; i++) {
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pRxbd = &usocRXBD[i];
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if(pRxbd->status == RXBD_STAT_OK ){
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pRxbd->status = RXBD_STAT_INIT;
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}
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}
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}
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void usoc_txbd_irq_handle()
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{
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USOC_TX_BD* pTxbd = NULL;
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u32 txbd_sw_idx = USOC_TXBD_SWIDX_Get(USOC_REG);
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int ret = SUCCESS;
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pTxbd = &usocTXBD[txbd_sw_idx];
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/* When TX has no data and RX is full quit loop */
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while(pTxbd->status == TXBD_STAT_OK) {
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DBG_8195A("tx bd seqno:%d addr:%x size:%d stat:%x\n", pTxbd->seqNum, pTxbd->address, pTxbd->pktSize, pTxbd->status);
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memset(pTxbd->address, 0, USOC_TX_BUFFER_SIZE);
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pTxbd->status = TXBD_STAT_RDY;
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txbd_sw_idx++;
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txbd_sw_idx = txbd_sw_idx%USOC_TXBD_RING_SIZE;
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pTxbd = &usocTXBD[txbd_sw_idx];
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}
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/* Update idx */
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USOC_TXBD_SWIDX_Cfg(USOC_REG, txbd_sw_idx);
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// pkt_one_gen(1, USOC_RX_BUFFER_SIZE, 0);
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}
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void usoc_isr_handle(void *DATA)
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{
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volatile u32 intr_stat = 0;
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intr_stat = USOC_INTGet(USOC_REG);
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if( intr_stat & BIT_INTR_RX_PKT_OK) {
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DBG_8195A(">>>>>>RX_PKT_OK interrupt>>>>>>\n");
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usoc_rxbd_irq_handle();
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/* Clear RX_PKT_OK */
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USOC_INTClr(USOC_REG, BIT_INTR_RX_PKT_OK);
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}
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if(intr_stat & BIT_INTR_TX_PKT_OK) {
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DBG_8195A(">>>>>>TX_PKT_OK interrupt>>>>>>\n");
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usoc_txbd_irq_handle();
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/* Clear TX_PKT_OK */
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USOC_INTClr(USOC_REG, BIT_INTR_TX_PKT_OK);
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}
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if( intr_stat & BIT_INTR_NO_TX_BD ) {
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USOC_INTClr(USOC_REG, BIT_INTR_NO_TX_BD);
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usoc_txbd_irq_handle();
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}
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if(intr_stat & ~(BIT_INTR_TX_PKT_OK | BIT_INTR_RX_PKT_OK | BIT_INTR_NO_TX_BD) ) {
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DBG_8195A("Error!Interrupt!!!\n");
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DBG_8195A("Interrupt status : %x\n", intr_stat);
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}
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/* Enable the interrupt */
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USOC_INTCfg(USOC_REG, USOC_INIT_INTR_MASK);
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}
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int usoc_txbd_init(void)
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{
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u32 i;
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/*init txbd */
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for( i=0 ; i<USOC_TXBD_RING_SIZE ; i++ )
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{
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/* For convinient just 4 bytes align */
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usocTXBD[i].address = (u32)_rtw_zmalloc(USOC_TX_BUFFER_SIZE);
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if(!usocTXBD[i].address) {
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DBG_8195A("Malloc fail : TXBD[%d] \n",i);
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usocTXBD[i].status = TXBD_STAT_INIT;
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return -1;
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}
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else {
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/* set status to ready */
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usocTXBD[i].status = TXBD_STAT_RDY;
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}
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}
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return 0;
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}
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int usoc_rxbd_init(void)
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{
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u32 i;
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/*init rxbd */
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for( i=0 ; i<USOC_RXBD_RING_SIZE ; i++ )
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{
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/* For convinient just 4 bytes align */
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usocRXBD[i].address = (u32)_rtw_zmalloc(USOC_RX_BUFFER_SIZE);
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if(!usocRXBD[i].address) {
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DBG_8195A("Malloc fail : RXBD[%d] \n",i);
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usocRXBD[i].status = RXBD_STAT_INIT;
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return -1;
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}
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else {
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usocRXBD[i].status = RXBD_STAT_INIT;
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}
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}
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return 0;
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}
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void usb_device(void)
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{
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int ret;
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USOC_InitTypeDef USOCInit_Struct;
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/* usoc init */
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RCC_PeriphClockCmd(APBPeriph_OTG, APBPeriph_OTG_CLOCK, DISABLE);
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USOC_POWER_On();
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/* Register the ISR */
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InterruptRegister((IRQ_FUN) usoc_isr_handle, USB_IRQ, NULL, 10);
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InterruptEn(USB_IRQ, 10);
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ret = usoc_txbd_init();
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if(ret != 0)
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goto fail;
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ret = usoc_rxbd_init();
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if(ret != 0)
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goto fail;
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/* disable usoc first */
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USOC_Cmd(USOC_REG, DISABLE);
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/* init SIE control register */
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USOC_MODE_Cfg(USOC_REG, USB_INIC_MODE);
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USOC_StructInit(&USOCInit_Struct);
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USOCInit_Struct.TXBD_BAR = (u32)usocTXBD; /* init txbd_bar */
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USOCInit_Struct.RXBD_BAR = (u32)usocRXBD; /* init rxbd_bar reg */
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USOC_Init(USOC_REG, &USOCInit_Struct);
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/* disable usoc mitigation function */
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USOC_MIT_Cfg(USOC_REG, DISABLE);
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/* Enable the interrupt */
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USOC_INTCfg(USOC_REG, USOC_INIT_INTR_MASK);
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HAL_WRITE8(SIE_REG_BASE, 0x5A, 1);
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HAL_WRITE8(SIE_REG_BASE, 0xF8, 0x80);
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/* enable usoc after init TXBD/RXBD */
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USOC_Cmd(USOC_REG, ENABLE);
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DelayUs(100);
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pkt_one_gen(1, USOC_RX_BUFFER_SIZE, 0);
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fail:
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vTaskDelete(NULL);
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}
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/**
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* @brief Main program.
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* @param None
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* @retval None
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*/
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void main(void)
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{
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if(xTaskCreate( (TaskFunction_t)usb_device, "USB DEVICE DEMO", (2048/4), NULL, (tskIDLE_PRIORITY + 1), NULL)!= pdPASS) {
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DBG_8195A("Cannot create usb device demo task\n\r");
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goto end_demo;
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}
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vTaskStartScheduler();
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end_demo:
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while(1);
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}
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