initial commit

project/realtek_amebaz_va0_example/example_sources/uart_clock/Makefile

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+
+
+.PHONY: all copy clean
+
+#*****************************************************************************#
+#                               Source FILE LIST                              #
+#*****************************************************************************#
+CSRC        = src inc
+		
+
+
+#*****************************************************************************#
+#                        RULES TO GENERATE TARGETS                            #
+#*****************************************************************************#
+
+# Define the Rules to build the core targets
+all: copy
+copy:
+		for cpf in $(CSRC); do \
+			cp -rf $$cpf ../..; \
+		done	 
+	
+
+

project/realtek_amebaz_va0_example/example_sources/uart_clock/readme.txt

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+Example Description
+
+This example describes how to use UART TX to simulate clock source
+
+Required Components:
+    Oscilloscope
+
+UART0 pin mappings used in this test demo:
+            PA23(TX)
+            PA18(RX)
+
+UART0 or UART1 can be used for us.
+Connect the TX pin of UART0 with the oscilloscope, and 
+we can watch the clock source waveform we want to generate.
+
+This example shows: 
+1. Clock signal output from UART1_TX to oscilloscope

project/realtek_amebaz_va0_example/example_sources/uart_clock/src/Makefile

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+
+include $(MAKE_INCLUDE_GEN)
+#include ./Makefile.inc
+
+.PHONY: all clean
+
+CHIP = rtl8195a
+HALINCDIR = realtek/v3_0/include
+
+MODULE_IFLAGS += -I$(shell pwd -L)/../inc
+MODULE_IFLAGS += -I$(SWLIBDIR)/api
+MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/hal/
+MODULE_IFLAGS += -I$(SWLIBDIR)/api/mbed/api/
+MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/cmsis/rtl8195a/
+MODULE_IFLAGS += -I$(SWLIBDIR)/drivers/targets/hal/rtl8195a/
+
+GLOBAL_CFLAGS += -DCONFIG_PLATFORM_8195A
+#*****************************************************************************#
+#                               Source FILE LIST                              #
+#*****************************************************************************#
+CSRC       += main.c 
+		
+		
+#*****************************************************************************#
+#                               Object FILE LIST                              #
+#*****************************************************************************#
+OBJS        = $(CSRC:.c=.o)
+
+
+#*****************************************************************************#
+#                               Object FILE LIST                              #
+#*****************************************************************************#
+#OBJS = monitor.o rtl_consol.o
+
+#*****************************************************************************#
+#                        RULES TO GENERATE TARGETS                            #
+#*****************************************************************************#
+
+# Define the Rules to build the core targets
+all: CORE_TARGETS COPY_RAM_OBJS
+	
+#*****************************************************************************#
+#              GENERATE OBJECT FILE 
+#*****************************************************************************#
+CORE_TARGETS:	$(OBJS)
+
+
+#*****************************************************************************#
+#              GENERATE OBJECT FILE 
+#*****************************************************************************#
+clean:
+	rm -f $(CSRC:.c=.o) $(CSRC:.c=.d) $(CSRC:.c=.i) $(CSRC:.c=.s)

project/realtek_amebaz_va0_example/example_sources/uart_clock/src/main.c

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+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2015 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#include "device.h"
+#include "serial_api.h"
+#include "serial_ex_api.h"
+#include "main.h"
+
+
+/*UART pin location:     
+   UART0: 
+   PA_23  (TX)
+   PA_18  (RX)
+   */
+#define UART_TX    PA_23	//UART0  TX
+#define UART_RX    PA_18	//UART0  RX
+
+/* 100 bytes data, 500 clocks, provide buadrate/2 frequency */
+#define SREAM_LEN 128
+char sim_clock[SREAM_LEN+1];
+
+
+volatile uint32_t is_stop = 0;
+static serial_t    sobj_clk;
+
+void uart_clock_send_string(serial_t *sobj, char *pstr)
+{
+    int32_t ret=0;
+
+    ret = serial_send_stream_dma(sobj, pstr, _strlen(pstr));
+    if (ret != 0) {
+        DBG_8195A("%s Error(%d)\n", __FUNCTION__, ret);        
+    }
+}
+
+void uart_clock_send_string_done(uint32_t id)
+{
+    serial_t    *sobj = (void*)id;
+	if(!is_stop)
+		uart_clock_send_string(sobj, sim_clock);
+}
+
+void uart_clock_deinit(void)
+{
+	is_stop = 1;
+	serial_free(&sobj_clk);
+}
+
+void uart_clock_init(int rate)
+{
+    //serial_t    sobj;
+    int ret;
+    int i;
+
+    for (i=0;i<SREAM_LEN;i++) {
+        sim_clock[i] = 0x55;
+    }
+    sim_clock[i] = 0;
+    
+    serial_init(&sobj_clk,UART_TX,UART_RX);
+	serial_baud(&sobj_clk, rate*2);
+    
+    serial_format(&sobj_clk, 8, ParityNone, 0);
+
+    serial_send_comp_handler(&sobj_clk, (void*)uart_clock_send_string_done, (uint32_t) &sobj_clk);
+}
+
+void uart_clock_on(void)
+{
+	is_stop = 0;
+	uart_clock_send_string(&sobj_clk, sim_clock);
+}
+
+void uart_clock_off(void)
+{
+	is_stop = 1;
+    serial_send_stream_abort(&sobj_clk);
+}
+
+void main(void)
+{
+	// only support 33kHz, 36kHz, 36.7kHz 38kHz, 40kHz, 56kHz
+	uart_clock_init(38000);
+	
+	while(1) {
+        uart_clock_on();
+        wait_ms(5000);
+        uart_clock_off();
+        wait_ms(5000);        
+    }
+
+}
+
+