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https://github.com/taubel/sdk-ameba-v4.0b-gcc.git
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initial commit
This commit is contained in:
Tautvydas Belgeras
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2528 changed files with 1001987 additions and 0 deletions
291
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c
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291
component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#include "rtl8195a.h"
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#include "rtl8195a_gdma.h"
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#include "hal_gdma.h"
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#ifndef CONFIG_CHIP_E_CUT
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BOOL
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HalGdmaChBlockSetingRtl8195a_Patch(
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IN VOID *Data
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)
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{
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PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
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PGDMA_CH_LLI_ELE pLliEle;
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struct GDMA_CH_LLI *pGdmaChLli;
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struct BLOCK_SIZE_LIST *pGdmaChBkLi;
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u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock;
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u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp;
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u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
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u8 ChNum = pHalGdmaAdapter->ChNum;
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u32 ChEn = pHalGdmaAdapter->ChEn;
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u8 GdmaChIsrBitmap = (ChEn & 0xFF);
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u8 PendingIsrIndex;
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pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
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pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
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pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
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//4 1) Check chanel is avaliable
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if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
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//4 Disable Channel
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DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
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HalGdmaChDisRtl8195a(Data);
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}
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//4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran, Error
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for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) {
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u32 PendRaw, PendStstus;
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PendRaw = HAL_GDMAX_READ32(GdmaIndex,
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(REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8));
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PendStstus = HAL_GDMAX_READ32(GdmaIndex,
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(REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8));
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if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) {
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//4 Clear Pending Isr
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HAL_GDMAX_WRITE32(GdmaIndex,
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(REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8),
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(PendStstus & (GdmaChIsrBitmap))
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);
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}
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}
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//4 Fill in SARx register
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HAL_GDMAX_WRITE32(GdmaIndex,
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(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF),
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(pHalGdmaAdapter->ChSar)
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);
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//4 Fill in DARx register
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HAL_GDMAX_WRITE32(GdmaIndex,
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(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF),
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(pHalGdmaAdapter->ChDar)
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);
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//4 3) Process CTLx
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CtlxLow = HAL_GDMAX_READ32(GdmaIndex,
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(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF));
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//4 Clear Config low register bits
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CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN &
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BIT_INVC_CTLX_LO_DST_TR_WIDTH &
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BIT_INVC_CTLX_LO_SRC_TR_WIDTH &
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BIT_INVC_CTLX_LO_DINC &
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BIT_INVC_CTLX_LO_SINC &
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BIT_INVC_CTLX_LO_DEST_MSIZE &
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BIT_INVC_CTLX_LO_SRC_MSIZE &
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BIT_INVC_CTLX_LO_TT_FC &
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BIT_INVC_CTLX_LO_LLP_DST_EN &
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BIT_INVC_CTLX_LO_LLP_SRC_EN);
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CtlxUp = HAL_GDMAX_READ32(GdmaIndex,
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(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4));
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//4 Clear Config upper register bits
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CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS &
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BIT_INVC_CTLX_UP_DONE);
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CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) |
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BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
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BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) |
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BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) |
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BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) |
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BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) |
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BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) |
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BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) |
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BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) |
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BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) |
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CtlxLow;
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CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) |
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BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) |
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CtlxUp;
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//4 Fill in CTLx register
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HAL_GDMAX_WRITE32(GdmaIndex,
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(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF),
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CtlxLow
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);
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HAL_GDMAX_WRITE32(GdmaIndex,
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(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4),
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CtlxUp
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);
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//4 4) Program CFGx
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CfgxLow = HAL_GDMAX_READ32(GdmaIndex,
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(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF));
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CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR &
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BIT_INVC_CFGX_LO_CH_SUSP &
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BIT_INVC_CFGX_LO_HS_SEL_DST &
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BIT_INVC_CFGX_LO_HS_SEL_SRC &
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BIT_INVC_CFGX_LO_LOCK_CH_L &
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BIT_INVC_CFGX_LO_LOCK_B_L &
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BIT_INVC_CFGX_LO_LOCK_CH &
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BIT_INVC_CFGX_LO_LOCK_B &
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BIT_INVC_CFGX_LO_RELOAD_SRC &
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BIT_INVC_CFGX_LO_RELOAD_DST);
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CfgxUp = HAL_GDMAX_READ32(GdmaIndex,
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(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4));
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CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE &
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BIT_INVC_CFGX_UP_DS_UPD_EN &
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BIT_INVC_CFGX_UP_SS_UPD_EN &
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BIT_INVC_CFGX_UP_SRC_PER &
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BIT_INVC_CFGX_UP_DEST_PER);
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CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) |
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BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) |
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BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) |
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BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) |
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BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) |
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BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) |
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BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) |
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BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) |
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BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) |
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BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) |
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CfgxLow;
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CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) |
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BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) |
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BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) |
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BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) |
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BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) |
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CfgxUp;
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HAL_GDMAX_WRITE32(GdmaIndex,
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(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF),
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CfgxLow
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);
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HAL_GDMAX_WRITE32(GdmaIndex,
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(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4),
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CfgxUp
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);
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//4 Check 4 Bytes Alignment
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if ((u32)(pLliEle) & 0x3) {
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DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!!!!\n",
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pHalGdmaAdapter->pLli);
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return _FALSE;
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}
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HAL_GDMAX_WRITE32(GdmaIndex,
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(REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF),
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pLliEle
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);
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//4 Update the first llp0
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pLliEle->CtlxLow = CtlxLow;
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pLliEle->CtlxUp = CtlxUp;
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pLliEle->Llpx = (u32)pGdmaChLli->pLliEle;
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DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
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pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
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while (MultiBlockCount > 1) {
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MultiBlockCount--;
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DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
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pLliEle = pGdmaChLli->pLliEle;
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if (NULL == pLliEle) {
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DBG_GDMA_ERR("pLliEle Null Point!!!!!\n");
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return _FALSE;
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}
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//4 Clear the last element llp enable bit
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if (1 == MultiBlockCount) {
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if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 1){
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CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN &
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BIT_INVC_CTLX_LO_LLP_SRC_EN);
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}
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}
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//4 Update block size for transfer
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CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
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CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
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//4 Update tje Lli and Block size list point to next llp
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pGdmaChLli = pGdmaChLli->pNextLli;
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pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
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//4 Updatethe Llpx context
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pLliEle->CtlxLow = CtlxLow;
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pLliEle->CtlxUp = CtlxUp;
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pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle);
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}
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return _TRUE;
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}
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u32
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HalGdmaQueryDArRtl8195a(
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IN VOID *Data
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)
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{
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PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
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u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
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u8 ChNum = pHalGdmaAdapter->ChNum;
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u32 dar;
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dar = HAL_GDMAX_READ32(GdmaIndex,
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(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF));
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return dar;
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}
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u32
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HalGdmaQuerySArRtl8195a(
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IN VOID *Data
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)
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{
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PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
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u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
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u8 ChNum = pHalGdmaAdapter->ChNum;
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u32 dar;
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dar = HAL_GDMAX_READ32(GdmaIndex,
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(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF));
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return dar;
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}
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BOOL
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HalGdmaQueryChEnRtl8195a (
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IN VOID *Data
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)
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{
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PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
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if (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN) & (pHalGdmaAdapter->ChEn)) {
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return 1;
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} else {
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return 0;
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}
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}
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#endif
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