initial commit

component/common/drivers/ethernet_mii/ethernet_mii.c

@@ -0,0 +1,377 @@
+#include "rtl8195a.h"
+#include "build_info.h"
+#ifdef PLATFORM_FREERTOS
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+#endif
+#include "osdep_service.h"
+#include "lwip_netconf.h"
+#include "ethernet_api.h"
+#include "lwip_intf.h"
+#include "ethernet_mii.h"
+#include "platform_opts.h"
+#include "ethernet_ex_api.h"
+
+static _sema mii_rx_sema;
+static _mutex mii_tx_mutex;
+extern volatile u32 ethernet_unplug;
+
+extern struct netif  xnetif[NET_IF_NUM];
+
+static u8 TX_BUFFER[1536];
+static u8 RX_BUFFER[1536];
+
+static u8 *pTmpTxDesc = NULL;
+static u8 *pTmpRxDesc = NULL;
+static u8 *pTmpTxPktBuf = NULL;
+static u8 *pTmpRxPktBuf = NULL;	
+
+int ethernet_init_done = 0;
+int dhcp_ethernet_mii = 1;
+int ethernet_if_default = 0;
+int link_is_up = 0;
+
+
+link_up_down_callback p_link_change_callback = 0;
+
+extern int lwip_init_done;
+
+static _sema mii_linkup_sema;
+
+void mii_rx_thread(void* param){
+	u32 len = 0;
+	u8* pbuf = RX_BUFFER;
+	while(1){
+		if (rtw_down_sema(&mii_rx_sema) == _FAIL){
+			DBG_8195A("%s, Take Semaphore Fail\n", __FUNCTION__);
+			goto exit;
+		}
+		// continues read the rx ring until its empty
+		while(1){
+			len = ethernet_receive();
+			if(len){
+				//DBG_8195A("mii_recv len = %d\n\r", len);
+				ethernet_read(pbuf, len);
+// calculate the time duration
+				ethernetif_mii_recv(&xnetif[ETHERNET_IDX], len);		
+				//__rtl_memDump_v1_00(pbuf, len, "ethernet_receive Data:");
+				//rtw_memset(pbuf, 0, len);
+			}else if(len == 0){
+				break;
+			}
+		}
+	}
+exit:
+	rtw_free_sema(&mii_rx_sema);
+	vTaskDelete(NULL);
+}
+
+void mii_intr_thread(void* param)
+{
+	u32 dhcp_status = 0;
+	
+	while(1)
+	{
+		if (rtw_down_sema(&mii_linkup_sema) == _FAIL){
+			DBG_8195A("%s, Take Semaphore Fail\n", __FUNCTION__);
+			break;
+		}
+
+		//Used to process there is no cable plugged in when power-on
+		if(1 == ethernet_unplug){
+			if(p_link_change_callback)
+				p_link_change_callback(link_is_up);
+		}
+
+		if(1 == ethernet_init_done){		
+			if(link_is_up){
+				DBG_8195A("...Link up\n");
+				if(dhcp_ethernet_mii == 1)
+		    		dhcp_status = LwIP_DHCP(ETHERNET_IDX, DHCP_START);
+				if(DHCP_ADDRESS_ASSIGNED == dhcp_status){
+					if(1 == ethernet_if_default)
+						netif_set_default(&xnetif[ETHERNET_IDX]);  //Set default gw to ether netif
+					else
+						netif_set_default(&xnetif[WLAN_IDX]);
+				}
+			}else{
+				DBG_8195A("...Link down\n");
+				netif_set_default(&xnetif[WLAN_IDX]);	//Set default gw to wlan netif
+#if CONFIG_LWIP_LAYER
+				LwIP_ReleaseIP(ETHERNET_IDX);
+#endif
+			}
+		
+			if(p_link_change_callback)
+				p_link_change_callback(link_is_up);
+		}
+	}
+	
+	rtw_free_sema(&mii_linkup_sema);
+	vTaskDelete(NULL);
+}
+
+
+void mii_intr_handler(u32 Event, u32 Data)
+{
+	switch(Event)
+	{
+		case ETH_TXDONE:
+			//DBG_8195A("TX Data = %d\n", Data);
+			break;
+		case ETH_RXDONE:
+			//DBG_8195A("\r\nRX Data = %d\n", Data);
+			// wake up rx thread to receive data
+			rtw_up_sema_from_isr(&mii_rx_sema);
+			break;
+		case ETH_LINKUP:
+			DBG_8195A("Link Up\n");
+			link_is_up = 1;
+			rtw_up_sema_from_isr(&mii_linkup_sema);
+			break;
+		case ETH_LINKDOWN:
+			DBG_8195A("Link Down\n");
+			link_is_up = 0;
+			rtw_up_sema_from_isr(&mii_linkup_sema);
+			break;
+		default:
+			DBG_8195A("Unknown event !!\n");
+			break;
+	}
+}
+
+void ethernet_demo(void* param){
+	u8 mac[6];
+	/* Initilaize the LwIP stack */
+	// can not init twice
+	if(!lwip_init_done)
+	  LwIP_Init();
+	DBG_8195A("LWIP Init done\n");
+
+	ethernet_irq_hook(mii_intr_handler);
+
+    if(pTmpTxDesc)
+    {
+        free(pTmpTxDesc);
+        pTmpTxDesc = NULL;
+    }
+    if(pTmpRxDesc)
+    {
+        free(pTmpRxDesc);
+        pTmpRxDesc = NULL;
+    }
+    if(pTmpTxPktBuf)
+    {
+        free(pTmpTxPktBuf);
+        pTmpTxPktBuf = NULL;
+    }
+    if(pTmpRxPktBuf)
+    {
+        free(pTmpRxPktBuf);
+        pTmpRxPktBuf = NULL;
+    }
+    
+    pTmpTxDesc = (u8 *)malloc(/*MII_TX_DESC_CNT*/MII_TX_DESC_NO * ETH_TX_DESC_SIZE);
+    pTmpRxDesc = (u8 *)malloc(/*MII_RX_DESC_CNT*/MII_RX_DESC_NO * ETH_RX_DESC_SIZE);
+    pTmpTxPktBuf = (u8 *)malloc(/*MII_TX_DESC_CNT*/MII_TX_DESC_NO * ETH_PKT_BUF_SIZE);
+    pTmpRxPktBuf = (u8 *)malloc(/*MII_RX_DESC_CNT*/MII_RX_DESC_NO * ETH_PKT_BUF_SIZE);
+    if(pTmpTxDesc == NULL || pTmpRxDesc == NULL || pTmpTxPktBuf == NULL || pTmpRxPktBuf == NULL)
+    {
+        printf("TX/RX descriptor malloc fail\n");
+        return;
+    }
+    memset(pTmpTxDesc, 0, MII_TX_DESC_NO * ETH_TX_DESC_SIZE);
+    memset(pTmpRxDesc, 0, MII_RX_DESC_NO * ETH_RX_DESC_SIZE);
+    memset(pTmpTxPktBuf, 0, MII_TX_DESC_NO * ETH_PKT_BUF_SIZE);
+    memset(pTmpRxPktBuf, 0, MII_RX_DESC_NO * ETH_PKT_BUF_SIZE);
+    //size 160        128     12288   12288            
+    
+    ethernet_set_descnum(MII_TX_DESC_NO, MII_RX_DESC_NO);
+    printf("TRX descriptor number setting done\n");
+    ethernet_trx_pre_setting(pTmpTxDesc, pTmpRxDesc, pTmpTxPktBuf, pTmpRxPktBuf);
+    printf("TRX pre setting done\n");
+
+	ethernet_init();
+
+	DBG_INFO_MSG_OFF(_DBG_MII_);  
+	DBG_WARN_MSG_OFF(_DBG_MII_);
+	DBG_ERR_MSG_ON(_DBG_MII_);
+	
+	/*get mac*/
+	ethernet_address(mac);
+	memcpy((void*)xnetif[ETHERNET_IDX].hwaddr,(void*)mac, 6);
+
+	rtw_init_sema(&mii_rx_sema,0);
+	rtw_mutex_init(&mii_tx_mutex);
+
+	if(xTaskCreate(mii_rx_thread, ((const char*)"mii_rx_thread"), 1024, NULL, tskIDLE_PRIORITY+5, NULL) != pdPASS)
+		DBG_8195A("\n\r%s xTaskCreate(mii_rx_thread) failed", __FUNCTION__);
+	
+	DBG_8195A("\nEthernet_mii Init done, interface %d", ETHERNET_IDX);
+	
+	if(dhcp_ethernet_mii == 1){
+	  LwIP_DHCP(ETHERNET_IDX, DHCP_START);
+	  netif_set_default(&xnetif[ETHERNET_IDX]);  //Set default gw to ether netif
+	}
+	ethernet_init_done = 1;
+	
+	vTaskDelete(NULL);
+}
+
+int ethernet_is_linked()
+{
+	 if((link_is_up == 1)&&(1 == ethernet_init_done))
+		   return TRUE;
+	 else
+		   return FALSE;
+}
+
+int ethernet_is_unplug()
+{
+	if(ethernet_unplug == 1)
+		   return TRUE;
+	 else
+		   return FALSE;
+}
+
+
+void ethernet_mii_init()
+{
+	printf("\ninitializing Ethernet_mii......\n");
+  
+	// set the ethernet interface as default
+	ethernet_if_default = 1;
+	vSemaphoreCreateBinary(mii_linkup_sema);
+	if( xTaskCreate((TaskFunction_t)mii_intr_thread, "DHCP_START_MII", 1024, NULL, 3, NULL) != pdPASS) {
+		DBG_8195A("Cannot create demo task\n\r");
+	}	
+
+	if( xTaskCreate((TaskFunction_t)ethernet_demo, "ETHERNET DEMO", 1024, NULL, 2, NULL) != pdPASS) {
+		DBG_8195A("Cannot create demo task\n\r");
+	}
+#if 0
+	extern void ethernet_wlan_iperf_test_task(void *param);
+	if(xTaskCreate((TaskFunction_t)ethernet_wlan_iperf_test_task, "wifi_entry_task", 1024, NULL, 2, NULL) != pdPASS){
+		printf("\n\r%s xTaskCreate(wifi_entry_task) failed", __FUNCTION__);
+	}
+#endif
+	
+}
+
+
+void rltk_mii_recv(struct eth_drv_sg *sg_list, int sg_len){
+	struct eth_drv_sg *last_sg;
+	u8* pbuf = RX_BUFFER;
+
+	for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
+		if (sg_list->buf != 0) {
+			rtw_memcpy((void *)(sg_list->buf), pbuf, sg_list->len);
+			pbuf+=sg_list->len;
+		}			 
+	}
+}
+
+
+s8 rltk_mii_send(struct eth_drv_sg *sg_list, int sg_len, int total_len){
+	int ret =0;
+	struct eth_drv_sg *last_sg;
+	u8* pdata = TX_BUFFER;
+	u8	retry_cnt = 0;
+	u32 size = 0;
+	for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
+		rtw_memcpy(pdata, (void *)(sg_list->buf), sg_list->len);
+		pdata += sg_list->len;
+		size += sg_list->len;		
+	}
+	pdata = TX_BUFFER;
+	//DBG_8195A("mii_send len= %d\n\r", size);
+	rtw_mutex_get(&mii_tx_mutex);
+	while(1){
+		ret = ethernet_write(pdata, size);
+		if(ret > 0){
+			ethernet_send();
+			ret = 0;
+			break;
+		}
+		if(++retry_cnt > 3){
+			DBG_8195A("TX drop\n\r");
+			ret = -1;
+		}
+		else
+			rtw_udelay_os(1);
+	}
+	rtw_mutex_put(&mii_tx_mutex);
+
+	return ret; 	
+}
+
+#define ____TEST____
+/* used for test */
+#if 0
+#include "wifi_constants.h"
+struct iperf_data_t{
+	uint64_t total_size;
+	uint64_t bandwidth;
+	int  server_fd;
+	int  client_fd;
+	uint32_t buf_size;
+	uint32_t time;
+	uint32_t report_interval;
+	uint16_t port;
+	uint8_t  server_ip[16];
+	uint8_t  start;
+	uint8_t  tos_value;
+};
+
+/*ATWT=-c,192.168.31.111,-t,10*/
+int ethernet_wlan_iperf_test()
+{
+	char server_ip[] = "192.168.31.111";
+	u16  time = 10;
+	struct iperf_data_t tcp_client_data;
+
+	printf("\n###################ethernet wlan iperf test !!!...\n");
+	memset(&tcp_client_data, 0, sizeof(tcp_client_data));
+
+	strncpy(tcp_client_data.server_ip, server_ip, (strlen(server_ip)>16)?16:strlen(server_ip));
+	tcp_client_data.time = time;
+	tcp_client_data.bandwidth = 268459220;
+	tcp_client_data.buf_size = 1460;
+	tcp_client_data.client_fd = 0;
+	tcp_client_data.port = 5001;
+	tcp_client_data.report_interval = -1;
+	tcp_client_data.server_fd = 0;
+	tcp_client_data.start = 1;
+	tcp_client_data.tos_value = 0;
+	tcp_client_data.total_size = 0;
+	
+	tcp_client_func(tcp_client_data);
+
+	return 0;	
+}
+
+void ethernet_wlan_iperf_test_task(void *param)
+{
+	printf("\n#########################ethernet wlan iperf test task...\n");
+
+	/* used for test */
+	p_link_change_callback = (link_up_down_callback)ethernet_wlan_iperf_test;
+	
+	/*sys_reset is not necessary, upper layer can define p_link_change_callback on demand*/
+	//p_link_change_callback = (link_up_down_callback)sys_reset();
+	while(1)
+	{
+		if(((wifi_is_ready_to_transceive(RTW_STA_INTERFACE)==RTW_SUCCESS)&&ethernet_is_unplug())||(ethernet_is_linked()))
+			break;
+		else
+			vTaskDelay(500);
+	}
+	ethernet_wlan_iperf_test();
+	
+	printf("\r\n[%s] task del", __func__);
+	vTaskDelete(NULL);
+}
+
+#endif
+

component/common/drivers/ethernet_mii/ethernet_mii.h

@@ -0,0 +1,14 @@
+#ifndef __MII_ETHERNETIF_H__
+#define __MII_ETHERNETIF_H__
+
+#include "lwip_netconf.h"
+
+#define MII_TX_DESC_CNT		4
+#define MII_RX_DESC_CNT		10
+
+#define ETHERNET_IDX (NET_IF_NUM - 1)
+#define WLAN_IDX 0
+
+typedef void (*link_up_down_callback)(int blinkup);
+
+#endif // __MII_ETHERNETIF_H__

component/common/drivers/i2s/alc5640.c

@@ -0,0 +1,181 @@
+#include <stdio.h>
+#include "FreeRTOS.h"
+#include "PinNames.h"
+#include "basic_types.h"
+#include "diag.h" 
+#include <osdep_api.h>
+
+#include "i2c_api.h"
+#include "pinmap.h"
+
+//#define I2C_MTR_SDA			PC_4//PB_3
+//#define I2C_MTR_SCL			PC_5//PB_2
+#if defined(CONFIG_PLATFORM_8195A)
+	#define I2C_MTR_SDA			PB_3
+	#define I2C_MTR_SCL			PB_2
+#elif defined(CONFIG_PLATFORM_8711B)
+	#define I2C_MTR_SDA			PA_30
+	#define I2C_MTR_SCL			PA_29
+#endif 
+#define I2C_BUS_CLK			100000  //hz
+
+#define I2C_ALC5640_ADDR	(0x38/2)
+
+#define RT5640_PRIV_INDEX	0x6a
+#define RT5640_PRIV_DATA	0x6c
+	 
+#if defined (__ICCARM__)
+i2c_t   alc5640_i2c;
+#else
+volatile i2c_t   alc5640_i2c;
+#endif
+
+static void alc5640_delay(void)
+{
+    int i;
+
+	i=10000;
+    while (i) {
+        i--;
+        asm volatile ("nop\n\t");
+    }
+}
+
+void alc5640_reg_write(unsigned int reg, unsigned int value)
+{
+	char buf[4];
+	buf[0] = (char)reg;
+	buf[1] = (char)(value>>8);
+	buf[2] = (char)(value&0xff);
+	
+	i2c_write(&alc5640_i2c, I2C_ALC5640_ADDR, &buf[0], 3, 1);
+	alc5640_delay();
+}
+
+void alc5640_reg_read(unsigned int reg, unsigned int *value)
+{
+	int tmp;
+	char *buf = (char*)&tmp;	
+	
+	buf[0] = (char)reg;
+	i2c_write(&alc5640_i2c, I2C_ALC5640_ADDR, &buf[0], 1, 1);
+	alc5640_delay();
+	
+	buf[0] = 0xaa;
+	buf[1] = 0xaa;
+	
+	i2c_read(&alc5640_i2c, I2C_ALC5640_ADDR, &buf[0], 2, 1);
+	alc5640_delay();
+	
+	*value= ((buf[0]&0xFF)<<8)|(buf[1]&0xFF); 
+}
+
+void alc5640_index_write(unsigned int reg, unsigned int value)
+{
+	alc5640_reg_write(RT5640_PRIV_INDEX, reg);
+	alc5640_reg_write(RT5640_PRIV_DATA, value);
+}
+
+void alc5640_index_read(unsigned int reg, unsigned int *value)
+{
+	alc5640_reg_write(RT5640_PRIV_INDEX, reg);
+	alc5640_reg_read(RT5640_PRIV_DATA, value);
+}
+
+void alc5640_reg_dump(void)
+{
+	int i;
+	unsigned int value;
+  
+	printf("alc5640 codec reg dump\n\r");
+	printf("------------------------\n\r");
+	for(i=0;i<=0xff;i++){
+		alc5640_reg_read(i, &value);
+		printf("%02x : %04x\n\r", i, (unsigned short)value);
+	}
+	printf("------------------------\n\r");
+}
+
+void alc5640_index_dump(void)
+{
+	int i;
+	unsigned int value;
+  
+	printf("alc5640 codec index dump\n\r");
+	printf("------------------------\n\r");
+	for(i=0;i<=0xff;i++){
+		alc5640_index_read(i, &value);
+		printf("%02x : %04x\n\r", i, (unsigned short)value);
+	}
+	printf("------------------------\n\r");
+}
+
+void alc5640_init(void)
+{
+    i2c_init(&alc5640_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
+    i2c_frequency(&alc5640_i2c, I2C_BUS_CLK);
+}
+
+void alc5640_set_word_len(int len_idx)	// interface2
+{
+	// 0: 16 1: 20 2: 24 3: 8
+	unsigned int val;
+	alc5640_reg_read(0x71,&val);
+	val &= (~(0x3<<2));
+	val |= (len_idx<<2);
+	alc5640_reg_write(0x71,val);
+	alc5640_reg_read(0x70,&val);
+	val &= (~(0x3<<2));
+	val |= (len_idx<<2);
+	alc5640_reg_write(0x70,val);	
+	
+}
+
+void alc5640_init_interface1(void)
+{
+    // I2S1 -> DAC -> SPK R/L
+    alc5640_reg_write(0x00,0x0021);
+    alc5640_reg_write(0xD9,0x0009);
+    alc5640_reg_write(0x73,0x0014);
+    alc5640_reg_write(0xFA,0x3401);
+    alc5640_index_write(0x1C,0x0D21);
+    alc5640_reg_write(0x63,0xA8F0);
+    wait_ms(100);  // delay 100 ms.
+    alc5640_reg_write(0x63,0xE8F8);
+    alc5640_reg_write(0x61,0x9801);
+    alc5640_index_write(0x3D,0x2600);
+    alc5640_index_write(0x1C,0xFD21);
+    alc5640_reg_write(0x2A,0x1414);
+    alc5640_reg_write(0x48,0xB800);
+    alc5640_reg_write(0x49,0x1800);
+    alc5640_reg_write(0x01,0x4848);
+    alc5640_reg_write(0xD9,0x0809);  
+}
+
+void alc5640_init_interface2(void)
+{
+    alc5640_reg_write(0x00,0x0021);
+    alc5640_reg_write(0x63,0xE8FE);
+    alc5640_reg_write(0x61,0x5800);
+    alc5640_reg_write(0x62,0x0C00);
+    alc5640_reg_write(0x73,0x0000);
+    alc5640_reg_write(0x2A,0x4242);
+    alc5640_reg_write(0x45,0x2000);
+    alc5640_reg_write(0x02,0x4848);
+    alc5640_reg_write(0x8E,0x0019);
+    alc5640_reg_write(0x8F,0x3100);
+    alc5640_reg_write(0x91,0x0E00);
+    alc5640_index_write(0x3D,0x3E00);
+    alc5640_reg_write(0xFA,0x0011);
+    alc5640_reg_write(0x83,0x0800);
+    alc5640_reg_write(0x84,0xA000);
+    alc5640_reg_write(0xFA,0x0C11);
+    alc5640_reg_write(0x64,0x4010);
+    alc5640_reg_write(0x65,0x0C00);
+    alc5640_reg_write(0x61,0x5806);
+    alc5640_reg_write(0x62,0xCC00);
+    alc5640_reg_write(0x3C,0x004F);
+    alc5640_reg_write(0x3E,0x004F);
+    alc5640_reg_write(0x28,0x3030);
+    alc5640_reg_write(0x2F,0x0080);	
+}

component/common/drivers/i2s/alc5640.h

@@ -0,0 +1,9 @@
+#ifndef _ALC5640_H_
+#define _ALC5640_H_
+void alc5640_reg_dump(void);
+void alc5640_index_dump(void);
+void alc5640_init(void);
+void alc5640_set_word_len(int len_idx);
+void alc5640_init_interface1(void);
+void alc5640_init_interface2(void);
+#endif

component/common/drivers/i2s/alc5651.c

@@ -0,0 +1,201 @@
+#include <stdio.h>
+#include "PinNames.h"
+#include "basic_types.h"
+#include "diag.h" 
+#include <osdep_api.h>
+
+#include "i2c_api.h"
+#include "pinmap.h"
+
+//#define I2C_MTR_SDA			PC_4//PB_3
+//#define I2C_MTR_SCL			PC_5//PB_2
+#if defined(CONFIG_PLATFORM_8195A)
+	#define I2C_MTR_SDA			PB_3
+	#define I2C_MTR_SCL			PB_2
+#elif defined(CONFIG_PLATFORM_8711B)
+	#define I2C_MTR_SDA			PA_30
+	#define I2C_MTR_SCL			PA_29
+#endif 
+#define I2C_BUS_CLK			100000  //hz
+
+#define I2C_ALC5651_ADDR	(0x34/2)
+
+#define RT5651_PRIV_INDEX	0x6a
+#define RT5651_PRIV_DATA	0x6c
+	 
+#if defined (__ICCARM__)
+i2c_t   alc5651_i2c;
+#else
+volatile i2c_t   alc5651_i2c;
+#define printf  DBG_8195A
+#endif
+
+static void alc5651_delay(void)
+{
+    int i;
+
+	i=10000;
+    while (i) {
+        i--;
+        asm volatile ("nop\n\t");
+    }
+}
+
+void alc5651_reg_write(unsigned int reg, unsigned int value)
+{
+	char buf[4];
+	buf[0] = (char)reg;
+	buf[1] = (char)(value>>8);
+	buf[2] = (char)(value&0xff);
+	
+	i2c_write(&alc5651_i2c, I2C_ALC5651_ADDR, &buf[0], 3, 1);
+	alc5651_delay();
+}
+
+void alc5651_reg_read(unsigned int reg, unsigned int *value)
+{
+	int tmp;
+	char *buf = (char*)&tmp;	
+	
+	buf[0] = (char)reg;
+	i2c_write(&alc5651_i2c, I2C_ALC5651_ADDR, &buf[0], 1, 1);
+	alc5651_delay();
+	
+	buf[0] = 0xaa;
+	buf[1] = 0xaa;
+	
+	i2c_read(&alc5651_i2c, I2C_ALC5651_ADDR, &buf[0], 2, 1);
+	alc5651_delay();
+	
+	*value= ((buf[0]&0xFF)<<8)|(buf[1]&0xFF); 
+}
+
+void alc5651_index_write(unsigned int reg, unsigned int value)
+{
+	alc5651_reg_write(RT5651_PRIV_INDEX, reg);
+	alc5651_reg_write(RT5651_PRIV_DATA, value);
+}
+
+void alc5651_index_read(unsigned int reg, unsigned int *value)
+{
+	alc5651_reg_write(RT5651_PRIV_INDEX, reg);
+	alc5651_reg_read(RT5651_PRIV_DATA, value);
+}
+
+void alc5651_reg_dump(void)
+{
+	int i;
+	unsigned int value;
+  
+	printf("alc5651 codec reg dump\n\r");
+	printf("------------------------\n\r");
+	for(i=0;i<=0xff;i++){
+		alc5651_reg_read(i, &value);
+		printf("%02x : %04x\n\r", i, (unsigned short)value);
+	}
+	printf("------------------------\n\r");
+}
+
+void alc5651_index_dump(void)
+{
+	int i;
+	unsigned int value;
+  
+	printf("alc5651 codec index dump\n\r");
+	printf("------------------------\n\r");
+	for(i=0;i<=0xff;i++){
+		alc5651_index_read(i, &value);
+		printf("%02x : %04x\n\r", i, (unsigned short)value);
+	}
+	printf("------------------------\n\r");
+}
+
+void alc5651_init(void)
+{
+    i2c_init(&alc5651_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
+    i2c_frequency(&alc5651_i2c, I2C_BUS_CLK);
+}
+
+void alc5651_set_word_len(int len_idx)	// interface2
+{
+	// 0: 16 1: 20 2: 24 3: 8
+	unsigned int val;
+	alc5651_reg_read(0x71,&val);
+	val &= (~(0x3<<2));
+	val |= (len_idx<<2);
+	alc5651_reg_write(0x71,val);
+	alc5651_reg_read(0x70,&val);
+	val &= (~(0x3<<2));
+	val |= (len_idx<<2);
+	alc5651_reg_write(0x70,val);	
+	
+}
+
+void alc5651_init_interface1(void)
+{
+    alc5651_reg_write(0x00,0x0021);
+    alc5651_reg_write(0x63,0xE8FE);
+    alc5651_reg_write(0x61,0x5800);
+    alc5651_reg_write(0x62,0x0C00);
+    alc5651_reg_write(0x73,0x0000);
+    alc5651_reg_write(0x2A,0x4242);
+    alc5651_reg_write(0x45,0x2000);
+    alc5651_reg_write(0x02,0x4848);
+    alc5651_reg_write(0x8E,0x0019);
+    alc5651_reg_write(0x8F,0x3100);
+    alc5651_reg_write(0x91,0x0E00);
+    alc5651_index_write(0x3D,0x3E00);
+    alc5651_reg_write(0xFA,0x0011);
+    alc5651_reg_write(0x83,0x0800);
+    alc5651_reg_write(0x84,0xA000);
+    alc5651_reg_write(0xFA,0x0C11);
+    alc5651_reg_write(0x64,0x4010);
+    alc5651_reg_write(0x65,0x0C00);
+    alc5651_reg_write(0x61,0x5806);
+    alc5651_reg_write(0x62,0xCC00);
+    alc5651_reg_write(0x3C,0x004F);
+    alc5651_reg_write(0x3E,0x004F);
+    alc5651_reg_write(0x27,0x3820);
+    alc5651_reg_write(0x77,0x0000);	
+}
+
+void alc5651_init_interface2(void)
+{
+  	int reg_value=0;
+    alc5651_reg_write(0x00,0x0021);//reset all, device id 1
+	alc5651_reg_write(0x63,0xE8FE);//Power managerment control 3: 
+	//VREF1&2 on, both slow VREF, MBIAS on, MBIAS bandcap power on, L & R HP Amp on, improve HP Amp driving enabled
+	alc5651_reg_write(0x61,0x5800);//power managerment control 1:
+	//I2S2 digital interface on, Analog DACL1 & DACR1 on. 
+    alc5651_reg_write(0x62,0x0C00);//stereo1 & 2 DAC filter power on
+	alc5651_reg_write(0x73,0x0000);//ADC/DAC Clock control 1:
+	//I2S Clock Pre-Divider 1 & 2: /1.  Stereo DAC Over Sample Rate : 128Fs
+    alc5651_reg_write(0x2A,0x4242);//Stereo DAC digital mixer control
+	//Un-mute DACL2 to Stereo DAC Left & Right Mixer
+	alc5651_reg_write(0x45,0x2000);//HPOMIX: Un-mute DAC1 to HPOMIX
+	alc5651_reg_write(0x02,0x4848);//HP Output Control:
+	//Unmute HPOL, HPOR
+//    alc5651_reg_write(0x0F,0x1F1F);//INL & INR Volume Control
+//    alc5651_reg_write(0x0D,0x0800);//IN1/2 Input Control
+//    alc5651_reg_write(0x1C,0x7F7F);//Stereo1 ADC Digital Volume Control
+//    alc5651_reg_write(0x1E,0xF000);// ADC Digital Boost Gain Control
+    alc5651_reg_write(0x8E,0x0019);//HP Amp Control 1
+//	Enable HP Output, Charge Pump Power On, HP Amp All Power On
+    alc5651_reg_write(0x8F,0x3100);//HP Amp Control 2, HP Depop Mode 2
+    alc5651_reg_write(0x91,0x0E00);//HP Amp Control 3, select HP capless power mode
+    alc5651_index_write(0x3D,0x3E00);//unknown
+    alc5651_reg_write(0xFA,0x0011);//enable input clock
+    alc5651_reg_write(0x83,0x0800);//default ASRC control 1
+	alc5651_reg_write(0x84,0xA000);//ASRC control 2: I2S1 enable ASRC mode, Sterol1 DAC filter ASRC mode. 
+//	alc5651_reg_write(0xFA,0x0C11);//?  ?  ?  MX-FAh[15:4]reserved
+	alc5651_reg_write(0x64,0x4010);//power managerment control 4: 
+	//MIC BST2 Power On; MIC2 SE Mode single-end mode or line-input mode
+	alc5651_reg_write(0x65,0x0C00);//power managerment control 5:  RECMIX L & R power on
+	alc5651_reg_write(0x61,0x5806);//power managerment control 1: 
+//	I2S2 Digital Interface On, Analog DACL1, DACR1 power on; Analog ADCL, ADCR power on
+	alc5651_reg_write(0x62,0xCC00);//power managerment control 2: Stereo1&2 ADC/DAC digital filter power on
+    alc5651_reg_write(0x3C,0x004F);//RECMIXL
+    alc5651_reg_write(0x3E,0x004F);//RECMIXR
+	alc5651_reg_write(0x28,0x3030);//stereo2 ADC digital mixer control : Mute Stereo2 ADC L&R channel, ADCR
+	alc5651_reg_write(0x2F,0x0080);	//Interface DAC/ADC Data control: Select IF2 ADCDAT Data Source IF1_ADC2 
+}

component/common/drivers/i2s/alc5651.h

@@ -0,0 +1,9 @@
+#ifndef _ALC5651_H_
+#define _ALC5651_H_
+void alc5651_reg_dump(void);
+void alc5651_index_dump(void);
+void alc5651_init(void);
+void alc5651_set_word_len(int len_idx);
+void alc5651_init_interface1(void);
+void alc5651_init_interface2(void);
+#endif

component/common/drivers/i2s/alc5679.c

@@ -0,0 +1,227 @@
+#include "PinNames.h"
+#include "basic_types.h"
+#include <osdep_api.h>
+
+#include "i2c_api.h"
+#include "i2c_ex_api.h"
+#include "pinmap.h"
+#include "wait_api.h"
+#include "alc5679.h"
+
+#define I2C_ALC5679_ADDR	        (0X5A/2)//(0x58/2)
+#if defined(CONFIG_PLATFORM_8195A)
+	#define I2C_MTR_SDA			PB_3
+	#define I2C_MTR_SCL			PB_2
+#elif defined(CONFIG_PLATFORM_8711B)
+	#define I2C_MTR_SDA			PA_30
+	#define I2C_MTR_SCL			PA_29
+#endif 
+#define I2C_BUS_CLK			100000  //100K HZ
+
+//i2c_t   rt5679_i2c;
+#if defined (__ICCARM__)
+i2c_t   rt5679_i2c;
+#else
+volatile i2c_t   rt5679_i2c;
+#define printf  DBG_8195A
+#endif
+
+
+static void rt5679_delay(void)
+{
+    int i;
+    
+    i=10000;
+    
+    while (i) {
+        i--;
+        asm volatile ("nop\n\t");
+    }
+}
+
+u8 rt5679_reg_write(u16 reg, u16 val)
+{
+	int length = 0;
+	char buf[4];
+	buf[0] = (char)(reg >> 8);
+	buf[1] = (char)(reg&0xff);
+	buf[2] = (char)(val>>8);
+	buf[3] = (char)(val&0xff);
+
+	length = i2c_write(&rt5679_i2c, I2C_ALC5679_ADDR, &buf[0], 4, 1);
+        rt5679_delay();
+	return (length==4)?0:1;
+}
+
+u8 rt5679_reg_read(u16 reg, u16* val)
+{
+	int tmp;
+	char *buf = (char*)&tmp;	
+	u8 ret = 0;
+	
+	buf[0] = (char)(reg >> 8);
+	buf[1] = (char)(reg&0xff);
+        
+	if(i2c_write(&rt5679_i2c, I2C_ALC5679_ADDR, &buf[0], 2, 1) != 2){
+		DBG_8195A("rt5679_reg_read(): write register addr fail\n");
+		ret = 1;
+	}
+	rt5679_delay();
+	
+	buf[0] = 0xaa;
+	buf[1] = 0xaa;
+	
+	if(i2c_read(&rt5679_i2c, I2C_ALC5679_ADDR, &buf[0], 2, 1) < 2){
+		DBG_8195A("rt5679_reg_read(): read register value fail\n");
+		ret = 1;
+	}else
+		*val = ((buf[0]&0xFF)<<8)|(buf[1]&0xFF); 
+        rt5679_delay();
+	return ret;
+}
+
+u16 rt5679_reg_modify(u16 reg, u16 val, u16 iMask)
+{
+	u16 val1;
+	
+	rt5679_reg_read(reg, &val1);
+	
+	u16 val2 = (val1 &(~iMask))|val;
+	if(!rt5679_reg_write(reg, val2)) return 0;
+	return val2;
+}
+
+void rt5679_i2c_init(void)
+{
+    i2c_init(&rt5679_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
+    i2c_frequency(&rt5679_i2c, I2C_BUS_CLK);
+}
+
+int rt5679_check_id(void)
+{
+	unsigned short ret = 0;
+  	rt5679_reg_read(RT5679_VENDOR_ID2, &ret);
+        printf("Device with ID register is %x \n", ret);
+            if (ret != RT5679_DEVICE_ID) {
+                    printf("Device with ID register %x is not rt5679\n", ret);
+                    return 1;
+            }else{
+            return 0;
+        }
+}
+
+void rt5679_reg_dump(void)
+{
+	int i;
+	unsigned short value;
+  
+	printf("rt5679 codec reg dump\n\r");
+	printf("------------------------\n\r");
+	for(i=0;i<=0xff;i++){
+		rt5679_reg_read(i, &value);
+		printf("%02x : %04x\n\r", i, value);
+	}
+	printf("------------------------\n\r");
+}
+
+void rt5679_mic_to_i2s(void)
+{
+        rt5679_reg_write(0x0000,0x10EC);
+	rt5679_reg_write(0x00FA,0x0001);
+	rt5679_reg_write(0x0076,0x0777);
+	rt5679_reg_write(0x0078,0x0000);
+	rt5679_reg_write(0x004A,0x8080);
+	rt5679_reg_write(0x0050,0x8553);
+	rt5679_reg_write(0x0061,0x8000);
+	rt5679_reg_write(0x0062,0x8000);
+	rt5679_reg_write(0x00C2,0x5000);
+}
+
+void rt5679_linein_to_i2s(void)
+{
+	rt5679_reg_write(0x0000,0x10EC);
+	rt5679_reg_write(0x061D,0x04DF);
+	rt5679_reg_write(0x0007,0x1010);
+	rt5679_reg_write(0x004A,0x4040);
+	rt5679_reg_write(0x0060,0x0060);
+	rt5679_reg_write(0x0061,0x8000);
+	rt5679_reg_write(0x0062,0x8000);
+	rt5679_reg_write(0x0063,0xE340);
+	rt5679_reg_write(0x0064,0xC000);
+	rt5679_reg_write(0x0066,0x2000);
+	//rt5679_reg_write(0x0070,0x8020);//32 bit
+        rt5679_reg_write(0x0070,0x8000);//16bit
+        //rt5679_reg_write(0x0070,0x8040);//enable mono mode
+	rt5679_reg_write(0x0076,0x0777);
+	rt5679_reg_write(0x0078,0x0000);
+	rt5679_reg_write(0x00FA,0x0001);
+	rt5679_reg_write(0x0610,0xB490);
+}
+
+void rt5679_i2s_to_hp(void)
+{
+	rt5679_reg_write(0x0000,0x10EC);
+	rt5679_reg_write(0x0609,0x1122);
+	rt5679_reg_write(0x060A,0x3622);
+	rt5679_reg_write(0x060B,0x1022);
+	rt5679_reg_write(0x060C,0x3622);
+	rt5679_reg_write(0x0671,0xC0D0);
+	rt5679_reg_write(0x0603,0x0444);
+	rt5679_reg_write(0x068F,0x0007);
+	rt5679_reg_write(0x0690,0x0007);
+	rt5679_reg_write(0x0684,0x0217);
+	rt5679_reg_write(0x0122,0x0000);
+	rt5679_reg_write(0x0121,0x0000);
+	rt5679_reg_write(0x0014,0x5454);
+	rt5679_reg_write(0x0673,0xAEAA);
+	rt5679_reg_write(0x0660,0x3840);
+	///////////////////////////////
+	rt5679_reg_write(0x0661,0x3840);
+	rt5679_reg_write(0x0665,0x0101);
+	rt5679_reg_write(0x0681,0x0118);
+	rt5679_reg_write(0x0682,0x0118);
+	rt5679_reg_write(0x07F3,0x0008);
+	rt5679_reg_write(0x061D,0xE4CF);
+	rt5679_reg_write(0x00FA,0x0001);
+	rt5679_reg_write(0x0076,0x0777);
+	rt5679_reg_write(0x0078,0x0000);
+	rt5679_reg_write(0x0660,0x3840);
+	rt5679_reg_write(0x0661,0x3840);
+	rt5679_reg_write(0x0070,0x8000);//16bit 8000 32bit 8020
+	rt5679_reg_write(0x0040,0xF0AA);
+	rt5679_reg_write(0x0046,0x8080);
+	////////////////////////////////
+	rt5679_reg_write(0x0061,0x8000);
+	rt5679_reg_write(0x0062,0x0400);
+	rt5679_reg_write(0x061D,0xE4CF);
+	rt5679_reg_write(0x0063,0xA240);
+	rt5679_reg_write(0x0066,0x1680);
+	wait_ms(20); 
+	rt5679_reg_write(0x0063,0xE340);
+	rt5679_reg_write(0x0066,0x1F80);
+	rt5679_reg_write(0x0066,0xDF80);
+	rt5679_reg_write(0x0080,0x6000);
+	rt5679_reg_write(0x0063,0xE342);
+	rt5679_reg_write(0x0076,0x1777);
+	rt5679_reg_write(0x0066,0xFF80);
+	rt5679_reg_write(0x000A,0x5353);
+	rt5679_reg_write(0x0614,0xB490);
+	rt5679_reg_write(0x0060,0x0003);
+	rt5679_reg_write(0x0401,0x0630);
+	////////////////////////////////
+	rt5679_reg_write(0x0403,0x0267);
+	rt5679_reg_write(0x0404,0x9ECD);
+	rt5679_reg_write(0x0400,0x7D00);
+	rt5679_reg_write(0x0400,0xFD00);
+	wait_ms(650); 
+	rt5679_reg_write(0x0080,0x0000);
+	rt5679_reg_write(0x0063,0xE340);
+	rt5679_reg_write(0x0076,0x0777);
+	rt5679_reg_write(0x019B,0x0003);
+	rt5679_reg_write(0x0003,0x8080);
+	rt5679_reg_write(0x0066,0xDF80);
+	rt5679_reg_write(0x000A,0x5455);
+	rt5679_reg_write(0x0614,0xA490);
+	rt5679_reg_write(0x0060,0x0000);
+	rt5679_reg_write(0x0404,0x9E0C);
+}

component/common/drivers/i2s/alc5679.h

@@ -0,0 +1,13 @@
+#ifndef _ALC5679_H_
+#define _ALC5679_H_
+
+#define RT5679_DEVICE_ID			0x6385
+#define RT5679_VENDOR_ID2			0x00ff
+
+/////////////////////////////////////////////////////
+void rt5679_i2c_init(void);
+int check_id();
+void rt5679_linein_to_i2s(void);
+void rt5679_i2s_to_hp(void);
+void rt5679_mic_to_i2s(void);
+#endif

component/common/drivers/i2s/sgtl5000.c

@@ -0,0 +1,200 @@
+#include "sgtl5000.h"
+#include "PinNames.h"
+#include "basic_types.h"
+
+#include "i2c_api.h"
+#include "i2c_ex_api.h"
+#include "pinmap.h"
+#include "wait_api.h"
+
+//#define I2C_MTR_SDA			PC_4//PB_3
+//#define I2C_MTR_SCL			PC_5//PB_2
+#define I2C_MTR_SDA			PB_3
+#define I2C_MTR_SCL			PB_2
+#define I2C_BUS_CLK			100000  //100K HZ
+
+i2c_t   sgtl5000_i2c;
+
+uint16_t ana_ctrl;
+uint8_t i2c_addr;
+
+bool muted;
+
+
+
+u8 sgtl5000_reg_write(u16 reg, u16 val)
+{
+	int length = 0;
+	char buf[4];
+	buf[0] = (char)(reg >> 8);
+	buf[1] = (char)(reg&0xff);
+	buf[2] = (char)(val>>8);
+	buf[3] = (char)(val&0xff);
+
+	length = i2c_write(&sgtl5000_i2c, i2c_addr, &buf[0], 4, 1);
+	return (length==4)?0:1;
+}
+
+u8 sgtl5000_reg_read(u16 reg, u16* val)
+{
+	int tmp;
+	char *buf = (char*)&tmp;	
+	u8 ret = 0;
+	
+	buf[0] = (char)(reg >> 8);
+	buf[1] = (char)(reg&0xff);
+
+	if(i2c_write(&sgtl5000_i2c, i2c_addr, &buf[0], 2, 1) != 2){
+		DBG_8195A("sgtl5000_reg_read(): write register addr fail\n");
+		ret = 1;
+	}
+	
+	buf[0] = 0xaa;
+	buf[1] = 0xaa;
+	
+	if(i2c_read(&sgtl5000_i2c, i2c_addr, &buf[0], 2, 1) < 2){
+		DBG_8195A("sgtl5000_reg_read(): read register value fail\n");
+		ret = 1;
+	}else
+		*val = ((buf[0]&0xFF)<<8)|(buf[1]&0xFF); 
+	return ret;
+}
+
+u16 sgtl5000_reg_modify(u16 reg, u16 val, u16 iMask)
+{
+	u16 val1;
+	
+	sgtl5000_reg_read(reg, &val1);
+	
+	u16 val2 = (val1 &(~iMask))|val;
+	if(!sgtl5000_reg_write(reg, val2)) return 0;
+	return val2;
+}
+
+void sgtl5000_setAddress(uint8_t level)
+{
+	if (level == 0) {
+		i2c_addr = SGTL5000_I2C_ADDR_CS_LOW;
+	} else {
+		i2c_addr = SGTL5000_I2C_ADDR_CS_HIGH;
+	}
+}
+
+
+void sgtl5000_i2c_master_txc_callback(void *userdata)
+{
+
+}
+
+void sgtl5000_i2c_master_rxc_callback(void *userdata)
+{
+
+}
+
+void sgtl5000_i2c_master_err_callback(void *userdata)
+{	
+    //DBG_8195A("I2C Ack address:%d", (sgtl5000_i2c.I2Cx->IC_TAR)& BIT_CTRL_IC_TAR);//sgtl5000_i2c.SalI2CHndPriv.SalI2CHndPriv.I2CAckAddr);
+    //DBG_8195A("I2C Error:%x\n", sgtl5000_i2c.I2Cx->IC_TX_ABRT_SOURCE);//sgtl5000_i2c.SalI2CHndPriv.SalI2CHndPriv.ErrType);
+}
+
+void sgtl5000_reg_dump(void);
+
+u8 sgtl5000_enable(void){
+	u16 temp = 0;
+	u8 ret = 0;
+	muted = 1;
+	memset(&sgtl5000_i2c, 0x00, sizeof(sgtl5000_i2c));
+	i2c_init(&sgtl5000_i2c, I2C_MTR_SDA, I2C_MTR_SCL);
+	i2c_frequency(&sgtl5000_i2c, I2C_BUS_CLK);
+    i2c_set_user_callback(&sgtl5000_i2c, I2C_ERR_OCCURRED, sgtl5000_i2c_master_err_callback);
+
+	// set I2C address
+	sgtl5000_setAddress(0);  // CTRL_ADR0_CS is tied to GND
+	wait_ms(5);
+	
+	ret = sgtl5000_reg_read(CHIP_ID, &temp);
+	if(ret == 0)
+		DBG_8195A("SGTL5000 CHIP ID:0x%04X\n", temp);
+	else
+		DBG_8195A("Get SGTL5000 CHIP ID fail\n");
+
+	sgtl5000_reg_write(CHIP_ANA_POWER, 0x4060);	// VDDD is externally driven with 1.8V
+	sgtl5000_reg_write(CHIP_LINREG_CTRL, 0x006C);  // VDDA & VDDIO both over 3.1V
+	sgtl5000_reg_write(CHIP_REF_CTRL, 0x01F2); // VAG=1.575, normal ramp, +12.5% bias current
+	sgtl5000_reg_write(CHIP_LINE_OUT_CTRL, 0x0F22); // LO_VAGCNTRL=1.65V, OUT_CURRENT=0.54mA
+	sgtl5000_reg_write(CHIP_SHORT_CTRL, 0x4446);  // allow up to 125mA
+	sgtl5000_reg_write(CHIP_ANA_CTRL, 0x0137);  // enable zero cross detectors
+	sgtl5000_reg_write(CHIP_ANA_POWER, 0x40FF); // power up: lineout, hp, adc, dac
+	sgtl5000_reg_write(CHIP_DIG_POWER, 0x0073); // power up all digital stuff
+	wait_ms(400);
+	sgtl5000_reg_write(CHIP_LINE_OUT_VOL, 0x1D1D); // default approx 1.3 volts peak-to-peak
+	sgtl5000_reg_write(CHIP_CLK_CTRL, 0x0004);  // 44.1 kHz, 256*Fs
+	sgtl5000_reg_write(CHIP_I2S_CTRL, 0x0130); // SCLK=32*Fs, 16bit, I2S format
+	// default signal routing is ok?
+	sgtl5000_reg_write(CHIP_SSS_CTRL, 0x0010); // ADC->I2S, I2S->DAC
+	sgtl5000_reg_write(CHIP_ADCDAC_CTRL, 0x0000); // disable dac mute
+	sgtl5000_reg_write(CHIP_DAC_VOL, 0x3C3C); // digital gain, 0dB
+	sgtl5000_reg_write(CHIP_ANA_HP_CTRL, 0x7F7F); // set volume (lowest level)
+	sgtl5000_reg_write(CHIP_ANA_CTRL, 0x0036);  // enable zero cross detectors
+	//semi_automated = true;
+	
+	//sgtl5000_reg_dump();
+
+    return 0;
+}
+
+bool sgtl5000_muteHeadphone(void) { 
+	return sgtl5000_reg_write(CHIP_ANA_CTRL, ana_ctrl | (1<<4)); 
+}
+bool sgtl5000_unmuteHeadphone(void) { 
+	return sgtl5000_reg_write(CHIP_ANA_CTRL, ana_ctrl & ~(1<<4)); 
+}
+bool sgtl5000_muteLineout(void) { 
+	return sgtl5000_reg_write(CHIP_ANA_CTRL, ana_ctrl | (1<<8)); 
+}
+bool sgtl5000_unmuteLineout(void) { 
+	return sgtl5000_reg_write(CHIP_ANA_CTRL, ana_ctrl & ~(1<<8)); 
+}
+
+u8 sgtl5000_setVolume(float val){
+	int volumeInt = 0; 
+
+	volumeInt = (int)(val * 129 + 0.499);
+
+	if (volumeInt == 0) {
+		muted = 1;
+		sgtl5000_reg_write(CHIP_ANA_HP_CTRL, 0x7F7F);
+		return sgtl5000_muteHeadphone();
+	} else if (volumeInt > 0x80) {
+		volumeInt = 0;
+	} else {
+		volumeInt = 0x80 - volumeInt;
+	}
+	if (muted) {
+		muted = 0;
+		sgtl5000_unmuteHeadphone();
+	}
+	volumeInt = volumeInt | (volumeInt << 8);
+
+	return sgtl5000_reg_write(CHIP_ANA_HP_CTRL, volumeInt);	// set volume
+}
+
+
+void sgtl5000_reg_dump(void)
+{
+	u16 reg;
+	u8 ret = 0;
+	u16 value;
+  
+	DBG_8195A("SGTL5000 codec reg dump\n\r");
+	DBG_8195A("------------------------\n\r");
+	for(reg = 0; reg <= 0x013A; ){
+		ret = sgtl5000_reg_read(reg, &value);
+		if(ret == 0)
+			DBG_8195A("0x%04X : 0x%04X\n\r", reg, value);
+        reg += 0x02;
+	}
+	DBG_8195A("------------------------\n\r");
+}
+
+

component/common/drivers/i2s/sgtl5000.h

@@ -0,0 +1,479 @@
+#ifndef _SGTL5000_H_
+#define _SGTL5000_H_
+
+#define CHIP_ID				0x0000
+// 15:8 PARTID		0xA0 - 8 bit identifier for SGTL5000
+// 7:0  REVID		0x00 - revision number for SGTL5000.
+
+#define CHIP_DIG_POWER			0x0002
+// 6	ADC_POWERUP	1=Enable, 0=disable the ADC block, both digital & analog, 
+// 5	DAC_POWERUP	1=Enable, 0=disable the DAC block, both analog and digital
+// 4	DAP_POWERUP	1=Enable, 0=disable the DAP block
+// 1	I2S_OUT_POWERUP	1=Enable, 0=disable the I2S data output
+// 0	I2S_IN_POWERUP	1=Enable, 0=disable the I2S data input
+
+#define CHIP_CLK_CTRL			0x0004
+// 5:4	RATE_MODE	Sets the sample rate mode. MCLK_FREQ is still specified
+//			relative to the rate in SYS_FS
+//				0x0 = SYS_FS specifies the rate
+//				0x1 = Rate is 1/2 of the SYS_FS rate
+//				0x2 = Rate is 1/4 of the SYS_FS rate
+//				0x3 = Rate is 1/6 of the SYS_FS rate
+// 3:2	SYS_FS		Sets the internal system sample rate (default=2)
+//				0x0 = 32 kHz
+//				0x1 = 44.1 kHz
+//				0x2 = 48 kHz
+//				0x3 = 96 kHz
+// 1:0	MCLK_FREQ	Identifies incoming SYS_MCLK frequency and if the PLL should be used
+//				0x0 = 256*Fs
+//				0x1 = 384*Fs
+//				0x2 = 512*Fs
+//				0x3 = Use PLL
+//				The 0x3 (Use PLL) setting must be used if the SYS_MCLK is not
+//				a standard multiple of Fs (256, 384, or 512). This setting can
+//				also be used if SYS_MCLK is a standard multiple of Fs.
+//				Before this field is set to 0x3 (Use PLL), the PLL must be
+//				powered up by setting CHIP_ANA_POWER->PLL_POWERUP and
+//				CHIP_ANA_POWER->VCOAMP_POWERUP.  Also, the PLL dividers must
+//				be calculated based on the external MCLK rate and
+//				CHIP_PLL_CTRL register must be set (see CHIP_PLL_CTRL register
+//				description details on how to calculate the divisors).
+
+#define CHIP_I2S_CTRL			0x0006
+// 8	SCLKFREQ	Sets frequency of I2S_SCLK when in master mode (MS=1). When in slave
+//			mode (MS=0), this field must be set appropriately to match SCLK input
+//			rate.
+//				0x0 = 64Fs
+//				0x1 = 32Fs - Not supported for RJ mode (I2S_MODE = 1)
+// 7	MS		Configures master or slave of I2S_LRCLK and I2S_SCLK.
+//				0x0 = Slave: I2S_LRCLK an I2S_SCLK are inputs
+//				0x1 = Master: I2S_LRCLK and I2S_SCLK are outputs
+//				NOTE: If the PLL is used (CHIP_CLK_CTRL->MCLK_FREQ==0x3),
+//				the SGTL5000 must be a master of the I2S port (MS==1)
+// 6	SCLK_INV	Sets the edge that data (input and output) is clocked in on for I2S_SCLK
+//				0x0 = data is valid on rising edge of I2S_SCLK
+//				0x1 = data is valid on falling edge of I2S_SCLK
+// 5:4	DLEN		I2S data length (default=1)
+//				0x0 = 32 bits (only valid when SCLKFREQ=0),
+//					not valid for Right Justified Mode
+//				0x1 = 24 bits (only valid when SCLKFREQ=0)
+//				0x2 = 20 bits
+//				0x3 = 16 bits
+// 3:2	I2S_MODE	Sets the mode for the I2S port
+//				0x0 = I2S mode or Left Justified (Use LRALIGN to select)
+//				0x1 = Right Justified Mode
+//				0x2 = PCM Format A/B
+//				0x3 = RESERVED
+// 1	LRALIGN		I2S_LRCLK Alignment to data word. Not used for Right Justified mode
+//				0x0 = Data word starts 1 I2S_SCLK delay after I2S_LRCLK
+//					transition (I2S format, PCM format A)
+//				0x1 = Data word starts after I2S_LRCLK transition (left
+//					justified format, PCM format B)
+// 0	LRPOL		I2S_LRCLK Polarity when data is presented.
+//				0x0 = I2S_LRCLK = 0 - Left, 1 - Right
+//				1x0 = I2S_LRCLK = 0 - Right, 1 - Left
+//				The left subframe should be presented first regardless of
+//				the setting of LRPOL.
+
+#define CHIP_SSS_CTRL			0x000A
+// 14	DAP_MIX_LRSWAP	DAP Mixer Input Swap
+//				0x0 = Normal Operation
+//				0x1 = Left and Right channels for the DAP MIXER Input are swapped.
+// 13	DAP_LRSWAP	DAP Mixer Input Swap
+//				0x0 = Normal Operation
+//				0x1 = Left and Right channels for the DAP Input are swapped
+// 12	DAC_LRSWAP	DAC Input Swap
+//				0x0 = Normal Operation
+//				0x1 = Left and Right channels for the DAC are swapped
+// 10	I2S_LRSWAP	I2S_DOUT Swap
+//				0x0 = Normal Operation
+//				0x1 = Left and Right channels for the I2S_DOUT are swapped
+// 9:8	DAP_MIX_SELECT	Select data source for DAP mixer
+//				0x0 = ADC
+//				0x1 = I2S_IN
+//				0x2 = Reserved
+//				0x3 = Reserved
+// 7:6	DAP_SELECT	Select data source for DAP
+//				0x0 = ADC
+//				0x1 = I2S_IN
+//				0x2 = Reserved
+//				0x3 = Reserved
+// 5:4	DAC_SELECT	Select data source for DAC (default=1)
+//				0x0 = ADC
+//				0x1 = I2S_IN
+//				0x2 = Reserved
+//				0x3 = DAP
+// 1:0	I2S_SELECT	Select data source for I2S_DOUT
+//				0x0 = ADC
+//				0x1 = I2S_IN
+//				0x2 = Reserved
+//				0x3 = DAP
+
+#define CHIP_ADCDAC_CTRL		0x000E
+// 13	VOL_BUSY_DAC_RIGHT Volume Busy DAC Right
+//				0x0 = Ready
+//				0x1 = Busy - This indicates the channel has not reached its
+//					programmed volume/mute level
+// 12	VOL_BUSY_DAC_LEFT  Volume Busy DAC Left
+//				0x0 = Ready
+//				0x1 = Busy - This indicates the channel has not reached its
+//					programmed volume/mute level
+// 9	VOL_RAMP_EN	Volume Ramp Enable (default=1)
+//				0x0 = Disables volume ramp. New volume settings take immediate
+//					effect without a ramp
+//				0x1 = Enables volume ramp
+//				This field affects DAC_VOL. The volume ramp effects both
+//				volume settings and mute When set to 1 a soft mute is enabled.
+// 8	VOL_EXPO_RAMP	Exponential Volume Ramp Enable
+//				0x0 = Linear ramp over top 4 volume octaves
+//				0x1 = Exponential ramp over full volume range
+//				This bit only takes effect if VOL_RAMP_EN is 1.
+// 3	DAC_MUTE_RIGHT	DAC Right Mute (default=1)
+//				0x0 = Unmute
+//				0x1 = Muted
+//				If VOL_RAMP_EN = 1, this is a soft mute.
+// 2	DAC_MUTE_LEFT	DAC Left Mute (default=1)
+//				0x0 = Unmute
+//				0x1 = Muted
+//				If VOL_RAMP_EN = 1, this is a soft mute.
+// 1	ADC_HPF_FREEZE	ADC High Pass Filter Freeze
+//				0x0 = Normal operation
+//				0x1 = Freeze the ADC high-pass filter offset register.  The
+//				offset continues to be subtracted from the ADC data stream.
+// 0	ADC_HPF_BYPASS	ADC High Pass Filter Bypass
+//				0x0 = Normal operation
+//				0x1 = Bypassed and offset not updated
+
+#define CHIP_DAC_VOL			0x0010
+// 15:8	DAC_VOL_RIGHT	DAC Right Channel Volume.  Set the Right channel DAC volume
+//			with 0.5017 dB steps from 0 to -90 dB
+//				0x3B and less = Reserved
+//				0x3C = 0 dB
+//				0x3D = -0.5 dB
+//				0xF0 = -90 dB
+//				0xFC and greater = Muted
+//				If VOL_RAMP_EN = 1, there is an automatic ramp to the
+//				new volume setting.
+// 7:0	DAC_VOL_LEFT	DAC Left Channel Volume.  Set the Left channel DAC volume
+//			with 0.5017 dB steps from 0 to -90 dB
+//				0x3B and less = Reserved
+//				0x3C = 0 dB
+//				0x3D = -0.5 dB
+//				0xF0 = -90 dB
+//				0xFC and greater = Muted
+//				If VOL_RAMP_EN = 1, there is an automatic ramp to the
+//				new volume setting.
+
+#define CHIP_PAD_STRENGTH		0x0014
+// 9:8	I2S_LRCLK	I2S LRCLK Pad Drive Strength (default=1)
+//				Sets drive strength for output pads per the table below.
+//				 VDDIO    1.8 V     2.5 V     3.3 V
+//				0x0 = Disable
+//				0x1 =     1.66 mA   2.87 mA   4.02 mA
+//				0x2 =     3.33 mA   5.74 mA   8.03 mA
+//				0x3 =     4.99 mA   8.61 mA   12.05 mA
+// 7:6	I2S_SCLK	I2S SCLK Pad Drive Strength (default=1)
+// 5:4	I2S_DOUT	I2S DOUT Pad Drive Strength (default=1)
+// 3:2	CTRL_DATA	I2C DATA Pad Drive Strength (default=3)
+// 1:0	CTRL_CLK	I2C CLK Pad Drive Strength (default=3)
+//				(all use same table as I2S_LRCLK)
+
+#define CHIP_ANA_ADC_CTRL		0x0020
+// 8	ADC_VOL_M6DB	ADC Volume Range Reduction
+//				This bit shifts both right and left analog ADC volume
+//				range down by 6.0 dB.
+//				0x0 = No change in ADC range
+//				0x1 = ADC range reduced by 6.0 dB
+// 7:4	ADC_VOL_RIGHT	ADC Right Channel Volume
+//				Right channel analog ADC volume control in 1.5 dB steps.
+//				0x0 = 0 dB
+//				0x1 = +1.5 dB
+//				...
+//				0xF = +22.5 dB
+//				This range is -6.0 dB to +16.5 dB if ADC_VOL_M6DB is set to 1.
+// 3:0	ADC_VOL_LEFT	ADC Left Channel Volume
+//				(same scale as ADC_VOL_RIGHT)
+
+#define CHIP_ANA_HP_CTRL		0x0022
+// 14:8	HP_VOL_RIGHT	Headphone Right Channel Volume  (default 0x18)
+//				Right channel headphone volume control with 0.5 dB steps.
+//				0x00 = +12 dB
+//				0x01 = +11.5 dB
+//				0x18 = 0 dB
+//				...
+//				0x7F = -51.5 dB
+// 6:0	HP_VOL_LEFT	Headphone Left Channel Volume  (default 0x18)
+//				(same scale as HP_VOL_RIGHT)
+
+#define CHIP_ANA_CTRL			0x0024
+// 8	MUTE_LO		LINEOUT Mute, 0 = Unmute, 1 = Mute  (default 1)
+// 6	SELECT_HP	Select the headphone input, 0 = DAC, 1 = LINEIN
+// 5	EN_ZCD_HP	Enable the headphone zero cross detector (ZCD)
+//				0x0 = HP ZCD disabled
+//				0x1 = HP ZCD enabled
+// 4	MUTE_HP		Mute the headphone outputs, 0 = Unmute, 1 = Mute (default)
+// 2	SELECT_ADC	Select the ADC input, 0 = Microphone, 1 = LINEIN
+// 1	EN_ZCD_ADC	Enable the ADC analog zero cross detector (ZCD)
+//				0x0 = ADC ZCD disabled
+//				0x1 = ADC ZCD enabled
+// 0	MUTE_ADC	Mute the ADC analog volume, 0 = Unmute, 1 = Mute (default)
+
+#define CHIP_LINREG_CTRL		0x0026
+// 6	VDDC_MAN_ASSN	Determines chargepump source when VDDC_ASSN_OVRD is set.
+//				0x0 = VDDA
+//				0x1 = VDDIO
+// 5	VDDC_ASSN_OVRD	Charge pump Source Assignment Override
+//				0x0 = Charge pump source is automatically assigned based
+//					on higher of VDDA and VDDIO
+//				0x1 = the source of charge pump is manually assigned by
+//					VDDC_MAN_ASSN If VDDIO and VDDA are both the same
+//					and greater than 3.1 V, VDDC_ASSN_OVRD and
+//					VDDC_MAN_ASSN should be used to manually assign
+//					VDDIO as the source for charge pump.
+// 3:0	D_PROGRAMMING	Sets the VDDD linear regulator output voltage in 50 mV steps.
+//			Must clear the LINREG_SIMPLE_POWERUP and STARTUP_POWERUP bits
+//			in the 0x0030 (CHIP_ANA_POWER) register after power-up, for
+//			this setting to produce the proper VDDD voltage.
+//				0x0 = 1.60
+//				0xF = 0.85
+
+#define CHIP_REF_CTRL			0x0028 // bandgap reference bias voltage and currents
+// 8:4	VAG_VAL		Analog Ground Voltage Control
+//				These bits control the analog ground voltage in 25 mV steps.
+//				This should usually be set to VDDA/2 or lower for best
+//				performance (maximum output swing at minimum THD). This VAG
+//				reference is also used for the DAC and ADC voltage reference.
+//				So changing this voltage scales the output swing of the DAC
+//				and the output signal of the ADC.
+//				0x00 = 0.800 V
+//				0x1F = 1.575 V
+// 3:1	BIAS_CTRL	Bias control
+//				These bits adjust the bias currents for all of the analog
+//				blocks. By lowering the bias current a lower quiescent power
+//				is achieved. It should be noted that this mode can affect
+//				performance by 3-4 dB.
+//				0x0 = Nominal
+//				0x1-0x3=+12.5%
+//				0x4=-12.5%
+//				0x5=-25%
+//				0x6=-37.5%
+//				0x7=-50%
+// 0	SMALL_POP	VAG Ramp Control
+//				Setting this bit slows down the VAG ramp from ~200 to ~400 ms
+//				to reduce the startup pop, but increases the turn on/off time.
+//				0x0 = Normal VAG ramp
+//				0x1 = Slow down VAG ramp
+
+#define CHIP_MIC_CTRL			0x002A // microphone gain & internal microphone bias
+// 9:8	BIAS_RESISTOR	MIC Bias Output Impedance Adjustment
+//				Controls an adjustable output impedance for the microphone bias.
+//				If this is set to zero the micbias block is powered off and
+//				the output is highZ.
+//				0x0 = Powered off
+//				0x1 = 2.0 kohm
+//				0x2 = 4.0 kohm
+//				0x3 = 8.0 kohm
+// 6:4	BIAS_VOLT	MIC Bias Voltage Adjustment
+//				Controls an adjustable bias voltage for the microphone bias
+//				amp in 250 mV steps. This bias voltage setting should be no
+//				more than VDDA-200 mV for adequate power supply rejection.
+//				0x0 = 1.25 V
+//				...
+//				0x7 = 3.00 V
+// 1:0	GAIN		MIC Amplifier Gain
+//				Sets the microphone amplifier gain. At 0 dB setting the THD
+//				can be slightly higher than other paths- typically around
+//				~65 dB. At other gain settings the THD are better.
+//				0x0 = 0 dB
+//				0x1 = +20 dB
+//				0x2 = +30 dB
+//				0x3 = +40 dB
+
+#define CHIP_LINE_OUT_CTRL		0x002C
+// 11:8	OUT_CURRENT	Controls the output bias current for the LINEOUT amplifiers.  The
+//			nominal recommended setting for a 10 kohm load with 1.0 nF load cap
+//			is 0x3. There are only 5 valid settings.
+//				0x0=0.18 mA
+//				0x1=0.27 mA
+//				0x3=0.36 mA
+//				0x7=0.45 mA
+//				0xF=0.54 mA
+// 5:0	LO_VAGCNTRL	LINEOUT Amplifier Analog Ground Voltage
+//				Controls the analog ground voltage for the LINEOUT amplifiers
+//				in 25 mV steps. This should usually be set to VDDIO/2.
+//				0x00 = 0.800 V
+//				...
+//				0x1F = 1.575 V
+//				...
+//				0x23 = 1.675 V
+//				0x24-0x3F are invalid
+
+#define CHIP_LINE_OUT_VOL		0x002E
+// 12:8	LO_VOL_RIGHT	LINEOUT Right Channel Volume (default=4)
+//				Controls the right channel LINEOUT volume in 0.5 dB steps.
+//				Higher codes have more attenuation.
+// 4:0	LO_VOL_LEFT	LINEOUT Left Channel Output Level (default=4)
+//				Used to normalize the output level of the left line output
+//				to full scale based on the values used to set
+//				LINE_OUT_CTRL->LO_VAGCNTRL and CHIP_REF_CTRL->VAG_VAL.
+//				In general this field should be set to:
+//				40*log((VAG_VAL)/(LO_VAGCNTRL)) + 15
+//				Suggested values based on typical VDDIO and VDDA voltages.
+//					VDDA  VAG_VAL VDDIO  LO_VAGCNTRL LO_VOL_*
+//					1.8 V    0.9   3.3 V     1.55      0x06
+//					1.8 V    0.9   1.8 V      0.9      0x0F
+//					3.3 V   1.55   1.8 V      0.9      0x19
+//					3.3 V   1.55   3.3 V     1.55      0x0F
+//				After setting to the nominal voltage, this field can be used
+//				to adjust the output level in +/-0.5 dB increments by using
+//				values higher or lower than the nominal setting.
+
+#define CHIP_ANA_POWER			0x0030 // power down controls for the analog blocks.
+		// The only other power-down controls are BIAS_RESISTOR in the MIC_CTRL register
+		//  and the EN_ZCD control bits in ANA_CTRL.
+// 14	DAC_MONO	While DAC_POWERUP is set, this allows the DAC to be put into left only
+//				mono operation for power savings. 0=mono, 1=stereo (default)
+// 13	LINREG_SIMPLE_POWERUP  Power up the simple (low power) digital supply regulator.
+//				After reset, this bit can be cleared IF VDDD is driven
+//				externally OR the primary digital linreg is enabled with
+//				LINREG_D_POWERUP
+// 12	STARTUP_POWERUP	Power up the circuitry needed during the power up ramp and reset.
+//				After reset this bit can be cleared if VDDD is coming from
+//				an external source.
+// 11	VDDC_CHRGPMP_POWERUP Power up the VDDC charge pump block. If neither VDDA or VDDIO
+//				is 3.0 V or larger this bit should be cleared before analog
+//				blocks are powered up.
+// 10	PLL_POWERUP	PLL Power Up, 0 = Power down, 1 = Power up
+//				When cleared, the PLL is turned off. This must be set before
+//				CHIP_CLK_CTRL->MCLK_FREQ is programmed to 0x3. The
+//				CHIP_PLL_CTRL register must be configured correctly before
+//				setting this bit.
+// 9	LINREG_D_POWERUP Power up the primary VDDD linear regulator, 0 = Power down, 1 = Power up
+// 8	VCOAMP_POWERUP	Power up the PLL VCO amplifier, 0 = Power down, 1 = Power up
+// 7	VAG_POWERUP	Power up the VAG reference buffer.
+//				Setting this bit starts the power up ramp for the headphone
+//				and LINEOUT. The headphone (and/or LINEOUT) powerup should
+//				be set BEFORE clearing this bit. When this bit is cleared
+//				the power-down ramp is started. The headphone (and/or LINEOUT)
+//				powerup should stay set until the VAG is fully ramped down
+//				(200 to 400 ms after clearing this bit).
+//				0x0 = Power down, 0x1 = Power up
+// 6	ADC_MONO	While ADC_POWERUP is set, this allows the ADC to be put into left only
+//				mono operation for power savings. This mode is useful when
+//				only using the microphone input.
+//				0x0 = Mono (left only), 0x1 = Stereo
+// 5	REFTOP_POWERUP	Power up the reference bias currents
+//				0x0 = Power down, 0x1 = Power up
+//				This bit can be cleared when the part is a sleep state
+//				to minimize analog power.
+// 4	HEADPHONE_POWERUP Power up the headphone amplifiers
+//				0x0 = Power down, 0x1 = Power up
+// 3	DAC_POWERUP	Power up the DACs
+//				0x0 = Power down, 0x1 = Power up
+// 2	CAPLESS_HEADPHONE_POWERUP Power up the capless headphone mode
+//				0x0 = Power down, 0x1 = Power up
+// 1	ADC_POWERUP	Power up the ADCs
+//				0x0 = Power down, 0x1 = Power up
+// 0	LINEOUT_POWERUP	Power up the LINEOUT amplifiers
+//				0x0 = Power down, 0x1 = Power up
+
+#define CHIP_PLL_CTRL			0x0032
+// 15:11 INT_DIVISOR
+// 10:0 FRAC_DIVISOR
+
+#define CHIP_CLK_TOP_CTRL		0x0034
+// 11	ENABLE_INT_OSC	Setting this bit enables an internal oscillator to be used for the
+//				zero cross detectors, the short detect recovery, and the
+//				charge pump. This allows the I2S clock to be shut off while
+//				still operating an analog signal path. This bit can be kept
+//				on when the I2S clock is enabled, but the I2S clock is more
+//				accurate so it is preferred to clear this bit when I2S is present.
+// 3	INPUT_FREQ_DIV2	SYS_MCLK divider before PLL input
+//				0x0 = pass through
+//				0x1 = SYS_MCLK is divided by 2 before entering PLL
+//				This must be set when the input clock is above 17 Mhz. This
+//				has no effect when the PLL is powered down.
+
+#define CHIP_ANA_STATUS			0x0036
+// 9	LRSHORT_STS	This bit is high whenever a short is detected on the left or right
+//				channel headphone drivers.
+// 8	CSHORT_STS	This bit is high whenever a short is detected on the capless headphone
+//				common/center channel driver.
+// 4	PLL_IS_LOCKED	This bit goes high after the PLL is locked.
+
+#define CHIP_ANA_TEST1			0x0038 //  intended only for debug.
+#define CHIP_ANA_TEST2			0x003A //  intended only for debug.
+
+#define CHIP_SHORT_CTRL			0x003C
+// 14:12 LVLADJR	Right channel headphone	short detector in 25 mA steps.
+//				0x3=25 mA
+//				0x2=50 mA
+//				0x1=75 mA
+//				0x0=100 mA
+//				0x4=125 mA
+//				0x5=150 mA
+//				0x6=175 mA
+//				0x7=200 mA
+//				This trip point can vary by ~30% over process so leave plenty
+//				of guard band to avoid false trips.  This short detect trip
+//				point is also effected by the bias current adjustments made
+//				by CHIP_REF_CTRL->BIAS_CTRL and by CHIP_ANA_TEST1->HP_IALL_ADJ.
+// 10:8	LVLADJL		Left channel headphone short detector in 25 mA steps.
+//				(same scale as LVLADJR)
+// 6:4	LVLADJC		Capless headphone center channel short detector in 50 mA steps.
+//				0x3=50 mA
+//				0x2=100 mA
+//				0x1=150 mA
+//				0x0=200 mA
+//				0x4=250 mA
+//				0x5=300 mA
+//				0x6=350 mA
+//				0x7=400 mA
+// 3:2	MODE_LR		Behavior of left/right short detection
+//				0x0 = Disable short detector, reset short detect latch,
+//					software view non-latched short signal
+//				0x1 = Enable short detector and reset the latch at timeout
+//					(every ~50 ms)
+//				0x2 = This mode is not used/invalid
+//				0x3 = Enable short detector with only manual reset (have
+//					to return to 0x0 to reset the latch)
+// 1:0	MODE_CM		Behavior of capless headphone central short detection
+//				(same settings as MODE_LR)
+
+#define DAP_CONTROL			0x0100
+#define DAP_PEQ				0x0102
+#define DAP_BASS_ENHANCE		0x0104
+#define DAP_BASS_ENHANCE_CTRL		0x0106
+#define DAP_AUDIO_EQ			0x0108
+#define DAP_SGTL_SURROUND		0x010A
+#define DAP_FILTER_COEF_ACCESS		0x010C
+#define DAP_COEF_WR_B0_MSB		0x010E
+#define DAP_COEF_WR_B0_LSB		0x0110
+#define DAP_AUDIO_EQ_BASS_BAND0		0x0116 // 115 Hz
+#define DAP_AUDIO_EQ_BAND1		0x0118 // 330 Hz
+#define DAP_AUDIO_EQ_BAND2		0x011A // 990 Hz
+#define DAP_AUDIO_EQ_BAND3		0x011C // 3000 Hz
+#define DAP_AUDIO_EQ_TREBLE_BAND4	0x011E // 9900 Hz
+#define DAP_MAIN_CHAN			0x0120
+#define DAP_MIX_CHAN			0x0122
+#define DAP_AVC_CTRL			0x0124
+#define DAP_AVC_THRESHOLD		0x0126
+#define DAP_AVC_ATTACK			0x0128
+#define DAP_AVC_DECAY			0x012A
+#define DAP_COEF_WR_B1_MSB		0x012C
+#define DAP_COEF_WR_B1_LSB		0x012E
+#define DAP_COEF_WR_B2_MSB		0x0130
+#define DAP_COEF_WR_B2_LSB		0x0132
+#define DAP_COEF_WR_A1_MSB		0x0134
+#define DAP_COEF_WR_A1_LSB		0x0136
+#define DAP_COEF_WR_A2_MSB		0x0138
+#define DAP_COEF_WR_A2_LSB		0x013A
+
+#define SGTL5000_I2C_ADDR_CS_LOW	0x0A  // CTRL_ADR0_CS pin low (normal configuration)
+#define SGTL5000_I2C_ADDR_CS_HIGH	0x2A // CTRL_ADR0_CS  pin high
+
+unsigned char sgtl5000_enable(void);
+unsigned char sgtl5000_setVolume(float val);
+
+
+#endif

component/common/drivers/wlan/realtek/include/autoconf.h

@@ -0,0 +1,508 @@
+#ifndef WLANCONFIG_H
+#define WLANCONFIG_H
+
+/*
+ * Include user defined options first. Anything not defined in these files
+ * will be set to standard values. Override anything you dont like!
+ */
+ #if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) || defined(CONFIG_HARDWARE_8188F)
+#include "platform_opts.h"
+#endif
+
+#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
+#define CONFIG_PLATFORM_AMEBA_X
+#endif
+
+#if !defined(CONFIG_PLATFORM_AMEBA_X)
+#define PLATFORM_FREERTOS 	1
+#define CONFIG_GSPI_HCI
+#else
+#define CONFIG_LX_HCI
+#endif
+
+#ifndef CONFIG_INIC_EN
+#define CONFIG_INIC_EN 0 //For iNIC project
+#endif
+
+#if CONFIG_INIC_EN
+#define CONFIG_LWIP_LAYER    0
+#endif
+
+#define CONFIG_LITTLE_ENDIAN
+#define CONFIG_80211N_HT 
+//#define CONFIG_RECV_REORDERING_CTRL
+#define RTW_NOTCH_FILTER 0
+#define CONFIG_EMBEDDED_FWIMG
+#define CONFIG_PHY_SETTING_WITH_ODM
+#if !defined(CONFIG_PLATFORM_AMEBA_X)
+#define CONFIG_ODM_REFRESH_RAMASK
+#define HAL_MAC_ENABLE 1
+#define HAL_BB_ENABLE 1
+#define HAL_RF_ENABLE 1
+#endif
+#if defined(CONFIG_PLATFORM_AMEBA_X)
+/* Patch when dynamic mechanism is not ready */
+//#define CONFIG_DM_PATCH
+#endif
+
+//#define CONFIG_DEBUG
+//#define CONFIG_DEBUG_RTL871X
+#if defined(CONFIG_PLATFORM_AMEBA_X)
+	#define CONFIG_MEM_MONITOR	MEM_MONITOR_SIMPLE
+	#define WLAN_INTF_DBG		0 
+	//#define CONFIG_DEBUG_DYNAMIC
+	//#define DBG_TX 1
+	//#define DBG_XMIT_BUF 1
+	//#define DBG_XMIT_BUF_EXT 1
+	#define DBG_TX_DROP_FRAME
+#else
+	#define CONFIG_MEM_MONITOR	MEM_MONITOR_LEAK
+	//#define CONFIG_TRACE_SKB
+	//#define WLAN_INTF_DBG
+#endif // CONFIG_PLATFORM_AMEBA_X
+
+//#define CONFIG_DONT_CARE_TP
+//#define CONFIG_HIGH_TP
+//#define CONFIG_MEMORY_ACCESS_ALIGNED
+#define CONFIG_POWER_SAVING
+#ifdef CONFIG_POWER_SAVING
+	#define CONFIG_IPS
+	#define CONFIG_LPS
+	//#define CONFIG_LPS_LCLK
+	#define CONFIG_LPS_32K
+	#define TDMA_POWER_SAVING
+	#define CONFIG_WAIT_PS_ACK
+#endif
+
+#define BAD_MIC_COUNTERMEASURE 1
+#define DEFRAGMENTATION 1
+
+#define WIFI_LOGO_CERTIFICATION 0
+#if WIFI_LOGO_CERTIFICATION
+    #define RX_AGGREGATION 1
+	#define RX_AMSDU 1
+#else
+    #define RX_AGGREGATION 0
+	#define RX_AMSDU 0
+#endif
+
+#if defined(CONFIG_PLATFORM_AMEBA_X)
+	#if !defined(CONFIG_PLATFORM_8711B)
+		#define CONFIG_USE_TCM_HEAP 1					/* USE TCM HEAP */
+	#endif
+	#define CONFIG_RECV_TASKLET_THREAD
+	#define CONFIG_XMIT_TASKLET_THREAD
+#else
+	#define CONFIG_XMIT_THREAD_MODE
+#endif // CONFIG_PLATFORM_AMEBA_X
+//#define CONFIG_RECV_THREAD_MODE				/* Wlan IRQ Polling  Mode*/
+//#define CONFIG_ISR_THREAD_MODE_POLLING		/* Wlan IRQ Polling  Mode*/
+
+//1 Chris
+#ifndef CONFIG_SDIO_HCI
+#define CONFIG_ISR_THREAD_MODE_INTERRUPT	/* Wlan IRQ Interrupt  Mode*/
+#endif
+
+#if defined(CONFIG_ISR_THREAD_MODE_POLLING) && defined(CONFIG_ISR_THREAD_MODE_INTERRUPT)
+#error "CONFIG_ISR_THREAD_MODE_POLLING and CONFIG_ISR_THREAD_MODE_INTERRUPT are mutually exclusive. "
+#endif
+
+#if defined(CONFIG_PLATFORM_AMEBA_X)
+/* CRC DMEM optimized mode consume 1k less SRM memory consumption */
+#define CRC_IMPLEMENTATION_MODE CRC_IMPLEMENTATION_DMEM_OPTIMIZED
+#endif
+
+/* AES DMEM optimized mode comsume 10k less memory compare to 
+     IMEM optimized mode AES_IMPLEMENTATION_IMEM_OPTIMIZED */
+#define AES_IMPLEMENTATION_MODE AES_IMPLEMENTATION_DMEM_OPTIMIZED
+
+#define USE_SKB_AS_XMITBUF	1
+#if defined(CONFIG_PLATFORM_AMEBA_X)
+#define USE_XMIT_EXTBUFF	1
+#else
+#define USE_XMIT_EXTBUFF	0
+#endif
+#define USE_MUTEX_FOR_SPINLOCK	1
+
+// remove function to reduce code
+#define NOT_SUPPORT_5G
+#define NOT_SUPPORT_RF_MULTIPATH
+#define NOT_SUPPORT_VHT
+#define NOT_SUPPORT_40M
+#define NOT_SUPPORT_80M
+#ifndef CONFIG_PLATFORM_8711B
+#define NOT_SUPPORT_BBSWING
+#endif
+#define NOT_SUPPORT_OLD_CHANNEL_PLAN
+#define NOT_SUPPORT_BT
+
+#define CONFIG_WIFI_SPEC	0
+#define CONFIG_FAKE_EFUSE	0
+#if CONFIG_FAKE_EFUSE
+	#define FAKE_CHIPID		CHIPID_8710BN
+#endif
+
+#define CONFIG_AUTO_RECONNECT 1
+#define ENABLE_HWPDN_PIN
+#define SUPPORT_SCAN_BUF	1
+#if !defined(CONFIG_PLATFORM_AMEBA_X)
+#define BE_I_CUT			1
+#endif
+
+/* For WPA2 */
+#define CONFIG_INCLUDE_WPA_PSK
+#ifdef CONFIG_INCLUDE_WPA_PSK
+#define CONFIG_MULTIPLE_WPA_STA
+//#define CONFIG_WPA2_PREAUTH
+#define PSK_SUPPORT_TKIP	1
+#endif
+//#define AP_PSK_SUPPORT_TKIP
+
+/* For promiscuous mode */
+#define CONFIG_PROMISC
+
+#define PROMISC_DENY_PAIRWISE	0
+
+/* For Simple Link */
+#ifndef CONFIG_INCLUDE_SIMPLE_CONFIG
+//#define CONFIG_INCLUDE_SIMPLE_CONFIG 1
+#endif
+
+// for probe request with custom vendor specific IE
+#define CONFIG_CUSTOM_IE
+
+#if !defined(CONFIG_PLATFORM_AMEBA_X)
+/* For multicast */
+#define CONFIG_MULTICAST
+#endif
+
+/* For STA+AP Concurrent MODE */
+#define CONFIG_CONCURRENT_MODE
+#ifdef CONFIG_CONCURRENT_MODE
+  #if defined(CONFIG_PLATFORM_8195A)
+    #define CONFIG_RUNTIME_PORT_SWITCH
+  #endif
+  #if defined(CONFIG_HARDWARE_8188F)
+  #define NET_IF_NUM 2
+  #else
+  #define NET_IF_NUM ((CONFIG_ETHERNET) + (CONFIG_WLAN) + 1)
+  #endif
+#else
+  #if defined(CONFIG_HARDWARE_8188F)
+  #define NET_IF_NUM 1
+  #else
+  #define NET_IF_NUM ((CONFIG_ETHERNET) + (CONFIG_WLAN))
+  #endif
+#endif
+
+
+/****************** For EAP auth configurations *******************/
+#define CONFIG_TLS	0
+#define CONFIG_PEAP	0
+#define CONFIG_TTLS	0
+
+// DO NOT change the below config of EAP
+#ifdef PRE_CONFIG_EAP
+#undef CONFIG_TLS
+#define CONFIG_TLS	1
+#undef CONFIG_PEAP
+#define CONFIG_PEAP	1
+#undef CONFIG_TTLS
+#define CONFIG_TTLS	1
+#endif
+
+// enable 1X code in lib_wlan as default (increase 380 bytes)
+#define CONFIG_EAP
+
+#if CONFIG_TLS || CONFIG_PEAP || CONFIG_TTLS
+#define EAP_REMOVE_UNUSED_CODE 1
+#endif	     
+	     
+#define EAP_SSL_VERIFY_SERVER
+
+#if CONFIG_TLS
+#define EAP_SSL_VERIFY_CLIENT
+#endif
+
+#if CONFIG_TTLS
+#define EAP_MSCHAPv2
+#define EAP_TTLS_MSCHAPv2
+//#define EAP_TTLS_EAP
+//#define EAP_TTLS_MSCHAP
+//#define EAP_TTLS_PAP
+//#define EAP_TTLS_CHAP
+#endif
+/****************** End of EAP configurations *******************/
+
+/* For WPS and P2P */
+#define CONFIG_WPS
+#if 0
+#define CONFIG_WPS_AP
+#define CONFIG_P2P_NEW
+#if (!defined(SUPPORT_SCAN_BUF)||!defined(CONFIG_WPS_AP)) && defined(CONFIG_P2P_NEW)
+#error "If CONFIG_P2P_NEW, need to SUPPORT_SCAN_BUF"
+#endif
+#endif
+
+#define CONFIG_NEW_SIGNAL_STAT_PROCESS
+#define CONFIG_SKIP_SIGNAL_SCALE_MAPPING
+
+/* For AP_MODE */
+#define CONFIG_AP_MODE
+extern unsigned char g_user_ap_sta_num;
+#define USER_AP_STA_NUM g_user_ap_sta_num
+#if defined(CONFIG_PLATFORM_AMEBA_X)
+#define AP_STA_NUM	3	//2014/10/27 modify to 3
+#define USE_DEDICATED_BCN_TX	0
+#if USE_DEDICATED_BCN_TX
+#error "WLAN driver for Ameba should not enable USE_DEDICATED_BCN_TX"
+#endif
+#else
+extern unsigned int g_ap_sta_num;
+#define AP_STA_NUM 3//g_ap_sta_num
+#endif
+#ifdef CONFIG_AP_MODE
+#if defined(CONFIG_PLATFORM_8195A)  
+	 //softap sent qos null0 polling client alive or not
+	#define CONFIG_AP_POLLING_CLIENT_ALIVE 
+#endif
+	#define CONFIG_NATIVEAP_MLME
+#if defined(CONFIG_PLATFORM_AMEBA_X)
+	#define CONFIG_INTERRUPT_BASED_TXBCN
+#endif
+	#ifdef CONFIG_INTERRUPT_BASED_TXBCN
+		//#define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+		#define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+	#endif
+//	#define CONFIG_GK_REKEY
+#if !defined(CONFIG_PLATFORM_AMEBA_X)
+	#define USE_DEDICATED_BCN_TX	1
+#endif
+#if CONFIG_INIC_EN
+//	#define REPORT_STA_EVENT //useless
+#endif
+#else
+#if !defined(CONFIG_PLATFORM_AMEBA_X)
+	#define USE_DEDICATED_BCN_TX	0
+#endif
+#endif
+
+#if defined(CONFIG_AP_MODE) && defined(CONFIG_GK_REKEY) && !defined(CONFIG_MULTIPLE_WPA_STA)
+#error "If CONFIG_GK_REKEY when CONFIG_AP_MODE, need to CONFIG_MULTIPLE_WPA_STA"
+#endif
+
+#if !defined(CONFIG_PLATFORM_AMEBA_X)
+#if !defined(CONFIG_AP_MODE) && defined(CONFIG_CONCURRENT_MODE)
+#error "If CONFIG_CONCURRENT_MODEE, need to CONFIG_AP_MODE"
+#endif
+#endif
+
+/* For efuse or flash config */
+#if defined(CONFIG_PLATFORM_AMEBA_X)
+	#define CONFIG_RW_PHYSICAL_EFUSE			0	// Mask efuse user blocks
+	#define CONFIG_HIDE_PROTECT_EFUSE			1
+	#define CONFIG_ADAPTOR_INFO_CACHING_FLASH	1
+	#define CHECK_FLASH_VALID_MASK				1
+	#define CHECK_EFUSE_VALID_MASK				1
+	/* For K-free */
+//	#if !defined(CONFIG_PLATFORM_8711B)
+		#define CONFIG_RF_GAIN_OFFSET
+//	#endif
+#endif	// CONFIG_PLATFORM_AMEBA_X
+
+/* For MP_MODE */
+//#define CONFIG_MP_INCLUDED
+#ifdef CONFIG_MP_INCLUDED
+	#define MP_DRIVER		1
+	#define CONFIG_MP_IWPRIV_SUPPORT
+//	#define HAL_EFUSE_MEMORY
+	#if defined(CONFIG_PLATFORM_AMEBA_X)
+		#define MP_REG_TEST
+	#endif
+#else
+	#define MP_DRIVER		0
+	#if defined(CONFIG_PLATFORM_8195A)
+		//Control wifi mcu function
+		#define CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD
+		#define CONFIG_ODM_REFRESH_RAMASK
+		//#define CONFIG_ANTENNA_DIVERSITY
+		//#define CONFIG_BT_COEXIST
+	#endif
+#endif // #ifdef CONFIG_MP_INCLUDED
+
+#ifdef CONFIG_BT_COEXIST
+	#undef NOT_SUPPORT_BT
+	#define CONFIG_BT_MAILBOX
+	//#define CONFIG_BT_TWO_ANTENNA
+#endif
+
+#if defined(CONFIG_PLATFORM_AMEBA_X)
+	#if defined(CONFIG_PLATFORM_8195A)
+		#undef CONFIG_RTL8195A
+		#define CONFIG_RTL8195A
+	#endif
+	#if defined(CONFIG_PLATFORM_8711B)
+		#ifndef CONFIG_RTL8711B 
+			#define CONFIG_RTL8711B
+		#endif
+		#undef CONFIG_ADAPTOR_INFO_CACHING_FLASH
+		#define CONFIG_ADAPTOR_INFO_CACHING_FLASH 0
+		//#undef CONFIG_EAP
+		//#undef CONFIG_IPS
+		#define CONFIG_8710B_MOVE_TO_ROM
+		#define CONFIG_EFUSE_SEPARATE
+		#define CONFIG_MOVE_PSK_TO_ROM
+		#define CONFIG_WOWLAN
+		#define CONFIG_TRAFFIC_PROTECT
+		#ifdef CONFIG_LPS
+		#define REKEY_LEAVE_LPS
+		#endif
+	#endif
+#elif defined(CONFIG_HARDWARE_8188F)
+#define CONFIG_RTL8188F
+#else
+#define CONFIG_RTL8188E
+#endif
+#define RTL8192C_SUPPORT 0
+#define RTL8192CE_SUPPORT 0
+#define RTL8192CU_SUPPORT 0
+#define RTL8192D_SUPPORT 0
+#define RTL8192DE_SUPPORT 0
+#define RTL8192DU_SUPPORT 0
+#define RTL8723A_SUPPORT 0
+#define RTL8723AU_SUPPORT 0
+#define RTL8723AS_SUPPORT 0
+#define RTL8192E_SUPPORT 0
+#define RTL8812A_SUPPORT 0
+#define RTL8821A_SUPPORT 0
+#define RTL8723B_SUPPORT 0
+#define RTL8195A_SUPPORT 0
+#define RTL8188E_SUPPORT 0
+#define RTL8188F_SUPPORT 0
+#define RTL8711B_SUPPORT 0
+#if defined(CONFIG_PLATFORM_8195A)
+#undef RTL8195A_SUPPORT
+#define RTL8195A_SUPPORT 1
+#elif defined(CONFIG_PLATFORM_8711B)
+#undef RTL8711B_SUPPORT
+#define RTL8711B_SUPPORT 1
+#elif defined(CONFIG_HARDWARE_8188F)
+#undef	RTL8188F_SUPPORT
+#define RTL8188F_SUPPORT 1
+#else
+#undef RTL8188E_SUPPORT
+#define RTL8188E_SUPPORT 1
+#endif
+
+#define TEST_CHIP_SUPPORT 0
+
+#define RTL8188E_FOR_TEST_CHIP 0
+#define RTL8188E_FPGA_TRUE_PHY_VERIFICATION 0
+
+// for Debug message
+#define DBG 0
+#if defined(CONFIG_PLATFORM_AMEBA_X)
+#if(DBG == 0)
+	#define ROM_E_RTW_MSG 1
+	#define ROM_F_RTW_MSG 1
+	/* For DM debug*/
+	// BB
+	#define DBG_RX_INFO 1
+	#define DBG_DM_DIG 1			// DebugComponents: bit0
+	#define DBG_DM_RA_MASK 1		// DebugComponents: bit1
+	#define DBG_DM_ANT_DIV 1		// DebugComponents: bit6
+	#define DBG_TX_RATE 1			// DebugComponents: bit9
+	#define DBG_DM_RA 1				// DebugComponents: bit9
+	#define DBG_DM_ADAPTIVITY 1		// DebugComponents: bit17
+	// RF
+	#define DBG_PWR_TRACKING 1		// DebugComponents: bit24
+	#define DBG_RF_IQK 1			// DebugComponents: bit26
+	// Common
+	#define DBG_PWR_INDEX 1			// DebugComponents: bit30
+#endif
+#endif
+
+/* For DM support */
+#if defined(CONFIG_RTL8188F)
+#define RATE_ADAPTIVE_SUPPORT 0
+#elif defined(CONFIG_PLATFORM_8711B)
+#define RATE_ADAPTIVE_SUPPORT 0
+#define CONFIG_ODM_REFRESH_RAMASK
+#else
+#define RATE_ADAPTIVE_SUPPORT 1
+#endif
+// adaptivity
+#define RTW_ADAPTIVITY_EN_DISABLE			0
+#define RTW_ADAPTIVITY_EN_ENABLE			1
+#define CONFIG_RTW_ADAPTIVITY_EN			RTW_ADAPTIVITY_EN_DISABLE
+#define RTW_ADAPTIVITY_MODE_NORMAL			0
+#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE	1
+#define CONFIG_RTW_ADAPTIVITY_MODE			RTW_ADAPTIVITY_MODE_CARRIER_SENSE
+#define CONFIG_RTW_ADAPTIVITY_DML			0
+
+
+#if defined(CONFIG_PLATFORM_AMEBA_X)
+	#define CONFIG_POWER_TRAINING_WIL 0 // in RA
+#else
+	#define POWER_BY_RATE_SUPPORT 0
+#endif
+
+#if defined(CONFIG_PLATFORM_AMEBA_X)
+#define RTL8195A_FOR_TEST_CHIP 0
+
+//#define CONFIG_WIFI_TEST 1
+//#define CONFIG_MAC_LOOPBACK_DRIVER 1
+//#define CONFIG_WLAN_HAL_TEST 1
+//#define SKB_PRE_ALLOCATE_TX 1
+#define SKB_PRE_ALLOCATE_RX	0
+#define TX_CHECK_DSEC_ALWAYS 1
+#define CONFIG_DBG_DISABLE_RDU_INTERRUPT
+//#define CONFIG_WLAN_HAL_RX_TASK
+#if (SKB_PRE_ALLOCATE_RX == 1)
+	#define EXCHANGE_LXBUS_RX_SKB 0
+#endif
+#ifdef CONFIG_FPGA
+	//Enable mac loopback for test mode (Ameba)
+	#define CONFIG_TWO_MAC_DRIVER // for test mode
+#endif
+
+#ifdef ENABLE_MAC_LB_FOR_TEST_MODE
+	#define CONFIG_SUDO_PHY_SETTING
+	#define INT_HANDLE_IN_ISR 1
+	#define CONFIG_LWIP_LAYER 0
+	#define CONFIG_WLAN_HAL_TEST
+	#define CONFIG_WLAN_HAL_RX_TASK
+	#define CONFIG_MAC_LOOPBACK_DRIVER_RTL8711B 1
+	#define HAL_MAC_ENABLE 1
+	#define CONFIG_TWO_MAC_TEST_MODE 
+	#define DISABLE_BB_RF 1
+#else
+	//#define CONFIG_TWO_MAC_DRIVER //for mornal driver; two mac
+	#ifdef CONFIG_TWO_MAC_DRIVER
+		#define CONFIG_SUDO_PHY_SETTING
+		#define HAL_MAC_ENABLE 1
+		#define DISABLE_BB_RF 1
+	#else
+		#define HAL_MAC_ENABLE 1
+		#define HAL_BB_ENABLE 1
+		#define HAL_RF_ENABLE 1
+		#define DISABLE_BB_RF 0
+	#endif
+	//#define INT_HANDLE_IN_ISR 1
+#endif
+#endif // CONFIG_PLATFORM_AMEBA_X
+
+#ifndef CONFIG_LWIP_LAYER
+#define CONFIG_LWIP_LAYER 1
+#endif
+#define CONFIG_MAC_ADDRESS 0
+//fast reconnection
+//#define CONFIG_FAST_RECONNECTION 1
+#if defined(CONFIG_INIC_EN)&&(CONFIG_INIC_EN==1)
+#define CONFIG_RECV_REORDERING_CTRL //enable reordering for iNIC high throughput
+#undef RX_AGGREGATION
+#define RX_AGGREGATION 1
+#undef NOT_SUPPORT_40M
+#undef CONFIG_CONCURRENT_MODE
+#endif
+#endif //WLANCONFIG_H

component/common/drivers/wlan/realtek/include/drv_conf.h

@@ -0,0 +1,106 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __DRV_CONF_H__
+#define __DRV_CONF_H__
+
+#include "autoconf.h"
+#if ((RTL8195A_SUPPORT==1) || (RTL8711B_SUPPORT==1))
+#include "platform_autoconf.h"
+#endif
+
+#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+
+#error "Shall be Linux or Windows, but not both!\n"
+
+#endif
+
+//Older Android kernel doesn't has CONFIG_ANDROID defined,
+//add this to force CONFIG_ANDROID defined
+#ifdef CONFIG_PLATFORM_ANDROID
+#define CONFIG_ANDROID
+#endif
+
+#ifdef CONFIG_ANDROID
+//Some Android build will restart the UI while non-printable ascii is passed
+//between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID
+//for Android here. If you are sure there is no risk on your system about this,
+//mask this macro define to support non-printable ascii ssid.
+//#define CONFIG_VALIDATE_SSID
+#ifdef CONFIG_PLATFORM_ARM_SUNxI
+	#ifdef CONFIG_VALIDATE_SSID
+		#undef CONFIG_VALIDATE_SSID
+	#endif
+#endif
+
+//Android expect dbm as the rx signal strength unit
+#define CONFIG_SIGNAL_DISPLAY_DBM
+#endif
+
+#if defined(CONFIG_HAS_EARLYSUSPEND) && defined (CONFIG_RESUME_IN_WORKQUEUE)
+	#warning "You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
+	#undef CONFIG_RESUME_IN_WORKQUEUE
+#endif
+
+#if defined(CONFIG_ANDROID_POWER) && defined (CONFIG_RESUME_IN_WORKQUEUE)
+	#warning "You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
+	#undef CONFIG_RESUME_IN_WORKQUEUE
+#endif
+
+#ifdef CONFIG_RESUME_IN_WORKQUEUE //this can be removed, because there is no case for this...
+	#if !defined( CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER)
+	#error "enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality..."
+	#error "If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK..."
+	#endif
+#endif
+
+//About USB VENDOR REQ
+#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX) 
+	#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically"
+	#define CONFIG_USB_VENDOR_REQ_MUTEX
+#endif
+#if defined(CONFIG_VENDOR_REQ_RETRY) &&  !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
+	#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically"
+	#define CONFIG_USB_VENDOR_REQ_MUTEX
+#endif
+
+#ifndef CONFIG_RTW_ADAPTIVITY_EN
+	#define CONFIG_RTW_ADAPTIVITY_EN 0
+#endif
+
+#ifndef CONFIG_RTW_ADAPTIVITY_MODE
+	#define CONFIG_RTW_ADAPTIVITY_MODE 0
+#endif
+
+#ifndef CONFIG_RTW_ADAPTIVITY_DML
+	#define CONFIG_RTW_ADAPTIVITY_DML 0
+#endif
+
+#ifndef CONFIG_RTW_ADAPTIVITY_DC_BACKOFF
+	#define CONFIG_RTW_ADAPTIVITY_DC_BACKOFF 4
+#endif
+
+#ifndef CONFIG_RTW_NHM_EN
+	#define CONFIG_RTW_NHM_EN 0
+#endif
+
+//#include <rtl871x_byteorder.h>
+
+#endif // __DRV_CONF_H__
+

component/common/drivers/wlan/realtek/include/rom_aes.h

@@ -0,0 +1,38 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved.
+ *                                        
+ * This is ROM code section. 
+ *
+ *
+ ******************************************************************************/
+#ifndef ROM_AES_H
+#define ROM_AES_H
+
+typedef struct
+{
+    u32 erk[64];     				/* encryption round keys */
+    u32 drk[64];     				/* decryption round keys */
+    int nr;             					/* number of rounds */
+}aes_context;
+
+
+#define AES_BLOCKSIZE8	8
+#define AES_BLK_SIZE    	16     	// # octets in an AES block
+typedef union _aes_block  		// AES cipher block
+{
+    unsigned long  x[AES_BLK_SIZE/4];    	// access as 8-bit octets or 32-bit words
+    unsigned char  b[AES_BLK_SIZE];
+}aes_block;
+
+
+void AES_WRAP(unsigned char * plain, int plain_len,
+			  		unsigned char * iv,	int iv_len,
+					unsigned char * kek,	int kek_len,
+			  		unsigned char *cipher, unsigned short *cipher_len);
+
+void AES_UnWRAP(unsigned char * cipher, int cipher_len,
+			   		 unsigned char * kek,	int kek_len,
+			    		unsigned char * plain);
+
+#endif

component/common/drivers/wlan/realtek/include/rtw_debug.h

@@ -0,0 +1,468 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __RTW_DEBUG_H__
+#define __RTW_DEBUG_H__
+
+
+#define _drv_always_		1
+#define _drv_emerg_			2
+#define _drv_alert_			3
+#define _drv_crit_			4
+#define _drv_err_			5
+#define	_drv_warning_		6
+#define _drv_notice_		7
+#define _drv_info_			8
+#define _drv_dump_			9
+#define	_drv_debug_			10
+
+
+#define _module_rtl871x_xmit_c_		BIT(0)
+#define _module_xmit_osdep_c_		BIT(1)
+#define _module_rtl871x_recv_c_		BIT(2)
+#define _module_recv_osdep_c_		BIT(3)
+#define _module_rtl871x_mlme_c_		BIT(4)
+#define _module_mlme_osdep_c_		BIT(5)
+#define _module_rtl871x_sta_mgt_c_		BIT(6)
+#define _module_rtl871x_cmd_c_			BIT(7)
+#define _module_cmd_osdep_c_		BIT(8)
+#define _module_rtl871x_io_c_				BIT(9)
+#define _module_io_osdep_c_		BIT(10)
+#define _module_os_intfs_c_			BIT(11)
+#define _module_rtl871x_security_c_		BIT(12)
+#define _module_rtl871x_eeprom_c_			BIT(13)
+#define _module_hal_init_c_		BIT(14)
+#define _module_hci_hal_init_c_		BIT(15)
+#define _module_rtl871x_ioctl_c_		BIT(16)
+#define _module_rtl871x_ioctl_set_c_		BIT(17)
+#define _module_rtl871x_ioctl_query_c_	BIT(18)
+#define _module_rtl871x_pwrctrl_c_			BIT(19)
+#define _module_hci_intfs_c_			BIT(20)
+#define _module_hci_ops_c_			BIT(21)
+#define _module_osdep_service_c_			BIT(22)
+#define _module_mp_			BIT(23)
+#define _module_hci_ops_os_c_			BIT(24)
+#define _module_rtl871x_ioctl_os_c		BIT(25)
+#define _module_rtl8712_cmd_c_		BIT(26)
+#define _module_fwcmd_c_			BIT(27)
+#define _module_rtl8192c_xmit_c_ BIT(28)
+#define _module_hal_xmit_c_	BIT(28)
+#define _module_efuse_			BIT(29)
+#define _module_rtl8712_recv_c_		BIT(30)
+#define _module_rtl8712_led_c_		BIT(31)
+
+#undef _MODULE_DEFINE_
+
+#if defined _RTW_XMIT_C_
+	#define _MODULE_DEFINE_	_module_rtl871x_xmit_c_
+#elif defined _XMIT_OSDEP_C_
+	#define _MODULE_DEFINE_	_module_xmit_osdep_c_
+#elif defined _RTW_RECV_C_
+	#define _MODULE_DEFINE_	_module_rtl871x_recv_c_
+#elif defined _RECV_OSDEP_C_
+	#define _MODULE_DEFINE_	_module_recv_osdep_c_
+#elif defined _RTW_MLME_C_
+	#define _MODULE_DEFINE_	_module_rtl871x_mlme_c_
+#elif defined _MLME_OSDEP_C_
+	#define _MODULE_DEFINE_	_module_mlme_osdep_c_
+#elif defined _RTW_MLME_EXT_C_
+	#define _MODULE_DEFINE_ 1
+#elif defined _RTW_STA_MGT_C_
+	#define _MODULE_DEFINE_	_module_rtl871x_sta_mgt_c_
+#elif defined _RTW_CMD_C_
+	#define _MODULE_DEFINE_	_module_rtl871x_cmd_c_
+#elif defined _CMD_OSDEP_C_
+	#define _MODULE_DEFINE_	_module_cmd_osdep_c_
+#elif defined _RTW_IO_C_
+	#define _MODULE_DEFINE_	_module_rtl871x_io_c_
+#elif defined _IO_OSDEP_C_
+	#define _MODULE_DEFINE_	_module_io_osdep_c_
+#elif defined _OS_INTFS_C_
+	#define	_MODULE_DEFINE_	_module_os_intfs_c_
+#elif defined _RTW_SECURITY_C_
+	#define	_MODULE_DEFINE_	_module_rtl871x_security_c_
+#elif defined _RTW_EEPROM_C_
+	#define	_MODULE_DEFINE_	_module_rtl871x_eeprom_c_
+#elif defined _HAL_INTF_C_
+	#define	_MODULE_DEFINE_	_module_hal_init_c_
+#elif (defined _HCI_HAL_INIT_C_) || (defined _SDIO_HALINIT_C_)
+	#define	_MODULE_DEFINE_	_module_hci_hal_init_c_
+#elif defined _RTL871X_IOCTL_C_
+	#define	_MODULE_DEFINE_	_module_rtl871x_ioctl_c_
+#elif defined _RTL871X_IOCTL_SET_C_
+	#define	_MODULE_DEFINE_	_module_rtl871x_ioctl_set_c_
+#elif defined _RTL871X_IOCTL_QUERY_C_
+	#define	_MODULE_DEFINE_	_module_rtl871x_ioctl_query_c_
+#elif defined _RTL871X_PWRCTRL_C_
+	#define	_MODULE_DEFINE_	_module_rtl871x_pwrctrl_c_
+#elif defined _RTW_PWRCTRL_C_
+	#define	_MODULE_DEFINE_	1
+#elif defined _HCI_INTF_C_
+	#define	_MODULE_DEFINE_	_module_hci_intfs_c_
+#elif defined _HCI_OPS_C_
+	#define	_MODULE_DEFINE_	_module_hci_ops_c_
+#elif defined _SDIO_OPS_C_
+	#define	_MODULE_DEFINE_ 1
+#elif defined _OSDEP_HCI_INTF_C_
+	#define	_MODULE_DEFINE_	_module_hci_intfs_c_
+#elif defined _OSDEP_SERVICE_C_
+	#define	_MODULE_DEFINE_	_module_osdep_service_c_
+#elif defined _HCI_OPS_OS_C_
+	#define	_MODULE_DEFINE_	_module_hci_ops_os_c_
+#elif defined _RTL871X_IOCTL_LINUX_C_
+	#define	_MODULE_DEFINE_	_module_rtl871x_ioctl_os_c
+#elif defined _RTL8712_CMD_C_
+	#define	_MODULE_DEFINE_	_module_rtl8712_cmd_c_
+#elif defined _RTL8192C_XMIT_C_
+	#define	_MODULE_DEFINE_	1
+#elif defined _RTL8723AS_XMIT_C_
+	#define	_MODULE_DEFINE_	1
+#elif defined _RTL8712_RECV_C_
+	#define	_MODULE_DEFINE_	_module_rtl8712_recv_c_
+#elif defined _RTL8192CU_RECV_C_
+	#define	_MODULE_DEFINE_	_module_rtl8712_recv_c_
+#elif defined _RTL871X_MLME_EXT_C_
+	#define _MODULE_DEFINE_	_module_mlme_osdep_c_
+#elif defined _RTW_MP_C_
+	#define	_MODULE_DEFINE_	_module_mp_
+#elif defined _RTW_MP_IOCTL_C_
+	#define	_MODULE_DEFINE_	_module_mp_
+#elif defined _RTW_EFUSE_C_
+	#define	_MODULE_DEFINE_	_module_efuse_
+#endif
+
+#ifdef PLATFORM_OS_CE
+extern void rtl871x_cedbg(const char *fmt, ...);
+#endif
+
+extern u32 GlobalDebugEnable;
+
+#define RT_TRACE(_Comp, _Level, Fmt) do{}while(0)
+#define _func_enter_ do{}while(0)
+#define _func_exit_ do{}while(0)
+#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) do{}while(0)
+
+#ifdef PLATFORM_WINDOWS
+	#define DBG_871X do {} while(0)
+	#define MSG_8192C do {} while(0)
+	#define DBG_8192C do {} while(0)
+	#define DBG_871X_LEVEL do {} while(0)
+#else
+	#define DBG_871X(x, ...) do {} while(0)
+	#define MSG_8192C(x, ...) do {} while(0)
+	#define DBG_8192C(x,...) do {} while(0)
+	#define DBG_871X_LEVEL(x,...) do {} while(0)
+#endif
+
+#ifdef CONFIG_BT_COEXIST
+	#define RTW_INFO(x,...) do {} while (0)
+	#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0)
+#endif
+
+#undef	_dbgdump
+#ifdef PLATFORM_WINDOWS
+
+	#ifdef PLATFORM_OS_XP
+		#define _dbgdump	DbgPrint
+	#elif defined PLATFORM_OS_CE
+		#define _dbgdump	rtl871x_cedbg
+	#endif
+
+#elif defined PLATFORM_LINUX
+	#define _dbgdump	printk
+#elif defined PLATFORM_ECOS
+	#define _dbgdump	diag_printf
+#elif defined PLATFORM_FREERTOS
+	#define _dbgdump	printf("\n\r"); printf
+#elif defined PLATFORM_FREEBSD
+	#define _dbgdump	printf
+#endif
+
+#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B)
+#define DRIVER_PREFIX	"RTL871X: "
+#endif
+
+#define DEBUG_LEVEL	(_drv_err_)
+#if 	defined (_dbgdump)
+	#undef DBG_871X_LEVEL
+#if defined (__ICCARM__) || defined (__CC_ARM) ||defined(__GNUC__)|| defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
+	#define DBG_871X_LEVEL(level, ...)     \
+	do {\
+             if(GlobalDebugEnable){\
+			_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
+		}\
+	}while(0)
+#else
+	#define DBG_871X_LEVEL(level, fmt, arg...)     \
+	do {\
+		if(GlobalDebugEnable){\
+			if (level <= DEBUG_LEVEL) {\
+				if (level <= _drv_err_ && level > _drv_always_) {\
+					_dbgdump(DRIVER_PREFIX"ERROR " fmt, ##arg);\
+				} \
+				else {\
+					_dbgdump(DRIVER_PREFIX fmt, ##arg);\
+				} \
+			}\
+		}\
+	}while(0)
+
+#endif	//#ifdef __CC_ARM
+#endif
+
+#ifdef CONFIG_DEBUG
+#if	defined (_dbgdump)
+	#undef DBG_871X
+	#define DBG_871X(...)     do {\
+		_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
+	}while(0)
+
+	#undef MSG_8192C
+	#define MSG_8192C(...)     do {\
+		_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
+	}while(0)
+
+	#undef DBG_8192C
+	#define DBG_8192C(...)     do {\
+		_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
+	}while(0)
+#endif
+#endif /* CONFIG_DEBUG */
+
+#ifdef CONFIG_DEBUG_RTL871X
+#ifndef _RTL871X_DEBUG_C_
+	extern u32 GlobalDebugLevel;
+	extern u64 GlobalDebugComponents;
+#endif
+
+#if	defined (_dbgdump) && defined (_MODULE_DEFINE_)
+
+		#undef RT_TRACE
+		#define RT_TRACE(_Comp, _Level, Fmt)\
+		do {\
+			if((_Comp & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) {\
+				_dbgdump("%s [0x%08x,%d]", DRIVER_PREFIX, (unsigned int)_Comp, _Level);\
+				_dbgdump Fmt;\
+			}\
+		}while(0)
+
+#endif
+
+
+#if	defined (_dbgdump)
+
+		#undef  _func_enter_
+		#define _func_enter_ \
+		do {	\
+			if (GlobalDebugLevel >= _drv_debug_) \
+			{																	\
+				_dbgdump("\n %s : %s enters at %d\n", DRIVER_PREFIX, __FUNCTION__, __LINE__);\
+			}		\
+		} while(0)
+
+		#undef  _func_exit_
+		#define _func_exit_ \
+		do {	\
+			if (GlobalDebugLevel >= _drv_debug_) \
+			{																	\
+				_dbgdump("\n %s : %s exits at %d\n", DRIVER_PREFIX, __FUNCTION__, __LINE__); \
+			}	\
+		} while(0)
+
+		#undef RT_PRINT_DATA
+		#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)			\
+			if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel))	\
+			{									\
+				int __i;								\
+				u8	*ptr = (u8 *)_HexData;				\
+				printf("\r\n%s", DRIVER_PREFIX);						\
+				printf(_TitleString "--------Len=%d\n\r", _HexDataLen);						\
+				for( __i=0; __i<(int)_HexDataLen; __i++ )				\
+				{								\
+					printf("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?"  ":" ");	\
+					if (((__i + 1) % 16) == 0)	printf("\n\r");			\
+				}								\
+				printf("\n\r");							\
+			}
+#endif
+#endif /* CONFIG_DEBUG_RTL871X */
+
+
+#ifdef CONFIG_PROC_DEBUG
+
+	int proc_get_drv_version(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_write_reg(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+ 	int proc_set_write_reg(struct file *file, const char *buffer,
+		unsigned long count, void *data);
+
+	int proc_get_read_reg(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_set_read_reg(struct file *file, const char *buffer,
+		unsigned long count, void *data);
+
+
+	int proc_get_fwstate(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_sec_info(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_mlmext_state(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_qos_option(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_ht_option(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_rf_info(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_ap_info(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_adapter_state(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_trx_info(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_mac_reg_dump1(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_mac_reg_dump2(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_mac_reg_dump3(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_bb_reg_dump1(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_bb_reg_dump2(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_bb_reg_dump3(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_rf_reg_dump1(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_rf_reg_dump2(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_rf_reg_dump3(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_rf_reg_dump4(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+#ifdef CONFIG_AP_MODE
+
+	int proc_get_all_sta_info(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+#endif
+
+#ifdef DBG_MEMORY_LEAK
+	int proc_get_malloc_cnt(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+#endif
+
+#ifdef CONFIG_FIND_BEST_CHANNEL
+	int proc_get_best_channel(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+#endif
+
+	int proc_get_rx_signal(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_set_rx_signal(struct file *file, const char *buffer,
+		unsigned long count, void *data);
+#ifdef CONFIG_80211N_HT
+	int proc_get_cbw40_enable(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_set_cbw40_enable(struct file *file, const char *buffer,
+		unsigned long count, void *data);
+	
+	int proc_get_ampdu_enable(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+			  
+	int proc_set_ampdu_enable(struct file *file, const char *buffer,
+		unsigned long count, void *data);
+	
+	int proc_get_rx_stbc(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+		
+	int proc_set_rx_stbc(struct file *file, const char *buffer,
+		unsigned long count, void *data);
+#endif //CONFIG_80211N_HT
+
+	int proc_get_two_path_rssi(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_get_rssi_disp(char *page, char **start,
+			  off_t offset, int count,
+			  int *eof, void *data);
+
+	int proc_set_rssi_disp(struct file *file, const char *buffer,
+		unsigned long count, void *data);
+
+
+#endif //CONFIG_PROC_DEBUG
+
+#endif	//__RTW_DEBUG_H__
+

component/common/drivers/wlan/realtek/include/wifi_constants.h

@@ -0,0 +1,527 @@
+/**
+  ******************************************************************************
+  * @file    wifi_constants.h
+  * @author
+  * @version
+  * @brief   This file provides the data types used for wlan API.
+  ******************************************************************************
+  * @attention
+  *
+  * This module is a confidential and proprietary property of RealTek and
+  * possession or use of this module requires written permission of RealTek.
+  *
+  * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
+  ****************************************************************************** 
+  */
+
+#ifndef _WIFI_CONSTANTS_H
+#define _WIFI_CONSTANTS_H
+
+/** @addtogroup nic NIC
+ *  @ingroup    wlan
+ *  @brief      NIC functions
+ *  @{
+ */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifndef WLAN0_NAME
+  #define WLAN0_NAME		"wlan0"
+#endif
+#ifndef WLAN1_NAME
+  #define WLAN1_NAME		"wlan1"
+#endif
+
+#define WEP_ENABLED        0x0001
+#define TKIP_ENABLED       0x0002
+#define AES_ENABLED        0x0004
+#define WSEC_SWFLAG        0x0008
+
+#define SHARED_ENABLED  0x00008000
+#define WPA_SECURITY    0x00200000
+#define WPA2_SECURITY   0x00400000
+#define WPS_ENABLED     0x10000000
+
+#define RTW_MAX_PSK_LEN		(64)
+#define RTW_MIN_PSK_LEN		(8)
+
+#define MCSSET_LEN			16
+
+/**
+  * @brief  The enumeration lists the results of the function.
+  */
+typedef enum
+{
+    RTW_SUCCESS                      = 0,    /**< Success */
+    RTW_PENDING                      = 1,    /**< Pending */
+    RTW_TIMEOUT                      = 2,    /**< Timeout */
+    RTW_PARTIAL_RESULTS              = 3,    /**< Partial results */
+    RTW_INVALID_KEY                  = 4,    /**< Invalid key */
+    RTW_DOES_NOT_EXIST               = 5,    /**< Does not exist */
+    RTW_NOT_AUTHENTICATED            = 6,    /**< Not authenticated */
+    RTW_NOT_KEYED                    = 7,    /**< Not keyed */
+    RTW_IOCTL_FAIL                   = 8,    /**< IOCTL fail */
+    RTW_BUFFER_UNAVAILABLE_TEMPORARY = 9,    /**< Buffer unavailable temporarily */
+    RTW_BUFFER_UNAVAILABLE_PERMANENT = 10,   /**< Buffer unavailable permanently */
+    RTW_WPS_PBC_OVERLAP              = 11,   /**< WPS PBC overlap */
+    RTW_CONNECTION_LOST              = 12,   /**< Connection lost */
+
+    RTW_ERROR                        = -1,   /**< Generic Error */
+    RTW_BADARG                       = -2,   /**< Bad Argument */
+    RTW_BADOPTION                    = -3,   /**< Bad option */
+    RTW_NOTUP                        = -4,   /**< Not up */
+    RTW_NOTDOWN                      = -5,   /**< Not down */
+    RTW_NOTAP                        = -6,   /**< Not AP */
+    RTW_NOTSTA                       = -7,   /**< Not STA  */
+    RTW_BADKEYIDX                    = -8,   /**< BAD Key Index */
+    RTW_RADIOOFF                     = -9,   /**< Radio Off */
+    RTW_NOTBANDLOCKED                = -10,  /**< Not  band locked */
+    RTW_NOCLK                        = -11,  /**< No Clock */
+    RTW_BADRATESET                   = -12,  /**< BAD Rate valueset */
+    RTW_BADBAND                      = -13,  /**< BAD Band */
+    RTW_BUFTOOSHORT                  = -14,  /**< Buffer too short */
+    RTW_BUFTOOLONG                   = -15,  /**< Buffer too long */
+    RTW_BUSY                         = -16,  /**< Busy */
+    RTW_NOTASSOCIATED                = -17,  /**< Not Associated */
+    RTW_BADSSIDLEN                   = -18,  /**< Bad SSID len */
+    RTW_OUTOFRANGECHAN               = -19,  /**< Out of Range Channel */
+    RTW_BADCHAN                      = -20,  /**< Bad Channel */
+    RTW_BADADDR                      = -21,  /**< Bad Address */
+    RTW_NORESOURCE                   = -22,  /**< Not Enough Resources */
+    RTW_UNSUPPORTED                  = -23,  /**< Unsupported */
+    RTW_BADLEN                       = -24,  /**< Bad length */
+    RTW_NOTREADY                     = -25,  /**< Not Ready */
+    RTW_EPERM                        = -26,  /**< Not Permitted */
+    RTW_NOMEM                        = -27,  /**< No Memory */
+    RTW_ASSOCIATED                   = -28,  /**< Associated */
+    RTW_RANGE                        = -29,  /**< Not In Range */
+    RTW_NOTFOUND                     = -30,  /**< Not Found */
+    RTW_WME_NOT_ENABLED              = -31,  /**< WME Not Enabled */
+    RTW_TSPEC_NOTFOUND               = -32,  /**< TSPEC Not Found */
+    RTW_ACM_NOTSUPPORTED             = -33,  /**< ACM Not Supported */
+    RTW_NOT_WME_ASSOCIATION          = -34,  /**< Not WME Association */
+    RTW_SDIO_ERROR                   = -35,  /**< SDIO Bus Error */
+    RTW_WLAN_DOWN                    = -36,  /**< WLAN Not Accessible */
+    RTW_BAD_VERSION                  = -37,  /**< Incorrect version */
+    RTW_TXFAIL                       = -38,  /**< TX failure */
+    RTW_RXFAIL                       = -39,  /**< RX failure */
+    RTW_NODEVICE                     = -40,  /**< Device not present */
+    RTW_UNFINISHED                   = -41,  /**< To be finished */
+    RTW_NONRESIDENT                  = -42,  /**< access to nonresident overlay */
+    RTW_DISABLED                     = -43   /**< Disabled in this build */
+} rtw_result_t;
+
+/**
+  * @brief  The enumeration lists the possible security types to set when connection.\n
+  *			Station mode supports OPEN, WEP, and WPA2.\n
+  *			AP mode support OPEN and WPA2.
+  */
+typedef enum {
+    RTW_SECURITY_OPEN           = 0,                                                /**< Open security                           */
+    RTW_SECURITY_WEP_PSK        = WEP_ENABLED,                                      /**< WEP Security with open authentication   */
+    RTW_SECURITY_WEP_SHARED     = ( WEP_ENABLED | SHARED_ENABLED ),                 /**< WEP Security with shared authentication */
+    RTW_SECURITY_WPA_TKIP_PSK   = ( WPA_SECURITY  | TKIP_ENABLED ),                 /**< WPA Security with TKIP                  */
+    RTW_SECURITY_WPA_AES_PSK    = ( WPA_SECURITY  | AES_ENABLED ),                  /**< WPA Security with AES                   */
+    RTW_SECURITY_WPA2_AES_PSK   = ( WPA2_SECURITY | AES_ENABLED ),                  /**< WPA2 Security with AES                  */
+    RTW_SECURITY_WPA2_TKIP_PSK  = ( WPA2_SECURITY | TKIP_ENABLED ),                 /**< WPA2 Security with TKIP                 */
+    RTW_SECURITY_WPA2_MIXED_PSK = ( WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED ),   /**< WPA2 Security with AES & TKIP           */
+    RTW_SECURITY_WPA_WPA2_MIXED = ( WPA_SECURITY  | WPA2_SECURITY ),                /**< WPA/WPA2 Security                       */
+
+    RTW_SECURITY_WPS_OPEN       = WPS_ENABLED,                                      /**< WPS with open security                  */
+    RTW_SECURITY_WPS_SECURE     = (WPS_ENABLED | AES_ENABLED),                      /**< WPS with AES security                   */
+
+    RTW_SECURITY_UNKNOWN        = -1,                                               /**< May be returned by scan function if security is unknown. Do not pass this to the join function! */
+
+    RTW_SECURITY_FORCE_32_BIT   = 0x7fffffff                                        /**< Exists only to force rtw_security_t type to 32 bits */
+} rtw_security_t;
+
+typedef enum {
+    RTW_ENCRYPTION_UNKNOWN = 0,                 
+    RTW_ENCRYPTION_OPEN = 1,
+    RTW_ENCRYPTION_WEP40 = 2,
+    RTW_ENCRYPTION_WPA_TKIP = 3,
+    RTW_ENCRYPTION_WPA_AES = 4,
+    RTW_ENCRYPTION_WPA2_TKIP = 5,
+    RTW_ENCRYPTION_WPA2_AES = 6,
+    RTW_ENCRYPTION_WPA2_MIXED = 7,
+    RTW_ENCRYPTION_WEP104 = 9,
+    RTW_ENCRYPTION_UNDEF = 0xFF,                 
+} rtw_encryption_t;
+
+typedef enum {
+	RTW_FALSE = 0,
+	RTW_TRUE  = 1
+} rtw_bool_t;
+
+/**
+  * @brief  The enumeration lists the band types.
+  */
+typedef enum {
+	RTW_802_11_BAND_5GHZ   = 0, /**< Denotes 5GHz radio band   */
+	RTW_802_11_BAND_2_4GHZ = 1  /**< Denotes 2.4GHz radio band */
+} rtw_802_11_band_t;
+
+/**
+  * @brief  The enumeration lists all the country codes able to set to Wi-Fi driver.
+  */
+typedef enum {
+	/* CHANNEL PLAN */
+	RTW_COUNTRY_WORLD1,	// 0x20
+	RTW_COUNTRY_ETSI1,	// 0x21
+	RTW_COUNTRY_FCC1,	// 0x22
+	RTW_COUNTRY_MKK1,	// 0x23
+	RTW_COUNTRY_ETSI2,	// 0x24
+	RTW_COUNTRY_FCC2,	// 0x2A
+	RTW_COUNTRY_WORLD2,	// 0x47
+	RTW_COUNTRY_MKK2,	// 0x58
+	RTW_COUNTRY_GLOBAL,	// 0x41
+
+	/* SPECIAL */
+	RTW_COUNTRY_WORLD,	// WORLD1
+	RTW_COUNTRY_EU,		// ETSI1
+
+	/* JAPANESE */
+	RTW_COUNTRY_JP,		// MKK1
+
+	/* FCC , 19 countries*/
+	RTW_COUNTRY_AS,		// FCC2
+	RTW_COUNTRY_BM,
+	RTW_COUNTRY_CA,
+	RTW_COUNTRY_DM,
+	RTW_COUNTRY_DO,
+	RTW_COUNTRY_FM,
+	RTW_COUNTRY_GD,
+	RTW_COUNTRY_GT,
+	RTW_COUNTRY_GU,
+	RTW_COUNTRY_HT,
+	RTW_COUNTRY_MH,
+	RTW_COUNTRY_MP,
+	RTW_COUNTRY_NI,
+	RTW_COUNTRY_PA,
+	RTW_COUNTRY_PR,
+	RTW_COUNTRY_PW,
+	RTW_COUNTRY_TW,
+	RTW_COUNTRY_US,
+	RTW_COUNTRY_VI,
+
+	/* others,  ETSI */
+	RTW_COUNTRY_AD,		// ETSI1
+	RTW_COUNTRY_AE,
+	RTW_COUNTRY_AF,
+	RTW_COUNTRY_AI,
+	RTW_COUNTRY_AL,
+	RTW_COUNTRY_AM,
+	RTW_COUNTRY_AN,
+	RTW_COUNTRY_AR,
+	RTW_COUNTRY_AT,
+	RTW_COUNTRY_AU,
+	RTW_COUNTRY_AW,
+	RTW_COUNTRY_AZ,
+	RTW_COUNTRY_BA,
+	RTW_COUNTRY_BB,
+	RTW_COUNTRY_BD,
+	RTW_COUNTRY_BE,
+	RTW_COUNTRY_BF,
+	RTW_COUNTRY_BG,
+	RTW_COUNTRY_BH,
+	RTW_COUNTRY_BL,
+	RTW_COUNTRY_BN,
+	RTW_COUNTRY_BO,
+	RTW_COUNTRY_BR,
+	RTW_COUNTRY_BS,
+	RTW_COUNTRY_BT,
+	RTW_COUNTRY_BY,
+	RTW_COUNTRY_BZ,
+	RTW_COUNTRY_CF,
+	RTW_COUNTRY_CH,
+	RTW_COUNTRY_CI,
+	RTW_COUNTRY_CL,
+	RTW_COUNTRY_CN,
+	RTW_COUNTRY_CO,
+	RTW_COUNTRY_CR,
+	RTW_COUNTRY_CX,
+	RTW_COUNTRY_CY,
+	RTW_COUNTRY_CZ,
+	RTW_COUNTRY_DE,
+	RTW_COUNTRY_DK,
+	RTW_COUNTRY_DZ,
+	RTW_COUNTRY_EC,
+	RTW_COUNTRY_EE,
+	RTW_COUNTRY_EG,
+	RTW_COUNTRY_ES,
+	RTW_COUNTRY_ET,
+	RTW_COUNTRY_FI,
+	RTW_COUNTRY_FR,
+	RTW_COUNTRY_GB,
+	RTW_COUNTRY_GE,
+	RTW_COUNTRY_GF,
+	RTW_COUNTRY_GH,
+	RTW_COUNTRY_GL,
+	RTW_COUNTRY_GP,
+	RTW_COUNTRY_GR,
+	RTW_COUNTRY_GY,
+	RTW_COUNTRY_HK,
+	RTW_COUNTRY_HN,
+	RTW_COUNTRY_HR,
+	RTW_COUNTRY_HU,
+	RTW_COUNTRY_ID,
+	RTW_COUNTRY_IE,
+	RTW_COUNTRY_IL,
+	RTW_COUNTRY_IN,
+	RTW_COUNTRY_IQ,
+	RTW_COUNTRY_IR,
+	RTW_COUNTRY_IS,
+	RTW_COUNTRY_IT,
+	RTW_COUNTRY_JM,
+	RTW_COUNTRY_JO,
+	RTW_COUNTRY_KE,
+	RTW_COUNTRY_KH,
+	RTW_COUNTRY_KN,
+	RTW_COUNTRY_KP,
+	RTW_COUNTRY_KR,
+	RTW_COUNTRY_KW,
+	RTW_COUNTRY_KY,
+	RTW_COUNTRY_KZ,
+	RTW_COUNTRY_LA,
+	RTW_COUNTRY_LB,
+	RTW_COUNTRY_LC,
+	RTW_COUNTRY_LI,
+	RTW_COUNTRY_LK,
+	RTW_COUNTRY_LR,
+	RTW_COUNTRY_LS,
+	RTW_COUNTRY_LT,
+	RTW_COUNTRY_LU,
+	RTW_COUNTRY_LV,
+	RTW_COUNTRY_MA,
+	RTW_COUNTRY_MC,
+	RTW_COUNTRY_MD,
+	RTW_COUNTRY_ME,
+	RTW_COUNTRY_MF,
+	RTW_COUNTRY_MK,
+	RTW_COUNTRY_MN,
+	RTW_COUNTRY_MO,
+	RTW_COUNTRY_MQ,
+	RTW_COUNTRY_MR,
+	RTW_COUNTRY_MT,
+	RTW_COUNTRY_MU,
+	RTW_COUNTRY_MV,
+	RTW_COUNTRY_MW,
+	RTW_COUNTRY_MX,
+	RTW_COUNTRY_MY,
+	RTW_COUNTRY_NG,
+	RTW_COUNTRY_NL,
+	RTW_COUNTRY_NO,
+	RTW_COUNTRY_NP,
+	RTW_COUNTRY_NZ,
+	RTW_COUNTRY_OM,
+	RTW_COUNTRY_PE,
+	RTW_COUNTRY_PF,
+	RTW_COUNTRY_PG,
+	RTW_COUNTRY_PH,
+	RTW_COUNTRY_PK,
+	RTW_COUNTRY_PL,
+	RTW_COUNTRY_PM,
+	RTW_COUNTRY_PT,
+	RTW_COUNTRY_PY,
+	RTW_COUNTRY_QA,
+	RTW_COUNTRY_RS,
+	RTW_COUNTRY_RU,
+	RTW_COUNTRY_RW,
+	RTW_COUNTRY_SA,
+	RTW_COUNTRY_SE,
+	RTW_COUNTRY_SG,
+	RTW_COUNTRY_SI,
+	RTW_COUNTRY_SK,
+	RTW_COUNTRY_SN,
+	RTW_COUNTRY_SR,
+	RTW_COUNTRY_SV,
+	RTW_COUNTRY_SY,
+	RTW_COUNTRY_TC,
+	RTW_COUNTRY_TD,
+	RTW_COUNTRY_TG,
+	RTW_COUNTRY_TH,
+	RTW_COUNTRY_TN,
+	RTW_COUNTRY_TR,
+	RTW_COUNTRY_TT,
+	RTW_COUNTRY_TZ,
+	RTW_COUNTRY_UA,
+	RTW_COUNTRY_UG,
+	RTW_COUNTRY_UY,
+	RTW_COUNTRY_UZ,
+	RTW_COUNTRY_VC,
+	RTW_COUNTRY_VE,
+	RTW_COUNTRY_VN,
+	RTW_COUNTRY_VU,
+	RTW_COUNTRY_WF,
+	RTW_COUNTRY_WS,
+	RTW_COUNTRY_YE,
+	RTW_COUNTRY_YT,
+	RTW_COUNTRY_ZA,
+	RTW_COUNTRY_ZW,
+	
+	RTW_COUNTRY_MAX
+
+}rtw_country_code_t;
+
+/**
+  * @brief  The enumeration lists the adaptivity types.
+  */
+typedef enum {
+	RTW_ADAPTIVITY_DISABLE = 0,
+	RTW_ADAPTIVITY_NORMAL,			// CE
+	RTW_ADAPTIVITY_CARRIER_SENSE	// MKK
+} rtw_adaptivity_mode_t;
+
+/**
+  * @brief  The enumeration lists the supported operation mode by WIFI driver,
+  *			including station and AP mode.
+  */
+typedef enum {
+	RTW_MODE_NONE = 0,
+	RTW_MODE_STA,
+	RTW_MODE_AP,
+	RTW_MODE_STA_AP,
+	RTW_MODE_PROMISC,
+	RTW_MODE_P2P
+}rtw_mode_t;
+
+typedef enum {
+	RTW_SCAN_FULL = 0,
+	RTW_SCAN_SOCIAL,
+	RTW_SCAN_ONE
+}rtw_scan_mode_t;
+
+/**
+  * @brief  The enumeration lists the status to describe the connection link.
+  */
+typedef enum {
+	RTW_LINK_DISCONNECTED = 0,
+	RTW_LINK_CONNECTED
+} rtw_link_status_t;
+
+/**
+  * @brief  The enumeration lists the scan types.
+  */
+typedef enum {
+    RTW_SCAN_TYPE_ACTIVE              = 0x00,  /**< Actively scan a network by sending 802.11 probe(s)         */
+    RTW_SCAN_TYPE_PASSIVE             = 0x01,  /**< Passively scan a network by listening for beacons from APs */
+    RTW_SCAN_TYPE_PROHIBITED_CHANNELS = 0x04   /**< Passively scan on channels not enabled by the country code */
+} rtw_scan_type_t;
+
+/**
+  * @brief  The enumeration lists the bss types.
+  */
+typedef enum {
+    RTW_BSS_TYPE_INFRASTRUCTURE = 0, /**< Denotes infrastructure network                  */
+    RTW_BSS_TYPE_ADHOC          = 1, /**< Denotes an 802.11 ad-hoc IBSS network           */
+    RTW_BSS_TYPE_ANY            = 2, /**< Denotes either infrastructure or ad-hoc network */
+
+    RTW_BSS_TYPE_UNKNOWN        = -1 /**< May be returned by scan function if BSS type is unknown. Do not pass this to the Join function */
+} rtw_bss_type_t;
+
+typedef enum {
+	RTW_SCAN_COMMAMD = 0x01
+} rtw_scan_command_t;
+
+typedef enum{
+	COMMAND1					= 0x01
+}rtw_command_type;
+
+typedef enum {
+	RTW_WPS_TYPE_DEFAULT 		    	= 0x0000,
+	RTW_WPS_TYPE_USER_SPECIFIED 		= 0x0001,
+	RTW_WPS_TYPE_MACHINE_SPECIFIED   	= 0x0002,
+	RTW_WPS_TYPE_REKEY 			        = 0x0003,
+	RTW_WPS_TYPE_PUSHBUTTON 		    = 0x0004,
+	RTW_WPS_TYPE_REGISTRAR_SPECIFIED 	= 0x0005,
+    RTW_WPS_TYPE_NONE                   = 0x0006,
+    RTW_WPS_TYPE_WSC                    = 0x0007
+} rtw_wps_type_t;
+
+/**
+  * @brief  The enumeration lists all the network bgn mode.
+  */
+typedef enum {
+    RTW_NETWORK_B   = 1,
+	RTW_NETWORK_BG  = 3,
+	RTW_NETWORK_BGN = 11
+} rtw_network_mode_t;
+
+/**
+  * @brief  The enumeration lists the interfaces.
+  */
+typedef enum {
+    RTW_STA_INTERFACE     = 0, /**< STA or Client Interface  */
+    RTW_AP_INTERFACE      = 1, /**< SoftAP Interface         */
+} rtw_interface_t;
+
+/**
+  * @brief  The enumeration lists the packet filter rules.
+  */
+typedef enum {
+	RTW_POSITIVE_MATCHING  = 0, /**< Receive the data matching with this pattern and discard the other data   */
+	RTW_NEGATIVE_MATCHING  = 1  /**< Discard the data matching with this pattern and receive the other data */
+} rtw_packet_filter_rule_t;
+
+/**
+  * @brief  The enumeration lists the promisc levels.
+  */
+typedef enum {
+	RTW_PROMISC_DISABLE = 0,  /**< Disable the promisc */
+	RTW_PROMISC_ENABLE = 1,   /**< Fetch all ethernet packets */
+	RTW_PROMISC_ENABLE_1 = 2, /**< Fetch only B/M packets */
+	RTW_PROMISC_ENABLE_2 = 3, /**< Fetch all 802.11 packets*/
+	RTW_PROMISC_ENABLE_3 = 4, /**< Fetch only B/M 802.11 packets*/
+} rtw_rcr_level_t;
+
+/**
+  * @brief  The enumeration lists the disconnect reasons.
+  */
+typedef enum{
+	RTW_NO_ERROR = 0,
+	RTW_NONE_NETWORK = 1,
+	RTW_CONNECT_FAIL = 2,
+	RTW_WRONG_PASSWORD = 3 ,
+	RTW_DHCP_FAIL = 4,
+	RTW_UNKNOWN,
+}rtw_connect_error_flag_t;
+
+typedef enum {
+	RTW_TX_PWR_PERCENTAGE_100 = 0, /* 100%, default target output power.	 */
+	RTW_TX_PWR_PERCENTAGE_75 = 1, /* 75% */
+	RTW_TX_PWR_PERCENTAGE_50 = 2, /* 50% */
+	RTW_TX_PWR_PERCENTAGE_25 = 3, /* 25% */
+	RTW_TX_PWR_PERCENTAGE_12_5 = 4, /* 12.5% */
+}rtw_tx_pwr_percentage_t;
+
+/**
+  * @brief  The enumeration is event type indicated from wlan driver.
+  */
+typedef enum _WIFI_EVENT_INDICATE{
+	WIFI_EVENT_CONNECT = 0,
+	WIFI_EVENT_DISCONNECT = 1,
+	WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2,	
+	WIFI_EVENT_SCAN_RESULT_REPORT = 3,
+	WIFI_EVENT_SCAN_DONE = 4,
+	WIFI_EVENT_RECONNECTION_FAIL = 5,
+	WIFI_EVENT_SEND_ACTION_DONE = 6,
+	WIFI_EVENT_RX_MGNT = 7,
+	WIFI_EVENT_STA_ASSOC = 8,
+	WIFI_EVENT_STA_DISASSOC = 9,
+	WIFI_EVENT_STA_WPS_START = 10,
+	WIFI_EVENT_WPS_FINISH = 11,
+	WIFI_EVENT_EAPOL_START = 12,
+	WIFI_EVENT_EAPOL_RECVD = 13,
+	WIFI_EVENT_NO_NETWORK = 14,
+	WIFI_EVENT_BEACON_AFTER_DHCP = 15,
+	WIFI_EVENT_MAX,
+}rtw_event_indicate_t;
+#ifdef	__cplusplus
+}
+#endif
+
+/*\@}*/
+
+#endif /* _WIFI_CONSTANTS_H */

component/common/drivers/wlan/realtek/include/wifi_structures.h

@@ -0,0 +1,233 @@
+/**
+  ******************************************************************************
+  * @file    wifi_structures.h
+  * @author
+  * @version
+  * @brief   This file provides the data structures used for wlan API.
+  ******************************************************************************
+  * @attention
+  *
+  * This module is a confidential and proprietary property of RealTek and
+  * possession or use of this module requires written permission of RealTek.
+  *
+  * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
+  ****************************************************************************** 
+  */
+
+#ifndef _WIFI_STRUCTURES_H
+#define _WIFI_STRUCTURES_H
+
+/** @addtogroup nic NIC
+ *  @ingroup    wlan
+ *  @brief      NIC functions
+ *  @{
+ */
+
+//#include <freertos/freertos_service.h>
+#include "wifi_constants.h"
+#include "dlist.h"
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#if defined(__IAR_SYSTEMS_ICC__)|| defined (__GNUC__)
+#pragma pack(1)
+#endif
+
+/**
+  * @brief  The structure is used to describe the SSID.
+  */
+typedef struct rtw_ssid {
+    unsigned char len;     /**< SSID length */
+    unsigned char val[33]; /**< SSID name (AP name)  */
+} rtw_ssid_t;
+#if defined(__IAR_SYSTEMS_ICC__)|| defined (__GNUC__)
+#pragma pack()
+#endif
+
+#if defined(__IAR_SYSTEMS_ICC__)|| defined (__GNUC__)
+#pragma pack(1)
+#endif
+
+/**
+  * @brief  The structure is used to describe the unique 6-byte MAC address.
+  */
+typedef struct rtw_mac {
+    unsigned char octet[6]; /**< Unique 6-byte MAC address */
+} rtw_mac_t;
+#if defined(__IAR_SYSTEMS_ICC__)|| defined (__GNUC__)
+#pragma pack()
+#endif
+
+/**
+  * @brief  The structure is used to describe the setting about SSID,
+  *			security type, password and default channel, used to start AP mode.
+  * @note  The data length of string pointed by ssid and password should not exceed 32.
+  */
+typedef struct rtw_ap_info {
+	rtw_ssid_t 			ssid;
+	rtw_security_t		security_type;
+	unsigned char 		*password;
+	int 				password_len;
+	int					channel;
+}rtw_ap_info_t;
+
+/**
+  * @brief  The structure is used to describe the station mode setting about SSID, 
+  *			security type and password, used when connecting to an AP.
+  * @note  The data length of string pointed by ssid and password should not exceed 32.
+  */
+typedef struct rtw_network_info {
+	rtw_ssid_t 			ssid;
+	rtw_mac_t			bssid;
+	rtw_security_t		security_type;
+	unsigned char 		*password;
+	int 				password_len;
+	int					key_id;
+}rtw_network_info_t;
+
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
+#pragma pack(1)
+#endif
+
+/**
+  * @brief  The structure is used to describe the scan result of the AP.
+  */
+typedef struct rtw_scan_result {
+    rtw_ssid_t              SSID;             /**< Service Set Identification (i.e. Name of Access Point)                    */
+    rtw_mac_t               BSSID;            /**< Basic Service Set Identification (i.e. MAC address of Access Point)       */
+    signed short		                  signal_strength;  /**< Receive Signal Strength Indication in dBm. <-90=Very poor, >-30=Excellent */
+    rtw_bss_type_t          bss_type;         /**< Network type                                                              */
+    rtw_security_t          security;         /**< Security type                                                             */
+    rtw_wps_type_t          wps_type;         /**< WPS type                                                                  */
+    unsigned int                      channel;          /**< Radio channel that the AP beacon was received on                          */
+    rtw_802_11_band_t       band;             /**< Radio band                                                                */                                        
+} rtw_scan_result_t;
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
+#pragma pack()
+#endif
+
+/**
+  * @brief  The structure is used to describe the data needed by scan result handler function.
+  */
+typedef struct rtw_scan_handler_result {
+    rtw_scan_result_t ap_details;
+    rtw_bool_t        scan_complete;
+    void*               user_data;
+
+} rtw_scan_handler_result_t;
+
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
+#pragma pack(1)
+#endif
+
+/**
+  * @brief  The structure is used to store the WIFI setting gotten from WIFI driver.
+  */
+typedef struct rtw_wifi_setting {
+	rtw_mode_t		mode;
+	unsigned char 		ssid[33];
+	unsigned char		channel;
+	rtw_security_t		security_type;
+	unsigned char 		password[65];
+	unsigned char		key_idx;
+}rtw_wifi_setting_t;
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
+#pragma pack()
+#endif
+
+/**
+  * @brief  The structure is used to describe the setting when configure the network.
+  */
+typedef struct rtw_wifi_config {
+	unsigned int		boot_mode;
+	unsigned char 		ssid[32];
+	unsigned char		ssid_len;
+	unsigned char		security_type;
+	unsigned char		password[65];
+	unsigned char		password_len;
+	unsigned char		channel;
+} rtw_wifi_config_t;
+
+/**
+  * @brief  The structure is used to describe the maclist.
+  */
+typedef struct
+{
+    unsigned int    count;         /**< Number of MAC addresses in the list    */
+    rtw_mac_t mac_list[1];   /**< Variable length array of MAC addresses */
+} rtw_maclist_t;
+
+/**
+  * @brief  The structure is used to describe the bss info of the network.\n
+  *			It include the version, BSSID, beacon_period, capability, SSID,
+  *			channel, atm_window, dtim_period, RSSI e.g.
+  */
+typedef struct {
+    unsigned int      version;                /**< version field */
+    unsigned int      length;                 /**< byte length of data in this record,   */
+                                          /* starting at version and including IEs */
+    rtw_mac_t     BSSID;
+    unsigned short      beacon_period;          /**< units are Kusec */
+    unsigned short      capability;             /**< Capability information */
+    unsigned char       SSID_len;
+    unsigned char       SSID[32];
+    unsigned char       channel;
+//    struct {
+//        uint32_t    count;                /* # rates in this set */
+//        uint8_t   rates[16];              /* rates in 500kbps units w/hi bit set if basic */
+//    } rateset;                            /* supported rates */
+//    rtw_chanspec_t  chanspec;              /* chanspec for bss */
+    unsigned short      atim_window;            /**< units are Kusec */
+    unsigned char       dtim_period;            /**< DTIM period */
+    signed short       RSSI;                   /**< receive signal strength (in dBm) */
+
+    unsigned char       n_cap;                  /**< BSS is 802.11N Capable */
+    unsigned int      nbss_cap;               /**< 802.11N BSS Capabilities (based on HT_CAP_*) */
+    unsigned char       basic_mcs[MCSSET_LEN];  /**< 802.11N BSS required MCS set */
+
+    unsigned short      ie_offset;              /**< offset at which IEs start, from beginning */
+    unsigned int      ie_length;             /**< byte length of Information Elements */
+} rtw_bss_info_t;
+
+/**
+  * @brief  The structure is used to set WIFI packet filter pattern.
+  */
+typedef struct {
+	unsigned short	offset;     /**< Offset in bytes to start filtering (referenced to the start of the ethernet packet) */
+	unsigned short	mask_size;  /**< Size of the mask in bytes */
+	unsigned char*	mask;       /**< Pattern mask bytes to be ANDed with the pattern eg. "\xff00" (must be in network byte order) */
+	unsigned char*	pattern;    /**< Pattern bytes used to filter eg. "\x0800"  (must be in network byte order) */
+} rtw_packet_filter_pattern_t;
+
+typedef struct ieee80211_frame_info{
+	unsigned short i_fc;
+	unsigned short i_dur;
+	unsigned char i_addr1[6];
+	unsigned char i_addr2[6];
+	unsigned char i_addr3[6];
+	unsigned short i_seq;
+	unsigned char bssid[6];
+	unsigned char encrypt;
+	signed char rssi;
+}ieee80211_frame_info_t;
+
+typedef struct {
+	char filter_id;
+	rtw_packet_filter_pattern_t patt;
+	rtw_packet_filter_rule_t rule;
+	unsigned char enable;
+}rtw_packet_filter_info_t;
+
+typedef struct rtw_mac_filter_list{
+	struct list_head node;
+	unsigned char mac_addr[6];
+}rtw_mac_filter_list_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+/*\@}*/
+
+#endif /* _WIFI_STRUCTURES_H */

component/common/drivers/wlan/realtek/src/core/option/rtw_opt_skbuf.c

@@ -0,0 +1,70 @@
+#include <section_config.h>
+#include <osdep_service.h>
+#include <skbuff.h>
+
+#define MAX_SKB_BUF_SIZE     1650	// should >= the size in wlan driver
+#define MAX_SKB_BUF_NUM      8
+#define MAX_LOCAL_SKB_NUM    (MAX_SKB_BUF_NUM + 2)
+
+/* DO NOT modify skb_buf and skb_data structure */
+struct skb_buf {
+	struct list_head list;
+	struct sk_buff skb;
+};
+
+struct skb_data {
+	struct list_head list;
+	unsigned char buf[MAX_SKB_BUF_SIZE];
+	atomic_t ref;
+};
+
+unsigned int nr_xmitframe = MAX_SKB_BUF_NUM;
+unsigned int nr_xmitbuff = MAX_SKB_BUF_NUM;
+int max_local_skb_num = MAX_LOCAL_SKB_NUM;
+int max_skb_buf_num = MAX_SKB_BUF_NUM;
+
+/* DO NOT access skb_pool and skb_data_pool out of wlan driver */
+struct skb_buf skb_pool[MAX_LOCAL_SKB_NUM];
+
+#define SKB_DATA_POOL_USING_GLOBAL_BUF	1
+#if SKB_DATA_POOL_USING_GLOBAL_BUF
+// SRAM_BD_DATA_SECTION default in SRAM. Can modify image2.icf to link to the end of SDRAM
+SRAM_BD_DATA_SECTION
+struct skb_data skb_data_pool[MAX_SKB_BUF_NUM];
+
+#else
+// Change to use heap (malloc) to save SRAM memory
+SRAM_BD_DATA_SECTION
+struct skb_data * skb_data_pool;
+
+extern struct list_head skbdata_list;
+extern int skbdata_used_num;
+extern int max_skbdata_used_num;
+void init_skb_data_pool(void)
+{
+	int i;
+	
+	//printf("\ninit_skb_data_pool\n");
+	skb_data_pool = (struct skb_data *)rtw_zmalloc(max_skb_buf_num * sizeof(struct skb_data));
+	if(!skb_data_pool){
+		printf("\nskb_data_pool alloc fail\n");
+		return;
+	}
+	
+	memset(skb_data_pool, '\0', max_skb_buf_num*sizeof(struct skb_data));
+	INIT_LIST_HEAD(&skbdata_list);
+	
+	for (i=0; i<max_skb_buf_num; i++) {
+		INIT_LIST_HEAD(&skb_data_pool[i].list);
+		list_add_tail(&skb_data_pool[i].list, &skbdata_list);
+	}
+	skbdata_used_num = 0;	
+	max_skbdata_used_num = 0;
+}
+
+void deinit_skb_data_pool(void)
+{
+	//printf("\ndeinit_skb_data_pool\n");
+	rtw_mfree(skb_data_pool, MAX_SKB_BUF_NUM * sizeof(struct skb_data));
+}
+#endif

component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h

@@ -0,0 +1,440 @@
+#ifndef __WRAPPER_H__
+#define __WRAPPER_H__
+/**************************************************************************
+  *  Wrapper provide a linux-like interface 
+  *
+  *  Copyright (c) 2013 Realtek Semiconductor Corp.
+  ************************************************************************/
+
+//----- ------------------------------------------------------------------
+// Include Files
+//----- ------------------------------------------------------------------
+#include <stdio.h>
+#include <string.h>
+#include "wireless.h"
+#include <skbuff.h>
+#include "freertos_service.h"
+
+#ifndef __LIST_H
+#warning "DLIST_NOT_DEFINE!!!!!!"
+//----- ------------------------------------------------------------------
+// Linled List
+//----- ------------------------------------------------------------------
+/*
+ * Simple doubly linked list implementation.
+ *
+ * Some of the internal functions ("__xxx") are useful when
+ * manipulating whole lists rather than single entries, as
+ * sometimes we already know the next/prev entries and we can
+ * generate better code by using them directly rather than
+ * using the generic single-entry routines.
+ */
+// struct list_head {
+// 	struct list_head *next, *prev;
+// };
+
+#define LIST_HEAD_INIT(name) { &(name), &(name) }
+
+#define INIT_LIST_HEAD(ptr) do { \
+	(ptr)->next = (ptr); (ptr)->prev = (ptr); \
+} while (0)
+
+/*
+ * Insert a new entry between two known consecutive entries. 
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+static __inline void __list_add(struct list_head * new,
+	struct list_head * prev,
+	struct list_head * next)
+{
+	next->prev = new;
+	new->next = next;
+	new->prev = prev;
+	prev->next = new;
+}
+
+/*
+ * Delete a list entry by making the prev/next entries
+ * point to each other.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+static __inline void __list_del(struct list_head * prev,
+				  struct list_head * next)
+{
+	next->prev = prev;
+	prev->next = next;
+}
+
+/**
+ * list_del - deletes entry from list.
+ * @entry: the element to delete from the list.
+ * Note: list_empty on entry does not return true after this, the entry is in an undefined state.
+ */
+static __inline void list_del(struct list_head *entry)
+{
+	__list_del(entry->prev, entry->next);
+}
+
+/**
+ * list_del_init - deletes entry from list and reinitialize it.
+ * @entry: the element to delete from the list.
+ */
+static __inline void list_del_init(struct list_head *entry)
+{
+	__list_del(entry->prev, entry->next);
+	INIT_LIST_HEAD(entry); 
+}
+
+/**
+ * list_empty - tests whether a list is empty
+ * @head: the list to test.
+ */
+static __inline int list_empty(struct list_head *head)
+{
+	return head->next == head;
+}
+
+/**
+ * list_splice - join two lists
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ */
+static __inline void list_splice(struct list_head *list, struct list_head *head)
+{
+	struct list_head *first = list->next;
+
+	if (first != list) {
+		struct list_head *last = list->prev;
+		struct list_head *at = head->next;
+
+		first->prev = head;
+		head->next = first;
+
+		last->next = at;
+		at->prev = last;
+	}
+}
+
+void list_add(struct list_head *new, struct list_head *head);
+void list_add_tail(struct list_head *new, struct list_head *head);
+#endif
+
+extern void save_and_cli(void);
+extern void restore_flags(void);
+//----- ------------------------------------------------------------------
+// SKB Operation
+//----- ------------------------------------------------------------------
+
+#define SMP_CACHE_BYTES		4
+#define SKB_DATA_ALIGN(X)	(((X) + (SMP_CACHE_BYTES - 1)) & ~(SMP_CACHE_BYTES - 1))
+
+// Consideration for SKB size
+//	Tx: [INTF_CMD][TX_DESC][WLAN_HDR][QoS][IV][SNAP][Data][MIC][ICV][INTF_STATUS]
+//			Since SKB is used to accept ethernet packet from upper layer, SKB length of WLAN_MAX_ETHFRM_LEN 
+//			(= 1514) is enough. But since SKB is also used to get spi receive packet, overall buffer space 
+//			should be taken into consideration.
+//	RX: [INTF_CMD][RX_DESC][Drv_Info][WLAN_HDR][QoS][IV][SNAP][Data][MIC][ICV][CRC][INTF_STATUS]
+//
+//	32: Driver_Info that carry phy related information for each packets. Required only for receive case.
+//	WLAN_MAX_ETHFRM_LEN : May not be required because WLAN_HEADER +SNAP can totally 
+//			cover ethernet header. Keep in only for safety.
+//
+//     **Notes** SDIO requires 512 blocks r/w, so 512*4 = 2048 is required.
+//	2003/12/26. The value is reduced from 2048 to 1658 for GSPI
+//	2014/02/05. The value is 1650 for 8195A LX_BUS
+#define SKB_RESERVED_FOR_SAFETY	0
+#define SKB_WLAN_TX_EXTRA_LEN	(TXDESC_SIZE + WLAN_HDR_A4_QOS_LEN + WLAN_MAX_IV_LEN + WLAN_SNAP_HEADER - WLAN_ETHHDR_LEN)
+#define RX_DRIVER_INFO				32
+
+#if (defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI)
+#define HAL_INTERFACE_OVERHEAD_SKB_DATA 12	//HAL_INTERFACE_CMD (4) + HAL_INTERFACE_STATUS (8)
+#elif defined(CONFIG_LX_HCI)
+#define HAL_INTERFACE_OVERHEAD_SKB_DATA 0
+#endif
+
+#if defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI || defined(CONFIG_LX_HCI)
+	#if defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B)
+		#if defined(CONFIG_MP_INCLUDED)
+			#ifdef CONFIG_DONT_CARE_TP
+				#define MAX_RX_PKT_LIMIT		((WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN + 511) / 512) // 4, for lxbus
+			#else
+				#define MAX_RX_PKT_LIMIT		((WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN + 511) / 512) // 4, for lxbus
+			#endif
+			#define MAX_RX_PKT_SIZE				MAX_RX_PKT_LIMIT*512	// MAX_SKB_BUF_SIZE = 0+32+40+512*4+0 = 2120
+		#else
+			#ifdef CONFIG_DONT_CARE_TP
+				#define MAX_RX_PKT_SIZE			WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN
+			#else
+				#define MAX_RX_PKT_SIZE			WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN	// MAX_RX_PKT_SIZE = 64+1514 = 1578
+			#endif
+			#define MAX_RX_PKT_LIMIT			((MAX_RX_PKT_SIZE + 511) / 512)			// ((1578 + 512)  / 512) = 4
+		#endif
+	#else
+		#ifdef CONFIG_DONT_CARE_TP
+			#define MAX_RX_PKT_SIZE				WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN
+		#else
+			#define MAX_RX_PKT_SIZE				WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN
+		#endif
+	#endif
+	
+	#ifdef CONFIG_DONT_CARE_TP
+		#define MAX_TX_SKB_BUF_SIZE				(HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\
+												((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\
+												WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_TX_ETHFRM_LEN +\
+												SKB_RESERVED_FOR_SAFETY)
+		#define MAX_RX_SKB_BUF_SIZE				(HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\
+												((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\
+												MAX_RX_PKT_SIZE +\
+												SKB_RESERVED_FOR_SAFETY)
+	#else
+		#define MAX_SKB_BUF_SIZE				(HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\
+												((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\
+												MAX_RX_PKT_SIZE +\
+												SKB_RESERVED_FOR_SAFETY)	// 0+32+40+1578+0 = 1650
+	#endif
+#else
+#define MAX_SKB_BUF_SIZE	2048
+#endif
+
+#if 0
+struct  sk_buff_head {
+	struct list_head	*next, *prev;
+	u32			qlen;
+};
+
+struct sk_buff {
+	/* These two members must be first. */
+	struct sk_buff		*next;		/* Next buffer in list */
+	struct sk_buff		*prev;		/* Previous buffer in list */
+	
+	struct sk_buff_head	*list;		/* List we are on */	
+	unsigned char		*head;		/* Head of buffer */
+	unsigned char		*data;		/* Data head pointer */
+	unsigned char		*tail;		/* Tail pointer	*/
+	unsigned char		*end;		/* End pointer */ 
+	struct net_device 	*dev;		/* Device we arrived on/are leaving by */	
+	unsigned int 		len;		/* Length of actual data */	
+};
+
+/**
+ *	skb_put - add data to a buffer
+ *	@skb: buffer to use 
+ *	@len: amount of data to add
+ *
+ *	This function extends the used data area of the buffer. If this would
+ *	exceed the total buffer size the kernel will panic. A pointer to the
+ *	first byte of the extra data is returned.
+ */
+ 
+static __inline__ unsigned char *skb_put(struct sk_buff *skb, unsigned int len)
+{
+	unsigned char *tmp=skb->tail;
+	skb->tail+=len;
+	skb->len+=len;
+	if(skb->tail>skb->end) {
+		ASSERT(0);		
+	}
+	
+	return tmp;
+}
+
+static __inline__ unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len)
+{
+	skb->len-=len;
+	skb->data = (unsigned char *)(((unsigned int)skb->data) + len);
+
+	return skb->data;
+}
+
+/**
+ *	skb_reserve - adjust headroom
+ *	@skb: buffer to alter
+ *	@len: bytes to move
+ *
+ *	Increase the headroom of an empty &sk_buff by reducing the tail
+ *	room. This is only allowed for an empty buffer.
+ */
+
+static __inline__ void skb_reserve(struct sk_buff *skb, unsigned int len)
+{
+	skb->data+=len;
+	skb->tail+=len;
+}
+
+static __inline__ void skb_queue_head_init(struct sk_buff_head *list)
+{
+        list->prev = (struct list_head *)list;
+        list->next = (struct list_head *)list;
+        list->qlen = 0;
+}
+
+/**
+ *      __skb_queue_tail - queue a buffer at the list tail
+ *      @list: list to use
+ *      @newsk: buffer to queue
+ *
+ *      Queue a buffer at the end of a list. This function takes no locks
+ *      and you must therefore hold required locks before calling it.
+ *
+ *      A buffer cannot be placed on two lists at the same time.
+ */     
+
+static __inline__ void __skb_queue_tail(struct sk_buff_head *list, struct sk_buff *newsk)
+{
+        struct sk_buff *prev, *next;
+
+        newsk->list = list;
+        list->qlen++;
+        next = (struct sk_buff *)list;
+        prev = next->prev;
+        newsk->next = next;
+        newsk->prev = prev;
+        next->prev = newsk;
+        prev->next = newsk;
+}
+
+/**
+ *      skb_queue_tail - queue a buffer at the list tail
+ *      @list: list to use
+ *      @newsk: buffer to queue
+ *
+ *      Queue a buffer at the tail of the list. This function takes the
+ *      list lock and can be used safely with other locking &sk_buff functions
+ *      safely.
+ *
+ *      A buffer cannot be placed on two lists at the same time.
+ */     
+
+static __inline__ void skb_queue_tail(struct sk_buff_head *list, struct sk_buff *newsk)
+{
+        save_and_cli();
+        __skb_queue_tail(list, newsk);
+        restore_flags();
+}
+
+static __inline__ void skb_assign_buf(struct sk_buff *skb, unsigned char *buf, unsigned int len)
+{	
+	skb->head = buf;
+	skb->data = buf;
+	skb->tail = buf;
+	skb->end = buf + len;
+}
+
+static __inline__ unsigned char *skb_tail_pointer(const struct sk_buff *skb)
+{
+	return skb->tail;
+}
+
+static __inline__ void skb_reset_tail_pointer(struct sk_buff *skb)
+{
+	skb->tail = skb->data;
+}
+
+static __inline__ void skb_set_tail_pointer(struct sk_buff *skb, const int offset)
+{
+	skb->tail = skb->data + offset;
+}
+
+static __inline__ unsigned char *skb_end_pointer(const struct sk_buff *skb)
+{
+	return skb->end;
+}
+#endif
+/*
+ *	External functions
+ */
+struct net_device;
+extern void kfree_skb_chk_key(struct sk_buff *skb, struct net_device *root_dev);
+#ifdef CONFIG_TRACE_SKB
+extern void show_skb(void);
+extern int _set_skb_list_flag(struct sk_buff *skb, unsigned int queueflag);
+extern void dump_skb_list(void);
+#define set_skb_list_flag(skb, queueflag) \
+	(\
+		_set_skb_list_flag((skb), queueflag), \
+		(skb) ? (skb)->funcname[(skb)->list_idx] = __FUNCTION__:NULL \
+	)
+extern int _clear_skb_list_flag(struct sk_buff *skb, unsigned int queueflag);
+#define clear_skb_list_flag(skb, queueflag) \
+	(\
+		_clear_skb_list_flag((skb), queueflag), \
+		(skb) ? (skb)->funcname[(skb)->list_idx] = __FUNCTION__ : NULL \
+	)
+#define dev_kfree_skb_any(trx, holder, skb)	\
+	do{\
+		clear_skb_list_flag(skb, SKBLIST_##trx##holder##_MASK);\
+		set_skb_list_flag(skb, SKBLIST_POOL);\
+		kfree_skb_chk_key(skb, skb->dev);\
+	}while (0)
+#else
+#define dev_kfree_skb_any(skb)	kfree_skb_chk_key(skb, skb->dev)
+#endif
+extern struct sk_buff *dev_alloc_skb(unsigned int length, unsigned int reserve_len);
+extern struct sk_buff *skb_clone(struct sk_buff *skb, int gfp_mask);
+extern struct sk_buff *skb_copy(const struct sk_buff *skb, int gfp_mask, unsigned int reserve_len);
+extern unsigned char *skb_pull(struct sk_buff *skb, unsigned int len);
+
+//----- ------------------------------------------------------------------
+// Device structure
+//----- ------------------------------------------------------------------
+struct net_device_stats {
+	unsigned long   rx_packets;             /* total packets received       */
+	unsigned long   tx_packets;             /* total packets transmitted    */
+	unsigned long   rx_dropped;             /* no space in linux buffers    */
+	unsigned long   tx_dropped;             /* no space available in linux  */
+	unsigned long   rx_bytes;               /* total bytes received         */
+	unsigned long   tx_bytes;               /* total bytes transmitted      */
+	unsigned long   rx_overflow;            /* rx fifo overflow count       */
+};
+
+struct net_device {
+	char			name[16];
+	void			*priv;		/* pointer to private data */
+	unsigned char		dev_addr[6];	/* set during bootup */
+	int (*init)(void);
+	int (*open)(struct net_device *dev);
+	int (*stop)(struct net_device *dev);
+	int (*hard_start_xmit)(struct sk_buff *skb, struct net_device *dev);
+	int (*do_ioctl)(struct net_device *dev, struct iwreq *ifr, int cmd);
+	struct net_device_stats* (*get_stats)(struct net_device *dev);
+};
+
+typedef struct {
+	struct net_device *dev;		/* Binding wlan driver netdev */
+	void *skb;			/* pending Rx packet */
+	unsigned int tx_busy;
+	unsigned int rx_busy;
+	unsigned char enable;
+	unsigned char mac[6];
+} Rltk_wlan_t;
+
+#define netdev_priv(dev)		dev->priv
+
+extern struct net_device *alloc_etherdev(int sizeof_priv);
+void free_netdev(struct net_device *dev);
+int dev_alloc_name(struct net_device *net_dev, const char *ifname);
+
+
+//----- ------------------------------------------------------------------
+// Timer Operation
+//----- ------------------------------------------------------------------
+void init_timer(struct timer_list *timer);
+void mod_timer(struct timer_list *timer, u32 delay_time_ms);
+void  cancel_timer_ex(struct timer_list * timer);
+void del_timer_sync(struct timer_list * timer);
+void init_timer_wrapper(void);
+void deinit_timer_wrapper(void);
+
+void	rtw_init_timer(_timer *ptimer, void *adapter, TIMER_FUN pfunc,void* cntx, const char *name);
+void	rtw_set_timer(_timer *ptimer,u32 delay_time);
+u8		rtw_cancel_timer(_timer *ptimer);
+void	rtw_del_timer(_timer *ptimer);
+
+#endif //__WRAPPER_H__
+
+
+

component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c

@@ -0,0 +1,236 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+//#define _LWIP_INTF_C_
+
+#include <autoconf.h>
+#include <lwip_intf.h>
+#include <lwip/netif.h>
+#include <lwip_netconf.h>
+#include <ethernetif.h>
+#include <osdep_service.h>
+#include <wifi/wifi_util.h>
+//----- ------------------------------------------------------------------
+// External Reference
+//----- ------------------------------------------------------------------
+#if (CONFIG_LWIP_LAYER == 1)
+extern struct netif xnetif[];			//LWIP netif
+#endif
+
+/**
+ *      rltk_wlan_set_netif_info - set netif hw address and register dev pointer to netif device
+ *      @idx_wlan: netif index
+ *			    0 for STA only or SoftAP only or STA in STA+SoftAP concurrent mode, 
+ *			    1 for SoftAP in STA+SoftAP concurrent mode
+ *      @dev: register netdev pointer to LWIP. Reserved.
+ *      @dev_addr: set netif hw address
+ *
+ *      Return Value: None
+ */     
+void rltk_wlan_set_netif_info(int idx_wlan, void * dev, unsigned char * dev_addr)
+{
+#if (CONFIG_LWIP_LAYER == 1)
+	rtw_memcpy(xnetif[idx_wlan].hwaddr, dev_addr, 6);
+	xnetif[idx_wlan].state = dev;
+#endif
+}
+
+/**
+ *      rltk_wlan_send - send IP packets to WLAN. Called by low_level_output().
+ *      @idx: netif index
+ *      @sg_list: data buffer list
+ *      @sg_len: size of each data buffer
+ *      @total_len: total data len
+ *
+ *      Return Value: None
+ */     
+int rltk_wlan_send(int idx, struct eth_drv_sg *sg_list, int sg_len, int total_len)
+{
+#if (CONFIG_LWIP_LAYER == 1)
+	struct eth_drv_sg *last_sg;
+	struct sk_buff *skb = NULL;
+	int ret = 0;
+
+	if(idx == -1){
+		DBG_ERR("netif is DOWN");
+		return -1;
+	}
+	DBG_TRACE("%s is called", __FUNCTION__);
+	
+	save_and_cli();
+	if(rltk_wlan_check_isup(idx))
+		rltk_wlan_tx_inc(idx);
+	else {
+		DBG_ERR("netif is DOWN");
+		restore_flags();
+		return -1;
+	}
+	restore_flags();
+
+	skb = rltk_wlan_alloc_skb(total_len);
+	if (skb == NULL) {
+		//DBG_ERR("rltk_wlan_alloc_skb() for data len=%d failed!", total_len);
+		ret = -1;
+		goto exit;
+	}
+
+	for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
+		rtw_memcpy(skb->tail, (void *)(sg_list->buf), sg_list->len);
+		skb_put(skb,  sg_list->len);		
+	}
+
+	rltk_wlan_send_skb(idx, skb);
+
+exit:
+	save_and_cli();
+	rltk_wlan_tx_dec(idx);
+	restore_flags();
+	return ret;
+#endif
+}
+
+/**
+ *      rltk_wlan_recv - indicate packets to LWIP. Called by ethernetif_recv().
+ *      @idx: netif index
+ *      @sg_list: data buffer list
+ *      @sg_len: size of each data buffer
+ *
+ *      Return Value: None
+ */     
+void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len)
+{
+#if (CONFIG_LWIP_LAYER == 1)
+	struct eth_drv_sg *last_sg;
+	struct sk_buff *skb;
+	
+	DBG_TRACE("%s is called", __FUNCTION__);
+	if(idx == -1){
+		DBG_ERR("skb is NULL");
+		return;
+	}
+	skb = rltk_wlan_get_recv_skb(idx);
+	DBG_ASSERT(skb, "No pending rx skb");
+
+	for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
+		if (sg_list->buf != 0) {
+			rtw_memcpy((void *)(sg_list->buf), skb->data, sg_list->len);
+			skb_pull(skb, sg_list->len);
+		}
+	}
+#endif
+}
+
+int netif_is_valid_IP(int idx, unsigned char *ip_dest)
+{
+#if CONFIG_LWIP_LAYER == 1
+	struct netif * pnetif = &xnetif[idx];
+	struct ip_addr addr = { 0 };
+#ifdef CONFIG_MEMORY_ACCESS_ALIGNED
+	unsigned int temp;
+	memcpy(&temp, ip_dest, sizeof(unsigned int));
+	u32_t *ip_dest_addr = &temp;
+#else
+	u32_t *ip_dest_addr  = (u32_t*)ip_dest;
+#endif
+	addr.addr = *ip_dest_addr;
+	
+	if(pnetif->ip_addr.addr == 0)
+		return 1;
+	
+	if(ip_addr_ismulticast(&addr) || ip_addr_isbroadcast(&addr,pnetif)){
+		return 1;
+	}
+		
+	//if(ip_addr_netcmp(&(pnetif->ip_addr), &addr, &(pnetif->netmask))) //addr&netmask
+	//	return 1;
+
+	if(ip_addr_cmp(&(pnetif->ip_addr),&addr))
+		return 1;
+
+	DBG_TRACE("invalid IP: %d.%d.%d.%d ",ip_dest[0],ip_dest[1],ip_dest[2],ip_dest[3]);
+#endif	
+#ifdef CONFIG_DONT_CARE_TP
+	if(pnetif->flags & NETIF_FLAG_IPSWITCH)
+		return 1;
+	else
+#endif
+	return 0;
+}
+
+int netif_get_idx(struct netif* pnetif)
+{
+#if CONFIG_LWIP_LAYER == 1
+	int idx = pnetif - xnetif;
+
+	switch(idx) {
+	case 0:
+		return 0;
+	case 1:
+		return 1;
+	default:
+		return -1;
+	}
+#else	
+	return -1;
+#endif
+}
+
+unsigned char *netif_get_hwaddr(int idx_wlan)
+{
+#if (CONFIG_LWIP_LAYER == 1)
+	return xnetif[idx_wlan].hwaddr;
+#else
+	return NULL;
+#endif
+}
+
+void netif_rx(int idx, unsigned int len)
+{
+#if (CONFIG_LWIP_LAYER == 1)
+	ethernetif_recv(&xnetif[idx], len);
+#endif
+#if (CONFIG_INIC_EN == 1)
+        inic_netif_rx(idx, len);
+#endif
+}
+
+void netif_post_sleep_processing(void)
+{
+#if (CONFIG_LWIP_LAYER == 1)
+	lwip_POST_SLEEP_PROCESSING();	//For FreeRTOS tickless to enable Lwip ARP timer when leaving IPS - Alex Fang
+#endif
+}
+
+void netif_pre_sleep_processing(void)
+{
+#if (CONFIG_LWIP_LAYER == 1)
+	lwip_PRE_SLEEP_PROCESSING();	
+#endif
+}
+
+#ifdef CONFIG_WOWLAN
+unsigned char *rltk_wlan_get_ip(int idx){
+#if (CONFIG_LWIP_LAYER == 1)
+	return LwIP_GetIP(&xnetif[idx]);
+#else
+	return NULL;
+#endif
+}
+#endif
+

component/common/drivers/wlan/realtek/src/osdep/lwip_intf.h

@@ -0,0 +1,61 @@
+#ifndef __LWIP_INTF_H__
+#define __LWIP_INTF_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include <wireless.h>
+#include <skbuff.h>
+#include "ethernetif.h"
+#if 0 // moved to ethernetif.h by jimmy 12/2/2015
+//----- ------------------------------------------------------------------
+// Ethernet Buffer
+//----- ------------------------------------------------------------------
+struct eth_drv_sg {
+    unsigned int	buf;
+    unsigned int 	len;
+};
+
+#define MAX_ETH_DRV_SG	32
+#define MAX_ETH_MSG	1540
+#endif
+//----- ------------------------------------------------------------------
+// Wlan Interface Provided
+//----- ------------------------------------------------------------------
+unsigned char rltk_wlan_check_isup(int idx);
+void rltk_wlan_tx_inc(int idx);
+void rltk_wlan_tx_dec(int idx);
+struct sk_buff * rltk_wlan_get_recv_skb(int idx);
+struct sk_buff * rltk_wlan_alloc_skb(unsigned int total_len);
+void rltk_wlan_set_netif_info(int idx_wlan, void * dev, unsigned char * dev_addr);
+void rltk_wlan_send_skb(int idx, struct sk_buff *skb);	//struct sk_buff as defined above comment line
+int rltk_wlan_send(int idx, struct eth_drv_sg *sg_list, int sg_len, int total_len);
+void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len);
+unsigned char rltk_wlan_running(unsigned char idx);		// interface is up. 0: interface is down
+
+//----- ------------------------------------------------------------------
+// Network Interface provided
+//----- ------------------------------------------------------------------
+struct netif;
+int netif_is_valid_IP(int idx,unsigned char * ip_dest);
+int netif_get_idx(struct netif *pnetif);
+unsigned char *netif_get_hwaddr(int idx_wlan);
+void netif_rx(int idx, unsigned int len);
+void netif_post_sleep_processing(void);
+void netif_pre_sleep_processing(void);
+#if (CONFIG_LWIP_LAYER == 1)
+extern void ethernetif_recv(struct netif *netif, int total_len);
+extern void lwip_PRE_SLEEP_PROCESSING(void);
+extern void lwip_POST_SLEEP_PROCESSING(void);
+#endif //CONFIG_LWIP_LAYER == 1
+
+#ifdef CONFIG_WOWLAN
+extern unsigned char *rltk_wlan_get_ip(int idx);
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif //#ifndef __LWIP_INTF_H__

component/common/drivers/wlan/realtek/src/osdep/skbuff.h

@@ -0,0 +1,57 @@
+#ifndef __SKBUFF_H__
+#define __SKBUFF_H__
+
+struct  sk_buff_head {
+	struct list_head	*next, *prev;
+	unsigned int 		qlen;
+};
+
+#ifdef CONFIG_TRACE_SKB
+#define	TRACE_SKB_DEPTH			8
+#endif
+
+struct sk_buff {
+	/* These two members must be first. */
+	struct sk_buff		*next;		/* Next buffer in list */
+	struct sk_buff		*prev;		/* Previous buffer in list */
+	
+	struct sk_buff_head	*list;		/* List we are on */	
+	unsigned char		*head;		/* Head of buffer */
+	unsigned char		*data;		/* Data head pointer */
+	unsigned char		*tail;		/* Tail pointer	*/
+	unsigned char		*end;		/* End pointer */ 
+	void	*dev;		/* Device we arrived on/are leaving by */	
+	unsigned int 		len;		/* Length of actual data */	
+#ifdef CONFIG_TRACE_SKB
+	unsigned int		liston[TRACE_SKB_DEPTH];	/* Trace the Lists we went through */
+	const char		*funcname[TRACE_SKB_DEPTH];
+	unsigned int		list_idx;	/* Trace the List we are on */
+#endif	
+//#ifdef CONFIG_DONT_CARE_TP
+	int 			dyalloc_flag;
+//#endif
+};
+
+unsigned char *skb_put(struct sk_buff *skb, unsigned int len);
+unsigned char *skb_pull(struct sk_buff *skb, unsigned int len);
+void skb_reserve(struct sk_buff *skb, unsigned int len);
+void skb_assign_buf(struct sk_buff *skb, unsigned char *buf, unsigned int len);
+unsigned char *skb_tail_pointer(const struct sk_buff *skb);
+void skb_set_tail_pointer(struct sk_buff *skb, const int offset);
+unsigned char *skb_end_pointer(const struct sk_buff *skb);
+
+void init_skb_pool(void);
+void init_skb_data_pool(void);
+
+#ifndef CONFIG_DONT_CARE_TP
+struct sk_buff *dev_alloc_skb(unsigned int length, unsigned int reserve_len);
+#else
+struct sk_buff *dev_alloc_tx_skb(unsigned int length, unsigned int reserve_len);
+struct sk_buff *dev_alloc_rx_skb(unsigned int length, unsigned int reserve_len);
+#define dev_alloc_skb	dev_alloc_tx_skb
+#endif
+void kfree_skb(struct sk_buff *skb);
+
+
+#endif //__SKBUFF_H__
+

component/common/drivers/wlan/realtek/src/osdep/wlan_intf.h

@@ -0,0 +1,66 @@
+#ifndef __WLAN_INTF_H__
+#define __WLAN_INTF_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+#include <autoconf.h>
+
+#include <wireless.h>
+#include "wifi_constants.h"
+
+#ifndef WLAN0_IDX
+	#define WLAN0_IDX	0
+#endif
+#ifndef WLAN1_IDX
+	#define WLAN1_IDX	1
+#endif
+#ifndef WLAN_UNDEF
+	#define WLAN_UNDEF	-1
+#endif
+
+/***********************************************************/
+/* 
+struct sk_buff {
+	// These two members must be first.
+	struct sk_buff		*next;		// Next buffer in list
+	struct sk_buff		*prev;		// Previous buffer in list
+	
+	struct sk_buff_head	*list;			// List we are on	
+	unsigned char		*head;		// Head of buffer
+	unsigned char		*data;		// Data head pointer
+	unsigned char		*tail;		// Tail pointer
+	unsigned char		*end;		//End pointer
+	struct net_device 	*dev;		//Device we arrived on/are leaving by 	
+	unsigned int 		len;			// Length of actual data 
+};
+*/
+/************************************************************/
+
+//----- ------------------------------------------------------------------
+// Wlan Interface opened for upper layer
+//----- ------------------------------------------------------------------
+int rltk_wlan_init(int idx_wlan, rtw_mode_t mode);				//return 0: success. -1:fail
+void rltk_wlan_deinit(void);
+void rltk_wlan_deinit_fastly(void);
+int rltk_wlan_start(int idx_wlan);
+void rltk_wlan_statistic(unsigned char idx);
+unsigned char rltk_wlan_running(unsigned char idx);		// interface is up. 0: interface is down
+int rltk_wlan_control(unsigned long cmd, void *data);
+int rltk_wlan_handshake_done(void);
+int rltk_wlan_rf_on(void);
+int rltk_wlan_rf_off(void);
+int rltk_wlan_check_bus(void);
+int rltk_wlan_wireless_mode(unsigned char mode);
+int rltk_wlan_set_wps_phase(unsigned char is_trigger_wps);
+int rtw_ps_enable(int enable);
+int rltk_wlan_is_connected_to_ap(void);
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+
+#endif //#ifndef __WLAN_INTF_H__

component/common/drivers/wlan/realtek/wlan_ram_map/rom/rom_wlan_ram_map.h

@@ -0,0 +1,9 @@
+#ifndef ROM_WLAN_RAM_MAP_H
+#define ROM_WLAN_RAM_MAP_H
+
+struct _rom_wlan_ram_map {
+	unsigned char * (*rtw_malloc)(unsigned int sz);
+	void (*rtw_mfree)(unsigned char *pbuf, unsigned int sz);
+};
+
+#endif	/* ROM_WLAN_RAM_MAP_H */